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/************************************************************************
statusLED.v
Status LED control module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email: [email protected]
************************************************************************/
module statusLED (
input nReset,
input clock,
// Outputs
output reg [7:0] leds
);
// Control the status LEDs
reg [31:0] timer;
reg direction;
reg [3:0] position; // 4-bit value 0-15
always @ (posedge clock, negedge nReset) begin
if (!nReset) begin
leds <= 8'b00000001;
timer <= 16'd0;
direction <= 1'b1;
position <= 4'd0;
end else begin
timer <= timer + 32'd1;
// Wait for the timer to elapse before updating LEDs
if (timer >= 32'd4000000) begin
case(position)
4'd0:leds <= 8'b00000001;
4'd1:leds <= 8'b00000010;
4'd2:leds <= 8'b00000100;
4'd3:leds <= 8'b00001000;
4'd4:leds <= 8'b00010000;
4'd5:leds <= 8'b00100000;
4'd6:leds <= 8'b01000000;
4'd7:leds <= 8'b10000000;
endcase
if (direction) begin
if (position == 4'd7) begin
position <= 4'd6;
direction <= 1'b0;
end else begin
position <= position + 4'd1;
end
end else begin
if (position == 4'd0) begin
position <= 4'd1;
direction <= 1'b1;
end else begin
position <= position - 4'd1;
end
end
// Reset timer
timer <= 16'd0;
end
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_1_V
`define SKY130_FD_SC_HD__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_1_V
|
//*******************************************************************************************
//Author: Zhiyoong Foo, Yejoong Kim
//Last Modified: Aug 23 2017
//Description: (Testbench) MBus CLK/DATA Swapper
// - Generates Data & Clock Flip Interrupt;
// - Maintains Last seen Clock State
//Update History: Mar 06 2013 - First Commit (Zhiyoong Foo)
// May 21 2016 - Included in MBus r03 (Yejoong Kim)
// Dec 16 2016 - Included in MBus r04 (Yejoong Kim)
// Aug 23 2017 - Checked for mbus_testbench
//*******************************************************************************************
module mbus_swapper_testbench (
//Inputs
input CLK,
input RESETn,
input DATA,
input INT_FLAG_RESETn,
//Outputs
output reg LAST_CLK,
output reg INT_FLAG
);
//Internal Declerations
wire negp_reset;
wire posp_reset;
//Negative Phase Clock Resets
reg pose_negp_clk_0; //Positive Edge
reg nege_negp_clk_1; //Negative Edge
reg pose_negp_clk_2;
reg nege_negp_clk_3;
reg pose_negp_clk_4;
reg nege_negp_clk_5;
wire negp_int; //Negative Phase Interrupt
//Interrupt Reset
wire int_resetn;
assign negp_reset = ~( CLK && RESETn);
//////////////////////////////////////////
// Interrupt Generation
//////////////////////////////////////////
//Negative Phase Clock Resets
always @(posedge DATA or posedge negp_reset) begin
if (negp_reset) begin
pose_negp_clk_0 = 0;
pose_negp_clk_2 = 0;
pose_negp_clk_4 = 0;
end
else begin
pose_negp_clk_0 = 1;
pose_negp_clk_2 = nege_negp_clk_1;
pose_negp_clk_4 = nege_negp_clk_3;
end
end
always @(negedge DATA or posedge negp_reset) begin
if (negp_reset) begin
nege_negp_clk_1 = 0;
nege_negp_clk_3 = 0;
nege_negp_clk_5 = 0;
end
else begin
nege_negp_clk_1 = pose_negp_clk_0;
nege_negp_clk_3 = pose_negp_clk_2;
nege_negp_clk_5 = pose_negp_clk_4;
end
end
//Negative Phase Interrupt Generation
assign negp_int = pose_negp_clk_0 && nege_negp_clk_1 &&
pose_negp_clk_2 && nege_negp_clk_3 &&
pose_negp_clk_4 && nege_negp_clk_5;
//Interrupt Check & Clear
assign int_resetn = RESETn && INT_FLAG_RESETn;
always @(posedge negp_int or negedge int_resetn) begin
if (~int_resetn) INT_FLAG = 0;
else INT_FLAG = 1;
end
//////////////////////////////////////////
// Last Seen Clock
//////////////////////////////////////////
always @(posedge negp_int or negedge RESETn) begin
if (~RESETn) LAST_CLK = 0;
else LAST_CLK = CLK;
end
endmodule // mbus_swapper_testbench
|
/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
/* verilator lint_off PINNOCONNECT */
/* verilator lint_off PINMISSING */
/* verilator lint_off UNOPTFLAT */
module uart_16750 ( CLK, RST, BAUDCE, CS, WR, RD, A, DIN, DOUT, DDIS, INT,
OUT1N, OUT2N, RCLK, BAUDOUTN, RTSN, DTRN, CTSN, DSRN, DCDN, RIN, SIN,
SOUT );
input [2:0] A;
input [7:0] DIN;
output [7:0] DOUT;
input CLK, RST, BAUDCE, CS, WR, RD, RCLK, CTSN, DSRN, DCDN, RIN, SIN;
output DDIS, INT, OUT1N, OUT2N, BAUDOUTN, RTSN, DTRN, SOUT;
wire N48, iWriteFE, iReadFE, iSINr, iCTSNs, iDSRNs, iDCDNs, iRINs,
iBaudtick2x, iCTSn, iDSRn, iDCDn, iRIn, iTHRInterrupt, iCharTimeout,
iIIR_6, iLSR_THRERE, N66, iRXFIFOEmpty, iRXFIFOWrite, N94, N95,
iFCR_5, iPERE, iFERE, iBIRE, iLSR_FIFOERR, iRXFIFOClear, N130, N131,
N132, N133, N134, N135, N146, iTXFIFOEmpty, iTXRunning, iRTS, N154,
N155, N156, N157, iCTSnFE, iDSRnFE, iRInFE, iDCDnFE, iBaudtick16x,
iRCLK, iTXFIFORead, iTXFIFO64Full, \iTXFIFOUsage[4] , N169,
iRXFIFO64Full, iTXStart, iTXFinished, iSOUT, iSIN, iRXPE, iRXFE,
iRXBI, N181, N182, N183, State_snps_wire, N190, N191, N197, N198,
N199, N200, N201, N202, \U3/U1/Z_0 , n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354,
n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365,
n366, n367, n368, n369, n371, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n424, n425, n426, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n440,
n441, n442, n443, n444, n446, n447, n448, n449, n450, n451, n452,
n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n495, n496, n497, n498,
n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520,
n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, \UART_ED_WRITE/n1 , \UART_ED_WRITE/iDd , \UART_ED_READ/n1 ,
\UART_ED_READ/iDd , \UART_IS_SIN/n1 , \UART_IS_SIN/iD[0] ,
\UART_IS_CTS/n1 , \UART_IS_CTS/iD[0] , \UART_IS_DSR/n1 ,
\UART_IS_DSR/iD[0] , \UART_IS_DCD/n1 , \UART_IS_DCD/iD[0] ,
\UART_IS_RI/n1 , \UART_IS_RI/iD[0] , \UART_IF_CTS/n8 ,
\UART_IF_CTS/n7 , \UART_IF_CTS/n6 , \UART_IF_CTS/n5 ,
\UART_IF_CTS/n4 , \UART_IF_CTS/n2 , \UART_IF_CTS/n1 ,
\UART_IF_CTS/n18 , \UART_IF_CTS/n17 , \UART_IF_CTS/n16 ,
\UART_IF_CTS/iCount[0] , \UART_IF_CTS/iCount[1] , \UART_IF_DSR/n11 ,
\UART_IF_DSR/n10 , \UART_IF_DSR/n9 , \UART_IF_DSR/n8 ,
\UART_IF_DSR/n7 , \UART_IF_DSR/n6 , \UART_IF_DSR/n5 ,
\UART_IF_DSR/n4 , \UART_IF_DSR/n2 , \UART_IF_DSR/n1 ,
\UART_IF_DSR/iCount[0] , \UART_IF_DSR/iCount[1] , \UART_IF_DCD/n11 ,
\UART_IF_DCD/n10 , \UART_IF_DCD/n9 , \UART_IF_DCD/n7 ,
\UART_IF_DCD/n6 , \UART_IF_DCD/n5 , \UART_IF_DCD/n4 ,
\UART_IF_DCD/n2 , \UART_IF_DCD/n1 , \UART_IF_DCD/iCount[0] ,
\UART_IF_DCD/iCount[1] , \UART_IF_RI/n11 , \UART_IF_RI/n10 ,
\UART_IF_RI/n9 , \UART_IF_RI/n7 , \UART_IF_RI/n6 , \UART_IF_RI/n5 ,
\UART_IF_RI/n4 , \UART_IF_RI/n3 , \UART_IF_RI/n2 , \UART_IF_RI/n1 ,
\UART_IF_RI/iCount[0] , \UART_IF_RI/iCount[1] , \UART_IIC/n9 ,
\UART_IIC/n8 , \UART_IIC/n7 , \UART_IIC/n6 , \UART_IIC/n5 ,
\UART_IIC/n4 , \UART_IIC/n3 , \UART_IIC/n2 , \UART_IIC/n1 ,
\UART_IIC/N22 , \UART_IIC/N21 , \UART_IIC/N20 , \UART_IIC/N19 ,
\UART_IIC/IIR[0] , \UART_IIC_THRE_ED/n1 , \UART_IIC_THRE_ED/iDd ,
\UART_PEDET/n1 , \UART_PEDET/iDd , \UART_FEDET/n1 , \UART_FEDET/iDd ,
\UART_BIDET/n1 , \UART_BIDET/iDd , \UART_ED_CTS/n1 ,
\UART_ED_CTS/iDd , \UART_ED_DSR/n1 , \UART_ED_DSR/iDd ,
\UART_ED_RI/n1 , \UART_ED_RI/iDd , \UART_ED_DCD/n1 ,
\UART_ED_DCD/iDd , \UART_BG16/n72 , \UART_BG16/n71 , \UART_BG16/n70 ,
\UART_BG16/n69 , \UART_BG16/n68 , \UART_BG16/n67 , \UART_BG16/n66 ,
\UART_BG16/n65 , \UART_BG16/n64 , \UART_BG16/n63 , \UART_BG16/n62 ,
\UART_BG16/n61 , \UART_BG16/n60 , \UART_BG16/n59 , \UART_BG16/n58 ,
\UART_BG16/n57 , \UART_BG16/n56 , \UART_BG16/n39 , \UART_BG16/n38 ,
\UART_BG16/n37 , \UART_BG16/n35 , \UART_BG16/n33 , \UART_BG16/n32 ,
\UART_BG16/n31 , \UART_BG16/n30 , \UART_BG16/n29 , \UART_BG16/n28 ,
\UART_BG16/n27 , \UART_BG16/n26 , \UART_BG16/n25 , \UART_BG16/n24 ,
\UART_BG16/n23 , \UART_BG16/n22 , \UART_BG16/n21 , \UART_BG16/n20 ,
\UART_BG16/n19 , \UART_BG16/n18 , \UART_BG16/n17 , \UART_BG16/n16 ,
\UART_BG16/n15 , \UART_BG16/n14 , \UART_BG16/n13 , \UART_BG16/n12 ,
\UART_BG16/n11 , \UART_BG16/n10 , \UART_BG16/n9 , \UART_BG16/n8 ,
\UART_BG16/n7 , \UART_BG16/n6 , \UART_BG16/n5 , \UART_BG16/n4 ,
\UART_BG16/n2 , \UART_BG16/n1 , \UART_BG16/n55 , \UART_BG16/n54 ,
\UART_BG16/n53 , \UART_BG16/n52 , \UART_BG16/n51 , \UART_BG16/n50 ,
\UART_BG16/n49 , \UART_BG16/n48 , \UART_BG16/n47 , \UART_BG16/n46 ,
\UART_BG16/n45 , \UART_BG16/n44 , \UART_BG16/n43 , \UART_BG16/n42 ,
\UART_BG16/n41 , \UART_BG16/n40 , \UART_BG16/N40 , \UART_BG16/N22 ,
\UART_BG16/N21 , \UART_BG16/N20 , \UART_BG16/N19 , \UART_BG16/N18 ,
\UART_BG16/N17 , \UART_BG16/N16 , \UART_BG16/N15 , \UART_BG16/N14 ,
\UART_BG16/N13 , \UART_BG16/N12 , \UART_BG16/N11 , \UART_BG16/N10 ,
\UART_BG16/N9 , \UART_BG16/N8 , \UART_BG16/iCounter[0] ,
\UART_BG16/iCounter[1] , \UART_BG16/iCounter[2] ,
\UART_BG16/iCounter[3] , \UART_BG16/iCounter[4] ,
\UART_BG16/iCounter[5] , \UART_BG16/iCounter[6] ,
\UART_BG16/iCounter[7] , \UART_BG16/iCounter[8] ,
\UART_BG16/iCounter[9] , \UART_BG16/iCounter[10] ,
\UART_BG16/iCounter[11] , \UART_BG16/iCounter[12] ,
\UART_BG16/iCounter[13] , \UART_BG16/iCounter[14] ,
\UART_BG16/iCounter[15] , \UART_BG2/n2 , \UART_BG2/n1 , \UART_BG2/n6 ,
\UART_BG2/n4 , \UART_BG2/n3 , \UART_BG2/N14 , \UART_BG2/iCounter[0] ,
\UART_BG2/iCounter[1] , \UART_BG2/iCounter[2] , \UART_RCLK/n1 ,
\UART_RCLK/iDd , \UART_TXFF/n373 , \UART_TXFF/n372 , \UART_TXFF/n371 ,
\UART_TXFF/n370 , \UART_TXFF/n369 , \UART_TXFF/n368 ,
\UART_TXFF/n367 , \UART_TXFF/n366 , \UART_TXFF/n365 ,
\UART_TXFF/n364 , \UART_TXFF/n363 , \UART_TXFF/n362 ,
\UART_TXFF/n361 , \UART_TXFF/n360 , \UART_TXFF/n359 ,
\UART_TXFF/n358 , \UART_TXFF/n356 , \UART_TXFF/n355 ,
\UART_TXFF/n354 , \UART_TXFF/n350 , \UART_TXFF/n349 ,
\UART_TXFF/n348 , \UART_TXFF/n347 , \UART_TXFF/n346 ,
\UART_TXFF/n345 , \UART_TXFF/n344 , \UART_TXFF/n343 ,
\UART_TXFF/n342 , \UART_TXFF/n341 , \UART_TXFF/n340 ,
\UART_TXFF/n339 , \UART_TXFF/n338 , \UART_TXFF/n337 ,
\UART_TXFF/n336 , \UART_TXFF/n335 , \UART_TXFF/n334 ,
\UART_TXFF/n333 , \UART_TXFF/n332 , \UART_TXFF/n331 ,
\UART_TXFF/n330 , \UART_TXFF/n329 , \UART_TXFF/n328 ,
\UART_TXFF/n327 , \UART_TXFF/n326 , \UART_TXFF/n325 ,
\UART_TXFF/n324 , \UART_TXFF/n323 , \UART_TXFF/n322 ,
\UART_TXFF/n321 , \UART_TXFF/n320 , \UART_TXFF/n319 ,
\UART_TXFF/n318 , \UART_TXFF/n317 , \UART_TXFF/n316 ,
\UART_TXFF/n315 , \UART_TXFF/n314 , \UART_TXFF/n313 ,
\UART_TXFF/n312 , \UART_TXFF/n311 , \UART_TXFF/n310 ,
\UART_TXFF/n309 , \UART_TXFF/n308 , \UART_TXFF/n307 ,
\UART_TXFF/n306 , \UART_TXFF/n305 , \UART_TXFF/n304 ,
\UART_TXFF/n303 , \UART_TXFF/n302 , \UART_TXFF/n301 ,
\UART_TXFF/n300 , \UART_TXFF/n299 , \UART_TXFF/n298 ,
\UART_TXFF/n297 , \UART_TXFF/n296 , \UART_TXFF/n295 ,
\UART_TXFF/n294 , \UART_TXFF/n293 , \UART_TXFF/n292 ,
\UART_TXFF/n291 , \UART_TXFF/n290 , \UART_TXFF/n289 ,
\UART_TXFF/n288 , \UART_TXFF/n287 , \UART_TXFF/n286 ,
\UART_TXFF/n285 , \UART_TXFF/n284 , \UART_TXFF/n283 ,
\UART_TXFF/n282 , \UART_TXFF/n281 , \UART_TXFF/n280 ,
\UART_TXFF/n279 , \UART_TXFF/n278 , \UART_TXFF/n277 ,
\UART_TXFF/n276 , \UART_TXFF/n275 , \UART_TXFF/n274 ,
\UART_TXFF/n273 , \UART_TXFF/n272 , \UART_TXFF/n271 ,
\UART_TXFF/n270 , \UART_TXFF/n269 , \UART_TXFF/n268 ,
\UART_TXFF/n267 , \UART_TXFF/n266 , \UART_TXFF/n265 ,
\UART_TXFF/n264 , \UART_TXFF/n263 , \UART_TXFF/n262 ,
\UART_TXFF/n261 , \UART_TXFF/n260 , \UART_TXFF/n259 ,
\UART_TXFF/n258 , \UART_TXFF/n257 , \UART_TXFF/n256 ,
\UART_TXFF/n255 , \UART_TXFF/n254 , \UART_TXFF/n253 ,
\UART_TXFF/n252 , \UART_TXFF/n251 , \UART_TXFF/n250 ,
\UART_TXFF/n249 , \UART_TXFF/n248 , \UART_TXFF/n247 ,
\UART_TXFF/n246 , \UART_TXFF/n245 , \UART_TXFF/n244 ,
\UART_TXFF/n243 , \UART_TXFF/n242 , \UART_TXFF/n240 ,
\UART_TXFF/n239 , \UART_TXFF/n238 , \UART_TXFF/n237 ,
\UART_TXFF/n236 , \UART_TXFF/n235 , \UART_TXFF/n234 ,
\UART_TXFF/n233 , \UART_TXFF/n232 , \UART_TXFF/n231 ,
\UART_TXFF/n230 , \UART_TXFF/n229 , \UART_TXFF/n228 ,
\UART_TXFF/n227 , \UART_TXFF/n226 , \UART_TXFF/n225 ,
\UART_TXFF/n224 , \UART_TXFF/n223 , \UART_TXFF/n222 ,
\UART_TXFF/n221 , \UART_TXFF/n220 , \UART_TXFF/n219 ,
\UART_TXFF/n218 , \UART_TXFF/n217 , \UART_TXFF/n216 ,
\UART_TXFF/n215 , \UART_TXFF/n214 , \UART_TXFF/n213 ,
\UART_TXFF/n212 , \UART_TXFF/n211 , \UART_TXFF/n210 ,
\UART_TXFF/n209 , \UART_TXFF/n208 , \UART_TXFF/n207 ,
\UART_TXFF/n206 , \UART_TXFF/n205 , \UART_TXFF/n204 ,
\UART_TXFF/n203 , \UART_TXFF/n202 , \UART_TXFF/n201 ,
\UART_TXFF/n200 , \UART_TXFF/n199 , \UART_TXFF/n198 ,
\UART_TXFF/n197 , \UART_TXFF/n196 , \UART_TXFF/n195 ,
\UART_TXFF/n194 , \UART_TXFF/n193 , \UART_TXFF/n192 ,
\UART_TXFF/n191 , \UART_TXFF/n190 , \UART_TXFF/n189 ,
\UART_TXFF/n188 , \UART_TXFF/n187 , \UART_TXFF/n186 ,
\UART_TXFF/n185 , \UART_TXFF/n184 , \UART_TXFF/n183 ,
\UART_TXFF/n182 , \UART_TXFF/n181 , \UART_TXFF/n180 ,
\UART_TXFF/n179 , \UART_TXFF/n178 , \UART_TXFF/n177 ,
\UART_TXFF/n176 , \UART_TXFF/n175 , \UART_TXFF/n174 ,
\UART_TXFF/n173 , \UART_TXFF/n172 , \UART_TXFF/n171 ,
\UART_TXFF/n170 , \UART_TXFF/n169 , \UART_TXFF/n168 ,
\UART_TXFF/n167 , \UART_TXFF/n166 , \UART_TXFF/n165 ,
\UART_TXFF/n164 , \UART_TXFF/n163 , \UART_TXFF/n162 ,
\UART_TXFF/n161 , \UART_TXFF/n160 , \UART_TXFF/n159 ,
\UART_TXFF/n158 , \UART_TXFF/n157 , \UART_TXFF/n156 ,
\UART_TXFF/n155 , \UART_TXFF/n154 , \UART_TXFF/n153 ,
\UART_TXFF/n152 , \UART_TXFF/n151 , \UART_TXFF/n150 ,
\UART_TXFF/n149 , \UART_TXFF/n148 , \UART_TXFF/n147 ,
\UART_TXFF/n146 , \UART_TXFF/n145 , \UART_TXFF/n144 ,
\UART_TXFF/n143 , \UART_TXFF/n142 , \UART_TXFF/n141 ,
\UART_TXFF/n140 , \UART_TXFF/n139 , \UART_TXFF/n138 ,
\UART_TXFF/n137 , \UART_TXFF/n136 , \UART_TXFF/n135 ,
\UART_TXFF/n134 , \UART_TXFF/n133 , \UART_TXFF/n132 ,
\UART_TXFF/n131 , \UART_TXFF/n130 , \UART_TXFF/n129 ,
\UART_TXFF/n128 , \UART_TXFF/n127 , \UART_TXFF/n126 ,
\UART_TXFF/n125 , \UART_TXFF/n124 , \UART_TXFF/n123 ,
\UART_TXFF/n122 , \UART_TXFF/n121 , \UART_TXFF/n120 ,
\UART_TXFF/n119 , \UART_TXFF/n118 , \UART_TXFF/n117 ,
\UART_TXFF/n116 , \UART_TXFF/n115 , \UART_TXFF/n114 ,
\UART_TXFF/n113 , \UART_TXFF/n112 , \UART_TXFF/n111 ,
\UART_TXFF/n110 , \UART_TXFF/n109 , \UART_TXFF/n108 ,
\UART_TXFF/n107 , \UART_TXFF/n106 , \UART_TXFF/n105 ,
\UART_TXFF/n104 , \UART_TXFF/n103 , \UART_TXFF/n102 ,
\UART_TXFF/n101 , \UART_TXFF/n100 , \UART_TXFF/n99 , \UART_TXFF/n98 ,
\UART_TXFF/n97 , \UART_TXFF/n96 , \UART_TXFF/n95 , \UART_TXFF/n94 ,
\UART_TXFF/n93 , \UART_TXFF/n92 , \UART_TXFF/n91 , \UART_TXFF/n90 ,
\UART_TXFF/n89 , \UART_TXFF/n88 , \UART_TXFF/n87 , \UART_TXFF/n86 ,
\UART_TXFF/n85 , \UART_TXFF/n84 , \UART_TXFF/n83 , \UART_TXFF/n82 ,
\UART_TXFF/n81 , \UART_TXFF/n80 , \UART_TXFF/n79 , \UART_TXFF/n78 ,
\UART_TXFF/n77 , \UART_TXFF/n76 , \UART_TXFF/n75 , \UART_TXFF/n74 ,
\UART_TXFF/n73 , \UART_TXFF/n72 , \UART_TXFF/n71 , \UART_TXFF/n70 ,
\UART_TXFF/n69 , \UART_TXFF/n68 , \UART_TXFF/n67 , \UART_TXFF/n66 ,
\UART_TXFF/n65 , \UART_TXFF/n64 , \UART_TXFF/n63 , \UART_TXFF/n62 ,
\UART_TXFF/n61 , \UART_TXFF/n60 , \UART_TXFF/n59 , \UART_TXFF/n58 ,
\UART_TXFF/n57 , \UART_TXFF/n56 , \UART_TXFF/n55 , \UART_TXFF/n54 ,
\UART_TXFF/n53 , \UART_TXFF/n52 , \UART_TXFF/n51 , \UART_TXFF/n50 ,
\UART_TXFF/n49 , \UART_TXFF/n48 , \UART_TXFF/n47 , \UART_TXFF/n46 ,
\UART_TXFF/n45 , \UART_TXFF/n44 , \UART_TXFF/n43 , \UART_TXFF/n42 ,
\UART_TXFF/n41 , \UART_TXFF/n40 , \UART_TXFF/n39 , \UART_TXFF/n38 ,
\UART_TXFF/n37 , \UART_TXFF/n36 , \UART_TXFF/n35 , \UART_TXFF/n34 ,
\UART_TXFF/n32 , \UART_TXFF/n31 , \UART_TXFF/n30 , \UART_TXFF/n29 ,
\UART_TXFF/n28 , \UART_TXFF/n27 , \UART_TXFF/n26 , \UART_TXFF/n25 ,
\UART_TXFF/n24 , \UART_TXFF/n23 , \UART_TXFF/n22 , \UART_TXFF/n21 ,
\UART_TXFF/n20 , \UART_TXFF/n19 , \UART_TXFF/n18 , \UART_TXFF/n17 ,
\UART_TXFF/n16 , \UART_TXFF/n15 , \UART_TXFF/n14 , \UART_TXFF/n13 ,
\UART_TXFF/n12 , \UART_TXFF/n11 , \UART_TXFF/n10 , \UART_TXFF/n9 ,
\UART_TXFF/n8 , \UART_TXFF/n7 , \UART_TXFF/n6 , \UART_TXFF/n5 ,
\UART_TXFF/n4 , \UART_TXFF/n3 , \UART_TXFF/n2 , \UART_TXFF/n1 ,
\UART_TXFF/n1817 , \UART_TXFF/n1816 , \UART_TXFF/n1815 ,
\UART_TXFF/n1814 , \UART_TXFF/n1813 , \UART_TXFF/n1812 ,
\UART_TXFF/n1811 , \UART_TXFF/n1810 , \UART_TXFF/n1809 ,
\UART_TXFF/n1808 , \UART_TXFF/n1807 , \UART_TXFF/n1806 ,
\UART_TXFF/n1805 , \UART_TXFF/n1804 , \UART_TXFF/n1803 ,
\UART_TXFF/n1802 , \UART_TXFF/n1801 , \UART_TXFF/n1800 ,
\UART_TXFF/n1799 , \UART_TXFF/n1798 , \UART_TXFF/n1797 ,
\UART_TXFF/n1796 , \UART_TXFF/n1795 , \UART_TXFF/n1794 ,
\UART_TXFF/n1793 , \UART_TXFF/n1792 , \UART_TXFF/n1791 ,
\UART_TXFF/n1790 , \UART_TXFF/n1789 , \UART_TXFF/n1788 ,
\UART_TXFF/n1787 , \UART_TXFF/n1786 , \UART_TXFF/n1785 ,
\UART_TXFF/n1784 , \UART_TXFF/n1783 , \UART_TXFF/n1782 ,
\UART_TXFF/n1781 , \UART_TXFF/n1780 , \UART_TXFF/n1779 ,
\UART_TXFF/n1778 , \UART_TXFF/n1777 , \UART_TXFF/n1776 ,
\UART_TXFF/n1775 , \UART_TXFF/n1774 , \UART_TXFF/n1773 ,
\UART_TXFF/n1772 , \UART_TXFF/n1771 , \UART_TXFF/n1770 ,
\UART_TXFF/n1769 , \UART_TXFF/n1768 , \UART_TXFF/n1767 ,
\UART_TXFF/n1766 , \UART_TXFF/n1765 , \UART_TXFF/n1764 ,
\UART_TXFF/n1763 , \UART_TXFF/n1762 , \UART_TXFF/n1761 ,
\UART_TXFF/n1760 , \UART_TXFF/n1759 , \UART_TXFF/n1758 ,
\UART_TXFF/n1757 , \UART_TXFF/n1756 , \UART_TXFF/n1755 ,
\UART_TXFF/n1754 , \UART_TXFF/n1753 , \UART_TXFF/n1752 ,
\UART_TXFF/n1751 , \UART_TXFF/n1750 , \UART_TXFF/n1749 ,
\UART_TXFF/n1748 , \UART_TXFF/n1747 , \UART_TXFF/n1746 ,
\UART_TXFF/n1745 , \UART_TXFF/n1744 , \UART_TXFF/n1743 ,
\UART_TXFF/n1742 , \UART_TXFF/n1741 , \UART_TXFF/n1740 ,
\UART_TXFF/n1739 , \UART_TXFF/n1738 , \UART_TXFF/n1737 ,
\UART_TXFF/n1736 , \UART_TXFF/n1735 , \UART_TXFF/n1734 ,
\UART_TXFF/n1733 , \UART_TXFF/n1732 , \UART_TXFF/n1731 ,
\UART_TXFF/n1730 , \UART_TXFF/n1729 , \UART_TXFF/n1728 ,
\UART_TXFF/n1727 , \UART_TXFF/n1726 , \UART_TXFF/n1725 ,
\UART_TXFF/n1724 , \UART_TXFF/n1723 , \UART_TXFF/n1722 ,
\UART_TXFF/n1721 , \UART_TXFF/n1720 , \UART_TXFF/n1719 ,
\UART_TXFF/n1718 , \UART_TXFF/n1717 , \UART_TXFF/n1716 ,
\UART_TXFF/n1715 , \UART_TXFF/n1714 , \UART_TXFF/n1713 ,
\UART_TXFF/n1712 , \UART_TXFF/n1711 , \UART_TXFF/n1710 ,
\UART_TXFF/n1709 , \UART_TXFF/n1708 , \UART_TXFF/n1707 ,
\UART_TXFF/n1706 , \UART_TXFF/n1705 , \UART_TXFF/n1704 ,
\UART_TXFF/n1703 , \UART_TXFF/n1702 , \UART_TXFF/n1701 ,
\UART_TXFF/n1700 , \UART_TXFF/n1699 , \UART_TXFF/n1698 ,
\UART_TXFF/n1697 , \UART_TXFF/n1696 , \UART_TXFF/n1695 ,
\UART_TXFF/n1694 , \UART_TXFF/n1693 , \UART_TXFF/n1692 ,
\UART_TXFF/n1691 , \UART_TXFF/n1690 , \UART_TXFF/n1689 ,
\UART_TXFF/n1688 , \UART_TXFF/n1687 , \UART_TXFF/n1686 ,
\UART_TXFF/n1685 , \UART_TXFF/n1684 , \UART_TXFF/n1683 ,
\UART_TXFF/n1682 , \UART_TXFF/n1681 , \UART_TXFF/n1680 ,
\UART_TXFF/n1679 , \UART_TXFF/n1678 , \UART_TXFF/n1677 ,
\UART_TXFF/n1676 , \UART_TXFF/n1675 , \UART_TXFF/n1674 ,
\UART_TXFF/n1673 , \UART_TXFF/n1672 , \UART_TXFF/n1671 ,
\UART_TXFF/n1670 , \UART_TXFF/n1669 , \UART_TXFF/n1668 ,
\UART_TXFF/n1667 , \UART_TXFF/n1666 , \UART_TXFF/n1665 ,
\UART_TXFF/n1664 , \UART_TXFF/n1663 , \UART_TXFF/n1662 ,
\UART_TXFF/n1661 , \UART_TXFF/n1660 , \UART_TXFF/n1659 ,
\UART_TXFF/n1658 , \UART_TXFF/n1657 , \UART_TXFF/n1656 ,
\UART_TXFF/n1655 , \UART_TXFF/n1654 , \UART_TXFF/n1653 ,
\UART_TXFF/n1652 , \UART_TXFF/n1651 , \UART_TXFF/n1650 ,
\UART_TXFF/n1649 , \UART_TXFF/n1648 , \UART_TXFF/n1647 ,
\UART_TXFF/n1646 , \UART_TXFF/n1645 , \UART_TXFF/n1644 ,
\UART_TXFF/n1643 , \UART_TXFF/n1642 , \UART_TXFF/n1641 ,
\UART_TXFF/n1640 , \UART_TXFF/n1639 , \UART_TXFF/n1638 ,
\UART_TXFF/n1637 , \UART_TXFF/n1636 , \UART_TXFF/n1635 ,
\UART_TXFF/n1634 , \UART_TXFF/n1633 , \UART_TXFF/n1632 ,
\UART_TXFF/n1631 , \UART_TXFF/n1630 , \UART_TXFF/n1629 ,
\UART_TXFF/n1628 , \UART_TXFF/n1627 , \UART_TXFF/n1626 ,
\UART_TXFF/n1625 , \UART_TXFF/n1624 , \UART_TXFF/n1623 ,
\UART_TXFF/n1622 , \UART_TXFF/n1621 , \UART_TXFF/n1620 ,
\UART_TXFF/n1619 , \UART_TXFF/n1618 , \UART_TXFF/n1617 ,
\UART_TXFF/n1616 , \UART_TXFF/n1615 , \UART_TXFF/n1614 ,
\UART_TXFF/n1613 , \UART_TXFF/n1612 , \UART_TXFF/n1611 ,
\UART_TXFF/n1610 , \UART_TXFF/n1609 , \UART_TXFF/n1608 ,
\UART_TXFF/n1607 , \UART_TXFF/n1606 , \UART_TXFF/n1605 ,
\UART_TXFF/n1604 , \UART_TXFF/n1603 , \UART_TXFF/n1602 ,
\UART_TXFF/n1601 , \UART_TXFF/n1600 , \UART_TXFF/n1599 ,
\UART_TXFF/n1598 , \UART_TXFF/n1597 , \UART_TXFF/n1596 ,
\UART_TXFF/n1595 , \UART_TXFF/n1594 , \UART_TXFF/n1593 ,
\UART_TXFF/n1592 , \UART_TXFF/n1591 , \UART_TXFF/n1590 ,
\UART_TXFF/n1589 , \UART_TXFF/n1588 , \UART_TXFF/n1587 ,
\UART_TXFF/n1586 , \UART_TXFF/n1585 , \UART_TXFF/n1584 ,
\UART_TXFF/n1583 , \UART_TXFF/n1582 , \UART_TXFF/n1581 ,
\UART_TXFF/n1580 , \UART_TXFF/n1579 , \UART_TXFF/n1578 ,
\UART_TXFF/n1577 , \UART_TXFF/n1576 , \UART_TXFF/n1575 ,
\UART_TXFF/n1574 , \UART_TXFF/n1573 , \UART_TXFF/n1572 ,
\UART_TXFF/n1571 , \UART_TXFF/n1570 , \UART_TXFF/n1569 ,
\UART_TXFF/n1568 , \UART_TXFF/n1567 , \UART_TXFF/n1566 ,
\UART_TXFF/n1565 , \UART_TXFF/n1564 , \UART_TXFF/n1563 ,
\UART_TXFF/n1562 , \UART_TXFF/n1561 , \UART_TXFF/n1560 ,
\UART_TXFF/n1559 , \UART_TXFF/n1558 , \UART_TXFF/n1557 ,
\UART_TXFF/n1556 , \UART_TXFF/n1555 , \UART_TXFF/n1554 ,
\UART_TXFF/n1553 , \UART_TXFF/n1552 , \UART_TXFF/n1551 ,
\UART_TXFF/n1550 , \UART_TXFF/n1549 , \UART_TXFF/n1548 ,
\UART_TXFF/n1547 , \UART_TXFF/n1546 , \UART_TXFF/n1545 ,
\UART_TXFF/n1544 , \UART_TXFF/n1543 , \UART_TXFF/n1542 ,
\UART_TXFF/n1541 , \UART_TXFF/n1540 , \UART_TXFF/n1539 ,
\UART_TXFF/n1538 , \UART_TXFF/n1537 , \UART_TXFF/n1536 ,
\UART_TXFF/n1535 , \UART_TXFF/n1534 , \UART_TXFF/n1533 ,
\UART_TXFF/n1532 , \UART_TXFF/n1531 , \UART_TXFF/n1530 ,
\UART_TXFF/n1529 , \UART_TXFF/n1528 , \UART_TXFF/n1527 ,
\UART_TXFF/n1526 , \UART_TXFF/n1525 , \UART_TXFF/n1524 ,
\UART_TXFF/n1523 , \UART_TXFF/n1522 , \UART_TXFF/n1521 ,
\UART_TXFF/n1520 , \UART_TXFF/n1519 , \UART_TXFF/n1518 ,
\UART_TXFF/n1517 , \UART_TXFF/n1516 , \UART_TXFF/n1515 ,
\UART_TXFF/n1514 , \UART_TXFF/n1513 , \UART_TXFF/n1512 ,
\UART_TXFF/n1511 , \UART_TXFF/n1510 , \UART_TXFF/n1509 ,
\UART_TXFF/n1508 , \UART_TXFF/n1507 , \UART_TXFF/n1506 ,
\UART_TXFF/n1505 , \UART_TXFF/n1504 , \UART_TXFF/n1503 ,
\UART_TXFF/n1502 , \UART_TXFF/n1501 , \UART_TXFF/n1500 ,
\UART_TXFF/n1499 , \UART_TXFF/n1498 , \UART_TXFF/n1497 ,
\UART_TXFF/n1496 , \UART_TXFF/n1495 , \UART_TXFF/n1494 ,
\UART_TXFF/n1493 , \UART_TXFF/n1492 , \UART_TXFF/n1491 ,
\UART_TXFF/n1490 , \UART_TXFF/n1489 , \UART_TXFF/n1488 ,
\UART_TXFF/n1487 , \UART_TXFF/n1486 , \UART_TXFF/n1485 ,
\UART_TXFF/n1484 , \UART_TXFF/n1483 , \UART_TXFF/n1482 ,
\UART_TXFF/n1481 , \UART_TXFF/n1480 , \UART_TXFF/n1479 ,
\UART_TXFF/n1478 , \UART_TXFF/n1477 , \UART_TXFF/n1476 ,
\UART_TXFF/n1475 , \UART_TXFF/n1474 , \UART_TXFF/n1473 ,
\UART_TXFF/n1472 , \UART_TXFF/n1471 , \UART_TXFF/n1470 ,
\UART_TXFF/n1469 , \UART_TXFF/n1468 , \UART_TXFF/n1467 ,
\UART_TXFF/n1466 , \UART_TXFF/n1465 , \UART_TXFF/n1464 ,
\UART_TXFF/n1463 , \UART_TXFF/n1462 , \UART_TXFF/n1461 ,
\UART_TXFF/n1460 , \UART_TXFF/n1459 , \UART_TXFF/n1458 ,
\UART_TXFF/n1457 , \UART_TXFF/n1456 , \UART_TXFF/n1455 ,
\UART_TXFF/n1454 , \UART_TXFF/n1453 , \UART_TXFF/n1452 ,
\UART_TXFF/n1451 , \UART_TXFF/n1450 , \UART_TXFF/n1449 ,
\UART_TXFF/n1448 , \UART_TXFF/n1447 , \UART_TXFF/n1446 ,
\UART_TXFF/n1445 , \UART_TXFF/n1444 , \UART_TXFF/n1443 ,
\UART_TXFF/n1442 , \UART_TXFF/n1441 , \UART_TXFF/n1440 ,
\UART_TXFF/n1439 , \UART_TXFF/n1438 , \UART_TXFF/n1437 ,
\UART_TXFF/n1436 , \UART_TXFF/n1435 , \UART_TXFF/n1434 ,
\UART_TXFF/n1433 , \UART_TXFF/n1432 , \UART_TXFF/n1431 ,
\UART_TXFF/n1430 , \UART_TXFF/n1429 , \UART_TXFF/n1428 ,
\UART_TXFF/n1427 , \UART_TXFF/n1426 , \UART_TXFF/n1425 ,
\UART_TXFF/n1424 , \UART_TXFF/n1423 , \UART_TXFF/n1422 ,
\UART_TXFF/n1421 , \UART_TXFF/n1420 , \UART_TXFF/n1419 ,
\UART_TXFF/n1418 , \UART_TXFF/n1417 , \UART_TXFF/n1416 ,
\UART_TXFF/n1415 , \UART_TXFF/n1414 , \UART_TXFF/n1413 ,
\UART_TXFF/n1412 , \UART_TXFF/n1411 , \UART_TXFF/n1410 ,
\UART_TXFF/n1409 , \UART_TXFF/n1408 , \UART_TXFF/n1407 ,
\UART_TXFF/n1406 , \UART_TXFF/n1405 , \UART_TXFF/n1404 ,
\UART_TXFF/n1403 , \UART_TXFF/n1402 , \UART_TXFF/n1401 ,
\UART_TXFF/n1400 , \UART_TXFF/n1399 , \UART_TXFF/n1398 ,
\UART_TXFF/n1397 , \UART_TXFF/n1396 , \UART_TXFF/n1395 ,
\UART_TXFF/n1394 , \UART_TXFF/n1393 , \UART_TXFF/n1392 ,
\UART_TXFF/n1391 , \UART_TXFF/n1390 , \UART_TXFF/n1389 ,
\UART_TXFF/n1388 , \UART_TXFF/n1387 , \UART_TXFF/n1386 ,
\UART_TXFF/n1385 , \UART_TXFF/n1384 , \UART_TXFF/n1383 ,
\UART_TXFF/n1382 , \UART_TXFF/n1381 , \UART_TXFF/n1380 ,
\UART_TXFF/n1379 , \UART_TXFF/n1378 , \UART_TXFF/n1377 ,
\UART_TXFF/n1376 , \UART_TXFF/n1375 , \UART_TXFF/n1374 ,
\UART_TXFF/n1373 , \UART_TXFF/n1372 , \UART_TXFF/n1371 ,
\UART_TXFF/n1370 , \UART_TXFF/n1369 , \UART_TXFF/n1368 ,
\UART_TXFF/n1367 , \UART_TXFF/n1366 , \UART_TXFF/n1365 ,
\UART_TXFF/n1364 , \UART_TXFF/n1363 , \UART_TXFF/n1362 ,
\UART_TXFF/n1361 , \UART_TXFF/n1360 , \UART_TXFF/n1359 ,
\UART_TXFF/n1358 , \UART_TXFF/n1357 , \UART_TXFF/n1356 ,
\UART_TXFF/n1355 , \UART_TXFF/n1354 , \UART_TXFF/n1353 ,
\UART_TXFF/n1352 , \UART_TXFF/n1351 , \UART_TXFF/n1350 ,
\UART_TXFF/n1349 , \UART_TXFF/n1348 , \UART_TXFF/n1347 ,
\UART_TXFF/n1346 , \UART_TXFF/n1345 , \UART_TXFF/n1344 ,
\UART_TXFF/n1343 , \UART_TXFF/n1342 , \UART_TXFF/n1341 ,
\UART_TXFF/n1340 , \UART_TXFF/n1339 , \UART_TXFF/n1338 ,
\UART_TXFF/n1337 , \UART_TXFF/n1336 , \UART_TXFF/n1335 ,
\UART_TXFF/n1334 , \UART_TXFF/n1333 , \UART_TXFF/n1332 ,
\UART_TXFF/n1331 , \UART_TXFF/n1330 , \UART_TXFF/n1329 ,
\UART_TXFF/n1328 , \UART_TXFF/n1327 , \UART_TXFF/n1326 ,
\UART_TXFF/n1325 , \UART_TXFF/n1324 , \UART_TXFF/n1323 ,
\UART_TXFF/n1322 , \UART_TXFF/n1321 , \UART_TXFF/n1320 ,
\UART_TXFF/n1319 , \UART_TXFF/n1318 , \UART_TXFF/n1317 ,
\UART_TXFF/n1316 , \UART_TXFF/n1315 , \UART_TXFF/n1314 ,
\UART_TXFF/n1313 , \UART_TXFF/n1312 , \UART_TXFF/n1311 ,
\UART_TXFF/n1310 , \UART_TXFF/n1309 , \UART_TXFF/n1308 ,
\UART_TXFF/n1307 , \UART_TXFF/n1306 , \UART_TXFF/n1305 ,
\UART_TXFF/n1304 , \UART_TXFF/n1303 , \UART_TXFF/n1302 ,
\UART_TXFF/n1301 , \UART_TXFF/n1300 , \UART_TXFF/n1299 ,
\UART_TXFF/n1298 , \UART_TXFF/n1297 , \UART_TXFF/n1296 ,
\UART_TXFF/n1295 , \UART_TXFF/n1294 , \UART_TXFF/n1293 ,
\UART_TXFF/n1292 , \UART_TXFF/n1291 , \UART_TXFF/n1290 ,
\UART_TXFF/n1289 , \UART_TXFF/n1288 , \UART_TXFF/n1287 ,
\UART_TXFF/n772 , \UART_TXFF/n770 , \UART_TXFF/n768 ,
\UART_TXFF/n766 , \UART_TXFF/n764 , \UART_TXFF/n762 ,
\UART_TXFF/n760 , \UART_TXFF/n758 , \UART_TXFF/N130 ,
\UART_TXFF/N129 , \UART_TXFF/N128 , \UART_TXFF/N127 ,
\UART_TXFF/N126 , \UART_TXFF/N125 , \UART_TXFF/N124 ,
\UART_TXFF/N123 , \UART_TXFF/iFIFOMem[0][0] ,
\UART_TXFF/iFIFOMem[0][1] , \UART_TXFF/iFIFOMem[0][2] ,
\UART_TXFF/iFIFOMem[0][3] , \UART_TXFF/iFIFOMem[0][4] ,
\UART_TXFF/iFIFOMem[0][5] , \UART_TXFF/iFIFOMem[0][6] ,
\UART_TXFF/iFIFOMem[0][7] , \UART_TXFF/iFIFOMem[1][0] ,
\UART_TXFF/iFIFOMem[1][1] , \UART_TXFF/iFIFOMem[1][2] ,
\UART_TXFF/iFIFOMem[1][3] , \UART_TXFF/iFIFOMem[1][4] ,
\UART_TXFF/iFIFOMem[1][5] , \UART_TXFF/iFIFOMem[1][6] ,
\UART_TXFF/iFIFOMem[1][7] , \UART_TXFF/iFIFOMem[2][0] ,
\UART_TXFF/iFIFOMem[2][1] , \UART_TXFF/iFIFOMem[2][2] ,
\UART_TXFF/iFIFOMem[2][3] , \UART_TXFF/iFIFOMem[2][4] ,
\UART_TXFF/iFIFOMem[2][5] , \UART_TXFF/iFIFOMem[2][6] ,
\UART_TXFF/iFIFOMem[2][7] , \UART_TXFF/iFIFOMem[3][0] ,
\UART_TXFF/iFIFOMem[3][1] , \UART_TXFF/iFIFOMem[3][2] ,
\UART_TXFF/iFIFOMem[3][3] , \UART_TXFF/iFIFOMem[3][4] ,
\UART_TXFF/iFIFOMem[3][5] , \UART_TXFF/iFIFOMem[3][6] ,
\UART_TXFF/iFIFOMem[3][7] , \UART_TXFF/iFIFOMem[4][0] ,
\UART_TXFF/iFIFOMem[4][1] , \UART_TXFF/iFIFOMem[4][2] ,
\UART_TXFF/iFIFOMem[4][3] , \UART_TXFF/iFIFOMem[4][4] ,
\UART_TXFF/iFIFOMem[4][5] , \UART_TXFF/iFIFOMem[4][6] ,
\UART_TXFF/iFIFOMem[4][7] , \UART_TXFF/iFIFOMem[5][0] ,
\UART_TXFF/iFIFOMem[5][1] , \UART_TXFF/iFIFOMem[5][2] ,
\UART_TXFF/iFIFOMem[5][3] , \UART_TXFF/iFIFOMem[5][4] ,
\UART_TXFF/iFIFOMem[5][5] , \UART_TXFF/iFIFOMem[5][6] ,
\UART_TXFF/iFIFOMem[5][7] , \UART_TXFF/iFIFOMem[6][0] ,
\UART_TXFF/iFIFOMem[6][1] , \UART_TXFF/iFIFOMem[6][2] ,
\UART_TXFF/iFIFOMem[6][3] , \UART_TXFF/iFIFOMem[6][4] ,
\UART_TXFF/iFIFOMem[6][5] , \UART_TXFF/iFIFOMem[6][6] ,
\UART_TXFF/iFIFOMem[6][7] , \UART_TXFF/iFIFOMem[7][0] ,
\UART_TXFF/iFIFOMem[7][1] , \UART_TXFF/iFIFOMem[7][2] ,
\UART_TXFF/iFIFOMem[7][3] , \UART_TXFF/iFIFOMem[7][4] ,
\UART_TXFF/iFIFOMem[7][5] , \UART_TXFF/iFIFOMem[7][6] ,
\UART_TXFF/iFIFOMem[7][7] , \UART_TXFF/iFIFOMem[8][0] ,
\UART_TXFF/iFIFOMem[8][1] , \UART_TXFF/iFIFOMem[8][2] ,
\UART_TXFF/iFIFOMem[8][3] , \UART_TXFF/iFIFOMem[8][4] ,
\UART_TXFF/iFIFOMem[8][5] , \UART_TXFF/iFIFOMem[8][6] ,
\UART_TXFF/iFIFOMem[8][7] , \UART_TXFF/iFIFOMem[9][0] ,
\UART_TXFF/iFIFOMem[9][1] , \UART_TXFF/iFIFOMem[9][2] ,
\UART_TXFF/iFIFOMem[9][3] , \UART_TXFF/iFIFOMem[9][4] ,
\UART_TXFF/iFIFOMem[9][5] , \UART_TXFF/iFIFOMem[9][6] ,
\UART_TXFF/iFIFOMem[9][7] , \UART_TXFF/iFIFOMem[10][0] ,
\UART_TXFF/iFIFOMem[10][1] , \UART_TXFF/iFIFOMem[10][2] ,
\UART_TXFF/iFIFOMem[10][3] , \UART_TXFF/iFIFOMem[10][4] ,
\UART_TXFF/iFIFOMem[10][5] , \UART_TXFF/iFIFOMem[10][6] ,
\UART_TXFF/iFIFOMem[10][7] , \UART_TXFF/iFIFOMem[11][0] ,
\UART_TXFF/iFIFOMem[11][1] , \UART_TXFF/iFIFOMem[11][2] ,
\UART_TXFF/iFIFOMem[11][3] , \UART_TXFF/iFIFOMem[11][4] ,
\UART_TXFF/iFIFOMem[11][5] , \UART_TXFF/iFIFOMem[11][6] ,
\UART_TXFF/iFIFOMem[11][7] , \UART_TXFF/iFIFOMem[12][0] ,
\UART_TXFF/iFIFOMem[12][1] , \UART_TXFF/iFIFOMem[12][2] ,
\UART_TXFF/iFIFOMem[12][3] , \UART_TXFF/iFIFOMem[12][4] ,
\UART_TXFF/iFIFOMem[12][5] , \UART_TXFF/iFIFOMem[12][6] ,
\UART_TXFF/iFIFOMem[12][7] , \UART_TXFF/iFIFOMem[13][0] ,
\UART_TXFF/iFIFOMem[13][1] , \UART_TXFF/iFIFOMem[13][2] ,
\UART_TXFF/iFIFOMem[13][3] , \UART_TXFF/iFIFOMem[13][4] ,
\UART_TXFF/iFIFOMem[13][5] , \UART_TXFF/iFIFOMem[13][6] ,
\UART_TXFF/iFIFOMem[13][7] , \UART_TXFF/iFIFOMem[14][0] ,
\UART_TXFF/iFIFOMem[14][1] , \UART_TXFF/iFIFOMem[14][2] ,
\UART_TXFF/iFIFOMem[14][3] , \UART_TXFF/iFIFOMem[14][4] ,
\UART_TXFF/iFIFOMem[14][5] , \UART_TXFF/iFIFOMem[14][6] ,
\UART_TXFF/iFIFOMem[14][7] , \UART_TXFF/iFIFOMem[15][0] ,
\UART_TXFF/iFIFOMem[15][1] , \UART_TXFF/iFIFOMem[15][2] ,
\UART_TXFF/iFIFOMem[15][3] , \UART_TXFF/iFIFOMem[15][4] ,
\UART_TXFF/iFIFOMem[15][5] , \UART_TXFF/iFIFOMem[15][6] ,
\UART_TXFF/iFIFOMem[15][7] , \UART_TXFF/iFIFOMem[16][0] ,
\UART_TXFF/iFIFOMem[16][1] , \UART_TXFF/iFIFOMem[16][2] ,
\UART_TXFF/iFIFOMem[16][3] , \UART_TXFF/iFIFOMem[16][4] ,
\UART_TXFF/iFIFOMem[16][5] , \UART_TXFF/iFIFOMem[16][6] ,
\UART_TXFF/iFIFOMem[16][7] , \UART_TXFF/iFIFOMem[17][0] ,
\UART_TXFF/iFIFOMem[17][1] , \UART_TXFF/iFIFOMem[17][2] ,
\UART_TXFF/iFIFOMem[17][3] , \UART_TXFF/iFIFOMem[17][4] ,
\UART_TXFF/iFIFOMem[17][5] , \UART_TXFF/iFIFOMem[17][6] ,
\UART_TXFF/iFIFOMem[17][7] , \UART_TXFF/iFIFOMem[18][0] ,
\UART_TXFF/iFIFOMem[18][1] , \UART_TXFF/iFIFOMem[18][2] ,
\UART_TXFF/iFIFOMem[18][3] , \UART_TXFF/iFIFOMem[18][4] ,
\UART_TXFF/iFIFOMem[18][5] , \UART_TXFF/iFIFOMem[18][6] ,
\UART_TXFF/iFIFOMem[18][7] , \UART_TXFF/iFIFOMem[19][0] ,
\UART_TXFF/iFIFOMem[19][1] , \UART_TXFF/iFIFOMem[19][2] ,
\UART_TXFF/iFIFOMem[19][3] , \UART_TXFF/iFIFOMem[19][4] ,
\UART_TXFF/iFIFOMem[19][5] , \UART_TXFF/iFIFOMem[19][6] ,
\UART_TXFF/iFIFOMem[19][7] , \UART_TXFF/iFIFOMem[20][0] ,
\UART_TXFF/iFIFOMem[20][1] , \UART_TXFF/iFIFOMem[20][2] ,
\UART_TXFF/iFIFOMem[20][3] , \UART_TXFF/iFIFOMem[20][4] ,
\UART_TXFF/iFIFOMem[20][5] , \UART_TXFF/iFIFOMem[20][6] ,
\UART_TXFF/iFIFOMem[20][7] , \UART_TXFF/iFIFOMem[21][0] ,
\UART_TXFF/iFIFOMem[21][1] , \UART_TXFF/iFIFOMem[21][2] ,
\UART_TXFF/iFIFOMem[21][3] , \UART_TXFF/iFIFOMem[21][4] ,
\UART_TXFF/iFIFOMem[21][5] , \UART_TXFF/iFIFOMem[21][6] ,
\UART_TXFF/iFIFOMem[21][7] , \UART_TXFF/iFIFOMem[22][0] ,
\UART_TXFF/iFIFOMem[22][1] , \UART_TXFF/iFIFOMem[22][2] ,
\UART_TXFF/iFIFOMem[22][3] , \UART_TXFF/iFIFOMem[22][4] ,
\UART_TXFF/iFIFOMem[22][5] , \UART_TXFF/iFIFOMem[22][6] ,
\UART_TXFF/iFIFOMem[22][7] , \UART_TXFF/iFIFOMem[23][0] ,
\UART_TXFF/iFIFOMem[23][1] , \UART_TXFF/iFIFOMem[23][2] ,
\UART_TXFF/iFIFOMem[23][3] , \UART_TXFF/iFIFOMem[23][4] ,
\UART_TXFF/iFIFOMem[23][5] , \UART_TXFF/iFIFOMem[23][6] ,
\UART_TXFF/iFIFOMem[23][7] , \UART_TXFF/iFIFOMem[24][0] ,
\UART_TXFF/iFIFOMem[24][1] , \UART_TXFF/iFIFOMem[24][2] ,
\UART_TXFF/iFIFOMem[24][3] , \UART_TXFF/iFIFOMem[24][4] ,
\UART_TXFF/iFIFOMem[24][5] , \UART_TXFF/iFIFOMem[24][6] ,
\UART_TXFF/iFIFOMem[24][7] , \UART_TXFF/iFIFOMem[25][0] ,
\UART_TXFF/iFIFOMem[25][1] , \UART_TXFF/iFIFOMem[25][2] ,
\UART_TXFF/iFIFOMem[25][3] , \UART_TXFF/iFIFOMem[25][4] ,
\UART_TXFF/iFIFOMem[25][5] , \UART_TXFF/iFIFOMem[25][6] ,
\UART_TXFF/iFIFOMem[25][7] , \UART_TXFF/iFIFOMem[26][0] ,
\UART_TXFF/iFIFOMem[26][1] , \UART_TXFF/iFIFOMem[26][2] ,
\UART_TXFF/iFIFOMem[26][3] , \UART_TXFF/iFIFOMem[26][4] ,
\UART_TXFF/iFIFOMem[26][5] , \UART_TXFF/iFIFOMem[26][6] ,
\UART_TXFF/iFIFOMem[26][7] , \UART_TXFF/iFIFOMem[27][0] ,
\UART_TXFF/iFIFOMem[27][1] , \UART_TXFF/iFIFOMem[27][2] ,
\UART_TXFF/iFIFOMem[27][3] , \UART_TXFF/iFIFOMem[27][4] ,
\UART_TXFF/iFIFOMem[27][5] , \UART_TXFF/iFIFOMem[27][6] ,
\UART_TXFF/iFIFOMem[27][7] , \UART_TXFF/iFIFOMem[28][0] ,
\UART_TXFF/iFIFOMem[28][1] , \UART_TXFF/iFIFOMem[28][2] ,
\UART_TXFF/iFIFOMem[28][3] , \UART_TXFF/iFIFOMem[28][4] ,
\UART_TXFF/iFIFOMem[28][5] , \UART_TXFF/iFIFOMem[28][6] ,
\UART_TXFF/iFIFOMem[28][7] , \UART_TXFF/iFIFOMem[29][0] ,
\UART_TXFF/iFIFOMem[29][1] , \UART_TXFF/iFIFOMem[29][2] ,
\UART_TXFF/iFIFOMem[29][3] , \UART_TXFF/iFIFOMem[29][4] ,
\UART_TXFF/iFIFOMem[29][5] , \UART_TXFF/iFIFOMem[29][6] ,
\UART_TXFF/iFIFOMem[29][7] , \UART_TXFF/iFIFOMem[30][0] ,
\UART_TXFF/iFIFOMem[30][1] , \UART_TXFF/iFIFOMem[30][2] ,
\UART_TXFF/iFIFOMem[30][3] , \UART_TXFF/iFIFOMem[30][4] ,
\UART_TXFF/iFIFOMem[30][5] , \UART_TXFF/iFIFOMem[30][6] ,
\UART_TXFF/iFIFOMem[30][7] , \UART_TXFF/iFIFOMem[31][0] ,
\UART_TXFF/iFIFOMem[31][1] , \UART_TXFF/iFIFOMem[31][2] ,
\UART_TXFF/iFIFOMem[31][3] , \UART_TXFF/iFIFOMem[31][4] ,
\UART_TXFF/iFIFOMem[31][5] , \UART_TXFF/iFIFOMem[31][6] ,
\UART_TXFF/iFIFOMem[31][7] , \UART_TXFF/iFIFOMem[32][0] ,
\UART_TXFF/iFIFOMem[32][1] , \UART_TXFF/iFIFOMem[32][2] ,
\UART_TXFF/iFIFOMem[32][3] , \UART_TXFF/iFIFOMem[32][4] ,
\UART_TXFF/iFIFOMem[32][5] , \UART_TXFF/iFIFOMem[32][6] ,
\UART_TXFF/iFIFOMem[32][7] , \UART_TXFF/iFIFOMem[33][0] ,
\UART_TXFF/iFIFOMem[33][1] , \UART_TXFF/iFIFOMem[33][2] ,
\UART_TXFF/iFIFOMem[33][3] , \UART_TXFF/iFIFOMem[33][4] ,
\UART_TXFF/iFIFOMem[33][5] , \UART_TXFF/iFIFOMem[33][6] ,
\UART_TXFF/iFIFOMem[33][7] , \UART_TXFF/iFIFOMem[34][0] ,
\UART_TXFF/iFIFOMem[34][1] , \UART_TXFF/iFIFOMem[34][2] ,
\UART_TXFF/iFIFOMem[34][3] , \UART_TXFF/iFIFOMem[34][4] ,
\UART_TXFF/iFIFOMem[34][5] , \UART_TXFF/iFIFOMem[34][6] ,
\UART_TXFF/iFIFOMem[34][7] , \UART_TXFF/iFIFOMem[35][0] ,
\UART_TXFF/iFIFOMem[35][1] , \UART_TXFF/iFIFOMem[35][2] ,
\UART_TXFF/iFIFOMem[35][3] , \UART_TXFF/iFIFOMem[35][4] ,
\UART_TXFF/iFIFOMem[35][5] , \UART_TXFF/iFIFOMem[35][6] ,
\UART_TXFF/iFIFOMem[35][7] , \UART_TXFF/iFIFOMem[36][0] ,
\UART_TXFF/iFIFOMem[36][1] , \UART_TXFF/iFIFOMem[36][2] ,
\UART_TXFF/iFIFOMem[36][3] , \UART_TXFF/iFIFOMem[36][4] ,
\UART_TXFF/iFIFOMem[36][5] , \UART_TXFF/iFIFOMem[36][6] ,
\UART_TXFF/iFIFOMem[36][7] , \UART_TXFF/iFIFOMem[37][0] ,
\UART_TXFF/iFIFOMem[37][1] , \UART_TXFF/iFIFOMem[37][2] ,
\UART_TXFF/iFIFOMem[37][3] , \UART_TXFF/iFIFOMem[37][4] ,
\UART_TXFF/iFIFOMem[37][5] , \UART_TXFF/iFIFOMem[37][6] ,
\UART_TXFF/iFIFOMem[37][7] , \UART_TXFF/iFIFOMem[38][0] ,
\UART_TXFF/iFIFOMem[38][1] , \UART_TXFF/iFIFOMem[38][2] ,
\UART_TXFF/iFIFOMem[38][3] , \UART_TXFF/iFIFOMem[38][4] ,
\UART_TXFF/iFIFOMem[38][5] , \UART_TXFF/iFIFOMem[38][6] ,
\UART_TXFF/iFIFOMem[38][7] , \UART_TXFF/iFIFOMem[39][0] ,
\UART_TXFF/iFIFOMem[39][1] , \UART_TXFF/iFIFOMem[39][2] ,
\UART_TXFF/iFIFOMem[39][3] , \UART_TXFF/iFIFOMem[39][4] ,
\UART_TXFF/iFIFOMem[39][5] , \UART_TXFF/iFIFOMem[39][6] ,
\UART_TXFF/iFIFOMem[39][7] , \UART_TXFF/iFIFOMem[40][0] ,
\UART_TXFF/iFIFOMem[40][1] , \UART_TXFF/iFIFOMem[40][2] ,
\UART_TXFF/iFIFOMem[40][3] , \UART_TXFF/iFIFOMem[40][4] ,
\UART_TXFF/iFIFOMem[40][5] , \UART_TXFF/iFIFOMem[40][6] ,
\UART_TXFF/iFIFOMem[40][7] , \UART_TXFF/iFIFOMem[41][0] ,
\UART_TXFF/iFIFOMem[41][1] , \UART_TXFF/iFIFOMem[41][2] ,
\UART_TXFF/iFIFOMem[41][3] , \UART_TXFF/iFIFOMem[41][4] ,
\UART_TXFF/iFIFOMem[41][5] , \UART_TXFF/iFIFOMem[41][6] ,
\UART_TXFF/iFIFOMem[41][7] , \UART_TXFF/iFIFOMem[42][0] ,
\UART_TXFF/iFIFOMem[42][1] , \UART_TXFF/iFIFOMem[42][2] ,
\UART_TXFF/iFIFOMem[42][3] , \UART_TXFF/iFIFOMem[42][4] ,
\UART_TXFF/iFIFOMem[42][5] , \UART_TXFF/iFIFOMem[42][6] ,
\UART_TXFF/iFIFOMem[42][7] , \UART_TXFF/iFIFOMem[43][0] ,
\UART_TXFF/iFIFOMem[43][1] , \UART_TXFF/iFIFOMem[43][2] ,
\UART_TXFF/iFIFOMem[43][3] , \UART_TXFF/iFIFOMem[43][4] ,
\UART_TXFF/iFIFOMem[43][5] , \UART_TXFF/iFIFOMem[43][6] ,
\UART_TXFF/iFIFOMem[43][7] , \UART_TXFF/iFIFOMem[44][0] ,
\UART_TXFF/iFIFOMem[44][1] , \UART_TXFF/iFIFOMem[44][2] ,
\UART_TXFF/iFIFOMem[44][3] , \UART_TXFF/iFIFOMem[44][4] ,
\UART_TXFF/iFIFOMem[44][5] , \UART_TXFF/iFIFOMem[44][6] ,
\UART_TXFF/iFIFOMem[44][7] , \UART_TXFF/iFIFOMem[45][0] ,
\UART_TXFF/iFIFOMem[45][1] , \UART_TXFF/iFIFOMem[45][2] ,
\UART_TXFF/iFIFOMem[45][3] , \UART_TXFF/iFIFOMem[45][4] ,
\UART_TXFF/iFIFOMem[45][5] , \UART_TXFF/iFIFOMem[45][6] ,
\UART_TXFF/iFIFOMem[45][7] , \UART_TXFF/iFIFOMem[46][0] ,
\UART_TXFF/iFIFOMem[46][1] , \UART_TXFF/iFIFOMem[46][2] ,
\UART_TXFF/iFIFOMem[46][3] , \UART_TXFF/iFIFOMem[46][4] ,
\UART_TXFF/iFIFOMem[46][5] , \UART_TXFF/iFIFOMem[46][6] ,
\UART_TXFF/iFIFOMem[46][7] , \UART_TXFF/iFIFOMem[47][0] ,
\UART_TXFF/iFIFOMem[47][1] , \UART_TXFF/iFIFOMem[47][2] ,
\UART_TXFF/iFIFOMem[47][3] , \UART_TXFF/iFIFOMem[47][4] ,
\UART_TXFF/iFIFOMem[47][5] , \UART_TXFF/iFIFOMem[47][6] ,
\UART_TXFF/iFIFOMem[47][7] , \UART_TXFF/iFIFOMem[48][0] ,
\UART_TXFF/iFIFOMem[48][1] , \UART_TXFF/iFIFOMem[48][2] ,
\UART_TXFF/iFIFOMem[48][3] , \UART_TXFF/iFIFOMem[48][4] ,
\UART_TXFF/iFIFOMem[48][5] , \UART_TXFF/iFIFOMem[48][6] ,
\UART_TXFF/iFIFOMem[48][7] , \UART_TXFF/iFIFOMem[49][0] ,
\UART_TXFF/iFIFOMem[49][1] , \UART_TXFF/iFIFOMem[49][2] ,
\UART_TXFF/iFIFOMem[49][3] , \UART_TXFF/iFIFOMem[49][4] ,
\UART_TXFF/iFIFOMem[49][5] , \UART_TXFF/iFIFOMem[49][6] ,
\UART_TXFF/iFIFOMem[49][7] , \UART_TXFF/iFIFOMem[50][0] ,
\UART_TXFF/iFIFOMem[50][1] , \UART_TXFF/iFIFOMem[50][2] ,
\UART_TXFF/iFIFOMem[50][3] , \UART_TXFF/iFIFOMem[50][4] ,
\UART_TXFF/iFIFOMem[50][5] , \UART_TXFF/iFIFOMem[50][6] ,
\UART_TXFF/iFIFOMem[50][7] , \UART_TXFF/iFIFOMem[51][0] ,
\UART_TXFF/iFIFOMem[51][1] , \UART_TXFF/iFIFOMem[51][2] ,
\UART_TXFF/iFIFOMem[51][3] , \UART_TXFF/iFIFOMem[51][4] ,
\UART_TXFF/iFIFOMem[51][5] , \UART_TXFF/iFIFOMem[51][6] ,
\UART_TXFF/iFIFOMem[51][7] , \UART_TXFF/iFIFOMem[52][0] ,
\UART_TXFF/iFIFOMem[52][1] , \UART_TXFF/iFIFOMem[52][2] ,
\UART_TXFF/iFIFOMem[52][3] , \UART_TXFF/iFIFOMem[52][4] ,
\UART_TXFF/iFIFOMem[52][5] , \UART_TXFF/iFIFOMem[52][6] ,
\UART_TXFF/iFIFOMem[52][7] , \UART_TXFF/iFIFOMem[53][0] ,
\UART_TXFF/iFIFOMem[53][1] , \UART_TXFF/iFIFOMem[53][2] ,
\UART_TXFF/iFIFOMem[53][3] , \UART_TXFF/iFIFOMem[53][4] ,
\UART_TXFF/iFIFOMem[53][5] , \UART_TXFF/iFIFOMem[53][6] ,
\UART_TXFF/iFIFOMem[53][7] , \UART_TXFF/iFIFOMem[54][0] ,
\UART_TXFF/iFIFOMem[54][1] , \UART_TXFF/iFIFOMem[54][2] ,
\UART_TXFF/iFIFOMem[54][3] , \UART_TXFF/iFIFOMem[54][4] ,
\UART_TXFF/iFIFOMem[54][5] , \UART_TXFF/iFIFOMem[54][6] ,
\UART_TXFF/iFIFOMem[54][7] , \UART_TXFF/iFIFOMem[55][0] ,
\UART_TXFF/iFIFOMem[55][1] , \UART_TXFF/iFIFOMem[55][2] ,
\UART_TXFF/iFIFOMem[55][3] , \UART_TXFF/iFIFOMem[55][4] ,
\UART_TXFF/iFIFOMem[55][5] , \UART_TXFF/iFIFOMem[55][6] ,
\UART_TXFF/iFIFOMem[55][7] , \UART_TXFF/iFIFOMem[56][0] ,
\UART_TXFF/iFIFOMem[56][1] , \UART_TXFF/iFIFOMem[56][2] ,
\UART_TXFF/iFIFOMem[56][3] , \UART_TXFF/iFIFOMem[56][4] ,
\UART_TXFF/iFIFOMem[56][5] , \UART_TXFF/iFIFOMem[56][6] ,
\UART_TXFF/iFIFOMem[56][7] , \UART_TXFF/iFIFOMem[57][0] ,
\UART_TXFF/iFIFOMem[57][1] , \UART_TXFF/iFIFOMem[57][2] ,
\UART_TXFF/iFIFOMem[57][3] , \UART_TXFF/iFIFOMem[57][4] ,
\UART_TXFF/iFIFOMem[57][5] , \UART_TXFF/iFIFOMem[57][6] ,
\UART_TXFF/iFIFOMem[57][7] , \UART_TXFF/iFIFOMem[58][0] ,
\UART_TXFF/iFIFOMem[58][1] , \UART_TXFF/iFIFOMem[58][2] ,
\UART_TXFF/iFIFOMem[58][3] , \UART_TXFF/iFIFOMem[58][4] ,
\UART_TXFF/iFIFOMem[58][5] , \UART_TXFF/iFIFOMem[58][6] ,
\UART_TXFF/iFIFOMem[58][7] , \UART_TXFF/iFIFOMem[59][0] ,
\UART_TXFF/iFIFOMem[59][1] , \UART_TXFF/iFIFOMem[59][2] ,
\UART_TXFF/iFIFOMem[59][3] , \UART_TXFF/iFIFOMem[59][4] ,
\UART_TXFF/iFIFOMem[59][5] , \UART_TXFF/iFIFOMem[59][6] ,
\UART_TXFF/iFIFOMem[59][7] , \UART_TXFF/iFIFOMem[60][0] ,
\UART_TXFF/iFIFOMem[60][1] , \UART_TXFF/iFIFOMem[60][2] ,
\UART_TXFF/iFIFOMem[60][3] , \UART_TXFF/iFIFOMem[60][4] ,
\UART_TXFF/iFIFOMem[60][5] , \UART_TXFF/iFIFOMem[60][6] ,
\UART_TXFF/iFIFOMem[60][7] , \UART_TXFF/iFIFOMem[61][0] ,
\UART_TXFF/iFIFOMem[61][1] , \UART_TXFF/iFIFOMem[61][2] ,
\UART_TXFF/iFIFOMem[61][3] , \UART_TXFF/iFIFOMem[61][4] ,
\UART_TXFF/iFIFOMem[61][5] , \UART_TXFF/iFIFOMem[61][6] ,
\UART_TXFF/iFIFOMem[61][7] , \UART_TXFF/iFIFOMem[62][0] ,
\UART_TXFF/iFIFOMem[62][1] , \UART_TXFF/iFIFOMem[62][2] ,
\UART_TXFF/iFIFOMem[62][3] , \UART_TXFF/iFIFOMem[62][4] ,
\UART_TXFF/iFIFOMem[62][5] , \UART_TXFF/iFIFOMem[62][6] ,
\UART_TXFF/iFIFOMem[62][7] , \UART_TXFF/iFIFOMem[63][0] ,
\UART_TXFF/iFIFOMem[63][1] , \UART_TXFF/iFIFOMem[63][2] ,
\UART_TXFF/iFIFOMem[63][3] , \UART_TXFF/iFIFOMem[63][4] ,
\UART_TXFF/iFIFOMem[63][5] , \UART_TXFF/iFIFOMem[63][6] ,
\UART_TXFF/iFIFOMem[63][7] , \UART_TXFF/N56 , \UART_TXFF/N38 ,
\UART_TXFF/N37 , \UART_TXFF/N36 , \UART_TXFF/N35 , \UART_TXFF/N34 ,
\UART_TXFF/N33 , \UART_TXFF/N30 , \UART_TXFF/N29 , \UART_TXFF/N28 ,
\UART_TXFF/N27 , \UART_TXFF/N26 , \UART_TXFF/N25 ,
\UART_TXFF/iWRAddr[0] , \UART_TXFF/iWRAddr[1] ,
\UART_TXFF/iWRAddr[2] , \UART_TXFF/iWRAddr[3] ,
\UART_TXFF/iWRAddr[4] , \UART_TXFF/iWRAddr[5] ,
\UART_TXFF/iWRAddr[6] , \UART_TXFF/iRDAddr[6] , \UART_TXFF/USAGE[0] ,
\UART_TXFF/USAGE[1] , \UART_TXFF/USAGE[2] , \UART_TXFF/USAGE[3] ,
\UART_TXFF/N17 , \UART_TXFF/N16 , \UART_TXFF/N15 , \UART_TXFF/N14 ,
\UART_TXFF/N13 , \UART_TXFF/N12 , \UART_RXFF/n451 , \UART_RXFF/n450 ,
\UART_RXFF/n449 , \UART_RXFF/n448 , \UART_RXFF/n447 ,
\UART_RXFF/n446 , \UART_RXFF/n445 , \UART_RXFF/n444 ,
\UART_RXFF/n443 , \UART_RXFF/n442 , \UART_RXFF/n441 ,
\UART_RXFF/n440 , \UART_RXFF/n439 , \UART_RXFF/n438 ,
\UART_RXFF/n437 , \UART_RXFF/n436 , \UART_RXFF/n435 ,
\UART_RXFF/n434 , \UART_RXFF/n433 , \UART_RXFF/n432 ,
\UART_RXFF/n431 , \UART_RXFF/n430 , \UART_RXFF/n429 ,
\UART_RXFF/n428 , \UART_RXFF/n427 , \UART_RXFF/n426 ,
\UART_RXFF/n425 , \UART_RXFF/n424 , \UART_RXFF/n423 ,
\UART_RXFF/n422 , \UART_RXFF/n421 , \UART_RXFF/n420 ,
\UART_RXFF/n419 , \UART_RXFF/n418 , \UART_RXFF/n417 ,
\UART_RXFF/n416 , \UART_RXFF/n415 , \UART_RXFF/n414 ,
\UART_RXFF/n413 , \UART_RXFF/n412 , \UART_RXFF/n411 ,
\UART_RXFF/n410 , \UART_RXFF/n409 , \UART_RXFF/n408 ,
\UART_RXFF/n407 , \UART_RXFF/n406 , \UART_RXFF/n405 ,
\UART_RXFF/n404 , \UART_RXFF/n403 , \UART_RXFF/n402 ,
\UART_RXFF/n401 , \UART_RXFF/n400 , \UART_RXFF/n399 ,
\UART_RXFF/n398 , \UART_RXFF/n397 , \UART_RXFF/n396 ,
\UART_RXFF/n395 , \UART_RXFF/n394 , \UART_RXFF/n393 ,
\UART_RXFF/n392 , \UART_RXFF/n391 , \UART_RXFF/n390 ,
\UART_RXFF/n389 , \UART_RXFF/n388 , \UART_RXFF/n387 ,
\UART_RXFF/n386 , \UART_RXFF/n385 , \UART_RXFF/n384 ,
\UART_RXFF/n383 , \UART_RXFF/n382 , \UART_RXFF/n381 ,
\UART_RXFF/n380 , \UART_RXFF/n379 , \UART_RXFF/n378 ,
\UART_RXFF/n377 , \UART_RXFF/n376 , \UART_RXFF/n375 ,
\UART_RXFF/n374 , \UART_RXFF/n373 , \UART_RXFF/n372 ,
\UART_RXFF/n371 , \UART_RXFF/n370 , \UART_RXFF/n369 ,
\UART_RXFF/n368 , \UART_RXFF/n367 , \UART_RXFF/n366 ,
\UART_RXFF/n365 , \UART_RXFF/n364 , \UART_RXFF/n363 ,
\UART_RXFF/n362 , \UART_RXFF/n361 , \UART_RXFF/n360 ,
\UART_RXFF/n359 , \UART_RXFF/n358 , \UART_RXFF/n357 ,
\UART_RXFF/n356 , \UART_RXFF/n355 , \UART_RXFF/n354 ,
\UART_RXFF/n353 , \UART_RXFF/n352 , \UART_RXFF/n351 ,
\UART_RXFF/n350 , \UART_RXFF/n349 , \UART_RXFF/n348 ,
\UART_RXFF/n347 , \UART_RXFF/n346 , \UART_RXFF/n345 ,
\UART_RXFF/n344 , \UART_RXFF/n343 , \UART_RXFF/n342 ,
\UART_RXFF/n341 , \UART_RXFF/n340 , \UART_RXFF/n339 ,
\UART_RXFF/n338 , \UART_RXFF/n337 , \UART_RXFF/n336 ,
\UART_RXFF/n335 , \UART_RXFF/n334 , \UART_RXFF/n333 ,
\UART_RXFF/n332 , \UART_RXFF/n331 , \UART_RXFF/n330 ,
\UART_RXFF/n329 , \UART_RXFF/n328 , \UART_RXFF/n327 ,
\UART_RXFF/n326 , \UART_RXFF/n325 , \UART_RXFF/n324 ,
\UART_RXFF/n323 , \UART_RXFF/n322 , \UART_RXFF/n321 ,
\UART_RXFF/n320 , \UART_RXFF/n318 , \UART_RXFF/n317 ,
\UART_RXFF/n316 , \UART_RXFF/n315 , \UART_RXFF/n314 ,
\UART_RXFF/n313 , \UART_RXFF/n312 , \UART_RXFF/n311 ,
\UART_RXFF/n310 , \UART_RXFF/n309 , \UART_RXFF/n308 ,
\UART_RXFF/n307 , \UART_RXFF/n306 , \UART_RXFF/n305 ,
\UART_RXFF/n304 , \UART_RXFF/n303 , \UART_RXFF/n302 ,
\UART_RXFF/n301 , \UART_RXFF/n300 , \UART_RXFF/n299 ,
\UART_RXFF/n298 , \UART_RXFF/n297 , \UART_RXFF/n296 ,
\UART_RXFF/n295 , \UART_RXFF/n294 , \UART_RXFF/n293 ,
\UART_RXFF/n292 , \UART_RXFF/n291 , \UART_RXFF/n290 ,
\UART_RXFF/n289 , \UART_RXFF/n288 , \UART_RXFF/n287 ,
\UART_RXFF/n286 , \UART_RXFF/n285 , \UART_RXFF/n284 ,
\UART_RXFF/n283 , \UART_RXFF/n282 , \UART_RXFF/n281 ,
\UART_RXFF/n280 , \UART_RXFF/n279 , \UART_RXFF/n278 ,
\UART_RXFF/n277 , \UART_RXFF/n276 , \UART_RXFF/n275 ,
\UART_RXFF/n274 , \UART_RXFF/n273 , \UART_RXFF/n272 ,
\UART_RXFF/n271 , \UART_RXFF/n270 , \UART_RXFF/n269 ,
\UART_RXFF/n268 , \UART_RXFF/n267 , \UART_RXFF/n266 ,
\UART_RXFF/n265 , \UART_RXFF/n264 , \UART_RXFF/n263 ,
\UART_RXFF/n262 , \UART_RXFF/n261 , \UART_RXFF/n260 ,
\UART_RXFF/n259 , \UART_RXFF/n258 , \UART_RXFF/n257 ,
\UART_RXFF/n256 , \UART_RXFF/n255 , \UART_RXFF/n254 ,
\UART_RXFF/n253 , \UART_RXFF/n252 , \UART_RXFF/n251 ,
\UART_RXFF/n250 , \UART_RXFF/n249 , \UART_RXFF/n248 ,
\UART_RXFF/n247 , \UART_RXFF/n246 , \UART_RXFF/n245 ,
\UART_RXFF/n244 , \UART_RXFF/n243 , \UART_RXFF/n242 ,
\UART_RXFF/n241 , \UART_RXFF/n240 , \UART_RXFF/n239 ,
\UART_RXFF/n238 , \UART_RXFF/n237 , \UART_RXFF/n236 ,
\UART_RXFF/n235 , \UART_RXFF/n234 , \UART_RXFF/n233 ,
\UART_RXFF/n232 , \UART_RXFF/n231 , \UART_RXFF/n230 ,
\UART_RXFF/n229 , \UART_RXFF/n228 , \UART_RXFF/n227 ,
\UART_RXFF/n226 , \UART_RXFF/n225 , \UART_RXFF/n224 ,
\UART_RXFF/n223 , \UART_RXFF/n222 , \UART_RXFF/n221 ,
\UART_RXFF/n220 , \UART_RXFF/n219 , \UART_RXFF/n218 ,
\UART_RXFF/n217 , \UART_RXFF/n216 , \UART_RXFF/n215 ,
\UART_RXFF/n214 , \UART_RXFF/n213 , \UART_RXFF/n212 ,
\UART_RXFF/n211 , \UART_RXFF/n210 , \UART_RXFF/n209 ,
\UART_RXFF/n208 , \UART_RXFF/n207 , \UART_RXFF/n206 ,
\UART_RXFF/n205 , \UART_RXFF/n204 , \UART_RXFF/n203 ,
\UART_RXFF/n202 , \UART_RXFF/n201 , \UART_RXFF/n200 ,
\UART_RXFF/n199 , \UART_RXFF/n198 , \UART_RXFF/n197 ,
\UART_RXFF/n196 , \UART_RXFF/n195 , \UART_RXFF/n194 ,
\UART_RXFF/n193 , \UART_RXFF/n192 , \UART_RXFF/n191 ,
\UART_RXFF/n190 , \UART_RXFF/n189 , \UART_RXFF/n188 ,
\UART_RXFF/n187 , \UART_RXFF/n186 , \UART_RXFF/n185 ,
\UART_RXFF/n184 , \UART_RXFF/n183 , \UART_RXFF/n182 ,
\UART_RXFF/n181 , \UART_RXFF/n180 , \UART_RXFF/n179 ,
\UART_RXFF/n178 , \UART_RXFF/n177 , \UART_RXFF/n176 ,
\UART_RXFF/n175 , \UART_RXFF/n174 , \UART_RXFF/n173 ,
\UART_RXFF/n172 , \UART_RXFF/n171 , \UART_RXFF/n170 ,
\UART_RXFF/n169 , \UART_RXFF/n168 , \UART_RXFF/n167 ,
\UART_RXFF/n166 , \UART_RXFF/n165 , \UART_RXFF/n164 ,
\UART_RXFF/n163 , \UART_RXFF/n162 , \UART_RXFF/n161 ,
\UART_RXFF/n160 , \UART_RXFF/n159 , \UART_RXFF/n158 ,
\UART_RXFF/n157 , \UART_RXFF/n156 , \UART_RXFF/n155 ,
\UART_RXFF/n154 , \UART_RXFF/n153 , \UART_RXFF/n152 ,
\UART_RXFF/n151 , \UART_RXFF/n150 , \UART_RXFF/n149 ,
\UART_RXFF/n148 , \UART_RXFF/n147 , \UART_RXFF/n146 ,
\UART_RXFF/n145 , \UART_RXFF/n144 , \UART_RXFF/n143 ,
\UART_RXFF/n142 , \UART_RXFF/n141 , \UART_RXFF/n140 ,
\UART_RXFF/n139 , \UART_RXFF/n138 , \UART_RXFF/n137 ,
\UART_RXFF/n136 , \UART_RXFF/n135 , \UART_RXFF/n134 ,
\UART_RXFF/n133 , \UART_RXFF/n132 , \UART_RXFF/n131 ,
\UART_RXFF/n130 , \UART_RXFF/n129 , \UART_RXFF/n128 ,
\UART_RXFF/n127 , \UART_RXFF/n126 , \UART_RXFF/n125 ,
\UART_RXFF/n124 , \UART_RXFF/n123 , \UART_RXFF/n122 ,
\UART_RXFF/n121 , \UART_RXFF/n120 , \UART_RXFF/n119 ,
\UART_RXFF/n118 , \UART_RXFF/n117 , \UART_RXFF/n116 ,
\UART_RXFF/n115 , \UART_RXFF/n114 , \UART_RXFF/n113 ,
\UART_RXFF/n112 , \UART_RXFF/n111 , \UART_RXFF/n110 ,
\UART_RXFF/n109 , \UART_RXFF/n108 , \UART_RXFF/n107 ,
\UART_RXFF/n106 , \UART_RXFF/n105 , \UART_RXFF/n104 ,
\UART_RXFF/n103 , \UART_RXFF/n102 , \UART_RXFF/n101 ,
\UART_RXFF/n100 , \UART_RXFF/n99 , \UART_RXFF/n98 , \UART_RXFF/n97 ,
\UART_RXFF/n96 , \UART_RXFF/n95 , \UART_RXFF/n94 , \UART_RXFF/n93 ,
\UART_RXFF/n92 , \UART_RXFF/n91 , \UART_RXFF/n90 , \UART_RXFF/n89 ,
\UART_RXFF/n88 , \UART_RXFF/n87 , \UART_RXFF/n86 , \UART_RXFF/n85 ,
\UART_RXFF/n84 , \UART_RXFF/n83 , \UART_RXFF/n82 , \UART_RXFF/n81 ,
\UART_RXFF/n80 , \UART_RXFF/n79 , \UART_RXFF/n78 , \UART_RXFF/n77 ,
\UART_RXFF/n76 , \UART_RXFF/n75 , \UART_RXFF/n74 , \UART_RXFF/n73 ,
\UART_RXFF/n72 , \UART_RXFF/n71 , \UART_RXFF/n70 , \UART_RXFF/n69 ,
\UART_RXFF/n68 , \UART_RXFF/n67 , \UART_RXFF/n66 , \UART_RXFF/n65 ,
\UART_RXFF/n64 , \UART_RXFF/n63 , \UART_RXFF/n62 , \UART_RXFF/n61 ,
\UART_RXFF/n60 , \UART_RXFF/n59 , \UART_RXFF/n58 , \UART_RXFF/n57 ,
\UART_RXFF/n56 , \UART_RXFF/n55 , \UART_RXFF/n54 , \UART_RXFF/n53 ,
\UART_RXFF/n52 , \UART_RXFF/n51 , \UART_RXFF/n50 , \UART_RXFF/n49 ,
\UART_RXFF/n48 , \UART_RXFF/n47 , \UART_RXFF/n46 , \UART_RXFF/n44 ,
\UART_RXFF/n43 , \UART_RXFF/n42 , \UART_RXFF/n40 , \UART_RXFF/n39 ,
\UART_RXFF/n38 , \UART_RXFF/n37 , \UART_RXFF/n36 , \UART_RXFF/n35 ,
\UART_RXFF/n34 , \UART_RXFF/n33 , \UART_RXFF/n32 , \UART_RXFF/n31 ,
\UART_RXFF/n30 , \UART_RXFF/n29 , \UART_RXFF/n28 , \UART_RXFF/n27 ,
\UART_RXFF/n26 , \UART_RXFF/n25 , \UART_RXFF/n24 , \UART_RXFF/n23 ,
\UART_RXFF/n22 , \UART_RXFF/n21 , \UART_RXFF/n20 , \UART_RXFF/n19 ,
\UART_RXFF/n18 , \UART_RXFF/n17 , \UART_RXFF/n16 , \UART_RXFF/n15 ,
\UART_RXFF/n14 , \UART_RXFF/n13 , \UART_RXFF/n12 , \UART_RXFF/n11 ,
\UART_RXFF/n10 , \UART_RXFF/n9 , \UART_RXFF/n8 , \UART_RXFF/n7 ,
\UART_RXFF/n6 , \UART_RXFF/n5 , \UART_RXFF/n4 , \UART_RXFF/n3 ,
\UART_RXFF/n2 , \UART_RXFF/n1 , \UART_RXFF/n2408 , \UART_RXFF/n2407 ,
\UART_RXFF/n2406 , \UART_RXFF/n2405 , \UART_RXFF/n2404 ,
\UART_RXFF/n2403 , \UART_RXFF/n2402 , \UART_RXFF/n2401 ,
\UART_RXFF/n2400 , \UART_RXFF/n2399 , \UART_RXFF/n2398 ,
\UART_RXFF/n2397 , \UART_RXFF/n2396 , \UART_RXFF/n2395 ,
\UART_RXFF/n2394 , \UART_RXFF/n2393 , \UART_RXFF/n2392 ,
\UART_RXFF/n2391 , \UART_RXFF/n2390 , \UART_RXFF/n2389 ,
\UART_RXFF/n2388 , \UART_RXFF/n2387 , \UART_RXFF/n2386 ,
\UART_RXFF/n2385 , \UART_RXFF/n2384 , \UART_RXFF/n2383 ,
\UART_RXFF/n2382 , \UART_RXFF/n2381 , \UART_RXFF/n2380 ,
\UART_RXFF/n2379 , \UART_RXFF/n2378 , \UART_RXFF/n2377 ,
\UART_RXFF/n2376 , \UART_RXFF/n2375 , \UART_RXFF/n2374 ,
\UART_RXFF/n2373 , \UART_RXFF/n2372 , \UART_RXFF/n2371 ,
\UART_RXFF/n2370 , \UART_RXFF/n2369 , \UART_RXFF/n2368 ,
\UART_RXFF/n2367 , \UART_RXFF/n2366 , \UART_RXFF/n2365 ,
\UART_RXFF/n2364 , \UART_RXFF/n2363 , \UART_RXFF/n2362 ,
\UART_RXFF/n2361 , \UART_RXFF/n2360 , \UART_RXFF/n2359 ,
\UART_RXFF/n2358 , \UART_RXFF/n2357 , \UART_RXFF/n2356 ,
\UART_RXFF/n2355 , \UART_RXFF/n2354 , \UART_RXFF/n2353 ,
\UART_RXFF/n2352 , \UART_RXFF/n2351 , \UART_RXFF/n2350 ,
\UART_RXFF/n2349 , \UART_RXFF/n2348 , \UART_RXFF/n2347 ,
\UART_RXFF/n2346 , \UART_RXFF/n2345 , \UART_RXFF/n2344 ,
\UART_RXFF/n2343 , \UART_RXFF/n2342 , \UART_RXFF/n2341 ,
\UART_RXFF/n2340 , \UART_RXFF/n2339 , \UART_RXFF/n2338 ,
\UART_RXFF/n2337 , \UART_RXFF/n2336 , \UART_RXFF/n2335 ,
\UART_RXFF/n2334 , \UART_RXFF/n2333 , \UART_RXFF/n2332 ,
\UART_RXFF/n2331 , \UART_RXFF/n2330 , \UART_RXFF/n2329 ,
\UART_RXFF/n2328 , \UART_RXFF/n2327 , \UART_RXFF/n2326 ,
\UART_RXFF/n2325 , \UART_RXFF/n2324 , \UART_RXFF/n2323 ,
\UART_RXFF/n2322 , \UART_RXFF/n2321 , \UART_RXFF/n2320 ,
\UART_RXFF/n2319 , \UART_RXFF/n2318 , \UART_RXFF/n2317 ,
\UART_RXFF/n2316 , \UART_RXFF/n2315 , \UART_RXFF/n2314 ,
\UART_RXFF/n2313 , \UART_RXFF/n2312 , \UART_RXFF/n2311 ,
\UART_RXFF/n2310 , \UART_RXFF/n2309 , \UART_RXFF/n2308 ,
\UART_RXFF/n2307 , \UART_RXFF/n2306 , \UART_RXFF/n2305 ,
\UART_RXFF/n2304 , \UART_RXFF/n2303 , \UART_RXFF/n2302 ,
\UART_RXFF/n2301 , \UART_RXFF/n2300 , \UART_RXFF/n2299 ,
\UART_RXFF/n2298 , \UART_RXFF/n2297 , \UART_RXFF/n2296 ,
\UART_RXFF/n2295 , \UART_RXFF/n2294 , \UART_RXFF/n2293 ,
\UART_RXFF/n2292 , \UART_RXFF/n2291 , \UART_RXFF/n2290 ,
\UART_RXFF/n2289 , \UART_RXFF/n2288 , \UART_RXFF/n2287 ,
\UART_RXFF/n2286 , \UART_RXFF/n2285 , \UART_RXFF/n2284 ,
\UART_RXFF/n2283 , \UART_RXFF/n2282 , \UART_RXFF/n2281 ,
\UART_RXFF/n2280 , \UART_RXFF/n2279 , \UART_RXFF/n2278 ,
\UART_RXFF/n2277 , \UART_RXFF/n2276 , \UART_RXFF/n2275 ,
\UART_RXFF/n2274 , \UART_RXFF/n2273 , \UART_RXFF/n2272 ,
\UART_RXFF/n2271 , \UART_RXFF/n2270 , \UART_RXFF/n2269 ,
\UART_RXFF/n2268 , \UART_RXFF/n2267 , \UART_RXFF/n2266 ,
\UART_RXFF/n2265 , \UART_RXFF/n2264 , \UART_RXFF/n2263 ,
\UART_RXFF/n2262 , \UART_RXFF/n2261 , \UART_RXFF/n2260 ,
\UART_RXFF/n2259 , \UART_RXFF/n2258 , \UART_RXFF/n2257 ,
\UART_RXFF/n2256 , \UART_RXFF/n2255 , \UART_RXFF/n2254 ,
\UART_RXFF/n2253 , \UART_RXFF/n2252 , \UART_RXFF/n2251 ,
\UART_RXFF/n2250 , \UART_RXFF/n2249 , \UART_RXFF/n2248 ,
\UART_RXFF/n2247 , \UART_RXFF/n2246 , \UART_RXFF/n2245 ,
\UART_RXFF/n2244 , \UART_RXFF/n2243 , \UART_RXFF/n2242 ,
\UART_RXFF/n2241 , \UART_RXFF/n2240 , \UART_RXFF/n2239 ,
\UART_RXFF/n2238 , \UART_RXFF/n2237 , \UART_RXFF/n2236 ,
\UART_RXFF/n2235 , \UART_RXFF/n2234 , \UART_RXFF/n2233 ,
\UART_RXFF/n2232 , \UART_RXFF/n2231 , \UART_RXFF/n2230 ,
\UART_RXFF/n2229 , \UART_RXFF/n2228 , \UART_RXFF/n2227 ,
\UART_RXFF/n2226 , \UART_RXFF/n2225 , \UART_RXFF/n2224 ,
\UART_RXFF/n2223 , \UART_RXFF/n2222 , \UART_RXFF/n2221 ,
\UART_RXFF/n2220 , \UART_RXFF/n2219 , \UART_RXFF/n2218 ,
\UART_RXFF/n2217 , \UART_RXFF/n2216 , \UART_RXFF/n2215 ,
\UART_RXFF/n2214 , \UART_RXFF/n2213 , \UART_RXFF/n2212 ,
\UART_RXFF/n2211 , \UART_RXFF/n2210 , \UART_RXFF/n2209 ,
\UART_RXFF/n2208 , \UART_RXFF/n2207 , \UART_RXFF/n2206 ,
\UART_RXFF/n2205 , \UART_RXFF/n2204 , \UART_RXFF/n2203 ,
\UART_RXFF/n2202 , \UART_RXFF/n2201 , \UART_RXFF/n2200 ,
\UART_RXFF/n2199 , \UART_RXFF/n2198 , \UART_RXFF/n2197 ,
\UART_RXFF/n2196 , \UART_RXFF/n2195 , \UART_RXFF/n2194 ,
\UART_RXFF/n2193 , \UART_RXFF/n2192 , \UART_RXFF/n2191 ,
\UART_RXFF/n2190 , \UART_RXFF/n2189 , \UART_RXFF/n2188 ,
\UART_RXFF/n2187 , \UART_RXFF/n2186 , \UART_RXFF/n2185 ,
\UART_RXFF/n2184 , \UART_RXFF/n2183 , \UART_RXFF/n2182 ,
\UART_RXFF/n2181 , \UART_RXFF/n2180 , \UART_RXFF/n2179 ,
\UART_RXFF/n2178 , \UART_RXFF/n2177 , \UART_RXFF/n2176 ,
\UART_RXFF/n2175 , \UART_RXFF/n2174 , \UART_RXFF/n2173 ,
\UART_RXFF/n2172 , \UART_RXFF/n2171 , \UART_RXFF/n2170 ,
\UART_RXFF/n2169 , \UART_RXFF/n2168 , \UART_RXFF/n2167 ,
\UART_RXFF/n2166 , \UART_RXFF/n2165 , \UART_RXFF/n2164 ,
\UART_RXFF/n2163 , \UART_RXFF/n2162 , \UART_RXFF/n2161 ,
\UART_RXFF/n2160 , \UART_RXFF/n2159 , \UART_RXFF/n2158 ,
\UART_RXFF/n2157 , \UART_RXFF/n2156 , \UART_RXFF/n2155 ,
\UART_RXFF/n2154 , \UART_RXFF/n2153 , \UART_RXFF/n2152 ,
\UART_RXFF/n2151 , \UART_RXFF/n2150 , \UART_RXFF/n2149 ,
\UART_RXFF/n2148 , \UART_RXFF/n2147 , \UART_RXFF/n2146 ,
\UART_RXFF/n2145 , \UART_RXFF/n2144 , \UART_RXFF/n2143 ,
\UART_RXFF/n2142 , \UART_RXFF/n2141 , \UART_RXFF/n2140 ,
\UART_RXFF/n2139 , \UART_RXFF/n2138 , \UART_RXFF/n2137 ,
\UART_RXFF/n2136 , \UART_RXFF/n2135 , \UART_RXFF/n2134 ,
\UART_RXFF/n2133 , \UART_RXFF/n2132 , \UART_RXFF/n2131 ,
\UART_RXFF/n2130 , \UART_RXFF/n2129 , \UART_RXFF/n2128 ,
\UART_RXFF/n2127 , \UART_RXFF/n2126 , \UART_RXFF/n2125 ,
\UART_RXFF/n2124 , \UART_RXFF/n2123 , \UART_RXFF/n2122 ,
\UART_RXFF/n2121 , \UART_RXFF/n2120 , \UART_RXFF/n2119 ,
\UART_RXFF/n2118 , \UART_RXFF/n2117 , \UART_RXFF/n2116 ,
\UART_RXFF/n2115 , \UART_RXFF/n2114 , \UART_RXFF/n2113 ,
\UART_RXFF/n2112 , \UART_RXFF/n2111 , \UART_RXFF/n2110 ,
\UART_RXFF/n2109 , \UART_RXFF/n2108 , \UART_RXFF/n2107 ,
\UART_RXFF/n2106 , \UART_RXFF/n2105 , \UART_RXFF/n2104 ,
\UART_RXFF/n2103 , \UART_RXFF/n2102 , \UART_RXFF/n2101 ,
\UART_RXFF/n2100 , \UART_RXFF/n2099 , \UART_RXFF/n2098 ,
\UART_RXFF/n2097 , \UART_RXFF/n2096 , \UART_RXFF/n2095 ,
\UART_RXFF/n2094 , \UART_RXFF/n2093 , \UART_RXFF/n2092 ,
\UART_RXFF/n2091 , \UART_RXFF/n2090 , \UART_RXFF/n2089 ,
\UART_RXFF/n2088 , \UART_RXFF/n2087 , \UART_RXFF/n2086 ,
\UART_RXFF/n2085 , \UART_RXFF/n2084 , \UART_RXFF/n2083 ,
\UART_RXFF/n2082 , \UART_RXFF/n2081 , \UART_RXFF/n2080 ,
\UART_RXFF/n2079 , \UART_RXFF/n2078 , \UART_RXFF/n2077 ,
\UART_RXFF/n2076 , \UART_RXFF/n2075 , \UART_RXFF/n2074 ,
\UART_RXFF/n2073 , \UART_RXFF/n2072 , \UART_RXFF/n2071 ,
\UART_RXFF/n2070 , \UART_RXFF/n2069 , \UART_RXFF/n2068 ,
\UART_RXFF/n2067 , \UART_RXFF/n2066 , \UART_RXFF/n2065 ,
\UART_RXFF/n2064 , \UART_RXFF/n2063 , \UART_RXFF/n2062 ,
\UART_RXFF/n2061 , \UART_RXFF/n2060 , \UART_RXFF/n2059 ,
\UART_RXFF/n2058 , \UART_RXFF/n2057 , \UART_RXFF/n2056 ,
\UART_RXFF/n2055 , \UART_RXFF/n2054 , \UART_RXFF/n2053 ,
\UART_RXFF/n2052 , \UART_RXFF/n2051 , \UART_RXFF/n2050 ,
\UART_RXFF/n2049 , \UART_RXFF/n2048 , \UART_RXFF/n2047 ,
\UART_RXFF/n2046 , \UART_RXFF/n2045 , \UART_RXFF/n2044 ,
\UART_RXFF/n2043 , \UART_RXFF/n2042 , \UART_RXFF/n2041 ,
\UART_RXFF/n2040 , \UART_RXFF/n2039 , \UART_RXFF/n2038 ,
\UART_RXFF/n2037 , \UART_RXFF/n2036 , \UART_RXFF/n2035 ,
\UART_RXFF/n2034 , \UART_RXFF/n2033 , \UART_RXFF/n2032 ,
\UART_RXFF/n2031 , \UART_RXFF/n2030 , \UART_RXFF/n2029 ,
\UART_RXFF/n2028 , \UART_RXFF/n2027 , \UART_RXFF/n2026 ,
\UART_RXFF/n2025 , \UART_RXFF/n2024 , \UART_RXFF/n2023 ,
\UART_RXFF/n2022 , \UART_RXFF/n2021 , \UART_RXFF/n2020 ,
\UART_RXFF/n2019 , \UART_RXFF/n2018 , \UART_RXFF/n2017 ,
\UART_RXFF/n2016 , \UART_RXFF/n2015 , \UART_RXFF/n2014 ,
\UART_RXFF/n2013 , \UART_RXFF/n2012 , \UART_RXFF/n2011 ,
\UART_RXFF/n2010 , \UART_RXFF/n2009 , \UART_RXFF/n2008 ,
\UART_RXFF/n2007 , \UART_RXFF/n2006 , \UART_RXFF/n2005 ,
\UART_RXFF/n2004 , \UART_RXFF/n2003 , \UART_RXFF/n2002 ,
\UART_RXFF/n2001 , \UART_RXFF/n2000 , \UART_RXFF/n1999 ,
\UART_RXFF/n1998 , \UART_RXFF/n1997 , \UART_RXFF/n1996 ,
\UART_RXFF/n1995 , \UART_RXFF/n1994 , \UART_RXFF/n1993 ,
\UART_RXFF/n1992 , \UART_RXFF/n1991 , \UART_RXFF/n1990 ,
\UART_RXFF/n1989 , \UART_RXFF/n1988 , \UART_RXFF/n1987 ,
\UART_RXFF/n1986 , \UART_RXFF/n1985 , \UART_RXFF/n1984 ,
\UART_RXFF/n1983 , \UART_RXFF/n1982 , \UART_RXFF/n1981 ,
\UART_RXFF/n1980 , \UART_RXFF/n1979 , \UART_RXFF/n1978 ,
\UART_RXFF/n1977 , \UART_RXFF/n1976 , \UART_RXFF/n1975 ,
\UART_RXFF/n1974 , \UART_RXFF/n1973 , \UART_RXFF/n1972 ,
\UART_RXFF/n1971 , \UART_RXFF/n1970 , \UART_RXFF/n1969 ,
\UART_RXFF/n1968 , \UART_RXFF/n1967 , \UART_RXFF/n1966 ,
\UART_RXFF/n1965 , \UART_RXFF/n1964 , \UART_RXFF/n1963 ,
\UART_RXFF/n1962 , \UART_RXFF/n1961 , \UART_RXFF/n1960 ,
\UART_RXFF/n1959 , \UART_RXFF/n1958 , \UART_RXFF/n1957 ,
\UART_RXFF/n1956 , \UART_RXFF/n1955 , \UART_RXFF/n1954 ,
\UART_RXFF/n1953 , \UART_RXFF/n1952 , \UART_RXFF/n1951 ,
\UART_RXFF/n1950 , \UART_RXFF/n1949 , \UART_RXFF/n1948 ,
\UART_RXFF/n1947 , \UART_RXFF/n1946 , \UART_RXFF/n1945 ,
\UART_RXFF/n1944 , \UART_RXFF/n1943 , \UART_RXFF/n1942 ,
\UART_RXFF/n1941 , \UART_RXFF/n1940 , \UART_RXFF/n1939 ,
\UART_RXFF/n1938 , \UART_RXFF/n1937 , \UART_RXFF/n1936 ,
\UART_RXFF/n1935 , \UART_RXFF/n1934 , \UART_RXFF/n1933 ,
\UART_RXFF/n1932 , \UART_RXFF/n1931 , \UART_RXFF/n1930 ,
\UART_RXFF/n1929 , \UART_RXFF/n1928 , \UART_RXFF/n1927 ,
\UART_RXFF/n1926 , \UART_RXFF/n1925 , \UART_RXFF/n1924 ,
\UART_RXFF/n1923 , \UART_RXFF/n1922 , \UART_RXFF/n1921 ,
\UART_RXFF/n1920 , \UART_RXFF/n1919 , \UART_RXFF/n1918 ,
\UART_RXFF/n1917 , \UART_RXFF/n1916 , \UART_RXFF/n1915 ,
\UART_RXFF/n1914 , \UART_RXFF/n1913 , \UART_RXFF/n1912 ,
\UART_RXFF/n1911 , \UART_RXFF/n1910 , \UART_RXFF/n1909 ,
\UART_RXFF/n1908 , \UART_RXFF/n1907 , \UART_RXFF/n1906 ,
\UART_RXFF/n1905 , \UART_RXFF/n1904 , \UART_RXFF/n1903 ,
\UART_RXFF/n1902 , \UART_RXFF/n1901 , \UART_RXFF/n1900 ,
\UART_RXFF/n1899 , \UART_RXFF/n1898 , \UART_RXFF/n1897 ,
\UART_RXFF/n1896 , \UART_RXFF/n1895 , \UART_RXFF/n1894 ,
\UART_RXFF/n1893 , \UART_RXFF/n1892 , \UART_RXFF/n1891 ,
\UART_RXFF/n1890 , \UART_RXFF/n1889 , \UART_RXFF/n1888 ,
\UART_RXFF/n1887 , \UART_RXFF/n1886 , \UART_RXFF/n1885 ,
\UART_RXFF/n1884 , \UART_RXFF/n1883 , \UART_RXFF/n1882 ,
\UART_RXFF/n1881 , \UART_RXFF/n1880 , \UART_RXFF/n1879 ,
\UART_RXFF/n1878 , \UART_RXFF/n1877 , \UART_RXFF/n1876 ,
\UART_RXFF/n1875 , \UART_RXFF/n1874 , \UART_RXFF/n1873 ,
\UART_RXFF/n1872 , \UART_RXFF/n1871 , \UART_RXFF/n1870 ,
\UART_RXFF/n1869 , \UART_RXFF/n1868 , \UART_RXFF/n1867 ,
\UART_RXFF/n1866 , \UART_RXFF/n1865 , \UART_RXFF/n1864 ,
\UART_RXFF/n1863 , \UART_RXFF/n1862 , \UART_RXFF/n1861 ,
\UART_RXFF/n1860 , \UART_RXFF/n1859 , \UART_RXFF/n1858 ,
\UART_RXFF/n1857 , \UART_RXFF/n1856 , \UART_RXFF/n1855 ,
\UART_RXFF/n1854 , \UART_RXFF/n1853 , \UART_RXFF/n1852 ,
\UART_RXFF/n1851 , \UART_RXFF/n1850 , \UART_RXFF/n1849 ,
\UART_RXFF/n1848 , \UART_RXFF/n1847 , \UART_RXFF/n1846 ,
\UART_RXFF/n1845 , \UART_RXFF/n1844 , \UART_RXFF/n1843 ,
\UART_RXFF/n1842 , \UART_RXFF/n1841 , \UART_RXFF/n1840 ,
\UART_RXFF/n1839 , \UART_RXFF/n1838 , \UART_RXFF/n1837 ,
\UART_RXFF/n1836 , \UART_RXFF/n1835 , \UART_RXFF/n1834 ,
\UART_RXFF/n1833 , \UART_RXFF/n1832 , \UART_RXFF/n1831 ,
\UART_RXFF/n1830 , \UART_RXFF/n1829 , \UART_RXFF/n1828 ,
\UART_RXFF/n1827 , \UART_RXFF/n1826 , \UART_RXFF/n1825 ,
\UART_RXFF/n1824 , \UART_RXFF/n1823 , \UART_RXFF/n1822 ,
\UART_RXFF/n1821 , \UART_RXFF/n1820 , \UART_RXFF/n1819 ,
\UART_RXFF/n1818 , \UART_RXFF/n1817 , \UART_RXFF/n1816 ,
\UART_RXFF/n1815 , \UART_RXFF/n1814 , \UART_RXFF/n1813 ,
\UART_RXFF/n1812 , \UART_RXFF/n1811 , \UART_RXFF/n1810 ,
\UART_RXFF/n1809 , \UART_RXFF/n1808 , \UART_RXFF/n1807 ,
\UART_RXFF/n1806 , \UART_RXFF/n1805 , \UART_RXFF/n1804 ,
\UART_RXFF/n1803 , \UART_RXFF/n1802 , \UART_RXFF/n1801 ,
\UART_RXFF/n1800 , \UART_RXFF/n1799 , \UART_RXFF/n1798 ,
\UART_RXFF/n1797 , \UART_RXFF/n1796 , \UART_RXFF/n1795 ,
\UART_RXFF/n1794 , \UART_RXFF/n1793 , \UART_RXFF/n1792 ,
\UART_RXFF/n1791 , \UART_RXFF/n1790 , \UART_RXFF/n1789 ,
\UART_RXFF/n1788 , \UART_RXFF/n1787 , \UART_RXFF/n1786 ,
\UART_RXFF/n1785 , \UART_RXFF/n1784 , \UART_RXFF/n1783 ,
\UART_RXFF/n1782 , \UART_RXFF/n1781 , \UART_RXFF/n1780 ,
\UART_RXFF/n1779 , \UART_RXFF/n1778 , \UART_RXFF/n1777 ,
\UART_RXFF/n1776 , \UART_RXFF/n1775 , \UART_RXFF/n1774 ,
\UART_RXFF/n1773 , \UART_RXFF/n1772 , \UART_RXFF/n1771 ,
\UART_RXFF/n1770 , \UART_RXFF/n1769 , \UART_RXFF/n1768 ,
\UART_RXFF/n1767 , \UART_RXFF/n1766 , \UART_RXFF/n1765 ,
\UART_RXFF/n1764 , \UART_RXFF/n1763 , \UART_RXFF/n1762 ,
\UART_RXFF/n1761 , \UART_RXFF/n1760 , \UART_RXFF/n1759 ,
\UART_RXFF/n1758 , \UART_RXFF/n1757 , \UART_RXFF/n1756 ,
\UART_RXFF/n1755 , \UART_RXFF/n1754 , \UART_RXFF/n1753 ,
\UART_RXFF/n1752 , \UART_RXFF/n1751 , \UART_RXFF/n1750 ,
\UART_RXFF/n1749 , \UART_RXFF/n1748 , \UART_RXFF/n1747 ,
\UART_RXFF/n1746 , \UART_RXFF/n1745 , \UART_RXFF/n1744 ,
\UART_RXFF/n1743 , \UART_RXFF/n1742 , \UART_RXFF/n1741 ,
\UART_RXFF/n1740 , \UART_RXFF/n1739 , \UART_RXFF/n1738 ,
\UART_RXFF/n1737 , \UART_RXFF/n1736 , \UART_RXFF/n1735 ,
\UART_RXFF/n1734 , \UART_RXFF/n1733 , \UART_RXFF/n1732 ,
\UART_RXFF/n1731 , \UART_RXFF/n1730 , \UART_RXFF/n1729 ,
\UART_RXFF/n1728 , \UART_RXFF/n1727 , \UART_RXFF/n1726 ,
\UART_RXFF/n1725 , \UART_RXFF/n1724 , \UART_RXFF/n1723 ,
\UART_RXFF/n1722 , \UART_RXFF/n1721 , \UART_RXFF/n1720 ,
\UART_RXFF/n1719 , \UART_RXFF/n1718 , \UART_RXFF/n1717 ,
\UART_RXFF/n1716 , \UART_RXFF/n1715 , \UART_RXFF/n1714 ,
\UART_RXFF/n1713 , \UART_RXFF/n1712 , \UART_RXFF/n1711 ,
\UART_RXFF/n1710 , \UART_RXFF/n1709 , \UART_RXFF/n1708 ,
\UART_RXFF/n1707 , \UART_RXFF/n1706 , \UART_RXFF/n1705 ,
\UART_RXFF/n1704 , \UART_RXFF/n1703 , \UART_RXFF/n1702 ,
\UART_RXFF/n1701 , \UART_RXFF/n1700 , \UART_RXFF/n1699 ,
\UART_RXFF/n1698 , \UART_RXFF/n1697 , \UART_RXFF/n1696 ,
\UART_RXFF/n1695 , \UART_RXFF/n1694 , \UART_RXFF/n1693 ,
\UART_RXFF/n1692 , \UART_RXFF/n1691 , \UART_RXFF/n1690 ,
\UART_RXFF/n1689 , \UART_RXFF/n1688 , \UART_RXFF/n1687 ,
\UART_RXFF/n1686 , \UART_RXFF/n1685 , \UART_RXFF/n979 ,
\UART_RXFF/n977 , \UART_RXFF/n975 , \UART_RXFF/n973 ,
\UART_RXFF/n971 , \UART_RXFF/n969 , \UART_RXFF/n967 ,
\UART_RXFF/n965 , \UART_RXFF/n963 , \UART_RXFF/n961 ,
\UART_RXFF/n959 , \UART_RXFF/N133 , \UART_RXFF/N132 ,
\UART_RXFF/N131 , \UART_RXFF/N130 , \UART_RXFF/N129 ,
\UART_RXFF/N128 , \UART_RXFF/N127 , \UART_RXFF/N126 ,
\UART_RXFF/N125 , \UART_RXFF/N124 , \UART_RXFF/N123 ,
\UART_RXFF/iFIFOMem[0][0] , \UART_RXFF/iFIFOMem[0][1] ,
\UART_RXFF/iFIFOMem[0][2] , \UART_RXFF/iFIFOMem[0][3] ,
\UART_RXFF/iFIFOMem[0][4] , \UART_RXFF/iFIFOMem[0][5] ,
\UART_RXFF/iFIFOMem[0][6] , \UART_RXFF/iFIFOMem[0][7] ,
\UART_RXFF/iFIFOMem[0][8] , \UART_RXFF/iFIFOMem[0][9] ,
\UART_RXFF/iFIFOMem[0][10] , \UART_RXFF/iFIFOMem[1][0] ,
\UART_RXFF/iFIFOMem[1][1] , \UART_RXFF/iFIFOMem[1][2] ,
\UART_RXFF/iFIFOMem[1][3] , \UART_RXFF/iFIFOMem[1][4] ,
\UART_RXFF/iFIFOMem[1][5] , \UART_RXFF/iFIFOMem[1][6] ,
\UART_RXFF/iFIFOMem[1][7] , \UART_RXFF/iFIFOMem[1][8] ,
\UART_RXFF/iFIFOMem[1][9] , \UART_RXFF/iFIFOMem[1][10] ,
\UART_RXFF/iFIFOMem[2][0] , \UART_RXFF/iFIFOMem[2][1] ,
\UART_RXFF/iFIFOMem[2][2] , \UART_RXFF/iFIFOMem[2][3] ,
\UART_RXFF/iFIFOMem[2][4] , \UART_RXFF/iFIFOMem[2][5] ,
\UART_RXFF/iFIFOMem[2][6] , \UART_RXFF/iFIFOMem[2][7] ,
\UART_RXFF/iFIFOMem[2][8] , \UART_RXFF/iFIFOMem[2][9] ,
\UART_RXFF/iFIFOMem[2][10] , \UART_RXFF/iFIFOMem[3][0] ,
\UART_RXFF/iFIFOMem[3][1] , \UART_RXFF/iFIFOMem[3][2] ,
\UART_RXFF/iFIFOMem[3][3] , \UART_RXFF/iFIFOMem[3][4] ,
\UART_RXFF/iFIFOMem[3][5] , \UART_RXFF/iFIFOMem[3][6] ,
\UART_RXFF/iFIFOMem[3][7] , \UART_RXFF/iFIFOMem[3][8] ,
\UART_RXFF/iFIFOMem[3][9] , \UART_RXFF/iFIFOMem[3][10] ,
\UART_RXFF/iFIFOMem[4][0] , \UART_RXFF/iFIFOMem[4][1] ,
\UART_RXFF/iFIFOMem[4][2] , \UART_RXFF/iFIFOMem[4][3] ,
\UART_RXFF/iFIFOMem[4][4] , \UART_RXFF/iFIFOMem[4][5] ,
\UART_RXFF/iFIFOMem[4][6] , \UART_RXFF/iFIFOMem[4][7] ,
\UART_RXFF/iFIFOMem[4][8] , \UART_RXFF/iFIFOMem[4][9] ,
\UART_RXFF/iFIFOMem[4][10] , \UART_RXFF/iFIFOMem[5][0] ,
\UART_RXFF/iFIFOMem[5][1] , \UART_RXFF/iFIFOMem[5][2] ,
\UART_RXFF/iFIFOMem[5][3] , \UART_RXFF/iFIFOMem[5][4] ,
\UART_RXFF/iFIFOMem[5][5] , \UART_RXFF/iFIFOMem[5][6] ,
\UART_RXFF/iFIFOMem[5][7] , \UART_RXFF/iFIFOMem[5][8] ,
\UART_RXFF/iFIFOMem[5][9] , \UART_RXFF/iFIFOMem[5][10] ,
\UART_RXFF/iFIFOMem[6][0] , \UART_RXFF/iFIFOMem[6][1] ,
\UART_RXFF/iFIFOMem[6][2] , \UART_RXFF/iFIFOMem[6][3] ,
\UART_RXFF/iFIFOMem[6][4] , \UART_RXFF/iFIFOMem[6][5] ,
\UART_RXFF/iFIFOMem[6][6] , \UART_RXFF/iFIFOMem[6][7] ,
\UART_RXFF/iFIFOMem[6][8] , \UART_RXFF/iFIFOMem[6][9] ,
\UART_RXFF/iFIFOMem[6][10] , \UART_RXFF/iFIFOMem[7][0] ,
\UART_RXFF/iFIFOMem[7][1] , \UART_RXFF/iFIFOMem[7][2] ,
\UART_RXFF/iFIFOMem[7][3] , \UART_RXFF/iFIFOMem[7][4] ,
\UART_RXFF/iFIFOMem[7][5] , \UART_RXFF/iFIFOMem[7][6] ,
\UART_RXFF/iFIFOMem[7][7] , \UART_RXFF/iFIFOMem[7][8] ,
\UART_RXFF/iFIFOMem[7][9] , \UART_RXFF/iFIFOMem[7][10] ,
\UART_RXFF/iFIFOMem[8][0] , \UART_RXFF/iFIFOMem[8][1] ,
\UART_RXFF/iFIFOMem[8][2] , \UART_RXFF/iFIFOMem[8][3] ,
\UART_RXFF/iFIFOMem[8][4] , \UART_RXFF/iFIFOMem[8][5] ,
\UART_RXFF/iFIFOMem[8][6] , \UART_RXFF/iFIFOMem[8][7] ,
\UART_RXFF/iFIFOMem[8][8] , \UART_RXFF/iFIFOMem[8][9] ,
\UART_RXFF/iFIFOMem[8][10] , \UART_RXFF/iFIFOMem[9][0] ,
\UART_RXFF/iFIFOMem[9][1] , \UART_RXFF/iFIFOMem[9][2] ,
\UART_RXFF/iFIFOMem[9][3] , \UART_RXFF/iFIFOMem[9][4] ,
\UART_RXFF/iFIFOMem[9][5] , \UART_RXFF/iFIFOMem[9][6] ,
\UART_RXFF/iFIFOMem[9][7] , \UART_RXFF/iFIFOMem[9][8] ,
\UART_RXFF/iFIFOMem[9][9] , \UART_RXFF/iFIFOMem[9][10] ,
\UART_RXFF/iFIFOMem[10][0] , \UART_RXFF/iFIFOMem[10][1] ,
\UART_RXFF/iFIFOMem[10][2] , \UART_RXFF/iFIFOMem[10][3] ,
\UART_RXFF/iFIFOMem[10][4] , \UART_RXFF/iFIFOMem[10][5] ,
\UART_RXFF/iFIFOMem[10][6] , \UART_RXFF/iFIFOMem[10][7] ,
\UART_RXFF/iFIFOMem[10][8] , \UART_RXFF/iFIFOMem[10][9] ,
\UART_RXFF/iFIFOMem[10][10] , \UART_RXFF/iFIFOMem[11][0] ,
\UART_RXFF/iFIFOMem[11][1] , \UART_RXFF/iFIFOMem[11][2] ,
\UART_RXFF/iFIFOMem[11][3] , \UART_RXFF/iFIFOMem[11][4] ,
\UART_RXFF/iFIFOMem[11][5] , \UART_RXFF/iFIFOMem[11][6] ,
\UART_RXFF/iFIFOMem[11][7] , \UART_RXFF/iFIFOMem[11][8] ,
\UART_RXFF/iFIFOMem[11][9] , \UART_RXFF/iFIFOMem[11][10] ,
\UART_RXFF/iFIFOMem[12][0] , \UART_RXFF/iFIFOMem[12][1] ,
\UART_RXFF/iFIFOMem[12][2] , \UART_RXFF/iFIFOMem[12][3] ,
\UART_RXFF/iFIFOMem[12][4] , \UART_RXFF/iFIFOMem[12][5] ,
\UART_RXFF/iFIFOMem[12][6] , \UART_RXFF/iFIFOMem[12][7] ,
\UART_RXFF/iFIFOMem[12][8] , \UART_RXFF/iFIFOMem[12][9] ,
\UART_RXFF/iFIFOMem[12][10] , \UART_RXFF/iFIFOMem[13][0] ,
\UART_RXFF/iFIFOMem[13][1] , \UART_RXFF/iFIFOMem[13][2] ,
\UART_RXFF/iFIFOMem[13][3] , \UART_RXFF/iFIFOMem[13][4] ,
\UART_RXFF/iFIFOMem[13][5] , \UART_RXFF/iFIFOMem[13][6] ,
\UART_RXFF/iFIFOMem[13][7] , \UART_RXFF/iFIFOMem[13][8] ,
\UART_RXFF/iFIFOMem[13][9] , \UART_RXFF/iFIFOMem[13][10] ,
\UART_RXFF/iFIFOMem[14][0] , \UART_RXFF/iFIFOMem[14][1] ,
\UART_RXFF/iFIFOMem[14][2] , \UART_RXFF/iFIFOMem[14][3] ,
\UART_RXFF/iFIFOMem[14][4] , \UART_RXFF/iFIFOMem[14][5] ,
\UART_RXFF/iFIFOMem[14][6] , \UART_RXFF/iFIFOMem[14][7] ,
\UART_RXFF/iFIFOMem[14][8] , \UART_RXFF/iFIFOMem[14][9] ,
\UART_RXFF/iFIFOMem[14][10] , \UART_RXFF/iFIFOMem[15][0] ,
\UART_RXFF/iFIFOMem[15][1] , \UART_RXFF/iFIFOMem[15][2] ,
\UART_RXFF/iFIFOMem[15][3] , \UART_RXFF/iFIFOMem[15][4] ,
\UART_RXFF/iFIFOMem[15][5] , \UART_RXFF/iFIFOMem[15][6] ,
\UART_RXFF/iFIFOMem[15][7] , \UART_RXFF/iFIFOMem[15][8] ,
\UART_RXFF/iFIFOMem[15][9] , \UART_RXFF/iFIFOMem[15][10] ,
\UART_RXFF/iFIFOMem[16][0] , \UART_RXFF/iFIFOMem[16][1] ,
\UART_RXFF/iFIFOMem[16][2] , \UART_RXFF/iFIFOMem[16][3] ,
\UART_RXFF/iFIFOMem[16][4] , \UART_RXFF/iFIFOMem[16][5] ,
\UART_RXFF/iFIFOMem[16][6] , \UART_RXFF/iFIFOMem[16][7] ,
\UART_RXFF/iFIFOMem[16][8] , \UART_RXFF/iFIFOMem[16][9] ,
\UART_RXFF/iFIFOMem[16][10] , \UART_RXFF/iFIFOMem[17][0] ,
\UART_RXFF/iFIFOMem[17][1] , \UART_RXFF/iFIFOMem[17][2] ,
\UART_RXFF/iFIFOMem[17][3] , \UART_RXFF/iFIFOMem[17][4] ,
\UART_RXFF/iFIFOMem[17][5] , \UART_RXFF/iFIFOMem[17][6] ,
\UART_RXFF/iFIFOMem[17][7] , \UART_RXFF/iFIFOMem[17][8] ,
\UART_RXFF/iFIFOMem[17][9] , \UART_RXFF/iFIFOMem[17][10] ,
\UART_RXFF/iFIFOMem[18][0] , \UART_RXFF/iFIFOMem[18][1] ,
\UART_RXFF/iFIFOMem[18][2] , \UART_RXFF/iFIFOMem[18][3] ,
\UART_RXFF/iFIFOMem[18][4] , \UART_RXFF/iFIFOMem[18][5] ,
\UART_RXFF/iFIFOMem[18][6] , \UART_RXFF/iFIFOMem[18][7] ,
\UART_RXFF/iFIFOMem[18][8] , \UART_RXFF/iFIFOMem[18][9] ,
\UART_RXFF/iFIFOMem[18][10] , \UART_RXFF/iFIFOMem[19][0] ,
\UART_RXFF/iFIFOMem[19][1] , \UART_RXFF/iFIFOMem[19][2] ,
\UART_RXFF/iFIFOMem[19][3] , \UART_RXFF/iFIFOMem[19][4] ,
\UART_RXFF/iFIFOMem[19][5] , \UART_RXFF/iFIFOMem[19][6] ,
\UART_RXFF/iFIFOMem[19][7] , \UART_RXFF/iFIFOMem[19][8] ,
\UART_RXFF/iFIFOMem[19][9] , \UART_RXFF/iFIFOMem[19][10] ,
\UART_RXFF/iFIFOMem[20][0] , \UART_RXFF/iFIFOMem[20][1] ,
\UART_RXFF/iFIFOMem[20][2] , \UART_RXFF/iFIFOMem[20][3] ,
\UART_RXFF/iFIFOMem[20][4] , \UART_RXFF/iFIFOMem[20][5] ,
\UART_RXFF/iFIFOMem[20][6] , \UART_RXFF/iFIFOMem[20][7] ,
\UART_RXFF/iFIFOMem[20][8] , \UART_RXFF/iFIFOMem[20][9] ,
\UART_RXFF/iFIFOMem[20][10] , \UART_RXFF/iFIFOMem[21][0] ,
\UART_RXFF/iFIFOMem[21][1] , \UART_RXFF/iFIFOMem[21][2] ,
\UART_RXFF/iFIFOMem[21][3] , \UART_RXFF/iFIFOMem[21][4] ,
\UART_RXFF/iFIFOMem[21][5] , \UART_RXFF/iFIFOMem[21][6] ,
\UART_RXFF/iFIFOMem[21][7] , \UART_RXFF/iFIFOMem[21][8] ,
\UART_RXFF/iFIFOMem[21][9] , \UART_RXFF/iFIFOMem[21][10] ,
\UART_RXFF/iFIFOMem[22][0] , \UART_RXFF/iFIFOMem[22][1] ,
\UART_RXFF/iFIFOMem[22][2] , \UART_RXFF/iFIFOMem[22][3] ,
\UART_RXFF/iFIFOMem[22][4] , \UART_RXFF/iFIFOMem[22][5] ,
\UART_RXFF/iFIFOMem[22][6] , \UART_RXFF/iFIFOMem[22][7] ,
\UART_RXFF/iFIFOMem[22][8] , \UART_RXFF/iFIFOMem[22][9] ,
\UART_RXFF/iFIFOMem[22][10] , \UART_RXFF/iFIFOMem[23][0] ,
\UART_RXFF/iFIFOMem[23][1] , \UART_RXFF/iFIFOMem[23][2] ,
\UART_RXFF/iFIFOMem[23][3] , \UART_RXFF/iFIFOMem[23][4] ,
\UART_RXFF/iFIFOMem[23][5] , \UART_RXFF/iFIFOMem[23][6] ,
\UART_RXFF/iFIFOMem[23][7] , \UART_RXFF/iFIFOMem[23][8] ,
\UART_RXFF/iFIFOMem[23][9] , \UART_RXFF/iFIFOMem[23][10] ,
\UART_RXFF/iFIFOMem[24][0] , \UART_RXFF/iFIFOMem[24][1] ,
\UART_RXFF/iFIFOMem[24][2] , \UART_RXFF/iFIFOMem[24][3] ,
\UART_RXFF/iFIFOMem[24][4] , \UART_RXFF/iFIFOMem[24][5] ,
\UART_RXFF/iFIFOMem[24][6] , \UART_RXFF/iFIFOMem[24][7] ,
\UART_RXFF/iFIFOMem[24][8] , \UART_RXFF/iFIFOMem[24][9] ,
\UART_RXFF/iFIFOMem[24][10] , \UART_RXFF/iFIFOMem[25][0] ,
\UART_RXFF/iFIFOMem[25][1] , \UART_RXFF/iFIFOMem[25][2] ,
\UART_RXFF/iFIFOMem[25][3] , \UART_RXFF/iFIFOMem[25][4] ,
\UART_RXFF/iFIFOMem[25][5] , \UART_RXFF/iFIFOMem[25][6] ,
\UART_RXFF/iFIFOMem[25][7] , \UART_RXFF/iFIFOMem[25][8] ,
\UART_RXFF/iFIFOMem[25][9] , \UART_RXFF/iFIFOMem[25][10] ,
\UART_RXFF/iFIFOMem[26][0] , \UART_RXFF/iFIFOMem[26][1] ,
\UART_RXFF/iFIFOMem[26][2] , \UART_RXFF/iFIFOMem[26][3] ,
\UART_RXFF/iFIFOMem[26][4] , \UART_RXFF/iFIFOMem[26][5] ,
\UART_RXFF/iFIFOMem[26][6] , \UART_RXFF/iFIFOMem[26][7] ,
\UART_RXFF/iFIFOMem[26][8] , \UART_RXFF/iFIFOMem[26][9] ,
\UART_RXFF/iFIFOMem[26][10] , \UART_RXFF/iFIFOMem[27][0] ,
\UART_RXFF/iFIFOMem[27][1] , \UART_RXFF/iFIFOMem[27][2] ,
\UART_RXFF/iFIFOMem[27][3] , \UART_RXFF/iFIFOMem[27][4] ,
\UART_RXFF/iFIFOMem[27][5] , \UART_RXFF/iFIFOMem[27][6] ,
\UART_RXFF/iFIFOMem[27][7] , \UART_RXFF/iFIFOMem[27][8] ,
\UART_RXFF/iFIFOMem[27][9] , \UART_RXFF/iFIFOMem[27][10] ,
\UART_RXFF/iFIFOMem[28][0] , \UART_RXFF/iFIFOMem[28][1] ,
\UART_RXFF/iFIFOMem[28][2] , \UART_RXFF/iFIFOMem[28][3] ,
\UART_RXFF/iFIFOMem[28][4] , \UART_RXFF/iFIFOMem[28][5] ,
\UART_RXFF/iFIFOMem[28][6] , \UART_RXFF/iFIFOMem[28][7] ,
\UART_RXFF/iFIFOMem[28][8] , \UART_RXFF/iFIFOMem[28][9] ,
\UART_RXFF/iFIFOMem[28][10] , \UART_RXFF/iFIFOMem[29][0] ,
\UART_RXFF/iFIFOMem[29][1] , \UART_RXFF/iFIFOMem[29][2] ,
\UART_RXFF/iFIFOMem[29][3] , \UART_RXFF/iFIFOMem[29][4] ,
\UART_RXFF/iFIFOMem[29][5] , \UART_RXFF/iFIFOMem[29][6] ,
\UART_RXFF/iFIFOMem[29][7] , \UART_RXFF/iFIFOMem[29][8] ,
\UART_RXFF/iFIFOMem[29][9] , \UART_RXFF/iFIFOMem[29][10] ,
\UART_RXFF/iFIFOMem[30][0] , \UART_RXFF/iFIFOMem[30][1] ,
\UART_RXFF/iFIFOMem[30][2] , \UART_RXFF/iFIFOMem[30][3] ,
\UART_RXFF/iFIFOMem[30][4] , \UART_RXFF/iFIFOMem[30][5] ,
\UART_RXFF/iFIFOMem[30][6] , \UART_RXFF/iFIFOMem[30][7] ,
\UART_RXFF/iFIFOMem[30][8] , \UART_RXFF/iFIFOMem[30][9] ,
\UART_RXFF/iFIFOMem[30][10] , \UART_RXFF/iFIFOMem[31][0] ,
\UART_RXFF/iFIFOMem[31][1] , \UART_RXFF/iFIFOMem[31][2] ,
\UART_RXFF/iFIFOMem[31][3] , \UART_RXFF/iFIFOMem[31][4] ,
\UART_RXFF/iFIFOMem[31][5] , \UART_RXFF/iFIFOMem[31][6] ,
\UART_RXFF/iFIFOMem[31][7] , \UART_RXFF/iFIFOMem[31][8] ,
\UART_RXFF/iFIFOMem[31][9] , \UART_RXFF/iFIFOMem[31][10] ,
\UART_RXFF/iFIFOMem[32][0] , \UART_RXFF/iFIFOMem[32][1] ,
\UART_RXFF/iFIFOMem[32][2] , \UART_RXFF/iFIFOMem[32][3] ,
\UART_RXFF/iFIFOMem[32][4] , \UART_RXFF/iFIFOMem[32][5] ,
\UART_RXFF/iFIFOMem[32][6] , \UART_RXFF/iFIFOMem[32][7] ,
\UART_RXFF/iFIFOMem[32][8] , \UART_RXFF/iFIFOMem[32][9] ,
\UART_RXFF/iFIFOMem[32][10] , \UART_RXFF/iFIFOMem[33][0] ,
\UART_RXFF/iFIFOMem[33][1] , \UART_RXFF/iFIFOMem[33][2] ,
\UART_RXFF/iFIFOMem[33][3] , \UART_RXFF/iFIFOMem[33][4] ,
\UART_RXFF/iFIFOMem[33][5] , \UART_RXFF/iFIFOMem[33][6] ,
\UART_RXFF/iFIFOMem[33][7] , \UART_RXFF/iFIFOMem[33][8] ,
\UART_RXFF/iFIFOMem[33][9] , \UART_RXFF/iFIFOMem[33][10] ,
\UART_RXFF/iFIFOMem[34][0] , \UART_RXFF/iFIFOMem[34][1] ,
\UART_RXFF/iFIFOMem[34][2] , \UART_RXFF/iFIFOMem[34][3] ,
\UART_RXFF/iFIFOMem[34][4] , \UART_RXFF/iFIFOMem[34][5] ,
\UART_RXFF/iFIFOMem[34][6] , \UART_RXFF/iFIFOMem[34][7] ,
\UART_RXFF/iFIFOMem[34][8] , \UART_RXFF/iFIFOMem[34][9] ,
\UART_RXFF/iFIFOMem[34][10] , \UART_RXFF/iFIFOMem[35][0] ,
\UART_RXFF/iFIFOMem[35][1] , \UART_RXFF/iFIFOMem[35][2] ,
\UART_RXFF/iFIFOMem[35][3] , \UART_RXFF/iFIFOMem[35][4] ,
\UART_RXFF/iFIFOMem[35][5] , \UART_RXFF/iFIFOMem[35][6] ,
\UART_RXFF/iFIFOMem[35][7] , \UART_RXFF/iFIFOMem[35][8] ,
\UART_RXFF/iFIFOMem[35][9] , \UART_RXFF/iFIFOMem[35][10] ,
\UART_RXFF/iFIFOMem[36][0] , \UART_RXFF/iFIFOMem[36][1] ,
\UART_RXFF/iFIFOMem[36][2] , \UART_RXFF/iFIFOMem[36][3] ,
\UART_RXFF/iFIFOMem[36][4] , \UART_RXFF/iFIFOMem[36][5] ,
\UART_RXFF/iFIFOMem[36][6] , \UART_RXFF/iFIFOMem[36][7] ,
\UART_RXFF/iFIFOMem[36][8] , \UART_RXFF/iFIFOMem[36][9] ,
\UART_RXFF/iFIFOMem[36][10] , \UART_RXFF/iFIFOMem[37][0] ,
\UART_RXFF/iFIFOMem[37][1] , \UART_RXFF/iFIFOMem[37][2] ,
\UART_RXFF/iFIFOMem[37][3] , \UART_RXFF/iFIFOMem[37][4] ,
\UART_RXFF/iFIFOMem[37][5] , \UART_RXFF/iFIFOMem[37][6] ,
\UART_RXFF/iFIFOMem[37][7] , \UART_RXFF/iFIFOMem[37][8] ,
\UART_RXFF/iFIFOMem[37][9] , \UART_RXFF/iFIFOMem[37][10] ,
\UART_RXFF/iFIFOMem[38][0] , \UART_RXFF/iFIFOMem[38][1] ,
\UART_RXFF/iFIFOMem[38][2] , \UART_RXFF/iFIFOMem[38][3] ,
\UART_RXFF/iFIFOMem[38][4] , \UART_RXFF/iFIFOMem[38][5] ,
\UART_RXFF/iFIFOMem[38][6] , \UART_RXFF/iFIFOMem[38][7] ,
\UART_RXFF/iFIFOMem[38][8] , \UART_RXFF/iFIFOMem[38][9] ,
\UART_RXFF/iFIFOMem[38][10] , \UART_RXFF/iFIFOMem[39][0] ,
\UART_RXFF/iFIFOMem[39][1] , \UART_RXFF/iFIFOMem[39][2] ,
\UART_RXFF/iFIFOMem[39][3] , \UART_RXFF/iFIFOMem[39][4] ,
\UART_RXFF/iFIFOMem[39][5] , \UART_RXFF/iFIFOMem[39][6] ,
\UART_RXFF/iFIFOMem[39][7] , \UART_RXFF/iFIFOMem[39][8] ,
\UART_RXFF/iFIFOMem[39][9] , \UART_RXFF/iFIFOMem[39][10] ,
\UART_RXFF/iFIFOMem[40][0] , \UART_RXFF/iFIFOMem[40][1] ,
\UART_RXFF/iFIFOMem[40][2] , \UART_RXFF/iFIFOMem[40][3] ,
\UART_RXFF/iFIFOMem[40][4] , \UART_RXFF/iFIFOMem[40][5] ,
\UART_RXFF/iFIFOMem[40][6] , \UART_RXFF/iFIFOMem[40][7] ,
\UART_RXFF/iFIFOMem[40][8] , \UART_RXFF/iFIFOMem[40][9] ,
\UART_RXFF/iFIFOMem[40][10] , \UART_RXFF/iFIFOMem[41][0] ,
\UART_RXFF/iFIFOMem[41][1] , \UART_RXFF/iFIFOMem[41][2] ,
\UART_RXFF/iFIFOMem[41][3] , \UART_RXFF/iFIFOMem[41][4] ,
\UART_RXFF/iFIFOMem[41][5] , \UART_RXFF/iFIFOMem[41][6] ,
\UART_RXFF/iFIFOMem[41][7] , \UART_RXFF/iFIFOMem[41][8] ,
\UART_RXFF/iFIFOMem[41][9] , \UART_RXFF/iFIFOMem[41][10] ,
\UART_RXFF/iFIFOMem[42][0] , \UART_RXFF/iFIFOMem[42][1] ,
\UART_RXFF/iFIFOMem[42][2] , \UART_RXFF/iFIFOMem[42][3] ,
\UART_RXFF/iFIFOMem[42][4] , \UART_RXFF/iFIFOMem[42][5] ,
\UART_RXFF/iFIFOMem[42][6] , \UART_RXFF/iFIFOMem[42][7] ,
\UART_RXFF/iFIFOMem[42][8] , \UART_RXFF/iFIFOMem[42][9] ,
\UART_RXFF/iFIFOMem[42][10] , \UART_RXFF/iFIFOMem[43][0] ,
\UART_RXFF/iFIFOMem[43][1] , \UART_RXFF/iFIFOMem[43][2] ,
\UART_RXFF/iFIFOMem[43][3] , \UART_RXFF/iFIFOMem[43][4] ,
\UART_RXFF/iFIFOMem[43][5] , \UART_RXFF/iFIFOMem[43][6] ,
\UART_RXFF/iFIFOMem[43][7] , \UART_RXFF/iFIFOMem[43][8] ,
\UART_RXFF/iFIFOMem[43][9] , \UART_RXFF/iFIFOMem[43][10] ,
\UART_RXFF/iFIFOMem[44][0] , \UART_RXFF/iFIFOMem[44][1] ,
\UART_RXFF/iFIFOMem[44][2] , \UART_RXFF/iFIFOMem[44][3] ,
\UART_RXFF/iFIFOMem[44][4] , \UART_RXFF/iFIFOMem[44][5] ,
\UART_RXFF/iFIFOMem[44][6] , \UART_RXFF/iFIFOMem[44][7] ,
\UART_RXFF/iFIFOMem[44][8] , \UART_RXFF/iFIFOMem[44][9] ,
\UART_RXFF/iFIFOMem[44][10] , \UART_RXFF/iFIFOMem[45][0] ,
\UART_RXFF/iFIFOMem[45][1] , \UART_RXFF/iFIFOMem[45][2] ,
\UART_RXFF/iFIFOMem[45][3] , \UART_RXFF/iFIFOMem[45][4] ,
\UART_RXFF/iFIFOMem[45][5] , \UART_RXFF/iFIFOMem[45][6] ,
\UART_RXFF/iFIFOMem[45][7] , \UART_RXFF/iFIFOMem[45][8] ,
\UART_RXFF/iFIFOMem[45][9] , \UART_RXFF/iFIFOMem[45][10] ,
\UART_RXFF/iFIFOMem[46][0] , \UART_RXFF/iFIFOMem[46][1] ,
\UART_RXFF/iFIFOMem[46][2] , \UART_RXFF/iFIFOMem[46][3] ,
\UART_RXFF/iFIFOMem[46][4] , \UART_RXFF/iFIFOMem[46][5] ,
\UART_RXFF/iFIFOMem[46][6] , \UART_RXFF/iFIFOMem[46][7] ,
\UART_RXFF/iFIFOMem[46][8] , \UART_RXFF/iFIFOMem[46][9] ,
\UART_RXFF/iFIFOMem[46][10] , \UART_RXFF/iFIFOMem[47][0] ,
\UART_RXFF/iFIFOMem[47][1] , \UART_RXFF/iFIFOMem[47][2] ,
\UART_RXFF/iFIFOMem[47][3] , \UART_RXFF/iFIFOMem[47][4] ,
\UART_RXFF/iFIFOMem[47][5] , \UART_RXFF/iFIFOMem[47][6] ,
\UART_RXFF/iFIFOMem[47][7] , \UART_RXFF/iFIFOMem[47][8] ,
\UART_RXFF/iFIFOMem[47][9] , \UART_RXFF/iFIFOMem[47][10] ,
\UART_RXFF/iFIFOMem[48][0] , \UART_RXFF/iFIFOMem[48][1] ,
\UART_RXFF/iFIFOMem[48][2] , \UART_RXFF/iFIFOMem[48][3] ,
\UART_RXFF/iFIFOMem[48][4] , \UART_RXFF/iFIFOMem[48][5] ,
\UART_RXFF/iFIFOMem[48][6] , \UART_RXFF/iFIFOMem[48][7] ,
\UART_RXFF/iFIFOMem[48][8] , \UART_RXFF/iFIFOMem[48][9] ,
\UART_RXFF/iFIFOMem[48][10] , \UART_RXFF/iFIFOMem[49][0] ,
\UART_RXFF/iFIFOMem[49][1] , \UART_RXFF/iFIFOMem[49][2] ,
\UART_RXFF/iFIFOMem[49][3] , \UART_RXFF/iFIFOMem[49][4] ,
\UART_RXFF/iFIFOMem[49][5] , \UART_RXFF/iFIFOMem[49][6] ,
\UART_RXFF/iFIFOMem[49][7] , \UART_RXFF/iFIFOMem[49][8] ,
\UART_RXFF/iFIFOMem[49][9] , \UART_RXFF/iFIFOMem[49][10] ,
\UART_RXFF/iFIFOMem[50][0] , \UART_RXFF/iFIFOMem[50][1] ,
\UART_RXFF/iFIFOMem[50][2] , \UART_RXFF/iFIFOMem[50][3] ,
\UART_RXFF/iFIFOMem[50][4] , \UART_RXFF/iFIFOMem[50][5] ,
\UART_RXFF/iFIFOMem[50][6] , \UART_RXFF/iFIFOMem[50][7] ,
\UART_RXFF/iFIFOMem[50][8] , \UART_RXFF/iFIFOMem[50][9] ,
\UART_RXFF/iFIFOMem[50][10] , \UART_RXFF/iFIFOMem[51][0] ,
\UART_RXFF/iFIFOMem[51][1] , \UART_RXFF/iFIFOMem[51][2] ,
\UART_RXFF/iFIFOMem[51][3] , \UART_RXFF/iFIFOMem[51][4] ,
\UART_RXFF/iFIFOMem[51][5] , \UART_RXFF/iFIFOMem[51][6] ,
\UART_RXFF/iFIFOMem[51][7] , \UART_RXFF/iFIFOMem[51][8] ,
\UART_RXFF/iFIFOMem[51][9] , \UART_RXFF/iFIFOMem[51][10] ,
\UART_RXFF/iFIFOMem[52][0] , \UART_RXFF/iFIFOMem[52][1] ,
\UART_RXFF/iFIFOMem[52][2] , \UART_RXFF/iFIFOMem[52][3] ,
\UART_RXFF/iFIFOMem[52][4] , \UART_RXFF/iFIFOMem[52][5] ,
\UART_RXFF/iFIFOMem[52][6] , \UART_RXFF/iFIFOMem[52][7] ,
\UART_RXFF/iFIFOMem[52][8] , \UART_RXFF/iFIFOMem[52][9] ,
\UART_RXFF/iFIFOMem[52][10] , \UART_RXFF/iFIFOMem[53][0] ,
\UART_RXFF/iFIFOMem[53][1] , \UART_RXFF/iFIFOMem[53][2] ,
\UART_RXFF/iFIFOMem[53][3] , \UART_RXFF/iFIFOMem[53][4] ,
\UART_RXFF/iFIFOMem[53][5] , \UART_RXFF/iFIFOMem[53][6] ,
\UART_RXFF/iFIFOMem[53][7] , \UART_RXFF/iFIFOMem[53][8] ,
\UART_RXFF/iFIFOMem[53][9] , \UART_RXFF/iFIFOMem[53][10] ,
\UART_RXFF/iFIFOMem[54][0] , \UART_RXFF/iFIFOMem[54][1] ,
\UART_RXFF/iFIFOMem[54][2] , \UART_RXFF/iFIFOMem[54][3] ,
\UART_RXFF/iFIFOMem[54][4] , \UART_RXFF/iFIFOMem[54][5] ,
\UART_RXFF/iFIFOMem[54][6] , \UART_RXFF/iFIFOMem[54][7] ,
\UART_RXFF/iFIFOMem[54][8] , \UART_RXFF/iFIFOMem[54][9] ,
\UART_RXFF/iFIFOMem[54][10] , \UART_RXFF/iFIFOMem[55][0] ,
\UART_RXFF/iFIFOMem[55][1] , \UART_RXFF/iFIFOMem[55][2] ,
\UART_RXFF/iFIFOMem[55][3] , \UART_RXFF/iFIFOMem[55][4] ,
\UART_RXFF/iFIFOMem[55][5] , \UART_RXFF/iFIFOMem[55][6] ,
\UART_RXFF/iFIFOMem[55][7] , \UART_RXFF/iFIFOMem[55][8] ,
\UART_RXFF/iFIFOMem[55][9] , \UART_RXFF/iFIFOMem[55][10] ,
\UART_RXFF/iFIFOMem[56][0] , \UART_RXFF/iFIFOMem[56][1] ,
\UART_RXFF/iFIFOMem[56][2] , \UART_RXFF/iFIFOMem[56][3] ,
\UART_RXFF/iFIFOMem[56][4] , \UART_RXFF/iFIFOMem[56][5] ,
\UART_RXFF/iFIFOMem[56][6] , \UART_RXFF/iFIFOMem[56][7] ,
\UART_RXFF/iFIFOMem[56][8] , \UART_RXFF/iFIFOMem[56][9] ,
\UART_RXFF/iFIFOMem[56][10] , \UART_RXFF/iFIFOMem[57][0] ,
\UART_RXFF/iFIFOMem[57][1] , \UART_RXFF/iFIFOMem[57][2] ,
\UART_RXFF/iFIFOMem[57][3] , \UART_RXFF/iFIFOMem[57][4] ,
\UART_RXFF/iFIFOMem[57][5] , \UART_RXFF/iFIFOMem[57][6] ,
\UART_RXFF/iFIFOMem[57][7] , \UART_RXFF/iFIFOMem[57][8] ,
\UART_RXFF/iFIFOMem[57][9] , \UART_RXFF/iFIFOMem[57][10] ,
\UART_RXFF/iFIFOMem[58][0] , \UART_RXFF/iFIFOMem[58][1] ,
\UART_RXFF/iFIFOMem[58][2] , \UART_RXFF/iFIFOMem[58][3] ,
\UART_RXFF/iFIFOMem[58][4] , \UART_RXFF/iFIFOMem[58][5] ,
\UART_RXFF/iFIFOMem[58][6] , \UART_RXFF/iFIFOMem[58][7] ,
\UART_RXFF/iFIFOMem[58][8] , \UART_RXFF/iFIFOMem[58][9] ,
\UART_RXFF/iFIFOMem[58][10] , \UART_RXFF/iFIFOMem[59][0] ,
\UART_RXFF/iFIFOMem[59][1] , \UART_RXFF/iFIFOMem[59][2] ,
\UART_RXFF/iFIFOMem[59][3] , \UART_RXFF/iFIFOMem[59][4] ,
\UART_RXFF/iFIFOMem[59][5] , \UART_RXFF/iFIFOMem[59][6] ,
\UART_RXFF/iFIFOMem[59][7] , \UART_RXFF/iFIFOMem[59][8] ,
\UART_RXFF/iFIFOMem[59][9] , \UART_RXFF/iFIFOMem[59][10] ,
\UART_RXFF/iFIFOMem[60][0] , \UART_RXFF/iFIFOMem[60][1] ,
\UART_RXFF/iFIFOMem[60][2] , \UART_RXFF/iFIFOMem[60][3] ,
\UART_RXFF/iFIFOMem[60][4] , \UART_RXFF/iFIFOMem[60][5] ,
\UART_RXFF/iFIFOMem[60][6] , \UART_RXFF/iFIFOMem[60][7] ,
\UART_RXFF/iFIFOMem[60][8] , \UART_RXFF/iFIFOMem[60][9] ,
\UART_RXFF/iFIFOMem[60][10] , \UART_RXFF/iFIFOMem[61][0] ,
\UART_RXFF/iFIFOMem[61][1] , \UART_RXFF/iFIFOMem[61][2] ,
\UART_RXFF/iFIFOMem[61][3] , \UART_RXFF/iFIFOMem[61][4] ,
\UART_RXFF/iFIFOMem[61][5] , \UART_RXFF/iFIFOMem[61][6] ,
\UART_RXFF/iFIFOMem[61][7] , \UART_RXFF/iFIFOMem[61][8] ,
\UART_RXFF/iFIFOMem[61][9] , \UART_RXFF/iFIFOMem[61][10] ,
\UART_RXFF/iFIFOMem[62][0] , \UART_RXFF/iFIFOMem[62][1] ,
\UART_RXFF/iFIFOMem[62][2] , \UART_RXFF/iFIFOMem[62][3] ,
\UART_RXFF/iFIFOMem[62][4] , \UART_RXFF/iFIFOMem[62][5] ,
\UART_RXFF/iFIFOMem[62][6] , \UART_RXFF/iFIFOMem[62][7] ,
\UART_RXFF/iFIFOMem[62][8] , \UART_RXFF/iFIFOMem[62][9] ,
\UART_RXFF/iFIFOMem[62][10] , \UART_RXFF/iFIFOMem[63][0] ,
\UART_RXFF/iFIFOMem[63][1] , \UART_RXFF/iFIFOMem[63][2] ,
\UART_RXFF/iFIFOMem[63][3] , \UART_RXFF/iFIFOMem[63][4] ,
\UART_RXFF/iFIFOMem[63][5] , \UART_RXFF/iFIFOMem[63][6] ,
\UART_RXFF/iFIFOMem[63][7] , \UART_RXFF/iFIFOMem[63][8] ,
\UART_RXFF/iFIFOMem[63][9] , \UART_RXFF/iFIFOMem[63][10] ,
\UART_RXFF/N56 , \UART_RXFF/N38 , \UART_RXFF/N37 , \UART_RXFF/N36 ,
\UART_RXFF/N35 , \UART_RXFF/N34 , \UART_RXFF/N33 , \UART_RXFF/N30 ,
\UART_RXFF/N29 , \UART_RXFF/N28 , \UART_RXFF/N27 , \UART_RXFF/N26 ,
\UART_RXFF/N25 , \UART_RXFF/iWRAddr[0] , \UART_RXFF/iWRAddr[1] ,
\UART_RXFF/iWRAddr[2] , \UART_RXFF/iWRAddr[3] ,
\UART_RXFF/iWRAddr[4] , \UART_RXFF/iWRAddr[5] ,
\UART_RXFF/iWRAddr[6] , \UART_RXFF/iRDAddr[6] , \UART_RXFF/USAGE[0] ,
\UART_RXFF/N17 , \UART_RXFF/N16 , \UART_RXFF/N15 , \UART_RXFF/N14 ,
\UART_RXFF/N13 , \UART_RXFF/N12 , \UART_TX/n84 , \UART_TX/n83 ,
\UART_TX/n82 , \UART_TX/n81 , \UART_TX/n80 , \UART_TX/n79 ,
\UART_TX/n78 , \UART_TX/n77 , \UART_TX/n76 , \UART_TX/n75 ,
\UART_TX/n74 , \UART_TX/n73 , \UART_TX/n72 , \UART_TX/n71 ,
\UART_TX/n70 , \UART_TX/n69 , \UART_TX/n68 , \UART_TX/n67 ,
\UART_TX/n66 , \UART_TX/n65 , \UART_TX/n64 , \UART_TX/n63 ,
\UART_TX/n62 , \UART_TX/n61 , \UART_TX/n60 , \UART_TX/n59 ,
\UART_TX/n58 , \UART_TX/n57 , \UART_TX/n56 , \UART_TX/n54 ,
\UART_TX/n53 , \UART_TX/n52 , \UART_TX/n51 , \UART_TX/n50 ,
\UART_TX/n49 , \UART_TX/n48 , \UART_TX/n47 , \UART_TX/n46 ,
\UART_TX/n45 , \UART_TX/n44 , \UART_TX/n43 , \UART_TX/n42 ,
\UART_TX/n41 , \UART_TX/n40 , \UART_TX/n39 , \UART_TX/n38 ,
\UART_TX/n37 , \UART_TX/n36 , \UART_TX/n35 , \UART_TX/n34 ,
\UART_TX/n33 , \UART_TX/n32 , \UART_TX/n31 , \UART_TX/n30 ,
\UART_TX/n29 , \UART_TX/n28 , \UART_TX/n27 , \UART_TX/n26 ,
\UART_TX/n25 , \UART_TX/n24 , \UART_TX/n23 , \UART_TX/n22 ,
\UART_TX/n21 , \UART_TX/n20 , \UART_TX/n19 , \UART_TX/n18 ,
\UART_TX/n17 , \UART_TX/n16 , \UART_TX/n15 , \UART_TX/n14 ,
\UART_TX/n13 , \UART_TX/n12 , \UART_TX/n11 , \UART_TX/n10 ,
\UART_TX/n9 , \UART_TX/n8 , \UART_TX/n7 , \UART_TX/n6 , \UART_TX/n5 ,
\UART_TX/n4 , \UART_TX/n3 , \UART_TX/n2 , \UART_TX/n1 , \UART_TX/n93 ,
\UART_TX/n92 , \UART_TX/n90 , \UART_TX/n89 , \UART_TX/n88 ,
\UART_TX/n87 , \UART_TX/N127 , \UART_TX/iLast , \UART_TX/iTx2 ,
\UART_TX/CState[0] , \UART_TX/CState[1] , \UART_TX/CState[2] ,
\UART_TX/CState[3] , \UART_RX/n85 , \UART_RX/n84 , \UART_RX/n83 ,
\UART_RX/n82 , \UART_RX/n81 , \UART_RX/n80 , \UART_RX/n79 ,
\UART_RX/n78 , \UART_RX/n77 , \UART_RX/n76 , \UART_RX/n75 ,
\UART_RX/n74 , \UART_RX/n73 , \UART_RX/n72 , \UART_RX/n70 ,
\UART_RX/n69 , \UART_RX/n68 , \UART_RX/n67 , \UART_RX/n66 ,
\UART_RX/n65 , \UART_RX/n64 , \UART_RX/n63 , \UART_RX/n62 ,
\UART_RX/n61 , \UART_RX/n59 , \UART_RX/n58 , \UART_RX/n57 ,
\UART_RX/n56 , \UART_RX/n55 , \UART_RX/n54 , \UART_RX/n53 ,
\UART_RX/n52 , \UART_RX/n51 , \UART_RX/n50 , \UART_RX/n49 ,
\UART_RX/n48 , \UART_RX/n47 , \UART_RX/n46 , \UART_RX/n45 ,
\UART_RX/n44 , \UART_RX/n43 , \UART_RX/n42 , \UART_RX/n41 ,
\UART_RX/n40 , \UART_RX/n39 , \UART_RX/n38 , \UART_RX/n37 ,
\UART_RX/n36 , \UART_RX/n35 , \UART_RX/n34 , \UART_RX/n33 ,
\UART_RX/n32 , \UART_RX/n31 , \UART_RX/n30 , \UART_RX/n29 ,
\UART_RX/n28 , \UART_RX/n27 , \UART_RX/n26 , \UART_RX/n25 ,
\UART_RX/n24 , \UART_RX/n23 , \UART_RX/n22 , \UART_RX/n21 ,
\UART_RX/n20 , \UART_RX/n19 , \UART_RX/n18 , \UART_RX/n17 ,
\UART_RX/n16 , \UART_RX/n15 , \UART_RX/n14 , \UART_RX/n13 ,
\UART_RX/n12 , \UART_RX/n11 , \UART_RX/n10 , \UART_RX/n9 ,
\UART_RX/n8 , \UART_RX/n7 , \UART_RX/n6 , \UART_RX/n5 , \UART_RX/n4 ,
\UART_RX/n3 , \UART_RX/n2 , \UART_RX/n1 , \UART_RX/n117 ,
\UART_RX/n116 , \UART_RX/n115 , \UART_RX/n114 , \UART_RX/n113 ,
\UART_RX/n112 , \UART_RX/n111 , \UART_RX/n110 , \UART_RX/n109 ,
\UART_RX/n108 , \UART_RX/n107 , \UART_RX/n106 , \UART_RX/n105 ,
\UART_RX/N106 , \UART_RX/iParityReceived , \UART_RX/N75 ,
\UART_RX/CState[0] , \UART_RX/CState[1] , \UART_RX/CState[2] ,
\UART_RX/iDataCount[0] , \UART_RX/iDataCount[1] ,
\UART_RX/iDataCount[2] , \UART_RX/iDataCount[3] ,
\UART_RX/iBaudStepD , \UART_RX/iFStopBit , \UART_RX/iFSIN ,
\UART_RX/iFilterClear , \UART_RX/iBaudStep , \UART_RX/iBaudCount[3] ,
\UART_RX/RX_BRC/n23 , \UART_RX/RX_BRC/n22 , \UART_RX/RX_BRC/n21 ,
\UART_RX/RX_BRC/n18 , \UART_RX/RX_BRC/n17 , \UART_RX/RX_BRC/n13 ,
\UART_RX/RX_BRC/n12 , \UART_RX/RX_BRC/n9 , \UART_RX/RX_BRC/n8 ,
\UART_RX/RX_BRC/n7 , \UART_RX/RX_BRC/n6 , \UART_RX/RX_BRC/n5 ,
\UART_RX/RX_BRC/n1 , \UART_RX/RX_BRC/n30 , \UART_RX/RX_BRC/n29 ,
\UART_RX/RX_BRC/n28 , \UART_RX/RX_BRC/n27 , \UART_RX/RX_BRC/n26 ,
\UART_RX/RX_BRC/Q[0] , \UART_RX/RX_BRC/Q[1] , \UART_RX/RX_BRC/Q[2] ,
\UART_RX/RX_MVF/n18 , \UART_RX/RX_MVF/n17 , \UART_RX/RX_MVF/n16 ,
\UART_RX/RX_MVF/n15 , \UART_RX/RX_MVF/n14 , \UART_RX/RX_MVF/n13 ,
\UART_RX/RX_MVF/n12 , \UART_RX/RX_MVF/n11 , \UART_RX/RX_MVF/n10 ,
\UART_RX/RX_MVF/n9 , \UART_RX/RX_MVF/n8 , \UART_RX/RX_MVF/n7 ,
\UART_RX/RX_MVF/n6 , \UART_RX/RX_MVF/n5 , \UART_RX/RX_MVF/n3 ,
\UART_RX/RX_MVF/n2 , \UART_RX/RX_MVF/n1 , \UART_RX/RX_MVF/n26 ,
\UART_RX/RX_MVF/n24 , \UART_RX/RX_MVF/n23 , \UART_RX/RX_MVF/n22 ,
\UART_RX/RX_MVF/n21 , \UART_RX/RX_MVF/iCounter[0] ,
\UART_RX/RX_MVF/iCounter[1] , \UART_RX/RX_MVF/iCounter[2] ,
\UART_RX/RX_MVF/iCounter[3] , \UART_RX/RX_IFSB/n18 ,
\UART_RX/RX_IFSB/n17 , \UART_RX/RX_IFSB/n16 , \UART_RX/RX_IFSB/n15 ,
\UART_RX/RX_IFSB/n14 , \UART_RX/RX_IFSB/n13 , \UART_RX/RX_IFSB/n12 ,
\UART_RX/RX_IFSB/n11 , \UART_RX/RX_IFSB/n10 , \UART_RX/RX_IFSB/n9 ,
\UART_RX/RX_IFSB/n8 , \UART_RX/RX_IFSB/n7 , \UART_RX/RX_IFSB/n6 ,
\UART_RX/RX_IFSB/n5 , \UART_RX/RX_IFSB/n4 , \UART_RX/RX_IFSB/n3 ,
\UART_RX/RX_IFSB/n2 , \UART_RX/RX_IFSB/n1 , \UART_RX/RX_IFSB/n33 ,
\UART_RX/RX_IFSB/n32 , \UART_RX/RX_IFSB/n31 , \UART_RX/RX_IFSB/n30 ,
\UART_RX/RX_IFSB/iCount[0] , \UART_RX/RX_IFSB/iCount[1] ,
\UART_RX/RX_IFSB/iCount[2] , \r108/n1 , n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689;
wire [2:0] iA;
wire [7:0] iDIN;
wire [7:0] iDLL;
wire [7:0] iDLM;
wire [3:0] iIER;
wire [7:0] iLSR;
wire [7:0] iMSR;
wire [3:0] iIIR;
wire [5:0] iTimeoutCount;
wire [1:0] iFCR_RXTrigger;
wire [2:1] iFCR;
wire [7:0] iLCR;
wire [5:0] iMCR;
wire [6:0] iFECounter;
wire [10:0] iRXFIFOQ;
wire [10:0] iRXFIFOD;
wire [7:0] iSCR;
wire [7:0] iTXFIFOQ;
wire [5:1] iRXFIFOUsage;
wire [7:0] iTSR;
wire [7:0] iRXData;
wire [1:0] State;
wire [15:2] \UART_BG16/add_54/carry ;
wire [6:2] \UART_TXFF/add_73/carry ;
wire [6:2] \UART_TXFF/add_77/carry ;
wire [6:2] \UART_RXFF/add_73/carry ;
wire [6:2] \UART_RXFF/add_77/carry ;
wire [2:0] \UART_RX/NState ;
wire [6:0] \r108/carry ;
notech_reg \iDIN_reg[7] ( .D(DIN[7]), .CP(CLK), .CD(n416), .Q(iDIN[7]) );
notech_reg \iDIN_reg[6] ( .D(DIN[6]), .CP(CLK), .CD(n420), .Q(iDIN[6]) );
notech_reg \iDIN_reg[5] ( .D(DIN[5]), .CP(CLK), .CD(n419), .Q(iDIN[5]) );
notech_reg \iDIN_reg[4] ( .D(DIN[4]), .CP(CLK), .CD(n415), .Q(iDIN[4]) );
notech_reg \iDIN_reg[3] ( .D(DIN[3]), .CP(CLK), .CD(n420), .Q(iDIN[3]) );
notech_reg \iDIN_reg[2] ( .D(DIN[2]), .CP(CLK), .CD(n420), .Q(iDIN[2]) );
notech_reg \iDIN_reg[1] ( .D(DIN[1]), .CP(CLK), .CD(n415), .Q(iDIN[1]) );
notech_reg \iDIN_reg[0] ( .D(DIN[0]), .CP(CLK), .CD(n416), .Q(iDIN[0]) );
notech_reg \iA_reg[2] ( .D(A[2]), .CP(CLK), .CD(n416), .Q(iA[2]) );
notech_reg \iA_reg[1] ( .D(A[1]), .CP(CLK), .CD(n415), .Q(iA[1]) );
notech_reg \iA_reg[0] ( .D(A[0]), .CP(CLK), .CD(n420), .Q(iA[0]) );
notech_reg \iFCR_RXTrigger_reg[1] ( .D(n369), .CP(CLK), .CD(n420), .Q(
iFCR_RXTrigger[1]) );
notech_reg \iFCR_RXTrigger_reg[0] ( .D(n368), .CP(CLK), .CD(n419), .Q(
iFCR_RXTrigger[0]) );
notech_reg iFCR_FIFOEnable_reg ( .D(n367), .CP(CLK), .CD(n416), .Q(iIIR_6)
);
notech_reg iFCR_RXFIFOReset_reg ( .D(N94), .CP(CLK), .CD(n418), .Q(iFCR[1])
);
notech_reg iFCR_TXFIFOReset_reg ( .D(N95), .CP(CLK), .CD(n417), .Q(iFCR[2])
);
notech_reg \iLCR_reg[7] ( .D(n366), .CP(CLK), .CD(n417), .Q(iLCR[7]) );
notech_reg \iDLL_reg[7] ( .D(n365), .CP(CLK), .CD(n416), .Q(iDLL[7]) );
notech_reg \iDLL_reg[6] ( .D(n364), .CP(CLK), .CD(n419), .Q(iDLL[6]) );
notech_reg \iDLL_reg[5] ( .D(n363), .CP(CLK), .CD(n420), .Q(iDLL[5]) );
notech_reg \iDLL_reg[4] ( .D(n362), .CP(CLK), .CD(n418), .Q(iDLL[4]) );
notech_reg \iDLL_reg[3] ( .D(n361), .CP(CLK), .CD(n416), .Q(iDLL[3]) );
notech_reg \iDLL_reg[2] ( .D(n360), .CP(CLK), .CD(n418), .Q(iDLL[2]) );
notech_reg \iDLL_reg[1] ( .D(n359), .CP(CLK), .CD(n419), .Q(iDLL[1]) );
notech_reg \iDLL_reg[0] ( .D(n358), .CP(CLK), .CD(n415), .Q(iDLL[0]) );
notech_reg \iDLM_reg[7] ( .D(n357), .CP(CLK), .CD(n420), .Q(iDLM[7]) );
notech_reg \iDLM_reg[6] ( .D(n356), .CP(CLK), .CD(n417), .Q(iDLM[6]) );
notech_reg \iDLM_reg[5] ( .D(n355), .CP(CLK), .CD(n415), .Q(iDLM[5]) );
notech_reg \iDLM_reg[4] ( .D(n354), .CP(CLK), .CD(n418), .Q(iDLM[4]) );
notech_reg \iDLM_reg[3] ( .D(n353), .CP(CLK), .CD(n415), .Q(iDLM[3]) );
notech_reg \iDLM_reg[2] ( .D(n352), .CP(CLK), .CD(n416), .Q(iDLM[2]) );
notech_reg \iDLM_reg[1] ( .D(n351), .CP(CLK), .CD(n420), .Q(iDLM[1]) );
notech_reg \iDLM_reg[0] ( .D(n350), .CP(CLK), .CD(n415), .Q(iDLM[0]) );
notech_reg iFCR_FIFO64E_reg ( .D(n412), .CP(CLK), .CD(n420), .Q(iFCR_5) );
notech_reg \iIER_reg[3] ( .D(n349), .CP(CLK), .CD(n420), .Q(iIER[3]) );
notech_reg \iIER_reg[2] ( .D(n348), .CP(CLK), .CD(n417), .Q(iIER[2]) );
notech_reg \iIER_reg[1] ( .D(n347), .CP(CLK), .CD(n419), .Q(iIER[1]) );
notech_reg \iIER_reg[0] ( .D(n346), .CP(CLK), .CD(n417), .Q(iIER[0]) );
notech_reg \iLCR_reg[6] ( .D(n345), .CP(CLK), .CD(n416), .Q(iLCR[6]) );
notech_reg \iLCR_reg[5] ( .D(n344), .CP(CLK), .CD(n418), .Q(iLCR[5]) );
notech_reg \iLCR_reg[4] ( .D(n343), .CP(CLK), .CD(n417), .Q(iLCR[4]) );
notech_reg \iLCR_reg[3] ( .D(n342), .CP(CLK), .CD(n416), .Q(iLCR[3]) );
notech_reg \iLCR_reg[2] ( .D(n341), .CP(CLK), .CD(n419), .Q(iLCR[2]) );
notech_reg \iLCR_reg[1] ( .D(n340), .CP(CLK), .CD(n419), .Q(iLCR[1]) );
notech_reg \iLCR_reg[0] ( .D(n339), .CP(CLK), .CD(n418), .Q(iLCR[0]) );
notech_reg \iMCR_reg[5] ( .D(n338), .CP(CLK), .CD(n417), .Q(iMCR[5]) );
notech_reg \iMCR_reg[4] ( .D(n337), .CP(CLK), .CD(n417), .Q(iMCR[4]) );
notech_reg \iMCR_reg[3] ( .D(n336), .CP(CLK), .CD(n420), .Q(iMCR[3]) );
notech_reg \iMCR_reg[2] ( .D(n335), .CP(CLK), .CD(n417), .Q(iMCR[2]) );
notech_reg \iMCR_reg[1] ( .D(n334), .CP(CLK), .CD(n418), .Q(iMCR[1]) );
notech_reg \iMCR_reg[0] ( .D(n333), .CP(CLK), .CD(n415), .Q(iMCR[0]) );
notech_reg iMSR_dDCD_reg ( .D(n411), .CP(CLK), .CD(n419), .Q(iMSR[3]) );
notech_reg iMSR_dDSR_reg ( .D(n410), .CP(CLK), .CD(n415), .Q(iMSR[1]) );
notech_reg iMSR_TERI_reg ( .D(n409), .CP(CLK), .CD(n417), .Q(iMSR[2]) );
notech_reg \iSCR_reg[7] ( .D(n332), .CP(CLK), .CD(n416), .Q(iSCR[7]) );
notech_reg \iSCR_reg[6] ( .D(n331), .CP(CLK), .CD(n419), .Q(iSCR[6]) );
notech_reg \iSCR_reg[5] ( .D(n330), .CP(CLK), .CD(n418), .Q(iSCR[5]) );
notech_reg \iSCR_reg[4] ( .D(n329), .CP(CLK), .CD(n415), .Q(iSCR[4]) );
notech_reg \iSCR_reg[3] ( .D(n328), .CP(CLK), .CD(n415), .Q(iSCR[3]) );
notech_reg \iSCR_reg[2] ( .D(n327), .CP(CLK), .CD(n419), .Q(iSCR[2]) );
notech_reg \iSCR_reg[1] ( .D(n326), .CP(CLK), .CD(n416), .Q(iSCR[1]) );
notech_reg \iSCR_reg[0] ( .D(n325), .CP(CLK), .CD(n417), .Q(iSCR[0]) );
notech_reg iRTS_reg ( .D(n408), .CP(CLK), .CD(n418), .Q(iRTS) );
notech_reg iMSR_dCTS_reg ( .D(n407), .CP(CLK), .CD(n416), .Q(iMSR[0]) );
notech_reg \State_reg[0] ( .D(N181), .CP(CLK), .CD(n415), .Q(State[0]) );
notech_reg iTXFIFORead_reg ( .D(n679), .CP(CLK), .CD(n416), .Q(iTXFIFORead)
);
notech_reg \iTSR_reg[7] ( .D(n324), .CP(CLK), .CD(n415), .Q(iTSR[7]) );
notech_reg \iTSR_reg[6] ( .D(n323), .CP(CLK), .CD(n419), .Q(iTSR[6]) );
notech_reg \iTSR_reg[5] ( .D(n322), .CP(CLK), .CD(n418), .Q(iTSR[5]) );
notech_reg \iTSR_reg[4] ( .D(n321), .CP(CLK), .CD(n417), .Q(iTSR[4]) );
notech_reg \iTSR_reg[3] ( .D(n320), .CP(CLK), .CD(n418), .Q(iTSR[3]) );
notech_reg \iTSR_reg[2] ( .D(n319), .CP(CLK), .CD(n420), .Q(iTSR[2]) );
notech_reg \iTSR_reg[1] ( .D(n318), .CP(CLK), .CD(n419), .Q(iTSR[1]) );
notech_reg \iTSR_reg[0] ( .D(n317), .CP(CLK), .CD(n416), .Q(iTSR[0]) );
notech_reg \State_reg[1] ( .D(N182), .CP(CLK), .CD(n419), .Q(State[1]) );
notech_reg iTXRunning_reg ( .D(n414), .CP(CLK), .CD(n416), .Q(iTXRunning) );
notech_reg iTXStart_reg ( .D(N183), .CP(CLK), .CD(n418), .Q(iTXStart) );
notech_reg iRXFIFOClear_reg ( .D(N190), .CP(CLK), .CD(n420), .Q(iRXFIFOClear) );
notech_reg State_reg2 ( .D(n673), .CP(CLK), .CD(n420), .Q(State_snps_wire)
);
notech_reg \iRXFIFOD_reg[0] ( .D(n406), .CP(CLK), .CD(n420), .Q(iRXFIFOD[0]) );
notech_reg \iRXFIFOD_reg[1] ( .D(n405), .CP(CLK), .CD(n419), .Q(iRXFIFOD[1]) );
notech_reg \iRXFIFOD_reg[2] ( .D(n404), .CP(CLK), .CD(n416), .Q(iRXFIFOD[2]) );
notech_reg \iRXFIFOD_reg[3] ( .D(n403), .CP(CLK), .CD(n418), .Q(iRXFIFOD[3]) );
notech_reg \iRXFIFOD_reg[4] ( .D(n402), .CP(CLK), .CD(n419), .Q(iRXFIFOD[4]) );
notech_reg \iRXFIFOD_reg[5] ( .D(n401), .CP(CLK), .CD(n418), .Q(iRXFIFOD[5]) );
notech_reg \iRXFIFOD_reg[6] ( .D(n400), .CP(CLK), .CD(n417), .Q(iRXFIFOD[6]) );
notech_reg \iRXFIFOD_reg[7] ( .D(n399), .CP(CLK), .CD(n415), .Q(iRXFIFOD[7]) );
notech_reg \iRXFIFOD_reg[10] ( .D(n398), .CP(CLK), .CD(n420), .Q(
iRXFIFOD[10]) );
notech_reg \iRXFIFOD_reg[9] ( .D(n397), .CP(CLK), .CD(n417), .Q(iRXFIFOD[9]) );
notech_reg \iRXFIFOD_reg[8] ( .D(n396), .CP(CLK), .CD(n419), .Q(iRXFIFOD[8]) );
notech_reg iRXFIFOWrite_reg ( .D(N191), .CP(CLK), .CD(n415), .Q(iRXFIFOWrite) );
notech_reg iLSR_OE_reg ( .D(n395), .CP(CLK), .CD(n418), .Q(iLSR[1]) );
notech_reg \iTimeoutCount_reg[5] ( .D(n394), .CP(CLK), .CD(n417), .Q(
iTimeoutCount[5]) );
notech_reg \iTimeoutCount_reg[0] ( .D(n393), .CP(CLK), .CD(n415), .Q(
iTimeoutCount[0]) );
notech_reg \iTimeoutCount_reg[1] ( .D(n392), .CP(CLK), .CD(n416), .Q(
iTimeoutCount[1]) );
notech_reg \iTimeoutCount_reg[2] ( .D(n391), .CP(CLK), .CD(n419), .Q(
iTimeoutCount[2]) );
notech_reg \iTimeoutCount_reg[3] ( .D(n390), .CP(CLK), .CD(n419), .Q(
iTimeoutCount[3]) );
notech_reg \iTimeoutCount_reg[4] ( .D(n389), .CP(CLK), .CD(n418), .Q(
iTimeoutCount[4]) );
notech_reg iCharTimeout_reg ( .D(n388), .CP(CLK), .CD(n420), .Q(iCharTimeout) );
notech_reg iLSR_PE_reg ( .D(n387), .CP(CLK), .CD(n417), .Q(iLSR[2]) );
notech_reg iLSR_FE_reg ( .D(n386), .CP(CLK), .CD(n415), .Q(iLSR[3]) );
notech_reg iLSR_BI_reg ( .D(n377), .CP(CLK), .CD(n417), .Q(iLSR[4]) );
notech_reg iTHRInterrupt_reg ( .D(n376), .CP(CLK), .CD(n420), .Q(
iTHRInterrupt) );
notech_reg \iFECounter_reg[6] ( .D(n379), .CP(CLK), .CD(n418), .Q(
iFECounter[6]) );
notech_reg \iFECounter_reg[0] ( .D(n385), .CP(CLK), .CD(n420), .Q(
iFECounter[0]) );
notech_reg \iFECounter_reg[1] ( .D(n384), .CP(CLK), .CD(n416), .Q(
iFECounter[1]) );
notech_reg \iFECounter_reg[2] ( .D(n383), .CP(CLK), .CD(n415), .Q(
iFECounter[2]) );
notech_reg \iFECounter_reg[3] ( .D(n382), .CP(CLK), .CD(n415), .Q(
iFECounter[3]) );
notech_reg \iFECounter_reg[4] ( .D(n381), .CP(CLK), .CD(n417), .Q(
iFECounter[4]) );
notech_reg \iFECounter_reg[5] ( .D(n380), .CP(CLK), .CD(n417), .Q(
iFECounter[5]) );
notech_reg iLSR_FIFOERR_reg ( .D(n378), .CP(CLK), .CD(1'b1), .Q(iLSR_FIFOERR) );
notech_reg_set SOUT_reg ( .D(N202), .CP(CLK), .SD(n418), .Q(SOUT) );
notech_reg_set DDIS_reg ( .D(N197), .CP(CLK), .SD(n417), .Q(DDIS) );
notech_reg_set BAUDOUTN_reg ( .D(n677), .CP(CLK), .SD(n419), .Q(BAUDOUTN) );
notech_reg_set OUT1N_reg ( .D(N198), .CP(CLK), .SD(n418), .Q(OUT1N) );
notech_reg_set OUT2N_reg ( .D(N199), .CP(CLK), .SD(n415), .Q(OUT2N) );
notech_reg_set RTSN_reg ( .D(N200), .CP(CLK), .SD(n416), .Q(RTSN) );
notech_reg_set DTRN_reg ( .D(N201), .CP(CLK), .SD(n416), .Q(DTRN) );
notech_inv U447 ( .A(RST), .Z(n415) );
notech_inv U448 ( .A(RST), .Z(n416) );
notech_inv U449 ( .A(RST), .Z(n417) );
notech_inv U450 ( .A(RST), .Z(n418) );
notech_inv U451 ( .A(RST), .Z(n419) );
notech_inv U452 ( .A(RST), .Z(n420) );
notech_inv U453 ( .A(iBaudtick16x), .Z(n677) );
notech_mux2 U454 ( .A(iFCR_5), .B(iDIN[5]), .S(n421), .Z(n412) );
notech_and2 U455 ( .A(n422), .B(iLCR[7]), .Z(n421) );
notech_nao3 U456 ( .C(iDCDnFE), .A(n685), .B(n424), .Z(n411) );
notech_or2 U457 ( .A(n425), .B(n426), .Z(n424) );
notech_nao3 U459 ( .C(iDSRnFE), .A(n684), .B(n428), .Z(n410) );
notech_or2 U460 ( .A(n425), .B(n429), .Z(n428) );
notech_or2 U462 ( .A(n430), .B(iRInFE), .Z(n409) );
notech_nor2 U463 ( .A(n425), .B(n431), .Z(n430) );
notech_and2 U464 ( .A(n432), .B(iMCR[1]), .Z(n408) );
notech_or2 U465 ( .A(n433), .B(n434), .Z(n432) );
notech_and2 U466 ( .A(n435), .B(n436), .Z(n433) );
notech_nand2 U467 ( .A(n437), .B(n438), .Z(n436) );
notech_nao3 U468 ( .C(iCTSnFE), .A(n683), .B(n440), .Z(n407) );
notech_or2 U469 ( .A(n425), .B(n441), .Z(n440) );
notech_and4 U470 ( .A(iA[2]), .B(iReadFE), .C(n442), .D(iA[1]), .Z(n425) );
notech_mux2 U472 ( .A(iRXFIFOD[0]), .B(iRXData[0]), .S(n673), .Z(n406) );
notech_mux2 U473 ( .A(iRXFIFOD[1]), .B(iRXData[1]), .S(n673), .Z(n405) );
notech_mux2 U474 ( .A(iRXFIFOD[2]), .B(iRXData[2]), .S(n673), .Z(n404) );
notech_mux2 U475 ( .A(iRXFIFOD[3]), .B(iRXData[3]), .S(n673), .Z(n403) );
notech_mux2 U476 ( .A(iRXFIFOD[4]), .B(iRXData[4]), .S(n673), .Z(n402) );
notech_mux2 U477 ( .A(iRXFIFOD[5]), .B(iRXData[5]), .S(n673), .Z(n401) );
notech_mux2 U478 ( .A(iRXFIFOD[6]), .B(iRXData[6]), .S(n673), .Z(n400) );
notech_mux2 U479 ( .A(iRXFIFOD[7]), .B(iRXData[7]), .S(n673), .Z(n399) );
notech_mux2 U480 ( .A(iRXFIFOD[10]), .B(iRXBI), .S(n673), .Z(n398) );
notech_mux2 U481 ( .A(iRXFIFOD[9]), .B(iRXFE), .S(n673), .Z(n397) );
notech_mux2 U482 ( .A(iRXFIFOD[8]), .B(iRXPE), .S(n673), .Z(n396) );
notech_nao4 U483 ( .A(n443), .B(n444), .C(n680), .D(n446), .Z(n395) );
notech_inv U484 ( .A(n447), .Z(n446) );
notech_mux2 U485 ( .A(n448), .B(n676), .S(n449), .Z(n447) );
notech_inv U486 ( .A(n450), .Z(n676) );
notech_nao4 U487 ( .A(n451), .B(n452), .C(n453), .D(n454), .Z(n394) );
notech_mux2 U488 ( .A(n455), .B(n456), .S(n457), .Z(n393) );
notech_mux2 U489 ( .A(n458), .B(n459), .S(iTimeoutCount[1]), .Z(n392) );
notech_nor2 U490 ( .A(n460), .B(n457), .Z(n458) );
notech_inv U491 ( .A(iTimeoutCount[0]), .Z(n457) );
notech_mux2 U492 ( .A(n461), .B(n462), .S(iTimeoutCount[2]), .Z(n391) );
notech_or2 U493 ( .A(n459), .B(n463), .Z(n462) );
notech_nor2 U494 ( .A(n460), .B(iTimeoutCount[1]), .Z(n463) );
notech_or2 U495 ( .A(n464), .B(n455), .Z(n459) );
notech_nor2 U496 ( .A(n460), .B(iTimeoutCount[0]), .Z(n464) );
notech_ao3 U497 ( .A(iTimeoutCount[1]), .B(iTimeoutCount[0]), .C(n460), .Z(
n461) );
notech_mux2 U498 ( .A(n465), .B(n466), .S(iTimeoutCount[3]), .Z(n390) );
notech_and2 U499 ( .A(n456), .B(n467), .Z(n465) );
notech_inv U500 ( .A(n460), .Z(n456) );
notech_inv U501 ( .A(n468), .Z(n389) );
notech_mux2 U502 ( .A(n451), .B(n453), .S(n454), .Z(n468) );
notech_inv U503 ( .A(iTimeoutCount[4]), .Z(n454) );
notech_nao3 U504 ( .C(n460), .A(iTimeoutCount[3]), .B(n467), .Z(n453) );
notech_nor2 U505 ( .A(n466), .B(n469), .Z(n451) );
notech_nor2 U506 ( .A(n460), .B(iTimeoutCount[3]), .Z(n469) );
notech_or2 U507 ( .A(n470), .B(n455), .Z(n466) );
notech_nor2 U508 ( .A(n460), .B(n467), .Z(n470) );
notech_and3 U509 ( .A(iTimeoutCount[2]), .B(iTimeoutCount[1]), .C(
iTimeoutCount[0]), .Z(n467) );
notech_or2 U510 ( .A(n455), .B(n471), .Z(n460) );
notech_nor2 U511 ( .A(n471), .B(n472), .Z(n455) );
notech_and2 U512 ( .A(iBaudtick2x), .B(n452), .Z(n472) );
notech_inv U513 ( .A(iTimeoutCount[5]), .Z(n452) );
notech_nao3 U514 ( .C(n371), .A(n438), .B(\UART_RXFF/n441 ), .Z(n471) );
notech_ao3 U515 ( .A(n474), .B(iIIR_6), .C(n371), .Z(n388) );
notech_or2 U516 ( .A(iCharTimeout), .B(iTimeoutCount[5]), .Z(n474) );
notech_or2 U517 ( .A(n475), .B(iPERE), .Z(n387) );
notech_nor2 U518 ( .A(n443), .B(n476), .Z(n475) );
notech_or2 U519 ( .A(n477), .B(iFERE), .Z(n386) );
notech_nor2 U520 ( .A(n443), .B(n478), .Z(n477) );
notech_inv U521 ( .A(n479), .Z(n385) );
notech_mux2 U522 ( .A(n480), .B(n481), .S(iFECounter[0]), .Z(n479) );
notech_nao4 U523 ( .A(n481), .B(n482), .C(n480), .D(n483), .Z(n384) );
notech_inv U524 ( .A(N130), .Z(n483) );
notech_inv U525 ( .A(iFECounter[1]), .Z(n482) );
notech_nao4 U526 ( .A(n481), .B(n484), .C(n480), .D(n485), .Z(n383) );
notech_inv U527 ( .A(N131), .Z(n485) );
notech_inv U528 ( .A(iFECounter[2]), .Z(n484) );
notech_nao4 U529 ( .A(n481), .B(n486), .C(n480), .D(n487), .Z(n382) );
notech_inv U530 ( .A(N132), .Z(n487) );
notech_inv U531 ( .A(iFECounter[3]), .Z(n486) );
notech_nao4 U532 ( .A(n481), .B(n488), .C(n480), .D(n489), .Z(n381) );
notech_inv U533 ( .A(N133), .Z(n489) );
notech_inv U534 ( .A(iFECounter[4]), .Z(n488) );
notech_nao4 U535 ( .A(n481), .B(n490), .C(n480), .D(n491), .Z(n380) );
notech_inv U536 ( .A(N134), .Z(n491) );
notech_inv U537 ( .A(iFECounter[5]), .Z(n490) );
notech_nao4 U538 ( .A(n481), .B(n492), .C(n480), .D(n493), .Z(n379) );
notech_inv U539 ( .A(N135), .Z(n493) );
notech_nand2 U540 ( .A(n481), .B(\UART_RXFF/n308 ), .Z(n480) );
notech_inv U541 ( .A(iFECounter[6]), .Z(n492) );
notech_nand3 U542 ( .A(\UART_RXFF/n308 ), .B(\U3/U1/Z_0 ), .C(n495), .Z(n481) );
notech_or4 U543 ( .A(n496), .B(n497), .C(iRXFIFOEmpty), .D(n498), .Z(n495)
);
notech_nor2 U544 ( .A(n499), .B(\UART_RXFF/n441 ), .Z(n497) );
notech_mux2 U547 ( .A(iLSR_FIFOERR), .B(n500), .S(n501), .Z(n378) );
notech_nor2 U548 ( .A(n502), .B(RST), .Z(n501) );
notech_nor2 U549 ( .A(n503), .B(n500), .Z(n502) );
notech_ao3 U550 ( .A(n504), .B(n505), .C(n674), .Z(n503) );
notech_and2 U551 ( .A(iRXFIFOQ[10]), .B(n438), .Z(n674) );
notech_inv U552 ( .A(N146), .Z(n505) );
notech_inv U553 ( .A(n675), .Z(n504) );
notech_and2 U554 ( .A(iRXFIFOQ[9]), .B(n438), .Z(n675) );
notech_or2 U555 ( .A(n506), .B(iBIRE), .Z(n377) );
notech_nor2 U556 ( .A(n443), .B(n507), .Z(n506) );
notech_and4 U557 ( .A(iReadFE), .B(iA[0]), .C(n508), .D(iA[2]), .Z(n443) );
notech_or4 U558 ( .A(n509), .B(n510), .C(iLSR_THRERE), .D(iFCR[2]), .Z(n376)
);
notech_and2 U559 ( .A(iTHRInterrupt), .B(n511), .Z(n510) );
notech_nao3 U560 ( .C(iA[0]), .A(n512), .B(n513), .Z(n511) );
notech_mux2 U561 ( .A(n514), .B(n515), .S(n508), .Z(n513) );
notech_and2 U562 ( .A(n516), .B(iWriteFE), .Z(n515) );
notech_and4 U563 ( .A(iIIR[1]), .B(iReadFE), .C(n517), .D(n518), .Z(n514) );
notech_ao3 U564 ( .A(iDIN[1]), .B(n519), .C(n520), .Z(n509) );
notech_ao3 U565 ( .A(iReadFE), .B(n521), .C(iA[0]), .Z(n371) );
notech_mux2 U566 ( .A(iFCR_RXTrigger[1]), .B(iDIN[7]), .S(n422), .Z(n369) );
notech_mux2 U567 ( .A(iFCR_RXTrigger[0]), .B(iDIN[6]), .S(n422), .Z(n368) );
notech_mux2 U568 ( .A(iIIR_6), .B(iDIN[0]), .S(n422), .Z(n367) );
notech_mux2 U569 ( .A(iLCR[7]), .B(iDIN[7]), .S(n522), .Z(n366) );
notech_mux2 U570 ( .A(iDLL[7]), .B(iDIN[7]), .S(n523), .Z(n365) );
notech_mux2 U571 ( .A(iDLL[6]), .B(iDIN[6]), .S(n523), .Z(n364) );
notech_mux2 U572 ( .A(iDLL[5]), .B(iDIN[5]), .S(n523), .Z(n363) );
notech_mux2 U573 ( .A(iDLL[4]), .B(iDIN[4]), .S(n523), .Z(n362) );
notech_mux2 U574 ( .A(iDLL[3]), .B(iDIN[3]), .S(n523), .Z(n361) );
notech_mux2 U575 ( .A(iDLL[2]), .B(iDIN[2]), .S(n523), .Z(n360) );
notech_mux2 U576 ( .A(iDLL[1]), .B(iDIN[1]), .S(n523), .Z(n359) );
notech_mux2 U577 ( .A(iDLL[0]), .B(iDIN[0]), .S(n523), .Z(n358) );
notech_and2 U578 ( .A(n524), .B(n442), .Z(n523) );
notech_mux2 U579 ( .A(iDLM[7]), .B(iDIN[7]), .S(n525), .Z(n357) );
notech_mux2 U580 ( .A(iDLM[6]), .B(iDIN[6]), .S(n525), .Z(n356) );
notech_mux2 U581 ( .A(iDLM[5]), .B(iDIN[5]), .S(n525), .Z(n355) );
notech_mux2 U582 ( .A(iDLM[4]), .B(iDIN[4]), .S(n525), .Z(n354) );
notech_mux2 U583 ( .A(iDLM[3]), .B(iDIN[3]), .S(n525), .Z(n353) );
notech_mux2 U584 ( .A(iDLM[2]), .B(iDIN[2]), .S(n525), .Z(n352) );
notech_mux2 U585 ( .A(iDLM[1]), .B(iDIN[1]), .S(n525), .Z(n351) );
notech_mux2 U586 ( .A(iDLM[0]), .B(iDIN[0]), .S(n525), .Z(n350) );
notech_and2 U587 ( .A(n524), .B(iA[0]), .Z(n525) );
notech_and4 U588 ( .A(iWriteFE), .B(iLCR[7]), .C(n512), .D(n508), .Z(n524)
);
notech_mux2 U589 ( .A(iIER[3]), .B(iDIN[3]), .S(n519), .Z(n349) );
notech_mux2 U590 ( .A(iIER[2]), .B(iDIN[2]), .S(n519), .Z(n348) );
notech_mux2 U591 ( .A(iIER[1]), .B(iDIN[1]), .S(n519), .Z(n347) );
notech_mux2 U592 ( .A(iIER[0]), .B(iDIN[0]), .S(n519), .Z(n346) );
notech_and3 U593 ( .A(n521), .B(iWriteFE), .C(iA[0]), .Z(n519) );
notech_mux2 U594 ( .A(iLCR[6]), .B(iDIN[6]), .S(n522), .Z(n345) );
notech_mux2 U595 ( .A(iLCR[5]), .B(iDIN[5]), .S(n522), .Z(n344) );
notech_mux2 U596 ( .A(iLCR[4]), .B(iDIN[4]), .S(n522), .Z(n343) );
notech_mux2 U597 ( .A(iLCR[3]), .B(iDIN[3]), .S(n522), .Z(n342) );
notech_mux2 U598 ( .A(iLCR[2]), .B(iDIN[2]), .S(n522), .Z(n341) );
notech_mux2 U599 ( .A(iLCR[1]), .B(iDIN[1]), .S(n522), .Z(n340) );
notech_mux2 U600 ( .A(iLCR[0]), .B(iDIN[0]), .S(n522), .Z(n339) );
notech_and2 U601 ( .A(n526), .B(n512), .Z(n522) );
notech_mux2 U602 ( .A(iMCR[5]), .B(iDIN[5]), .S(n527), .Z(n338) );
notech_mux2 U603 ( .A(iMCR[4]), .B(iDIN[4]), .S(n527), .Z(n337) );
notech_mux2 U604 ( .A(iMCR[3]), .B(iDIN[3]), .S(n527), .Z(n336) );
notech_mux2 U605 ( .A(iMCR[2]), .B(iDIN[2]), .S(n527), .Z(n335) );
notech_mux2 U606 ( .A(iMCR[1]), .B(iDIN[1]), .S(n527), .Z(n334) );
notech_mux2 U607 ( .A(iMCR[0]), .B(iDIN[0]), .S(n527), .Z(n333) );
notech_and3 U608 ( .A(n528), .B(n508), .C(iA[2]), .Z(n527) );
notech_mux2 U609 ( .A(iSCR[7]), .B(iDIN[7]), .S(n529), .Z(n332) );
notech_mux2 U610 ( .A(iSCR[6]), .B(iDIN[6]), .S(n529), .Z(n331) );
notech_mux2 U611 ( .A(iSCR[5]), .B(iDIN[5]), .S(n529), .Z(n330) );
notech_mux2 U612 ( .A(iSCR[4]), .B(iDIN[4]), .S(n529), .Z(n329) );
notech_mux2 U613 ( .A(iSCR[3]), .B(iDIN[3]), .S(n529), .Z(n328) );
notech_mux2 U614 ( .A(iSCR[2]), .B(iDIN[2]), .S(n529), .Z(n327) );
notech_mux2 U615 ( .A(iSCR[1]), .B(iDIN[1]), .S(n529), .Z(n326) );
notech_mux2 U616 ( .A(iSCR[0]), .B(iDIN[0]), .S(n529), .Z(n325) );
notech_and2 U617 ( .A(n526), .B(iA[2]), .Z(n529) );
notech_and3 U618 ( .A(iA[1]), .B(iWriteFE), .C(iA[0]), .Z(n526) );
notech_mux2 U619 ( .A(iTSR[7]), .B(iTXFIFOQ[7]), .S(n679), .Z(n324) );
notech_mux2 U620 ( .A(iTSR[6]), .B(iTXFIFOQ[6]), .S(n679), .Z(n323) );
notech_mux2 U621 ( .A(iTSR[5]), .B(iTXFIFOQ[5]), .S(n679), .Z(n322) );
notech_mux2 U622 ( .A(iTSR[4]), .B(iTXFIFOQ[4]), .S(n679), .Z(n321) );
notech_mux2 U623 ( .A(iTSR[3]), .B(iTXFIFOQ[3]), .S(n679), .Z(n320) );
notech_mux2 U624 ( .A(iTSR[2]), .B(iTXFIFOQ[2]), .S(n679), .Z(n319) );
notech_mux2 U625 ( .A(iTSR[1]), .B(iTXFIFOQ[1]), .S(n679), .Z(n318) );
notech_mux2 U626 ( .A(iTSR[0]), .B(iTXFIFOQ[0]), .S(n679), .Z(n317) );
notech_mux2 U627 ( .A(iSOUT), .B(iSINr), .S(n530), .Z(iSIN) );
notech_nao3 U628 ( .C(n499), .A(n531), .B(iRXFIFOWrite), .Z(\U3/U1/Z_0 ) );
notech_nao3 U629 ( .C(n496), .A(n500), .B(n438), .Z(n531) );
notech_inv U630 ( .A(n498), .Z(n500) );
notech_nor4 U631 ( .A(iFECounter[2]), .B(iFECounter[1]), .C(iFECounter[0]),
.D(n532), .Z(n498) );
notech_or4 U632 ( .A(iFECounter[4]), .B(iFECounter[3]), .C(iFECounter[6]),
.D(iFECounter[5]), .Z(n532) );
notech_ao3 U633 ( .A(n533), .B(n534), .C(iFERE), .Z(n496) );
notech_inv U634 ( .A(iPERE), .Z(n534) );
notech_inv U635 ( .A(iBIRE), .Z(n533) );
notech_ao3 U636 ( .A(n535), .B(\UART_RXFF/n37 ), .C(iRXFIFOD[8]), .Z(n499)
);
notech_inv U638 ( .A(iRXFIFOD[10]), .Z(n535) );
notech_and2 U639 ( .A(n422), .B(n537), .Z(N95) );
notech_or2 U640 ( .A(iDIN[2]), .B(n538), .Z(n537) );
notech_and2 U641 ( .A(n422), .B(n539), .Z(N94) );
notech_or2 U642 ( .A(iDIN[1]), .B(n538), .Z(n539) );
notech_xor2 U643 ( .A(iDIN[0]), .B(iIIR_6), .Z(n538) );
notech_ao3 U644 ( .A(n528), .B(iA[1]), .C(iA[2]), .Z(n422) );
notech_inv U645 ( .A(n540), .Z(N66) );
notech_mux2 U646 ( .A(n435), .B(n450), .S(n449), .Z(n540) );
notech_ao3 U647 ( .A(n541), .B(n542), .C(n448), .Z(n435) );
notech_nand2 U648 ( .A(n543), .B(n544), .Z(n542) );
notech_xor2 U649 ( .A(iFCR_RXTrigger[1]), .B(iFCR_RXTrigger[0]), .Z(n544) );
notech_mux2 U650 ( .A(iRXFIFOUsage[5]), .B(iRXFIFOUsage[3]), .S(n545), .Z(
n543) );
notech_mux2 U651 ( .A(n546), .B(n547), .S(iFCR_RXTrigger[0]), .Z(n541) );
notech_nao4 U652 ( .A(iRXFIFOUsage[4]), .B(n548), .C(n549), .D(n550), .Z(
n547) );
notech_and2 U653 ( .A(n551), .B(iRXFIFOUsage[3]), .Z(n549) );
notech_ao4 U654 ( .A(iRXFIFOUsage[5]), .B(n548), .C(iRXFIFOUsage[4]), .D(
iRXFIFOUsage[1]), .Z(n551) );
notech_and2 U655 ( .A(iRXFIFOUsage[2]), .B(n545), .Z(n548) );
notech_nand2 U656 ( .A(n438), .B(n550), .Z(n546) );
notech_inv U657 ( .A(iFCR_RXTrigger[1]), .Z(n550) );
notech_and2 U658 ( .A(WR), .B(CS), .Z(N48) );
notech_or2 U659 ( .A(iMCR[4]), .B(iSOUT), .Z(N202) );
notech_nand2 U660 ( .A(n530), .B(iMCR[0]), .Z(N201) );
notech_nand2 U661 ( .A(n530), .B(iRTS), .Z(N200) );
notech_nand2 U662 ( .A(n530), .B(iMCR[3]), .Z(N199) );
notech_nand2 U663 ( .A(n530), .B(iMCR[2]), .Z(N198) );
notech_inv U664 ( .A(n678), .Z(N197) );
notech_and2 U665 ( .A(RD), .B(CS), .Z(n678) );
notech_and2 U666 ( .A(n552), .B(State_snps_wire), .Z(N191) );
notech_nand2 U667 ( .A(n448), .B(iIIR_6), .Z(n552) );
notech_mux2 U668 ( .A(iRXFIFO64Full), .B(iRXFIFOUsage[4]), .S(n545), .Z(n448) );
notech_or2 U669 ( .A(n553), .B(iFCR[1]), .Z(N190) );
notech_and2 U670 ( .A(n673), .B(n449), .Z(n553) );
notech_nor2 U671 ( .A(n680), .B(State_snps_wire), .Z(n673) );
notech_or2 U673 ( .A(n554), .B(N182), .Z(N183) );
notech_or2 U674 ( .A(n679), .B(n414), .Z(N182) );
notech_nor2 U675 ( .A(n555), .B(State[1]), .Z(n679) );
notech_or2 U676 ( .A(n554), .B(n556), .Z(N181) );
notech_and2 U677 ( .A(iTXFinished), .B(n414), .Z(n556) );
notech_and2 U678 ( .A(State[1]), .B(n555), .Z(n414) );
notech_inv U679 ( .A(State[0]), .Z(n555) );
notech_nor4 U680 ( .A(State[0]), .B(n557), .C(iTXFIFOEmpty), .D(State[1]),
.Z(n554) );
notech_and2 U681 ( .A(n558), .B(iMCR[5]), .Z(n557) );
notech_ao3 U682 ( .A(n521), .B(n528), .C(n559), .Z(N169) );
notech_mux2 U683 ( .A(n560), .B(n520), .S(n449), .Z(n559) );
notech_mux2 U684 ( .A(iTXFIFO64Full), .B(\iTXFIFOUsage[4] ), .S(n545), .Z(
n560) );
notech_and2 U685 ( .A(n442), .B(iWriteFE), .Z(n528) );
notech_inv U686 ( .A(iA[0]), .Z(n442) );
notech_and3 U687 ( .A(n512), .B(n516), .C(n508), .Z(n521) );
notech_inv U688 ( .A(iA[1]), .Z(n508) );
notech_inv U689 ( .A(iA[2]), .Z(n512) );
notech_inv U690 ( .A(n561), .Z(N157) );
notech_inv U691 ( .A(n562), .Z(N156) );
notech_inv U692 ( .A(n563), .Z(N155) );
notech_inv U693 ( .A(n558), .Z(N154) );
notech_and2 U694 ( .A(iRXFIFOQ[8]), .B(n438), .Z(N146) );
notech_nand3 U695 ( .A(n564), .B(n565), .C(n566), .Z(DOUT[7]) );
notech_and3 U696 ( .A(n567), .B(n568), .C(n569), .Z(n566) );
notech_ao4 U697 ( .A(n561), .B(n570), .C(n516), .D(n571), .Z(n569) );
notech_inv U698 ( .A(iLCR[7]), .Z(n516) );
notech_mux2 U699 ( .A(n572), .B(iDCDn), .S(n530), .Z(n561) );
notech_nao3 U700 ( .C(n449), .A(iLSR_FIFOERR), .B(n573), .Z(n567) );
notech_ao4 U701 ( .A(n574), .B(n575), .C(n576), .D(n577), .Z(n565) );
notech_inv U702 ( .A(iDLL[7]), .Z(n576) );
notech_inv U703 ( .A(iDLM[7]), .Z(n574) );
notech_ao4 U704 ( .A(n578), .B(n579), .C(n580), .D(n581), .Z(n564) );
notech_inv U705 ( .A(iSCR[7]), .Z(n580) );
notech_inv U706 ( .A(iRXFIFOQ[7]), .Z(n579) );
notech_nand3 U707 ( .A(n582), .B(n583), .C(n584), .Z(DOUT[6]) );
notech_and3 U708 ( .A(n585), .B(n568), .C(n586), .Z(n584) );
notech_ao4 U709 ( .A(n562), .B(n570), .C(n587), .D(n571), .Z(n586) );
notech_inv U710 ( .A(iLCR[6]), .Z(n587) );
notech_mux2 U711 ( .A(n588), .B(iRIn), .S(n530), .Z(n562) );
notech_nao3 U712 ( .C(iTXRunning), .A(iTXFIFOEmpty), .B(n573), .Z(n585) );
notech_ao4 U713 ( .A(n589), .B(n575), .C(n590), .D(n577), .Z(n583) );
notech_inv U714 ( .A(iDLL[6]), .Z(n590) );
notech_inv U715 ( .A(iDLM[6]), .Z(n589) );
notech_ao4 U716 ( .A(n578), .B(n591), .C(n592), .D(n581), .Z(n582) );
notech_inv U717 ( .A(iSCR[6]), .Z(n592) );
notech_inv U718 ( .A(iRXFIFOQ[6]), .Z(n591) );
notech_or4 U719 ( .A(n593), .B(n594), .C(n595), .D(n596), .Z(DOUT[5]) );
notech_nao4 U720 ( .A(n597), .B(n571), .C(n434), .D(n598), .Z(n596) );
notech_inv U721 ( .A(iMCR[5]), .Z(n434) );
notech_inv U722 ( .A(iLCR[5]), .Z(n597) );
notech_nand2 U723 ( .A(n599), .B(n600), .Z(n595) );
notech_or2 U724 ( .A(n601), .B(n520), .Z(n600) );
notech_inv U725 ( .A(iTXFIFOEmpty), .Z(n520) );
notech_ao4 U726 ( .A(n545), .B(n568), .C(n563), .D(n570), .Z(n599) );
notech_mux2 U727 ( .A(n602), .B(iDSRn), .S(n530), .Z(n563) );
notech_or2 U728 ( .A(n603), .B(n449), .Z(n568) );
notech_inv U729 ( .A(iIIR_6), .Z(n449) );
notech_inv U730 ( .A(iFCR_5), .Z(n545) );
notech_nao4 U731 ( .A(n604), .B(n581), .C(n578), .D(n605), .Z(n594) );
notech_inv U732 ( .A(iRXFIFOQ[5]), .Z(n605) );
notech_inv U733 ( .A(iSCR[5]), .Z(n604) );
notech_nao4 U734 ( .A(n606), .B(n577), .C(n607), .D(n575), .Z(n593) );
notech_inv U735 ( .A(iDLM[5]), .Z(n607) );
notech_inv U736 ( .A(iDLL[5]), .Z(n606) );
notech_or4 U737 ( .A(n608), .B(n609), .C(n610), .D(n611), .Z(DOUT[4]) );
notech_nao4 U738 ( .A(n612), .B(n571), .C(n530), .D(n598), .Z(n611) );
notech_inv U739 ( .A(iLCR[4]), .Z(n612) );
notech_nao4 U740 ( .A(n507), .B(n601), .C(n558), .D(n570), .Z(n610) );
notech_mux2 U741 ( .A(n437), .B(iCTSn), .S(n530), .Z(n558) );
notech_inv U742 ( .A(iMCR[4]), .Z(n530) );
notech_inv U743 ( .A(iRTS), .Z(n437) );
notech_inv U744 ( .A(iLSR[4]), .Z(n507) );
notech_nao4 U745 ( .A(n613), .B(n581), .C(n578), .D(n614), .Z(n609) );
notech_inv U746 ( .A(iRXFIFOQ[4]), .Z(n614) );
notech_inv U747 ( .A(n615), .Z(n578) );
notech_inv U748 ( .A(iSCR[4]), .Z(n613) );
notech_nao4 U749 ( .A(n616), .B(n577), .C(n617), .D(n575), .Z(n608) );
notech_inv U750 ( .A(iDLM[4]), .Z(n617) );
notech_inv U751 ( .A(iDLL[4]), .Z(n616) );
notech_or4 U752 ( .A(n618), .B(n619), .C(n620), .D(n621), .Z(DOUT[3]) );
notech_nand3 U753 ( .A(n622), .B(n623), .C(n624), .Z(n621) );
notech_ao4 U754 ( .A(\UART_RX/n47 ), .B(n571), .C(n603), .D(n518), .Z(n624)
);
notech_inv U755 ( .A(iIIR[3]), .Z(n518) );
notech_or2 U757 ( .A(n598), .B(n572), .Z(n623) );
notech_inv U758 ( .A(iMCR[3]), .Z(n572) );
notech_ao4 U759 ( .A(n426), .B(n570), .C(n478), .D(n601), .Z(n622) );
notech_inv U760 ( .A(iLSR[3]), .Z(n478) );
notech_inv U761 ( .A(iMSR[3]), .Z(n426) );
notech_nao4 U762 ( .A(n626), .B(n627), .C(n628), .D(n581), .Z(n620) );
notech_inv U763 ( .A(iSCR[3]), .Z(n628) );
notech_inv U764 ( .A(iIER[3]), .Z(n626) );
notech_nao4 U765 ( .A(n629), .B(n577), .C(n630), .D(n575), .Z(n619) );
notech_inv U766 ( .A(iDLM[3]), .Z(n630) );
notech_inv U767 ( .A(iDLL[3]), .Z(n629) );
notech_and2 U768 ( .A(iRXFIFOQ[3]), .B(n615), .Z(n618) );
notech_or4 U769 ( .A(n631), .B(n632), .C(n633), .D(n634), .Z(DOUT[2]) );
notech_nand3 U770 ( .A(n635), .B(n636), .C(n637), .Z(n634) );
notech_ao4 U771 ( .A(n638), .B(n571), .C(n603), .D(n517), .Z(n637) );
notech_inv U772 ( .A(iIIR[2]), .Z(n517) );
notech_inv U773 ( .A(iLCR[2]), .Z(n638) );
notech_or2 U774 ( .A(n598), .B(n588), .Z(n636) );
notech_inv U775 ( .A(iMCR[2]), .Z(n588) );
notech_ao4 U776 ( .A(n431), .B(n570), .C(n476), .D(n601), .Z(n635) );
notech_inv U777 ( .A(iLSR[2]), .Z(n476) );
notech_inv U778 ( .A(iMSR[2]), .Z(n431) );
notech_nao4 U779 ( .A(n639), .B(n627), .C(n640), .D(n581), .Z(n633) );
notech_inv U780 ( .A(iSCR[2]), .Z(n640) );
notech_inv U781 ( .A(iIER[2]), .Z(n639) );
notech_nao4 U782 ( .A(n641), .B(n577), .C(n642), .D(n575), .Z(n632) );
notech_inv U783 ( .A(iDLM[2]), .Z(n642) );
notech_inv U784 ( .A(iDLL[2]), .Z(n641) );
notech_and2 U785 ( .A(iRXFIFOQ[2]), .B(n615), .Z(n631) );
notech_or4 U786 ( .A(n643), .B(n644), .C(n645), .D(n646), .Z(DOUT[1]) );
notech_nand3 U787 ( .A(n647), .B(n648), .C(n649), .Z(n646) );
notech_ao4 U788 ( .A(\UART_TX/n37 ), .B(n571), .C(n651), .D(n603), .Z(n649)
);
notech_inv U789 ( .A(iIIR[1]), .Z(n651) );
notech_nand2 U791 ( .A(n652), .B(iMCR[1]), .Z(n648) );
notech_ao4 U792 ( .A(n429), .B(n570), .C(n444), .D(n601), .Z(n647) );
notech_inv U793 ( .A(iLSR[1]), .Z(n444) );
notech_inv U794 ( .A(iMSR[1]), .Z(n429) );
notech_nao4 U795 ( .A(n653), .B(n627), .C(n654), .D(n581), .Z(n645) );
notech_inv U796 ( .A(iSCR[1]), .Z(n654) );
notech_inv U797 ( .A(iIER[1]), .Z(n653) );
notech_nao4 U798 ( .A(n655), .B(n577), .C(n656), .D(n575), .Z(n644) );
notech_inv U799 ( .A(iDLM[1]), .Z(n656) );
notech_inv U800 ( .A(iDLL[1]), .Z(n655) );
notech_and2 U801 ( .A(iRXFIFOQ[1]), .B(n615), .Z(n643) );
notech_or4 U802 ( .A(n657), .B(n658), .C(n659), .D(n660), .Z(DOUT[0]) );
notech_nand3 U803 ( .A(n661), .B(n662), .C(n663), .Z(n660) );
notech_ao4 U804 ( .A(\UART_TX/n24 ), .B(n571), .C(n603), .D(INT), .Z(n663)
);
notech_nao3 U805 ( .C(n665), .A(n666), .B(n667), .Z(n603) );
notech_nand3 U806 ( .A(n666), .B(A[1]), .C(A[0]), .Z(n571) );
notech_or2 U808 ( .A(n598), .B(n602), .Z(n662) );
notech_inv U809 ( .A(iMCR[0]), .Z(n602) );
notech_inv U810 ( .A(n652), .Z(n598) );
notech_ao3 U811 ( .A(A[2]), .B(n665), .C(A[0]), .Z(n652) );
notech_ao4 U812 ( .A(n441), .B(n570), .C(n450), .D(n601), .Z(n661) );
notech_inv U813 ( .A(n573), .Z(n601) );
notech_ao3 U814 ( .A(A[2]), .B(A[0]), .C(A[1]), .Z(n573) );
notech_nor2 U815 ( .A(n438), .B(iRXFIFOWrite), .Z(n450) );
notech_inv U816 ( .A(iRXFIFOEmpty), .Z(n438) );
notech_nand3 U817 ( .A(n667), .B(A[1]), .C(A[2]), .Z(n570) );
notech_inv U818 ( .A(iMSR[0]), .Z(n441) );
notech_nao4 U819 ( .A(n668), .B(n627), .C(n669), .D(n581), .Z(n659) );
notech_nao3 U820 ( .C(n667), .A(A[1]), .B(A[2]), .Z(n581) );
notech_inv U821 ( .A(iSCR[0]), .Z(n669) );
notech_or4 U822 ( .A(A[1]), .B(n667), .C(iLCR[7]), .D(A[2]), .Z(n627) );
notech_inv U823 ( .A(iIER[0]), .Z(n668) );
notech_nao4 U824 ( .A(n670), .B(n577), .C(n671), .D(n575), .Z(n658) );
notech_nand2 U825 ( .A(n672), .B(A[0]), .Z(n575) );
notech_inv U826 ( .A(iDLM[0]), .Z(n671) );
notech_nand2 U827 ( .A(n672), .B(n667), .Z(n577) );
notech_inv U828 ( .A(A[0]), .Z(n667) );
notech_and3 U829 ( .A(n665), .B(n666), .C(iLCR[7]), .Z(n672) );
notech_inv U830 ( .A(A[2]), .Z(n666) );
notech_inv U831 ( .A(A[1]), .Z(n665) );
notech_inv U832 ( .A(iDLL[0]), .Z(n670) );
notech_and2 U833 ( .A(iRXFIFOQ[0]), .B(n615), .Z(n657) );
notech_nor4 U834 ( .A(A[1]), .B(A[0]), .C(iLCR[7]), .D(A[2]), .Z(n615) );
notech_inv \UART_ED_WRITE/U6 ( .A(\UART_ED_WRITE/iDd ), .Z(
\UART_ED_WRITE/n1 ) );
notech_nor2 \UART_ED_WRITE/U4 ( .A(\UART_ED_WRITE/n1 ), .B(N48), .Z(
iWriteFE) );
notech_reg \UART_ED_WRITE/iDd_reg ( .D(N48), .CP(CLK), .CD(\UART_IS_DSR/n1 ), .Q(\UART_ED_WRITE/iDd ) );
notech_inv \UART_ED_READ/U6 ( .A(\UART_ED_READ/iDd ), .Z(\UART_ED_READ/n1 )
);
notech_nor2 \UART_ED_READ/U4 ( .A(\UART_ED_READ/n1 ), .B(n678), .Z(iReadFE)
);
notech_reg \UART_ED_READ/iDd_reg ( .D(n678), .CP(CLK), .CD(\UART_IS_DSR/n1 ), .Q(\UART_ED_READ/iDd ) );
notech_inv \UART_IS_SIN/U3 ( .A(RST), .Z(\UART_IS_SIN/n1 ) );
notech_reg \UART_IS_SIN/iD_reg[1] ( .D(\UART_IS_SIN/iD[0] ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(iSINr) );
notech_reg \UART_IS_SIN/iD_reg[0] ( .D(SIN), .CP(CLK), .CD(\UART_IS_SIN/n1 ), .Q(\UART_IS_SIN/iD[0] ) );
notech_inv \UART_IS_CTS/U3 ( .A(RST), .Z(\UART_IS_CTS/n1 ) );
notech_reg \UART_IS_CTS/iD_reg[1] ( .D(\UART_IS_CTS/iD[0] ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(iCTSNs) );
notech_reg \UART_IS_CTS/iD_reg[0] ( .D(CTSN), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_IS_CTS/iD[0] ) );
notech_inv \UART_IS_DSR/U3 ( .A(RST), .Z(\UART_IS_DSR/n1 ) );
notech_reg \UART_IS_DSR/iD_reg[1] ( .D(\UART_IS_DSR/iD[0] ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(iDSRNs) );
notech_reg \UART_IS_DSR/iD_reg[0] ( .D(DSRN), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_IS_DSR/iD[0] ) );
notech_inv \UART_IS_DCD/U3 ( .A(RST), .Z(\UART_IS_DCD/n1 ) );
notech_reg \UART_IS_DCD/iD_reg[1] ( .D(\UART_IS_DCD/iD[0] ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(iDCDNs) );
notech_reg \UART_IS_DCD/iD_reg[0] ( .D(DCDN), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_IS_DCD/iD[0] ) );
notech_inv \UART_IS_RI/U3 ( .A(RST), .Z(\UART_IS_RI/n1 ) );
notech_reg \UART_IS_RI/iD_reg[1] ( .D(\UART_IS_RI/iD[0] ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(iRINs) );
notech_reg \UART_IS_RI/iD_reg[0] ( .D(RIN), .CP(CLK), .CD(\UART_IS_RI/n1 ),
.Q(\UART_IS_RI/iD[0] ) );
notech_mux2 \UART_IF_CTS/U13 ( .A(\UART_IF_CTS/iCount[1] ), .B(iCTSn), .S(
\UART_IF_CTS/iCount[0] ), .Z(\UART_IF_CTS/n16 ) );
notech_and3 \UART_IF_CTS/U12 ( .A(\UART_IF_CTS/iCount[0] ), .B(iCTSNs), .C(
iBaudtick2x), .Z(\UART_IF_CTS/n5 ) );
notech_xor2 \UART_IF_CTS/U10 ( .A(\UART_IF_CTS/iCount[0] ), .B(iCTSNs), .Z(
\UART_IF_CTS/n7 ) );
notech_or2 \UART_IF_CTS/U9 ( .A(\UART_IF_RI/n3 ), .B(\UART_IF_CTS/n7 ), .Z(
\UART_IF_CTS/n6 ) );
notech_mux2 \UART_IF_CTS/U8 ( .A(\UART_IF_CTS/n5 ), .B(\UART_IF_CTS/n6 ),
.S(\UART_IF_CTS/iCount[1] ), .Z(\UART_IF_CTS/n17 ) );
notech_xor2 \UART_IF_CTS/U7 ( .A(\UART_IF_CTS/iCount[1] ), .B(iCTSNs), .Z(
\UART_IF_CTS/n4 ) );
notech_nor2 \UART_IF_CTS/U6 ( .A(\UART_IF_CTS/iCount[0] ), .B(
\UART_IF_CTS/n4 ), .Z(\UART_IF_CTS/n2 ) );
notech_nor2 \UART_IF_CTS/U5 ( .A(\UART_IF_CTS/n2 ), .B(\UART_IF_RI/n3 ),
.Z(\UART_IF_CTS/n1 ) );
notech_xor2 \UART_IF_CTS/U4 ( .A(\UART_IF_CTS/iCount[0] ), .B(
\UART_IF_CTS/n1 ), .Z(\UART_IF_CTS/n18 ) );
notech_inv \UART_IF_CTS/U3 ( .A(RST), .Z(\UART_IF_CTS/n8 ) );
notech_reg \UART_IF_CTS/Q_reg ( .D(\UART_IF_CTS/n16 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(iCTSn) );
notech_reg \UART_IF_CTS/iCount_reg[1] ( .D(\UART_IF_CTS/n17 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_IF_CTS/iCount[1] ) );
notech_reg \UART_IF_CTS/iCount_reg[0] ( .D(\UART_IF_CTS/n18 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_IF_CTS/iCount[0] ) );
notech_mux2 \UART_IF_DSR/U13 ( .A(\UART_IF_DSR/iCount[1] ), .B(iDSRn), .S(
\UART_IF_DSR/iCount[0] ), .Z(\UART_IF_DSR/n11 ) );
notech_and3 \UART_IF_DSR/U12 ( .A(\UART_IF_DSR/iCount[0] ), .B(iDSRNs), .C(
iBaudtick2x), .Z(\UART_IF_DSR/n5 ) );
notech_xor2 \UART_IF_DSR/U10 ( .A(\UART_IF_DSR/iCount[0] ), .B(iDSRNs), .Z(
\UART_IF_DSR/n7 ) );
notech_or2 \UART_IF_DSR/U9 ( .A(\UART_IF_RI/n3 ), .B(\UART_IF_DSR/n7 ), .Z(
\UART_IF_DSR/n6 ) );
notech_mux2 \UART_IF_DSR/U8 ( .A(\UART_IF_DSR/n5 ), .B(\UART_IF_DSR/n6 ),
.S(\UART_IF_DSR/iCount[1] ), .Z(\UART_IF_DSR/n10 ) );
notech_xor2 \UART_IF_DSR/U7 ( .A(\UART_IF_DSR/iCount[1] ), .B(iDSRNs), .Z(
\UART_IF_DSR/n4 ) );
notech_nor2 \UART_IF_DSR/U6 ( .A(\UART_IF_DSR/iCount[0] ), .B(
\UART_IF_DSR/n4 ), .Z(\UART_IF_DSR/n2 ) );
notech_nor2 \UART_IF_DSR/U5 ( .A(\UART_IF_DSR/n2 ), .B(\UART_IF_RI/n3 ),
.Z(\UART_IF_DSR/n1 ) );
notech_xor2 \UART_IF_DSR/U4 ( .A(\UART_IF_DSR/iCount[0] ), .B(
\UART_IF_DSR/n1 ), .Z(\UART_IF_DSR/n9 ) );
notech_inv \UART_IF_DSR/U3 ( .A(RST), .Z(\UART_IF_DSR/n8 ) );
notech_reg \UART_IF_DSR/Q_reg ( .D(\UART_IF_DSR/n11 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(iDSRn) );
notech_reg \UART_IF_DSR/iCount_reg[1] ( .D(\UART_IF_DSR/n10 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_IF_DSR/iCount[1] ) );
notech_reg \UART_IF_DSR/iCount_reg[0] ( .D(\UART_IF_DSR/n9 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_IF_DSR/iCount[0] ) );
notech_mux2 \UART_IF_DCD/U13 ( .A(\UART_IF_DCD/iCount[1] ), .B(iDCDn), .S(
\UART_IF_DCD/iCount[0] ), .Z(\UART_IF_DCD/n11 ) );
notech_and3 \UART_IF_DCD/U12 ( .A(\UART_IF_DCD/iCount[0] ), .B(iDCDNs), .C(
iBaudtick2x), .Z(\UART_IF_DCD/n5 ) );
notech_xor2 \UART_IF_DCD/U10 ( .A(\UART_IF_DCD/iCount[0] ), .B(iDCDNs), .Z(
\UART_IF_DCD/n7 ) );
notech_or2 \UART_IF_DCD/U9 ( .A(\UART_IF_RI/n3 ), .B(\UART_IF_DCD/n7 ), .Z(
\UART_IF_DCD/n6 ) );
notech_mux2 \UART_IF_DCD/U8 ( .A(\UART_IF_DCD/n5 ), .B(\UART_IF_DCD/n6 ),
.S(\UART_IF_DCD/iCount[1] ), .Z(\UART_IF_DCD/n10 ) );
notech_xor2 \UART_IF_DCD/U7 ( .A(\UART_IF_DCD/iCount[1] ), .B(iDCDNs), .Z(
\UART_IF_DCD/n4 ) );
notech_nor2 \UART_IF_DCD/U6 ( .A(\UART_IF_DCD/iCount[0] ), .B(
\UART_IF_DCD/n4 ), .Z(\UART_IF_DCD/n2 ) );
notech_nor2 \UART_IF_DCD/U5 ( .A(\UART_IF_DCD/n2 ), .B(\UART_IF_RI/n3 ),
.Z(\UART_IF_DCD/n1 ) );
notech_xor2 \UART_IF_DCD/U4 ( .A(\UART_IF_DCD/iCount[0] ), .B(
\UART_IF_DCD/n1 ), .Z(\UART_IF_DCD/n9 ) );
notech_reg \UART_IF_DCD/Q_reg ( .D(\UART_IF_DCD/n11 ), .CP(CLK), .CD(n419),
.Q(iDCDn) );
notech_reg \UART_IF_DCD/iCount_reg[1] ( .D(\UART_IF_DCD/n10 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_IF_DCD/iCount[1] ) );
notech_reg \UART_IF_DCD/iCount_reg[0] ( .D(\UART_IF_DCD/n9 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_IF_DCD/iCount[0] ) );
notech_mux2 \UART_IF_RI/U13 ( .A(\UART_IF_RI/iCount[1] ), .B(iRIn), .S(
\UART_IF_RI/iCount[0] ), .Z(\UART_IF_RI/n11 ) );
notech_and3 \UART_IF_RI/U12 ( .A(\UART_IF_RI/iCount[0] ), .B(iRINs), .C(
iBaudtick2x), .Z(\UART_IF_RI/n5 ) );
notech_inv \UART_IF_RI/U11 ( .A(iBaudtick2x), .Z(\UART_IF_RI/n3 ) );
notech_xor2 \UART_IF_RI/U10 ( .A(\UART_IF_RI/iCount[0] ), .B(iRINs), .Z(
\UART_IF_RI/n7 ) );
notech_or2 \UART_IF_RI/U9 ( .A(\UART_IF_RI/n3 ), .B(\UART_IF_RI/n7 ), .Z(
\UART_IF_RI/n6 ) );
notech_mux2 \UART_IF_RI/U8 ( .A(\UART_IF_RI/n5 ), .B(\UART_IF_RI/n6 ), .S(
\UART_IF_RI/iCount[1] ), .Z(\UART_IF_RI/n10 ) );
notech_xor2 \UART_IF_RI/U7 ( .A(\UART_IF_RI/iCount[1] ), .B(iRINs), .Z(
\UART_IF_RI/n4 ) );
notech_nor2 \UART_IF_RI/U6 ( .A(\UART_IF_RI/iCount[0] ), .B(\UART_IF_RI/n4 ), .Z(\UART_IF_RI/n2 ) );
notech_nor2 \UART_IF_RI/U5 ( .A(\UART_IF_RI/n2 ), .B(\UART_IF_RI/n3 ), .Z(
\UART_IF_RI/n1 ) );
notech_xor2 \UART_IF_RI/U4 ( .A(\UART_IF_RI/iCount[0] ), .B(\UART_IF_RI/n1 ), .Z(\UART_IF_RI/n9 ) );
notech_reg \UART_IF_RI/Q_reg ( .D(\UART_IF_RI/n11 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(iRIn) );
notech_reg \UART_IF_RI/iCount_reg[1] ( .D(\UART_IF_RI/n10 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_IF_RI/iCount[1] ) );
notech_reg \UART_IF_RI/iCount_reg[0] ( .D(\UART_IF_RI/n9 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_IF_RI/iCount[0] ) );
notech_nand2 \UART_IIC/U18 ( .A(iTHRInterrupt), .B(iIER[1]), .Z(
\UART_IIC/n5 ) );
notech_and2 \UART_IIC/U16 ( .A(iMSR[0]), .B(n434), .Z(\UART_IIC/n9 ) );
notech_or4 \UART_IIC/U15 ( .A(iMSR[1]), .B(\UART_IIC/n9 ), .C(iMSR[3]), .D(
iMSR[2]), .Z(\UART_IIC/n8 ) );
notech_nand2 \UART_IIC/U14 ( .A(iIER[3]), .B(\UART_IIC/n8 ), .Z(
\UART_IIC/n6 ) );
notech_or4 \UART_IIC/U13 ( .A(iLSR[2]), .B(iLSR[1]), .C(iLSR[4]), .D(
iLSR[3]), .Z(\UART_IIC/n7 ) );
notech_and2 \UART_IIC/U12 ( .A(iIER[2]), .B(\UART_IIC/n7 ), .Z(
\UART_IIC/n1 ) );
notech_nand2 \UART_IIC/U11 ( .A(iIER[0]), .B(iCharTimeout), .Z(
\UART_IIC/n2 ) );
notech_nand2 \UART_IIC/U10 ( .A(N66), .B(iIER[0]), .Z(\UART_IIC/n4 ) );
notech_nao3 \UART_IIC/U9 ( .C(\UART_IIC/n1 ), .A(\UART_IIC/n2 ), .B(
\UART_IIC/n4 ), .Z(\UART_IIC/N21 ) );
notech_ao3 \UART_IIC/U8 ( .A(\UART_IIC/n5 ), .B(\UART_IIC/n6 ), .C(
\UART_IIC/N21 ), .Z(\UART_IIC/N19 ) );
notech_ao3 \UART_IIC/U7 ( .A(\UART_IIC/n4 ), .B(\UART_IIC/n2 ), .C(
\UART_IIC/n5 ), .Z(\UART_IIC/n3 ) );
notech_or2 \UART_IIC/U6 ( .A(\UART_IIC/n3 ), .B(\UART_IIC/n1 ), .Z(
\UART_IIC/N20 ) );
notech_nor2 \UART_IIC/U5 ( .A(\UART_IIC/n1 ), .B(\UART_IIC/n2 ), .Z(
\UART_IIC/N22 ) );
notech_inv \UART_IIC/U3 ( .A(\UART_IIC/IIR[0] ), .Z(INT) );
notech_reg_set \UART_IIC/iIIR_reg[0] ( .D(\UART_IIC/N19 ), .CP(CLK), .SD(
\UART_IS_DSR/n1 ), .Q(\UART_IIC/IIR[0] ) );
notech_reg \UART_IIC/iIIR_reg[1] ( .D(\UART_IIC/N20 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(iIIR[1]) );
notech_reg \UART_IIC/iIIR_reg[2] ( .D(\UART_IIC/N21 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(iIIR[2]) );
notech_reg \UART_IIC/iIIR_reg[3] ( .D(\UART_IIC/N22 ), .CP(CLK), .CD(n420),
.Q(iIIR[3]) );
notech_inv \UART_IIC_THRE_ED/U6 ( .A(\UART_IIC_THRE_ED/iDd ), .Z(
\UART_IIC_THRE_ED/n1 ) );
notech_and2 \UART_IIC_THRE_ED/U5 ( .A(iTXFIFOEmpty), .B(
\UART_IIC_THRE_ED/n1 ), .Z(iLSR_THRERE) );
notech_reg \UART_IIC_THRE_ED/iDd_reg ( .D(iTXFIFOEmpty), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(\UART_IIC_THRE_ED/iDd ) );
notech_inv \UART_PEDET/U6 ( .A(\UART_PEDET/iDd ), .Z(\UART_PEDET/n1 ) );
notech_and2 \UART_PEDET/U5 ( .A(N146), .B(\UART_PEDET/n1 ), .Z(iPERE) );
notech_reg \UART_PEDET/iDd_reg ( .D(N146), .CP(CLK), .CD(\UART_IS_CTS/n1 ),
.Q(\UART_PEDET/iDd ) );
notech_inv \UART_FEDET/U6 ( .A(\UART_FEDET/iDd ), .Z(\UART_FEDET/n1 ) );
notech_and2 \UART_FEDET/U5 ( .A(n675), .B(\UART_FEDET/n1 ), .Z(iFERE) );
notech_reg \UART_FEDET/iDd_reg ( .D(n675), .CP(CLK), .CD(\UART_IS_RI/n1 ),
.Q(\UART_FEDET/iDd ) );
notech_inv \UART_BIDET/U6 ( .A(\UART_BIDET/iDd ), .Z(\UART_BIDET/n1 ) );
notech_and2 \UART_BIDET/U5 ( .A(n674), .B(\UART_BIDET/n1 ), .Z(iBIRE) );
notech_reg \UART_BIDET/iDd_reg ( .D(n674), .CP(CLK), .CD(\UART_IF_CTS/n8 ),
.Q(\UART_BIDET/iDd ) );
notech_inv \UART_ED_CTS/U6 ( .A(\UART_ED_CTS/iDd ), .Z(\UART_ED_CTS/n1 ) );
notech_nor2 \UART_ED_CTS/U4 ( .A(\UART_ED_CTS/n1 ), .B(N154), .Z(iCTSnFE)
);
notech_reg \UART_ED_CTS/iDd_reg ( .D(N154), .CP(CLK), .CD(\UART_IS_RI/n1 ),
.Q(\UART_ED_CTS/iDd ) );
notech_inv \UART_ED_DSR/U6 ( .A(\UART_ED_DSR/iDd ), .Z(\UART_ED_DSR/n1 ) );
notech_nor2 \UART_ED_DSR/U4 ( .A(\UART_ED_DSR/n1 ), .B(N155), .Z(iDSRnFE)
);
notech_reg \UART_ED_DSR/iDd_reg ( .D(N155), .CP(CLK), .CD(\UART_IS_SIN/n1 ),
.Q(\UART_ED_DSR/iDd ) );
notech_inv \UART_ED_RI/U6 ( .A(\UART_ED_RI/iDd ), .Z(\UART_ED_RI/n1 ) );
notech_nor2 \UART_ED_RI/U4 ( .A(\UART_ED_RI/n1 ), .B(N156), .Z(iRInFE) );
notech_reg \UART_ED_RI/iDd_reg ( .D(N156), .CP(CLK), .CD(\UART_IF_DSR/n8 ),
.Q(\UART_ED_RI/iDd ) );
notech_inv \UART_ED_DCD/U6 ( .A(\UART_ED_DCD/iDd ), .Z(\UART_ED_DCD/n1 ) );
notech_nor2 \UART_ED_DCD/U4 ( .A(\UART_ED_DCD/n1 ), .B(N157), .Z(iDCDnFE)
);
notech_reg \UART_ED_DCD/iDd_reg ( .D(N157), .CP(CLK), .CD(\UART_IS_CTS/n1 ),
.Q(\UART_ED_DCD/iDd ) );
notech_xor2 \UART_BG16/U76 ( .A(\UART_BG16/iCounter[4] ), .B(iDLL[4]), .Z(
\UART_BG16/n69 ) );
notech_xor2 \UART_BG16/U75 ( .A(\UART_BG16/iCounter[5] ), .B(iDLL[5]), .Z(
\UART_BG16/n70 ) );
notech_xor2 \UART_BG16/U74 ( .A(\UART_BG16/iCounter[9] ), .B(iDLM[1]), .Z(
\UART_BG16/n71 ) );
notech_xor2 \UART_BG16/U73 ( .A(\UART_BG16/iCounter[10] ), .B(iDLM[2]), .Z(
\UART_BG16/n72 ) );
notech_or4 \UART_BG16/U72 ( .A(\UART_BG16/n69 ), .B(\UART_BG16/n70 ), .C(
\UART_BG16/n71 ), .D(\UART_BG16/n72 ), .Z(\UART_BG16/n37 ) );
notech_xor2 \UART_BG16/U71 ( .A(\UART_BG16/iCounter[1] ), .B(iDLL[1]), .Z(
\UART_BG16/n65 ) );
notech_xor2 \UART_BG16/U70 ( .A(\UART_BG16/iCounter[2] ), .B(iDLL[2]), .Z(
\UART_BG16/n66 ) );
notech_xor2 \UART_BG16/U69 ( .A(\UART_BG16/iCounter[6] ), .B(iDLL[6]), .Z(
\UART_BG16/n67 ) );
notech_xor2 \UART_BG16/U68 ( .A(\UART_BG16/iCounter[0] ), .B(iDLL[0]), .Z(
\UART_BG16/n68 ) );
notech_or4 \UART_BG16/U67 ( .A(\UART_BG16/n65 ), .B(\UART_BG16/n66 ), .C(
\UART_BG16/n67 ), .D(\UART_BG16/n68 ), .Z(\UART_BG16/n38 ) );
notech_xor2 \UART_BG16/U66 ( .A(\UART_BG16/iCounter[3] ), .B(iDLL[3]), .Z(
\UART_BG16/n61 ) );
notech_xor2 \UART_BG16/U65 ( .A(\UART_BG16/iCounter[15] ), .B(iDLM[7]), .Z(
\UART_BG16/n62 ) );
notech_xor2 \UART_BG16/U64 ( .A(\UART_BG16/iCounter[11] ), .B(iDLM[3]), .Z(
\UART_BG16/n63 ) );
notech_xor2 \UART_BG16/U63 ( .A(\UART_BG16/iCounter[7] ), .B(iDLL[7]), .Z(
\UART_BG16/n64 ) );
notech_or4 \UART_BG16/U62 ( .A(\UART_BG16/n61 ), .B(\UART_BG16/n62 ), .C(
\UART_BG16/n63 ), .D(\UART_BG16/n64 ), .Z(\UART_BG16/n39 ) );
notech_xor2 \UART_BG16/U61 ( .A(\UART_BG16/iCounter[14] ), .B(iDLM[6]), .Z(
\UART_BG16/n57 ) );
notech_xor2 \UART_BG16/U60 ( .A(\UART_BG16/iCounter[8] ), .B(iDLM[0]), .Z(
\UART_BG16/n58 ) );
notech_xor2 \UART_BG16/U59 ( .A(\UART_BG16/iCounter[12] ), .B(iDLM[4]), .Z(
\UART_BG16/n59 ) );
notech_xor2 \UART_BG16/U58 ( .A(\UART_BG16/iCounter[13] ), .B(iDLM[5]), .Z(
\UART_BG16/n60 ) );
notech_or4 \UART_BG16/U57 ( .A(\UART_BG16/n57 ), .B(\UART_BG16/n58 ), .C(
\UART_BG16/n59 ), .D(\UART_BG16/n60 ), .Z(\UART_BG16/n56 ) );
notech_nor4 \UART_BG16/U56 ( .A(\UART_BG16/n37 ), .B(\UART_BG16/n38 ), .C(
\UART_BG16/n39 ), .D(\UART_BG16/n56 ), .Z(\UART_BG16/N40 ) );
notech_inv \UART_BG16/U55 ( .A(\UART_BG16/N40 ), .Z(\UART_BG16/n35 ) );
notech_inv \UART_BG16/U53 ( .A(\UART_BG16/N22 ), .Z(\UART_BG16/n32 ) );
notech_inv \UART_BG16/U52 ( .A(\UART_BG16/iCounter[15] ), .Z(
\UART_BG16/n33 ) );
notech_nao4 \UART_BG16/U48 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n32 ), .C(
\UART_BG16/n33 ), .D(n682), .Z(\UART_BG16/n40 ) );
notech_inv \UART_BG16/U47 ( .A(\UART_BG16/N21 ), .Z(\UART_BG16/n30 ) );
notech_inv \UART_BG16/U46 ( .A(\UART_BG16/iCounter[14] ), .Z(
\UART_BG16/n31 ) );
notech_nao4 \UART_BG16/U45 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n30 ), .C(
\UART_BG16/n31 ), .D(n682), .Z(\UART_BG16/n41 ) );
notech_inv \UART_BG16/U44 ( .A(\UART_BG16/N20 ), .Z(\UART_BG16/n28 ) );
notech_inv \UART_BG16/U43 ( .A(\UART_BG16/iCounter[13] ), .Z(
\UART_BG16/n29 ) );
notech_nao4 \UART_BG16/U42 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n28 ), .C(
\UART_BG16/n29 ), .D(n682), .Z(\UART_BG16/n42 ) );
notech_inv \UART_BG16/U41 ( .A(\UART_BG16/N19 ), .Z(\UART_BG16/n26 ) );
notech_inv \UART_BG16/U40 ( .A(\UART_BG16/iCounter[12] ), .Z(
\UART_BG16/n27 ) );
notech_nao4 \UART_BG16/U39 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n26 ), .C(
\UART_BG16/n27 ), .D(n682), .Z(\UART_BG16/n43 ) );
notech_inv \UART_BG16/U38 ( .A(\UART_BG16/N18 ), .Z(\UART_BG16/n24 ) );
notech_inv \UART_BG16/U37 ( .A(\UART_BG16/iCounter[11] ), .Z(
\UART_BG16/n25 ) );
notech_nao4 \UART_BG16/U36 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n24 ), .C(
\UART_BG16/n25 ), .D(n682), .Z(\UART_BG16/n44 ) );
notech_inv \UART_BG16/U35 ( .A(\UART_BG16/N17 ), .Z(\UART_BG16/n22 ) );
notech_inv \UART_BG16/U34 ( .A(\UART_BG16/iCounter[10] ), .Z(
\UART_BG16/n23 ) );
notech_nao4 \UART_BG16/U33 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n22 ), .C(
\UART_BG16/n23 ), .D(n682), .Z(\UART_BG16/n45 ) );
notech_inv \UART_BG16/U32 ( .A(\UART_BG16/N16 ), .Z(\UART_BG16/n20 ) );
notech_inv \UART_BG16/U31 ( .A(\UART_BG16/iCounter[9] ), .Z(\UART_BG16/n21 ) );
notech_nao4 \UART_BG16/U30 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n20 ), .C(
\UART_BG16/n21 ), .D(n682), .Z(\UART_BG16/n46 ) );
notech_inv \UART_BG16/U29 ( .A(\UART_BG16/N15 ), .Z(\UART_BG16/n18 ) );
notech_inv \UART_BG16/U28 ( .A(\UART_BG16/iCounter[8] ), .Z(\UART_BG16/n19 ) );
notech_nao4 \UART_BG16/U27 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n18 ), .C(
\UART_BG16/n19 ), .D(n682), .Z(\UART_BG16/n47 ) );
notech_inv \UART_BG16/U26 ( .A(\UART_BG16/N14 ), .Z(\UART_BG16/n16 ) );
notech_inv \UART_BG16/U25 ( .A(\UART_BG16/iCounter[7] ), .Z(\UART_BG16/n17 ) );
notech_nao4 \UART_BG16/U24 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n16 ), .C(
\UART_BG16/n17 ), .D(n682), .Z(\UART_BG16/n48 ) );
notech_inv \UART_BG16/U23 ( .A(\UART_BG16/N13 ), .Z(\UART_BG16/n14 ) );
notech_inv \UART_BG16/U22 ( .A(\UART_BG16/iCounter[6] ), .Z(\UART_BG16/n15 ) );
notech_nao4 \UART_BG16/U21 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n14 ), .C(
\UART_BG16/n15 ), .D(n682), .Z(\UART_BG16/n49 ) );
notech_inv \UART_BG16/U20 ( .A(\UART_BG16/N12 ), .Z(\UART_BG16/n12 ) );
notech_inv \UART_BG16/U19 ( .A(\UART_BG16/iCounter[5] ), .Z(\UART_BG16/n13 ) );
notech_nao4 \UART_BG16/U18 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n12 ), .C(
\UART_BG16/n13 ), .D(n682), .Z(\UART_BG16/n50 ) );
notech_inv \UART_BG16/U17 ( .A(\UART_BG16/N11 ), .Z(\UART_BG16/n10 ) );
notech_inv \UART_BG16/U16 ( .A(\UART_BG16/iCounter[4] ), .Z(\UART_BG16/n11 ) );
notech_nao4 \UART_BG16/U15 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n10 ), .C(
\UART_BG16/n11 ), .D(n682), .Z(\UART_BG16/n51 ) );
notech_inv \UART_BG16/U14 ( .A(\UART_BG16/N10 ), .Z(\UART_BG16/n8 ) );
notech_inv \UART_BG16/U13 ( .A(\UART_BG16/iCounter[3] ), .Z(\UART_BG16/n9 )
);
notech_nao4 \UART_BG16/U12 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n8 ), .C(
\UART_BG16/n9 ), .D(n682), .Z(\UART_BG16/n52 ) );
notech_inv \UART_BG16/U11 ( .A(\UART_BG16/N9 ), .Z(\UART_BG16/n6 ) );
notech_inv \UART_BG16/U10 ( .A(\UART_BG16/iCounter[2] ), .Z(\UART_BG16/n7 )
);
notech_nao4 \UART_BG16/U9 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n6 ), .C(
\UART_BG16/n7 ), .D(n682), .Z(\UART_BG16/n53 ) );
notech_inv \UART_BG16/U8 ( .A(\UART_BG16/N8 ), .Z(\UART_BG16/n4 ) );
notech_inv \UART_BG16/U7 ( .A(\UART_BG16/iCounter[1] ), .Z(\UART_BG16/n5 )
);
notech_nao4 \UART_BG16/U6 ( .A(\UART_BG16/n2 ), .B(\UART_BG16/n4 ), .C(
\UART_BG16/n5 ), .D(n682), .Z(\UART_BG16/n54 ) );
notech_mux2 \UART_BG16/U5 ( .A(\UART_BG16/n2 ), .B(n682), .S(
\UART_BG16/iCounter[0] ), .Z(\UART_BG16/n1 ) );
notech_inv \UART_BG16/U4 ( .A(\UART_BG16/n1 ), .Z(\UART_BG16/n55 ) );
notech_reg \UART_BG16/iCounter_reg[15] ( .D(\UART_BG16/n40 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_BG16/iCounter[15] ) );
notech_reg \UART_BG16/iCounter_reg[14] ( .D(\UART_BG16/n41 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_BG16/iCounter[14] ) );
notech_reg \UART_BG16/iCounter_reg[13] ( .D(\UART_BG16/n42 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_BG16/iCounter[13] ) );
notech_reg \UART_BG16/iCounter_reg[12] ( .D(\UART_BG16/n43 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_BG16/iCounter[12] ) );
notech_reg \UART_BG16/iCounter_reg[11] ( .D(\UART_BG16/n44 ), .CP(CLK),
.CD(\UART_IS_SIN/n1 ), .Q(\UART_BG16/iCounter[11] ) );
notech_reg \UART_BG16/iCounter_reg[10] ( .D(\UART_BG16/n45 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_BG16/iCounter[10] ) );
notech_reg \UART_BG16/iCounter_reg[9] ( .D(\UART_BG16/n46 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_BG16/iCounter[9] ) );
notech_reg \UART_BG16/iCounter_reg[8] ( .D(\UART_BG16/n47 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_BG16/iCounter[8] ) );
notech_reg \UART_BG16/iCounter_reg[7] ( .D(\UART_BG16/n48 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(\UART_BG16/iCounter[7] ) );
notech_reg \UART_BG16/iCounter_reg[6] ( .D(\UART_BG16/n49 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(\UART_BG16/iCounter[6] ) );
notech_reg \UART_BG16/iCounter_reg[5] ( .D(\UART_BG16/n50 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(\UART_BG16/iCounter[5] ) );
notech_reg \UART_BG16/iCounter_reg[4] ( .D(\UART_BG16/n51 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(\UART_BG16/iCounter[4] ) );
notech_reg \UART_BG16/iCounter_reg[3] ( .D(\UART_BG16/n52 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(\UART_BG16/iCounter[3] ) );
notech_reg \UART_BG16/iCounter_reg[2] ( .D(\UART_BG16/n53 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_BG16/iCounter[2] ) );
notech_reg \UART_BG16/iCounter_reg[1] ( .D(\UART_BG16/n54 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_BG16/iCounter[1] ) );
notech_reg \UART_BG16/BAUDTICK_reg ( .D(\UART_BG16/N40 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(iBaudtick16x) );
notech_reg \UART_BG16/iCounter_reg[0] ( .D(\UART_BG16/n55 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_BG16/iCounter[0] ) );
notech_xor2 \UART_BG16/add_54/U1 ( .A(\UART_BG16/add_54/carry [15]), .B(
\UART_BG16/iCounter[15] ), .Z(\UART_BG16/N22 ) );
notech_ha2 \UART_BG16/add_54/U1_1_1 ( .A(\UART_BG16/iCounter[1] ), .B(
\UART_BG16/iCounter[0] ), .CO(\UART_BG16/add_54/carry [2]), .Z(
\UART_BG16/N8 ) );
notech_ha2 \UART_BG16/add_54/U1_1_2 ( .A(\UART_BG16/iCounter[2] ), .B(
\UART_BG16/add_54/carry [2]), .CO(\UART_BG16/add_54/carry [3]), .Z(
\UART_BG16/N9 ) );
notech_ha2 \UART_BG16/add_54/U1_1_3 ( .A(\UART_BG16/iCounter[3] ), .B(
\UART_BG16/add_54/carry [3]), .CO(\UART_BG16/add_54/carry [4]), .Z(
\UART_BG16/N10 ) );
notech_ha2 \UART_BG16/add_54/U1_1_4 ( .A(\UART_BG16/iCounter[4] ), .B(
\UART_BG16/add_54/carry [4]), .CO(\UART_BG16/add_54/carry [5]), .Z(
\UART_BG16/N11 ) );
notech_ha2 \UART_BG16/add_54/U1_1_5 ( .A(\UART_BG16/iCounter[5] ), .B(
\UART_BG16/add_54/carry [5]), .CO(\UART_BG16/add_54/carry [6]), .Z(
\UART_BG16/N12 ) );
notech_ha2 \UART_BG16/add_54/U1_1_6 ( .A(\UART_BG16/iCounter[6] ), .B(
\UART_BG16/add_54/carry [6]), .CO(\UART_BG16/add_54/carry [7]), .Z(
\UART_BG16/N13 ) );
notech_ha2 \UART_BG16/add_54/U1_1_7 ( .A(\UART_BG16/iCounter[7] ), .B(
\UART_BG16/add_54/carry [7]), .CO(\UART_BG16/add_54/carry [8]), .Z(
\UART_BG16/N14 ) );
notech_ha2 \UART_BG16/add_54/U1_1_8 ( .A(\UART_BG16/iCounter[8] ), .B(
\UART_BG16/add_54/carry [8]), .CO(\UART_BG16/add_54/carry [9]), .Z(
\UART_BG16/N15 ) );
notech_ha2 \UART_BG16/add_54/U1_1_9 ( .A(\UART_BG16/iCounter[9] ), .B(
\UART_BG16/add_54/carry [9]), .CO(\UART_BG16/add_54/carry [10]), .Z(
\UART_BG16/N16 ) );
notech_ha2 \UART_BG16/add_54/U1_1_10 ( .A(\UART_BG16/iCounter[10] ), .B(
\UART_BG16/add_54/carry [10]), .CO(\UART_BG16/add_54/carry [11]), .Z(
\UART_BG16/N17 ) );
notech_ha2 \UART_BG16/add_54/U1_1_11 ( .A(\UART_BG16/iCounter[11] ), .B(
\UART_BG16/add_54/carry [11]), .CO(\UART_BG16/add_54/carry [12]), .Z(
\UART_BG16/N18 ) );
notech_ha2 \UART_BG16/add_54/U1_1_12 ( .A(\UART_BG16/iCounter[12] ), .B(
\UART_BG16/add_54/carry [12]), .CO(\UART_BG16/add_54/carry [13]), .Z(
\UART_BG16/N19 ) );
notech_ha2 \UART_BG16/add_54/U1_1_13 ( .A(\UART_BG16/iCounter[13] ), .B(
\UART_BG16/add_54/carry [13]), .CO(\UART_BG16/add_54/carry [14]), .Z(
\UART_BG16/N20 ) );
notech_ha2 \UART_BG16/add_54/U1_1_14 ( .A(\UART_BG16/iCounter[14] ), .B(
\UART_BG16/add_54/carry [14]), .CO(\UART_BG16/add_54/carry [15]), .Z(
\UART_BG16/N21 ) );
notech_and2 \UART_BG2/U9 ( .A(iBaudtick16x), .B(\UART_BG2/iCounter[0] ),
.Z(\UART_BG2/n1 ) );
notech_and3 \UART_BG2/U8 ( .A(\UART_BG2/n1 ), .B(\UART_BG2/iCounter[1] ),
.C(\UART_BG2/iCounter[2] ), .Z(\UART_BG2/N14 ) );
notech_and2 \UART_BG2/U7 ( .A(\UART_BG2/n1 ), .B(\UART_BG2/iCounter[1] ),
.Z(\UART_BG2/n2 ) );
notech_xor2 \UART_BG2/U6 ( .A(\UART_BG2/iCounter[2] ), .B(\UART_BG2/n2 ),
.Z(\UART_BG2/n3 ) );
notech_xor2 \UART_BG2/U5 ( .A(\UART_BG2/iCounter[1] ), .B(\UART_BG2/n1 ),
.Z(\UART_BG2/n4 ) );
notech_xor2 \UART_BG2/U4 ( .A(\UART_BG2/iCounter[0] ), .B(iBaudtick16x),
.Z(\UART_BG2/n6 ) );
notech_reg \UART_BG2/iQ_reg ( .D(\UART_BG2/N14 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(iBaudtick2x) );
notech_reg \UART_BG2/iCounter_reg[2] ( .D(\UART_BG2/n3 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_BG2/iCounter[2] ) );
notech_reg \UART_BG2/iCounter_reg[1] ( .D(\UART_BG2/n4 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_BG2/iCounter[1] ) );
notech_reg \UART_BG2/iCounter_reg[0] ( .D(\UART_BG2/n6 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_BG2/iCounter[0] ) );
notech_inv \UART_RCLK/U6 ( .A(\UART_RCLK/iDd ), .Z(\UART_RCLK/n1 ) );
notech_and2 \UART_RCLK/U5 ( .A(RCLK), .B(\UART_RCLK/n1 ), .Z(iRCLK) );
notech_reg \UART_RCLK/iDd_reg ( .D(RCLK), .CP(CLK), .CD(\UART_IS_DSR/n1 ),
.Q(\UART_RCLK/iDd ) );
notech_xor2 \UART_TXFF/U926 ( .A(\UART_TXFF/iWRAddr[1] ), .B(
\UART_TXFF/N13 ), .Z(\UART_TXFF/n367 ) );
notech_xor2 \UART_TXFF/U925 ( .A(\UART_TXFF/iWRAddr[5] ), .B(
\UART_TXFF/N17 ), .Z(\UART_TXFF/n368 ) );
notech_xor2 \UART_TXFF/U924 ( .A(\UART_TXFF/iWRAddr[0] ), .B(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n369 ) );
notech_inv \UART_TXFF/U923 ( .A(\UART_TXFF/N14 ), .Z(\UART_TXFF/n232 ) );
notech_xor2 \UART_TXFF/U922 ( .A(\UART_TXFF/n232 ), .B(
\UART_TXFF/iWRAddr[2] ), .Z(\UART_TXFF/n371 ) );
notech_inv \UART_TXFF/U921 ( .A(\UART_TXFF/N15 ), .Z(\UART_TXFF/n234 ) );
notech_xor2 \UART_TXFF/U920 ( .A(\UART_TXFF/n234 ), .B(
\UART_TXFF/iWRAddr[3] ), .Z(\UART_TXFF/n372 ) );
notech_inv \UART_TXFF/U919 ( .A(\UART_TXFF/N16 ), .Z(\UART_TXFF/n236 ) );
notech_xor2 \UART_TXFF/U918 ( .A(\UART_TXFF/n236 ), .B(
\UART_TXFF/iWRAddr[4] ), .Z(\UART_TXFF/n373 ) );
notech_nand3 \UART_TXFF/U917 ( .A(\UART_TXFF/n371 ), .B(\UART_TXFF/n372 ),
.C(\UART_TXFF/n373 ), .Z(\UART_TXFF/n370 ) );
notech_nor4 \UART_TXFF/U916 ( .A(\UART_TXFF/n367 ), .B(\UART_TXFF/n368 ),
.C(\UART_TXFF/n369 ), .D(\UART_TXFF/n370 ), .Z(\UART_TXFF/n364 ) );
notech_inv \UART_TXFF/U915 ( .A(\UART_TXFF/n364 ), .Z(\UART_TXFF/n366 ) );
notech_inv \UART_TXFF/U914 ( .A(\UART_TXFF/iWRAddr[6] ), .Z(
\UART_TXFF/n213 ) );
notech_xor2 \UART_TXFF/U913 ( .A(\UART_TXFF/iRDAddr[6] ), .B(
\UART_TXFF/n213 ), .Z(\UART_TXFF/n365 ) );
notech_nor2 \UART_TXFF/U912 ( .A(\UART_TXFF/n366 ), .B(\UART_TXFF/n365 ),
.Z(iTXFIFO64Full) );
notech_and2 \UART_TXFF/U911 ( .A(\UART_TXFF/n364 ), .B(\UART_TXFF/n365 ),
.Z(\UART_TXFF/N56 ) );
notech_and3 \UART_TXFF/U910 ( .A(\UART_TXFF/USAGE[2] ), .B(
\UART_TXFF/USAGE[0] ), .C(\UART_TXFF/USAGE[1] ), .Z(\UART_TXFF/n346 )
);
notech_inv \UART_TXFF/U909 ( .A(N169), .Z(\UART_TXFF/n363 ) );
notech_nand3 \UART_TXFF/U907 ( .A(\UART_TXFF/n363 ), .B(iTXFIFORead), .C(
n520), .Z(\UART_TXFF/n358 ) );
notech_nor2 \UART_TXFF/U906 ( .A(iTXFIFO64Full), .B(\UART_TXFF/n363 ), .Z(
\UART_TXFF/n287 ) );
notech_or2 \UART_TXFF/U905 ( .A(\UART_TXFF/n287 ), .B(iFCR[2]), .Z(
\UART_TXFF/n214 ) );
notech_inv \UART_TXFF/U904 ( .A(iFCR[2]), .Z(\UART_TXFF/n228 ) );
notech_nand2 \UART_TXFF/U903 ( .A(\UART_TXFF/n228 ), .B(iTXFIFORead), .Z(
\UART_TXFF/n362 ) );
notech_nand2 \UART_TXFF/U902 ( .A(\UART_TXFF/n214 ), .B(\UART_TXFF/n362 ),
.Z(\UART_TXFF/n361 ) );
notech_nand2 \UART_TXFF/U901 ( .A(\UART_TXFF/n361 ), .B(\UART_TXFF/n358 ),
.Z(\UART_TXFF/n328 ) );
notech_ao3 \UART_TXFF/U900 ( .A(\UART_TXFF/n358 ), .B(\UART_TXFF/n328 ),
.C(iFCR[2]), .Z(\UART_TXFF/n334 ) );
notech_and3 \UART_TXFF/U899 ( .A(\UART_TXFF/n346 ), .B(\UART_TXFF/USAGE[3] ), .C(\UART_TXFF/n334 ), .Z(\UART_TXFF/n349 ) );
notech_inv \UART_TXFF/U897 ( .A(\UART_TXFF/USAGE[1] ), .Z(\UART_TXFF/n359 )
);
notech_inv \UART_TXFF/U896 ( .A(\UART_TXFF/USAGE[0] ), .Z(\UART_TXFF/n360 )
);
notech_ao3 \UART_TXFF/U895 ( .A(\UART_TXFF/n359 ), .B(\UART_TXFF/n360 ),
.C(\UART_TXFF/USAGE[2] ), .Z(\UART_TXFF/n337 ) );
notech_or2 \UART_TXFF/U894 ( .A(\UART_TXFF/n358 ), .B(iFCR[2]), .Z(
\UART_TXFF/n330 ) );
notech_inv \UART_TXFF/U893 ( .A(\UART_TXFF/n330 ), .Z(\UART_TXFF/n333 ) );
notech_nao3 \UART_TXFF/U892 ( .C(\UART_TXFF/USAGE[3] ), .A(\UART_TXFF/n337 ), .B(\UART_TXFF/n333 ), .Z(\UART_TXFF/n343 ) );
notech_nor2 \UART_TXFF/U891 ( .A(\UART_TXFF/n343 ), .B(\iTXFIFOUsage[4] ),
.Z(\UART_TXFF/n348 ) );
notech_or2 \UART_TXFF/U889 ( .A(\UART_TXFF/n330 ), .B(\UART_TXFF/n337 ),
.Z(\UART_TXFF/n355 ) );
notech_inv \UART_TXFF/U888 ( .A(\UART_TXFF/n334 ), .Z(\UART_TXFF/n329 ) );
notech_or2 \UART_TXFF/U887 ( .A(\UART_TXFF/n329 ), .B(\UART_TXFF/n346 ),
.Z(\UART_TXFF/n356 ) );
notech_and3 \UART_TXFF/U886 ( .A(\UART_TXFF/n355 ), .B(\UART_TXFF/n356 ),
.C(\UART_TXFF/n328 ), .Z(\UART_TXFF/n345 ) );
notech_mux2 \UART_TXFF/U885 ( .A(\UART_TXFF/n329 ), .B(\UART_TXFF/n330 ),
.S(\UART_TXFF/USAGE[3] ), .Z(\UART_TXFF/n354 ) );
notech_nand2 \UART_TXFF/U884 ( .A(\UART_TXFF/n345 ), .B(\UART_TXFF/n354 ),
.Z(\UART_TXFF/n350 ) );
notech_mux2 \UART_TXFF/U880 ( .A(\UART_TXFF/n349 ), .B(\UART_TXFF/n350 ),
.S(\iTXFIFOUsage[4] ), .Z(\UART_TXFF/n347 ) );
notech_or2 \UART_TXFF/U879 ( .A(\UART_TXFF/n347 ), .B(\UART_TXFF/n348 ),
.Z(\UART_TXFF/n1287 ) );
notech_nand2 \UART_TXFF/U878 ( .A(\UART_TXFF/n334 ), .B(\UART_TXFF/n346 ),
.Z(\UART_TXFF/n344 ) );
notech_mux2 \UART_TXFF/U877 ( .A(\UART_TXFF/n344 ), .B(\UART_TXFF/n345 ),
.S(\UART_TXFF/USAGE[3] ), .Z(\UART_TXFF/n342 ) );
notech_nand2 \UART_TXFF/U876 ( .A(\UART_TXFF/n342 ), .B(\UART_TXFF/n343 ),
.Z(\UART_TXFF/n1288 ) );
notech_nand3 \UART_TXFF/U875 ( .A(\UART_TXFF/n334 ), .B(
\UART_TXFF/USAGE[0] ), .C(\UART_TXFF/USAGE[1] ), .Z(\UART_TXFF/n338 )
);
notech_mux2 \UART_TXFF/U874 ( .A(\UART_TXFF/n329 ), .B(\UART_TXFF/n330 ),
.S(\UART_TXFF/USAGE[0] ), .Z(\UART_TXFF/n341 ) );
notech_nand2 \UART_TXFF/U873 ( .A(\UART_TXFF/n341 ), .B(\UART_TXFF/n328 ),
.Z(\UART_TXFF/n332 ) );
notech_mux2 \UART_TXFF/U872 ( .A(\UART_TXFF/n334 ), .B(\UART_TXFF/n333 ),
.S(\UART_TXFF/USAGE[1] ), .Z(\UART_TXFF/n340 ) );
notech_nor2 \UART_TXFF/U871 ( .A(\UART_TXFF/n332 ), .B(\UART_TXFF/n340 ),
.Z(\UART_TXFF/n339 ) );
notech_mux2 \UART_TXFF/U870 ( .A(\UART_TXFF/n338 ), .B(\UART_TXFF/n339 ),
.S(\UART_TXFF/USAGE[2] ), .Z(\UART_TXFF/n335 ) );
notech_nand2 \UART_TXFF/U869 ( .A(\UART_TXFF/n333 ), .B(\UART_TXFF/n337 ),
.Z(\UART_TXFF/n336 ) );
notech_nand2 \UART_TXFF/U868 ( .A(\UART_TXFF/n335 ), .B(\UART_TXFF/n336 ),
.Z(\UART_TXFF/n1289 ) );
notech_mux2 \UART_TXFF/U867 ( .A(\UART_TXFF/n333 ), .B(\UART_TXFF/n334 ),
.S(\UART_TXFF/USAGE[0] ), .Z(\UART_TXFF/n331 ) );
notech_mux2 \UART_TXFF/U866 ( .A(\UART_TXFF/n331 ), .B(\UART_TXFF/n332 ),
.S(\UART_TXFF/USAGE[1] ), .Z(\UART_TXFF/n1290 ) );
notech_nand2 \UART_TXFF/U865 ( .A(\UART_TXFF/n329 ), .B(\UART_TXFF/n330 ),
.Z(\UART_TXFF/n326 ) );
notech_inv \UART_TXFF/U864 ( .A(\UART_TXFF/n328 ), .Z(\UART_TXFF/n327 ) );
notech_mux2 \UART_TXFF/U863 ( .A(\UART_TXFF/n326 ), .B(\UART_TXFF/n327 ),
.S(\UART_TXFF/USAGE[0] ), .Z(\UART_TXFF/n1291 ) );
notech_inv \UART_TXFF/U862 ( .A(\UART_TXFF/iWRAddr[3] ), .Z(
\UART_TXFF/n222 ) );
notech_ao3 \UART_TXFF/U860 ( .A(\UART_IF_CTS/n8 ), .B(\UART_TXFF/n287 ),
.C(\UART_TXFF/iWRAddr[5] ), .Z(\UART_TXFF/n297 ) );
notech_ao3 \UART_TXFF/U859 ( .A(\UART_TXFF/n222 ), .B(\UART_TXFF/n297 ),
.C(\UART_TXFF/iWRAddr[4] ), .Z(\UART_TXFF/n317 ) );
notech_inv \UART_TXFF/U858 ( .A(\UART_TXFF/iWRAddr[0] ), .Z(
\UART_TXFF/n319 ) );
notech_inv \UART_TXFF/U857 ( .A(\UART_TXFF/iWRAddr[2] ), .Z(
\UART_TXFF/n220 ) );
notech_inv \UART_TXFF/U856 ( .A(\UART_TXFF/iWRAddr[1] ), .Z(
\UART_TXFF/n218 ) );
notech_and3 \UART_TXFF/U855 ( .A(\UART_TXFF/n319 ), .B(\UART_TXFF/n220 ),
.C(\UART_TXFF/n218 ), .Z(\UART_TXFF/n258 ) );
notech_and2 \UART_TXFF/U854 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n325 ) );
notech_mux2 \UART_TXFF/U853 ( .A(\UART_TXFF/iFIFOMem[0][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1292 ) );
notech_mux2 \UART_TXFF/U852 ( .A(\UART_TXFF/iFIFOMem[0][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1293 ) );
notech_mux2 \UART_TXFF/U851 ( .A(\UART_TXFF/iFIFOMem[0][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1294 ) );
notech_mux2 \UART_TXFF/U850 ( .A(\UART_TXFF/iFIFOMem[0][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1295 ) );
notech_mux2 \UART_TXFF/U849 ( .A(\UART_TXFF/iFIFOMem[0][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1296 ) );
notech_mux2 \UART_TXFF/U848 ( .A(\UART_TXFF/iFIFOMem[0][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1297 ) );
notech_mux2 \UART_TXFF/U847 ( .A(\UART_TXFF/iFIFOMem[0][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1298 ) );
notech_mux2 \UART_TXFF/U846 ( .A(\UART_TXFF/iFIFOMem[0][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n325 ), .Z(\UART_TXFF/n1299 ) );
notech_and3 \UART_TXFF/U845 ( .A(\UART_TXFF/iWRAddr[0] ), .B(
\UART_TXFF/n220 ), .C(\UART_TXFF/n218 ), .Z(\UART_TXFF/n256 ) );
notech_and2 \UART_TXFF/U844 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n324 ) );
notech_mux2 \UART_TXFF/U843 ( .A(\UART_TXFF/iFIFOMem[1][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1300 ) );
notech_mux2 \UART_TXFF/U842 ( .A(\UART_TXFF/iFIFOMem[1][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1301 ) );
notech_mux2 \UART_TXFF/U841 ( .A(\UART_TXFF/iFIFOMem[1][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1302 ) );
notech_mux2 \UART_TXFF/U840 ( .A(\UART_TXFF/iFIFOMem[1][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1303 ) );
notech_mux2 \UART_TXFF/U839 ( .A(\UART_TXFF/iFIFOMem[1][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1304 ) );
notech_mux2 \UART_TXFF/U838 ( .A(\UART_TXFF/iFIFOMem[1][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1305 ) );
notech_mux2 \UART_TXFF/U837 ( .A(\UART_TXFF/iFIFOMem[1][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1306 ) );
notech_mux2 \UART_TXFF/U836 ( .A(\UART_TXFF/iFIFOMem[1][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n324 ), .Z(\UART_TXFF/n1307 ) );
notech_and3 \UART_TXFF/U835 ( .A(\UART_TXFF/iWRAddr[1] ), .B(
\UART_TXFF/n220 ), .C(\UART_TXFF/n319 ), .Z(\UART_TXFF/n254 ) );
notech_and2 \UART_TXFF/U834 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n323 ) );
notech_mux2 \UART_TXFF/U833 ( .A(\UART_TXFF/iFIFOMem[2][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1308 ) );
notech_mux2 \UART_TXFF/U832 ( .A(\UART_TXFF/iFIFOMem[2][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1309 ) );
notech_mux2 \UART_TXFF/U831 ( .A(\UART_TXFF/iFIFOMem[2][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1310 ) );
notech_mux2 \UART_TXFF/U830 ( .A(\UART_TXFF/iFIFOMem[2][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1311 ) );
notech_mux2 \UART_TXFF/U829 ( .A(\UART_TXFF/iFIFOMem[2][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1312 ) );
notech_mux2 \UART_TXFF/U828 ( .A(\UART_TXFF/iFIFOMem[2][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1313 ) );
notech_mux2 \UART_TXFF/U827 ( .A(\UART_TXFF/iFIFOMem[2][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1314 ) );
notech_mux2 \UART_TXFF/U826 ( .A(\UART_TXFF/iFIFOMem[2][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n323 ), .Z(\UART_TXFF/n1315 ) );
notech_and3 \UART_TXFF/U825 ( .A(\UART_TXFF/iWRAddr[0] ), .B(
\UART_TXFF/iWRAddr[1] ), .C(\UART_TXFF/n220 ), .Z(\UART_TXFF/n252 ) );
notech_and2 \UART_TXFF/U824 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n322 ) );
notech_mux2 \UART_TXFF/U823 ( .A(\UART_TXFF/iFIFOMem[3][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1316 ) );
notech_mux2 \UART_TXFF/U822 ( .A(\UART_TXFF/iFIFOMem[3][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1317 ) );
notech_mux2 \UART_TXFF/U821 ( .A(\UART_TXFF/iFIFOMem[3][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1318 ) );
notech_mux2 \UART_TXFF/U820 ( .A(\UART_TXFF/iFIFOMem[3][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1319 ) );
notech_mux2 \UART_TXFF/U819 ( .A(\UART_TXFF/iFIFOMem[3][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1320 ) );
notech_mux2 \UART_TXFF/U818 ( .A(\UART_TXFF/iFIFOMem[3][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1321 ) );
notech_mux2 \UART_TXFF/U817 ( .A(\UART_TXFF/iFIFOMem[3][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1322 ) );
notech_mux2 \UART_TXFF/U816 ( .A(\UART_TXFF/iFIFOMem[3][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n322 ), .Z(\UART_TXFF/n1323 ) );
notech_and3 \UART_TXFF/U815 ( .A(\UART_TXFF/iWRAddr[2] ), .B(
\UART_TXFF/n218 ), .C(\UART_TXFF/n319 ), .Z(\UART_TXFF/n250 ) );
notech_and2 \UART_TXFF/U814 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n321 ) );
notech_mux2 \UART_TXFF/U813 ( .A(\UART_TXFF/iFIFOMem[4][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1324 ) );
notech_mux2 \UART_TXFF/U812 ( .A(\UART_TXFF/iFIFOMem[4][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1325 ) );
notech_mux2 \UART_TXFF/U811 ( .A(\UART_TXFF/iFIFOMem[4][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1326 ) );
notech_mux2 \UART_TXFF/U810 ( .A(\UART_TXFF/iFIFOMem[4][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1327 ) );
notech_mux2 \UART_TXFF/U809 ( .A(\UART_TXFF/iFIFOMem[4][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1328 ) );
notech_mux2 \UART_TXFF/U808 ( .A(\UART_TXFF/iFIFOMem[4][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1329 ) );
notech_mux2 \UART_TXFF/U807 ( .A(\UART_TXFF/iFIFOMem[4][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1330 ) );
notech_mux2 \UART_TXFF/U806 ( .A(\UART_TXFF/iFIFOMem[4][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n321 ), .Z(\UART_TXFF/n1331 ) );
notech_and3 \UART_TXFF/U805 ( .A(\UART_TXFF/iWRAddr[0] ), .B(
\UART_TXFF/iWRAddr[2] ), .C(\UART_TXFF/n218 ), .Z(\UART_TXFF/n248 ) );
notech_and2 \UART_TXFF/U804 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n320 ) );
notech_mux2 \UART_TXFF/U803 ( .A(\UART_TXFF/iFIFOMem[5][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1332 ) );
notech_mux2 \UART_TXFF/U802 ( .A(\UART_TXFF/iFIFOMem[5][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1333 ) );
notech_mux2 \UART_TXFF/U801 ( .A(\UART_TXFF/iFIFOMem[5][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1334 ) );
notech_mux2 \UART_TXFF/U800 ( .A(\UART_TXFF/iFIFOMem[5][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1335 ) );
notech_mux2 \UART_TXFF/U799 ( .A(\UART_TXFF/iFIFOMem[5][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1336 ) );
notech_mux2 \UART_TXFF/U798 ( .A(\UART_TXFF/iFIFOMem[5][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1337 ) );
notech_mux2 \UART_TXFF/U797 ( .A(\UART_TXFF/iFIFOMem[5][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1338 ) );
notech_mux2 \UART_TXFF/U796 ( .A(\UART_TXFF/iFIFOMem[5][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n320 ), .Z(\UART_TXFF/n1339 ) );
notech_and3 \UART_TXFF/U795 ( .A(\UART_TXFF/iWRAddr[1] ), .B(
\UART_TXFF/iWRAddr[2] ), .C(\UART_TXFF/n319 ), .Z(\UART_TXFF/n246 ) );
notech_and2 \UART_TXFF/U794 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n318 ) );
notech_mux2 \UART_TXFF/U793 ( .A(\UART_TXFF/iFIFOMem[6][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1340 ) );
notech_mux2 \UART_TXFF/U792 ( .A(\UART_TXFF/iFIFOMem[6][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1341 ) );
notech_mux2 \UART_TXFF/U791 ( .A(\UART_TXFF/iFIFOMem[6][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1342 ) );
notech_mux2 \UART_TXFF/U790 ( .A(\UART_TXFF/iFIFOMem[6][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1343 ) );
notech_mux2 \UART_TXFF/U789 ( .A(\UART_TXFF/iFIFOMem[6][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1344 ) );
notech_mux2 \UART_TXFF/U788 ( .A(\UART_TXFF/iFIFOMem[6][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1345 ) );
notech_mux2 \UART_TXFF/U787 ( .A(\UART_TXFF/iFIFOMem[6][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1346 ) );
notech_mux2 \UART_TXFF/U786 ( .A(\UART_TXFF/iFIFOMem[6][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n318 ), .Z(\UART_TXFF/n1347 ) );
notech_and3 \UART_TXFF/U785 ( .A(\UART_TXFF/iWRAddr[0] ), .B(
\UART_TXFF/iWRAddr[2] ), .C(\UART_TXFF/iWRAddr[1] ), .Z(
\UART_TXFF/n244 ) );
notech_and2 \UART_TXFF/U784 ( .A(\UART_TXFF/n317 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n316 ) );
notech_mux2 \UART_TXFF/U783 ( .A(\UART_TXFF/iFIFOMem[7][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1348 ) );
notech_mux2 \UART_TXFF/U782 ( .A(\UART_TXFF/iFIFOMem[7][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1349 ) );
notech_mux2 \UART_TXFF/U781 ( .A(\UART_TXFF/iFIFOMem[7][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1350 ) );
notech_mux2 \UART_TXFF/U780 ( .A(\UART_TXFF/iFIFOMem[7][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1351 ) );
notech_mux2 \UART_TXFF/U779 ( .A(\UART_TXFF/iFIFOMem[7][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1352 ) );
notech_mux2 \UART_TXFF/U778 ( .A(\UART_TXFF/iFIFOMem[7][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1353 ) );
notech_mux2 \UART_TXFF/U777 ( .A(\UART_TXFF/iFIFOMem[7][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1354 ) );
notech_mux2 \UART_TXFF/U776 ( .A(\UART_TXFF/iFIFOMem[7][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n316 ), .Z(\UART_TXFF/n1355 ) );
notech_ao3 \UART_TXFF/U775 ( .A(\UART_TXFF/iWRAddr[3] ), .B(
\UART_TXFF/n297 ), .C(\UART_TXFF/iWRAddr[4] ), .Z(\UART_TXFF/n308 ) );
notech_and2 \UART_TXFF/U774 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n315 ) );
notech_mux2 \UART_TXFF/U773 ( .A(\UART_TXFF/iFIFOMem[8][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1356 ) );
notech_mux2 \UART_TXFF/U772 ( .A(\UART_TXFF/iFIFOMem[8][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1357 ) );
notech_mux2 \UART_TXFF/U771 ( .A(\UART_TXFF/iFIFOMem[8][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1358 ) );
notech_mux2 \UART_TXFF/U770 ( .A(\UART_TXFF/iFIFOMem[8][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1359 ) );
notech_mux2 \UART_TXFF/U769 ( .A(\UART_TXFF/iFIFOMem[8][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1360 ) );
notech_mux2 \UART_TXFF/U768 ( .A(\UART_TXFF/iFIFOMem[8][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1361 ) );
notech_mux2 \UART_TXFF/U767 ( .A(\UART_TXFF/iFIFOMem[8][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1362 ) );
notech_mux2 \UART_TXFF/U766 ( .A(\UART_TXFF/iFIFOMem[8][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n315 ), .Z(\UART_TXFF/n1363 ) );
notech_and2 \UART_TXFF/U765 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n314 ) );
notech_mux2 \UART_TXFF/U764 ( .A(\UART_TXFF/iFIFOMem[9][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1364 ) );
notech_mux2 \UART_TXFF/U763 ( .A(\UART_TXFF/iFIFOMem[9][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1365 ) );
notech_mux2 \UART_TXFF/U762 ( .A(\UART_TXFF/iFIFOMem[9][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1366 ) );
notech_mux2 \UART_TXFF/U761 ( .A(\UART_TXFF/iFIFOMem[9][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1367 ) );
notech_mux2 \UART_TXFF/U760 ( .A(\UART_TXFF/iFIFOMem[9][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1368 ) );
notech_mux2 \UART_TXFF/U759 ( .A(\UART_TXFF/iFIFOMem[9][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1369 ) );
notech_mux2 \UART_TXFF/U758 ( .A(\UART_TXFF/iFIFOMem[9][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1370 ) );
notech_mux2 \UART_TXFF/U757 ( .A(\UART_TXFF/iFIFOMem[9][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n314 ), .Z(\UART_TXFF/n1371 ) );
notech_and2 \UART_TXFF/U756 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n313 ) );
notech_mux2 \UART_TXFF/U755 ( .A(\UART_TXFF/iFIFOMem[10][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1372 ) );
notech_mux2 \UART_TXFF/U754 ( .A(\UART_TXFF/iFIFOMem[10][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1373 ) );
notech_mux2 \UART_TXFF/U753 ( .A(\UART_TXFF/iFIFOMem[10][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1374 ) );
notech_mux2 \UART_TXFF/U752 ( .A(\UART_TXFF/iFIFOMem[10][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1375 ) );
notech_mux2 \UART_TXFF/U751 ( .A(\UART_TXFF/iFIFOMem[10][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1376 ) );
notech_mux2 \UART_TXFF/U750 ( .A(\UART_TXFF/iFIFOMem[10][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1377 ) );
notech_mux2 \UART_TXFF/U749 ( .A(\UART_TXFF/iFIFOMem[10][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1378 ) );
notech_mux2 \UART_TXFF/U748 ( .A(\UART_TXFF/iFIFOMem[10][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n313 ), .Z(\UART_TXFF/n1379 ) );
notech_and2 \UART_TXFF/U747 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n312 ) );
notech_mux2 \UART_TXFF/U746 ( .A(\UART_TXFF/iFIFOMem[11][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1380 ) );
notech_mux2 \UART_TXFF/U745 ( .A(\UART_TXFF/iFIFOMem[11][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1381 ) );
notech_mux2 \UART_TXFF/U744 ( .A(\UART_TXFF/iFIFOMem[11][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1382 ) );
notech_mux2 \UART_TXFF/U743 ( .A(\UART_TXFF/iFIFOMem[11][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1383 ) );
notech_mux2 \UART_TXFF/U742 ( .A(\UART_TXFF/iFIFOMem[11][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1384 ) );
notech_mux2 \UART_TXFF/U741 ( .A(\UART_TXFF/iFIFOMem[11][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1385 ) );
notech_mux2 \UART_TXFF/U740 ( .A(\UART_TXFF/iFIFOMem[11][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1386 ) );
notech_mux2 \UART_TXFF/U739 ( .A(\UART_TXFF/iFIFOMem[11][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n312 ), .Z(\UART_TXFF/n1387 ) );
notech_and2 \UART_TXFF/U738 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n311 ) );
notech_mux2 \UART_TXFF/U737 ( .A(\UART_TXFF/iFIFOMem[12][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1388 ) );
notech_mux2 \UART_TXFF/U736 ( .A(\UART_TXFF/iFIFOMem[12][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1389 ) );
notech_mux2 \UART_TXFF/U735 ( .A(\UART_TXFF/iFIFOMem[12][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1390 ) );
notech_mux2 \UART_TXFF/U734 ( .A(\UART_TXFF/iFIFOMem[12][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1391 ) );
notech_mux2 \UART_TXFF/U733 ( .A(\UART_TXFF/iFIFOMem[12][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1392 ) );
notech_mux2 \UART_TXFF/U732 ( .A(\UART_TXFF/iFIFOMem[12][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1393 ) );
notech_mux2 \UART_TXFF/U731 ( .A(\UART_TXFF/iFIFOMem[12][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1394 ) );
notech_mux2 \UART_TXFF/U730 ( .A(\UART_TXFF/iFIFOMem[12][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n311 ), .Z(\UART_TXFF/n1395 ) );
notech_and2 \UART_TXFF/U729 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n310 ) );
notech_mux2 \UART_TXFF/U728 ( .A(\UART_TXFF/iFIFOMem[13][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1396 ) );
notech_mux2 \UART_TXFF/U727 ( .A(\UART_TXFF/iFIFOMem[13][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1397 ) );
notech_mux2 \UART_TXFF/U726 ( .A(\UART_TXFF/iFIFOMem[13][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1398 ) );
notech_mux2 \UART_TXFF/U725 ( .A(\UART_TXFF/iFIFOMem[13][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1399 ) );
notech_mux2 \UART_TXFF/U724 ( .A(\UART_TXFF/iFIFOMem[13][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1400 ) );
notech_mux2 \UART_TXFF/U723 ( .A(\UART_TXFF/iFIFOMem[13][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1401 ) );
notech_mux2 \UART_TXFF/U722 ( .A(\UART_TXFF/iFIFOMem[13][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1402 ) );
notech_mux2 \UART_TXFF/U721 ( .A(\UART_TXFF/iFIFOMem[13][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n310 ), .Z(\UART_TXFF/n1403 ) );
notech_and2 \UART_TXFF/U720 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n309 ) );
notech_mux2 \UART_TXFF/U719 ( .A(\UART_TXFF/iFIFOMem[14][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1404 ) );
notech_mux2 \UART_TXFF/U718 ( .A(\UART_TXFF/iFIFOMem[14][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1405 ) );
notech_mux2 \UART_TXFF/U717 ( .A(\UART_TXFF/iFIFOMem[14][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1406 ) );
notech_mux2 \UART_TXFF/U716 ( .A(\UART_TXFF/iFIFOMem[14][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1407 ) );
notech_mux2 \UART_TXFF/U715 ( .A(\UART_TXFF/iFIFOMem[14][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1408 ) );
notech_mux2 \UART_TXFF/U714 ( .A(\UART_TXFF/iFIFOMem[14][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1409 ) );
notech_mux2 \UART_TXFF/U713 ( .A(\UART_TXFF/iFIFOMem[14][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1410 ) );
notech_mux2 \UART_TXFF/U712 ( .A(\UART_TXFF/iFIFOMem[14][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n309 ), .Z(\UART_TXFF/n1411 ) );
notech_and2 \UART_TXFF/U711 ( .A(\UART_TXFF/n308 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n307 ) );
notech_mux2 \UART_TXFF/U710 ( .A(\UART_TXFF/iFIFOMem[15][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1412 ) );
notech_mux2 \UART_TXFF/U709 ( .A(\UART_TXFF/iFIFOMem[15][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1413 ) );
notech_mux2 \UART_TXFF/U708 ( .A(\UART_TXFF/iFIFOMem[15][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1414 ) );
notech_mux2 \UART_TXFF/U707 ( .A(\UART_TXFF/iFIFOMem[15][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1415 ) );
notech_mux2 \UART_TXFF/U706 ( .A(\UART_TXFF/iFIFOMem[15][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1416 ) );
notech_mux2 \UART_TXFF/U705 ( .A(\UART_TXFF/iFIFOMem[15][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1417 ) );
notech_mux2 \UART_TXFF/U704 ( .A(\UART_TXFF/iFIFOMem[15][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1418 ) );
notech_mux2 \UART_TXFF/U703 ( .A(\UART_TXFF/iFIFOMem[15][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n307 ), .Z(\UART_TXFF/n1419 ) );
notech_ao3 \UART_TXFF/U702 ( .A(\UART_TXFF/iWRAddr[4] ), .B(
\UART_TXFF/n297 ), .C(\UART_TXFF/iWRAddr[3] ), .Z(\UART_TXFF/n299 ) );
notech_and2 \UART_TXFF/U701 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n306 ) );
notech_mux2 \UART_TXFF/U700 ( .A(\UART_TXFF/iFIFOMem[16][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1420 ) );
notech_mux2 \UART_TXFF/U699 ( .A(\UART_TXFF/iFIFOMem[16][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1421 ) );
notech_mux2 \UART_TXFF/U698 ( .A(\UART_TXFF/iFIFOMem[16][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1422 ) );
notech_mux2 \UART_TXFF/U697 ( .A(\UART_TXFF/iFIFOMem[16][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1423 ) );
notech_mux2 \UART_TXFF/U696 ( .A(\UART_TXFF/iFIFOMem[16][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1424 ) );
notech_mux2 \UART_TXFF/U695 ( .A(\UART_TXFF/iFIFOMem[16][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1425 ) );
notech_mux2 \UART_TXFF/U694 ( .A(\UART_TXFF/iFIFOMem[16][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1426 ) );
notech_mux2 \UART_TXFF/U693 ( .A(\UART_TXFF/iFIFOMem[16][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n306 ), .Z(\UART_TXFF/n1427 ) );
notech_and2 \UART_TXFF/U692 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n305 ) );
notech_mux2 \UART_TXFF/U691 ( .A(\UART_TXFF/iFIFOMem[17][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1428 ) );
notech_mux2 \UART_TXFF/U690 ( .A(\UART_TXFF/iFIFOMem[17][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1429 ) );
notech_mux2 \UART_TXFF/U689 ( .A(\UART_TXFF/iFIFOMem[17][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1430 ) );
notech_mux2 \UART_TXFF/U688 ( .A(\UART_TXFF/iFIFOMem[17][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1431 ) );
notech_mux2 \UART_TXFF/U687 ( .A(\UART_TXFF/iFIFOMem[17][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1432 ) );
notech_mux2 \UART_TXFF/U686 ( .A(\UART_TXFF/iFIFOMem[17][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1433 ) );
notech_mux2 \UART_TXFF/U685 ( .A(\UART_TXFF/iFIFOMem[17][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1434 ) );
notech_mux2 \UART_TXFF/U684 ( .A(\UART_TXFF/iFIFOMem[17][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n305 ), .Z(\UART_TXFF/n1435 ) );
notech_and2 \UART_TXFF/U683 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n304 ) );
notech_mux2 \UART_TXFF/U682 ( .A(\UART_TXFF/iFIFOMem[18][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1436 ) );
notech_mux2 \UART_TXFF/U681 ( .A(\UART_TXFF/iFIFOMem[18][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1437 ) );
notech_mux2 \UART_TXFF/U680 ( .A(\UART_TXFF/iFIFOMem[18][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1438 ) );
notech_mux2 \UART_TXFF/U679 ( .A(\UART_TXFF/iFIFOMem[18][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1439 ) );
notech_mux2 \UART_TXFF/U678 ( .A(\UART_TXFF/iFIFOMem[18][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1440 ) );
notech_mux2 \UART_TXFF/U677 ( .A(\UART_TXFF/iFIFOMem[18][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1441 ) );
notech_mux2 \UART_TXFF/U676 ( .A(\UART_TXFF/iFIFOMem[18][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1442 ) );
notech_mux2 \UART_TXFF/U675 ( .A(\UART_TXFF/iFIFOMem[18][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n304 ), .Z(\UART_TXFF/n1443 ) );
notech_and2 \UART_TXFF/U674 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n303 ) );
notech_mux2 \UART_TXFF/U673 ( .A(\UART_TXFF/iFIFOMem[19][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1444 ) );
notech_mux2 \UART_TXFF/U672 ( .A(\UART_TXFF/iFIFOMem[19][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1445 ) );
notech_mux2 \UART_TXFF/U671 ( .A(\UART_TXFF/iFIFOMem[19][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1446 ) );
notech_mux2 \UART_TXFF/U670 ( .A(\UART_TXFF/iFIFOMem[19][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1447 ) );
notech_mux2 \UART_TXFF/U669 ( .A(\UART_TXFF/iFIFOMem[19][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1448 ) );
notech_mux2 \UART_TXFF/U668 ( .A(\UART_TXFF/iFIFOMem[19][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1449 ) );
notech_mux2 \UART_TXFF/U667 ( .A(\UART_TXFF/iFIFOMem[19][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1450 ) );
notech_mux2 \UART_TXFF/U666 ( .A(\UART_TXFF/iFIFOMem[19][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n303 ), .Z(\UART_TXFF/n1451 ) );
notech_and2 \UART_TXFF/U665 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n302 ) );
notech_mux2 \UART_TXFF/U664 ( .A(\UART_TXFF/iFIFOMem[20][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1452 ) );
notech_mux2 \UART_TXFF/U663 ( .A(\UART_TXFF/iFIFOMem[20][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1453 ) );
notech_mux2 \UART_TXFF/U662 ( .A(\UART_TXFF/iFIFOMem[20][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1454 ) );
notech_mux2 \UART_TXFF/U661 ( .A(\UART_TXFF/iFIFOMem[20][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1455 ) );
notech_mux2 \UART_TXFF/U660 ( .A(\UART_TXFF/iFIFOMem[20][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1456 ) );
notech_mux2 \UART_TXFF/U659 ( .A(\UART_TXFF/iFIFOMem[20][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1457 ) );
notech_mux2 \UART_TXFF/U658 ( .A(\UART_TXFF/iFIFOMem[20][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1458 ) );
notech_mux2 \UART_TXFF/U657 ( .A(\UART_TXFF/iFIFOMem[20][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n302 ), .Z(\UART_TXFF/n1459 ) );
notech_and2 \UART_TXFF/U656 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n301 ) );
notech_mux2 \UART_TXFF/U655 ( .A(\UART_TXFF/iFIFOMem[21][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1460 ) );
notech_mux2 \UART_TXFF/U654 ( .A(\UART_TXFF/iFIFOMem[21][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1461 ) );
notech_mux2 \UART_TXFF/U653 ( .A(\UART_TXFF/iFIFOMem[21][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1462 ) );
notech_mux2 \UART_TXFF/U652 ( .A(\UART_TXFF/iFIFOMem[21][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1463 ) );
notech_mux2 \UART_TXFF/U651 ( .A(\UART_TXFF/iFIFOMem[21][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1464 ) );
notech_mux2 \UART_TXFF/U650 ( .A(\UART_TXFF/iFIFOMem[21][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1465 ) );
notech_mux2 \UART_TXFF/U649 ( .A(\UART_TXFF/iFIFOMem[21][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1466 ) );
notech_mux2 \UART_TXFF/U648 ( .A(\UART_TXFF/iFIFOMem[21][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n301 ), .Z(\UART_TXFF/n1467 ) );
notech_and2 \UART_TXFF/U647 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n300 ) );
notech_mux2 \UART_TXFF/U646 ( .A(\UART_TXFF/iFIFOMem[22][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1468 ) );
notech_mux2 \UART_TXFF/U645 ( .A(\UART_TXFF/iFIFOMem[22][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1469 ) );
notech_mux2 \UART_TXFF/U644 ( .A(\UART_TXFF/iFIFOMem[22][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1470 ) );
notech_mux2 \UART_TXFF/U643 ( .A(\UART_TXFF/iFIFOMem[22][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1471 ) );
notech_mux2 \UART_TXFF/U642 ( .A(\UART_TXFF/iFIFOMem[22][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1472 ) );
notech_mux2 \UART_TXFF/U641 ( .A(\UART_TXFF/iFIFOMem[22][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1473 ) );
notech_mux2 \UART_TXFF/U640 ( .A(\UART_TXFF/iFIFOMem[22][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1474 ) );
notech_mux2 \UART_TXFF/U639 ( .A(\UART_TXFF/iFIFOMem[22][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n300 ), .Z(\UART_TXFF/n1475 ) );
notech_and2 \UART_TXFF/U638 ( .A(\UART_TXFF/n299 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n298 ) );
notech_mux2 \UART_TXFF/U637 ( .A(\UART_TXFF/iFIFOMem[23][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1476 ) );
notech_mux2 \UART_TXFF/U636 ( .A(\UART_TXFF/iFIFOMem[23][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1477 ) );
notech_mux2 \UART_TXFF/U635 ( .A(\UART_TXFF/iFIFOMem[23][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1478 ) );
notech_mux2 \UART_TXFF/U634 ( .A(\UART_TXFF/iFIFOMem[23][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1479 ) );
notech_mux2 \UART_TXFF/U633 ( .A(\UART_TXFF/iFIFOMem[23][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1480 ) );
notech_mux2 \UART_TXFF/U632 ( .A(\UART_TXFF/iFIFOMem[23][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1481 ) );
notech_mux2 \UART_TXFF/U631 ( .A(\UART_TXFF/iFIFOMem[23][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1482 ) );
notech_mux2 \UART_TXFF/U630 ( .A(\UART_TXFF/iFIFOMem[23][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n298 ), .Z(\UART_TXFF/n1483 ) );
notech_ao3 \UART_TXFF/U629 ( .A(\UART_TXFF/iWRAddr[4] ), .B(
\UART_TXFF/n297 ), .C(\UART_TXFF/n222 ), .Z(\UART_TXFF/n289 ) );
notech_and2 \UART_TXFF/U628 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n296 ) );
notech_mux2 \UART_TXFF/U627 ( .A(\UART_TXFF/iFIFOMem[24][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1484 ) );
notech_mux2 \UART_TXFF/U626 ( .A(\UART_TXFF/iFIFOMem[24][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1485 ) );
notech_mux2 \UART_TXFF/U625 ( .A(\UART_TXFF/iFIFOMem[24][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1486 ) );
notech_mux2 \UART_TXFF/U624 ( .A(\UART_TXFF/iFIFOMem[24][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1487 ) );
notech_mux2 \UART_TXFF/U623 ( .A(\UART_TXFF/iFIFOMem[24][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1488 ) );
notech_mux2 \UART_TXFF/U622 ( .A(\UART_TXFF/iFIFOMem[24][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1489 ) );
notech_mux2 \UART_TXFF/U621 ( .A(\UART_TXFF/iFIFOMem[24][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1490 ) );
notech_mux2 \UART_TXFF/U620 ( .A(\UART_TXFF/iFIFOMem[24][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n296 ), .Z(\UART_TXFF/n1491 ) );
notech_and2 \UART_TXFF/U619 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n295 ) );
notech_mux2 \UART_TXFF/U618 ( .A(\UART_TXFF/iFIFOMem[25][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1492 ) );
notech_mux2 \UART_TXFF/U617 ( .A(\UART_TXFF/iFIFOMem[25][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1493 ) );
notech_mux2 \UART_TXFF/U616 ( .A(\UART_TXFF/iFIFOMem[25][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1494 ) );
notech_mux2 \UART_TXFF/U615 ( .A(\UART_TXFF/iFIFOMem[25][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1495 ) );
notech_mux2 \UART_TXFF/U614 ( .A(\UART_TXFF/iFIFOMem[25][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1496 ) );
notech_mux2 \UART_TXFF/U613 ( .A(\UART_TXFF/iFIFOMem[25][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1497 ) );
notech_mux2 \UART_TXFF/U612 ( .A(\UART_TXFF/iFIFOMem[25][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1498 ) );
notech_mux2 \UART_TXFF/U611 ( .A(\UART_TXFF/iFIFOMem[25][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n295 ), .Z(\UART_TXFF/n1499 ) );
notech_and2 \UART_TXFF/U610 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n294 ) );
notech_mux2 \UART_TXFF/U609 ( .A(\UART_TXFF/iFIFOMem[26][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1500 ) );
notech_mux2 \UART_TXFF/U608 ( .A(\UART_TXFF/iFIFOMem[26][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1501 ) );
notech_mux2 \UART_TXFF/U607 ( .A(\UART_TXFF/iFIFOMem[26][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1502 ) );
notech_mux2 \UART_TXFF/U606 ( .A(\UART_TXFF/iFIFOMem[26][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1503 ) );
notech_mux2 \UART_TXFF/U605 ( .A(\UART_TXFF/iFIFOMem[26][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1504 ) );
notech_mux2 \UART_TXFF/U604 ( .A(\UART_TXFF/iFIFOMem[26][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1505 ) );
notech_mux2 \UART_TXFF/U603 ( .A(\UART_TXFF/iFIFOMem[26][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1506 ) );
notech_mux2 \UART_TXFF/U602 ( .A(\UART_TXFF/iFIFOMem[26][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n294 ), .Z(\UART_TXFF/n1507 ) );
notech_and2 \UART_TXFF/U601 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n293 ) );
notech_mux2 \UART_TXFF/U600 ( .A(\UART_TXFF/iFIFOMem[27][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1508 ) );
notech_mux2 \UART_TXFF/U599 ( .A(\UART_TXFF/iFIFOMem[27][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1509 ) );
notech_mux2 \UART_TXFF/U598 ( .A(\UART_TXFF/iFIFOMem[27][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1510 ) );
notech_mux2 \UART_TXFF/U597 ( .A(\UART_TXFF/iFIFOMem[27][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1511 ) );
notech_mux2 \UART_TXFF/U596 ( .A(\UART_TXFF/iFIFOMem[27][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1512 ) );
notech_mux2 \UART_TXFF/U595 ( .A(\UART_TXFF/iFIFOMem[27][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1513 ) );
notech_mux2 \UART_TXFF/U594 ( .A(\UART_TXFF/iFIFOMem[27][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1514 ) );
notech_mux2 \UART_TXFF/U593 ( .A(\UART_TXFF/iFIFOMem[27][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n293 ), .Z(\UART_TXFF/n1515 ) );
notech_and2 \UART_TXFF/U592 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n292 ) );
notech_mux2 \UART_TXFF/U591 ( .A(\UART_TXFF/iFIFOMem[28][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1516 ) );
notech_mux2 \UART_TXFF/U590 ( .A(\UART_TXFF/iFIFOMem[28][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1517 ) );
notech_mux2 \UART_TXFF/U589 ( .A(\UART_TXFF/iFIFOMem[28][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1518 ) );
notech_mux2 \UART_TXFF/U588 ( .A(\UART_TXFF/iFIFOMem[28][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1519 ) );
notech_mux2 \UART_TXFF/U587 ( .A(\UART_TXFF/iFIFOMem[28][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1520 ) );
notech_mux2 \UART_TXFF/U586 ( .A(\UART_TXFF/iFIFOMem[28][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1521 ) );
notech_mux2 \UART_TXFF/U585 ( .A(\UART_TXFF/iFIFOMem[28][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1522 ) );
notech_mux2 \UART_TXFF/U584 ( .A(\UART_TXFF/iFIFOMem[28][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n292 ), .Z(\UART_TXFF/n1523 ) );
notech_and2 \UART_TXFF/U583 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n291 ) );
notech_mux2 \UART_TXFF/U582 ( .A(\UART_TXFF/iFIFOMem[29][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1524 ) );
notech_mux2 \UART_TXFF/U581 ( .A(\UART_TXFF/iFIFOMem[29][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1525 ) );
notech_mux2 \UART_TXFF/U580 ( .A(\UART_TXFF/iFIFOMem[29][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1526 ) );
notech_mux2 \UART_TXFF/U579 ( .A(\UART_TXFF/iFIFOMem[29][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1527 ) );
notech_mux2 \UART_TXFF/U578 ( .A(\UART_TXFF/iFIFOMem[29][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1528 ) );
notech_mux2 \UART_TXFF/U577 ( .A(\UART_TXFF/iFIFOMem[29][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1529 ) );
notech_mux2 \UART_TXFF/U576 ( .A(\UART_TXFF/iFIFOMem[29][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1530 ) );
notech_mux2 \UART_TXFF/U575 ( .A(\UART_TXFF/iFIFOMem[29][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n291 ), .Z(\UART_TXFF/n1531 ) );
notech_and2 \UART_TXFF/U574 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n290 ) );
notech_mux2 \UART_TXFF/U573 ( .A(\UART_TXFF/iFIFOMem[30][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1532 ) );
notech_mux2 \UART_TXFF/U572 ( .A(\UART_TXFF/iFIFOMem[30][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1533 ) );
notech_mux2 \UART_TXFF/U571 ( .A(\UART_TXFF/iFIFOMem[30][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1534 ) );
notech_mux2 \UART_TXFF/U570 ( .A(\UART_TXFF/iFIFOMem[30][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1535 ) );
notech_mux2 \UART_TXFF/U569 ( .A(\UART_TXFF/iFIFOMem[30][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1536 ) );
notech_mux2 \UART_TXFF/U568 ( .A(\UART_TXFF/iFIFOMem[30][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1537 ) );
notech_mux2 \UART_TXFF/U567 ( .A(\UART_TXFF/iFIFOMem[30][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1538 ) );
notech_mux2 \UART_TXFF/U566 ( .A(\UART_TXFF/iFIFOMem[30][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n290 ), .Z(\UART_TXFF/n1539 ) );
notech_and2 \UART_TXFF/U565 ( .A(\UART_TXFF/n289 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n288 ) );
notech_mux2 \UART_TXFF/U564 ( .A(\UART_TXFF/iFIFOMem[31][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1540 ) );
notech_mux2 \UART_TXFF/U563 ( .A(\UART_TXFF/iFIFOMem[31][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1541 ) );
notech_mux2 \UART_TXFF/U562 ( .A(\UART_TXFF/iFIFOMem[31][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1542 ) );
notech_mux2 \UART_TXFF/U561 ( .A(\UART_TXFF/iFIFOMem[31][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1543 ) );
notech_mux2 \UART_TXFF/U560 ( .A(\UART_TXFF/iFIFOMem[31][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1544 ) );
notech_mux2 \UART_TXFF/U559 ( .A(\UART_TXFF/iFIFOMem[31][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1545 ) );
notech_mux2 \UART_TXFF/U558 ( .A(\UART_TXFF/iFIFOMem[31][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1546 ) );
notech_mux2 \UART_TXFF/U557 ( .A(\UART_TXFF/iFIFOMem[31][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n288 ), .Z(\UART_TXFF/n1547 ) );
notech_ao3 \UART_TXFF/U556 ( .A(\UART_TXFF/iWRAddr[5] ), .B(
\UART_TXFF/n287 ), .C(RST), .Z(\UART_TXFF/n259 ) );
notech_ao3 \UART_TXFF/U555 ( .A(\UART_TXFF/n222 ), .B(\UART_TXFF/n259 ),
.C(\UART_TXFF/iWRAddr[4] ), .Z(\UART_TXFF/n279 ) );
notech_and2 \UART_TXFF/U554 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n286 ) );
notech_mux2 \UART_TXFF/U553 ( .A(\UART_TXFF/iFIFOMem[32][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1548 ) );
notech_mux2 \UART_TXFF/U552 ( .A(\UART_TXFF/iFIFOMem[32][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1549 ) );
notech_mux2 \UART_TXFF/U551 ( .A(\UART_TXFF/iFIFOMem[32][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1550 ) );
notech_mux2 \UART_TXFF/U550 ( .A(\UART_TXFF/iFIFOMem[32][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1551 ) );
notech_mux2 \UART_TXFF/U549 ( .A(\UART_TXFF/iFIFOMem[32][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1552 ) );
notech_mux2 \UART_TXFF/U548 ( .A(\UART_TXFF/iFIFOMem[32][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1553 ) );
notech_mux2 \UART_TXFF/U547 ( .A(\UART_TXFF/iFIFOMem[32][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1554 ) );
notech_mux2 \UART_TXFF/U546 ( .A(\UART_TXFF/iFIFOMem[32][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n286 ), .Z(\UART_TXFF/n1555 ) );
notech_and2 \UART_TXFF/U545 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n285 ) );
notech_mux2 \UART_TXFF/U544 ( .A(\UART_TXFF/iFIFOMem[33][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1556 ) );
notech_mux2 \UART_TXFF/U543 ( .A(\UART_TXFF/iFIFOMem[33][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1557 ) );
notech_mux2 \UART_TXFF/U542 ( .A(\UART_TXFF/iFIFOMem[33][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1558 ) );
notech_mux2 \UART_TXFF/U541 ( .A(\UART_TXFF/iFIFOMem[33][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1559 ) );
notech_mux2 \UART_TXFF/U540 ( .A(\UART_TXFF/iFIFOMem[33][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1560 ) );
notech_mux2 \UART_TXFF/U539 ( .A(\UART_TXFF/iFIFOMem[33][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1561 ) );
notech_mux2 \UART_TXFF/U538 ( .A(\UART_TXFF/iFIFOMem[33][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1562 ) );
notech_mux2 \UART_TXFF/U537 ( .A(\UART_TXFF/iFIFOMem[33][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n285 ), .Z(\UART_TXFF/n1563 ) );
notech_and2 \UART_TXFF/U536 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n284 ) );
notech_mux2 \UART_TXFF/U535 ( .A(\UART_TXFF/iFIFOMem[34][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1564 ) );
notech_mux2 \UART_TXFF/U534 ( .A(\UART_TXFF/iFIFOMem[34][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1565 ) );
notech_mux2 \UART_TXFF/U533 ( .A(\UART_TXFF/iFIFOMem[34][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1566 ) );
notech_mux2 \UART_TXFF/U532 ( .A(\UART_TXFF/iFIFOMem[34][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1567 ) );
notech_mux2 \UART_TXFF/U531 ( .A(\UART_TXFF/iFIFOMem[34][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1568 ) );
notech_mux2 \UART_TXFF/U530 ( .A(\UART_TXFF/iFIFOMem[34][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1569 ) );
notech_mux2 \UART_TXFF/U529 ( .A(\UART_TXFF/iFIFOMem[34][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1570 ) );
notech_mux2 \UART_TXFF/U528 ( .A(\UART_TXFF/iFIFOMem[34][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n284 ), .Z(\UART_TXFF/n1571 ) );
notech_and2 \UART_TXFF/U527 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n283 ) );
notech_mux2 \UART_TXFF/U526 ( .A(\UART_TXFF/iFIFOMem[35][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1572 ) );
notech_mux2 \UART_TXFF/U525 ( .A(\UART_TXFF/iFIFOMem[35][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1573 ) );
notech_mux2 \UART_TXFF/U524 ( .A(\UART_TXFF/iFIFOMem[35][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1574 ) );
notech_mux2 \UART_TXFF/U523 ( .A(\UART_TXFF/iFIFOMem[35][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1575 ) );
notech_mux2 \UART_TXFF/U522 ( .A(\UART_TXFF/iFIFOMem[35][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1576 ) );
notech_mux2 \UART_TXFF/U521 ( .A(\UART_TXFF/iFIFOMem[35][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1577 ) );
notech_mux2 \UART_TXFF/U520 ( .A(\UART_TXFF/iFIFOMem[35][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1578 ) );
notech_mux2 \UART_TXFF/U519 ( .A(\UART_TXFF/iFIFOMem[35][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n283 ), .Z(\UART_TXFF/n1579 ) );
notech_and2 \UART_TXFF/U518 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n282 ) );
notech_mux2 \UART_TXFF/U517 ( .A(\UART_TXFF/iFIFOMem[36][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1580 ) );
notech_mux2 \UART_TXFF/U516 ( .A(\UART_TXFF/iFIFOMem[36][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1581 ) );
notech_mux2 \UART_TXFF/U515 ( .A(\UART_TXFF/iFIFOMem[36][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1582 ) );
notech_mux2 \UART_TXFF/U514 ( .A(\UART_TXFF/iFIFOMem[36][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1583 ) );
notech_mux2 \UART_TXFF/U513 ( .A(\UART_TXFF/iFIFOMem[36][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1584 ) );
notech_mux2 \UART_TXFF/U512 ( .A(\UART_TXFF/iFIFOMem[36][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1585 ) );
notech_mux2 \UART_TXFF/U511 ( .A(\UART_TXFF/iFIFOMem[36][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1586 ) );
notech_mux2 \UART_TXFF/U510 ( .A(\UART_TXFF/iFIFOMem[36][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n282 ), .Z(\UART_TXFF/n1587 ) );
notech_and2 \UART_TXFF/U509 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n281 ) );
notech_mux2 \UART_TXFF/U508 ( .A(\UART_TXFF/iFIFOMem[37][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1588 ) );
notech_mux2 \UART_TXFF/U507 ( .A(\UART_TXFF/iFIFOMem[37][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1589 ) );
notech_mux2 \UART_TXFF/U506 ( .A(\UART_TXFF/iFIFOMem[37][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1590 ) );
notech_mux2 \UART_TXFF/U505 ( .A(\UART_TXFF/iFIFOMem[37][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1591 ) );
notech_mux2 \UART_TXFF/U504 ( .A(\UART_TXFF/iFIFOMem[37][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1592 ) );
notech_mux2 \UART_TXFF/U503 ( .A(\UART_TXFF/iFIFOMem[37][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1593 ) );
notech_mux2 \UART_TXFF/U502 ( .A(\UART_TXFF/iFIFOMem[37][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1594 ) );
notech_mux2 \UART_TXFF/U501 ( .A(\UART_TXFF/iFIFOMem[37][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n281 ), .Z(\UART_TXFF/n1595 ) );
notech_and2 \UART_TXFF/U500 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n280 ) );
notech_mux2 \UART_TXFF/U499 ( .A(\UART_TXFF/iFIFOMem[38][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1596 ) );
notech_mux2 \UART_TXFF/U498 ( .A(\UART_TXFF/iFIFOMem[38][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1597 ) );
notech_mux2 \UART_TXFF/U497 ( .A(\UART_TXFF/iFIFOMem[38][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1598 ) );
notech_mux2 \UART_TXFF/U496 ( .A(\UART_TXFF/iFIFOMem[38][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1599 ) );
notech_mux2 \UART_TXFF/U495 ( .A(\UART_TXFF/iFIFOMem[38][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1600 ) );
notech_mux2 \UART_TXFF/U494 ( .A(\UART_TXFF/iFIFOMem[38][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1601 ) );
notech_mux2 \UART_TXFF/U493 ( .A(\UART_TXFF/iFIFOMem[38][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1602 ) );
notech_mux2 \UART_TXFF/U492 ( .A(\UART_TXFF/iFIFOMem[38][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n280 ), .Z(\UART_TXFF/n1603 ) );
notech_and2 \UART_TXFF/U491 ( .A(\UART_TXFF/n279 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n278 ) );
notech_mux2 \UART_TXFF/U490 ( .A(\UART_TXFF/iFIFOMem[39][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1604 ) );
notech_mux2 \UART_TXFF/U489 ( .A(\UART_TXFF/iFIFOMem[39][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1605 ) );
notech_mux2 \UART_TXFF/U488 ( .A(\UART_TXFF/iFIFOMem[39][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1606 ) );
notech_mux2 \UART_TXFF/U487 ( .A(\UART_TXFF/iFIFOMem[39][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1607 ) );
notech_mux2 \UART_TXFF/U486 ( .A(\UART_TXFF/iFIFOMem[39][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1608 ) );
notech_mux2 \UART_TXFF/U485 ( .A(\UART_TXFF/iFIFOMem[39][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1609 ) );
notech_mux2 \UART_TXFF/U484 ( .A(\UART_TXFF/iFIFOMem[39][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1610 ) );
notech_mux2 \UART_TXFF/U483 ( .A(\UART_TXFF/iFIFOMem[39][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n278 ), .Z(\UART_TXFF/n1611 ) );
notech_ao3 \UART_TXFF/U482 ( .A(\UART_TXFF/iWRAddr[3] ), .B(
\UART_TXFF/n259 ), .C(\UART_TXFF/iWRAddr[4] ), .Z(\UART_TXFF/n270 ) );
notech_and2 \UART_TXFF/U481 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n277 ) );
notech_mux2 \UART_TXFF/U480 ( .A(\UART_TXFF/iFIFOMem[40][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1612 ) );
notech_mux2 \UART_TXFF/U479 ( .A(\UART_TXFF/iFIFOMem[40][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1613 ) );
notech_mux2 \UART_TXFF/U478 ( .A(\UART_TXFF/iFIFOMem[40][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1614 ) );
notech_mux2 \UART_TXFF/U477 ( .A(\UART_TXFF/iFIFOMem[40][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1615 ) );
notech_mux2 \UART_TXFF/U476 ( .A(\UART_TXFF/iFIFOMem[40][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1616 ) );
notech_mux2 \UART_TXFF/U475 ( .A(\UART_TXFF/iFIFOMem[40][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1617 ) );
notech_mux2 \UART_TXFF/U474 ( .A(\UART_TXFF/iFIFOMem[40][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1618 ) );
notech_mux2 \UART_TXFF/U473 ( .A(\UART_TXFF/iFIFOMem[40][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n277 ), .Z(\UART_TXFF/n1619 ) );
notech_and2 \UART_TXFF/U472 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n276 ) );
notech_mux2 \UART_TXFF/U471 ( .A(\UART_TXFF/iFIFOMem[41][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1620 ) );
notech_mux2 \UART_TXFF/U470 ( .A(\UART_TXFF/iFIFOMem[41][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1621 ) );
notech_mux2 \UART_TXFF/U469 ( .A(\UART_TXFF/iFIFOMem[41][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1622 ) );
notech_mux2 \UART_TXFF/U468 ( .A(\UART_TXFF/iFIFOMem[41][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1623 ) );
notech_mux2 \UART_TXFF/U467 ( .A(\UART_TXFF/iFIFOMem[41][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1624 ) );
notech_mux2 \UART_TXFF/U466 ( .A(\UART_TXFF/iFIFOMem[41][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1625 ) );
notech_mux2 \UART_TXFF/U465 ( .A(\UART_TXFF/iFIFOMem[41][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1626 ) );
notech_mux2 \UART_TXFF/U464 ( .A(\UART_TXFF/iFIFOMem[41][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n276 ), .Z(\UART_TXFF/n1627 ) );
notech_and2 \UART_TXFF/U463 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n275 ) );
notech_mux2 \UART_TXFF/U462 ( .A(\UART_TXFF/iFIFOMem[42][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1628 ) );
notech_mux2 \UART_TXFF/U461 ( .A(\UART_TXFF/iFIFOMem[42][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1629 ) );
notech_mux2 \UART_TXFF/U460 ( .A(\UART_TXFF/iFIFOMem[42][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1630 ) );
notech_mux2 \UART_TXFF/U459 ( .A(\UART_TXFF/iFIFOMem[42][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1631 ) );
notech_mux2 \UART_TXFF/U458 ( .A(\UART_TXFF/iFIFOMem[42][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1632 ) );
notech_mux2 \UART_TXFF/U457 ( .A(\UART_TXFF/iFIFOMem[42][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1633 ) );
notech_mux2 \UART_TXFF/U456 ( .A(\UART_TXFF/iFIFOMem[42][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1634 ) );
notech_mux2 \UART_TXFF/U455 ( .A(\UART_TXFF/iFIFOMem[42][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n275 ), .Z(\UART_TXFF/n1635 ) );
notech_and2 \UART_TXFF/U454 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n274 ) );
notech_mux2 \UART_TXFF/U453 ( .A(\UART_TXFF/iFIFOMem[43][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1636 ) );
notech_mux2 \UART_TXFF/U452 ( .A(\UART_TXFF/iFIFOMem[43][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1637 ) );
notech_mux2 \UART_TXFF/U451 ( .A(\UART_TXFF/iFIFOMem[43][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1638 ) );
notech_mux2 \UART_TXFF/U450 ( .A(\UART_TXFF/iFIFOMem[43][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1639 ) );
notech_mux2 \UART_TXFF/U449 ( .A(\UART_TXFF/iFIFOMem[43][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1640 ) );
notech_mux2 \UART_TXFF/U448 ( .A(\UART_TXFF/iFIFOMem[43][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1641 ) );
notech_mux2 \UART_TXFF/U447 ( .A(\UART_TXFF/iFIFOMem[43][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1642 ) );
notech_mux2 \UART_TXFF/U446 ( .A(\UART_TXFF/iFIFOMem[43][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n274 ), .Z(\UART_TXFF/n1643 ) );
notech_and2 \UART_TXFF/U445 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n273 ) );
notech_mux2 \UART_TXFF/U444 ( .A(\UART_TXFF/iFIFOMem[44][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1644 ) );
notech_mux2 \UART_TXFF/U443 ( .A(\UART_TXFF/iFIFOMem[44][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1645 ) );
notech_mux2 \UART_TXFF/U442 ( .A(\UART_TXFF/iFIFOMem[44][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1646 ) );
notech_mux2 \UART_TXFF/U441 ( .A(\UART_TXFF/iFIFOMem[44][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1647 ) );
notech_mux2 \UART_TXFF/U440 ( .A(\UART_TXFF/iFIFOMem[44][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1648 ) );
notech_mux2 \UART_TXFF/U439 ( .A(\UART_TXFF/iFIFOMem[44][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1649 ) );
notech_mux2 \UART_TXFF/U438 ( .A(\UART_TXFF/iFIFOMem[44][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1650 ) );
notech_mux2 \UART_TXFF/U437 ( .A(\UART_TXFF/iFIFOMem[44][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n273 ), .Z(\UART_TXFF/n1651 ) );
notech_and2 \UART_TXFF/U436 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n272 ) );
notech_mux2 \UART_TXFF/U435 ( .A(\UART_TXFF/iFIFOMem[45][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1652 ) );
notech_mux2 \UART_TXFF/U434 ( .A(\UART_TXFF/iFIFOMem[45][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1653 ) );
notech_mux2 \UART_TXFF/U433 ( .A(\UART_TXFF/iFIFOMem[45][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1654 ) );
notech_mux2 \UART_TXFF/U432 ( .A(\UART_TXFF/iFIFOMem[45][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1655 ) );
notech_mux2 \UART_TXFF/U431 ( .A(\UART_TXFF/iFIFOMem[45][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1656 ) );
notech_mux2 \UART_TXFF/U430 ( .A(\UART_TXFF/iFIFOMem[45][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1657 ) );
notech_mux2 \UART_TXFF/U429 ( .A(\UART_TXFF/iFIFOMem[45][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1658 ) );
notech_mux2 \UART_TXFF/U428 ( .A(\UART_TXFF/iFIFOMem[45][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n272 ), .Z(\UART_TXFF/n1659 ) );
notech_and2 \UART_TXFF/U427 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n271 ) );
notech_mux2 \UART_TXFF/U426 ( .A(\UART_TXFF/iFIFOMem[46][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1660 ) );
notech_mux2 \UART_TXFF/U425 ( .A(\UART_TXFF/iFIFOMem[46][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1661 ) );
notech_mux2 \UART_TXFF/U424 ( .A(\UART_TXFF/iFIFOMem[46][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1662 ) );
notech_mux2 \UART_TXFF/U423 ( .A(\UART_TXFF/iFIFOMem[46][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1663 ) );
notech_mux2 \UART_TXFF/U422 ( .A(\UART_TXFF/iFIFOMem[46][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1664 ) );
notech_mux2 \UART_TXFF/U421 ( .A(\UART_TXFF/iFIFOMem[46][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1665 ) );
notech_mux2 \UART_TXFF/U420 ( .A(\UART_TXFF/iFIFOMem[46][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1666 ) );
notech_mux2 \UART_TXFF/U419 ( .A(\UART_TXFF/iFIFOMem[46][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n271 ), .Z(\UART_TXFF/n1667 ) );
notech_and2 \UART_TXFF/U418 ( .A(\UART_TXFF/n270 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n269 ) );
notech_mux2 \UART_TXFF/U417 ( .A(\UART_TXFF/iFIFOMem[47][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1668 ) );
notech_mux2 \UART_TXFF/U416 ( .A(\UART_TXFF/iFIFOMem[47][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1669 ) );
notech_mux2 \UART_TXFF/U415 ( .A(\UART_TXFF/iFIFOMem[47][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1670 ) );
notech_mux2 \UART_TXFF/U414 ( .A(\UART_TXFF/iFIFOMem[47][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1671 ) );
notech_mux2 \UART_TXFF/U413 ( .A(\UART_TXFF/iFIFOMem[47][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1672 ) );
notech_mux2 \UART_TXFF/U412 ( .A(\UART_TXFF/iFIFOMem[47][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1673 ) );
notech_mux2 \UART_TXFF/U411 ( .A(\UART_TXFF/iFIFOMem[47][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1674 ) );
notech_mux2 \UART_TXFF/U410 ( .A(\UART_TXFF/iFIFOMem[47][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n269 ), .Z(\UART_TXFF/n1675 ) );
notech_ao3 \UART_TXFF/U409 ( .A(\UART_TXFF/iWRAddr[4] ), .B(
\UART_TXFF/n259 ), .C(\UART_TXFF/iWRAddr[3] ), .Z(\UART_TXFF/n261 ) );
notech_and2 \UART_TXFF/U408 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n268 ) );
notech_mux2 \UART_TXFF/U407 ( .A(\UART_TXFF/iFIFOMem[48][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1676 ) );
notech_mux2 \UART_TXFF/U406 ( .A(\UART_TXFF/iFIFOMem[48][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1677 ) );
notech_mux2 \UART_TXFF/U405 ( .A(\UART_TXFF/iFIFOMem[48][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1678 ) );
notech_mux2 \UART_TXFF/U404 ( .A(\UART_TXFF/iFIFOMem[48][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1679 ) );
notech_mux2 \UART_TXFF/U403 ( .A(\UART_TXFF/iFIFOMem[48][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1680 ) );
notech_mux2 \UART_TXFF/U402 ( .A(\UART_TXFF/iFIFOMem[48][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1681 ) );
notech_mux2 \UART_TXFF/U401 ( .A(\UART_TXFF/iFIFOMem[48][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1682 ) );
notech_mux2 \UART_TXFF/U400 ( .A(\UART_TXFF/iFIFOMem[48][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n268 ), .Z(\UART_TXFF/n1683 ) );
notech_and2 \UART_TXFF/U399 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n267 ) );
notech_mux2 \UART_TXFF/U398 ( .A(\UART_TXFF/iFIFOMem[49][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1684 ) );
notech_mux2 \UART_TXFF/U397 ( .A(\UART_TXFF/iFIFOMem[49][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1685 ) );
notech_mux2 \UART_TXFF/U396 ( .A(\UART_TXFF/iFIFOMem[49][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1686 ) );
notech_mux2 \UART_TXFF/U395 ( .A(\UART_TXFF/iFIFOMem[49][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1687 ) );
notech_mux2 \UART_TXFF/U394 ( .A(\UART_TXFF/iFIFOMem[49][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1688 ) );
notech_mux2 \UART_TXFF/U393 ( .A(\UART_TXFF/iFIFOMem[49][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1689 ) );
notech_mux2 \UART_TXFF/U392 ( .A(\UART_TXFF/iFIFOMem[49][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1690 ) );
notech_mux2 \UART_TXFF/U391 ( .A(\UART_TXFF/iFIFOMem[49][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n267 ), .Z(\UART_TXFF/n1691 ) );
notech_and2 \UART_TXFF/U390 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n266 ) );
notech_mux2 \UART_TXFF/U389 ( .A(\UART_TXFF/iFIFOMem[50][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1692 ) );
notech_mux2 \UART_TXFF/U388 ( .A(\UART_TXFF/iFIFOMem[50][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1693 ) );
notech_mux2 \UART_TXFF/U387 ( .A(\UART_TXFF/iFIFOMem[50][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1694 ) );
notech_mux2 \UART_TXFF/U386 ( .A(\UART_TXFF/iFIFOMem[50][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1695 ) );
notech_mux2 \UART_TXFF/U385 ( .A(\UART_TXFF/iFIFOMem[50][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1696 ) );
notech_mux2 \UART_TXFF/U384 ( .A(\UART_TXFF/iFIFOMem[50][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1697 ) );
notech_mux2 \UART_TXFF/U383 ( .A(\UART_TXFF/iFIFOMem[50][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1698 ) );
notech_mux2 \UART_TXFF/U382 ( .A(\UART_TXFF/iFIFOMem[50][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n266 ), .Z(\UART_TXFF/n1699 ) );
notech_and2 \UART_TXFF/U381 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n265 ) );
notech_mux2 \UART_TXFF/U380 ( .A(\UART_TXFF/iFIFOMem[51][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1700 ) );
notech_mux2 \UART_TXFF/U379 ( .A(\UART_TXFF/iFIFOMem[51][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1701 ) );
notech_mux2 \UART_TXFF/U378 ( .A(\UART_TXFF/iFIFOMem[51][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1702 ) );
notech_mux2 \UART_TXFF/U377 ( .A(\UART_TXFF/iFIFOMem[51][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1703 ) );
notech_mux2 \UART_TXFF/U376 ( .A(\UART_TXFF/iFIFOMem[51][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1704 ) );
notech_mux2 \UART_TXFF/U375 ( .A(\UART_TXFF/iFIFOMem[51][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1705 ) );
notech_mux2 \UART_TXFF/U374 ( .A(\UART_TXFF/iFIFOMem[51][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1706 ) );
notech_mux2 \UART_TXFF/U373 ( .A(\UART_TXFF/iFIFOMem[51][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n265 ), .Z(\UART_TXFF/n1707 ) );
notech_and2 \UART_TXFF/U372 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n264 ) );
notech_mux2 \UART_TXFF/U371 ( .A(\UART_TXFF/iFIFOMem[52][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1708 ) );
notech_mux2 \UART_TXFF/U370 ( .A(\UART_TXFF/iFIFOMem[52][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1709 ) );
notech_mux2 \UART_TXFF/U369 ( .A(\UART_TXFF/iFIFOMem[52][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1710 ) );
notech_mux2 \UART_TXFF/U368 ( .A(\UART_TXFF/iFIFOMem[52][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1711 ) );
notech_mux2 \UART_TXFF/U367 ( .A(\UART_TXFF/iFIFOMem[52][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1712 ) );
notech_mux2 \UART_TXFF/U366 ( .A(\UART_TXFF/iFIFOMem[52][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1713 ) );
notech_mux2 \UART_TXFF/U365 ( .A(\UART_TXFF/iFIFOMem[52][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1714 ) );
notech_mux2 \UART_TXFF/U364 ( .A(\UART_TXFF/iFIFOMem[52][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n264 ), .Z(\UART_TXFF/n1715 ) );
notech_and2 \UART_TXFF/U363 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n263 ) );
notech_mux2 \UART_TXFF/U362 ( .A(\UART_TXFF/iFIFOMem[53][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1716 ) );
notech_mux2 \UART_TXFF/U361 ( .A(\UART_TXFF/iFIFOMem[53][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1717 ) );
notech_mux2 \UART_TXFF/U360 ( .A(\UART_TXFF/iFIFOMem[53][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1718 ) );
notech_mux2 \UART_TXFF/U359 ( .A(\UART_TXFF/iFIFOMem[53][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1719 ) );
notech_mux2 \UART_TXFF/U358 ( .A(\UART_TXFF/iFIFOMem[53][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1720 ) );
notech_mux2 \UART_TXFF/U357 ( .A(\UART_TXFF/iFIFOMem[53][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1721 ) );
notech_mux2 \UART_TXFF/U356 ( .A(\UART_TXFF/iFIFOMem[53][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1722 ) );
notech_mux2 \UART_TXFF/U355 ( .A(\UART_TXFF/iFIFOMem[53][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n263 ), .Z(\UART_TXFF/n1723 ) );
notech_and2 \UART_TXFF/U354 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n262 ) );
notech_mux2 \UART_TXFF/U353 ( .A(\UART_TXFF/iFIFOMem[54][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1724 ) );
notech_mux2 \UART_TXFF/U352 ( .A(\UART_TXFF/iFIFOMem[54][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1725 ) );
notech_mux2 \UART_TXFF/U351 ( .A(\UART_TXFF/iFIFOMem[54][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1726 ) );
notech_mux2 \UART_TXFF/U350 ( .A(\UART_TXFF/iFIFOMem[54][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1727 ) );
notech_mux2 \UART_TXFF/U349 ( .A(\UART_TXFF/iFIFOMem[54][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1728 ) );
notech_mux2 \UART_TXFF/U348 ( .A(\UART_TXFF/iFIFOMem[54][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1729 ) );
notech_mux2 \UART_TXFF/U347 ( .A(\UART_TXFF/iFIFOMem[54][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1730 ) );
notech_mux2 \UART_TXFF/U346 ( .A(\UART_TXFF/iFIFOMem[54][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n262 ), .Z(\UART_TXFF/n1731 ) );
notech_and2 \UART_TXFF/U345 ( .A(\UART_TXFF/n261 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n260 ) );
notech_mux2 \UART_TXFF/U344 ( .A(\UART_TXFF/iFIFOMem[55][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1732 ) );
notech_mux2 \UART_TXFF/U343 ( .A(\UART_TXFF/iFIFOMem[55][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1733 ) );
notech_mux2 \UART_TXFF/U342 ( .A(\UART_TXFF/iFIFOMem[55][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1734 ) );
notech_mux2 \UART_TXFF/U341 ( .A(\UART_TXFF/iFIFOMem[55][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1735 ) );
notech_mux2 \UART_TXFF/U340 ( .A(\UART_TXFF/iFIFOMem[55][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1736 ) );
notech_mux2 \UART_TXFF/U339 ( .A(\UART_TXFF/iFIFOMem[55][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1737 ) );
notech_mux2 \UART_TXFF/U338 ( .A(\UART_TXFF/iFIFOMem[55][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1738 ) );
notech_mux2 \UART_TXFF/U337 ( .A(\UART_TXFF/iFIFOMem[55][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n260 ), .Z(\UART_TXFF/n1739 ) );
notech_and3 \UART_TXFF/U336 ( .A(\UART_TXFF/iWRAddr[4] ), .B(
\UART_TXFF/n259 ), .C(\UART_TXFF/iWRAddr[3] ), .Z(\UART_TXFF/n243 ) );
notech_and2 \UART_TXFF/U335 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n258 ),
.Z(\UART_TXFF/n257 ) );
notech_mux2 \UART_TXFF/U334 ( .A(\UART_TXFF/iFIFOMem[56][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1740 ) );
notech_mux2 \UART_TXFF/U333 ( .A(\UART_TXFF/iFIFOMem[56][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1741 ) );
notech_mux2 \UART_TXFF/U332 ( .A(\UART_TXFF/iFIFOMem[56][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1742 ) );
notech_mux2 \UART_TXFF/U331 ( .A(\UART_TXFF/iFIFOMem[56][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1743 ) );
notech_mux2 \UART_TXFF/U330 ( .A(\UART_TXFF/iFIFOMem[56][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1744 ) );
notech_mux2 \UART_TXFF/U329 ( .A(\UART_TXFF/iFIFOMem[56][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1745 ) );
notech_mux2 \UART_TXFF/U328 ( .A(\UART_TXFF/iFIFOMem[56][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1746 ) );
notech_mux2 \UART_TXFF/U327 ( .A(\UART_TXFF/iFIFOMem[56][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n257 ), .Z(\UART_TXFF/n1747 ) );
notech_and2 \UART_TXFF/U326 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n256 ),
.Z(\UART_TXFF/n255 ) );
notech_mux2 \UART_TXFF/U325 ( .A(\UART_TXFF/iFIFOMem[57][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1748 ) );
notech_mux2 \UART_TXFF/U324 ( .A(\UART_TXFF/iFIFOMem[57][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1749 ) );
notech_mux2 \UART_TXFF/U323 ( .A(\UART_TXFF/iFIFOMem[57][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1750 ) );
notech_mux2 \UART_TXFF/U322 ( .A(\UART_TXFF/iFIFOMem[57][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1751 ) );
notech_mux2 \UART_TXFF/U321 ( .A(\UART_TXFF/iFIFOMem[57][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1752 ) );
notech_mux2 \UART_TXFF/U320 ( .A(\UART_TXFF/iFIFOMem[57][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1753 ) );
notech_mux2 \UART_TXFF/U319 ( .A(\UART_TXFF/iFIFOMem[57][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1754 ) );
notech_mux2 \UART_TXFF/U318 ( .A(\UART_TXFF/iFIFOMem[57][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n255 ), .Z(\UART_TXFF/n1755 ) );
notech_and2 \UART_TXFF/U317 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n254 ),
.Z(\UART_TXFF/n253 ) );
notech_mux2 \UART_TXFF/U316 ( .A(\UART_TXFF/iFIFOMem[58][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1756 ) );
notech_mux2 \UART_TXFF/U315 ( .A(\UART_TXFF/iFIFOMem[58][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1757 ) );
notech_mux2 \UART_TXFF/U314 ( .A(\UART_TXFF/iFIFOMem[58][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1758 ) );
notech_mux2 \UART_TXFF/U313 ( .A(\UART_TXFF/iFIFOMem[58][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1759 ) );
notech_mux2 \UART_TXFF/U312 ( .A(\UART_TXFF/iFIFOMem[58][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1760 ) );
notech_mux2 \UART_TXFF/U311 ( .A(\UART_TXFF/iFIFOMem[58][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1761 ) );
notech_mux2 \UART_TXFF/U310 ( .A(\UART_TXFF/iFIFOMem[58][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1762 ) );
notech_mux2 \UART_TXFF/U309 ( .A(\UART_TXFF/iFIFOMem[58][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n253 ), .Z(\UART_TXFF/n1763 ) );
notech_and2 \UART_TXFF/U308 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n252 ),
.Z(\UART_TXFF/n251 ) );
notech_mux2 \UART_TXFF/U307 ( .A(\UART_TXFF/iFIFOMem[59][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1764 ) );
notech_mux2 \UART_TXFF/U306 ( .A(\UART_TXFF/iFIFOMem[59][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1765 ) );
notech_mux2 \UART_TXFF/U305 ( .A(\UART_TXFF/iFIFOMem[59][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1766 ) );
notech_mux2 \UART_TXFF/U304 ( .A(\UART_TXFF/iFIFOMem[59][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1767 ) );
notech_mux2 \UART_TXFF/U303 ( .A(\UART_TXFF/iFIFOMem[59][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1768 ) );
notech_mux2 \UART_TXFF/U302 ( .A(\UART_TXFF/iFIFOMem[59][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1769 ) );
notech_mux2 \UART_TXFF/U301 ( .A(\UART_TXFF/iFIFOMem[59][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1770 ) );
notech_mux2 \UART_TXFF/U300 ( .A(\UART_TXFF/iFIFOMem[59][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n251 ), .Z(\UART_TXFF/n1771 ) );
notech_and2 \UART_TXFF/U299 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n250 ),
.Z(\UART_TXFF/n249 ) );
notech_mux2 \UART_TXFF/U298 ( .A(\UART_TXFF/iFIFOMem[60][0] ), .B(iDIN[0]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1772 ) );
notech_mux2 \UART_TXFF/U297 ( .A(\UART_TXFF/iFIFOMem[60][1] ), .B(iDIN[1]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1773 ) );
notech_mux2 \UART_TXFF/U296 ( .A(\UART_TXFF/iFIFOMem[60][2] ), .B(iDIN[2]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1774 ) );
notech_mux2 \UART_TXFF/U295 ( .A(\UART_TXFF/iFIFOMem[60][3] ), .B(iDIN[3]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1775 ) );
notech_mux2 \UART_TXFF/U294 ( .A(\UART_TXFF/iFIFOMem[60][4] ), .B(iDIN[4]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1776 ) );
notech_mux2 \UART_TXFF/U293 ( .A(\UART_TXFF/iFIFOMem[60][5] ), .B(iDIN[5]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1777 ) );
notech_mux2 \UART_TXFF/U292 ( .A(\UART_TXFF/iFIFOMem[60][6] ), .B(iDIN[6]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1778 ) );
notech_mux2 \UART_TXFF/U291 ( .A(\UART_TXFF/iFIFOMem[60][7] ), .B(iDIN[7]),
.S(\UART_TXFF/n249 ), .Z(\UART_TXFF/n1779 ) );
notech_and2 \UART_TXFF/U290 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n248 ),
.Z(\UART_TXFF/n247 ) );
notech_mux2 \UART_TXFF/U289 ( .A(\UART_TXFF/iFIFOMem[61][0] ), .B(
\UART_TXFF/n4 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1780 ) );
notech_mux2 \UART_TXFF/U288 ( .A(\UART_TXFF/iFIFOMem[61][1] ), .B(
\UART_TXFF/n8 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1781 ) );
notech_mux2 \UART_TXFF/U287 ( .A(\UART_TXFF/iFIFOMem[61][2] ), .B(
\UART_TXFF/n12 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1782 ) );
notech_mux2 \UART_TXFF/U286 ( .A(\UART_TXFF/iFIFOMem[61][3] ), .B(
\UART_TXFF/n16 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1783 ) );
notech_mux2 \UART_TXFF/U285 ( .A(\UART_TXFF/iFIFOMem[61][4] ), .B(
\UART_TXFF/n20 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1784 ) );
notech_mux2 \UART_TXFF/U284 ( .A(\UART_TXFF/iFIFOMem[61][5] ), .B(
\UART_TXFF/n24 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1785 ) );
notech_mux2 \UART_TXFF/U283 ( .A(\UART_TXFF/iFIFOMem[61][6] ), .B(
\UART_TXFF/n28 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1786 ) );
notech_mux2 \UART_TXFF/U282 ( .A(\UART_TXFF/iFIFOMem[61][7] ), .B(
\UART_TXFF/n32 ), .S(\UART_TXFF/n247 ), .Z(\UART_TXFF/n1787 ) );
notech_and2 \UART_TXFF/U281 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n246 ),
.Z(\UART_TXFF/n245 ) );
notech_mux2 \UART_TXFF/U280 ( .A(\UART_TXFF/iFIFOMem[62][0] ), .B(
\UART_TXFF/n3 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1788 ) );
notech_mux2 \UART_TXFF/U279 ( .A(\UART_TXFF/iFIFOMem[62][1] ), .B(
\UART_TXFF/n7 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1789 ) );
notech_mux2 \UART_TXFF/U278 ( .A(\UART_TXFF/iFIFOMem[62][2] ), .B(
\UART_TXFF/n11 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1790 ) );
notech_mux2 \UART_TXFF/U277 ( .A(\UART_TXFF/iFIFOMem[62][3] ), .B(
\UART_TXFF/n15 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1791 ) );
notech_mux2 \UART_TXFF/U276 ( .A(\UART_TXFF/iFIFOMem[62][4] ), .B(
\UART_TXFF/n19 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1792 ) );
notech_mux2 \UART_TXFF/U275 ( .A(\UART_TXFF/iFIFOMem[62][5] ), .B(
\UART_TXFF/n23 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1793 ) );
notech_mux2 \UART_TXFF/U274 ( .A(\UART_TXFF/iFIFOMem[62][6] ), .B(
\UART_TXFF/n27 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1794 ) );
notech_mux2 \UART_TXFF/U273 ( .A(\UART_TXFF/iFIFOMem[62][7] ), .B(
\UART_TXFF/n31 ), .S(\UART_TXFF/n245 ), .Z(\UART_TXFF/n1795 ) );
notech_and2 \UART_TXFF/U272 ( .A(\UART_TXFF/n243 ), .B(\UART_TXFF/n244 ),
.Z(\UART_TXFF/n242 ) );
notech_mux2 \UART_TXFF/U271 ( .A(\UART_TXFF/iFIFOMem[63][0] ), .B(
\UART_TXFF/n2 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1796 ) );
notech_mux2 \UART_TXFF/U270 ( .A(\UART_TXFF/iFIFOMem[63][1] ), .B(
\UART_TXFF/n6 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1797 ) );
notech_mux2 \UART_TXFF/U269 ( .A(\UART_TXFF/iFIFOMem[63][2] ), .B(
\UART_TXFF/n10 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1798 ) );
notech_mux2 \UART_TXFF/U268 ( .A(\UART_TXFF/iFIFOMem[63][3] ), .B(
\UART_TXFF/n14 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1799 ) );
notech_mux2 \UART_TXFF/U267 ( .A(\UART_TXFF/iFIFOMem[63][4] ), .B(
\UART_TXFF/n18 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1800 ) );
notech_mux2 \UART_TXFF/U266 ( .A(\UART_TXFF/iFIFOMem[63][5] ), .B(
\UART_TXFF/n22 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1801 ) );
notech_mux2 \UART_TXFF/U265 ( .A(\UART_TXFF/iFIFOMem[63][6] ), .B(
\UART_TXFF/n26 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1802 ) );
notech_mux2 \UART_TXFF/U264 ( .A(\UART_TXFF/iFIFOMem[63][7] ), .B(
\UART_TXFF/n30 ), .S(\UART_TXFF/n242 ), .Z(\UART_TXFF/n1803 ) );
notech_and2 \UART_TXFF/U263 ( .A(iTXFIFORead), .B(n520), .Z(
\UART_TXFF/n240 ) );
notech_or2 \UART_TXFF/U262 ( .A(\UART_TXFF/n240 ), .B(iFCR[2]), .Z(
\UART_TXFF/n212 ) );
notech_inv \UART_TXFF/U261 ( .A(\UART_TXFF/N17 ), .Z(\UART_TXFF/n238 ) );
notech_nand2 \UART_TXFF/U260 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n228 ),
.Z(\UART_TXFF/n211 ) );
notech_inv \UART_TXFF/U259 ( .A(\UART_TXFF/N37 ), .Z(\UART_TXFF/n239 ) );
notech_nao4 \UART_TXFF/U258 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n238 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n239 ), .Z(\UART_TXFF/n1804 ) );
notech_inv \UART_TXFF/U257 ( .A(\UART_TXFF/N36 ), .Z(\UART_TXFF/n237 ) );
notech_nao4 \UART_TXFF/U256 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n236 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n237 ), .Z(\UART_TXFF/n1805 ) );
notech_inv \UART_TXFF/U255 ( .A(\UART_TXFF/N35 ), .Z(\UART_TXFF/n235 ) );
notech_nao4 \UART_TXFF/U254 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n234 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n235 ), .Z(\UART_TXFF/n1806 ) );
notech_inv \UART_TXFF/U253 ( .A(\UART_TXFF/N34 ), .Z(\UART_TXFF/n233 ) );
notech_nao4 \UART_TXFF/U252 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n232 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n233 ), .Z(\UART_TXFF/n1807 ) );
notech_inv \UART_TXFF/U251 ( .A(\UART_TXFF/N33 ), .Z(\UART_TXFF/n231 ) );
notech_nao4 \UART_TXFF/U250 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n42 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n231 ), .Z(\UART_TXFF/n1808 ) );
notech_inv \UART_TXFF/U249 ( .A(\UART_TXFF/iRDAddr[6] ), .Z(
\UART_TXFF/n229 ) );
notech_inv \UART_TXFF/U248 ( .A(\UART_TXFF/N38 ), .Z(\UART_TXFF/n230 ) );
notech_nao4 \UART_TXFF/U247 ( .A(\UART_TXFF/n212 ), .B(\UART_TXFF/n229 ),
.C(\UART_TXFF/n211 ), .D(\UART_TXFF/n230 ), .Z(\UART_TXFF/n1809 ) );
notech_inv \UART_TXFF/U246 ( .A(\UART_TXFF/iWRAddr[5] ), .Z(
\UART_TXFF/n226 ) );
notech_nand2 \UART_TXFF/U245 ( .A(\UART_TXFF/n214 ), .B(\UART_TXFF/n228 ),
.Z(\UART_TXFF/n215 ) );
notech_inv \UART_TXFF/U244 ( .A(\UART_TXFF/N29 ), .Z(\UART_TXFF/n227 ) );
notech_nao4 \UART_TXFF/U243 ( .A(\UART_TXFF/n226 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n227 ), .Z(\UART_TXFF/n1810 ) );
notech_inv \UART_TXFF/U242 ( .A(\UART_TXFF/iWRAddr[4] ), .Z(
\UART_TXFF/n224 ) );
notech_inv \UART_TXFF/U241 ( .A(\UART_TXFF/N28 ), .Z(\UART_TXFF/n225 ) );
notech_nao4 \UART_TXFF/U240 ( .A(\UART_TXFF/n224 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n225 ), .Z(\UART_TXFF/n1811 ) );
notech_inv \UART_TXFF/U239 ( .A(\UART_TXFF/N27 ), .Z(\UART_TXFF/n223 ) );
notech_nao4 \UART_TXFF/U238 ( .A(\UART_TXFF/n222 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n223 ), .Z(\UART_TXFF/n1812 ) );
notech_inv \UART_TXFF/U237 ( .A(\UART_TXFF/N26 ), .Z(\UART_TXFF/n221 ) );
notech_nao4 \UART_TXFF/U236 ( .A(\UART_TXFF/n220 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n221 ), .Z(\UART_TXFF/n1813 ) );
notech_inv \UART_TXFF/U235 ( .A(\UART_TXFF/N25 ), .Z(\UART_TXFF/n219 ) );
notech_nao4 \UART_TXFF/U234 ( .A(\UART_TXFF/n218 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n219 ), .Z(\UART_TXFF/n1814 ) );
notech_mux2 \UART_TXFF/U233 ( .A(\UART_TXFF/n215 ), .B(\UART_TXFF/n214 ),
.S(\UART_TXFF/iWRAddr[0] ), .Z(\UART_TXFF/n217 ) );
notech_inv \UART_TXFF/U232 ( .A(\UART_TXFF/n217 ), .Z(\UART_TXFF/n1815 ) );
notech_inv \UART_TXFF/U231 ( .A(\UART_TXFF/N30 ), .Z(\UART_TXFF/n216 ) );
notech_nao4 \UART_TXFF/U230 ( .A(\UART_TXFF/n213 ), .B(\UART_TXFF/n214 ),
.C(\UART_TXFF/n215 ), .D(\UART_TXFF/n216 ), .Z(\UART_TXFF/n1816 ) );
notech_mux2 \UART_TXFF/U229 ( .A(\UART_TXFF/n211 ), .B(\UART_TXFF/n212 ),
.S(\UART_TXFF/N12 ), .Z(\UART_TXFF/n210 ) );
notech_inv \UART_TXFF/U228 ( .A(\UART_TXFF/n210 ), .Z(\UART_TXFF/n1817 ) );
notech_mux2 \UART_TXFF/U227 ( .A(\UART_TXFF/N130 ), .B(iTXFIFOQ[0]), .S(RST), .Z(\UART_TXFF/n758 ) );
notech_mux2 \UART_TXFF/U226 ( .A(\UART_TXFF/N129 ), .B(iTXFIFOQ[1]), .S(RST), .Z(\UART_TXFF/n760 ) );
notech_mux2 \UART_TXFF/U225 ( .A(\UART_TXFF/N128 ), .B(iTXFIFOQ[2]), .S(RST), .Z(\UART_TXFF/n762 ) );
notech_mux2 \UART_TXFF/U224 ( .A(\UART_TXFF/N127 ), .B(iTXFIFOQ[3]), .S(RST), .Z(\UART_TXFF/n764 ) );
notech_mux2 \UART_TXFF/U223 ( .A(\UART_TXFF/N126 ), .B(iTXFIFOQ[4]), .S(RST), .Z(\UART_TXFF/n766 ) );
notech_mux2 \UART_TXFF/U222 ( .A(\UART_TXFF/N125 ), .B(iTXFIFOQ[5]), .S(RST), .Z(\UART_TXFF/n768 ) );
notech_mux2 \UART_TXFF/U221 ( .A(\UART_TXFF/N124 ), .B(iTXFIFOQ[6]), .S(RST), .Z(\UART_TXFF/n770 ) );
notech_mux2 \UART_TXFF/U220 ( .A(\UART_TXFF/N123 ), .B(iTXFIFOQ[7]), .S(RST), .Z(\UART_TXFF/n772 ) );
notech_mux4 \UART_TXFF/U219 ( .A(\UART_TXFF/n209 ), .B(\UART_TXFF/n199 ),
.C(\UART_TXFF/n204 ), .D(\UART_TXFF/n194 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N123 ) );
notech_mux4 \UART_TXFF/U218 ( .A(\UART_TXFF/n208 ), .B(\UART_TXFF/n206 ),
.C(\UART_TXFF/n207 ), .D(\UART_TXFF/n205 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n209 ) );
notech_mux4 \UART_TXFF/U217 ( .A(\UART_TXFF/iFIFOMem[0][7] ), .B(
\UART_TXFF/iFIFOMem[2][7] ), .C(\UART_TXFF/iFIFOMem[1][7] ), .D(
\UART_TXFF/iFIFOMem[3][7] ), .S0(\UART_TXFF/N13 ), .S1(\UART_TXFF/N12 ), .Z(\UART_TXFF/n208 ) );
notech_mux4 \UART_TXFF/U216 ( .A(\UART_TXFF/iFIFOMem[4][7] ), .B(
\UART_TXFF/iFIFOMem[6][7] ), .C(\UART_TXFF/iFIFOMem[5][7] ), .D(
\UART_TXFF/iFIFOMem[7][7] ), .S0(\UART_TXFF/N13 ), .S1(\UART_TXFF/N12 ), .Z(\UART_TXFF/n207 ) );
notech_mux4 \UART_TXFF/U215 ( .A(\UART_TXFF/iFIFOMem[8][7] ), .B(
\UART_TXFF/iFIFOMem[10][7] ), .C(\UART_TXFF/iFIFOMem[9][7] ), .D(
\UART_TXFF/iFIFOMem[11][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n206 ) );
notech_mux4 \UART_TXFF/U214 ( .A(\UART_TXFF/iFIFOMem[12][7] ), .B(
\UART_TXFF/iFIFOMem[14][7] ), .C(\UART_TXFF/iFIFOMem[13][7] ), .D(
\UART_TXFF/iFIFOMem[15][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n205 ) );
notech_mux4 \UART_TXFF/U213 ( .A(\UART_TXFF/n203 ), .B(\UART_TXFF/n201 ),
.C(\UART_TXFF/n202 ), .D(\UART_TXFF/n200 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n204 ) );
notech_mux4 \UART_TXFF/U212 ( .A(\UART_TXFF/iFIFOMem[16][7] ), .B(
\UART_TXFF/iFIFOMem[18][7] ), .C(\UART_TXFF/iFIFOMem[17][7] ), .D(
\UART_TXFF/iFIFOMem[19][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n203 ) );
notech_mux4 \UART_TXFF/U211 ( .A(\UART_TXFF/iFIFOMem[20][7] ), .B(
\UART_TXFF/iFIFOMem[22][7] ), .C(\UART_TXFF/iFIFOMem[21][7] ), .D(
\UART_TXFF/iFIFOMem[23][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n202 ) );
notech_mux4 \UART_TXFF/U210 ( .A(\UART_TXFF/iFIFOMem[24][7] ), .B(
\UART_TXFF/iFIFOMem[26][7] ), .C(\UART_TXFF/iFIFOMem[25][7] ), .D(
\UART_TXFF/iFIFOMem[27][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n201 ) );
notech_mux4 \UART_TXFF/U209 ( .A(\UART_TXFF/iFIFOMem[28][7] ), .B(
\UART_TXFF/iFIFOMem[30][7] ), .C(\UART_TXFF/iFIFOMem[29][7] ), .D(
\UART_TXFF/iFIFOMem[31][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n200 ) );
notech_mux4 \UART_TXFF/U208 ( .A(\UART_TXFF/n198 ), .B(\UART_TXFF/n196 ),
.C(\UART_TXFF/n197 ), .D(\UART_TXFF/n195 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n199 ) );
notech_mux4 \UART_TXFF/U207 ( .A(\UART_TXFF/iFIFOMem[32][7] ), .B(
\UART_TXFF/iFIFOMem[34][7] ), .C(\UART_TXFF/iFIFOMem[33][7] ), .D(
\UART_TXFF/iFIFOMem[35][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n198 ) );
notech_mux4 \UART_TXFF/U206 ( .A(\UART_TXFF/iFIFOMem[36][7] ), .B(
\UART_TXFF/iFIFOMem[38][7] ), .C(\UART_TXFF/iFIFOMem[37][7] ), .D(
\UART_TXFF/iFIFOMem[39][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n197 ) );
notech_mux4 \UART_TXFF/U205 ( .A(\UART_TXFF/iFIFOMem[40][7] ), .B(
\UART_TXFF/iFIFOMem[42][7] ), .C(\UART_TXFF/iFIFOMem[41][7] ), .D(
\UART_TXFF/iFIFOMem[43][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n196 ) );
notech_mux4 \UART_TXFF/U204 ( .A(\UART_TXFF/iFIFOMem[44][7] ), .B(
\UART_TXFF/iFIFOMem[46][7] ), .C(\UART_TXFF/iFIFOMem[45][7] ), .D(
\UART_TXFF/iFIFOMem[47][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n195 ) );
notech_mux4 \UART_TXFF/U203 ( .A(\UART_TXFF/n193 ), .B(\UART_TXFF/n191 ),
.C(\UART_TXFF/n192 ), .D(\UART_TXFF/n190 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n194 ) );
notech_mux4 \UART_TXFF/U202 ( .A(\UART_TXFF/iFIFOMem[48][7] ), .B(
\UART_TXFF/iFIFOMem[50][7] ), .C(\UART_TXFF/iFIFOMem[49][7] ), .D(
\UART_TXFF/iFIFOMem[51][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n193 ) );
notech_mux4 \UART_TXFF/U201 ( .A(\UART_TXFF/iFIFOMem[52][7] ), .B(
\UART_TXFF/iFIFOMem[54][7] ), .C(\UART_TXFF/iFIFOMem[53][7] ), .D(
\UART_TXFF/iFIFOMem[55][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n192 ) );
notech_mux4 \UART_TXFF/U200 ( .A(\UART_TXFF/iFIFOMem[56][7] ), .B(
\UART_TXFF/iFIFOMem[58][7] ), .C(\UART_TXFF/iFIFOMem[57][7] ), .D(
\UART_TXFF/iFIFOMem[59][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n191 ) );
notech_mux4 \UART_TXFF/U199 ( .A(\UART_TXFF/iFIFOMem[60][7] ), .B(
\UART_TXFF/iFIFOMem[62][7] ), .C(\UART_TXFF/iFIFOMem[61][7] ), .D(
\UART_TXFF/iFIFOMem[63][7] ), .S0(\UART_TXFF/N13 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n190 ) );
notech_mux4 \UART_TXFF/U198 ( .A(\UART_TXFF/n189 ), .B(\UART_TXFF/n179 ),
.C(\UART_TXFF/n184 ), .D(\UART_TXFF/n174 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N124 ) );
notech_mux4 \UART_TXFF/U197 ( .A(\UART_TXFF/n188 ), .B(\UART_TXFF/n186 ),
.C(\UART_TXFF/n187 ), .D(\UART_TXFF/n185 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n189 ) );
notech_mux4 \UART_TXFF/U196 ( .A(\UART_TXFF/iFIFOMem[0][6] ), .B(
\UART_TXFF/iFIFOMem[2][6] ), .C(\UART_TXFF/iFIFOMem[1][6] ), .D(
\UART_TXFF/iFIFOMem[3][6] ), .S0(\UART_TXFF/n41 ), .S1(\UART_TXFF/n48 ), .Z(\UART_TXFF/n188 ) );
notech_mux4 \UART_TXFF/U195 ( .A(\UART_TXFF/iFIFOMem[4][6] ), .B(
\UART_TXFF/iFIFOMem[6][6] ), .C(\UART_TXFF/iFIFOMem[5][6] ), .D(
\UART_TXFF/iFIFOMem[7][6] ), .S0(\UART_TXFF/n36 ), .S1(\UART_TXFF/n48 ), .Z(\UART_TXFF/n187 ) );
notech_mux4 \UART_TXFF/U194 ( .A(\UART_TXFF/iFIFOMem[8][6] ), .B(
\UART_TXFF/iFIFOMem[10][6] ), .C(\UART_TXFF/iFIFOMem[9][6] ), .D(
\UART_TXFF/iFIFOMem[11][6] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n186 ) );
notech_mux4 \UART_TXFF/U193 ( .A(\UART_TXFF/iFIFOMem[12][6] ), .B(
\UART_TXFF/iFIFOMem[14][6] ), .C(\UART_TXFF/iFIFOMem[13][6] ), .D(
\UART_TXFF/iFIFOMem[15][6] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n185 ) );
notech_mux4 \UART_TXFF/U192 ( .A(\UART_TXFF/n183 ), .B(\UART_TXFF/n181 ),
.C(\UART_TXFF/n182 ), .D(\UART_TXFF/n180 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n184 ) );
notech_mux4 \UART_TXFF/U191 ( .A(\UART_TXFF/iFIFOMem[16][6] ), .B(
\UART_TXFF/iFIFOMem[18][6] ), .C(\UART_TXFF/iFIFOMem[17][6] ), .D(
\UART_TXFF/iFIFOMem[19][6] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n183 ) );
notech_mux4 \UART_TXFF/U190 ( .A(\UART_TXFF/iFIFOMem[20][6] ), .B(
\UART_TXFF/iFIFOMem[22][6] ), .C(\UART_TXFF/iFIFOMem[21][6] ), .D(
\UART_TXFF/iFIFOMem[23][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n182 ) );
notech_mux4 \UART_TXFF/U189 ( .A(\UART_TXFF/iFIFOMem[24][6] ), .B(
\UART_TXFF/iFIFOMem[26][6] ), .C(\UART_TXFF/iFIFOMem[25][6] ), .D(
\UART_TXFF/iFIFOMem[27][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n181 ) );
notech_mux4 \UART_TXFF/U188 ( .A(\UART_TXFF/iFIFOMem[28][6] ), .B(
\UART_TXFF/iFIFOMem[30][6] ), .C(\UART_TXFF/iFIFOMem[29][6] ), .D(
\UART_TXFF/iFIFOMem[31][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n180 ) );
notech_mux4 \UART_TXFF/U187 ( .A(\UART_TXFF/n178 ), .B(\UART_TXFF/n176 ),
.C(\UART_TXFF/n177 ), .D(\UART_TXFF/n175 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n179 ) );
notech_mux4 \UART_TXFF/U186 ( .A(\UART_TXFF/iFIFOMem[32][6] ), .B(
\UART_TXFF/iFIFOMem[34][6] ), .C(\UART_TXFF/iFIFOMem[33][6] ), .D(
\UART_TXFF/iFIFOMem[35][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n178 ) );
notech_mux4 \UART_TXFF/U185 ( .A(\UART_TXFF/iFIFOMem[36][6] ), .B(
\UART_TXFF/iFIFOMem[38][6] ), .C(\UART_TXFF/iFIFOMem[37][6] ), .D(
\UART_TXFF/iFIFOMem[39][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n177 ) );
notech_mux4 \UART_TXFF/U184 ( .A(\UART_TXFF/iFIFOMem[40][6] ), .B(
\UART_TXFF/iFIFOMem[42][6] ), .C(\UART_TXFF/iFIFOMem[41][6] ), .D(
\UART_TXFF/iFIFOMem[43][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n176 ) );
notech_mux4 \UART_TXFF/U183 ( .A(\UART_TXFF/iFIFOMem[44][6] ), .B(
\UART_TXFF/iFIFOMem[46][6] ), .C(\UART_TXFF/iFIFOMem[45][6] ), .D(
\UART_TXFF/iFIFOMem[47][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n175 ) );
notech_mux4 \UART_TXFF/U182 ( .A(\UART_TXFF/n173 ), .B(\UART_TXFF/n171 ),
.C(\UART_TXFF/n172 ), .D(\UART_TXFF/n170 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n174 ) );
notech_mux4 \UART_TXFF/U181 ( .A(\UART_TXFF/iFIFOMem[48][6] ), .B(
\UART_TXFF/iFIFOMem[50][6] ), .C(\UART_TXFF/iFIFOMem[49][6] ), .D(
\UART_TXFF/iFIFOMem[51][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n173 ) );
notech_mux4 \UART_TXFF/U180 ( .A(\UART_TXFF/iFIFOMem[52][6] ), .B(
\UART_TXFF/iFIFOMem[54][6] ), .C(\UART_TXFF/iFIFOMem[53][6] ), .D(
\UART_TXFF/iFIFOMem[55][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n172 ) );
notech_mux4 \UART_TXFF/U179 ( .A(\UART_TXFF/iFIFOMem[56][6] ), .B(
\UART_TXFF/iFIFOMem[58][6] ), .C(\UART_TXFF/iFIFOMem[57][6] ), .D(
\UART_TXFF/iFIFOMem[59][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n171 ) );
notech_mux4 \UART_TXFF/U178 ( .A(\UART_TXFF/iFIFOMem[60][6] ), .B(
\UART_TXFF/iFIFOMem[62][6] ), .C(\UART_TXFF/iFIFOMem[61][6] ), .D(
\UART_TXFF/iFIFOMem[63][6] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n170 ) );
notech_mux4 \UART_TXFF/U177 ( .A(\UART_TXFF/n169 ), .B(\UART_TXFF/n159 ),
.C(\UART_TXFF/n164 ), .D(\UART_TXFF/n154 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N125 ) );
notech_mux4 \UART_TXFF/U176 ( .A(\UART_TXFF/n168 ), .B(\UART_TXFF/n166 ),
.C(\UART_TXFF/n167 ), .D(\UART_TXFF/n165 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n169 ) );
notech_mux4 \UART_TXFF/U175 ( .A(\UART_TXFF/iFIFOMem[0][5] ), .B(
\UART_TXFF/iFIFOMem[2][5] ), .C(\UART_TXFF/iFIFOMem[1][5] ), .D(
\UART_TXFF/iFIFOMem[3][5] ), .S0(\UART_TXFF/n41 ), .S1(\UART_TXFF/n47 ), .Z(\UART_TXFF/n168 ) );
notech_mux4 \UART_TXFF/U174 ( .A(\UART_TXFF/iFIFOMem[4][5] ), .B(
\UART_TXFF/iFIFOMem[6][5] ), .C(\UART_TXFF/iFIFOMem[5][5] ), .D(
\UART_TXFF/iFIFOMem[7][5] ), .S0(\UART_TXFF/n41 ), .S1(\UART_TXFF/n47 ), .Z(\UART_TXFF/n167 ) );
notech_mux4 \UART_TXFF/U173 ( .A(\UART_TXFF/iFIFOMem[8][5] ), .B(
\UART_TXFF/iFIFOMem[10][5] ), .C(\UART_TXFF/iFIFOMem[9][5] ), .D(
\UART_TXFF/iFIFOMem[11][5] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n166 ) );
notech_mux4 \UART_TXFF/U172 ( .A(\UART_TXFF/iFIFOMem[12][5] ), .B(
\UART_TXFF/iFIFOMem[14][5] ), .C(\UART_TXFF/iFIFOMem[13][5] ), .D(
\UART_TXFF/iFIFOMem[15][5] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n165 ) );
notech_mux4 \UART_TXFF/U171 ( .A(\UART_TXFF/n163 ), .B(\UART_TXFF/n161 ),
.C(\UART_TXFF/n162 ), .D(\UART_TXFF/n160 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n164 ) );
notech_mux4 \UART_TXFF/U170 ( .A(\UART_TXFF/iFIFOMem[16][5] ), .B(
\UART_TXFF/iFIFOMem[18][5] ), .C(\UART_TXFF/iFIFOMem[17][5] ), .D(
\UART_TXFF/iFIFOMem[19][5] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n163 ) );
notech_mux4 \UART_TXFF/U169 ( .A(\UART_TXFF/iFIFOMem[20][5] ), .B(
\UART_TXFF/iFIFOMem[22][5] ), .C(\UART_TXFF/iFIFOMem[21][5] ), .D(
\UART_TXFF/iFIFOMem[23][5] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n162 ) );
notech_mux4 \UART_TXFF/U168 ( .A(\UART_TXFF/iFIFOMem[24][5] ), .B(
\UART_TXFF/iFIFOMem[26][5] ), .C(\UART_TXFF/iFIFOMem[25][5] ), .D(
\UART_TXFF/iFIFOMem[27][5] ), .S0(\UART_TXFF/n41 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n161 ) );
notech_mux4 \UART_TXFF/U167 ( .A(\UART_TXFF/iFIFOMem[28][5] ), .B(
\UART_TXFF/iFIFOMem[30][5] ), .C(\UART_TXFF/iFIFOMem[29][5] ), .D(
\UART_TXFF/iFIFOMem[31][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n160 ) );
notech_mux4 \UART_TXFF/U166 ( .A(\UART_TXFF/n158 ), .B(\UART_TXFF/n156 ),
.C(\UART_TXFF/n157 ), .D(\UART_TXFF/n155 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n159 ) );
notech_mux4 \UART_TXFF/U165 ( .A(\UART_TXFF/iFIFOMem[32][5] ), .B(
\UART_TXFF/iFIFOMem[34][5] ), .C(\UART_TXFF/iFIFOMem[33][5] ), .D(
\UART_TXFF/iFIFOMem[35][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n158 ) );
notech_mux4 \UART_TXFF/U164 ( .A(\UART_TXFF/iFIFOMem[36][5] ), .B(
\UART_TXFF/iFIFOMem[38][5] ), .C(\UART_TXFF/iFIFOMem[37][5] ), .D(
\UART_TXFF/iFIFOMem[39][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n157 ) );
notech_mux4 \UART_TXFF/U163 ( .A(\UART_TXFF/iFIFOMem[40][5] ), .B(
\UART_TXFF/iFIFOMem[42][5] ), .C(\UART_TXFF/iFIFOMem[41][5] ), .D(
\UART_TXFF/iFIFOMem[43][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n156 ) );
notech_mux4 \UART_TXFF/U162 ( .A(\UART_TXFF/iFIFOMem[44][5] ), .B(
\UART_TXFF/iFIFOMem[46][5] ), .C(\UART_TXFF/iFIFOMem[45][5] ), .D(
\UART_TXFF/iFIFOMem[47][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n155 ) );
notech_mux4 \UART_TXFF/U161 ( .A(\UART_TXFF/n153 ), .B(\UART_TXFF/n151 ),
.C(\UART_TXFF/n152 ), .D(\UART_TXFF/n150 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n154 ) );
notech_mux4 \UART_TXFF/U160 ( .A(\UART_TXFF/iFIFOMem[48][5] ), .B(
\UART_TXFF/iFIFOMem[50][5] ), .C(\UART_TXFF/iFIFOMem[49][5] ), .D(
\UART_TXFF/iFIFOMem[51][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n153 ) );
notech_mux4 \UART_TXFF/U159 ( .A(\UART_TXFF/iFIFOMem[52][5] ), .B(
\UART_TXFF/iFIFOMem[54][5] ), .C(\UART_TXFF/iFIFOMem[53][5] ), .D(
\UART_TXFF/iFIFOMem[55][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n152 ) );
notech_mux4 \UART_TXFF/U158 ( .A(\UART_TXFF/iFIFOMem[56][5] ), .B(
\UART_TXFF/iFIFOMem[58][5] ), .C(\UART_TXFF/iFIFOMem[57][5] ), .D(
\UART_TXFF/iFIFOMem[59][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n151 ) );
notech_mux4 \UART_TXFF/U157 ( .A(\UART_TXFF/iFIFOMem[60][5] ), .B(
\UART_TXFF/iFIFOMem[62][5] ), .C(\UART_TXFF/iFIFOMem[61][5] ), .D(
\UART_TXFF/iFIFOMem[63][5] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n150 ) );
notech_mux4 \UART_TXFF/U156 ( .A(\UART_TXFF/n149 ), .B(\UART_TXFF/n139 ),
.C(\UART_TXFF/n144 ), .D(\UART_TXFF/n134 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N126 ) );
notech_mux4 \UART_TXFF/U155 ( .A(\UART_TXFF/n148 ), .B(\UART_TXFF/n146 ),
.C(\UART_TXFF/n147 ), .D(\UART_TXFF/n145 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n149 ) );
notech_mux4 \UART_TXFF/U154 ( .A(\UART_TXFF/iFIFOMem[0][4] ), .B(
\UART_TXFF/iFIFOMem[2][4] ), .C(\UART_TXFF/iFIFOMem[1][4] ), .D(
\UART_TXFF/iFIFOMem[3][4] ), .S0(\UART_TXFF/n40 ), .S1(\UART_TXFF/n46 ), .Z(\UART_TXFF/n148 ) );
notech_mux4 \UART_TXFF/U153 ( .A(\UART_TXFF/iFIFOMem[4][4] ), .B(
\UART_TXFF/iFIFOMem[6][4] ), .C(\UART_TXFF/iFIFOMem[5][4] ), .D(
\UART_TXFF/iFIFOMem[7][4] ), .S0(\UART_TXFF/n40 ), .S1(\UART_TXFF/n46 ), .Z(\UART_TXFF/n147 ) );
notech_mux4 \UART_TXFF/U152 ( .A(\UART_TXFF/iFIFOMem[8][4] ), .B(
\UART_TXFF/iFIFOMem[10][4] ), .C(\UART_TXFF/iFIFOMem[9][4] ), .D(
\UART_TXFF/iFIFOMem[11][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n146 ) );
notech_mux4 \UART_TXFF/U151 ( .A(\UART_TXFF/iFIFOMem[12][4] ), .B(
\UART_TXFF/iFIFOMem[14][4] ), .C(\UART_TXFF/iFIFOMem[13][4] ), .D(
\UART_TXFF/iFIFOMem[15][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n145 ) );
notech_mux4 \UART_TXFF/U150 ( .A(\UART_TXFF/n143 ), .B(\UART_TXFF/n141 ),
.C(\UART_TXFF/n142 ), .D(\UART_TXFF/n140 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n144 ) );
notech_mux4 \UART_TXFF/U149 ( .A(\UART_TXFF/iFIFOMem[16][4] ), .B(
\UART_TXFF/iFIFOMem[18][4] ), .C(\UART_TXFF/iFIFOMem[17][4] ), .D(
\UART_TXFF/iFIFOMem[19][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n143 ) );
notech_mux4 \UART_TXFF/U148 ( .A(\UART_TXFF/iFIFOMem[20][4] ), .B(
\UART_TXFF/iFIFOMem[22][4] ), .C(\UART_TXFF/iFIFOMem[21][4] ), .D(
\UART_TXFF/iFIFOMem[23][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n142 ) );
notech_mux4 \UART_TXFF/U147 ( .A(\UART_TXFF/iFIFOMem[24][4] ), .B(
\UART_TXFF/iFIFOMem[26][4] ), .C(\UART_TXFF/iFIFOMem[25][4] ), .D(
\UART_TXFF/iFIFOMem[27][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n141 ) );
notech_mux4 \UART_TXFF/U146 ( .A(\UART_TXFF/iFIFOMem[28][4] ), .B(
\UART_TXFF/iFIFOMem[30][4] ), .C(\UART_TXFF/iFIFOMem[29][4] ), .D(
\UART_TXFF/iFIFOMem[31][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n140 ) );
notech_mux4 \UART_TXFF/U145 ( .A(\UART_TXFF/n138 ), .B(\UART_TXFF/n136 ),
.C(\UART_TXFF/n137 ), .D(\UART_TXFF/n135 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n139 ) );
notech_mux4 \UART_TXFF/U144 ( .A(\UART_TXFF/iFIFOMem[32][4] ), .B(
\UART_TXFF/iFIFOMem[34][4] ), .C(\UART_TXFF/iFIFOMem[33][4] ), .D(
\UART_TXFF/iFIFOMem[35][4] ), .S0(\UART_TXFF/n40 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n138 ) );
notech_mux4 \UART_TXFF/U143 ( .A(\UART_TXFF/iFIFOMem[36][4] ), .B(
\UART_TXFF/iFIFOMem[38][4] ), .C(\UART_TXFF/iFIFOMem[37][4] ), .D(
\UART_TXFF/iFIFOMem[39][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n46 ), .Z(\UART_TXFF/n137 ) );
notech_mux4 \UART_TXFF/U142 ( .A(\UART_TXFF/iFIFOMem[40][4] ), .B(
\UART_TXFF/iFIFOMem[42][4] ), .C(\UART_TXFF/iFIFOMem[41][4] ), .D(
\UART_TXFF/iFIFOMem[43][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n136 ) );
notech_mux4 \UART_TXFF/U141 ( .A(\UART_TXFF/iFIFOMem[44][4] ), .B(
\UART_TXFF/iFIFOMem[46][4] ), .C(\UART_TXFF/iFIFOMem[45][4] ), .D(
\UART_TXFF/iFIFOMem[47][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n135 ) );
notech_mux4 \UART_TXFF/U140 ( .A(\UART_TXFF/n133 ), .B(\UART_TXFF/n131 ),
.C(\UART_TXFF/n132 ), .D(\UART_TXFF/n130 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n134 ) );
notech_mux4 \UART_TXFF/U139 ( .A(\UART_TXFF/iFIFOMem[48][4] ), .B(
\UART_TXFF/iFIFOMem[50][4] ), .C(\UART_TXFF/iFIFOMem[49][4] ), .D(
\UART_TXFF/iFIFOMem[51][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n133 ) );
notech_mux4 \UART_TXFF/U138 ( .A(\UART_TXFF/iFIFOMem[52][4] ), .B(
\UART_TXFF/iFIFOMem[54][4] ), .C(\UART_TXFF/iFIFOMem[53][4] ), .D(
\UART_TXFF/iFIFOMem[55][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n132 ) );
notech_mux4 \UART_TXFF/U137 ( .A(\UART_TXFF/iFIFOMem[56][4] ), .B(
\UART_TXFF/iFIFOMem[58][4] ), .C(\UART_TXFF/iFIFOMem[57][4] ), .D(
\UART_TXFF/iFIFOMem[59][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n131 ) );
notech_mux4 \UART_TXFF/U136 ( .A(\UART_TXFF/iFIFOMem[60][4] ), .B(
\UART_TXFF/iFIFOMem[62][4] ), .C(\UART_TXFF/iFIFOMem[61][4] ), .D(
\UART_TXFF/iFIFOMem[63][4] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n130 ) );
notech_mux4 \UART_TXFF/U135 ( .A(\UART_TXFF/n129 ), .B(\UART_TXFF/n119 ),
.C(\UART_TXFF/n124 ), .D(\UART_TXFF/n114 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N127 ) );
notech_mux4 \UART_TXFF/U134 ( .A(\UART_TXFF/n128 ), .B(\UART_TXFF/n126 ),
.C(\UART_TXFF/n127 ), .D(\UART_TXFF/n125 ), .S0(\UART_TXFF/n35 ), .S1(
\UART_TXFF/n34 ), .Z(\UART_TXFF/n129 ) );
notech_mux4 \UART_TXFF/U133 ( .A(\UART_TXFF/iFIFOMem[0][3] ), .B(
\UART_TXFF/iFIFOMem[2][3] ), .C(\UART_TXFF/iFIFOMem[1][3] ), .D(
\UART_TXFF/iFIFOMem[3][3] ), .S0(\UART_TXFF/n39 ), .S1(\UART_TXFF/n45 ), .Z(\UART_TXFF/n128 ) );
notech_mux4 \UART_TXFF/U132 ( .A(\UART_TXFF/iFIFOMem[4][3] ), .B(
\UART_TXFF/iFIFOMem[6][3] ), .C(\UART_TXFF/iFIFOMem[5][3] ), .D(
\UART_TXFF/iFIFOMem[7][3] ), .S0(\UART_TXFF/n39 ), .S1(\UART_TXFF/n45 ), .Z(\UART_TXFF/n127 ) );
notech_mux4 \UART_TXFF/U131 ( .A(\UART_TXFF/iFIFOMem[8][3] ), .B(
\UART_TXFF/iFIFOMem[10][3] ), .C(\UART_TXFF/iFIFOMem[9][3] ), .D(
\UART_TXFF/iFIFOMem[11][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n126 ) );
notech_mux4 \UART_TXFF/U130 ( .A(\UART_TXFF/iFIFOMem[12][3] ), .B(
\UART_TXFF/iFIFOMem[14][3] ), .C(\UART_TXFF/iFIFOMem[13][3] ), .D(
\UART_TXFF/iFIFOMem[15][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n125 ) );
notech_mux4 \UART_TXFF/U129 ( .A(\UART_TXFF/n123 ), .B(\UART_TXFF/n121 ),
.C(\UART_TXFF/n122 ), .D(\UART_TXFF/n120 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n124 ) );
notech_mux4 \UART_TXFF/U128 ( .A(\UART_TXFF/iFIFOMem[16][3] ), .B(
\UART_TXFF/iFIFOMem[18][3] ), .C(\UART_TXFF/iFIFOMem[17][3] ), .D(
\UART_TXFF/iFIFOMem[19][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n123 ) );
notech_mux4 \UART_TXFF/U127 ( .A(\UART_TXFF/iFIFOMem[20][3] ), .B(
\UART_TXFF/iFIFOMem[22][3] ), .C(\UART_TXFF/iFIFOMem[21][3] ), .D(
\UART_TXFF/iFIFOMem[23][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n122 ) );
notech_mux4 \UART_TXFF/U126 ( .A(\UART_TXFF/iFIFOMem[24][3] ), .B(
\UART_TXFF/iFIFOMem[26][3] ), .C(\UART_TXFF/iFIFOMem[25][3] ), .D(
\UART_TXFF/iFIFOMem[27][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n121 ) );
notech_mux4 \UART_TXFF/U125 ( .A(\UART_TXFF/iFIFOMem[28][3] ), .B(
\UART_TXFF/iFIFOMem[30][3] ), .C(\UART_TXFF/iFIFOMem[29][3] ), .D(
\UART_TXFF/iFIFOMem[31][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n120 ) );
notech_mux4 \UART_TXFF/U124 ( .A(\UART_TXFF/n118 ), .B(\UART_TXFF/n116 ),
.C(\UART_TXFF/n117 ), .D(\UART_TXFF/n115 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n119 ) );
notech_mux4 \UART_TXFF/U123 ( .A(\UART_TXFF/iFIFOMem[32][3] ), .B(
\UART_TXFF/iFIFOMem[34][3] ), .C(\UART_TXFF/iFIFOMem[33][3] ), .D(
\UART_TXFF/iFIFOMem[35][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n118 ) );
notech_mux4 \UART_TXFF/U122 ( .A(\UART_TXFF/iFIFOMem[36][3] ), .B(
\UART_TXFF/iFIFOMem[38][3] ), .C(\UART_TXFF/iFIFOMem[37][3] ), .D(
\UART_TXFF/iFIFOMem[39][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n117 ) );
notech_mux4 \UART_TXFF/U121 ( .A(\UART_TXFF/iFIFOMem[40][3] ), .B(
\UART_TXFF/iFIFOMem[42][3] ), .C(\UART_TXFF/iFIFOMem[41][3] ), .D(
\UART_TXFF/iFIFOMem[43][3] ), .S0(\UART_TXFF/n39 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n116 ) );
notech_mux4 \UART_TXFF/U120 ( .A(\UART_TXFF/iFIFOMem[44][3] ), .B(
\UART_TXFF/iFIFOMem[46][3] ), .C(\UART_TXFF/iFIFOMem[45][3] ), .D(
\UART_TXFF/iFIFOMem[47][3] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n115 ) );
notech_mux4 \UART_TXFF/U119 ( .A(\UART_TXFF/n113 ), .B(\UART_TXFF/n111 ),
.C(\UART_TXFF/n112 ), .D(\UART_TXFF/n110 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n114 ) );
notech_mux4 \UART_TXFF/U118 ( .A(\UART_TXFF/iFIFOMem[48][3] ), .B(
\UART_TXFF/iFIFOMem[50][3] ), .C(\UART_TXFF/iFIFOMem[49][3] ), .D(
\UART_TXFF/iFIFOMem[51][3] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n113 ) );
notech_mux4 \UART_TXFF/U117 ( .A(\UART_TXFF/iFIFOMem[52][3] ), .B(
\UART_TXFF/iFIFOMem[54][3] ), .C(\UART_TXFF/iFIFOMem[53][3] ), .D(
\UART_TXFF/iFIFOMem[55][3] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n112 ) );
notech_mux4 \UART_TXFF/U116 ( .A(\UART_TXFF/iFIFOMem[56][3] ), .B(
\UART_TXFF/iFIFOMem[58][3] ), .C(\UART_TXFF/iFIFOMem[57][3] ), .D(
\UART_TXFF/iFIFOMem[59][3] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n111 ) );
notech_mux4 \UART_TXFF/U115 ( .A(\UART_TXFF/iFIFOMem[60][3] ), .B(
\UART_TXFF/iFIFOMem[62][3] ), .C(\UART_TXFF/iFIFOMem[61][3] ), .D(
\UART_TXFF/iFIFOMem[63][3] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n110 ) );
notech_mux4 \UART_TXFF/U114 ( .A(\UART_TXFF/n109 ), .B(\UART_TXFF/n99 ),
.C(\UART_TXFF/n104 ), .D(\UART_TXFF/n94 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N128 ) );
notech_mux4 \UART_TXFF/U113 ( .A(\UART_TXFF/n108 ), .B(\UART_TXFF/n106 ),
.C(\UART_TXFF/n107 ), .D(\UART_TXFF/n105 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n109 ) );
notech_mux4 \UART_TXFF/U112 ( .A(\UART_TXFF/iFIFOMem[0][2] ), .B(
\UART_TXFF/iFIFOMem[2][2] ), .C(\UART_TXFF/iFIFOMem[1][2] ), .D(
\UART_TXFF/iFIFOMem[3][2] ), .S0(\UART_TXFF/n38 ), .S1(\UART_TXFF/n44 ), .Z(\UART_TXFF/n108 ) );
notech_mux4 \UART_TXFF/U111 ( .A(\UART_TXFF/iFIFOMem[4][2] ), .B(
\UART_TXFF/iFIFOMem[6][2] ), .C(\UART_TXFF/iFIFOMem[5][2] ), .D(
\UART_TXFF/iFIFOMem[7][2] ), .S0(\UART_TXFF/n38 ), .S1(\UART_TXFF/n44 ), .Z(\UART_TXFF/n107 ) );
notech_mux4 \UART_TXFF/U110 ( .A(\UART_TXFF/iFIFOMem[8][2] ), .B(
\UART_TXFF/iFIFOMem[10][2] ), .C(\UART_TXFF/iFIFOMem[9][2] ), .D(
\UART_TXFF/iFIFOMem[11][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n106 ) );
notech_mux4 \UART_TXFF/U109 ( .A(\UART_TXFF/iFIFOMem[12][2] ), .B(
\UART_TXFF/iFIFOMem[14][2] ), .C(\UART_TXFF/iFIFOMem[13][2] ), .D(
\UART_TXFF/iFIFOMem[15][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n105 ) );
notech_mux4 \UART_TXFF/U108 ( .A(\UART_TXFF/n103 ), .B(\UART_TXFF/n101 ),
.C(\UART_TXFF/n102 ), .D(\UART_TXFF/n100 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n104 ) );
notech_mux4 \UART_TXFF/U107 ( .A(\UART_TXFF/iFIFOMem[16][2] ), .B(
\UART_TXFF/iFIFOMem[18][2] ), .C(\UART_TXFF/iFIFOMem[17][2] ), .D(
\UART_TXFF/iFIFOMem[19][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n103 ) );
notech_mux4 \UART_TXFF/U106 ( .A(\UART_TXFF/iFIFOMem[20][2] ), .B(
\UART_TXFF/iFIFOMem[22][2] ), .C(\UART_TXFF/iFIFOMem[21][2] ), .D(
\UART_TXFF/iFIFOMem[23][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n102 ) );
notech_mux4 \UART_TXFF/U105 ( .A(\UART_TXFF/iFIFOMem[24][2] ), .B(
\UART_TXFF/iFIFOMem[26][2] ), .C(\UART_TXFF/iFIFOMem[25][2] ), .D(
\UART_TXFF/iFIFOMem[27][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n101 ) );
notech_mux4 \UART_TXFF/U104 ( .A(\UART_TXFF/iFIFOMem[28][2] ), .B(
\UART_TXFF/iFIFOMem[30][2] ), .C(\UART_TXFF/iFIFOMem[29][2] ), .D(
\UART_TXFF/iFIFOMem[31][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n100 ) );
notech_mux4 \UART_TXFF/U103 ( .A(\UART_TXFF/n98 ), .B(\UART_TXFF/n96 ), .C(
\UART_TXFF/n97 ), .D(\UART_TXFF/n95 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n99 ) );
notech_mux4 \UART_TXFF/U102 ( .A(\UART_TXFF/iFIFOMem[32][2] ), .B(
\UART_TXFF/iFIFOMem[34][2] ), .C(\UART_TXFF/iFIFOMem[33][2] ), .D(
\UART_TXFF/iFIFOMem[35][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n98 ) );
notech_mux4 \UART_TXFF/U101 ( .A(\UART_TXFF/iFIFOMem[36][2] ), .B(
\UART_TXFF/iFIFOMem[38][2] ), .C(\UART_TXFF/iFIFOMem[37][2] ), .D(
\UART_TXFF/iFIFOMem[39][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n97 ) );
notech_mux4 \UART_TXFF/U100 ( .A(\UART_TXFF/iFIFOMem[40][2] ), .B(
\UART_TXFF/iFIFOMem[42][2] ), .C(\UART_TXFF/iFIFOMem[41][2] ), .D(
\UART_TXFF/iFIFOMem[43][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n96 ) );
notech_mux4 \UART_TXFF/U99 ( .A(\UART_TXFF/iFIFOMem[44][2] ), .B(
\UART_TXFF/iFIFOMem[46][2] ), .C(\UART_TXFF/iFIFOMem[45][2] ), .D(
\UART_TXFF/iFIFOMem[47][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n95 ) );
notech_mux4 \UART_TXFF/U98 ( .A(\UART_TXFF/n93 ), .B(\UART_TXFF/n91 ), .C(
\UART_TXFF/n92 ), .D(\UART_TXFF/n90 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n94 ) );
notech_mux4 \UART_TXFF/U97 ( .A(\UART_TXFF/iFIFOMem[48][2] ), .B(
\UART_TXFF/iFIFOMem[50][2] ), .C(\UART_TXFF/iFIFOMem[49][2] ), .D(
\UART_TXFF/iFIFOMem[51][2] ), .S0(\UART_TXFF/n38 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n93 ) );
notech_mux4 \UART_TXFF/U96 ( .A(\UART_TXFF/iFIFOMem[52][2] ), .B(
\UART_TXFF/iFIFOMem[54][2] ), .C(\UART_TXFF/iFIFOMem[53][2] ), .D(
\UART_TXFF/iFIFOMem[55][2] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n92 ) );
notech_mux4 \UART_TXFF/U95 ( .A(\UART_TXFF/iFIFOMem[56][2] ), .B(
\UART_TXFF/iFIFOMem[58][2] ), .C(\UART_TXFF/iFIFOMem[57][2] ), .D(
\UART_TXFF/iFIFOMem[59][2] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n91 ) );
notech_mux4 \UART_TXFF/U94 ( .A(\UART_TXFF/iFIFOMem[60][2] ), .B(
\UART_TXFF/iFIFOMem[62][2] ), .C(\UART_TXFF/iFIFOMem[61][2] ), .D(
\UART_TXFF/iFIFOMem[63][2] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n90 ) );
notech_mux4 \UART_TXFF/U93 ( .A(\UART_TXFF/n89 ), .B(\UART_TXFF/n79 ), .C(
\UART_TXFF/n84 ), .D(\UART_TXFF/n74 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N129 ) );
notech_mux4 \UART_TXFF/U92 ( .A(\UART_TXFF/n88 ), .B(\UART_TXFF/n86 ), .C(
\UART_TXFF/n87 ), .D(\UART_TXFF/n85 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n89 ) );
notech_mux4 \UART_TXFF/U91 ( .A(\UART_TXFF/iFIFOMem[0][1] ), .B(
\UART_TXFF/iFIFOMem[2][1] ), .C(\UART_TXFF/iFIFOMem[1][1] ), .D(
\UART_TXFF/iFIFOMem[3][1] ), .S0(\UART_TXFF/n37 ), .S1(\UART_TXFF/n43 ), .Z(\UART_TXFF/n88 ) );
notech_mux4 \UART_TXFF/U90 ( .A(\UART_TXFF/iFIFOMem[4][1] ), .B(
\UART_TXFF/iFIFOMem[6][1] ), .C(\UART_TXFF/iFIFOMem[5][1] ), .D(
\UART_TXFF/iFIFOMem[7][1] ), .S0(\UART_TXFF/n37 ), .S1(\UART_TXFF/n43 ), .Z(\UART_TXFF/n87 ) );
notech_mux4 \UART_TXFF/U89 ( .A(\UART_TXFF/iFIFOMem[8][1] ), .B(
\UART_TXFF/iFIFOMem[10][1] ), .C(\UART_TXFF/iFIFOMem[9][1] ), .D(
\UART_TXFF/iFIFOMem[11][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n86 ) );
notech_mux4 \UART_TXFF/U88 ( .A(\UART_TXFF/iFIFOMem[12][1] ), .B(
\UART_TXFF/iFIFOMem[14][1] ), .C(\UART_TXFF/iFIFOMem[13][1] ), .D(
\UART_TXFF/iFIFOMem[15][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n85 ) );
notech_mux4 \UART_TXFF/U87 ( .A(\UART_TXFF/n83 ), .B(\UART_TXFF/n81 ), .C(
\UART_TXFF/n82 ), .D(\UART_TXFF/n80 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n84 ) );
notech_mux4 \UART_TXFF/U86 ( .A(\UART_TXFF/iFIFOMem[16][1] ), .B(
\UART_TXFF/iFIFOMem[18][1] ), .C(\UART_TXFF/iFIFOMem[17][1] ), .D(
\UART_TXFF/iFIFOMem[19][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n83 ) );
notech_mux4 \UART_TXFF/U85 ( .A(\UART_TXFF/iFIFOMem[20][1] ), .B(
\UART_TXFF/iFIFOMem[22][1] ), .C(\UART_TXFF/iFIFOMem[21][1] ), .D(
\UART_TXFF/iFIFOMem[23][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n82 ) );
notech_mux4 \UART_TXFF/U84 ( .A(\UART_TXFF/iFIFOMem[24][1] ), .B(
\UART_TXFF/iFIFOMem[26][1] ), .C(\UART_TXFF/iFIFOMem[25][1] ), .D(
\UART_TXFF/iFIFOMem[27][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n81 ) );
notech_mux4 \UART_TXFF/U83 ( .A(\UART_TXFF/iFIFOMem[28][1] ), .B(
\UART_TXFF/iFIFOMem[30][1] ), .C(\UART_TXFF/iFIFOMem[29][1] ), .D(
\UART_TXFF/iFIFOMem[31][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n80 ) );
notech_mux4 \UART_TXFF/U82 ( .A(\UART_TXFF/n78 ), .B(\UART_TXFF/n76 ), .C(
\UART_TXFF/n77 ), .D(\UART_TXFF/n75 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n79 ) );
notech_mux4 \UART_TXFF/U81 ( .A(\UART_TXFF/iFIFOMem[32][1] ), .B(
\UART_TXFF/iFIFOMem[34][1] ), .C(\UART_TXFF/iFIFOMem[33][1] ), .D(
\UART_TXFF/iFIFOMem[35][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n78 ) );
notech_mux4 \UART_TXFF/U80 ( .A(\UART_TXFF/iFIFOMem[36][1] ), .B(
\UART_TXFF/iFIFOMem[38][1] ), .C(\UART_TXFF/iFIFOMem[37][1] ), .D(
\UART_TXFF/iFIFOMem[39][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n77 ) );
notech_mux4 \UART_TXFF/U79 ( .A(\UART_TXFF/iFIFOMem[40][1] ), .B(
\UART_TXFF/iFIFOMem[42][1] ), .C(\UART_TXFF/iFIFOMem[41][1] ), .D(
\UART_TXFF/iFIFOMem[43][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n76 ) );
notech_mux4 \UART_TXFF/U78 ( .A(\UART_TXFF/iFIFOMem[44][1] ), .B(
\UART_TXFF/iFIFOMem[46][1] ), .C(\UART_TXFF/iFIFOMem[45][1] ), .D(
\UART_TXFF/iFIFOMem[47][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n75 ) );
notech_mux4 \UART_TXFF/U77 ( .A(\UART_TXFF/n73 ), .B(\UART_TXFF/n71 ), .C(
\UART_TXFF/n72 ), .D(\UART_TXFF/n70 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n74 ) );
notech_mux4 \UART_TXFF/U76 ( .A(\UART_TXFF/iFIFOMem[48][1] ), .B(
\UART_TXFF/iFIFOMem[50][1] ), .C(\UART_TXFF/iFIFOMem[49][1] ), .D(
\UART_TXFF/iFIFOMem[51][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n73 ) );
notech_mux4 \UART_TXFF/U75 ( .A(\UART_TXFF/iFIFOMem[52][1] ), .B(
\UART_TXFF/iFIFOMem[54][1] ), .C(\UART_TXFF/iFIFOMem[53][1] ), .D(
\UART_TXFF/iFIFOMem[55][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n72 ) );
notech_mux4 \UART_TXFF/U74 ( .A(\UART_TXFF/iFIFOMem[56][1] ), .B(
\UART_TXFF/iFIFOMem[58][1] ), .C(\UART_TXFF/iFIFOMem[57][1] ), .D(
\UART_TXFF/iFIFOMem[59][1] ), .S0(\UART_TXFF/n37 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n71 ) );
notech_mux4 \UART_TXFF/U73 ( .A(\UART_TXFF/iFIFOMem[60][1] ), .B(
\UART_TXFF/iFIFOMem[62][1] ), .C(\UART_TXFF/iFIFOMem[61][1] ), .D(
\UART_TXFF/iFIFOMem[63][1] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n70 ) );
notech_mux4 \UART_TXFF/U72 ( .A(\UART_TXFF/n69 ), .B(\UART_TXFF/n59 ), .C(
\UART_TXFF/n64 ), .D(\UART_TXFF/n54 ), .S0(\UART_TXFF/N17 ), .S1(
\UART_TXFF/N16 ), .Z(\UART_TXFF/N130 ) );
notech_mux4 \UART_TXFF/U71 ( .A(\UART_TXFF/n68 ), .B(\UART_TXFF/n66 ), .C(
\UART_TXFF/n67 ), .D(\UART_TXFF/n65 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n69 ) );
notech_mux4 \UART_TXFF/U70 ( .A(\UART_TXFF/iFIFOMem[0][0] ), .B(
\UART_TXFF/iFIFOMem[2][0] ), .C(\UART_TXFF/iFIFOMem[1][0] ), .D(
\UART_TXFF/iFIFOMem[3][0] ), .S0(\UART_TXFF/n36 ), .S1(\UART_TXFF/N12 ), .Z(\UART_TXFF/n68 ) );
notech_mux4 \UART_TXFF/U69 ( .A(\UART_TXFF/iFIFOMem[4][0] ), .B(
\UART_TXFF/iFIFOMem[6][0] ), .C(\UART_TXFF/iFIFOMem[5][0] ), .D(
\UART_TXFF/iFIFOMem[7][0] ), .S0(\UART_TXFF/n36 ), .S1(\UART_TXFF/N12 ), .Z(\UART_TXFF/n67 ) );
notech_mux4 \UART_TXFF/U68 ( .A(\UART_TXFF/iFIFOMem[8][0] ), .B(
\UART_TXFF/iFIFOMem[10][0] ), .C(\UART_TXFF/iFIFOMem[9][0] ), .D(
\UART_TXFF/iFIFOMem[11][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n66 ) );
notech_mux4 \UART_TXFF/U67 ( .A(\UART_TXFF/iFIFOMem[12][0] ), .B(
\UART_TXFF/iFIFOMem[14][0] ), .C(\UART_TXFF/iFIFOMem[13][0] ), .D(
\UART_TXFF/iFIFOMem[15][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n65 ) );
notech_mux4 \UART_TXFF/U66 ( .A(\UART_TXFF/n63 ), .B(\UART_TXFF/n61 ), .C(
\UART_TXFF/n62 ), .D(\UART_TXFF/n60 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n64 ) );
notech_mux4 \UART_TXFF/U65 ( .A(\UART_TXFF/iFIFOMem[16][0] ), .B(
\UART_TXFF/iFIFOMem[18][0] ), .C(\UART_TXFF/iFIFOMem[17][0] ), .D(
\UART_TXFF/iFIFOMem[19][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n63 ) );
notech_mux4 \UART_TXFF/U64 ( .A(\UART_TXFF/iFIFOMem[20][0] ), .B(
\UART_TXFF/iFIFOMem[22][0] ), .C(\UART_TXFF/iFIFOMem[21][0] ), .D(
\UART_TXFF/iFIFOMem[23][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n62 ) );
notech_mux4 \UART_TXFF/U63 ( .A(\UART_TXFF/iFIFOMem[24][0] ), .B(
\UART_TXFF/iFIFOMem[26][0] ), .C(\UART_TXFF/iFIFOMem[25][0] ), .D(
\UART_TXFF/iFIFOMem[27][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n61 ) );
notech_mux4 \UART_TXFF/U62 ( .A(\UART_TXFF/iFIFOMem[28][0] ), .B(
\UART_TXFF/iFIFOMem[30][0] ), .C(\UART_TXFF/iFIFOMem[29][0] ), .D(
\UART_TXFF/iFIFOMem[31][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n60 ) );
notech_mux4 \UART_TXFF/U61 ( .A(\UART_TXFF/n58 ), .B(\UART_TXFF/n56 ), .C(
\UART_TXFF/n57 ), .D(\UART_TXFF/n55 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n59 ) );
notech_mux4 \UART_TXFF/U60 ( .A(\UART_TXFF/iFIFOMem[32][0] ), .B(
\UART_TXFF/iFIFOMem[34][0] ), .C(\UART_TXFF/iFIFOMem[33][0] ), .D(
\UART_TXFF/iFIFOMem[35][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n58 ) );
notech_mux4 \UART_TXFF/U59 ( .A(\UART_TXFF/iFIFOMem[36][0] ), .B(
\UART_TXFF/iFIFOMem[38][0] ), .C(\UART_TXFF/iFIFOMem[37][0] ), .D(
\UART_TXFF/iFIFOMem[39][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n57 ) );
notech_mux4 \UART_TXFF/U58 ( .A(\UART_TXFF/iFIFOMem[40][0] ), .B(
\UART_TXFF/iFIFOMem[42][0] ), .C(\UART_TXFF/iFIFOMem[41][0] ), .D(
\UART_TXFF/iFIFOMem[43][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/N12 ), .Z(\UART_TXFF/n56 ) );
notech_mux4 \UART_TXFF/U57 ( .A(\UART_TXFF/iFIFOMem[44][0] ), .B(
\UART_TXFF/iFIFOMem[46][0] ), .C(\UART_TXFF/iFIFOMem[45][0] ), .D(
\UART_TXFF/iFIFOMem[47][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n43 ), .Z(\UART_TXFF/n55 ) );
notech_mux4 \UART_TXFF/U56 ( .A(\UART_TXFF/n53 ), .B(\UART_TXFF/n51 ), .C(
\UART_TXFF/n52 ), .D(\UART_TXFF/n50 ), .S0(\UART_TXFF/N15 ), .S1(
\UART_TXFF/N14 ), .Z(\UART_TXFF/n54 ) );
notech_mux4 \UART_TXFF/U55 ( .A(\UART_TXFF/iFIFOMem[48][0] ), .B(
\UART_TXFF/iFIFOMem[50][0] ), .C(\UART_TXFF/iFIFOMem[49][0] ), .D(
\UART_TXFF/iFIFOMem[51][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n47 ), .Z(\UART_TXFF/n53 ) );
notech_mux4 \UART_TXFF/U54 ( .A(\UART_TXFF/iFIFOMem[52][0] ), .B(
\UART_TXFF/iFIFOMem[54][0] ), .C(\UART_TXFF/iFIFOMem[53][0] ), .D(
\UART_TXFF/iFIFOMem[55][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n48 ), .Z(\UART_TXFF/n52 ) );
notech_mux4 \UART_TXFF/U53 ( .A(\UART_TXFF/iFIFOMem[56][0] ), .B(
\UART_TXFF/iFIFOMem[58][0] ), .C(\UART_TXFF/iFIFOMem[57][0] ), .D(
\UART_TXFF/iFIFOMem[59][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n44 ), .Z(\UART_TXFF/n51 ) );
notech_mux4 \UART_TXFF/U52 ( .A(\UART_TXFF/iFIFOMem[60][0] ), .B(
\UART_TXFF/iFIFOMem[62][0] ), .C(\UART_TXFF/iFIFOMem[61][0] ), .D(
\UART_TXFF/iFIFOMem[63][0] ), .S0(\UART_TXFF/n36 ), .S1(
\UART_TXFF/n45 ), .Z(\UART_TXFF/n50 ) );
notech_inv \UART_TXFF/U51 ( .A(\UART_TXFF/N12 ), .Z(\UART_TXFF/n49 ) );
notech_inv \UART_TXFF/U50 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n48 ) );
notech_inv \UART_TXFF/U49 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n47 ) );
notech_inv \UART_TXFF/U48 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n46 ) );
notech_inv \UART_TXFF/U47 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n45 ) );
notech_inv \UART_TXFF/U46 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n44 ) );
notech_inv \UART_TXFF/U45 ( .A(\UART_TXFF/n49 ), .Z(\UART_TXFF/n43 ) );
notech_inv \UART_TXFF/U44 ( .A(\UART_TXFF/N13 ), .Z(\UART_TXFF/n42 ) );
notech_inv \UART_TXFF/U43 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n41 ) );
notech_inv \UART_TXFF/U42 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n40 ) );
notech_inv \UART_TXFF/U41 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n39 ) );
notech_inv \UART_TXFF/U40 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n38 ) );
notech_inv \UART_TXFF/U39 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n37 ) );
notech_inv \UART_TXFF/U38 ( .A(\UART_TXFF/n42 ), .Z(\UART_TXFF/n36 ) );
notech_inv \UART_TXFF/U37 ( .A(\UART_TXFF/n234 ), .Z(\UART_TXFF/n35 ) );
notech_inv \UART_TXFF/U36 ( .A(\UART_TXFF/n232 ), .Z(\UART_TXFF/n34 ) );
notech_inv \UART_TXFF/U34 ( .A(\UART_TXFF/n29 ), .Z(\UART_TXFF/n32 ) );
notech_inv \UART_TXFF/U33 ( .A(\UART_TXFF/n29 ), .Z(\UART_TXFF/n31 ) );
notech_inv \UART_TXFF/U32 ( .A(\UART_TXFF/n29 ), .Z(\UART_TXFF/n30 ) );
notech_inv \UART_TXFF/U31 ( .A(iDIN[7]), .Z(\UART_TXFF/n29 ) );
notech_inv \UART_TXFF/U30 ( .A(\UART_TXFF/n25 ), .Z(\UART_TXFF/n28 ) );
notech_inv \UART_TXFF/U29 ( .A(\UART_TXFF/n25 ), .Z(\UART_TXFF/n27 ) );
notech_inv \UART_TXFF/U28 ( .A(\UART_TXFF/n25 ), .Z(\UART_TXFF/n26 ) );
notech_inv \UART_TXFF/U27 ( .A(iDIN[6]), .Z(\UART_TXFF/n25 ) );
notech_inv \UART_TXFF/U26 ( .A(\UART_TXFF/n21 ), .Z(\UART_TXFF/n24 ) );
notech_inv \UART_TXFF/U25 ( .A(\UART_TXFF/n21 ), .Z(\UART_TXFF/n23 ) );
notech_inv \UART_TXFF/U24 ( .A(\UART_TXFF/n21 ), .Z(\UART_TXFF/n22 ) );
notech_inv \UART_TXFF/U23 ( .A(iDIN[5]), .Z(\UART_TXFF/n21 ) );
notech_inv \UART_TXFF/U22 ( .A(\UART_TXFF/n17 ), .Z(\UART_TXFF/n20 ) );
notech_inv \UART_TXFF/U21 ( .A(\UART_TXFF/n17 ), .Z(\UART_TXFF/n19 ) );
notech_inv \UART_TXFF/U20 ( .A(\UART_TXFF/n17 ), .Z(\UART_TXFF/n18 ) );
notech_inv \UART_TXFF/U19 ( .A(iDIN[4]), .Z(\UART_TXFF/n17 ) );
notech_inv \UART_TXFF/U18 ( .A(\UART_TXFF/n13 ), .Z(\UART_TXFF/n16 ) );
notech_inv \UART_TXFF/U17 ( .A(\UART_TXFF/n13 ), .Z(\UART_TXFF/n15 ) );
notech_inv \UART_TXFF/U16 ( .A(\UART_TXFF/n13 ), .Z(\UART_TXFF/n14 ) );
notech_inv \UART_TXFF/U15 ( .A(iDIN[3]), .Z(\UART_TXFF/n13 ) );
notech_inv \UART_TXFF/U14 ( .A(\UART_TXFF/n9 ), .Z(\UART_TXFF/n12 ) );
notech_inv \UART_TXFF/U13 ( .A(\UART_TXFF/n9 ), .Z(\UART_TXFF/n11 ) );
notech_inv \UART_TXFF/U12 ( .A(\UART_TXFF/n9 ), .Z(\UART_TXFF/n10 ) );
notech_inv \UART_TXFF/U11 ( .A(iDIN[2]), .Z(\UART_TXFF/n9 ) );
notech_inv \UART_TXFF/U10 ( .A(\UART_TXFF/n5 ), .Z(\UART_TXFF/n8 ) );
notech_inv \UART_TXFF/U9 ( .A(\UART_TXFF/n5 ), .Z(\UART_TXFF/n7 ) );
notech_inv \UART_TXFF/U8 ( .A(\UART_TXFF/n5 ), .Z(\UART_TXFF/n6 ) );
notech_inv \UART_TXFF/U7 ( .A(iDIN[1]), .Z(\UART_TXFF/n5 ) );
notech_inv \UART_TXFF/U6 ( .A(\UART_TXFF/n1 ), .Z(\UART_TXFF/n4 ) );
notech_inv \UART_TXFF/U5 ( .A(\UART_TXFF/n1 ), .Z(\UART_TXFF/n3 ) );
notech_inv \UART_TXFF/U4 ( .A(\UART_TXFF/n1 ), .Z(\UART_TXFF/n2 ) );
notech_inv \UART_TXFF/U3 ( .A(iDIN[0]), .Z(\UART_TXFF/n1 ) );
notech_reg \UART_TXFF/iUSAGE_reg[4] ( .D(\UART_TXFF/n1287 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(\iTXFIFOUsage[4] ) );
notech_reg \UART_TXFF/iUSAGE_reg[3] ( .D(\UART_TXFF/n1288 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_TXFF/USAGE[3] ) );
notech_reg \UART_TXFF/iUSAGE_reg[2] ( .D(\UART_TXFF/n1289 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(\UART_TXFF/USAGE[2] ) );
notech_reg \UART_TXFF/iUSAGE_reg[1] ( .D(\UART_TXFF/n1290 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(\UART_TXFF/USAGE[1] ) );
notech_reg \UART_TXFF/iUSAGE_reg[0] ( .D(\UART_TXFF/n1291 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(\UART_TXFF/USAGE[0] ) );
notech_reg \UART_TXFF/Q_reg[0] ( .D(\UART_TXFF/n758 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[0]) );
notech_reg \UART_TXFF/Q_reg[1] ( .D(\UART_TXFF/n760 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[1]) );
notech_reg \UART_TXFF/Q_reg[2] ( .D(\UART_TXFF/n762 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[2]) );
notech_reg \UART_TXFF/Q_reg[3] ( .D(\UART_TXFF/n764 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[3]) );
notech_reg \UART_TXFF/Q_reg[4] ( .D(\UART_TXFF/n766 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[4]) );
notech_reg \UART_TXFF/Q_reg[5] ( .D(\UART_TXFF/n768 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[5]) );
notech_reg \UART_TXFF/Q_reg[6] ( .D(\UART_TXFF/n770 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[6]) );
notech_reg \UART_TXFF/Q_reg[7] ( .D(\UART_TXFF/n772 ), .CP(CLK), .CD(1'b1),
.Q(iTXFIFOQ[7]) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][0] ( .D(\UART_TXFF/n1292 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][1] ( .D(\UART_TXFF/n1293 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][2] ( .D(\UART_TXFF/n1294 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][3] ( .D(\UART_TXFF/n1295 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][4] ( .D(\UART_TXFF/n1296 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][5] ( .D(\UART_TXFF/n1297 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][6] ( .D(\UART_TXFF/n1298 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[0][7] ( .D(\UART_TXFF/n1299 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[0][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][0] ( .D(\UART_TXFF/n1300 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][1] ( .D(\UART_TXFF/n1301 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][2] ( .D(\UART_TXFF/n1302 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][3] ( .D(\UART_TXFF/n1303 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][4] ( .D(\UART_TXFF/n1304 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][5] ( .D(\UART_TXFF/n1305 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][6] ( .D(\UART_TXFF/n1306 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[1][7] ( .D(\UART_TXFF/n1307 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[1][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][0] ( .D(\UART_TXFF/n1308 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][1] ( .D(\UART_TXFF/n1309 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][2] ( .D(\UART_TXFF/n1310 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][3] ( .D(\UART_TXFF/n1311 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][4] ( .D(\UART_TXFF/n1312 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][5] ( .D(\UART_TXFF/n1313 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][6] ( .D(\UART_TXFF/n1314 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[2][7] ( .D(\UART_TXFF/n1315 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[2][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][0] ( .D(\UART_TXFF/n1316 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][1] ( .D(\UART_TXFF/n1317 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][2] ( .D(\UART_TXFF/n1318 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][3] ( .D(\UART_TXFF/n1319 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][4] ( .D(\UART_TXFF/n1320 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][5] ( .D(\UART_TXFF/n1321 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][6] ( .D(\UART_TXFF/n1322 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[3][7] ( .D(\UART_TXFF/n1323 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[3][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][0] ( .D(\UART_TXFF/n1324 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][1] ( .D(\UART_TXFF/n1325 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][2] ( .D(\UART_TXFF/n1326 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][3] ( .D(\UART_TXFF/n1327 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][4] ( .D(\UART_TXFF/n1328 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][5] ( .D(\UART_TXFF/n1329 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][6] ( .D(\UART_TXFF/n1330 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[4][7] ( .D(\UART_TXFF/n1331 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[4][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][0] ( .D(\UART_TXFF/n1332 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][1] ( .D(\UART_TXFF/n1333 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][2] ( .D(\UART_TXFF/n1334 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][3] ( .D(\UART_TXFF/n1335 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][4] ( .D(\UART_TXFF/n1336 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][5] ( .D(\UART_TXFF/n1337 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][6] ( .D(\UART_TXFF/n1338 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[5][7] ( .D(\UART_TXFF/n1339 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[5][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][0] ( .D(\UART_TXFF/n1340 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][1] ( .D(\UART_TXFF/n1341 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][2] ( .D(\UART_TXFF/n1342 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][3] ( .D(\UART_TXFF/n1343 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][4] ( .D(\UART_TXFF/n1344 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][5] ( .D(\UART_TXFF/n1345 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][6] ( .D(\UART_TXFF/n1346 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[6][7] ( .D(\UART_TXFF/n1347 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[6][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][0] ( .D(\UART_TXFF/n1348 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][1] ( .D(\UART_TXFF/n1349 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][2] ( .D(\UART_TXFF/n1350 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][3] ( .D(\UART_TXFF/n1351 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][4] ( .D(\UART_TXFF/n1352 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][5] ( .D(\UART_TXFF/n1353 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][6] ( .D(\UART_TXFF/n1354 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[7][7] ( .D(\UART_TXFF/n1355 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[7][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][0] ( .D(\UART_TXFF/n1356 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][1] ( .D(\UART_TXFF/n1357 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][2] ( .D(\UART_TXFF/n1358 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][3] ( .D(\UART_TXFF/n1359 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][4] ( .D(\UART_TXFF/n1360 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][5] ( .D(\UART_TXFF/n1361 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][6] ( .D(\UART_TXFF/n1362 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[8][7] ( .D(\UART_TXFF/n1363 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[8][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][0] ( .D(\UART_TXFF/n1364 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][1] ( .D(\UART_TXFF/n1365 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][2] ( .D(\UART_TXFF/n1366 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][3] ( .D(\UART_TXFF/n1367 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][4] ( .D(\UART_TXFF/n1368 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][5] ( .D(\UART_TXFF/n1369 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][6] ( .D(\UART_TXFF/n1370 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[9][7] ( .D(\UART_TXFF/n1371 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[9][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][0] ( .D(\UART_TXFF/n1372 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][1] ( .D(\UART_TXFF/n1373 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][2] ( .D(\UART_TXFF/n1374 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][3] ( .D(\UART_TXFF/n1375 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][4] ( .D(\UART_TXFF/n1376 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][5] ( .D(\UART_TXFF/n1377 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][6] ( .D(\UART_TXFF/n1378 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[10][7] ( .D(\UART_TXFF/n1379 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[10][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][0] ( .D(\UART_TXFF/n1380 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][1] ( .D(\UART_TXFF/n1381 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][2] ( .D(\UART_TXFF/n1382 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][3] ( .D(\UART_TXFF/n1383 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][4] ( .D(\UART_TXFF/n1384 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][5] ( .D(\UART_TXFF/n1385 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][6] ( .D(\UART_TXFF/n1386 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[11][7] ( .D(\UART_TXFF/n1387 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[11][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][0] ( .D(\UART_TXFF/n1388 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][1] ( .D(\UART_TXFF/n1389 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][2] ( .D(\UART_TXFF/n1390 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][3] ( .D(\UART_TXFF/n1391 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][4] ( .D(\UART_TXFF/n1392 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][5] ( .D(\UART_TXFF/n1393 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][6] ( .D(\UART_TXFF/n1394 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[12][7] ( .D(\UART_TXFF/n1395 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[12][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][0] ( .D(\UART_TXFF/n1396 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][1] ( .D(\UART_TXFF/n1397 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][2] ( .D(\UART_TXFF/n1398 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][3] ( .D(\UART_TXFF/n1399 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][4] ( .D(\UART_TXFF/n1400 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][5] ( .D(\UART_TXFF/n1401 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][6] ( .D(\UART_TXFF/n1402 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[13][7] ( .D(\UART_TXFF/n1403 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[13][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][0] ( .D(\UART_TXFF/n1404 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][1] ( .D(\UART_TXFF/n1405 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][2] ( .D(\UART_TXFF/n1406 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][3] ( .D(\UART_TXFF/n1407 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][4] ( .D(\UART_TXFF/n1408 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][5] ( .D(\UART_TXFF/n1409 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][6] ( .D(\UART_TXFF/n1410 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[14][7] ( .D(\UART_TXFF/n1411 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[14][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][0] ( .D(\UART_TXFF/n1412 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][1] ( .D(\UART_TXFF/n1413 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][2] ( .D(\UART_TXFF/n1414 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][3] ( .D(\UART_TXFF/n1415 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][4] ( .D(\UART_TXFF/n1416 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][5] ( .D(\UART_TXFF/n1417 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][6] ( .D(\UART_TXFF/n1418 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[15][7] ( .D(\UART_TXFF/n1419 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[15][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][0] ( .D(\UART_TXFF/n1420 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][1] ( .D(\UART_TXFF/n1421 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][2] ( .D(\UART_TXFF/n1422 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][3] ( .D(\UART_TXFF/n1423 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][4] ( .D(\UART_TXFF/n1424 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][5] ( .D(\UART_TXFF/n1425 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][6] ( .D(\UART_TXFF/n1426 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[16][7] ( .D(\UART_TXFF/n1427 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[16][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][0] ( .D(\UART_TXFF/n1428 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][1] ( .D(\UART_TXFF/n1429 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][2] ( .D(\UART_TXFF/n1430 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][3] ( .D(\UART_TXFF/n1431 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][4] ( .D(\UART_TXFF/n1432 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][5] ( .D(\UART_TXFF/n1433 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][6] ( .D(\UART_TXFF/n1434 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[17][7] ( .D(\UART_TXFF/n1435 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[17][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][0] ( .D(\UART_TXFF/n1436 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][1] ( .D(\UART_TXFF/n1437 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][2] ( .D(\UART_TXFF/n1438 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][3] ( .D(\UART_TXFF/n1439 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][4] ( .D(\UART_TXFF/n1440 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][5] ( .D(\UART_TXFF/n1441 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][6] ( .D(\UART_TXFF/n1442 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[18][7] ( .D(\UART_TXFF/n1443 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[18][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][0] ( .D(\UART_TXFF/n1444 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][1] ( .D(\UART_TXFF/n1445 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][2] ( .D(\UART_TXFF/n1446 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][3] ( .D(\UART_TXFF/n1447 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][4] ( .D(\UART_TXFF/n1448 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][5] ( .D(\UART_TXFF/n1449 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][6] ( .D(\UART_TXFF/n1450 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[19][7] ( .D(\UART_TXFF/n1451 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[19][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][0] ( .D(\UART_TXFF/n1452 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][1] ( .D(\UART_TXFF/n1453 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][2] ( .D(\UART_TXFF/n1454 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][3] ( .D(\UART_TXFF/n1455 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][4] ( .D(\UART_TXFF/n1456 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][5] ( .D(\UART_TXFF/n1457 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][6] ( .D(\UART_TXFF/n1458 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[20][7] ( .D(\UART_TXFF/n1459 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[20][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][0] ( .D(\UART_TXFF/n1460 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][1] ( .D(\UART_TXFF/n1461 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][2] ( .D(\UART_TXFF/n1462 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][3] ( .D(\UART_TXFF/n1463 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][4] ( .D(\UART_TXFF/n1464 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][5] ( .D(\UART_TXFF/n1465 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][6] ( .D(\UART_TXFF/n1466 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[21][7] ( .D(\UART_TXFF/n1467 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[21][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][0] ( .D(\UART_TXFF/n1468 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][1] ( .D(\UART_TXFF/n1469 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][2] ( .D(\UART_TXFF/n1470 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][3] ( .D(\UART_TXFF/n1471 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][4] ( .D(\UART_TXFF/n1472 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][5] ( .D(\UART_TXFF/n1473 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][6] ( .D(\UART_TXFF/n1474 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[22][7] ( .D(\UART_TXFF/n1475 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[22][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][0] ( .D(\UART_TXFF/n1476 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][1] ( .D(\UART_TXFF/n1477 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][2] ( .D(\UART_TXFF/n1478 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][3] ( .D(\UART_TXFF/n1479 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][4] ( .D(\UART_TXFF/n1480 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][5] ( .D(\UART_TXFF/n1481 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][6] ( .D(\UART_TXFF/n1482 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[23][7] ( .D(\UART_TXFF/n1483 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[23][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][0] ( .D(\UART_TXFF/n1484 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][1] ( .D(\UART_TXFF/n1485 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][2] ( .D(\UART_TXFF/n1486 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][3] ( .D(\UART_TXFF/n1487 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][4] ( .D(\UART_TXFF/n1488 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][5] ( .D(\UART_TXFF/n1489 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][6] ( .D(\UART_TXFF/n1490 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[24][7] ( .D(\UART_TXFF/n1491 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[24][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][0] ( .D(\UART_TXFF/n1492 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][1] ( .D(\UART_TXFF/n1493 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][2] ( .D(\UART_TXFF/n1494 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][3] ( .D(\UART_TXFF/n1495 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][4] ( .D(\UART_TXFF/n1496 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][5] ( .D(\UART_TXFF/n1497 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][6] ( .D(\UART_TXFF/n1498 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[25][7] ( .D(\UART_TXFF/n1499 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[25][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][0] ( .D(\UART_TXFF/n1500 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][1] ( .D(\UART_TXFF/n1501 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][2] ( .D(\UART_TXFF/n1502 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][3] ( .D(\UART_TXFF/n1503 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][4] ( .D(\UART_TXFF/n1504 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][5] ( .D(\UART_TXFF/n1505 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][6] ( .D(\UART_TXFF/n1506 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[26][7] ( .D(\UART_TXFF/n1507 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[26][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][0] ( .D(\UART_TXFF/n1508 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][1] ( .D(\UART_TXFF/n1509 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][2] ( .D(\UART_TXFF/n1510 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][3] ( .D(\UART_TXFF/n1511 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][4] ( .D(\UART_TXFF/n1512 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][5] ( .D(\UART_TXFF/n1513 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][6] ( .D(\UART_TXFF/n1514 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[27][7] ( .D(\UART_TXFF/n1515 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[27][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][0] ( .D(\UART_TXFF/n1516 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][1] ( .D(\UART_TXFF/n1517 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][2] ( .D(\UART_TXFF/n1518 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][3] ( .D(\UART_TXFF/n1519 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][4] ( .D(\UART_TXFF/n1520 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][5] ( .D(\UART_TXFF/n1521 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][6] ( .D(\UART_TXFF/n1522 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[28][7] ( .D(\UART_TXFF/n1523 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[28][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][0] ( .D(\UART_TXFF/n1524 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][1] ( .D(\UART_TXFF/n1525 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][2] ( .D(\UART_TXFF/n1526 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][3] ( .D(\UART_TXFF/n1527 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][4] ( .D(\UART_TXFF/n1528 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][5] ( .D(\UART_TXFF/n1529 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][6] ( .D(\UART_TXFF/n1530 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[29][7] ( .D(\UART_TXFF/n1531 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[29][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][0] ( .D(\UART_TXFF/n1532 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][1] ( .D(\UART_TXFF/n1533 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][2] ( .D(\UART_TXFF/n1534 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][3] ( .D(\UART_TXFF/n1535 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][4] ( .D(\UART_TXFF/n1536 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][5] ( .D(\UART_TXFF/n1537 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][6] ( .D(\UART_TXFF/n1538 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[30][7] ( .D(\UART_TXFF/n1539 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[30][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][0] ( .D(\UART_TXFF/n1540 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][1] ( .D(\UART_TXFF/n1541 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][2] ( .D(\UART_TXFF/n1542 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][3] ( .D(\UART_TXFF/n1543 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][4] ( .D(\UART_TXFF/n1544 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][5] ( .D(\UART_TXFF/n1545 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][6] ( .D(\UART_TXFF/n1546 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[31][7] ( .D(\UART_TXFF/n1547 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[31][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][0] ( .D(\UART_TXFF/n1548 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][1] ( .D(\UART_TXFF/n1549 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][2] ( .D(\UART_TXFF/n1550 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][3] ( .D(\UART_TXFF/n1551 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][4] ( .D(\UART_TXFF/n1552 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][5] ( .D(\UART_TXFF/n1553 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][6] ( .D(\UART_TXFF/n1554 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[32][7] ( .D(\UART_TXFF/n1555 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[32][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][0] ( .D(\UART_TXFF/n1556 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][1] ( .D(\UART_TXFF/n1557 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][2] ( .D(\UART_TXFF/n1558 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][3] ( .D(\UART_TXFF/n1559 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][4] ( .D(\UART_TXFF/n1560 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][5] ( .D(\UART_TXFF/n1561 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][6] ( .D(\UART_TXFF/n1562 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[33][7] ( .D(\UART_TXFF/n1563 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[33][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][0] ( .D(\UART_TXFF/n1564 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][1] ( .D(\UART_TXFF/n1565 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][2] ( .D(\UART_TXFF/n1566 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][3] ( .D(\UART_TXFF/n1567 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][4] ( .D(\UART_TXFF/n1568 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][5] ( .D(\UART_TXFF/n1569 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][6] ( .D(\UART_TXFF/n1570 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[34][7] ( .D(\UART_TXFF/n1571 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[34][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][0] ( .D(\UART_TXFF/n1572 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][1] ( .D(\UART_TXFF/n1573 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][2] ( .D(\UART_TXFF/n1574 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][3] ( .D(\UART_TXFF/n1575 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][4] ( .D(\UART_TXFF/n1576 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][5] ( .D(\UART_TXFF/n1577 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][6] ( .D(\UART_TXFF/n1578 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[35][7] ( .D(\UART_TXFF/n1579 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[35][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][0] ( .D(\UART_TXFF/n1580 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][1] ( .D(\UART_TXFF/n1581 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][2] ( .D(\UART_TXFF/n1582 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][3] ( .D(\UART_TXFF/n1583 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][4] ( .D(\UART_TXFF/n1584 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][5] ( .D(\UART_TXFF/n1585 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][6] ( .D(\UART_TXFF/n1586 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[36][7] ( .D(\UART_TXFF/n1587 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[36][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][0] ( .D(\UART_TXFF/n1588 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][1] ( .D(\UART_TXFF/n1589 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][2] ( .D(\UART_TXFF/n1590 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][3] ( .D(\UART_TXFF/n1591 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][4] ( .D(\UART_TXFF/n1592 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][5] ( .D(\UART_TXFF/n1593 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][6] ( .D(\UART_TXFF/n1594 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[37][7] ( .D(\UART_TXFF/n1595 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[37][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][0] ( .D(\UART_TXFF/n1596 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][1] ( .D(\UART_TXFF/n1597 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][2] ( .D(\UART_TXFF/n1598 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][3] ( .D(\UART_TXFF/n1599 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][4] ( .D(\UART_TXFF/n1600 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][5] ( .D(\UART_TXFF/n1601 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][6] ( .D(\UART_TXFF/n1602 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[38][7] ( .D(\UART_TXFF/n1603 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[38][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][0] ( .D(\UART_TXFF/n1604 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][1] ( .D(\UART_TXFF/n1605 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][2] ( .D(\UART_TXFF/n1606 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][3] ( .D(\UART_TXFF/n1607 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][4] ( .D(\UART_TXFF/n1608 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][5] ( .D(\UART_TXFF/n1609 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][6] ( .D(\UART_TXFF/n1610 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[39][7] ( .D(\UART_TXFF/n1611 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[39][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][0] ( .D(\UART_TXFF/n1612 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][1] ( .D(\UART_TXFF/n1613 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][2] ( .D(\UART_TXFF/n1614 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][3] ( .D(\UART_TXFF/n1615 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][4] ( .D(\UART_TXFF/n1616 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][5] ( .D(\UART_TXFF/n1617 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][6] ( .D(\UART_TXFF/n1618 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[40][7] ( .D(\UART_TXFF/n1619 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[40][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][0] ( .D(\UART_TXFF/n1620 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][1] ( .D(\UART_TXFF/n1621 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][2] ( .D(\UART_TXFF/n1622 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][3] ( .D(\UART_TXFF/n1623 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][4] ( .D(\UART_TXFF/n1624 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][5] ( .D(\UART_TXFF/n1625 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][6] ( .D(\UART_TXFF/n1626 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[41][7] ( .D(\UART_TXFF/n1627 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[41][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][0] ( .D(\UART_TXFF/n1628 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][1] ( .D(\UART_TXFF/n1629 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][2] ( .D(\UART_TXFF/n1630 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][3] ( .D(\UART_TXFF/n1631 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][4] ( .D(\UART_TXFF/n1632 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][5] ( .D(\UART_TXFF/n1633 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][6] ( .D(\UART_TXFF/n1634 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[42][7] ( .D(\UART_TXFF/n1635 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[42][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][0] ( .D(\UART_TXFF/n1636 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][1] ( .D(\UART_TXFF/n1637 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][2] ( .D(\UART_TXFF/n1638 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][3] ( .D(\UART_TXFF/n1639 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][4] ( .D(\UART_TXFF/n1640 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][5] ( .D(\UART_TXFF/n1641 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][6] ( .D(\UART_TXFF/n1642 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[43][7] ( .D(\UART_TXFF/n1643 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[43][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][0] ( .D(\UART_TXFF/n1644 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][1] ( .D(\UART_TXFF/n1645 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][2] ( .D(\UART_TXFF/n1646 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][3] ( .D(\UART_TXFF/n1647 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][4] ( .D(\UART_TXFF/n1648 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][5] ( .D(\UART_TXFF/n1649 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][6] ( .D(\UART_TXFF/n1650 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[44][7] ( .D(\UART_TXFF/n1651 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[44][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][0] ( .D(\UART_TXFF/n1652 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][1] ( .D(\UART_TXFF/n1653 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][2] ( .D(\UART_TXFF/n1654 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][3] ( .D(\UART_TXFF/n1655 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][4] ( .D(\UART_TXFF/n1656 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][5] ( .D(\UART_TXFF/n1657 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][6] ( .D(\UART_TXFF/n1658 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[45][7] ( .D(\UART_TXFF/n1659 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[45][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][0] ( .D(\UART_TXFF/n1660 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][1] ( .D(\UART_TXFF/n1661 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][2] ( .D(\UART_TXFF/n1662 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][3] ( .D(\UART_TXFF/n1663 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][4] ( .D(\UART_TXFF/n1664 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][5] ( .D(\UART_TXFF/n1665 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][6] ( .D(\UART_TXFF/n1666 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[46][7] ( .D(\UART_TXFF/n1667 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[46][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][0] ( .D(\UART_TXFF/n1668 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][1] ( .D(\UART_TXFF/n1669 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][2] ( .D(\UART_TXFF/n1670 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][3] ( .D(\UART_TXFF/n1671 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][4] ( .D(\UART_TXFF/n1672 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][5] ( .D(\UART_TXFF/n1673 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][6] ( .D(\UART_TXFF/n1674 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[47][7] ( .D(\UART_TXFF/n1675 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[47][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][0] ( .D(\UART_TXFF/n1676 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][1] ( .D(\UART_TXFF/n1677 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][2] ( .D(\UART_TXFF/n1678 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][3] ( .D(\UART_TXFF/n1679 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][4] ( .D(\UART_TXFF/n1680 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][5] ( .D(\UART_TXFF/n1681 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][6] ( .D(\UART_TXFF/n1682 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[48][7] ( .D(\UART_TXFF/n1683 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[48][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][0] ( .D(\UART_TXFF/n1684 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][1] ( .D(\UART_TXFF/n1685 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][2] ( .D(\UART_TXFF/n1686 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][3] ( .D(\UART_TXFF/n1687 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][4] ( .D(\UART_TXFF/n1688 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][5] ( .D(\UART_TXFF/n1689 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][6] ( .D(\UART_TXFF/n1690 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[49][7] ( .D(\UART_TXFF/n1691 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[49][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][0] ( .D(\UART_TXFF/n1692 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][1] ( .D(\UART_TXFF/n1693 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][2] ( .D(\UART_TXFF/n1694 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][3] ( .D(\UART_TXFF/n1695 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][4] ( .D(\UART_TXFF/n1696 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][5] ( .D(\UART_TXFF/n1697 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][6] ( .D(\UART_TXFF/n1698 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[50][7] ( .D(\UART_TXFF/n1699 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[50][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][0] ( .D(\UART_TXFF/n1700 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][1] ( .D(\UART_TXFF/n1701 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][2] ( .D(\UART_TXFF/n1702 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][3] ( .D(\UART_TXFF/n1703 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][4] ( .D(\UART_TXFF/n1704 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][5] ( .D(\UART_TXFF/n1705 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][6] ( .D(\UART_TXFF/n1706 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[51][7] ( .D(\UART_TXFF/n1707 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[51][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][0] ( .D(\UART_TXFF/n1708 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][1] ( .D(\UART_TXFF/n1709 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][2] ( .D(\UART_TXFF/n1710 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][3] ( .D(\UART_TXFF/n1711 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][4] ( .D(\UART_TXFF/n1712 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][5] ( .D(\UART_TXFF/n1713 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][6] ( .D(\UART_TXFF/n1714 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[52][7] ( .D(\UART_TXFF/n1715 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[52][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][0] ( .D(\UART_TXFF/n1716 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][1] ( .D(\UART_TXFF/n1717 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][2] ( .D(\UART_TXFF/n1718 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][3] ( .D(\UART_TXFF/n1719 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][4] ( .D(\UART_TXFF/n1720 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][5] ( .D(\UART_TXFF/n1721 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][6] ( .D(\UART_TXFF/n1722 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[53][7] ( .D(\UART_TXFF/n1723 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[53][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][0] ( .D(\UART_TXFF/n1724 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][1] ( .D(\UART_TXFF/n1725 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][2] ( .D(\UART_TXFF/n1726 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][3] ( .D(\UART_TXFF/n1727 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][4] ( .D(\UART_TXFF/n1728 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][5] ( .D(\UART_TXFF/n1729 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][6] ( .D(\UART_TXFF/n1730 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[54][7] ( .D(\UART_TXFF/n1731 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[54][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][0] ( .D(\UART_TXFF/n1732 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][1] ( .D(\UART_TXFF/n1733 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][2] ( .D(\UART_TXFF/n1734 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][3] ( .D(\UART_TXFF/n1735 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][4] ( .D(\UART_TXFF/n1736 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][5] ( .D(\UART_TXFF/n1737 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][6] ( .D(\UART_TXFF/n1738 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[55][7] ( .D(\UART_TXFF/n1739 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[55][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][0] ( .D(\UART_TXFF/n1740 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][1] ( .D(\UART_TXFF/n1741 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][2] ( .D(\UART_TXFF/n1742 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][3] ( .D(\UART_TXFF/n1743 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][4] ( .D(\UART_TXFF/n1744 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][5] ( .D(\UART_TXFF/n1745 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][6] ( .D(\UART_TXFF/n1746 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[56][7] ( .D(\UART_TXFF/n1747 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[56][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][0] ( .D(\UART_TXFF/n1748 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][1] ( .D(\UART_TXFF/n1749 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][2] ( .D(\UART_TXFF/n1750 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][3] ( .D(\UART_TXFF/n1751 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][4] ( .D(\UART_TXFF/n1752 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][5] ( .D(\UART_TXFF/n1753 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][6] ( .D(\UART_TXFF/n1754 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[57][7] ( .D(\UART_TXFF/n1755 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[57][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][0] ( .D(\UART_TXFF/n1756 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][1] ( .D(\UART_TXFF/n1757 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][2] ( .D(\UART_TXFF/n1758 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][3] ( .D(\UART_TXFF/n1759 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][4] ( .D(\UART_TXFF/n1760 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][5] ( .D(\UART_TXFF/n1761 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][6] ( .D(\UART_TXFF/n1762 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[58][7] ( .D(\UART_TXFF/n1763 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[58][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][0] ( .D(\UART_TXFF/n1764 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][1] ( .D(\UART_TXFF/n1765 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][2] ( .D(\UART_TXFF/n1766 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][3] ( .D(\UART_TXFF/n1767 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][4] ( .D(\UART_TXFF/n1768 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][5] ( .D(\UART_TXFF/n1769 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][6] ( .D(\UART_TXFF/n1770 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[59][7] ( .D(\UART_TXFF/n1771 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[59][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][0] ( .D(\UART_TXFF/n1772 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][1] ( .D(\UART_TXFF/n1773 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][2] ( .D(\UART_TXFF/n1774 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][3] ( .D(\UART_TXFF/n1775 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][4] ( .D(\UART_TXFF/n1776 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][5] ( .D(\UART_TXFF/n1777 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][6] ( .D(\UART_TXFF/n1778 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[60][7] ( .D(\UART_TXFF/n1779 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[60][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][0] ( .D(\UART_TXFF/n1780 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][1] ( .D(\UART_TXFF/n1781 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][2] ( .D(\UART_TXFF/n1782 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][3] ( .D(\UART_TXFF/n1783 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][4] ( .D(\UART_TXFF/n1784 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][5] ( .D(\UART_TXFF/n1785 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][6] ( .D(\UART_TXFF/n1786 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[61][7] ( .D(\UART_TXFF/n1787 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[61][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][0] ( .D(\UART_TXFF/n1788 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][1] ( .D(\UART_TXFF/n1789 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][2] ( .D(\UART_TXFF/n1790 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][3] ( .D(\UART_TXFF/n1791 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][4] ( .D(\UART_TXFF/n1792 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][5] ( .D(\UART_TXFF/n1793 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][6] ( .D(\UART_TXFF/n1794 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[62][7] ( .D(\UART_TXFF/n1795 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[62][7] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][0] ( .D(\UART_TXFF/n1796 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][0] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][1] ( .D(\UART_TXFF/n1797 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][1] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][2] ( .D(\UART_TXFF/n1798 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][2] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][3] ( .D(\UART_TXFF/n1799 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][3] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][4] ( .D(\UART_TXFF/n1800 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][4] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][5] ( .D(\UART_TXFF/n1801 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][5] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][6] ( .D(\UART_TXFF/n1802 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][6] ) );
notech_reg \UART_TXFF/iFIFOMem_reg[63][7] ( .D(\UART_TXFF/n1803 ), .CP(CLK),
.CD(1'b1), .Q(\UART_TXFF/iFIFOMem[63][7] ) );
notech_reg \UART_TXFF/iWRAddr_reg[5] ( .D(\UART_TXFF/n1810 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_TXFF/iWRAddr[5] ) );
notech_reg \UART_TXFF/iWRAddr_reg[4] ( .D(\UART_TXFF/n1811 ), .CP(CLK),
.CD(\UART_IS_DSR/n1 ), .Q(\UART_TXFF/iWRAddr[4] ) );
notech_reg \UART_TXFF/iWRAddr_reg[3] ( .D(\UART_TXFF/n1812 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_TXFF/iWRAddr[3] ) );
notech_reg \UART_TXFF/iWRAddr_reg[2] ( .D(\UART_TXFF/n1813 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_TXFF/iWRAddr[2] ) );
notech_reg \UART_TXFF/iWRAddr_reg[1] ( .D(\UART_TXFF/n1814 ), .CP(CLK),
.CD(\UART_IS_SIN/n1 ), .Q(\UART_TXFF/iWRAddr[1] ) );
notech_reg \UART_TXFF/iWRAddr_reg[0] ( .D(\UART_TXFF/n1815 ), .CP(CLK),
.CD(\UART_IS_SIN/n1 ), .Q(\UART_TXFF/iWRAddr[0] ) );
notech_reg \UART_TXFF/iWRAddr_reg[6] ( .D(\UART_TXFF/n1816 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_TXFF/iWRAddr[6] ) );
notech_reg \UART_TXFF/iRDAddr_reg[5] ( .D(\UART_TXFF/n1804 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_TXFF/N17 ) );
notech_reg \UART_TXFF/iRDAddr_reg[4] ( .D(\UART_TXFF/n1805 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_TXFF/N16 ) );
notech_reg \UART_TXFF/iRDAddr_reg[3] ( .D(\UART_TXFF/n1806 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_TXFF/N15 ) );
notech_reg \UART_TXFF/iRDAddr_reg[2] ( .D(\UART_TXFF/n1807 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_TXFF/N14 ) );
notech_reg \UART_TXFF/iRDAddr_reg[1] ( .D(\UART_TXFF/n1808 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_TXFF/N13 ) );
notech_reg \UART_TXFF/iRDAddr_reg[6] ( .D(\UART_TXFF/n1809 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_TXFF/iRDAddr[6] ) );
notech_reg_set \UART_TXFF/iEMPTY_reg ( .D(\UART_TXFF/N56 ), .CP(CLK), .SD(
\UART_IS_SIN/n1 ), .Q(iTXFIFOEmpty) );
notech_reg \UART_TXFF/iRDAddr_reg[0] ( .D(\UART_TXFF/n1817 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_TXFF/N12 ) );
notech_xor2 \UART_TXFF/add_73/U1 ( .A(\UART_TXFF/add_73/carry [6]), .B(
\UART_TXFF/iWRAddr[6] ), .Z(\UART_TXFF/N30 ) );
notech_ha2 \UART_TXFF/add_73/U1_1_1 ( .A(\UART_TXFF/iWRAddr[1] ), .B(
\UART_TXFF/iWRAddr[0] ), .CO(\UART_TXFF/add_73/carry [2]), .Z(
\UART_TXFF/N25 ) );
notech_ha2 \UART_TXFF/add_73/U1_1_2 ( .A(\UART_TXFF/iWRAddr[2] ), .B(
\UART_TXFF/add_73/carry [2]), .CO(\UART_TXFF/add_73/carry [3]), .Z(
\UART_TXFF/N26 ) );
notech_ha2 \UART_TXFF/add_73/U1_1_3 ( .A(\UART_TXFF/iWRAddr[3] ), .B(
\UART_TXFF/add_73/carry [3]), .CO(\UART_TXFF/add_73/carry [4]), .Z(
\UART_TXFF/N27 ) );
notech_ha2 \UART_TXFF/add_73/U1_1_4 ( .A(\UART_TXFF/iWRAddr[4] ), .B(
\UART_TXFF/add_73/carry [4]), .CO(\UART_TXFF/add_73/carry [5]), .Z(
\UART_TXFF/N28 ) );
notech_ha2 \UART_TXFF/add_73/U1_1_5 ( .A(\UART_TXFF/iWRAddr[5] ), .B(
\UART_TXFF/add_73/carry [5]), .CO(\UART_TXFF/add_73/carry [6]), .Z(
\UART_TXFF/N29 ) );
notech_xor2 \UART_TXFF/add_77/U1 ( .A(\UART_TXFF/add_77/carry [6]), .B(
\UART_TXFF/iRDAddr[6] ), .Z(\UART_TXFF/N38 ) );
notech_ha2 \UART_TXFF/add_77/U1_1_1 ( .A(\UART_TXFF/n36 ), .B(
\UART_TXFF/n46 ), .CO(\UART_TXFF/add_77/carry [2]), .Z(\UART_TXFF/N33 ) );
notech_ha2 \UART_TXFF/add_77/U1_1_2 ( .A(\UART_TXFF/N14 ), .B(
\UART_TXFF/add_77/carry [2]), .CO(\UART_TXFF/add_77/carry [3]), .Z(
\UART_TXFF/N34 ) );
notech_ha2 \UART_TXFF/add_77/U1_1_3 ( .A(\UART_TXFF/N15 ), .B(
\UART_TXFF/add_77/carry [3]), .CO(\UART_TXFF/add_77/carry [4]), .Z(
\UART_TXFF/N35 ) );
notech_ha2 \UART_TXFF/add_77/U1_1_4 ( .A(\UART_TXFF/N16 ), .B(
\UART_TXFF/add_77/carry [4]), .CO(\UART_TXFF/add_77/carry [5]), .Z(
\UART_TXFF/N36 ) );
notech_ha2 \UART_TXFF/add_77/U1_1_5 ( .A(\UART_TXFF/N17 ), .B(
\UART_TXFF/add_77/carry [5]), .CO(\UART_TXFF/add_77/carry [6]), .Z(
\UART_TXFF/N37 ) );
notech_xor2 \UART_RXFF/U1202 ( .A(\UART_RXFF/iWRAddr[1] ), .B(
\UART_RXFF/N13 ), .Z(\UART_RXFF/n445 ) );
notech_xor2 \UART_RXFF/U1201 ( .A(\UART_RXFF/iWRAddr[5] ), .B(
\UART_RXFF/N17 ), .Z(\UART_RXFF/n446 ) );
notech_xor2 \UART_RXFF/U1200 ( .A(\UART_RXFF/iWRAddr[0] ), .B(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n447 ) );
notech_xor2 \UART_RXFF/U1199 ( .A(\UART_RXFF/n46 ), .B(
\UART_RXFF/iWRAddr[2] ), .Z(\UART_RXFF/n449 ) );
notech_xor2 \UART_RXFF/U1198 ( .A(\UART_RXFF/n49 ), .B(
\UART_RXFF/iWRAddr[3] ), .Z(\UART_RXFF/n450 ) );
notech_inv \UART_RXFF/U1197 ( .A(\UART_RXFF/N16 ), .Z(\UART_RXFF/n314 ) );
notech_xor2 \UART_RXFF/U1196 ( .A(\UART_RXFF/n314 ), .B(
\UART_RXFF/iWRAddr[4] ), .Z(\UART_RXFF/n451 ) );
notech_nand3 \UART_RXFF/U1195 ( .A(\UART_RXFF/n449 ), .B(\UART_RXFF/n450 ),
.C(\UART_RXFF/n451 ), .Z(\UART_RXFF/n448 ) );
notech_nor4 \UART_RXFF/U1194 ( .A(\UART_RXFF/n445 ), .B(\UART_RXFF/n446 ),
.C(\UART_RXFF/n447 ), .D(\UART_RXFF/n448 ), .Z(\UART_RXFF/n442 ) );
notech_inv \UART_RXFF/U1193 ( .A(\UART_RXFF/n442 ), .Z(\UART_RXFF/n444 ) );
notech_inv \UART_RXFF/U1192 ( .A(\UART_RXFF/iWRAddr[6] ), .Z(
\UART_RXFF/n293 ) );
notech_xor2 \UART_RXFF/U1191 ( .A(\UART_RXFF/iRDAddr[6] ), .B(
\UART_RXFF/n293 ), .Z(\UART_RXFF/n443 ) );
notech_nor2 \UART_RXFF/U1190 ( .A(\UART_RXFF/n444 ), .B(\UART_RXFF/n443 ),
.Z(iRXFIFO64Full) );
notech_and2 \UART_RXFF/U1189 ( .A(\UART_RXFF/n442 ), .B(\UART_RXFF/n443 ),
.Z(\UART_RXFF/N56 ) );
notech_and3 \UART_RXFF/U1188 ( .A(iRXFIFOUsage[2]), .B(\UART_RXFF/USAGE[0] ), .C(iRXFIFOUsage[1]), .Z(\UART_RXFF/n424 ) );
notech_inv \UART_RXFF/U1187 ( .A(iRXFIFOWrite), .Z(\UART_RXFF/n441 ) );
notech_nand3 \UART_RXFF/U1185 ( .A(\UART_RXFF/n441 ), .B(n371), .C(n438),
.Z(\UART_RXFF/n436 ) );
notech_nor2 \UART_RXFF/U1184 ( .A(iRXFIFO64Full), .B(\UART_RXFF/n441 ), .Z(
\UART_RXFF/n365 ) );
notech_or2 \UART_RXFF/U1183 ( .A(\UART_RXFF/n365 ), .B(iRXFIFOClear), .Z(
\UART_RXFF/n294 ) );
notech_inv \UART_RXFF/U1182 ( .A(iRXFIFOClear), .Z(\UART_RXFF/n308 ) );
notech_nand2 \UART_RXFF/U1181 ( .A(\UART_RXFF/n308 ), .B(n371), .Z(
\UART_RXFF/n440 ) );
notech_nand2 \UART_RXFF/U1180 ( .A(\UART_RXFF/n294 ), .B(\UART_RXFF/n440 ),
.Z(\UART_RXFF/n439 ) );
notech_nand2 \UART_RXFF/U1179 ( .A(\UART_RXFF/n439 ), .B(\UART_RXFF/n436 ),
.Z(\UART_RXFF/n406 ) );
notech_ao3 \UART_RXFF/U1178 ( .A(\UART_RXFF/n436 ), .B(\UART_RXFF/n406 ),
.C(iRXFIFOClear), .Z(\UART_RXFF/n412 ) );
notech_and3 \UART_RXFF/U1177 ( .A(\UART_RXFF/n424 ), .B(iRXFIFOUsage[3]),
.C(\UART_RXFF/n412 ), .Z(\UART_RXFF/n427 ) );
notech_and2 \UART_RXFF/U1176 ( .A(\UART_RXFF/n427 ), .B(iRXFIFOUsage[4]),
.Z(\UART_RXFF/n435 ) );
notech_inv \UART_RXFF/U1175 ( .A(iRXFIFOUsage[1]), .Z(\UART_RXFF/n437 ) );
notech_inv \UART_RXFF/U1174 ( .A(\UART_RXFF/USAGE[0] ), .Z(\UART_RXFF/n438 ) );
notech_ao3 \UART_RXFF/U1173 ( .A(\UART_RXFF/n437 ), .B(\UART_RXFF/n438 ),
.C(iRXFIFOUsage[2]), .Z(\UART_RXFF/n415 ) );
notech_or2 \UART_RXFF/U1172 ( .A(\UART_RXFF/n436 ), .B(iRXFIFOClear), .Z(
\UART_RXFF/n408 ) );
notech_inv \UART_RXFF/U1171 ( .A(\UART_RXFF/n408 ), .Z(\UART_RXFF/n411 ) );
notech_nao3 \UART_RXFF/U1170 ( .C(iRXFIFOUsage[3]), .A(\UART_RXFF/n415 ),
.B(\UART_RXFF/n411 ), .Z(\UART_RXFF/n421 ) );
notech_nor2 \UART_RXFF/U1169 ( .A(\UART_RXFF/n421 ), .B(iRXFIFOUsage[4]),
.Z(\UART_RXFF/n426 ) );
notech_or2 \UART_RXFF/U1168 ( .A(\UART_RXFF/n435 ), .B(\UART_RXFF/n426 ),
.Z(\UART_RXFF/n429 ) );
notech_or2 \UART_RXFF/U1167 ( .A(\UART_RXFF/n408 ), .B(\UART_RXFF/n415 ),
.Z(\UART_RXFF/n433 ) );
notech_inv \UART_RXFF/U1166 ( .A(\UART_RXFF/n412 ), .Z(\UART_RXFF/n407 ) );
notech_or2 \UART_RXFF/U1165 ( .A(\UART_RXFF/n407 ), .B(\UART_RXFF/n424 ),
.Z(\UART_RXFF/n434 ) );
notech_and3 \UART_RXFF/U1164 ( .A(\UART_RXFF/n433 ), .B(\UART_RXFF/n434 ),
.C(\UART_RXFF/n406 ), .Z(\UART_RXFF/n423 ) );
notech_mux2 \UART_RXFF/U1163 ( .A(\UART_RXFF/n407 ), .B(\UART_RXFF/n408 ),
.S(iRXFIFOUsage[3]), .Z(\UART_RXFF/n432 ) );
notech_nand2 \UART_RXFF/U1162 ( .A(\UART_RXFF/n423 ), .B(\UART_RXFF/n432 ),
.Z(\UART_RXFF/n428 ) );
notech_mux2 \UART_RXFF/U1161 ( .A(\UART_RXFF/n412 ), .B(\UART_RXFF/n411 ),
.S(iRXFIFOUsage[4]), .Z(\UART_RXFF/n431 ) );
notech_or2 \UART_RXFF/U1160 ( .A(\UART_RXFF/n428 ), .B(\UART_RXFF/n431 ),
.Z(\UART_RXFF/n430 ) );
notech_mux2 \UART_RXFF/U1159 ( .A(\UART_RXFF/n429 ), .B(\UART_RXFF/n430 ),
.S(iRXFIFOUsage[5]), .Z(\UART_RXFF/n1685 ) );
notech_mux2 \UART_RXFF/U1158 ( .A(\UART_RXFF/n427 ), .B(\UART_RXFF/n428 ),
.S(iRXFIFOUsage[4]), .Z(\UART_RXFF/n425 ) );
notech_or2 \UART_RXFF/U1157 ( .A(\UART_RXFF/n425 ), .B(\UART_RXFF/n426 ),
.Z(\UART_RXFF/n1686 ) );
notech_nand2 \UART_RXFF/U1156 ( .A(\UART_RXFF/n412 ), .B(\UART_RXFF/n424 ),
.Z(\UART_RXFF/n422 ) );
notech_mux2 \UART_RXFF/U1155 ( .A(\UART_RXFF/n422 ), .B(\UART_RXFF/n423 ),
.S(iRXFIFOUsage[3]), .Z(\UART_RXFF/n420 ) );
notech_nand2 \UART_RXFF/U1154 ( .A(\UART_RXFF/n420 ), .B(\UART_RXFF/n421 ),
.Z(\UART_RXFF/n1687 ) );
notech_nand3 \UART_RXFF/U1153 ( .A(\UART_RXFF/n412 ), .B(
\UART_RXFF/USAGE[0] ), .C(iRXFIFOUsage[1]), .Z(\UART_RXFF/n416 ) );
notech_mux2 \UART_RXFF/U1152 ( .A(\UART_RXFF/n407 ), .B(\UART_RXFF/n408 ),
.S(\UART_RXFF/USAGE[0] ), .Z(\UART_RXFF/n419 ) );
notech_nand2 \UART_RXFF/U1151 ( .A(\UART_RXFF/n419 ), .B(\UART_RXFF/n406 ),
.Z(\UART_RXFF/n410 ) );
notech_mux2 \UART_RXFF/U1150 ( .A(\UART_RXFF/n412 ), .B(\UART_RXFF/n411 ),
.S(iRXFIFOUsage[1]), .Z(\UART_RXFF/n418 ) );
notech_nor2 \UART_RXFF/U1149 ( .A(\UART_RXFF/n410 ), .B(\UART_RXFF/n418 ),
.Z(\UART_RXFF/n417 ) );
notech_mux2 \UART_RXFF/U1148 ( .A(\UART_RXFF/n416 ), .B(\UART_RXFF/n417 ),
.S(iRXFIFOUsage[2]), .Z(\UART_RXFF/n413 ) );
notech_nand2 \UART_RXFF/U1147 ( .A(\UART_RXFF/n411 ), .B(\UART_RXFF/n415 ),
.Z(\UART_RXFF/n414 ) );
notech_nand2 \UART_RXFF/U1146 ( .A(\UART_RXFF/n413 ), .B(\UART_RXFF/n414 ),
.Z(\UART_RXFF/n1688 ) );
notech_mux2 \UART_RXFF/U1145 ( .A(\UART_RXFF/n411 ), .B(\UART_RXFF/n412 ),
.S(\UART_RXFF/USAGE[0] ), .Z(\UART_RXFF/n409 ) );
notech_mux2 \UART_RXFF/U1144 ( .A(\UART_RXFF/n409 ), .B(\UART_RXFF/n410 ),
.S(iRXFIFOUsage[1]), .Z(\UART_RXFF/n1689 ) );
notech_nand2 \UART_RXFF/U1143 ( .A(\UART_RXFF/n407 ), .B(\UART_RXFF/n408 ),
.Z(\UART_RXFF/n404 ) );
notech_inv \UART_RXFF/U1142 ( .A(\UART_RXFF/n406 ), .Z(\UART_RXFF/n405 ) );
notech_mux2 \UART_RXFF/U1141 ( .A(\UART_RXFF/n404 ), .B(\UART_RXFF/n405 ),
.S(\UART_RXFF/USAGE[0] ), .Z(\UART_RXFF/n1690 ) );
notech_inv \UART_RXFF/U1140 ( .A(\UART_RXFF/iWRAddr[3] ), .Z(
\UART_RXFF/n302 ) );
notech_ao3 \UART_RXFF/U1138 ( .A(\UART_IS_RI/n1 ), .B(\UART_RXFF/n365 ),
.C(\UART_RXFF/iWRAddr[5] ), .Z(\UART_RXFF/n375 ) );
notech_ao3 \UART_RXFF/U1137 ( .A(\UART_RXFF/n302 ), .B(\UART_RXFF/n375 ),
.C(\UART_RXFF/iWRAddr[4] ), .Z(\UART_RXFF/n395 ) );
notech_inv \UART_RXFF/U1136 ( .A(\UART_RXFF/iWRAddr[0] ), .Z(
\UART_RXFF/n397 ) );
notech_inv \UART_RXFF/U1135 ( .A(\UART_RXFF/iWRAddr[2] ), .Z(
\UART_RXFF/n300 ) );
notech_inv \UART_RXFF/U1134 ( .A(\UART_RXFF/iWRAddr[1] ), .Z(
\UART_RXFF/n298 ) );
notech_and3 \UART_RXFF/U1133 ( .A(\UART_RXFF/n397 ), .B(\UART_RXFF/n300 ),
.C(\UART_RXFF/n298 ), .Z(\UART_RXFF/n336 ) );
notech_and2 \UART_RXFF/U1132 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n403 ) );
notech_mux2 \UART_RXFF/U1131 ( .A(\UART_RXFF/iFIFOMem[0][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1691 ) );
notech_mux2 \UART_RXFF/U1130 ( .A(\UART_RXFF/iFIFOMem[0][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1692 ) );
notech_mux2 \UART_RXFF/U1129 ( .A(\UART_RXFF/iFIFOMem[0][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1693 ) );
notech_mux2 \UART_RXFF/U1128 ( .A(\UART_RXFF/iFIFOMem[0][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1694 ) );
notech_mux2 \UART_RXFF/U1127 ( .A(\UART_RXFF/iFIFOMem[0][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1695 ) );
notech_mux2 \UART_RXFF/U1126 ( .A(\UART_RXFF/iFIFOMem[0][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1696 ) );
notech_mux2 \UART_RXFF/U1125 ( .A(\UART_RXFF/iFIFOMem[0][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1697 ) );
notech_mux2 \UART_RXFF/U1124 ( .A(\UART_RXFF/iFIFOMem[0][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1698 ) );
notech_mux2 \UART_RXFF/U1123 ( .A(\UART_RXFF/iFIFOMem[0][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1699 ) );
notech_mux2 \UART_RXFF/U1122 ( .A(\UART_RXFF/iFIFOMem[0][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1700 ) );
notech_mux2 \UART_RXFF/U1121 ( .A(\UART_RXFF/iFIFOMem[0][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n403 ), .Z(\UART_RXFF/n1701 ) );
notech_and3 \UART_RXFF/U1120 ( .A(\UART_RXFF/iWRAddr[0] ), .B(
\UART_RXFF/n300 ), .C(\UART_RXFF/n298 ), .Z(\UART_RXFF/n334 ) );
notech_and2 \UART_RXFF/U1119 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n402 ) );
notech_mux2 \UART_RXFF/U1118 ( .A(\UART_RXFF/iFIFOMem[1][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1702 ) );
notech_mux2 \UART_RXFF/U1117 ( .A(\UART_RXFF/iFIFOMem[1][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1703 ) );
notech_mux2 \UART_RXFF/U1116 ( .A(\UART_RXFF/iFIFOMem[1][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1704 ) );
notech_mux2 \UART_RXFF/U1115 ( .A(\UART_RXFF/iFIFOMem[1][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1705 ) );
notech_mux2 \UART_RXFF/U1114 ( .A(\UART_RXFF/iFIFOMem[1][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1706 ) );
notech_mux2 \UART_RXFF/U1113 ( .A(\UART_RXFF/iFIFOMem[1][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1707 ) );
notech_mux2 \UART_RXFF/U1112 ( .A(\UART_RXFF/iFIFOMem[1][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1708 ) );
notech_mux2 \UART_RXFF/U1111 ( .A(\UART_RXFF/iFIFOMem[1][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1709 ) );
notech_mux2 \UART_RXFF/U1110 ( .A(\UART_RXFF/iFIFOMem[1][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1710 ) );
notech_mux2 \UART_RXFF/U1109 ( .A(\UART_RXFF/iFIFOMem[1][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1711 ) );
notech_mux2 \UART_RXFF/U1108 ( .A(\UART_RXFF/iFIFOMem[1][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n402 ), .Z(\UART_RXFF/n1712 ) );
notech_and3 \UART_RXFF/U1107 ( .A(\UART_RXFF/iWRAddr[1] ), .B(
\UART_RXFF/n300 ), .C(\UART_RXFF/n397 ), .Z(\UART_RXFF/n332 ) );
notech_and2 \UART_RXFF/U1106 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n401 ) );
notech_mux2 \UART_RXFF/U1105 ( .A(\UART_RXFF/iFIFOMem[2][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1713 ) );
notech_mux2 \UART_RXFF/U1104 ( .A(\UART_RXFF/iFIFOMem[2][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1714 ) );
notech_mux2 \UART_RXFF/U1103 ( .A(\UART_RXFF/iFIFOMem[2][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1715 ) );
notech_mux2 \UART_RXFF/U1102 ( .A(\UART_RXFF/iFIFOMem[2][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1716 ) );
notech_mux2 \UART_RXFF/U1101 ( .A(\UART_RXFF/iFIFOMem[2][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1717 ) );
notech_mux2 \UART_RXFF/U1100 ( .A(\UART_RXFF/iFIFOMem[2][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1718 ) );
notech_mux2 \UART_RXFF/U1099 ( .A(\UART_RXFF/iFIFOMem[2][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1719 ) );
notech_mux2 \UART_RXFF/U1098 ( .A(\UART_RXFF/iFIFOMem[2][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1720 ) );
notech_mux2 \UART_RXFF/U1097 ( .A(\UART_RXFF/iFIFOMem[2][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1721 ) );
notech_mux2 \UART_RXFF/U1096 ( .A(\UART_RXFF/iFIFOMem[2][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1722 ) );
notech_mux2 \UART_RXFF/U1095 ( .A(\UART_RXFF/iFIFOMem[2][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n401 ), .Z(\UART_RXFF/n1723 ) );
notech_and3 \UART_RXFF/U1094 ( .A(\UART_RXFF/iWRAddr[0] ), .B(
\UART_RXFF/iWRAddr[1] ), .C(\UART_RXFF/n300 ), .Z(\UART_RXFF/n330 ) );
notech_and2 \UART_RXFF/U1093 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n400 ) );
notech_mux2 \UART_RXFF/U1092 ( .A(\UART_RXFF/iFIFOMem[3][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1724 ) );
notech_mux2 \UART_RXFF/U1091 ( .A(\UART_RXFF/iFIFOMem[3][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1725 ) );
notech_mux2 \UART_RXFF/U1090 ( .A(\UART_RXFF/iFIFOMem[3][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1726 ) );
notech_mux2 \UART_RXFF/U1089 ( .A(\UART_RXFF/iFIFOMem[3][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1727 ) );
notech_mux2 \UART_RXFF/U1088 ( .A(\UART_RXFF/iFIFOMem[3][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1728 ) );
notech_mux2 \UART_RXFF/U1087 ( .A(\UART_RXFF/iFIFOMem[3][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1729 ) );
notech_mux2 \UART_RXFF/U1086 ( .A(\UART_RXFF/iFIFOMem[3][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1730 ) );
notech_mux2 \UART_RXFF/U1085 ( .A(\UART_RXFF/iFIFOMem[3][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1731 ) );
notech_mux2 \UART_RXFF/U1084 ( .A(\UART_RXFF/iFIFOMem[3][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1732 ) );
notech_mux2 \UART_RXFF/U1083 ( .A(\UART_RXFF/iFIFOMem[3][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1733 ) );
notech_mux2 \UART_RXFF/U1082 ( .A(\UART_RXFF/iFIFOMem[3][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n400 ), .Z(\UART_RXFF/n1734 ) );
notech_and3 \UART_RXFF/U1081 ( .A(\UART_RXFF/iWRAddr[2] ), .B(
\UART_RXFF/n298 ), .C(\UART_RXFF/n397 ), .Z(\UART_RXFF/n328 ) );
notech_and2 \UART_RXFF/U1080 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n399 ) );
notech_mux2 \UART_RXFF/U1079 ( .A(\UART_RXFF/iFIFOMem[4][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1735 ) );
notech_mux2 \UART_RXFF/U1078 ( .A(\UART_RXFF/iFIFOMem[4][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1736 ) );
notech_mux2 \UART_RXFF/U1077 ( .A(\UART_RXFF/iFIFOMem[4][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1737 ) );
notech_mux2 \UART_RXFF/U1076 ( .A(\UART_RXFF/iFIFOMem[4][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1738 ) );
notech_mux2 \UART_RXFF/U1075 ( .A(\UART_RXFF/iFIFOMem[4][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1739 ) );
notech_mux2 \UART_RXFF/U1074 ( .A(\UART_RXFF/iFIFOMem[4][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1740 ) );
notech_mux2 \UART_RXFF/U1073 ( .A(\UART_RXFF/iFIFOMem[4][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1741 ) );
notech_mux2 \UART_RXFF/U1072 ( .A(\UART_RXFF/iFIFOMem[4][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1742 ) );
notech_mux2 \UART_RXFF/U1071 ( .A(\UART_RXFF/iFIFOMem[4][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1743 ) );
notech_mux2 \UART_RXFF/U1070 ( .A(\UART_RXFF/iFIFOMem[4][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1744 ) );
notech_mux2 \UART_RXFF/U1069 ( .A(\UART_RXFF/iFIFOMem[4][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n399 ), .Z(\UART_RXFF/n1745 ) );
notech_and3 \UART_RXFF/U1068 ( .A(\UART_RXFF/iWRAddr[0] ), .B(
\UART_RXFF/iWRAddr[2] ), .C(\UART_RXFF/n298 ), .Z(\UART_RXFF/n326 ) );
notech_and2 \UART_RXFF/U1067 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n398 ) );
notech_mux2 \UART_RXFF/U1066 ( .A(\UART_RXFF/iFIFOMem[5][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1746 ) );
notech_mux2 \UART_RXFF/U1065 ( .A(\UART_RXFF/iFIFOMem[5][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1747 ) );
notech_mux2 \UART_RXFF/U1064 ( .A(\UART_RXFF/iFIFOMem[5][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1748 ) );
notech_mux2 \UART_RXFF/U1063 ( .A(\UART_RXFF/iFIFOMem[5][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1749 ) );
notech_mux2 \UART_RXFF/U1062 ( .A(\UART_RXFF/iFIFOMem[5][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1750 ) );
notech_mux2 \UART_RXFF/U1061 ( .A(\UART_RXFF/iFIFOMem[5][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1751 ) );
notech_mux2 \UART_RXFF/U1060 ( .A(\UART_RXFF/iFIFOMem[5][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1752 ) );
notech_mux2 \UART_RXFF/U1059 ( .A(\UART_RXFF/iFIFOMem[5][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1753 ) );
notech_mux2 \UART_RXFF/U1058 ( .A(\UART_RXFF/iFIFOMem[5][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1754 ) );
notech_mux2 \UART_RXFF/U1057 ( .A(\UART_RXFF/iFIFOMem[5][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1755 ) );
notech_mux2 \UART_RXFF/U1056 ( .A(\UART_RXFF/iFIFOMem[5][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n398 ), .Z(\UART_RXFF/n1756 ) );
notech_and3 \UART_RXFF/U1055 ( .A(\UART_RXFF/iWRAddr[1] ), .B(
\UART_RXFF/iWRAddr[2] ), .C(\UART_RXFF/n397 ), .Z(\UART_RXFF/n324 ) );
notech_and2 \UART_RXFF/U1054 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n396 ) );
notech_mux2 \UART_RXFF/U1053 ( .A(\UART_RXFF/iFIFOMem[6][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1757 ) );
notech_mux2 \UART_RXFF/U1052 ( .A(\UART_RXFF/iFIFOMem[6][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1758 ) );
notech_mux2 \UART_RXFF/U1051 ( .A(\UART_RXFF/iFIFOMem[6][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1759 ) );
notech_mux2 \UART_RXFF/U1050 ( .A(\UART_RXFF/iFIFOMem[6][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1760 ) );
notech_mux2 \UART_RXFF/U1049 ( .A(\UART_RXFF/iFIFOMem[6][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1761 ) );
notech_mux2 \UART_RXFF/U1048 ( .A(\UART_RXFF/iFIFOMem[6][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1762 ) );
notech_mux2 \UART_RXFF/U1047 ( .A(\UART_RXFF/iFIFOMem[6][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1763 ) );
notech_mux2 \UART_RXFF/U1046 ( .A(\UART_RXFF/iFIFOMem[6][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1764 ) );
notech_mux2 \UART_RXFF/U1045 ( .A(\UART_RXFF/iFIFOMem[6][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1765 ) );
notech_mux2 \UART_RXFF/U1044 ( .A(\UART_RXFF/iFIFOMem[6][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1766 ) );
notech_mux2 \UART_RXFF/U1043 ( .A(\UART_RXFF/iFIFOMem[6][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n396 ), .Z(\UART_RXFF/n1767 ) );
notech_and3 \UART_RXFF/U1042 ( .A(\UART_RXFF/iWRAddr[0] ), .B(
\UART_RXFF/iWRAddr[2] ), .C(\UART_RXFF/iWRAddr[1] ), .Z(
\UART_RXFF/n322 ) );
notech_and2 \UART_RXFF/U1041 ( .A(\UART_RXFF/n395 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n394 ) );
notech_mux2 \UART_RXFF/U1040 ( .A(\UART_RXFF/iFIFOMem[7][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1768 ) );
notech_mux2 \UART_RXFF/U1039 ( .A(\UART_RXFF/iFIFOMem[7][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1769 ) );
notech_mux2 \UART_RXFF/U1038 ( .A(\UART_RXFF/iFIFOMem[7][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1770 ) );
notech_mux2 \UART_RXFF/U1037 ( .A(\UART_RXFF/iFIFOMem[7][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1771 ) );
notech_mux2 \UART_RXFF/U1036 ( .A(\UART_RXFF/iFIFOMem[7][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1772 ) );
notech_mux2 \UART_RXFF/U1035 ( .A(\UART_RXFF/iFIFOMem[7][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1773 ) );
notech_mux2 \UART_RXFF/U1034 ( .A(\UART_RXFF/iFIFOMem[7][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1774 ) );
notech_mux2 \UART_RXFF/U1033 ( .A(\UART_RXFF/iFIFOMem[7][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1775 ) );
notech_mux2 \UART_RXFF/U1032 ( .A(\UART_RXFF/iFIFOMem[7][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1776 ) );
notech_mux2 \UART_RXFF/U1031 ( .A(\UART_RXFF/iFIFOMem[7][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1777 ) );
notech_mux2 \UART_RXFF/U1030 ( .A(\UART_RXFF/iFIFOMem[7][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n394 ), .Z(\UART_RXFF/n1778 ) );
notech_ao3 \UART_RXFF/U1029 ( .A(\UART_RXFF/iWRAddr[3] ), .B(
\UART_RXFF/n375 ), .C(\UART_RXFF/iWRAddr[4] ), .Z(\UART_RXFF/n386 ) );
notech_and2 \UART_RXFF/U1028 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n393 ) );
notech_mux2 \UART_RXFF/U1027 ( .A(\UART_RXFF/iFIFOMem[8][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1779 ) );
notech_mux2 \UART_RXFF/U1026 ( .A(\UART_RXFF/iFIFOMem[8][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1780 ) );
notech_mux2 \UART_RXFF/U1025 ( .A(\UART_RXFF/iFIFOMem[8][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1781 ) );
notech_mux2 \UART_RXFF/U1024 ( .A(\UART_RXFF/iFIFOMem[8][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1782 ) );
notech_mux2 \UART_RXFF/U1023 ( .A(\UART_RXFF/iFIFOMem[8][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1783 ) );
notech_mux2 \UART_RXFF/U1022 ( .A(\UART_RXFF/iFIFOMem[8][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1784 ) );
notech_mux2 \UART_RXFF/U1021 ( .A(\UART_RXFF/iFIFOMem[8][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1785 ) );
notech_mux2 \UART_RXFF/U1020 ( .A(\UART_RXFF/iFIFOMem[8][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1786 ) );
notech_mux2 \UART_RXFF/U1019 ( .A(\UART_RXFF/iFIFOMem[8][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1787 ) );
notech_mux2 \UART_RXFF/U1018 ( .A(\UART_RXFF/iFIFOMem[8][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1788 ) );
notech_mux2 \UART_RXFF/U1017 ( .A(\UART_RXFF/iFIFOMem[8][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n393 ), .Z(\UART_RXFF/n1789 ) );
notech_and2 \UART_RXFF/U1016 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n392 ) );
notech_mux2 \UART_RXFF/U1015 ( .A(\UART_RXFF/iFIFOMem[9][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1790 ) );
notech_mux2 \UART_RXFF/U1014 ( .A(\UART_RXFF/iFIFOMem[9][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1791 ) );
notech_mux2 \UART_RXFF/U1013 ( .A(\UART_RXFF/iFIFOMem[9][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1792 ) );
notech_mux2 \UART_RXFF/U1012 ( .A(\UART_RXFF/iFIFOMem[9][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1793 ) );
notech_mux2 \UART_RXFF/U1011 ( .A(\UART_RXFF/iFIFOMem[9][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1794 ) );
notech_mux2 \UART_RXFF/U1010 ( .A(\UART_RXFF/iFIFOMem[9][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1795 ) );
notech_mux2 \UART_RXFF/U1009 ( .A(\UART_RXFF/iFIFOMem[9][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1796 ) );
notech_mux2 \UART_RXFF/U1008 ( .A(\UART_RXFF/iFIFOMem[9][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1797 ) );
notech_mux2 \UART_RXFF/U1007 ( .A(\UART_RXFF/iFIFOMem[9][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1798 ) );
notech_mux2 \UART_RXFF/U1006 ( .A(\UART_RXFF/iFIFOMem[9][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1799 ) );
notech_mux2 \UART_RXFF/U1005 ( .A(\UART_RXFF/iFIFOMem[9][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n392 ), .Z(\UART_RXFF/n1800 ) );
notech_and2 \UART_RXFF/U1004 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n391 ) );
notech_mux2 \UART_RXFF/U1003 ( .A(\UART_RXFF/iFIFOMem[10][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1801 ) );
notech_mux2 \UART_RXFF/U1002 ( .A(\UART_RXFF/iFIFOMem[10][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1802 ) );
notech_mux2 \UART_RXFF/U1001 ( .A(\UART_RXFF/iFIFOMem[10][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1803 ) );
notech_mux2 \UART_RXFF/U1000 ( .A(\UART_RXFF/iFIFOMem[10][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1804 ) );
notech_mux2 \UART_RXFF/U999 ( .A(\UART_RXFF/iFIFOMem[10][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1805 ) );
notech_mux2 \UART_RXFF/U998 ( .A(\UART_RXFF/iFIFOMem[10][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1806 ) );
notech_mux2 \UART_RXFF/U997 ( .A(\UART_RXFF/iFIFOMem[10][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1807 ) );
notech_mux2 \UART_RXFF/U996 ( .A(\UART_RXFF/iFIFOMem[10][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1808 ) );
notech_mux2 \UART_RXFF/U995 ( .A(\UART_RXFF/iFIFOMem[10][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1809 ) );
notech_mux2 \UART_RXFF/U994 ( .A(\UART_RXFF/iFIFOMem[10][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1810 ) );
notech_mux2 \UART_RXFF/U993 ( .A(\UART_RXFF/iFIFOMem[10][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n391 ), .Z(\UART_RXFF/n1811 ) );
notech_and2 \UART_RXFF/U992 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n390 ) );
notech_mux2 \UART_RXFF/U991 ( .A(\UART_RXFF/iFIFOMem[11][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1812 ) );
notech_mux2 \UART_RXFF/U990 ( .A(\UART_RXFF/iFIFOMem[11][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1813 ) );
notech_mux2 \UART_RXFF/U989 ( .A(\UART_RXFF/iFIFOMem[11][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1814 ) );
notech_mux2 \UART_RXFF/U988 ( .A(\UART_RXFF/iFIFOMem[11][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1815 ) );
notech_mux2 \UART_RXFF/U987 ( .A(\UART_RXFF/iFIFOMem[11][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1816 ) );
notech_mux2 \UART_RXFF/U986 ( .A(\UART_RXFF/iFIFOMem[11][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1817 ) );
notech_mux2 \UART_RXFF/U985 ( .A(\UART_RXFF/iFIFOMem[11][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1818 ) );
notech_mux2 \UART_RXFF/U984 ( .A(\UART_RXFF/iFIFOMem[11][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1819 ) );
notech_mux2 \UART_RXFF/U983 ( .A(\UART_RXFF/iFIFOMem[11][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1820 ) );
notech_mux2 \UART_RXFF/U982 ( .A(\UART_RXFF/iFIFOMem[11][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1821 ) );
notech_mux2 \UART_RXFF/U981 ( .A(\UART_RXFF/iFIFOMem[11][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n390 ), .Z(\UART_RXFF/n1822 ) );
notech_and2 \UART_RXFF/U980 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n389 ) );
notech_mux2 \UART_RXFF/U979 ( .A(\UART_RXFF/iFIFOMem[12][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1823 ) );
notech_mux2 \UART_RXFF/U978 ( .A(\UART_RXFF/iFIFOMem[12][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1824 ) );
notech_mux2 \UART_RXFF/U977 ( .A(\UART_RXFF/iFIFOMem[12][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1825 ) );
notech_mux2 \UART_RXFF/U976 ( .A(\UART_RXFF/iFIFOMem[12][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1826 ) );
notech_mux2 \UART_RXFF/U975 ( .A(\UART_RXFF/iFIFOMem[12][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1827 ) );
notech_mux2 \UART_RXFF/U974 ( .A(\UART_RXFF/iFIFOMem[12][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1828 ) );
notech_mux2 \UART_RXFF/U973 ( .A(\UART_RXFF/iFIFOMem[12][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1829 ) );
notech_mux2 \UART_RXFF/U972 ( .A(\UART_RXFF/iFIFOMem[12][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1830 ) );
notech_mux2 \UART_RXFF/U971 ( .A(\UART_RXFF/iFIFOMem[12][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1831 ) );
notech_mux2 \UART_RXFF/U970 ( .A(\UART_RXFF/iFIFOMem[12][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1832 ) );
notech_mux2 \UART_RXFF/U969 ( .A(\UART_RXFF/iFIFOMem[12][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n389 ), .Z(\UART_RXFF/n1833 ) );
notech_and2 \UART_RXFF/U968 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n388 ) );
notech_mux2 \UART_RXFF/U967 ( .A(\UART_RXFF/iFIFOMem[13][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1834 ) );
notech_mux2 \UART_RXFF/U966 ( .A(\UART_RXFF/iFIFOMem[13][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1835 ) );
notech_mux2 \UART_RXFF/U965 ( .A(\UART_RXFF/iFIFOMem[13][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1836 ) );
notech_mux2 \UART_RXFF/U964 ( .A(\UART_RXFF/iFIFOMem[13][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1837 ) );
notech_mux2 \UART_RXFF/U963 ( .A(\UART_RXFF/iFIFOMem[13][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1838 ) );
notech_mux2 \UART_RXFF/U962 ( .A(\UART_RXFF/iFIFOMem[13][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1839 ) );
notech_mux2 \UART_RXFF/U961 ( .A(\UART_RXFF/iFIFOMem[13][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1840 ) );
notech_mux2 \UART_RXFF/U960 ( .A(\UART_RXFF/iFIFOMem[13][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1841 ) );
notech_mux2 \UART_RXFF/U959 ( .A(\UART_RXFF/iFIFOMem[13][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1842 ) );
notech_mux2 \UART_RXFF/U958 ( .A(\UART_RXFF/iFIFOMem[13][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1843 ) );
notech_mux2 \UART_RXFF/U957 ( .A(\UART_RXFF/iFIFOMem[13][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n388 ), .Z(\UART_RXFF/n1844 ) );
notech_and2 \UART_RXFF/U956 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n387 ) );
notech_mux2 \UART_RXFF/U955 ( .A(\UART_RXFF/iFIFOMem[14][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1845 ) );
notech_mux2 \UART_RXFF/U954 ( .A(\UART_RXFF/iFIFOMem[14][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1846 ) );
notech_mux2 \UART_RXFF/U953 ( .A(\UART_RXFF/iFIFOMem[14][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1847 ) );
notech_mux2 \UART_RXFF/U952 ( .A(\UART_RXFF/iFIFOMem[14][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1848 ) );
notech_mux2 \UART_RXFF/U951 ( .A(\UART_RXFF/iFIFOMem[14][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1849 ) );
notech_mux2 \UART_RXFF/U950 ( .A(\UART_RXFF/iFIFOMem[14][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1850 ) );
notech_mux2 \UART_RXFF/U949 ( .A(\UART_RXFF/iFIFOMem[14][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1851 ) );
notech_mux2 \UART_RXFF/U948 ( .A(\UART_RXFF/iFIFOMem[14][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1852 ) );
notech_mux2 \UART_RXFF/U947 ( .A(\UART_RXFF/iFIFOMem[14][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1853 ) );
notech_mux2 \UART_RXFF/U946 ( .A(\UART_RXFF/iFIFOMem[14][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1854 ) );
notech_mux2 \UART_RXFF/U945 ( .A(\UART_RXFF/iFIFOMem[14][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n387 ), .Z(\UART_RXFF/n1855 ) );
notech_and2 \UART_RXFF/U944 ( .A(\UART_RXFF/n386 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n385 ) );
notech_mux2 \UART_RXFF/U943 ( .A(\UART_RXFF/iFIFOMem[15][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1856 ) );
notech_mux2 \UART_RXFF/U942 ( .A(\UART_RXFF/iFIFOMem[15][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1857 ) );
notech_mux2 \UART_RXFF/U941 ( .A(\UART_RXFF/iFIFOMem[15][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1858 ) );
notech_mux2 \UART_RXFF/U940 ( .A(\UART_RXFF/iFIFOMem[15][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1859 ) );
notech_mux2 \UART_RXFF/U939 ( .A(\UART_RXFF/iFIFOMem[15][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1860 ) );
notech_mux2 \UART_RXFF/U938 ( .A(\UART_RXFF/iFIFOMem[15][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1861 ) );
notech_mux2 \UART_RXFF/U937 ( .A(\UART_RXFF/iFIFOMem[15][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1862 ) );
notech_mux2 \UART_RXFF/U936 ( .A(\UART_RXFF/iFIFOMem[15][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1863 ) );
notech_mux2 \UART_RXFF/U935 ( .A(\UART_RXFF/iFIFOMem[15][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1864 ) );
notech_mux2 \UART_RXFF/U934 ( .A(\UART_RXFF/iFIFOMem[15][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1865 ) );
notech_mux2 \UART_RXFF/U933 ( .A(\UART_RXFF/iFIFOMem[15][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n385 ), .Z(\UART_RXFF/n1866 ) );
notech_ao3 \UART_RXFF/U932 ( .A(\UART_RXFF/iWRAddr[4] ), .B(
\UART_RXFF/n375 ), .C(\UART_RXFF/iWRAddr[3] ), .Z(\UART_RXFF/n377 ) );
notech_and2 \UART_RXFF/U931 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n384 ) );
notech_mux2 \UART_RXFF/U930 ( .A(\UART_RXFF/iFIFOMem[16][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1867 ) );
notech_mux2 \UART_RXFF/U929 ( .A(\UART_RXFF/iFIFOMem[16][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1868 ) );
notech_mux2 \UART_RXFF/U928 ( .A(\UART_RXFF/iFIFOMem[16][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1869 ) );
notech_mux2 \UART_RXFF/U927 ( .A(\UART_RXFF/iFIFOMem[16][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1870 ) );
notech_mux2 \UART_RXFF/U926 ( .A(\UART_RXFF/iFIFOMem[16][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1871 ) );
notech_mux2 \UART_RXFF/U925 ( .A(\UART_RXFF/iFIFOMem[16][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1872 ) );
notech_mux2 \UART_RXFF/U924 ( .A(\UART_RXFF/iFIFOMem[16][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1873 ) );
notech_mux2 \UART_RXFF/U923 ( .A(\UART_RXFF/iFIFOMem[16][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1874 ) );
notech_mux2 \UART_RXFF/U922 ( .A(\UART_RXFF/iFIFOMem[16][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1875 ) );
notech_mux2 \UART_RXFF/U921 ( .A(\UART_RXFF/iFIFOMem[16][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1876 ) );
notech_mux2 \UART_RXFF/U920 ( .A(\UART_RXFF/iFIFOMem[16][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n384 ), .Z(\UART_RXFF/n1877 ) );
notech_and2 \UART_RXFF/U919 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n383 ) );
notech_mux2 \UART_RXFF/U918 ( .A(\UART_RXFF/iFIFOMem[17][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1878 ) );
notech_mux2 \UART_RXFF/U917 ( .A(\UART_RXFF/iFIFOMem[17][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1879 ) );
notech_mux2 \UART_RXFF/U916 ( .A(\UART_RXFF/iFIFOMem[17][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1880 ) );
notech_mux2 \UART_RXFF/U915 ( .A(\UART_RXFF/iFIFOMem[17][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1881 ) );
notech_mux2 \UART_RXFF/U914 ( .A(\UART_RXFF/iFIFOMem[17][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1882 ) );
notech_mux2 \UART_RXFF/U913 ( .A(\UART_RXFF/iFIFOMem[17][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1883 ) );
notech_mux2 \UART_RXFF/U912 ( .A(\UART_RXFF/iFIFOMem[17][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1884 ) );
notech_mux2 \UART_RXFF/U911 ( .A(\UART_RXFF/iFIFOMem[17][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1885 ) );
notech_mux2 \UART_RXFF/U910 ( .A(\UART_RXFF/iFIFOMem[17][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1886 ) );
notech_mux2 \UART_RXFF/U909 ( .A(\UART_RXFF/iFIFOMem[17][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1887 ) );
notech_mux2 \UART_RXFF/U908 ( .A(\UART_RXFF/iFIFOMem[17][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n383 ), .Z(\UART_RXFF/n1888 ) );
notech_and2 \UART_RXFF/U907 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n382 ) );
notech_mux2 \UART_RXFF/U906 ( .A(\UART_RXFF/iFIFOMem[18][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1889 ) );
notech_mux2 \UART_RXFF/U905 ( .A(\UART_RXFF/iFIFOMem[18][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1890 ) );
notech_mux2 \UART_RXFF/U904 ( .A(\UART_RXFF/iFIFOMem[18][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1891 ) );
notech_mux2 \UART_RXFF/U903 ( .A(\UART_RXFF/iFIFOMem[18][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1892 ) );
notech_mux2 \UART_RXFF/U902 ( .A(\UART_RXFF/iFIFOMem[18][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1893 ) );
notech_mux2 \UART_RXFF/U901 ( .A(\UART_RXFF/iFIFOMem[18][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1894 ) );
notech_mux2 \UART_RXFF/U900 ( .A(\UART_RXFF/iFIFOMem[18][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1895 ) );
notech_mux2 \UART_RXFF/U899 ( .A(\UART_RXFF/iFIFOMem[18][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1896 ) );
notech_mux2 \UART_RXFF/U898 ( .A(\UART_RXFF/iFIFOMem[18][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1897 ) );
notech_mux2 \UART_RXFF/U897 ( .A(\UART_RXFF/iFIFOMem[18][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1898 ) );
notech_mux2 \UART_RXFF/U896 ( .A(\UART_RXFF/iFIFOMem[18][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n382 ), .Z(\UART_RXFF/n1899 ) );
notech_and2 \UART_RXFF/U895 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n381 ) );
notech_mux2 \UART_RXFF/U894 ( .A(\UART_RXFF/iFIFOMem[19][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1900 ) );
notech_mux2 \UART_RXFF/U893 ( .A(\UART_RXFF/iFIFOMem[19][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1901 ) );
notech_mux2 \UART_RXFF/U892 ( .A(\UART_RXFF/iFIFOMem[19][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1902 ) );
notech_mux2 \UART_RXFF/U891 ( .A(\UART_RXFF/iFIFOMem[19][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1903 ) );
notech_mux2 \UART_RXFF/U890 ( .A(\UART_RXFF/iFIFOMem[19][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1904 ) );
notech_mux2 \UART_RXFF/U889 ( .A(\UART_RXFF/iFIFOMem[19][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1905 ) );
notech_mux2 \UART_RXFF/U888 ( .A(\UART_RXFF/iFIFOMem[19][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1906 ) );
notech_mux2 \UART_RXFF/U887 ( .A(\UART_RXFF/iFIFOMem[19][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1907 ) );
notech_mux2 \UART_RXFF/U886 ( .A(\UART_RXFF/iFIFOMem[19][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1908 ) );
notech_mux2 \UART_RXFF/U885 ( .A(\UART_RXFF/iFIFOMem[19][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1909 ) );
notech_mux2 \UART_RXFF/U884 ( .A(\UART_RXFF/iFIFOMem[19][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n381 ), .Z(\UART_RXFF/n1910 ) );
notech_and2 \UART_RXFF/U883 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n380 ) );
notech_mux2 \UART_RXFF/U882 ( .A(\UART_RXFF/iFIFOMem[20][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1911 ) );
notech_mux2 \UART_RXFF/U881 ( .A(\UART_RXFF/iFIFOMem[20][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1912 ) );
notech_mux2 \UART_RXFF/U880 ( .A(\UART_RXFF/iFIFOMem[20][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1913 ) );
notech_mux2 \UART_RXFF/U879 ( .A(\UART_RXFF/iFIFOMem[20][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1914 ) );
notech_mux2 \UART_RXFF/U878 ( .A(\UART_RXFF/iFIFOMem[20][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1915 ) );
notech_mux2 \UART_RXFF/U877 ( .A(\UART_RXFF/iFIFOMem[20][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1916 ) );
notech_mux2 \UART_RXFF/U876 ( .A(\UART_RXFF/iFIFOMem[20][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1917 ) );
notech_mux2 \UART_RXFF/U875 ( .A(\UART_RXFF/iFIFOMem[20][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1918 ) );
notech_mux2 \UART_RXFF/U874 ( .A(\UART_RXFF/iFIFOMem[20][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1919 ) );
notech_mux2 \UART_RXFF/U873 ( .A(\UART_RXFF/iFIFOMem[20][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1920 ) );
notech_mux2 \UART_RXFF/U872 ( .A(\UART_RXFF/iFIFOMem[20][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n380 ), .Z(\UART_RXFF/n1921 ) );
notech_and2 \UART_RXFF/U871 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n379 ) );
notech_mux2 \UART_RXFF/U870 ( .A(\UART_RXFF/iFIFOMem[21][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1922 ) );
notech_mux2 \UART_RXFF/U869 ( .A(\UART_RXFF/iFIFOMem[21][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1923 ) );
notech_mux2 \UART_RXFF/U868 ( .A(\UART_RXFF/iFIFOMem[21][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1924 ) );
notech_mux2 \UART_RXFF/U867 ( .A(\UART_RXFF/iFIFOMem[21][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1925 ) );
notech_mux2 \UART_RXFF/U866 ( .A(\UART_RXFF/iFIFOMem[21][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1926 ) );
notech_mux2 \UART_RXFF/U865 ( .A(\UART_RXFF/iFIFOMem[21][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1927 ) );
notech_mux2 \UART_RXFF/U864 ( .A(\UART_RXFF/iFIFOMem[21][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1928 ) );
notech_mux2 \UART_RXFF/U863 ( .A(\UART_RXFF/iFIFOMem[21][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1929 ) );
notech_mux2 \UART_RXFF/U862 ( .A(\UART_RXFF/iFIFOMem[21][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1930 ) );
notech_mux2 \UART_RXFF/U861 ( .A(\UART_RXFF/iFIFOMem[21][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1931 ) );
notech_mux2 \UART_RXFF/U860 ( .A(\UART_RXFF/iFIFOMem[21][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n379 ), .Z(\UART_RXFF/n1932 ) );
notech_and2 \UART_RXFF/U859 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n378 ) );
notech_mux2 \UART_RXFF/U858 ( .A(\UART_RXFF/iFIFOMem[22][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1933 ) );
notech_mux2 \UART_RXFF/U857 ( .A(\UART_RXFF/iFIFOMem[22][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1934 ) );
notech_mux2 \UART_RXFF/U856 ( .A(\UART_RXFF/iFIFOMem[22][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1935 ) );
notech_mux2 \UART_RXFF/U855 ( .A(\UART_RXFF/iFIFOMem[22][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1936 ) );
notech_mux2 \UART_RXFF/U854 ( .A(\UART_RXFF/iFIFOMem[22][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1937 ) );
notech_mux2 \UART_RXFF/U853 ( .A(\UART_RXFF/iFIFOMem[22][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1938 ) );
notech_mux2 \UART_RXFF/U852 ( .A(\UART_RXFF/iFIFOMem[22][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1939 ) );
notech_mux2 \UART_RXFF/U851 ( .A(\UART_RXFF/iFIFOMem[22][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1940 ) );
notech_mux2 \UART_RXFF/U850 ( .A(\UART_RXFF/iFIFOMem[22][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1941 ) );
notech_mux2 \UART_RXFF/U849 ( .A(\UART_RXFF/iFIFOMem[22][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1942 ) );
notech_mux2 \UART_RXFF/U848 ( .A(\UART_RXFF/iFIFOMem[22][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n378 ), .Z(\UART_RXFF/n1943 ) );
notech_and2 \UART_RXFF/U847 ( .A(\UART_RXFF/n377 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n376 ) );
notech_mux2 \UART_RXFF/U846 ( .A(\UART_RXFF/iFIFOMem[23][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1944 ) );
notech_mux2 \UART_RXFF/U845 ( .A(\UART_RXFF/iFIFOMem[23][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1945 ) );
notech_mux2 \UART_RXFF/U844 ( .A(\UART_RXFF/iFIFOMem[23][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1946 ) );
notech_mux2 \UART_RXFF/U843 ( .A(\UART_RXFF/iFIFOMem[23][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1947 ) );
notech_mux2 \UART_RXFF/U842 ( .A(\UART_RXFF/iFIFOMem[23][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1948 ) );
notech_mux2 \UART_RXFF/U841 ( .A(\UART_RXFF/iFIFOMem[23][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1949 ) );
notech_mux2 \UART_RXFF/U840 ( .A(\UART_RXFF/iFIFOMem[23][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1950 ) );
notech_mux2 \UART_RXFF/U839 ( .A(\UART_RXFF/iFIFOMem[23][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1951 ) );
notech_mux2 \UART_RXFF/U838 ( .A(\UART_RXFF/iFIFOMem[23][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1952 ) );
notech_mux2 \UART_RXFF/U837 ( .A(\UART_RXFF/iFIFOMem[23][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1953 ) );
notech_mux2 \UART_RXFF/U836 ( .A(\UART_RXFF/iFIFOMem[23][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n376 ), .Z(\UART_RXFF/n1954 ) );
notech_ao3 \UART_RXFF/U835 ( .A(\UART_RXFF/iWRAddr[4] ), .B(
\UART_RXFF/n375 ), .C(\UART_RXFF/n302 ), .Z(\UART_RXFF/n367 ) );
notech_and2 \UART_RXFF/U834 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n374 ) );
notech_mux2 \UART_RXFF/U833 ( .A(\UART_RXFF/iFIFOMem[24][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1955 ) );
notech_mux2 \UART_RXFF/U832 ( .A(\UART_RXFF/iFIFOMem[24][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1956 ) );
notech_mux2 \UART_RXFF/U831 ( .A(\UART_RXFF/iFIFOMem[24][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1957 ) );
notech_mux2 \UART_RXFF/U830 ( .A(\UART_RXFF/iFIFOMem[24][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1958 ) );
notech_mux2 \UART_RXFF/U829 ( .A(\UART_RXFF/iFIFOMem[24][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1959 ) );
notech_mux2 \UART_RXFF/U828 ( .A(\UART_RXFF/iFIFOMem[24][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1960 ) );
notech_mux2 \UART_RXFF/U827 ( .A(\UART_RXFF/iFIFOMem[24][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1961 ) );
notech_mux2 \UART_RXFF/U826 ( .A(\UART_RXFF/iFIFOMem[24][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1962 ) );
notech_mux2 \UART_RXFF/U825 ( .A(\UART_RXFF/iFIFOMem[24][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1963 ) );
notech_mux2 \UART_RXFF/U824 ( .A(\UART_RXFF/iFIFOMem[24][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1964 ) );
notech_mux2 \UART_RXFF/U823 ( .A(\UART_RXFF/iFIFOMem[24][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n374 ), .Z(\UART_RXFF/n1965 ) );
notech_and2 \UART_RXFF/U822 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n373 ) );
notech_mux2 \UART_RXFF/U821 ( .A(\UART_RXFF/iFIFOMem[25][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1966 ) );
notech_mux2 \UART_RXFF/U820 ( .A(\UART_RXFF/iFIFOMem[25][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1967 ) );
notech_mux2 \UART_RXFF/U819 ( .A(\UART_RXFF/iFIFOMem[25][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1968 ) );
notech_mux2 \UART_RXFF/U818 ( .A(\UART_RXFF/iFIFOMem[25][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1969 ) );
notech_mux2 \UART_RXFF/U817 ( .A(\UART_RXFF/iFIFOMem[25][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1970 ) );
notech_mux2 \UART_RXFF/U816 ( .A(\UART_RXFF/iFIFOMem[25][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1971 ) );
notech_mux2 \UART_RXFF/U815 ( .A(\UART_RXFF/iFIFOMem[25][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1972 ) );
notech_mux2 \UART_RXFF/U814 ( .A(\UART_RXFF/iFIFOMem[25][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1973 ) );
notech_mux2 \UART_RXFF/U813 ( .A(\UART_RXFF/iFIFOMem[25][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1974 ) );
notech_mux2 \UART_RXFF/U812 ( .A(\UART_RXFF/iFIFOMem[25][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1975 ) );
notech_mux2 \UART_RXFF/U811 ( .A(\UART_RXFF/iFIFOMem[25][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n373 ), .Z(\UART_RXFF/n1976 ) );
notech_and2 \UART_RXFF/U810 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n372 ) );
notech_mux2 \UART_RXFF/U809 ( .A(\UART_RXFF/iFIFOMem[26][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1977 ) );
notech_mux2 \UART_RXFF/U808 ( .A(\UART_RXFF/iFIFOMem[26][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1978 ) );
notech_mux2 \UART_RXFF/U807 ( .A(\UART_RXFF/iFIFOMem[26][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1979 ) );
notech_mux2 \UART_RXFF/U806 ( .A(\UART_RXFF/iFIFOMem[26][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1980 ) );
notech_mux2 \UART_RXFF/U805 ( .A(\UART_RXFF/iFIFOMem[26][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1981 ) );
notech_mux2 \UART_RXFF/U804 ( .A(\UART_RXFF/iFIFOMem[26][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1982 ) );
notech_mux2 \UART_RXFF/U803 ( .A(\UART_RXFF/iFIFOMem[26][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1983 ) );
notech_mux2 \UART_RXFF/U802 ( .A(\UART_RXFF/iFIFOMem[26][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1984 ) );
notech_mux2 \UART_RXFF/U801 ( .A(\UART_RXFF/iFIFOMem[26][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1985 ) );
notech_mux2 \UART_RXFF/U800 ( .A(\UART_RXFF/iFIFOMem[26][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1986 ) );
notech_mux2 \UART_RXFF/U799 ( .A(\UART_RXFF/iFIFOMem[26][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n372 ), .Z(\UART_RXFF/n1987 ) );
notech_and2 \UART_RXFF/U798 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n371 ) );
notech_mux2 \UART_RXFF/U797 ( .A(\UART_RXFF/iFIFOMem[27][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1988 ) );
notech_mux2 \UART_RXFF/U796 ( .A(\UART_RXFF/iFIFOMem[27][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1989 ) );
notech_mux2 \UART_RXFF/U795 ( .A(\UART_RXFF/iFIFOMem[27][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1990 ) );
notech_mux2 \UART_RXFF/U794 ( .A(\UART_RXFF/iFIFOMem[27][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1991 ) );
notech_mux2 \UART_RXFF/U793 ( .A(\UART_RXFF/iFIFOMem[27][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1992 ) );
notech_mux2 \UART_RXFF/U792 ( .A(\UART_RXFF/iFIFOMem[27][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1993 ) );
notech_mux2 \UART_RXFF/U791 ( .A(\UART_RXFF/iFIFOMem[27][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1994 ) );
notech_mux2 \UART_RXFF/U790 ( .A(\UART_RXFF/iFIFOMem[27][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1995 ) );
notech_mux2 \UART_RXFF/U789 ( .A(\UART_RXFF/iFIFOMem[27][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1996 ) );
notech_mux2 \UART_RXFF/U788 ( .A(\UART_RXFF/iFIFOMem[27][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1997 ) );
notech_mux2 \UART_RXFF/U787 ( .A(\UART_RXFF/iFIFOMem[27][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n371 ), .Z(\UART_RXFF/n1998 ) );
notech_and2 \UART_RXFF/U786 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n370 ) );
notech_mux2 \UART_RXFF/U785 ( .A(\UART_RXFF/iFIFOMem[28][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n1999 ) );
notech_mux2 \UART_RXFF/U784 ( .A(\UART_RXFF/iFIFOMem[28][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2000 ) );
notech_mux2 \UART_RXFF/U783 ( .A(\UART_RXFF/iFIFOMem[28][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2001 ) );
notech_mux2 \UART_RXFF/U782 ( .A(\UART_RXFF/iFIFOMem[28][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2002 ) );
notech_mux2 \UART_RXFF/U781 ( .A(\UART_RXFF/iFIFOMem[28][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2003 ) );
notech_mux2 \UART_RXFF/U780 ( .A(\UART_RXFF/iFIFOMem[28][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2004 ) );
notech_mux2 \UART_RXFF/U779 ( .A(\UART_RXFF/iFIFOMem[28][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2005 ) );
notech_mux2 \UART_RXFF/U778 ( .A(\UART_RXFF/iFIFOMem[28][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2006 ) );
notech_mux2 \UART_RXFF/U777 ( .A(\UART_RXFF/iFIFOMem[28][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2007 ) );
notech_mux2 \UART_RXFF/U776 ( .A(\UART_RXFF/iFIFOMem[28][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2008 ) );
notech_mux2 \UART_RXFF/U775 ( .A(\UART_RXFF/iFIFOMem[28][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n370 ), .Z(\UART_RXFF/n2009 ) );
notech_and2 \UART_RXFF/U774 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n369 ) );
notech_mux2 \UART_RXFF/U773 ( .A(\UART_RXFF/iFIFOMem[29][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2010 ) );
notech_mux2 \UART_RXFF/U772 ( .A(\UART_RXFF/iFIFOMem[29][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2011 ) );
notech_mux2 \UART_RXFF/U771 ( .A(\UART_RXFF/iFIFOMem[29][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2012 ) );
notech_mux2 \UART_RXFF/U770 ( .A(\UART_RXFF/iFIFOMem[29][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2013 ) );
notech_mux2 \UART_RXFF/U769 ( .A(\UART_RXFF/iFIFOMem[29][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2014 ) );
notech_mux2 \UART_RXFF/U768 ( .A(\UART_RXFF/iFIFOMem[29][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2015 ) );
notech_mux2 \UART_RXFF/U767 ( .A(\UART_RXFF/iFIFOMem[29][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2016 ) );
notech_mux2 \UART_RXFF/U766 ( .A(\UART_RXFF/iFIFOMem[29][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2017 ) );
notech_mux2 \UART_RXFF/U765 ( .A(\UART_RXFF/iFIFOMem[29][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2018 ) );
notech_mux2 \UART_RXFF/U764 ( .A(\UART_RXFF/iFIFOMem[29][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2019 ) );
notech_mux2 \UART_RXFF/U763 ( .A(\UART_RXFF/iFIFOMem[29][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n369 ), .Z(\UART_RXFF/n2020 ) );
notech_and2 \UART_RXFF/U762 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n368 ) );
notech_mux2 \UART_RXFF/U761 ( .A(\UART_RXFF/iFIFOMem[30][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2021 ) );
notech_mux2 \UART_RXFF/U760 ( .A(\UART_RXFF/iFIFOMem[30][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2022 ) );
notech_mux2 \UART_RXFF/U759 ( .A(\UART_RXFF/iFIFOMem[30][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2023 ) );
notech_mux2 \UART_RXFF/U758 ( .A(\UART_RXFF/iFIFOMem[30][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2024 ) );
notech_mux2 \UART_RXFF/U757 ( .A(\UART_RXFF/iFIFOMem[30][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2025 ) );
notech_mux2 \UART_RXFF/U756 ( .A(\UART_RXFF/iFIFOMem[30][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2026 ) );
notech_mux2 \UART_RXFF/U755 ( .A(\UART_RXFF/iFIFOMem[30][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2027 ) );
notech_mux2 \UART_RXFF/U754 ( .A(\UART_RXFF/iFIFOMem[30][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2028 ) );
notech_mux2 \UART_RXFF/U753 ( .A(\UART_RXFF/iFIFOMem[30][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2029 ) );
notech_mux2 \UART_RXFF/U752 ( .A(\UART_RXFF/iFIFOMem[30][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2030 ) );
notech_mux2 \UART_RXFF/U751 ( .A(\UART_RXFF/iFIFOMem[30][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n368 ), .Z(\UART_RXFF/n2031 ) );
notech_and2 \UART_RXFF/U750 ( .A(\UART_RXFF/n367 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n366 ) );
notech_mux2 \UART_RXFF/U749 ( .A(\UART_RXFF/iFIFOMem[31][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2032 ) );
notech_mux2 \UART_RXFF/U748 ( .A(\UART_RXFF/iFIFOMem[31][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2033 ) );
notech_mux2 \UART_RXFF/U747 ( .A(\UART_RXFF/iFIFOMem[31][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2034 ) );
notech_mux2 \UART_RXFF/U746 ( .A(\UART_RXFF/iFIFOMem[31][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2035 ) );
notech_mux2 \UART_RXFF/U745 ( .A(\UART_RXFF/iFIFOMem[31][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2036 ) );
notech_mux2 \UART_RXFF/U744 ( .A(\UART_RXFF/iFIFOMem[31][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2037 ) );
notech_mux2 \UART_RXFF/U743 ( .A(\UART_RXFF/iFIFOMem[31][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2038 ) );
notech_mux2 \UART_RXFF/U742 ( .A(\UART_RXFF/iFIFOMem[31][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2039 ) );
notech_mux2 \UART_RXFF/U741 ( .A(\UART_RXFF/iFIFOMem[31][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2040 ) );
notech_mux2 \UART_RXFF/U740 ( .A(\UART_RXFF/iFIFOMem[31][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2041 ) );
notech_mux2 \UART_RXFF/U739 ( .A(\UART_RXFF/iFIFOMem[31][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n366 ), .Z(\UART_RXFF/n2042 ) );
notech_ao3 \UART_RXFF/U738 ( .A(\UART_RXFF/iWRAddr[5] ), .B(
\UART_RXFF/n365 ), .C(RST), .Z(\UART_RXFF/n337 ) );
notech_ao3 \UART_RXFF/U737 ( .A(\UART_RXFF/n302 ), .B(\UART_RXFF/n337 ),
.C(\UART_RXFF/iWRAddr[4] ), .Z(\UART_RXFF/n357 ) );
notech_and2 \UART_RXFF/U736 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n364 ) );
notech_mux2 \UART_RXFF/U735 ( .A(\UART_RXFF/iFIFOMem[32][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2043 ) );
notech_mux2 \UART_RXFF/U734 ( .A(\UART_RXFF/iFIFOMem[32][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2044 ) );
notech_mux2 \UART_RXFF/U733 ( .A(\UART_RXFF/iFIFOMem[32][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2045 ) );
notech_mux2 \UART_RXFF/U732 ( .A(\UART_RXFF/iFIFOMem[32][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2046 ) );
notech_mux2 \UART_RXFF/U731 ( .A(\UART_RXFF/iFIFOMem[32][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2047 ) );
notech_mux2 \UART_RXFF/U730 ( .A(\UART_RXFF/iFIFOMem[32][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2048 ) );
notech_mux2 \UART_RXFF/U729 ( .A(\UART_RXFF/iFIFOMem[32][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2049 ) );
notech_mux2 \UART_RXFF/U728 ( .A(\UART_RXFF/iFIFOMem[32][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2050 ) );
notech_mux2 \UART_RXFF/U727 ( .A(\UART_RXFF/iFIFOMem[32][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2051 ) );
notech_mux2 \UART_RXFF/U726 ( .A(\UART_RXFF/iFIFOMem[32][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2052 ) );
notech_mux2 \UART_RXFF/U725 ( .A(\UART_RXFF/iFIFOMem[32][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n364 ), .Z(\UART_RXFF/n2053 ) );
notech_and2 \UART_RXFF/U724 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n363 ) );
notech_mux2 \UART_RXFF/U723 ( .A(\UART_RXFF/iFIFOMem[33][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2054 ) );
notech_mux2 \UART_RXFF/U722 ( .A(\UART_RXFF/iFIFOMem[33][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2055 ) );
notech_mux2 \UART_RXFF/U721 ( .A(\UART_RXFF/iFIFOMem[33][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2056 ) );
notech_mux2 \UART_RXFF/U720 ( .A(\UART_RXFF/iFIFOMem[33][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2057 ) );
notech_mux2 \UART_RXFF/U719 ( .A(\UART_RXFF/iFIFOMem[33][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2058 ) );
notech_mux2 \UART_RXFF/U718 ( .A(\UART_RXFF/iFIFOMem[33][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2059 ) );
notech_mux2 \UART_RXFF/U717 ( .A(\UART_RXFF/iFIFOMem[33][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2060 ) );
notech_mux2 \UART_RXFF/U716 ( .A(\UART_RXFF/iFIFOMem[33][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2061 ) );
notech_mux2 \UART_RXFF/U715 ( .A(\UART_RXFF/iFIFOMem[33][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2062 ) );
notech_mux2 \UART_RXFF/U714 ( .A(\UART_RXFF/iFIFOMem[33][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2063 ) );
notech_mux2 \UART_RXFF/U713 ( .A(\UART_RXFF/iFIFOMem[33][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n363 ), .Z(\UART_RXFF/n2064 ) );
notech_and2 \UART_RXFF/U712 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n362 ) );
notech_mux2 \UART_RXFF/U711 ( .A(\UART_RXFF/iFIFOMem[34][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2065 ) );
notech_mux2 \UART_RXFF/U710 ( .A(\UART_RXFF/iFIFOMem[34][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2066 ) );
notech_mux2 \UART_RXFF/U709 ( .A(\UART_RXFF/iFIFOMem[34][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2067 ) );
notech_mux2 \UART_RXFF/U708 ( .A(\UART_RXFF/iFIFOMem[34][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2068 ) );
notech_mux2 \UART_RXFF/U707 ( .A(\UART_RXFF/iFIFOMem[34][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2069 ) );
notech_mux2 \UART_RXFF/U706 ( .A(\UART_RXFF/iFIFOMem[34][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2070 ) );
notech_mux2 \UART_RXFF/U705 ( .A(\UART_RXFF/iFIFOMem[34][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2071 ) );
notech_mux2 \UART_RXFF/U704 ( .A(\UART_RXFF/iFIFOMem[34][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2072 ) );
notech_mux2 \UART_RXFF/U703 ( .A(\UART_RXFF/iFIFOMem[34][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2073 ) );
notech_mux2 \UART_RXFF/U702 ( .A(\UART_RXFF/iFIFOMem[34][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2074 ) );
notech_mux2 \UART_RXFF/U701 ( .A(\UART_RXFF/iFIFOMem[34][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n362 ), .Z(\UART_RXFF/n2075 ) );
notech_and2 \UART_RXFF/U700 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n361 ) );
notech_mux2 \UART_RXFF/U699 ( .A(\UART_RXFF/iFIFOMem[35][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2076 ) );
notech_mux2 \UART_RXFF/U698 ( .A(\UART_RXFF/iFIFOMem[35][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2077 ) );
notech_mux2 \UART_RXFF/U697 ( .A(\UART_RXFF/iFIFOMem[35][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2078 ) );
notech_mux2 \UART_RXFF/U696 ( .A(\UART_RXFF/iFIFOMem[35][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2079 ) );
notech_mux2 \UART_RXFF/U695 ( .A(\UART_RXFF/iFIFOMem[35][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2080 ) );
notech_mux2 \UART_RXFF/U694 ( .A(\UART_RXFF/iFIFOMem[35][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2081 ) );
notech_mux2 \UART_RXFF/U693 ( .A(\UART_RXFF/iFIFOMem[35][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2082 ) );
notech_mux2 \UART_RXFF/U692 ( .A(\UART_RXFF/iFIFOMem[35][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2083 ) );
notech_mux2 \UART_RXFF/U691 ( .A(\UART_RXFF/iFIFOMem[35][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2084 ) );
notech_mux2 \UART_RXFF/U690 ( .A(\UART_RXFF/iFIFOMem[35][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2085 ) );
notech_mux2 \UART_RXFF/U689 ( .A(\UART_RXFF/iFIFOMem[35][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n361 ), .Z(\UART_RXFF/n2086 ) );
notech_and2 \UART_RXFF/U688 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n360 ) );
notech_mux2 \UART_RXFF/U687 ( .A(\UART_RXFF/iFIFOMem[36][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2087 ) );
notech_mux2 \UART_RXFF/U686 ( .A(\UART_RXFF/iFIFOMem[36][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2088 ) );
notech_mux2 \UART_RXFF/U685 ( .A(\UART_RXFF/iFIFOMem[36][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2089 ) );
notech_mux2 \UART_RXFF/U684 ( .A(\UART_RXFF/iFIFOMem[36][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2090 ) );
notech_mux2 \UART_RXFF/U683 ( .A(\UART_RXFF/iFIFOMem[36][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2091 ) );
notech_mux2 \UART_RXFF/U682 ( .A(\UART_RXFF/iFIFOMem[36][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2092 ) );
notech_mux2 \UART_RXFF/U681 ( .A(\UART_RXFF/iFIFOMem[36][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2093 ) );
notech_mux2 \UART_RXFF/U680 ( .A(\UART_RXFF/iFIFOMem[36][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2094 ) );
notech_mux2 \UART_RXFF/U679 ( .A(\UART_RXFF/iFIFOMem[36][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2095 ) );
notech_mux2 \UART_RXFF/U678 ( .A(\UART_RXFF/iFIFOMem[36][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2096 ) );
notech_mux2 \UART_RXFF/U677 ( .A(\UART_RXFF/iFIFOMem[36][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n360 ), .Z(\UART_RXFF/n2097 ) );
notech_and2 \UART_RXFF/U676 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n359 ) );
notech_mux2 \UART_RXFF/U675 ( .A(\UART_RXFF/iFIFOMem[37][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2098 ) );
notech_mux2 \UART_RXFF/U674 ( .A(\UART_RXFF/iFIFOMem[37][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2099 ) );
notech_mux2 \UART_RXFF/U673 ( .A(\UART_RXFF/iFIFOMem[37][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2100 ) );
notech_mux2 \UART_RXFF/U672 ( .A(\UART_RXFF/iFIFOMem[37][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2101 ) );
notech_mux2 \UART_RXFF/U671 ( .A(\UART_RXFF/iFIFOMem[37][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2102 ) );
notech_mux2 \UART_RXFF/U670 ( .A(\UART_RXFF/iFIFOMem[37][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2103 ) );
notech_mux2 \UART_RXFF/U669 ( .A(\UART_RXFF/iFIFOMem[37][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2104 ) );
notech_mux2 \UART_RXFF/U668 ( .A(\UART_RXFF/iFIFOMem[37][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2105 ) );
notech_mux2 \UART_RXFF/U667 ( .A(\UART_RXFF/iFIFOMem[37][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2106 ) );
notech_mux2 \UART_RXFF/U666 ( .A(\UART_RXFF/iFIFOMem[37][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2107 ) );
notech_mux2 \UART_RXFF/U665 ( .A(\UART_RXFF/iFIFOMem[37][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n359 ), .Z(\UART_RXFF/n2108 ) );
notech_and2 \UART_RXFF/U664 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n358 ) );
notech_mux2 \UART_RXFF/U663 ( .A(\UART_RXFF/iFIFOMem[38][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2109 ) );
notech_mux2 \UART_RXFF/U662 ( .A(\UART_RXFF/iFIFOMem[38][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2110 ) );
notech_mux2 \UART_RXFF/U661 ( .A(\UART_RXFF/iFIFOMem[38][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2111 ) );
notech_mux2 \UART_RXFF/U660 ( .A(\UART_RXFF/iFIFOMem[38][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2112 ) );
notech_mux2 \UART_RXFF/U659 ( .A(\UART_RXFF/iFIFOMem[38][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2113 ) );
notech_mux2 \UART_RXFF/U658 ( .A(\UART_RXFF/iFIFOMem[38][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2114 ) );
notech_mux2 \UART_RXFF/U657 ( .A(\UART_RXFF/iFIFOMem[38][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2115 ) );
notech_mux2 \UART_RXFF/U656 ( .A(\UART_RXFF/iFIFOMem[38][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2116 ) );
notech_mux2 \UART_RXFF/U655 ( .A(\UART_RXFF/iFIFOMem[38][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2117 ) );
notech_mux2 \UART_RXFF/U654 ( .A(\UART_RXFF/iFIFOMem[38][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2118 ) );
notech_mux2 \UART_RXFF/U653 ( .A(\UART_RXFF/iFIFOMem[38][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n358 ), .Z(\UART_RXFF/n2119 ) );
notech_and2 \UART_RXFF/U652 ( .A(\UART_RXFF/n357 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n356 ) );
notech_mux2 \UART_RXFF/U651 ( .A(\UART_RXFF/iFIFOMem[39][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2120 ) );
notech_mux2 \UART_RXFF/U650 ( .A(\UART_RXFF/iFIFOMem[39][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2121 ) );
notech_mux2 \UART_RXFF/U649 ( .A(\UART_RXFF/iFIFOMem[39][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2122 ) );
notech_mux2 \UART_RXFF/U648 ( .A(\UART_RXFF/iFIFOMem[39][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2123 ) );
notech_mux2 \UART_RXFF/U647 ( .A(\UART_RXFF/iFIFOMem[39][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2124 ) );
notech_mux2 \UART_RXFF/U646 ( .A(\UART_RXFF/iFIFOMem[39][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2125 ) );
notech_mux2 \UART_RXFF/U645 ( .A(\UART_RXFF/iFIFOMem[39][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2126 ) );
notech_mux2 \UART_RXFF/U644 ( .A(\UART_RXFF/iFIFOMem[39][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2127 ) );
notech_mux2 \UART_RXFF/U643 ( .A(\UART_RXFF/iFIFOMem[39][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2128 ) );
notech_mux2 \UART_RXFF/U642 ( .A(\UART_RXFF/iFIFOMem[39][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2129 ) );
notech_mux2 \UART_RXFF/U641 ( .A(\UART_RXFF/iFIFOMem[39][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n356 ), .Z(\UART_RXFF/n2130 ) );
notech_ao3 \UART_RXFF/U640 ( .A(\UART_RXFF/iWRAddr[3] ), .B(
\UART_RXFF/n337 ), .C(\UART_RXFF/iWRAddr[4] ), .Z(\UART_RXFF/n348 ) );
notech_and2 \UART_RXFF/U639 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n355 ) );
notech_mux2 \UART_RXFF/U638 ( .A(\UART_RXFF/iFIFOMem[40][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2131 ) );
notech_mux2 \UART_RXFF/U637 ( .A(\UART_RXFF/iFIFOMem[40][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2132 ) );
notech_mux2 \UART_RXFF/U636 ( .A(\UART_RXFF/iFIFOMem[40][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2133 ) );
notech_mux2 \UART_RXFF/U635 ( .A(\UART_RXFF/iFIFOMem[40][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2134 ) );
notech_mux2 \UART_RXFF/U634 ( .A(\UART_RXFF/iFIFOMem[40][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2135 ) );
notech_mux2 \UART_RXFF/U633 ( .A(\UART_RXFF/iFIFOMem[40][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2136 ) );
notech_mux2 \UART_RXFF/U632 ( .A(\UART_RXFF/iFIFOMem[40][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2137 ) );
notech_mux2 \UART_RXFF/U631 ( .A(\UART_RXFF/iFIFOMem[40][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2138 ) );
notech_mux2 \UART_RXFF/U630 ( .A(\UART_RXFF/iFIFOMem[40][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2139 ) );
notech_mux2 \UART_RXFF/U629 ( .A(\UART_RXFF/iFIFOMem[40][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2140 ) );
notech_mux2 \UART_RXFF/U628 ( .A(\UART_RXFF/iFIFOMem[40][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n355 ), .Z(\UART_RXFF/n2141 ) );
notech_and2 \UART_RXFF/U627 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n354 ) );
notech_mux2 \UART_RXFF/U626 ( .A(\UART_RXFF/iFIFOMem[41][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2142 ) );
notech_mux2 \UART_RXFF/U625 ( .A(\UART_RXFF/iFIFOMem[41][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2143 ) );
notech_mux2 \UART_RXFF/U624 ( .A(\UART_RXFF/iFIFOMem[41][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2144 ) );
notech_mux2 \UART_RXFF/U623 ( .A(\UART_RXFF/iFIFOMem[41][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2145 ) );
notech_mux2 \UART_RXFF/U622 ( .A(\UART_RXFF/iFIFOMem[41][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2146 ) );
notech_mux2 \UART_RXFF/U621 ( .A(\UART_RXFF/iFIFOMem[41][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2147 ) );
notech_mux2 \UART_RXFF/U620 ( .A(\UART_RXFF/iFIFOMem[41][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2148 ) );
notech_mux2 \UART_RXFF/U619 ( .A(\UART_RXFF/iFIFOMem[41][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2149 ) );
notech_mux2 \UART_RXFF/U618 ( .A(\UART_RXFF/iFIFOMem[41][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2150 ) );
notech_mux2 \UART_RXFF/U617 ( .A(\UART_RXFF/iFIFOMem[41][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2151 ) );
notech_mux2 \UART_RXFF/U616 ( .A(\UART_RXFF/iFIFOMem[41][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n354 ), .Z(\UART_RXFF/n2152 ) );
notech_and2 \UART_RXFF/U615 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n353 ) );
notech_mux2 \UART_RXFF/U614 ( .A(\UART_RXFF/iFIFOMem[42][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2153 ) );
notech_mux2 \UART_RXFF/U613 ( .A(\UART_RXFF/iFIFOMem[42][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2154 ) );
notech_mux2 \UART_RXFF/U612 ( .A(\UART_RXFF/iFIFOMem[42][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2155 ) );
notech_mux2 \UART_RXFF/U611 ( .A(\UART_RXFF/iFIFOMem[42][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2156 ) );
notech_mux2 \UART_RXFF/U610 ( .A(\UART_RXFF/iFIFOMem[42][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2157 ) );
notech_mux2 \UART_RXFF/U609 ( .A(\UART_RXFF/iFIFOMem[42][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2158 ) );
notech_mux2 \UART_RXFF/U608 ( .A(\UART_RXFF/iFIFOMem[42][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2159 ) );
notech_mux2 \UART_RXFF/U607 ( .A(\UART_RXFF/iFIFOMem[42][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2160 ) );
notech_mux2 \UART_RXFF/U606 ( .A(\UART_RXFF/iFIFOMem[42][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2161 ) );
notech_mux2 \UART_RXFF/U605 ( .A(\UART_RXFF/iFIFOMem[42][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2162 ) );
notech_mux2 \UART_RXFF/U604 ( .A(\UART_RXFF/iFIFOMem[42][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n353 ), .Z(\UART_RXFF/n2163 ) );
notech_and2 \UART_RXFF/U603 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n352 ) );
notech_mux2 \UART_RXFF/U602 ( .A(\UART_RXFF/iFIFOMem[43][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2164 ) );
notech_mux2 \UART_RXFF/U601 ( .A(\UART_RXFF/iFIFOMem[43][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2165 ) );
notech_mux2 \UART_RXFF/U600 ( .A(\UART_RXFF/iFIFOMem[43][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2166 ) );
notech_mux2 \UART_RXFF/U599 ( .A(\UART_RXFF/iFIFOMem[43][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2167 ) );
notech_mux2 \UART_RXFF/U598 ( .A(\UART_RXFF/iFIFOMem[43][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2168 ) );
notech_mux2 \UART_RXFF/U597 ( .A(\UART_RXFF/iFIFOMem[43][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2169 ) );
notech_mux2 \UART_RXFF/U596 ( .A(\UART_RXFF/iFIFOMem[43][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2170 ) );
notech_mux2 \UART_RXFF/U595 ( .A(\UART_RXFF/iFIFOMem[43][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2171 ) );
notech_mux2 \UART_RXFF/U594 ( .A(\UART_RXFF/iFIFOMem[43][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2172 ) );
notech_mux2 \UART_RXFF/U593 ( .A(\UART_RXFF/iFIFOMem[43][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2173 ) );
notech_mux2 \UART_RXFF/U592 ( .A(\UART_RXFF/iFIFOMem[43][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n352 ), .Z(\UART_RXFF/n2174 ) );
notech_and2 \UART_RXFF/U591 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n351 ) );
notech_mux2 \UART_RXFF/U590 ( .A(\UART_RXFF/iFIFOMem[44][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2175 ) );
notech_mux2 \UART_RXFF/U589 ( .A(\UART_RXFF/iFIFOMem[44][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2176 ) );
notech_mux2 \UART_RXFF/U588 ( .A(\UART_RXFF/iFIFOMem[44][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2177 ) );
notech_mux2 \UART_RXFF/U587 ( .A(\UART_RXFF/iFIFOMem[44][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2178 ) );
notech_mux2 \UART_RXFF/U586 ( .A(\UART_RXFF/iFIFOMem[44][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2179 ) );
notech_mux2 \UART_RXFF/U585 ( .A(\UART_RXFF/iFIFOMem[44][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2180 ) );
notech_mux2 \UART_RXFF/U584 ( .A(\UART_RXFF/iFIFOMem[44][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2181 ) );
notech_mux2 \UART_RXFF/U583 ( .A(\UART_RXFF/iFIFOMem[44][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2182 ) );
notech_mux2 \UART_RXFF/U582 ( .A(\UART_RXFF/iFIFOMem[44][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2183 ) );
notech_mux2 \UART_RXFF/U581 ( .A(\UART_RXFF/iFIFOMem[44][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2184 ) );
notech_mux2 \UART_RXFF/U580 ( .A(\UART_RXFF/iFIFOMem[44][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n351 ), .Z(\UART_RXFF/n2185 ) );
notech_and2 \UART_RXFF/U579 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n350 ) );
notech_mux2 \UART_RXFF/U578 ( .A(\UART_RXFF/iFIFOMem[45][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2186 ) );
notech_mux2 \UART_RXFF/U577 ( .A(\UART_RXFF/iFIFOMem[45][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2187 ) );
notech_mux2 \UART_RXFF/U576 ( .A(\UART_RXFF/iFIFOMem[45][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2188 ) );
notech_mux2 \UART_RXFF/U575 ( .A(\UART_RXFF/iFIFOMem[45][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2189 ) );
notech_mux2 \UART_RXFF/U574 ( .A(\UART_RXFF/iFIFOMem[45][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2190 ) );
notech_mux2 \UART_RXFF/U573 ( .A(\UART_RXFF/iFIFOMem[45][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2191 ) );
notech_mux2 \UART_RXFF/U572 ( .A(\UART_RXFF/iFIFOMem[45][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2192 ) );
notech_mux2 \UART_RXFF/U571 ( .A(\UART_RXFF/iFIFOMem[45][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2193 ) );
notech_mux2 \UART_RXFF/U570 ( .A(\UART_RXFF/iFIFOMem[45][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2194 ) );
notech_mux2 \UART_RXFF/U569 ( .A(\UART_RXFF/iFIFOMem[45][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2195 ) );
notech_mux2 \UART_RXFF/U568 ( .A(\UART_RXFF/iFIFOMem[45][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n350 ), .Z(\UART_RXFF/n2196 ) );
notech_and2 \UART_RXFF/U567 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n349 ) );
notech_mux2 \UART_RXFF/U566 ( .A(\UART_RXFF/iFIFOMem[46][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2197 ) );
notech_mux2 \UART_RXFF/U565 ( .A(\UART_RXFF/iFIFOMem[46][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2198 ) );
notech_mux2 \UART_RXFF/U564 ( .A(\UART_RXFF/iFIFOMem[46][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2199 ) );
notech_mux2 \UART_RXFF/U563 ( .A(\UART_RXFF/iFIFOMem[46][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2200 ) );
notech_mux2 \UART_RXFF/U562 ( .A(\UART_RXFF/iFIFOMem[46][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2201 ) );
notech_mux2 \UART_RXFF/U561 ( .A(\UART_RXFF/iFIFOMem[46][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2202 ) );
notech_mux2 \UART_RXFF/U560 ( .A(\UART_RXFF/iFIFOMem[46][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2203 ) );
notech_mux2 \UART_RXFF/U559 ( .A(\UART_RXFF/iFIFOMem[46][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2204 ) );
notech_mux2 \UART_RXFF/U558 ( .A(\UART_RXFF/iFIFOMem[46][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2205 ) );
notech_mux2 \UART_RXFF/U557 ( .A(\UART_RXFF/iFIFOMem[46][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2206 ) );
notech_mux2 \UART_RXFF/U556 ( .A(\UART_RXFF/iFIFOMem[46][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n349 ), .Z(\UART_RXFF/n2207 ) );
notech_and2 \UART_RXFF/U555 ( .A(\UART_RXFF/n348 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n347 ) );
notech_mux2 \UART_RXFF/U554 ( .A(\UART_RXFF/iFIFOMem[47][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2208 ) );
notech_mux2 \UART_RXFF/U553 ( .A(\UART_RXFF/iFIFOMem[47][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2209 ) );
notech_mux2 \UART_RXFF/U552 ( .A(\UART_RXFF/iFIFOMem[47][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2210 ) );
notech_mux2 \UART_RXFF/U551 ( .A(\UART_RXFF/iFIFOMem[47][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2211 ) );
notech_mux2 \UART_RXFF/U550 ( .A(\UART_RXFF/iFIFOMem[47][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2212 ) );
notech_mux2 \UART_RXFF/U549 ( .A(\UART_RXFF/iFIFOMem[47][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2213 ) );
notech_mux2 \UART_RXFF/U548 ( .A(\UART_RXFF/iFIFOMem[47][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2214 ) );
notech_mux2 \UART_RXFF/U547 ( .A(\UART_RXFF/iFIFOMem[47][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2215 ) );
notech_mux2 \UART_RXFF/U546 ( .A(\UART_RXFF/iFIFOMem[47][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2216 ) );
notech_mux2 \UART_RXFF/U545 ( .A(\UART_RXFF/iFIFOMem[47][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2217 ) );
notech_mux2 \UART_RXFF/U544 ( .A(\UART_RXFF/iFIFOMem[47][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n347 ), .Z(\UART_RXFF/n2218 ) );
notech_ao3 \UART_RXFF/U543 ( .A(\UART_RXFF/iWRAddr[4] ), .B(
\UART_RXFF/n337 ), .C(\UART_RXFF/iWRAddr[3] ), .Z(\UART_RXFF/n339 ) );
notech_and2 \UART_RXFF/U542 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n346 ) );
notech_mux2 \UART_RXFF/U541 ( .A(\UART_RXFF/iFIFOMem[48][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2219 ) );
notech_mux2 \UART_RXFF/U540 ( .A(\UART_RXFF/iFIFOMem[48][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2220 ) );
notech_mux2 \UART_RXFF/U539 ( .A(\UART_RXFF/iFIFOMem[48][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2221 ) );
notech_mux2 \UART_RXFF/U538 ( .A(\UART_RXFF/iFIFOMem[48][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2222 ) );
notech_mux2 \UART_RXFF/U537 ( .A(\UART_RXFF/iFIFOMem[48][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2223 ) );
notech_mux2 \UART_RXFF/U536 ( .A(\UART_RXFF/iFIFOMem[48][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2224 ) );
notech_mux2 \UART_RXFF/U535 ( .A(\UART_RXFF/iFIFOMem[48][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2225 ) );
notech_mux2 \UART_RXFF/U534 ( .A(\UART_RXFF/iFIFOMem[48][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2226 ) );
notech_mux2 \UART_RXFF/U533 ( .A(\UART_RXFF/iFIFOMem[48][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2227 ) );
notech_mux2 \UART_RXFF/U532 ( .A(\UART_RXFF/iFIFOMem[48][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2228 ) );
notech_mux2 \UART_RXFF/U531 ( .A(\UART_RXFF/iFIFOMem[48][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n346 ), .Z(\UART_RXFF/n2229 ) );
notech_and2 \UART_RXFF/U530 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n345 ) );
notech_mux2 \UART_RXFF/U529 ( .A(\UART_RXFF/iFIFOMem[49][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2230 ) );
notech_mux2 \UART_RXFF/U528 ( .A(\UART_RXFF/iFIFOMem[49][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2231 ) );
notech_mux2 \UART_RXFF/U527 ( .A(\UART_RXFF/iFIFOMem[49][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2232 ) );
notech_mux2 \UART_RXFF/U526 ( .A(\UART_RXFF/iFIFOMem[49][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2233 ) );
notech_mux2 \UART_RXFF/U525 ( .A(\UART_RXFF/iFIFOMem[49][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2234 ) );
notech_mux2 \UART_RXFF/U524 ( .A(\UART_RXFF/iFIFOMem[49][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2235 ) );
notech_mux2 \UART_RXFF/U523 ( .A(\UART_RXFF/iFIFOMem[49][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2236 ) );
notech_mux2 \UART_RXFF/U522 ( .A(\UART_RXFF/iFIFOMem[49][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2237 ) );
notech_mux2 \UART_RXFF/U521 ( .A(\UART_RXFF/iFIFOMem[49][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2238 ) );
notech_mux2 \UART_RXFF/U520 ( .A(\UART_RXFF/iFIFOMem[49][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2239 ) );
notech_mux2 \UART_RXFF/U519 ( .A(\UART_RXFF/iFIFOMem[49][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n345 ), .Z(\UART_RXFF/n2240 ) );
notech_and2 \UART_RXFF/U518 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n344 ) );
notech_mux2 \UART_RXFF/U517 ( .A(\UART_RXFF/iFIFOMem[50][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2241 ) );
notech_mux2 \UART_RXFF/U516 ( .A(\UART_RXFF/iFIFOMem[50][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2242 ) );
notech_mux2 \UART_RXFF/U515 ( .A(\UART_RXFF/iFIFOMem[50][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2243 ) );
notech_mux2 \UART_RXFF/U514 ( .A(\UART_RXFF/iFIFOMem[50][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2244 ) );
notech_mux2 \UART_RXFF/U513 ( .A(\UART_RXFF/iFIFOMem[50][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2245 ) );
notech_mux2 \UART_RXFF/U512 ( .A(\UART_RXFF/iFIFOMem[50][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2246 ) );
notech_mux2 \UART_RXFF/U511 ( .A(\UART_RXFF/iFIFOMem[50][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2247 ) );
notech_mux2 \UART_RXFF/U510 ( .A(\UART_RXFF/iFIFOMem[50][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2248 ) );
notech_mux2 \UART_RXFF/U509 ( .A(\UART_RXFF/iFIFOMem[50][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2249 ) );
notech_mux2 \UART_RXFF/U508 ( .A(\UART_RXFF/iFIFOMem[50][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2250 ) );
notech_mux2 \UART_RXFF/U507 ( .A(\UART_RXFF/iFIFOMem[50][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n344 ), .Z(\UART_RXFF/n2251 ) );
notech_and2 \UART_RXFF/U506 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n343 ) );
notech_mux2 \UART_RXFF/U505 ( .A(\UART_RXFF/iFIFOMem[51][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2252 ) );
notech_mux2 \UART_RXFF/U504 ( .A(\UART_RXFF/iFIFOMem[51][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2253 ) );
notech_mux2 \UART_RXFF/U503 ( .A(\UART_RXFF/iFIFOMem[51][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2254 ) );
notech_mux2 \UART_RXFF/U502 ( .A(\UART_RXFF/iFIFOMem[51][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2255 ) );
notech_mux2 \UART_RXFF/U501 ( .A(\UART_RXFF/iFIFOMem[51][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2256 ) );
notech_mux2 \UART_RXFF/U500 ( .A(\UART_RXFF/iFIFOMem[51][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2257 ) );
notech_mux2 \UART_RXFF/U499 ( .A(\UART_RXFF/iFIFOMem[51][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2258 ) );
notech_mux2 \UART_RXFF/U498 ( .A(\UART_RXFF/iFIFOMem[51][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2259 ) );
notech_mux2 \UART_RXFF/U497 ( .A(\UART_RXFF/iFIFOMem[51][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2260 ) );
notech_mux2 \UART_RXFF/U496 ( .A(\UART_RXFF/iFIFOMem[51][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2261 ) );
notech_mux2 \UART_RXFF/U495 ( .A(\UART_RXFF/iFIFOMem[51][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n343 ), .Z(\UART_RXFF/n2262 ) );
notech_and2 \UART_RXFF/U494 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n342 ) );
notech_mux2 \UART_RXFF/U493 ( .A(\UART_RXFF/iFIFOMem[52][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2263 ) );
notech_mux2 \UART_RXFF/U492 ( .A(\UART_RXFF/iFIFOMem[52][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2264 ) );
notech_mux2 \UART_RXFF/U491 ( .A(\UART_RXFF/iFIFOMem[52][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2265 ) );
notech_mux2 \UART_RXFF/U490 ( .A(\UART_RXFF/iFIFOMem[52][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2266 ) );
notech_mux2 \UART_RXFF/U489 ( .A(\UART_RXFF/iFIFOMem[52][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2267 ) );
notech_mux2 \UART_RXFF/U488 ( .A(\UART_RXFF/iFIFOMem[52][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2268 ) );
notech_mux2 \UART_RXFF/U487 ( .A(\UART_RXFF/iFIFOMem[52][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2269 ) );
notech_mux2 \UART_RXFF/U486 ( .A(\UART_RXFF/iFIFOMem[52][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2270 ) );
notech_mux2 \UART_RXFF/U485 ( .A(\UART_RXFF/iFIFOMem[52][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2271 ) );
notech_mux2 \UART_RXFF/U484 ( .A(\UART_RXFF/iFIFOMem[52][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2272 ) );
notech_mux2 \UART_RXFF/U483 ( .A(\UART_RXFF/iFIFOMem[52][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n342 ), .Z(\UART_RXFF/n2273 ) );
notech_and2 \UART_RXFF/U482 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n341 ) );
notech_mux2 \UART_RXFF/U481 ( .A(\UART_RXFF/iFIFOMem[53][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2274 ) );
notech_mux2 \UART_RXFF/U480 ( .A(\UART_RXFF/iFIFOMem[53][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2275 ) );
notech_mux2 \UART_RXFF/U479 ( .A(\UART_RXFF/iFIFOMem[53][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2276 ) );
notech_mux2 \UART_RXFF/U478 ( .A(\UART_RXFF/iFIFOMem[53][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2277 ) );
notech_mux2 \UART_RXFF/U477 ( .A(\UART_RXFF/iFIFOMem[53][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2278 ) );
notech_mux2 \UART_RXFF/U476 ( .A(\UART_RXFF/iFIFOMem[53][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2279 ) );
notech_mux2 \UART_RXFF/U475 ( .A(\UART_RXFF/iFIFOMem[53][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2280 ) );
notech_mux2 \UART_RXFF/U474 ( .A(\UART_RXFF/iFIFOMem[53][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2281 ) );
notech_mux2 \UART_RXFF/U473 ( .A(\UART_RXFF/iFIFOMem[53][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2282 ) );
notech_mux2 \UART_RXFF/U472 ( .A(\UART_RXFF/iFIFOMem[53][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2283 ) );
notech_mux2 \UART_RXFF/U471 ( .A(\UART_RXFF/iFIFOMem[53][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n341 ), .Z(\UART_RXFF/n2284 ) );
notech_and2 \UART_RXFF/U470 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n340 ) );
notech_mux2 \UART_RXFF/U469 ( .A(\UART_RXFF/iFIFOMem[54][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2285 ) );
notech_mux2 \UART_RXFF/U468 ( .A(\UART_RXFF/iFIFOMem[54][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2286 ) );
notech_mux2 \UART_RXFF/U467 ( .A(\UART_RXFF/iFIFOMem[54][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2287 ) );
notech_mux2 \UART_RXFF/U466 ( .A(\UART_RXFF/iFIFOMem[54][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2288 ) );
notech_mux2 \UART_RXFF/U465 ( .A(\UART_RXFF/iFIFOMem[54][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2289 ) );
notech_mux2 \UART_RXFF/U464 ( .A(\UART_RXFF/iFIFOMem[54][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2290 ) );
notech_mux2 \UART_RXFF/U463 ( .A(\UART_RXFF/iFIFOMem[54][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2291 ) );
notech_mux2 \UART_RXFF/U462 ( .A(\UART_RXFF/iFIFOMem[54][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2292 ) );
notech_mux2 \UART_RXFF/U461 ( .A(\UART_RXFF/iFIFOMem[54][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2293 ) );
notech_mux2 \UART_RXFF/U460 ( .A(\UART_RXFF/iFIFOMem[54][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2294 ) );
notech_mux2 \UART_RXFF/U459 ( .A(\UART_RXFF/iFIFOMem[54][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n340 ), .Z(\UART_RXFF/n2295 ) );
notech_and2 \UART_RXFF/U458 ( .A(\UART_RXFF/n339 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n338 ) );
notech_mux2 \UART_RXFF/U457 ( .A(\UART_RXFF/iFIFOMem[55][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2296 ) );
notech_mux2 \UART_RXFF/U456 ( .A(\UART_RXFF/iFIFOMem[55][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2297 ) );
notech_mux2 \UART_RXFF/U455 ( .A(\UART_RXFF/iFIFOMem[55][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2298 ) );
notech_mux2 \UART_RXFF/U454 ( .A(\UART_RXFF/iFIFOMem[55][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2299 ) );
notech_mux2 \UART_RXFF/U453 ( .A(\UART_RXFF/iFIFOMem[55][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2300 ) );
notech_mux2 \UART_RXFF/U452 ( .A(\UART_RXFF/iFIFOMem[55][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2301 ) );
notech_mux2 \UART_RXFF/U451 ( .A(\UART_RXFF/iFIFOMem[55][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2302 ) );
notech_mux2 \UART_RXFF/U450 ( .A(\UART_RXFF/iFIFOMem[55][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2303 ) );
notech_mux2 \UART_RXFF/U449 ( .A(\UART_RXFF/iFIFOMem[55][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2304 ) );
notech_mux2 \UART_RXFF/U448 ( .A(\UART_RXFF/iFIFOMem[55][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2305 ) );
notech_mux2 \UART_RXFF/U447 ( .A(\UART_RXFF/iFIFOMem[55][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n338 ), .Z(\UART_RXFF/n2306 ) );
notech_and3 \UART_RXFF/U446 ( .A(\UART_RXFF/iWRAddr[4] ), .B(
\UART_RXFF/n337 ), .C(\UART_RXFF/iWRAddr[3] ), .Z(\UART_RXFF/n321 ) );
notech_and2 \UART_RXFF/U445 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n336 ),
.Z(\UART_RXFF/n335 ) );
notech_mux2 \UART_RXFF/U444 ( .A(\UART_RXFF/iFIFOMem[56][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2307 ) );
notech_mux2 \UART_RXFF/U443 ( .A(\UART_RXFF/iFIFOMem[56][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2308 ) );
notech_mux2 \UART_RXFF/U442 ( .A(\UART_RXFF/iFIFOMem[56][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2309 ) );
notech_mux2 \UART_RXFF/U441 ( .A(\UART_RXFF/iFIFOMem[56][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2310 ) );
notech_mux2 \UART_RXFF/U440 ( .A(\UART_RXFF/iFIFOMem[56][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2311 ) );
notech_mux2 \UART_RXFF/U439 ( .A(\UART_RXFF/iFIFOMem[56][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2312 ) );
notech_mux2 \UART_RXFF/U438 ( .A(\UART_RXFF/iFIFOMem[56][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2313 ) );
notech_mux2 \UART_RXFF/U437 ( .A(\UART_RXFF/iFIFOMem[56][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2314 ) );
notech_mux2 \UART_RXFF/U436 ( .A(\UART_RXFF/iFIFOMem[56][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2315 ) );
notech_mux2 \UART_RXFF/U435 ( .A(\UART_RXFF/iFIFOMem[56][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2316 ) );
notech_mux2 \UART_RXFF/U434 ( .A(\UART_RXFF/iFIFOMem[56][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n335 ), .Z(\UART_RXFF/n2317 ) );
notech_and2 \UART_RXFF/U433 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n334 ),
.Z(\UART_RXFF/n333 ) );
notech_mux2 \UART_RXFF/U432 ( .A(\UART_RXFF/iFIFOMem[57][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2318 ) );
notech_mux2 \UART_RXFF/U431 ( .A(\UART_RXFF/iFIFOMem[57][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2319 ) );
notech_mux2 \UART_RXFF/U430 ( .A(\UART_RXFF/iFIFOMem[57][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2320 ) );
notech_mux2 \UART_RXFF/U429 ( .A(\UART_RXFF/iFIFOMem[57][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2321 ) );
notech_mux2 \UART_RXFF/U428 ( .A(\UART_RXFF/iFIFOMem[57][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2322 ) );
notech_mux2 \UART_RXFF/U427 ( .A(\UART_RXFF/iFIFOMem[57][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2323 ) );
notech_mux2 \UART_RXFF/U426 ( .A(\UART_RXFF/iFIFOMem[57][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2324 ) );
notech_mux2 \UART_RXFF/U425 ( .A(\UART_RXFF/iFIFOMem[57][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2325 ) );
notech_mux2 \UART_RXFF/U424 ( .A(\UART_RXFF/iFIFOMem[57][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2326 ) );
notech_mux2 \UART_RXFF/U423 ( .A(\UART_RXFF/iFIFOMem[57][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2327 ) );
notech_mux2 \UART_RXFF/U422 ( .A(\UART_RXFF/iFIFOMem[57][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n333 ), .Z(\UART_RXFF/n2328 ) );
notech_and2 \UART_RXFF/U421 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n332 ),
.Z(\UART_RXFF/n331 ) );
notech_mux2 \UART_RXFF/U420 ( .A(\UART_RXFF/iFIFOMem[58][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2329 ) );
notech_mux2 \UART_RXFF/U419 ( .A(\UART_RXFF/iFIFOMem[58][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2330 ) );
notech_mux2 \UART_RXFF/U418 ( .A(\UART_RXFF/iFIFOMem[58][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2331 ) );
notech_mux2 \UART_RXFF/U417 ( .A(\UART_RXFF/iFIFOMem[58][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2332 ) );
notech_mux2 \UART_RXFF/U416 ( .A(\UART_RXFF/iFIFOMem[58][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2333 ) );
notech_mux2 \UART_RXFF/U415 ( .A(\UART_RXFF/iFIFOMem[58][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2334 ) );
notech_mux2 \UART_RXFF/U414 ( .A(\UART_RXFF/iFIFOMem[58][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2335 ) );
notech_mux2 \UART_RXFF/U413 ( .A(\UART_RXFF/iFIFOMem[58][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2336 ) );
notech_mux2 \UART_RXFF/U412 ( .A(\UART_RXFF/iFIFOMem[58][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2337 ) );
notech_mux2 \UART_RXFF/U411 ( .A(\UART_RXFF/iFIFOMem[58][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2338 ) );
notech_mux2 \UART_RXFF/U410 ( .A(\UART_RXFF/iFIFOMem[58][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n331 ), .Z(\UART_RXFF/n2339 ) );
notech_and2 \UART_RXFF/U409 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n330 ),
.Z(\UART_RXFF/n329 ) );
notech_mux2 \UART_RXFF/U408 ( .A(\UART_RXFF/iFIFOMem[59][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2340 ) );
notech_mux2 \UART_RXFF/U407 ( .A(\UART_RXFF/iFIFOMem[59][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2341 ) );
notech_mux2 \UART_RXFF/U406 ( .A(\UART_RXFF/iFIFOMem[59][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2342 ) );
notech_mux2 \UART_RXFF/U405 ( .A(\UART_RXFF/iFIFOMem[59][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2343 ) );
notech_mux2 \UART_RXFF/U404 ( .A(\UART_RXFF/iFIFOMem[59][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2344 ) );
notech_mux2 \UART_RXFF/U403 ( .A(\UART_RXFF/iFIFOMem[59][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2345 ) );
notech_mux2 \UART_RXFF/U402 ( .A(\UART_RXFF/iFIFOMem[59][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2346 ) );
notech_mux2 \UART_RXFF/U401 ( .A(\UART_RXFF/iFIFOMem[59][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2347 ) );
notech_mux2 \UART_RXFF/U400 ( .A(\UART_RXFF/iFIFOMem[59][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2348 ) );
notech_mux2 \UART_RXFF/U399 ( .A(\UART_RXFF/iFIFOMem[59][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2349 ) );
notech_mux2 \UART_RXFF/U398 ( .A(\UART_RXFF/iFIFOMem[59][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n329 ), .Z(\UART_RXFF/n2350 ) );
notech_and2 \UART_RXFF/U397 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n328 ),
.Z(\UART_RXFF/n327 ) );
notech_mux2 \UART_RXFF/U396 ( .A(\UART_RXFF/iFIFOMem[60][0] ), .B(
iRXFIFOD[0]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2351 ) );
notech_mux2 \UART_RXFF/U395 ( .A(\UART_RXFF/iFIFOMem[60][1] ), .B(
iRXFIFOD[1]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2352 ) );
notech_mux2 \UART_RXFF/U394 ( .A(\UART_RXFF/iFIFOMem[60][2] ), .B(
iRXFIFOD[2]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2353 ) );
notech_mux2 \UART_RXFF/U393 ( .A(\UART_RXFF/iFIFOMem[60][3] ), .B(
iRXFIFOD[3]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2354 ) );
notech_mux2 \UART_RXFF/U392 ( .A(\UART_RXFF/iFIFOMem[60][4] ), .B(
iRXFIFOD[4]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2355 ) );
notech_mux2 \UART_RXFF/U391 ( .A(\UART_RXFF/iFIFOMem[60][5] ), .B(
iRXFIFOD[5]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2356 ) );
notech_mux2 \UART_RXFF/U390 ( .A(\UART_RXFF/iFIFOMem[60][6] ), .B(
iRXFIFOD[6]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2357 ) );
notech_mux2 \UART_RXFF/U389 ( .A(\UART_RXFF/iFIFOMem[60][7] ), .B(
iRXFIFOD[7]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2358 ) );
notech_mux2 \UART_RXFF/U388 ( .A(\UART_RXFF/iFIFOMem[60][8] ), .B(
iRXFIFOD[8]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2359 ) );
notech_mux2 \UART_RXFF/U387 ( .A(\UART_RXFF/iFIFOMem[60][9] ), .B(
iRXFIFOD[9]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2360 ) );
notech_mux2 \UART_RXFF/U386 ( .A(\UART_RXFF/iFIFOMem[60][10] ), .B(
iRXFIFOD[10]), .S(\UART_RXFF/n327 ), .Z(\UART_RXFF/n2361 ) );
notech_and2 \UART_RXFF/U385 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n326 ),
.Z(\UART_RXFF/n325 ) );
notech_mux2 \UART_RXFF/U384 ( .A(\UART_RXFF/iFIFOMem[61][0] ), .B(
\UART_RXFF/n4 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2362 ) );
notech_mux2 \UART_RXFF/U383 ( .A(\UART_RXFF/iFIFOMem[61][1] ), .B(
\UART_RXFF/n8 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2363 ) );
notech_mux2 \UART_RXFF/U382 ( .A(\UART_RXFF/iFIFOMem[61][2] ), .B(
\UART_RXFF/n12 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2364 ) );
notech_mux2 \UART_RXFF/U381 ( .A(\UART_RXFF/iFIFOMem[61][3] ), .B(
\UART_RXFF/n16 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2365 ) );
notech_mux2 \UART_RXFF/U380 ( .A(\UART_RXFF/iFIFOMem[61][4] ), .B(
\UART_RXFF/n20 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2366 ) );
notech_mux2 \UART_RXFF/U379 ( .A(\UART_RXFF/iFIFOMem[61][5] ), .B(
\UART_RXFF/n24 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2367 ) );
notech_mux2 \UART_RXFF/U378 ( .A(\UART_RXFF/iFIFOMem[61][6] ), .B(
\UART_RXFF/n28 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2368 ) );
notech_mux2 \UART_RXFF/U377 ( .A(\UART_RXFF/iFIFOMem[61][7] ), .B(
\UART_RXFF/n32 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2369 ) );
notech_mux2 \UART_RXFF/U376 ( .A(\UART_RXFF/iFIFOMem[61][8] ), .B(
\UART_RXFF/n36 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2370 ) );
notech_mux2 \UART_RXFF/U375 ( .A(\UART_RXFF/iFIFOMem[61][9] ), .B(
\UART_RXFF/n40 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2371 ) );
notech_mux2 \UART_RXFF/U374 ( .A(\UART_RXFF/iFIFOMem[61][10] ), .B(
\UART_RXFF/n44 ), .S(\UART_RXFF/n325 ), .Z(\UART_RXFF/n2372 ) );
notech_and2 \UART_RXFF/U373 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n324 ),
.Z(\UART_RXFF/n323 ) );
notech_mux2 \UART_RXFF/U372 ( .A(\UART_RXFF/iFIFOMem[62][0] ), .B(
\UART_RXFF/n3 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2373 ) );
notech_mux2 \UART_RXFF/U371 ( .A(\UART_RXFF/iFIFOMem[62][1] ), .B(
\UART_RXFF/n7 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2374 ) );
notech_mux2 \UART_RXFF/U370 ( .A(\UART_RXFF/iFIFOMem[62][2] ), .B(
\UART_RXFF/n11 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2375 ) );
notech_mux2 \UART_RXFF/U369 ( .A(\UART_RXFF/iFIFOMem[62][3] ), .B(
\UART_RXFF/n15 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2376 ) );
notech_mux2 \UART_RXFF/U368 ( .A(\UART_RXFF/iFIFOMem[62][4] ), .B(
\UART_RXFF/n19 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2377 ) );
notech_mux2 \UART_RXFF/U367 ( .A(\UART_RXFF/iFIFOMem[62][5] ), .B(
\UART_RXFF/n23 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2378 ) );
notech_mux2 \UART_RXFF/U366 ( .A(\UART_RXFF/iFIFOMem[62][6] ), .B(
\UART_RXFF/n27 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2379 ) );
notech_mux2 \UART_RXFF/U365 ( .A(\UART_RXFF/iFIFOMem[62][7] ), .B(
\UART_RXFF/n31 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2380 ) );
notech_mux2 \UART_RXFF/U364 ( .A(\UART_RXFF/iFIFOMem[62][8] ), .B(
\UART_RXFF/n35 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2381 ) );
notech_mux2 \UART_RXFF/U363 ( .A(\UART_RXFF/iFIFOMem[62][9] ), .B(
\UART_RXFF/n39 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2382 ) );
notech_mux2 \UART_RXFF/U362 ( .A(\UART_RXFF/iFIFOMem[62][10] ), .B(
\UART_RXFF/n43 ), .S(\UART_RXFF/n323 ), .Z(\UART_RXFF/n2383 ) );
notech_and2 \UART_RXFF/U361 ( .A(\UART_RXFF/n321 ), .B(\UART_RXFF/n322 ),
.Z(\UART_RXFF/n320 ) );
notech_mux2 \UART_RXFF/U360 ( .A(\UART_RXFF/iFIFOMem[63][0] ), .B(
\UART_RXFF/n2 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2384 ) );
notech_mux2 \UART_RXFF/U359 ( .A(\UART_RXFF/iFIFOMem[63][1] ), .B(
\UART_RXFF/n6 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2385 ) );
notech_mux2 \UART_RXFF/U358 ( .A(\UART_RXFF/iFIFOMem[63][2] ), .B(
\UART_RXFF/n10 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2386 ) );
notech_mux2 \UART_RXFF/U357 ( .A(\UART_RXFF/iFIFOMem[63][3] ), .B(
\UART_RXFF/n14 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2387 ) );
notech_mux2 \UART_RXFF/U356 ( .A(\UART_RXFF/iFIFOMem[63][4] ), .B(
\UART_RXFF/n18 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2388 ) );
notech_mux2 \UART_RXFF/U355 ( .A(\UART_RXFF/iFIFOMem[63][5] ), .B(
\UART_RXFF/n22 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2389 ) );
notech_mux2 \UART_RXFF/U354 ( .A(\UART_RXFF/iFIFOMem[63][6] ), .B(
\UART_RXFF/n26 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2390 ) );
notech_mux2 \UART_RXFF/U353 ( .A(\UART_RXFF/iFIFOMem[63][7] ), .B(
\UART_RXFF/n30 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2391 ) );
notech_mux2 \UART_RXFF/U352 ( .A(\UART_RXFF/iFIFOMem[63][8] ), .B(
\UART_RXFF/n34 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2392 ) );
notech_mux2 \UART_RXFF/U351 ( .A(\UART_RXFF/iFIFOMem[63][9] ), .B(
\UART_RXFF/n38 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2393 ) );
notech_mux2 \UART_RXFF/U350 ( .A(\UART_RXFF/iFIFOMem[63][10] ), .B(
\UART_RXFF/n42 ), .S(\UART_RXFF/n320 ), .Z(\UART_RXFF/n2394 ) );
notech_and2 \UART_RXFF/U349 ( .A(n371), .B(n438), .Z(\UART_RXFF/n318 ) );
notech_or2 \UART_RXFF/U348 ( .A(\UART_RXFF/n318 ), .B(iRXFIFOClear), .Z(
\UART_RXFF/n292 ) );
notech_inv \UART_RXFF/U347 ( .A(\UART_RXFF/N17 ), .Z(\UART_RXFF/n316 ) );
notech_nand2 \UART_RXFF/U346 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n308 ),
.Z(\UART_RXFF/n291 ) );
notech_inv \UART_RXFF/U345 ( .A(\UART_RXFF/N37 ), .Z(\UART_RXFF/n317 ) );
notech_nao4 \UART_RXFF/U344 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n316 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n317 ), .Z(\UART_RXFF/n2395 ) );
notech_inv \UART_RXFF/U343 ( .A(\UART_RXFF/N36 ), .Z(\UART_RXFF/n315 ) );
notech_nao4 \UART_RXFF/U342 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n314 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n315 ), .Z(\UART_RXFF/n2396 ) );
notech_inv \UART_RXFF/U341 ( .A(\UART_RXFF/N35 ), .Z(\UART_RXFF/n313 ) );
notech_nao4 \UART_RXFF/U340 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n49 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n313 ), .Z(\UART_RXFF/n2397 ) );
notech_inv \UART_RXFF/U339 ( .A(\UART_RXFF/N34 ), .Z(\UART_RXFF/n312 ) );
notech_nao4 \UART_RXFF/U338 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n46 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n312 ), .Z(\UART_RXFF/n2398 ) );
notech_inv \UART_RXFF/U337 ( .A(\UART_RXFF/N33 ), .Z(\UART_RXFF/n311 ) );
notech_nao4 \UART_RXFF/U336 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n60 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n311 ), .Z(\UART_RXFF/n2399 ) );
notech_inv \UART_RXFF/U335 ( .A(\UART_RXFF/iRDAddr[6] ), .Z(
\UART_RXFF/n309 ) );
notech_inv \UART_RXFF/U334 ( .A(\UART_RXFF/N38 ), .Z(\UART_RXFF/n310 ) );
notech_nao4 \UART_RXFF/U333 ( .A(\UART_RXFF/n292 ), .B(\UART_RXFF/n309 ),
.C(\UART_RXFF/n291 ), .D(\UART_RXFF/n310 ), .Z(\UART_RXFF/n2400 ) );
notech_inv \UART_RXFF/U332 ( .A(\UART_RXFF/iWRAddr[5] ), .Z(
\UART_RXFF/n306 ) );
notech_nand2 \UART_RXFF/U331 ( .A(\UART_RXFF/n294 ), .B(\UART_RXFF/n308 ),
.Z(\UART_RXFF/n295 ) );
notech_inv \UART_RXFF/U330 ( .A(\UART_RXFF/N29 ), .Z(\UART_RXFF/n307 ) );
notech_nao4 \UART_RXFF/U329 ( .A(\UART_RXFF/n306 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n307 ), .Z(\UART_RXFF/n2401 ) );
notech_inv \UART_RXFF/U328 ( .A(\UART_RXFF/iWRAddr[4] ), .Z(
\UART_RXFF/n304 ) );
notech_inv \UART_RXFF/U327 ( .A(\UART_RXFF/N28 ), .Z(\UART_RXFF/n305 ) );
notech_nao4 \UART_RXFF/U326 ( .A(\UART_RXFF/n304 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n305 ), .Z(\UART_RXFF/n2402 ) );
notech_inv \UART_RXFF/U325 ( .A(\UART_RXFF/N27 ), .Z(\UART_RXFF/n303 ) );
notech_nao4 \UART_RXFF/U324 ( .A(\UART_RXFF/n302 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n303 ), .Z(\UART_RXFF/n2403 ) );
notech_inv \UART_RXFF/U323 ( .A(\UART_RXFF/N26 ), .Z(\UART_RXFF/n301 ) );
notech_nao4 \UART_RXFF/U322 ( .A(\UART_RXFF/n300 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n301 ), .Z(\UART_RXFF/n2404 ) );
notech_inv \UART_RXFF/U321 ( .A(\UART_RXFF/N25 ), .Z(\UART_RXFF/n299 ) );
notech_nao4 \UART_RXFF/U320 ( .A(\UART_RXFF/n298 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n299 ), .Z(\UART_RXFF/n2405 ) );
notech_mux2 \UART_RXFF/U319 ( .A(\UART_RXFF/n295 ), .B(\UART_RXFF/n294 ),
.S(\UART_RXFF/iWRAddr[0] ), .Z(\UART_RXFF/n297 ) );
notech_inv \UART_RXFF/U318 ( .A(\UART_RXFF/n297 ), .Z(\UART_RXFF/n2406 ) );
notech_inv \UART_RXFF/U317 ( .A(\UART_RXFF/N30 ), .Z(\UART_RXFF/n296 ) );
notech_nao4 \UART_RXFF/U316 ( .A(\UART_RXFF/n293 ), .B(\UART_RXFF/n294 ),
.C(\UART_RXFF/n295 ), .D(\UART_RXFF/n296 ), .Z(\UART_RXFF/n2407 ) );
notech_mux2 \UART_RXFF/U315 ( .A(\UART_RXFF/n291 ), .B(\UART_RXFF/n292 ),
.S(\UART_RXFF/n64 ), .Z(\UART_RXFF/n290 ) );
notech_inv \UART_RXFF/U314 ( .A(\UART_RXFF/n290 ), .Z(\UART_RXFF/n2408 ) );
notech_mux2 \UART_RXFF/U313 ( .A(\UART_RXFF/N133 ), .B(iRXFIFOQ[0]), .S(RST), .Z(\UART_RXFF/n959 ) );
notech_mux2 \UART_RXFF/U312 ( .A(\UART_RXFF/N132 ), .B(iRXFIFOQ[1]), .S(RST), .Z(\UART_RXFF/n961 ) );
notech_mux2 \UART_RXFF/U311 ( .A(\UART_RXFF/N131 ), .B(iRXFIFOQ[2]), .S(RST), .Z(\UART_RXFF/n963 ) );
notech_mux2 \UART_RXFF/U310 ( .A(\UART_RXFF/N130 ), .B(iRXFIFOQ[3]), .S(RST), .Z(\UART_RXFF/n965 ) );
notech_mux2 \UART_RXFF/U309 ( .A(\UART_RXFF/N129 ), .B(iRXFIFOQ[4]), .S(RST), .Z(\UART_RXFF/n967 ) );
notech_mux2 \UART_RXFF/U308 ( .A(\UART_RXFF/N128 ), .B(iRXFIFOQ[5]), .S(RST), .Z(\UART_RXFF/n969 ) );
notech_mux2 \UART_RXFF/U307 ( .A(\UART_RXFF/N127 ), .B(iRXFIFOQ[6]), .S(RST), .Z(\UART_RXFF/n971 ) );
notech_mux2 \UART_RXFF/U306 ( .A(\UART_RXFF/N126 ), .B(iRXFIFOQ[7]), .S(RST), .Z(\UART_RXFF/n973 ) );
notech_mux2 \UART_RXFF/U305 ( .A(\UART_RXFF/N125 ), .B(iRXFIFOQ[8]), .S(RST), .Z(\UART_RXFF/n975 ) );
notech_mux2 \UART_RXFF/U304 ( .A(\UART_RXFF/N124 ), .B(iRXFIFOQ[9]), .S(RST), .Z(\UART_RXFF/n977 ) );
notech_mux2 \UART_RXFF/U303 ( .A(\UART_RXFF/N123 ), .B(iRXFIFOQ[10]), .S(
RST), .Z(\UART_RXFF/n979 ) );
notech_mux4 \UART_RXFF/U302 ( .A(\UART_RXFF/n289 ), .B(\UART_RXFF/n279 ),
.C(\UART_RXFF/n284 ), .D(\UART_RXFF/n274 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N123 ) );
notech_mux4 \UART_RXFF/U301 ( .A(\UART_RXFF/n288 ), .B(\UART_RXFF/n286 ),
.C(\UART_RXFF/n287 ), .D(\UART_RXFF/n285 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n289 ) );
notech_mux4 \UART_RXFF/U300 ( .A(\UART_RXFF/iFIFOMem[0][10] ), .B(
\UART_RXFF/iFIFOMem[2][10] ), .C(\UART_RXFF/iFIFOMem[1][10] ), .D(
\UART_RXFF/iFIFOMem[3][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n288 ) );
notech_mux4 \UART_RXFF/U299 ( .A(\UART_RXFF/iFIFOMem[4][10] ), .B(
\UART_RXFF/iFIFOMem[6][10] ), .C(\UART_RXFF/iFIFOMem[5][10] ), .D(
\UART_RXFF/iFIFOMem[7][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n287 ) );
notech_mux4 \UART_RXFF/U298 ( .A(\UART_RXFF/iFIFOMem[8][10] ), .B(
\UART_RXFF/iFIFOMem[10][10] ), .C(\UART_RXFF/iFIFOMem[9][10] ), .D(
\UART_RXFF/iFIFOMem[11][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n286 ) );
notech_mux4 \UART_RXFF/U297 ( .A(\UART_RXFF/iFIFOMem[12][10] ), .B(
\UART_RXFF/iFIFOMem[14][10] ), .C(\UART_RXFF/iFIFOMem[13][10] ), .D(
\UART_RXFF/iFIFOMem[15][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n285 ) );
notech_mux4 \UART_RXFF/U296 ( .A(\UART_RXFF/n283 ), .B(\UART_RXFF/n281 ),
.C(\UART_RXFF/n282 ), .D(\UART_RXFF/n280 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n284 ) );
notech_mux4 \UART_RXFF/U295 ( .A(\UART_RXFF/iFIFOMem[16][10] ), .B(
\UART_RXFF/iFIFOMem[18][10] ), .C(\UART_RXFF/iFIFOMem[17][10] ), .D(
\UART_RXFF/iFIFOMem[19][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n283 ) );
notech_mux4 \UART_RXFF/U294 ( .A(\UART_RXFF/iFIFOMem[20][10] ), .B(
\UART_RXFF/iFIFOMem[22][10] ), .C(\UART_RXFF/iFIFOMem[21][10] ), .D(
\UART_RXFF/iFIFOMem[23][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n282 ) );
notech_mux4 \UART_RXFF/U293 ( .A(\UART_RXFF/iFIFOMem[24][10] ), .B(
\UART_RXFF/iFIFOMem[26][10] ), .C(\UART_RXFF/iFIFOMem[25][10] ), .D(
\UART_RXFF/iFIFOMem[27][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n281 ) );
notech_mux4 \UART_RXFF/U292 ( .A(\UART_RXFF/iFIFOMem[28][10] ), .B(
\UART_RXFF/iFIFOMem[30][10] ), .C(\UART_RXFF/iFIFOMem[29][10] ), .D(
\UART_RXFF/iFIFOMem[31][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n280 ) );
notech_mux4 \UART_RXFF/U291 ( .A(\UART_RXFF/n278 ), .B(\UART_RXFF/n276 ),
.C(\UART_RXFF/n277 ), .D(\UART_RXFF/n275 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n279 ) );
notech_mux4 \UART_RXFF/U290 ( .A(\UART_RXFF/iFIFOMem[32][10] ), .B(
\UART_RXFF/iFIFOMem[34][10] ), .C(\UART_RXFF/iFIFOMem[33][10] ), .D(
\UART_RXFF/iFIFOMem[35][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n278 ) );
notech_mux4 \UART_RXFF/U289 ( .A(\UART_RXFF/iFIFOMem[36][10] ), .B(
\UART_RXFF/iFIFOMem[38][10] ), .C(\UART_RXFF/iFIFOMem[37][10] ), .D(
\UART_RXFF/iFIFOMem[39][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n277 ) );
notech_mux4 \UART_RXFF/U288 ( .A(\UART_RXFF/iFIFOMem[40][10] ), .B(
\UART_RXFF/iFIFOMem[42][10] ), .C(\UART_RXFF/iFIFOMem[41][10] ), .D(
\UART_RXFF/iFIFOMem[43][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n276 ) );
notech_mux4 \UART_RXFF/U287 ( .A(\UART_RXFF/iFIFOMem[44][10] ), .B(
\UART_RXFF/iFIFOMem[46][10] ), .C(\UART_RXFF/iFIFOMem[45][10] ), .D(
\UART_RXFF/iFIFOMem[47][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n275 ) );
notech_mux4 \UART_RXFF/U286 ( .A(\UART_RXFF/n273 ), .B(\UART_RXFF/n271 ),
.C(\UART_RXFF/n272 ), .D(\UART_RXFF/n270 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n274 ) );
notech_mux4 \UART_RXFF/U285 ( .A(\UART_RXFF/iFIFOMem[48][10] ), .B(
\UART_RXFF/iFIFOMem[50][10] ), .C(\UART_RXFF/iFIFOMem[49][10] ), .D(
\UART_RXFF/iFIFOMem[51][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n273 ) );
notech_mux4 \UART_RXFF/U284 ( .A(\UART_RXFF/iFIFOMem[52][10] ), .B(
\UART_RXFF/iFIFOMem[54][10] ), .C(\UART_RXFF/iFIFOMem[53][10] ), .D(
\UART_RXFF/iFIFOMem[55][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n272 ) );
notech_mux4 \UART_RXFF/U283 ( .A(\UART_RXFF/iFIFOMem[56][10] ), .B(
\UART_RXFF/iFIFOMem[58][10] ), .C(\UART_RXFF/iFIFOMem[57][10] ), .D(
\UART_RXFF/iFIFOMem[59][10] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n271 ) );
notech_mux4 \UART_RXFF/U282 ( .A(\UART_RXFF/iFIFOMem[60][10] ), .B(
\UART_RXFF/iFIFOMem[62][10] ), .C(\UART_RXFF/iFIFOMem[61][10] ), .D(
\UART_RXFF/iFIFOMem[63][10] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n270 ) );
notech_mux4 \UART_RXFF/U281 ( .A(\UART_RXFF/n269 ), .B(\UART_RXFF/n259 ),
.C(\UART_RXFF/n264 ), .D(\UART_RXFF/n254 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N124 ) );
notech_mux4 \UART_RXFF/U280 ( .A(\UART_RXFF/n268 ), .B(\UART_RXFF/n266 ),
.C(\UART_RXFF/n267 ), .D(\UART_RXFF/n265 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n269 ) );
notech_mux4 \UART_RXFF/U279 ( .A(\UART_RXFF/iFIFOMem[0][9] ), .B(
\UART_RXFF/iFIFOMem[2][9] ), .C(\UART_RXFF/iFIFOMem[1][9] ), .D(
\UART_RXFF/iFIFOMem[3][9] ), .S0(\UART_RXFF/n59 ), .S1(\UART_RXFF/n68 ), .Z(\UART_RXFF/n268 ) );
notech_mux4 \UART_RXFF/U278 ( .A(\UART_RXFF/iFIFOMem[4][9] ), .B(
\UART_RXFF/iFIFOMem[6][9] ), .C(\UART_RXFF/iFIFOMem[5][9] ), .D(
\UART_RXFF/iFIFOMem[7][9] ), .S0(\UART_RXFF/n59 ), .S1(\UART_RXFF/n68 ), .Z(\UART_RXFF/n267 ) );
notech_mux4 \UART_RXFF/U277 ( .A(\UART_RXFF/iFIFOMem[8][9] ), .B(
\UART_RXFF/iFIFOMem[10][9] ), .C(\UART_RXFF/iFIFOMem[9][9] ), .D(
\UART_RXFF/iFIFOMem[11][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n266 ) );
notech_mux4 \UART_RXFF/U276 ( .A(\UART_RXFF/iFIFOMem[12][9] ), .B(
\UART_RXFF/iFIFOMem[14][9] ), .C(\UART_RXFF/iFIFOMem[13][9] ), .D(
\UART_RXFF/iFIFOMem[15][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n265 ) );
notech_mux4 \UART_RXFF/U275 ( .A(\UART_RXFF/n263 ), .B(\UART_RXFF/n261 ),
.C(\UART_RXFF/n262 ), .D(\UART_RXFF/n260 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n264 ) );
notech_mux4 \UART_RXFF/U274 ( .A(\UART_RXFF/iFIFOMem[16][9] ), .B(
\UART_RXFF/iFIFOMem[18][9] ), .C(\UART_RXFF/iFIFOMem[17][9] ), .D(
\UART_RXFF/iFIFOMem[19][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n263 ) );
notech_mux4 \UART_RXFF/U273 ( .A(\UART_RXFF/iFIFOMem[20][9] ), .B(
\UART_RXFF/iFIFOMem[22][9] ), .C(\UART_RXFF/iFIFOMem[21][9] ), .D(
\UART_RXFF/iFIFOMem[23][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n262 ) );
notech_mux4 \UART_RXFF/U272 ( .A(\UART_RXFF/iFIFOMem[24][9] ), .B(
\UART_RXFF/iFIFOMem[26][9] ), .C(\UART_RXFF/iFIFOMem[25][9] ), .D(
\UART_RXFF/iFIFOMem[27][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n261 ) );
notech_mux4 \UART_RXFF/U271 ( .A(\UART_RXFF/iFIFOMem[28][9] ), .B(
\UART_RXFF/iFIFOMem[30][9] ), .C(\UART_RXFF/iFIFOMem[29][9] ), .D(
\UART_RXFF/iFIFOMem[31][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n260 ) );
notech_mux4 \UART_RXFF/U270 ( .A(\UART_RXFF/n258 ), .B(\UART_RXFF/n256 ),
.C(\UART_RXFF/n257 ), .D(\UART_RXFF/n255 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n259 ) );
notech_mux4 \UART_RXFF/U269 ( .A(\UART_RXFF/iFIFOMem[32][9] ), .B(
\UART_RXFF/iFIFOMem[34][9] ), .C(\UART_RXFF/iFIFOMem[33][9] ), .D(
\UART_RXFF/iFIFOMem[35][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n258 ) );
notech_mux4 \UART_RXFF/U268 ( .A(\UART_RXFF/iFIFOMem[36][9] ), .B(
\UART_RXFF/iFIFOMem[38][9] ), .C(\UART_RXFF/iFIFOMem[37][9] ), .D(
\UART_RXFF/iFIFOMem[39][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n257 ) );
notech_mux4 \UART_RXFF/U267 ( .A(\UART_RXFF/iFIFOMem[40][9] ), .B(
\UART_RXFF/iFIFOMem[42][9] ), .C(\UART_RXFF/iFIFOMem[41][9] ), .D(
\UART_RXFF/iFIFOMem[43][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n256 ) );
notech_mux4 \UART_RXFF/U266 ( .A(\UART_RXFF/iFIFOMem[44][9] ), .B(
\UART_RXFF/iFIFOMem[46][9] ), .C(\UART_RXFF/iFIFOMem[45][9] ), .D(
\UART_RXFF/iFIFOMem[47][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n255 ) );
notech_mux4 \UART_RXFF/U265 ( .A(\UART_RXFF/n253 ), .B(\UART_RXFF/n251 ),
.C(\UART_RXFF/n252 ), .D(\UART_RXFF/n250 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n254 ) );
notech_mux4 \UART_RXFF/U264 ( .A(\UART_RXFF/iFIFOMem[48][9] ), .B(
\UART_RXFF/iFIFOMem[50][9] ), .C(\UART_RXFF/iFIFOMem[49][9] ), .D(
\UART_RXFF/iFIFOMem[51][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n253 ) );
notech_mux4 \UART_RXFF/U263 ( .A(\UART_RXFF/iFIFOMem[52][9] ), .B(
\UART_RXFF/iFIFOMem[54][9] ), .C(\UART_RXFF/iFIFOMem[53][9] ), .D(
\UART_RXFF/iFIFOMem[55][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n252 ) );
notech_mux4 \UART_RXFF/U262 ( .A(\UART_RXFF/iFIFOMem[56][9] ), .B(
\UART_RXFF/iFIFOMem[58][9] ), .C(\UART_RXFF/iFIFOMem[57][9] ), .D(
\UART_RXFF/iFIFOMem[59][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n251 ) );
notech_mux4 \UART_RXFF/U261 ( .A(\UART_RXFF/iFIFOMem[60][9] ), .B(
\UART_RXFF/iFIFOMem[62][9] ), .C(\UART_RXFF/iFIFOMem[61][9] ), .D(
\UART_RXFF/iFIFOMem[63][9] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n68 ), .Z(\UART_RXFF/n250 ) );
notech_mux4 \UART_RXFF/U260 ( .A(\UART_RXFF/n249 ), .B(\UART_RXFF/n239 ),
.C(\UART_RXFF/n244 ), .D(\UART_RXFF/n234 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N125 ) );
notech_mux4 \UART_RXFF/U259 ( .A(\UART_RXFF/n248 ), .B(\UART_RXFF/n246 ),
.C(\UART_RXFF/n247 ), .D(\UART_RXFF/n245 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n249 ) );
notech_mux4 \UART_RXFF/U258 ( .A(\UART_RXFF/iFIFOMem[0][8] ), .B(
\UART_RXFF/iFIFOMem[2][8] ), .C(\UART_RXFF/iFIFOMem[1][8] ), .D(
\UART_RXFF/iFIFOMem[3][8] ), .S0(\UART_RXFF/n59 ), .S1(\UART_RXFF/n68 ), .Z(\UART_RXFF/n248 ) );
notech_mux4 \UART_RXFF/U257 ( .A(\UART_RXFF/iFIFOMem[4][8] ), .B(
\UART_RXFF/iFIFOMem[6][8] ), .C(\UART_RXFF/iFIFOMem[5][8] ), .D(
\UART_RXFF/iFIFOMem[7][8] ), .S0(\UART_RXFF/N13 ), .S1(\UART_RXFF/n68 ), .Z(\UART_RXFF/n247 ) );
notech_mux4 \UART_RXFF/U256 ( .A(\UART_RXFF/iFIFOMem[8][8] ), .B(
\UART_RXFF/iFIFOMem[10][8] ), .C(\UART_RXFF/iFIFOMem[9][8] ), .D(
\UART_RXFF/iFIFOMem[11][8] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n246 ) );
notech_mux4 \UART_RXFF/U255 ( .A(\UART_RXFF/iFIFOMem[12][8] ), .B(
\UART_RXFF/iFIFOMem[14][8] ), .C(\UART_RXFF/iFIFOMem[13][8] ), .D(
\UART_RXFF/iFIFOMem[15][8] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n245 ) );
notech_mux4 \UART_RXFF/U254 ( .A(\UART_RXFF/n243 ), .B(\UART_RXFF/n241 ),
.C(\UART_RXFF/n242 ), .D(\UART_RXFF/n240 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n244 ) );
notech_mux4 \UART_RXFF/U253 ( .A(\UART_RXFF/iFIFOMem[16][8] ), .B(
\UART_RXFF/iFIFOMem[18][8] ), .C(\UART_RXFF/iFIFOMem[17][8] ), .D(
\UART_RXFF/iFIFOMem[19][8] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n243 ) );
notech_mux4 \UART_RXFF/U252 ( .A(\UART_RXFF/iFIFOMem[20][8] ), .B(
\UART_RXFF/iFIFOMem[22][8] ), .C(\UART_RXFF/iFIFOMem[21][8] ), .D(
\UART_RXFF/iFIFOMem[23][8] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n242 ) );
notech_mux4 \UART_RXFF/U251 ( .A(\UART_RXFF/iFIFOMem[24][8] ), .B(
\UART_RXFF/iFIFOMem[26][8] ), .C(\UART_RXFF/iFIFOMem[25][8] ), .D(
\UART_RXFF/iFIFOMem[27][8] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n241 ) );
notech_mux4 \UART_RXFF/U250 ( .A(\UART_RXFF/iFIFOMem[28][8] ), .B(
\UART_RXFF/iFIFOMem[30][8] ), .C(\UART_RXFF/iFIFOMem[29][8] ), .D(
\UART_RXFF/iFIFOMem[31][8] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n240 ) );
notech_mux4 \UART_RXFF/U249 ( .A(\UART_RXFF/n238 ), .B(\UART_RXFF/n236 ),
.C(\UART_RXFF/n237 ), .D(\UART_RXFF/n235 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n239 ) );
notech_mux4 \UART_RXFF/U248 ( .A(\UART_RXFF/iFIFOMem[32][8] ), .B(
\UART_RXFF/iFIFOMem[34][8] ), .C(\UART_RXFF/iFIFOMem[33][8] ), .D(
\UART_RXFF/iFIFOMem[35][8] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n238 ) );
notech_mux4 \UART_RXFF/U247 ( .A(\UART_RXFF/iFIFOMem[36][8] ), .B(
\UART_RXFF/iFIFOMem[38][8] ), .C(\UART_RXFF/iFIFOMem[37][8] ), .D(
\UART_RXFF/iFIFOMem[39][8] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n237 ) );
notech_mux4 \UART_RXFF/U246 ( .A(\UART_RXFF/iFIFOMem[40][8] ), .B(
\UART_RXFF/iFIFOMem[42][8] ), .C(\UART_RXFF/iFIFOMem[41][8] ), .D(
\UART_RXFF/iFIFOMem[43][8] ), .S0(\UART_RXFF/N13 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n236 ) );
notech_mux4 \UART_RXFF/U245 ( .A(\UART_RXFF/iFIFOMem[44][8] ), .B(
\UART_RXFF/iFIFOMem[46][8] ), .C(\UART_RXFF/iFIFOMem[45][8] ), .D(
\UART_RXFF/iFIFOMem[47][8] ), .S0(\UART_RXFF/n59 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n235 ) );
notech_mux4 \UART_RXFF/U244 ( .A(\UART_RXFF/n233 ), .B(\UART_RXFF/n231 ),
.C(\UART_RXFF/n232 ), .D(\UART_RXFF/n230 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n234 ) );
notech_mux4 \UART_RXFF/U243 ( .A(\UART_RXFF/iFIFOMem[48][8] ), .B(
\UART_RXFF/iFIFOMem[50][8] ), .C(\UART_RXFF/iFIFOMem[49][8] ), .D(
\UART_RXFF/iFIFOMem[51][8] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n233 ) );
notech_mux4 \UART_RXFF/U242 ( .A(\UART_RXFF/iFIFOMem[52][8] ), .B(
\UART_RXFF/iFIFOMem[54][8] ), .C(\UART_RXFF/iFIFOMem[53][8] ), .D(
\UART_RXFF/iFIFOMem[55][8] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n232 ) );
notech_mux4 \UART_RXFF/U241 ( .A(\UART_RXFF/iFIFOMem[56][8] ), .B(
\UART_RXFF/iFIFOMem[58][8] ), .C(\UART_RXFF/iFIFOMem[57][8] ), .D(
\UART_RXFF/iFIFOMem[59][8] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n231 ) );
notech_mux4 \UART_RXFF/U240 ( .A(\UART_RXFF/iFIFOMem[60][8] ), .B(
\UART_RXFF/iFIFOMem[62][8] ), .C(\UART_RXFF/iFIFOMem[61][8] ), .D(
\UART_RXFF/iFIFOMem[63][8] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n230 ) );
notech_mux4 \UART_RXFF/U239 ( .A(\UART_RXFF/n229 ), .B(\UART_RXFF/n219 ),
.C(\UART_RXFF/n224 ), .D(\UART_RXFF/n214 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N126 ) );
notech_mux4 \UART_RXFF/U238 ( .A(\UART_RXFF/n228 ), .B(\UART_RXFF/n226 ),
.C(\UART_RXFF/n227 ), .D(\UART_RXFF/n225 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n229 ) );
notech_mux4 \UART_RXFF/U237 ( .A(\UART_RXFF/iFIFOMem[0][7] ), .B(
\UART_RXFF/iFIFOMem[2][7] ), .C(\UART_RXFF/iFIFOMem[1][7] ), .D(
\UART_RXFF/iFIFOMem[3][7] ), .S0(\UART_RXFF/n56 ), .S1(\UART_RXFF/n67 ), .Z(\UART_RXFF/n228 ) );
notech_mux4 \UART_RXFF/U236 ( .A(\UART_RXFF/iFIFOMem[4][7] ), .B(
\UART_RXFF/iFIFOMem[6][7] ), .C(\UART_RXFF/iFIFOMem[5][7] ), .D(
\UART_RXFF/iFIFOMem[7][7] ), .S0(\UART_RXFF/n57 ), .S1(\UART_RXFF/n67 ), .Z(\UART_RXFF/n227 ) );
notech_mux4 \UART_RXFF/U235 ( .A(\UART_RXFF/iFIFOMem[8][7] ), .B(
\UART_RXFF/iFIFOMem[10][7] ), .C(\UART_RXFF/iFIFOMem[9][7] ), .D(
\UART_RXFF/iFIFOMem[11][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n226 ) );
notech_mux4 \UART_RXFF/U234 ( .A(\UART_RXFF/iFIFOMem[12][7] ), .B(
\UART_RXFF/iFIFOMem[14][7] ), .C(\UART_RXFF/iFIFOMem[13][7] ), .D(
\UART_RXFF/iFIFOMem[15][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n67 ), .Z(\UART_RXFF/n225 ) );
notech_mux4 \UART_RXFF/U233 ( .A(\UART_RXFF/n223 ), .B(\UART_RXFF/n221 ),
.C(\UART_RXFF/n222 ), .D(\UART_RXFF/n220 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n224 ) );
notech_mux4 \UART_RXFF/U232 ( .A(\UART_RXFF/iFIFOMem[16][7] ), .B(
\UART_RXFF/iFIFOMem[18][7] ), .C(\UART_RXFF/iFIFOMem[17][7] ), .D(
\UART_RXFF/iFIFOMem[19][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n223 ) );
notech_mux4 \UART_RXFF/U231 ( .A(\UART_RXFF/iFIFOMem[20][7] ), .B(
\UART_RXFF/iFIFOMem[22][7] ), .C(\UART_RXFF/iFIFOMem[21][7] ), .D(
\UART_RXFF/iFIFOMem[23][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n222 ) );
notech_mux4 \UART_RXFF/U230 ( .A(\UART_RXFF/iFIFOMem[24][7] ), .B(
\UART_RXFF/iFIFOMem[26][7] ), .C(\UART_RXFF/iFIFOMem[25][7] ), .D(
\UART_RXFF/iFIFOMem[27][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n221 ) );
notech_mux4 \UART_RXFF/U229 ( .A(\UART_RXFF/iFIFOMem[28][7] ), .B(
\UART_RXFF/iFIFOMem[30][7] ), .C(\UART_RXFF/iFIFOMem[29][7] ), .D(
\UART_RXFF/iFIFOMem[31][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n220 ) );
notech_mux4 \UART_RXFF/U228 ( .A(\UART_RXFF/n218 ), .B(\UART_RXFF/n216 ),
.C(\UART_RXFF/n217 ), .D(\UART_RXFF/n215 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n219 ) );
notech_mux4 \UART_RXFF/U227 ( .A(\UART_RXFF/iFIFOMem[32][7] ), .B(
\UART_RXFF/iFIFOMem[34][7] ), .C(\UART_RXFF/iFIFOMem[33][7] ), .D(
\UART_RXFF/iFIFOMem[35][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n218 ) );
notech_mux4 \UART_RXFF/U226 ( .A(\UART_RXFF/iFIFOMem[36][7] ), .B(
\UART_RXFF/iFIFOMem[38][7] ), .C(\UART_RXFF/iFIFOMem[37][7] ), .D(
\UART_RXFF/iFIFOMem[39][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n217 ) );
notech_mux4 \UART_RXFF/U225 ( .A(\UART_RXFF/iFIFOMem[40][7] ), .B(
\UART_RXFF/iFIFOMem[42][7] ), .C(\UART_RXFF/iFIFOMem[41][7] ), .D(
\UART_RXFF/iFIFOMem[43][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n216 ) );
notech_mux4 \UART_RXFF/U224 ( .A(\UART_RXFF/iFIFOMem[44][7] ), .B(
\UART_RXFF/iFIFOMem[46][7] ), .C(\UART_RXFF/iFIFOMem[45][7] ), .D(
\UART_RXFF/iFIFOMem[47][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n215 ) );
notech_mux4 \UART_RXFF/U223 ( .A(\UART_RXFF/n213 ), .B(\UART_RXFF/n211 ),
.C(\UART_RXFF/n212 ), .D(\UART_RXFF/n210 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n214 ) );
notech_mux4 \UART_RXFF/U222 ( .A(\UART_RXFF/iFIFOMem[48][7] ), .B(
\UART_RXFF/iFIFOMem[50][7] ), .C(\UART_RXFF/iFIFOMem[49][7] ), .D(
\UART_RXFF/iFIFOMem[51][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n213 ) );
notech_mux4 \UART_RXFF/U221 ( .A(\UART_RXFF/iFIFOMem[52][7] ), .B(
\UART_RXFF/iFIFOMem[54][7] ), .C(\UART_RXFF/iFIFOMem[53][7] ), .D(
\UART_RXFF/iFIFOMem[55][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n212 ) );
notech_mux4 \UART_RXFF/U220 ( .A(\UART_RXFF/iFIFOMem[56][7] ), .B(
\UART_RXFF/iFIFOMem[58][7] ), .C(\UART_RXFF/iFIFOMem[57][7] ), .D(
\UART_RXFF/iFIFOMem[59][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n211 ) );
notech_mux4 \UART_RXFF/U219 ( .A(\UART_RXFF/iFIFOMem[60][7] ), .B(
\UART_RXFF/iFIFOMem[62][7] ), .C(\UART_RXFF/iFIFOMem[61][7] ), .D(
\UART_RXFF/iFIFOMem[63][7] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n210 ) );
notech_mux4 \UART_RXFF/U218 ( .A(\UART_RXFF/n209 ), .B(\UART_RXFF/n199 ),
.C(\UART_RXFF/n204 ), .D(\UART_RXFF/n194 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N127 ) );
notech_mux4 \UART_RXFF/U217 ( .A(\UART_RXFF/n208 ), .B(\UART_RXFF/n206 ),
.C(\UART_RXFF/n207 ), .D(\UART_RXFF/n205 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n209 ) );
notech_mux4 \UART_RXFF/U216 ( .A(\UART_RXFF/iFIFOMem[0][6] ), .B(
\UART_RXFF/iFIFOMem[2][6] ), .C(\UART_RXFF/iFIFOMem[1][6] ), .D(
\UART_RXFF/iFIFOMem[3][6] ), .S0(\UART_RXFF/n58 ), .S1(\UART_RXFF/n66 ), .Z(\UART_RXFF/n208 ) );
notech_mux4 \UART_RXFF/U215 ( .A(\UART_RXFF/iFIFOMem[4][6] ), .B(
\UART_RXFF/iFIFOMem[6][6] ), .C(\UART_RXFF/iFIFOMem[5][6] ), .D(
\UART_RXFF/iFIFOMem[7][6] ), .S0(\UART_RXFF/n58 ), .S1(\UART_RXFF/n66 ), .Z(\UART_RXFF/n207 ) );
notech_mux4 \UART_RXFF/U214 ( .A(\UART_RXFF/iFIFOMem[8][6] ), .B(
\UART_RXFF/iFIFOMem[10][6] ), .C(\UART_RXFF/iFIFOMem[9][6] ), .D(
\UART_RXFF/iFIFOMem[11][6] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n206 ) );
notech_mux4 \UART_RXFF/U213 ( .A(\UART_RXFF/iFIFOMem[12][6] ), .B(
\UART_RXFF/iFIFOMem[14][6] ), .C(\UART_RXFF/iFIFOMem[13][6] ), .D(
\UART_RXFF/iFIFOMem[15][6] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n205 ) );
notech_mux4 \UART_RXFF/U212 ( .A(\UART_RXFF/n203 ), .B(\UART_RXFF/n201 ),
.C(\UART_RXFF/n202 ), .D(\UART_RXFF/n200 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n204 ) );
notech_mux4 \UART_RXFF/U211 ( .A(\UART_RXFF/iFIFOMem[16][6] ), .B(
\UART_RXFF/iFIFOMem[18][6] ), .C(\UART_RXFF/iFIFOMem[17][6] ), .D(
\UART_RXFF/iFIFOMem[19][6] ), .S0(\UART_RXFF/n58 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n203 ) );
notech_mux4 \UART_RXFF/U210 ( .A(\UART_RXFF/iFIFOMem[20][6] ), .B(
\UART_RXFF/iFIFOMem[22][6] ), .C(\UART_RXFF/iFIFOMem[21][6] ), .D(
\UART_RXFF/iFIFOMem[23][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n66 ), .Z(\UART_RXFF/n202 ) );
notech_mux4 \UART_RXFF/U209 ( .A(\UART_RXFF/iFIFOMem[24][6] ), .B(
\UART_RXFF/iFIFOMem[26][6] ), .C(\UART_RXFF/iFIFOMem[25][6] ), .D(
\UART_RXFF/iFIFOMem[27][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n201 ) );
notech_mux4 \UART_RXFF/U208 ( .A(\UART_RXFF/iFIFOMem[28][6] ), .B(
\UART_RXFF/iFIFOMem[30][6] ), .C(\UART_RXFF/iFIFOMem[29][6] ), .D(
\UART_RXFF/iFIFOMem[31][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n200 ) );
notech_mux4 \UART_RXFF/U207 ( .A(\UART_RXFF/n198 ), .B(\UART_RXFF/n196 ),
.C(\UART_RXFF/n197 ), .D(\UART_RXFF/n195 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n199 ) );
notech_mux4 \UART_RXFF/U206 ( .A(\UART_RXFF/iFIFOMem[32][6] ), .B(
\UART_RXFF/iFIFOMem[34][6] ), .C(\UART_RXFF/iFIFOMem[33][6] ), .D(
\UART_RXFF/iFIFOMem[35][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n198 ) );
notech_mux4 \UART_RXFF/U205 ( .A(\UART_RXFF/iFIFOMem[36][6] ), .B(
\UART_RXFF/iFIFOMem[38][6] ), .C(\UART_RXFF/iFIFOMem[37][6] ), .D(
\UART_RXFF/iFIFOMem[39][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n197 ) );
notech_mux4 \UART_RXFF/U204 ( .A(\UART_RXFF/iFIFOMem[40][6] ), .B(
\UART_RXFF/iFIFOMem[42][6] ), .C(\UART_RXFF/iFIFOMem[41][6] ), .D(
\UART_RXFF/iFIFOMem[43][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n196 ) );
notech_mux4 \UART_RXFF/U203 ( .A(\UART_RXFF/iFIFOMem[44][6] ), .B(
\UART_RXFF/iFIFOMem[46][6] ), .C(\UART_RXFF/iFIFOMem[45][6] ), .D(
\UART_RXFF/iFIFOMem[47][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n195 ) );
notech_mux4 \UART_RXFF/U202 ( .A(\UART_RXFF/n193 ), .B(\UART_RXFF/n191 ),
.C(\UART_RXFF/n192 ), .D(\UART_RXFF/n190 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n194 ) );
notech_mux4 \UART_RXFF/U201 ( .A(\UART_RXFF/iFIFOMem[48][6] ), .B(
\UART_RXFF/iFIFOMem[50][6] ), .C(\UART_RXFF/iFIFOMem[49][6] ), .D(
\UART_RXFF/iFIFOMem[51][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n193 ) );
notech_mux4 \UART_RXFF/U200 ( .A(\UART_RXFF/iFIFOMem[52][6] ), .B(
\UART_RXFF/iFIFOMem[54][6] ), .C(\UART_RXFF/iFIFOMem[53][6] ), .D(
\UART_RXFF/iFIFOMem[55][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n192 ) );
notech_mux4 \UART_RXFF/U199 ( .A(\UART_RXFF/iFIFOMem[56][6] ), .B(
\UART_RXFF/iFIFOMem[58][6] ), .C(\UART_RXFF/iFIFOMem[57][6] ), .D(
\UART_RXFF/iFIFOMem[59][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n191 ) );
notech_mux4 \UART_RXFF/U198 ( .A(\UART_RXFF/iFIFOMem[60][6] ), .B(
\UART_RXFF/iFIFOMem[62][6] ), .C(\UART_RXFF/iFIFOMem[61][6] ), .D(
\UART_RXFF/iFIFOMem[63][6] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n190 ) );
notech_mux4 \UART_RXFF/U197 ( .A(\UART_RXFF/n189 ), .B(\UART_RXFF/n179 ),
.C(\UART_RXFF/n184 ), .D(\UART_RXFF/n174 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N128 ) );
notech_mux4 \UART_RXFF/U196 ( .A(\UART_RXFF/n188 ), .B(\UART_RXFF/n186 ),
.C(\UART_RXFF/n187 ), .D(\UART_RXFF/n185 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n189 ) );
notech_mux4 \UART_RXFF/U195 ( .A(\UART_RXFF/iFIFOMem[0][5] ), .B(
\UART_RXFF/iFIFOMem[2][5] ), .C(\UART_RXFF/iFIFOMem[1][5] ), .D(
\UART_RXFF/iFIFOMem[3][5] ), .S0(\UART_RXFF/n57 ), .S1(\UART_RXFF/n65 ), .Z(\UART_RXFF/n188 ) );
notech_mux4 \UART_RXFF/U194 ( .A(\UART_RXFF/iFIFOMem[4][5] ), .B(
\UART_RXFF/iFIFOMem[6][5] ), .C(\UART_RXFF/iFIFOMem[5][5] ), .D(
\UART_RXFF/iFIFOMem[7][5] ), .S0(\UART_RXFF/n57 ), .S1(\UART_RXFF/n65 ), .Z(\UART_RXFF/n187 ) );
notech_mux4 \UART_RXFF/U193 ( .A(\UART_RXFF/iFIFOMem[8][5] ), .B(
\UART_RXFF/iFIFOMem[10][5] ), .C(\UART_RXFF/iFIFOMem[9][5] ), .D(
\UART_RXFF/iFIFOMem[11][5] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n186 ) );
notech_mux4 \UART_RXFF/U192 ( .A(\UART_RXFF/iFIFOMem[12][5] ), .B(
\UART_RXFF/iFIFOMem[14][5] ), .C(\UART_RXFF/iFIFOMem[13][5] ), .D(
\UART_RXFF/iFIFOMem[15][5] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n185 ) );
notech_mux4 \UART_RXFF/U191 ( .A(\UART_RXFF/n183 ), .B(\UART_RXFF/n181 ),
.C(\UART_RXFF/n182 ), .D(\UART_RXFF/n180 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n184 ) );
notech_mux4 \UART_RXFF/U190 ( .A(\UART_RXFF/iFIFOMem[16][5] ), .B(
\UART_RXFF/iFIFOMem[18][5] ), .C(\UART_RXFF/iFIFOMem[17][5] ), .D(
\UART_RXFF/iFIFOMem[19][5] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n183 ) );
notech_mux4 \UART_RXFF/U189 ( .A(\UART_RXFF/iFIFOMem[20][5] ), .B(
\UART_RXFF/iFIFOMem[22][5] ), .C(\UART_RXFF/iFIFOMem[21][5] ), .D(
\UART_RXFF/iFIFOMem[23][5] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n182 ) );
notech_mux4 \UART_RXFF/U188 ( .A(\UART_RXFF/iFIFOMem[24][5] ), .B(
\UART_RXFF/iFIFOMem[26][5] ), .C(\UART_RXFF/iFIFOMem[25][5] ), .D(
\UART_RXFF/iFIFOMem[27][5] ), .S0(\UART_RXFF/n57 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n181 ) );
notech_mux4 \UART_RXFF/U187 ( .A(\UART_RXFF/iFIFOMem[28][5] ), .B(
\UART_RXFF/iFIFOMem[30][5] ), .C(\UART_RXFF/iFIFOMem[29][5] ), .D(
\UART_RXFF/iFIFOMem[31][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n65 ), .Z(\UART_RXFF/n180 ) );
notech_mux4 \UART_RXFF/U186 ( .A(\UART_RXFF/n178 ), .B(\UART_RXFF/n176 ),
.C(\UART_RXFF/n177 ), .D(\UART_RXFF/n175 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n179 ) );
notech_mux4 \UART_RXFF/U185 ( .A(\UART_RXFF/iFIFOMem[32][5] ), .B(
\UART_RXFF/iFIFOMem[34][5] ), .C(\UART_RXFF/iFIFOMem[33][5] ), .D(
\UART_RXFF/iFIFOMem[35][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n178 ) );
notech_mux4 \UART_RXFF/U184 ( .A(\UART_RXFF/iFIFOMem[36][5] ), .B(
\UART_RXFF/iFIFOMem[38][5] ), .C(\UART_RXFF/iFIFOMem[37][5] ), .D(
\UART_RXFF/iFIFOMem[39][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n177 ) );
notech_mux4 \UART_RXFF/U183 ( .A(\UART_RXFF/iFIFOMem[40][5] ), .B(
\UART_RXFF/iFIFOMem[42][5] ), .C(\UART_RXFF/iFIFOMem[41][5] ), .D(
\UART_RXFF/iFIFOMem[43][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n176 ) );
notech_mux4 \UART_RXFF/U182 ( .A(\UART_RXFF/iFIFOMem[44][5] ), .B(
\UART_RXFF/iFIFOMem[46][5] ), .C(\UART_RXFF/iFIFOMem[45][5] ), .D(
\UART_RXFF/iFIFOMem[47][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n175 ) );
notech_mux4 \UART_RXFF/U181 ( .A(\UART_RXFF/n173 ), .B(\UART_RXFF/n171 ),
.C(\UART_RXFF/n172 ), .D(\UART_RXFF/n170 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n174 ) );
notech_mux4 \UART_RXFF/U180 ( .A(\UART_RXFF/iFIFOMem[48][5] ), .B(
\UART_RXFF/iFIFOMem[50][5] ), .C(\UART_RXFF/iFIFOMem[49][5] ), .D(
\UART_RXFF/iFIFOMem[51][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n173 ) );
notech_mux4 \UART_RXFF/U179 ( .A(\UART_RXFF/iFIFOMem[52][5] ), .B(
\UART_RXFF/iFIFOMem[54][5] ), .C(\UART_RXFF/iFIFOMem[53][5] ), .D(
\UART_RXFF/iFIFOMem[55][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n172 ) );
notech_mux4 \UART_RXFF/U178 ( .A(\UART_RXFF/iFIFOMem[56][5] ), .B(
\UART_RXFF/iFIFOMem[58][5] ), .C(\UART_RXFF/iFIFOMem[57][5] ), .D(
\UART_RXFF/iFIFOMem[59][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n171 ) );
notech_mux4 \UART_RXFF/U177 ( .A(\UART_RXFF/iFIFOMem[60][5] ), .B(
\UART_RXFF/iFIFOMem[62][5] ), .C(\UART_RXFF/iFIFOMem[61][5] ), .D(
\UART_RXFF/iFIFOMem[63][5] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n170 ) );
notech_mux4 \UART_RXFF/U176 ( .A(\UART_RXFF/n169 ), .B(\UART_RXFF/n159 ),
.C(\UART_RXFF/n164 ), .D(\UART_RXFF/n154 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N129 ) );
notech_mux4 \UART_RXFF/U175 ( .A(\UART_RXFF/n168 ), .B(\UART_RXFF/n166 ),
.C(\UART_RXFF/n167 ), .D(\UART_RXFF/n165 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n169 ) );
notech_mux4 \UART_RXFF/U174 ( .A(\UART_RXFF/iFIFOMem[0][4] ), .B(
\UART_RXFF/iFIFOMem[2][4] ), .C(\UART_RXFF/iFIFOMem[1][4] ), .D(
\UART_RXFF/iFIFOMem[3][4] ), .S0(\UART_RXFF/n56 ), .S1(\UART_RXFF/n64 ), .Z(\UART_RXFF/n168 ) );
notech_mux4 \UART_RXFF/U173 ( .A(\UART_RXFF/iFIFOMem[4][4] ), .B(
\UART_RXFF/iFIFOMem[6][4] ), .C(\UART_RXFF/iFIFOMem[5][4] ), .D(
\UART_RXFF/iFIFOMem[7][4] ), .S0(\UART_RXFF/n56 ), .S1(\UART_RXFF/n64 ), .Z(\UART_RXFF/n167 ) );
notech_mux4 \UART_RXFF/U172 ( .A(\UART_RXFF/iFIFOMem[8][4] ), .B(
\UART_RXFF/iFIFOMem[10][4] ), .C(\UART_RXFF/iFIFOMem[9][4] ), .D(
\UART_RXFF/iFIFOMem[11][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n166 ) );
notech_mux4 \UART_RXFF/U171 ( .A(\UART_RXFF/iFIFOMem[12][4] ), .B(
\UART_RXFF/iFIFOMem[14][4] ), .C(\UART_RXFF/iFIFOMem[13][4] ), .D(
\UART_RXFF/iFIFOMem[15][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n165 ) );
notech_mux4 \UART_RXFF/U170 ( .A(\UART_RXFF/n163 ), .B(\UART_RXFF/n161 ),
.C(\UART_RXFF/n162 ), .D(\UART_RXFF/n160 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n164 ) );
notech_mux4 \UART_RXFF/U169 ( .A(\UART_RXFF/iFIFOMem[16][4] ), .B(
\UART_RXFF/iFIFOMem[18][4] ), .C(\UART_RXFF/iFIFOMem[17][4] ), .D(
\UART_RXFF/iFIFOMem[19][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n163 ) );
notech_mux4 \UART_RXFF/U168 ( .A(\UART_RXFF/iFIFOMem[20][4] ), .B(
\UART_RXFF/iFIFOMem[22][4] ), .C(\UART_RXFF/iFIFOMem[21][4] ), .D(
\UART_RXFF/iFIFOMem[23][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n162 ) );
notech_mux4 \UART_RXFF/U167 ( .A(\UART_RXFF/iFIFOMem[24][4] ), .B(
\UART_RXFF/iFIFOMem[26][4] ), .C(\UART_RXFF/iFIFOMem[25][4] ), .D(
\UART_RXFF/iFIFOMem[27][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n161 ) );
notech_mux4 \UART_RXFF/U166 ( .A(\UART_RXFF/iFIFOMem[28][4] ), .B(
\UART_RXFF/iFIFOMem[30][4] ), .C(\UART_RXFF/iFIFOMem[29][4] ), .D(
\UART_RXFF/iFIFOMem[31][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n160 ) );
notech_mux4 \UART_RXFF/U165 ( .A(\UART_RXFF/n158 ), .B(\UART_RXFF/n156 ),
.C(\UART_RXFF/n157 ), .D(\UART_RXFF/n155 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n159 ) );
notech_mux4 \UART_RXFF/U164 ( .A(\UART_RXFF/iFIFOMem[32][4] ), .B(
\UART_RXFF/iFIFOMem[34][4] ), .C(\UART_RXFF/iFIFOMem[33][4] ), .D(
\UART_RXFF/iFIFOMem[35][4] ), .S0(\UART_RXFF/n56 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n158 ) );
notech_mux4 \UART_RXFF/U163 ( .A(\UART_RXFF/iFIFOMem[36][4] ), .B(
\UART_RXFF/iFIFOMem[38][4] ), .C(\UART_RXFF/iFIFOMem[37][4] ), .D(
\UART_RXFF/iFIFOMem[39][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n64 ), .Z(\UART_RXFF/n157 ) );
notech_mux4 \UART_RXFF/U162 ( .A(\UART_RXFF/iFIFOMem[40][4] ), .B(
\UART_RXFF/iFIFOMem[42][4] ), .C(\UART_RXFF/iFIFOMem[41][4] ), .D(
\UART_RXFF/iFIFOMem[43][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n156 ) );
notech_mux4 \UART_RXFF/U161 ( .A(\UART_RXFF/iFIFOMem[44][4] ), .B(
\UART_RXFF/iFIFOMem[46][4] ), .C(\UART_RXFF/iFIFOMem[45][4] ), .D(
\UART_RXFF/iFIFOMem[47][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n155 ) );
notech_mux4 \UART_RXFF/U160 ( .A(\UART_RXFF/n153 ), .B(\UART_RXFF/n151 ),
.C(\UART_RXFF/n152 ), .D(\UART_RXFF/n150 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n154 ) );
notech_mux4 \UART_RXFF/U159 ( .A(\UART_RXFF/iFIFOMem[48][4] ), .B(
\UART_RXFF/iFIFOMem[50][4] ), .C(\UART_RXFF/iFIFOMem[49][4] ), .D(
\UART_RXFF/iFIFOMem[51][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n153 ) );
notech_mux4 \UART_RXFF/U158 ( .A(\UART_RXFF/iFIFOMem[52][4] ), .B(
\UART_RXFF/iFIFOMem[54][4] ), .C(\UART_RXFF/iFIFOMem[53][4] ), .D(
\UART_RXFF/iFIFOMem[55][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n152 ) );
notech_mux4 \UART_RXFF/U157 ( .A(\UART_RXFF/iFIFOMem[56][4] ), .B(
\UART_RXFF/iFIFOMem[58][4] ), .C(\UART_RXFF/iFIFOMem[57][4] ), .D(
\UART_RXFF/iFIFOMem[59][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n151 ) );
notech_mux4 \UART_RXFF/U156 ( .A(\UART_RXFF/iFIFOMem[60][4] ), .B(
\UART_RXFF/iFIFOMem[62][4] ), .C(\UART_RXFF/iFIFOMem[61][4] ), .D(
\UART_RXFF/iFIFOMem[63][4] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n150 ) );
notech_mux4 \UART_RXFF/U155 ( .A(\UART_RXFF/n149 ), .B(\UART_RXFF/n139 ),
.C(\UART_RXFF/n144 ), .D(\UART_RXFF/n134 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N130 ) );
notech_mux4 \UART_RXFF/U154 ( .A(\UART_RXFF/n148 ), .B(\UART_RXFF/n146 ),
.C(\UART_RXFF/n147 ), .D(\UART_RXFF/n145 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n149 ) );
notech_mux4 \UART_RXFF/U153 ( .A(\UART_RXFF/iFIFOMem[0][3] ), .B(
\UART_RXFF/iFIFOMem[2][3] ), .C(\UART_RXFF/iFIFOMem[1][3] ), .D(
\UART_RXFF/iFIFOMem[3][3] ), .S0(\UART_RXFF/n55 ), .S1(\UART_RXFF/n63 ), .Z(\UART_RXFF/n148 ) );
notech_mux4 \UART_RXFF/U152 ( .A(\UART_RXFF/iFIFOMem[4][3] ), .B(
\UART_RXFF/iFIFOMem[6][3] ), .C(\UART_RXFF/iFIFOMem[5][3] ), .D(
\UART_RXFF/iFIFOMem[7][3] ), .S0(\UART_RXFF/n55 ), .S1(\UART_RXFF/n63 ), .Z(\UART_RXFF/n147 ) );
notech_mux4 \UART_RXFF/U151 ( .A(\UART_RXFF/iFIFOMem[8][3] ), .B(
\UART_RXFF/iFIFOMem[10][3] ), .C(\UART_RXFF/iFIFOMem[9][3] ), .D(
\UART_RXFF/iFIFOMem[11][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n146 ) );
notech_mux4 \UART_RXFF/U150 ( .A(\UART_RXFF/iFIFOMem[12][3] ), .B(
\UART_RXFF/iFIFOMem[14][3] ), .C(\UART_RXFF/iFIFOMem[13][3] ), .D(
\UART_RXFF/iFIFOMem[15][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n145 ) );
notech_mux4 \UART_RXFF/U149 ( .A(\UART_RXFF/n143 ), .B(\UART_RXFF/n141 ),
.C(\UART_RXFF/n142 ), .D(\UART_RXFF/n140 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n144 ) );
notech_mux4 \UART_RXFF/U148 ( .A(\UART_RXFF/iFIFOMem[16][3] ), .B(
\UART_RXFF/iFIFOMem[18][3] ), .C(\UART_RXFF/iFIFOMem[17][3] ), .D(
\UART_RXFF/iFIFOMem[19][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n143 ) );
notech_mux4 \UART_RXFF/U147 ( .A(\UART_RXFF/iFIFOMem[20][3] ), .B(
\UART_RXFF/iFIFOMem[22][3] ), .C(\UART_RXFF/iFIFOMem[21][3] ), .D(
\UART_RXFF/iFIFOMem[23][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n142 ) );
notech_mux4 \UART_RXFF/U146 ( .A(\UART_RXFF/iFIFOMem[24][3] ), .B(
\UART_RXFF/iFIFOMem[26][3] ), .C(\UART_RXFF/iFIFOMem[25][3] ), .D(
\UART_RXFF/iFIFOMem[27][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n141 ) );
notech_mux4 \UART_RXFF/U145 ( .A(\UART_RXFF/iFIFOMem[28][3] ), .B(
\UART_RXFF/iFIFOMem[30][3] ), .C(\UART_RXFF/iFIFOMem[29][3] ), .D(
\UART_RXFF/iFIFOMem[31][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n140 ) );
notech_mux4 \UART_RXFF/U144 ( .A(\UART_RXFF/n138 ), .B(\UART_RXFF/n136 ),
.C(\UART_RXFF/n137 ), .D(\UART_RXFF/n135 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n139 ) );
notech_mux4 \UART_RXFF/U143 ( .A(\UART_RXFF/iFIFOMem[32][3] ), .B(
\UART_RXFF/iFIFOMem[34][3] ), .C(\UART_RXFF/iFIFOMem[33][3] ), .D(
\UART_RXFF/iFIFOMem[35][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n138 ) );
notech_mux4 \UART_RXFF/U142 ( .A(\UART_RXFF/iFIFOMem[36][3] ), .B(
\UART_RXFF/iFIFOMem[38][3] ), .C(\UART_RXFF/iFIFOMem[37][3] ), .D(
\UART_RXFF/iFIFOMem[39][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n137 ) );
notech_mux4 \UART_RXFF/U141 ( .A(\UART_RXFF/iFIFOMem[40][3] ), .B(
\UART_RXFF/iFIFOMem[42][3] ), .C(\UART_RXFF/iFIFOMem[41][3] ), .D(
\UART_RXFF/iFIFOMem[43][3] ), .S0(\UART_RXFF/n55 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n136 ) );
notech_mux4 \UART_RXFF/U140 ( .A(\UART_RXFF/iFIFOMem[44][3] ), .B(
\UART_RXFF/iFIFOMem[46][3] ), .C(\UART_RXFF/iFIFOMem[45][3] ), .D(
\UART_RXFF/iFIFOMem[47][3] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n63 ), .Z(\UART_RXFF/n135 ) );
notech_mux4 \UART_RXFF/U139 ( .A(\UART_RXFF/n133 ), .B(\UART_RXFF/n131 ),
.C(\UART_RXFF/n132 ), .D(\UART_RXFF/n130 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n134 ) );
notech_mux4 \UART_RXFF/U138 ( .A(\UART_RXFF/iFIFOMem[48][3] ), .B(
\UART_RXFF/iFIFOMem[50][3] ), .C(\UART_RXFF/iFIFOMem[49][3] ), .D(
\UART_RXFF/iFIFOMem[51][3] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n133 ) );
notech_mux4 \UART_RXFF/U137 ( .A(\UART_RXFF/iFIFOMem[52][3] ), .B(
\UART_RXFF/iFIFOMem[54][3] ), .C(\UART_RXFF/iFIFOMem[53][3] ), .D(
\UART_RXFF/iFIFOMem[55][3] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n132 ) );
notech_mux4 \UART_RXFF/U136 ( .A(\UART_RXFF/iFIFOMem[56][3] ), .B(
\UART_RXFF/iFIFOMem[58][3] ), .C(\UART_RXFF/iFIFOMem[57][3] ), .D(
\UART_RXFF/iFIFOMem[59][3] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n131 ) );
notech_mux4 \UART_RXFF/U135 ( .A(\UART_RXFF/iFIFOMem[60][3] ), .B(
\UART_RXFF/iFIFOMem[62][3] ), .C(\UART_RXFF/iFIFOMem[61][3] ), .D(
\UART_RXFF/iFIFOMem[63][3] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n130 ) );
notech_mux4 \UART_RXFF/U134 ( .A(\UART_RXFF/n129 ), .B(\UART_RXFF/n119 ),
.C(\UART_RXFF/n124 ), .D(\UART_RXFF/n114 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N131 ) );
notech_mux4 \UART_RXFF/U133 ( .A(\UART_RXFF/n128 ), .B(\UART_RXFF/n126 ),
.C(\UART_RXFF/n127 ), .D(\UART_RXFF/n125 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n129 ) );
notech_mux4 \UART_RXFF/U132 ( .A(\UART_RXFF/iFIFOMem[0][2] ), .B(
\UART_RXFF/iFIFOMem[2][2] ), .C(\UART_RXFF/iFIFOMem[1][2] ), .D(
\UART_RXFF/iFIFOMem[3][2] ), .S0(\UART_RXFF/n54 ), .S1(\UART_RXFF/n62 ), .Z(\UART_RXFF/n128 ) );
notech_mux4 \UART_RXFF/U131 ( .A(\UART_RXFF/iFIFOMem[4][2] ), .B(
\UART_RXFF/iFIFOMem[6][2] ), .C(\UART_RXFF/iFIFOMem[5][2] ), .D(
\UART_RXFF/iFIFOMem[7][2] ), .S0(\UART_RXFF/n54 ), .S1(\UART_RXFF/n62 ), .Z(\UART_RXFF/n127 ) );
notech_mux4 \UART_RXFF/U130 ( .A(\UART_RXFF/iFIFOMem[8][2] ), .B(
\UART_RXFF/iFIFOMem[10][2] ), .C(\UART_RXFF/iFIFOMem[9][2] ), .D(
\UART_RXFF/iFIFOMem[11][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n126 ) );
notech_mux4 \UART_RXFF/U129 ( .A(\UART_RXFF/iFIFOMem[12][2] ), .B(
\UART_RXFF/iFIFOMem[14][2] ), .C(\UART_RXFF/iFIFOMem[13][2] ), .D(
\UART_RXFF/iFIFOMem[15][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n125 ) );
notech_mux4 \UART_RXFF/U128 ( .A(\UART_RXFF/n123 ), .B(\UART_RXFF/n121 ),
.C(\UART_RXFF/n122 ), .D(\UART_RXFF/n120 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n124 ) );
notech_mux4 \UART_RXFF/U127 ( .A(\UART_RXFF/iFIFOMem[16][2] ), .B(
\UART_RXFF/iFIFOMem[18][2] ), .C(\UART_RXFF/iFIFOMem[17][2] ), .D(
\UART_RXFF/iFIFOMem[19][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n123 ) );
notech_mux4 \UART_RXFF/U126 ( .A(\UART_RXFF/iFIFOMem[20][2] ), .B(
\UART_RXFF/iFIFOMem[22][2] ), .C(\UART_RXFF/iFIFOMem[21][2] ), .D(
\UART_RXFF/iFIFOMem[23][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n122 ) );
notech_mux4 \UART_RXFF/U125 ( .A(\UART_RXFF/iFIFOMem[24][2] ), .B(
\UART_RXFF/iFIFOMem[26][2] ), .C(\UART_RXFF/iFIFOMem[25][2] ), .D(
\UART_RXFF/iFIFOMem[27][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n121 ) );
notech_mux4 \UART_RXFF/U124 ( .A(\UART_RXFF/iFIFOMem[28][2] ), .B(
\UART_RXFF/iFIFOMem[30][2] ), .C(\UART_RXFF/iFIFOMem[29][2] ), .D(
\UART_RXFF/iFIFOMem[31][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n120 ) );
notech_mux4 \UART_RXFF/U123 ( .A(\UART_RXFF/n118 ), .B(\UART_RXFF/n116 ),
.C(\UART_RXFF/n117 ), .D(\UART_RXFF/n115 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n119 ) );
notech_mux4 \UART_RXFF/U122 ( .A(\UART_RXFF/iFIFOMem[32][2] ), .B(
\UART_RXFF/iFIFOMem[34][2] ), .C(\UART_RXFF/iFIFOMem[33][2] ), .D(
\UART_RXFF/iFIFOMem[35][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n118 ) );
notech_mux4 \UART_RXFF/U121 ( .A(\UART_RXFF/iFIFOMem[36][2] ), .B(
\UART_RXFF/iFIFOMem[38][2] ), .C(\UART_RXFF/iFIFOMem[37][2] ), .D(
\UART_RXFF/iFIFOMem[39][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n117 ) );
notech_mux4 \UART_RXFF/U120 ( .A(\UART_RXFF/iFIFOMem[40][2] ), .B(
\UART_RXFF/iFIFOMem[42][2] ), .C(\UART_RXFF/iFIFOMem[41][2] ), .D(
\UART_RXFF/iFIFOMem[43][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n116 ) );
notech_mux4 \UART_RXFF/U119 ( .A(\UART_RXFF/iFIFOMem[44][2] ), .B(
\UART_RXFF/iFIFOMem[46][2] ), .C(\UART_RXFF/iFIFOMem[45][2] ), .D(
\UART_RXFF/iFIFOMem[47][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n115 ) );
notech_mux4 \UART_RXFF/U118 ( .A(\UART_RXFF/n113 ), .B(\UART_RXFF/n111 ),
.C(\UART_RXFF/n112 ), .D(\UART_RXFF/n110 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n114 ) );
notech_mux4 \UART_RXFF/U117 ( .A(\UART_RXFF/iFIFOMem[48][2] ), .B(
\UART_RXFF/iFIFOMem[50][2] ), .C(\UART_RXFF/iFIFOMem[49][2] ), .D(
\UART_RXFF/iFIFOMem[51][2] ), .S0(\UART_RXFF/n54 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n113 ) );
notech_mux4 \UART_RXFF/U116 ( .A(\UART_RXFF/iFIFOMem[52][2] ), .B(
\UART_RXFF/iFIFOMem[54][2] ), .C(\UART_RXFF/iFIFOMem[53][2] ), .D(
\UART_RXFF/iFIFOMem[55][2] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n62 ), .Z(\UART_RXFF/n112 ) );
notech_mux4 \UART_RXFF/U115 ( .A(\UART_RXFF/iFIFOMem[56][2] ), .B(
\UART_RXFF/iFIFOMem[58][2] ), .C(\UART_RXFF/iFIFOMem[57][2] ), .D(
\UART_RXFF/iFIFOMem[59][2] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n111 ) );
notech_mux4 \UART_RXFF/U114 ( .A(\UART_RXFF/iFIFOMem[60][2] ), .B(
\UART_RXFF/iFIFOMem[62][2] ), .C(\UART_RXFF/iFIFOMem[61][2] ), .D(
\UART_RXFF/iFIFOMem[63][2] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n110 ) );
notech_mux4 \UART_RXFF/U113 ( .A(\UART_RXFF/n109 ), .B(\UART_RXFF/n99 ),
.C(\UART_RXFF/n104 ), .D(\UART_RXFF/n94 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N132 ) );
notech_mux4 \UART_RXFF/U112 ( .A(\UART_RXFF/n108 ), .B(\UART_RXFF/n106 ),
.C(\UART_RXFF/n107 ), .D(\UART_RXFF/n105 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n109 ) );
notech_mux4 \UART_RXFF/U111 ( .A(\UART_RXFF/iFIFOMem[0][1] ), .B(
\UART_RXFF/iFIFOMem[2][1] ), .C(\UART_RXFF/iFIFOMem[1][1] ), .D(
\UART_RXFF/iFIFOMem[3][1] ), .S0(\UART_RXFF/n53 ), .S1(\UART_RXFF/n61 ), .Z(\UART_RXFF/n108 ) );
notech_mux4 \UART_RXFF/U110 ( .A(\UART_RXFF/iFIFOMem[4][1] ), .B(
\UART_RXFF/iFIFOMem[6][1] ), .C(\UART_RXFF/iFIFOMem[5][1] ), .D(
\UART_RXFF/iFIFOMem[7][1] ), .S0(\UART_RXFF/n53 ), .S1(\UART_RXFF/n61 ), .Z(\UART_RXFF/n107 ) );
notech_mux4 \UART_RXFF/U109 ( .A(\UART_RXFF/iFIFOMem[8][1] ), .B(
\UART_RXFF/iFIFOMem[10][1] ), .C(\UART_RXFF/iFIFOMem[9][1] ), .D(
\UART_RXFF/iFIFOMem[11][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n106 ) );
notech_mux4 \UART_RXFF/U108 ( .A(\UART_RXFF/iFIFOMem[12][1] ), .B(
\UART_RXFF/iFIFOMem[14][1] ), .C(\UART_RXFF/iFIFOMem[13][1] ), .D(
\UART_RXFF/iFIFOMem[15][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n105 ) );
notech_mux4 \UART_RXFF/U107 ( .A(\UART_RXFF/n103 ), .B(\UART_RXFF/n101 ),
.C(\UART_RXFF/n102 ), .D(\UART_RXFF/n100 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n104 ) );
notech_mux4 \UART_RXFF/U106 ( .A(\UART_RXFF/iFIFOMem[16][1] ), .B(
\UART_RXFF/iFIFOMem[18][1] ), .C(\UART_RXFF/iFIFOMem[17][1] ), .D(
\UART_RXFF/iFIFOMem[19][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n103 ) );
notech_mux4 \UART_RXFF/U105 ( .A(\UART_RXFF/iFIFOMem[20][1] ), .B(
\UART_RXFF/iFIFOMem[22][1] ), .C(\UART_RXFF/iFIFOMem[21][1] ), .D(
\UART_RXFF/iFIFOMem[23][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n102 ) );
notech_mux4 \UART_RXFF/U104 ( .A(\UART_RXFF/iFIFOMem[24][1] ), .B(
\UART_RXFF/iFIFOMem[26][1] ), .C(\UART_RXFF/iFIFOMem[25][1] ), .D(
\UART_RXFF/iFIFOMem[27][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n101 ) );
notech_mux4 \UART_RXFF/U103 ( .A(\UART_RXFF/iFIFOMem[28][1] ), .B(
\UART_RXFF/iFIFOMem[30][1] ), .C(\UART_RXFF/iFIFOMem[29][1] ), .D(
\UART_RXFF/iFIFOMem[31][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n100 ) );
notech_mux4 \UART_RXFF/U102 ( .A(\UART_RXFF/n98 ), .B(\UART_RXFF/n96 ), .C(
\UART_RXFF/n97 ), .D(\UART_RXFF/n95 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n99 ) );
notech_mux4 \UART_RXFF/U101 ( .A(\UART_RXFF/iFIFOMem[32][1] ), .B(
\UART_RXFF/iFIFOMem[34][1] ), .C(\UART_RXFF/iFIFOMem[33][1] ), .D(
\UART_RXFF/iFIFOMem[35][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n98 ) );
notech_mux4 \UART_RXFF/U100 ( .A(\UART_RXFF/iFIFOMem[36][1] ), .B(
\UART_RXFF/iFIFOMem[38][1] ), .C(\UART_RXFF/iFIFOMem[37][1] ), .D(
\UART_RXFF/iFIFOMem[39][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n97 ) );
notech_mux4 \UART_RXFF/U99 ( .A(\UART_RXFF/iFIFOMem[40][1] ), .B(
\UART_RXFF/iFIFOMem[42][1] ), .C(\UART_RXFF/iFIFOMem[41][1] ), .D(
\UART_RXFF/iFIFOMem[43][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n96 ) );
notech_mux4 \UART_RXFF/U98 ( .A(\UART_RXFF/iFIFOMem[44][1] ), .B(
\UART_RXFF/iFIFOMem[46][1] ), .C(\UART_RXFF/iFIFOMem[45][1] ), .D(
\UART_RXFF/iFIFOMem[47][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n95 ) );
notech_mux4 \UART_RXFF/U97 ( .A(\UART_RXFF/n93 ), .B(\UART_RXFF/n91 ), .C(
\UART_RXFF/n92 ), .D(\UART_RXFF/n90 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n94 ) );
notech_mux4 \UART_RXFF/U96 ( .A(\UART_RXFF/iFIFOMem[48][1] ), .B(
\UART_RXFF/iFIFOMem[50][1] ), .C(\UART_RXFF/iFIFOMem[49][1] ), .D(
\UART_RXFF/iFIFOMem[51][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n93 ) );
notech_mux4 \UART_RXFF/U95 ( .A(\UART_RXFF/iFIFOMem[52][1] ), .B(
\UART_RXFF/iFIFOMem[54][1] ), .C(\UART_RXFF/iFIFOMem[53][1] ), .D(
\UART_RXFF/iFIFOMem[55][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n92 ) );
notech_mux4 \UART_RXFF/U94 ( .A(\UART_RXFF/iFIFOMem[56][1] ), .B(
\UART_RXFF/iFIFOMem[58][1] ), .C(\UART_RXFF/iFIFOMem[57][1] ), .D(
\UART_RXFF/iFIFOMem[59][1] ), .S0(\UART_RXFF/n53 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n91 ) );
notech_mux4 \UART_RXFF/U93 ( .A(\UART_RXFF/iFIFOMem[60][1] ), .B(
\UART_RXFF/iFIFOMem[62][1] ), .C(\UART_RXFF/iFIFOMem[61][1] ), .D(
\UART_RXFF/iFIFOMem[63][1] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/n61 ), .Z(\UART_RXFF/n90 ) );
notech_mux4 \UART_RXFF/U92 ( .A(\UART_RXFF/n89 ), .B(\UART_RXFF/n79 ), .C(
\UART_RXFF/n84 ), .D(\UART_RXFF/n74 ), .S0(\UART_RXFF/N17 ), .S1(
\UART_RXFF/N16 ), .Z(\UART_RXFF/N133 ) );
notech_mux4 \UART_RXFF/U91 ( .A(\UART_RXFF/n88 ), .B(\UART_RXFF/n86 ), .C(
\UART_RXFF/n87 ), .D(\UART_RXFF/n85 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n89 ) );
notech_mux4 \UART_RXFF/U90 ( .A(\UART_RXFF/iFIFOMem[0][0] ), .B(
\UART_RXFF/iFIFOMem[2][0] ), .C(\UART_RXFF/iFIFOMem[1][0] ), .D(
\UART_RXFF/iFIFOMem[3][0] ), .S0(\UART_RXFF/n52 ), .S1(\UART_RXFF/N12 ), .Z(\UART_RXFF/n88 ) );
notech_mux4 \UART_RXFF/U89 ( .A(\UART_RXFF/iFIFOMem[4][0] ), .B(
\UART_RXFF/iFIFOMem[6][0] ), .C(\UART_RXFF/iFIFOMem[5][0] ), .D(
\UART_RXFF/iFIFOMem[7][0] ), .S0(\UART_RXFF/n52 ), .S1(\UART_RXFF/N12 ), .Z(\UART_RXFF/n87 ) );
notech_mux4 \UART_RXFF/U88 ( .A(\UART_RXFF/iFIFOMem[8][0] ), .B(
\UART_RXFF/iFIFOMem[10][0] ), .C(\UART_RXFF/iFIFOMem[9][0] ), .D(
\UART_RXFF/iFIFOMem[11][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n86 ) );
notech_mux4 \UART_RXFF/U87 ( .A(\UART_RXFF/iFIFOMem[12][0] ), .B(
\UART_RXFF/iFIFOMem[14][0] ), .C(\UART_RXFF/iFIFOMem[13][0] ), .D(
\UART_RXFF/iFIFOMem[15][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n85 ) );
notech_mux4 \UART_RXFF/U86 ( .A(\UART_RXFF/n83 ), .B(\UART_RXFF/n81 ), .C(
\UART_RXFF/n82 ), .D(\UART_RXFF/n80 ), .S0(\UART_RXFF/n50 ), .S1(
\UART_RXFF/n48 ), .Z(\UART_RXFF/n84 ) );
notech_mux4 \UART_RXFF/U85 ( .A(\UART_RXFF/iFIFOMem[16][0] ), .B(
\UART_RXFF/iFIFOMem[18][0] ), .C(\UART_RXFF/iFIFOMem[17][0] ), .D(
\UART_RXFF/iFIFOMem[19][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n83 ) );
notech_mux4 \UART_RXFF/U84 ( .A(\UART_RXFF/iFIFOMem[20][0] ), .B(
\UART_RXFF/iFIFOMem[22][0] ), .C(\UART_RXFF/iFIFOMem[21][0] ), .D(
\UART_RXFF/iFIFOMem[23][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n82 ) );
notech_mux4 \UART_RXFF/U83 ( .A(\UART_RXFF/iFIFOMem[24][0] ), .B(
\UART_RXFF/iFIFOMem[26][0] ), .C(\UART_RXFF/iFIFOMem[25][0] ), .D(
\UART_RXFF/iFIFOMem[27][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n81 ) );
notech_mux4 \UART_RXFF/U82 ( .A(\UART_RXFF/iFIFOMem[28][0] ), .B(
\UART_RXFF/iFIFOMem[30][0] ), .C(\UART_RXFF/iFIFOMem[29][0] ), .D(
\UART_RXFF/iFIFOMem[31][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n80 ) );
notech_mux4 \UART_RXFF/U81 ( .A(\UART_RXFF/n78 ), .B(\UART_RXFF/n76 ), .C(
\UART_RXFF/n77 ), .D(\UART_RXFF/n75 ), .S0(\UART_RXFF/N15 ), .S1(
\UART_RXFF/n47 ), .Z(\UART_RXFF/n79 ) );
notech_mux4 \UART_RXFF/U80 ( .A(\UART_RXFF/iFIFOMem[32][0] ), .B(
\UART_RXFF/iFIFOMem[34][0] ), .C(\UART_RXFF/iFIFOMem[33][0] ), .D(
\UART_RXFF/iFIFOMem[35][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n78 ) );
notech_mux4 \UART_RXFF/U79 ( .A(\UART_RXFF/iFIFOMem[36][0] ), .B(
\UART_RXFF/iFIFOMem[38][0] ), .C(\UART_RXFF/iFIFOMem[37][0] ), .D(
\UART_RXFF/iFIFOMem[39][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n77 ) );
notech_mux4 \UART_RXFF/U78 ( .A(\UART_RXFF/iFIFOMem[40][0] ), .B(
\UART_RXFF/iFIFOMem[42][0] ), .C(\UART_RXFF/iFIFOMem[41][0] ), .D(
\UART_RXFF/iFIFOMem[43][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n76 ) );
notech_mux4 \UART_RXFF/U77 ( .A(\UART_RXFF/iFIFOMem[44][0] ), .B(
\UART_RXFF/iFIFOMem[46][0] ), .C(\UART_RXFF/iFIFOMem[45][0] ), .D(
\UART_RXFF/iFIFOMem[47][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n75 ) );
notech_mux4 \UART_RXFF/U76 ( .A(\UART_RXFF/n73 ), .B(\UART_RXFF/n71 ), .C(
\UART_RXFF/n72 ), .D(\UART_RXFF/n70 ), .S0(\UART_RXFF/n51 ), .S1(
\UART_RXFF/N14 ), .Z(\UART_RXFF/n74 ) );
notech_mux4 \UART_RXFF/U75 ( .A(\UART_RXFF/iFIFOMem[48][0] ), .B(
\UART_RXFF/iFIFOMem[50][0] ), .C(\UART_RXFF/iFIFOMem[49][0] ), .D(
\UART_RXFF/iFIFOMem[51][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n73 ) );
notech_mux4 \UART_RXFF/U74 ( .A(\UART_RXFF/iFIFOMem[52][0] ), .B(
\UART_RXFF/iFIFOMem[54][0] ), .C(\UART_RXFF/iFIFOMem[53][0] ), .D(
\UART_RXFF/iFIFOMem[55][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n72 ) );
notech_mux4 \UART_RXFF/U73 ( .A(\UART_RXFF/iFIFOMem[56][0] ), .B(
\UART_RXFF/iFIFOMem[58][0] ), .C(\UART_RXFF/iFIFOMem[57][0] ), .D(
\UART_RXFF/iFIFOMem[59][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n71 ) );
notech_mux4 \UART_RXFF/U72 ( .A(\UART_RXFF/iFIFOMem[60][0] ), .B(
\UART_RXFF/iFIFOMem[62][0] ), .C(\UART_RXFF/iFIFOMem[61][0] ), .D(
\UART_RXFF/iFIFOMem[63][0] ), .S0(\UART_RXFF/n52 ), .S1(
\UART_RXFF/N12 ), .Z(\UART_RXFF/n70 ) );
notech_inv \UART_RXFF/U71 ( .A(\UART_RXFF/N12 ), .Z(\UART_RXFF/n69 ) );
notech_inv \UART_RXFF/U70 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n68 ) );
notech_inv \UART_RXFF/U69 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n67 ) );
notech_inv \UART_RXFF/U68 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n66 ) );
notech_inv \UART_RXFF/U67 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n65 ) );
notech_inv \UART_RXFF/U66 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n64 ) );
notech_inv \UART_RXFF/U65 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n63 ) );
notech_inv \UART_RXFF/U64 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n62 ) );
notech_inv \UART_RXFF/U63 ( .A(\UART_RXFF/n69 ), .Z(\UART_RXFF/n61 ) );
notech_inv \UART_RXFF/U62 ( .A(\UART_RXFF/N13 ), .Z(\UART_RXFF/n60 ) );
notech_inv \UART_RXFF/U61 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n59 ) );
notech_inv \UART_RXFF/U60 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n58 ) );
notech_inv \UART_RXFF/U59 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n57 ) );
notech_inv \UART_RXFF/U58 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n56 ) );
notech_inv \UART_RXFF/U57 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n55 ) );
notech_inv \UART_RXFF/U56 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n54 ) );
notech_inv \UART_RXFF/U55 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n53 ) );
notech_inv \UART_RXFF/U54 ( .A(\UART_RXFF/n60 ), .Z(\UART_RXFF/n52 ) );
notech_inv \UART_RXFF/U53 ( .A(\UART_RXFF/n49 ), .Z(\UART_RXFF/n51 ) );
notech_inv \UART_RXFF/U52 ( .A(\UART_RXFF/n49 ), .Z(\UART_RXFF/n50 ) );
notech_inv \UART_RXFF/U51 ( .A(\UART_RXFF/N15 ), .Z(\UART_RXFF/n49 ) );
notech_inv \UART_RXFF/U50 ( .A(\UART_RXFF/n46 ), .Z(\UART_RXFF/n48 ) );
notech_inv \UART_RXFF/U49 ( .A(\UART_RXFF/n46 ), .Z(\UART_RXFF/n47 ) );
notech_inv \UART_RXFF/U48 ( .A(\UART_RXFF/N14 ), .Z(\UART_RXFF/n46 ) );
notech_inv \UART_RXFF/U46 ( .A(n535), .Z(\UART_RXFF/n44 ) );
notech_inv \UART_RXFF/U45 ( .A(n535), .Z(\UART_RXFF/n43 ) );
notech_inv \UART_RXFF/U44 ( .A(n535), .Z(\UART_RXFF/n42 ) );
notech_inv \UART_RXFF/U42 ( .A(\UART_RXFF/n37 ), .Z(\UART_RXFF/n40 ) );
notech_inv \UART_RXFF/U41 ( .A(\UART_RXFF/n37 ), .Z(\UART_RXFF/n39 ) );
notech_inv \UART_RXFF/U40 ( .A(\UART_RXFF/n37 ), .Z(\UART_RXFF/n38 ) );
notech_inv \UART_RXFF/U39 ( .A(iRXFIFOD[9]), .Z(\UART_RXFF/n37 ) );
notech_inv \UART_RXFF/U38 ( .A(\UART_RXFF/n33 ), .Z(\UART_RXFF/n36 ) );
notech_inv \UART_RXFF/U37 ( .A(\UART_RXFF/n33 ), .Z(\UART_RXFF/n35 ) );
notech_inv \UART_RXFF/U36 ( .A(\UART_RXFF/n33 ), .Z(\UART_RXFF/n34 ) );
notech_inv \UART_RXFF/U35 ( .A(iRXFIFOD[8]), .Z(\UART_RXFF/n33 ) );
notech_inv \UART_RXFF/U34 ( .A(\UART_RXFF/n29 ), .Z(\UART_RXFF/n32 ) );
notech_inv \UART_RXFF/U33 ( .A(\UART_RXFF/n29 ), .Z(\UART_RXFF/n31 ) );
notech_inv \UART_RXFF/U32 ( .A(\UART_RXFF/n29 ), .Z(\UART_RXFF/n30 ) );
notech_inv \UART_RXFF/U31 ( .A(iRXFIFOD[7]), .Z(\UART_RXFF/n29 ) );
notech_inv \UART_RXFF/U30 ( .A(\UART_RXFF/n25 ), .Z(\UART_RXFF/n28 ) );
notech_inv \UART_RXFF/U29 ( .A(\UART_RXFF/n25 ), .Z(\UART_RXFF/n27 ) );
notech_inv \UART_RXFF/U28 ( .A(\UART_RXFF/n25 ), .Z(\UART_RXFF/n26 ) );
notech_inv \UART_RXFF/U27 ( .A(iRXFIFOD[6]), .Z(\UART_RXFF/n25 ) );
notech_inv \UART_RXFF/U26 ( .A(\UART_RXFF/n21 ), .Z(\UART_RXFF/n24 ) );
notech_inv \UART_RXFF/U25 ( .A(\UART_RXFF/n21 ), .Z(\UART_RXFF/n23 ) );
notech_inv \UART_RXFF/U24 ( .A(\UART_RXFF/n21 ), .Z(\UART_RXFF/n22 ) );
notech_inv \UART_RXFF/U23 ( .A(iRXFIFOD[5]), .Z(\UART_RXFF/n21 ) );
notech_inv \UART_RXFF/U22 ( .A(\UART_RXFF/n17 ), .Z(\UART_RXFF/n20 ) );
notech_inv \UART_RXFF/U21 ( .A(\UART_RXFF/n17 ), .Z(\UART_RXFF/n19 ) );
notech_inv \UART_RXFF/U20 ( .A(\UART_RXFF/n17 ), .Z(\UART_RXFF/n18 ) );
notech_inv \UART_RXFF/U19 ( .A(iRXFIFOD[4]), .Z(\UART_RXFF/n17 ) );
notech_inv \UART_RXFF/U18 ( .A(\UART_RXFF/n13 ), .Z(\UART_RXFF/n16 ) );
notech_inv \UART_RXFF/U17 ( .A(\UART_RXFF/n13 ), .Z(\UART_RXFF/n15 ) );
notech_inv \UART_RXFF/U16 ( .A(\UART_RXFF/n13 ), .Z(\UART_RXFF/n14 ) );
notech_inv \UART_RXFF/U15 ( .A(iRXFIFOD[3]), .Z(\UART_RXFF/n13 ) );
notech_inv \UART_RXFF/U14 ( .A(\UART_RXFF/n9 ), .Z(\UART_RXFF/n12 ) );
notech_inv \UART_RXFF/U13 ( .A(\UART_RXFF/n9 ), .Z(\UART_RXFF/n11 ) );
notech_inv \UART_RXFF/U12 ( .A(\UART_RXFF/n9 ), .Z(\UART_RXFF/n10 ) );
notech_inv \UART_RXFF/U11 ( .A(iRXFIFOD[2]), .Z(\UART_RXFF/n9 ) );
notech_inv \UART_RXFF/U10 ( .A(\UART_RXFF/n5 ), .Z(\UART_RXFF/n8 ) );
notech_inv \UART_RXFF/U9 ( .A(\UART_RXFF/n5 ), .Z(\UART_RXFF/n7 ) );
notech_inv \UART_RXFF/U8 ( .A(\UART_RXFF/n5 ), .Z(\UART_RXFF/n6 ) );
notech_inv \UART_RXFF/U7 ( .A(iRXFIFOD[1]), .Z(\UART_RXFF/n5 ) );
notech_inv \UART_RXFF/U6 ( .A(\UART_RXFF/n1 ), .Z(\UART_RXFF/n4 ) );
notech_inv \UART_RXFF/U5 ( .A(\UART_RXFF/n1 ), .Z(\UART_RXFF/n3 ) );
notech_inv \UART_RXFF/U4 ( .A(\UART_RXFF/n1 ), .Z(\UART_RXFF/n2 ) );
notech_inv \UART_RXFF/U3 ( .A(iRXFIFOD[0]), .Z(\UART_RXFF/n1 ) );
notech_reg \UART_RXFF/iUSAGE_reg[4] ( .D(\UART_RXFF/n1686 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(iRXFIFOUsage[4]) );
notech_reg \UART_RXFF/iUSAGE_reg[3] ( .D(\UART_RXFF/n1687 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(iRXFIFOUsage[3]) );
notech_reg \UART_RXFF/iUSAGE_reg[2] ( .D(\UART_RXFF/n1688 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(iRXFIFOUsage[2]) );
notech_reg \UART_RXFF/iUSAGE_reg[1] ( .D(\UART_RXFF/n1689 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(iRXFIFOUsage[1]) );
notech_reg \UART_RXFF/iUSAGE_reg[5] ( .D(\UART_RXFF/n1685 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(iRXFIFOUsage[5]) );
notech_reg \UART_RXFF/iUSAGE_reg[0] ( .D(\UART_RXFF/n1690 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(\UART_RXFF/USAGE[0] ) );
notech_reg \UART_RXFF/Q_reg[0] ( .D(\UART_RXFF/n959 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[0]) );
notech_reg \UART_RXFF/Q_reg[1] ( .D(\UART_RXFF/n961 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[1]) );
notech_reg \UART_RXFF/Q_reg[2] ( .D(\UART_RXFF/n963 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[2]) );
notech_reg \UART_RXFF/Q_reg[3] ( .D(\UART_RXFF/n965 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[3]) );
notech_reg \UART_RXFF/Q_reg[4] ( .D(\UART_RXFF/n967 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[4]) );
notech_reg \UART_RXFF/Q_reg[5] ( .D(\UART_RXFF/n969 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[5]) );
notech_reg \UART_RXFF/Q_reg[6] ( .D(\UART_RXFF/n971 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[6]) );
notech_reg \UART_RXFF/Q_reg[7] ( .D(\UART_RXFF/n973 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[7]) );
notech_reg \UART_RXFF/Q_reg[8] ( .D(\UART_RXFF/n975 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[8]) );
notech_reg \UART_RXFF/Q_reg[9] ( .D(\UART_RXFF/n977 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[9]) );
notech_reg \UART_RXFF/Q_reg[10] ( .D(\UART_RXFF/n979 ), .CP(CLK), .CD(1'b1),
.Q(iRXFIFOQ[10]) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][0] ( .D(\UART_RXFF/n1691 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][1] ( .D(\UART_RXFF/n1692 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][2] ( .D(\UART_RXFF/n1693 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][3] ( .D(\UART_RXFF/n1694 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][4] ( .D(\UART_RXFF/n1695 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][5] ( .D(\UART_RXFF/n1696 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][6] ( .D(\UART_RXFF/n1697 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][7] ( .D(\UART_RXFF/n1698 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][8] ( .D(\UART_RXFF/n1699 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][9] ( .D(\UART_RXFF/n1700 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[0][10] ( .D(\UART_RXFF/n1701 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[0][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][0] ( .D(\UART_RXFF/n1702 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][1] ( .D(\UART_RXFF/n1703 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][2] ( .D(\UART_RXFF/n1704 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][3] ( .D(\UART_RXFF/n1705 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][4] ( .D(\UART_RXFF/n1706 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][5] ( .D(\UART_RXFF/n1707 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][6] ( .D(\UART_RXFF/n1708 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][7] ( .D(\UART_RXFF/n1709 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][8] ( .D(\UART_RXFF/n1710 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][9] ( .D(\UART_RXFF/n1711 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[1][10] ( .D(\UART_RXFF/n1712 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[1][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][0] ( .D(\UART_RXFF/n1713 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][1] ( .D(\UART_RXFF/n1714 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][2] ( .D(\UART_RXFF/n1715 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][3] ( .D(\UART_RXFF/n1716 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][4] ( .D(\UART_RXFF/n1717 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][5] ( .D(\UART_RXFF/n1718 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][6] ( .D(\UART_RXFF/n1719 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][7] ( .D(\UART_RXFF/n1720 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][8] ( .D(\UART_RXFF/n1721 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][9] ( .D(\UART_RXFF/n1722 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[2][10] ( .D(\UART_RXFF/n1723 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[2][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][0] ( .D(\UART_RXFF/n1724 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][1] ( .D(\UART_RXFF/n1725 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][2] ( .D(\UART_RXFF/n1726 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][3] ( .D(\UART_RXFF/n1727 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][4] ( .D(\UART_RXFF/n1728 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][5] ( .D(\UART_RXFF/n1729 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][6] ( .D(\UART_RXFF/n1730 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][7] ( .D(\UART_RXFF/n1731 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][8] ( .D(\UART_RXFF/n1732 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][9] ( .D(\UART_RXFF/n1733 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[3][10] ( .D(\UART_RXFF/n1734 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[3][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][0] ( .D(\UART_RXFF/n1735 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][1] ( .D(\UART_RXFF/n1736 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][2] ( .D(\UART_RXFF/n1737 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][3] ( .D(\UART_RXFF/n1738 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][4] ( .D(\UART_RXFF/n1739 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][5] ( .D(\UART_RXFF/n1740 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][6] ( .D(\UART_RXFF/n1741 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][7] ( .D(\UART_RXFF/n1742 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][8] ( .D(\UART_RXFF/n1743 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][9] ( .D(\UART_RXFF/n1744 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[4][10] ( .D(\UART_RXFF/n1745 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[4][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][0] ( .D(\UART_RXFF/n1746 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][1] ( .D(\UART_RXFF/n1747 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][2] ( .D(\UART_RXFF/n1748 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][3] ( .D(\UART_RXFF/n1749 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][4] ( .D(\UART_RXFF/n1750 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][5] ( .D(\UART_RXFF/n1751 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][6] ( .D(\UART_RXFF/n1752 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][7] ( .D(\UART_RXFF/n1753 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][8] ( .D(\UART_RXFF/n1754 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][9] ( .D(\UART_RXFF/n1755 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[5][10] ( .D(\UART_RXFF/n1756 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[5][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][0] ( .D(\UART_RXFF/n1757 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][1] ( .D(\UART_RXFF/n1758 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][2] ( .D(\UART_RXFF/n1759 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][3] ( .D(\UART_RXFF/n1760 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][4] ( .D(\UART_RXFF/n1761 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][5] ( .D(\UART_RXFF/n1762 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][6] ( .D(\UART_RXFF/n1763 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][7] ( .D(\UART_RXFF/n1764 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][8] ( .D(\UART_RXFF/n1765 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][9] ( .D(\UART_RXFF/n1766 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[6][10] ( .D(\UART_RXFF/n1767 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[6][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][0] ( .D(\UART_RXFF/n1768 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][1] ( .D(\UART_RXFF/n1769 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][2] ( .D(\UART_RXFF/n1770 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][3] ( .D(\UART_RXFF/n1771 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][4] ( .D(\UART_RXFF/n1772 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][5] ( .D(\UART_RXFF/n1773 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][6] ( .D(\UART_RXFF/n1774 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][7] ( .D(\UART_RXFF/n1775 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][8] ( .D(\UART_RXFF/n1776 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][9] ( .D(\UART_RXFF/n1777 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[7][10] ( .D(\UART_RXFF/n1778 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[7][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][0] ( .D(\UART_RXFF/n1779 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][1] ( .D(\UART_RXFF/n1780 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][2] ( .D(\UART_RXFF/n1781 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][3] ( .D(\UART_RXFF/n1782 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][4] ( .D(\UART_RXFF/n1783 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][5] ( .D(\UART_RXFF/n1784 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][6] ( .D(\UART_RXFF/n1785 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][7] ( .D(\UART_RXFF/n1786 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][8] ( .D(\UART_RXFF/n1787 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][9] ( .D(\UART_RXFF/n1788 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[8][10] ( .D(\UART_RXFF/n1789 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[8][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][0] ( .D(\UART_RXFF/n1790 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][1] ( .D(\UART_RXFF/n1791 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][2] ( .D(\UART_RXFF/n1792 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][3] ( .D(\UART_RXFF/n1793 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][4] ( .D(\UART_RXFF/n1794 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][5] ( .D(\UART_RXFF/n1795 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][6] ( .D(\UART_RXFF/n1796 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][7] ( .D(\UART_RXFF/n1797 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][8] ( .D(\UART_RXFF/n1798 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][9] ( .D(\UART_RXFF/n1799 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[9][10] ( .D(\UART_RXFF/n1800 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[9][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][0] ( .D(\UART_RXFF/n1801 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][1] ( .D(\UART_RXFF/n1802 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][2] ( .D(\UART_RXFF/n1803 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][3] ( .D(\UART_RXFF/n1804 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][4] ( .D(\UART_RXFF/n1805 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][5] ( .D(\UART_RXFF/n1806 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][6] ( .D(\UART_RXFF/n1807 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][7] ( .D(\UART_RXFF/n1808 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][8] ( .D(\UART_RXFF/n1809 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][9] ( .D(\UART_RXFF/n1810 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[10][10] ( .D(\UART_RXFF/n1811 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[10][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][0] ( .D(\UART_RXFF/n1812 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][1] ( .D(\UART_RXFF/n1813 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][2] ( .D(\UART_RXFF/n1814 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][3] ( .D(\UART_RXFF/n1815 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][4] ( .D(\UART_RXFF/n1816 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][5] ( .D(\UART_RXFF/n1817 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][6] ( .D(\UART_RXFF/n1818 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][7] ( .D(\UART_RXFF/n1819 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][8] ( .D(\UART_RXFF/n1820 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][9] ( .D(\UART_RXFF/n1821 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[11][10] ( .D(\UART_RXFF/n1822 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[11][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][0] ( .D(\UART_RXFF/n1823 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][1] ( .D(\UART_RXFF/n1824 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][2] ( .D(\UART_RXFF/n1825 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][3] ( .D(\UART_RXFF/n1826 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][4] ( .D(\UART_RXFF/n1827 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][5] ( .D(\UART_RXFF/n1828 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][6] ( .D(\UART_RXFF/n1829 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][7] ( .D(\UART_RXFF/n1830 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][8] ( .D(\UART_RXFF/n1831 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][9] ( .D(\UART_RXFF/n1832 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[12][10] ( .D(\UART_RXFF/n1833 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[12][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][0] ( .D(\UART_RXFF/n1834 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][1] ( .D(\UART_RXFF/n1835 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][2] ( .D(\UART_RXFF/n1836 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][3] ( .D(\UART_RXFF/n1837 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][4] ( .D(\UART_RXFF/n1838 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][5] ( .D(\UART_RXFF/n1839 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][6] ( .D(\UART_RXFF/n1840 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][7] ( .D(\UART_RXFF/n1841 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][8] ( .D(\UART_RXFF/n1842 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][9] ( .D(\UART_RXFF/n1843 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[13][10] ( .D(\UART_RXFF/n1844 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[13][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][0] ( .D(\UART_RXFF/n1845 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][1] ( .D(\UART_RXFF/n1846 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][2] ( .D(\UART_RXFF/n1847 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][3] ( .D(\UART_RXFF/n1848 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][4] ( .D(\UART_RXFF/n1849 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][5] ( .D(\UART_RXFF/n1850 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][6] ( .D(\UART_RXFF/n1851 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][7] ( .D(\UART_RXFF/n1852 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][8] ( .D(\UART_RXFF/n1853 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][9] ( .D(\UART_RXFF/n1854 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[14][10] ( .D(\UART_RXFF/n1855 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[14][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][0] ( .D(\UART_RXFF/n1856 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][1] ( .D(\UART_RXFF/n1857 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][2] ( .D(\UART_RXFF/n1858 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][3] ( .D(\UART_RXFF/n1859 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][4] ( .D(\UART_RXFF/n1860 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][5] ( .D(\UART_RXFF/n1861 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][6] ( .D(\UART_RXFF/n1862 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][7] ( .D(\UART_RXFF/n1863 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][8] ( .D(\UART_RXFF/n1864 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][9] ( .D(\UART_RXFF/n1865 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[15][10] ( .D(\UART_RXFF/n1866 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[15][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][0] ( .D(\UART_RXFF/n1867 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][1] ( .D(\UART_RXFF/n1868 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][2] ( .D(\UART_RXFF/n1869 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][3] ( .D(\UART_RXFF/n1870 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][4] ( .D(\UART_RXFF/n1871 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][5] ( .D(\UART_RXFF/n1872 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][6] ( .D(\UART_RXFF/n1873 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][7] ( .D(\UART_RXFF/n1874 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][8] ( .D(\UART_RXFF/n1875 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][9] ( .D(\UART_RXFF/n1876 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[16][10] ( .D(\UART_RXFF/n1877 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[16][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][0] ( .D(\UART_RXFF/n1878 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][1] ( .D(\UART_RXFF/n1879 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][2] ( .D(\UART_RXFF/n1880 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][3] ( .D(\UART_RXFF/n1881 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][4] ( .D(\UART_RXFF/n1882 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][5] ( .D(\UART_RXFF/n1883 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][6] ( .D(\UART_RXFF/n1884 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][7] ( .D(\UART_RXFF/n1885 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][8] ( .D(\UART_RXFF/n1886 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][9] ( .D(\UART_RXFF/n1887 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[17][10] ( .D(\UART_RXFF/n1888 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[17][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][0] ( .D(\UART_RXFF/n1889 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][1] ( .D(\UART_RXFF/n1890 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][2] ( .D(\UART_RXFF/n1891 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][3] ( .D(\UART_RXFF/n1892 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][4] ( .D(\UART_RXFF/n1893 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][5] ( .D(\UART_RXFF/n1894 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][6] ( .D(\UART_RXFF/n1895 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][7] ( .D(\UART_RXFF/n1896 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][8] ( .D(\UART_RXFF/n1897 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][9] ( .D(\UART_RXFF/n1898 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[18][10] ( .D(\UART_RXFF/n1899 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[18][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][0] ( .D(\UART_RXFF/n1900 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][1] ( .D(\UART_RXFF/n1901 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][2] ( .D(\UART_RXFF/n1902 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][3] ( .D(\UART_RXFF/n1903 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][4] ( .D(\UART_RXFF/n1904 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][5] ( .D(\UART_RXFF/n1905 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][6] ( .D(\UART_RXFF/n1906 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][7] ( .D(\UART_RXFF/n1907 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][8] ( .D(\UART_RXFF/n1908 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][9] ( .D(\UART_RXFF/n1909 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[19][10] ( .D(\UART_RXFF/n1910 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[19][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][0] ( .D(\UART_RXFF/n1911 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][1] ( .D(\UART_RXFF/n1912 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][2] ( .D(\UART_RXFF/n1913 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][3] ( .D(\UART_RXFF/n1914 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][4] ( .D(\UART_RXFF/n1915 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][5] ( .D(\UART_RXFF/n1916 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][6] ( .D(\UART_RXFF/n1917 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][7] ( .D(\UART_RXFF/n1918 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][8] ( .D(\UART_RXFF/n1919 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][9] ( .D(\UART_RXFF/n1920 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[20][10] ( .D(\UART_RXFF/n1921 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[20][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][0] ( .D(\UART_RXFF/n1922 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][1] ( .D(\UART_RXFF/n1923 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][2] ( .D(\UART_RXFF/n1924 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][3] ( .D(\UART_RXFF/n1925 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][4] ( .D(\UART_RXFF/n1926 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][5] ( .D(\UART_RXFF/n1927 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][6] ( .D(\UART_RXFF/n1928 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][7] ( .D(\UART_RXFF/n1929 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][8] ( .D(\UART_RXFF/n1930 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][9] ( .D(\UART_RXFF/n1931 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[21][10] ( .D(\UART_RXFF/n1932 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[21][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][0] ( .D(\UART_RXFF/n1933 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][1] ( .D(\UART_RXFF/n1934 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][2] ( .D(\UART_RXFF/n1935 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][3] ( .D(\UART_RXFF/n1936 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][4] ( .D(\UART_RXFF/n1937 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][5] ( .D(\UART_RXFF/n1938 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][6] ( .D(\UART_RXFF/n1939 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][7] ( .D(\UART_RXFF/n1940 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][8] ( .D(\UART_RXFF/n1941 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][9] ( .D(\UART_RXFF/n1942 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[22][10] ( .D(\UART_RXFF/n1943 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[22][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][0] ( .D(\UART_RXFF/n1944 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][1] ( .D(\UART_RXFF/n1945 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][2] ( .D(\UART_RXFF/n1946 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][3] ( .D(\UART_RXFF/n1947 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][4] ( .D(\UART_RXFF/n1948 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][5] ( .D(\UART_RXFF/n1949 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][6] ( .D(\UART_RXFF/n1950 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][7] ( .D(\UART_RXFF/n1951 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][8] ( .D(\UART_RXFF/n1952 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][9] ( .D(\UART_RXFF/n1953 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[23][10] ( .D(\UART_RXFF/n1954 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[23][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][0] ( .D(\UART_RXFF/n1955 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][1] ( .D(\UART_RXFF/n1956 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][2] ( .D(\UART_RXFF/n1957 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][3] ( .D(\UART_RXFF/n1958 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][4] ( .D(\UART_RXFF/n1959 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][5] ( .D(\UART_RXFF/n1960 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][6] ( .D(\UART_RXFF/n1961 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][7] ( .D(\UART_RXFF/n1962 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][8] ( .D(\UART_RXFF/n1963 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][9] ( .D(\UART_RXFF/n1964 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[24][10] ( .D(\UART_RXFF/n1965 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[24][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][0] ( .D(\UART_RXFF/n1966 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][1] ( .D(\UART_RXFF/n1967 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][2] ( .D(\UART_RXFF/n1968 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][3] ( .D(\UART_RXFF/n1969 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][4] ( .D(\UART_RXFF/n1970 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][5] ( .D(\UART_RXFF/n1971 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][6] ( .D(\UART_RXFF/n1972 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][7] ( .D(\UART_RXFF/n1973 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][8] ( .D(\UART_RXFF/n1974 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][9] ( .D(\UART_RXFF/n1975 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[25][10] ( .D(\UART_RXFF/n1976 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[25][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][0] ( .D(\UART_RXFF/n1977 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][1] ( .D(\UART_RXFF/n1978 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][2] ( .D(\UART_RXFF/n1979 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][3] ( .D(\UART_RXFF/n1980 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][4] ( .D(\UART_RXFF/n1981 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][5] ( .D(\UART_RXFF/n1982 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][6] ( .D(\UART_RXFF/n1983 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][7] ( .D(\UART_RXFF/n1984 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][8] ( .D(\UART_RXFF/n1985 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][9] ( .D(\UART_RXFF/n1986 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[26][10] ( .D(\UART_RXFF/n1987 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[26][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][0] ( .D(\UART_RXFF/n1988 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][1] ( .D(\UART_RXFF/n1989 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][2] ( .D(\UART_RXFF/n1990 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][3] ( .D(\UART_RXFF/n1991 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][4] ( .D(\UART_RXFF/n1992 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][5] ( .D(\UART_RXFF/n1993 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][6] ( .D(\UART_RXFF/n1994 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][7] ( .D(\UART_RXFF/n1995 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][8] ( .D(\UART_RXFF/n1996 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][9] ( .D(\UART_RXFF/n1997 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[27][10] ( .D(\UART_RXFF/n1998 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[27][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][0] ( .D(\UART_RXFF/n1999 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][1] ( .D(\UART_RXFF/n2000 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][2] ( .D(\UART_RXFF/n2001 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][3] ( .D(\UART_RXFF/n2002 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][4] ( .D(\UART_RXFF/n2003 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][5] ( .D(\UART_RXFF/n2004 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][6] ( .D(\UART_RXFF/n2005 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][7] ( .D(\UART_RXFF/n2006 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][8] ( .D(\UART_RXFF/n2007 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][9] ( .D(\UART_RXFF/n2008 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[28][10] ( .D(\UART_RXFF/n2009 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[28][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][0] ( .D(\UART_RXFF/n2010 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][1] ( .D(\UART_RXFF/n2011 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][2] ( .D(\UART_RXFF/n2012 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][3] ( .D(\UART_RXFF/n2013 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][4] ( .D(\UART_RXFF/n2014 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][5] ( .D(\UART_RXFF/n2015 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][6] ( .D(\UART_RXFF/n2016 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][7] ( .D(\UART_RXFF/n2017 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][8] ( .D(\UART_RXFF/n2018 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][9] ( .D(\UART_RXFF/n2019 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[29][10] ( .D(\UART_RXFF/n2020 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[29][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][0] ( .D(\UART_RXFF/n2021 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][1] ( .D(\UART_RXFF/n2022 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][2] ( .D(\UART_RXFF/n2023 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][3] ( .D(\UART_RXFF/n2024 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][4] ( .D(\UART_RXFF/n2025 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][5] ( .D(\UART_RXFF/n2026 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][6] ( .D(\UART_RXFF/n2027 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][7] ( .D(\UART_RXFF/n2028 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][8] ( .D(\UART_RXFF/n2029 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][9] ( .D(\UART_RXFF/n2030 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[30][10] ( .D(\UART_RXFF/n2031 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[30][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][0] ( .D(\UART_RXFF/n2032 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][1] ( .D(\UART_RXFF/n2033 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][2] ( .D(\UART_RXFF/n2034 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][3] ( .D(\UART_RXFF/n2035 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][4] ( .D(\UART_RXFF/n2036 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][5] ( .D(\UART_RXFF/n2037 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][6] ( .D(\UART_RXFF/n2038 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][7] ( .D(\UART_RXFF/n2039 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][8] ( .D(\UART_RXFF/n2040 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][9] ( .D(\UART_RXFF/n2041 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[31][10] ( .D(\UART_RXFF/n2042 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[31][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][0] ( .D(\UART_RXFF/n2043 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][1] ( .D(\UART_RXFF/n2044 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][2] ( .D(\UART_RXFF/n2045 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][3] ( .D(\UART_RXFF/n2046 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][4] ( .D(\UART_RXFF/n2047 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][5] ( .D(\UART_RXFF/n2048 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][6] ( .D(\UART_RXFF/n2049 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][7] ( .D(\UART_RXFF/n2050 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][8] ( .D(\UART_RXFF/n2051 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][9] ( .D(\UART_RXFF/n2052 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[32][10] ( .D(\UART_RXFF/n2053 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[32][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][0] ( .D(\UART_RXFF/n2054 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][1] ( .D(\UART_RXFF/n2055 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][2] ( .D(\UART_RXFF/n2056 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][3] ( .D(\UART_RXFF/n2057 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][4] ( .D(\UART_RXFF/n2058 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][5] ( .D(\UART_RXFF/n2059 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][6] ( .D(\UART_RXFF/n2060 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][7] ( .D(\UART_RXFF/n2061 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][8] ( .D(\UART_RXFF/n2062 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][9] ( .D(\UART_RXFF/n2063 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[33][10] ( .D(\UART_RXFF/n2064 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[33][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][0] ( .D(\UART_RXFF/n2065 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][1] ( .D(\UART_RXFF/n2066 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][2] ( .D(\UART_RXFF/n2067 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][3] ( .D(\UART_RXFF/n2068 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][4] ( .D(\UART_RXFF/n2069 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][5] ( .D(\UART_RXFF/n2070 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][6] ( .D(\UART_RXFF/n2071 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][7] ( .D(\UART_RXFF/n2072 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][8] ( .D(\UART_RXFF/n2073 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][9] ( .D(\UART_RXFF/n2074 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[34][10] ( .D(\UART_RXFF/n2075 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[34][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][0] ( .D(\UART_RXFF/n2076 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][1] ( .D(\UART_RXFF/n2077 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][2] ( .D(\UART_RXFF/n2078 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][3] ( .D(\UART_RXFF/n2079 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][4] ( .D(\UART_RXFF/n2080 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][5] ( .D(\UART_RXFF/n2081 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][6] ( .D(\UART_RXFF/n2082 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][7] ( .D(\UART_RXFF/n2083 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][8] ( .D(\UART_RXFF/n2084 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][9] ( .D(\UART_RXFF/n2085 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[35][10] ( .D(\UART_RXFF/n2086 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[35][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][0] ( .D(\UART_RXFF/n2087 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][1] ( .D(\UART_RXFF/n2088 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][2] ( .D(\UART_RXFF/n2089 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][3] ( .D(\UART_RXFF/n2090 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][4] ( .D(\UART_RXFF/n2091 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][5] ( .D(\UART_RXFF/n2092 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][6] ( .D(\UART_RXFF/n2093 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][7] ( .D(\UART_RXFF/n2094 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][8] ( .D(\UART_RXFF/n2095 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][9] ( .D(\UART_RXFF/n2096 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[36][10] ( .D(\UART_RXFF/n2097 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[36][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][0] ( .D(\UART_RXFF/n2098 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][1] ( .D(\UART_RXFF/n2099 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][2] ( .D(\UART_RXFF/n2100 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][3] ( .D(\UART_RXFF/n2101 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][4] ( .D(\UART_RXFF/n2102 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][5] ( .D(\UART_RXFF/n2103 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][6] ( .D(\UART_RXFF/n2104 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][7] ( .D(\UART_RXFF/n2105 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][8] ( .D(\UART_RXFF/n2106 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][9] ( .D(\UART_RXFF/n2107 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[37][10] ( .D(\UART_RXFF/n2108 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[37][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][0] ( .D(\UART_RXFF/n2109 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][1] ( .D(\UART_RXFF/n2110 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][2] ( .D(\UART_RXFF/n2111 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][3] ( .D(\UART_RXFF/n2112 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][4] ( .D(\UART_RXFF/n2113 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][5] ( .D(\UART_RXFF/n2114 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][6] ( .D(\UART_RXFF/n2115 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][7] ( .D(\UART_RXFF/n2116 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][8] ( .D(\UART_RXFF/n2117 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][9] ( .D(\UART_RXFF/n2118 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[38][10] ( .D(\UART_RXFF/n2119 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[38][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][0] ( .D(\UART_RXFF/n2120 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][1] ( .D(\UART_RXFF/n2121 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][2] ( .D(\UART_RXFF/n2122 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][3] ( .D(\UART_RXFF/n2123 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][4] ( .D(\UART_RXFF/n2124 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][5] ( .D(\UART_RXFF/n2125 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][6] ( .D(\UART_RXFF/n2126 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][7] ( .D(\UART_RXFF/n2127 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][8] ( .D(\UART_RXFF/n2128 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][9] ( .D(\UART_RXFF/n2129 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[39][10] ( .D(\UART_RXFF/n2130 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[39][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][0] ( .D(\UART_RXFF/n2131 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][1] ( .D(\UART_RXFF/n2132 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][2] ( .D(\UART_RXFF/n2133 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][3] ( .D(\UART_RXFF/n2134 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][4] ( .D(\UART_RXFF/n2135 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][5] ( .D(\UART_RXFF/n2136 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][6] ( .D(\UART_RXFF/n2137 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][7] ( .D(\UART_RXFF/n2138 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][8] ( .D(\UART_RXFF/n2139 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][9] ( .D(\UART_RXFF/n2140 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[40][10] ( .D(\UART_RXFF/n2141 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[40][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][0] ( .D(\UART_RXFF/n2142 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][1] ( .D(\UART_RXFF/n2143 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][2] ( .D(\UART_RXFF/n2144 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][3] ( .D(\UART_RXFF/n2145 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][4] ( .D(\UART_RXFF/n2146 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][5] ( .D(\UART_RXFF/n2147 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][6] ( .D(\UART_RXFF/n2148 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][7] ( .D(\UART_RXFF/n2149 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][8] ( .D(\UART_RXFF/n2150 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][9] ( .D(\UART_RXFF/n2151 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[41][10] ( .D(\UART_RXFF/n2152 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[41][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][0] ( .D(\UART_RXFF/n2153 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][1] ( .D(\UART_RXFF/n2154 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][2] ( .D(\UART_RXFF/n2155 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][3] ( .D(\UART_RXFF/n2156 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][4] ( .D(\UART_RXFF/n2157 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][5] ( .D(\UART_RXFF/n2158 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][6] ( .D(\UART_RXFF/n2159 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][7] ( .D(\UART_RXFF/n2160 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][8] ( .D(\UART_RXFF/n2161 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][9] ( .D(\UART_RXFF/n2162 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[42][10] ( .D(\UART_RXFF/n2163 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[42][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][0] ( .D(\UART_RXFF/n2164 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][1] ( .D(\UART_RXFF/n2165 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][2] ( .D(\UART_RXFF/n2166 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][3] ( .D(\UART_RXFF/n2167 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][4] ( .D(\UART_RXFF/n2168 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][5] ( .D(\UART_RXFF/n2169 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][6] ( .D(\UART_RXFF/n2170 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][7] ( .D(\UART_RXFF/n2171 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][8] ( .D(\UART_RXFF/n2172 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][9] ( .D(\UART_RXFF/n2173 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[43][10] ( .D(\UART_RXFF/n2174 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[43][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][0] ( .D(\UART_RXFF/n2175 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][1] ( .D(\UART_RXFF/n2176 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][2] ( .D(\UART_RXFF/n2177 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][3] ( .D(\UART_RXFF/n2178 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][4] ( .D(\UART_RXFF/n2179 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][5] ( .D(\UART_RXFF/n2180 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][6] ( .D(\UART_RXFF/n2181 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][7] ( .D(\UART_RXFF/n2182 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][8] ( .D(\UART_RXFF/n2183 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][9] ( .D(\UART_RXFF/n2184 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[44][10] ( .D(\UART_RXFF/n2185 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[44][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][0] ( .D(\UART_RXFF/n2186 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][1] ( .D(\UART_RXFF/n2187 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][2] ( .D(\UART_RXFF/n2188 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][3] ( .D(\UART_RXFF/n2189 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][4] ( .D(\UART_RXFF/n2190 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][5] ( .D(\UART_RXFF/n2191 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][6] ( .D(\UART_RXFF/n2192 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][7] ( .D(\UART_RXFF/n2193 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][8] ( .D(\UART_RXFF/n2194 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][9] ( .D(\UART_RXFF/n2195 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[45][10] ( .D(\UART_RXFF/n2196 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[45][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][0] ( .D(\UART_RXFF/n2197 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][1] ( .D(\UART_RXFF/n2198 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][2] ( .D(\UART_RXFF/n2199 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][3] ( .D(\UART_RXFF/n2200 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][4] ( .D(\UART_RXFF/n2201 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][5] ( .D(\UART_RXFF/n2202 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][6] ( .D(\UART_RXFF/n2203 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][7] ( .D(\UART_RXFF/n2204 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][8] ( .D(\UART_RXFF/n2205 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][9] ( .D(\UART_RXFF/n2206 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[46][10] ( .D(\UART_RXFF/n2207 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[46][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][0] ( .D(\UART_RXFF/n2208 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][1] ( .D(\UART_RXFF/n2209 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][2] ( .D(\UART_RXFF/n2210 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][3] ( .D(\UART_RXFF/n2211 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][4] ( .D(\UART_RXFF/n2212 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][5] ( .D(\UART_RXFF/n2213 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][6] ( .D(\UART_RXFF/n2214 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][7] ( .D(\UART_RXFF/n2215 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][8] ( .D(\UART_RXFF/n2216 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][9] ( .D(\UART_RXFF/n2217 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[47][10] ( .D(\UART_RXFF/n2218 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[47][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][0] ( .D(\UART_RXFF/n2219 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][1] ( .D(\UART_RXFF/n2220 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][2] ( .D(\UART_RXFF/n2221 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][3] ( .D(\UART_RXFF/n2222 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][4] ( .D(\UART_RXFF/n2223 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][5] ( .D(\UART_RXFF/n2224 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][6] ( .D(\UART_RXFF/n2225 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][7] ( .D(\UART_RXFF/n2226 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][8] ( .D(\UART_RXFF/n2227 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][9] ( .D(\UART_RXFF/n2228 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[48][10] ( .D(\UART_RXFF/n2229 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[48][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][0] ( .D(\UART_RXFF/n2230 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][1] ( .D(\UART_RXFF/n2231 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][2] ( .D(\UART_RXFF/n2232 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][3] ( .D(\UART_RXFF/n2233 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][4] ( .D(\UART_RXFF/n2234 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][5] ( .D(\UART_RXFF/n2235 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][6] ( .D(\UART_RXFF/n2236 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][7] ( .D(\UART_RXFF/n2237 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][8] ( .D(\UART_RXFF/n2238 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][9] ( .D(\UART_RXFF/n2239 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[49][10] ( .D(\UART_RXFF/n2240 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[49][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][0] ( .D(\UART_RXFF/n2241 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][1] ( .D(\UART_RXFF/n2242 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][2] ( .D(\UART_RXFF/n2243 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][3] ( .D(\UART_RXFF/n2244 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][4] ( .D(\UART_RXFF/n2245 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][5] ( .D(\UART_RXFF/n2246 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][6] ( .D(\UART_RXFF/n2247 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][7] ( .D(\UART_RXFF/n2248 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][8] ( .D(\UART_RXFF/n2249 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][9] ( .D(\UART_RXFF/n2250 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[50][10] ( .D(\UART_RXFF/n2251 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[50][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][0] ( .D(\UART_RXFF/n2252 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][1] ( .D(\UART_RXFF/n2253 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][2] ( .D(\UART_RXFF/n2254 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][3] ( .D(\UART_RXFF/n2255 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][4] ( .D(\UART_RXFF/n2256 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][5] ( .D(\UART_RXFF/n2257 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][6] ( .D(\UART_RXFF/n2258 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][7] ( .D(\UART_RXFF/n2259 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][8] ( .D(\UART_RXFF/n2260 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][9] ( .D(\UART_RXFF/n2261 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[51][10] ( .D(\UART_RXFF/n2262 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[51][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][0] ( .D(\UART_RXFF/n2263 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][1] ( .D(\UART_RXFF/n2264 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][2] ( .D(\UART_RXFF/n2265 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][3] ( .D(\UART_RXFF/n2266 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][4] ( .D(\UART_RXFF/n2267 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][5] ( .D(\UART_RXFF/n2268 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][6] ( .D(\UART_RXFF/n2269 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][7] ( .D(\UART_RXFF/n2270 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][8] ( .D(\UART_RXFF/n2271 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][9] ( .D(\UART_RXFF/n2272 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[52][10] ( .D(\UART_RXFF/n2273 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[52][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][0] ( .D(\UART_RXFF/n2274 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][1] ( .D(\UART_RXFF/n2275 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][2] ( .D(\UART_RXFF/n2276 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][3] ( .D(\UART_RXFF/n2277 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][4] ( .D(\UART_RXFF/n2278 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][5] ( .D(\UART_RXFF/n2279 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][6] ( .D(\UART_RXFF/n2280 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][7] ( .D(\UART_RXFF/n2281 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][8] ( .D(\UART_RXFF/n2282 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][9] ( .D(\UART_RXFF/n2283 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[53][10] ( .D(\UART_RXFF/n2284 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[53][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][0] ( .D(\UART_RXFF/n2285 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][1] ( .D(\UART_RXFF/n2286 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][2] ( .D(\UART_RXFF/n2287 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][3] ( .D(\UART_RXFF/n2288 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][4] ( .D(\UART_RXFF/n2289 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][5] ( .D(\UART_RXFF/n2290 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][6] ( .D(\UART_RXFF/n2291 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][7] ( .D(\UART_RXFF/n2292 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][8] ( .D(\UART_RXFF/n2293 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][9] ( .D(\UART_RXFF/n2294 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[54][10] ( .D(\UART_RXFF/n2295 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[54][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][0] ( .D(\UART_RXFF/n2296 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][1] ( .D(\UART_RXFF/n2297 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][2] ( .D(\UART_RXFF/n2298 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][3] ( .D(\UART_RXFF/n2299 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][4] ( .D(\UART_RXFF/n2300 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][5] ( .D(\UART_RXFF/n2301 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][6] ( .D(\UART_RXFF/n2302 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][7] ( .D(\UART_RXFF/n2303 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][8] ( .D(\UART_RXFF/n2304 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][9] ( .D(\UART_RXFF/n2305 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[55][10] ( .D(\UART_RXFF/n2306 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[55][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][0] ( .D(\UART_RXFF/n2307 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][1] ( .D(\UART_RXFF/n2308 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][2] ( .D(\UART_RXFF/n2309 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][3] ( .D(\UART_RXFF/n2310 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][4] ( .D(\UART_RXFF/n2311 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][5] ( .D(\UART_RXFF/n2312 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][6] ( .D(\UART_RXFF/n2313 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][7] ( .D(\UART_RXFF/n2314 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][8] ( .D(\UART_RXFF/n2315 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][9] ( .D(\UART_RXFF/n2316 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[56][10] ( .D(\UART_RXFF/n2317 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[56][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][0] ( .D(\UART_RXFF/n2318 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][1] ( .D(\UART_RXFF/n2319 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][2] ( .D(\UART_RXFF/n2320 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][3] ( .D(\UART_RXFF/n2321 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][4] ( .D(\UART_RXFF/n2322 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][5] ( .D(\UART_RXFF/n2323 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][6] ( .D(\UART_RXFF/n2324 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][7] ( .D(\UART_RXFF/n2325 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][8] ( .D(\UART_RXFF/n2326 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][9] ( .D(\UART_RXFF/n2327 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[57][10] ( .D(\UART_RXFF/n2328 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[57][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][0] ( .D(\UART_RXFF/n2329 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][1] ( .D(\UART_RXFF/n2330 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][2] ( .D(\UART_RXFF/n2331 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][3] ( .D(\UART_RXFF/n2332 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][4] ( .D(\UART_RXFF/n2333 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][5] ( .D(\UART_RXFF/n2334 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][6] ( .D(\UART_RXFF/n2335 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][7] ( .D(\UART_RXFF/n2336 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][8] ( .D(\UART_RXFF/n2337 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][9] ( .D(\UART_RXFF/n2338 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[58][10] ( .D(\UART_RXFF/n2339 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[58][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][0] ( .D(\UART_RXFF/n2340 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][1] ( .D(\UART_RXFF/n2341 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][2] ( .D(\UART_RXFF/n2342 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][3] ( .D(\UART_RXFF/n2343 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][4] ( .D(\UART_RXFF/n2344 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][5] ( .D(\UART_RXFF/n2345 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][6] ( .D(\UART_RXFF/n2346 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][7] ( .D(\UART_RXFF/n2347 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][8] ( .D(\UART_RXFF/n2348 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][9] ( .D(\UART_RXFF/n2349 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[59][10] ( .D(\UART_RXFF/n2350 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[59][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][0] ( .D(\UART_RXFF/n2351 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][1] ( .D(\UART_RXFF/n2352 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][2] ( .D(\UART_RXFF/n2353 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][3] ( .D(\UART_RXFF/n2354 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][4] ( .D(\UART_RXFF/n2355 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][5] ( .D(\UART_RXFF/n2356 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][6] ( .D(\UART_RXFF/n2357 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][7] ( .D(\UART_RXFF/n2358 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][8] ( .D(\UART_RXFF/n2359 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][9] ( .D(\UART_RXFF/n2360 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[60][10] ( .D(\UART_RXFF/n2361 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[60][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][0] ( .D(\UART_RXFF/n2362 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][1] ( .D(\UART_RXFF/n2363 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][2] ( .D(\UART_RXFF/n2364 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][3] ( .D(\UART_RXFF/n2365 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][4] ( .D(\UART_RXFF/n2366 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][5] ( .D(\UART_RXFF/n2367 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][6] ( .D(\UART_RXFF/n2368 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][7] ( .D(\UART_RXFF/n2369 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][8] ( .D(\UART_RXFF/n2370 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][9] ( .D(\UART_RXFF/n2371 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[61][10] ( .D(\UART_RXFF/n2372 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[61][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][0] ( .D(\UART_RXFF/n2373 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][1] ( .D(\UART_RXFF/n2374 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][2] ( .D(\UART_RXFF/n2375 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][3] ( .D(\UART_RXFF/n2376 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][4] ( .D(\UART_RXFF/n2377 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][5] ( .D(\UART_RXFF/n2378 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][6] ( .D(\UART_RXFF/n2379 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][7] ( .D(\UART_RXFF/n2380 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][8] ( .D(\UART_RXFF/n2381 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][9] ( .D(\UART_RXFF/n2382 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[62][10] ( .D(\UART_RXFF/n2383 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[62][10] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][0] ( .D(\UART_RXFF/n2384 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][0] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][1] ( .D(\UART_RXFF/n2385 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][1] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][2] ( .D(\UART_RXFF/n2386 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][2] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][3] ( .D(\UART_RXFF/n2387 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][3] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][4] ( .D(\UART_RXFF/n2388 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][4] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][5] ( .D(\UART_RXFF/n2389 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][5] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][6] ( .D(\UART_RXFF/n2390 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][6] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][7] ( .D(\UART_RXFF/n2391 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][7] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][8] ( .D(\UART_RXFF/n2392 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][8] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][9] ( .D(\UART_RXFF/n2393 ), .CP(CLK),
.CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][9] ) );
notech_reg \UART_RXFF/iFIFOMem_reg[63][10] ( .D(\UART_RXFF/n2394 ), .CP(CLK), .CD(1'b1), .Q(\UART_RXFF/iFIFOMem[63][10] ) );
notech_reg \UART_RXFF/iWRAddr_reg[5] ( .D(\UART_RXFF/n2401 ), .CP(CLK),
.CD(\UART_IS_DSR/n1 ), .Q(\UART_RXFF/iWRAddr[5] ) );
notech_reg \UART_RXFF/iWRAddr_reg[4] ( .D(\UART_RXFF/n2402 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_RXFF/iWRAddr[4] ) );
notech_reg \UART_RXFF/iWRAddr_reg[3] ( .D(\UART_RXFF/n2403 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_RXFF/iWRAddr[3] ) );
notech_reg \UART_RXFF/iWRAddr_reg[2] ( .D(\UART_RXFF/n2404 ), .CP(CLK),
.CD(\UART_IS_SIN/n1 ), .Q(\UART_RXFF/iWRAddr[2] ) );
notech_reg \UART_RXFF/iWRAddr_reg[1] ( .D(\UART_RXFF/n2405 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_RXFF/iWRAddr[1] ) );
notech_reg \UART_RXFF/iWRAddr_reg[0] ( .D(\UART_RXFF/n2406 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_RXFF/iWRAddr[0] ) );
notech_reg \UART_RXFF/iWRAddr_reg[6] ( .D(\UART_RXFF/n2407 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_RXFF/iWRAddr[6] ) );
notech_reg \UART_RXFF/iRDAddr_reg[5] ( .D(\UART_RXFF/n2395 ), .CP(CLK),
.CD(\UART_IS_DSR/n1 ), .Q(\UART_RXFF/N17 ) );
notech_reg \UART_RXFF/iRDAddr_reg[4] ( .D(\UART_RXFF/n2396 ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_RXFF/N16 ) );
notech_reg \UART_RXFF/iRDAddr_reg[3] ( .D(\UART_RXFF/n2397 ), .CP(CLK),
.CD(\UART_IS_SIN/n1 ), .Q(\UART_RXFF/N15 ) );
notech_reg \UART_RXFF/iRDAddr_reg[2] ( .D(\UART_RXFF/n2398 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_RXFF/N14 ) );
notech_reg \UART_RXFF/iRDAddr_reg[1] ( .D(\UART_RXFF/n2399 ), .CP(CLK),
.CD(\UART_IS_DSR/n1 ), .Q(\UART_RXFF/N13 ) );
notech_reg \UART_RXFF/iRDAddr_reg[6] ( .D(\UART_RXFF/n2400 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_RXFF/iRDAddr[6] ) );
notech_reg_set \UART_RXFF/iEMPTY_reg ( .D(\UART_RXFF/N56 ), .CP(CLK), .SD(
\UART_IS_DCD/n1 ), .Q(iRXFIFOEmpty) );
notech_reg \UART_RXFF/iRDAddr_reg[0] ( .D(\UART_RXFF/n2408 ), .CP(CLK),
.CD(\UART_IS_RI/n1 ), .Q(\UART_RXFF/N12 ) );
notech_xor2 \UART_RXFF/add_73/U1 ( .A(\UART_RXFF/add_73/carry [6]), .B(
\UART_RXFF/iWRAddr[6] ), .Z(\UART_RXFF/N30 ) );
notech_ha2 \UART_RXFF/add_73/U1_1_1 ( .A(\UART_RXFF/iWRAddr[1] ), .B(
\UART_RXFF/iWRAddr[0] ), .CO(\UART_RXFF/add_73/carry [2]), .Z(
\UART_RXFF/N25 ) );
notech_ha2 \UART_RXFF/add_73/U1_1_2 ( .A(\UART_RXFF/iWRAddr[2] ), .B(
\UART_RXFF/add_73/carry [2]), .CO(\UART_RXFF/add_73/carry [3]), .Z(
\UART_RXFF/N26 ) );
notech_ha2 \UART_RXFF/add_73/U1_1_3 ( .A(\UART_RXFF/iWRAddr[3] ), .B(
\UART_RXFF/add_73/carry [3]), .CO(\UART_RXFF/add_73/carry [4]), .Z(
\UART_RXFF/N27 ) );
notech_ha2 \UART_RXFF/add_73/U1_1_4 ( .A(\UART_RXFF/iWRAddr[4] ), .B(
\UART_RXFF/add_73/carry [4]), .CO(\UART_RXFF/add_73/carry [5]), .Z(
\UART_RXFF/N28 ) );
notech_ha2 \UART_RXFF/add_73/U1_1_5 ( .A(\UART_RXFF/iWRAddr[5] ), .B(
\UART_RXFF/add_73/carry [5]), .CO(\UART_RXFF/add_73/carry [6]), .Z(
\UART_RXFF/N29 ) );
notech_xor2 \UART_RXFF/add_77/U1 ( .A(\UART_RXFF/add_77/carry [6]), .B(
\UART_RXFF/iRDAddr[6] ), .Z(\UART_RXFF/N38 ) );
notech_ha2 \UART_RXFF/add_77/U1_1_1 ( .A(\UART_RXFF/n52 ), .B(
\UART_RXFF/N12 ), .CO(\UART_RXFF/add_77/carry [2]), .Z(\UART_RXFF/N33 ) );
notech_ha2 \UART_RXFF/add_77/U1_1_2 ( .A(\UART_RXFF/n48 ), .B(
\UART_RXFF/add_77/carry [2]), .CO(\UART_RXFF/add_77/carry [3]), .Z(
\UART_RXFF/N34 ) );
notech_ha2 \UART_RXFF/add_77/U1_1_3 ( .A(\UART_RXFF/n50 ), .B(
\UART_RXFF/add_77/carry [3]), .CO(\UART_RXFF/add_77/carry [4]), .Z(
\UART_RXFF/N35 ) );
notech_ha2 \UART_RXFF/add_77/U1_1_4 ( .A(\UART_RXFF/N16 ), .B(
\UART_RXFF/add_77/carry [4]), .CO(\UART_RXFF/add_77/carry [5]), .Z(
\UART_RXFF/N36 ) );
notech_ha2 \UART_RXFF/add_77/U1_1_5 ( .A(\UART_RXFF/N17 ), .B(
\UART_RXFF/add_77/carry [5]), .CO(\UART_RXFF/add_77/carry [6]), .Z(
\UART_RXFF/N37 ) );
notech_inv \UART_TX/U95 ( .A(\UART_TX/CState[1] ), .Z(\UART_TX/n28 ) );
notech_nor2 \UART_TX/U94 ( .A(\UART_TX/n28 ), .B(\UART_TX/CState[2] ), .Z(
\UART_TX/n15 ) );
notech_nand2 \UART_TX/U93 ( .A(\UART_TX/n15 ), .B(\UART_TX/CState[0] ), .Z(
\UART_TX/n40 ) );
notech_inv \UART_TX/U92 ( .A(\UART_TX/CState[3] ), .Z(\UART_TX/n20 ) );
notech_or2 \UART_TX/U91 ( .A(\UART_TX/n40 ), .B(\UART_TX/n20 ), .Z(
\UART_TX/n25 ) );
notech_nor2 \UART_TX/U90 ( .A(\UART_TX/iLast ), .B(\UART_TX/n25 ), .Z(
\UART_TX/N127 ) );
notech_inv \UART_TX/U89 ( .A(\UART_TX/CState[2] ), .Z(\UART_TX/n21 ) );
notech_inv \UART_TX/U88 ( .A(iTSR[1]), .Z(\UART_TX/n83 ) );
notech_ao4 \UART_TX/U87 ( .A(\UART_TX/n20 ), .B(\UART_TX/n21 ), .C(
\UART_TX/n40 ), .D(\UART_TX/n83 ), .Z(\UART_TX/n59 ) );
notech_nor2 \UART_TX/U86 ( .A(\UART_TX/n21 ), .B(\UART_TX/CState[3] ), .Z(
\UART_TX/n43 ) );
notech_and2 \UART_TX/U85 ( .A(\UART_TX/n43 ), .B(\UART_TX/n28 ), .Z(
\UART_TX/n44 ) );
notech_nand2 \UART_TX/U84 ( .A(\UART_TX/n44 ), .B(iTSR[3]), .Z(
\UART_TX/n67 ) );
notech_inv \UART_TX/U83 ( .A(iTSR[6]), .Z(\UART_TX/n64 ) );
notech_fa2 \UART_TX/U82 ( .A(iTSR[4]), .B(iTSR[3]), .CI(iTSR[2]), .Z(
\UART_TX/n84 ) );
notech_fa2 \UART_TX/U81 ( .A(\UART_TX/n83 ), .B(\UART_TX/n84 ), .CI(iTSR[0]), .Z(\UART_TX/n81 ) );
notech_xor2 \UART_TX/U80 ( .A(\UART_TX/n81 ), .B(iTSR[5]), .Z(\UART_TX/n80 ) );
notech_nand2 \UART_TX/U79 ( .A(iTSR[7]), .B(iLCR[0]), .Z(\UART_TX/n82 ) );
notech_fa2 \UART_TX/U78 ( .A(\UART_TX/n64 ), .B(\UART_TX/n80 ), .CI(
\UART_TX/n82 ), .Z(\UART_TX/n78 ) );
notech_inv \UART_TX/U77 ( .A(iLCR[0]), .Z(\UART_TX/n24 ) );
notech_mux2 \UART_TX/U76 ( .A(\UART_TX/n80 ), .B(\UART_TX/n81 ), .S(
\UART_TX/n24 ), .Z(\UART_TX/n79 ) );
notech_inv \UART_TX/U75 ( .A(iLCR[1]), .Z(\UART_TX/n37 ) );
notech_mux2 \UART_TX/U74 ( .A(\UART_TX/n78 ), .B(\UART_TX/n79 ), .S(
\UART_TX/n37 ), .Z(\UART_TX/n77 ) );
notech_nor2 \UART_TX/U73 ( .A(iLCR[5]), .B(\UART_TX/n77 ), .Z(\UART_TX/n76 ) );
notech_xor2 \UART_TX/U72 ( .A(iLCR[4]), .B(\UART_TX/n76 ), .Z(\UART_TX/n74 ) );
notech_inv \UART_TX/U71 ( .A(\UART_TX/n43 ), .Z(\UART_TX/n18 ) );
notech_inv \UART_TX/U70 ( .A(iTSR[4]), .Z(\UART_TX/n75 ) );
notech_ao4 \UART_TX/U69 ( .A(\UART_TX/n20 ), .B(\UART_TX/n74 ), .C(
\UART_TX/n18 ), .D(\UART_TX/n75 ), .Z(\UART_TX/n73 ) );
notech_or2 \UART_TX/U68 ( .A(\UART_TX/n73 ), .B(\UART_TX/n28 ), .Z(
\UART_TX/n69 ) );
notech_or2 \UART_TX/U67 ( .A(\UART_TX/n28 ), .B(iTSR[0]), .Z(\UART_TX/n72 )
);
notech_nao3 \UART_TX/U66 ( .C(\UART_TX/CState[2] ), .A(\UART_TX/n20 ), .B(
\UART_TX/n72 ), .Z(\UART_TX/n70 ) );
notech_nand2 \UART_TX/U65 ( .A(\UART_TX/n44 ), .B(iTSR[2]), .Z(
\UART_TX/n71 ) );
notech_and3 \UART_TX/U64 ( .A(\UART_TX/n69 ), .B(\UART_TX/n70 ), .C(
\UART_TX/n71 ), .Z(\UART_TX/n68 ) );
notech_inv \UART_TX/U63 ( .A(\UART_TX/CState[0] ), .Z(\UART_TX/n5 ) );
notech_mux2 \UART_TX/U62 ( .A(\UART_TX/n67 ), .B(\UART_TX/n68 ), .S(
\UART_TX/n5 ), .Z(\UART_TX/n60 ) );
notech_and3 \UART_TX/U61 ( .A(\UART_TX/n28 ), .B(\UART_TX/n21 ), .C(
\UART_TX/CState[3] ), .Z(\UART_TX/n66 ) );
notech_and2 \UART_TX/U60 ( .A(\UART_TX/n66 ), .B(\UART_TX/CState[0] ), .Z(
\UART_TX/n51 ) );
notech_nand2 \UART_TX/U59 ( .A(\UART_TX/n51 ), .B(iTSR[7]), .Z(
\UART_TX/n62 ) );
notech_and2 \UART_TX/U58 ( .A(\UART_TX/n66 ), .B(\UART_TX/n5 ), .Z(
\UART_TX/n22 ) );
notech_inv \UART_TX/U57 ( .A(\UART_TX/n22 ), .Z(\UART_TX/n50 ) );
notech_nao3 \UART_TX/U56 ( .C(\UART_TX/n18 ), .A(\UART_TX/CState[1] ), .B(
\UART_TX/CState[0] ), .Z(\UART_TX/n36 ) );
notech_inv \UART_TX/U55 ( .A(iTSR[5]), .Z(\UART_TX/n65 ) );
notech_ao4 \UART_TX/U54 ( .A(\UART_TX/n50 ), .B(\UART_TX/n64 ), .C(
\UART_TX/n36 ), .D(\UART_TX/n65 ), .Z(\UART_TX/n63 ) );
notech_and3 \UART_TX/U53 ( .A(\UART_TX/n62 ), .B(\UART_TX/n63 ), .C(
\UART_TX/n25 ), .Z(\UART_TX/n61 ) );
notech_and3 \UART_TX/U52 ( .A(\UART_TX/n59 ), .B(\UART_TX/n60 ), .C(
\UART_TX/n61 ), .Z(\UART_TX/n58 ) );
notech_nor2 \UART_TX/U51 ( .A(iLCR[6]), .B(\UART_TX/n58 ), .Z(iSOUT) );
notech_and4 \UART_TX/U50 ( .A(\UART_TX/n37 ), .B(\UART_TX/n24 ), .C(
\UART_TX/n28 ), .D(\UART_TX/n5 ), .Z(\UART_TX/n57 ) );
notech_and4 \UART_TX/U49 ( .A(\UART_TX/CState[2] ), .B(\UART_TX/CState[3] ),
.C(iLCR[2]), .D(\UART_TX/n57 ), .Z(\UART_TX/n56 ) );
notech_inv \UART_TX/U48 ( .A(\UART_TX/iTx2 ), .Z(\UART_TX/n53 ) );
notech_nor2 \UART_TX/U47 ( .A(\UART_TX/n56 ), .B(\UART_TX/n53 ), .Z(
\UART_TX/n54 ) );
notech_nor2 \UART_TX/U45 ( .A(\UART_TX/n54 ), .B(\UART_IF_RI/n3 ), .Z(
\UART_TX/n29 ) );
notech_inv \UART_TX/U44 ( .A(\UART_TX/n29 ), .Z(\UART_TX/n6 ) );
notech_or2 \UART_TX/U43 ( .A(\UART_TX/n53 ), .B(iBaudtick2x), .Z(
\UART_TX/n52 ) );
notech_nand2 \UART_TX/U42 ( .A(\UART_TX/n6 ), .B(\UART_TX/n52 ), .Z(
\UART_TX/n87 ) );
notech_or4 \UART_TX/U41 ( .A(\UART_TX/n28 ), .B(\UART_TX/n18 ), .C(iLCR[1]),
.D(iLCR[0]), .Z(\UART_TX/n49 ) );
notech_inv \UART_TX/U40 ( .A(\UART_TX/n51 ), .Z(\UART_TX/n3 ) );
notech_and4 \UART_TX/U39 ( .A(\UART_TX/n49 ), .B(\UART_TX/n36 ), .C(
\UART_TX/n50 ), .D(\UART_TX/n3 ), .Z(\UART_TX/n45 ) );
notech_or2 \UART_TX/U38 ( .A(\UART_TX/n5 ), .B(iLCR[2]), .Z(\UART_TX/n48 )
);
notech_nand2 \UART_TX/U37 ( .A(\UART_TX/n15 ), .B(\UART_TX/n48 ), .Z(
\UART_TX/n47 ) );
notech_and2 \UART_TX/U36 ( .A(\UART_TX/n29 ), .B(\UART_TX/n47 ), .Z(
\UART_TX/n46 ) );
notech_nao4 \UART_TX/U35 ( .A(\UART_TX/n45 ), .B(\UART_TX/n6 ), .C(
\UART_TX/n46 ), .D(\UART_TX/n20 ), .Z(\UART_TX/n88 ) );
notech_inv \UART_TX/U34 ( .A(\UART_TX/n44 ), .Z(\UART_TX/n13 ) );
notech_nand2 \UART_TX/U33 ( .A(\UART_TX/n37 ), .B(\UART_TX/n24 ), .Z(
\UART_TX/n42 ) );
notech_nao3 \UART_TX/U32 ( .C(\UART_TX/CState[0] ), .A(\UART_TX/n42 ), .B(
\UART_TX/n43 ), .Z(\UART_TX/n8 ) );
notech_nor2 \UART_TX/U31 ( .A(\UART_TX/n20 ), .B(iLCR[2]), .Z(\UART_TX/n41 ) );
notech_or2 \UART_TX/U30 ( .A(\UART_TX/n40 ), .B(\UART_TX/n41 ), .Z(
\UART_TX/n39 ) );
notech_nand3 \UART_TX/U29 ( .A(\UART_TX/n13 ), .B(\UART_TX/n8 ), .C(
\UART_TX/n39 ), .Z(\UART_TX/n38 ) );
notech_mux2 \UART_TX/U28 ( .A(\UART_TX/n38 ), .B(\UART_TX/CState[2] ), .S(
\UART_TX/n6 ), .Z(\UART_TX/n89 ) );
notech_nao3 \UART_TX/U27 ( .C(\UART_TX/n37 ), .A(\UART_TX/n24 ), .B(
\UART_TX/n22 ), .Z(\UART_TX/n32 ) );
notech_nao3 \UART_TX/U26 ( .C(\UART_TX/n36 ), .A(\UART_TX/n37 ), .B(iLCR[0]), .Z(\UART_TX/n11 ) );
notech_nand2 \UART_TX/U25 ( .A(\UART_TX/n21 ), .B(\UART_TX/n28 ), .Z(
\UART_TX/n35 ) );
notech_and2 \UART_TX/U24 ( .A(\UART_TX/n13 ), .B(\UART_TX/n35 ), .Z(
\UART_TX/n34 ) );
notech_or2 \UART_TX/U23 ( .A(\UART_TX/n34 ), .B(\UART_TX/n5 ), .Z(
\UART_TX/n33 ) );
notech_and3 \UART_TX/U22 ( .A(\UART_TX/n32 ), .B(\UART_TX/n11 ), .C(
\UART_TX/n33 ), .Z(\UART_TX/n26 ) );
notech_nand2 \UART_TX/U21 ( .A(\UART_TX/n18 ), .B(\UART_TX/CState[2] ), .Z(
\UART_TX/n31 ) );
notech_nand2 \UART_TX/U20 ( .A(\UART_TX/n31 ), .B(\UART_TX/n5 ), .Z(
\UART_TX/n30 ) );
notech_and2 \UART_TX/U19 ( .A(\UART_TX/n29 ), .B(\UART_TX/n30 ), .Z(
\UART_TX/n27 ) );
notech_nao4 \UART_TX/U18 ( .A(\UART_TX/n26 ), .B(\UART_TX/n6 ), .C(
\UART_TX/n27 ), .D(\UART_TX/n28 ), .Z(\UART_TX/n90 ) );
notech_inv \UART_TX/U17 ( .A(\UART_TX/n25 ), .Z(\UART_TX/n93 ) );
notech_nao3 \UART_TX/U16 ( .C(iLCR[2]), .A(\UART_TX/n93 ), .B(iTXStart),
.Z(\UART_TX/n7 ) );
notech_nand3 \UART_TX/U15 ( .A(\UART_TX/n24 ), .B(iLCR[3]), .C(iLCR[1]),
.Z(\UART_TX/n23 ) );
notech_nand2 \UART_TX/U14 ( .A(\UART_TX/n22 ), .B(\UART_TX/n23 ), .Z(
\UART_TX/n9 ) );
notech_inv \UART_TX/U13 ( .A(iTXStart), .Z(\UART_TX/n16 ) );
notech_or2 \UART_TX/U12 ( .A(\UART_TX/n21 ), .B(\UART_TX/CState[1] ), .Z(
\UART_TX/n19 ) );
notech_mux2 \UART_TX/U11 ( .A(\UART_TX/n19 ), .B(\UART_TX/CState[2] ), .S(
\UART_TX/n20 ), .Z(\UART_TX/n17 ) );
notech_ao4 \UART_TX/U10 ( .A(\UART_TX/n16 ), .B(\UART_TX/n17 ), .C(iLCR[3]),
.D(\UART_TX/n18 ), .Z(\UART_TX/n14 ) );
notech_ao3 \UART_TX/U9 ( .A(\UART_TX/n13 ), .B(\UART_TX/n14 ), .C(
\UART_TX/n15 ), .Z(\UART_TX/n12 ) );
notech_ao4 \UART_TX/U8 ( .A(iLCR[3]), .B(\UART_TX/n11 ), .C(
\UART_TX/CState[0] ), .D(\UART_TX/n12 ), .Z(\UART_TX/n10 ) );
notech_and4 \UART_TX/U7 ( .A(\UART_TX/n7 ), .B(\UART_TX/n8 ), .C(
\UART_TX/n9 ), .D(\UART_TX/n10 ), .Z(\UART_TX/n4 ) );
notech_mux2 \UART_TX/U6 ( .A(\UART_TX/n4 ), .B(\UART_TX/n5 ), .S(
\UART_TX/n6 ), .Z(\UART_TX/n1 ) );
notech_or2 \UART_TX/U5 ( .A(\UART_TX/n3 ), .B(iLCR[3]), .Z(\UART_TX/n2 ) );
notech_nand2 \UART_TX/U4 ( .A(\UART_TX/n1 ), .B(\UART_TX/n2 ), .Z(
\UART_TX/n92 ) );
notech_reg \UART_TX/iFinished_reg ( .D(\UART_TX/N127 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(iTXFinished) );
notech_reg \UART_TX/iLast_reg ( .D(\UART_TX/n93 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_TX/iLast ) );
notech_reg \UART_TX/iTx2_reg ( .D(\UART_TX/n87 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(\UART_TX/iTx2 ) );
notech_reg \UART_TX/CState_reg[3] ( .D(\UART_TX/n88 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_TX/CState[3] ) );
notech_reg \UART_TX/CState_reg[2] ( .D(\UART_TX/n89 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(\UART_TX/CState[2] ) );
notech_reg \UART_TX/CState_reg[1] ( .D(\UART_TX/n90 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_TX/CState[1] ) );
notech_reg \UART_TX/CState_reg[0] ( .D(\UART_TX/n92 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(\UART_TX/CState[0] ) );
notech_inv \UART_RX/U110 ( .A(iRXData[2]), .Z(\UART_RX/n78 ) );
notech_xor2 \UART_RX/U109 ( .A(iRXData[3]), .B(\UART_RX/n78 ), .Z(
\UART_RX/n82 ) );
notech_inv \UART_RX/U108 ( .A(iRXData[1]), .Z(\UART_RX/n77 ) );
notech_inv \UART_RX/U107 ( .A(iRXData[0]), .Z(\UART_RX/n73 ) );
notech_xor2 \UART_RX/U106 ( .A(\UART_RX/n77 ), .B(\UART_RX/n73 ), .Z(
\UART_RX/n83 ) );
notech_xor2 \UART_RX/U105 ( .A(iRXData[7]), .B(iRXData[6]), .Z(
\UART_RX/n85 ) );
notech_fa2 \UART_RX/U104 ( .A(iRXData[5]), .B(\UART_RX/n85 ), .CI(
iRXData[4]), .Z(\UART_RX/n84 ) );
notech_fa2 \UART_RX/U103 ( .A(\UART_RX/n82 ), .B(\UART_RX/n83 ), .CI(
\UART_RX/n84 ), .Z(\UART_RX/n81 ) );
notech_nor2 \UART_RX/U102 ( .A(iLCR[5]), .B(\UART_RX/n81 ), .Z(
\UART_RX/n80 ) );
notech_fa2 \UART_RX/U101 ( .A(iLCR[4]), .B(\UART_RX/n80 ), .CI(
\UART_RX/iParityReceived ), .Z(\UART_RX/n79 ) );
notech_inv \UART_RX/U100 ( .A(iLCR[3]), .Z(\UART_RX/n47 ) );
notech_nor2 \UART_RX/U99 ( .A(\UART_RX/n79 ), .B(\UART_RX/n47 ), .Z(
\UART_RX/N106 ) );
notech_inv \UART_RX/U98 ( .A(\UART_RX/CState[0] ), .Z(\UART_RX/n63 ) );
notech_nao3 \UART_RX/U97 ( .C(\UART_RX/CState[1] ), .A(\UART_RX/CState[2] ),
.B(\UART_RX/n63 ), .Z(\UART_RX/n50 ) );
notech_nor2 \UART_RX/U96 ( .A(\UART_RX/n50 ), .B(\UART_RX/iFStopBit ), .Z(
iRXFE) );
notech_ao3 \UART_RX/U95 ( .A(\UART_RX/n77 ), .B(\UART_RX/n78 ), .C(
iRXData[3]), .Z(\UART_RX/n74 ) );
notech_or2 \UART_RX/U94 ( .A(\UART_RX/iParityReceived ), .B(iRXData[7]),
.Z(\UART_RX/n76 ) );
notech_nor4 \UART_RX/U93 ( .A(iRXData[4]), .B(iRXData[5]), .C(\UART_RX/n76 ), .D(iRXData[6]), .Z(\UART_RX/n75 ) );
notech_and4 \UART_RX/U92 ( .A(iRXFE), .B(\UART_RX/n73 ), .C(\UART_RX/n74 ),
.D(\UART_RX/n75 ), .Z(iRXBI) );
notech_nor2 \UART_RX/U91 ( .A(\UART_RX/CState[2] ), .B(\UART_RX/CState[1] ),
.Z(\UART_RX/n5 ) );
notech_nand2 \UART_RX/U90 ( .A(\UART_RX/n5 ), .B(\UART_RX/n63 ), .Z(
\UART_RX/n61 ) );
notech_inv \UART_RX/U89 ( .A(\UART_RX/n61 ), .Z(\UART_RX/N75 ) );
notech_inv \UART_RX/U88 ( .A(\UART_RX/CState[2] ), .Z(\UART_RX/n72 ) );
notech_nor4 \UART_RX/U87 ( .A(\UART_RX/n72 ), .B(\UART_RX/n63 ), .C(iSIN),
.D(\UART_RX/CState[1] ), .Z(\UART_RX/n48 ) );
notech_inv \UART_RX/U86 ( .A(\UART_RX/iBaudStep ), .Z(\UART_RX/n42 ) );
notech_and3 \UART_RX/U85 ( .A(\UART_RX/n72 ), .B(\UART_RX/n42 ), .C(
\UART_RX/CState[0] ), .Z(\UART_RX/n57 ) );
notech_nand2 \UART_RX/U84 ( .A(\UART_RX/CState[1] ), .B(\UART_RX/n72 ), .Z(
\UART_RX/n52 ) );
notech_and2 \UART_RX/U83 ( .A(\UART_RX/iDataCount[1] ), .B(
\UART_RX/iDataCount[0] ), .Z(\UART_RX/n6 ) );
notech_and2 \UART_RX/U81 ( .A(\UART_RX/n6 ), .B(\UART_TX/n37 ), .Z(
\UART_RX/n67 ) );
notech_inv \UART_RX/U80 ( .A(\UART_RX/iDataCount[0] ), .Z(\UART_RX/n22 ) );
notech_mux2 \UART_RX/U79 ( .A(\UART_RX/n22 ), .B(iLCR[1]), .S(iLCR[0]), .Z(
\UART_RX/n68 ) );
notech_or2 \UART_RX/U78 ( .A(iLCR[0]), .B(iLCR[1]), .Z(\UART_RX/n70 ) );
notech_inv \UART_RX/U77 ( .A(\UART_RX/iDataCount[1] ), .Z(\UART_RX/n24 ) );
notech_and2 \UART_RX/U76 ( .A(\UART_RX/n70 ), .B(\UART_RX/n24 ), .Z(
\UART_RX/n69 ) );
notech_nor4 \UART_RX/U75 ( .A(\UART_RX/n67 ), .B(\UART_RX/n68 ), .C(
\UART_RX/iDataCount[3] ), .D(\UART_RX/n69 ), .Z(\UART_RX/n64 ) );
notech_and2 \UART_RX/U74 ( .A(\UART_RX/n24 ), .B(\UART_RX/n22 ), .Z(
\UART_RX/n66 ) );
notech_and4 \UART_RX/U73 ( .A(iLCR[1]), .B(\UART_RX/iDataCount[3] ), .C(
iLCR[0]), .D(\UART_RX/n66 ), .Z(\UART_RX/n65 ) );
notech_inv \UART_RX/U72 ( .A(\UART_RX/iDataCount[2] ), .Z(\UART_RX/n31 ) );
notech_mux2 \UART_RX/U71 ( .A(\UART_RX/n64 ), .B(\UART_RX/n65 ), .S(
\UART_RX/n31 ), .Z(\UART_RX/n41 ) );
notech_nao3 \UART_RX/U70 ( .C(\UART_RX/n52 ), .A(\UART_RX/n41 ), .B(
\UART_RX/n63 ), .Z(\UART_RX/n51 ) );
notech_nor2 \UART_RX/U69 ( .A(\UART_RX/n51 ), .B(\UART_RX/n47 ), .Z(
\UART_RX/n58 ) );
notech_inv \UART_RX/U68 ( .A(\UART_RX/n50 ), .Z(\UART_RX/n62 ) );
notech_nao4 \UART_RX/U65 ( .A(\UART_RX/iFStopBit ), .B(n680), .C(iSIN), .D(
\UART_RX/n61 ), .Z(\UART_RX/n59 ) );
notech_or4 \UART_RX/U64 ( .A(\UART_RX/n48 ), .B(\UART_RX/n57 ), .C(
\UART_RX/n58 ), .D(\UART_RX/n59 ), .Z(\UART_RX/NState [0]) );
notech_and2 \UART_RX/U63 ( .A(\UART_RX/n41 ), .B(\UART_RX/n47 ), .Z(
\UART_RX/n56 ) );
notech_mux2 \UART_RX/U62 ( .A(\UART_RX/n56 ), .B(\UART_RX/iBaudStep ), .S(
\UART_RX/CState[0] ), .Z(\UART_RX/n53 ) );
notech_inv \UART_RX/U61 ( .A(\UART_RX/iFSIN ), .Z(\UART_RX/n43 ) );
notech_nand2 \UART_RX/U60 ( .A(\UART_RX/iBaudStep ), .B(\UART_RX/n43 ), .Z(
\UART_RX/n54 ) );
notech_nand2 \UART_RX/U59 ( .A(\UART_RX/n5 ), .B(\UART_RX/CState[0] ), .Z(
\UART_RX/n55 ) );
notech_nao4 \UART_RX/U58 ( .A(\UART_RX/n52 ), .B(\UART_RX/n53 ), .C(
\UART_RX/n54 ), .D(\UART_RX/n55 ), .Z(\UART_RX/NState [1]) );
notech_ao3 \UART_RX/U57 ( .A(\UART_RX/CState[0] ), .B(\UART_RX/iBaudStep ),
.C(\UART_RX/n52 ), .Z(\UART_RX/n46 ) );
notech_nao4 \UART_RX/U56 ( .A(\UART_RX/iBaudCount[3] ), .B(\UART_RX/n50 ),
.C(iLCR[3]), .D(\UART_RX/n51 ), .Z(\UART_RX/n49 ) );
notech_or4 \UART_RX/U55 ( .A(iRXFE), .B(\UART_RX/n46 ), .C(\UART_RX/n48 ),
.D(\UART_RX/n49 ), .Z(\UART_RX/NState [2]) );
notech_or2 \UART_RX/U54 ( .A(\UART_RX/N75 ), .B(\UART_RX/iBaudStepD ), .Z(
\UART_RX/iFilterClear ) );
notech_and2 \UART_RX/U53 ( .A(iLCR[3]), .B(\UART_RX/iFSIN ), .Z(
\UART_RX/n44 ) );
notech_nor2 \UART_RX/U52 ( .A(\UART_RX/n46 ), .B(\UART_RX/n47 ), .Z(
\UART_RX/n45 ) );
notech_mux2 \UART_RX/U51 ( .A(\UART_RX/n44 ), .B(\UART_RX/iParityReceived ),
.S(\UART_RX/n45 ), .Z(\UART_RX/n105 ) );
notech_nor2 \UART_RX/U50 ( .A(\UART_RX/n5 ), .B(\UART_RX/n43 ), .Z(
\UART_RX/n19 ) );
notech_nor2 \UART_RX/U49 ( .A(\UART_RX/n41 ), .B(\UART_RX/n42 ), .Z(
\UART_RX/n18 ) );
notech_and2 \UART_RX/U48 ( .A(\UART_RX/n18 ), .B(\UART_RX/iDataCount[2] ),
.Z(\UART_RX/n34 ) );
notech_and2 \UART_RX/U47 ( .A(\UART_RX/n34 ), .B(\UART_RX/n6 ), .Z(
\UART_RX/n40 ) );
notech_nor2 \UART_RX/U46 ( .A(\UART_RX/n40 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n39 ) );
notech_mux2 \UART_RX/U45 ( .A(\UART_RX/n19 ), .B(iRXData[7]), .S(
\UART_RX/n39 ), .Z(\UART_RX/n106 ) );
notech_and2 \UART_RX/U44 ( .A(\UART_RX/iDataCount[1] ), .B(\UART_RX/n22 ),
.Z(\UART_RX/n14 ) );
notech_and2 \UART_RX/U43 ( .A(\UART_RX/n34 ), .B(\UART_RX/n14 ), .Z(
\UART_RX/n38 ) );
notech_nor2 \UART_RX/U42 ( .A(\UART_RX/n38 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n37 ) );
notech_mux2 \UART_RX/U41 ( .A(\UART_RX/n19 ), .B(iRXData[6]), .S(
\UART_RX/n37 ), .Z(\UART_RX/n107 ) );
notech_and2 \UART_RX/U40 ( .A(\UART_RX/iDataCount[0] ), .B(\UART_RX/n24 ),
.Z(\UART_RX/n15 ) );
notech_and2 \UART_RX/U39 ( .A(\UART_RX/n34 ), .B(\UART_RX/n15 ), .Z(
\UART_RX/n36 ) );
notech_nor2 \UART_RX/U38 ( .A(\UART_RX/n36 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n35 ) );
notech_mux2 \UART_RX/U37 ( .A(\UART_RX/n19 ), .B(iRXData[5]), .S(
\UART_RX/n35 ), .Z(\UART_RX/n108 ) );
notech_and3 \UART_RX/U36 ( .A(\UART_RX/n22 ), .B(\UART_RX/n34 ), .C(
\UART_RX/n24 ), .Z(\UART_RX/n33 ) );
notech_nor2 \UART_RX/U35 ( .A(\UART_RX/n33 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n32 ) );
notech_mux2 \UART_RX/U34 ( .A(\UART_RX/n19 ), .B(iRXData[4]), .S(
\UART_RX/n32 ), .Z(\UART_RX/n109 ) );
notech_and2 \UART_RX/U33 ( .A(\UART_RX/n18 ), .B(\UART_RX/n31 ), .Z(
\UART_RX/n23 ) );
notech_and2 \UART_RX/U32 ( .A(\UART_RX/n23 ), .B(\UART_RX/n6 ), .Z(
\UART_RX/n30 ) );
notech_nor2 \UART_RX/U31 ( .A(\UART_RX/n30 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n29 ) );
notech_mux2 \UART_RX/U30 ( .A(\UART_RX/n19 ), .B(iRXData[3]), .S(
\UART_RX/n29 ), .Z(\UART_RX/n110 ) );
notech_and2 \UART_RX/U29 ( .A(\UART_RX/n23 ), .B(\UART_RX/n14 ), .Z(
\UART_RX/n28 ) );
notech_nor2 \UART_RX/U28 ( .A(\UART_RX/n28 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n27 ) );
notech_mux2 \UART_RX/U27 ( .A(\UART_RX/n19 ), .B(iRXData[2]), .S(
\UART_RX/n27 ), .Z(\UART_RX/n111 ) );
notech_and2 \UART_RX/U26 ( .A(\UART_RX/n23 ), .B(\UART_RX/n15 ), .Z(
\UART_RX/n26 ) );
notech_nor2 \UART_RX/U25 ( .A(\UART_RX/n26 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n25 ) );
notech_mux2 \UART_RX/U24 ( .A(\UART_RX/n19 ), .B(iRXData[1]), .S(
\UART_RX/n25 ), .Z(\UART_RX/n112 ) );
notech_and3 \UART_RX/U23 ( .A(\UART_RX/n22 ), .B(\UART_RX/n23 ), .C(
\UART_RX/n24 ), .Z(\UART_RX/n21 ) );
notech_nor2 \UART_RX/U22 ( .A(\UART_RX/n21 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n20 ) );
notech_mux2 \UART_RX/U21 ( .A(\UART_RX/n19 ), .B(iRXData[0]), .S(
\UART_RX/n20 ), .Z(\UART_RX/n113 ) );
notech_nor2 \UART_RX/U20 ( .A(\UART_RX/n18 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n8 ) );
notech_or2 \UART_RX/U19 ( .A(\UART_RX/n8 ), .B(\UART_RX/n5 ), .Z(
\UART_RX/n11 ) );
notech_inv \UART_RX/U18 ( .A(\UART_RX/n11 ), .Z(\UART_RX/n7 ) );
notech_and2 \UART_RX/U17 ( .A(\UART_RX/n7 ), .B(\UART_RX/n6 ), .Z(
\UART_RX/n16 ) );
notech_nor2 \UART_RX/U16 ( .A(\UART_RX/n5 ), .B(\UART_RX/n6 ), .Z(
\UART_RX/n17 ) );
notech_or2 \UART_RX/U15 ( .A(\UART_RX/n8 ), .B(\UART_RX/n17 ), .Z(
\UART_RX/n3 ) );
notech_mux2 \UART_RX/U14 ( .A(\UART_RX/n16 ), .B(\UART_RX/n3 ), .S(
\UART_RX/iDataCount[2] ), .Z(\UART_RX/n114 ) );
notech_inv \UART_RX/U13 ( .A(\UART_RX/n15 ), .Z(\UART_RX/n12 ) );
notech_inv \UART_RX/U12 ( .A(\UART_RX/n14 ), .Z(\UART_RX/n13 ) );
notech_ao4 \UART_RX/U11 ( .A(\UART_RX/n11 ), .B(\UART_RX/n12 ), .C(
\UART_RX/n5 ), .D(\UART_RX/n13 ), .Z(\UART_RX/n9 ) );
notech_nand2 \UART_RX/U10 ( .A(\UART_RX/n8 ), .B(\UART_RX/iDataCount[1] ),
.Z(\UART_RX/n10 ) );
notech_nand2 \UART_RX/U9 ( .A(\UART_RX/n9 ), .B(\UART_RX/n10 ), .Z(
\UART_RX/n115 ) );
notech_mux2 \UART_RX/U8 ( .A(\UART_RX/n7 ), .B(\UART_RX/n8 ), .S(
\UART_RX/iDataCount[0] ), .Z(\UART_RX/n116 ) );
notech_and3 \UART_RX/U7 ( .A(\UART_RX/iDataCount[2] ), .B(\UART_RX/n6 ),
.C(\UART_RX/n7 ), .Z(\UART_RX/n1 ) );
notech_nor2 \UART_RX/U6 ( .A(\UART_RX/n5 ), .B(\UART_RX/iDataCount[2] ),
.Z(\UART_RX/n4 ) );
notech_or2 \UART_RX/U5 ( .A(\UART_RX/n3 ), .B(\UART_RX/n4 ), .Z(
\UART_RX/n2 ) );
notech_mux2 \UART_RX/U4 ( .A(\UART_RX/n1 ), .B(\UART_RX/n2 ), .S(
\UART_RX/iDataCount[3] ), .Z(\UART_RX/n117 ) );
notech_reg \UART_RX/PE_reg ( .D(\UART_RX/N106 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(iRXPE) );
notech_reg \UART_RX/iParityReceived_reg ( .D(\UART_RX/n105 ), .CP(CLK),
.CD(\UART_IF_CTS/n8 ), .Q(\UART_RX/iParityReceived ) );
notech_reg \UART_RX/iDOUT_reg[7] ( .D(\UART_RX/n106 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(iRXData[7]) );
notech_reg \UART_RX/iDOUT_reg[6] ( .D(\UART_RX/n107 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(iRXData[6]) );
notech_reg \UART_RX/iDOUT_reg[5] ( .D(\UART_RX/n108 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(iRXData[5]) );
notech_reg \UART_RX/iDOUT_reg[4] ( .D(\UART_RX/n109 ), .CP(CLK), .CD(
\UART_IS_CTS/n1 ), .Q(iRXData[4]) );
notech_reg \UART_RX/iDOUT_reg[3] ( .D(\UART_RX/n110 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(iRXData[3]) );
notech_reg \UART_RX/iDOUT_reg[2] ( .D(\UART_RX/n111 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(iRXData[2]) );
notech_reg \UART_RX/iDOUT_reg[1] ( .D(\UART_RX/n112 ), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(iRXData[1]) );
notech_reg \UART_RX/iDOUT_reg[0] ( .D(\UART_RX/n113 ), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(iRXData[0]) );
notech_reg \UART_RX/CState_reg[2] ( .D(\UART_RX/NState [2]), .CP(CLK), .CD(
\UART_IS_RI/n1 ), .Q(\UART_RX/CState[2] ) );
notech_reg \UART_RX/iDataCount_reg[2] ( .D(\UART_RX/n114 ), .CP(CLK), .CD(
\UART_IS_DCD/n1 ), .Q(\UART_RX/iDataCount[2] ) );
notech_reg \UART_RX/iDataCount_reg[1] ( .D(\UART_RX/n115 ), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_RX/iDataCount[1] ) );
notech_reg \UART_RX/iDataCount_reg[0] ( .D(\UART_RX/n116 ), .CP(CLK), .CD(
\UART_IS_SIN/n1 ), .Q(\UART_RX/iDataCount[0] ) );
notech_reg \UART_RX/iDataCount_reg[3] ( .D(\UART_RX/n117 ), .CP(CLK), .CD(
\UART_IF_DSR/n8 ), .Q(\UART_RX/iDataCount[3] ) );
notech_reg \UART_RX/iBaudStepD_reg ( .D(\UART_RX/iBaudStep ), .CP(CLK),
.CD(\UART_IS_DCD/n1 ), .Q(\UART_RX/iBaudStepD ) );
notech_reg \UART_RX/CState_reg[1] ( .D(\UART_RX/NState [1]), .CP(CLK), .CD(
\UART_IS_DSR/n1 ), .Q(\UART_RX/CState[1] ) );
notech_reg \UART_RX/CState_reg[0] ( .D(\UART_RX/NState [0]), .CP(CLK), .CD(
\UART_IF_CTS/n8 ), .Q(\UART_RX/CState[0] ) );
notech_inv \UART_RX/RX_BRC/U33 ( .A(\UART_RX/RX_BRC/Q[2] ), .Z(
\UART_RX/RX_BRC/n12 ) );
notech_inv \UART_RX/RX_BRC/U29 ( .A(\UART_RX/iBaudCount[3] ), .Z(
\UART_RX/RX_BRC/n17 ) );
notech_and3 \UART_RX/RX_BRC/U22 ( .A(\UART_RX/RX_BRC/n22 ), .B(iRCLK), .C(
\UART_RX/RX_BRC/n23 ), .Z(\UART_RX/RX_BRC/n26 ) );
notech_nand2 \UART_RX/RX_BRC/U20 ( .A(\UART_RX/RX_BRC/n6 ), .B(
\UART_RX/n61 ), .Z(\UART_RX/RX_BRC/n7 ) );
notech_nao4 \UART_RX/RX_BRC/U16 ( .A(\UART_RX/RX_BRC/n6 ), .B(
\UART_RX/RX_BRC/n17 ), .C(\UART_RX/RX_BRC/n7 ), .D(
\UART_RX/RX_BRC/n18 ), .Z(\UART_RX/RX_BRC/n27 ) );
notech_nao4 \UART_RX/RX_BRC/U12 ( .A(\UART_RX/RX_BRC/n6 ), .B(
\UART_RX/RX_BRC/n12 ), .C(\UART_RX/RX_BRC/n7 ), .D(
\UART_RX/RX_BRC/n13 ), .Z(\UART_RX/RX_BRC/n28 ) );
notech_inv \UART_RX/RX_BRC/U11 ( .A(\UART_RX/RX_BRC/Q[1] ), .Z(
\UART_RX/RX_BRC/n5 ) );
notech_inv \UART_RX/RX_BRC/U8 ( .A(\UART_RX/RX_BRC/n9 ), .Z(
\UART_RX/RX_BRC/n8 ) );
notech_nao4 \UART_RX/RX_BRC/U7 ( .A(\UART_RX/RX_BRC/n5 ), .B(
\UART_RX/RX_BRC/n6 ), .C(\UART_RX/RX_BRC/n7 ), .D(\UART_RX/RX_BRC/n8 ),
.Z(\UART_RX/RX_BRC/n29 ) );
notech_xor2 \UART_RX/RX_BRC/U6 ( .A(\UART_RX/RX_BRC/Q[0] ), .B(iRCLK), .Z(
\UART_RX/RX_BRC/n1 ) );
notech_and2 \UART_RX/RX_BRC/U4 ( .A(\UART_RX/RX_BRC/n1 ), .B(\UART_RX/n61 ),
.Z(\UART_RX/RX_BRC/n30 ) );
notech_reg \UART_RX/RX_BRC/iCounter_reg[4] ( .D(\UART_RX/RX_BRC/n26 ), .CP(
CLK), .CD(\UART_IS_DSR/n1 ), .Q(\UART_RX/iBaudStep ) );
notech_reg \UART_RX/RX_BRC/iCounter_reg[3] ( .D(\UART_RX/RX_BRC/n27 ), .CP(
CLK), .CD(\UART_IF_DSR/n8 ), .Q(\UART_RX/iBaudCount[3] ) );
notech_reg \UART_RX/RX_BRC/iCounter_reg[2] ( .D(\UART_RX/RX_BRC/n28 ), .CP(
CLK), .CD(\UART_IF_CTS/n8 ), .Q(\UART_RX/RX_BRC/Q[2] ) );
notech_reg \UART_RX/RX_BRC/iCounter_reg[1] ( .D(\UART_RX/RX_BRC/n29 ), .CP(
CLK), .CD(\UART_IS_RI/n1 ), .Q(\UART_RX/RX_BRC/Q[1] ) );
notech_reg \UART_RX/RX_BRC/iCounter_reg[0] ( .D(\UART_RX/RX_BRC/n30 ), .CP(
CLK), .CD(\UART_IS_DCD/n1 ), .Q(\UART_RX/RX_BRC/Q[0] ) );
notech_nor2 \UART_RX/RX_MVF/U26 ( .A(\UART_RX/RX_MVF/iCounter[2] ), .B(
\UART_RX/RX_MVF/iCounter[1] ), .Z(\UART_RX/RX_MVF/n18 ) );
notech_inv \UART_RX/RX_MVF/U25 ( .A(\UART_RX/RX_MVF/iCounter[3] ), .Z(
\UART_RX/RX_MVF/n12 ) );
notech_or2 \UART_RX/RX_MVF/U24 ( .A(\UART_RX/RX_MVF/n18 ), .B(
\UART_RX/RX_MVF/n12 ), .Z(\UART_RX/RX_MVF/n16 ) );
notech_nor2 \UART_RX/RX_MVF/U23 ( .A(\UART_RX/RX_MVF/n17 ), .B(
\UART_RX/iFilterClear ), .Z(\UART_RX/RX_MVF/n21 ) );
notech_nor2 \UART_RX/RX_MVF/U22 ( .A(\UART_RX/RX_MVF/n15 ), .B(
\UART_RX/iFilterClear ), .Z(\UART_RX/RX_MVF/n2 ) );
notech_or2 \UART_RX/RX_MVF/U21 ( .A(\UART_RX/RX_MVF/n2 ), .B(
\UART_RX/iFilterClear ), .Z(\UART_RX/RX_MVF/n10 ) );
notech_inv \UART_RX/RX_MVF/U20 ( .A(\UART_RX/RX_MVF/n10 ), .Z(
\UART_RX/RX_MVF/n1 ) );
notech_nor2 \UART_RX/RX_MVF/U19 ( .A(\UART_RX/RX_MVF/n1 ), .B(
\UART_RX/RX_MVF/n2 ), .Z(\UART_RX/RX_MVF/n3 ) );
notech_nand2 \UART_RX/RX_MVF/U18 ( .A(\UART_RX/RX_MVF/n1 ), .B(
\UART_RX/RX_MVF/iCounter[0] ), .Z(\UART_RX/RX_MVF/n13 ) );
notech_nand2 \UART_RX/RX_MVF/U17 ( .A(\UART_RX/RX_MVF/iCounter[2] ), .B(
\UART_RX/RX_MVF/iCounter[1] ), .Z(\UART_RX/RX_MVF/n14 ) );
notech_nao4 \UART_RX/RX_MVF/U16 ( .A(\UART_RX/RX_MVF/n3 ), .B(
\UART_RX/RX_MVF/n12 ), .C(\UART_RX/RX_MVF/n13 ), .D(
\UART_RX/RX_MVF/n14 ), .Z(\UART_RX/RX_MVF/n22 ) );
notech_ao3 \UART_RX/RX_MVF/U15 ( .A(\UART_RX/RX_MVF/iCounter[1] ), .B(
\UART_RX/RX_MVF/iCounter[0] ), .C(\UART_RX/RX_MVF/n10 ), .Z(
\UART_RX/RX_MVF/n7 ) );
notech_nor2 \UART_RX/RX_MVF/U14 ( .A(\UART_RX/RX_MVF/n10 ), .B(
\UART_RX/RX_MVF/iCounter[0] ), .Z(\UART_RX/RX_MVF/n11 ) );
notech_or2 \UART_RX/RX_MVF/U13 ( .A(\UART_RX/RX_MVF/n11 ), .B(
\UART_RX/RX_MVF/n2 ), .Z(\UART_RX/RX_MVF/n6 ) );
notech_nor2 \UART_RX/RX_MVF/U12 ( .A(\UART_RX/RX_MVF/n10 ), .B(
\UART_RX/RX_MVF/iCounter[1] ), .Z(\UART_RX/RX_MVF/n9 ) );
notech_or2 \UART_RX/RX_MVF/U11 ( .A(\UART_RX/RX_MVF/n6 ), .B(
\UART_RX/RX_MVF/n9 ), .Z(\UART_RX/RX_MVF/n8 ) );
notech_mux2 \UART_RX/RX_MVF/U10 ( .A(\UART_RX/RX_MVF/n7 ), .B(
\UART_RX/RX_MVF/n8 ), .S(\UART_RX/RX_MVF/iCounter[2] ), .Z(
\UART_RX/RX_MVF/n23 ) );
notech_and2 \UART_RX/RX_MVF/U9 ( .A(\UART_RX/RX_MVF/n1 ), .B(
\UART_RX/RX_MVF/iCounter[0] ), .Z(\UART_RX/RX_MVF/n5 ) );
notech_mux2 \UART_RX/RX_MVF/U8 ( .A(\UART_RX/RX_MVF/n5 ), .B(
\UART_RX/RX_MVF/n6 ), .S(\UART_RX/RX_MVF/iCounter[1] ), .Z(
\UART_RX/RX_MVF/n24 ) );
notech_mux2 \UART_RX/RX_MVF/U7 ( .A(\UART_RX/RX_MVF/n1 ), .B(
\UART_RX/RX_MVF/n2 ), .S(\UART_RX/RX_MVF/iCounter[0] ), .Z(
\UART_RX/RX_MVF/n26 ) );
notech_and3 \UART_RX/RX_MVF/U3 ( .A(iSIN), .B(\UART_RX/RX_MVF/n16 ), .C(
iRCLK), .Z(\UART_RX/RX_MVF/n15 ) );
notech_reg \UART_RX/RX_MVF/iQ_reg ( .D(\UART_RX/RX_MVF/n21 ), .CP(CLK),
.CD(\UART_IS_CTS/n1 ), .Q(\UART_RX/iFSIN ) );
notech_reg \UART_RX/RX_MVF/iCounter_reg[1] ( .D(\UART_RX/RX_MVF/n24 ), .CP(
CLK), .CD(\UART_IF_CTS/n8 ), .Q(\UART_RX/RX_MVF/iCounter[1] ) );
notech_reg \UART_RX/RX_MVF/iCounter_reg[2] ( .D(\UART_RX/RX_MVF/n23 ), .CP(
CLK), .CD(\UART_IS_SIN/n1 ), .Q(\UART_RX/RX_MVF/iCounter[2] ) );
notech_reg \UART_RX/RX_MVF/iCounter_reg[3] ( .D(\UART_RX/RX_MVF/n22 ), .CP(
CLK), .CD(\UART_IS_SIN/n1 ), .Q(\UART_RX/RX_MVF/iCounter[3] ) );
notech_reg \UART_RX/RX_MVF/iCounter_reg[0] ( .D(\UART_RX/RX_MVF/n26 ), .CP(
CLK), .CD(\UART_IF_DSR/n8 ), .Q(\UART_RX/RX_MVF/iCounter[0] ) );
notech_nor2 \UART_RX/RX_IFSB/U25 ( .A(\UART_RX/RX_IFSB/iCount[0] ), .B(
\UART_RX/RX_IFSB/iCount[1] ), .Z(\UART_RX/RX_IFSB/n18 ) );
notech_inv \UART_RX/RX_IFSB/U24 ( .A(\UART_RX/RX_IFSB/n18 ), .Z(
\UART_RX/RX_IFSB/n15 ) );
notech_and2 \UART_RX/RX_IFSB/U23 ( .A(\UART_RX/iFStopBit ), .B(
\UART_RX/RX_IFSB/n15 ), .Z(\UART_RX/RX_IFSB/n17 ) );
notech_and2 \UART_RX/RX_IFSB/U22 ( .A(\UART_RX/RX_IFSB/n18 ), .B(
\UART_RX/RX_IFSB/iCount[2] ), .Z(\UART_RX/RX_IFSB/n16 ) );
notech_or2 \UART_RX/RX_IFSB/U21 ( .A(\UART_RX/RX_IFSB/n17 ), .B(
\UART_RX/RX_IFSB/n16 ), .Z(\UART_RX/RX_IFSB/n30 ) );
notech_inv \UART_RX/RX_IFSB/U20 ( .A(iSIN), .Z(\UART_RX/RX_IFSB/n8 ) );
notech_nor2 \UART_RX/RX_IFSB/U19 ( .A(\UART_RX/RX_IFSB/n16 ), .B(
\UART_RX/RX_IFSB/n8 ), .Z(\UART_RX/RX_IFSB/n11 ) );
notech_or2 \UART_RX/RX_IFSB/U18 ( .A(\UART_RX/RX_IFSB/n15 ), .B(
\UART_RX/RX_IFSB/iCount[2] ), .Z(\UART_RX/RX_IFSB/n14 ) );
notech_and2 \UART_RX/RX_IFSB/U17 ( .A(\UART_RX/RX_IFSB/n14 ), .B(
\UART_RX/RX_IFSB/n8 ), .Z(\UART_RX/RX_IFSB/n13 ) );
notech_or2 \UART_RX/RX_IFSB/U16 ( .A(\UART_RX/RX_IFSB/n11 ), .B(
\UART_RX/RX_IFSB/n13 ), .Z(\UART_RX/RX_IFSB/n12 ) );
notech_nand2 \UART_RX/RX_IFSB/U15 ( .A(\UART_RX/RX_IFSB/n12 ), .B(iRCLK),
.Z(\UART_RX/RX_IFSB/n2 ) );
notech_xor2 \UART_RX/RX_IFSB/U14 ( .A(\UART_RX/RX_IFSB/iCount[0] ), .B(
\UART_RX/RX_IFSB/n11 ), .Z(\UART_RX/RX_IFSB/n10 ) );
notech_nor2 \UART_RX/RX_IFSB/U13 ( .A(\UART_RX/RX_IFSB/n2 ), .B(
\UART_RX/RX_IFSB/n10 ), .Z(\UART_RX/RX_IFSB/n9 ) );
notech_xor2 \UART_RX/RX_IFSB/U12 ( .A(\UART_RX/RX_IFSB/iCount[1] ), .B(
\UART_RX/RX_IFSB/n9 ), .Z(\UART_RX/RX_IFSB/n31 ) );
notech_and4 \UART_RX/RX_IFSB/U11 ( .A(\UART_RX/RX_IFSB/iCount[1] ), .B(
\UART_RX/RX_IFSB/iCount[0] ), .C(iRCLK), .D(iSIN), .Z(
\UART_RX/RX_IFSB/n3 ) );
notech_inv \UART_RX/RX_IFSB/U10 ( .A(\UART_RX/RX_IFSB/iCount[1] ), .Z(
\UART_RX/RX_IFSB/n7 ) );
notech_nand2 \UART_RX/RX_IFSB/U9 ( .A(\UART_RX/RX_IFSB/iCount[0] ), .B(
\UART_RX/RX_IFSB/n7 ), .Z(\UART_RX/RX_IFSB/n5 ) );
notech_mux2 \UART_RX/RX_IFSB/U8 ( .A(\UART_RX/RX_IFSB/iCount[0] ), .B(
\UART_RX/RX_IFSB/n7 ), .S(\UART_RX/RX_IFSB/n8 ), .Z(
\UART_RX/RX_IFSB/n6 ) );
notech_nand3 \UART_RX/RX_IFSB/U7 ( .A(iRCLK), .B(\UART_RX/RX_IFSB/n5 ), .C(
\UART_RX/RX_IFSB/n6 ), .Z(\UART_RX/RX_IFSB/n4 ) );
notech_mux2 \UART_RX/RX_IFSB/U6 ( .A(\UART_RX/RX_IFSB/n3 ), .B(
\UART_RX/RX_IFSB/n4 ), .S(\UART_RX/RX_IFSB/iCount[2] ), .Z(
\UART_RX/RX_IFSB/n32 ) );
notech_xor2 \UART_RX/RX_IFSB/U5 ( .A(\UART_RX/RX_IFSB/iCount[0] ), .B(
\UART_RX/RX_IFSB/n2 ), .Z(\UART_RX/RX_IFSB/n1 ) );
notech_inv \UART_RX/RX_IFSB/U4 ( .A(\UART_RX/RX_IFSB/n1 ), .Z(
\UART_RX/RX_IFSB/n33 ) );
notech_reg \UART_RX/RX_IFSB/Q_reg ( .D(\UART_RX/RX_IFSB/n30 ), .CP(CLK),
.CD(\UART_IF_DSR/n8 ), .Q(\UART_RX/iFStopBit ) );
notech_reg \UART_RX/RX_IFSB/iCount_reg[2] ( .D(\UART_RX/RX_IFSB/n32 ), .CP(
CLK), .CD(\UART_IF_DSR/n8 ), .Q(\UART_RX/RX_IFSB/iCount[2] ) );
notech_reg \UART_RX/RX_IFSB/iCount_reg[1] ( .D(\UART_RX/RX_IFSB/n31 ), .CP(
CLK), .CD(\UART_IS_DCD/n1 ), .Q(\UART_RX/RX_IFSB/iCount[1] ) );
notech_reg \UART_RX/RX_IFSB/iCount_reg[0] ( .D(\UART_RX/RX_IFSB/n33 ), .CP(
CLK), .CD(\UART_IS_SIN/n1 ), .Q(\UART_RX/RX_IFSB/iCount[0] ) );
notech_inv \r108/U1 ( .A(\U3/U1/Z_0 ), .Z(\r108/n1 ) );
notech_fa2 \r108/U1_0 ( .A(iFECounter[0]), .B(\U3/U1/Z_0 ), .CI(\r108/n1 ),
.CO(\r108/carry [1]) );
notech_fa2 \r108/U1_1 ( .A(iFECounter[1]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [1]), .CO(\r108/carry [2]), .Z(N130) );
notech_fa2 \r108/U1_2 ( .A(iFECounter[2]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [2]), .CO(\r108/carry [3]), .Z(N131) );
notech_fa2 \r108/U1_3 ( .A(iFECounter[3]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [3]), .CO(\r108/carry [4]), .Z(N132) );
notech_fa2 \r108/U1_4 ( .A(iFECounter[4]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [4]), .CO(\r108/carry [5]), .Z(N133) );
notech_fa2 \r108/U1_5 ( .A(iFECounter[5]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [5]), .CO(\r108/carry [6]), .Z(N134) );
notech_fa2 \r108/U1_6 ( .A(iFECounter[6]), .B(\U3/U1/Z_0 ), .CI(
\r108/carry [6]), .Z(N135) );
notech_nand2 U458 ( .A(\UART_RX/n62 ), .B(\UART_RX/iBaudCount[3] ), .Z(n680)
);
notech_nand2 U461 ( .A(\UART_RX/RX_BRC/Q[1] ), .B(\UART_RX/RX_BRC/Q[0] ),
.Z(n681) );
notech_nand2 U471 ( .A(\UART_BG16/n35 ), .B(n686), .Z(n682) );
notech_nand2 U545 ( .A(N154), .B(\UART_ED_CTS/n1 ), .Z(n683) );
notech_nand2 U546 ( .A(N155), .B(\UART_ED_DSR/n1 ), .Z(n684) );
notech_nand2 U637 ( .A(N157), .B(\UART_ED_DCD/n1 ), .Z(n685) );
notech_inv U672 ( .A(BAUDCE), .Z(n686) );
notech_nand2 U756 ( .A(\UART_RX/n61 ), .B(n687), .Z(\UART_RX/RX_BRC/n6 ) );
notech_inv U790 ( .A(iRCLK), .Z(n687) );
notech_and2 U807 ( .A(\UART_RX/n61 ), .B(\UART_RX/n42 ), .Z(
\UART_RX/RX_BRC/n23 ) );
notech_xor2 U835 ( .A(n688), .B(\UART_RX/RX_BRC/n5 ), .Z(\UART_RX/RX_BRC/n9 ) );
notech_inv U836 ( .A(\UART_RX/RX_BRC/Q[0] ), .Z(n688) );
notech_xor2 U837 ( .A(n681), .B(\UART_RX/RX_BRC/Q[2] ), .Z(
\UART_RX/RX_BRC/n13 ) );
notech_xor2 U838 ( .A(n689), .B(\UART_RX/RX_BRC/n17 ), .Z(
\UART_RX/RX_BRC/n18 ) );
notech_inv U839 ( .A(\UART_RX/RX_BRC/n21 ), .Z(n689) );
notech_nor2 U840 ( .A(\UART_RX/RX_BRC/n21 ), .B(\UART_RX/RX_BRC/n17 ), .Z(
\UART_RX/RX_BRC/n22 ) );
notech_or2 U841 ( .A(\UART_RX/RX_BRC/n12 ), .B(n681), .Z(
\UART_RX/RX_BRC/n21 ) );
notech_and2 U842 ( .A(\UART_RX/RX_MVF/n16 ), .B(\UART_RX/n43 ), .Z(
\UART_RX/RX_MVF/n17 ) );
notech_nand2 U843 ( .A(BAUDCE), .B(\UART_BG16/n35 ), .Z(\UART_BG16/n2 ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKMUX2_PP_BLACKBOX_V
/**
* clkmux2: Clock mux.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkmux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_PP_BLACKBOX_V
|
/* ********************************************************************************************* */
/* * SPI Slave Module with delayed response * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* * Luciano Falqueto * */
/* * Wallison de Oliveira * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina, Luciano Falqueto and Wallison de Oliveira * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module SPISlaveDelayedResponse#(
/* Width of data to be received and sent (in bits */
parameter WIDTH = 32,
/* Delay inserted in transaction between read and write (in clock cycles, clocked by s_sclk) */
parameter DELAY = 32
) (
rst_n,
s_sclk,
s_mosi,
s_miso,
p_mosi,
p_miso,
p_valid
);
/* ************************************************************* */
/* Timing diagram: */
/* Example: WIDTH = 4, DELAY = 32 */
/* */
/* s_sclk: ____--__--__--__--__--__////--__--__--__--__--______ */
/* s_mosi: ____----____--------____////________________________ */
/* s_miso: ________________________////________----____----____ */
/* p_mosi: < XXX >< 0xB > */
/* p_miso: < 0x5 > */
/* p_valid: ----________________-------------------------------- */
/* Stages: <-1><-------------2><-----3><-----------------4><-5> */
/* */
/* Stages description: */
/* 1: Prior start of transaction; */
/* 2: Data being received. p_mosi holds invalid values; */
/* 3: Delay stage: s_sclk will cycle DELAY = 32 times; */
/* 4: Data being sent through s_miso. */
/* ************************************************************* */
/* Ugly assert: (2 * WIDTH) + DELAY - 1 should be less than 4096 */
generate
if((2 * WIDTH) + DELAY - 'h1 >= 4096) begin
WIDTH_times_2_plus_DELAY_must_be_less_than_4097();
end
endgenerate
/* Reset input (assert on low) */
input rst_n;
/* SPI: SCLK */
input s_sclk;
/* SPI: MOSI */
input s_mosi;
/* SPI: MISO */
output s_miso;
/* Parallel: MOSI */
output [WIDTH-1:0] p_mosi;
/* Parallel: MISO */
input [WIDTH-1:0] p_miso;
/* Data validity bit */
output p_valid;
reg [WIDTH-1:0] mosi;
reg [11:0] counter;
reg [11:0] counterOut;
/* SPI MISO feeder */
assign s_miso = (counter <= WIDTH - 'h1)? p_miso[counter] : 'b0;
assign p_mosi = mosi;
/* Validity bit is set when transaction completes */
assign p_valid = (counter < (DELAY + WIDTH)) || (((2 * WIDTH) + DELAY - 'h1) == counter);
always @(posedge s_sclk or negedge rst_n) begin
if(!rst_n) begin
counter <= (2 * WIDTH) + DELAY - 'h1;
end
else begin
/* SPI MOSI Register Feeder */
if(counter >= (DELAY + WIDTH)) begin
mosi[counter - (DELAY + WIDTH)] <= s_mosi;
end
/* Transaction counter. A full transaction comprises 2 * WIDTH + DELAY cycles */
counter <= counter? (counter - 'h1) : ((2 * WIDTH) + DELAY - 'h1);
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: swrvr_dlib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// DP library
// 2:1 MUX WITH ENCODED SELECT
module dp_mux2es (dout, in0, in1, sel) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
reg [SIZE-1:0] dout ;
always @ (sel or in0 or in1)
begin
case (sel)
1'b1: dout = in1 ;
1'b0: dout = in0;
default:
begin
if (in0 == in1) begin
dout = in0;
end
else
dout = {SIZE{1'bx}};
end
endcase // case(sel)
end
endmodule // dp_mux2es
// ----------------------------------------------------------------------
// 4:1 MUX WITH DECODED SELECTS
module dp_mux4ds (dout, in0, in1, in2, in3,
sel0_l, sel1_l, sel2_l, sel3_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk4 ($one_cold ({sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [3:0] sel = {sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3)
case ({sel3_l,sel2_l,sel1_l,sel0_l})
4'b1110 : dout = in0 ;
4'b1101 : dout = in1 ;
4'b1011 : dout = in2 ;
4'b0111 : dout = in3 ;
4'b1111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux4ds
// ----------------------------------------------------------------------
// 5:1 MUX WITH DECODED SELECTS
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk5 ($one_cold ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
in0 or in1 or in2 or in3 or in4)
case ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
5'b11110 : dout = in0 ;
5'b11101 : dout = in1 ;
5'b11011 : dout = in2 ;
5'b10111 : dout = in3 ;
5'b01111 : dout = in4 ;
5'b11111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux5ds
// --------------------------------------------------------------------
// 8:1 MUX WITH DECODED SELECTS
module dp_mux8ds (dout, in0, in1, in2, in3,
in4, in5, in6, in7,
sel0_l, sel1_l, sel2_l, sel3_l,
sel4_l, sel5_l, sel6_l, sel7_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input [SIZE-1:0] in5;
input [SIZE-1:0] in6;
input [SIZE-1:0] in7;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
input sel5_l;
input sel6_l;
input sel7_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk8 ($one_cold ({sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
sel4_l or sel5_l or sel6_l or sel7_l or in4 or in5 or in6 or in7)
case ({sel7_l,sel6_l,sel5_l,sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
8'b11111110 : dout = in0 ;
8'b11111101 : dout = in1 ;
8'b11111011 : dout = in2 ;
8'b11110111 : dout = in3 ;
8'b11101111 : dout = in4 ;
8'b11011111 : dout = in5 ;
8'b10111111 : dout = in6 ;
8'b01111111 : dout = in7 ;
8'b11111111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux8ds
// ----------------------------------------------------------------------
// 3:1 MUX WITH DECODED SELECTS
module dp_mux3ds (dout, in0, in1, in2,
sel0_l, sel1_l, sel2_l);
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0_l;
input sel1_l;
input sel2_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk3 ($one_cold ({sel2_l,sel1_l,sel0_l}));
`endif
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
case ({sel2_l,sel1_l,sel0_l})
3'b110 : dout = in0 ;
3'b101 : dout = in1 ;
3'b011 : dout = in2 ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux3ds
// ----------------------------------------------------------------------
module dp_buffer(dout, in);
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in;
assign dout = in;
endmodule // dp_buffer
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:35:55 11/19/2013
// Design Name:
// Module Name: sounds_bank
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sounds_bank (
input lrck,
input c_pad_sync,
input d_pad_sync,
input e_pad_sync,
input f_pad_sync,
input g_pad_sync,
input play,
output[15:0] c_data_out,
output[15:0] d_data_out,
output[15:0] e_data_out,
output[15:0] f_data_out,
output[15:0] g_data_out
);
wire[15:0] sine_c, sine_d, sine_e, sine_f, sine_g;
nco_c gen_c (
.clk(lrck), // input clk
.sine(sine_c) // output [15 : 0] sine
);
mux2x1 mux_c (
.selector(play & c_pad_sync),
.data(sine_c),
.out(c_data_out)
);
nco_d gen_d (
.clk(lrck), // input clk
.sine(sine_d) // output [15 : 0] sine
);
mux2x1 mux_d (
.selector(play & d_pad_sync),
.data(sine_d),
.out(d_data_out)
);
nco_e gen_e (
.clk(lrck), // input clk
.sine(sine_e) // output [15 : 0] sine
);
mux2x1 mux_e (
.selector(play & e_pad_sync),
.data(sine_e),
.out(e_data_out)
);
nco_f gen_f (
.clk(lrck), // input clk
.sine(sine_f) // output [15 : 0] sine
);
mux2x1 mux_f (
.selector(play & f_pad_sync),
.data(sine_f),
.out(f_data_out)
);
nco_g gen_g (
.clk(lrck), // input clk
.sine(sine_g) // output [15 : 0] sine
);
mux2x1 mux_g (
.selector(play & g_pad_sync),
.data(sine_g),
.out(g_data_out)
);
endmodule
|
//# 19 inputs
//# 7 outputs
//# 6 D-type flipflops
//# 32 inverters
//# 179 gates (34 ANDs + 61 NANDs + 29 ORs + 55 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s510(GND,VDD,CK,cblank,cclr,cnt10,cnt13,cnt21,cnt261,cnt272,cnt283,
cnt284,cnt44,cnt45,cnt509,cnt511,cnt567,cnt591,csm,csync,john,pc,pclr,
pcnt12,pcnt17,pcnt241,pcnt27,pcnt6,vsync);
input GND,VDD,CK,john,cnt13,cnt21,cnt284,pcnt6,cnt261,cnt44,pcnt12,pcnt17,
cnt591,cnt45,cnt567,pcnt27,cnt283,cnt272,cnt10,cnt511,pcnt241,cnt509;
output csm,pclr,pc,cclr,vsync,cblank,csync;
wire st_5,II2,st_4,II3,st_3,II4,st_2,II5,st_1,II6,st_0,II7,II68,II67,II78,
II73,II61,II60,II59,II58,II57,II56,II69,II70,II554,II555,II591,II590,II594,
II595,II546,II547,II667,II666,II475,II474,II798,II799,II495,II494,II467,
II466,II462,II463,II130,II131,II567,II566,II483,II482,II530,II531,II486,
II487,II607,II606,II778,II779,II347,II346,II204,II205,II216,II217,II936_2,
II946_1,II946_2,II936_1,II1089_1,II1044_1,II943_1,II578,II1102_2,II675,
II1059_1,II671,II1071_1,II551,II1106_1,II1123_1,II663,II967_1,II498,
II1055_1,II570,II1062_1,II535,II598,II1120_1,II795,II618,II1116_1,II95,
II603,II950_2,II950_1,II455,II1102_1,II954_2,II587,II104,II1081_1,II543,
II490,II1106_2,II940_1,II1077_1,II539,II988_1,II694,II698,II1085_1,II787,
II954_1,II1081_2,II1116_2,II230,II1065_1,II232,II1113_1,II234,II1055_2,
II1085_2,II1038_1,II985_1,II914_1,II1068_1,II933_1,II958_1,II958_2,II642,
II924_2,II903_2,II478,II1092_1,II917_1,II458,II921_1,II909_1,II627,II962_2,
II1095_1,II506,II1099_1,II209,II917_2,II982_1,II559,II1074_1,II1095_2,
II970_1,II900_1,II207,II903_1,II742,II962_1,II975_1,II978_1,II747,II928_1,
II1110_1,II924_1,II731,II658,II814,II574,II511,II638,II739,II774,II390,
II583,II834,II563,II274,II810,II782,II870,II298,II710,II714,II326,II837,
II270,II615,II838,II872,II266,II877,II213,II278,II282,II823,II855,II867,
II841,II884,II861,II889,II827,II881,II899,II895,II821,II874,II863,II831,
II887,II259,II371;
dff DFF_0(CK,st_5,II2);
dff DFF_1(CK,st_4,II3);
dff DFF_2(CK,st_3,II4);
dff DFF_3(CK,st_2,II5);
dff DFF_4(CK,st_1,II6);
dff DFF_5(CK,st_0,II7);
not NOT_0(II68,cnt44);
not NOT_1(II67,cnt261);
not NOT_2(II78,cnt511);
not NOT_3(II73,cnt567);
not NOT_4(II61,st_0);
not NOT_5(II60,st_1);
not NOT_6(II59,st_2);
not NOT_7(II58,st_3);
not NOT_8(II57,st_4);
not NOT_9(II56,st_5);
not NOT_10(II69,pcnt12);
not NOT_11(II70,pcnt17);
not NOT_12(II554,II555);
not NOT_13(II591,II590);
not NOT_14(II594,II595);
not NOT_15(II546,II547);
not NOT_16(II667,II666);
not NOT_17(II475,II474);
not NOT_18(II798,II799);
not NOT_19(II495,II494);
not NOT_20(II467,II466);
not NOT_21(II462,II463);
not NOT_22(II130,II131);
not NOT_23(II567,II566);
not NOT_24(II483,II482);
not NOT_25(II530,II531);
not NOT_26(II486,II487);
not NOT_27(II607,II606);
not NOT_28(II778,II779);
not NOT_29(II347,II346);
not NOT_30(II204,II205);
not NOT_31(II216,II217);
and AND2_0(II936_2,cnt272,st_2);
and AND2_1(II946_1,cnt10,st_5);
and AND2_2(II946_2,john,st_4);
and AND2_3(II936_1,cnt591,II59);
and AND2_4(II1089_1,II59,II555);
and AND2_5(II1044_1,II70,cnt284);
and AND2_6(II943_1,II578,st_3);
and AND2_7(II1102_2,II56,II675);
and AND2_8(II1059_1,st_5,II671);
and AND2_9(II1071_1,II551,II671);
and AND2_10(II1106_1,II60,II551);
and AND2_11(II1123_1,II551,II663);
and AND2_12(II967_1,II498,II57);
and AND3_0(II1055_1,II570,st_0,st_2);
and AND2_13(II1062_1,II535,II598);
and AND2_14(II1120_1,II795,II618);
and AND2_15(II1116_1,II95,II603);
and AND2_16(II950_2,II463,cnt283);
and AND2_17(II950_1,II455,cnt45);
and AND2_18(II1102_1,st_5,II455);
and AND3_1(II954_2,cnt45,II587,II104);
and AND3_2(II1081_1,II543,II490,II58);
and AND2_19(II1106_2,II57,II543);
and AND2_20(II940_1,II495,II60);
and AND2_21(II1077_1,II104,II539);
and AND2_22(II988_1,II694,II698);
and AND2_23(II1085_1,II787,II130);
and AND3_3(II954_1,st_5,cnt509,II567);
and AND2_24(II1081_2,st_2,II483);
and AND2_25(II1116_2,II61,II230);
and AND2_26(II1065_1,II475,II232);
and AND2_27(II1113_1,st_4,II234);
and AND2_28(II1055_2,II58,II204);
and AND2_29(II1085_2,II61,II216);
or OR2_0(II1038_1,cnt21,st_0);
or OR2_1(II985_1,pcnt27,II73);
or OR2_2(II914_1,II60,II61);
or OR2_3(II1068_1,st_4,II590);
or OR2_4(II933_1,II57,II58);
or OR2_5(II958_1,II57,II59);
or OR2_6(II958_2,cnt284,II642);
or OR2_7(II924_2,II474,II666);
or OR2_8(II903_2,II58,II478);
or OR2_9(II1092_1,st_4,II478);
or OR3_0(II917_1,II458,II494,st_5);
or OR2_10(II921_1,II494,II570);
or OR2_11(II909_1,II466,II627);
or OR2_12(II962_2,II466,II78);
or OR2_13(II1095_1,cnt13,II506);
or OR2_14(II1099_1,II506,II209);
or OR2_15(II917_2,II482,II590);
or OR2_16(II982_1,II559,II487);
or OR2_17(II1074_1,II475,II546);
or OR2_18(II1095_2,II475,II578);
or OR2_19(II970_1,II495,II603);
or OR2_20(II900_1,II56,II207);
or OR2_21(II903_1,II606,II742);
or OR2_22(II962_1,II462,II73);
or OR2_23(II975_1,II531,II483);
or OR2_24(II978_1,II483,II747);
or OR2_25(II928_1,st_0,II530);
or OR2_26(II1110_1,II61,II530);
or OR2_27(II924_1,st_0,II731);
nand NAND2_0(II590,st_1,st_2);
nand NAND2_1(II458,st_3,st_1);
nand NAND2_2(II490,cnt284,pcnt17);
nand NAND2_3(II578,II61,st_1);
nand NAND2_4(II666,II61,st_3);
nand NAND2_5(II658,st_2,II58);
nand NAND3_0(II814,II58,cnt21,II595);
nand NAND2_6(II574,st_3,II57);
nand NAND2_7(II498,II511,II587);
nand NAND2_8(II638,II511,st_0);
nand NAND2_9(II642,II739,st_2);
nand NAND2_10(II474,II56,II57);
nand NAND2_11(II570,II458,II56);
nand NAND2_12(II598,cnt13,II56);
nand NAND2_13(II742,II56,st_0);
nand NAND2_14(II618,II69,cnt44);
nand NAND2_15(II478,II547,II739);
nand NAND2_16(II494,II57,II547);
nand NAND3_1(II774,st_5,II547,II458);
nand NAND2_17(II466,st_3,II535);
nand NAND2_18(II506,II535,II58);
nand NAND2_19(II566,II663,st_2);
nand NAND2_20(II104,II933_1,II56);
nand NAND2_21(II482,II58,II551);
nand NAND2_22(II390,st_0,II583);
nand NAND2_23(II834,II1068_1,II642);
nand NAND2_24(II698,II563,II59);
nand NAND2_25(II694,II795,II57);
nand NAND2_26(II274,II56,II667);
nand NAND2_27(II606,II95,II57);
nand NAND2_28(II346,II985_1,II463);
nand NAND3_2(II810,pcnt6,cnt284,II455);
nand NAND3_3(II782,II67,II559,II675);
nand NAND2_29(II230,II958_1,II958_2);
nand NAND2_30(II870,II1092_1,II566);
nand NAND2_31(II298,II539,II574);
nand NAND2_32(II710,II467,cnt10);
nand NAND2_33(II714,II1038_1,II567);
nand NAND2_34(pclr,II917_1,II917_2);
nand NAND2_35(II326,II982_1,II61);
nand NAND2_36(pc,II921_1,II837);
nand NAND2_37(II270,st_3,II615);
nand NAND2_38(II838,II1074_1,II530);
nand NAND3_4(II872,II1095_1,II1095_2,II774);
nand NAND2_39(II266,II970_1,st_1);
nand NAND3_5(II232,II962_1,II962_2,II810);
nand NAND4_0(cclr,II486,II877,II546,II390);
nand NAND4_1(II234,II213,II814,II710,II714);
nand NAND2_40(II278,II975_1,II60);
nand NAND2_41(II282,II978_1,st_1);
nand NAND3_6(II3,II903_1,II903_2,II823);
nand NAND3_7(vsync,II914_1,II855,II867);
nand NAND2_42(cblank,II928_1,II841);
nand NAND4_2(II4,II278,II274,II270,II266);
nand NAND3_8(II884,II1110_1,II861,II326);
nand NAND4_3(II5,II282,II889,II827,II298);
nand NAND3_9(csync,II924_1,II924_2,II881);
nand NAND3_10(II6,II909_1,II899,II895);
nand NAND2_43(II2,II900_1,II821);
nand NAND3_11(II874,II1099_1,II863,II831);
nand NAND3_12(II7,II778,II782,II887);
nor NOR2_0(II555,st_0,st_1);
nor NOR2_1(II587,st_1,st_2);
nor NOR2_2(II595,st_0,st_2);
nor NOR2_3(II511,st_3,st_5);
nor NOR2_4(II739,st_5,st_1);
nor NOR2_5(II627,pcnt241,II78);
nor NOR2_6(II547,II61,st_2);
nor NOR2_7(II675,II61,st_1);
nor NOR2_8(II535,II590,st_0);
nor NOR2_9(II671,II458,II59);
nor NOR2_10(II663,st_1,II58);
nor NOR2_11(II551,II61,II57);
nor NOR2_12(II583,II511,II60);
nor NOR2_13(II603,II61,II56);
nor NOR3_0(II799,II56,II58,II59);
nor NOR2_14(II209,II946_1,II946_2);
nor NOR2_15(II563,II578,II56);
nor NOR3_1(II795,st_3,st_2,II578);
nor NOR2_16(II95,II587,II591);
nor NOR2_17(II463,II458,II594);
nor NOR2_18(II131,II936_1,II936_2);
nor NOR2_19(II455,II554,II658);
nor NOR2_20(II559,II658,II56);
nor NOR2_21(II531,II574,II59);
nor NOR3_2(II787,II554,st_5,II574);
nor NOR2_22(II487,st_4,II498);
nor NOR2_23(II543,II742,II590);
nor NOR2_24(II747,II638,II1044_1);
nor NOR2_25(II539,II546,II60);
nor NOR2_26(II207,II595,II943_1);
nor NOR3_3(II779,II95,st_4,II638);
nor NOR2_27(II259,st_0,II967_1);
nor NOR2_28(II837,II487,II1071_1);
nor NOR2_29(II867,II834,II1089_1);
nor NOR2_30(II615,II475,st_2);
nor NOR2_31(II827,II531,II1062_1);
nor NOR2_32(csm,II555,II798);
nor NOR2_33(II213,II950_1,II950_2);
nor NOR3_4(II877,II1102_1,II1102_2,II551);
nor NOR2_34(II823,II259,II1059_1);
nor NOR2_35(II855,II615,st_3);
nor NOR2_36(II205,II563,II940_1);
nor NOR2_37(II841,II799,II1077_1);
nor NOR2_38(II371,II68,II988_1);
nor NOR2_39(II731,II583,II607);
nor NOR2_40(II217,II954_1,II954_2);
nor NOR2_41(II861,II1081_1,II1081_2);
nor NOR3_5(II889,II1116_1,II1116_2,II870);
nor NOR3_6(II881,II1106_1,II1106_2,II838);
nor NOR3_7(II899,II872,II347,II1123_1);
nor NOR2_42(II831,II371,II1065_1);
nor NOR2_43(II895,II884,II1120_1);
nor NOR2_44(II821,II1055_1,II1055_2);
nor NOR2_45(II863,II1085_1,II1085_2);
nor NOR2_46(II887,II874,II1113_1);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:21:30 02/22/2015
// Design Name:
// Module Name: Allign2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Allign2(
input [1:0] idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [1:0] modeout_Allign,
input operationout_Allign,
input NatLogFlagout_Allign,
input [7:0] difference_Allign,
input [7:0] InsTag_Allign,
input clock,
output reg [1:0] idle_Allign2,
output reg [35:0] cout_Allign2,
output reg [35:0] zout_Allign2,
output reg [31:0] sout_Allign2,
output reg [1:0] modeout_Allign2,
output reg operationout_Allign2,
output reg NatLogFlagout_Allign2,
output reg [7:0] InsTag_Allign2
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign[35];
assign z_exponent = zout_Allign[34:27] - 127;
assign z_mantissa = {zout_Allign[26:0]};
assign c_sign = cout_Allign[35];
assign c_exponent = cout_Allign[34:27] - 127;
assign c_mantissa = {cout_Allign[26:0]};
always @ (posedge clock)
begin
InsTag_Allign2 <= InsTag_Allign;
idle_Allign2 <= idle_Allign;
modeout_Allign2 <= modeout_Allign;
operationout_Allign2 <= operationout_Allign;
sout_Allign2 <= sout_Allign;
if (idle_Allign != put_idle) begin
if ($signed(c_exponent) > $signed(z_exponent)) begin
zout_Allign2[35] <= zout_Allign[35];
zout_Allign2[34:27] <= z_exponent + difference_Allign + 127;
zout_Allign2[26:0] <= z_mantissa >> difference_Allign;
zout_Allign2[0] <= z_mantissa[0] | z_mantissa[1];
cout_Allign2 <= cout_Allign;
end else if ($signed(c_exponent) <= $signed(z_exponent)) begin
cout_Allign2[35] <= cout_Allign[35];
cout_Allign2[34:27] <= c_exponent + difference_Allign + 127;
cout_Allign2[26:0] <= c_mantissa >> difference_Allign;
cout_Allign2[0] <= c_mantissa[0] | c_mantissa[1];
zout_Allign2 <= zout_Allign;
end
end
else begin
zout_Allign2 <= zout_Allign;
cout_Allign2 <= cout_Allign;
end
end
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_5 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_5;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4bb (
VPWR,
VGND,
Y ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
module scratch_pad(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
parameter PORTS = 8;
parameter WIDTH = 64;
parameter FRAGMENT_DEPTH = 512;
parameter REORDER_DEPTH = 32;
parameter REORDER_BITS = log2(REORDER_DEPTH-1) + 1;
parameter FIFO_DEPTH = REORDER_DEPTH;
parameter DEPTH = FRAGMENT_DEPTH * PORTS;
parameter ADDR_WIDTH = log2(DEPTH-1);
parameter PORTS_ADDR_WIDTH = log2(PORTS-1);
input rst;
input clk;
input [0:PORTS-1] rd_en;
input [0:PORTS-1] wr_en;
input [WIDTH*PORTS-1:0] d;
output reg [WIDTH*PORTS-1:0] q;
input [ADDR_WIDTH*PORTS-1:0] addr;
output [0:PORTS-1] full;
input [0:PORTS-1]stall;
output [0:PORTS-1]valid;
integer i, j;
reg r_rst;
always @(posedge clk)
r_rst <= rst;
//TODO: stall logic
reg [0:PORTS-1] r_full;
wire [0:PORTS-1] reorder_full, send_buffer_full, recv_min_full;
wire [0:PORTS-1] send_buffer_almost_full, recv_min_almost_full;
wire [0:PORTS-1]linked_fifo_full;
wire [0:PORTS-1]linked_fifo_almost_full;
always @* begin
r_full = reorder_full | linked_fifo_almost_full;
end
assign full = r_full;
always @(posedge clk) begin
/*
for(i=0;i<PORTS;i=i+1) begin
if(linked_fifo_full[i]) begin
$display("WARNING: %d:%m send cross bar full port %d", $time, i);
$display("full: %b", full);
$display("rd_en: %b", rd_en);
$display("wr_en: %b", wr_en);
//$finish;
end
end
for(i=0;i<PORTS;i=i+1) begin
if(full[i] && (rd_en[i] || wr_en[i])) begin
$display("ERROR: %d:%m OVERFLOW port %d", $time, i);
$finish;
end
end
for(i=0;i<PORTS;i=i+1) begin
if(send_buffer_almost_full[i]) begin
$display("WARNING: %d:%m send cross bar almost full port %d", $time, i);
$display("full signal: %b", full);
//$finish;
end
end
for(i=0;i<PORTS;i=i+1) begin
if(reorder_full[i] && $time > 3000) begin
$display("WARNING: %d:%m reorder full port %d", $time, i);
$finish;
end
end
*/
end
//input
//{data, address, memory port}
reg [WIDTH+ADDR_WIDTH-1:0] send_input_stage_data [0:PORTS-1];
always @*
for(i = 0; i < PORTS; i = i + 1) begin
for(j = 0; j < ADDR_WIDTH; j = j + 1)
send_input_stage_data[i][j] = addr[(PORTS-i-1)*(ADDR_WIDTH)+j];
for(j = 0; j < WIDTH; j = j + 1)
send_input_stage_data[i][j+ADDR_WIDTH] = d[(PORTS-i-1)*(WIDTH)+j];
end
//output
wire [WIDTH+REORDER_BITS-1:0] recv_reorder_stage_data [0:PORTS-1];
always @*
for(i = 0; i < PORTS; i = i + 1)
for(j = 0; j < WIDTH; j = j + 1)
q[(PORTS-i-1)*WIDTH+j] = recv_reorder_stage_data[i][j+REORDER_BITS];
//TODO: reorder queue
genvar g;
//{data, address, memory port,
reg [2+ADDR_WIDTH+WIDTH-1:0] send_reorder_stage_data[0:PORTS-1];
reg [0:PORTS-1] send_reorder_stage_data_valid;
reg [0:PORTS-1] send_reorder_stage_data_write;
reg [PORTS_ADDR_WIDTH-1:0] send_reorder_stage_data_addr_low[0:PORTS-1];
reg [ADDR_WIDTH-PORTS_ADDR_WIDTH-1:0] send_reorder_stage_data_addr_high[0:PORTS-1];
reg [WIDTH-1:0] send_reorder_stage_data_data[0:PORTS-1];
always @*
for(i = 0; i < PORTS; i = i + 1)begin
send_reorder_stage_data_valid[i] = send_reorder_stage_data[i][0];
send_reorder_stage_data_write[i] = send_reorder_stage_data[i][1];
send_reorder_stage_data_addr_low[i] = send_reorder_stage_data[i][PORTS_ADDR_WIDTH+1:2];
send_reorder_stage_data_addr_high[i] = send_reorder_stage_data[i][ADDR_WIDTH+1:PORTS_ADDR_WIDTH+2];
send_reorder_stage_data_data[i] = send_reorder_stage_data[i][WIDTH+ADDR_WIDTH+1: ADDR_WIDTH+2];
end
reg [WIDTH+REORDER_BITS-1:0]recv_min_stage_data[0:PORTS-1];
wire [0:PORTS-1] recv_min_stage_valid;
wire [REORDER_BITS-1:0] index_tag [0:PORTS-1];
generate for(g = 0; g < PORTS; g = g + 1) begin: generate_reorder
reorder_queue #(WIDTH+REORDER_BITS, REORDER_DEPTH) rq(r_rst, clk, rd_en[g], index_tag[g], reorder_full[g], recv_min_stage_valid[g], recv_min_stage_data[g], recv_reorder_stage_data[g], valid[g], stall[g]);
end
endgenerate
/*
always @(posedge clk) begin
if(generate_reorder[0].rq.wr_en) begin
$display("reorder end: %d", generate_reorder[0].rq.end_ptr);
$display("reorder begin: %d", generate_reorder[0].rq.beg_ptr);
$display("occupy_array: %b", generate_reorder[0].rq.occupency_array);
$display("occupency_array_d: %b", generate_reorder[0].rq.occupency_array_d);
$display("occupency_array_addr_a: %d", generate_reorder[0].rq.occupency_array_addr_a);
$display("wr_en: %b", generate_reorder[0].rq.wr_en);
end
end
*/
always @(posedge clk)begin
for(i = 0; i < PORTS; i = i + 1)begin
send_reorder_stage_data[i][0] <= rd_en[i] || wr_en[i];
send_reorder_stage_data[i][1] <= wr_en[i];
send_reorder_stage_data[i][ADDR_WIDTH+WIDTH+1:2] <= send_input_stage_data[i];
if(rd_en[i])
send_reorder_stage_data[i][2+REORDER_BITS+ADDR_WIDTH+PORTS_ADDR_WIDTH-1:ADDR_WIDTH+2] <= {index_tag[i], i[PORTS_ADDR_WIDTH-1:0]};
end
end
//TODO: buffer
wire [0:PORTS-1]linked_fifo_empty;
wire [0:PORTS-1]lf_empty_check;
assign send_buffer_almost_full = linked_fifo_full; //TODO: fix
reg [0:PORTS-1]linked_fifo_pop[0:3];
reg [PORTS_ADDR_WIDTH-1:0] request_routing [0:PORTS-1];
reg [PORTS_ADDR_WIDTH - 1:0] request_routing_check [0:PORTS - 1];
wire [WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH:0] send_buffer_stage_data[0:PORTS-1];
localparam LOG2_FIFO_DEPTH = log2(FIFO_DEPTH - 1);
wire [PORTS * LOG2_FIFO_DEPTH - 1:0] lf_count [0:PORTS - 1];
generate for(g = 0; g < PORTS; g = g + 1) begin: generate_buffer
linked_list_fifo #(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1, FIFO_DEPTH, PORTS, 1, 1, 0, 0) lf(r_rst, clk, send_reorder_stage_data_valid[g], send_reorder_stage_data_addr_low[g], linked_fifo_pop[0][g], request_routing[g],{send_reorder_stage_data_data[g], send_reorder_stage_data_addr_high[g], send_reorder_stage_data_write[g]}, send_buffer_stage_data[g],linked_fifo_empty[g],linked_fifo_full[g], lf_count[g],linked_fifo_almost_full[g], , request_routing_check[g], lf_empty_check[g]);
end
endgenerate
localparam COUNTER_LL_STAGES = 1;
localparam SEND_MIN_STAGES = 2;
reg [PORTS_ADDR_WIDTH-1:0] rr_counter;
reg [PORTS_ADDR_WIDTH-1:0] rr_counter_fat[0:PORTS - 1];
//reg [PORTS_ADDR_WIDTH-1:0] rr_counter_fat_pipeline[0:1][0:PORTS - 1];
reg [PORTS_ADDR_WIDTH-1:0] counter_pipeline[0:COUNTER_LL_STAGES + SEND_MIN_STAGES + 2*2*PORTS_ADDR_WIDTH];
initial begin
rr_counter = 0;
for(i = 0; i < PORTS; i = i + 1)
rr_counter_fat[i] = 0;
end
always @(posedge clk) begin
rr_counter <= rr_counter + 1;
for(i = 0; i < PORTS; i = i + 1)
rr_counter_fat[i] <= rr_counter_fat[i] + 1;
counter_pipeline[0] <= rr_counter;
for(i = 0; i < COUNTER_LL_STAGES + SEND_MIN_STAGES + 2*2*PORTS_ADDR_WIDTH; i = i + 1)
counter_pipeline[i+1] <= counter_pipeline[i];
/*
for(i = 0; i < PORTS; i = i + 1)
rr_counter_fat_pipeline[0][i] <= rr_counter_fat[i];
for(i = 0; i < 1; i = i + 1)
rr_counter_fat_pipeline[i + 1] <= rr_counter_fit_pipline[i];
*/
end
always @(posedge clk) begin
for(i = 0; i < PORTS; i = i + 1) begin
//request_routing[i] <= i ^ counter_pipeline[COUNTER_LL_STAGES - 1];
//request_routing[i] <= i ^ rr_counter;
//request_routing_check[i] <= i ^ rr_counter;
request_routing_check[i] <= i ^ rr_counter_fat[i];
request_routing[i] <= request_routing_check[i];
//request_routing[i] <= rr_counter_fat_pipeline[0][i];
end
end
initial linked_fifo_pop[0] = 0;
initial linked_fifo_pop[1] = 0;
initial linked_fifo_pop[2] = 0;
initial linked_fifo_pop[3] = 0;
always @(posedge clk)
linked_fifo_pop[0] <= ~lf_empty_check;
always @(posedge clk) begin
linked_fifo_pop[1] <= linked_fifo_pop[0];
linked_fifo_pop[2] <= linked_fifo_pop[1];
linked_fifo_pop[3] <= linked_fifo_pop[2];
end
//TODO: request MIN
reg [PORTS*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)-1:0]send_buffer_stage_data_1d;
reg [PORTS*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)-1:0]send_buffer_stage_data_1d_r[0:1];
always @* for(i = 0; i < PORTS; i = i + 1)
send_buffer_stage_data_1d[(i+1)*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1) - 1 -: WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1] = send_buffer_stage_data[i];
always @(posedge clk) begin
send_buffer_stage_data_1d_r[0] <= send_buffer_stage_data_1d;
send_buffer_stage_data_1d_r[1] <= send_buffer_stage_data_1d_r[0];
end
wire [PORTS*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)-1:0]send_min_stage_data_1d;
reg [0:PORTS-1] send_min_stage_write;
reg [ADDR_WIDTH-PORTS_ADDR_WIDTH-1:0] send_min_stage_addr[0:PORTS-1];
reg [WIDTH-1:0] send_min_stage_data[0:PORTS-1];
wire [0:PORTS-1] request_min_valid;
always @* for(i = 0; i < PORTS; i = i + 1) begin
send_min_stage_write[i] = send_min_stage_data_1d[i*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)];
send_min_stage_addr[i] = send_min_stage_data_1d[i*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)+ADDR_WIDTH-PORTS_ADDR_WIDTH -: ADDR_WIDTH-PORTS_ADDR_WIDTH];
send_min_stage_data[i] = send_min_stage_data_1d[(i+1)*(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1)-1 -: WIDTH];
end
reg[PORTS_ADDR_WIDTH-1:0]request_min_control;
always @* for(i = 0; i < PORTS_ADDR_WIDTH; i = i + 1)
request_min_control[PORTS_ADDR_WIDTH-i-1] = counter_pipeline[COUNTER_LL_STAGES + SEND_MIN_STAGES + 1+2*i][PORTS_ADDR_WIDTH-i-1];
omega_network_ff #(WIDTH+ADDR_WIDTH-PORTS_ADDR_WIDTH+1,PORTS)request_min(clk,linked_fifo_pop[3],send_buffer_stage_data_1d_r[1], request_min_valid, send_min_stage_data_1d, request_min_control);
//TODO: RAMs
wire [WIDTH-1:0] recv_memory_stage_data[0:PORTS-1];
reg [0:PORTS-1]recv_memory_stage_valid;
generate for(g = 0; g < PORTS; g = g + 1) begin: banks
simple_ram #(WIDTH, FRAGMENT_DEPTH) bank(clk, send_min_stage_write[g] && request_min_valid[g], send_min_stage_data[g], send_min_stage_addr[g], recv_memory_stage_data[g]);
end
endgenerate
always @(posedge clk)
recv_memory_stage_valid <= request_min_valid & ~send_min_stage_write;
reg [REORDER_BITS-1:0]recv_memory_stage_reorder[0:PORTS-1];
always @(posedge clk) for(i = 0; i < PORTS; i = i + 1) begin
recv_memory_stage_reorder[i] <= send_min_stage_data[i][REORDER_BITS+PORTS_ADDR_WIDTH-1:PORTS_ADDR_WIDTH];
end
//TODO: response MIN
wire [PORTS*(WIDTH+REORDER_BITS)-1:0] recv_memory_stage_1d;
generate for(g = 0; g < PORTS; g = g + 1) begin: memory_stage
assign recv_memory_stage_1d[(g+1)*(WIDTH+REORDER_BITS)-1 -: WIDTH+REORDER_BITS] = {recv_memory_stage_data[g], recv_memory_stage_reorder[g]};
end
endgenerate
reg [PORTS_ADDR_WIDTH-1:0] recv_min_control;
always @* for(i = 0; i < PORTS_ADDR_WIDTH; i = i + 1) begin
recv_min_control[PORTS_ADDR_WIDTH-i-1] = counter_pipeline[COUNTER_LL_STAGES + SEND_MIN_STAGES + 2+2*PORTS_ADDR_WIDTH+2*i][PORTS_ADDR_WIDTH-i-1];
end
wire [PORTS*(WIDTH+REORDER_BITS)-1:0]recv_min_stage_data_1d;
omega_network_ff #(WIDTH+REORDER_BITS,PORTS) response_min(clk, recv_memory_stage_valid, recv_memory_stage_1d, recv_min_stage_valid, recv_min_stage_data_1d, recv_min_control);
always @* for(i = 0; i < PORTS; i = i + 1) begin
recv_min_stage_data[i] = recv_min_stage_data_1d[(i+1)*(WIDTH+REORDER_BITS)-1 -: WIDTH+REORDER_BITS];
end
/*
always @(posedge clk) begin
if(linked_fifo_pop[0] != 0) begin
$display("linked_fifo_pop: %b", linked_fifo_pop[0]);
end
if(request_min_valid != 0) begin
$display("request_min_valid: %b", request_min_valid);
$display("send_min_stage_write: %b", send_min_stage_write);
$display("send_min_stage_addr: %d", send_min_stage_addr[0]);
$display("send_min_stage_data: %d", send_min_stage_data[0]);
end
if(recv_memory_stage_valid != 0) begin
$display("recv_memory_stage_valid: %b", recv_memory_stage_valid);
$display("reorder: %d", recv_memory_stage_reorder[0]);
end
if(recv_min_stage_valid != 0) begin
$display("recv_min_valid: %b", recv_min_stage_valid);
$display("data: %b", recv_min_stage_data[0][WIDTH+REORDER_BITS-1:REORDER_BITS]);
$display("reorder: %H", recv_min_stage_data[0][REORDER_BITS-1:0]);
end
if(valid != 0) begin
$display("valid: %b", valid);
end
end
*/
`include "log2.vh"
`include "constants.vh"
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter ve14d63 = 6000000,
parameter v2af3e8 = 4'hA,
parameter v98e11a = 4'h5
) (
input vclk,
output v7b511e,
output [3:0] v1469d9
);
localparam p2 = v2af3e8;
localparam p5 = v98e11a;
localparam p6 = ve14d63;
wire w0;
wire [0:3] w1;
wire [0:3] w3;
wire [0:3] w4;
wire w7;
wire w8;
wire w9;
wire w10;
assign v7b511e = w0;
assign v1469d9 = w1;
assign w9 = vclk;
assign w10 = vclk;
assign w10 = w9;
vfebcfe v14f857 (
.v9fb85f(w0)
);
v9b9118 #(
.vc5c8ea(p5)
) v7d370f (
.v1ef182(w4)
);
v9b9118 #(
.vc5c8ea(p2)
) v8f4039 (
.v1ef182(w3)
);
v952eda v06ea2a (
.v6833fd(w1),
.ve2616d(w3),
.v54ac99(w4),
.v2d3366(w8)
);
vbce541 #(
.va04f5d(p6)
) v69348d (
.v4642b6(w7),
.v6dda25(w9)
);
vbef3fc v778e1f (
.v3dc29f(w7),
.v4642b6(w8),
.v6dda25(w10)
);
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module v9b9118 #(
parameter vc5c8ea = 0
) (
output [3:0] v1ef182
);
localparam p0 = vc5c8ea;
wire [0:3] w1;
assign v1ef182 = w1;
v9b9118_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 4-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 4-bits generic constant (0-15)
//---------------------------------------------------
module v9b9118_v465065 #(
parameter VALUE = 0
) (
output [3:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module vbce541 #(
parameter va04f5d = 16777216
) (
input v6dda25,
output v4642b6
);
localparam p1 = va04f5d;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire w4;
wire w5;
assign v4642b6 = w0;
assign w5 = v6dda25;
assign w4 = w0;
vef98b5 #(
.vc5c8ea(p1)
) v4016e8 (
.ve70c2d(w3)
);
vd84ae0 v45b714 (
.v4642b6(w0),
.va89056(w2),
.v06bdfb(w3)
);
v97d607 v2299cf (
.v9e1c43(w2),
.ve556f1(w4),
.v6dda25(w5)
);
endmodule
//---------------------------------------------------
//-- sysclk_divN_24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- sysclk_divN_24bits: Generate a signal from the division of the system clock by N. (24-bits precision) (N = 2,3,4,..,0x1000000))
//---------------------------------------------------
//---- Top entity
module vef98b5 #(
parameter vc5c8ea = 1
) (
output [23:0] ve70c2d
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign ve70c2d = w1;
vef98b5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-k-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits k-1 constant (Input values: 1,2,...,h1000000). It returns the value input by the user minus 1. Outputs: 0,1,2,...,FFFFFF
//---------------------------------------------------
module vef98b5_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE-1;
endmodule
//---- Top entity
module vd84ae0 (
input [23:0] v06bdfb,
input [23:0] va89056,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:23] w4;
wire [0:23] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
wire [0:7] w11;
assign v4642b6 = w0;
assign w4 = v06bdfb;
assign w5 = va89056;
vb2762a vb6832a (
.v4642b6(w1),
.v715730(w8),
.vf191e6(w11)
);
vb2762a v302658 (
.v4642b6(w2),
.v715730(w7),
.vf191e6(w10)
);
vae245c v9196c7 (
.vcbab45(w0),
.v3ca442(w1),
.v0e28cb(w2),
.v033bf6(w3)
);
v6fef69 vb1e577 (
.v9804b7(w5),
.vd83cb2(w9),
.v243fb2(w10),
.va2a3a1(w11)
);
v6fef69 v62b64f (
.v9804b7(w4),
.vd83cb2(w6),
.v243fb2(w7),
.va2a3a1(w8)
);
vb2762a v9a65c6 (
.v4642b6(w3),
.v715730(w6),
.vf191e6(w9)
);
endmodule
//---------------------------------------------------
//-- comp2-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-24bit: Comparator of two 24-bit numbers
//---------------------------------------------------
//---- Top entity
module vb2762a (
input [7:0] v715730,
input [7:0] vf191e6,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w3 = v715730;
assign w4 = vf191e6;
v438230 v577a36 (
.v4642b6(w2),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w2)
);
v6bdcd9 v921a9f (
.vcc8c7c(w4),
.v651522(w7),
.v2cc41f(w8)
);
v6bdcd9 v8cfa4d (
.vcc8c7c(w3),
.v651522(w5),
.v2cc41f(w6)
);
v438230 vfc1765 (
.v4642b6(w1),
.v693354(w5),
.v5369cd(w7)
);
endmodule
//---------------------------------------------------
//-- comp2-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-8bit: Comparator of two 8-bit numbers
//---------------------------------------------------
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vae245c (
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v033bf6;
assign w1 = v0e28cb;
assign w2 = v3ca442;
assign vcbab45 = w4;
vba518e v19b5b0 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
vba518e vf3ef0f (
.v3ca442(w2),
.v0e28cb(w3),
.vcbab45(w4)
);
endmodule
//---------------------------------------------------
//-- AND3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6fef69 (
input [23:0] v9804b7,
output [7:0] vd83cb2,
output [7:0] v243fb2,
output [7:0] va2a3a1
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:23] w3;
assign v243fb2 = w0;
assign vd83cb2 = w1;
assign va2a3a1 = w2;
assign w3 = v9804b7;
v6fef69_v9a2a06 v9a2a06 (
.o1(w0),
.o2(w1),
.o0(w2),
.i(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-one-third: Split the 24-bits bus into three buses of the same size
//---------------------------------------------------
module v6fef69_v9a2a06 (
input [23:0] i,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v97d607 (
input v6dda25,
input ve556f1,
output [23:0] v9e1c43,
output ve37344
);
wire w0;
wire [0:23] w1;
wire [0:23] w2;
wire w3;
wire [0:23] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v9e1c43 = w4;
assign ve37344 = w5;
assign w4 = w1;
v5495b5 v5e4c9c (
.v782748(w0),
.vb02eea(w1),
.v15c6e6(w2),
.v6dda25(w3)
);
v9c4559 v62e821 (
.v005b83(w1),
.v53d485(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 24-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v5495b5 (
input v6dda25,
input v782748,
input [23:0] v15c6e6,
output [23:0] vb02eea
);
wire [0:23] w0;
wire [0:23] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign vb02eea = w0;
assign w1 = v15c6e6;
assign w8 = v6dda25;
assign w9 = v6dda25;
assign w10 = v6dda25;
assign w11 = v782748;
assign w12 = v782748;
assign w13 = v782748;
assign w9 = w8;
assign w10 = w8;
assign w10 = w9;
assign w12 = w11;
assign w13 = w11;
assign w13 = w12;
v6fef69 vad6f1d (
.v9804b7(w1),
.va2a3a1(w5),
.v243fb2(w6),
.vd83cb2(w7)
);
v33e50d vba7365 (
.v6d326e(w0),
.v77c6e9(w2),
.vf7d213(w3),
.vba04ee(w4)
);
vcf4344 v13ddeb (
.vc1f0d2(w2),
.vd85d4e(w5),
.v6dda25(w10),
.v782748(w13)
);
vcf4344 v08e1bd (
.vc1f0d2(w3),
.vd85d4e(w6),
.v6dda25(w9),
.v782748(w12)
);
vcf4344 v5c3b0f (
.vc1f0d2(w4),
.vd85d4e(w7),
.v6dda25(w8),
.v782748(w11)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x24: 24 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v33e50d (
input [7:0] vba04ee,
input [7:0] vf7d213,
input [7:0] v77c6e9,
output [23:0] v6d326e
);
wire [0:23] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
assign v6d326e = w0;
assign w1 = vf7d213;
assign w2 = v77c6e9;
assign w3 = vba04ee;
v33e50d_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2),
.i2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-one-third: Join the three buses into an 24-bits Bus
//---------------------------------------------------
module v33e50d_v9a2a06 (
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [23:0] o
);
assign o = {i2, i1, i0};
endmodule
//---- Top entity
module vcf4344 (
input v6dda25,
input v782748,
input [7:0] vd85d4e,
output [7:0] vc1f0d2
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w2 = vd85d4e;
assign vc1f0d2 = w3;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v5c75f6 vbdef88 (
.v50034e(w0),
.v4de61b(w1),
.v6dda25(w7),
.v782748(w9)
);
v6bdcd9 vc95779 (
.v2cc41f(w1),
.vcc8c7c(w2),
.v651522(w4)
);
vafb28f v618315 (
.v3c88fc(w0),
.va9ac17(w3),
.v515fe7(w5)
);
v5c75f6 v6188f9 (
.v4de61b(w4),
.v50034e(w5),
.v6dda25(w6),
.v782748(w8)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x08: Eight D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v9c4559 #(
parameter v6c5139 = 1
) (
input [23:0] v005b83,
output v4642b6,
output [23:0] v53d485
);
localparam p1 = v6c5139;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
assign v4642b6 = w0;
assign w2 = v005b83;
assign v53d485 = w3;
v44c099 #(
.vd73390(p1)
) v8c0045 (
.v4642b6(w0),
.vd90f46(w2),
.v8826c0(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-24bit: Increment a 24-bits number by one
//---------------------------------------------------
//---- Top entity
module v44c099 #(
parameter vd73390 = 0
) (
input [23:0] vd90f46,
output v4642b6,
output [23:0] v8826c0
);
localparam p1 = vd73390;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire [0:23] w4;
assign v4642b6 = w0;
assign v8826c0 = w2;
assign w3 = vd90f46;
v4c802f #(
.vc5c8ea(p1)
) ve78914 (
.v8513f7(w4)
);
v91404d v19ed8b (
.v4642b6(w0),
.vb5c06c(w2),
.v7959e8(w3),
.vb5a2f2(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-24bit: Adder of 24-bit operand and 24-bit constant
//---------------------------------------------------
//---- Top entity
module v4c802f #(
parameter vc5c8ea = 0
) (
output [23:0] v8513f7
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign v8513f7 = w1;
v4c802f_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits generic constant
//---------------------------------------------------
module v4c802f_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v91404d (
input [23:0] vb5a2f2,
input [23:0] v7959e8,
output v4642b6,
output [23:0] vb5c06c
);
wire w0;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
wire [0:15] w5;
wire [0:23] w6;
wire [0:15] w7;
wire [0:23] w8;
wire [0:15] w9;
wire [0:7] w10;
wire [0:23] w11;
wire [0:7] w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
assign v4642b6 = w4;
assign w6 = v7959e8;
assign w8 = vb5a2f2;
assign vb5c06c = w11;
vcb23aa v8e0bba (
.v4642b6(w0),
.v62bf25(w2),
.v39966a(w16),
.veb2f59(w17)
);
vc3c498 v917bbf (
.vb9cfc3(w0),
.veeaa8e(w1),
.v4642b6(w3),
.v45c6ee(w14),
.v20212e(w15)
);
v8cc49c v03c3e3 (
.vb334ae(w1),
.v2b8a97(w2),
.v14a530(w5)
);
vab13f0 v43653c (
.vb18564(w6),
.vf0a06e(w7),
.v5246f6(w17)
);
v306ca3 v177126 (
.v91b9c1(w7),
.vef5eee(w13),
.vd3ef3b(w15)
);
vab13f0 vf15711 (
.vb18564(w8),
.vf0a06e(w9),
.v5246f6(w16)
);
v306ca3 vf9ed57 (
.v91b9c1(w9),
.vef5eee(w12),
.vd3ef3b(w14)
);
vc3c498 vf0db78 (
.vb9cfc3(w3),
.v4642b6(w4),
.veeaa8e(w10),
.v45c6ee(w12),
.v20212e(w13)
);
va52e3b v67022b (
.vbf8961(w5),
.vf7d213(w10),
.v6d326e(w11)
);
endmodule
//---------------------------------------------------
//-- Adder-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-24bits: Adder of two operands of 24 bits
//---------------------------------------------------
//---- Top entity
module vcb23aa (
input [7:0] v39966a,
input [7:0] veb2f59,
output v4642b6,
output [7:0] v62bf25
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
assign w0 = veb2f59;
assign w1 = v39966a;
assign v62bf25 = w4;
assign v4642b6 = w5;
v6bdcd9 vd88c66 (
.vcc8c7c(w0),
.v651522(w9),
.v2cc41f(w10)
);
v6bdcd9 v26a0bb (
.vcc8c7c(w1),
.v651522(w7),
.v2cc41f(w8)
);
v25966b v9ea427 (
.v817794(w3),
.v4642b6(w6),
.v0550b6(w8),
.v24708e(w10)
);
vafb28f vc75346 (
.v515fe7(w2),
.v3c88fc(w3),
.va9ac17(w4)
);
va1ce30 v40c17f (
.v817794(w2),
.v4642b6(w5),
.vb9cfc3(w6),
.v0550b6(w7),
.v24708e(w9)
);
endmodule
//---------------------------------------------------
//-- Adder-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-8bits: Adder of two operands of 8 bits
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module va1ce30 (
input [3:0] v0550b6,
input [3:0] v24708e,
input vb9cfc3,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
assign w11 = vb9cfc3;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w13),
.v82de4f(w17)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w14),
.vda577d(w17),
.v3f8943(w18),
.v64d863(w19)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w12),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w12),
.v82de4f(w14)
);
vad119b v3599be (
.v4642b6(w0),
.v8e8a67(w2),
.v0ef266(w11),
.v27dec4(w16),
.v82de4f(w19)
);
endmodule
//---------------------------------------------------
//-- AdderC-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-4bits: Adder of two operands of 4 bits and Carry in
//---------------------------------------------------
//---- Top entity
module vc3c498 (
input [7:0] v45c6ee,
input [7:0] v20212e,
input vb9cfc3,
output v4642b6,
output [7:0] veeaa8e
);
wire w0;
wire w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
wire [0:3] w11;
assign w1 = vb9cfc3;
assign w2 = v45c6ee;
assign w3 = v20212e;
assign veeaa8e = w4;
assign v4642b6 = w7;
v6bdcd9 v8d795a (
.vcc8c7c(w3),
.v651522(w10),
.v2cc41f(w11)
);
v6bdcd9 v23dbc5 (
.vcc8c7c(w2),
.v651522(w8),
.v2cc41f(w9)
);
vafb28f vef3a58 (
.va9ac17(w4),
.v3c88fc(w5),
.v515fe7(w6)
);
va1ce30 v0ff71a (
.v4642b6(w0),
.vb9cfc3(w1),
.v817794(w5),
.v0550b6(w9),
.v24708e(w11)
);
va1ce30 v12f94f (
.vb9cfc3(w0),
.v817794(w6),
.v4642b6(w7),
.v0550b6(w8),
.v24708e(w10)
);
endmodule
//---------------------------------------------------
//-- AdderC-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-8bits: Adder of two operands of 8 bits and Carry in
//---------------------------------------------------
//---- Top entity
module v8cc49c (
input [7:0] vb334ae,
input [7:0] v2b8a97,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign v14a530 = w0;
assign w1 = v2b8a97;
assign w2 = vb334ae;
v8cc49c_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-half: Join the two same halves into an 16-bits Bus
//---------------------------------------------------
module v8cc49c_v9a2a06 (
input [7:0] i1,
input [7:0] i0,
output [15:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vab13f0 (
input [23:0] vb18564,
output [15:0] vf0a06e,
output [7:0] v5246f6
);
wire [0:23] w0;
wire [0:15] w1;
wire [0:7] w2;
assign w0 = vb18564;
assign vf0a06e = w1;
assign v5246f6 = w2;
vab13f0_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-16-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-16-8: Split the 24-bits bus into two buses of 16 and 8 wires
//---------------------------------------------------
module vab13f0_v9a2a06 (
input [23:0] i,
output [15:0] o1,
output [7:0] o0
);
assign o1 = i[23:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v306ca3 (
input [15:0] v91b9c1,
output [7:0] vef5eee,
output [7:0] vd3ef3b
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign w0 = v91b9c1;
assign vef5eee = w1;
assign vd3ef3b = w2;
v306ca3_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-half: Split the 16-bits bus into two buses of the same size
//---------------------------------------------------
module v306ca3_v9a2a06 (
input [15:0] i,
output [7:0] o1,
output [7:0] o0
);
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module va52e3b (
input [7:0] vf7d213,
input [15:0] vbf8961,
output [23:0] v6d326e
);
wire [0:15] w0;
wire [0:23] w1;
wire [0:7] w2;
assign w0 = vbf8961;
assign v6d326e = w1;
assign w2 = vf7d213;
va52e3b_v9a2a06 v9a2a06 (
.i0(w0),
.o(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-8-16 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-8-16: Join the two buses into an 24-bits Bus
//---------------------------------------------------
module va52e3b_v9a2a06 (
input [7:0] i1,
input [15:0] i0,
output [23:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vbef3fc #(
parameter v8bcde4 = 0
) (
input v6dda25,
input v3dc29f,
output v4642b6
);
localparam p1 = v8bcde4;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
assign w2 = v3dc29f;
assign w3 = v6dda25;
assign v4642b6 = w4;
assign w5 = w4;
v3676a0 vdebd76 (
.vcbab45(w0),
.v0e28cb(w5)
);
v22cb98 #(
.v5462c0(p1)
) v51de32 (
.v27dec4(w0),
.vd793aa(w2),
.ve4a668(w3),
.v4642b6(w4)
);
endmodule
//---------------------------------------------------
//-- Counter-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Counter-x01: 1-bit counter
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd2 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file bram_decoder.v when simulating
// the core, bram_decoder. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module bram_decoder(
clka,
addra,
douta
);
input clka;
input [4 : 0] addra;
output [12 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_3 #(
.C_ADDRA_WIDTH(5),
.C_ADDRB_WIDTH(5),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("bram_decoder.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(22),
.C_READ_DEPTH_B(22),
.C_READ_WIDTH_A(13),
.C_READ_WIDTH_B(13),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(22),
.C_WRITE_DEPTH_B(22),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(13),
.C_WRITE_WIDTH_B(13),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK video output
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: rk_video.v
//
module rk_video(
input clk50mhz,
output hr,
output vr,
output cce,
output [3:0] r,
output [3:0] g,
output [3:0] b,
input[3:0] line,
input[6:0] ichar,
input vsp,
input lten,
input rvv,
input videomode
);
reg[1:0] state;
reg[9:0] h_cnt;
reg[9:0] v_cnt;
reg[2:0] d_cnt;
reg[5:0] data;
wire[7:0] fdata;
assign hr = h_cnt >= 10'd478 && h_cnt < 10'd530 ? 1'b0 : 1'b1;
assign vr = v_cnt >= 10'd608 && v_cnt < 10'd614 ? 1'b0 : 1'b1;
assign cce = d_cnt==3'b000 && state==2'b01;
assign r = data[5] ? (videomode ? 4'b0011 : 4'b1000): 4'b0;
assign g = data[5] ? (videomode ? 4'b1000 : 4'b1000): 4'b0;
assign b = data[5] ? (videomode ? 4'b0011 : 4'b1000): 4'b0;
font from(.addra({ichar[6:0],line[2:0]}), .clka(clk50mhz), .douta(fdata));
always @(posedge clk50mhz)
begin
casex (state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b1x: state <= 2'b00;
endcase
if (state==2'b00) begin
if (d_cnt==3'b101) begin
data <= lten ? 6'h3F : vsp ? 6'b0 : fdata[5:0]^{6{rvv}};
end else
data <= {data[4:0],1'b0};
if (h_cnt+1'b1 == 10'd533) begin
h_cnt <= 0; d_cnt <= 0;
if (v_cnt+1'b1 == 10'd625 ) begin
v_cnt <= 0;
end else begin
v_cnt <= v_cnt+1'b1;
end
end else begin
h_cnt <= h_cnt+1'b1;
if (d_cnt+1'b1 == 3'b110) begin
d_cnt <= 0;
end else
d_cnt <= d_cnt+1'b1;
end
end
end
endmodule
|
//manages all the stuff needed to read and write to the flash ROM
module flash_manager(
clock, reset,
dots,
writemode,
wdata,
dowrite,
raddr,
frdata,
doread,
busy,
flash_data,
flash_address,
flash_ce_b,
flash_oe_b,
flash_we_b,
flash_reset_b,
flash_sts,
flash_byte_b,
fsmstate);
input reset, clock; //clock and reset
output [639:0] dots; //outputs to dot-matrix to help debug flash, not necessary
input writemode; //if true then we're in write mode, else we're in read mode
input [15:0] wdata; //data to be written
input dowrite; //putting this high tells the manager the data it has is new, write it
input [22:0] raddr; //address to read from
output[15:0] frdata; //data being read
reg[15:0] rdata;
input doread; //putting this high tells the manager to perform a read on the current address
output busy; //and an output to tell folks we're still working on the last thing
reg busy;
inout [15:0] flash_data; //direct passthrough from labkit to low-level modules (flash_int and test_fsm)
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b;
output flash_reset_b, flash_byte_b;
input flash_sts;
wire flash_busy; //except these, which are internal to the interface
wire[15:0] fwdata;
wire[15:0] frdata;
wire[22:0] address;
wire [1:0] op;
reg [1:0] mode;
wire fsm_busy;
reg[2:0] state; //210
output[11:0] fsmstate;
wire [7:0] fsmstateinv;
assign fsmstate = {state,flash_busy,fsm_busy,fsmstateinv[4:0],mode}; //for debugging only
//this guy takes care of /some/ of flash's tantrums
flash_int flash(reset, clock, op, address, fwdata, frdata, flash_busy, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b);
//and this guy takes care of the rest of its tantrums
test_fsm fsm (reset, clock, op, address, fwdata, frdata, flash_busy, dots, mode, fsm_busy, wdata, raddr, fsmstateinv);
parameter MODE_IDLE = 0;
parameter MODE_INIT = 1;
parameter MODE_WRITE = 2;
parameter MODE_READ = 3;
parameter HOME = 3'd0;
parameter MEM_INIT = 3'd1;
parameter MEM_WAIT = 3'd2;
parameter WRITE_READY= 3'd3;
parameter WRITE_WAIT = 3'd4;
parameter READ_READY = 3'd5;
parameter READ_WAIT = 3'd6;
always @ (posedge clock)
if(reset)
begin
busy <= 1;
state <= HOME;
mode <= MODE_IDLE;
end
else begin
case(state)
HOME://0 //we always start here
if(!fsm_busy)
begin
busy <= 0;
if(writemode)
begin
busy <= 1;
state <= MEM_INIT;
end
else
begin
busy <= 1;
state <= READ_READY;
end
end
else
mode <= MODE_IDLE;
MEM_INIT://1 //begin wiping the memory
begin
busy <= 1;
mode <= MODE_INIT;
if(fsm_busy) //to give the fsm a chance to raise its busy signal
state <= MEM_WAIT;
end
MEM_WAIT://2 //finished wiping
if(!fsm_busy)
begin
busy <= 0;
state<= WRITE_READY;
end
else
mode <= MODE_IDLE;
WRITE_READY://3 //waiting for data to write to flash
if(dowrite)
begin
busy <= 1;
mode <= MODE_WRITE;
end
else if(busy)
state <= WRITE_WAIT;
else if(!writemode)
state <= READ_READY;
WRITE_WAIT://4 //waiting for flash to finish writing
if(!fsm_busy)
begin
busy <= 0;
state <= WRITE_READY;
end
else
mode <= MODE_IDLE;
READ_READY://5 //ready to read data
if(doread)
begin
busy <= 1;
mode <= MODE_READ;
if(busy) //lets the fsm raise its busy level
state <= READ_WAIT;
end
else
busy <= 0;
READ_WAIT://6 //waiting for flash to give the data up
if(!fsm_busy)
begin
busy <= 0;
state <= READ_READY;
end
else
mode <= MODE_IDLE;
default: begin //should never happen...
state <= 3'd7;
end
endcase
end
endmodule |
`default_nettype none
module scheduler2_allocate_rsv_station #(
parameter P_ALU2_PRIORITY_LEVEL = 4'h0
)(
//Register
input wire iORDER_LOCK,
input wire iORDER_0_VALID,
input wire iORDER_0_EX_SYS_REG,
input wire iORDER_0_EX_SYS_LDST,
input wire iORDER_0_EX_LOGIC,
input wire iORDER_0_EX_SHIFT,
input wire iORDER_0_EX_ADDER,
input wire iORDER_0_EX_MUL,
input wire iORDER_0_EX_SDIV,
input wire iORDER_0_EX_UDIV,
input wire iORDER_0_EX_LDST,
input wire iORDER_0_EX_BRANCH,
input wire iORDER_1_VALID,
input wire iORDER_1_EX_SYS_REG,
input wire iORDER_1_EX_SYS_LDST,
input wire iORDER_1_EX_LOGIC,
input wire iORDER_1_EX_SHIFT,
input wire iORDER_1_EX_ADDER,
input wire iORDER_1_EX_MUL,
input wire iORDER_1_EX_SDIV,
input wire iORDER_1_EX_UDIV,
input wire iORDER_1_EX_LDST,
input wire iORDER_1_EX_BRANCH,
//RS-INFO
input wire [3:0] iRS1_COUNT,
input wire [3:0] iRS2_COUNT,
//Output
output wire oRS0_0_VALID,
output wire oRS1_0_VALID,
output wire oRS2_0_VALID,
output wire oRS3_0_VALID,
output wire oRS0_1_VALID,
output wire oRS1_1_VALID,
output wire oRS2_1_VALID,
output wire oRS3_1_VALID
);
//ALU1, 2
wire rs1_0_select;
wire rs1_1_select;
wire rs2_0_select;
wire rs2_1_select;
/*
reg b_alu_last;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_alu_last <= 1'b0;
end
else if(iRESET_SYNC)begin
b_alu_last <= 1'b0;
end
else begin
if(rs1_0_select)begin
b_alu_last <= 1'b0;
end
else if(rs2_0_select)begin
b_alu_last <= 1'b1;
end
else begin
b_alu_last <= b_alu_last;
end
end
end
*/
localparam PL_ALU_SEL_ALU1 = 1'h0;
localparam PL_ALU_SEL_ALU2 = 1'h1;
//[1]Valid bit, [0]0=Rs1/1=Rs2
function [1:0] func_alu_select;
//input func_alu_last;
input [3:0] func_alu1_cnt;
input [3:0] func_alu2_cnt;
input func_valid;
input func_ex_mul; //only ALU1
input func_ex_sdiv; //only ALU1
input func_ex_udiv; //only ALU1
input func_ex_logic;
input func_ex_shift;
input func_ex_adder;
input func_ex_sys_reg;
begin
if(!func_valid)begin
func_alu_select = 2'h0;
end
else begin
if(func_ex_mul || func_ex_sdiv || func_ex_udiv)begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU1};
end
else if(func_ex_logic || func_ex_shift || func_ex_adder || func_ex_sys_reg)begin
if(func_alu1_cnt < (func_alu2_cnt-P_ALU2_PRIORITY_LEVEL))begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU1};
end
else begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU2};
end
end
else begin
func_alu_select = 2'h0;
end
end
end
endfunction
wire pipe0_alu_valid;
wire pipe0_alu_valid_number;
assign {pipe0_alu_valid, pipe0_alu_valid_number} = func_alu_select(
iRS1_COUNT,
iRS2_COUNT,
(!iORDER_LOCK && iORDER_0_VALID),
iORDER_0_EX_MUL,
iORDER_0_EX_SDIV,
iORDER_0_EX_UDIV,
iORDER_0_EX_LOGIC,
iORDER_0_EX_SHIFT,
iORDER_0_EX_ADDER,
iORDER_0_EX_SYS_REG
);
wire pipe1_alu_valid;
wire pipe1_alu_valid_number;
assign {pipe1_alu_valid, pipe1_alu_valid_number} = func_alu_select(
iRS1_COUNT,
iRS2_COUNT,
(!iORDER_LOCK && iORDER_1_VALID),
iORDER_1_EX_MUL,
iORDER_1_EX_SDIV,
iORDER_1_EX_UDIV,
iORDER_1_EX_LOGIC,
iORDER_1_EX_SHIFT,
iORDER_1_EX_ADDER,
iORDER_1_EX_SYS_REG
);
//RS0
assign oRS0_0_VALID = !iORDER_LOCK && iORDER_0_VALID && iORDER_0_EX_BRANCH;
assign oRS0_1_VALID = !iORDER_LOCK && iORDER_1_VALID && iORDER_1_EX_BRANCH;
/*
//RS1
assign oRS1_0_VALID = !iORDER_LOCK && iORDER_0_VALID && (iORDER_0_EX_MUL || iORDER_0_EX_SDIV || iORDER_0_EX_UDIV || ((iRS1_COUNT < iRS2_COUNT)? iORDER_0_EX_LOGIC || iORDER_0_EX_SHIFT || iORDER_0_EX_ADDER || iORDER_0_EX_SYS_REG : 1'b0));
assign oRS1_1_VALID = !iORDER_LOCK && iORDER_1_VALID && (iORDER_1_EX_MUL || iORDER_1_EX_SDIV || iORDER_1_EX_UDIV || ((iRS1_COUNT < iRS2_COUNT)? iORDER_1_EX_LOGIC || iORDER_1_EX_SHIFT || iORDER_1_EX_ADDER || iORDER_1_EX_SYS_REG : 1'b0));
//RS2
assign oRS2_0_VALID = !iORDER_LOCK && iORDER_0_VALID && ((iRS1_COUNT < iRS2_COUNT)? 1'b0 : iORDER_0_EX_LOGIC || iORDER_0_EX_SHIFT || iORDER_0_EX_ADDER || iORDER_0_EX_SYS_REG);
assign oRS2_1_VALID = !iORDER_LOCK && iORDER_1_VALID && ((iRS1_COUNT < iRS2_COUNT)? 1'b0 : iORDER_1_EX_LOGIC || iORDER_1_EX_SHIFT || iORDER_1_EX_ADDER || iORDER_1_EX_SYS_REG);
*/
//RS1
assign oRS1_0_VALID = pipe0_alu_valid && (pipe0_alu_valid_number == PL_ALU_SEL_ALU1); //rs1_0_select;
assign oRS1_1_VALID = pipe1_alu_valid && (pipe1_alu_valid_number == PL_ALU_SEL_ALU1); //rs1_1_select;
//RS2
assign oRS2_0_VALID = pipe0_alu_valid && (pipe0_alu_valid_number == PL_ALU_SEL_ALU2); //rs2_0_select;
assign oRS2_1_VALID = pipe1_alu_valid && (pipe1_alu_valid_number == PL_ALU_SEL_ALU2); //rs2_1_select;
//RS3
assign oRS3_0_VALID = !iORDER_LOCK && iORDER_0_VALID && (iORDER_0_EX_LDST || iORDER_0_EX_SYS_LDST);
assign oRS3_1_VALID = !iORDER_LOCK && iORDER_1_VALID && (iORDER_1_EX_LDST || iORDER_1_EX_SYS_LDST);
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/23/07 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module OBUFT (O, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
input I, T;
bufif0 T1 (O, I, T);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
`define TV80_REFRESH
module tv80_core (/*AUTOARG*/
// Outputs
m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
ts, intcycle_n, IntE, stop,
// Inputs
reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
);
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input reset_n;
input clk;
input cen;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output iorq;
output no_read;
output write;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] dinst;
input [7:0] di;
output [7:0] dout;
output [6:0] mc;
output [6:0] ts;
output intcycle_n;
output IntE;
output stop;
reg m1_n;
reg iorq;
`ifdef TV80_REFRESH
reg rfsh_n;
`endif
reg halt_n;
reg busak_n;
reg [15:0] A;
reg [7:0] dout;
reg [6:0] mc;
reg [6:0] ts;
reg intcycle_n;
reg IntE;
reg stop;
parameter aNone = 3'b111;
parameter aBC = 3'b000;
parameter aDE = 3'b001;
parameter aXY = 3'b010;
parameter aIOA = 3'b100;
parameter aSP = 3'b101;
parameter aZI = 3'b110;
// Registers
reg [7:0] ACC, F;
reg [7:0] Ap, Fp;
reg [7:0] I;
`ifdef TV80_REFRESH
reg [7:0] R;
`endif
reg [15:0] SP, PC;
reg [7:0] RegDIH;
reg [7:0] RegDIL;
wire [15:0] RegBusA;
wire [15:0] RegBusB;
wire [15:0] RegBusC;
reg [2:0] RegAddrA_r;
reg [2:0] RegAddrA;
reg [2:0] RegAddrB_r;
reg [2:0] RegAddrB;
reg [2:0] RegAddrC;
reg RegWEH;
reg RegWEL;
reg Alternate;
// Help Registers
reg [15:0] TmpAddr; // Temporary address register
reg [7:0] IR; // Instruction register
reg [1:0] ISet; // Instruction set selector
reg [15:0] RegBusA_r;
reg [15:0] ID16;
reg [7:0] Save_Mux;
reg [6:0] tstate;
reg [6:0] mcycle;
reg last_mcycle, last_tstate;
reg IntE_FF1;
reg IntE_FF2;
reg Halt_FF;
reg BusReq_s;
reg BusAck;
reg ClkEn;
reg NMI_s;
reg INT_s;
reg [1:0] IStatus;
reg [7:0] DI_Reg;
reg T_Res;
reg [1:0] XY_State;
reg [2:0] Pre_XY_F_M;
reg NextIs_XY_Fetch;
reg XY_Ind;
reg No_BTR;
reg BTR_r;
reg Auto_Wait;
reg Auto_Wait_t1;
reg Auto_Wait_t2;
reg IncDecZ;
// ALU signals
reg [7:0] BusB;
reg [7:0] BusA;
wire [7:0] ALU_Q;
wire [7:0] F_Out;
// Registered micro code outputs
reg [4:0] Read_To_Reg_r;
reg Arith16_r;
reg Z16_r;
reg [3:0] ALU_Op_r;
reg Save_ALU_r;
reg PreserveC_r;
reg [2:0] mcycles;
// Micro code outputs
wire [2:0] mcycles_d;
wire [2:0] tstates;
reg IntCycle;
reg NMICycle;
wire Inc_PC;
wire Inc_WZ;
wire [3:0] IncDec_16;
wire [1:0] Prefix;
wire Read_To_Acc;
wire Read_To_Reg;
wire [3:0] Set_BusB_To;
wire [3:0] Set_BusA_To;
wire [3:0] ALU_Op;
wire Save_ALU;
wire PreserveC;
wire Arith16;
wire [2:0] Set_Addr_To;
wire Jump;
wire JumpE;
wire JumpXY;
wire Call;
wire RstP;
wire LDZ;
wire LDW;
wire LDSPHL;
wire iorq_i;
wire [2:0] Special_LD;
wire ExchangeDH;
wire ExchangeRp;
wire ExchangeAF;
wire ExchangeRS;
wire I_DJNZ;
wire I_CPL;
wire I_CCF;
wire I_SCF;
wire I_RETN;
wire I_BT;
wire I_BC;
wire I_BTR;
wire I_RLD;
wire I_RRD;
wire I_INRC;
wire SetDI;
wire SetEI;
wire [1:0] IMode;
wire Halt;
reg [15:0] PC16;
reg [15:0] PC16_B;
reg [15:0] SP16, SP16_A, SP16_B;
reg [15:0] ID16_B;
reg Oldnmi_n;
tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
(
.IR (IR),
.ISet (ISet),
.MCycle (mcycle),
.F (F),
.NMICycle (NMICycle),
.IntCycle (IntCycle),
.MCycles (mcycles_d),
.TStates (tstates),
.Prefix (Prefix),
.Inc_PC (Inc_PC),
.Inc_WZ (Inc_WZ),
.IncDec_16 (IncDec_16),
.Read_To_Acc (Read_To_Acc),
.Read_To_Reg (Read_To_Reg),
.Set_BusB_To (Set_BusB_To),
.Set_BusA_To (Set_BusA_To),
.ALU_Op (ALU_Op),
.Save_ALU (Save_ALU),
.PreserveC (PreserveC),
.Arith16 (Arith16),
.Set_Addr_To (Set_Addr_To),
.IORQ (iorq_i),
.Jump (Jump),
.JumpE (JumpE),
.JumpXY (JumpXY),
.Call (Call),
.RstP (RstP),
.LDZ (LDZ),
.LDW (LDW),
.LDSPHL (LDSPHL),
.Special_LD (Special_LD),
.ExchangeDH (ExchangeDH),
.ExchangeRp (ExchangeRp),
.ExchangeAF (ExchangeAF),
.ExchangeRS (ExchangeRS),
.I_DJNZ (I_DJNZ),
.I_CPL (I_CPL),
.I_CCF (I_CCF),
.I_SCF (I_SCF),
.I_RETN (I_RETN),
.I_BT (I_BT),
.I_BC (I_BC),
.I_BTR (I_BTR),
.I_RLD (I_RLD),
.I_RRD (I_RRD),
.I_INRC (I_INRC),
.SetDI (SetDI),
.SetEI (SetEI),
.IMode (IMode),
.Halt (Halt),
.NoRead (no_read),
.Write (write)
);
tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
(
.Arith16 (Arith16_r),
.Z16 (Z16_r),
.ALU_Op (ALU_Op_r),
.IR (IR[5:0]),
.ISet (ISet),
.BusA (BusA),
.BusB (BusB),
.F_In (F),
.Q (ALU_Q),
.F_Out (F_Out)
);
function [6:0] number_to_bitvec;
input [2:0] num;
begin
case (num)
1 : number_to_bitvec = 7'b0000001;
2 : number_to_bitvec = 7'b0000010;
3 : number_to_bitvec = 7'b0000100;
4 : number_to_bitvec = 7'b0001000;
5 : number_to_bitvec = 7'b0010000;
6 : number_to_bitvec = 7'b0100000;
7 : number_to_bitvec = 7'b1000000;
default : number_to_bitvec = 7'bx;
endcase // case(num)
end
endfunction // number_to_bitvec
function [2:0] mcyc_to_number;
input [6:0] mcyc;
begin
casez (mcyc)
7'b1zzzzzz : mcyc_to_number = 3'h7;
7'b01zzzzz : mcyc_to_number = 3'h6;
7'b001zzzz : mcyc_to_number = 3'h5;
7'b0001zzz : mcyc_to_number = 3'h4;
7'b00001zz : mcyc_to_number = 3'h3;
7'b000001z : mcyc_to_number = 3'h2;
7'b0000001 : mcyc_to_number = 3'h1;
default : mcyc_to_number = 3'h1;
endcase
end
endfunction
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
begin
case (mcycles)
1 : last_mcycle = mcycle[0];
2 : last_mcycle = mcycle[1];
3 : last_mcycle = mcycle[2];
4 : last_mcycle = mcycle[3];
5 : last_mcycle = mcycle[4];
6 : last_mcycle = mcycle[5];
7 : last_mcycle = mcycle[6];
default : last_mcycle = 1'bx;
endcase // case(mcycles)
case (tstates)
0 : last_tstate = tstate[0];
1 : last_tstate = tstate[1];
2 : last_tstate = tstate[2];
3 : last_tstate = tstate[3];
4 : last_tstate = tstate[4];
5 : last_tstate = tstate[5];
6 : last_tstate = tstate[6];
default : last_tstate = 1'bx;
endcase
end // always @ (...
always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
or XY_State or cen or last_tstate or mcycle)
begin
ClkEn = cen && ~ BusAck;
if (last_tstate)
T_Res = 1'b1;
else T_Res = 1'b0;
if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
((Set_Addr_To == aXY) ||
(mcycle[0] && IR == 8'b11001011) ||
(mcycle[0] && IR == 8'b00110110)))
NextIs_XY_Fetch = 1'b1;
else
NextIs_XY_Fetch = 1'b0;
if (ExchangeRp)
Save_Mux = BusB;
else if (!Save_ALU_r)
Save_Mux = DI_Reg;
else
Save_Mux = ALU_Q;
end // always @ *
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
PC <= #1 0; // Program Counter
A <= #1 0;
TmpAddr <= #1 0;
IR <= #1 8'b00000000;
ISet <= #1 2'b00;
XY_State <= #1 2'b00;
IStatus <= #1 2'b00;
mcycles <= #1 3'b000;
dout <= #1 8'b00000000;
ACC <= #1 8'hFF;
F <= #1 8'hFF;
Ap <= #1 8'hFF;
Fp <= #1 8'hFF;
I <= #1 0;
`ifdef TV80_REFRESH
R <= #1 0;
`endif
SP <= #1 16'hFFFF;
Alternate <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
Arith16_r <= #1 1'b0;
BTR_r <= #1 1'b0;
Z16_r <= #1 1'b0;
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
PreserveC_r <= #1 1'b0;
XY_Ind <= #1 1'b0;
end
else
begin
if (ClkEn == 1'b1 )
begin
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
mcycles <= #1 mcycles_d;
if (IMode != 2'b11 )
begin
IStatus <= #1 IMode;
end
Arith16_r <= #1 Arith16;
PreserveC_r <= #1 PreserveC;
if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
begin
Z16_r <= #1 1'b1;
end
else
begin
Z16_r <= #1 1'b0;
end
if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
begin
// mcycle == 1 && tstate == 1, 2, || 3
if (tstate[2] && wait_n == 1'b1 )
begin
`ifdef TV80_REFRESH
if (Mode < 2 )
begin
A[7:0] <= #1 R;
A[15:8] <= #1 I;
R[6:0] <= #1 R[6:0] + 1;
end
`endif
if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
begin
PC <= #1 PC16;
end
if (IntCycle == 1'b1 && IStatus == 2'b01 )
begin
IR <= #1 8'b11111111;
end
else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 )
begin
IR <= #1 8'b00000000;
TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
end
else
begin
IR <= #1 dinst;
end
ISet <= #1 2'b00;
if (Prefix != 2'b00 )
begin
if (Prefix == 2'b11 )
begin
if (IR[5] == 1'b1 )
begin
XY_State <= #1 2'b10;
end
else
begin
XY_State <= #1 2'b01;
end
end
else
begin
if (Prefix == 2'b10 )
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
ISet <= #1 Prefix;
end
end
else
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
end // if (tstate == 2 && wait_n == 1'b1 )
end
else
begin
// either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
if (mcycle[5] )
begin
XY_Ind <= #1 1'b1;
if (Prefix == 2'b01 )
begin
ISet <= #1 2'b01;
end
end
if (T_Res == 1'b1 )
begin
BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
if (Jump == 1'b1 )
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 DI_Reg;
PC[7:0] <= #1 TmpAddr[7:0];
end
else if (JumpXY == 1'b1 )
begin
A <= #1 RegBusC;
PC <= #1 RegBusC;
end else if (Call == 1'b1 || RstP == 1'b1 )
begin
A <= #1 TmpAddr;
PC <= #1 TmpAddr;
end
else if (last_mcycle && NMICycle == 1'b1 )
begin
A <= #1 16'b0000000001100110;
PC <= #1 16'b0000000001100110;
end
else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
begin
A[15:8] <= #1 I;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 I;
PC[7:0] <= #1 TmpAddr[7:0];
end
else
begin
case (Set_Addr_To)
aXY :
begin
if (XY_State == 2'b00 )
begin
A <= #1 RegBusC;
end
else
begin
if (NextIs_XY_Fetch == 1'b1 )
begin
A <= #1 PC;
end
else
begin
A <= #1 TmpAddr;
end
end // else: !if(XY_State == 2'b00 )
end // case: aXY
aIOA :
begin
if (Mode == 3 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
end
else if (Mode == 2 )
begin
// Duplicate I/O address on 8080
A[15:8] <= #1 DI_Reg;
end
else
begin
A[15:8] <= #1 ACC;
end
A[7:0] <= #1 DI_Reg;
end // case: aIOA
aSP :
begin
A <= #1 SP;
end
aBC :
begin
if (Mode == 3 && iorq_i == 1'b1 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
A[7:0] <= #1 RegBusC[7:0];
end
else
begin
A <= #1 RegBusC;
end
end // case: aBC
aDE :
begin
A <= #1 RegBusC;
end
aZI :
begin
if (Inc_WZ == 1'b1 )
begin
A <= #1 TmpAddr + 1;
end
else
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
end
end // case: aZI
default :
begin
A <= #1 PC;
end
endcase // case(Set_Addr_To)
end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
Save_ALU_r <= #1 Save_ALU;
ALU_Op_r <= #1 ALU_Op;
if (I_CPL == 1'b1 )
begin
// CPL
ACC <= #1 ~ ACC;
F[Flag_Y] <= #1 ~ ACC[5];
F[Flag_H] <= #1 1'b1;
F[Flag_X] <= #1 ~ ACC[3];
F[Flag_N] <= #1 1'b1;
end
if (I_CCF == 1'b1 )
begin
// CCF
F[Flag_C] <= #1 ~ F[Flag_C];
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 F[Flag_C];
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
if (I_SCF == 1'b1 )
begin
// SCF
F[Flag_C] <= #1 1'b1;
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 1'b0;
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
end // if (T_Res == 1'b1 )
if (tstate[2] && wait_n == 1'b1 )
begin
if (ISet == 2'b01 && mcycle[6] )
begin
IR <= #1 dinst;
end
if (JumpE == 1'b1 )
begin
PC <= #1 PC16;
end
else if (Inc_PC == 1'b1 )
begin
//PC <= #1 PC + 1;
PC <= #1 PC16;
end
if (BTR_r == 1'b1 )
begin
//PC <= #1 PC - 2;
PC <= #1 PC16;
end
if (RstP == 1'b1 )
begin
TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
//TmpAddr <= #1 (others =>1'b0);
//TmpAddr[5:3] <= #1 IR[5:3];
end
end
if (tstate[3] && mcycle[5] )
begin
TmpAddr <= #1 SP16;
end
if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) )
begin
if (IncDec_16[2:0] == 3'b111 )
begin
SP <= #1 SP16;
end
end
if (LDSPHL == 1'b1 )
begin
SP <= #1 RegBusC;
end
if (ExchangeAF == 1'b1 )
begin
Ap <= #1 ACC;
ACC <= #1 Ap;
Fp <= #1 F;
F <= #1 Fp;
end
if (ExchangeRS == 1'b1 )
begin
Alternate <= #1 ~ Alternate;
end
end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 )
if (tstate[3] )
begin
if (LDZ == 1'b1 )
begin
TmpAddr[7:0] <= #1 DI_Reg;
end
if (LDW == 1'b1 )
begin
TmpAddr[15:8] <= #1 DI_Reg;
end
if (Special_LD[2] == 1'b1 )
begin
case (Special_LD[1:0])
2'b00 :
begin
ACC <= #1 I;
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b01 :
begin
`ifdef TV80_REFRESH
ACC <= #1 R;
`else
ACC <= #1 0;
`endif
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b10 :
I <= #1 ACC;
`ifdef TV80_REFRESH
default :
R <= #1 ACC;
`else
default : ;
`endif
endcase
end
end // if (tstate == 3 )
if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
begin
if (Mode == 3 )
begin
F[6] <= #1 F_Out[6];
F[5] <= #1 F_Out[5];
F[7] <= #1 F_Out[7];
if (PreserveC_r == 1'b0 )
begin
F[4] <= #1 F_Out[4];
end
end
else
begin
F[7:1] <= #1 F_Out[7:1];
if (PreserveC_r == 1'b0 )
begin
F[Flag_C] <= #1 F_Out[0];
end
end
end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
if (T_Res == 1'b1 && I_INRC == 1'b1 )
begin
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
if (DI_Reg[7:0] == 8'b00000000 )
begin
F[Flag_Z] <= #1 1'b1;
end
else
begin
F[Flag_Z] <= #1 1'b0;
end
F[Flag_S] <= #1 DI_Reg[7];
F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
if (tstate[1] && Auto_Wait_t1 == 1'b0 )
begin
dout <= #1 BusB;
if (I_RLD == 1'b1 )
begin
dout[3:0] <= #1 BusA[3:0];
dout[7:4] <= #1 BusB[3:0];
end
if (I_RRD == 1'b1 )
begin
dout[3:0] <= #1 BusB[7:4];
dout[7:4] <= #1 BusA[3:0];
end
end
if (T_Res == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
Read_To_Reg_r[4] <= #1 Read_To_Reg;
if (Read_To_Acc == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 4'b0111;
Read_To_Reg_r[4] <= #1 1'b1;
end
end
if (tstate[1] && I_BT == 1'b1 )
begin
F[Flag_X] <= #1 ALU_Q[3];
F[Flag_Y] <= #1 ALU_Q[1];
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
end
if (I_BC == 1'b1 || I_BT == 1'b1 )
begin
F[Flag_P] <= #1 IncDecZ;
end
if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
begin
case (Read_To_Reg_r)
5'b10111 :
ACC <= #1 Save_Mux;
5'b10110 :
dout <= #1 Save_Mux;
5'b11000 :
SP[7:0] <= #1 Save_Mux;
5'b11001 :
SP[15:8] <= #1 Save_Mux;
5'b11011 :
F <= #1 Save_Mux;
default : ;
endcase
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
end // if (ClkEn == 1'b1 )
end // else: !if(reset_n == 1'b0 )
end
//-------------------------------------------------------------------------
//
// BC('), DE('), HL('), IX && IY
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
// Bus A / Write
RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
begin
RegAddrA_r <= #1 { XY_State[1], 2'b11 };
end
// Bus B
RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
begin
RegAddrB_r <= #1 { XY_State[1], 2'b11 };
end
// Address from register
RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] };
// Jump (HL), LD SP,HL
if ((JumpXY == 1'b1 || LDSPHL == 1'b1) )
begin
RegAddrC <= #1 { Alternate, 2'b10 };
end
if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) )
begin
RegAddrC <= #1 { XY_State[1], 2'b11 };
end
if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
begin
IncDecZ <= #1 F_Out[Flag_Z];
end
if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
begin
if (ID16 == 0 )
begin
IncDecZ <= #1 1'b0;
end
else
begin
IncDecZ <= #1 1'b1;
end
end
RegBusA_r <= #1 RegBusA;
end
end // always @ (posedge clk)
always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
begin
if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
RegAddrA = { Alternate, IncDec_16[1:0] };
else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
RegAddrA = { XY_State[1], 2'b11 };
else if (ExchangeDH == 1'b1 && tstate[3])
RegAddrA = { Alternate, 2'b10 };
else if (ExchangeDH == 1'b1 && tstate[4])
RegAddrA = { Alternate, 2'b01 };
else
RegAddrA = RegAddrA_r;
if (ExchangeDH == 1'b1 && tstate[3])
RegAddrB = { Alternate, 2'b01 };
else
RegAddrB = RegAddrB_r;
end // always @ *
always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
or tstate or wait_n)
begin
RegWEH = 1'b0;
RegWEL = 1'b0;
if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
(Save_ALU_r && (ALU_Op_r != 4'b0111)) )
begin
case (Read_To_Reg_r)
5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
begin
RegWEH = ~ Read_To_Reg_r[0];
RegWEL = Read_To_Reg_r[0];
end // UNMATCHED !!
default : ;
endcase // case(Read_To_Reg_r)
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
if (ExchangeDH && (tstate[3] || tstate[4]) )
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end
if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
case (IncDec_16[1:0])
2'b00 , 2'b01 , 2'b10 :
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end // UNMATCHED !!
default : ;
endcase
end
end // always @ *
always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
or RegBusB or Save_Mux or mcycle or tstate)
begin
RegDIH = Save_Mux;
RegDIL = Save_Mux;
if (ExchangeDH == 1'b1 && tstate[3] )
begin
RegDIH = RegBusB[15:8];
RegDIL = RegBusB[7:0];
end
else if (ExchangeDH == 1'b1 && tstate[4] )
begin
RegDIH = RegBusA_r[15:8];
RegDIL = RegBusA_r[7:0];
end
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
RegDIH = ID16[15:8];
RegDIL = ID16[7:0];
end
end
tv80_reg i_reg
(
.clk (clk),
.CEN (ClkEn),
.WEH (RegWEH),
.WEL (RegWEL),
.AddrA (RegAddrA),
.AddrB (RegAddrB),
.AddrC (RegAddrC),
.DIH (RegDIH),
.DIL (RegDIL),
.DOAH (RegBusA[15:8]),
.DOAL (RegBusA[7:0]),
.DOBH (RegBusB[15:8]),
.DOBL (RegBusB[7:0]),
.DOCH (RegBusC[15:8]),
.DOCL (RegBusC[7:0])
);
//-------------------------------------------------------------------------
//
// Buses
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
case (Set_BusB_To)
4'b0111 :
BusB <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusB_To[0] == 1'b1 )
begin
BusB <= #1 RegBusB[7:0];
end
else
begin
BusB <= #1 RegBusB[15:8];
end
end
4'b0110 :
BusB <= #1 DI_Reg;
4'b1000 :
BusB <= #1 SP[7:0];
4'b1001 :
BusB <= #1 SP[15:8];
4'b1010 :
BusB <= #1 8'b00000001;
4'b1011 :
BusB <= #1 F;
4'b1100 :
BusB <= #1 PC[7:0];
4'b1101 :
BusB <= #1 PC[15:8];
4'b1110 :
BusB <= #1 8'b00000000;
default :
BusB <= #1 8'h0;
endcase
case (Set_BusA_To)
4'b0111 :
BusA <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusA_To[0] == 1'b1 )
begin
BusA <= #1 RegBusA[7:0];
end
else
begin
BusA <= #1 RegBusA[15:8];
end
end
4'b0110 :
BusA <= #1 DI_Reg;
4'b1000 :
BusA <= #1 SP[7:0];
4'b1001 :
BusA <= #1 SP[15:8];
4'b1010 :
BusA <= #1 8'b00000000;
default :
BusA <= #1 8'h0;
endcase
end
end
//-------------------------------------------------------------------------
//
// Generate external control signals
//
//-------------------------------------------------------------------------
`ifdef TV80_REFRESH
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
rfsh_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) )
begin
rfsh_n <= #1 1'b0;
end
else
begin
rfsh_n <= #1 1'b1;
end
end
end
end // always @ (posedge clk or negedge reset_n)
`else // !`ifdef TV80_REFRESH
assign rfsh_n = 1'b1;
`endif
always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
or IntE_FF1 or di or iorq_i or mcycle or tstate)
begin
mc = mcycle;
ts = tstate;
DI_Reg = di;
halt_n = ~ Halt_FF;
busak_n = ~ BusAck;
intcycle_n = ~ IntCycle;
IntE = IntE_FF1;
iorq = iorq_i;
stop = I_DJNZ;
end
//-----------------------------------------------------------------------
//
// Syncronise inputs
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : sync_inputs
if (~reset_n)
begin
BusReq_s <= #1 1'b0;
INT_s <= #1 1'b0;
NMI_s <= #1 1'b0;
Oldnmi_n <= #1 1'b0;
end
else
begin
if (cen == 1'b1 )
begin
BusReq_s <= #1 ~ busrq_n;
INT_s <= #1 ~ int_n;
if (NMICycle == 1'b1 )
begin
NMI_s <= #1 1'b0;
end
else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
begin
NMI_s <= #1 1'b1;
end
Oldnmi_n <= #1 nmi_n;
end
end
end
//-----------------------------------------------------------------------
//
// Main state machine
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
mcycle <= #1 7'b0000001;
tstate <= #1 7'b0000001;
Pre_XY_F_M <= #1 3'b000;
Halt_FF <= #1 1'b0;
BusAck <= #1 1'b0;
NMICycle <= #1 1'b0;
IntCycle <= #1 1'b0;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
No_BTR <= #1 1'b0;
Auto_Wait_t1 <= #1 1'b0;
Auto_Wait_t2 <= #1 1'b0;
m1_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (T_Res == 1'b1 )
begin
Auto_Wait_t1 <= #1 1'b0;
end
else
begin
Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
end
Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
(I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
(I_BTR && (~ IR[4] || F[Flag_Z]));
if (tstate[2] )
begin
if (SetEI == 1'b1 )
begin
if (!NMICycle)
IntE_FF1 <= #1 1'b1;
IntE_FF2 <= #1 1'b1;
end
if (I_RETN == 1'b1 )
begin
IntE_FF1 <= #1 IntE_FF2;
end
end
if (tstate[3] )
begin
if (SetDI == 1'b1 )
begin
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
Halt_FF <= #1 1'b0;
end
if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
begin
m1_n <= #1 1'b1;
end
if (BusReq_s == 1'b1 && BusAck == 1'b1 )
begin
end
else
begin
BusAck <= #1 1'b0;
if (tstate[2] && wait_n == 1'b0 )
begin
end
else if (T_Res == 1'b1 )
begin
if (Halt == 1'b1 )
begin
Halt_FF <= #1 1'b1;
end
if (BusReq_s == 1'b1 )
begin
BusAck <= #1 1'b1;
end
else
begin
tstate <= #1 7'b0000010;
if (NextIs_XY_Fetch == 1'b1 )
begin
mcycle <= #1 7'b0100000;
Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
if (IR == 8'b00110110 && Mode == 0 )
begin
Pre_XY_F_M <= #1 3'b010;
end
end
else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) )
begin
mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
end
else if ((last_mcycle) ||
No_BTR == 1'b1 ||
(mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
begin
m1_n <= #1 1'b0;
mcycle <= #1 7'b0000001;
IntCycle <= #1 1'b0;
NMICycle <= #1 1'b0;
if (NMI_s == 1'b1 && Prefix == 2'b00 )
begin
NMICycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
end
else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
begin
IntCycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
else
begin
mcycle <= #1 { mcycle[5:0], mcycle[6] };
end
end
end
else
begin // verilog has no "nor" operator
if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
begin
tstate <= #1 { tstate[5:0], tstate[6] };
end
end
end
if (tstate[0])
begin
m1_n <= #1 1'b0;
end
end
end
end
always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
or RegBusA or RegBusC or SP or tstate)
begin
if (JumpE == 1'b1 )
begin
PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else if (BTR_r == 1'b1 )
begin
PC16_B = -2;
end
else
begin
PC16_B = 1;
end
if (tstate[3])
begin
SP16_A = RegBusC;
SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else
begin
// suspect that ID16 and SP16 could be shared
SP16_A = SP;
if (IncDec_16[3] == 1'b1)
SP16_B = -1;
else
SP16_B = 1;
end
if (IncDec_16[3])
ID16_B = -1;
else
ID16_B = 1;
ID16 = RegBusA + ID16_B;
PC16 = PC + PC16_B;
SP16 = SP16_A + SP16_B;
end // always @ *
always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
begin
Auto_Wait = 1'b0;
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
if (mcycle[0] )
begin
Auto_Wait = 1'b1;
end
end
end // always @ *
endmodule // T80
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// divide subcarrier frequency by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
/*
* NAME
* ----
*
* main.v - SPI slave, switch input, LED display
*
* DESCRIPTION
* -----------
*
* This module takes input from input switches (in_sw) and
* outputs them over the SPI (MISO pin).
* And the input it receives over the SPI is written to the
* external LEDs (led_ext).
*
* The following SPI settings used by this module:
*
* MSB first
* CPOL = 0
* CPHA = 0
* SS_L (enable on low)
*
* The slave select line (SS_L) is used in a somewhat unique way.
* On the cleared (enabled) to set (disabled) transition the
* new data is latched in to the register.
* This was done because in the other orientation it was impossible
* to determine when to initialize the data because ss_l was
* the same value when it is sampling/propagating.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module main(
input wire rst_l,
input wire ss_l,
input wire sclk,
input wire mosi,
output wire miso,
output wire [7:0] led_ext,
input wire [7:0] in_sw
);
GSR GSR_INST(.GSR(rst_l));
// N is the last offset of data that is transferred.
// Currently there are 8-bits (0 - 7).
// This could be changed to support 16 bits
// needed.
parameter N=7;
// provide user feedback for switch actuation
wire [N:0] n_in_sw; // negated version of in_sw, sw closed -> set
assign n_in_sw = ~(in_sw);
// read register and next read register
reg [N:0] r_reg;
wire [N:0] r_next;
// write register, for storing received data
reg [N:0] w_reg;
// store the received data on the external led's
assign led_ext = ~(w_reg); // invert so 0 -> off, 1 -> on
// ### main SPI control: sample, propagate ###
assign r_next = {r_reg[N-1:0], mosi_sample};
assign miso = r_reg[N] & ~(ss_l);
// SAMPLE
reg mosi_sample;
always @(posedge sclk) begin
mosi_sample <= mosi;
end
always @(negedge sclk or negedge rst_l) begin
if (~rst_l) begin
r_reg <= 8'b0;
w_reg <= 8'b0;
end else begin
if (ss_l) begin
// RESET
// reset when sclk falls while ss_l is high (disabled)
r_reg <= n_in_sw; // switch input
w_reg <= r_next; // update the write register with the last read
// use r_next (not r_reg) so we don't miss the last mosi (SAMPLE)
end else begin
// PROPAGATE
r_reg <= r_next;
//w_reg <= w_reg;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_2_V
`define SKY130_FD_SC_LS__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_2_V
`define SKY130_FD_SC_LS__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_2_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_a.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
`ifdef insert_emu_mux_inst_aa
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_aa = 1'b0;
wire sig_04_emux_s;
wire sig_04_vc_s;
assign sig_04_emux_s = emu_mux_inst_aa ? sig_04_vc_s : sig_04;
`endif
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
`ifdef insert_emu_mux_inst_aa
.port_aa_4(sig_04_emux_s),
`else
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
`endif
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
);
// End of Generated Instance Port Map for inst_aa
`ifdef insert_emu_mux_inst_ab
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ab = 1'b0;
wire sig_01_emux_s;
wire sig_01_vc_s;
wire [4:0] sig_13_emux_s;
wire [4:0] sig_13_vc_s;
wire [6:0] sig_14_emux_s;
wire [6:0] sig_14_vc_s;
assign sig_01_emux_s = emu_mux_inst_ab ? sig_01_vc_s : sig_01;
assign sig_13_emux_s = emu_mux_inst_ab ? sig_13_vc_s : sig_13;
assign sig_14_emux_s = emu_mux_inst_ab ? sig_14_vc_s : sig_14;
`endif
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
`ifdef insert_emu_mux_inst_ab
.port_ab_1(sig_01_emux_s),
`else
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
`endif
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
`ifdef insert_emu_mux_inst_ab
.sig_13(sig_13_emux_s),
`else
.sig_13(sig_13), // Create internal signal name
`endif
`ifdef insert_emu_mux_inst_ab
.sig_14(sig_14_emux_s)
`else
.sig_14(sig_14) // Multiline comment 1
`endif
);
// End of Generated Instance Port Map for inst_ab
`ifdef insert_emu_mux_inst_ac
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ac = 1'b0;
wire sig_02_3_emux_s;
wire sig_02_3_vc_s;
assign sig_02[3] = emu_mux_inst_ac ? sig_02_3_vc_s : sig_02_3_emux_s;
`endif
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
`ifdef insert_emu_mux_inst_ac
.port_ac_2(sig_02_3_emux_s)
`else
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
`endif
);
// End of Generated Instance Port Map for inst_ac
`ifdef insert_emu_mux_inst_ad
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ad = 1'b0;
wire sig_02_4_emux_s;
wire sig_02_4_vc_s;
assign sig_02[4] = emu_mux_inst_ad ? sig_02_4_vc_s : sig_02_4_emux_s;
`endif
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
`ifdef insert_emu_mux_inst_ad
.port_ad_2(sig_02_4_emux_s)
`else
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
`endif
);
// End of Generated Instance Port Map for inst_ad
`ifdef insert_emu_mux_inst_ae
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ae = 1'b0;
wire [1:0] sig_02_1_0_emux_s;
wire [1:0] sig_02_1_0_vc_s;
wire [4:3] sig_02_4_3_emux_s;
wire [4:3] sig_02_4_3_vc_s;
wire [3:0] sig_05_emux_s;
wire [3:0] sig_05_vc_s;
wire [3:0] sig_06_emux_s;
wire [3:0] sig_06_vc_s;
wire [5:0] sig_07_emux_s;
wire [5:0] sig_07_vc_s;
wire [8:2] sig_08_emux_s;
wire [8:2] sig_08_vc_s;
wire [6:0] sig_i_ae_emux_s;
wire [6:0] sig_i_ae_vc_s;
assign sig_02_1_0_emux_s = emu_mux_inst_ae ? sig_02_1_0_vc_s : sig_02[1:0];
assign sig_02_4_3_emux_s = emu_mux_inst_ae ? sig_02_4_3_vc_s : sig_02[4:3];
assign sig_05_emux_s = emu_mux_inst_ae ? sig_05_vc_s : sig_05;
assign sig_06_emux_s = emu_mux_inst_ae ? sig_06_vc_s : sig_06;
assign sig_07_emux_s = emu_mux_inst_ae ? sig_07_vc_s : sig_07;
assign sig_08_emux_s = emu_mux_inst_ae ? sig_08_vc_s : sig_08;
assign sig_i_ae_emux_s = emu_mux_inst_ae ? sig_i_ae_vc_s : sig_i_ae;
`endif
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
`ifdef insert_emu_mux_inst_ae
.port_ae_2[1:0](sig_02_1_0_emux_s),
`else
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated
`endif
`ifdef insert_emu_mux_inst_ae
.port_ae_2[4:3](sig_02_4_3_emux_s),
`else
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated
`endif
`ifdef insert_emu_mux_inst_ae
.port_ae_5(sig_05_emux_s),
`else
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
`endif
`ifdef insert_emu_mux_inst_ae
.port_ae_6(sig_06_emux_s),
`else
.port_ae_6(sig_06), // Conflicting definition (X2)
`endif
`ifdef insert_emu_mux_inst_ae
.sig_07(sig_07_emux_s),
`else
.sig_07(sig_07), // Conflicting definition, IN false!
`endif
`ifdef insert_emu_mux_inst_ae
.sig_08(sig_08_emux_s),
`else
.sig_08(sig_08), // VHDL intermediate needed (port name)
`endif
`ifdef insert_emu_mux_inst_ae
.sig_i_ae(sig_i_ae_emux_s),
`else
.sig_i_ae(sig_i_ae), // Input Bus
`endif
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - Clock divider
Description: This module decodes a 4-bit
little-endian number into signals for a seven
segment display
================================================*/
`timescale 100 ns / 1 ns
module sevseg_decoder(val, a, b, c, d, e, f, g);
input [3:0] val;
output reg a, b, c, d, e, f, g;
// Allow for common anode or cathode displays
parameter led_on = 1'b0;
parameter led_off = 1'b1;
// Only change if val changes
always @(val)
case (val)
4'h0: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'h1: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h2: begin
a = led_on;
b = led_on;
c = led_off;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'h3: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_off;
f = led_off;
g = led_on;
end
4'h4: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'h5: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_off;
f = led_on;
g = led_on;
end
4'h6: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h7: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h8: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h9: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'hA: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
4'hB: begin
a = led_off;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'hC: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'hD: begin
a = led_off;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'hE: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
default: begin
a = led_on;
b = led_off;
c = led_off;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_BLACKBOX_V
`define SKY130_FD_SC_HD__O32A_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_BLACKBOX_V
|
// cat $FILENAME
// grep -i integer $FILENAME | sed -r 's/^.*[^A-Za-z0-9_]([A-Za-z0-9_]+).*:.*:= *([A-F0-9#]*).*$/ parameter \1 = \2;/' | sed -r "s/16#(.*)#/'h\1/"
// grep -i integer $FILENAME | sed -r 's/^.*[^A-Za-z0-9_]([A-Za-z0-9_]+).*:.*:= *([A-F0-9#]*).*$/ .\1(\2),/' | sed -r "s/16#(.*)#/'h\1/"
`ifndef SkipSPIMaster
module SPI_Master ( Reset_n, Clk, CPOL_i, CPHA_i, LSBFE_i, SPPR_i,
SPR_i, SCK_o, MOSI_o, MISO_i, Transmission_o, Write_i, ReadNext_i,
Data_i, Data_o, FIFOFull_o, FIFOEmpty_o, ScanEnable_i, ScanClk_i,
ScanDataIn_i, ScanDataOut_o );
parameter DataWidth = 8;
parameter SPPRWidth = 3;
parameter SPRWidth = 3;
parameter FIFOReadWidth = 4;
parameter FIFOWriteWidth = 4;
input [(SPPRWidth-1):0] SPPR_i;
input [(SPRWidth-1):0] SPR_i;
input [(DataWidth-1):0] Data_i;
output [7:0] Data_o;
input Reset_n, Clk, CPOL_i, CPHA_i, LSBFE_i, MISO_i, Write_i, ReadNext_i,
ScanEnable_i, ScanClk_i, ScanDataIn_i;
output SCK_o, MOSI_o, Transmission_o, FIFOFull_o, FIFOEmpty_o, ScanDataOut_o;
parameter X = 3;
endmodule
`endif
`ifndef SkipI2CMaster
module i2c_master ( Reset_i, Clk_i, F100_400_n_i, Divider800_i,
StartProcess_i, ReceiveSend_n_i, Busy_o, ReadCount_i, FIFOReadNext_i,
FIFOWrite_i, FIFOEmpty_o, FIFOFull_o, Data_i, Data_o, ErrAck_i,
ErrBusColl_o, ErrFIFOFull_o, ErrGotNAck_o, ErrCoreBusy_o,
ErrFIFOEmpty_o, ErrCoreStopped_o, ErrDevNotPresent_o,
ErrReadCountZero_o, SDA_i, SDA_o, SCL_o, ScanEnable_i, ScanClk_i,
ScanDataIn_i, ScanDataOut_o );
parameter ReadCountWidth_g = 4;
parameter FIFOAddressWidth_g = 4;
parameter DividerWidth_g = 16;
input [(DividerWidth_g-1):0] Divider800_i;
input [(ReadCountWidth_g-1):0] ReadCount_i;
input [7:0] Data_i;
output [7:0] Data_o;
input Reset_i, Clk_i, F100_400_n_i, StartProcess_i, ReceiveSend_n_i,
FIFOReadNext_i, FIFOWrite_i, ErrAck_i, SDA_i, ScanEnable_i, ScanClk_i,
ScanDataIn_i;
output Busy_o, FIFOEmpty_o, FIFOFull_o, ErrBusColl_o, ErrFIFOFull_o,
ErrGotNAck_o, ErrCoreBusy_o, ErrFIFOEmpty_o, ErrCoreStopped_o,
ErrDevNotPresent_o, ErrReadCountZero_o, SDA_o, SCL_o, ScanDataOut_o;
endmodule
`endif
module onewire_master ( Clk, Reset, OWIn_i, OWOut_o,
OWReset_i, DeactivateOverdriveMode_i, SearchROM_i, ReadROM_i,
MatchROM_i, SkipROM_i, CondSearchROM_i, OverdriveSkipROM_i,
OverdriveMatchROM_i, CondReadROM_i, ResumeROM_i, WriteByte_i,
ReadByte_i, GetROMID_i, Data_i, Data_o, ROMIDsInArray_o, Noslaves_o,
ROMIDArrayToSmall_o, PDROut_o, Ready_o, ResetLowTime, ResetTime,
ResetWaitForDetectionDuration, ResetPrecenceIntervalDuration,
WRSlotHighDataTime, RDSlotSampleTime, SlotLowDataTime, SlotDuration,
RDSlotInitTime, ODResetLowTime, ODResetTime,
ODResetWaitForDetectionDuration, ODResetPrecenceIntervalDuration,
ODWRSlotHighDataTime, ODRDSlotSampleTime, ODSlotLowDataTime,
ODSlotDuration, ODRDSlotInitTime, ScanEnable_i, ScanClk_i,
ScanDataIn_i, ScanDataOut_o );
parameter ROMIDArraySize = 4;
parameter ROMIDIndexSize = 2;
parameter ROMIDByteIndexSize = 3;
parameter SearchCommand = 'hF0;
parameter CondSearchCommand = 'hEC;
parameter MatchCommand = 'h55;
parameter ReadCommand = 'h33;
parameter SkipCommand = 'hCC;
parameter OverdriveSkipCommand = 'h3C;
parameter OverdriveMatchCommand = 'h69;
parameter ConditionalReadCommand = 'h0F;
parameter ResumeCommand = 'hA5;
parameter TimerWidth = 16;
input [7:0] Data_i;
output [7:0] Data_o;
output [(ROMIDIndexSize-1):0] ROMIDsInArray_o;
input [(TimerWidth-1):0] ResetLowTime;
input [(TimerWidth-1):0] ResetTime;
input [(TimerWidth-1):0] ResetWaitForDetectionDuration;
input [(TimerWidth-1):0] ResetPrecenceIntervalDuration;
input [(TimerWidth-1):0] WRSlotHighDataTime;
input [(TimerWidth-1):0] RDSlotSampleTime;
input [(TimerWidth-1):0] SlotLowDataTime;
input [(TimerWidth-1):0] SlotDuration;
input [(TimerWidth-1):0] RDSlotInitTime;
input [(TimerWidth-1):0] ODResetLowTime;
input [(TimerWidth-1):0] ODResetTime;
input [(TimerWidth-1):0] ODResetWaitForDetectionDuration;
input [(TimerWidth-1):0] ODResetPrecenceIntervalDuration;
input [(TimerWidth-1):0] ODWRSlotHighDataTime;
input [(TimerWidth-1):0] ODRDSlotSampleTime;
input [(TimerWidth-1):0] ODSlotLowDataTime;
input [(TimerWidth-1):0] ODSlotDuration;
input [(TimerWidth-1):0] ODRDSlotInitTime;
input Clk, Reset, OWIn_i, OWReset_i, DeactivateOverdriveMode_i, SearchROM_i,
ReadROM_i, MatchROM_i, SkipROM_i, CondSearchROM_i, OverdriveSkipROM_i,
OverdriveMatchROM_i, CondReadROM_i, ResumeROM_i, WriteByte_i,
ReadByte_i, GetROMID_i, ScanEnable_i, ScanClk_i, ScanDataIn_i;
output OWOut_o, Noslaves_o, ROMIDArrayToSmall_o, PDROut_o, Ready_o,
ScanDataOut_o;
endmodule
module pwm_master ( Clk, Reset, Polarity_i, Input_i, Value_o, NewValue_o,
ScanEnable_i, ScanClk_i, ScanDataIn_i, ScanDataOut_o );
parameter Resolution_g = 12;
parameter CounterWidth_g = 20;
output [(Resolution_g-1):0] Value_o;
input Clk, Reset, Polarity_i, Input_i, ScanEnable_i, ScanClk_i, ScanDataIn_i;
output NewValue_o, ScanDataOut_o;
endmodule
module sent_master ( Clk, Reset, Chipselect_i, NumDatNibble_i, Input_i,
MinSync_i, Out_o, NewData_o, CrcOk_o, ScanEnable_i, ScanClk_i,
ScanDataIn_i, ScanDataOut_o );
parameter MaxDatNibble_g = 6;
parameter CountWidth_g = 16;
input [2:0] NumDatNibble_i; // width is RoundUp(Ld(MaxDatNibble_g))
input [(CountWidth_g-1):0] MinSync_i;
output [(MaxDatNibble_g*4+3):0] Out_o;
input Clk, Reset, Chipselect_i, Input_i, ScanEnable_i, ScanClk_i,
ScanDataIn_i;
output NewData_o, CrcOk_o, ScanDataOut_o;
endmodule
module spc_master ( Clk, Reset, Input_i, Start_i, NumDatNibble_i,
LengthTrigger_i, LengthTimeout_i, MinSync_i, Out_o, DataOut_o,
NewData_o, CrcOk_o, SPCReady_o, ScanEnable_i, ScanClk_i, ScanDataIn_i,
ScanDataOut_o );
parameter MaxDatNibble_g = 6;
parameter CountWidth_g = 16;
parameter TimeoutWidth_g = 16;
parameter UseTimeout_g = 1;
input [2:0] NumDatNibble_i; // width is RoundUp(Ld(MaxDatNibble_g))
input [(CountWidth_g-1):0] LengthTrigger_i;
input [(CountWidth_g-1):0] MinSync_i;
output [(MaxDatNibble_g*4+3):0] DataOut_o;
input [(TimeoutWidth_g-1):0] LengthTimeout_i;
input Clk, Reset, Input_i, Start_i, ScanEnable_i, ScanClk_i, ScanDataIn_i;
output Out_o, NewData_o, CrcOk_o, SPCReady_o, ScanDataOut_o;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sdc_controller.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Top level entity. ////
//// This core is based on the "sd card controller" project from ////
//// http://opencores.org/project,sdcard_mass_storage_controller ////
//// but has been largely rewritten. A lot of effort has been ////
//// made to make the core more generic and easily usable ////
//// with OSs like Linux. ////
//// - data transfer commands are not fixed ////
//// - data transfer block size is configurable ////
//// - multiple block transfer support ////
//// - R2 responses (136 bit) support ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sdc_controller(
// WISHBONE common
wb_clk_i,
wb_rst_i,
// WISHBONE slave
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
// WISHBONE master
m_wb_dat_o,
m_wb_dat_i,
m_wb_adr_o,
m_wb_sel_o,
m_wb_we_o,
m_wb_cyc_o,
m_wb_stb_o,
m_wb_ack_i,
m_wb_cti_o,
m_wb_bte_o,
//SD BUS
sd_cmd_dat_i,
sd_cmd_out_o,
sd_cmd_oe_o,
//card_detect,
sd_dat_dat_i,
sd_dat_out_o,
sd_dat_oe_o,
sd_clk_o_pad,
sd_clk_i_pad,
int_cmd,
int_data
);
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
//input card_detect;
input [7:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
output [2:0] m_wb_cti_o;
output [1:0] m_wb_bte_o;
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
input wire sd_clk_i_pad;
output int_cmd, int_data;
//SD clock
wire sd_clk_o; //Sd_clk used in the system
wire go_idle;
wire cmd_start_wb_clk;
wire cmd_start_sd_clk;
wire cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire [31:0] data_out_tx_fifo;
wire start_tx_fifo;
wire start_rx_fifo;
wire tx_fifo_empty;
wire tx_fifo_full;
wire rx_fifo_full;
wire sd_data_busy;
wire data_busy;
wire data_crc_ok;
wire rd_fifo;
wire we_fifo;
wire data_start_rx;
wire data_start_tx;
wire cmd_int_rst_wb_clk;
wire cmd_int_rst_sd_clk;
wire cmd_int_rst;
wire data_int_rst_wb_clk;
wire data_int_rst_sd_clk;
wire data_int_rst;
//wb accessible registers
wire [31:0] argument_reg_wb_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_wb_clk;
wire [15:0] timeout_reg_wb_clk;
wire [0:0] software_reset_reg_wb_clk;
wire [31:0] response_0_reg_wb_clk;
wire [31:0] response_1_reg_wb_clk;
wire [31:0] response_2_reg_wb_clk;
wire [31:0] response_3_reg_wb_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_wb_clk;
wire [15:0] controll_setting_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_enable_reg_wb_clk;
wire [`BLKCNT_W-1:0] block_count_reg_wb_clk;
wire [31:0] dma_addr_reg_wb_clk;
wire [7:0] clock_divider_reg_wb_clk;
wire [31:0] argument_reg_sd_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_sd_clk;
wire [15:0] timeout_reg_sd_clk;
wire [0:0] software_reset_reg_sd_clk;
wire [31:0] response_0_reg_sd_clk;
wire [31:0] response_1_reg_sd_clk;
wire [31:0] response_2_reg_sd_clk;
wire [31:0] response_3_reg_sd_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_sd_clk;
wire [15:0] controll_setting_reg_sd_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_sd_clk;
wire [2:0] data_int_status_reg_sd_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_sd_clk;
wire [2:0] data_int_enable_reg_sd_clk;
wire [`BLKCNT_W-1:0] block_count_reg_sd_clk;
wire [31:0] dma_addr_reg_sd_clk;
wire [7:0] clock_divider_reg_sd_clk;
sd_clock_divider clock_divider0(
.CLK (sd_clk_i_pad),
.DIVIDER (clock_divider_reg_sd_clk),
.RST (wb_rst_i),
.SD_CLK (sd_clk_o)
);
assign sd_clk_o_pad = sd_clk_o ;
sd_cmd_master sd_cmd_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.start_i (cmd_start_sd_clk),
.int_status_rst_i(cmd_int_rst_sd_clk),
.setting_o (cmd_setting),
.start_xfr_o (cmd_start_tx),
.go_idle_o (go_idle),
.cmd_o (cmd),
.response_i (cmd_response),
.crc_ok_i (cmd_crc_ok),
.index_ok_i (cmd_index_ok),
.busy_i (sd_data_busy),
.finish_i (cmd_finish),
//input card_detect,
.argument_i (argument_reg_sd_clk),
.command_i (command_reg_sd_clk),
.timeout_i (timeout_reg_sd_clk),
.int_status_o (cmd_int_status_reg_sd_clk),
.response_0_o (response_0_reg_sd_clk),
.response_1_o (response_1_reg_sd_clk),
.response_2_o (response_2_reg_sd_clk),
.response_3_o (response_3_reg_sd_clk)
);
sd_cmd_serial_host cmd_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0] | go_idle),
.setting_i (cmd_setting),
.cmd_i (cmd),
.start_i (cmd_start_tx),
.finish_o (cmd_finish),
.response_o (cmd_response),
.crc_ok_o (cmd_crc_ok),
.index_ok_o (cmd_index_ok),
.cmd_dat_i (sd_cmd_dat_i),
.cmd_out_o (sd_cmd_out_o),
.cmd_oe_o (sd_cmd_oe_o)
);
sd_data_master sd_data_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.start_tx_i (data_start_tx),
.start_rx_i (data_start_rx),
.d_write_o (d_write),
.d_read_o (d_read),
.start_tx_fifo_o (start_tx_fifo),
.start_rx_fifo_o (start_rx_fifo),
.tx_fifo_empty_i (tx_fifo_empty),
.tx_fifo_full_i (tx_fifo_full),
.rx_fifo_full_i (rx_fifo_full),
.xfr_complete_i (!data_busy),
.crc_ok_i (data_crc_ok),
.int_status_o (data_int_status_reg_sd_clk),
.int_status_rst_i (data_int_rst_sd_clk)
);
sd_data_serial_host sd_data_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.data_in (data_out_tx_fifo),
.rd (rd_fifo),
.data_out (data_in_rx_fifo),
.we (we_fifo),
.DAT_oe_o (sd_dat_oe_o),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i),
.blksize (block_size_reg_sd_clk),
.bus_4bit (controll_setting_reg_sd_clk[0]),
.blkcnt (block_count_reg_sd_clk),
.start ({d_read, d_write}),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
sd_fifo_filler sd_fifo_filler0(
.wb_clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.wbm_adr_o (m_wb_adr_o),
.wbm_we_o (m_wb_we_o),
.wbm_dat_o (m_wb_dat_o),
.wbm_dat_i (m_wb_dat_i),
.wbm_cyc_o (m_wb_cyc_o),
.wbm_stb_o (m_wb_stb_o),
.wbm_ack_i (m_wb_ack_i),
.en_rx_i (start_rx_fifo),
.en_tx_i (start_tx_fifo),
.adr_i (dma_addr_reg_sd_clk),
.sd_clk (sd_clk_o),
.dat_i (data_in_rx_fifo),
.dat_o (data_out_tx_fifo),
.wr_i (we_fifo),
.rd_i (rd_fifo),
.sd_empty_o (tx_fifo_empty),
.sd_full_o (rx_fifo_full),
.wb_empty_o (),
.wb_full_o (tx_fifo_full)
);
sd_data_xfer_trig sd_data_xfer_trig0 (
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.cmd_with_data_start_i (cmd_start_sd_clk & (command_reg_sd_clk[`CMD_WITH_DATA] != 2'b00)),
.r_w_i (command_reg_sd_clk[`CMD_WITH_DATA] == 2'b01),
.cmd_int_status_i (cmd_int_status_reg_sd_clk),
.start_tx_o (data_start_tx),
.start_rx_o (data_start_rx)
);
sd_controller_wb sd_controller_wb0(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_i (wb_adr_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.wb_ack_o (wb_ack_o),
.cmd_start (cmd_start),
.data_int_rst (data_int_rst),
.cmd_int_rst (cmd_int_rst),
.argument_reg (argument_reg_wb_clk),
.command_reg (command_reg_wb_clk),
.response_0_reg (response_0_reg_wb_clk),
.response_1_reg (response_1_reg_wb_clk),
.response_2_reg (response_2_reg_wb_clk),
.response_3_reg (response_3_reg_wb_clk),
.software_reset_reg (software_reset_reg_wb_clk),
.timeout_reg (timeout_reg_wb_clk),
.block_size_reg (block_size_reg_wb_clk),
.controll_setting_reg (controll_setting_reg_wb_clk),
.cmd_int_status_reg (cmd_int_status_reg_wb_clk),
.cmd_int_enable_reg (cmd_int_enable_reg_wb_clk),
.clock_divider_reg (clock_divider_reg_wb_clk),
.block_count_reg (block_count_reg_wb_clk),
.dma_addr_reg (dma_addr_reg_wb_clk),
.data_int_status_reg (data_int_status_reg_wb_clk),
.data_int_enable_reg (data_int_enable_reg_wb_clk)
);
//clock domain crossing regiters
//assign cmd_start_sd_clk = cmd_start_wb_clk;
//assign data_int_rst_sd_clk = data_int_rst_wb_clk;
//assign cmd_int_rst_sd_clk = cmd_int_rst_wb_clk;
//assign argument_reg_sd_clk = argument_reg_wb_clk;
//assign command_reg_sd_clk = command_reg_wb_clk;
//assign response_0_reg_wb_clk = response_0_reg_sd_clk;
//assign response_1_reg_wb_clk = response_1_reg_sd_clk;
//assign response_2_reg_wb_clk = response_2_reg_sd_clk;
//assign response_3_reg_wb_clk = response_3_reg_sd_clk;
//assign software_reset_reg_sd_clk = software_reset_reg_wb_clk;
//assign timeout_reg_sd_clk = timeout_reg_wb_clk;
//assign block_size_reg_sd_clk = block_size_reg_wb_clk;
//assign controll_setting_reg_sd_clk = controll_setting_reg_wb_clk;
//assign cmd_int_status_reg_wb_clk = cmd_int_status_reg_sd_clk;
//assign cmd_int_enable_reg_sd_clk = cmd_int_enable_reg_wb_clk;
//assign clock_divider_reg_sd_clk = clock_divider_reg_wb_clk;
//assign block_count_reg_sd_clk = block_count_reg_wb_clk;
//assign dma_addr_reg_sd_clk = dma_addr_reg_wb_clk;
//assign data_int_status_reg_wb_clk = data_int_status_reg_sd_clk;
//assign data_int_enable_reg_sd_clk = data_int_enable_reg_wb_clk;
edge_detect cmd_start_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_start), .rise(cmd_start_wb_clk), .fall());
edge_detect data_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(data_int_rst), .rise(data_int_rst_wb_clk), .fall());
edge_detect cmd_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_int_rst), .rise(cmd_int_rst_wb_clk), .fall());
monostable_domain_cross cmd_start_cross(wb_rst_i, wb_clk_i, cmd_start_wb_clk, sd_clk_o, cmd_start_sd_clk);
monostable_domain_cross data_int_rst_cross(wb_rst_i, wb_clk_i, data_int_rst_wb_clk, sd_clk_o, data_int_rst_sd_clk);
monostable_domain_cross cmd_int_rst_cross(wb_rst_i, wb_clk_i, cmd_int_rst_wb_clk, sd_clk_o, cmd_int_rst_sd_clk);
bistable_domain_cross #(32) argument_reg_cross(wb_rst_i, wb_clk_i, argument_reg_wb_clk, sd_clk_o, argument_reg_sd_clk);
bistable_domain_cross #(`CMD_REG_SIZE) command_reg_cross(wb_rst_i, wb_clk_i, command_reg_wb_clk, sd_clk_o, command_reg_sd_clk);
bistable_domain_cross #(32) response_0_reg_cross(wb_rst_i, sd_clk_o, response_0_reg_sd_clk, wb_clk_i, response_0_reg_wb_clk);
bistable_domain_cross #(32) response_1_reg_cross(wb_rst_i, sd_clk_o, response_1_reg_sd_clk, wb_clk_i, response_1_reg_wb_clk);
bistable_domain_cross #(32) response_2_reg_cross(wb_rst_i, sd_clk_o, response_2_reg_sd_clk, wb_clk_i, response_2_reg_wb_clk);
bistable_domain_cross #(32) response_3_reg_cross(wb_rst_i, sd_clk_o, response_3_reg_sd_clk, wb_clk_i, response_3_reg_wb_clk);
bistable_domain_cross software_reset_reg_cross(wb_rst_i, wb_clk_i, software_reset_reg_wb_clk, sd_clk_o, software_reset_reg_sd_clk);
bistable_domain_cross #(16) timeout_reg_cross(wb_rst_i, wb_clk_i, timeout_reg_wb_clk, sd_clk_o, timeout_reg_sd_clk);
bistable_domain_cross #(`BLKSIZE_W) block_size_reg_cross(wb_rst_i, wb_clk_i, block_size_reg_wb_clk, sd_clk_o, block_size_reg_sd_clk);
bistable_domain_cross #(16) controll_setting_reg_cross(wb_rst_i, wb_clk_i, controll_setting_reg_wb_clk, sd_clk_o, controll_setting_reg_sd_clk);
bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_status_reg_cross(wb_rst_i, sd_clk_o, cmd_int_status_reg_sd_clk, wb_clk_i, cmd_int_status_reg_wb_clk);
bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_enable_reg_cross(wb_rst_i, wb_clk_i, cmd_int_enable_reg_wb_clk, sd_clk_o, cmd_int_enable_reg_sd_clk);
bistable_domain_cross #(8) clock_divider_reg_cross(wb_rst_i, wb_clk_i, clock_divider_reg_wb_clk, sd_clk_i_pad, clock_divider_reg_sd_clk);
bistable_domain_cross #(`BLKCNT_W) block_count_reg_cross(wb_rst_i, wb_clk_i, block_count_reg_wb_clk, sd_clk_o, block_count_reg_sd_clk);
bistable_domain_cross #(32) dma_addr_reg_cross(wb_rst_i, wb_clk_i, dma_addr_reg_wb_clk, sd_clk_o, dma_addr_reg_sd_clk);
bistable_domain_cross #(`INT_DATA_SIZE) data_int_status_reg_cross(wb_rst_i, sd_clk_o, data_int_status_reg_sd_clk, wb_clk_i, data_int_status_reg_wb_clk);
bistable_domain_cross #(`INT_DATA_SIZE) data_int_enable_reg_cross(wb_rst_i, wb_clk_i, data_int_enable_reg_wb_clk, sd_clk_o, data_int_enable_reg_sd_clk);
assign m_wb_cti_o = 3'b000;
assign m_wb_bte_o = 2'b00;
assign int_cmd = |(cmd_int_status_reg_wb_clk & cmd_int_enable_reg_wb_clk);
assign int_data = |(data_int_status_reg_wb_clk & data_int_enable_reg_wb_clk);
assign m_wb_sel_o = 4'b1111;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_TB_V
`define SKY130_FD_SC_HD__DLXBN_TB_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxbn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hd__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V |
/*
** -----------------------------------------------------------------------------**
** clkios353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002-2006 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// Some placement constraints are in this file
module dcm333#(
parameter IOSTANDARD_SDRAM_DIFF = "DIFF_SSTL2_I",
parameter SLEW_SDRAM_DIFF = "SLOW"
)(
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
sdcl_fb,
xclk, // 60MHz for compressor
phsel, // additional phase control for SDRAM CLK
dcm_rst, // reset DCM phase
dcm_incdec, // variable phase control to adjust SDCLK so read DQS is aligned with sclk90/sclk270
dcm_en,
dcm_clk,
dcm_done,
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input sclk;
output xclk;
output SDCLK, SDNCLK;
input [1:0] phsel;
input sdcl_fb; // SuppressThisWarning Veditor UNUSED - was designed to use external pin sync (maybe still use it?)
input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done;
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire isdclk0, isdclk90, isdclk180, isdclk270;
wire ixclk;
// wire gsdclk; //used only for the feedback
wire isdclk;
reg dcm_done;
wire dcm_done_dcm; // single-cycle
assign isdclk=phsel[1]? (phsel[0]?isdclk270:isdclk180):(phsel[0]?isdclk90:isdclk0);
FD i_ixclk (.C(sclk), .D(!ixclk), .Q(ixclk));
BUFG i_xclk (.I(ixclk), .O(xclk));
// second - adjustable DCM. Will be adjusted so read DQS (dependent on SDCLK) will be aligned with sclk90/270
// maybe will need some delay as there is DLL in SDRAM and responce may be slow.
DCM #(
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (8.33333),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE ("LOW"),
.DUTY_CYCLE_CORRECTION ("TRUE"),
.PHASE_SHIFT (0),
.CLKOUT_PHASE_SHIFT ("VARIABLE")
) i_dcm2(
.CLKIN (sclk),
.CLKFB (isdclk90),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (dcm_clk),.DSSEN (1'b0),
// .CLK0 (isdclk0),
// .CLK90 (isdclk90),
// .CLK180 (isdclk180),
// .CLK270 (isdclk270),
.CLK0 (isdclk90),
.CLK90 (isdclk180),
.CLK180 (isdclk270),
.CLK270 (isdclk0),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE (dcm_done_dcm));
// BUFG i_gsdclk (.I(isdclk90), .O(gsdclk));
OBUFDS #(
.IOSTANDARD(IOSTANDARD_SDRAM_DIFF),
.SLEW(SLEW_SDRAM_DIFF))
i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
// OBUFDS i_SDCLK (.O(SDNCLK),.OB(SDCLK),.I(!isdclk));
// make dcm_done behave as dcm_ready
always @ (posedge dcm_clk or posedge dcm_rst)
if (dcm_rst) dcm_done <= 1'b1;
else if (dcm_en) dcm_done <=1'b0;
else if (dcm_done_dcm) dcm_done <=1'b1;
endmodule
module clockios353#(
parameter IOSTANDARD = "LVCMOS33"
)(
CLK0, // input clock pad - 120MHz
sclk0, // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge)
/*sclk90,*/ // global clock, 120MHz, phase=90 (strobe data write to sdram)
sclk180, // global clock, 120MHz, phase=180 (just to generate DQS :-( )
sclk270, // global clock, 120MHz, phase=270 (strobe data write to sdram)
iclk0, //before BUFG
dcmrst, //reset dcm
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input CLK0;
output sclk0,/*sclk90,*/sclk270,sclk180;
output iclk0;
input dcmrst; //reset dcm
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire iclk0;
wire isclk0, /*isclk90,*/ isclk270, isclk180;
IBUFG #(.IOSTANDARD(IOSTANDARD)) i_iclk0 (.I(CLK0), .O(iclk0));
// DCM - just 4 phases out
DCM #(
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(8.33333),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE")
) i_dcm1(
.CLKIN (iclk0),
.CLKFB (sclk0),
.RST (dcmrst), .PSEN (1'b0),.PSINCDEC (1'b0), .PSCLK (1'b0),.DSSEN (1'b0),
.CLK0 (isclk0),
.CLK90 (/*isclk90*/),
.CLK180 (isclk180),
.CLK270 (isclk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE ());
BUFG i_sclk0 (.I(isclk0),. O(sclk0));
// s-ynthesis attribute loc of i_sclk0 is "BUFGMUX0"
/* BUFG i_sclk90 (.I(isclk90), .O(sclk90)); */
// s-ynthesis attribute loc of i_sclk90 is "BUFGMUX1"
BUFG i_sclk180(.I(isclk180),.O(sclk180));
// s-ynthesis attribute loc of i_sclk180 is "BUFGMUX2"
BUFG i_sclk270(.I(isclk270),.O(sclk270));
// s-ynthesis attribute loc of i_sclk270 is "BUFGMUX3"
endmodule
|
/*
* cla_adder_4bit.v - 4 bit carry lookahead adder
*/
`include "cla_full_adder.v"
`ifndef _cla_adder_4bit
`define _cla_adder_4bit
module cla_adder_4bit(
input wire [3:0] a,
input wire [3:0] b,
input wire c_in,
output wire [3:0] s,
output wire c_out);
wire [4:0] c;
wire [3:0] g, p;
assign c[0] = c_in;
assign c_out = c[4];
cla_full_adder add0(.a(a[0]), .b(b[0]), .c(c[0]),
.g(g[0]), .p(p[0]), .s(s[0]));
assign c[1] = g[0] | (p[0] & c[0]);
cla_full_adder add1(.a(a[1]), .b(b[1]), .c(c[1]),
.g(g[1]), .p(p[1]), .s(s[1]));
/*assign c[2] = g[1] | (p[1] & c[1]);*/
assign c[2] = g[1] | (p[1] & (g[0] | (p[0] & c[0])));
cla_full_adder add2(.a(a[2]), .b(b[2]), .c(c[2]),
.g(g[2]), .p(p[2]), .s(s[2]));
/*assign c[3] = g[2] | (p[2] & c[2]);*/
assign c[3] = g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))));
cla_full_adder add3(.a(a[3]), .b(b[3]), .c(c[3]),
.g(g[3]), .p(p[3]), .s(s[3]));
/*assign c[4] = g[3] | (p[3] & c[3]);*/
assign c[4] = g[3] | (p[3] &
(g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))))));
endmodule
`endif
|
///////////////////////////////////////////////////////////////////
//=================================================================
// Copyright(c) Superion Technology Group Inc., 2015
// ALL RIGHTS RESERVED
// $Id: $
//=================================================================
//
// File name: : xlr8_fdiv.v
// Author : Steve Berg
// Description : Floating point divide unit.
//
//=================================================================
///////////////////////////////////////////////////////////////////
module xlr8_fdiv
#(parameter DENOM_W = 32,
parameter NUMER_W = 32,
parameter EXP_W = 8,
parameter FRAC_W = 23,
parameter QUOTI_W = 32,
parameter REMAI_W = DENOM_W)
(input logic clk,
input logic rst_n,
input logic clken,
input logic [DENOM_W-1:0] denom,
input logic [NUMER_W-1:0] numer,
input logic start, // start a new divide
output logic [QUOTI_W-1:0] q_out
// output logic [REMAI_W-1:0] remain, // FIXME: unused
// output logic quotient_val // result valid: one shot
);
localparam MANT_W = FRAC_W+1;
localparam QUO_W = MANT_W+3;
localparam CNT_W = $clog2(MANT_W+1);
// need to do full width subtracts
// localparam SUB_W = DIVISOR_W > NUMER_W ? DIVISOR_W : NUMER_W;
localparam SUB_W = 28; //MANT_W+1;
logic sign;
logic [EXP_W-1:0] exp_q;
logic [EXP_W-1:0] temp_exp;
logic [EXP_W-1:0] exp_numer;
logic [EXP_W-1:0] exp_denom;
logic [FRAC_W-1:0] frac_numer;
logic [FRAC_W-1:0] frac_denom;
logic [MANT_W-1:0] mant_numer;
logic [MANT_W-1:0] mant_denom;
logic [MANT_W-1:0] mant_q;
logic exp_numer_0;
logic exp_denom_0;
logic exp_numer_255;
logic exp_denom_255;
logic frac_numer_0;
logic frac_denom_0;
logic numer_nan;
logic denom_nan;
logic numer_inf;
logic denom_inf;
logic numer_0;
logic denom_0;
logic [CNT_W-1:0] cnt;
logic [CNT_W-1:0] cnt_nxt;
logic [MANT_W:0] q_rnd;
// logic [MANT_W-1:0] quotient_nxt;
logic [QUO_W:0] quotient;
logic [QUO_W:0] quotient_nxt;
logic bsy;
logic [MANT_W-1:0] divisor, divisor_nxt;
logic [MANT_W:0] dividend, dividend_nxt, dividend_mux;
logic quotient_val; // result valid: one shot
logic [QUO_W:0] q_adjst;
logic [EXP_W-1:0] exp_adjst;
assign exp_numer = numer[23 +: EXP_W];
assign exp_denom = denom[23 +: EXP_W];
assign frac_numer = numer[FRAC_W-1:0];
assign frac_denom = denom[FRAC_W-1:0];
assign mant_numer = {1'b1,numer[FRAC_W-1:0]};
assign mant_denom = {1'b1,denom[FRAC_W-1:0]};
//calculate and hold sign and exp for result
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
sign <= 1'b0;
temp_exp <= 8'h0;
end
else begin
sign <= numer[31]^denom[31]; //sign - calculate and hold
temp_exp <= exp_numer - exp_denom + 'd127; //result exponent
end
always_comb begin
exp_numer_0 = exp_numer == 0;
exp_denom_0 = exp_denom == 0;
exp_numer_255 = exp_numer == 8'hff;
exp_denom_255 = exp_denom == 8'hff;
frac_numer_0 = frac_numer == 0;
frac_denom_0 = frac_denom == 0;
numer_nan = (exp_numer_255) && !frac_numer_0;
denom_nan = (exp_denom_255) && !frac_denom_0;
numer_inf = (exp_numer_255) && frac_numer_0;
denom_inf = (exp_denom_255) && frac_denom_0;
numer_0 = exp_numer_0;
denom_0 = exp_denom_0;
end
// figure out special cases up front
// assuming no denormals! If exp of operand is zero, then input is zero
always_comb begin
// nan: divide by 0, either input is NAN, both inputs==0, both inputs==inf
if (numer_nan || denom_nan || (numer_0 && denom_0) || (numer_inf && denom_inf)) begin
q_out = 32'h7fffffff;
end
// inf
else if (numer_inf || denom_0) begin
q_out = {sign,8'hff,23'h0};
end
// zero
else if (numer_0 || denom_inf) begin
q_out = {sign,31'h0};
end
else begin
// q_out = {sign,exp_q,mant_q[FRAC_W-1:0]};
q_out = {sign,exp_adjst,q_rnd[FRAC_W-1:0]};
end
end // always_comb
logic [23:0] rslt;
logic brw; // borrow bit
always_comb begin: calc_nxt
{brw,rslt} = dividend - divisor;
dividend_mux = brw ? dividend : rslt;
dividend_nxt = dividend_mux << 1;
quotient_nxt = (brw) ? {quotient[26:0],1'b0} : {quotient[26:0],1'b1};
divisor_nxt = divisor;
cnt_nxt = cnt - 'd1;
bsy = |cnt;
end
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
cnt <= {CNT_W{1'b0}};
dividend <= {25{1'b0}};
divisor <= {MANT_W{1'b0}};
quotient <= {QUO_W{1'b0}};
// End of automatics
end
else begin
if (clken) begin
cnt <= start && !bsy ? SUB_W :
bsy ? cnt_nxt : cnt;
divisor <= start && !bsy ? mant_denom :
bsy ? divisor_nxt :
divisor;
dividend <= start && !bsy ? {1'b0, mant_numer} :
bsy ? dividend_nxt :
dividend;
quotient <= start && !bsy ? '0 :
bsy ? quotient_nxt :
quotient;
end
end // else: !if(!rst_n)
logic stcky, g, r;
logic [25:0] q_inc_g;
//adjust exponent & mantissa
always_comb begin
if (quotient >= 28'h8000000) begin
exp_adjst = temp_exp ;
// mant_q = q_rnd >> 1;
q_adjst = quotient >>1;
end
else begin
q_adjst = quotient;
exp_adjst = temp_exp-1;
end // else: !if(quotient >= 25'h1000000)
end // always_comb begin
//round
// always_comb begin
// stcky = quotient[0] || |dividend;
// g = quotient[2];
// r = quotient[1];
// q_inc_g = quotient[27:2] +1;
//
// q_rnd[0] = g&&!r&&!stcky ? 1'b0 : q_inc_g[1];
// q_rnd[24:1] = q_inc_g[25:2];
//
// end
always_comb begin
stcky = q_adjst[0] || |dividend;
g = q_adjst[2];
r = q_adjst[1];
q_inc_g = q_adjst[27:2] +1;
q_rnd[0] = g&&!r&&!stcky ? 1'b0 : q_inc_g[1];
q_rnd[24:1] = q_inc_g[25:2];
end
//mantissa/exp adjust needed for case when round
//increments an all 1 case?
// logic quo_gteq;
// assign quo_gteq = q_rnd >= 25'h1000000;
// always_comb begin
// if (q_rnd >= 25'h1000000) begin
// exp_q = temp_exp;
// exp_q = exp_adjst+1;
// mant_q = q_rnd >> 1;
// end
//
// else begin
// mant_q = q_rnd;
// exp_q = exp_adjst;
// end
// end
// always_comb begin
// quotient_val = bsy && (~|cnt_nxt);
// end
always_ff @(posedge clk) begin
quotient_val <= bsy && (~|cnt_nxt);
end
//`ifndef VERILATOR
// ERROR_quoti_w_ne_numer_w: assert property
// (@(posedge clk) disable iff (!rst_n)
// start |-> (NUMER_W == QUOTI_W))
// else $error("quotient width != numer width is unsupported");
// ERROR_numer_w_lt_denom_w: assert property
// (@(posedge clk) disable iff (!rst_n)
// start |-> (NUMER_W >= DENOM_W))
// else $error("numerator width has to be at least as big as denominator width");
//`endif // `ifndef VERILATOR
endmodule // xlr8_fdiv
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
(negb (andb b1 b2)).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. simpl. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(andb (andb b1 b2) b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => (mult (factorial n') n)
end.
Example test_factorial1: (factorial 3) = 6.
Proof. simpl. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. simpl. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. simpl. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
match m with | O => false | S m' => (ble_nat n m') end.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros m n o.
intros H1. intros H2.
rewrite -> H1. rewrite -> H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
simpl.
intros H.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [| n'].
simpl. reflexivity.
simpl. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros H.
intros b.
rewrite -> H. rewrite -> H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f: bool -> bool),
(forall (x: bool), f x = (negb x)) ->
forall (b: bool), f (f b) = b.
Proof.
intros f. intros H.
intros b.
rewrite -> H. rewrite -> H.
destruct b.
simpl. reflexivity.
simpl. reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
destruct c.
simpl. reflexivity.
simpl. intros H. inversion H.
simpl. intros H. rewrite -> H. reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive tnat: Type :=
| TO : tnat
| TZ : tnat -> tnat
| TP : tnat -> tnat.
Fixpoint tnat_inc (t: tnat) : tnat :=
match t with
| TO => TP TO
| TZ t' => TP t'
| TP t' => TZ (tnat_inc t')
end.
Fixpoint tnat_to_nat(t: tnat) : nat :=
match t with
| TO => 0
| TZ t' => (tnat_to_nat t') + (tnat_to_nat t')
| TP t' => S((tnat_to_nat t') + (tnat_to_nat t'))
end.
Example test_tnat_to_nat_1 : (tnat_to_nat (TZ (TZ (TP TO)))) = 4.
Proof. simpl. reflexivity. Qed.
Example test_tnat_to_nat_2 : (tnat_to_nat (TZ (TP (TP TO)))) = 6.
Proof. simpl. reflexivity. Qed.
Example test_tnat_to_nat_3 : (tnat_to_nat (TP (TZ (TP TO)))) = 5.
Proof. simpl. reflexivity. Qed.
Example test_tnat_to_nat_0 : (tnat_to_nat TO) = 0.
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/*
* Copyright (c) 2015, Ziliang Guo
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Wisconsin Robotics nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL WISCONSIN ROBOTICS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module camera_deserializer
(
fmc_la00p_i,
fmc_la00n_i,
fmc_la02p_i,
fmc_la02n_i,
fmc_la03p_i,
fmc_la03n_i,
fmc_la04p_i,
fmc_la04n_i,
fmc_la05p_i,
fmc_la05n_i,
fmc_la14p_i,
fmc_la14n_i,
fmc_la15p_i,
fmc_la15n_i,
fmc_la18p_i,
fmc_la18n_i,
fmc_la19p_i,
fmc_la19n_i,
fmc_la20p_i,
fmc_la20n_i,
fmc_la21p_i,
fmc_la21n_i,
init_camera,
reset_camera,
take_photo,
stop_photo,
cl_locked,
cl_clk_debug,
cl_rd_addr,
cl_data,
uart_cfg_busy,
uart_tx_start_debug,
capture_state_debug,
cmd_gen_state_debug,
counter_debug,
rx_data_debug,
sys_clk_250,
sys_clk_50,
rst
);
input fmc_la00p_i;
input fmc_la00n_i;
input fmc_la02p_i;
input fmc_la02n_i;
input fmc_la03p_i;
input fmc_la03n_i;
input fmc_la04p_i;
input fmc_la04n_i;
input fmc_la05p_i;
input fmc_la05n_i;
input fmc_la14p_i;
input fmc_la14n_i;
output fmc_la15p_i;
output fmc_la15n_i;
output fmc_la18p_i;
output fmc_la18n_i;
output fmc_la19p_i;
output fmc_la19n_i;
output fmc_la20p_i;
output fmc_la20n_i;
output fmc_la21p_i;
output fmc_la21n_i;
input init_camera;
input reset_camera;
input take_photo;
input stop_photo;
output cl_locked;
output [6:0] cl_clk_debug;
input [9:0] cl_rd_addr;
output [15:0] cl_data;
output uart_cfg_busy;
output uart_tx_start_debug;
output [2:0] capture_state_debug;
output [4:0] cmd_gen_state_debug;
output [3:0] counter_debug;
output [7:0] rx_data_debug;
input sys_clk_250;
input sys_clk_50;
input rst;
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 4 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire xclk;
wire [3:0] x_net;
wire ser_tfg;
wire ser_tc;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
wire bitslip;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
wire rx_bufpll_lckd;
wire not_bufpll_lckd;
wire rx_serdesstrobe;
wire rx_bufpll_clk_xn;
wire rx_bufg_x1;
wire [7:0] uart_rx_data;
wire [7:0] uart_tx_data;
wire uart_tx_start;
wire uart_tx_busy;
wire uart_rx_valid;
wire uart_rx_idle;
assign uart_tx_start_debug = uart_tx_start;
assign not_bufpll_lckd = ~rx_bufpll_lckd;
assign cl_clk_debug = clk_iserdes_data;
assign cl_locked = rx_bufpll_lckd;
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
camera_link_fmc_bridge camera_link_inst
(
.fmc_la00p_i(fmc_la00p_i),
.fmc_la00n_i(fmc_la00n_i),
.fmc_la02p_i(fmc_la02p_i),
.fmc_la02n_i(fmc_la02n_i),
.fmc_la03p_i(fmc_la03p_i),
.fmc_la03n_i(fmc_la03n_i),
.fmc_la04p_i(fmc_la04p_i),
.fmc_la04n_i(fmc_la04n_i),
.fmc_la05p_i(fmc_la05p_i),
.fmc_la05n_i(fmc_la05n_i),
.fmc_la14p_i(fmc_la14p_i),
.fmc_la14n_i(fmc_la14n_i),
.fmc_la15p_i(fmc_la15p_i),
.fmc_la15n_i(fmc_la15n_i),
.fmc_la18p_i(fmc_la18p_i),
.fmc_la18n_i(fmc_la18n_i),
.fmc_la19p_i(fmc_la19p_i),
.fmc_la19n_i(fmc_la19n_i),
.fmc_la20p_i(fmc_la20p_i),
.fmc_la20n_i(fmc_la20n_i),
.fmc_la21p_i(fmc_la21p_i),
.fmc_la21n_i(fmc_la21n_i),
.xclk(xclk),
.x(x_net),
.cc(4'd0),
.ser_tfg(ser_tfg),
.ser_tc(ser_tc)
);
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (11.000),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.x_clk(xclk),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.input_data(x_net),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
cameralink_parser cameralink_parser_inst
(
.take_photo(take_photo),
.reset_state(reset_camera),
.xdata(rxr),
.cl_clk(rx_bufg_x1),
.sys_clk(sys_clk_50),
.rst(rst),
.pixel_rd_addr(cl_rd_addr),
.pixel_rd_data(cl_data),
.capture_state_debug(capture_state_debug)
);
uart cl_uart
(
.clk(sys_clk_50),
.txd(uart_tx_data),
.tx_start(uart_tx_start),
.tx_busy(uart_tx_busy),
.tx_out(ser_tc),
.rxd(uart_rx_data),
.rx_valid(uart_rx_valid),
.rx_in(ser_tfg),
.rx_idle(uart_rx_idle)
);
camera_serial_command_generator camera_serial_command_generator_inst
(
.init_camera(init_camera),
.take_photo(take_photo),
.stop_photo(stop_photo),
.tx_data(uart_tx_data),
.tx_en(uart_tx_start),
.tx_busy(uart_tx_busy),
.rx_data(uart_rx_data),
.rx_done(uart_rx_valid),
.sys_clk_50(sys_clk_50),
.rst(reset_camera),
.busy(uart_cfg_busy),
.cmd_gen_state_debug(cmd_gen_state_debug),
.counter_debug(counter_debug),
.rx_data_debug(rx_data_debug)
);
endmodule |
module CenterMaze(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
//Screen is divided into 20 intervals of 32 pixels each in the x direction
always @(posedge clk_vga) begin
//From x == 0 to 63, inclusive
if((CurrentX >= 0 && CurrentX <=63) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 64 to 95, inclusive
else if( (CurrentX >= 64 && CurrentX <= 95) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 96 to 127, inclusive
else if( (CurrentX >= 96 && CurrentX <= 127) && (
(CurrentY <= 199) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 128 to 159, inclusive
else if( (CurrentX >= 128 && CurrentX <= 159) && (
(CurrentY >= 120 && CurrentY <= 199) ) )
mColor[7:0] <= wall;
//From x == 160 to 191, inclusive
else if( (CurrentX >= 160 && CurrentX <= 191) && (
(CurrentY <= 39) ||
(CurrentY >= 120) ) )
mColor[7:0] <= wall;
//From x == 192 to 223, inclusive
else if( (CurrentX >= 192 && CurrentX <= 223) && (
(CurrentY <= 39) ) )
mColor[7:0] <= wall;
//From x == 224 to 255, inclusive
else if( (CurrentX >= 224 && CurrentX <= 255) )
mColor[7:0] <= wall;
//From X == 256 to 287, inclusive
else if( (CurrentX >= 256 && CurrentX <= 287) && (
(CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 352 to 383, inclusive
else if( (CurrentX >= 352 && CurrentX <= 383) && (
(CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 384 to 415, inclusive
else if( (CurrentX >= 384 && CurrentX <= 415) )
mColor[7:0] <= wall;
//From x == 416 to 447, inclusive
else if( (CurrentX >= 416 && CurrentX <= 447) && (
(CurrentY <= 39) ) )
mColor[7:0] <= wall;
//From x == 448 to 479, inclusive
else if( (CurrentX >= 448 && CurrentX <= 479) && (
(CurrentY <= 39) ||
(CurrentY >= 120) ) )
mColor[7:0] <= wall;
//From x == 480 to 511, inclusive
else if( (CurrentX >= 480 && CurrentX <= 511) && (
(CurrentY >= 120 && CurrentY <= 199) ) )
mColor[7:0] <= wall;
//From x == 512 to 543, inclusive
else if( (CurrentX >= 512 && CurrentX <= 543) && (
(CurrentY <= 199) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 544 to 575, inclusive
else if( (CurrentX >= 544 && CurrentX <= 575) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 576 to 640, inclusive
else if((CurrentX >= 576 && CurrentX <= 640) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//floor area - grey
else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_4_V
`define SKY130_FD_SC_HDLL__O2BB2A_4_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_4_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1403034160 : 2899645186;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_TB_V
`define SKY130_FD_SC_HDLL__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:12:26 11/03/2014
// Design Name:
// Module Name: spi_bonus
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_bonus(clk, reset, din, dout, wren, rden, addr, mosi, miso, sclk);
input clk, reset, wren, rden;
input [7:0] din;
output [7:0] dout;
input [1:0] addr;
output mosi; //serial data out
input miso; //serial data in
output sclk; //SPI clock
`define TXreg 2'b00
`define RXreg 2'b01
`define control 2'b10 //8bit
`define TXFULL control[0]
`define DATARDY control[1]
`define WAIT 2'b00
`define SHIFT 2'b01
`define SHIFT1 2'b10
`define WRITE 2'b11
reg [7:0] control, shiftin, shiftout, dout;
reg wr_tx, wr_rx, rd_tx, sout, sin, spi, wr_control, enspi, clr_count, rd_rx;
reg [6:0] spiclk;
reg [1:0] pstate, nstate;
reg [3:0] counter;
wire rx_empty, tx_full, tx_empty;
wire [7:0] txout, dout_rx;
assign mosi = shiftout[7];
assign sclk = spi;
txreg txfifo(
.clk (clk),
.rst (reset),
.din (din),
.wr_en (wr_tx),
.rd_en (rd_tx),
.dout (txout),
.full (tx_full),
.empty (tx_empty)
);
txreg rxfifo(
.clk (clk),
.rst (reset),
.din (shiftin),
.wr_en (wr_rx),
.rd_en (rd_rx),
.dout (dout_rx),
.full (rx_full),
.empty (rx_empty)
);
//1MHZ clock
always @(posedge clk or posedge reset) begin
if(reset) begin
spiclk <= 6'b00000;
spi <= 0;
end
else begin
begin
if(enspi) begin
if(spiclk >= 0 & spiclk <= 24) begin
spi <= 1;
spiclk <= spiclk + 1;
end
if(spiclk >=25 & spiclk <= 49) begin
spi <= 0;
spiclk <= spiclk + 1;
end
if(spiclk == 50)begin
spiclk <= 6'b00000;
end
end
else begin
spiclk <= 5'b00000;
spi <= 0;
end
end
end
end
//read mux
always @* begin
dout = 8'b00000000;
rd_rx = 0;
case(addr)
`RXreg: begin
if(rden)
rd_rx = 1;
dout = dout_rx;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
always @* begin
wr_tx = 0;
case(addr)
`TXreg: begin
if(wren)
wr_tx = 1;
end
endcase
end
//control reg
always @(posedge clk or posedge reset) begin
if(reset)
control <= 8'b00000000;
else begin
`DATARDY <= ~rx_empty;
`TXFULL <= tx_full;
if(wr_control)
control <= din;
end
end
//counter
always@(posedge spi or posedge reset)begin
if(reset)
counter <= 4'b0000;
else begin
if(enspi) counter <= counter + 1;
if(counter >= 8) counter <= 4'b0001;
end
end
////shift out reg
always @(posedge clk or posedge reset) begin
if(reset)
shiftout <= 8'b00000000;
else begin
if(sout)
shiftout <= {shiftout[6:0], 1'b0};
if(rd_tx)
shiftout <= txout;
end
end
// shift in reg
always @(posedge clk or posedge reset) begin
if(reset)
shiftin <= 8'b00000000;
else begin
if(sin)
shiftin <= {shiftin[6:0], miso};
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if(reset) pstate = `WAIT;
else pstate = nstate;
end
// fsm
always @* begin
rd_tx = 0; sout = 0;
enspi = 0; clr_count = 0;
wr_rx = 0; sin = 0;
nstate = pstate;
case(pstate)
`WAIT: begin
if(~tx_empty) begin
rd_tx = 1;
enspi = 1;
nstate = `SHIFT;
end
end
`SHIFT: begin
enspi = 1;
if(~spi) begin
nstate = `SHIFT1;
sin = 1;
if(counter == 4'b1000) begin
nstate = `WRITE;
end
end
end
`SHIFT1: begin
enspi = 1;
if(spi) begin
sout = 1;
nstate = `SHIFT;
end
end
`WRITE: begin
wr_rx = 1;
nstate = `WAIT;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_SYMBOL_V
`define SKY130_FD_SC_MS__O311AI_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o311ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_SYMBOL_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.29 - lichangbeiju - Change the xx_ to xx_n.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "cpu.h"
`include "bus.h"
module bus_if (
input wire clk, //clock
input wire reset, //reset
input wire stall, //delay signal
input wire flush, //refresh signal
output reg busy, //bus busy signal
input wire [`WordAddrBus] addr, //cpu address = if_pc
input wire as_n, //cpu : address valid
input wire rw, //cpu : read/write
input wire [`WordDataBus] wr_data, //cpu write data
output reg [`WordDataBus] rd_data, //cpu : read data
input wire [`WordDataBus] spm_rd_data, //spm : read data
output wire [`WordAddrBus] spm_addr, //spm : address
output reg spm_as_n, //spm : address valid
output wire spm_rw, //spm : read/write
output wire [`WordDataBus] spm_wr_data, //
input wire [`WordDataBus] bus_rd_data, //bus : read data
input wire bus_rdy_n, //bus : ready
input wire bus_grant_n, //bus : grant
output reg bus_req_n, //bus : request
output reg [`WordAddrBus] bus_addr, //bus : address
output reg bus_as_n, //bus : address select
output reg bus_rw, //
output reg [`WordDataBus] bus_wr_data //
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
reg [`BusIfStateBus] state; //bus inteface state
reg [`WordDataBus] rd_buf; //read buffer
wire [`BusSlaveIndexBus] s_index; //slave index
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
/********** generate the bus slave index**********/
//use the MSB 3 bit to control the index
assign s_index = addr[`BusSlaveIndexLoc];
/********** output assignemnt**********/
assign spm_addr = addr;
assign spm_rw = rw;
assign spm_wr_data = wr_data;
/********** memory access control**********/
always @(*) begin
/* default */
rd_data = `WORD_DATA_W'h0;
spm_as_n = `DISABLE_N;
busy = `DISABLE;
/* bus interface state */
case (state)
`BUS_IF_STATE_IDLE : begin //idle
/* memory access */
if ((flush == `DISABLE) && (as_n == `ENABLE_N)) begin
/* select the access target */
if (s_index == `BUS_SLAVE_1) begin // SPM access control
if (stall == `DISABLE) begin //dectect the delay[stall]
spm_as_n = `ENABLE_N;
if (rw == `READ) begin //read access control
rd_data = spm_rd_data;
end
end
end else begin //access the bus
busy = `ENABLE;
end
end
end
`BUS_IF_STATE_REQ : begin //bus request
busy = `ENABLE;
end
`BUS_IF_STATE_ACCESS : begin //read access
/* wait the ready */
if (bus_rdy_n == `ENABLE_N) begin //bus ready
if (rw == `READ) begin //read control
rd_data = bus_rd_data;
end
end else begin //the bus is not ready
busy = `ENABLE;
end
end
`BUS_IF_STATE_STALL : begin //delay
if (rw == `READ) begin //read control
rd_data = rd_buf;
end
end
endcase
end
/********** bus interface state contrl **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* asynchronous reset */
state <= #1 `BUS_IF_STATE_IDLE;
bus_req_n <= #1 `DISABLE_N;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_as_n <= #1 `DISABLE_N;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
rd_buf <= #1 `WORD_DATA_W'h0;
end else begin
/* bus interface state */
case (state)
`BUS_IF_STATE_IDLE : begin //Idle
/* memory access */
if ((flush == `DISABLE) && (as_n == `ENABLE_N)) begin
/* select the access target*/
if (s_index != `BUS_SLAVE_1) begin // access the bus
state <= #1 `BUS_IF_STATE_REQ;
bus_req_n <= #1 `ENABLE_N;
bus_addr <= #1 addr;
bus_rw <= #1 rw;
bus_wr_data <= #1 wr_data;
end
end
end
`BUS_IF_STATE_REQ : begin //bus request
/* wait the bus grant */
if (bus_grant_n == `ENABLE_N) begin //get the grant
state <= #1 `BUS_IF_STATE_ACCESS;
bus_as_n <= #1 `ENABLE_N;
end
end
`BUS_IF_STATE_ACCESS : begin //access the bus
/* disable the address select */
bus_as_n <= #1 `DISABLE_N;
/* wait the bus ready*/
if (bus_rdy_n == `ENABLE_N) begin //the bus is ready
bus_req_n <= #1 `DISABLE_N;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
/* save the read data into buffer*/
if (bus_rw == `READ) begin //read access
rd_buf <= #1 bus_rd_data;
end
/* detect the stall */
if (stall == `ENABLE) begin //have a stall
state <= #1 `BUS_IF_STATE_STALL;
end else begin //have not a stall
state <= #1 `BUS_IF_STATE_IDLE;
end
end
end
`BUS_IF_STATE_STALL : begin //STALL
/* detect the stall */
if (stall == `DISABLE) begin //disable the stall
state <= #1 `BUS_IF_STATE_IDLE;
end
end
endcase
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HD__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// Title : MIPS Single-Cycle Processor
// Project : ECE 313 - Computer Organization
//-----------------------------------------------------------------------------
// File : mips_single.v
// Author : John Nestor <[email protected]>
// Organization : Lafayette College
//
// Created : October 2002
// Last modified : 7 January 2005
//-----------------------------------------------------------------------------
// Description :
// "Single Cycle" implementation of the MIPS processor subset described in
// Section 5.4 of "Computer Organization and Design, 3rd ed."
// by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e).
//
// It implements the equivalent of Figure 5.19 on page 309 of COD3e
//
//-----------------------------------------------------------------------------
module mips_single(clk, reset);
input clk, reset;
// instruction bus
wire [31:0] instr;
// break out important fields from instruction
wire [5:0] opcode, funct;
wire [4:0] rs, rt, rd, shamt;
wire [15:0] immed;
wire [31:0] extend_immed, b_offset;
wire [25:0] jumpoffset;
assign opcode = instr[31:26];
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:11];
assign shamt = instr[10:6];
assign funct = instr[5:0];
assign immed = instr[15:0];
assign jumpoffset = instr[25:0];
// sign-extender
assign extend_immed = { {16{immed[15]}}, immed };
// branch offset shifter
assign b_offset = extend_immed << 2;
// datapath signals
wire [4:0] rfile_wn;
wire [31:0] rfile_rd1, rfile_rd2, rfile_wd, alu_b, alu_out, b_tgt, pc_next,
pc, pc_incr, br_add_out, dmem_rdata, pc_next2;
wire [31:0] jumpTo;
assign jumpTo = (jumpoffset<<2)+pc_incr[31:28];
// control signals
wire RegWrite, Branch, PCSrc, RegDst, MemtoReg, MemRead, MemWrite, ALUSrc, Zero, Jmp, Zero2;
wire [1:0] ALUOp;
wire [2:0] Operation;
// module instantiations
reg32 PC(clk, reset, pc_next, pc);
add32 PCADD(pc, 32'd4, pc_incr);
add32 BRADD(pc_incr, b_offset, b_tgt);
reg_file RFILE(clk, RegWrite, rs, rt, rfile_wn, rfile_rd1, rfile_rd2, rfile_wd);
alu ALU(Operation, rfile_rd1, alu_b, alu_out, Zero);
rom32 IMEM(pc, instr);
mem32 DMEM(clk, MemRead, MemWrite, alu_out, rfile_rd2, dmem_rdata);
xor BR_XOR(Zero2, opcode[0], Zero);
and BR_AND(PCSrc, Branch, Zero2);
mux2 #(5) RFMUX(RegDst, rt, rd, rfile_wn);
mux2 #(32) PCMUX(PCSrc, pc_incr, b_tgt, pc_next2);
mux2 #(32) JMUX(Jmp, pc_next2, jumpTo, pc_next); // control, input, output
mux2 #(32) ALUMUX(ALUSrc, rfile_rd2, extend_immed, alu_b);
mux2 #(32) WRMUX(MemtoReg, alu_out, dmem_rdata, rfile_wd);
control_single CTL(.opcode(opcode), .RegDst(RegDst), .ALUSrc(ALUSrc), .MemtoReg(MemtoReg),
.RegWrite(RegWrite), .MemRead(MemRead), .MemWrite(MemWrite), .Branch(Branch),
.Jmp(Jmp), .ALUOp(ALUOp));
alu_ctl ALUCTL(ALUOp, funct, Operation);
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
(* $Date: 2012-07-25 16:43:16 -0400 (Wed, 25 Jul 2012) $ *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for [aexp]s,
[bexp]s, and commands) have been formulated in a "big-step"
style -- they specify how a given expression can be evaluated to
its final value (or a command plus a store to a final store) "all
in one big step."
This style is simple and natural for many purposes (indeed, Gilles
Kahn, who popularized its use, called it _natural semantics_), but
there are some things it does not do well. In particular, it
does not give us a natural way of talking about _concurrent_
programming languages, where the "semantics" of a program -- i.e.,
the essence of how it behaves -- is not just which input states
get mapped to which output states, but also includes the
intermediate states that it passes through along the way, since
these states can also be observed by concurrently executing code.
Another shortcoming of the big-step style is more technical, but
critical for some applications. Consider the variant of Imp with
lists that we introduced in ImpList.v. We chose to define the
meaning of programs like [0 + nil] by specifying that a list
should be interpreted as [0] when it occurs in a context expecting
a number, but this was a bit of a hack. It would be better simply
to say that the behavior of such a program is _undefined_ -- it
doesn't evaluate to any result. We could easily do this: we'd
just have to use the formulations of [aeval] and [beval] as
inductive propositions (rather than Fixpoints), so that we can
make them partial functions instead of total ones.
However, this way of defining Imp has a serious deficiency. In
this language, a command might _fail_ to map a given starting
state to any ending state for two quite different reasons: either
because the execution gets into an infinite loop or because, at
some point, the program tries to do an operation that makes no
sense, such as taking the successor of a boolean variable, and
none of the evaluation rules can be applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * Relations *)
(** A _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings.
The optional [Rel] chapter tells a more detailed story about how
relations are treated in Coq. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
Module SimpleArith0.
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint eval (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => eval a1 + eval a2
end.
End SimpleArith0.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** A couple of examples of reasoning with the [step]
relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [plus t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 2 stars (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
apply ST_Plus2. apply ST_Plus2. apply ST_PlusConstConst.
Qed.
(** [] *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic.
_Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption. Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars, recommended (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hxy1.
generalize dependent y2.
step_cases (induction Hxy1) Case; intros y2 Hxy2.
Case "ST_PlusConstConst".
step_cases (inversion Hxy2) SCase; subst.
SCase "ST_PlusConstConst".
reflexivity.
SCase "ST_Plus1".
inversion H2.
SCase "ST_Plus2".
inversion H3.
Case "ST_Plus1".
step_cases (inversion Hxy2) SCase; subst.
SCase "ST_PlusConstConst".
inversion Hxy1.
SCase "ST_Plus1".
rewrite IHHxy1 with t1'0. reflexivity. assumption.
SCase "ST_Plus2".
inversion H1; subst. inversion Hxy1.
Case "ST_Plus2".
step_cases (inversion Hxy2) SCase; subst.
SCase "ST_PlusConstConst".
inversion Hxy1.
SCase "ST_Plus1".
inversion H; subst. inversion H3.
SCase "ST_Plus2".
rewrite IHHxy1 with t2'0. reflexivity. assumption.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): For all [t:tm], either [t] is a
value, or there exists a term [t'] such that [t ==> t'].
_Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense. To state
this fact, let's begin by giving a name to terms that cannot make
progress: We'll call them _normal forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall t,
value t -> normal_form step t.
Proof.
unfold normal_form. intros t H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting? For two reasons:
- Because [value] is a syntactic concept -- it is a defined by
looking at the form of a term -- while [normal_form] is a
semantic one -- it is defined by looking at how the term steps.
It is not obvious that these concepts should coincide!
- Indeed, there are lots of languages in which the concepts of
normal form and value do _not_ coincide. *)
(** Let's examine how this can happen... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, optional (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists t, value t /\ ~ normal_form step t.
Proof.
unfold normal_form. unfold not.
apply ex_intro with (P (C 0) (C 0)).
split.
apply v_funny.
intro H. apply H. apply ex_intro with (C 0). apply ST_PlusConstConst.
Qed.
(** [] *)
End Temp1.
(* ########################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, optional (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists t, value t /\ ~ normal_form step t.
Proof.
unfold normal_form. unfold not.
apply ex_intro with (C 0).
split.
apply v_const.
intro H. apply H. apply ex_intro with (P (C 0) (C 0)). apply ST_Funny.
Qed.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, evne in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
unfold normal_form. unfold not.
apply ex_intro with (P (C 0) (P (C 0) (C 0))).
split.
intro H. inversion H.
intro H. inversion H. inversion H0. inversion H4.
Qed.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
Example smallstep_bools_prop1 :
~ bool_step_prop1.
Proof.
unfold bool_step_prop1. unfold not. intro H. inversion H.
Qed.
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
Example smallstep_bools_prop2 :
~ bool_step_prop2.
Proof.
unfold bool_step_prop2. unfold not. intro H. inversion H.
Qed.
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
Example smallstep_bools_prop3 :
bool_step_prop3.
Proof.
unfold bool_step_prop3. apply ST_If. apply ST_IfTrue.
Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t.
Case "ttrue".
left. apply v_true.
Case "tfalse".
left. apply v_false.
Case "tif".
right. destruct t1.
SCase "ttrue".
apply ex_intro with t2. apply ST_IfTrue.
SCase "tfalse".
apply ex_intro with t3. apply ST_IfFalse.
SCase "tif".
inversion IHt1.
SSCase "left".
inversion H.
SSCase "right".
inversion H. apply ex_intro with (tif x t2 t3).
apply ST_If. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hxy1.
generalize dependent y2.
induction Hxy1.
Case "ST_IfTrue".
intros y2 Hxy2.
inversion Hxy2. reflexivity. inversion H3.
Case "ST_IfFalse".
intros y2 Hxy2.
inversion Hxy2. reflexivity. inversion H3.
Case "ST_If".
intros y2 Hxy2.
inversion Hxy2; subst. inversion Hxy1. inversion Hxy1.
apply IHHxy1 in H3. subst. reflexivity.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
| ST_IfShortCircuit : forall t1 v,
value v ->
tif t1 v v ==> v
where " t '==>' t' " := (step t t').
(** [] *)
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
unfold bool_step_prop4. apply ST_IfShortCircuit. apply v_false.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
Theorem step_nondeterministic :
~ deterministic step.
Proof.
unfold deterministic. unfold not. intro H.
remember (tif ttrue ttrue ttrue) as t1.
remember (tif t1 tfalse tfalse) as t.
assert (t ==> tif ttrue tfalse tfalse).
assert (t1 ==> ttrue) by (subst; apply ST_IfTrue).
subst. apply ST_If. assumption.
assert (t ==> tfalse).
subst. apply ST_IfShortCircuit. apply v_false.
assert (tif ttrue tfalse tfalse = tfalse).
apply H with t; assumption.
inversion H2.
Qed.
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t.
Case "ttrue".
left. apply v_true.
Case "tfalse".
left. apply v_false.
Case "tif".
right. destruct t1.
SCase "ttrue".
apply ex_intro with t2. apply ST_IfTrue.
SCase "tfalse".
apply ex_intro with t3. apply ST_IfFalse.
SCase "tif".
inversion IHt1. inversion H. inversion H.
apply ex_intro with (tif x t2 t3). apply ST_If. assumption.
Qed.
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* Yes, take away ST_If. *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** ** Definitions *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically. Given a relation [R], we
define a relation [multi R] as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] of [X] if either [x = y] or else there is
some (possibly empty) sequence [z1], [z2], ..., [zn] such that:
R x z1
R z1 z2
...
R zn y
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** The crucial properties of the [multi R] relation are
- [multi R] is reflexive
- [multi R] is transitive
- [multi R] relates everything related by [R] *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** We now write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Definition multistep := multi step.
Notation " t '==>*' t' " := (multistep t t') (at level 40).
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step.
apply ST_Plus2.
apply v_const.
apply ST_Plus2.
apply v_const.
apply ST_PlusConstConst.
eapply multi_step.
apply ST_Plus2.
apply v_const.
apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
multi_cases (induction P11) Case; intros y2 P21 P22.
Case "multi_refl".
multi_cases (inversion P21) SCase; subst.
SCase "multi_refl".
reflexivity.
SCase "multi_step".
unfold step_normal_form in P12. unfold normal_form in P12.
unfold not in P12. assert False. apply P12. apply ex_intro with y.
assumption. inversion H1.
Case "multi_step".
multi_cases (inversion P21) SCase; subst.
SCase "multi_refl".
unfold step_normal_form in P22. unfold normal_form in P22.
unfold not in P22. assert False. apply P22. apply ex_intro with y.
assumption. inversion H0.
SCase "multi_step".
apply IHP11. assumption.
assert (deterministic step) by apply step_deterministic.
unfold deterministic in H2.
assert (y = y0) by (apply H2 with x; assumption).
subst. assumption. assumption.
Qed.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
intros t1 t2 t2' H1 H2. multi_cases (induction H2) Case.
Case "multi_refl".
apply multi_refl.
Case "multi_step".
apply multi_step with (P t1 y).
apply ST_Plus2. apply H1. apply H.
apply IHmulti.
Qed.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny
programming language in two different styles, it makes sense to
ask whether these definitions actually define the same thing!
They do, though it takes a little work to show it. The details
are left to you. *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)].
To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction of the correspondence, we need one lemma,
which establishes a relation between single-step reduction and
big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The main theorem is now straightforward to prove, once it is
stated correctly. The proof proceeds by induction on the
multipstep reduction sequence that is buried in the hypothesis
[normal_form_of t v]. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values -- they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ; c2) / st ==> (c1' ; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp (Optional) *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "l '::=' a" :=
(CAss l a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ; c2) / st ==> (c1' ; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. reflexivity.
Qed.
End CImp.
|
module Datapath_RegisterFile( output reg [WORD_WIDTH-1:0] A_Data, B_Data, input [WORD_WIDTH-1:0] D_Data, input [2:0] AA, BA, DA, input RW, CLK );
parameter WORD_WIDTH = 16;
reg [WORD_WIDTH-1:0] REGS[7:0];
always@(posedge CLK)
if(RW)
case(DA)
3'b 000 : REGS[0] = D_Data;
3'b 001 : REGS[1] = D_Data;
3'b 010 : REGS[2] = D_Data;
3'b 011 : REGS[3] = D_Data;
3'b 100 : REGS[4] = D_Data;
3'b 101 : REGS[5] = D_Data;
3'b 110 : REGS[6] = D_Data;
3'b 111 : REGS[7] = D_Data;
endcase
always@(*)
begin
case(AA)
3'b 000 : A_Data = REGS[0];
3'b 001 : A_Data = REGS[1];
3'b 010 : A_Data = REGS[2];
3'b 011 : A_Data = REGS[3];
3'b 100 : A_Data = REGS[4];
3'b 101 : A_Data = REGS[5];
3'b 110 : A_Data = REGS[6];
3'b 111 : A_Data = REGS[7];
endcase
case(BA)
3'b 000 : B_Data = REGS[0];
3'b 001 : B_Data = REGS[1];
3'b 010 : B_Data = REGS[2];
3'b 011 : B_Data = REGS[3];
3'b 100 : B_Data = REGS[4];
3'b 101 : B_Data = REGS[5];
3'b 110 : B_Data = REGS[6];
3'b 111 : B_Data = REGS[7];
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all IMMU blocks. ////
//// ////
//// To Do: ////
//// - cache inhibit ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_top.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.15 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.11 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.10 2002/09/16 03:08:56 lampret
// Disabled cache inhibit atttribute.
//
// Revision 1.9 2002/08/18 19:54:17 lampret
// Added store buffer.
//
// Revision 1.8 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.7 2002/08/12 05:31:30 lampret
// Delayed external access at page crossing.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/17 08:03:35 lampret
// *** empty log message ***
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn MMU
//
module or1200_immu_top(
// Rst and clk
clk, rst,
// CPU i/f
ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// QMEM i/f
qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input ic_en;
input immu_en;
input supv;
input [aw-1:0] icpu_adr_i;
input icpu_cycstb_i;
output [aw-1:0] icpu_adr_o;
output [3:0] icpu_tag_o;
output icpu_rty_o;
output icpu_err_o;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// IC I/F
//
input qmemimmu_rty_i;
input qmemimmu_err_i;
input [3:0] qmemimmu_tag_i;
output [aw-1:0] qmemimmu_adr_o;
output qmemimmu_cycstb_o;
output qmemimmu_ci_o;
//
// Internal wires and regs
//
wire itlb_spr_access;
wire [31:`OR1200_IMMU_PS] itlb_ppn;
wire itlb_hit;
wire itlb_uxe;
wire itlb_sxe;
wire [31:0] itlb_dat_o;
wire itlb_en;
wire itlb_ci;
wire itlb_done;
wire fault;
wire miss;
wire page_cross;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`else
reg itlb_en_r;
reg dis_spr_access;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10 v 0
// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// icpu_adr_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge rst or posedge clk)
if (rst)
icpu_adr_o <= #1 32'h0000_0100;
else
icpu_adr_o <= #1 icpu_adr_i;
`else
Unsupported !!!
`endif
//
// Page cross
//
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
//
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
if (rst)
icpu_vpn_r <= #1 {32-`OR1200_IMMU_PS{1'b0}};
else
icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
`ifdef OR1200_NO_IMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// ITLB SPR access
//
// 1200 - 12FF itlbmr w0
// 1200 - 123F itlbmr w0 [63:0]
//
// 1300 - 13FF itlbtr w0
// 1300 - 133F itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & ~dis_spr_access;
//
// Disable ITLB SPR access
//
// This flop is used to mask ITLB miss/fault exception
// during first clock cycle of accessing ITLB SPR. In
// subsequent clock cycles it is assumed that ITLB SPR
// access was accomplished and that normal instruction fetching
// can proceed.
//
// spr_cs sets dis_spr_access and icpu_rty_o clears it.
//
always @(posedge clk or posedge rst)
if (rst)
dis_spr_access <= #1 1'b0;
else if (!icpu_rty_o)
dis_spr_access <= #1 1'b0;
else if (spr_cs)
dis_spr_access <= #1 1'b1;
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | qmemimmu_err_i;
//
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
//
always @(posedge clk or posedge rst)
if (rst)
itlb_en_r <= #1 1'b0;
else
itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
//
// ITLB lookup successful
//
assign itlb_done = itlb_en_r & ~page_cross;
//
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
//
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
//
// Cache Inhibit
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would doq it, we would doq it like this.
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes a async combinational loop so we stick to
// no cache inhibit.
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
//
// Output to SPRS unit
//
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
//
// Page fault exception logic
//
assign fault = itlb_done &
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = itlb_done & !itlb_hit;
//
// ITLB Enable
//
assign itlb_en = immu_en & icpu_cycstb_i;
//
// Instantiation of ITLB
//
or1200_immu_tlb or1200_immu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(itlb_en),
.vaddr(icpu_adr_i),
.hit(itlb_hit),
.ppn(itlb_ppn),
.uxe(itlb_uxe),
.sxe(itlb_sxe),
.ci(itlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(itlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(itlb_dat_o)
);
`endif
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
[] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
[] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly brackets around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
(* FILL IN HERE *) admit.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
(* FILL IN HERE *) Admitted.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([], [])
| (a, b) :: rest => (a :: fst (split rest), b :: snd (split rest))
end.
(* FILL IN HERE *)
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| nil => None
| x::_ => Some x
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
(* FILL IN HERE *) admit.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
(* FILL IN HERE *) admit.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(* FILL IN HERE *) admit.
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
(* FILL IN HERE *) admit.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
(* FILL IN HERE *) admit.
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The BIU module control the ICB request to external memory system
//
// ====================================================================
`include "e203_defines.v"
module e203_biu(
output biu_active,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from LSU
input lsu2biu_icb_cmd_valid,
output lsu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr,
input lsu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask,
input [1:0] lsu2biu_icb_cmd_burst,
input [1:0] lsu2biu_icb_cmd_beat,
input lsu2biu_icb_cmd_lock,
input lsu2biu_icb_cmd_excl,
input [1:0] lsu2biu_icb_cmd_size,
output lsu2biu_icb_rsp_valid,
input lsu2biu_icb_rsp_ready,
output lsu2biu_icb_rsp_err ,
output lsu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata,
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// the icb interface from ifetch
//
// * bus cmd channel
input ifu2biu_icb_cmd_valid,
output ifu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr,
input ifu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] ifu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ifu2biu_icb_cmd_wmask,
input [1:0] ifu2biu_icb_cmd_burst,
input [1:0] ifu2biu_icb_cmd_beat,
input ifu2biu_icb_cmd_lock,
input ifu2biu_icb_cmd_excl,
input [1:0] ifu2biu_icb_cmd_size,
//
// * bus rsp channel
output ifu2biu_icb_rsp_valid,
input ifu2biu_icb_rsp_ready,
output ifu2biu_icb_rsp_err ,
output ifu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata,
//output ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output [1:0] ppi_icb_cmd_burst,
output [1:0] ppi_icb_cmd_beat,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
// * Bus cmd channel
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output [1:0] clint_icb_cmd_burst,
output [1:0] clint_icb_cmd_beat,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
// * Bus cmd channel
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output [1:0] plic_icb_cmd_burst,
output [1:0] plic_icb_cmd_beat,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
input fio_icb_enable,
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output [1:0] fio_icb_cmd_burst,
output [1:0] fio_icb_cmd_beat,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
input clk,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_ARBT_I_NUM = 2;
localparam BIU_ARBT_I_PTR_W = 1;
`else//}{
localparam BIU_ARBT_I_NUM = 1;
localparam BIU_ARBT_I_PTR_W = 1;
`endif//}
// The SPLT_NUM is the sum of following components
// * ppi, clint, plic, SystemITF, Fast-IO, IFU-err
localparam BIU_SPLT_I_NUM_0 = 4;
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_SPLT_I_NUM_1 = (BIU_SPLT_I_NUM_0 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_1 = BIU_SPLT_I_NUM_0;
`endif//}
`ifdef E203_HAS_FIO //{
localparam BIU_SPLT_I_NUM_2 = (BIU_SPLT_I_NUM_1 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_2 = BIU_SPLT_I_NUM_1;
`endif//}
localparam BIU_SPLT_I_NUM = BIU_SPLT_I_NUM_2;
wire ifuerr_icb_cmd_valid;
wire ifuerr_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifuerr_icb_cmd_addr;
wire ifuerr_icb_cmd_read;
wire [2-1:0] ifuerr_icb_cmd_burst;
wire [2-1:0] ifuerr_icb_cmd_beat;
wire [`E203_XLEN-1:0] ifuerr_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] ifuerr_icb_cmd_wmask;
wire ifuerr_icb_cmd_lock;
wire ifuerr_icb_cmd_excl;
wire [1:0] ifuerr_icb_cmd_size;
wire ifuerr_icb_rsp_valid;
wire ifuerr_icb_rsp_ready;
wire ifuerr_icb_rsp_err ;
wire ifuerr_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifuerr_icb_rsp_rdata;
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_XLEN-1:0] arbt_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] arbt_icb_cmd_wmask;
wire [1:0] arbt_icb_cmd_burst;
wire [1:0] arbt_icb_cmd_beat;
wire arbt_icb_cmd_lock;
wire arbt_icb_cmd_excl;
wire [1:0] arbt_icb_cmd_size;
wire arbt_icb_cmd_usr;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire arbt_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] arbt_icb_rsp_rdata;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [BIU_ARBT_I_NUM*`E203_ADDR_SIZE-1:0] arbt_bus_icb_cmd_addr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_cmd_wdata;
wire [BIU_ARBT_I_NUM*`E203_XLEN/8-1:0] arbt_bus_icb_cmd_wmask;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_burst;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_beat;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_lock;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_excl;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_size;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_usr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_excl_ok;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_rsp_rdata;
//CMD Channel
assign arbt_bus_icb_cmd_valid =
// The LSU take higher priority
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_valid,
`endif//}
lsu2biu_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_addr,
`endif//}
lsu2biu_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_read,
`endif//}
lsu2biu_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wdata,
`endif//}
lsu2biu_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wmask,
`endif//}
lsu2biu_icb_cmd_wmask
} ;
assign arbt_bus_icb_cmd_burst =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_burst,
`endif//}
lsu2biu_icb_cmd_burst
} ;
assign arbt_bus_icb_cmd_beat =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_beat,
`endif//}
lsu2biu_icb_cmd_beat
} ;
assign arbt_bus_icb_cmd_lock =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_lock,
`endif//}
lsu2biu_icb_cmd_lock
} ;
assign arbt_bus_icb_cmd_excl =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_excl,
`endif//}
lsu2biu_icb_cmd_excl
} ;
assign arbt_bus_icb_cmd_size =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_size,
`endif//}
lsu2biu_icb_cmd_size
} ;
wire ifu2biu_icb_cmd_ifu = 1'b1;
wire lsu2biu_icb_cmd_ifu = 1'b0;
assign arbt_bus_icb_cmd_usr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ifu,
`endif//}
lsu2biu_icb_cmd_ifu
} ;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ready,
`endif//}
lsu2biu_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
//RSP Channel
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_valid,
`endif//}
lsu2biu_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_err,
`endif//}
lsu2biu_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_excl_ok,
`endif//}
lsu2biu_icb_rsp_excl_ok
} = arbt_bus_icb_rsp_excl_ok;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_rdata,
`endif//}
lsu2biu_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_ready,
`endif//}
lsu2biu_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because in BIU we always have CMD_DP larger than 0
// when the response come back from the external bus, it is at least 1 cycle later
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.ARBT_NUM (BIU_ARBT_I_NUM),
.ARBT_PTR_W (BIU_ARBT_I_PTR_W),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst (arbt_icb_cmd_burst) ,
.o_icb_cmd_beat (arbt_icb_cmd_beat ) ,
.o_icb_cmd_excl (arbt_icb_cmd_excl ) ,
.o_icb_cmd_lock (arbt_icb_cmd_lock ) ,
.o_icb_cmd_size (arbt_icb_cmd_size ) ,
.o_icb_cmd_usr (arbt_icb_cmd_usr ) ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0 ) ,
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst (arbt_bus_icb_cmd_burst),
.i_bus_icb_cmd_beat (arbt_bus_icb_cmd_beat ),
.i_bus_icb_cmd_excl (arbt_bus_icb_cmd_excl ),
.i_bus_icb_cmd_lock (arbt_bus_icb_cmd_lock ),
.i_bus_icb_cmd_size (arbt_bus_icb_cmd_size ),
.i_bus_icb_cmd_usr (arbt_bus_icb_cmd_usr ),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_excl_ok (arbt_bus_icb_rsp_excl_ok),
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr () ,
.clk (clk ) ,
.rst_n (rst_n)
);
//// To breakup the dead-lock cases, when incoming load/store request to the BIU but not granted
//// This kind of potential deadlock case only happened at the low end core, where the ifetch response
//// provided to IFU, but IFU cannot accept it because it is waiting the IR stage to be cleared, and IR
//// stage is waiting the LSU to be cleared, and LSU is waiting this BIU to be cleared.
//// At any mid of high end core (or with multiple oustandings), we definitely will update IFU
//// to make sure it always can accept any oustanding transactions traded with area cost.
//// So back to this very low end core, to save areas, we prefetch without knowing if IR can accept
//// the response or not, and also in very low end core it is just 1 oustanding (multiple oustanding
//// belong to mid or high end core), so to cut off this deadlocks, we just let the BIU to trigger
//// and replay indication if LSU cannot get granted, if IFU just overkilly forced to be replayed, it
//// just lost performance, but we dont care, because in low end core, ifetch to system mem is not
//// guranteed by performance. If IFU really suppose to be replayed, then good luck to break this deadlock.
//wire ifu_replay_r;
//// The IFU replay will be set when:
//// * Accessed by non-IFU access
//// * Or non-IFU access is to access ITCM, but not granted
//wire ifu_replay_set = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & lsu2biu_icb_cmd_valid)
// | (lsu2biu_icb_cmd_valid & (~lsu2biu_icb_cmd_ready));
//// The IFU replay will be cleared after accessed by a IFU access
//wire ifu_replay_clr = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & ifu2biu_icb_cmd_valid);
//wire ifu_replay_ena = ifu_replay_set | ifu_replay_clr;
//wire ifu_replay_nxt = ifu_replay_set | (~ifu_replay_clr);
//sirv_gnrl_dfflr #(1)ifu_replay_dffl(ifu_replay_ena, ifu_replay_nxt, ifu_replay_r, clk, rst_n);
//assign ifu2biu_replay = ifu_replay_r;
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [`E203_XLEN-1:0] buf_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] buf_icb_cmd_wmask;
wire [1:0] buf_icb_cmd_burst;
wire [1:0] buf_icb_cmd_beat;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_cmd_usr;
wire buf_icb_cmd_ifu = buf_icb_cmd_usr;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err;
wire buf_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] buf_icb_rsp_rdata;
wire icb_buffer_active;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (`E203_BIU_OUTS_CNT_W),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN),
.CMD_DP(`E203_BIU_CMD_DP),
.RSP_DP(`E203_BIU_RSP_DP),
.CMD_CUT_READY (`E203_BIU_CMD_CUT_READY),
.RSP_CUT_READY (`E203_BIU_RSP_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (icb_buffer_active),
.i_icb_cmd_valid (arbt_icb_cmd_valid),
.i_icb_cmd_ready (arbt_icb_cmd_ready),
.i_icb_cmd_read (arbt_icb_cmd_read ),
.i_icb_cmd_addr (arbt_icb_cmd_addr ),
.i_icb_cmd_wdata (arbt_icb_cmd_wdata),
.i_icb_cmd_wmask (arbt_icb_cmd_wmask),
.i_icb_cmd_lock (arbt_icb_cmd_lock ),
.i_icb_cmd_excl (arbt_icb_cmd_excl ),
.i_icb_cmd_size (arbt_icb_cmd_size ),
.i_icb_cmd_burst (arbt_icb_cmd_burst),
.i_icb_cmd_beat (arbt_icb_cmd_beat ),
.i_icb_cmd_usr (arbt_icb_cmd_usr ),
.i_icb_rsp_valid (arbt_icb_rsp_valid),
.i_icb_rsp_ready (arbt_icb_rsp_ready),
.i_icb_rsp_err (arbt_icb_rsp_err ),
.i_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok),
.i_icb_rsp_rdata (arbt_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (buf_icb_cmd_usr),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [BIU_SPLT_I_NUM*`E203_ADDR_SIZE-1:0] splt_bus_icb_cmd_addr;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_cmd_wdata;
wire [BIU_SPLT_I_NUM*`E203_XLEN/8-1:0] splt_bus_icb_cmd_wmask;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
ifuerr_icb_cmd_valid
, ppi_icb_cmd_valid
, clint_icb_cmd_valid
, plic_icb_cmd_valid
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_valid
`endif//}
} = splt_bus_icb_cmd_valid;
assign {
ifuerr_icb_cmd_addr
, ppi_icb_cmd_addr
, clint_icb_cmd_addr
, plic_icb_cmd_addr
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_addr
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_addr
`endif//}
} = splt_bus_icb_cmd_addr;
assign {
ifuerr_icb_cmd_read
, ppi_icb_cmd_read
, clint_icb_cmd_read
, plic_icb_cmd_read
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_read
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_read
`endif//}
} = splt_bus_icb_cmd_read;
assign {
ifuerr_icb_cmd_wdata
, ppi_icb_cmd_wdata
, clint_icb_cmd_wdata
, plic_icb_cmd_wdata
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wdata
`endif//}
} = splt_bus_icb_cmd_wdata;
assign {
ifuerr_icb_cmd_wmask
, ppi_icb_cmd_wmask
, clint_icb_cmd_wmask
, plic_icb_cmd_wmask
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wmask
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wmask
`endif//}
} = splt_bus_icb_cmd_wmask;
assign {
ifuerr_icb_cmd_burst
, ppi_icb_cmd_burst
, clint_icb_cmd_burst
, plic_icb_cmd_burst
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_burst
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_burst
`endif//}
} = splt_bus_icb_cmd_burst;
assign {
ifuerr_icb_cmd_beat
, ppi_icb_cmd_beat
, clint_icb_cmd_beat
, plic_icb_cmd_beat
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_beat
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_beat
`endif//}
} = splt_bus_icb_cmd_beat;
assign {
ifuerr_icb_cmd_lock
, ppi_icb_cmd_lock
, clint_icb_cmd_lock
, plic_icb_cmd_lock
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_lock
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_lock
`endif//}
} = splt_bus_icb_cmd_lock;
assign {
ifuerr_icb_cmd_excl
, ppi_icb_cmd_excl
, clint_icb_cmd_excl
, plic_icb_cmd_excl
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_excl
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_excl
`endif//}
} = splt_bus_icb_cmd_excl;
assign {
ifuerr_icb_cmd_size
, ppi_icb_cmd_size
, clint_icb_cmd_size
, plic_icb_cmd_size
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_size
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_size
`endif//}
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
ifuerr_icb_cmd_ready
, ppi_icb_cmd_ready
, clint_icb_cmd_ready
, plic_icb_cmd_ready
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_ready
`endif//}
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
ifuerr_icb_rsp_valid
, ppi_icb_rsp_valid
, clint_icb_rsp_valid
, plic_icb_rsp_valid
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_valid
`endif//}
};
assign splt_bus_icb_rsp_err = {
ifuerr_icb_rsp_err
, ppi_icb_rsp_err
, clint_icb_rsp_err
, plic_icb_rsp_err
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_err
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_err
`endif//}
};
assign splt_bus_icb_rsp_excl_ok = {
ifuerr_icb_rsp_excl_ok
, ppi_icb_rsp_excl_ok
, clint_icb_rsp_excl_ok
, plic_icb_rsp_excl_ok
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_excl_ok
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_excl_ok
`endif//}
};
assign splt_bus_icb_rsp_rdata = {
ifuerr_icb_rsp_rdata
, ppi_icb_rsp_rdata
, clint_icb_rsp_rdata
, plic_icb_rsp_rdata
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_rdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_rdata
`endif//}
};
assign {
ifuerr_icb_rsp_ready
, ppi_icb_rsp_ready
, clint_icb_rsp_ready
, plic_icb_rsp_ready
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_ready
`endif//}
} = splt_bus_icb_rsp_ready;
wire buf_icb_cmd_ppi = ppi_icb_enable & (buf_icb_cmd_addr[`E203_PPI_BASE_REGION] == ppi_region_indic[`E203_PPI_BASE_REGION]);
wire buf_icb_sel_ppi = buf_icb_cmd_ppi & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_clint = clint_icb_enable & (buf_icb_cmd_addr[`E203_CLINT_BASE_REGION] == clint_region_indic[`E203_CLINT_BASE_REGION]);
wire buf_icb_sel_clint = buf_icb_cmd_clint & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_plic = plic_icb_enable & (buf_icb_cmd_addr[`E203_PLIC_BASE_REGION] == plic_region_indic[`E203_PLIC_BASE_REGION]);
wire buf_icb_sel_plic = buf_icb_cmd_plic & (~buf_icb_cmd_ifu);
`ifdef E203_HAS_FIO //{
wire buf_icb_cmd_fio = fio_icb_enable & (buf_icb_cmd_addr[`E203_FIO_BASE_REGION] == fio_region_indic[`E203_FIO_BASE_REGION]);
wire buf_icb_sel_fio = buf_icb_cmd_fio & (~buf_icb_cmd_ifu);
`endif//}
wire buf_icb_sel_ifuerr =(
buf_icb_cmd_ppi
| buf_icb_cmd_clint
| buf_icb_cmd_plic
`ifdef E203_HAS_FIO //{
| buf_icb_cmd_fio
`endif//}
) & buf_icb_cmd_ifu;
`ifdef E203_HAS_MEM_ITF //{
wire buf_icb_sel_mem = mem_icb_enable
& (~buf_icb_sel_ifuerr)
& (~buf_icb_sel_ppi)
& (~buf_icb_sel_clint)
& (~buf_icb_sel_plic)
`ifdef E203_HAS_FIO //{
& (~buf_icb_sel_fio)
`endif//}
;
`endif//}
wire [BIU_SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
buf_icb_sel_ifuerr
, buf_icb_sel_ppi
, buf_icb_sel_clint
, buf_icb_sel_plic
`ifdef E203_HAS_FIO //{
, buf_icb_sel_fio
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, buf_icb_sel_mem
`endif//}
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.SPLT_NUM (BIU_SPLT_I_NUM),
.SPLT_PTR_W (BIU_SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0 ) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({BIU_SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
assign biu_active = ifu2biu_icb_cmd_valid | lsu2biu_icb_cmd_valid | icb_buffer_active;
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Implement the IFU-accessed-Peripheral region error
assign ifuerr_icb_cmd_ready = ifuerr_icb_rsp_ready;
// 0 Cycle response
assign ifuerr_icb_rsp_valid = ifuerr_icb_cmd_valid;
assign ifuerr_icb_rsp_err = 1'b1;
assign ifuerr_icb_rsp_excl_ok = 1'b0;
assign ifuerr_icb_rsp_rdata = {`E203_XLEN{1'b0}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_SYMBOL_V
`define SKY130_FD_SC_LP__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_SYMBOL_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ADC_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ADC_ROM (
address,
clock,
q);
input [10:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
Require Import Coq.Classes.RelationClasses.
Require Import Coq.Classes.Morphisms.
Require Import Coq.Reals.Rdefinitions.
Require Import ExtLib.Structures.Applicative.
Require Import ExtLib.Structures.Functor.
Require Import ExtLib.Data.Fun.
Require Import ExtLib.Data.Prop.
Require Import ExtLib.Tactics.
Require Import ChargeCore.Logics.ILogic.
Require Import ChargeCore.Logics.ILEmbed.
Require ChargeCore.Logics.ILInsts.
Require Import ChargeCore.Tactics.Tactics.
Require Import Temporal.Lifting.
Require Import Temporal.DiscreteStream.
Section parametric.
Variable tlaState : Type.
Definition Var (T : Type) : Type := tlaState -> T.
Local Existing Instance Applicative_Fun.
Local Existing Instance Functor_Fun.
Definition StateVal (T : Type) : Type :=
tlaState -> T.
Definition ActionVal (T : Type) : Type :=
tlaState -> tlaState -> T.
Definition RawTraceVal (T : Type) :=
trace tlaState -> T.
Definition TraceVal (T : Type) :=
{ P : RawTraceVal T | Proper (trace_eq eq ==> eq) P }.
Definition StateProp := StateVal Prop.
Definition ActionProp := ActionVal Prop.
Definition TraceProp :=
@ILInsts.ILPreFrm (trace tlaState) (trace_eq eq) Prop _.
Definition tpred (T : TraceProp) : trace tlaState -> Prop :=
ILInsts.ILPreFrm_pred T.
Definition mkTraceProp_iff (P : trace tlaState -> Prop)
(Pr : Proper (trace_eq eq ==> iff) P)
: TraceProp.
eapply (@ILInsts.mkILPreFrm _ _ _ _ P).
intros; simpl; eapply Pr; symmetry; assumption.
Defined.
Definition mkTraceProp (P : trace tlaState -> Prop)
(Pr : Proper (trace_eq eq ==> Basics.impl) P)
: TraceProp.
eapply (@ILInsts.mkILPreFrm _ _ _ _ P).
eapply Pr.
Defined.
Global Instance ILogicOps_StateProp : ILogicOps StateProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_ActionProp : ILogicOps ActionProp :=
@ILInsts.ILFun_Ops _ _ _.
Local Transparent ILInsts.ILFun_Ops.
Local Transparent ILInsts.ILPre_Ops.
Global Instance ILogicOps_TraceProp : ILogicOps TraceProp :=
ILInsts.ILPre_Ops.
Global Instance ILogic_StateProp : ILogic StateProp := _.
Global Instance ILogic_ActionProp : ILogic ActionProp := _.
Global Instance ILogic_TraceProp : ILogic TraceProp := _.
Global Instance EmbedOp_Prop_StateProp : EmbedOp Prop StateProp :=
{ embed := fun P _ => P }.
Global Instance Embed_Prop_StateProp : Embed Prop StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_ActionProp : EmbedOp Prop ActionProp :=
{ embed := fun P _ _ => P }.
Global Instance Embed_Prop_ActionProp : Embed Prop ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_TraceProp : EmbedOp Prop TraceProp :=
{ embed := fun P => mkTraceProp (fun _ => P) _ }.
Proof.
compute. auto.
Defined.
Global Instance Embed_Prop_TraceProp : Embed Prop TraceProp.
Proof.
constructor; simpl; intuition.
{ red. simpl. eauto. }
{ red. simpl. eauto. }
{ red. simpl. split.
- intros; eapply H; eauto; reflexivity.
- intros; eapply H; eauto; reflexivity. }
Qed.
Global Instance EmbedOp_StateVal_StateProp : EmbedOp (StateVal Prop) StateProp :=
{ embed := fun P => P }.
Global Instance Embed_StateVal_StateProp : Embed (StateVal Prop) StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_ActionVal_ActionProp : EmbedOp (ActionVal Prop) ActionProp :=
{ embed := fun P => P }.
Global Instance Embed_ActionVal_ActionProp : Embed (ActionVal Prop) ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
(* These are the "obvious" definitions, needed to help Coq *)
Global Instance Applicative_Action
: Applicative ActionVal :=
{ pure := fun _ x => fun _ _ => x
; ap := fun _ _ f x => fun st st' => (f st st') (x st st')
}.
Global Instance Functor_Action
: Functor ActionVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Global Instance Applicative_State
: Applicative StateVal :=
{ pure := fun _ x => fun _ => x
; ap := fun _ _ f x => fun st => (f st) (x st)
}.
Global Instance Functor_State
: Functor StateVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Definition now : StateProp -> TraceProp.
Proof.
refine (fun P => mkTraceProp (fun tr => P (hd tr)) _).
compute. intros.
destruct x; destruct y.
inversion H.
simpl in *. subst. auto.
Defined.
Definition always (P : TraceProp) : TraceProp.
refine (
mkTraceProp (fun s =>
forall s', skips_to s' s -> tpred P s') _).
Proof.
abstract (do 2 red; intros; setoid_rewrite H; reflexivity).
Defined.
Definition eventually (P : TraceProp) : TraceProp.
refine (
mkTraceProp (fun s =>
exists s', skips_to s s' /\ tpred P s') _).
Proof.
abstract (do 2 red; intros; setoid_rewrite H; reflexivity).
Defined.
Definition starts (P : ActionProp) : TraceProp.
refine (
mkTraceProp (fun tr => P (hd tr) (hd (tl tr))) _).
Proof.
abstract (do 2 red; intros; rewrite H; reflexivity).
Defined.
Definition pre {T} (f : StateVal T) : ActionVal T :=
fun st _ => f st.
Definition post {T} (f : StateVal T) : ActionVal T :=
fun _ st' => f st'.
Instance Proper_tpred : Proper (lequiv ==> trace_eq eq ==> iff) tpred.
Proof.
do 3 red. destruct x; destruct y; simpl.
intros. split.
{ intros. eapply ILPreFrm_closed0. 2: eapply H.
2: simpl; eapply ILPreFrm_closed; [ | eassumption ].
eassumption. reflexivity. }
{ intros. eapply ILPreFrm_closed.
2: eapply H; simpl. 2: eapply ILPreFrm_closed0; [ | eassumption ].
symmetry. eassumption. reflexivity. }
Qed.
(** This is not part of TLA **)
Definition next (P : TraceProp) : TraceProp.
refine (mkTraceProp (fun tr => tpred P (tl tr)) _).
Proof.
abstract (do 2 red; intros; rewrite H; reflexivity).
Defined.
Definition stutter {T} (f : tlaState -> T) : ActionProp :=
fun st st' => f st = f st'.
Lemma always_skips_to : forall P t1 t2,
skips_to t2 t1 ->
tpred (always P) t1 -> tpred (always P) t2.
Proof.
unfold always. intros.
compute in *. intros.
eapply H0. etransitivity; eauto.
Qed.
(** Always Facts **)
Lemma always_and : forall P Q,
always P //\\ always Q -|- always (P //\\ Q).
Proof.
intros. split.
{ red. red. simpl. unfold always. unfold tpred. intuition. }
{ red. red. simpl. unfold always.
intuition; edestruct H; eauto. }
Qed.
Lemma always_or : forall P Q,
always P \\// always Q |-- always (P \\// Q).
Proof.
red. red. simpl. unfold always, tpred. intuition.
Qed.
Lemma always_impl : forall P Q,
always (P -->> Q) |-- always P -->> always Q.
Proof.
red. red. simpl. unfold always, tpred. intuition.
rewrite <- x0 in H1.
eapply H. eassumption. reflexivity. eapply H0.
rewrite <- x0. assumption.
Qed.
Lemma always_tauto
: forall G P, |-- P -> G |-- always P.
Proof.
compute; intuition.
destruct P; destruct G; eauto.
Qed.
Lemma and_forall : forall {T} (F G : T -> Prop),
((forall x, F x) /\ (forall x, G x)) <->
(forall x, F x /\ G x).
Proof. firstorder. Qed.
Lemma now_entails : forall (A B : StateProp),
now (A -->> B) |-- now A -->> now B.
Proof.
unfold now. simpl. intros. revert H0.
rewrite <- x0. assumption.
Qed.
Definition before (P : StateProp) : ActionProp :=
fun st _ => P st.
Definition after (P : StateProp) : ActionProp :=
fun _ st' => P st'.
(*
Coercion starts : ActionProp >-> TraceProp.
Coercion discretely : DActionProp >-> ActionProp.
*)
Lemma now_starts_discretely_and : forall P Q,
now P //\\ starts Q -|- starts (before P //\\ Q).
Proof.
unfold now, starts, before; red; simpl; split; eauto.
Qed.
(*
Lemma starts_next_impl : forall (P : DActionProp) (Q : StateProp),
starts (discretely (fun st st' => P st st' -> Q st')) |-- starts (discretely P) -->> through (now Q).
Proof.
intros.
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl. tauto.
tauto. }
Qed.
*)
Lemma starts_after : forall (P : ActionProp) (Q : StateProp),
(forall st, P st |-- Q) ->
|-- starts P -->> starts (after Q).
Proof.
unfold starts, after. simpl; intros; eauto.
Qed.
Definition enabled (ap : ActionProp) : StateProp :=
Exists st', fun st => ap st st'.
(** Reasoning about [through] **)
Lemma starts_and : forall P Q, starts P //\\ starts Q -|- starts (P //\\ Q).
Proof.
intros. apply and_forall. intros.
unfold starts.
simpl. destruct x. destruct x. intuition.
Qed.
Lemma starts_or : forall P Q, starts P \\// starts Q -|- starts (P \\// Q).
Proof.
unfold starts; simpl; intros; split; simpl; eauto.
Qed.
Lemma starts_impl : forall P Q, starts P -->> starts Q -|- starts (P -->> Q).
Proof.
unfold starts; simpl; intros; split; simpl; intros.
{ eapply H; eauto. reflexivity. }
{ rewrite x0 in H. eauto. }
Qed.
Lemma starts_ex : forall T (P : T -> _),
Exists x : T, starts (P x) -|- starts (lexists P).
Proof.
unfold starts; simpl; intros; split; simpl; eauto.
Qed.
Lemma starts_all : forall T (P : T -> _),
Forall x : T, starts (P x) -|- starts (lforall P).
Proof.
unfold starts; simpl; intros; split; simpl; eauto.
Qed.
Lemma next_now : forall (P : StateProp),
next (now P) -|- starts (after P).
Proof.
unfold starts, next; simpl; intros; split; simpl; eauto.
Qed.
Lemma starts_tauto : forall (P : ActionProp),
|-- P ->
|-- starts P.
Proof.
compute. auto.
Qed.
Global Instance Proper_starts_lentails
: Proper (lentails ==> lentails) starts.
Proof.
red. red. intros.
unfold starts. red. simpl.
red in H. red in H. red in H.
intros.
eapply H. eassumption.
Qed.
Global Instance Proper_starts_lequiv
: Proper (lequiv ==> lequiv) starts.
Proof.
red. red. intros.
unfold starts. red. simpl.
split; intros; eapply H; eauto.
Qed.
(** This is standard discrete induction over time **)
Lemma dind_lem : forall (P : TraceProp),
|-- P -->> always (P -->> next P) -->> always P.
Proof.
intros. do 3 red.
intros. red. simpl.
intros. clear H.
change ILInsts.ILPreFrm_pred with tpred in *.
specialize (fun s' H => H1 s' H s' (Reflexive_trace_eq _)).
rewrite <- x0 in *; clear x0.
rewrite x2 in *; clear x2.
clear - H2 H0 H1.
induction H2; simpl.
{ (* Now *)
intros. rewrite H. assumption. }
{ (* Later *)
intros.
eapply IHskips_to.
{ eapply H1; eauto. reflexivity. }
{ intros. eapply H1; eauto using Later. } }
Qed.
Theorem hybrid_induction
: forall G P T,
G |-- always T ->
G |-- P ->
G |-- always (P -->> T -->> next P) ->
G |-- always P.
Proof.
intros G P T. intros.
generalize (dind_lem P).
intros.
charge_apply H2. eauto.
apply Lemmas.lcut with (R:=G).
charge_assumption.
rewrite H at 1. rewrite H1.
rewrite <- always_impl.
charge_revert.
rewrite <- always_impl.
apply always_tauto.
charge_tauto.
Qed.
End parametric.
Arguments pre {_ _} _ _ _.
Arguments post {_ _} _ _ _.
Arguments always {_} _.
Arguments eventually {_} _.
Arguments starts {_} _.
Arguments now {_} _.
Arguments stutter {_ _} _ _ _.
Arguments mkTraceProp {_} _ _.
Arguments tpred {_} _ _.
Lemma TraceProp_trace_eq {T} : forall (P : TraceProp T) x y,
trace_eq eq x y -> tpred P x -> tpred P y.
Proof.
destruct P; simpl; intros.
eapply ILPreFrm_closed; eauto.
Qed.
Lemma TraceProp_trace_eq_iff {T} : forall (P : TraceProp T) x y,
trace_eq eq x y -> tpred P x <-> tpred P y.
Proof.
intros. split; eapply TraceProp_trace_eq; eauto. symmetry; eauto.
Qed.
Require Import Coq.Classes.Morphisms.
(** TODO: These should be generalized to [TraceVal], [ActionVal], and [StateVal] **)
Section simulations.
Context {T U : Type}.
Local Transparent ILInsts.ILFun_Ops.
Local Transparent ILInsts.ILPre_Ops.
Variable f : U -> T.
Definition focusT (P : TraceProp T) : TraceProp U.
refine (
mkTraceProp (fun tu => (tpred P) (fmap f tu)) _).
eauto with typeclass_instances.
{ red. red. intros.
destruct P. red.
eapply TraceProp_trace_eq.
eapply Proper_fmap_trace_eq; [ | eassumption ].
reflexivity. }
Defined.
Definition focusS (P : StateProp T) : StateProp U :=
fun tu => P (f tu).
Definition focusA (P : ActionProp T) : ActionProp U :=
fun st st' => P (f st) (f st').
Theorem focusT_now : forall P, focusT (now P) -|- now (focusS P).
Proof.
compute; intros; split; destruct t; auto.
Qed.
Theorem focusT_starts : forall P, focusT (starts P) -|- starts (focusA P).
Proof.
compute; split; destruct t; destruct t; auto.
Qed.
End simulations.
(* Temporal Existential Quantification *)
Section temporal_exists.
Context {T U : Type}.
Local Transparent ILInsts.ILFun_Ops.
Local Transparent ILInsts.ILPre_Ops.
Definition texists (P : TraceProp (T * U)) : TraceProp U.
refine (
mkTraceProp (fun tr : trace U => exists tr' : trace T,
tpred P (trace_zip pair tr' tr)) _).
{ red. red. intros. red. intros.
destruct H0. exists x0.
eapply TraceProp_trace_eq. 2: eassumption.
eapply Proper_trace_zip; solve [ reflexivity | assumption ]. }
Defined.
Global Instance Proper_texists_lentails
: Proper (lentails ==> lentails) texists.
Proof.
unfold texists. repeat red.
intros. destruct H0. eexists. eapply H. eassumption.
Qed.
Global Instance Proper_texists_lequiv
: Proper (lequiv ==> lequiv) texists.
Proof.
unfold texists. split; repeat red; destruct 1; eexists; eapply H; eauto.
Qed.
Theorem texistsL : forall (P : TraceProp U) (Q : TraceProp (T * U)),
Q |-- focusT snd P ->
texists Q |-- P.
Proof.
intros. unfold texists.
simpl. intros.
destruct H0.
eapply H in H0.
clear - H0.
revert H0.
destruct P; simpl in *.
eapply ILPreFrm_closed.
clear.
rewrite fmap_trace_trace_zip_compose.
simpl.
revert x t.
cofix.
destruct x. destruct t0.
constructor.
- reflexivity.
- eapply texistsL.
Qed.
Definition exactTrace (tr : trace T) : TraceProp T :=
mkTraceProp (trace_eq eq tr) _.
Lemma exactTrace_exact : forall tr tr',
trace_eq eq tr tr' ->
tpred (exactTrace tr) tr'.
Proof. compute; auto. Qed.
Opaque exactTrace.
End temporal_exists.
Arguments texists _ {_} _.
(* Notation for fields *)
Notation "x # y" := (PreFun.compose y x) (at level 0).
Section temporal_history.
Local Transparent ILInsts.ILFun_Ops.
Local Transparent ILInsts.ILPre_Ops.
Local Opaque trace_zip.
Local Opaque fmap_trace.
Context {T U : Type}.
Theorem texists_history
: forall (P : TraceProp U) (x : StateVal U T),
P -|- texists (list T)
( focusT snd P
//\\ now (lift2 eq fst (pure nil))
//\\ always (starts (lift2 eq (post fst)
(lift2 cons (pre snd#x)
(pre fst))))).
Proof.
intros. simpl. unfold texists.
split.
{ simpl. intros.
exists (fmap (List.map x) (prefixes nil t)).
split; [ | split ].
- eapply Proper_tpred; [ reflexivity | | eassumption ].
rewrite fmap_trace_trace_zip_compose.
simpl.
clear. rewrite trace_zip_snd. reflexivity.
- simpl. destruct t. reflexivity.
- simpl. intros.
unfold pre, post.
assert (exists rst pre,
skips_to rst t /\
trace_eq eq s' (trace_zip pair (fmap_trace (List.map x) (prefixes pre rst)) rst)).
{ clear - H0.
remember (trace_zip pair (fmap_trace (List.map x) (prefixes nil t)) t).
generalize dependent (@nil U). generalize dependent t.
induction H0.
{ intros. subst. exists t0. exists l. split; eauto.
reflexivity. }
{ intros. subst.
destruct (IHskips_to (tl t0) (List.cons (hd t0) l)).
{ destruct t0. reflexivity. }
{ destruct H. destruct H.
exists x0. eexists. split; eauto.
constructor 2. eassumption. } } }
{ clear H0. destruct H1. destruct H0. destruct H0.
rewrite H1.
destruct x0. destruct x0. reflexivity. } }
{ simpl. intros.
destruct H. destruct H.
clear H0.
eapply Proper_tpred; [ reflexivity | | eassumption ].
rewrite fmap_trace_trace_zip_compose. simpl.
rewrite trace_zip_snd. reflexivity. }
Qed.
End temporal_history.
Export ChargeCore.Logics.ILogic. |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_PP_SYMBOL_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 42);
`assert(result_empty, 0);
`assert(trap, `ENDED);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_PP_SYMBOL_V
`define SKY130_FD_SC_MS__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkdlyinv5sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkdlyinv5sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
|
//======================================================================
//
// coretest_bp_entropy.v
// ---------------------
// Top level module for the BP FPGA entropy source tester.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module coretest_bp_entropy(
input wire clk,
input wire reset_n,
// External interface.
input wire rxd,
output wire txd,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter UART_ADDR_PREFIX = 8'h00;
parameter ENT_ADDR_PREFIX = 8'h10;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
// Coretest connections.
wire coretest_reset_n;
wire coretest_cs;
wire coretest_we;
wire [15 : 0] coretest_address;
wire [31 : 0] coretest_write_data;
reg [31 : 0] coretest_read_data;
reg coretest_error;
// uart connections
wire uart_rxd_syn;
wire [7 : 0] uart_rxd_data;
wire uart_rxd_ack;
wire uart_txd_syn;
wire [7 : 0] uart_txd_data;
wire uart_txd_ack;
reg uart_cs;
reg uart_we;
reg [7 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_error;
wire [7 : 0] uart_debug;
reg ent_cs;
reg ent_we;
reg [7 : 0] ent_address;
reg [31 : 0] ent_write_data;
wire [31 : 0] ent_read_data;
wire [7 : 0] ent_debug;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign debug = ent_debug;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
coretest coretest(
.clk(clk),
.reset_n(reset_n),
.rx_syn(uart_rxd_syn),
.rx_data(uart_rxd_data),
.rx_ack(uart_rxd_ack),
.tx_syn(uart_txd_syn),
.tx_data(uart_txd_data),
.tx_ack(uart_txd_ack),
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
.core_cs(coretest_cs),
.core_we(coretest_we),
.core_address(coretest_address),
.core_write_data(coretest_write_data),
.core_read_data(coretest_read_data),
.core_error(coretest_error)
);
uart uart(
.clk(clk),
.reset_n(reset_n),
.rxd(rxd),
.txd(txd),
.rxd_syn(uart_rxd_syn),
.rxd_data(uart_rxd_data),
.rxd_ack(uart_rxd_ack),
.txd_syn(uart_txd_syn),
.txd_data(uart_txd_data),
.txd_ack(uart_txd_ack),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),
.write_data(uart_write_data),
.read_data(uart_read_data),
.error(uart_error),
.debug(uart_debug)
);
entropy entropy(.clk(clk),
.nreset(reset_n),
.cs(ent_cs),
.we(ent_we),
.addr(ent_address),
.dwrite(ent_write_data),
.dread(ent_read_data),
.debug(ent_debug)
);
//----------------------------------------------------------------
// address_mux
//
// Combinational data mux that handles addressing between
// cores using the 32-bit memory like interface.
//----------------------------------------------------------------
always @*
begin : address_mux
// Default assignments.
coretest_read_data = 32'h00000000;
coretest_error = 0;
uart_cs = 0;
uart_we = 0;
uart_address = 8'h00;
uart_write_data = 32'h00000000;
ent_cs = 0;
ent_we = 0;
ent_address = 8'h00;
ent_write_data = 32'h00000000;
case (coretest_address[15 : 8])
UART_ADDR_PREFIX:
begin
uart_cs = coretest_cs;
uart_we = coretest_we;
uart_address = coretest_address[7 : 0];
uart_write_data = coretest_write_data;
coretest_read_data = uart_read_data;
coretest_error = uart_error;
end
ENT_ADDR_PREFIX:
begin
ent_cs = coretest_cs;
ent_we = coretest_we;
ent_address = coretest_address[7 : 0];
ent_write_data = coretest_write_data[15 : 0];
coretest_read_data = ent_read_data;
coretest_error = 1'b0;
end
default:
begin
end
endcase // case (coretest_address[15 : 8])
end // address_mux
endmodule // coretest_bp_entropy
//======================================================================
// EOF coretest_bp_entropy.v
//======================================================================
|
module lut_n(clk,n_clk, state);
/* This module contains the framework for an eighty-state look-up table.
It takes a seed value followed by an arbitrary list of 79 corner values in
ascending order and uses if-else conditionals, selecting
if(val<val0), state0, if(val<val1), state1, ..., else state_80.
State changes are made on clock edges.
*/
input clk;
input [13:0] n_clk;
output reg [6:0] state;
//To calibrate the matching network, it is useful to use a coarser look-up table
//with switches separated by wider frequency gaps. This increases the likelihood
//that we will actually see the center-frequency. To facilitate this, a macro
//is defined that lets us shift the subset of switching states selected from the total
//available set, advancing the coarse-grid by offset number of levels.
parameter OFFSET=4'b0100;
//Note that this file should not be included in the project because it is not
//a fully-defined Verilog entity, but a snippet of code. It should
//remain in the working directory, however.
//Load corner clock counts.
//parameter cornerNclkFilename="cornerNclk.v"
//Define a default parameter specifying which lookup table to use.
//This is a hack because 2D arrays cannot be passed in the port list.
parameter LOOKUP_ID=1;
`include "cornerNclk.v"
always @(posedge clk) begin
// if(n_clk>n_clk_corner[0]) state=7'b110011; //f>101&f<102
// else if(n_clk>n_clk_corner[1]) state=7'b110010; //f>102&f<103
// else if(n_clk>n_clk_corner[2]) state=7'b110001; //f>103&f<104
// else if(n_clk>n_clk_corner[3]) state=7'b110000; //f>104
// else state=7'b110000-7'b1; //f>104 Higher frequencies than period from n_clk_corner[3]
// if(n_clk>n_clk_corner[0]) state=7'b1001111; //Lowest frequency - hold state for all frequencies lower
// //else if(n_clk>n_clk_corner[1]) state=7'b1001111+OFFSET;
// else if(n_clk>n_clk_corner[9-OFFSET]) state=7'b1000111+OFFSET;
// else if(n_clk>n_clk_corner[17-OFFSET]) state=7'b111111+OFFSET;
// else if(n_clk>n_clk_corner[25-OFFSET]) state=7'b110111+OFFSET;
// else if(n_clk>n_clk_corner[33-OFFSET]) state=7'b101111+OFFSET;
// else if(n_clk>n_clk_corner[41-OFFSET]) state=7'b100111+OFFSET;
// else if(n_clk>n_clk_corner[49-OFFSET]) state=7'b11111+OFFSET;
// else if(n_clk>n_clk_corner[57-OFFSET]) state=7'b10111+OFFSET;
// else if(n_clk>n_clk_corner[65-OFFSET]) state=7'b1111+OFFSET;
// else if(n_clk>n_clk_corner[73-OFFSET]) state=7'b111+OFFSET;
// else state=7'b0+OFFSET; //Highest frequency = - baseload for all frequencies higher.
if(n_clk>n_clk_corner[0]) state=7'b1010000; //Lowest frequency - hold state for all frequencies lower
else if(n_clk>n_clk_corner[1]) state=7'b1001111;
else if(n_clk>n_clk_corner[2]) state=7'b1001110;
else if(n_clk>n_clk_corner[3]) state=7'b1001101;
else if(n_clk>n_clk_corner[4]) state=7'b1001100;
else if(n_clk>n_clk_corner[5]) state=7'b1001011;
else if(n_clk>n_clk_corner[6]) state=7'b1001010;
else if(n_clk>n_clk_corner[7]) state=7'b1001001;
else if(n_clk>n_clk_corner[8]) state=7'b1001000;
else if(n_clk>n_clk_corner[9]) state=7'b1000111;
else if(n_clk>n_clk_corner[10]) state=7'b1000110;
else if(n_clk>n_clk_corner[11]) state=7'b1000101;
else if(n_clk>n_clk_corner[12]) state=7'b1000100;
else if(n_clk>n_clk_corner[13]) state=7'b1000011;
else if(n_clk>n_clk_corner[14]) state=7'b1000010;
else if(n_clk>n_clk_corner[15]) state=7'b1000001;
else if(n_clk>n_clk_corner[16]) state=7'b1000000;
else if(n_clk>n_clk_corner[17]) state=7'b111111;
else if(n_clk>n_clk_corner[18]) state=7'b111110;
else if(n_clk>n_clk_corner[19]) state=7'b111101;
else if(n_clk>n_clk_corner[20]) state=7'b111100;
else if(n_clk>n_clk_corner[21]) state=7'b111011;
else if(n_clk>n_clk_corner[22]) state=7'b111010;
else if(n_clk>n_clk_corner[23]) state=7'b111001;
else if(n_clk>n_clk_corner[24]) state=7'b111000;
else if(n_clk>n_clk_corner[25]) state=7'b110111;
else if(n_clk>n_clk_corner[26]) state=7'b110110;
else if(n_clk>n_clk_corner[27]) state=7'b110101;
else if(n_clk>n_clk_corner[28]) state=7'b110100;
else if(n_clk>n_clk_corner[29]) state=7'b110011;
else if(n_clk>n_clk_corner[30]) state=7'b110010;
else if(n_clk>n_clk_corner[31]) state=7'b110001;
else if(n_clk>n_clk_corner[32]) state=7'b110000;
else if(n_clk>n_clk_corner[33]) state=7'b101111;
else if(n_clk>n_clk_corner[34]) state=7'b101110;
else if(n_clk>n_clk_corner[35]) state=7'b101101;
else if(n_clk>n_clk_corner[36]) state=7'b101100;
else if(n_clk>n_clk_corner[37]) state=7'b101011;
else if(n_clk>n_clk_corner[38]) state=7'b101010;
else if(n_clk>n_clk_corner[39]) state=7'b101001;
else if(n_clk>n_clk_corner[40]) state=7'b101000;
else if(n_clk>n_clk_corner[41]) state=7'b100111;
else if(n_clk>n_clk_corner[42]) state=7'b100110;
else if(n_clk>n_clk_corner[43]) state=7'b100101;
else if(n_clk>n_clk_corner[44]) state=7'b100100;
else if(n_clk>n_clk_corner[45]) state=7'b100011;
else if(n_clk>n_clk_corner[46]) state=7'b100010;
else if(n_clk>n_clk_corner[47]) state=7'b100001;
else if(n_clk>n_clk_corner[48]) state=7'b100000;
else if(n_clk>n_clk_corner[49]) state=7'b11111;
else if(n_clk>n_clk_corner[50]) state=7'b11110;
else if(n_clk>n_clk_corner[51]) state=7'b11101;
else if(n_clk>n_clk_corner[52]) state=7'b11100;
else if(n_clk>n_clk_corner[53]) state=7'b11011;
else if(n_clk>n_clk_corner[54]) state=7'b11010;
else if(n_clk>n_clk_corner[55]) state=7'b11001;
else if(n_clk>n_clk_corner[56]) state=7'b11000;
else if(n_clk>n_clk_corner[57]) state=7'b10111;
else if(n_clk>n_clk_corner[58]) state=7'b10110;
else if(n_clk>n_clk_corner[59]) state=7'b10101;
else if(n_clk>n_clk_corner[60]) state=7'b10100;
else if(n_clk>n_clk_corner[61]) state=7'b10011;
else if(n_clk>n_clk_corner[62]) state=7'b10010;
else if(n_clk>n_clk_corner[63]) state=7'b10001;
else if(n_clk>n_clk_corner[64]) state=7'b10000;
else if(n_clk>n_clk_corner[65]) state=7'b1111;
else if(n_clk>n_clk_corner[66]) state=7'b1110;
else if(n_clk>n_clk_corner[67]) state=7'b1101;
else if(n_clk>n_clk_corner[68]) state=7'b1100;
else if(n_clk>n_clk_corner[69]) state=7'b1011;
else if(n_clk>n_clk_corner[70]) state=7'b1010;
else if(n_clk>n_clk_corner[71]) state=7'b1001;
else if(n_clk>n_clk_corner[72]) state=7'b1000;
else if(n_clk>n_clk_corner[73]) state=7'b111;
else if(n_clk>n_clk_corner[74]) state=7'b110;
else if(n_clk>n_clk_corner[75]) state=7'b101;
else if(n_clk>n_clk_corner[76]) state=7'b100;
else if(n_clk>n_clk_corner[77]) state=7'b11;
else if(n_clk>n_clk_corner[78]) state=7'b10;
else if(n_clk>n_clk_corner[79]) state=7'b1;
else state=7'b0; //Highest frequency = - baseload for all frequencies higher.
end
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire [7:0] CX4_SNES_DATA_IN;
wire [7:0] CX4_SNES_DATA_OUT;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [23:0] cx4_datrom_data;
wire [9:0] cx4_datrom_addr;
wire cx4_datrom_we;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [7:0] SNES_ROMSELr;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg[17:0] SNES_DEAD_CNTr = 18'h00000;
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] | SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111100);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000011);
wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] | SNES_CPU_CLKr[6:1]) == 6'b111000);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
wire [23:0] SNES_ADDR = (SNES_ADDRr[6] & SNES_ADDRr[5]);
wire [7:0] SNES_PA = (SNES_PAr[6] & SNES_PAr[5]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 7'b0000001;
parameter ST_MCU_RD_ADDR = 7'b0000010;
parameter ST_MCU_RD_END = 7'b0000100;
parameter ST_MCU_WR_ADDR = 7'b0001000;
parameter ST_MCU_WR_END = 7'b0010000;
parameter ST_CX4_RD_ADDR = 7'b0100000;
parameter ST_CX4_RD_END = 7'b1000000;
parameter ROM_CYCLE_LEN = 4'd6;
parameter SNES_DEAD_TIMEOUT = 17'd80000; // 1ms
reg [6:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign CX4_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [7:0] featurebits;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
wire [15:0] dsp_feat;
wire [7:0] snescmd_data_in_mcu_dbg;
wire feat_cmd_unlock = featurebits[5];
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.featurebits_out(featurebits),
.cx4_reset_out(cx4_reset),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT),
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.featurebits(featurebits),
//MSU-1
.msu_enable(msu_enable),
//CX4
.cx4_enable(cx4_enable),
.cx4_vect_enable(cx4_vect_enable),
//region
.r213f_enable(r213f_enable),
//CMD Interface
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
assign DCM_RST=0;
//always @(posedge CLK2) begin
// non_hit_cycle <= 1'b0;
// if(SNES_cycle_start) non_hit_cycle <= ~ROM_HIT;
//end
reg [7:0] CX4_DINr;
wire [23:0] CX4_ADDR;
wire [2:0] cx4_busy;
cx4 snes_cx4 (
.DI(CX4_SNES_DATA_IN),
.DO(CX4_SNES_DATA_OUT),
.ADDR(SNES_ADDR[12:0]),
.CS(cx4_enable),
.SNES_VECT_EN(cx4_vect_enable),
.reg_we_rising(SNES_WR_end),
.CLK(CLK2),
.BUS_DI(CX4_DINr),
.BUS_ADDR(CX4_ADDR),
.BUS_RRQ(CX4_RRQ),
.BUS_RDY(CX4_RDY),
.cx4_active(cx4_active),
.cx4_busy_out(cx4_busy),
.speed(dsp_feat[0])
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_cycle_start(SNES_cycle_start),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (msu_enable ? MSU_SNES_DATA_OUT
:cx4_enable ? CX4_SNES_DATA_OUT
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
:(snescmd_unlock | feat_cmd_unlock) & snescmd_enable ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
): 8'bZ;
reg [4:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg CX4_RD_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg [23:0] CX4_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
reg RQ_CX4_RDYr;
initial RQ_CX4_RDYr = 1'b1;
assign CX4_RDY = RQ_CX4_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
wire CX4_HIT = |(STATE & ST_CX4_RD_ADDR);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : CX4_HIT ? CX4_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : CX4_HIT ? CX4_ADDRr[0] : MAPPED_SNES_ADDR[0];
always @(posedge CLK2) begin
if(cx4_active) begin
if(CX4_RRQ) begin
CX4_RD_PENDr <= 1'b1;
RQ_CX4_RDYr <= 1'b0;
CX4_ADDRr <= CX4_ADDR;
end else if(STATE == ST_CX4_RD_END) begin
CX4_RD_PENDr <= 1'b0;
RQ_CX4_RDYr <= 1'b1;
end
end
end
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(cx4_active) begin
if (CX4_RD_PENDr) begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= 16;
end
end else if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
ST_CX4_RD_ADDR: begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_CX4_RD_END;
CX4_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_CX4_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
// r213f_delay <= 3'b000;
// r213f_state <= 2'b10;
// end else if(r213f_state == 2'b10) begin
// r213f_delay <= r213f_delay - 1;
// if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
// end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
cx4_enable ? 1'b0 :
(cx4_active & cx4_vect_enable) ? 1'b0 :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
.TRIG3(ROM_ADDRr), // IN BUS [23:0]
.TRIG4(CX4_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(CX4_DINr), // IN BUS [7:0]
.TRIG7(STATE) // IN BUS [21:0]
);*/
/*
ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
*/
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_SYMBOL_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_SYMBOL_V
|
/*
* Copyright (C) 2015-2016 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
//
module halfband_decim
(
input c,
input [17:0] tap,
input [NDSP-1:0] load_tap,
input [23:0] id0, // input data n
input [23:0] id1, // input data n+1
output [23:0] od
);
parameter integer NCH = 4; // number of channels to process, clock is NCH*OSR
parameter integer NDSP = 3; // number of DSP blocks to use, = ((NTAPS-1 / 2) + 1)/2
wire signed [47:0] pcout [0:NDSP-1];
wire signed [47:0] p [0:NDSP-1];
wire signed [23:0] a [0:NDSP-1];
wire signed [23:0] d [0:NDSP-1];
assign a[0] = id0;
reg [23:0] odr = 0;
assign od = odr;
wire [23:0] center_data;
delay #(.NB(24), .DEL(1+2+NDSP * (NCH))) cdelay(.c(c), .i(id1), .o(center_data));
genvar i;
generate
for(i=0; i<NDSP; i=i+1) begin: dsp
DSP48E1 #(.USE_DPORT("TRUE"), .ADREG(1), .AREG(2), .BREG(1), .CREG(1), .DREG(1), .OPMODEREG(1))
dsp48_i
(
// status
.OVERFLOW(), .PATTERNDETECT(), .PATTERNBDETECT(), .UNDERFLOW(),
// outs
.CARRYOUT(),
.P(p[i]),
// control
.ALUMODE(4'd0),
.CARRYINSEL(3'd0),
.CLK(c),
.INMODE(5'b00100),
.OPMODE(i==0 ? 7'b0110101 : 7'b0010101), // if i==0: P + C+(A+D)*B else PCIN instead of C
// signal inputs
.A({5'd0, a[i][23], a[i]}), // 30
.B(tap), // 18
.C(i==0 ? {4'h0, center_data, 20'h80000} : 48'h0), // 48
.D({d[i][23], d[i]}), // 25
.CARRYIN(1'b0),
// cascade ports
.ACOUT(), .BCOUT(), .CARRYCASCOUT(), .MULTSIGNOUT(), .PCOUT(pcout[i]),
.ACIN(30'h0), .BCIN(18'h0), .CARRYCASCIN(1'b0), .MULTSIGNIN(1'b0),
.PCIN(i==0 ? 48'h0 : pcout[i-1]),
// clock enables
.CEA1(1'b1), .CEA2(1'b1), .CEAD(1'b1), .CEALUMODE(1'b1),
.CEB1(load_tap[i]), .CEB2(load_tap[i]), .CEC(1'b1),
.CECARRYIN(1'b1), .CECTRL(1'b1), // opmode
.CED(1'b1), .CEINMODE(1'b1), .CEM(1'b1), .CEP(1'b1),
.RSTA(1'b0), .RSTALLCARRYIN(1'b0), .RSTALUMODE(1'b0),
.RSTB(1'b0), .RSTC(1'b0), .RSTCTRL(1'b0), .RSTD(1'b0), .RSTINMODE(1'b0), .RSTM(1'b0), .RSTP(1'b0)
);
if(i!=0)
delay #(.NB(24), .DEL(1+NCH)) del_a(.c(c), .i(a[i-1]), .o(a[i]));
if(i==(NDSP-1))
delay #(.NB(24), .DEL(1+NCH)) del_d(.c(c), .i(a[NDSP-1]), .o(d[i]));
else
delay #(.NB(24), .DEL(NCH-1)) del_d(.c(c), .i(d[i+1]), .o(d[i]));
end
endgenerate
always @ (posedge c) begin
odr <= p[NDSP-1][43:20];
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
// i0 and i1 are each two TDM channels
// o0 is even samples
module halfband_reorder(input c, s, input [23:0] i0, i1, output reg [23:0] o0, o1);
parameter N = 2; // number of input TDM channels
wire [23:0] i0d2, i1d2, i1d4;
delay #(.NB(24), .DEL(N)) delay_1(.c(c), .i(i0), .o(i0d2));
delay #(.NB(24), .DEL(N)) delay_2(.c(c), .i(i1), .o(i1d2));
delay #(.NB(24), .DEL(N*2)) delay_3(.c(c), .i(i1), .o(i1d4));
o0 <= s ? i1d4 : i0d2;
o1 <= s ? i1d2 : i0;
endmodule
module halfband_8ch_decim4(input c, input[1:0] sync, input [23:0] i0, i1, i2, i3, output [23:0] o);
wire [23:0] i0r, i1r, i2r, i3r, fo0, fo1, fo0r, fo1r;
reg sr1, sr2;
reg [2:0] count;
always @ (posedge c)
begin
count <= sync ? 1'b0 : count + 1'b1;
case(count)
0: {sr1, sr2} <= 2'b00;
1: {sr1, sr2} <= 2'b00;
2: {sr1, sr2} <= 2'b10;
3: {sr1, sr2} <= 2'b10;
4: {sr1, sr2} <= 2'b01;
5: {sr1, sr2} <= 2'b01;
6: {sr1, sr2} <= 2'b11;
7: {sr1, sr2} <= 2'b11;
endcase
end
halfband_reorder #(.N(2)) reorder0(.c(c), .s(sr1), .i0(i0), .i1(i1), .o0(i0r), .o1(i1r));
halfband_reorder #(.N(2)) reorder1(.c(c), .s(sr1), .i0(i2), .i1(i3), .o0(i2r), .o1(i3r));
halfband_decim #(.NDSP(3)) decim0(.c(c), .tap(tap), .load_tap(lt[2:0]), .id0(i0r), .id1(i1r), .od(fo0));
halfband_decim #(.NDSP(3)) decim1(.c(c), .tap(tap), .load_tap(lt[2:0]), .id0(i2r), .id1(i2r), .od(fo1));
halfband_reorder #(.N(4)) reorder1(.c(c), .s(sr2), .i0(fo0), .i1(fo1), .o0(fo0r), .o1(fo1r));
halfband_decim #(.NDSP(3)) decim1(.c(c), .tap(tap), .load_tap(lt[5:3]), .id0(fo0r), .id1(fo1r), .od(o));
endmodule
module delay (input c, input [NB-1:0] i, output [NB-1:0] o);
parameter integer NB = 1;
parameter integer DEL = 2;
genvar j;
generate
if(DEL > 1) begin
for(j=0; j<NB; j=j+1) begin: dbit
reg [DEL-1:0] dreg = 0;
always @ (posedge c)
dreg <= {dreg[DEL-2:0], i[j]};
assign o[j] = dreg[DEL-1];
end
end
else if(DEL == 1) begin
reg [NB-1:0] oq;
always @ (posedge c)
oq <= i;
assign o = oq;
end
else begin
assign o = i;
end
endgenerate
endmodule |
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : ../source/server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 server return address 2
// 129 array 2
// 130 array 2
// 131 variable tx_start 2
// 132 variable tx_length 2
// 133 variable timeout 2
// 134 variable resend_wait 2
// 135 variable bytes 2
// 136 variable index 2
// 137 variable last_state 2
// 138 variable new_rx_data 2
// 139 variable state 2
// 140 temporary_register 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 4
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 2
// 147 temporary_register 2
// 148 temporary_register 1024
// 149 temporary_register 2
// 150 temporary_register 2
// 151 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3551:0];
reg [31:0] registers [151:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 28 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 29 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 30 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'op': 'report'}
// 41 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd128, 8'd0, 32'd2627};//{'dest': 128, 'label': 2627, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd140, 8'd1, 32'd0};//{'dest': 140, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd140, 8'd3, 32'd0};//{'dest': 140, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd140, 32'd0};//{'dest': 5, 'src': 140, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd140, 32'd0};//{'dest': 7, 'src': 140, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd140, 32'd0};//{'dest': 9, 'src': 140, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd145, 8'd14, 32'd0};//{'dest': 145, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd143, 8'd144, 32'd145};//{'srcb': 145, 'src': 144, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd143, 8'd144, 32'd65536};//{'src': 144, 'right': 65536, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd143, 32'd99};//{'src': 143, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd143, 8'd144, 32'd65535};//{'src': 144, 'right': 65535, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd143, 8'd144, 32'd1};//{'src': 144, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd143, 8'd11, 32'd0};//{'dest': 143, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd140, 8'd143, 32'd0};//{'dest': 140, 'src': 143, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd140, 32'd0};//{'dest': 16, 'src': 140, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd146, 8'd142, 32'd20};//{'dest': 146, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887811007192, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887811007192, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887811007192, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd140, 32'd0};//{'dest': 22, 'src': 140, 'op': 'move'}
instructions[128] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd142, 8'd141, 32'd20};//{'dest': 142, 'src': 141, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887811007696, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887811007696, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887811007696, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[141] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd140, 32'd157};//{'src': 140, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029472, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029472, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811029472, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd140, 32'd188};//{'src': 140, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029760, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029760, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811029760, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd140, 32'd212};//{'src': 140, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd140, 8'd22, 32'd0};//{'dest': 140, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd140, 8'd23, 32'd0};//{'dest': 140, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd140, 32'd0};//{'dest': 24, 'src': 140, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd140, 8'd24, 32'd0};//{'dest': 140, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd140, 32'd0};//{'dest': 18, 'src': 140, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd140, 8'd27, 32'd0};//{'dest': 140, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd140, 8'd28, 32'd0};//{'dest': 140, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd140, 8'd29, 32'd0};//{'dest': 140, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd140, 8'd30, 32'd0};//{'dest': 140, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd140, 8'd31, 32'd0};//{'dest': 140, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd140, 32'd0};//{'dest': 33, 'src': 140, 'op': 'move'}
instructions[289] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd140, 32'd327};//{'src': 140, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd142, 8'd33, 32'd0};//{'dest': 142, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd146, 8'd142, 32'd26};//{'dest': 146, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810549952, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810549952, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810549952, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd140, 8'd33, 32'd0};//{'dest': 140, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd141, 8'd7, 32'd0};//{'dest': 141, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd140, 32'd345};//{'src': 140, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd140, 32'd0};//{'dest': 37, 'src': 140, 'op': 'move'}
instructions[350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd140, 32'd0};//{'dest': 38, 'src': 140, 'op': 'move'}
instructions[354] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd142, 8'd37, 32'd0};//{'dest': 142, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd140, 32'd387};//{'src': 140, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd142, 8'd141, 32'd36};//{'dest': 142, 'src': 141, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd140, 8'd38, 32'd0};//{'dest': 140, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810550960, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810550960, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810550960, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd26, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd140, 32'd416};//{'src': 140, 'label': 416, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810551248, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810551248, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810551248, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd140, 32'd425};//{'src': 140, 'label': 425, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[423] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[424] = {6'd15, 8'd0, 8'd0, 32'd425};//{'label': 425, 'op': 'goto'}
instructions[425] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572368, 'op': 'memory_read_request'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572368, 'op': 'memory_read_wait'}
instructions[434] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810572368, 'element_size': 2, 'op': 'memory_read'}
instructions[435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd26, 8'd140, 8'd141, 32'd515};//{'src': 141, 'right': 515, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[440] = {6'd13, 8'd0, 8'd140, 32'd454};//{'src': 140, 'label': 454, 'op': 'jmp_if_false'}
instructions[441] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[444] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572656, 'op': 'memory_read_request'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572656, 'op': 'memory_read_wait'}
instructions[450] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810572656, 'element_size': 2, 'op': 'memory_read'}
instructions[451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd13, 8'd0, 8'd140, 32'd463};//{'src': 140, 'label': 463, 'op': 'jmp_if_false'}
instructions[457] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[461] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[462] = {6'd15, 8'd0, 8'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573232, 'op': 'memory_read_request'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573232, 'op': 'memory_read_wait'}
instructions[472] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810573232, 'element_size': 2, 'op': 'memory_read'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd26, 8'd140, 8'd141, 32'd1029};//{'src': 141, 'right': 1029, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd13, 8'd0, 8'd140, 32'd492};//{'src': 140, 'label': 492, 'op': 'jmp_if_false'}
instructions[479] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573520, 'op': 'memory_read_request'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573520, 'op': 'memory_read_wait'}
instructions[488] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810573520, 'element_size': 2, 'op': 'memory_read'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[491] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd13, 8'd0, 8'd140, 32'd501};//{'src': 140, 'label': 501, 'op': 'jmp_if_false'}
instructions[495] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[498] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[499] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[500] = {6'd15, 8'd0, 8'd0, 32'd501};//{'label': 501, 'op': 'goto'}
instructions[501] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574096, 'op': 'memory_read_request'}
instructions[508] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574096, 'op': 'memory_read_wait'}
instructions[510] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810574096, 'element_size': 2, 'op': 'memory_read'}
instructions[511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd13, 8'd0, 8'd140, 32'd749};//{'src': 140, 'label': 749, 'op': 'jmp_if_false'}
instructions[517] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574600, 'op': 'memory_read_request'}
instructions[524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574600, 'op': 'memory_read_wait'}
instructions[526] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810574600, 'element_size': 2, 'op': 'memory_read'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd13, 8'd0, 8'd140, 32'd743};//{'src': 140, 'label': 743, 'op': 'jmp_if_false'}
instructions[533] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[534] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[541] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[542] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[549] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[550] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[553] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[556] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[557] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[558] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[565] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[566] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[569] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[573] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[577] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[580] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[581] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[582] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[588] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[589] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[590] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[593] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[597] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[601] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[605] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[611] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810594864, 'op': 'memory_read_request'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810594864, 'op': 'memory_read_wait'}
instructions[614] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810594864, 'element_size': 2, 'op': 'memory_read'}
instructions[615] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[622] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[628] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595296, 'op': 'memory_read_request'}
instructions[629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[630] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595296, 'op': 'memory_read_wait'}
instructions[631] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810595296, 'element_size': 2, 'op': 'memory_read'}
instructions[632] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[633] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[635] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[639] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595728, 'op': 'memory_read_request'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595728, 'op': 'memory_read_wait'}
instructions[648] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810595728, 'element_size': 2, 'op': 'memory_read'}
instructions[649] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[656] = {6'd0, 8'd146, 8'd0, 32'd14};//{'dest': 146, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[657] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[660] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596160, 'op': 'memory_read_request'}
instructions[663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[664] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596160, 'op': 'memory_read_wait'}
instructions[665] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810596160, 'element_size': 2, 'op': 'memory_read'}
instructions[666] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[673] = {6'd0, 8'd146, 8'd0, 32'd15};//{'dest': 146, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596592, 'op': 'memory_read_request'}
instructions[680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[681] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596592, 'op': 'memory_read_wait'}
instructions[682] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810596592, 'element_size': 2, 'op': 'memory_read'}
instructions[683] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[690] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[694] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[697] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[698] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810617928, 'op': 'memory_read_request'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810617928, 'op': 'memory_read_wait'}
instructions[707] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810617928, 'element_size': 2, 'op': 'memory_read'}
instructions[708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[710] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[711] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[717] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618072, 'op': 'memory_read_request'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618072, 'op': 'memory_read_wait'}
instructions[720] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618072, 'element_size': 2, 'op': 'memory_read'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[724] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618216, 'op': 'memory_read_request'}
instructions[731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618216, 'op': 'memory_read_wait'}
instructions[733] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618216, 'element_size': 2, 'op': 'memory_read'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[737] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[741] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[742] = {6'd15, 8'd0, 8'd0, 32'd743};//{'label': 743, 'op': 'goto'}
instructions[743] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[747] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[748] = {6'd15, 8'd0, 8'd0, 32'd749};//{'label': 749, 'op': 'goto'}
instructions[749] = {6'd3, 8'd140, 8'd37, 32'd0};//{'dest': 140, 'src': 37, 'op': 'move'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[753] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[754] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[755] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[756] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[757] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd13, 8'd0, 8'd140, 32'd814};//{'src': 140, 'label': 814, 'op': 'jmp_if_false'}
instructions[771] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd11, 8'd146, 8'd142, 32'd40};//{'dest': 146, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618576, 'op': 'memory_read_request'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618576, 'op': 'memory_read_wait'}
instructions[780] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618576, 'element_size': 2, 'op': 'memory_read'}
instructions[781] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd13, 8'd0, 8'd140, 32'd802};//{'src': 140, 'label': 802, 'op': 'jmp_if_false'}
instructions[788] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd11, 8'd146, 8'd142, 32'd41};//{'dest': 146, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618864, 'op': 'memory_read_request'}
instructions[795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[796] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618864, 'op': 'memory_read_wait'}
instructions[797] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618864, 'element_size': 2, 'op': 'memory_read'}
instructions[798] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[801] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[804] = {6'd13, 8'd0, 8'd140, 32'd811};//{'src': 140, 'label': 811, 'op': 'jmp_if_false'}
instructions[805] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[808] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[809] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[810] = {6'd15, 8'd0, 8'd0, 32'd811};//{'label': 811, 'op': 'goto'}
instructions[811] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[812] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[813] = {6'd15, 8'd0, 8'd0, 32'd762};//{'label': 762, 'op': 'goto'}
instructions[814] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[815] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[818] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[822] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[826] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[829] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[830] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[831] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[838] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[839] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[845] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[846] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[847] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[854] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[855] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[858] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[861] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[862] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[863] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[866] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[869] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[870] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[871] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[874] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[878] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[879] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[882] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[885] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[886] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[887] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[894] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[895] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[898] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[901] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[902] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[906] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[910] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[914] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[918] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[921] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[922] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[925] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[926] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[927] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[928] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[931] = {6'd3, 8'd50, 8'd140, 32'd0};//{'dest': 50, 'src': 140, 'op': 'move'}
instructions[932] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[936] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[939] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[943] = {6'd3, 8'd142, 8'd50, 32'd0};//{'dest': 142, 'src': 50, 'op': 'move'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd13, 8'd0, 8'd140, 32'd979};//{'src': 140, 'label': 979, 'op': 'jmp_if_false'}
instructions[950] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[956] = {6'd13, 8'd0, 8'd140, 32'd967};//{'src': 140, 'label': 967, 'op': 'jmp_if_false'}
instructions[957] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[958] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[959] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd11, 8'd142, 8'd141, 32'd52};//{'dest': 142, 'src': 141, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[965] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[966] = {6'd15, 8'd0, 8'd0, 32'd969};//{'label': 969, 'op': 'goto'}
instructions[967] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[968] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[969] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[970] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[971] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[978] = {6'd15, 8'd0, 8'd0, 32'd940};//{'label': 940, 'op': 'goto'}
instructions[979] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[982] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[985] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673120, 'op': 'memory_read_request'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673120, 'op': 'memory_read_wait'}
instructions[988] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673120, 'element_size': 2, 'op': 'memory_read'}
instructions[989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[991] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd13, 8'd0, 8'd140, 32'd1008};//{'src': 140, 'label': 1008, 'op': 'jmp_if_false'}
instructions[995] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[998] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673408, 'op': 'memory_read_request'}
instructions[1002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673408, 'op': 'memory_read_wait'}
instructions[1004] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673408, 'element_size': 2, 'op': 'memory_read'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd13, 8'd0, 8'd140, 32'd1139};//{'src': 140, 'label': 1139, 'op': 'jmp_if_false'}
instructions[1011] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1013] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1014] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1017] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673984, 'op': 'memory_read_request'}
instructions[1018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673984, 'op': 'memory_read_wait'}
instructions[1020] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673984, 'element_size': 2, 'op': 'memory_read'}
instructions[1021] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[1022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd13, 8'd0, 8'd140, 32'd1042};//{'src': 140, 'label': 1042, 'op': 'jmp_if_false'}
instructions[1028] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1034] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810674272, 'op': 'memory_read_request'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810674272, 'op': 'memory_read_wait'}
instructions[1037] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810674272, 'element_size': 2, 'op': 'memory_read'}
instructions[1038] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1044] = {6'd13, 8'd0, 8'd140, 32'd1138};//{'src': 140, 'label': 1138, 'op': 'jmp_if_false'}
instructions[1045] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[1046] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd11, 8'd142, 8'd141, 32'd40};//{'dest': 142, 'src': 141, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[1050] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1053] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[1054] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd11, 8'd142, 8'd141, 32'd41};//{'dest': 142, 'src': 141, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[1058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1060] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1061] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1067] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810687992, 'op': 'memory_read_request'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810687992, 'op': 'memory_read_wait'}
instructions[1070] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810687992, 'element_size': 2, 'op': 'memory_read'}
instructions[1071] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1074] = {6'd11, 8'd142, 8'd141, 32'd42};//{'dest': 142, 'src': 141, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1078] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688424, 'op': 'memory_read_request'}
instructions[1085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1086] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688424, 'op': 'memory_read_wait'}
instructions[1087] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810688424, 'element_size': 2, 'op': 'memory_read'}
instructions[1088] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd11, 8'd142, 8'd141, 32'd43};//{'dest': 142, 'src': 141, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1094] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1095] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1098] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1101] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688856, 'op': 'memory_read_request'}
instructions[1102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1103] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688856, 'op': 'memory_read_wait'}
instructions[1104] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810688856, 'element_size': 2, 'op': 'memory_read'}
instructions[1105] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd11, 8'd142, 8'd141, 32'd44};//{'dest': 142, 'src': 141, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1111] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1112] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[1116] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1117] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd25, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1126] = {6'd13, 8'd0, 8'd140, 32'd1132};//{'src': 140, 'label': 1132, 'op': 'jmp_if_false'}
instructions[1127] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd3, 8'd45, 8'd140, 32'd0};//{'dest': 45, 'src': 140, 'op': 'move'}
instructions[1131] = {6'd15, 8'd0, 8'd0, 32'd1132};//{'label': 1132, 'op': 'goto'}
instructions[1132] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[1133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[1136] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1137] = {6'd15, 8'd0, 8'd0, 32'd1138};//{'label': 1138, 'op': 'goto'}
instructions[1138] = {6'd15, 8'd0, 8'd0, 32'd1139};//{'label': 1139, 'op': 'goto'}
instructions[1139] = {6'd15, 8'd0, 8'd0, 32'd927};//{'label': 927, 'op': 'goto'}
instructions[1140] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1141] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1142] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1143] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1146] = {6'd3, 8'd48, 8'd141, 32'd0};//{'dest': 48, 'src': 141, 'op': 'move'}
instructions[1147] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1150] = {6'd3, 8'd49, 8'd141, 32'd0};//{'dest': 49, 'src': 141, 'op': 'move'}
instructions[1151] = {6'd1, 8'd46, 8'd0, 32'd754};//{'dest': 46, 'label': 754, 'op': 'jmp_and_link'}
instructions[1152] = {6'd3, 8'd140, 8'd47, 32'd0};//{'dest': 140, 'src': 47, 'op': 'move'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1155] = {6'd3, 8'd62, 8'd140, 32'd0};//{'dest': 62, 'src': 140, 'op': 'move'}
instructions[1156] = {6'd0, 8'd140, 8'd0, 32'd17664};//{'dest': 140, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1157] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1160] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1161] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1163] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1164] = {6'd3, 8'd140, 8'd56, 32'd0};//{'dest': 140, 'src': 56, 'op': 'move'}
instructions[1165] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1173] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1176] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1179] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1180] = {6'd0, 8'd140, 8'd0, 32'd16384};//{'dest': 140, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1181] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1184] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1188] = {6'd3, 8'd146, 8'd57, 32'd0};//{'dest': 146, 'src': 57, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd30, 8'd140, 8'd146, 32'd65280};//{'src': 146, 'dest': 140, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1192] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1199] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1200] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1207] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1208] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1215] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1216] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1219] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1222] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1223] = {6'd3, 8'd140, 8'd58, 32'd0};//{'dest': 140, 'src': 58, 'op': 'move'}
instructions[1224] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1227] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1231] = {6'd3, 8'd140, 8'd59, 32'd0};//{'dest': 140, 'src': 59, 'op': 'move'}
instructions[1232] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1235] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1238] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1239] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1242] = {6'd14, 8'd140, 8'd141, 32'd14};//{'src': 141, 'right': 14, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1245] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1246] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1247] = {6'd0, 8'd140, 8'd0, 32'd7};//{'dest': 140, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1250] = {6'd3, 8'd61, 8'd140, 32'd0};//{'dest': 61, 'src': 140, 'op': 'move'}
instructions[1251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd31, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd13, 8'd0, 8'd140, 32'd1277};//{'src': 140, 'label': 1277, 'op': 'jmp_if_false'}
instructions[1260] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd11, 8'd146, 8'd142, 32'd55};//{'dest': 146, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810743112, 'op': 'memory_read_request'}
instructions[1267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1268] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810743112, 'op': 'memory_read_wait'}
instructions[1269] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810743112, 'element_size': 2, 'op': 'memory_read'}
instructions[1270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1273] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1274] = {6'd3, 8'd140, 8'd61, 32'd0};//{'dest': 140, 'src': 61, 'op': 'move'}
instructions[1275] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1276] = {6'd15, 8'd0, 8'd0, 32'd1251};//{'label': 1251, 'op': 'goto'}
instructions[1277] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1278] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1279] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1286] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd28, 8'd140, 8'd141, 32'd64};//{'src': 141, 'right': 64, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1292] = {6'd13, 8'd0, 8'd140, 32'd1298};//{'src': 140, 'label': 1298, 'op': 'jmp_if_false'}
instructions[1293] = {6'd0, 8'd140, 8'd0, 32'd64};//{'dest': 140, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1296] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1297] = {6'd15, 8'd0, 8'd0, 32'd1298};//{'label': 1298, 'op': 'goto'}
instructions[1298] = {6'd3, 8'd143, 8'd55, 32'd0};//{'dest': 143, 'src': 55, 'op': 'move'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd3, 8'd26, 8'd143, 32'd0};//{'dest': 26, 'src': 143, 'op': 'move'}
instructions[1302] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[1306] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd11, 8'd146, 8'd142, 32'd42};//{'dest': 146, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1312] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810748928, 'op': 'memory_read_request'}
instructions[1313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810748928, 'op': 'memory_read_wait'}
instructions[1315] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810748928, 'element_size': 2, 'op': 'memory_read'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[1319] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd11, 8'd146, 8'd142, 32'd43};//{'dest': 146, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749072, 'op': 'memory_read_request'}
instructions[1326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1327] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749072, 'op': 'memory_read_wait'}
instructions[1328] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749072, 'element_size': 2, 'op': 'memory_read'}
instructions[1329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[1332] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd11, 8'd146, 8'd142, 32'd44};//{'dest': 146, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749216, 'op': 'memory_read_request'}
instructions[1339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1340] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749216, 'op': 'memory_read_wait'}
instructions[1341] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749216, 'element_size': 2, 'op': 'memory_read'}
instructions[1342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[1345] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[1349] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1350] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1351] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1352] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1353] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1354] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1355] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1357] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1358] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1359] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1360] = {6'd3, 8'd143, 8'd65, 32'd0};//{'dest': 143, 'src': 65, 'op': 'move'}
instructions[1361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd3, 8'd36, 8'd143, 32'd0};//{'dest': 36, 'src': 143, 'op': 'move'}
instructions[1364] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1365] = {6'd3, 8'd140, 8'd35, 32'd0};//{'dest': 140, 'src': 35, 'op': 'move'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1368] = {6'd3, 8'd74, 8'd140, 32'd0};//{'dest': 74, 'src': 140, 'op': 'move'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1371] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1374] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1377] = {6'd13, 8'd0, 8'd140, 32'd1384};//{'src': 140, 'label': 1384, 'op': 'jmp_if_false'}
instructions[1378] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1382] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1383] = {6'd15, 8'd0, 8'd0, 32'd1384};//{'label': 1384, 'op': 'goto'}
instructions[1384] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1387] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1390] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749936, 'op': 'memory_read_request'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749936, 'op': 'memory_read_wait'}
instructions[1393] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749936, 'element_size': 2, 'op': 'memory_read'}
instructions[1394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd26, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1399] = {6'd13, 8'd0, 8'd140, 32'd1406};//{'src': 140, 'label': 1406, 'op': 'jmp_if_false'}
instructions[1400] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1404] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1405] = {6'd15, 8'd0, 8'd0, 32'd1406};//{'label': 1406, 'op': 'goto'}
instructions[1406] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1409] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1412] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750440, 'op': 'memory_read_request'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750440, 'op': 'memory_read_wait'}
instructions[1415] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810750440, 'element_size': 2, 'op': 'memory_read'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1418] = {6'd26, 8'd140, 8'd141, 32'd49320};//{'src': 141, 'right': 49320, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd13, 8'd0, 8'd140, 32'd1428};//{'src': 140, 'label': 1428, 'op': 'jmp_if_false'}
instructions[1422] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1426] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1427] = {6'd15, 8'd0, 8'd0, 32'd1428};//{'label': 1428, 'op': 'goto'}
instructions[1428] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1431] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750944, 'op': 'memory_read_request'}
instructions[1435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750944, 'op': 'memory_read_wait'}
instructions[1437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810750944, 'element_size': 2, 'op': 'memory_read'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1440] = {6'd26, 8'd140, 8'd141, 32'd119};//{'src': 141, 'right': 119, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1443] = {6'd13, 8'd0, 8'd140, 32'd1450};//{'src': 140, 'label': 1450, 'op': 'jmp_if_false'}
instructions[1444] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1447] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1448] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1449] = {6'd15, 8'd0, 8'd0, 32'd1450};//{'label': 1450, 'op': 'goto'}
instructions[1450] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811492968, 'op': 'memory_read_request'}
instructions[1457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1458] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811492968, 'op': 'memory_read_wait'}
instructions[1459] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811492968, 'element_size': 2, 'op': 'memory_read'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1462] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1465] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd13, 8'd0, 8'd140, 32'd1675};//{'src': 140, 'label': 1675, 'op': 'jmp_if_false'}
instructions[1469] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1472] = {6'd11, 8'd149, 8'd147, 32'd65};//{'dest': 149, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1475] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810781056, 'op': 'memory_read_request'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810781056, 'op': 'memory_read_wait'}
instructions[1478] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810781056, 'element_size': 2, 'op': 'memory_read'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1481] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1484] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1487] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1490] = {6'd3, 8'd67, 8'd140, 32'd0};//{'dest': 67, 'src': 140, 'op': 'move'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1493] = {6'd3, 8'd141, 8'd67, 32'd0};//{'dest': 141, 'src': 67, 'op': 'move'}
instructions[1494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1496] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1499] = {6'd3, 8'd68, 8'd140, 32'd0};//{'dest': 68, 'src': 140, 'op': 'move'}
instructions[1500] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1503] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1506] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810751160, 'op': 'memory_read_request'}
instructions[1507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1508] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810751160, 'op': 'memory_read_wait'}
instructions[1509] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810751160, 'element_size': 2, 'op': 'memory_read'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1512] = {6'd3, 8'd66, 8'd140, 32'd0};//{'dest': 66, 'src': 140, 'op': 'move'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1515] = {6'd3, 8'd146, 8'd66, 32'd0};//{'dest': 146, 'src': 66, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd14, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1522] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1528] = {6'd3, 8'd69, 8'd140, 32'd0};//{'dest': 69, 'src': 140, 'op': 'move'}
instructions[1529] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1531] = {6'd3, 8'd146, 8'd69, 32'd0};//{'dest': 146, 'src': 69, 'op': 'move'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1534] = {6'd11, 8'd141, 8'd142, 32'd146};//{'srcb': 146, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1537] = {6'd35, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1540] = {6'd3, 8'd73, 8'd140, 32'd0};//{'dest': 73, 'src': 140, 'op': 'move'}
instructions[1541] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1544] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1547] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810744192, 'op': 'memory_read_request'}
instructions[1548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1549] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810744192, 'op': 'memory_read_wait'}
instructions[1550] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810744192, 'element_size': 2, 'op': 'memory_read'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1553] = {6'd25, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1556] = {6'd13, 8'd0, 8'd140, 32'd1669};//{'src': 140, 'label': 1669, 'op': 'jmp_if_false'}
instructions[1557] = {6'd0, 8'd140, 8'd0, 32'd19};//{'dest': 140, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1558] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1560] = {6'd3, 8'd72, 8'd140, 32'd0};//{'dest': 72, 'src': 140, 'op': 'move'}
instructions[1561] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1562] = {6'd3, 8'd141, 8'd68, 32'd0};//{'dest': 141, 'src': 68, 'op': 'move'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1565] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1568] = {6'd3, 8'd71, 8'd140, 32'd0};//{'dest': 71, 'src': 140, 'op': 'move'}
instructions[1569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1571] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1572] = {6'd3, 8'd142, 8'd73, 32'd0};//{'dest': 142, 'src': 73, 'op': 'move'}
instructions[1573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd36, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd13, 8'd0, 8'd140, 32'd1612};//{'src': 140, 'label': 1612, 'op': 'jmp_if_false'}
instructions[1579] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1580] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1585] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810779904, 'op': 'memory_read_request'}
instructions[1586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1587] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810779904, 'op': 'memory_read_wait'}
instructions[1588] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810779904, 'element_size': 2, 'op': 'memory_read'}
instructions[1589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1591] = {6'd3, 8'd70, 8'd140, 32'd0};//{'dest': 70, 'src': 140, 'op': 'move'}
instructions[1592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1594] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1596] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1597] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1598] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1599] = {6'd3, 8'd140, 8'd70, 32'd0};//{'dest': 140, 'src': 70, 'op': 'move'}
instructions[1600] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1603] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1606] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1607] = {6'd3, 8'd140, 8'd72, 32'd0};//{'dest': 140, 'src': 72, 'op': 'move'}
instructions[1608] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1609] = {6'd3, 8'd140, 8'd71, 32'd0};//{'dest': 140, 'src': 71, 'op': 'move'}
instructions[1610] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1611] = {6'd15, 8'd0, 8'd0, 32'd1569};//{'label': 1569, 'op': 'goto'}
instructions[1612] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1613] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1620] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1621] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1622] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1628] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1629] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[1630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd3, 8'd55, 8'd148, 32'd0};//{'dest': 55, 'src': 148, 'op': 'move'}
instructions[1633] = {6'd3, 8'd141, 8'd66, 32'd0};//{'dest': 141, 'src': 66, 'op': 'move'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[1637] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[1641] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1644] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1647] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264096, 'op': 'memory_read_request'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264096, 'op': 'memory_read_wait'}
instructions[1650] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810264096, 'element_size': 2, 'op': 'memory_read'}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[1654] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1657] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264240, 'op': 'memory_read_request'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264240, 'op': 'memory_read_wait'}
instructions[1663] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810264240, 'element_size': 2, 'op': 'memory_read'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1666] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[1667] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[1668] = {6'd15, 8'd0, 8'd0, 32'd1669};//{'label': 1669, 'op': 'goto'}
instructions[1669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1673] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1674] = {6'd15, 8'd0, 8'd0, 32'd1675};//{'label': 1675, 'op': 'goto'}
instructions[1675] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1678] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1681] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810264672, 'op': 'memory_read_request'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810264672, 'op': 'memory_read_wait'}
instructions[1684] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810264672, 'element_size': 2, 'op': 'memory_read'}
instructions[1685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1687] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd26, 8'd140, 8'd141, 32'd6};//{'src': 141, 'right': 6, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd13, 8'd0, 8'd140, 32'd1700};//{'src': 140, 'label': 1700, 'op': 'jmp_if_false'}
instructions[1694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1697] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1698] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1699] = {6'd15, 8'd0, 8'd0, 32'd1700};//{'label': 1700, 'op': 'goto'}
instructions[1700] = {6'd3, 8'd140, 8'd74, 32'd0};//{'dest': 140, 'src': 74, 'op': 'move'}
instructions[1701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1704] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1705] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1706] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1707] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1708] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1709] = {6'd3, 8'd140, 8'd77, 32'd0};//{'dest': 140, 'src': 77, 'op': 'move'}
instructions[1710] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1713] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1716] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1719] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1720] = {6'd3, 8'd140, 8'd78, 32'd0};//{'dest': 140, 'src': 78, 'op': 'move'}
instructions[1721] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1724] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1727] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1730] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1731] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810299664, 'op': 'memory_read_request'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810299664, 'op': 'memory_read_wait'}
instructions[1740] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810299664, 'element_size': 2, 'op': 'memory_read'}
instructions[1741] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd14, 8'd141, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1751] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1757] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300240, 'op': 'memory_read_request'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300240, 'op': 'memory_read_wait'}
instructions[1760] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810300240, 'element_size': 2, 'op': 'memory_read'}
instructions[1761] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd141, 8'd146, 32'd3};//{'src': 146, 'right': 3, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1777] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300816, 'op': 'memory_read_request'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300816, 'op': 'memory_read_wait'}
instructions[1780] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810300816, 'element_size': 2, 'op': 'memory_read'}
instructions[1781] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd14, 8'd141, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1791] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810301392, 'op': 'memory_read_request'}
instructions[1798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1799] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810301392, 'op': 'memory_read_wait'}
instructions[1800] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810301392, 'element_size': 2, 'op': 'memory_read'}
instructions[1801] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1804] = {6'd14, 8'd141, 8'd146, 32'd5};//{'src': 146, 'right': 5, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1807] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1811] = {6'd0, 8'd140, 8'd0, 32'd20480};//{'dest': 140, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1812] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1822] = {6'd3, 8'd140, 8'd82, 32'd0};//{'dest': 140, 'src': 82, 'op': 'move'}
instructions[1823] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1834] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1844] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1845] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1848] = {6'd14, 8'd141, 8'd146, 32'd9};//{'src': 146, 'right': 9, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1851] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1854] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1855] = {6'd3, 8'd140, 8'd83, 32'd0};//{'dest': 140, 'src': 83, 'op': 'move'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1858] = {6'd13, 8'd0, 8'd140, 32'd1886};//{'src': 140, 'label': 1886, 'op': 'jmp_if_false'}
instructions[1859] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1865] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533136, 'op': 'memory_read_request'}
instructions[1869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1870] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533136, 'op': 'memory_read_wait'}
instructions[1871] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811533136, 'element_size': 2, 'op': 'memory_read'}
instructions[1872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd37, 8'd140, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1875] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1881] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1885] = {6'd15, 8'd0, 8'd0, 32'd1886};//{'label': 1886, 'op': 'goto'}
instructions[1886] = {6'd3, 8'd140, 8'd84, 32'd0};//{'dest': 140, 'src': 84, 'op': 'move'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1889] = {6'd13, 8'd0, 8'd140, 32'd1917};//{'src': 140, 'label': 1917, 'op': 'jmp_if_false'}
instructions[1890] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1896] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533856, 'op': 'memory_read_request'}
instructions[1900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1901] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533856, 'op': 'memory_read_wait'}
instructions[1902] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811533856, 'element_size': 2, 'op': 'memory_read'}
instructions[1903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd37, 8'd140, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1906] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1912] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1916] = {6'd15, 8'd0, 8'd0, 32'd1917};//{'label': 1917, 'op': 'goto'}
instructions[1917] = {6'd3, 8'd140, 8'd85, 32'd0};//{'dest': 140, 'src': 85, 'op': 'move'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1920] = {6'd13, 8'd0, 8'd140, 32'd1948};//{'src': 140, 'label': 1948, 'op': 'jmp_if_false'}
instructions[1921] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1927] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811534576, 'op': 'memory_read_request'}
instructions[1931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1932] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811534576, 'op': 'memory_read_wait'}
instructions[1933] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811534576, 'element_size': 2, 'op': 'memory_read'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd37, 8'd140, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1937] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1943] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1947] = {6'd15, 8'd0, 8'd0, 32'd1948};//{'label': 1948, 'op': 'goto'}
instructions[1948] = {6'd3, 8'd140, 8'd86, 32'd0};//{'dest': 140, 'src': 86, 'op': 'move'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd13, 8'd0, 8'd140, 32'd1979};//{'src': 140, 'label': 1979, 'op': 'jmp_if_false'}
instructions[1952] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1961] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327040, 'op': 'memory_read_request'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327040, 'op': 'memory_read_wait'}
instructions[1964] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810327040, 'element_size': 2, 'op': 'memory_read'}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd37, 8'd140, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1968] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1971] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1974] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1978] = {6'd15, 8'd0, 8'd0, 32'd1979};//{'label': 1979, 'op': 'goto'}
instructions[1979] = {6'd3, 8'd140, 8'd87, 32'd0};//{'dest': 140, 'src': 87, 'op': 'move'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1982] = {6'd13, 8'd0, 8'd140, 32'd2010};//{'src': 140, 'label': 2010, 'op': 'jmp_if_false'}
instructions[1983] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1986] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1989] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1992] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327760, 'op': 'memory_read_request'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327760, 'op': 'memory_read_wait'}
instructions[1995] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810327760, 'element_size': 2, 'op': 'memory_read'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd37, 8'd140, 8'd146, 32'd16};//{'src': 146, 'right': 16, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1999] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2002] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2005] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2008] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2009] = {6'd15, 8'd0, 8'd0, 32'd2010};//{'label': 2010, 'op': 'goto'}
instructions[2010] = {6'd3, 8'd140, 8'd88, 32'd0};//{'dest': 140, 'src': 88, 'op': 'move'}
instructions[2011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2013] = {6'd13, 8'd0, 8'd140, 32'd2041};//{'src': 140, 'label': 2041, 'op': 'jmp_if_false'}
instructions[2014] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2017] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2020] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2023] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810328480, 'op': 'memory_read_request'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810328480, 'op': 'memory_read_wait'}
instructions[2026] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810328480, 'element_size': 2, 'op': 'memory_read'}
instructions[2027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd37, 8'd140, 8'd146, 32'd32};//{'src': 146, 'right': 32, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[2030] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2038] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2039] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2040] = {6'd15, 8'd0, 8'd0, 32'd2041};//{'label': 2041, 'op': 'goto'}
instructions[2041] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[2042] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2046] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2047] = {6'd0, 8'd141, 8'd0, 32'd119};//{'dest': 141, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2050] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2051] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2052] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2055] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2056] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2057] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2060] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2061] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2062] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2066] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2067] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2070] = {6'd14, 8'd141, 8'd142, 32'd20};//{'src': 142, 'right': 20, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2073] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2074] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2075] = {6'd3, 8'd146, 8'd99, 32'd0};//{'dest': 146, 'src': 99, 'op': 'move'}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd14, 8'd142, 8'd146, 32'd20};//{'src': 146, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd32, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd101, 8'd140, 32'd0};//{'dest': 101, 'src': 140, 'op': 'move'}
instructions[2088] = {6'd3, 8'd140, 8'd100, 32'd0};//{'dest': 140, 'src': 100, 'op': 'move'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2091] = {6'd3, 8'd102, 8'd140, 32'd0};//{'dest': 102, 'src': 140, 'op': 'move'}
instructions[2092] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2094] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2095] = {6'd3, 8'd103, 8'd140, 32'd0};//{'dest': 103, 'src': 140, 'op': 'move'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2098] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[2099] = {6'd3, 8'd142, 8'd101, 32'd0};//{'dest': 142, 'src': 101, 'op': 'move'}
instructions[2100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd13, 8'd0, 8'd140, 32'd2125};//{'src': 140, 'label': 2125, 'op': 'jmp_if_false'}
instructions[2106] = {6'd3, 8'd142, 8'd102, 32'd0};//{'dest': 142, 'src': 102, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd11, 8'd146, 8'd142, 32'd98};//{'dest': 146, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810349176, 'op': 'memory_read_request'}
instructions[2113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2114] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810349176, 'op': 'memory_read_wait'}
instructions[2115] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810349176, 'element_size': 2, 'op': 'memory_read'}
instructions[2116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2119] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2120] = {6'd3, 8'd140, 8'd102, 32'd0};//{'dest': 140, 'src': 102, 'op': 'move'}
instructions[2121] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2122] = {6'd3, 8'd140, 8'd103, 32'd0};//{'dest': 140, 'src': 103, 'op': 'move'}
instructions[2123] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2124] = {6'd15, 8'd0, 8'd0, 32'd2096};//{'label': 2096, 'op': 'goto'}
instructions[2125] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2126] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[2127] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2130] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2133] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2136] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2137] = {6'd3, 8'd143, 8'd98, 32'd0};//{'dest': 143, 'src': 98, 'op': 'move'}
instructions[2138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd3, 8'd55, 8'd143, 32'd0};//{'dest': 55, 'src': 143, 'op': 'move'}
instructions[2141] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2142] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd14, 8'd141, 8'd142, 32'd40};//{'src': 142, 'right': 40, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[2148] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2151] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[2152] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[2156] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2159] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[2160] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[2161] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2162] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2163] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2164] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2165] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2166] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2167] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2168] = {6'd3, 8'd143, 8'd108, 32'd0};//{'dest': 143, 'src': 108, 'op': 'move'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd3, 8'd65, 8'd143, 32'd0};//{'dest': 65, 'src': 143, 'op': 'move'}
instructions[2172] = {6'd1, 8'd63, 8'd0, 32'd1351};//{'dest': 63, 'label': 1351, 'op': 'jmp_and_link'}
instructions[2173] = {6'd3, 8'd140, 8'd64, 32'd0};//{'dest': 140, 'src': 64, 'op': 'move'}
instructions[2174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd3, 8'd109, 8'd140, 32'd0};//{'dest': 109, 'src': 140, 'op': 'move'}
instructions[2177] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd11, 8'd149, 8'd147, 32'd108};//{'dest': 149, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810371096, 'op': 'memory_read_request'}
instructions[2184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2185] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810371096, 'op': 'memory_read_wait'}
instructions[2186] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810371096, 'element_size': 2, 'op': 'memory_read'}
instructions[2187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2195] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2198] = {6'd3, 8'd110, 8'd140, 32'd0};//{'dest': 110, 'src': 140, 'op': 'move'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2201] = {6'd3, 8'd141, 8'd110, 32'd0};//{'dest': 141, 'src': 110, 'op': 'move'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2204] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2207] = {6'd3, 8'd111, 8'd140, 32'd0};//{'dest': 111, 'src': 140, 'op': 'move'}
instructions[2208] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2211] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2214] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810777744, 'op': 'memory_read_request'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810777744, 'op': 'memory_read_wait'}
instructions[2217] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810777744, 'element_size': 2, 'op': 'memory_read'}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd3, 8'd112, 8'd140, 32'd0};//{'dest': 112, 'src': 140, 'op': 'move'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd3, 8'd141, 8'd112, 32'd0};//{'dest': 141, 'src': 112, 'op': 'move'}
instructions[2224] = {6'd3, 8'd146, 8'd110, 32'd0};//{'dest': 146, 'src': 110, 'op': 'move'}
instructions[2225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2227] = {6'd33, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd3, 8'd113, 8'd140, 32'd0};//{'dest': 113, 'src': 140, 'op': 'move'}
instructions[2234] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd146, 8'd149, 32'd6};//{'src': 149, 'right': 6, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381872, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381872, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810381872, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd12, 8'd141, 8'd142, 32'd61440};//{'src': 142, 'right': 61440, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd32, 8'd140, 8'd141, 32'd10};//{'src': 141, 'right': 10, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2255] = {6'd3, 8'd114, 8'd140, 32'd0};//{'dest': 114, 'src': 140, 'op': 'move'}
instructions[2256] = {6'd3, 8'd141, 8'd113, 32'd0};//{'dest': 141, 'src': 113, 'op': 'move'}
instructions[2257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2258] = {6'd3, 8'd142, 8'd114, 32'd0};//{'dest': 142, 'src': 114, 'op': 'move'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2261] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2264] = {6'd3, 8'd104, 8'd140, 32'd0};//{'dest': 104, 'src': 140, 'op': 'move'}
instructions[2265] = {6'd3, 8'd141, 8'd111, 32'd0};//{'dest': 141, 'src': 111, 'op': 'move'}
instructions[2266] = {6'd3, 8'd146, 8'd114, 32'd0};//{'dest': 146, 'src': 114, 'op': 'move'}
instructions[2267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd32, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2275] = {6'd3, 8'd105, 8'd140, 32'd0};//{'dest': 105, 'src': 140, 'op': 'move'}
instructions[2276] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810351048, 'op': 'memory_read_request'}
instructions[2286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2287] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810351048, 'op': 'memory_read_wait'}
instructions[2288] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810351048, 'element_size': 2, 'op': 'memory_read'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2291] = {6'd3, 8'd89, 8'd140, 32'd0};//{'dest': 89, 'src': 140, 'op': 'move'}
instructions[2292] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810367712, 'op': 'memory_read_request'}
instructions[2302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2303] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810367712, 'op': 'memory_read_wait'}
instructions[2304] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810367712, 'element_size': 2, 'op': 'memory_read'}
instructions[2305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2307] = {6'd3, 8'd90, 8'd140, 32'd0};//{'dest': 90, 'src': 140, 'op': 'move'}
instructions[2308] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd14, 8'd146, 8'd149, 32'd2};//{'src': 149, 'right': 2, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380504, 'op': 'memory_read_request'}
instructions[2318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2319] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380504, 'op': 'memory_read_wait'}
instructions[2320] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810380504, 'element_size': 2, 'op': 'memory_read'}
instructions[2321] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2328] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd14, 8'd146, 8'd149, 32'd3};//{'src': 149, 'right': 3, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2337] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380648, 'op': 'memory_read_request'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380648, 'op': 'memory_read_wait'}
instructions[2340] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810380648, 'element_size': 2, 'op': 'memory_read'}
instructions[2341] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2344] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2348] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2351] = {6'd14, 8'd146, 8'd149, 32'd4};//{'src': 149, 'right': 4, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2354] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2357] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381368, 'op': 'memory_read_request'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381368, 'op': 'memory_read_wait'}
instructions[2360] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810381368, 'element_size': 2, 'op': 'memory_read'}
instructions[2361] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2364] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2367] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2368] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd14, 8'd146, 8'd149, 32'd5};//{'src': 149, 'right': 5, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810382160, 'op': 'memory_read_request'}
instructions[2378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2379] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810382160, 'op': 'memory_read_wait'}
instructions[2380] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810382160, 'element_size': 2, 'op': 'memory_read'}
instructions[2381] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2388] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2391] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810382664, 'op': 'memory_read_request'}
instructions[2398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2399] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810382664, 'op': 'memory_read_wait'}
instructions[2400] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810382664, 'element_size': 2, 'op': 'memory_read'}
instructions[2401] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2407] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2410] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383168, 'op': 'memory_read_request'}
instructions[2411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2412] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383168, 'op': 'memory_read_wait'}
instructions[2413] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810383168, 'element_size': 2, 'op': 'memory_read'}
instructions[2414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd12, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2419] = {6'd3, 8'd93, 8'd140, 32'd0};//{'dest': 93, 'src': 140, 'op': 'move'}
instructions[2420] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2426] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2429] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383816, 'op': 'memory_read_request'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383816, 'op': 'memory_read_wait'}
instructions[2432] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810383816, 'element_size': 2, 'op': 'memory_read'}
instructions[2433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2435] = {6'd12, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2438] = {6'd3, 8'd94, 8'd140, 32'd0};//{'dest': 94, 'src': 140, 'op': 'move'}
instructions[2439] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2442] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2445] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2448] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810396816, 'op': 'memory_read_request'}
instructions[2449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2450] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810396816, 'op': 'memory_read_wait'}
instructions[2451] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810396816, 'element_size': 2, 'op': 'memory_read'}
instructions[2452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2454] = {6'd12, 8'd140, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2457] = {6'd3, 8'd95, 8'd140, 32'd0};//{'dest': 95, 'src': 140, 'op': 'move'}
instructions[2458] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2461] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2464] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2467] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810397464, 'op': 'memory_read_request'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810397464, 'op': 'memory_read_wait'}
instructions[2470] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810397464, 'element_size': 2, 'op': 'memory_read'}
instructions[2471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd12, 8'd140, 8'd141, 32'd8};//{'src': 141, 'right': 8, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2474] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2483] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398112, 'op': 'memory_read_request'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398112, 'op': 'memory_read_wait'}
instructions[2486] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810398112, 'element_size': 2, 'op': 'memory_read'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2489] = {6'd12, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2492] = {6'd3, 8'd96, 8'd140, 32'd0};//{'dest': 96, 'src': 140, 'op': 'move'}
instructions[2493] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2499] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398760, 'op': 'memory_read_request'}
instructions[2503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2504] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398760, 'op': 'memory_read_wait'}
instructions[2505] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810398760, 'element_size': 2, 'op': 'memory_read'}
instructions[2506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2508] = {6'd12, 8'd140, 8'd141, 32'd32};//{'src': 141, 'right': 32, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2509] = {6'd3, 8'd140, 8'd109, 32'd0};//{'dest': 140, 'src': 109, 'op': 'move'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2512] = {6'd3, 8'd107, 8'd140, 32'd0};//{'dest': 107, 'src': 140, 'op': 'move'}
instructions[2513] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2514] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd3, 8'd140, 8'd117, 32'd0};//{'dest': 140, 'src': 117, 'op': 'move'}
instructions[2517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2519] = {6'd3, 8'd120, 8'd140, 32'd0};//{'dest': 120, 'src': 140, 'op': 'move'}
instructions[2520] = {6'd3, 8'd141, 8'd118, 32'd0};//{'dest': 141, 'src': 118, 'op': 'move'}
instructions[2521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2523] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2524] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2525] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2532] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd13, 8'd0, 8'd140, 32'd2563};//{'src': 140, 'label': 2563, 'op': 'jmp_if_false'}
instructions[2539] = {6'd3, 8'd142, 8'd120, 32'd0};//{'dest': 142, 'src': 120, 'op': 'move'}
instructions[2540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd11, 8'd146, 8'd142, 32'd116};//{'dest': 146, 'src': 142, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2545] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810422904, 'op': 'memory_read_request'}
instructions[2546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2547] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810422904, 'op': 'memory_read_wait'}
instructions[2548] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810422904, 'element_size': 2, 'op': 'memory_read'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2551] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2552] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2553] = {6'd3, 8'd140, 8'd120, 32'd0};//{'dest': 140, 'src': 120, 'op': 'move'}
instructions[2554] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2555] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2562] = {6'd15, 8'd0, 8'd0, 32'd2529};//{'label': 2529, 'op': 'goto'}
instructions[2563] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2564] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2565] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2566] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2567] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd39, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd13, 8'd0, 8'd140, 32'd2580};//{'src': 140, 'label': 2580, 'op': 'jmp_if_false'}
instructions[2574] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2578] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2579] = {6'd15, 8'd0, 8'd0, 32'd2580};//{'label': 2580, 'op': 'goto'}
instructions[2580] = {6'd3, 8'd140, 8'd124, 32'd0};//{'dest': 140, 'src': 124, 'op': 'move'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd126, 8'd140, 32'd0};//{'dest': 126, 'src': 140, 'op': 'move'}
instructions[2584] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2585] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd3, 8'd127, 8'd140, 32'd0};//{'dest': 127, 'src': 140, 'op': 'move'}
instructions[2589] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2592] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2596] = {6'd3, 8'd142, 8'd127, 32'd0};//{'dest': 142, 'src': 127, 'op': 'move'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2602] = {6'd13, 8'd0, 8'd140, 32'd2622};//{'src': 140, 'label': 2622, 'op': 'jmp_if_false'}
instructions[2603] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2604] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2605] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2608] = {6'd11, 8'd142, 8'd141, 32'd123};//{'dest': 142, 'src': 141, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2612] = {6'd3, 8'd140, 8'd126, 32'd0};//{'dest': 140, 'src': 126, 'op': 'move'}
instructions[2613] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2614] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2617] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2621] = {6'd15, 8'd0, 8'd0, 32'd2593};//{'label': 2593, 'op': 'goto'}
instructions[2622] = {6'd3, 8'd140, 8'd127, 32'd0};//{'dest': 140, 'src': 127, 'op': 'move'}
instructions[2623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2625] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2626] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2627] = {6'd0, 8'd129, 8'd0, 32'd638};//{'dest': 129, 'literal': 638, 'op': 'literal'}
instructions[2628] = {6'd0, 8'd130, 8'd0, 32'd1662};//{'dest': 130, 'literal': 1662, 'op': 'literal'}
instructions[2629] = {6'd0, 8'd131, 8'd0, 32'd27};//{'dest': 131, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2630] = {6'd0, 8'd132, 8'd0, 32'd0};//{'dest': 132, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2631] = {6'd0, 8'd133, 8'd0, 32'd0};//{'dest': 133, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2632] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2633] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2634] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2635] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2636] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2637] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2638] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2639] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2642] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2645] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2646] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2647] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2650] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2653] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2654] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2657] = {6'd13, 8'd0, 8'd140, 32'd2661};//{'src': 140, 'label': 2661, 'op': 'jmp_if_false'}
instructions[2658] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2659] = {6'd35, 8'd133, 8'd133, 32'd1};//{'src': 133, 'right': 1, 'dest': 133, 'signed': False, 'op': '-', 'size': 2}
instructions[2660] = {6'd15, 8'd0, 8'd0, 32'd2928};//{'label': 2928, 'op': 'goto'}
instructions[2661] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2664] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[2665] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2668] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[2669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2672] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2673] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2676] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2677] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2680] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2681] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2684] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2685] = {6'd0, 8'd140, 8'd0, 32'd46};//{'dest': 140, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2688] = {6'd40, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': True, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'type': 'int', 'op': 'report'}
instructions[2689] = {6'd0, 8'd141, 8'd0, 32'd46};//{'dest': 141, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2690] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2692] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2693] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2697] = {6'd3, 8'd136, 8'd140, 32'd0};//{'dest': 136, 'src': 140, 'op': 'move'}
instructions[2698] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2699] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2704] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2705] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2706] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2707] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2713] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2714] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2715] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2719] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2720] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2721] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2722] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2723] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2729] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2730] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2731] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2737] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2738] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2739] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2740] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2745] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2746] = {6'd0, 8'd140, 8'd0, 32'd2054};//{'dest': 140, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2747] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2753] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2754] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2755] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2761] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2762] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2763] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2764] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2769] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2770] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2771] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2774] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2777] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2778] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2779] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2781] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2782] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2785] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2786] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2787] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2790] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2794] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2795] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2798] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2801] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2802] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2803] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2806] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2809] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2810] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2811] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2812] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2814] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2817] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2818] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2819] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2822] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2825] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2826] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2827] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2829] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2830] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2833] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2834] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2835] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2838] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2841] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2842] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2843] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2845] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2846] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2849] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2850] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2851] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2854] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2857] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2858] = {6'd0, 8'd140, 8'd0, 32'd105};//{'dest': 140, 'literal': 105, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2859] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2865] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2866] = {6'd0, 8'd140, 8'd0, 32'd58291};//{'dest': 140, 'literal': 58291, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2867] = {6'd0, 8'd141, 8'd0, 32'd21};//{'dest': 141, 'literal': 21, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2870] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2873] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2874] = {6'd0, 8'd140, 8'd0, 32'd12976};//{'dest': 140, 'literal': 12976, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2875] = {6'd0, 8'd141, 8'd0, 32'd22};//{'dest': 141, 'literal': 22, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2878] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2881] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2882] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2885] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2888] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2891] = {6'd28, 8'd140, 8'd141, 32'd46};//{'src': 141, 'right': 46, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd13, 8'd0, 8'd140, 32'd2919};//{'src': 140, 'label': 2919, 'op': 'jmp_if_false'}
instructions[2895] = {6'd3, 8'd142, 8'd136, 32'd0};//{'dest': 142, 'src': 136, 'op': 'move'}
instructions[2896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd11, 8'd146, 8'd142, 32'd130};//{'dest': 146, 'src': 142, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2901] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810502240, 'op': 'memory_read_request'}
instructions[2902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2903] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810502240, 'op': 'memory_read_wait'}
instructions[2904] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810502240, 'element_size': 2, 'op': 'memory_read'}
instructions[2905] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2906] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2907] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2908] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2909] = {6'd3, 8'd140, 8'd136, 32'd0};//{'dest': 140, 'src': 136, 'op': 'move'}
instructions[2910] = {6'd14, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '+', 'size': 2}
instructions[2911] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2914] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2918] = {6'd15, 8'd0, 8'd0, 32'd2886};//{'label': 2886, 'op': 'goto'}
instructions[2919] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2923] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2927] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2928] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[2929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2931] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2932] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2934] = {6'd22, 8'd0, 8'd141, 32'd2951};//{'src': 141, 'label': 2951, 'op': 'jmp_if_true'}
instructions[2935] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2936] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2938] = {6'd22, 8'd0, 8'd141, 32'd2968};//{'src': 141, 'label': 2968, 'op': 'jmp_if_true'}
instructions[2939] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2942] = {6'd22, 8'd0, 8'd141, 32'd3034};//{'src': 141, 'label': 3034, 'op': 'jmp_if_true'}
instructions[2943] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2946] = {6'd22, 8'd0, 8'd141, 32'd3113};//{'src': 141, 'label': 3113, 'op': 'jmp_if_true'}
instructions[2947] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2950] = {6'd22, 8'd0, 8'd141, 32'd3123};//{'src': 141, 'label': 3123, 'op': 'jmp_if_true'}
instructions[2951] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2954] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2955] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2958] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2959] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2962] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2963] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2966] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2967] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[2968] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2971] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810452368, 'op': 'memory_read_request'}
instructions[2975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2976] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810452368, 'op': 'memory_read_wait'}
instructions[2977] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810452368, 'element_size': 2, 'op': 'memory_read'}
instructions[2978] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2980] = {6'd3, 8'd75, 8'd140, 32'd0};//{'dest': 75, 'src': 140, 'op': 'move'}
instructions[2981] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2987] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810501808, 'op': 'memory_read_request'}
instructions[2988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2989] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810501808, 'op': 'memory_read_wait'}
instructions[2990] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810501808, 'element_size': 2, 'op': 'memory_read'}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2993] = {6'd3, 8'd76, 8'd140, 32'd0};//{'dest': 76, 'src': 140, 'op': 'move'}
instructions[2994] = {6'd3, 8'd140, 8'd89, 32'd0};//{'dest': 140, 'src': 89, 'op': 'move'}
instructions[2995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2997] = {6'd3, 8'd78, 8'd140, 32'd0};//{'dest': 78, 'src': 140, 'op': 'move'}
instructions[2998] = {6'd0, 8'd140, 8'd0, 32'd80};//{'dest': 140, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3001] = {6'd3, 8'd77, 8'd140, 32'd0};//{'dest': 77, 'src': 140, 'op': 'move'}
instructions[3002] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3005] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3006] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3009] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3010] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3013] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3014] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3015] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3016] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3019] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3020] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3023] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3024] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3027] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3028] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3031] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3032] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3033] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3034] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3037] = {6'd3, 8'd123, 8'd151, 32'd0};//{'dest': 123, 'src': 151, 'op': 'move'}
instructions[3038] = {6'd3, 8'd141, 8'd131, 32'd0};//{'dest': 141, 'src': 131, 'op': 'move'}
instructions[3039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3041] = {6'd3, 8'd124, 8'd141, 32'd0};//{'dest': 124, 'src': 141, 'op': 'move'}
instructions[3042] = {6'd1, 8'd121, 8'd0, 32'd2564};//{'dest': 121, 'label': 2564, 'op': 'jmp_and_link'}
instructions[3043] = {6'd3, 8'd140, 8'd122, 32'd0};//{'dest': 140, 'src': 122, 'op': 'move'}
instructions[3044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd3, 8'd132, 8'd140, 32'd0};//{'dest': 132, 'src': 140, 'op': 'move'}
instructions[3047] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3050] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3053] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810512656, 'op': 'memory_read_request'}
instructions[3054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3055] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810512656, 'op': 'memory_read_wait'}
instructions[3056] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810512656, 'element_size': 2, 'op': 'memory_read'}
instructions[3057] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3060] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3063] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3064] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3067] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3070] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810513088, 'op': 'memory_read_request'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810513088, 'op': 'memory_read_wait'}
instructions[3073] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810513088, 'element_size': 2, 'op': 'memory_read'}
instructions[3074] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3077] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3078] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3080] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3081] = {6'd3, 8'd143, 8'd80, 32'd0};//{'dest': 143, 'src': 80, 'op': 'move'}
instructions[3082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3084] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3085] = {6'd3, 8'd143, 8'd79, 32'd0};//{'dest': 143, 'src': 79, 'op': 'move'}
instructions[3086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3087] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3088] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3089] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3092] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3093] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3094] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3095] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3098] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3099] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3102] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3103] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3106] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3107] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3110] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3111] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3112] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3113] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3116] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3117] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3120] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3121] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3122] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3123] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3126] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[3127] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3130] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3131] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3134] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3135] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3138] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3139] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3142] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3143] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3144] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3145] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3148] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3149] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3152] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3153] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3154] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3155] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3158] = {6'd3, 8'd134, 8'd140, 32'd0};//{'dest': 134, 'src': 140, 'op': 'move'}
instructions[3159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3161] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3164] = {6'd13, 8'd0, 8'd140, 32'd3550};//{'src': 140, 'label': 3550, 'op': 'jmp_if_false'}
instructions[3165] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd3, 8'd108, 8'd151, 32'd0};//{'dest': 108, 'src': 151, 'op': 'move'}
instructions[3169] = {6'd1, 8'd106, 8'd0, 32'd2162};//{'dest': 106, 'label': 2162, 'op': 'jmp_and_link'}
instructions[3170] = {6'd3, 8'd140, 8'd107, 32'd0};//{'dest': 140, 'src': 107, 'op': 'move'}
instructions[3171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[3174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3176] = {6'd3, 8'd140, 8'd135, 32'd0};//{'dest': 140, 'src': 135, 'op': 'move'}
instructions[3177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3179] = {6'd13, 8'd0, 8'd140, 32'd3184};//{'src': 140, 'label': 3184, 'op': 'jmp_if_false'}
instructions[3180] = {6'd3, 8'd141, 8'd90, 32'd0};//{'dest': 141, 'src': 90, 'op': 'move'}
instructions[3181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3183] = {6'd25, 8'd140, 8'd141, 32'd80};//{'src': 141, 'right': 80, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3186] = {6'd13, 8'd0, 8'd140, 32'd3543};//{'src': 140, 'label': 3543, 'op': 'jmp_if_false'}
instructions[3187] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd26, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3192] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3193] = {6'd13, 8'd0, 8'd140, 32'd3199};//{'src': 140, 'label': 3199, 'op': 'jmp_if_false'}
instructions[3194] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3195] = {6'd3, 8'd142, 8'd78, 32'd0};//{'dest': 142, 'src': 78, 'op': 'move'}
instructions[3196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3201] = {6'd13, 8'd0, 8'd140, 32'd3204};//{'src': 140, 'label': 3204, 'op': 'jmp_if_false'}
instructions[3202] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3203] = {6'd15, 8'd0, 8'd0, 32'd3204};//{'label': 3204, 'op': 'goto'}
instructions[3204] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3207] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3208] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3211] = {6'd3, 8'd137, 8'd140, 32'd0};//{'dest': 137, 'src': 140, 'op': 'move'}
instructions[3212] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3215] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd22, 8'd0, 8'd141, 32'd3235};//{'src': 141, 'label': 3235, 'op': 'jmp_if_true'}
instructions[3219] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3222] = {6'd22, 8'd0, 8'd141, 32'd3258};//{'src': 141, 'label': 3258, 'op': 'jmp_if_true'}
instructions[3223] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3226] = {6'd22, 8'd0, 8'd141, 32'd3336};//{'src': 141, 'label': 3336, 'op': 'jmp_if_true'}
instructions[3227] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3230] = {6'd22, 8'd0, 8'd141, 32'd3372};//{'src': 141, 'label': 3372, 'op': 'jmp_if_true'}
instructions[3231] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3234] = {6'd22, 8'd0, 8'd141, 32'd3460};//{'src': 141, 'label': 3460, 'op': 'jmp_if_true'}
instructions[3235] = {6'd3, 8'd140, 8'd94, 32'd0};//{'dest': 140, 'src': 94, 'op': 'move'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd13, 8'd0, 8'd140, 32'd3244};//{'src': 140, 'label': 3244, 'op': 'jmp_if_false'}
instructions[3239] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3242] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3243] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3244] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3247] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[3248] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3251] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3252] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3255] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3256] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3257] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3258] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd13, 8'd0, 8'd140, 32'd3335};//{'src': 140, 'label': 3335, 'op': 'jmp_if_false'}
instructions[3262] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3265] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3268] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014384, 'op': 'memory_read_request'}
instructions[3269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3270] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014384, 'op': 'memory_read_wait'}
instructions[3271] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810014384, 'element_size': 2, 'op': 'memory_read'}
instructions[3272] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3275] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3278] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3279] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3285] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014816, 'op': 'memory_read_request'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014816, 'op': 'memory_read_wait'}
instructions[3288] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810014816, 'element_size': 2, 'op': 'memory_read'}
instructions[3289] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3292] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3295] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3296] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3299] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3302] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133520, 'op': 'memory_read_request'}
instructions[3303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3304] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133520, 'op': 'memory_read_wait'}
instructions[3305] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887811133520, 'element_size': 2, 'op': 'memory_read'}
instructions[3306] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3309] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3313] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133952, 'op': 'memory_read_request'}
instructions[3320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3321] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133952, 'op': 'memory_read_wait'}
instructions[3322] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887811133952, 'element_size': 2, 'op': 'memory_read'}
instructions[3323] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3326] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3330] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3333] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3334] = {6'd15, 8'd0, 8'd0, 32'd3335};//{'label': 3335, 'op': 'goto'}
instructions[3335] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3336] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3339] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3340] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3343] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3344] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3347] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3348] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3349] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3352] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3353] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3356] = {6'd13, 8'd0, 8'd140, 32'd3362};//{'src': 140, 'label': 3362, 'op': 'jmp_if_false'}
instructions[3357] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3360] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3361] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3362] = {6'd3, 8'd140, 8'd132, 32'd0};//{'dest': 140, 'src': 132, 'op': 'move'}
instructions[3363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3365] = {6'd13, 8'd0, 8'd140, 32'd3371};//{'src': 140, 'label': 3371, 'op': 'jmp_if_false'}
instructions[3366] = {6'd0, 8'd140, 8'd0, 32'd3};//{'dest': 140, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3369] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3370] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3371] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3372] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3376] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3379] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3380] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3383] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3384] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3385] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3388] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3389] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3392] = {6'd13, 8'd0, 8'd140, 32'd3398};//{'src': 140, 'label': 3398, 'op': 'jmp_if_false'}
instructions[3393] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3396] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3397] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3398] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3399] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3401] = {6'd13, 8'd0, 8'd140, 32'd3425};//{'src': 140, 'label': 3425, 'op': 'jmp_if_false'}
instructions[3402] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3405] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3408] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044416, 'op': 'memory_read_request'}
instructions[3409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3410] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044416, 'op': 'memory_read_wait'}
instructions[3411] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810044416, 'element_size': 2, 'op': 'memory_read'}
instructions[3412] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3415] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3418] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044560, 'op': 'memory_read_request'}
instructions[3419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3420] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044560, 'op': 'memory_read_wait'}
instructions[3421] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810044560, 'element_size': 2, 'op': 'memory_read'}
instructions[3422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3424] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3427] = {6'd13, 8'd0, 8'd140, 32'd3451};//{'src': 140, 'label': 3451, 'op': 'jmp_if_false'}
instructions[3428] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3431] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044848, 'op': 'memory_read_request'}
instructions[3435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044848, 'op': 'memory_read_wait'}
instructions[3437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810044848, 'element_size': 2, 'op': 'memory_read'}
instructions[3438] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3441] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3444] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044992, 'op': 'memory_read_request'}
instructions[3445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3446] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044992, 'op': 'memory_read_wait'}
instructions[3447] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810044992, 'element_size': 2, 'op': 'memory_read'}
instructions[3448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3450] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3453] = {6'd13, 8'd0, 8'd140, 32'd3459};//{'src': 140, 'label': 3459, 'op': 'jmp_if_false'}
instructions[3454] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3457] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3458] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3459] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3460] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3463] = {6'd13, 8'd0, 8'd140, 32'd3469};//{'src': 140, 'label': 3469, 'op': 'jmp_if_false'}
instructions[3464] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3467] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3468] = {6'd15, 8'd0, 8'd0, 32'd3469};//{'label': 3469, 'op': 'goto'}
instructions[3469] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3470] = {6'd3, 8'd140, 8'd95, 32'd0};//{'dest': 140, 'src': 95, 'op': 'move'}
instructions[3471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3473] = {6'd13, 8'd0, 8'd140, 32'd3479};//{'src': 140, 'label': 3479, 'op': 'jmp_if_false'}
instructions[3474] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3477] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3478] = {6'd15, 8'd0, 8'd0, 32'd3479};//{'label': 3479, 'op': 'goto'}
instructions[3479] = {6'd3, 8'd140, 8'd138, 32'd0};//{'dest': 140, 'src': 138, 'op': 'move'}
instructions[3480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3482] = {6'd13, 8'd0, 8'd140, 32'd3515};//{'src': 140, 'label': 3515, 'op': 'jmp_if_false'}
instructions[3483] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3486] = {6'd3, 8'd116, 8'd151, 32'd0};//{'dest': 116, 'src': 151, 'op': 'move'}
instructions[3487] = {6'd3, 8'd141, 8'd105, 32'd0};//{'dest': 141, 'src': 105, 'op': 'move'}
instructions[3488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3490] = {6'd3, 8'd117, 8'd141, 32'd0};//{'dest': 117, 'src': 141, 'op': 'move'}
instructions[3491] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3494] = {6'd3, 8'd118, 8'd141, 32'd0};//{'dest': 118, 'src': 141, 'op': 'move'}
instructions[3495] = {6'd1, 8'd115, 8'd0, 32'd2514};//{'dest': 115, 'label': 2514, 'op': 'jmp_and_link'}
instructions[3496] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3497] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3499] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3500] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3503] = {6'd13, 8'd0, 8'd140, 32'd3514};//{'src': 140, 'label': 3514, 'op': 'jmp_if_false'}
instructions[3504] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3507] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3508] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3511] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3512] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3513] = {6'd15, 8'd0, 8'd0, 32'd3514};//{'label': 3514, 'op': 'goto'}
instructions[3514] = {6'd15, 8'd0, 8'd0, 32'd3515};//{'label': 3515, 'op': 'goto'}
instructions[3515] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3518] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3521] = {6'd13, 8'd0, 8'd140, 32'd3523};//{'src': 140, 'label': 3523, 'op': 'jmp_if_false'}
instructions[3522] = {6'd38, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'ready'}
instructions[3523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3525] = {6'd13, 8'd0, 8'd140, 32'd3528};//{'src': 140, 'label': 3528, 'op': 'jmp_if_false'}
instructions[3526] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3527] = {6'd15, 8'd0, 8'd0, 32'd3528};//{'label': 3528, 'op': 'goto'}
instructions[3528] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3529] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3532] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3535] = {6'd13, 8'd0, 8'd140, 32'd3542};//{'src': 140, 'label': 3542, 'op': 'jmp_if_false'}
instructions[3536] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3539] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[3540] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3541] = {6'd15, 8'd0, 8'd0, 32'd3542};//{'label': 3542, 'op': 'goto'}
instructions[3542] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3543] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3546] = {6'd41, 8'd0, 8'd140, 32'd0};//{'src': 140, 'op': 'wait_clocks'}
instructions[3547] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3548] = {6'd35, 8'd134, 8'd134, 32'd1};//{'src': 134, 'right': 1, 'dest': 134, 'signed': False, 'op': '-', 'size': 2}
instructions[3549] = {6'd15, 8'd0, 8'd0, 32'd3159};//{'label': 3159, 'op': 'goto'}
instructions[3550] = {6'd15, 8'd0, 8'd0, 32'd2654};//{'label': 2654, 'op': 'goto'}
instructions[3551] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /home/amer/Nexys3/TCP3/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
$display ("%d (report at line: 542 in file: /home/amer/Nexys3/TCP3/source/server.h)", $signed(register_1));
end
16'd41:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
(* begin hide *)
Require Export HoTT Ch02.
(* end hide *)
(** printing <~> %\ensuremath{\eqvsym}% **)
(** printing == %\ensuremath{\sim}% **)
(** printing ^-1 %\ensuremath{^{-1}}% **)
(** * Sets and logic *)
Notation Brck Q := (merely Q).
(** %\exerdone{3.1}{127}%
Prove that if $A \eqvsym B$ and $A$ is a set, then so is $B$.
*)
(** %\soln%
Suppose that $A \eqvsym B$ and that $A$ is a set. Since $A$ is a set, $x =_{A}
y$ is a mere proposition. And since $A \eqvsym B$, this means that $x =_{B} y$
is a mere proposition, hence that $B$ is a set.
Alternatively, we can unravel some definitions. By assumption we have $f : A
\eqvsym B$ and
%\[
g : \isset(A) \equiv \prd{x, y:A}\prd{p,q : x=y} (p = q)
\]%
Now suppose that $x, y : B$ and $p, q : x = y$. Then $f^{-1}(x),
f^{-1}(y) : A$ and $f^{-1}(p), f^{-1}(q) : f^{-1}(x) =
f^{-1}(y)$, so
%\[
f\!\left(g(f^{-1}(x), f^{-1}(y), f^{-1}(p), f^{-1}(q))\right)
:
f(f^{-1}(p)) = f(f^{-1}(q))
\]%
Since $f^{-1}$ is a quasi-inverse of $f$, we have the homotopy $\alpha :
\prd{a:A} (f(f^{-1}(a)) = a)$, thus
%\[
\alpha_{x}^{-1} \ct
f\!\left(g(f^{-1}(x), f^{-1}(y), f^{-1}(p), f^{-1}(q))\right)
\ct \alpha_{y}
:
p = q
\]%
So we've constructed an element of
%\[
\isset(B) : \prd{x, y : B} \prd{p, q : x = y} (p = q)
\]%
*)
Theorem ex3_1 (A B : Type) `{Univalence} : A <~> B -> IsHSet A -> IsHSet B.
Proof.
intros f g.
apply equiv_path_universe in f.
rewrite <- f.
apply g.
Defined.
Theorem ex3_1' (A B : Type) : A <~> B -> IsHSet A -> IsHSet B.
Proof.
intros f g x y.
apply hprop_allpath. intros p q.
assert (ap f^-1 p = ap f^-1 q). apply g.
apply ((ap (ap f^-1))^-1 X).
Defined.
(** %\exerdone{3.2}{127}%
Prove that if $A$ and $B$ are sets, then so is $A + B$.
*)
(** %\soln%
Suppose that $A$ and $B$ are sets. Then for all $a, a' : A$ and $b, b': B$, $a
= a'$ and $b = b'$ are contractible. Given the characterization of the path
space of $A+B$ in \S2.12, it must also be contractible. Hence $A + B$ is a
set.
More explicitly, suppose that $z, z' : A + B$ and $p, q : z = z'$. By
induction, there are four cases.
- $z \equiv \inl(a)$ and $z' \equiv \inl(a')$. Then $(z = z') \eqvsym (a = a')$, and since $A$ is a set, $a = a'$ is contractible, so $(z = z')$ is as well.
- $z \equiv \inl(a)$ and $z' \equiv \inr(b)$. Then $(z = z') \eqvsym \emptyt$, so $p$ is a contradiction.
- $z \equiv \inr(b)$ and $z' \equiv \inl(a)$. Then $(z = z') \eqvsym \emptyt$, so $p$ is a contradiction.
- $z \equiv \inr(b)$ and $z' \equiv \inr(b')$. Then $(z = z') \eqvsym (b = b')$, and since $B$ is a set, this type is contractible.
So $z = z'$ is contractible, making $A + B$ a set.
*)
Theorem ex3_2 (A B : Type) : IsHSet A -> IsHSet B -> IsHSet (A + B).
Proof.
intros f g.
intros z z'. apply hprop_allpath. intros p q.
assert ((path_sum z z')^-1 p = (path_sum z z')^-1 q).
pose proof ((path_sum z z')^-1 p).
destruct z as [a | b], z' as [a' | b'].
apply f. contradiction. contradiction. apply g.
apply ((ap (path_sum z z')^-1)^-1 X).
Defined.
(** %\exerdone{3.3}{127}%
Prove that if $A$ is a set and $B : A \to \UU$ is a type family such that
$B(x)$ is a set for all $x:A$, then $\sm{x:A}B(x)$ is a set.
*)
(** %\soln%
At this point the pattern in these proofs is relatively obvious: show
that the path space of the combined types is determined by the path
spaces of the base types, and then apply the fact that the base types
are sets. So here we suppose that $w w' : \sm{x:A} B(x)$, and that $p
q : (w = w')$. Now
%\[
(w = w') \eqvsym \sm{p : \fst(w) = \fst(w')} p_{*}(\snd(w)) = \snd(w')
\]%
by Theorem 2.7.2. Since $A$ is a set, $\fst(w) = \fst(w')$ is
contractible, so $(w = w') \eqvsym ((\refl{\fst(w)})_{*}(\snd(w)) =
\snd(w')) \equiv (\snd(w) = \snd(w'))$ by Lemma 3.11.9. And since $B$
is a set, this too is contractible, making $w = w'$ contractible and
$\sm{x:A} B(x)$ a set.
*)
Theorem ex3_3 (A : Type) (B : A -> Type) :
IsHSet A -> (forall x:A, IsHSet (B x)) -> IsHSet {x : A & B x}.
Proof.
intros f g.
intros w w'. apply hprop_allpath. intros p q.
assert ((path_sigma_uncurried B w w')^-1 p = (path_sigma_uncurried B w w')^-1 q).
apply path_sigma_uncurried. simpl.
assert (p..1 = q..1). apply f. exists X. apply (g w'.1).
apply ((ap (path_sigma_uncurried B w w')^-1)^-1 X).
Defined.
(** %\exerdone{3.4}{127}%
Show that $A$ is a mere proposition if and only if $A \to A$ is contractible.
*)
(** %\soln%
For the forward direction, suppose that $A$ is a mere proposition. Then by
Example 3.6.2, $A \to A$ is a mere proposition. We also have $\idfunc{A} : A
\to A$ when $A$ is inhabited and $! : A \to A$ when it's not, so $A \to A$ is
contractible.
For the other direction, suppose that $A \to A$ is contractible and that $x y :
A$. We have the functions $z \mapsto x$ and $z \mapsto y$, and since $A \to A$
is contractible these functions are equal. $\happly$ then gives $x = y$, so
$A$ is a mere proposition.
*)
Theorem ex3_4 `{Funext} (A : Type) : IsHProp A <-> Contr (A -> A).
Proof.
split; intro H'.
(* forward *)
exists idmap; intro f.
apply path_forall; intro x. apply H'.
(* backward *)
apply hprop_allpath; intros x y.
assert ((fun z:A => x) = (fun z:A => y)).
destruct H'. transitivity center.
apply (contr (fun _ => x))^. apply (contr (fun _ : A => y)).
apply (apD10 X x).
Defined.
(** %\exerdone{3.5}{127}%
Show that $\isprop(A) \eqvsym (A \to \iscontr(A))$.
*)
(** %\soln%
Lemma 3.3.3 gives us maps $\isprop(A) \to (A \to \iscontr(A))$ and $(A
\to \iscontr(A)) \to \isprop(A)$. Note that $\iscontr(A)$ is a mere
proposition, so $A \to \iscontr(A)$ is as well. $\isprop(A)$ is
always a mere proposition, so by Lemma 3.3.3 we have the equivalence.
*)
Module Ex5.
Theorem equiv_hprop_inhabited_contr `{Funext} (A : Type)
: IsHProp A <~> (A -> Contr A).
Proof.
apply equiv_iff_hprop.
apply contr_inhabited_hprop.
apply hprop_inhabited_contr.
Defined.
End Ex5.
(** %\exerdone{3.6}{127}%
Show that if $A$ is a mere proposition, then so is $A + (\lnot A)$.
*)
(** %\soln%
Suppose that $A$ is a mere proposition, and that $x, y : A + (\lnot A)$. By a
case analysis, we have
- $x = \inl(a)$ and $y = \inl(a')$. Then $(x = y) \eqvsym (a = a')$, and $A$ is a mere proposition, so this holds.
- $x = \inl(a)$ and $y = \inr(f)$. Then $f(a) : \emptyt$, a contradiction.
- $x = \inr(f)$ and $y = \inl(a)$. Then $f(a) : \emptyt$, a contradiction.
- $x = \inr(f)$ and $y = \inr(f')$. Then $(x = y) \eqvsym (f = f')$, and $\lnot A$ is a mere proposition, so this holds.
*)
Theorem ex3_6 `{Funext} {A} : IsHProp A -> IsHProp (A + ~A).
Proof.
intro H'.
assert (IsHProp (~A)) as H''.
apply hprop_allpath. intros f f'. apply path_forall; intro x. contradiction.
apply hprop_allpath. intros x y.
destruct x as [a | f], y as [a' | f'].
apply (ap inl). apply H'.
contradiction.
contradiction.
apply (ap inr). apply H''.
Defined.
(** %\exerdone{3.7}{127}%
More generally, show that if $A$ and $B$ are mere propositions and $\lnot (A
\times B)$, then $A + B$ is also a mere proposition.
*)
(** %\soln%
Suppose that $A$ and $B$ are mere propositions with $f : \lnot (A \times B)$,
and let $x, y : A + B$. Then we have cases:
- $x = \inl(a)$ and $y = \inl(a')$. Then $(x = y) \eqvsym (a = a')$, and $A$ is a mere proposition, so this holds.
- $x = \inl(a)$ and $y = \inr(b)$. Then $f(a, b) : \emptyt$, a contradiction.
- $x = \inr(b)$ and $y = \inl(a)$. Then $f(a, b) : \emptyt$, a contradiction.
- $x = \inr(b)$ and $y = \inr(b')$. Then $(x = y) \eqvsym (b = b')$, and $B$ is a mere proposition, so this holds.
*)
Theorem ex3_7 {A B} : IsHProp A -> IsHProp B -> ~(A * B) -> IsHProp (A+B).
Proof.
intros HA HB f.
apply hprop_allpath; intros x y.
destruct x as [a | b], y as [a' | b'].
apply (ap inl). apply HA.
assert Empty. apply (f (a, b')). contradiction.
assert Empty. apply (f (a', b)). contradiction.
apply (ap inr). apply HB.
Defined.
(** %\exerdone{3.8}{127}%
Assuming that some type $\isequiv(f)$ satisfies
%\begin{itemize}
\item[(i)] For each $f : A \to B$, there is a function $\qinv(f) \to \isequiv(f)$;
\item[(ii)] For each $f$ we have $\isequiv(f) \to \qinv(f)$;
\item[(iii)] For any two $e_{1}, e_{2} : \isequiv(f)$ we have $e_{1} = e_{2}$,
\end{itemize}%
show that the type $\brck{\qinv(f)}$ satisfies the same conditions and is
equivalent to $\isequiv(f)$.
*)
(** %\soln%
Suppose that $f : A \to B$. There is a function $\qinv(f) \to \brck{\qinv(f)}$
by definition. Since $\isequiv(f)$ is a mere proposition (by iii), the
recursion principle for $\brck{\qinv(f)}$ gives a map $\brck{\qinv(f)} \to
\isequiv(f)$, which we compose with the map from (ii) to give a map
$\brck{\qinv(f)} \to \qinv(f)$. Finally, $\brck{\qinv(f)}$ is a mere
proposition by construction. Since $\brck{\qinv(f)}$ and $\isequiv(f)$ are
both mere propositions and logically equivalent, $\brck{\qinv(f)} \eqvsym
\isequiv(f)$ by Lemma 3.3.3.
*)
Section Exercise3_8.
Variables (E Q : Type).
Hypothesis H1 : Q -> E.
Hypothesis H2 : E -> Q.
Hypothesis H3 : forall e e' : E, e = e'.
Definition ex3_8_i : Q -> (Brck Q) := tr.
Definition ex3_8_ii : (Brck Q) -> Q.
intro q. apply H2. apply (@Trunc_ind -1 Q).
intro q'. apply hprop_allpath. apply H3.
apply H1. apply q.
Defined.
Theorem ex3_8_iii : forall q q' : Brck Q, q = q'.
apply path_ishprop.
Defined.
Theorem ex3_8_iv : (Brck Q) <~> E.
apply @equiv_iff_hprop.
apply hprop_allpath. apply ex3_8_iii.
apply hprop_allpath. apply H3.
apply (H1 o ex3_8_ii).
apply (ex3_8_i o H2).
Defined.
End Exercise3_8.
(** %\exerdone{3.9}{127}%
Show that if $\LEM{}$ holds, then the type $\prop \defeq \sm{A:\UU}\isprop(A)$
is equivalent to $\bool$.
*)
(** %\soln%
Suppose that
%\[
f : \prd{A:\UU}\left(\isprop(A) \to (A + \lnot A)\right)
\]%
To construct a map $\prop \to \bool$, it suffices to consider an element of the
form $(A, g)$, where $g : \isprop(A)$. Then $f(g) : A + \lnot A$, so we have
two cases:
- $f(g) \equiv \inl(a)$, in which case we send it to $1_{\bool}$, or
- $f(g) \equiv \inr(a)$, in which case we send it to $0_{\bool}$.
To go the other way, note that $\LEM{}$ splits $\prop$ into two equivalence
classes (basically, the true and false propositions), and $\unit$ and $\emptyt$
are in different classes. Univalence quotients out these classes, leaving us
with two elements. We'll use $\unit$ and $\emptyt$ as representatives, so we
send $0_{\bool}$ to $\emptyt$ and $1_{\bool}$ to $\unit$.
Coq has some trouble with the universes here, so we have to specify that we want [(Unit : Type)] and [(Empty : Type)]; otherwise we get the [Type0] versions.
*)
Section Exercise3_9.
Hypothesis LEM : forall (A : Type), IsHProp A -> (A + ~A).
Definition ex3_9_f (P : {A:Type & IsHProp A}) : Bool :=
match (LEM P.1 P.2) with
| inl a => true
| inr a' => false
end.
Lemma hprop_Unit : IsHProp (Unit : Type).
apply hprop_inhabited_contr. intro u. apply contr_unit.
Defined.
Definition ex3_9_inv (b : Bool) : {A : Type & IsHProp A} :=
match b with
| true => @existT Type IsHProp (Unit : Type) hprop_Unit
| false => @existT Type IsHProp (Empty : Type) hprop_Empty
end.
Theorem ex3_9 `{Univalence} : {A : Type & IsHProp A} <~> Bool.
Proof.
refine (equiv_adjointify ex3_9_f ex3_9_inv _ _).
intro b. unfold ex3_9_f, ex3_9_inv.
destruct b.
simpl. destruct (LEM (Unit:Type) hprop_Unit).
reflexivity.
contradiction n. exact tt.
simpl. destruct (LEM (Empty:Type) hprop_Empty).
contradiction. reflexivity.
intro w. destruct w as [A p]. unfold ex3_9_f, ex3_9_inv.
simpl. destruct (LEM A p) as [x | x].
apply path_sigma_uncurried. simpl.
assert ((Unit:Type) = A).
assert (Contr A). apply contr_inhabited_hprop. apply p. apply x.
apply equiv_path_universe. apply equiv_inverse. apply equiv_contr_unit.
exists X. induction X. simpl.
assert (IsHProp (IsHProp (Unit:Type))).
typeclasses eauto. apply X.
apply path_sigma_uncurried. simpl.
assert ((Empty:Type) = A).
apply equiv_path_universe. apply equiv_iff_hprop.
intro z. contradiction.
intro a. contradiction.
exists X. induction X. simpl.
assert (IsHProp (IsHProp (Empty:Type))).
typeclasses eauto. apply X.
Defined.
End Exercise3_9.
(** %\exerdone{3.10}{127}%
Show that if $\UU_{i+1}$ satisfies $\LEM{}$, then the canonical inclusion
$\prop_{\UU_{i}} \to \prop_{\UU_{i+1}}$ is an equivalence.
*)
(** %\soln%
If $\LEM{i+1}$ holds, then $\LEM{i}$ holds as well. For suppose that
$A : \UU_{i}$ and $p : \isprop(A)$. Then we also have $A :
\UU_{i+1}$, so $\LEM{i+1}(A, p) : A + \lnot A$, establishing
$\LEM{i}$. By the previous exercise, then, $\prop_{\UU_{i}} \eqvsym
\bool \eqvsym \prop_{\UU_{i+1}}$.
Since Coq doesn't let the user access the [Type]${}_{i}$ hierarchy,
there's not much to do here. This is really more of a ``proof by
contemplation'' anyway.
*)
(** %\exerdone{3.11}{127}%
Show that it is not the case that for all $A : \UU$ we have $\brck{A} \to A$.
*)
(** %\soln%
We can essentially just copy Theorem 3.2.2. Suppose given a function $f :
\prd{A:\UU} \brck{A} \to A$, and recall the equivalence $e : \bool \eqvsym
\bool$ from Exercise 2.13 given by $e(1_{\bool}) \defeq 0_{\bool}$ and
$e(0_{\bool}) = 1_{\bool}$. Then $\ua(e) : \bool = \bool$, $f(\bool)
: \brck{\bool} \to \bool$, and
%\[
\mapdepfunc{f}(\ua(e)) :
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)} = f(\bool)
\]%
So for $u : \brck{\bool}$,
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)}(u) = f(\bool)(u)
\]%
and by 2.9.4, we have
%\[
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)}(u)
=
\transfib{A \mapsto A}{\ua(e)}{f(\bool)(\transfib{\lvert \blank
\rvert}{\ua(e)^{-1}}{u}})
\]%
But, any two $u, v : \brck{A}$ are equal, since $\brck{A}$ is contractible. So
$\transfib{\lvert\blank\rvert}{\ua(e)^{-1}}{u} = u$, and so
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
\transfib{A \mapsto A}{\ua(e)}{f(\bool)(u)}
= f(\bool)(u)
\]%
and the propositional computation rule for $\ua$ gives
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
e(f(\bool)(u)) = f(\bool)(u)
\]%
But $e$ has no fixed points, so we have a contradiction.
*)
Lemma negb_no_fixpoint : forall b, ~ (negb b = b).
Proof.
intros b H. destruct b; simpl in H.
apply (false_ne_true H).
apply (true_ne_false H).
Defined.
Theorem ex3_11 `{Univalence} : ~ (forall A, Brck A -> A).
Proof.
intro f.
assert (forall b, negb (f Bool b) = f Bool b). intro b.
assert (transport (fun A => Brck A -> A) (path_universe negb) (f Bool) b
=
f Bool b).
apply (apD10 (apD f (path_universe negb)) b).
assert (transport (fun A => Brck A -> A) (path_universe negb) (f Bool) b
=
transport idmap (path_universe negb)
(f Bool (transport (fun A => Brck A)
(path_universe negb)^
b))).
refine (transport_arrow _ _ _).
rewrite X in X0.
assert (b = (transport (fun A : Type => Brck A) (path_universe negb) ^ b)).
apply path_ishprop. rewrite <- X1 in X0. symmetry in X0.
assert (transport idmap (path_universe negb) (f Bool b) = negb (f Bool b)).
apply transport_path_universe. rewrite X2 in X0. apply X0.
apply (@negb_no_fixpoint (f Bool (tr true))).
apply (X (tr true)).
Defined.
(** %\exerdone{3.12}{127}%
Show that if $\LEM{}$ holds, then for all $A : \UU$ we have $\bbrck{\brck{A}
\to A}$.
*)
(** %\soln%
Suppose that $\LEM{}$ holds, and that $A : \UU$. By $\LEM{}$, either $\brck{A}$
or $\lnot\brck{A}$. If the
former, then we can use the recursion principle for $\brck{A}$ to construct a
map to $\bbrck{\brck{A} \to A}$, then apply it to the element of $\brck{A}$.
So we need a map $A \to \bbrck{\brck{A} \to A}$, which is not hard to get:
%\[
\lam{a:A}\left\lvert\lam{a':\brck{A}}a\right\rvert : A \to \bbrck{\brck{A} \to A}
\]%
If the latter, then we have the canonical map out of the empty type $\brck{A}
\to A$, hence we have $\bbrck{\brck{A} \to A}$.
*)
Section Exercise3_12.
Hypothesis LEM : forall A, IsHProp A -> (A + ~A).
Theorem ex3_12 : forall A, Brck (Brck A -> A).
Proof.
intro A.
destruct (LEM (Brck A) _).
strip_truncations. apply tr. intro a. apply t.
apply tr. intro a. contradiction (n a).
Defined.
End Exercise3_12.
(** %\exerdone{3.13}{127}%
Show that the axiom
%\[
\LEM{}': \prd{A:\UU} (A + \lnot A)
\]%
implies that for $X : \UU$, $A : X \to \UU$, and $P : \prd{x:X} A(x) \to \UU$,
if $X$ is a set, $A(x)$ is a set for all $x:X$, and $P(x, a)$ is a mere
proposition for all $x:X$ and $a:A(x)$,
%\[
\left(\prd{x:X}\left\lVert\sm{a:A(x)}P(x, a)\right\rVert\right)
\to
\left\lVert \sm{g:\prd{x:X}A(x)}\prd{x:X}P(x, g(x))\right\rVert.
\]%
*)
(** %\soln%
By Lemma 3.8.2, it suffices to show that for any set $X$ and any $Y : X \to
\UU$ such that $Y(x)$ is a set, we have
%\[
\left(\prd{x:X}\brck{Y(x)}\right) \to \left\lVert\prd{x:X}Y(x)\right\rVert
\]%
Suppose that $f : \prd{x:X}\brck{Y(x)}$. By $\LEM{}'$, either $Y(x)$ is
inhabited or it's not. If it is, then $\LEM{}'(Y(x)) \equiv y : Y(x)$, and we
have
%\[
\left\lvert\lam{x:X}y\right\rvert : \left\lVert \prd{x:X} Y(x) \right\rVert
\]%
Suppose instead that $\lnot Y(x)$ and that $x:X$. Then $f(x) : \brck{Y(x)}$.
Since we're trying to derive a mere proposition, we can ignore this truncation
and suppose that $f(x) : Y(x)$, in which case we have a contradiction, and
we're done.
The reason we can ignore the truncation (and apply [strip_truncations] in Coq)
in hypotheses is given by the reasoning in the previous Exercise. If the
conclusion is a mere proposition, then the recursion principle for
$\brck{Y(x)}$ allows us to construct an arrow out of $\brck{Y(x)}$ if we have
one from $Y(x)$.
*)
Definition AC := forall X A P,
IsHSet X -> (forall x, IsHSet (A x)) -> (forall x a, IsHProp (P x a))
-> ((forall x:X, Brck {a:A x & P x a})
-> Brck {g : forall x, A x & forall x, P x (g x)}).
Definition AC_prod := forall (X : hSet) (Y : X -> Type),
(forall x, IsHSet (Y x)) ->
((forall x, Brck (Y x)) -> Brck (forall x, Y x)).
Lemma hprop_is_hset (A : Type) : IsHProp A -> IsHSet A.
Proof.
typeclasses eauto.
Defined.
Lemma AC_equiv_AC_prod `{Funext} : AC <~> AC_prod.
Proof.
apply equiv_iff_hprop; unfold AC, AC_prod.
(* forward *)
intros AC HX Y HY f.
transparent assert (He : (
Brck ({g : forall x, Y x & forall x, (fun x a => Unit) x (g x)})
<~>
Brck (forall x, Y x)
)).
apply equiv_iff_hprop.
intro w. strip_truncations. apply tr. apply w.1.
intro g. strip_truncations. apply tr. exists g. intro x. apply tt.
apply He. clear He. apply (AC _ Y (fun x a => Unit)). apply HX. apply HY.
intros. apply hprop_Unit. intros.
assert (y : Brck (Y x)) by apply f. strip_truncations.
apply tr. exists y. apply tt.
(* back *)
intros AC_prod X A P HX HA HP f.
transparent assert (He: (
Brck (forall x, {a : A x & P x a})
<~>
Brck {g : forall x, A x & forall x, P x (g x)}
)).
apply equiv_iff_hprop.
intros. strip_truncations. apply tr. exists (fun x => (X0 x).1).
intro x. apply (X0 x).2.
intros. strip_truncations. apply tr. intro x. apply (X0.1 x; X0.2 x).
apply He. clear He.
apply (AC_prod (BuildhSet X) (fun x => {a : A x & P x a})).
intros. apply ex3_3. apply (HA x). intro a.
apply hprop_is_hset. apply (HP x a).
intro x. apply (f x).
Defined.
Section Exercise3_13.
Hypothesis LEM' : forall A, A + ~A.
Theorem ex3_13 `{Funext} : AC.
Proof.
apply AC_equiv_AC_prod. intros X Y HX HY.
apply tr. intros.
destruct (LEM' (Y x)). apply y.
assert (Brck (Y x)) as y'. apply HY.
assert (~ Brck (Y x)) as nn. intro p. strip_truncations. contradiction.
contradiction nn.
Defined.
End Exercise3_13.
(** %\exerdone{3.14}{127}%
Show that assuming $\LEM{}$, the double negation $\lnot\lnot A$ has the same
universal property as the propositional truncation $\brck{A}$, and is therefore
equivalent to it.
*)
(** %\soln%
Suppose that $a : \lnot\lnot A$ and that we have some function $g : A \to B$,
where $B$ is a mere proposition, so $p : \isprop(B)$. We can construct a
function $\lnot \lnot A \to \lnot \lnot B$ by using contraposition twice,
producing $g'': \lnot \lnot A \to \lnot \lnot B$
%\[
g''(h) \defeq
\lam{f : \lnot B}h(\lam{a:A}f(g(a)))
\]%
$\LEM{}$ then allows us to use double negation elimination to produce a map
$\lnot \lnot B \to B$. Suppose that $f : \lnot \lnot B$. Then we have
$\LEM{}(B, p) : B + \lnot B$, and in the left case we can produce the witness,
and in the right case we use $f$ to derive a contradiction. Explicitly, we
have $\ell : \lnot \lnot B \to B$ given by
%\[
\ell(f) \defeq
\rec{B + \lnot\lnot B}(B, \idfunc{B}, f, \LEM{}(B, p))
\]%
The computation rule does not hold judgementally for $g'' \circ \ell$. I don't
see that it can, given the use of $\LEM{}$. Clearly it does hold
propositionally, if one takes $\lvert a \rvert' \defeq \lam{f}f(a)$ to be the
analogue of the constructor for $\brck{A}$; for any $a : A$, we have $g(a) :
B$, and the fact that $B$ is a mere proposition ensures that $(g'' \circ
\ell)(\lvert a \rvert') = g(a)$.
*)
Section Exercise3_14.
Hypothesis LEM : forall A, IsHProp A -> (A + ~A).
Definition Brck' (A : Type) := ~ ~ A.
Definition min1' {A : Type} (a : A) : Brck' A := fun f => f a.
Definition contrapositive {A B : Type} : (A -> B) -> (~ B -> ~ A).
intros. intro a. apply X0. apply X. apply a.
Defined.
Definition DNE {B : Type} `{IsHProp B} : ~ ~ B -> B.
intros. destruct (LEM B IsHProp0). apply b. contradiction X.
Defined.
Definition trunc_rect' {A B : Type} (g : A -> B) : IsHProp B -> Brck' A -> B.
intros HB a. apply DNE. apply (contrapositive (contrapositive g)). apply a.
Defined.
End Exercise3_14.
(** %\exerdone{3.15}{128}%
Show that if we assume propositional resizing, then the type
%\[
\prd{P:\prop}\left((A \to P) \to P\right)
\]%
has the same universal property as $\brck{A}$.
*)
(** %\soln%
Let $A:\UU_{i}$, so that for $\brck{A}'' \defeq \prd{P:\prop_{\UU_{i}}} ((A \to
P) \to P)$ we have $\brck{A}'' : \UU_{i+1}$. By propositional resizing,
however, we have a corresponding $\brck{A}'' : \UU_{i}$. To construct an arrow
$\brck{A}'' \to B$, suppose that $f : \brck{A}''$ and $g : A \to B$. Then
$f(B, g) : B$. So $\lam{f}\tilde{f}(B, g) : \brck{A}'' \to B$, where
$\tilde{f}$ is the image of $f$ under the inverse of the canonical inclusion
$\prop_{\UU_{i}} \to \prop_{\UU_{i+1}}$.
To show that the computation rule holds, let
%\[
\lvert a \rvert'' \defeq \lam{P}{f}f(a) : \prd{P:\prop}\left((A \to P) \to P
\right)
\]%
We need to show that $(\lam{f}\tilde{f}(B, g))(\lvert a \rvert'') \equiv g(a)$.
Assuming that propositional resizing gives a judgemental equality, we have
%\begin{align*}
(\lam{f}\tilde{f}(B, g))(\lvert a \rvert '')
&\equiv
(\lam{f}\tilde{f}(B, g))(\lam{P}{f}f(a))
\\&\equiv
(\lam{P}{f}f(a))(B, g)
\\&\equiv
g(a)
\end{align*}%
*)
Definition Brck'' (A : Type) := forall (P : hProp), ((A -> P) -> P).
Definition min1'' {A : Type} (a : A) := fun (P : hProp) (f : A -> P) => f a.
Definition trunc_rect'' {A B : Type} (g : A -> B) : IsHProp B -> Brck'' A -> B.
intros p f.
apply (f (BuildhProp B)). apply g.
Defined.
(** %\exerdone{3.16}{128}%
Assuming $\LEM{}$, show that double negation commutes with universal
quantification of mere propositions over sets. That is, show that if $X$ is a
set and each $Y(x)$ is a mere proposition, then $\LEM{}$ implies
%\[
\left(\prd{x:X}\lnot\lnot Y(x)\right)
\eqvsym
\left(\lnot\lnot\prd{x:X} Y(x)\right).
\]%
*)
(** %\soln%
Each side is a mere proposition, since one side is a dependent function into a
mere proposition and the other is a negation. So we just need to show that
each implies the other. From left to right we use the fact that $\LEM{}$
is equivalent to double negation to obtain $\prd{x:X}Y(x)$, and double negation
introduction is always allowed, giving the right side. For the other direction
we do the same.
*)
Section Exercise3_16.
Hypothesis LEM : forall A, IsHProp A -> (A + ~ A).
Theorem ex3_16 `{Funext} (X : hSet) (Y : X -> Type) :
(forall x, IsHProp (Y x)) ->
(forall x, ~ ~ Y x) <~> ~ ~ (forall x, Y x).
Proof.
intro HY. apply equiv_iff_hprop; intro H'.
intro f. apply f. intro x.
destruct (LEM (Y x)).
apply HY. apply y.
contradiction (H' x).
intro x.
destruct (LEM (Y x)).
apply HY. intro f. contradiction.
assert (~ (forall x, Y x)). intro f. contradiction (f x).
contradiction H'.
Qed.
End Exercise3_16.
(** %\exerdone{3.17}{128}%
Show that the rules for the propositional truncation given in %\S3.7% are
sufficient to imply the following induction principle: for any type family $B :
\brck{A} \to \UU$ such that each $B(x)$ is a mere proposition, if for every
$a:A$ we have $B(\lvert a \rvert)$, then for every $x : \brck{A}$ we have
$B(x)$.
*)
(** %\soln%
Suppose that $B : \brck{A} \to \UU$, $B(x)$ is a mere proposition for all $x :
\brck{A}$ and that $f : \prd{a:A} B(\lvert a \rvert)$. Suppose that $x
: \brck{A}$; we need to construct an element of $B(x)$. By the
induction principle for $\brck{A}$, it suffices to exhibit a map $A
\to B(x)$. So suppose that $a:A$, and we'll construct an element of
$B(x)$. Since $\brck{A}$ is contractible, we have $p : \lvert a
\rvert = x$, and $p_{*}(f(a)) : B(x)$.
*)
Theorem ex3_17 (A : Type) (B : Brck A -> Type) :
(forall x, IsHProp (B x)) -> (forall a, B (tr a)) -> (forall x, B x).
Proof.
intros HB f. intro x.
apply Trunc_ind. apply HB.
intro a. apply (f a).
Defined.
(** %\exerdone{3.18}{128}%
Show that the law of excluded middle
%\[
\LEM{} : \prd{A:\UU} \left( \isprop(A) \to (A + \lnot A)\right)
\]%
and the law of double negation
%\[
\DN : \prd{A:\UU} \left( \isprop(A) \to (\lnot\lnot A \to A)\right)
\]%
are logically equivalent.
*)
(** %\soln%
For the forward direction, suppose that $\LEM{}$ holds, that $A : \UU$,
that $H : \isprop(A)$, and that $f : \lnot\lnot A$. We then need to produce an
element of $A$. We have $z \defeq \LEM{}(A, H) : A + \lnot A$, so we can
consider cases:
- $z \equiv \inl(a)$, in which case we can produce $a$.
- $z \equiv \inr(x)$, in which case we have $f(x) : \emptyt$, a contradiction.
giving the forward direction.
Suppose instead that $\DN$ holds, and we have $A : \UU$ and $H : \isprop(A)$.
We need to provide an element of $A + \lnot A$. By Exercise 3.6, $A + \lnot A$
is a mere proposition, so by $\DN$, if we can give an element of $\lnot\lnot(A
+ \lnot A)$, then we'll get one of $A + \lnot A$. In Exercise 1.13 we
constructed such an element, so producing that gives one of $A + \lnot A$, and
we're done.
*)
Theorem ex3_18 `{Funext} :
(forall A, IsHProp A -> (A + ~A)) <-> (forall A, IsHProp A -> (~ ~A -> A)).
Proof.
split.
intros LEM A H' f. destruct (LEM A H'). apply a. contradiction.
intros DN A H'. apply (DN (A + ~A) (ex3_6 H')).
exact (fun g : ~ (A + ~ A) => g (inr (fun a:A => g (inl a)))).
Qed.
(** %\exerdone{3.19}{128}%
Suppose $P : \mathbb{N} \to \UU$ is a decidable family of mere propositions.
Prove that
%\[
\left\lVert \sm{n:\mathbb{N}} P(n) \right\rVert
\to
\sm{n:\mathbb{N}} P(n).
\]%
*)
(** %\soln%
Since $P : \mathbb{N} \to \UU$ is decidable, we have $f : \prd{n:\mathbb{N}}
(P(n) + \lnot P(n))$. So if $\bbrck{\sm{n:\mathbb{N}}
P(n)}$ is inhabited, then there is some smallest $n$ such that $P(n)$.
It would be nice if we could define a function to return the
smallest $n$ such that $P(n)$. But unbounded minimization isn't a
total function, so that won't obviously work. Following the
discussion of Corollary 3.9.2, what we can do instead is to define some
%\[
Q : \left(\sm{n:\mathbb{N}} P(n)\right) \to \UU
\]%
such that $\sm{w:\sm{n:\mathbb{N}} P(n)} Q(w)$ is a mere proposition. Then
we can project out an element of $\sm{n:\mathbb{N}} P(n)$.
$Q(w)$ will be the proposition that $w$ is the smallest member of
$\sm{n\mathbb{N}}P(n)$. Explicitly,
%\[
Q(w) \defeq
\prd{w' : \sm{n:\mathbb{N}}P(n)} \fst(w) \leq \fst(w')
\]%
Then we have
%\[
\sm{w : \sm{n : \mathbb{N}} P(n)} Q(w)
\equiv
\sm{w : \sm{n : \mathbb{N}} P(n)}
\prd{w' : \sm{n:\mathbb{N}}P(n)} \fst(w) \leq \fst(w')
\]%
which we must show to be a mere proposition. Suppose that $w$ and $w'$ are two
elements of this type. By $\snd(w)$ and $\snd(w')$, we have $\fst(\fst(w)) \leq
\fst(\fst(w'))$ and $\fst(\fst(w')) \leq \fst(\fst(w))$, so $\fst(\fst(w)) = \fst(\fst(w'))$. Since
$\mathbb{N}$ has decidable equality, $\fst(w) \leq \snd(w')$ is a mere
proposition for all $w$ and $w'$, meaning that $Q(w)$ is a mere proposition.
So $w = w'$, meaning that our type is contractible.
Now we can use the universal property of $\bbrck{\sm{n:\mathbb{N}}P(n)}$ to
construct an arrow into $\sm{w : \sm{n:\mathbb{N}} P(n)} Q(w)$ by way of a
function $\big(\sm{n:\mathbb{N}} P(n)\big) \to \sm{w : \sm{n:\mathbb{N}} P(n)}
Q(w)$. So suppose that we have some element $w : \sm{n:\mathbb{N}} P(n)$.
Using bounded minimization, we can obtain the smallest element of $\sm{n:
\mathbb{N}} P(n)$ that's less than or equal to $w$, and this will in fact be
the smallest element _tout court_. This means that it's a member of our
constructed type, so we've constructed a map
%\[
\left\lVert \sm{n:\mathbb{N}} P(n) \right\rVert
\to
\sm{w:\sm{n:\mathbb{N}}P(n)}Q(w)
\]%
and projecting out gives the function in the statement.
*)
Local Open Scope nat_scope.
Fixpoint nat_code (n m : nat) :=
match n, m with
| O, O => Unit
| S n', O => Empty
| O, S m' => Empty
| S n', S m' => nat_code n' m'
end.
Fixpoint nat_r (n : nat) : nat_code n n :=
match n with
| O => tt
| S n' => nat_r n'
end.
Definition nat_encode (n m : nat) (p : n = m) : (nat_code n m)
:= transport (nat_code n) p (nat_r n).
Definition nat_decode : forall (n m : nat), (nat_code n m) -> (n = m).
Proof.
induction n, m; intro H.
reflexivity. contradiction. contradiction.
apply (ap S). apply IHn. apply H.
Defined.
Theorem equiv_path_nat : forall n m, (nat_code n m) <~> (n = m).
Proof.
intros.
refine (equiv_adjointify (nat_decode n m) (nat_encode n m) _ _).
intro p. destruct p. simpl.
induction n. reflexivity. simpl.
apply (ap (ap S) IHn).
generalize dependent m.
induction n. induction m.
intro c. apply eta_unit.
intro c. contradiction.
induction m.
intro c. contradiction.
intro c. simpl. unfold nat_encode.
refine ((transport_compose _ S _ _)^ @ _).
simpl. apply IHn.
Defined.
Lemma Sn_neq_O : forall n, S n <> O.
Proof.
intros n H. apply nat_encode in H. contradiction.
Defined.
Lemma plus_eq_O (n m : nat) : n + m = O -> (n = O) /\ (m = O).
Proof.
destruct n.
intro H. split. reflexivity. apply H.
intro H. simpl in H. apply nat_encode in H. contradiction.
Defined.
Lemma le_trans : forall n m k, (n <= m) -> (m <= k) -> (n <= k).
Proof.
intros n m k Hnm Hmk.
destruct Hnm as [l p].
destruct Hmk as [l' p'].
exists (l + l').
refine ((plus_assoc _ _ _)^ @ _).
refine (_ @ p'). f_ap.
Defined.
Lemma le_Sn_le (n m : nat) : S n <= m -> n <= m.
Proof.
intro H. apply (le_trans n (S n) m). exists 1. apply (plus_1_r _)^. apply H.
Defined.
Lemma plus_cancelL : forall n m k, n + m = n + k -> m = k.
Proof.
intro n. induction n. trivial.
intros m k H.
apply S_inj in H. apply IHn. apply H.
Defined.
Lemma le_antisymmetric (n m : nat) : (n <= m) -> (m <= n) -> (n = m).
Proof.
intro H. destruct H as [k p].
intro H. destruct H as [k' p'].
transparent assert (q : (n + (k + k') = n + O)).
refine ((plus_assoc _ _ _)^ @ _).
refine ((ap (fun s => s + k') p) @ _).
refine (_ @ (plus_O_r _)).
apply p'.
apply plus_cancelL in q.
apply plus_eq_O in q.
refine ((plus_O_r _) @ _).
refine ((ap (plus n) (fst q))^ @ _).
apply p.
Defined.
Lemma decidable_paths_nat : DecidablePaths nat.
Proof.
intros n m.
generalize dependent m.
generalize dependent n.
induction n, m.
left. reflexivity.
right. intro H. apply nat_encode in H. contradiction.
right. intro H. apply nat_encode in H. contradiction.
destruct (IHn m).
left. apply (ap S p).
right. intro H. apply S_inj in H. apply n0. apply H.
Defined.
Lemma hset_nat : IsHSet nat.
Proof. apply hset_decpaths. apply decidable_paths_nat. Defined.
Lemma hprop_le (n m : nat) : IsHProp (n <= m).
Proof.
apply hprop_allpath. intros p q.
refine (path_sigma_hprop _ _ _).
destruct p as [k p], q as [k' p']. simpl.
apply (plus_cancelL n).
apply (p @ p'^).
Defined.
Lemma hprop_dependent `{Funext} (A : Type) (P : A -> Type) :
(forall a, IsHProp (P a)) -> IsHProp (forall a, P a).
Proof.
intro HP.
apply hprop_allpath. intros p p'. apply path_forall; intro a. apply HP.
Defined.
Definition n_le_n (n : nat) : n <= n := (O; (plus_O_r n)^).
Definition n_le_Sn (n : nat) : n <= S n := (S O; (plus_1_r n)^).
Lemma Spred (n : nat) : (n <> O) -> S (pred n) = n.
Proof.
induction n; intro H; [contradiction H|]; reflexivity.
Defined.
Lemma le_partitions (n : nat) : forall m, (m <= n) + (n <= m).
Proof.
induction n.
intro m. right. exists m. reflexivity.
intro m.
destruct (IHn m) as [IHnm | IHnm].
left. apply (le_trans _ n). apply IHnm. apply n_le_Sn.
destruct IHnm as [k p].
destruct (decidable_paths_nat n m).
left. exists 1. refine ((plus_1_r _)^ @ _). apply (ap S p0^).
right. exists (pred k). refine ((plus_n_Sm _ _) @ _). refine (_ @ p).
f_ap. apply Spred.
intro H. apply n0.
refine ((plus_O_r _) @ _). refine ((ap (plus n) H^) @ _). apply p.
Defined.
Lemma le_neq__lt (n m : nat) : (n <= m) -> (n <> m) -> (n < m).
Proof.
intros H1 H2. destruct H1 as [k p].
exists (pred k). refine (_ @ p). f_ap.
apply Spred. intro Hk. apply H2.
refine (_ @ p). refine ((plus_O_r _) @ _). f_ap.
apply Hk^.
Defined.
Lemma lt_partitions (n m : nat) : (n < m) + (n = m) + (m < n).
Proof.
destruct (decidable_paths_nat n m).
left. right. apply p.
destruct (le_partitions n m).
right. apply le_neq__lt. apply l. intro H. apply n0. apply H^.
left. left. apply le_neq__lt. apply l. apply n0.
Defined.
Lemma p_nnp : forall P, P -> ~ ~ P.
Proof. auto. Defined.
Lemma n_nlt_n (n : nat) : ~ (n < n).
Proof.
intros H. destruct H as [k p].
apply (nat_encode (S k) O).
apply (plus_cancelL n).
apply (p @ (plus_O_r _)).
Defined.
Lemma n_neq_Sn (n : nat) : n <> S n.
Proof.
induction n.
intro H. apply nat_encode in H. contradiction.
intro H. apply IHn. apply S_inj in H. apply H.
Defined.
Lemma n_lt_Sm__n_le_m (n m : nat) : (n < S m) -> (n <= m).
Proof.
intro H. destruct H as [k p]. exists k.
apply S_inj. refine (_ @ p).
apply plus_n_Sm.
Defined.
Lemma le_O (n : nat) : n <= O -> n = O.
Proof.
intro H. destruct H as [k p].
apply plus_eq_O in p. apply (fst p).
Defined.
Lemma lt_1 (n : nat) : n < 1 -> n = O.
Proof.
intro H.
apply le_O. apply n_lt_Sm__n_le_m. apply H.
Defined.
Lemma lt_le (n m : nat) : n < m -> n <= m.
Proof.
intro H. destruct H as [k p].
exists (S k). apply p.
Defined.
Lemma Sn_lt_Sm__n_lt_m (n m : nat) : S n < S m -> n < m.
Proof.
intro H. destruct H as [k p]. exists k.
simpl in p. apply S_inj in p. apply p.
Defined.
Lemma lt_neq (n m : nat) : n < m -> n <> m.
Proof.
generalize dependent m.
induction n.
intros m H HX.
destruct H as [k p]. simpl in p.
apply (nat_encode (S k) O).
apply (p @ HX^).
induction m.
intros H HX.
apply (nat_encode (S n) O). apply HX.
intros H Hx.
apply Sn_lt_Sm__n_lt_m in H.
apply IHn in H. apply H. apply S_inj. apply Hx.
Defined.
Lemma lt_trans (n m k : nat) : n < m -> m < k -> n < k.
Proof.
intros H1 H2.
destruct H1 as [l p], H2 as [l' p'].
exists (l + S l').
refine (_ @ p').
change (S (l + S l')) with (S l + S l').
refine ((plus_assoc _ _ _)^ @ _). f_ap.
Defined.
Lemma n_lt_Sn (n : nat) : n < S n.
Proof.
exists O. apply (plus_1_r _)^.
Defined.
Lemma bound_up (n m : nat) : (n <= m) -> (n <> m) -> (S n <= m).
Proof.
intros H1 H2.
apply le_neq__lt in H1.
destruct H1 as [k p]. exists k.
refine ((plus_n_Sm _ _) @ _). apply p. apply H2.
Defined.
Lemma le_lt__lt (n m k : nat) : n <= m -> m < k -> n < k.
Proof.
intros H1 H2.
destruct (decidable_paths_nat n m).
destruct H2 as [l q].
exists l. refine (_ @ q). f_ap.
apply (lt_trans _ m).
apply le_neq__lt. apply H1. apply n0. apply H2.
Defined.
Lemma lt_le__lt (n m k : nat) : n < m -> m <= k -> n < k.
Proof.
intros H1 H2.
destruct (decidable_paths_nat m k).
destruct H1 as [l q].
exists l. refine (_ @ p). apply q.
apply (lt_trans _ m).
apply H1. apply le_neq__lt. apply H2. apply n0.
Defined.
Lemma le_eq__le (n m k : nat) : (n <= m) -> (m = k) -> (n <= k).
Proof.
intros H1 H2.
destruct H1 as [l p].
exists l. apply (p @ H2).
Defined.
Lemma n_le_m__Sn_le_Sm (n m : nat) : n <= m -> (S n <= S m).
Proof.
intro H. destruct H as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma Sn_le_Sm__n_le_m (n m : nat) : S n <= S m -> n <= m.
Proof.
intro H. destruct H as [k p]. exists k.
simpl in p. apply S_inj in p. apply p.
Defined.
Lemma n_nlt_O (n : nat) : ~ (n < O).
Proof.
induction n. apply n_nlt_n.
intro H. destruct H as [k p]. apply nat_encode in p. contradiction.
Defined.
Lemma O_lt_n (n : nat) : (n <> O) -> (O < n).
Proof.
intro H.
exists (pred n).
apply Spred. apply H.
Defined.
Lemma n_lt_m__Sn_lt_Sm (n m : nat) : n < m -> S n < S m.
Proof.
intro H. destruct H as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma n_lt_m__n_le_Sm (n m : nat) : n < m -> n <= S m.
Proof.
intro H. destruct H as [k p].
exists (S (S k)). apply (ap S) in p. refine (_ @ p).
symmetry. apply plus_n_Sm.
Defined.
Lemma lt_bound_down (n m : nat) : n < S m -> (n <> m) -> n < m.
Proof.
intros H X. destruct H as [k p].
exists (pred k). refine ((plus_n_Sm _ _)^ @ _).
refine ((plus_n_Sm _ _) @ _). apply S_inj. refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. apply (ap S). apply Spred.
intro H. apply X. apply S_inj. refine (_ @ p).
refine (_ @ (plus_n_Sm _ _)). apply (ap S). refine ((plus_O_r _) @ _). f_ap.
apply H^.
Defined.
Lemma lt_bound_up (n m : nat) : n < m -> (S n <> m) -> S n < m.
Proof.
intros H X.
destruct H as [k p]. exists (pred k). refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. f_ap. apply Spred. intro H.
apply X. refine (_ @ p). refine ((plus_1_r _) @ _). f_ap. f_ap. apply H^.
Defined.
Lemma pred_n_eq_O : forall n, pred n = O -> (n = O) + (n = 1).
Proof.
induction n.
intros. left. reflexivity.
intros H. simpl in H. right. apply (ap S H).
Defined.
Lemma bound_down (n m : nat) : (n <= S m) -> (n <> S m) -> (n <= m).
Proof.
intros H1 H2.
apply le_neq__lt in H1.
destruct H1 as [k p]. exists k.
apply S_inj. refine ((plus_n_Sm _ _) @ _). apply p. apply H2.
Defined.
Lemma nle_lt (n m : nat) : ~ (n <= m) -> (m < n).
Proof.
generalize dependent m.
induction n.
intros m H. assert Empty. apply H. exists m. reflexivity. contradiction.
intros m H. destruct m.
exists n. reflexivity.
apply n_lt_m__Sn_lt_Sm. apply IHn. intro H'. apply H.
destruct H' as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma Sn_neq_n (n : nat) : S n <> n.
Proof.
intro H.
apply (nat_encode 1 0).
apply (plus_cancelL n).
refine ((plus_1_r _)^ @ _). refine (_ @ (plus_O_r _)).
apply H.
Defined.
Lemma lt_antisymmetric (n m : nat) : n < m -> ~ (m < n).
Proof.
intros H HX.
destruct H as [k p], HX as [k' p'].
transparent assert (H : (S k + S k' = O)).
apply (plus_cancelL n). refine (_ @ (plus_O_r _)).
refine (_ @ p'). refine ((plus_assoc _ _ _)^ @ _). f_ap.
apply nat_encode in H. contradiction.
Defined.
Lemma lt_eq__lt (n m k : nat) : (n < m) -> (m = k) -> (n < k).
Proof.
intros H1 H2.
destruct H1 as [l p].
exists l. refine (p @ _). apply H2.
Defined.
Lemma nlt_le (n m : nat) : ~ (n < m) -> (m <= n).
Proof.
generalize dependent m.
induction n.
intros m H. destruct (decidable_paths_nat m O). exists O. refine (_ @ p).
symmetry. apply plus_O_r.
assert Empty. apply H. apply O_lt_n. apply n. contradiction.
induction m.
intro H. exists (S n). reflexivity.
intro H. apply n_le_m__Sn_le_Sm. apply IHn.
intro H'. apply H. apply n_lt_m__Sn_lt_Sm. apply H'.
Defined.
Lemma n_lt_m__Sn_le_m (n m : nat) : (n < m) -> (S n <= m).
Proof.
intro H.
apply n_lt_m__Sn_lt_Sm in H.
apply n_lt_Sm__n_le_m in H.
apply H.
Defined.
Lemma n_le_m__n_lt_Sm (n m : nat) : n <= m -> n < S m.
Proof.
intro H.
destruct H as [k p].
exists k. refine ((plus_n_Sm _ _)^ @ _). f_ap.
Defined.
Section Exercise3_19.
Context {P : nat -> Type} {HP : forall n, IsHProp (P n)}
{DP : forall n, P n + ~ P n}.
Local Definition Q (w : {n : nat & P n}) : Type :=
forall w' : {n : nat & P n}, w.1 <= w'.1.
Lemma hprop_Q `{Funext} : forall w, IsHProp (Q w).
Proof.
intro w. unfold Q. apply hprop_dependent. intro w'. apply hprop_le.
Defined.
Lemma hprop_sigma_Q `{Funext} : IsHProp {w : {n : nat & P n} & Q w}.
Proof.
apply hprop_allpath. intros w w'.
refine (path_sigma_hprop _ _ _). apply hprop_Q.
apply path_sigma_hprop. apply le_antisymmetric.
apply (w.2 w'.1). apply (w'.2 w.1).
Defined.
Definition bmin (bound : nat) : nat.
Proof.
induction bound as [|z].
destruct (DP O). apply O. apply 1.
destruct (lt_partitions IHz (S z)) as [[Ho | Ho] | Ho].
apply IHz.
destruct (DP (S z)).
apply (S z).
apply (S (S z)).
apply (S (S z)).
Defined.
Lemma bmin_correct_O (n : nat) : P O -> bmin n = O.
Proof.
intro H.
induction n. simpl. destruct (DP O). reflexivity. apply n in H. contradiction.
simpl. rewrite IHn. reflexivity.
Defined.
Lemma bmin_correct_self_P (n : nat) : bmin n = n -> P n.
Proof.
induction n.
intros H. simpl in H.
destruct (DP O).
apply p.
apply nat_encode in H. contradiction.
intro H.
simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
rewrite H in Ho. apply n_nlt_n in Ho. contradiction.
destruct (DP (S n)). apply p.
transparent assert (X : Empty).
apply (n_neq_Sn (S n)). apply H^.
contradiction.
transparent assert (X : Empty).
apply (n_neq_Sn (S n)). apply H^.
contradiction.
Defined.
Lemma bmin_correct_bound (n : nat) : bmin n <= S n.
Proof.
induction n.
simpl.
destruct (DP O). exists 1. reflexivity.
exists O. apply plus_n_Sm.
simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
apply (le_trans _ (S n)). apply IHn. apply n_le_Sn.
destruct (DP (S n)).
apply n_le_Sn.
apply n_le_n.
apply n_le_n.
Defined.
Lemma bmin_correct_nPn (n : nat) : bmin n = S n -> ~ P n.
Proof.
induction n.
intros H HX.
apply (bmin_correct_O O) in HX.
apply (nat_encode 1 O). refine (H^ @ _). refine (_ @ HX). reflexivity.
intros H HX. simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
rewrite H in Ho. apply (n_nlt_n (S (S n))).
apply (lt_trans _ (S n)). apply Ho. apply n_lt_Sn.
destruct (DP (S n)).
apply (n_neq_Sn (S n)). apply H.
apply n0. apply HX.
clear H.
apply (n_nlt_n (bmin n)).
apply (le_lt__lt _ (S n)).
apply bmin_correct_bound.
apply Ho.
Defined.
Lemma bmin_correct_success (n : nat) : bmin n < S n -> P (bmin n).
Proof.
induction n.
intro H. apply lt_1 in H. apply bmin_correct_self_P in H.
apply ((bmin_correct_O _ H)^ # H).
simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
intro H. apply IHn. apply Ho.
destruct (DP (S n)).
intro H. apply p.
intro H. apply n_nlt_n in H. contradiction.
intro H. apply n_nlt_n in H. contradiction.
Defined.
Lemma bmin_correct_i (n : nat) : forall m, (m < n) -> (m < bmin n) -> ~ P m.
Proof.
induction n.
intros m H1 H2.
apply n_nlt_O in H1. contradiction.
induction m. intro H. clear H.
destruct (decidable_paths_nat n O).
(* Case: n = O *)
(* we just want the contrapositive of bmin_correct_O *)
intro H.
apply (contrapositive (bmin_correct_O (S n))).
intro H'. rewrite H' in H. apply n_nlt_n in H. contradiction.
(* Case: n <> O *)
intro H. apply IHn. apply O_lt_n. apply n0.
simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
(* Case: bmin n < S n *)
apply H.
(* Case: bmin n = S n *)
rewrite Ho. apply O_lt_n. apply Sn_neq_O.
apply (lt_trans _ (S n)). apply O_lt_n. apply Sn_neq_O. apply Ho.
intros H1. apply Sn_lt_Sm__n_lt_m in H1. simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
(* Case: bmin n < S n *)
intro H. apply IHn.
destruct (decidable_paths_nat (bmin n) n).
rewrite <- p. apply H.
apply lt_bound_down in Ho.
apply (lt_trans _ (bmin n)). apply H. apply Ho. apply n0. apply H.
(* Case: bmin n = S n *)
intro H.
destruct (decidable_paths_nat (S m) n).
apply bmin_correct_nPn. rewrite p. apply Ho.
apply lt_bound_up in H1. apply IHn. apply H1.
apply (lt_trans _ n). apply H1. rewrite Ho. apply n_lt_Sn.
apply n0.
(* Case: bmin n > S n *)
set (H := (bmin_correct_bound n)).
assert Empty. apply (n_nlt_n (S n)).
apply (lt_le__lt _ (bmin n)).
apply Ho. apply H. contradiction.
Defined.
Lemma bmin_correct_i' (n : nat) : forall m, (m <= n) -> (m < bmin n) -> ~ P m.
Proof.
intros m H.
destruct (decidable_paths_nat m n).
clear H.
intro H.
set (H' := (bmin_correct_nPn n)). rewrite p. apply H'. clear H'.
set (H' := (bmin_correct_bound n)). rewrite p in H.
apply le_antisymmetric. apply H'. destruct H as [k q].
exists k. refine ((plus_n_Sm _ _) @ _). apply q.
apply le_neq__lt in H. generalize H. apply bmin_correct_i. apply n0.
Defined.
Lemma bmin_correct_leb (n : nat) : P n -> (bmin n <= n).
Proof.
induction n.
intro H. apply (bmin_correct_O O) in H.
exists O. refine (_ @ H). symmetry. apply plus_O_r.
intro H.
simpl. destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
destruct Ho as [k p]. exists (S k). apply p.
destruct (DP (S n)). exists O. symmetry. apply plus_O_r.
apply n0 in H. contradiction.
apply (le_trans _ (bmin n)).
apply n_lt_m__Sn_le_m. apply Ho.
apply (bmin_correct_bound n).
Defined.
Lemma bmin_correct_i_cp (n m : nat) : P m -> (bmin n <= m).
Proof.
intro H.
transparent assert (H' : (
forall n m : nat, (m < n /\ m < bmin n) -> ~ P m
)).
intros n' m' H'. apply (bmin_correct_i n'). apply (fst H'). apply (snd H').
transparent assert (H'' : (~ ~ P m)). apply p_nnp. apply H.
apply (contrapositive (H' n m)) in H''.
transparent assert (H''' : (sum (~ (m < n)) (~ (m < bmin n)))).
destruct (lt_partitions n m) as [[Ho | Ho] | Ho].
left. apply lt_antisymmetric. apply Ho.
left. intro H'''. apply (n_nlt_n n). apply (lt_eq__lt m n m) in H'''.
apply (n_nlt_n m) in H'''. contradiction.
apply Ho.
right. intro H'''.
apply H''. split. apply Ho. apply H'''.
destruct H'''; clear H'' H'.
apply nlt_le in n0.
apply nlt_le. intro H'.
set (H'' := (bmin_correct_bound n)).
transparent assert (Heq : (n = m)).
apply le_antisymmetric. apply n0. apply n_lt_Sm__n_le_m.
apply (lt_le__lt _ (bmin n) _). apply H'. apply H''.
transparent assert (Hle : (m <= n)).
exists O. refine (_ @ Heq^). symmetry. apply plus_O_r.
generalize H. change (P m -> Empty) with (~ P m).
apply (bmin_correct_i' n). apply Hle. apply H'.
apply nlt_le in n0. apply n0.
Defined.
Lemma bmin_correct (bound : nat) :
{n : nat & P n /\ n <= bound} -> forall n, P n -> bmin bound <= n.
Proof.
induction bound.
intros w n p.
destruct w as [w [a b]].
apply le_O in b.
exists n. transitivity (O + n). f_ap. apply bmin_correct_O. apply (b # a).
reflexivity.
intros w n p. simpl.
destruct (lt_partitions (bmin bound) (S bound)) as [[Ho | Ho] | Ho].
(* bmin bound < S bound *)
apply IHbound. exists (bmin bound). split.
apply bmin_correct_success. apply Ho.
destruct Ho as [k q]. exists k. apply S_inj. refine (_ @ q).
refine ((plus_n_Sm _ _) @ _). reflexivity.
apply p.
(* bmin bound = S bound *)
destruct w as [w [a b]].
destruct (decidable_paths_nat w (S bound)).
destruct (DP (S bound)).
apply nlt_le. intro H.
generalize p. change (P n -> Empty) with (~ P n).
apply (bmin_correct_i' bound).
apply n_lt_Sm__n_le_m. apply H. rewrite Ho. apply H.
rewrite <- p0 in n0. apply n0 in a. contradiction.
apply le_neq__lt in b.
apply n_lt_Sm__n_le_m in b.
transparent assert (Hlt : (w < bmin bound)).
apply (lt_eq__lt _ (S bound)).
apply n_le_m__n_lt_Sm. apply b. apply Ho^.
assert Empty. generalize a. change (P w -> Empty) with (~ P w).
apply (bmin_correct_i' bound). apply b. apply Hlt. contradiction. apply n0.
(* S bound < bmin bound *)
set (H := (bmin_correct_bound bound)).
apply (lt_le__lt _ _ (S bound)) in Ho.
apply n_nlt_n in Ho. contradiction.
apply H.
Defined.
Lemma ex3_19 `{Funext} : Brck {n : nat & P n} -> {n : nat & P n}.
Proof.
intro w.
apply (@pr1 _ Q).
set (H' := hprop_sigma_Q).
strip_truncations.
transparent assert (w' : {n : nat & P n}).
exists (bmin w.1).
apply bmin_correct_success.
apply n_le_m__n_lt_Sm. apply bmin_correct_leb. apply w.2.
exists w'.
unfold Q.
intro w''.
apply bmin_correct.
exists w.1. split. apply w.2. apply n_le_n. apply w''.2.
Defined.
End Exercise3_19.
Local Close Scope nat_scope.
(** %\exerdone{3.20}{128}%
Prove Lemma 3.11.9(ii): if $A$ is contractible with center $a$, then
$\sm{x:A}P(x)$ is equivalent to $P(a)$.
*)
(** %\soln%
Suppose that $A$ is contractible with center $a$. For the forward direction,
suppose that $w : \sm{x:A} P(x)$. Then $\fst(w) = a$, since $A$ is
contractible, so from $\snd(w) : P(\fst(w))$ and the indiscernibility
of identicals, we have $P(a)$. For the backward direction, suppose
that $p : P(a)$. Then we have $(a, p) : \sm{x:A} P(x)$.
To show that these are quasi-inverses, suppose that $p : P(a)$. Going backward
gives $(a, p) : \sm{x:A} P(x)$, and going forward we have
$(\contr_{a}^{-1})_{*}p$. Since $A$ is contractible, $\contr_{a} =
\refl{a}$, so this reduces to $p$, as needed.
For the other direction, suppose that $w : \sm{x:X} P(x)$. Going forward gives
$(\contr_{\fst(w)}^{-1})_{*}\snd(w) : P(a)$, and going back gives
%\[
(a, (\contr_{\fst(w)}^{-1})_{*}\snd(w)) : \sm{x:A} P(x)
\]%
By Theorem 2.7.2, it suffices to show that $a = \fst(w)$ and that
%\[
(\contr_{\fst(w)})_{*}(\contr_{\fst(w)}^{-1})_{*} \snd(w) = \snd(w)
\]%
The first of these is given by the fact that $A$ is contractible. The second
results from the functorality of transport.
*)
Module Ex20.
Theorem equiv_sigma_contr_base (A : Type) (P : A -> Type) (HA : Contr A) :
{x : A & P x} <~> P (center A).
Proof.
simple refine (equiv_adjointify _ _ _ _).
intro w. apply (transport _ (contr w.1)^). apply w.2.
intro p. apply (center A; p).
intro p. simpl.
assert (Contr (center A = center A)). apply contr_paths_contr.
assert (contr (center A) = idpath). apply path_ishprop.
rewrite X0. reflexivity.
intro w. apply path_sigma_uncurried.
simpl. exists (contr w.1).
apply transport_pV.
Defined.
End Ex20.
(** %\exerdone{3.21}{128}%
Prove that $\isprop(P) \eqvsym (P \eqvsym \brck{P})$.
*)
(** %\soln%
$\isprop(P)$ is a mere proposition by Lemma 3.3.5. $P \eqvsym \brck{P}$ is
also a mere proposition. An equivalence is determined by its underlying
function, and for all $f, g : P \to \brck{P}$, $f = g$ by function
extensionality and the fact that $\brck{P}$ is a mere proposition. Since each
of the two sides is a mere proposition, we just need to show that they imply
each other, by Lemma 3.3.3. Lemma 3.9.1 gives the forward direction. For the
backward direction, suppose that $e : P \eqvsym \brck{P}$, and let $x, y : P$.
Then $e(x) = e(y)$, since $\brck{P}$ is a proposition, and applying $e^{-1}$ to
each side gives $x = y$. Thus $P$ is a mere proposition.
*)
Theorem ex3_21 `{Funext} (P : Type) : IsHProp P <~> (P <~> Brck P).
Proof.
assert (IsHProp (P <~> Brck P)). apply hprop_allpath; intros e1 e2.
apply path_equiv. apply path_forall; intro p.
apply hprop_allpath. apply path_ishprop.
apply equiv_iff_hprop.
intro HP. apply equiv_iff_hprop. apply tr.
apply Trunc_ind. intro p. apply HP. apply idmap.
intro e. apply hprop_allpath; intros x y.
assert (e x = e y) as p. apply hprop_allpath. apply path_ishprop.
rewrite (eissect e x)^. rewrite (eissect e y)^.
apply (ap e^-1 p).
Defined.
(** %\exerdone{3.22}{128}%
As in classical set theory, the finite version of the axiom of choice is a
theorem. Prove that the axiom of choice holds when $X$ is a finite type
$\Fin(n)$.
*)
(** %\soln%
We want to show that for all $n$, $A : \Fin(n) \to \UU$, and
$P : \prd{m_{n} : \Fin(n)} A(m_{n}) \to \UU$, if $A$ is a family of sets and
$P$ a family of propositions, then
%\[
\left(
\prd{m_{n} : \Fin(n)} \left\lVert \sm{a:A(m_{n})} P(m_{n}, a)\right\rVert
\right)
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A(m_{n})} \prd{m_{n} : \Fin(n)}
P(m_{n}, g(m_{n}))
}
\]%
We proceed by induction on $n$. Note first that $\eqv{\Fin(0)}{\emptyt}$ and
that $\eqv{\Fin(n + 1)}{\Fin(n) + \unit}$, which follow quickly from the fact
that $\N$ is a set. In particular, we'll use the equivalence which sends
$n_{n+1}$ to $\star$ and $m_{n+1}$ to $m_{n}$ for $m < n$.
For the base case, $n \equiv 0$, everything is easily provided by ex falso
quodlibet.
For the induction step, we can define a new family of sets $A' : (\Fin(n) +
\unit) \to \UU$ as follows:
%\begin{align*}
A'(z) &= \begin{cases}
A(m_{n+1}) & \text{if $z \equiv m_{n}$} \\
A(n_{n+1}) & \text{if $z \equiv \star$}
\end{cases}
\end{align*}%
And if $e : \eqv{\Fin(n+1)}{\Fin(n) + \unit}$, then we clearly have
$h : \eqv{A(z)}{A'(e(z))}$ for all $z : \Fin(n+1)$. Similarly, we can define
%\begin{align*}
P'(z, a) &= \begin{cases}
P(m_{n+1}, h^{-1}(a)) & \text{if $z \equiv m_{n}$} \\
P(n_{n+1}, h^{-1}(a)) & \text{if $z \equiv \star$}
\end{cases}
\end{align*}%
For which we clearly have $g : \eqv{P(z, a)}{P'(e(z), h(a))}$ for all $z$ and
$a$. So, by the functorality of equivalence (Ex.%~%2.17), we have
%\[
\eqv{
\prd{m_{n+1} : \Fin(n + 1)} \brck{\sm{a : A(m_{n+1})} P(m_{n+1}, a)}
}{
\prd{z : \Fin(n) + \unit} \brck{\sm{a : A'(z)} P'(z, a)}
}
\]%
But, since the induction principle for the sum type is an equivalence, we also
have
%\[
\eqv{
\prd{z : \Fin(n) + \unit} \brck{\sm{a : A'(z)} P'(z, a)}
}{
\left(\prd{z : \Fin(n)} \brck{\sm{a : A'(\inl(z))} P'(\inl(z), a)}\right)
\times
\left(\prd{z : \unit} \brck{\sm{a : A'(\inr(z))} P'(\inr(z), a)}\right)
}
\]%
And to construct an arrow out of this, we just need to give an arrow out of
each one. Now, by the same equivalences, we can rewrite the conclusion as
%\[
\brck{
\sm{g : \prd{z : \Fin(n) + \unit} A'(z)}
\prd{z : \Fin(n) + \unit}
P'(z, g(z))
}
\]%
Using the universal property of $\Sigma$ types, we get
%\[
\brck{
\prd{z : \Fin(n) + \unit} \sm{a : A'(z)} P'(z, a)
}
\]%
and the functorality of the induction principle for the sum gives
%\[
\brck{
\left(\prd{z : \Fin(n)} \sm{a : A'(\inl(z))} P'(\inl(z), a)\right)
\times
\left(\prd{z : \unit} \sm{a : A'(\inr(z))} P'(\inr(z), a)\right)
}
\]%
Since this is only a finite product, we can take it outside of the truncation,
giving
%\[
\brck{
\prd{z : \Fin(n)} \sm{a : A'(\inl(z))} P'(\inl(z), a)
}
\times
\brck{
\prd{z : \unit} \sm{a : A'(\inr(z))} P'(\inr(z), a)
}
\]%
and using the universal property of $\Sigma$ types to go back once more, we
finally arrive at
%\[
\brck{
\sm{g : \prd{z : \Fin(n)} A'(\inl(z))}
\prd{z : \Fin(n)}
P'(\inl(z), g(z))
}
\times
\brck{
\prd{z : \unit}
\sm{a : A'(\inr(z))}
P'(\inr(z), a)
}
\]%
Since each of the domain and codomain are products, we can produce the required
map by giving one between the first items of each product and one between the
second. So first we need an arrow
%\[
\prd{m_{n} : \Fin(n)} \brck{\sm{a : A'(\inl(m_{n}))} P'(\inl(m_{n}), a)}
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A'(\inl(m_{n}))}
\prd{m_{n} : \Fin(n)}
P'(\inl(m_{n}), g(m_{n}))
}
\]%
but by definition of $A'$ and $P'$, this is just
%\[
\prd{m_{n} : \Fin(n)} \brck{\sm{a : A(m_{n})} P(m_{n}, a)}
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A(m_{n})}
\prd{m_{n} : \Fin(n)}
P(m_{n}, g(m_{n}))
}
\]%
which is the induction hypothesis. For the second map, we need
%\[
\prd{z : \unit}\brck{\sm{a : A'(\inr(z))} P'(\inr(z), a)}
\to
\brck{\prd{z : \unit}\sm{a : A'(\inr(z))} P'(\inr(z), a)}
\]%
which by the computation rules for $A'$ and $P'$ is
%\[
\left(\unit \to \brck{\sm{a : A(n_{n+1})} P(n_{n+1}, a)}\right)
\to
\brck{\unit \to \sm{a : A(n_{n+1})} P(n_{n+1}, a)}
\]%
and this is easily constructed using the recursor for truncation.
*)
Definition cardO : Fin O -> Empty.
Proof.
intro w. destruct w as [n [k p]].
apply plus_eq_O in p. apply (nat_encode (S k) O). apply (snd p).
Defined.
Theorem isequiv_cardO : IsEquiv cardO.
Proof.
simple refine (isequiv_adjointify _ _ _ _).
apply Empty_rect.
(* Section *)
intro w. contradiction.
(* Retraction *)
intro w. destruct w as [n [k p]].
assert Empty.
apply (nat_encode (S k) O).
apply (@snd (n = O) _).
apply plus_eq_O.
apply p.
contradiction.
Defined.
Definition cardF {n : nat} : Fin (S n) -> Fin n + Unit.
Proof.
intro w.
destruct w as [m [k p]].
destruct (decidable_paths_nat m n).
right. apply tt.
left. exists m. exists (pred k).
apply S_inj. refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. f_ap. apply Spred.
intro H. apply n0. apply S_inj. refine (_ @ p).
refine ((plus_O_r _) @ _). refine ((plus_n_Sm _ _) @ _). f_ap. f_ap.
apply H^.
Defined.
Lemma plus_cancelR (n m k : nat) : plus m n = plus k n -> m = k.
Proof.
intro H.
apply (plus_cancelL n).
refine ((plus_comm _ _) @ _). refine (H @ _). apply (plus_comm _ _)^.
Defined.
Lemma hprop_lt (n m : nat) : IsHProp (lt n m).
Proof.
apply hprop_allpath. intros x y.
apply path_sigma_hprop.
destruct x as [x p], y as [y p'].
simpl. apply S_inj. apply (plus_cancelL n). apply (p @ p'^).
Defined.
Lemma path_Fin (n : nat) (w w' : Fin n) : (w.1 = w'.1) -> w = w'.
Proof.
intro p.
destruct w as [m w], w' as [m' w'].
simpl. apply path_sigma_uncurried. exists p.
set (H := hprop_lt m' n).
apply path_ishprop.
Defined.
Theorem isequiv_cardF : forall n, IsEquiv (@cardF n).
Proof.
intro n.
simple refine (isequiv_adjointify _ _ _ _).
(* inverse *)
intro H. destruct H as [w | t]. destruct w as [m [k p]].
exists m. exists (S k). refine ((plus_n_Sm _ _)^ @ _). apply (ap S). apply p.
exists n. exists O. apply (plus_1_r _)^.
(* Section *)
intro H. destruct H as [w | t].
(* w : Fin n *)
destruct w as [m [k p]]. unfold cardF. simpl.
destruct (decidable_paths_nat m n).
assert Empty. apply (nat_encode (S k) O). apply (plus_cancelL m).
refine (_ @ (plus_O_r _)). refine (_ @ p0^). apply p. contradiction.
apply (ap inl). apply path_Fin. reflexivity.
(* t : Unit *)
unfold cardF. simpl. destruct (decidable_paths_nat n n).
apply (ap inr). apply contr_unit. contradiction (n0 1).
(* Retraction *)
intro w. destruct w as [m [k p]]. unfold cardF. simpl.
destruct (decidable_paths_nat m n).
apply path_Fin. apply p0^.
apply path_Fin. reflexivity.
Defined.
Lemma eq_lt__lt (n m k : nat) : (n = m) -> (lt m k) -> (lt n k).
Proof.
intros p w.
destruct w as [l q].
exists l. refine (_ @ q). f_ap.
Defined.
Lemma pred_inj (n m : nat) : n <> O -> m <> O -> (pred n = pred m) -> n = m.
Proof.
intros Hn Hm H.
refine ((Spred n Hn)^ @ _). refine (_ @ (Spred m Hm)).
apply (ap S). apply H.
Defined.
Lemma pn_lt_n (n : nat) : n <> O -> (lt (pred n) n).
Proof.
intro H. exists O. refine ((plus_1_r _)^ @ _). apply Spred. apply H.
Defined.
Lemma brck_equiv (A B : Type) : (A <~> B) -> (Brck A <~> Brck B).
Proof.
intro e.
apply equiv_iff_hprop.
intro a'. strip_truncations. apply tr. apply e. apply a'.
intro b'. strip_truncations. apply tr. apply e^-1. apply b'.
Defined.
Theorem brck_functor_prod (A B : Type) : Brck (A * B) <~> Brck A * Brck B.
Proof.
apply equiv_iff_hprop.
intro x. split; strip_truncations; apply tr. apply (fst x). apply (snd x).
intro x. destruct x as [a b]. strip_truncations. apply tr. apply (a, b).
Defined.
(* The induction step of the proof *)
Section ISFAC.
Context {n : nat} {A : Fin (S n) -> Type} {P : forall m, A m -> Type}.
Local Definition A' := A o (@equiv_inv _ _ cardF (isequiv_cardF n)).
Local Definition P' : forall m, A' m -> Type.
Proof.
intros m a.
simple refine (P _ _).
apply (@equiv_inv _ _ cardF (isequiv_cardF n)).
apply m. apply a.
Defined.
Theorem domain_trans `{Funext} :
(forall m, Brck {a : A m & P m a})
<~>
(forall z, Brck {a : A ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z))
& P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) a})
*
(forall z : Unit, Brck {a : A (n; (O; (plus_1_r _)^)) &
P (n; (O; (plus_1_r _)^)) a}).
Proof.
equiv_via (forall z, Brck {a : A' z & P' z a}).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z.
apply brck_equiv.
simple refine (equiv_functor_sigma' _ _).
unfold A'. apply equiv_idmap.
intro a. unfold P'. simpl. apply equiv_idmap.
equiv_via (
(forall z, Brck {a : A' (inl z) & P' (inl z) a})
*
(forall z, Brck {a : A' (inr z) & P' (inr z) a})
).
apply equiv_inverse.
simple refine (equiv_sum_ind _).
apply equiv_functor_prod'; apply equiv_idmap.
Defined.
Theorem codomain_trans `{Funext} :
Brck {g : forall m, A m & forall m, P m (g m)}
<~>
Brck {g : forall z, (A o (@equiv_inv _ _ cardF (isequiv_cardF n)) o inl) z
& forall z,
P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) (g z)}
*
Brck (forall z : Unit, {a : A (n; (O; (plus_1_r _)^)) &
P (n; (O; (plus_1_r _)^)) a}).
Proof.
equiv_via (Brck {g : forall z, A' z & forall z, P' z (g z)}).
apply brck_equiv.
simple refine (equiv_functor_sigma' _ _).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z. apply equiv_idmap.
intro g. simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z. apply equiv_idmap.
equiv_via (Brck (forall z, {a : A' z & P' z a})).
apply brck_equiv. refine (equiv_sigT_coind _ _).
equiv_via (Brck ((forall z, {a : A' (inl z) & P' (inl z) a})
*
(forall z, {a : A' (inr z) & P' (inr z) a}))).
apply brck_equiv.
apply equiv_inverse. refine (equiv_sum_ind _).
equiv_via (Brck (forall z : Fin n, {a : A' (inl z) & P' (inl z) a})
*
Brck (forall z : Unit, {a : A' (inr z) & P' (inr z) a})).
apply brck_functor_prod.
refine (equiv_functor_prod' _ _).
apply brck_equiv.
unfold A', P'.
apply equiv_inverse.
refine (equiv_sigT_coind _ _).
apply brck_equiv. apply equiv_idmap.
Defined.
End ISFAC.
Theorem finite_AC `{Funext} (n : nat) (A : Fin n -> Type)
(P : forall m, A m -> Type) :
(forall m, Brck {a : A m & P m a})
-> Brck {g : forall m, A m & forall m, P m (g m)}.
Proof.
induction n.
intro H'. apply tr.
exists (fun m : Fin 0 => Empty_rect (fun _ => A m) (cardO m)).
intro m. contradiction (cardO m).
intro f.
apply domain_trans in f.
destruct f as [fn f1].
apply codomain_trans.
split.
apply (IHn _ ((fun z a =>
P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) a))).
apply fn.
set (z := tt).
apply f1 in z. strip_truncations. apply tr. intro t. apply z.
Defined.
(**
There's also a shorter proof by way of Lemma 3.8.2. It suffices to show
for all $n : \N$ and $Y : \Fin(n) \to \UU$
%\[
\left(\prd{m_{n} : \Fin(n)} \brck{Y(m_{n})}\right)
\to
\brck{\prd{m_{n} : \Fin(n)} Y(x)}
\]%
Things proceed by induction, as before. For $n \equiv 0$ everything follows
from a contradiction. For the induction step, we can define a new family $Y' :
(\Fin(n) + \unit) \to \UU$ as before. Then
%\[
\prd{m_{n+1} : \Fin(n+1)} \brck{Y(m_{n+1})}
\eqvsym
\prd{z : \Fin(n) + \unit} \brck{Y'(z)}
\eqvsym
\left(\prd{z : \Fin(n)} \brck{Y'(\inl(z))}\right)
\times
\left(\prd{z : \unit} \brck{Y'(\inr(z))}\right)
\]%
and
%\begin{align*}
\brck{\prd{m_{n+1} : \Fin(n+1)} Y(m_{n+1})}
&\eqvsym
\brck{\prd{z : \Fin(n) + \unit} Y'(z)}
\\&\eqvsym
\brck{\left(\prd{z : \Fin(n)} Y'(\inl(z))\right)
\times
\left(\prd{z : \unit} Y'(\inr(z))\right)}
\\&\eqvsym
\brck{\prd{z : \Fin(n)} Y'(\inl(z))}
\times
\brck{\prd{z : \unit} Y'(\inr(z))}
\end{align*}%
As before, we pair the induction hypothesis with a trivially constructed map to
produce the required arrow.
*)
(* the induction step *)
Section ISFAC'.
Context {n : nat} {Y : Fin (S n) -> Type}.
Local Definition Y' := Y o (@equiv_inv _ _ cardF (isequiv_cardF n)).
Theorem domain_trans' `{Funext} :
(forall m, Brck (Y m))
<~>
(forall z, Brck (Y ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z))))
* (forall z : Unit, Brck (Y (n; (O; (plus_1_r _)^)))).
Proof.
equiv_via (forall z, Brck (Y' z)).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro b. apply equiv_idmap.
equiv_via ((forall z, Brck (Y' (inl z))) * (forall z, Brck (Y' (inr z)))).
apply equiv_inverse. refine (equiv_sum_ind _).
apply equiv_idmap.
Defined.
Theorem codomain_trans' `{Funext} :
Brck (forall z, Y ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)))
*
Brck (forall z : Unit, Y (n; (O; (plus_1_r _)^)))
<~>
Brck (forall m, Y m).
Proof.
equiv_via (Brck (forall z, Y' (inl z)) * Brck (forall z : Unit, Y' (inr z))).
apply equiv_idmap.
equiv_via (Brck ((forall z, Y' (inl z)) * (forall z, Y' (inr z)))).
apply equiv_inverse. apply brck_functor_prod.
equiv_via (Brck (forall z, Y' z)).
apply brck_equiv. refine (equiv_sum_ind _).
apply brck_equiv. simple refine (equiv_functor_forall' _ _).
apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro b. unfold Y'. apply equiv_path.
f_ap. apply eissect.
Defined.
End ISFAC'.
Theorem finite_AC' `{Funext} (n : nat) (Y : Fin n -> Type) :
(forall m, Brck (Y m)) -> Brck (forall m, Y m).
Proof.
induction n.
intro H'. apply tr. intro m. contradiction (cardO m).
intro f.
apply domain_trans' in f. destruct f as [fn f1].
apply codomain_trans'. split.
apply IHn. apply fn.
set (z := tt). apply f1 in z. strip_truncations. apply tr. intro t. apply z.
Defined.
Theorem finite_AC_eqv_finite_AC' `{Funext} :
(forall (n : nat) (A : Fin n -> Type) P,
(forall m, Brck {a : A m & P m a})
->
Brck {g : forall m, A m & forall m, P m (g m)})
<~>
(forall (n : nat) (Y : Fin n -> Type),
(forall m, Brck (Y m)) -> Brck (forall m, Y m)).
Proof.
apply equiv_iff_hprop.
(* forward *)
intros finite_AC n Y f.
transparent assert (e : (
Brck {g : forall m, Y m & forall m, (fun z a => Unit) m (g m)}
<~>
Brck (forall m, Y m)
)).
equiv_via (Brck (forall m, {y : Y m & (fun z a => Unit) m y})).
apply brck_equiv. refine (equiv_sigT_coind _ _).
apply brck_equiv. simple refine (equiv_functor_forall' _ _). apply equiv_idmap.
intro b. apply equiv_sigma_contr. intro y. apply contr_unit.
apply e. clear e.
apply (finite_AC n Y (fun z a => Unit)).
intro m. assert (Brck (Y m)). apply (f m).
strip_truncations. apply tr. exists X. apply tt.
(* back *)
intros finite_AC' n A P f.
transparent assert (e : (
Brck (forall m, (fun x => {a : A x & P x a}) m)
<~>
Brck {g : forall m : Fin n, A m & forall m : Fin n, P m (g m)}
)).
apply brck_equiv.
apply equiv_inverse. refine (equiv_sigT_coind _ _).
apply e. clear e.
apply finite_AC'. apply f.
Defined.
Theorem finite_AC_alt `{Funext} (n : nat) (A : Fin n -> Type)
(P : forall m, A m -> Type) :
(forall m, Brck {a : A m & P m a})
-> Brck {g : forall m, A m & forall m, P m (g m)}.
Proof.
generalize dependent n.
apply finite_AC_eqv_finite_AC'.
apply finite_AC'.
Defined.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_1_V
`define SKY130_FD_SC_LP__NAND3B_1_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_1 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_1 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_ifqdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_ifqdp
// Description:
// The IFQ is the icache fill queue. This communicates between the
// IFU and the outside world. It handles icache misses and
// invalidate requests from the crossbar.
//
*/
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK_EN
`define FPGA_SYN_CLK_DFF
`endif
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "iop.h"
`include "ifu.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module sparc_ifu_ifqdp(/*AUTOARG*/
// Outputs
so, ifu_lsu_pcxpkt_e, ifq_fdp_fill_inst, ifq_erb_asidata_i2,
ifd_inv_ifqop_i2, ifq_icd_index_bf, ifq_icd_wrdata_i2,
ifq_ict_wrtag_f, ifq_erb_wrindex_f, ifq_icd_wrway_bf,
ifd_ifc_milhit_s, ifd_ifc_instoffset0, ifd_ifc_instoffset1,
ifd_ifc_instoffset2, ifd_ifc_instoffset3, ifd_ifc_cpxthr_nxt,
ifd_ifc_cpxreq_nxt, ifd_ifc_cpxreq_i1, ifd_ifc_destid0,
ifd_ifc_destid1, ifd_ifc_destid2, ifd_ifc_destid3,
ifd_ifc_newdestid_s, ifd_ifc_pcxline_d, ifd_ifc_asi_vachklo_i2,
ifd_ifc_cpxvld_i2, ifd_ifc_asiaddr_i2, ifd_ifc_iobpkt_i2,
ifd_ifc_fwd2ic_i2, ifd_ifc_4bpkt_i2, ifd_ifc_cpxnc_i2,
ifd_ifc_cpxce_i2, ifd_ifc_cpxue_i2, ifd_ifc_cpxms_i2,
ifd_ifc_miladdr4_i2, ifd_inv_wrway_i2,
// Inputs
rclk, se, si, lsu_ifu_cpxpkt_i1, lsu_ifu_asi_addr,
lsu_ifu_stxa_data, itlb_ifq_paddr_s, fdp_ifq_paddr_f,
ifc_ifd_reqvalid_e, ifc_ifd_filladdr4_i2, ifc_ifd_repway_s,
ifc_ifd_uncached_e, ifc_ifd_thrid_e, ifc_ifd_pcxline_adj_d,
ifc_ifd_errinv_e, ifc_ifd_ldmil_sel_new, ifc_ifd_ld_inq_i1,
ifc_ifd_idx_sel_fwd_i2, ifc_ifd_milreq_sel_d_l,
ifc_ifd_milfill_sel_i2_l, ifc_ifd_finst_sel_l,
ifc_ifd_ifqbyp_sel_fwd_l, ifc_ifd_ifqbyp_sel_inq_l,
ifc_ifd_ifqbyp_sel_asi_l, ifc_ifd_ifqbyp_sel_lsu_l,
ifc_ifd_ifqbyp_en_l, ifc_ifd_addr_sel_bist_i2_l,
ifc_ifd_addr_sel_asi_i2_l, ifc_ifd_addr_sel_old_i2_l,
ifc_ifd_addr_sel_fill_i2_l, mbist_icache_way, mbist_icache_word,
mbist_icache_index
);
input rclk,
se,
si;
input [`CPX_WIDTH-1:0] lsu_ifu_cpxpkt_i1;
input [17:0] lsu_ifu_asi_addr;
input [47:0] lsu_ifu_stxa_data;
input [39:10] itlb_ifq_paddr_s;
input [9:2] fdp_ifq_paddr_f;
// from ifqctl
input ifc_ifd_reqvalid_e;
input ifc_ifd_filladdr4_i2;
input [1:0] ifc_ifd_repway_s;
input ifc_ifd_uncached_e;
input [1:0] ifc_ifd_thrid_e;
input [4:2] ifc_ifd_pcxline_adj_d;
input ifc_ifd_errinv_e;
// 2:1 mux selects
input [3:0] ifc_ifd_ldmil_sel_new; // mil load enable
input ifc_ifd_ld_inq_i1; // ld new cpxreq to in buffer
input ifc_ifd_idx_sel_fwd_i2;
// other mux selects
input [3:0] ifc_ifd_milreq_sel_d_l, // selects outgoing mil_req
ifc_ifd_milfill_sel_i2_l; // selects the mil entry just
// returned from the fill
// port
input [3:0] ifc_ifd_finst_sel_l; // address to load to thr IR
input ifc_ifd_ifqbyp_sel_fwd_l, // select next input to process
ifc_ifd_ifqbyp_sel_inq_l,
ifc_ifd_ifqbyp_sel_asi_l,
ifc_ifd_ifqbyp_sel_lsu_l;
input ifc_ifd_ifqbyp_en_l;
input ifc_ifd_addr_sel_bist_i2_l,
ifc_ifd_addr_sel_asi_i2_l,
ifc_ifd_addr_sel_old_i2_l,
ifc_ifd_addr_sel_fill_i2_l;
input [1:0] mbist_icache_way;
input mbist_icache_word;
input [7:0] mbist_icache_index;
output so;
output [51:0] ifu_lsu_pcxpkt_e;
output [32:0] ifq_fdp_fill_inst;
output [47:0] ifq_erb_asidata_i2;
output [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;
output [`IC_IDX_HI:2] ifq_icd_index_bf; // index for wr and bist
output [135:0] ifq_icd_wrdata_i2;
output [`IC_TAG_SZ:0] ifq_ict_wrtag_f; // fill tag
// output [`IC_TAG_SZ-1:0] ifq_erb_wrtag_f; // tag w/o parity
output [`IC_IDX_HI:4] ifq_erb_wrindex_f;
output [1:0] ifq_icd_wrway_bf; // fill data way
output [3:0] ifd_ifc_milhit_s; // if an Imiss hits in MIL
// output [7:0] ifd_ifc_mil_repway_s;
output [1:0] ifd_ifc_instoffset0; // to select inst to TIR
output [1:0] ifd_ifc_instoffset1; // to select inst to TIR
output [1:0] ifd_ifc_instoffset2; // to select inst to TIR
output [1:0] ifd_ifc_instoffset3; // to select inst to TIR
output [1:0] ifd_ifc_cpxthr_nxt;
output [3:0] ifd_ifc_cpxreq_nxt; // cpx reqtype + vbit
output [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1; // cpx reqtype + vbit
output [2:0] ifd_ifc_destid0,
ifd_ifc_destid1,
ifd_ifc_destid2,
ifd_ifc_destid3,
ifd_ifc_newdestid_s;
output [4:2] ifd_ifc_pcxline_d;
output ifd_ifc_asi_vachklo_i2;
output ifd_ifc_cpxvld_i2;
output [3:2] ifd_ifc_asiaddr_i2;
output ifd_ifc_iobpkt_i2;
output ifd_ifc_fwd2ic_i2;
output ifd_ifc_4bpkt_i2;
output ifd_ifc_cpxnc_i2;
output ifd_ifc_cpxce_i2,
ifd_ifc_cpxue_i2,
ifd_ifc_cpxms_i2;
output [3:0] ifd_ifc_miladdr4_i2;
output [1:0] ifd_inv_wrway_i2;
//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------
// local signals
wire [39:0] imiss_paddr_s;
wire [9:2] lcl_paddr_s;
wire [42:2] mil_entry0, // mil entries
mil_entry1,
mil_entry2,
mil_entry3;
// wire [42:2] mil0_in_s, // inputs to mil
// mil1_in_s,
// mil2_in_s,
// mil3_in_s;
wire tag_par_s,
tag_par_i2;
wire [42:2] newmil_entry_s;
wire [42:2] mil_pcxreq_d, // outgoing request from mil
pcxreq_d, // mil or direct ic or prev req
pcxreq_e; // outgoing request to lsu
wire [42:2] fill_addr_i2,
fill_addr_adj,
icaddr_i2,
asi_addr_i2,
bist_addr_i2;
wire [42:4] wraddr_f;
wire [`CPX_WIDTH-1:0] inq_cpxpkt_i1, // output from inq
// inq_cpxpkt_nxt,
stxa_data_pkt,
fwd_data_pkt,
ifqop_i1,
ifqop_i2; // ifq op currently being processed
wire [3:0] swc_i2;
wire [135:0] icdata_i2;
wire [3:0] parity_i2,
par_i2;
wire [17:0] asi_va_i2,
asi_va_i1;
wire [13:2] asi_fwd_index;
wire clk;
// wire [`IC_IDX_HI:6] inv_addr_i2;
//
// Code start here
//
assign clk = rclk;
//----------------------------------------------------------------------
// Instruction Miss - Fill Request Datapath
//----------------------------------------------------------------------
// new set of flops
dff_s #(8) pcs_reg(.din (fdp_ifq_paddr_f[9:2]),
.q (lcl_paddr_s[9:2]),
.clk (clk), .se(se), .si(), .so());
// bits 1:0 are floating
assign imiss_paddr_s = {itlb_ifq_paddr_s[39:10],
lcl_paddr_s[9:2],
2'b0};
// Check for hit in MIL
// Should we enable the comps to save power? -- timing problem
// compare only top 35 bits (bot 5 bits are line offset of 32B line)
sparc_ifu_cmp35 milcmp0 (.hit (ifd_ifc_milhit_s[0]),
.a (imiss_paddr_s[39:5]),
.b (mil_entry0[39:5]),
.valid (1'b1)
);
sparc_ifu_cmp35 milcmp1 (.hit (ifd_ifc_milhit_s[1]),
.a (imiss_paddr_s[39:5]),
.b (mil_entry1[39:5]),
.valid (1'b1)
);
sparc_ifu_cmp35 milcmp2 (.hit (ifd_ifc_milhit_s[2]),
.a (imiss_paddr_s[39:5]),
.b (mil_entry2[39:5]),
.valid (1'b1)
);
sparc_ifu_cmp35 milcmp3 (.hit (ifd_ifc_milhit_s[3]),
.a (imiss_paddr_s[39:5]),
.b (mil_entry3[39:5]),
.valid (1'b1)
);
// Send replacement way to ctl logic
// assign ifd_ifc_mil_repway_s = {mil_entry3[41:40],
// mil_entry2[41:40],
// mil_entry1[41:40],
// mil_entry0[41:40]};
// calculate tag parity
sparc_ifu_par32 tag_par(.in ({{`ICT_FILL_BITS{1'b0}},
imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),
.out (tag_par_s));
// Missed Instruction List
// 43 - NOT cacheable
// 42 - tag parity
// 41:40 - repl way
// 39:0 - paddr
// Prepare Missed Instruction List entry
assign newmil_entry_s = {tag_par_s,
ifc_ifd_repway_s,
imiss_paddr_s[39:2]};
// ldmil_sel is thr_s[3:0] & imiss_s
// dp_mux2es #(41) milin_mux0(.dout (mil0_in_s),
// .in0 (mil_entry0),
// .in1 (newmil_entry_s),
// .sel (ifc_ifd_ldmil_sel_new[0]));
// dp_mux2es #(41) milin_mux1(.dout (mil1_in_s),
// .in0 (mil_entry1),
// .in1 (newmil_entry_s),
// .sel (ifc_ifd_ldmil_sel_new[1]));
// dp_mux2es #(41) milin_mux2(.dout (mil2_in_s),
// .in0 (mil_entry2),
// .in1 (newmil_entry_s),
// .sel (ifc_ifd_ldmil_sel_new[2]));
// dp_mux2es #(41) milin_mux3(.dout (mil3_in_s),
// .in0 (mil_entry3),
// .in1 (newmil_entry_s),
// .sel (ifc_ifd_ldmil_sel_new[3]));
wire clk_mil0;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenmil0(.rclk (rclk),
.clk (clk_mil0),
.en_l (~ifc_ifd_ldmil_sel_new[0]),
.tm_l (~se));
`endif
wire clk_mil1;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenmil1(.rclk (rclk),
.clk (clk_mil1),
.en_l (~ifc_ifd_ldmil_sel_new[1]),
.tm_l (~se));
`endif
wire clk_mil2;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenmil2(.rclk (rclk),
.clk (clk_mil2),
.en_l (~ifc_ifd_ldmil_sel_new[2]),
.tm_l (~se));
`endif
wire clk_mil3;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenmil3(.rclk (rclk),
.clk (clk_mil3),
.en_l (~ifc_ifd_ldmil_sel_new[3]),
.tm_l (~se));
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(41) mil0(.din (newmil_entry_s),
.en (~(~ifc_ifd_ldmil_sel_new[0])), .clk(rclk),
.q (mil_entry0),
.se (se), .si(), .so());
`else
dff_s #(41) mil0(.din (newmil_entry_s),
.clk (clk_mil0),
.q (mil_entry0),
.se (se), .si(), .so());
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(41) mil1(.din (newmil_entry_s),
.en (~(~ifc_ifd_ldmil_sel_new[1])), .clk(rclk),
.q (mil_entry1),
.se (se), .si(), .so());
`else
dff_s #(41) mil1(.din (newmil_entry_s),
.clk (clk_mil1),
.q (mil_entry1),
.se (se), .si(), .so());
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(41) mil2(.din (newmil_entry_s),
.en (~(~ifc_ifd_ldmil_sel_new[2])), .clk(rclk),
.q (mil_entry2),
.se (se), .si(), .so());
`else
dff_s #(41) mil2(.din (newmil_entry_s),
.clk (clk_mil2),
.q (mil_entry2),
.se (se), .si(), .so());
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(41) mil3(.din (newmil_entry_s),
.en (~(~ifc_ifd_ldmil_sel_new[3])), .clk(rclk),
.q (mil_entry3),
.se (se), .si(), .so());
`else
dff_s #(41) mil3(.din (newmil_entry_s),
.clk (clk_mil3),
.q (mil_entry3),
.se (se), .si(), .so());
`endif
assign ifd_ifc_newdestid_s = {imiss_paddr_s[39],
imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};
assign ifd_ifc_destid0 = {mil_entry0[39],
mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};
assign ifd_ifc_destid1 = {mil_entry1[39],
mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};
assign ifd_ifc_destid2 = {mil_entry2[39],
mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};
assign ifd_ifc_destid3 = {mil_entry3[39],
mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};
assign ifd_ifc_instoffset0 = mil_entry0[3:2];
assign ifd_ifc_instoffset1 = mil_entry1[3:2];
assign ifd_ifc_instoffset2 = mil_entry2[3:2];
assign ifd_ifc_instoffset3 = mil_entry3[3:2];
// MIL Request Out mux
dp_mux4ds #(41) milreq_mux (.dout (mil_pcxreq_d),
.in0 ({mil_entry0[42:2]}),
.in1 ({mil_entry1[42:2]}),
.in2 ({mil_entry2[42:2]}),
.in3 ({mil_entry3[42:2]}),
.sel0_l (ifc_ifd_milreq_sel_d_l[0]),
.sel1_l (ifc_ifd_milreq_sel_d_l[1]),
.sel2_l (ifc_ifd_milreq_sel_d_l[2]),
.sel3_l (ifc_ifd_milreq_sel_d_l[3]));
// Next PCX Request Mux
// dp_mux3ds #(44) nxtpcx_mux (.dout (pcxreq_d),
// .in0 (mil_pcxreq_d),
// .in1 (44'bx),
// .in2 (pcxreq_e),
// .sel0_l (ifc_ifd_nxtpcx_sel_new_d_l),
// .sel1_l (ifc_ifd_nxtpcx_sel_err_d_l),
// .sel2_l (ifc_ifd_nxtpcx_sel_prev_d_l));
// TBD: If destid == any L2 bank, need to zero out bit 4 for Rams
// -- done
assign ifd_ifc_pcxline_d[4:2] = mil_pcxreq_d[4:2];
assign pcxreq_d[42:5] = mil_pcxreq_d[42:5];
assign pcxreq_d[4:2] = ifc_ifd_pcxline_adj_d[4:2];
// assign pcxreq_d[1:0] = mil_pcxreq_d[1:0]; // dont need this
dff_s #(41) pcxreq_reg (.din (pcxreq_d),
.clk (clk),
.q (pcxreq_e),
.se (se), .si(), .so());
// CHANGE to regular dff
// dffe #(44) pcxreq_reg (.din (pcxreq_d),
// .clk (clk),
// .q (pcxreq_e),
// .en (ifc_ifd_nxtpcx_sel_new_d),
// .se (se), .si(), .so());
// PCX Req Reg -- req type is 5 bits
assign ifu_lsu_pcxpkt_e = {ifc_ifd_reqvalid_e, // 51 - valid
ifc_ifd_errinv_e, // 50 - inv all ways
ifc_ifd_uncached_e, // 49 - not cacheable
{`IMISS_RQ}, // 48:44 - req type
pcxreq_e[41:40], // 43:42 - rep way
ifc_ifd_thrid_e[1:0], // 41:40 - thrid
pcxreq_e[39:2], // 39:2 - word address
2'b0}; // force to zero
//----------------------------------------------------------------------
// Fill Return Address
//----------------------------------------------------------------------
// MIL Fill Return Mux
dp_mux4ds #(41) milfill_mux(.dout (fill_addr_i2),
.in0 ( mil_entry0),
.in1 ( mil_entry1),
.in2 ( mil_entry2),
.in3 ( mil_entry3),
.sel0_l (ifc_ifd_milfill_sel_i2_l[0]),
.sel1_l (ifc_ifd_milfill_sel_i2_l[1]),
.sel2_l (ifc_ifd_milfill_sel_i2_l[2]),
.sel3_l (ifc_ifd_milfill_sel_i2_l[3]));
assign ifd_ifc_miladdr4_i2[3:0] = {mil_entry3[4],
mil_entry2[4],
mil_entry1[4],
mil_entry0[4]};
assign ifd_ifc_iobpkt_i2 = fill_addr_i2[39];
assign fill_addr_adj = {fill_addr_i2[42:5],
ifc_ifd_filladdr4_i2,
fill_addr_i2[3:2]};
// determine if this is cacheable in I$
// moved to ifqctl
// assign ifd_ifc_uncached_i2 = fill_addr_i2[43];
// merged with addren mux to save some timing
dp_mux4ds #(41) icadr_mux(.dout (icaddr_i2),
.in0 (fill_addr_adj),
.in1 (asi_addr_i2),
.in2 (bist_addr_i2),
.in3 ({wraddr_f[42:4], 2'b0}),
.sel0_l (ifc_ifd_addr_sel_fill_i2_l),
.sel1_l (ifc_ifd_addr_sel_asi_i2_l),
.sel2_l (ifc_ifd_addr_sel_bist_i2_l),
.sel3_l (ifc_ifd_addr_sel_old_i2_l));
// way, 32B line sel
assign ifd_inv_wrway_i2 = icaddr_i2[41:40];
// dp_mux2es #(39) addren_mux(.dout (wraddr_i2),
// .in0 (wraddr_f),
// .in1 (icaddr_i2[42:4]),
// .sel (ifc_ifd_ifqadv_i2));
dff_s #(39) wraddr_reg(.din (icaddr_i2[42:4]),
.clk (clk),
.q (wraddr_f[42:4]),
.se (se), .si(), .so());
// tag = parity bit + `IC_TAG_SZ bits of address
assign ifq_erb_wrindex_f = wraddr_f[`IC_IDX_HI:4];
assign ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};
assign ifq_icd_index_bf = icaddr_i2[`IC_IDX_HI:2];
assign ifq_icd_wrway_bf = icaddr_i2[41:40];
//----------------------------------------------------------------------
// Fill Return Data
//----------------------------------------------------------------------
// IFQ-IBUF
// inq is the same size as the cpx_width
// inq is replaced with a single flop, ibuf
// ibuf enable mux
// dp_mux2es #(`CPX_WIDTH) ifqen_mux(.dout (inq_cpxpkt_nxt),
// .in0 (inq_cpxpkt_i1),
// .in1 (lsu_ifu_cpxpkt_i1),
// .sel (ifc_ifd_ld_inq_i1));
wire clk_ibuf1;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenibuf(.rclk (rclk),
.clk (clk_ibuf1),
.en_l (~ifc_ifd_ld_inq_i1),
.tm_l (~se));
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
.q (inq_cpxpkt_i1),
.en (~(~ifc_ifd_ld_inq_i1)), .clk(rclk),
.se (se), .si(), .so());
`else
dff_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
.q (inq_cpxpkt_i1),
.clk (clk_ibuf1),
.se (se), .si(), .so());
`endif
assign ifd_ifc_cpxreq_i1 = {inq_cpxpkt_i1[`CPX_VLD],
inq_cpxpkt_i1[`CPX_REQFIELD]};
// ifq operand bypass mux
// fill pkt is 128d+2w+2t+3iw+1v+1nc+4r = 140
dp_mux4ds #(`CPX_WIDTH) ifq_bypmux(.dout (ifqop_i1),
.in0 (fwd_data_pkt),
.in1 (inq_cpxpkt_i1),
.in2 (stxa_data_pkt),
.in3 (lsu_ifu_cpxpkt_i1),
.sel0_l (ifc_ifd_ifqbyp_sel_fwd_l),
.sel1_l (ifc_ifd_ifqbyp_sel_inq_l),
.sel2_l (ifc_ifd_ifqbyp_sel_asi_l),
.sel3_l (ifc_ifd_ifqbyp_sel_lsu_l));
wire clk_ifqop;
`ifdef FPGA_SYN_CLK_EN
`else
bw_u1_ckenbuf_6x ckenifop(.rclk (rclk),
.clk (clk_ifqop),
.en_l (ifc_ifd_ifqbyp_en_l),
.tm_l (~se));
`endif
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(`CPX_WIDTH) ifqop_reg(.din (ifqop_i1),
.q (ifqop_i2),
.en (~(ifc_ifd_ifqbyp_en_l)), .clk(rclk),
.se (se), .si(), .so());
`else
dff_s #(`CPX_WIDTH) ifqop_reg(.din (ifqop_i1),
.q (ifqop_i2),
.clk (clk_ifqop),
.se (se), .si(), .so());
`endif
assign ifd_inv_ifqop_i2 = ifqop_i2;
// switch condition pre decode
sparc_ifu_swpla swpla0(.in (ifqop_i2[31:0]),
.out (swc_i2[0]));
sparc_ifu_swpla swpla1(.in (ifqop_i2[63:32]),
.out (swc_i2[1]));
sparc_ifu_swpla swpla2(.in (ifqop_i2[95:64]),
.out (swc_i2[2]));
sparc_ifu_swpla swpla3(.in (ifqop_i2[127:96]),
.out (swc_i2[3]));
// Add Parity to each inst.
sparc_ifu_par32 par0(.in (ifqop_i2[31:0]),
.out (par_i2[0]));
sparc_ifu_par32 par1(.in (ifqop_i2[63:32]),
.out (par_i2[1]));
sparc_ifu_par32 par2(.in (ifqop_i2[95:64]),
.out (par_i2[2]));
sparc_ifu_par32 par3(.in (ifqop_i2[127:96]),
.out (par_i2[3]));
// add 8 xor gates in the dp
// assign parity_i2 = par_i2 ^ swc_i2 ^ {4{ifc_ifd_insert_pe}};
// assign tag_par_i2 = par_i2[0] ^ ifc_ifd_insert_pe;
// Make the par32 cell above, par33 and include cpxue_i2
assign parity_i2 = par_i2 ^ swc_i2 ^ {4{ifd_ifc_cpxue_i2}};
assign tag_par_i2 = par_i2[0] ^ ifd_ifc_cpxue_i2;
// parity, swc, inst[31:0]
assign icdata_i2 = {parity_i2[3], ifqop_i2[127:96], swc_i2[3],
parity_i2[2], ifqop_i2[95:64], swc_i2[2],
parity_i2[1], ifqop_i2[63:32], swc_i2[1],
parity_i2[0], ifqop_i2[31:0], swc_i2[0]};
// write data to icache
assign ifq_icd_wrdata_i2 = icdata_i2;
// very critical
assign ifd_ifc_cpxreq_nxt = ifqop_i1[`CPX_REQFIELD];
assign ifd_ifc_cpxthr_nxt = ifqop_i1[`CPX_THRFIELD];
assign ifd_ifc_cpxvld_i2 = ifqop_i2[`CPX_VLD];
assign ifd_ifc_4bpkt_i2 = ifqop_i2[`CPX_IF4B];
assign ifd_ifc_cpxce_i2 = ifqop_i2[`CPX_ERR_LO];
assign ifd_ifc_cpxue_i2 = ifqop_i2[(`CPX_ERR_LO + 1)];
assign ifd_ifc_cpxms_i2 = ifqop_i2[(`CPX_ERR_LO + 2)];
assign ifd_ifc_cpxnc_i2 = ifqop_i2[`CPX_NC];
assign ifd_ifc_fwd2ic_i2 = ifqop_i2[103];
// instr sel mux to write to thread inst regsiter in S stage
// instr is always BIG ENDIAN
dp_mux4ds #(33) fillinst_mux(.dout (ifq_fdp_fill_inst),
.in0 (icdata_i2[134:102]),
.in1 (icdata_i2[100:68]),
.in2 (icdata_i2[66:34]),
.in3 (icdata_i2[32:0]),
.sel0_l (ifc_ifd_finst_sel_l[0]),
.sel1_l (ifc_ifd_finst_sel_l[1]),
.sel2_l (ifc_ifd_finst_sel_l[2]),
.sel3_l (ifc_ifd_finst_sel_l[3]));
// synopsys translate_off
//`ifdef DEFINE_0IN
//`else
// always @ (ifq_fdp_fill_inst or ifd_ifc_cpxreq_i2)
// if (((^ifq_fdp_fill_inst[32:0]) == 1'bx) && (ifd_ifc_cpxreq_i2 == `CPX_IFILLPKT))
// begin
// $display("ifqdp.v: Imiss Return val = %h\n", ifqop_i2);
// $error("IFQCPX", "Error: X's detected in Imiss Return Inst %h",
// ifq_fdp_fill_inst[31:0]);
// end
//`endif
// synopsys translate_on
// TBD: 1. inv way in fill pkt -- DONE
// 2. inv packet -- DONE
// 3. DFT pkt from TAP -- NO NEED
// 4. Ld pkt to invalidate i$ -- DONE
//----------------------------------------------------------------------
// ASI Access
//----------------------------------------------------------------------
// mux stxa pkt into the cpx
assign stxa_data_pkt[`CPX_VLD] = 1'b0;
// vbits and parity are muxed into the cpxreq
assign stxa_data_pkt[`CPX_REQFIELD] = {1'b1, lsu_ifu_stxa_data[34:32]};
// assign stxa_data_pkt[`CPX_THRFIELD] = lsu_ifu_asi_thrid[1:0];
assign stxa_data_pkt[`CPX_THRFIELD] = 2'b0;
// use parity to insert error in icache inst or tag
assign stxa_data_pkt[(`CPX_ERR_LO + 1)] = lsu_ifu_stxa_data[32];
assign stxa_data_pkt[127:0] = {4{lsu_ifu_stxa_data[31:0]}};
// other bits need to be tied off
assign stxa_data_pkt[133:128] = 6'b0;
assign stxa_data_pkt[137:136] = 2'b0;
assign stxa_data_pkt[139] = 1'b0;
// format fwd data pkt in a similar way
assign fwd_data_pkt[`CPX_VLD:(`CPX_ERR_LO + 2)] = ifqop_i2[`CPX_VLD:(`CPX_ERR_LO + 2)];
assign fwd_data_pkt[(`CPX_ERR_LO + 1)] = ifqop_i2[32];
assign fwd_data_pkt[`CPX_ERR_LO:128] = ifqop_i2[`CPX_ERR_LO:128];
assign fwd_data_pkt[127:0] = {4{ifqop_i2[31:0]}};
dff_s #(16) stxa_ff(.din (lsu_ifu_stxa_data[47:32]),
.q (ifq_erb_asidata_i2[47:32]),
.clk (clk), .se(se), .si(), .so());
assign ifq_erb_asidata_i2[31:0] = ifqop_i2[31:0];
// va[63:32] is truncated
// In this architecture we only need va[17:0]
// rest of the bits ar ehere only for the address range check
// 12 new muxes (10 for addr, 2 for way)
// CHANGE: this mux has been moved before the asi_addr_reg, rather
// than after.
// Use mux flop soffm2?
dp_mux2es #(12) asifwd_mx(.dout (asi_fwd_index[13:2]),
.in0 ({lsu_ifu_asi_addr[17:16], // asi way
lsu_ifu_asi_addr[12:3]}), // asi addr
.in1 ({ifqop_i2[81:80], // fwd rq way
ifqop_i2[76:67]}), // fwd rq addr
.sel (ifc_ifd_idx_sel_fwd_i2));
assign asi_va_i1 = {asi_fwd_index[13:12],
lsu_ifu_asi_addr[15:13],
asi_fwd_index[11:2],
lsu_ifu_asi_addr[2:0]};
dff_s #(18) asi_addr_reg(.din (asi_va_i1[17:0]), // 15:13 is not used
.q (asi_va_i2[17:0]),
.clk (clk),
.se (se), .si(), .so());
// 16b zero cmp: leave out bit 3!! (imask is 0x8)
assign ifd_ifc_asi_vachklo_i2 = (|asi_va_i2[16:4]) | (|asi_va_i2[2:0]);
// mux in ifqop and asi_va_i2 to create new asi va?
// asi va is shifted by 1 bit to look like 64b op
assign ifd_ifc_asiaddr_i2[3:2] = asi_va_i2[4:3];
assign asi_addr_i2 = {tag_par_i2, // tag parity 42
asi_va_i2[17:16], // way 41:40
ifqop_i2[27:0], // tag 39:12
asi_va_i2[12:3] // index 11:2
};
// bist has to go to icache in the same cycle
// cannot flop it
assign bist_addr_i2 = {1'b0, // par
mbist_icache_way[1:0], // way 41:40
28'b0, // tag 39:12
mbist_icache_index[7:0], // index 11:4
mbist_icache_word, // 3
1'b0
};
// floating signals
sink #(2) s0(.in (imiss_paddr_s[1:0]));
sink s1(.in (pcxreq_e[42]));
sink s2(.in (fill_addr_i2[4]));
endmodule // sparc_ifu_ifqdp
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_SYMBOL_V
`define SKY130_FD_SC_LP__NOR3B_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_1_V
`define SKY130_FD_SC_MS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211a (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
|
`timescale 1ns / 1ps
/*
Group Members: Thomas Hudson and Warren Seto
Lab Name: Combinational Logic
Project Name: eng312_proj2
Design Name: mux_four_to_one_test.v
Design Description: Verilog Test Fixture for a Four to One Multiplexer
*/
module mux_four_to_one_test;
// Inputs
reg [3:0] DIN;
reg [1:0] SEL;
// Outputs
wire DOUT;
// Instantiate two counter variables for both loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
mux_four_to_one uut
(
.DIN(DIN),
.SEL(SEL),
.DOUT(DOUT)
);
initial begin
// Initialize Inputs
DIN = 0;
SEL = 0;
// Initialize counter variables
count = 0;
count2 = 0;
// Loops over the possible combinations for SEL and resets the value for DIN
for (count = 0; count < 4; count = count + 1) begin
SEL = count;
DIN = 0;
// Loops over the possible combinations for DIN for each SEL value
for (count2 = 0; count2 <= 16; count2 = count2 + 1) begin
#5 DIN = count2;
end
end
end
initial #340 $finish; // The test will run for a total interval of 340 nanoseconds
endmodule
|
module microc(input wire clk, reset, s_inc, s_inm, we3, s_es, s_rel, swe, s_ret, input wire [2:0] op, input wire [7:0] data_in,
output wire z, output wire [5:0] opcode, output wire [7:0] data_mem, data_reg, output wire [1:0] id_in, id_out); //Es necesario añadir nuevas señales de control
//Cables
wire [9:0] mux1_pc;
wire [9:0] pc_memprog; //tambien va a sum
wire [9:0] sum_mux1;
wire [15:0] memprog; // va a los 2 multiplexores y al banco de registros
wire [7:0] rd1,rd2,wd3;
wire [7:0] alu_mux2;
wire zero;
//Nuevos cables de E/S
wire [7:0] mux2_out;
//Nuevos cables adicionales
wire [9:0] mux4_sum, sub_mux5, mux5_pc, mux_subreg;
//Cables VGA
wire [3:0] num;
wire [15:0] num_vga;
// reg [9:0] DataR;
// reg Push, Pop, Reset;
// wire Full, Empty, Err;
// wire [1:0] SP;
/*
continuous assignment of DataIO to
DataR register, with delay 0 *
*/
// wire [9:0] #(0) DataIO = DataR;
//Enviar opcode a la UC
assign opcode = memprog[5:0];
//Asignaciones de la E/S
assign data_mem = memprog[11:4];
assign data_reg = rd1;
assign id_out = memprog[15:14];
assign id_in = memprog[5:4];
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Creación de instancias
mux1 #(10) mux1_(memprog[15:6], sum_mux1, s_inc, mux1_pc);
registro #(10) PC_(clk, reset, mux5_pc, pc_memprog);
sum sumador_(mux4_sum, pc_memprog, sum_mux1);
memprog memoria_(clk, pc_memprog, memprog);
regfile banco_(clk, we3, memprog[7:4], memprog[11:8], memprog[15:12], wd3, rd1, rd2);
alu alu_(rd1, rd2, op, alu_mux2, zero);
mux2 #(8) mux2_(alu_mux2, memprog[11:4], s_inm, mux2_out); //cambiar salida wd3 por mux2_out
registro #(1) ffzero(clk, reset, zero, z);
//EntradaSalida
mux2 #(8) mux3_(mux2_out,data_in,s_es,wd3);
//Adicionales
mux1 #(10) mux4_(1, memprog[15:6], s_rel, mux4_sum);
retorno_reg #(10) sub_reg(swe, reset, mux_subreg, sub_mux5);
// retorno_reg #(10) sub_reg(push, pop, reset, mux_subreg, sub_mux5);
//stack stack_(mux_subreg, reset, swe, s_ret, SP, full, empty, err);
mux1 #(10) mux5_(mux1_pc, sub_mux5, s_ret, mux5_pc);
// mux1 #(10) mux5_(mux1_pc, DataR, s_ret, mux5_pc);
sum sumador2(1, pc_memprog, mux_subreg);
//Controlar VGA
//regtovga regtovga_(clk, vgae2, rd1, num);
//memvga memvga_(clk, s42[4:0], e4);
//printvga printvga_(clk, reset, vgae2, num_vga, vgax, vgay, vgaw);
endmodule |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
`ifdef MODEL_TECH
`mti_v2k_int_delays_on
`endif
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEIIILS_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONEIIILS_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONEIIILS_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cycloneiiils_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEIIILS_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneiiils_mux21
module cycloneiiils_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneiiils_mux41
module cycloneiiils_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneiiils_and1
module cycloneiiils_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneiiils_and16
module cycloneiiils_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneiiils_bmux21
module cycloneiiils_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneiiils_b17mux21
module cycloneiiils_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneiiils_nmux21
module cycloneiiils_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneiiils_b5mux21
module cycloneiiils_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** cycloneiiils_latch
module cycloneiiils_latch(D, ENA, PRE, CLR, Q);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup (D, negedge ENA, 0) ;
$hold (negedge ENA, D, 0) ;
(D => Q) = (0, 0);
(negedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
(negedge CLR => (Q +: q_out)) = (0, 0);
endspecify
wire D_in;
wire ENA_in;
wire PRE_in;
wire CLR_in;
buf (D_in, D);
buf (ENA_in, ENA);
buf (PRE_in, PRE);
buf (CLR_in, CLR);
initial
begin
q_out <= 1'b0;
end
always @(D_in or ENA_in or PRE_in or CLR_in)
begin
if (PRE_in == 1'b0)
begin
// latch being preset, preset is active low
q_out <= 1'b1;
end
else if (CLR_in == 1'b0)
begin
// latch being cleared, clear is active low
q_out <= 1'b0;
end
else if (ENA_in == 1'b1)
begin
// latch is transparent
q_out <= D_in;
end
end
and (Q, q_out, 1'b1);
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiiils_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneiiils_routing_wire
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiiils_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CYCLONEIIILS PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiiils_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneiiils_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiiils_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CYCLONEIIILS PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiiils_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneiiils_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiiils_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0-C9
// output counters of the CYCLONEIIILS PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneiiils_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneiiils_scale_cntr
//BEGIN MF PORTING DELETE
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiiils_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneiiils_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneiiils_pll_reg
//END MF PORTING DELETE
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiiils_pll
//
// Description : Timing simulation model for the Cyclone III LS PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
// New Features : The list below outlines key new features in CYCLONEIIILS:
// 1. Dynamic Phase Reconfiguration
// 2. Dynamic PLL Reconfiguration (different protocol)
// 3. More output counters
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneiiils_pll (inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange
);
parameter operation_mode = "normal";
parameter pll_type = "auto"; // auto,fast(left_right),enhanced(top_bottom)
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0; // 0 .. 4095
parameter lock_low = 0; // 0 .. 7
parameter lock_window_ui = "0.05"; // "0.05", "0.1", "0.15", "0.2"
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1; // 1 .. 2
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; // "1.0", "2.0", "4.0", "6.0", "8.0", "12.0", "16.0", "20.0"
parameter loop_filter_c = 0; // 0 , 2 , 4
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneiiils_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter lock_c = 4;
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk3_phase_shift_num = 0;
parameter clk4_phase_shift_num = 0;
parameter family_name = "Cyclone III LS";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
// TEST ONLY
parameter init_block_reset_a_count = 1;
parameter init_block_reset_b_count = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter phase_counter_select_width = 3;
parameter lock_window = 5;
parameter inclk0_freq = inclk0_input_frequency;
parameter inclk1_freq = inclk1_input_frequency;
parameter charge_pump_current_bits = 0;
parameter lock_window_ui_bits = 0;
parameter loop_filter_c_bits = 0;
parameter loop_filter_r_bits = 0;
parameter test_counter_c0_delay_chain_bits = 0;
parameter test_counter_c1_delay_chain_bits = 0;
parameter test_counter_c2_delay_chain_bits = 0;
parameter test_counter_c3_delay_chain_bits = 0;
parameter test_counter_c4_delay_chain_bits = 0;
parameter test_counter_c5_delay_chain_bits = 0;
parameter test_counter_m_delay_chain_bits = 0;
parameter test_counter_n_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter test_input_comp_delay_chain_bits = 0;
parameter test_volt_reg_output_mode_bits = 0;
parameter test_volt_reg_output_voltage_bits = 0;
parameter test_volt_reg_test_mode = "false";
parameter vco_range_detector_high_bits = -1;
parameter vco_range_detector_low_bits = -1;
parameter scan_chain_mif_file = "";
parameter auto_settings = "true";
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
// OUTPUT PORTS
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
// TIMING CHECKS
specify
$setuphold(negedge scanclk, scandata, 0, 0);
$setuphold(negedge scanclk, scanclkena, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
reg [8*6:1] clk_num[0:4];
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
reg switch_clock;
reg [31:0] real_lock_high;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg locked_tmp;
reg areset_last_value;
reg pfdena_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
// Test bypass lock detect
reg pfd_locked;
integer cycles_pfd_low, cycles_pfd_high;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:9];
reg [31:0] c_low_val[0:9];
reg [8*6:1] c_mode_val[0:9];
reg [31:0] c_initial_val[0:9];
integer c_ph_val[0:9];
reg [31:0] c_val; // placeholder for c_high,c_low values
// VCO Frequency Range control
reg vco_over, vco_under;
// temporary registers for reprogramming
integer c_ph_val_tmp[0:9];
reg [31:0] c_high_val_tmp[0:9];
reg [31:0] c_hval[0:9];
reg [31:0] c_low_val_tmp[0:9];
reg [31:0] c_lval[0:9];
reg [8*6:1] c_mode_val_tmp[0:9];
// hold registers for reprogramming
integer c_ph_val_hold[0:9];
reg [31:0] c_high_val_hold[0:9];
reg [31:0] c_low_val_hold[0:9];
reg [8*6:1] c_mode_val_hold[0:9];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:9];
reg [31:0] c_low_val_old[0:9];
reg [8*6:1] c_mode_val_old[0:9];
integer c_ph_val_old[0:9];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
integer vco_cur;
integer vco_old;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [1:2] lfc_val_bit_setting, lfc_val_old_bit_setting;
reg vco_val_bit_setting, vco_val_old_bit_setting;
reg [3:7] lfr_val_bit_setting, lfr_val_old_bit_setting;
reg [14:16] cp_curr_bit_setting, cp_curr_old_bit_setting;
// Setting on - display real values
// Setting off - display only bits
reg pll_reconfig_display_full_setting;
reg [7:0] m_hi;
reg [7:0] m_lo;
reg [7:0] n_hi;
reg [7:0] n_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:9];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg inclk_man;
reg inclk_es;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c0_from_vco;
wire inclk_c1_from_vco;
wire inclk_c2_from_vco;
wire inclk_c3_from_vco;
wire inclk_c4_from_vco;
wire inclk_m_from_vco;
wire inclk_m;
wire pfdena_wire;
wire [4:0] clk_tmp, clk_out_pfd;
wire [4:0] clk_out;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
reg first_schedule;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// Self Reset
wire reset_self;
// Clock Switchover
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandata_in, scandata_out; // hold scan data in negative-edge triggered ff (on either side on chain)
reg scandone_tmp;
reg initiate_reconfig;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
wire update_conf_latches;
reg update_conf_latches_reg;
reg [-1:142] scan_data;
reg scanclkena_reg; // register scanclkena on negative edge of scanclk
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// Phase reconfig
reg [2:0] phasecounterselect_reg;
reg phaseupdown_reg;
reg phasestep_reg;
integer select_counter;
integer phasestep_high_count;
reg update_phase;
// LOCAL_PARAMETERS_BEGIN
parameter SCAN_CHAIN = 144;
parameter GPP_SCAN_CHAIN = 234;
parameter FAST_SCAN_CHAIN = 180;
// primary clk is always inclk0
parameter num_phase_taps = 8;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_clk6_mult_by;
integer i_clk6_div_by;
integer i_clk7_mult_by;
integer i_clk7_div_by;
integer i_clk8_mult_by;
integer i_clk8_div_by;
integer i_clk9_mult_by;
integer i_clk9_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
integer i_clk3_phase_shift;
integer i_clk4_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_c_high[0:9];
integer i_c_low[0:9];
integer i_c_initial[0:9];
integer i_c_ph[0:9];
reg [8*6:1] i_c_mode[0:9];
integer i_vco_min;
integer i_vco_max;
integer i_vco_min_no_division;
integer i_vco_max_no_division;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_has_just_been_reconfigured;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_vco_frequency_control;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_self_reset_on_loss_lock;
integer current_clock;
integer current_clock_man;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg init;
reg tap0_is_active;
real inclk0_period, last_inclk0_period,inclk1_period, last_inclk1_period;
real last_inclk0_edge,last_inclk1_edge,diff_percent_period;
reg first_inclk0_edge_detect,first_inclk1_edge_detect;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = (numerator == 0) ? 1 : numerator;
den = (denominator == 0) ? 1 : denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
fraction_num = m_value;
fraction_div = d_value;
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, C6, C6_mode, C7, C7_mode, C8, C8_mode, C9, C9_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5, C6, C7, C8, C9;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode, C6_mode, C7_mode, C8_mode, C9_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if (C6 > max_modulus && C6_mode != "bypass" && C6_mode != " off")
max_modulus = C6;
if (C7 > max_modulus && C7_mode != "bypass" && C7_mode != " off")
max_modulus = C7;
if (C8 > max_modulus && C8_mode != "bypass" && C8_mode != " off")
max_modulus = C8;
if (C9 > max_modulus && C9_mode != "bypass" && C9_mode != " off")
max_modulus = C9;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the M and N values for Manual phase based on the following 5 criterias:
// 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
// 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
// 3. M is less than 512
// 4. N is less than 512
// 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
// of the desired vco-phase-shift-step
task find_m_and_n_4_manual_phase;
input inclock_period;
input vco_phase_shift_step;
input clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
input clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
input clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
input clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
input clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
input clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
output m;
output n;
parameter max_m = 511;
parameter max_n = 511;
parameter max_pfd = 720;
parameter min_pfd = 5;
parameter max_vco = 1600; // max vco frequency. (in mHz)
parameter min_vco = 300; // min vco frequency. (in mHz)
parameter max_offset = 0.004;
reg[160:1] clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
reg[160:1] clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
integer inclock_period;
integer vco_phase_shift_step;
integer clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
integer clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
integer clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
integer clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
integer m;
integer n;
integer pre_m;
integer pre_n;
integer m_out;
integer n_out;
integer closest_vco_step_value;
integer vco_period;
integer pfd_freq;
integer vco_freq;
integer vco_ps_step_value;
real clk0_div_factor_real;
real clk1_div_factor_real;
real clk2_div_factor_real;
real clk3_div_factor_real;
real clk4_div_factor_real;
real clk5_div_factor_real;
real clk6_div_factor_real;
real clk7_div_factor_real;
real clk8_div_factor_real;
real clk9_div_factor_real;
real clk0_div_factor_diff;
real clk1_div_factor_diff;
real clk2_div_factor_diff;
real clk3_div_factor_diff;
real clk4_div_factor_diff;
real clk5_div_factor_diff;
real clk6_div_factor_diff;
real clk7_div_factor_diff;
real clk8_div_factor_diff;
real clk9_div_factor_diff;
integer clk0_div_factor_int;
integer clk1_div_factor_int;
integer clk2_div_factor_int;
integer clk3_div_factor_int;
integer clk4_div_factor_int;
integer clk5_div_factor_int;
integer clk6_div_factor_int;
integer clk7_div_factor_int;
integer clk8_div_factor_int;
integer clk9_div_factor_int;
begin
vco_period = vco_phase_shift_step * 8;
pre_m = 0;
pre_n = 0;
closest_vco_step_value = 0;
begin : LOOP_1
for (n_out = 1; n_out < max_n; n_out = n_out +1)
begin
for (m_out = 1; m_out < max_m; m_out = m_out +1)
begin
clk0_div_factor_real = (clk0_div * m_out * 1.0 ) / (clk0_mult * n_out);
clk1_div_factor_real = (clk1_div * m_out * 1.0) / (clk1_mult * n_out);
clk2_div_factor_real = (clk2_div * m_out * 1.0) / (clk2_mult * n_out);
clk3_div_factor_real = (clk3_div * m_out * 1.0) / (clk3_mult * n_out);
clk4_div_factor_real = (clk4_div * m_out * 1.0) / (clk4_mult * n_out);
clk5_div_factor_real = (clk5_div * m_out * 1.0) / (clk5_mult * n_out);
clk6_div_factor_real = (clk6_div * m_out * 1.0) / (clk6_mult * n_out);
clk7_div_factor_real = (clk7_div * m_out * 1.0) / (clk7_mult * n_out);
clk8_div_factor_real = (clk8_div * m_out * 1.0) / (clk8_mult * n_out);
clk9_div_factor_real = (clk9_div * m_out * 1.0) / (clk9_mult * n_out);
clk0_div_factor_int = clk0_div_factor_real;
clk1_div_factor_int = clk1_div_factor_real;
clk2_div_factor_int = clk2_div_factor_real;
clk3_div_factor_int = clk3_div_factor_real;
clk4_div_factor_int = clk4_div_factor_real;
clk5_div_factor_int = clk5_div_factor_real;
clk6_div_factor_int = clk6_div_factor_real;
clk7_div_factor_int = clk7_div_factor_real;
clk8_div_factor_int = clk8_div_factor_real;
clk9_div_factor_int = clk9_div_factor_real;
clk0_div_factor_diff = (clk0_div_factor_real - clk0_div_factor_int < 0) ? (clk0_div_factor_real - clk0_div_factor_int) * -1.0 : clk0_div_factor_real - clk0_div_factor_int;
clk1_div_factor_diff = (clk1_div_factor_real - clk1_div_factor_int < 0) ? (clk1_div_factor_real - clk1_div_factor_int) * -1.0 : clk1_div_factor_real - clk1_div_factor_int;
clk2_div_factor_diff = (clk2_div_factor_real - clk2_div_factor_int < 0) ? (clk2_div_factor_real - clk2_div_factor_int) * -1.0 : clk2_div_factor_real - clk2_div_factor_int;
clk3_div_factor_diff = (clk3_div_factor_real - clk3_div_factor_int < 0) ? (clk3_div_factor_real - clk3_div_factor_int) * -1.0 : clk3_div_factor_real - clk3_div_factor_int;
clk4_div_factor_diff = (clk4_div_factor_real - clk4_div_factor_int < 0) ? (clk4_div_factor_real - clk4_div_factor_int) * -1.0 : clk4_div_factor_real - clk4_div_factor_int;
clk5_div_factor_diff = (clk5_div_factor_real - clk5_div_factor_int < 0) ? (clk5_div_factor_real - clk5_div_factor_int) * -1.0 : clk5_div_factor_real - clk5_div_factor_int;
clk6_div_factor_diff = (clk6_div_factor_real - clk6_div_factor_int < 0) ? (clk6_div_factor_real - clk6_div_factor_int) * -1.0 : clk6_div_factor_real - clk6_div_factor_int;
clk7_div_factor_diff = (clk7_div_factor_real - clk7_div_factor_int < 0) ? (clk7_div_factor_real - clk7_div_factor_int) * -1.0 : clk7_div_factor_real - clk7_div_factor_int;
clk8_div_factor_diff = (clk8_div_factor_real - clk8_div_factor_int < 0) ? (clk8_div_factor_real - clk8_div_factor_int) * -1.0 : clk8_div_factor_real - clk8_div_factor_int;
clk9_div_factor_diff = (clk9_div_factor_real - clk9_div_factor_int < 0) ? (clk9_div_factor_real - clk9_div_factor_int) * -1.0 : clk9_div_factor_real - clk9_div_factor_int;
if (((clk0_div_factor_diff < max_offset) || (clk0_used == "unused")) &&
((clk1_div_factor_diff < max_offset) || (clk1_used == "unused")) &&
((clk2_div_factor_diff < max_offset) || (clk2_used == "unused")) &&
((clk3_div_factor_diff < max_offset) || (clk3_used == "unused")) &&
((clk4_div_factor_diff < max_offset) || (clk4_used == "unused")) &&
((clk5_div_factor_diff < max_offset) || (clk5_used == "unused")) &&
((clk6_div_factor_diff < max_offset) || (clk6_used == "unused")) &&
((clk7_div_factor_diff < max_offset) || (clk7_used == "unused")) &&
((clk8_div_factor_diff < max_offset) || (clk8_used == "unused")) &&
((clk9_div_factor_diff < max_offset) || (clk9_used == "unused")) )
begin
if ((m_out != 0) && (n_out != 0))
begin
pfd_freq = 1000000 / (inclock_period * n_out);
vco_freq = (1000000 * m_out) / (inclock_period * n_out);
vco_ps_step_value = (inclock_period * n_out) / (8 * m_out);
if ( (m_out < max_m) && (n_out < max_n) && (pfd_freq >= min_pfd) && (pfd_freq <= max_pfd) &&
(vco_freq >= min_vco) && (vco_freq <= max_vco) )
begin
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
begin
pre_m = m_out;
pre_n = n_out;
disable LOOP_1;
end
else
begin
if ((closest_vco_step_value == 0) || (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
begin
pre_m = m_out;
pre_n = n_out;
closest_vco_step_value = vco_ps_step_value;
end
end
end
end
end
end
end
end
if ((pre_m != 0) && (pre_n != 0))
begin
find_simple_integer_fraction(pre_m, pre_n,
max_n, m, n);
end
else
begin
n = 1;
m = lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end
end
endtask // find_m_and_n_4_manual_phase
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
real r;
integer r_int;
begin
r = (clk_divide * M * 1.0)/(clk_mult * N);
r_int = r;
output_counter_value = r_int;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360.0 * n)) + 0.6;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45.0;
if (counter_ph == 8)
counter_ph = 0;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneiiils lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_freq;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
scandata_out = 1'b0;
first_inclk0_edge_detect = 1'b0;
first_inclk1_edge_detect = 1'b0;
pll_reconfig_display_full_setting = 1'b0;
initiate_reconfig = 1'b0;
switch_over_count = 0;
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_compensate_clock = alpha_tolower(compensate_clock);
l_switch_over_type = alpha_tolower(switch_over_type);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_vco_frequency_control = alpha_tolower(vco_frequency_control);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_self_reset_on_loss_lock = alpha_tolower(self_reset_on_loss_lock);
real_lock_high = (l_sim_gate_lock_device_behavior == "on") ? lock_high : 0;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 0;
loop_filter_c_arr[1] = 0;
loop_filter_c_arr[2] = 0;
loop_filter_c_arr[3] = 0;
fpll_loop_filter_c_arr[0] = 0;
fpll_loop_filter_c_arr[1] = 0;
fpll_loop_filter_c_arr[2] = 0;
fpll_loop_filter_c_arr[3] = 0;
charge_pump_curr_arr[0] = 0;
charge_pump_curr_arr[1] = 0;
charge_pump_curr_arr[2] = 0;
charge_pump_curr_arr[3] = 0;
charge_pump_curr_arr[4] = 0;
charge_pump_curr_arr[5] = 0;
charge_pump_curr_arr[6] = 0;
charge_pump_curr_arr[7] = 0;
charge_pump_curr_arr[8] = 0;
charge_pump_curr_arr[9] = 0;
charge_pump_curr_arr[10] = 0;
charge_pump_curr_arr[11] = 0;
charge_pump_curr_arr[12] = 0;
charge_pump_curr_arr[13] = 0;
charge_pump_curr_arr[14] = 0;
charge_pump_curr_arr[15] = 0;
i_vco_max = vco_max;
i_vco_min = vco_min;
if(vco_post_scale == 1)
begin
i_vco_max_no_division = vco_max * 2;
i_vco_min_no_division = vco_min * 2;
end
else
begin
i_vco_max_no_division = vco_max;
i_vco_min_no_division = vco_min;
end
if (m == 0)
begin
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
// convert user parameters to advanced
if (l_vco_frequency_control == "manual_phase")
begin
find_m_and_n_4_manual_phase(inclk0_freq, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,i_clk4_div_by,
1, 1, 1, 1, 1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,clk4_counter,
"unused", "unused", "unused", "unused", "unused",
i_m, i_n);
end
else if (((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
if (((l_pll_type == "fast") || (l_pll_type == "left_right")) && (l_compensate_clock == "lvdsclk"))
i_m = i_clk0_mult_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
inclk0_freq);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
i_clk3_phase_shift = 0;
i_clk4_phase_shift = 0;
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
i_clk3_phase_shift = get_int_phase_shift(clk3_phase_shift, clk3_phase_shift_num);
i_clk4_phase_shift = get_int_phase_shift(clk4_phase_shift, clk4_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
i_clk3_phase_shift,
i_clk4_phase_shift,
0,
0,
0,
0,
0
);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(i_clk3_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(i_clk4_phase_shift, max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle,output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(i_clk3_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(i_clk4_phase_shift,max_neg_abs)), i_m, i_n);
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
switch_clock = 1'b0;
refclk_period = inclk0_freq * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
inclk_es = 0;
inclk_man = 0;
cycle_to_adjust = 0;
m_delay = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
inclk_out_of_range = 0;
scandone_tmp = 1'b0;
schedule_vco_last_value = 0;
scan_chain_length = SCAN_CHAIN;
num_output_cntrs = 5;
phasestep_high_count = 0;
update_phase = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 10; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_hval[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
c_lval[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
vco_cur = vco_post_scale;
i = 0;
j = 0;
inclk_last_value = 0;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
current_clock = 0;
current_clock_man = 0;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast" || (l_pll_type == "left_right"))
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch === 1'b1)
begin
current_clock_man = 1;
active_clock = 1;
end
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
c_high_val[6]+c_low_val[6], c_mode_val[6],
c_high_val[7]+c_low_val[7], c_mode_val[7],
c_high_val[8]+c_low_val[8], c_mode_val[8],
c_high_val[9]+c_low_val[9], c_mode_val[9],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
vco_over = 1'b0;
vco_under = 1'b0;
// Initialize the scan chain
// LF unused : bit 1
scan_data[-1:0] = 2'b00;
// LF Capacitance : bits 1,2 : all values are legal
scan_data[1:2] = loop_filter_c_bits;
// LF Resistance : bits 3-7
scan_data[3:7] = loop_filter_r_bits;
// VCO post scale
if(vco_post_scale == 1)
begin
scan_data[8] = 1'b1;
vco_val_old_bit_setting = 1'b1;
end
else
begin
scan_data[8] = 1'b0;
vco_val_old_bit_setting = 1'b0;
end
scan_data[9:13] = 5'b00000;
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
scan_data[14:16] = charge_pump_current_bits;
// store as old values
cp_curr_old_bit_setting = charge_pump_current_bits;
lfc_val_old_bit_setting = loop_filter_c_bits;
lfr_val_old_bit_setting = loop_filter_r_bits;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (c_mode_val[i] == "bypass")
begin
scan_data[53 + i*18 + 0] = 1'b1;
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
else
begin
scan_data[53 + i*18 + 0] = 1'b0;
// 3. Mode - odd/even
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
// 2. Hi
c_val = c_high_val[i];
for (j = 1; j <= 8; j = j + 1)
scan_data[53 + i*18 + j] = c_val[8 - j];
// 4. Low
c_val = c_low_val[i];
for (j = 10; j <= 17; j = j + 1)
scan_data[53 + i*18 + j] = c_val[17 - j];
end
// M counter
// 1. Mode - bypass (bit 17)
if (m_mode_val[0] == "bypass")
scan_data[35] = 1'b1;
else
scan_data[35] = 1'b0;
// 2. High (bit 18-25)
// 3. Mode - odd/even (bit 26)
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[36:43]= m_val[0]/2;
scan_data[44] = 1'b0;
end
else
begin
// M is odd : M high = low + 1
scan_data[36:43] = m_val[0]/2 + 1;
scan_data[44] = 1'b1;
end
// 4. Low (bit 27-34)
scan_data[45:52] = m_val[0]/2;
// N counter
// 1. Mode - bypass (bit 35)
if (n_mode_val[0] == "bypass")
scan_data[17] = 1'b1;
else
scan_data[17] = 1'b0;
// 2. High (bit 36-43)
// 3. Mode - odd/even (bit 44)
if (n_val[0] % 2 == 0)
begin
// N is an even no. : set N high = low,
// set odd/even bit to 0
scan_data[18:25] = n_val[0]/2;
scan_data[26] = 1'b0;
end
else
begin // N is odd : N high = N low + 1
scan_data[18:25] = n_val[0]/2+ 1;
scan_data[26] = 1'b1;
end
// 4. Low (bit 45-52)
scan_data[27:34] = n_val[0]/2;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
no_warn = 1'b0;
pfd_locked = 1'b0;
cycles_pfd_high = 0;
cycles_pfd_low = 0;
// check if pll is in test mode
if (m_test_source != -1 || c0_test_source != -1 || c1_test_source != -1 || c2_test_source != -1 || c3_test_source != -1 || c4_test_source != -1)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_has_just_been_reconfigured = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
tap0_is_active = 1;
// To display clock mapping
case( i_clk0_counter)
"c0" : clk_num[0] = " clk0";
"c1" : clk_num[0] = " clk1";
"c2" : clk_num[0] = " clk2";
"c3" : clk_num[0] = " clk3";
"c4" : clk_num[0] = " clk4";
default:clk_num[0] = "unused";
endcase
case( i_clk1_counter)
"c0" : clk_num[1] = " clk0";
"c1" : clk_num[1] = " clk1";
"c2" : clk_num[1] = " clk2";
"c3" : clk_num[1] = " clk3";
"c4" : clk_num[1] = " clk4";
default:clk_num[1] = "unused";
endcase
case( i_clk2_counter)
"c0" : clk_num[2] = " clk0";
"c1" : clk_num[2] = " clk1";
"c2" : clk_num[2] = " clk2";
"c3" : clk_num[2] = " clk3";
"c4" : clk_num[2] = " clk4";
default:clk_num[2] = "unused";
endcase
case( i_clk3_counter)
"c0" : clk_num[3] = " clk0";
"c1" : clk_num[3] = " clk1";
"c2" : clk_num[3] = " clk2";
"c3" : clk_num[3] = " clk3";
"c4" : clk_num[3] = " clk4";
default:clk_num[3] = "unused";
endcase
case( i_clk4_counter)
"c0" : clk_num[4] = " clk0";
"c1" : clk_num[4] = " clk1";
"c2" : clk_num[4] = " clk2";
"c3" : clk_num[4] = " clk3";
"c4" : clk_num[4] = " clk4";
default:clk_num[4] = "unused";
endcase
end
// Clock Switchover
always @(clkswitch)
begin
if (clkswitch === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if(clkswitch === 1'b1)
switch_clock = 1'b1;
else
switch_clock = 1'b0;
end
end
always @(posedge inclk[0])
begin
// Determine the inclk0 frequency
if (first_inclk0_edge_detect == 1'b0)
begin
first_inclk0_edge_detect = 1'b1;
end
else
begin
last_inclk0_period = inclk0_period;
inclk0_period = $realtime - last_inclk0_edge;
end
last_inclk0_edge = $realtime;
end
always @(posedge inclk[1])
begin
// Determine the inclk1 frequency
if (first_inclk1_edge_detect == 1'b0)
begin
first_inclk1_edge_detect = 1'b1;
end
else
begin
last_inclk1_period = inclk1_period;
inclk1_period = $realtime - last_inclk1_edge;
end
last_inclk1_edge = $realtime;
end
always @(inclk[0] or inclk[1])
begin
if(switch_clock == 1'b1)
begin
if(current_clock_man == 0)
begin
current_clock_man = 1;
active_clock = 1;
end
else
begin
current_clock_man = 0;
active_clock = 0;
end
switch_clock = 1'b0;
end
if (current_clock_man == 0)
inclk_man = inclk[0];
else
inclk_man = inclk[1];
// save the inclk event value
if (inclk[0] !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk[0];
end
if (inclk[1] !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk[1];
end
// check if either input clk is bad
if (inclk[0] === 1'b1 && inclk[0] !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk[1] === 1'b1 && inclk[1] !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk[0] !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[0] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[0];
end
end
else inclk_es = inclk[0];
end
if ((inclk[1] !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[1] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[1];
end
end
else inclk_es = inclk[1];
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (primary_clk_is_bad && (clkswitch !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
if (areset === 1'b0)
begin
if ((inclk0_period > inclk1_period) && (inclk1_period != 0))
diff_percent_period = (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else if (inclk0_period != 0)
diff_percent_period = (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
if((diff_percent_period > 20)&& (l_switch_over_type == "auto"))
begin
$display ("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.");
$display ("Time: %0t Instance: %m", $time);
end
end
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
else if(l_switch_over_type == "auto")
begin
if(current_clock == 0 && clk0_is_bad == 1'b1 && clk1_is_bad == 1'b0 )
begin
current_clock = 1;
active_clock = ~active_clock;
end
if(current_clock == 1 && clk1_is_bad == 1'b1 && clk0_is_bad == 1'b0 )
begin
current_clock = 0;
active_clock = ~active_clock;
end
end
end
if(l_switch_over_type == "manual")
inclk_n = inclk_man;
else
inclk_n = inclk_es;
inclk0_last_value = inclk[0];
inclk1_last_value = inclk[1];
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
assign inclk_m = (m_test_source == 0) ? fbclk : (m_test_source == 1) ? refclk : inclk_m_from_vco;
cycloneiiils_m_cntr m1 (.clk(inclk_m),
.reset(areset || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneiiils_n_cntr n1 (.clk(inclk_n),
.reset(areset),
.cout(refclk),
.modulus(n_val[0]));
// Update clock on /o counters from corresponding VCO tap
assign inclk_m_from_vco = vco_tap[m_ph_val];
assign inclk_c0_from_vco = vco_tap[c_ph_val[0]];
assign inclk_c1_from_vco = vco_tap[c_ph_val[1]];
assign inclk_c2_from_vco = vco_tap[c_ph_val[2]];
assign inclk_c3_from_vco = vco_tap[c_ph_val[3]];
assign inclk_c4_from_vco = vco_tap[c_ph_val[4]];
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// Update phase taps for C/M counters on negative edge of VCO clock output
if (update_phase == 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y < 10; y = y + 1)
begin
if (c_ph_val_tmp[y] == x)
c_ph_val[y] = c_ph_val_tmp[y];
end
if (m_ph_val_tmp == x)
m_ph_val = m_ph_val_tmp;
end
end
update_phase <= #(0.5*scanclk_period) 1'b0;
end
// On reset, set all C/M counter phase taps to POF programmed values
if (areset === 1'b1)
begin
m_ph_val = m_ph_val_orig;
m_ph_val_tmp = m_ph_val_orig;
for (i=0; i<= 9; i=i+1)
begin
c_ph_val[i] = c_ph_val_orig[i];
c_ph_val_tmp[i] = c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 0) ? fbclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
cycloneiiils_scale_cntr c0 (.clk(inclk_c0),
.reset(areset || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
// Update /o counters mode and duty cycle immediately after configupdate is asserted
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? fbclk : (c1_test_source == 1) ? refclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneiiils_scale_cntr c1 (.clk(inclk_c1),
.reset(areset || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? fbclk : (c2_test_source == 1) ? refclk :(ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneiiils_scale_cntr c2 (.clk(inclk_c2),
.reset(areset || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? fbclk : (c3_test_source == 1) ? refclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneiiils_scale_cntr c3 (.clk(inclk_c3),
.reset(areset || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? fbclk : (c4_test_source == 1) ? refclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneiiils_scale_cntr c4 (.clk(inclk_c4),
.reset(areset || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign locked = (test_bypass_lock_detect == "on") ? pfd_locked : locked_tmp;
// Register scanclk enable
always @(negedge scanclk)
scanclkena_reg <= scanclkena;
// Negative edge flip-flop in front of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_in <= scandata;
end
end
// Scan chain
always @(posedge scanclk)
begin
if (got_first_scanclk === 1'b0)
got_first_scanclk = 1'b1;
else
scanclk_period = $time - scanclk_last_rising_edge;
if (scanclkena_reg)
begin
for (j = scan_chain_length-2; j >= 0; j = j - 1)
scan_data[j] = scan_data[j - 1];
scan_data[-1] <= scandata_in;
end
scanclk_last_rising_edge = $realtime;
end
// Scan output
assign scandataout_tmp = scan_data[SCAN_CHAIN - 2];
// Negative edge flip-flop in rear of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_out <= scandataout_tmp;
end
end
// Scan complete
always @(negedge scandone_tmp)
begin
if (got_first_scanclk === 1'b1)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" %s : C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s)", clk_num[i],i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i]);
end
// display Charge pump and loop filter values
if (pll_reconfig_display_full_setting == 1'b1)
begin
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
$display (" VCO_Post_Scale = %0d (%0d) ", vco_cur, vco_old);
end
else
begin
$display (" Charge Pump Current = %0d (%0d) ", cp_curr_bit_setting, cp_curr_old_bit_setting);
$display (" Loop Filter Capacitor = %0d (%0d) ", lfc_val_bit_setting, lfc_val_old_bit_setting);
$display (" Loop Filter Resistor = %0d (%0d) ", lfr_val_bit_setting, lfr_val_old_bit_setting);
$display (" VCO_Post_Scale = %b (%b) ", vco_val_bit_setting, vco_val_old_bit_setting);
end
cp_curr_old_bit_setting = cp_curr_bit_setting;
lfc_val_old_bit_setting = lfc_val_bit_setting;
lfr_val_old_bit_setting = lfr_val_bit_setting;
vco_val_old_bit_setting = vco_val_bit_setting;
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
// ************ PLL Phase Reconfiguration ************* //
// Latch updown,counter values at pos edge of scan clock
always @(posedge scanclk)
begin
if (phasestep_reg == 1'b1)
begin
if (phasestep_high_count == 1)
begin
phasecounterselect_reg <= phasecounterselect;
phaseupdown_reg <= phaseupdown;
// start reconfiguration
if (phasecounterselect < 3'b111) // no counters selected
begin
if (phasecounterselect == 0) // all output counters selected
begin
for (i = 0; i < num_output_cntrs; i = i + 1)
c_ph_val_tmp[i] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[i] + 1) % num_phase_taps :
(c_ph_val_tmp[i] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[i] - 1) % num_phase_taps ;
end
else if (phasecounterselect == 1) // select M counter
begin
m_ph_val_tmp = (phaseupdown == 1'b1) ?
(m_ph_val + 1) % num_phase_taps :
(m_ph_val == 0) ? num_phase_taps - 1 : (m_ph_val - 1) % num_phase_taps ;
end
else // select C counters
begin
select_counter = phasecounterselect - 2;
c_ph_val_tmp[select_counter] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[select_counter] + 1) % num_phase_taps :
(c_ph_val_tmp[select_counter] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[select_counter] - 1) % num_phase_taps ;
end
update_phase <= 1'b1;
end
end
phasestep_high_count = phasestep_high_count + 1;
end
end
// Latch phase enable (same as phasestep) on neg edge of scan clock
always @(negedge scanclk)
begin
phasestep_reg <= phasestep;
end
always @(posedge phasestep)
begin
if (update_phase == 1'b0) phasestep_high_count = 0; // phase adjustments must be 1 cycle apart
// if not, next phasestep cycle is skipped
end
// ************ PLL Full Reconfiguration ************* //
assign update_conf_latches = configupdate;
// reset counter transfer flags
always @(negedge scandone_tmp)
begin
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
update_conf_latches_reg <= 1'b0;
end
always @(posedge update_conf_latches)
begin
initiate_reconfig <= 1'b1;
end
always @(posedge areset)
begin
if (scandone_tmp == 1'b1) scandone_tmp = 1'b0;
end
always @(posedge scanclk)
begin
if (initiate_reconfig == 1'b1)
begin
initiate_reconfig <= 1'b0;
$display ("NOTE : PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
scandone_tmp <= #(scanclk_period) 1'b1;
update_conf_latches_reg <= update_conf_latches;
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
vco_old = vco_cur;
// save old values of bit settings
cp_curr_bit_setting = scan_data[14:16];
lfc_val_bit_setting = scan_data[1:2];
lfr_val_bit_setting = scan_data[3:7];
vco_val_bit_setting = scan_data[8];
// LF unused : bit 1
// LF Capacitance : bits 1,2 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
lfc_val = fpll_loop_filter_c_arr[scan_data[1:2]];
else
lfc_val = loop_filter_c_arr[scan_data[1:2]];
// LF Resistance : bits 3-7
// valid values - 00000,00100,10000,10100,11000,11011,11100,11110
if (((scan_data[3:7] == 5'b00000) || (scan_data[3:7] == 5'b00100)) ||
((scan_data[3:7] == 5'b10000) || (scan_data[3:7] == 5'b10100)) ||
((scan_data[3:7] == 5'b11000) || (scan_data[3:7] == 5'b11011)) ||
((scan_data[3:7] == 5'b11100) || (scan_data[3:7] == 5'b11110))
)
begin
lfr_val = (scan_data[3:7] == 5'b00000) ? "20" :
(scan_data[3:7] == 5'b00100) ? "16" :
(scan_data[3:7] == 5'b10000) ? "12" :
(scan_data[3:7] == 5'b10100) ? "8" :
(scan_data[3:7] == 5'b11000) ? "6" :
(scan_data[3:7] == 5'b11011) ? "4" :
(scan_data[3:7] == 5'b11100) ? "2" : "1";
end
//VCO post scale value
if (scan_data[8] === 1'b1) // vco_post_scale = 1
begin
i_vco_max = i_vco_max_no_division/2;
i_vco_min = i_vco_min_no_division/2;
vco_cur = 1;
end
else
begin
i_vco_max = vco_max;
i_vco_min = vco_min;
vco_cur = 2;
end
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
cp_curr_val = scan_data[14:16];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
for (i=0; i< num_output_cntrs; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// M counter
// 1. Mode - bypass (bit 17)
if (scan_data[17] == 1'b1)
n_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 26)
else if (scan_data[26] == 1'b1)
n_mode_val[0] = " odd";
else
n_mode_val[0] = " even";
// 2. High (bit 18-25)
n_hi = scan_data[18:25];
// 4. Low (bit 27-34)
n_lo = scan_data[27:34];
// N counter
// 1. Mode - bypass (bit 35)
if (scan_data[35] == 1'b1)
m_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 44)
else if (scan_data[44] == 1'b1)
m_mode_val[0] = " odd";
else
m_mode_val[0] = " even";
// 2. High (bit 36-43)
m_hi = scan_data[36:43];
// 4. Low (bit 45-52)
m_lo = scan_data[45:52];
//Update the current M and N counter values if the counters are NOT bypassed
if (m_mode_val[0] != "bypass")
m_val[0] = m_hi + m_lo;
if (n_mode_val[0] != "bypass")
n_val[0] = n_hi + n_lo;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (scan_data[53 + i*18 + 0] == 1'b1)
c_mode_val_tmp[i] = "bypass";
// 3. Mode - odd/even
else if (scan_data[53 + i*18 + 9] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
// 2. Hi
for (j = 1; j <= 8; j = j + 1)
c_val[8-j] = scan_data[53 + i*18 + j];
c_hval[i] = c_val[7:0];
if (c_hval[i] !== 32'h00000000)
c_high_val_tmp[i] = c_hval[i];
else
c_high_val_tmp[i] = 9'b100000000;
// 4. Low
for (j = 10; j <= 17; j = j + 1)
c_val[17 - j] = scan_data[53 + i*18 + j];
c_lval[i] = c_val[7:0];
if (c_lval[i] !== 32'h00000000)
c_low_val_tmp[i] = c_lval[i];
else
c_low_val_tmp[i] = 9'b100000000;
end
// Legality Checks
if (m_mode_val[0] != "bypass")
begin
if ((m_hi !== m_lo) && (m_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (m_hi !== 8'b00000000)
begin
// counter value
m_val_tmp[0] = m_hi + m_lo;
end
else
m_val_tmp[0] = 9'b100000000;
end
else
m_val_tmp[0] = 8'b00000001;
if (n_mode_val[0] != "bypass")
begin
if ((n_hi !== n_lo) && (n_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The N counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (n_hi !== 8'b00000000)
begin
// counter value
n_val[0] = n_hi + n_lo;
end
else
n_val[0] = 9'b100000000;
end
else
n_val[0] = 8'b00000001;
// TODO : Give warnings/errors in the following cases?
// 1. Illegal counter values (error)
// 2. Change of mode (warning)
// 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
end
end
// Self reset on loss of lock
assign reset_self = (l_self_reset_on_loss_lock == "on") ? ~pll_is_locked : 1'b0;
always @(posedge reset_self)
begin
$display (" Note : %s PLL self reset due to loss of lock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// Phase shift on /o counters
always @(schedule_vco or areset)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset === 1'b1 && areset_last_value !== areset)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
tap0_is_active = 0;
phase_adjust_was_scheduled = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// illegal value on areset
if (areset === 1'bx && (areset_last_value === 1'b0 || areset_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((areset == 1'b1))
begin
pll_is_in_reset = 1;
got_first_refclk = 0;
got_second_refclk = 0;
end
if ((schedule_vco !== schedule_vco_last_value) && (areset == 1'b1 || stop_vco == 1'b1))
begin
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end else if (areset === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset === 1'b0 && areset_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
locked_tmp = 1'b0;
end
pll_is_in_reset = 0;
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
pull_back_M = initial_delay + fbk_phase;
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_last_value = areset;
schedule_vco_last_value = schedule_vco;
end
assign pfdena_wire = (pfdena === 1'b0) ? 1'b0 : 1'b1;
// PFD enable
always @(pfdena_wire)
begin
if (pfdena_wire === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_wire === 1'b1 && pfdena_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_last_value = pfdena_wire;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
// Bypass lock detect
always @(posedge refclk)
begin
if (test_bypass_lock_detect == "on")
begin
if (pfdena_wire === 1'b1)
begin
cycles_pfd_low = 0;
if (pfd_locked == 1'b0)
begin
if (cycles_pfd_high == lock_high)
begin
$display ("Note : %s PLL locked in test mode on PFD enable assert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b1;
end
cycles_pfd_high = cycles_pfd_high + 1;
end
end
if (pfdena_wire === 1'b0)
begin
cycles_pfd_high = 0;
if (pfd_locked == 1'b1)
begin
if (cycles_pfd_low == lock_low)
begin
$display ("Note : %s PLL lost lock in test mode on PFD enable deassert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b0;
end
cycles_pfd_low = cycles_pfd_low + 1;
end
end
end
end
always @(posedge scandone_tmp or posedge locked_tmp)
begin
if(scandone_tmp == 1)
pll_has_just_been_reconfigured <= 1;
else
pll_has_just_been_reconfigured <= 0;
end
// VCO Frequency Range check
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((i_vco_max != 0 && i_vco_min != 0) && (pfdena_wire === 1'b1) &&
((refclk_period/loop_xplier > i_vco_max) ||
(refclk_period/loop_xplier < i_vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
vco_over = 1'b0;
vco_under = 1'b0;
inclk_out_of_range = 0;
no_warn = 1'b0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
// Update M counter value on feedback clock edge
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (update_conf_latches === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_wire === 1'b1 && pll_is_locked === 1'b1) ||
( ($time - refclk_time > 5 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 0) ) ||
( ($time - refclk_time > 50 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 1) ) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.", family_name);
if ((i_vco_max == 0) && (i_vco_min == 0))
$display ("Note : Please run timing simulation to check whether the input clock is operating within the supported VCO range or not.");
$display ("Time: %0t Instance: %m", $time);
end
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
// Core lock functionality
if (got_second_refclk && pfdena_wire === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= lock_window || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
// considered in phase
if (cycles_to_lock == real_lock_high)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == lock_low)
begin
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = abs(m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = abs(m_times_vco_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : 1'b0;
assign clk_out_pfd[0] = (pfd_locked == 1'b1) ? clk_tmp[0] : 1'bx;
assign clk_out_pfd[1] = (pfd_locked == 1'b1) ? clk_tmp[1] : 1'bx;
assign clk_out_pfd[2] = (pfd_locked == 1'b1) ? clk_tmp[2] : 1'bx;
assign clk_out_pfd[3] = (pfd_locked == 1'b1) ? clk_tmp[3] : 1'bx;
assign clk_out_pfd[4] = (pfd_locked == 1'b1) ? clk_tmp[4] : 1'bx;
assign clk_out[0] = (test_bypass_lock_detect == "on") ? clk_out_pfd[0] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx);
assign clk_out[1] = (test_bypass_lock_detect == "on") ? clk_out_pfd[1] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx);
assign clk_out[2] = (test_bypass_lock_detect == "on") ? clk_out_pfd[2] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx);
assign clk_out[3] = (test_bypass_lock_detect == "on") ? clk_out_pfd[3] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx);
assign clk_out[4] = (test_bypass_lock_detect == "on") ? clk_out_pfd[4] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx);
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (scandataout, 1'b1, scandata_out);
and (scandone, 1'b1, scandone_tmp);
assign fbout = fbclk;
assign vcooverrange = (vco_range_detector_high_bits == -1) ? 1'bz : vco_over;
assign vcounderrange = (vco_range_detector_low_bits == -1) ? 1'bz :vco_under;
assign phasedone = ~update_phase;
endmodule // cycloneiiils_pll
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_lcell_comb
//
// Description : Cyclone III LS LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";
parameter lpm_type = "cycloneiiils_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
end
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_ff
//
// Description : Cyclone III LS FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "cycloneiiils_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneiiils_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneiiils_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneiiils_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneiiils_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneiiils_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2048'b0;
parameter mem_init2 = 2048'b0;
parameter mem_init3 = 2048'b0;
parameter mem_init4 = 2048'b0;
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter safe_write = "err_on_2clk";
parameter init_file_restructured = "unused";
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// Hardware write modes
parameter dual_clock = ((operation_mode == "dual_port") ||
(operation_mode == "bidir_dual_port")) &&
(port_b_address_clock == "clock1");
parameter both_new_data_same_port = (
((port_a_read_during_write_mode == "new_data_no_nbe_read") ||
(port_a_read_during_write_mode == "dont_care")) &&
((port_b_read_during_write_mode == "new_data_no_nbe_read") ||
(port_b_read_during_write_mode == "dont_care"))
) ? 1'b1 : 1'b0;
parameter hw_write_mode_a = (
((port_a_read_during_write_mode == "old_data") ||
(port_a_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter hw_write_mode_b = (
((port_b_read_during_write_mode == "old_data") ||
(port_b_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter delay_write_pulse_a = (hw_write_mode_a != "FW") ? 1'b1 : 1'b0;
parameter delay_write_pulse_b = (hw_write_mode_b != "FW") ? 1'b1 : 1'b0;
parameter be_mask_write_a = (port_a_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter be_mask_write_b = (port_b_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter old_data_write_a = (port_a_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter old_data_write_b = (port_b_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter read_before_write_a = (hw_write_mode_a == "R+W") ? 1'b1 : 1'b0;
parameter read_before_write_b = (hw_write_mode_b == "R+W") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri1 portare_int;
assign portare_int = portare;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbwe_int;
assign portbwe_int = portbwe;
tri1 portbre_int;
assign portbre_int = portbre;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 ena2_int,ena3_int;
assign ena2_int = ena2;
assign ena3_int = ena3;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_a_rena, clk_a_wena;
wire clk_a_core;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire clk_b_rena, clk_b_wena;
wire clk_b_core;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire dataout_a_clr_reg, dataout_b_clr_reg;
wire dataout_a_clr_reg_latch, dataout_b_clr_reg_latch;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr, re_a_clr, we_b_clr, re_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in, re_a_clr_in, we_b_clr_in, re_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire re_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire we_b_reg, re_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire rw_pulse_a, rw_pulse_b;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
wire rw_pulse_prime, rw_pulse_sec;
reg read_pulse_prime_last_value, read_pulse_sec_last_value;
reg rw_pulse_prime_last_value, rw_pulse_sec_last_value;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a_in, active_b_in;
wire active_a_core,active_a_core_in,active_b_core,active_b_core_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = 0;
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {
mem_init4 , mem_init3 , mem_init2 ,
mem_init1 , mem_init0
};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_wena = (port_a_write_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_rena = (port_a_read_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_wena = (port_b_write_enable_clock == "none") ? 1'b0 : (
(port_b_write_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_rena = (port_b_read_enable_clock == "none") ? 1'b0 : (
(port_b_read_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = 1'b0;
assign dataout_a_clr = (port_a_data_out_clock == "none") ? (
(port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_a_clr_reg = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = 1'b0;
assign dataout_b_clr = (port_b_data_out_clock == "none") ? (
(port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_b_clr_reg = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = 1'b0;
assign byteena_b_clr_in = 1'b0;
assign we_a_clr_in = 1'b0;
assign re_a_clr_in = 1'b0;
assign we_b_clr_in = 1'b0;
assign re_b_clr_in = 1'b0;
assign active_a_in = (clk0_input_clock_enable == "none") ? 1'b1 : (
(clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_a_core_in = (clk0_core_clock_enable == "none") ? 1'b1 : (
(clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_b_in = (port_b_address_clock == "clock0") ? (
(clk0_input_clock_enable == "none") ? 1'b1 : ((clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_input_clock_enable == "none") ? 1'b1 : ((clk1_input_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_b_core_in = (port_b_address_clock == "clock0") ? (
(clk0_core_clock_enable == "none") ? 1'b1 : ((clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_core_clock_enable == "none") ? 1'b1 : ((clk1_core_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_write_a = (byteena_a_reg !== 'b0);
assign active_write_b = (byteena_b_reg !== 'b0);
// Store core clock enable value for delayed write
// port A core active
cycloneiiils_ram_register active_core_port_a (
.d(active_a_core_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a_core),.aclrout()
);
defparam active_core_port_a.width = 1;
// port B core active
cycloneiiils_ram_register active_core_port_b (
.d(active_b_core_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b_core),.aclrout()
);
defparam active_core_port_b.width = 1;
// ------- A input registers -------
// write enable
cycloneiiils_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_wena),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// read enable
cycloneiiils_ram_register re_a_register (
.d(portare_int),
.clk(clk_a_rena),
.aclr(re_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(re_a_reg),
.aclrout(re_a_clr)
);
// address
cycloneiiils_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneiiils_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneiiils_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// write enable
cycloneiiils_ram_register we_b_register (
.d(portbwe_int),
.clk(clk_b_wena),
.aclr(we_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(we_b_reg),
.aclrout(we_b_clr)
);
defparam we_b_register.width = 1;
defparam we_b_register.preset = 1'b0;
// read enable
cycloneiiils_ram_register re_b_register (
.d(portbre_int),
.clk(clk_b_rena),
.aclr(re_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(re_b_reg),
.aclrout(re_b_clr)
);
defparam re_b_register.width = 1;
defparam re_b_register.preset = 1'b0;
// address
cycloneiiils_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneiiils_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneiiils_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Hardware Write Modes
// CYCLONEIIILS
// Write pulse generation
cycloneiiils_ram_pulse_generator wpgen_a (
.clk(clk_a_in),
.ena(active_a_core & active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
defparam wpgen_a.delay_pulse = delay_write_pulse_a;
cycloneiiils_ram_pulse_generator wpgen_b (
.clk(clk_b_in),
.ena(active_b_core & active_write_b & mode_is_bdp & we_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
defparam wpgen_b.delay_pulse = delay_write_pulse_b;
// Read pulse generation
cycloneiiils_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & ~we_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a),
.cycle(clk_a_core)
);
cycloneiiils_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~we_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b),
.cycle(clk_b_core)
);
// Read during write pulse generation
cycloneiiils_ram_pulse_generator rwpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & we_a_reg & read_before_write_a & ~dataout_a_clr),
.pulse(rw_pulse_a),.cycle()
);
cycloneiiils_ram_pulse_generator rwpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & re_b_reg & we_b_reg & read_before_write_b & ~dataout_b_clr),
.pulse(rw_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign rw_pulse_prime = (primary_port_is_a) ? rw_pulse_a : rw_pulse_b;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
assign rw_pulse_sec = (primary_port_is_a) ? rw_pulse_b : rw_pulse_a;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
// Latch Clear port A
always @(posedge dataout_a_clr)
begin
if (primary_port_is_a) begin read_data_latch = 'b0; dataout_a = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_a = 'b0; end
end
// Latch Clear port B
always @(posedge dataout_b_clr)
begin
if (primary_port_is_b) begin read_data_latch = 'b0; dataout_b = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_b = 'b0; end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
or posedge rw_pulse_prime or posedge rw_pulse_sec
)
begin
// Read before Write stage 1 : read data from memory
if (rw_pulse_prime && (rw_pulse_prime !== rw_pulse_prime_last_value))
begin
read_data_latch = mem[addr_prime_reg];
rw_pulse_prime_last_value = rw_pulse_prime;
end
if (rw_pulse_sec && (rw_pulse_sec !== rw_pulse_sec_last_value))
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
rw_pulse_sec_last_value = rw_pulse_sec;
end
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
if ((row_sec == addr_prime_reg) && (read_pulse_sec))
begin
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime && read_pulse_prime !== read_pulse_prime_last_value)
begin
read_data_latch = mem[addr_prime_reg];
read_pulse_prime_last_value = read_pulse_prime;
end
if (read_pulse_sec && read_pulse_sec !== read_pulse_sec_last_value)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
read_pulse_sec_last_value = read_pulse_sec;
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
always @(negedge read_pulse_prime) read_pulse_prime_last_value = 1'b0;
always @(negedge read_pulse_sec) read_pulse_sec_last_value = 1'b0;
always @(negedge rw_pulse_prime) rw_pulse_prime_last_value = 1'b0;
always @(negedge rw_pulse_sec) rw_pulse_sec_last_value = 1'b0;
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Read during Write stage 2 : Send data to output
always @(negedge rw_pulse_prime)
begin
if (primary_port_is_a)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_a[i] = read_data_latch[i];
end
else
dataout_a = read_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_b[i] = read_data_latch[i];
end
else
dataout_b = read_data_latch;
end
end
always @(negedge rw_pulse_sec)
begin
if (primary_port_is_b)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_a[i] = read_unit_data_latch[i];
end
else
dataout_a = read_unit_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_b[i] = read_unit_data_latch[i];
end
else
dataout_b = read_unit_data_latch;
end
end
// Same port feed through
cycloneiiils_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a_core & ~mode_is_dp & ~old_data_write_a & we_a_reg & re_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneiiils_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & ~old_data_write_b & we_b_reg & re_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_a[i] = datain_prime_reg[i];
end
else
dataout_a = datain_prime_reg ^ mask_vector_prime;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_b[i] = datain_prime_reg[i];
end
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_a[i] = datain_sec_reg[i];
end
else
dataout_a = datain_sec_reg ^ mask_vector_sec;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_b[i] = datain_sec_reg[i];
end
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a_core & re_a_reg & ~dataout_a_clr & ~dataout_a_clr_reg_latch)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge we_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
mem_invalidate = 1'b1;
else if ((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~dataout_b_clr & ~dataout_b_clr_reg_latch)
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge we_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Aclr mux registers (Latch Clear) --------
// port A
cycloneiiils_ram_register aclr__a__mux_register (
.d(dataout_a_clr),
.clk(clk_a_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_a_clr_reg_latch),.aclrout()
);
// port B
cycloneiiils_ram_register aclr__b__mux_register (
.d(dataout_b_clr),
.clk(clk_b_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_b_clr_reg_latch),.aclrout()
);
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneiiils_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr_reg),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneiiils_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr_reg),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneiiils_ram_block
//---------------------------------------------------------------------
//
// Module Name : cycloneiiils_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone III LS MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneiiils_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone III LS MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiiils_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneiiils_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_mac_mult_internal
//
// Description : Cyclone III LS MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_mac_mult
//
// Description : Cyclone III LS MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiiils_mac_mult";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneiiils_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneiiils_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneiiils_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneiiils_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneiiils_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_mac_out
//
// Description : Cyclone III LS MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneiiils_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiiils_io_ibuf //
//Description: Simulation model for Cyclone III LS IO Input Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiiils_io_ibuf (
i,
ibar,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cycloneiiils_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiiils_io_obuf //
//Description: Simulation model for Cyclone III LS IO Output Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiiils_io_obuf (
i,
oe,
seriesterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter lpm_type = "cycloneiiils_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input [15:0] seriesterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = (devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar = (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiiils_ddio_out //
//Description: Simulation model for Cyclone III LS DDIO Output //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiiils_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_new_clocking_model = "false";
parameter lpm_type = "cycloneiiils_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi ;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
reg sel_mux_hi_in_tmp;
reg dffhi_tmp1;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
muxsel_tmp <= mux_sel;
end
always@(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end
always@(dffhi_tmp1)
begin
sel_mux_hi_in_tmp <= dffhi_tmp1;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
cycloneiiils_latch ddioreg_hi(
.D(datainhi_tmp),
.ENA(!clk_hi & ena),
.PRE(ddioreg_prn),
.CLR(ddioreg_aclr),
.Q(dffhi_tmp)
);
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = (ddioreg_sclr == 1'b0 && ddioreg_sload == 1'b1)? 1'b1 : (ddioreg_sclr == 1'b1 && ddioreg_sload == 1'b0)? 1'b0: dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
//registered output selection
cycloneiiils_mux21 sel_mux(
.MO(dataout),
.A(sel_mux_hi_in),
.B(sel_mux_lo_in),
.S(!muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = sel_mux_hi_in_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiiils_ddio_oe //
//Description: Simulation model for Cyclone III LS DDIO OE //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiiils_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneiiils_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
cycloneiiils_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneiiils_pseudo_diff_out //
//Description: Simulation model for Cyclone III LS Pseudo Differential //
// Output Buffer //
//////////////////////////////////////////////////////////////////////////////////
module cycloneiiils_pseudo_diff_out(
i,
o,
obar
);
parameter lpm_type = "cycloneiiils_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneiiils_io_pad
// Description : Simulation model for cycloneiiils IO pad
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_io_pad (
padin,
padout
);
parameter lpm_type = "cycloneiiils_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneiiils_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk_in;
end
always @ (clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk_in === 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
clk_last_value = clk_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneiiils_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_clkctrl
//
// Description : Cyclone III LS CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
tri1 devclrn;
tri1 devpor;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneiiils_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg1_out; // output of ENA register1
wire cereg2_out; // output of ENA register2
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
specify
(inclk *> outclk) = (0, 0) ;
endspecify
cycloneiiils_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneiiils_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg1_out)
);
cycloneiiils_ena_reg extena1_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(cereg1_out),
.clrn(1'b1),
.prn(devpor),
.q(cereg2_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg1_out :
((ena_register_mode == "none") ? ena_ipd : cereg2_out);
and (outclk, ena_out, clkmux_out);
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIIILS RUBLOCK ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiiils_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "cycloneiiils_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneiiils_controller
//
// Description : cycloneiiils CONTROLLER Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_controller (
nceout
);
output nceout;
parameter lpm_type = "cycloneiiils_controller";
endmodule // cycloneiiils_controller
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_termination_ctrl_sub
//
// Description : Cyclone III LS Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_termination_ctrl (
clkusr,
intosc,
nclrusr,
nfrzdrv,
rclkdiv,
rclrusrinv,
rdivsel,
roctusr,
rsellvrefdn,
rsellvrefup,
rtest,
vccnx,
vssn,
clken,
clkin,
maskbit,
nclr,
noctdoneuser,
octdone,
oregclk,
oregnclr,
vref,
vrefh,
vrefl);
input clkusr;
input intosc; // clk source in powerup mode
input nclrusr;
input nfrzdrv; // devclrn
input rclkdiv; // - 14
input rclrusrinv; // invert nclrusr signal - 13
input rdivsel; // 0 = /32; 1 = /4; - 16
input roctusr; // run_time_control - 15
input rsellvrefdn; // shift_vref_rdn - 26
input rsellvrefup; // shift_vref_rup - 25
input rtest; // test_mode - 2
input vccnx; // VCC voltage src
input vssn; // GND voltage src
output clken;
output clkin;
output [8:0] maskbit;
output nclr;
output noctdoneuser;
output octdone;
output oregclk;
output oregnclr;
output vref;
output vrefh;
output vrefl;
parameter REG_TCO_DLY = 0; // 1;
reg divby2;
reg divby4;
reg divby8;
reg divby16;
reg divby32;
reg oregclk;
reg oregclkclk;
reg intosc_div4;
reg intosc_div32;
reg clken;
reg octdoneuser;
reg startbit;
reg [8:0] maskbit;
reg octdone;
wire [8:0] maskbit_d;
wire intoscin;
wire clk_sel;
wire intosc_clk;
wire clkin;
wire oregnclr;
wire clr_invert;
wire nclr;
wire adcclk;
// data flow in user mode:
// oregnclr = 1 forever so clkin is clkusr
//
// deasserting nclrusr starts off USER calibration
// upon rising edge of nclrusr
// (1). at 1st neg edge of clkin, clken = 1
// (2). enable adcclk
// (3). Mask bits [8:0] shifts from MSB=1 into LSB=1
// (4). oregclkclk = bit[0] (=1); 7th cycle
// (5). oregclk = 1 (after falling edge of oregclkclk) 8th cycle
// (6). clken = 0 (!oregclk)
// (7). octdoneuser = 1 (falling edge of clken)
initial
begin
octdone = 1'b1; // from powerup stage
octdoneuser = 1'b0;
startbit = 1'b0;
maskbit = 9'b000000000;
oregclk = 1'b0;
oregclkclk = 1'b0;
clken = 1'b0;
divby2 = 1'b0;
divby4 = 1'b0;
divby8 = 1'b0;
divby16 = 1'b0;
divby32 = 1'b0;
intosc_div4 = 1'b0;
intosc_div32 = 1'b0;
end
assign noctdoneuser = ~octdoneuser;
// c7216 clkdiv
always @(posedge intosc or negedge nfrzdrv) begin
if (!nfrzdrv) divby2 <= #(REG_TCO_DLY) 1'b0;
else divby2 <= #(REG_TCO_DLY) ~divby2;
end
always @(posedge divby2 or negedge nfrzdrv) begin
if (!nfrzdrv) divby4 <= #(REG_TCO_DLY) 1'b0;
else divby4 <= #(REG_TCO_DLY) ~divby4;
end
always @(posedge divby4 or negedge nfrzdrv) begin
if (!nfrzdrv) divby8 <= #(REG_TCO_DLY) 1'b0;
else divby8 <= #(REG_TCO_DLY) ~divby8;
end
always @(posedge divby8 or negedge nfrzdrv) begin
if (!nfrzdrv) divby16 <= #(REG_TCO_DLY) 1'b0;
else divby16 <= #(REG_TCO_DLY) ~divby16;
end
always @(posedge divby16 or negedge nfrzdrv) begin
if (!nfrzdrv) divby32 <= #(REG_TCO_DLY) 1'b0;
else divby32 <= #(REG_TCO_DLY) ~divby32;
end
assign intoscin = rdivsel ? divby4 : divby32;
assign clk_sel = octdone & roctusr; // always 1
assign intosc_clk = rclkdiv ? intoscin : intosc;
assign clkin = clk_sel ? clkusr : intosc_clk;
assign oregnclr = rtest | nfrzdrv; // always 1
assign clr_invert = rclrusrinv ? ~nclrusr : nclrusr;
assign nclr = clk_sel ? clr_invert : nfrzdrv;
// c7206
always @(negedge clkin or negedge nclr) begin
if (!nclr) clken <= #(REG_TCO_DLY) 1'b0;
else clken <= #(REG_TCO_DLY) ~oregclk;
end
always @(negedge clken or negedge oregnclr) begin
if (!oregnclr) octdone <= #(REG_TCO_DLY) 1'b0;
else octdone <= #(REG_TCO_DLY) 1'b1;
end
assign adcclk = clkin & clken;
always @(posedge adcclk or negedge nclr) begin
if (!nclr)
startbit <= #(REG_TCO_DLY) 1'b0;
else
startbit <= #(REG_TCO_DLY) 1'b1;
end
assign maskbit_d = {~startbit, maskbit[8:1]};
always @(posedge adcclk or negedge nclr) begin
if (!nclr) begin
maskbit <= #(REG_TCO_DLY) 9'b0;
oregclkclk <= #(REG_TCO_DLY) 1'b0;
end
else begin
maskbit <= #(REG_TCO_DLY) maskbit_d;
oregclkclk <= #(REG_TCO_DLY) maskbit[0];
end
end
always @(negedge oregclkclk or negedge nclr) begin
if (~nclr) oregclk <= #(REG_TCO_DLY) 1'b0;
else oregclk <= #(REG_TCO_DLY) 1'b1;
end
always @(negedge clken or negedge nclr) begin
if (~nclr) octdoneuser <= #(REG_TCO_DLY) 1'b0;
else octdoneuser <= #(REG_TCO_DLY) 1'b1;
end
// OCT VREF c7207 xvref (
// Functional code
assign vrefh = 1'b1;
assign vref = 1'b1;
assign vrefl = 1'b0;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_termination_ctrl_sub
//
// Description : Cyclone III LS Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_termination_rupdn (
clken,
clkin,
compout,
maskbit,
nclr,
octcal,
octpin,
octrpcd,
oregclk,
oregnclr,
radd,
rcompoutinv,
roctdone,
rpwrdn,
rshift,
rshiftvref,
rtest,
shiftedvref,
vccnx,
vref
);
input clken;
input clkin;
input [8:0] maskbit;
input nclr;
input octpin;
input oregclk;
input oregnclr;
input [7:0] radd;
input rcompoutinv;
input roctdone;
input rpwrdn;
input rshift;
input rshiftvref;
input rtest;
input shiftedvref;
input vccnx;
input vref;
output compout;
output [7:0] octcal; // to IO bank
output [7:0] octrpcd; // to the reference RUP/RDN
parameter is_rdn = "false";// initial value of octcal differ
parameter OCTCAL_DLY = 0; // 1;
parameter REG_TCO_DLY = 0; // 1;
//supply0 vss;
reg [7:0] comp_octrpcd;
reg [7:0] octcal_reg;
wire octref;
wire shftref_out;
wire compout_tmp;
wire nout;
wire nbias;
wire pbias;
wire [7:0] octrpcd;
wire [7:0] octcal_reg_in;
wire [7:0] reg_clk;
wire [7:0] srpcd;
wire [7:0] rpcdi;
wire [8:0] rpcdi_temp;
wire shift;
wire shftvrefhv;
wire compout;
wire clr;
wire reg_clkin;
wire reg_nclr;
wire shiftvref;
wire compadcen;
assign shift = rtest & ~clken;
assign compadcen = ~roctdone & clken;
assign shiftvref = ~(rshiftvref | maskbit[1]);
//c6419 xinverted_ls (
//vss, shiftvref, shftvrefhv, vccnx );
//c7223 xbias_ckt (
assign nbias = (compadcen === 1'b1) ? 1'b1 : 1'b0;
assign pbias = (compadcen === 1'b1) ? 1'b0 : 1'bz;
//c7202 xoct_comp (
assign compout_tmp = (compadcen === 1'b1) ? octpin : 1'b0;
assign shftvrefhv = shftref_out;
assign octref = shftvrefhv ? shiftedvref : vref;
assign compout = rcompoutinv ? compout_tmp : ~compout_tmp;
// c7208
assign reg_clk[7:0] = maskbit[7:0];
assign reg_nclr = (compadcen | ~rpwrdn) & nclr;
always @(posedge reg_clk[7] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[7] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[7] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[6] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[6] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[6] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[5] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[5] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[5] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[4] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[4] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[4] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[3] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[3] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[3] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[2] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[2] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[2] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[1] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[1] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[1] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[0] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[0] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[0] <= #(REG_TCO_DLY) compout;
end
// output sends to RUP/DN reference pins
assign octrpcd[7] = maskbit[8] ? 1'b1 : comp_octrpcd[7];
assign octrpcd[6] = maskbit[7] ? 1'b1 : comp_octrpcd[6];
// below: set octrpcd[5] and clear prior bit octrpcd[6] based on compout
assign octrpcd[5] = maskbit[6] ? 1'b1 : comp_octrpcd[5];
assign octrpcd[4] = maskbit[5] ? 1'b1 : comp_octrpcd[4];
assign octrpcd[3] = maskbit[4] ? 1'b1 : comp_octrpcd[3];
assign octrpcd[2] = maskbit[3] ? 1'b1 : comp_octrpcd[2];
assign octrpcd[1] = maskbit[2] ? 1'b1 : comp_octrpcd[1];
assign octrpcd[0] = maskbit[1] ? 1'b1 : comp_octrpcd[0];
// c7210 - leftshift
assign srpcd = rshift ? {octrpcd[6:0], 1'b0} : octrpcd;
// c7214 - Adder:
// overflow => max value 8'b1
// underflow => 0;
assign rpcdi_temp[8:0] = srpcd[7:0] + radd[7:0];
assign rpcdi[7:0] = {8{(~radd[7] & rpcdi_temp[8])}} | rpcdi_temp[7:0];
// left shift rotation in test mode - only when calibration is done (clken=0)
// calibration code (octcal) is 0 until calibration completed
// oregclk indicates 10th cycle since masket[8]=1 --> masket[0]=1 + one cycle
// clken is ~oregclk
assign reg_clkin = ~shift ? oregclk : clkin;
assign octcal_reg_in[7:0] = ~shift ? rpcdi[7:0] : ({octcal[6:0], octcal[7]});
initial begin
if (is_rdn == "true")
octcal_reg[7:0] = 8'hFF;
else
octcal_reg[7:0] = 8'h00;
end
// calibrated code cannot be cleared by user_clr
// it is only changed by code from calibration block which is
always @(posedge reg_clkin or negedge oregnclr) begin
if (!oregnclr) octcal_reg[7:0] <= #(REG_TCO_DLY) 8'h00;
else octcal_reg[7:0] <= #(REG_TCO_DLY) octcal_reg_in[7:0];
end
assign #(OCTCAL_DLY) octcal = octcal_reg;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneiiils_termination
//
// Description : Cyclone III LS Termination Atom Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_termination (
rup,
rdn,
terminationclock,
terminationclear,
devpor,
devclrn,
comparatorprobe,
terminationcontrolprobe,
calibrationdone,
terminationcontrol);
input rup;
input rdn;
input terminationclock;
input terminationclear;
input devpor;
input devclrn;
output comparatorprobe;
output terminationcontrolprobe;
output calibrationdone;
output [15:0] terminationcontrol;
parameter pullup_control_to_core = "false";
parameter power_down = "true";
parameter test_mode = "false";
parameter left_shift_termination_code = "false";
parameter pullup_adder = 0; // -128, 127
parameter pulldown_adder = 0; // -128, 127
parameter clock_divide_by = 32; // 1, 4, 32
parameter runtime_control = "false";
parameter shift_vref_rup = "true";
parameter shift_vref_rdn = "true";
parameter shifted_vref_control = "true";
parameter lpm_type = "cycloneiiils_termination";
tri1 devclrn;
tri1 devpor;
wire m_gnd;
wire m_vcc;
// interconnecting wires
// ctrl -----------------------------------------
wire xcbout_clken;
wire xcbout_clkin;
wire [8:0] xcbout_maskbit;
wire xcbout_nclr;
wire xcbout_noctdoneuser;
wire xcbout_octdone;
wire xcbout_oregclk;
wire xcbout_oregnclr;
wire xcbout_vref; // to run/dn comparator
wire xcbout_vrefh; // to rdn - shfitedvref
wire xcbout_vrefl; // to rup - shiftedvref
wire xcbin_clkusr;
wire xcbin_intosc; // clk source in powerup mode
wire xcbin_nclrusr;
wire xcbin_nfrzdrv; // devclrn
wire xcbin_rclkdiv; // - 14
wire xcbin_rclrusrinv; // invert nclrusr signal - 13
wire xcbin_rdivsel; // 0 = /32; 1 = /4; - 16
wire xcbin_roctusr; // run_time_control - 15
wire xcbin_rsellvrefdn; // shift_vref_rdn - 26
wire xcbin_rsellvrefup; // shift_vref_rup - 25
wire xcbin_rtest; // test_mode - 2
wire xcbin_vccnx; // VCC voltage src
wire xcbin_vssn; // GND voltage src
// rup and rdn ------------------------------------
// common
wire rshift_in;
wire rpwrdn_in;
wire rup_compout;
wire [7:0] rup_octrupn; // out from XRUP to rupref pin
wire [7:0] rup_octcalnout; // to the I/O bank
wire rupin;
reg [7:0] rup_radd;
wire rdn_compout;
wire [7:0] rdn_octrdnp; // out from XRDN to rdnref pin
wire [7:0] rdn_octcalpout; // to the I/O bank
wire rdnin;
reg [7:0] rdn_radd;
wire calout; // MSB of the calibration code
// primary input and outputs
assign rupin = rup;
assign rdnin = rdn;
// terminationclk and clear feeding into CTRL sub directly
assign calibrationdone = xcbout_octdone;
assign terminationcontrol = {rup_octcalnout, rdn_octcalpout};
assign comparatorprobe = (pullup_control_to_core == "true") ? rup_compout : rdn_compout;
assign calout = (pullup_control_to_core == "true") ? rup_octcalnout[7] : rdn_octcalpout[7];
assign terminationcontrolprobe = (test_mode == "true") ? calout : xcbout_noctdoneuser;
initial begin
rup_radd = pullup_adder;
rdn_radd = pulldown_adder;
end
// CTRL sub-block
assign xcbin_clkusr = terminationclock;
assign xcbin_intosc = 1'b0; // clk source in powerup mode
assign xcbin_nclrusr = (terminationclear === 1'b1) ? 1'b0 : 1'b1;
assign xcbin_nfrzdrv = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign xcbin_vccnx = 1'b1; // VCC voltage src
assign xcbin_vssn = 1'b0; // GND voltage src
assign xcbin_rclkdiv = (clock_divide_by != 1) ? 1'b1 : 1'b0; //- 14
assign xcbin_rclrusrinv = 1'b0; // invert nclrusr signal - 13
assign xcbin_rdivsel = (clock_divide_by == 32) ? 1'b0 : 1'b1; //- 16
assign xcbin_roctusr = (runtime_control == "true") ? 1'b1 : 1'b0; //- 15
assign xcbin_rsellvrefdn = (shift_vref_rdn == "true") ? 1'b1 : 1'b0; //- 26
assign xcbin_rsellvrefup = (shift_vref_rup == "true") ? 1'b1 : 1'b0; //- 25
assign xcbin_rtest = (test_mode == "true") ? 1'b1 : 1'b0; // - 2
cycloneiiils_termination_ctrl m_ctrl (
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.noctdoneuser (xcbout_noctdoneuser ),
.octdone (xcbout_octdone ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr ),
.vref (xcbout_vref ),
.vrefh (xcbout_vrefh ),
.vrefl (xcbout_vrefl ),
.clkusr (xcbin_clkusr ),
.intosc (xcbin_intosc ),
.nclrusr (xcbin_nclrusr ),
.nfrzdrv (xcbin_nfrzdrv ),
.vccnx (xcbin_vccnx ),
.vssn (xcbin_vssn ),
.rclkdiv (xcbin_rclkdiv ),
.rclrusrinv (xcbin_rclrusrinv ),
.rdivsel (xcbin_rdivsel ),
.roctusr (xcbin_roctusr ),
.rsellvrefdn (xcbin_rsellvrefdn ),
.rsellvrefup (xcbin_rsellvrefup ),
.rtest (xcbin_rtest )
);
assign m_vcc = 1'b1;
assign m_gnd = 1'b0;
assign rshift_in = (left_shift_termination_code == "true") ? 1'b1 : 1'b0;
assign rpwrdn_in = (power_down == "true") ? 1'b1 : 1'b0;
cycloneiiils_termination_rupdn m_rup (
.compout (rup_compout ),
.octrpcd (rup_octrupn ),
.octcal (rup_octcalnout ),
.octpin (rupin ),
.rcompoutinv (m_vcc ), // no inversion
.radd (rup_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefl ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rup.is_rdn = "false";
cycloneiiils_termination_rupdn m_rdn (
.compout (rdn_compout ),
.octrpcd (rdn_octrdnp ),
.octcal (rdn_octcalpout ),
.octpin (rdnin ),
.rcompoutinv (m_gnd ), // invert compout
.radd (rdn_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefh ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rdn.is_rdn = "true";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneiiils_jtag
//
// Description : cycloneiiils JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_jtag (
tms,
tck,
tdi,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cycloneiiils_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneiiils_crcblock
//
// Description : Cyclone III LS CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneiiils_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
cyclecomplete,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output cyclecomplete;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneiiils_crcblock";
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIIILS OSCILLATOR ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiiils_oscillator
(
oscena,
clkout1,
observableoutputport,
clkout
);
parameter lpm_type = "cycloneiiils_oscillator";
input oscena;
output clkout1;
output observableoutputport;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTERNAL wire
reg int_osc; // internal oscillator
specify
(posedge oscena => (clkout +: 1'b1)) = (0, 0);
endspecify
initial
int_osc = 1'b0;
always @(int_osc or oscena)
begin
if (oscena == 1'b1)
int_osc <= #OSC_PW ~int_osc;
end
and (clkout, int_osc, 1'b1);
endmodule
`ifdef MODEL_TECH
`mti_v2k_int_delays_off
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_SYMBOL_V
|
module sdram_fsm (
input wr_en,
input rd_en,
input [31:0] data,
input [31:0] addr,
output data
// SDRAM control signals
output reg [ 1:0] sdClkE,
output reg sdWeN,
output reg sdCasN,
output reg sdRasN,
output reg sdCsN,
output reg [11:0] sdA,
output reg [ 1:0] sdBa,
output reg [ 3:0] sdDqm,
input [31:0] sdDqIn,
output reg [31:0] sdDqOut,
output reg sdDqOeN
);
parameter IDLE = 0;
parameter PRE_CHARGE = 1;
parameter WAIT_FOR_RP = 2;
parameter AUTO_REFRESH = 3;
parameter LOAD_MODE = 4;
parameter ACTIVE = 5;
parameter RAS_TO_CAS = 6;
parameter READ_INIT = 7;
parameter WRITE_INIT = 8;
parameter CAS_LAT = 9;
parameter READ_DATA = 10;
parameter BURST_TERM = 11;
// controller engine state machine
always @ (posedge sdClk or negedge rstN) begin
if (!rstN) begin
presState <= IDLE;
brstCntr <= 9'd0;
counter <= 4'b0000;
rfshed <= 1'b0;
instrFifoRead <= 1'b0;
//sdClkE <= 2'b11;
sdWeNQ <= 1'b1;
sdCasN <= 1'b1;
sdRasN <= 1'b1;
sdCsN <= 1'b1;
sdA <= 12'd0;
sdBa <= 2'b00;
sdDqm <= 4'b1111;
sdDqOeN <= 1'b1;
accWasWrite <= 1'b0;
writing <= 1'b0;
initialize <= 1'b1;
end
else begin
writing <= 1'b0;
presState <= nextState; // state transition
accWasWrite <= accIsWrite;
rfshed <= 1'b0; // strobes
case (nextState)
IDLE : begin
sdCsN <= 1'b1;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
end
PRE_CHARGE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b1;
sdWeNQ <= 1'b0;
sdA[10] <= 1'b1; // all-bank precharge
counter <= {1'b0,rp}; // precharge command period
end
WAIT_FOR_RP: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
sdDqOeN <= 1'b1;
counter <= counter - 1'b1;
end
AUTO_REFRESH: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b0;
sdWeNQ <= 1'b1;
counter <= rfc; // minimum refresh period
rfshed <= 1'b1;
end
LOAD_MODE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b0;
sdWeNQ <= 1'b0;
sdA <= mode0val;
sdBa <= 2'b00;
initialize <= 1'b0;
end
ACTIVE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
// controlled by : row signal
sdBa <= accAddr[12:11]; // bank
sdA <= accAddr[24:13];
// Note that it is assumed that burst will be all on same row
// rowActive <= accAddr[24:13]; // record active row
counter <= rcd; // active to R/W delay
brstCntr <= 9'd0;
// lastPage <= accAddr[24:11]; // for page hit detection
end
RAS_TO_CAS: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
counter <= counter - 1'b1;
end
READ_INIT: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b0;
sdWeNQ <= 1'b1;
sdDqm <= sdDqm_c;
// Note that it is assumed that burst will be all on same row
// controlled by : col signal
sdBa <= accAddr[12:11]; // bank
sdA[10] <= 1'b0; // auto precharge disabled
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
counter <= {1'b0,cl - 1'b1}; // cas latency
end
WRITE_INIT: begin
writing <= 1'b1;
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b0;
sdWeNQ <= 1'b0;
sdDqm <= sdDqm_c;
// Note that it is assumed that burst will be all on same row
// controlled by : col signal
sdBa <= accAddr[12:11]; // bank
sdA[10] <= 1'b0; // auto precharge disabled
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
sdDqOeN <= 1'b0;
counter <= {1'b0,wr};
end
CAS_LAT: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
counter <= counter - 1'b1;
end
READ_DATA: begin
sdCsN <= 1'b0; // NOP
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b0000;
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
brstCntr <= brstCntr + 1'b1;
end
BURST_TERM: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b0;
sdDqm <= 4'b1111;
end
default: begin
sdCsN <= 1'b1;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
instrFifoRead <= 1'b0;
end
endcase
end
end
// next state calculation
always @ (*) begin
engRdDataRdy = 1'b0;
case (presState)
IDLE: begin
if(initialize)
nextState = PRECHRG;
else if(wr | rd)
nextState = ACTIVE;
else
nextState = IDLE;
end
PRE_CHARGE: begin
nextState = WAIT_FOR_RP;
end
WAIT_FOR_RP: begin
if (counter != 4'd0) nextState = WAIT_FOR_RP;
else begin
if (initialize)
nextState = AUTO_REFRESH;
else
nextState = IDLE;
end
end
AUTO_REFRESH: begin
if(counter != 4'd0)
nextState = AUTO_REFRESH;
else if(initialize)
nextState = LOAD_MODE;
else
nextState = IDLE;
end
LOAD_MODE: begin
nextState = IDLE;
end
ACTIVE: begin
nextState = RAS_TO_CAS;
end
RAS_TO_CAS: begin
if (counter != 4'd0) nextState = RAS_TO_CAS;
else begin
if (accIsWrite) nextState = WRITE_INIT;
else nextState = READ_INIT;
end
end
READ_INIT: begin
nextState = CAS_LAT;
end
WRITE_INIT: begin
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = WRITE_DATA;
end
CAS_LAT: begin
if (counter != 4'd0)
nextState = CAS_LAT;
else begin
engRdDataRdy = 1'b1;
nextState = READ_DATA;
end
end
READ_DATA: begin
engRdDataRdy = 1'b1;
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = READ_DATA;
end
WRITE_DATA: begin
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = WRITE_DATA;
end
BURST_TERM: begin
engRdDataRdy = 1'b0;
nextState = PRE_CHARGE;
end
default: begin
nextState = IDLE;
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: spu_lsurpt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module spu_lsurpt (
/*outputs*/
spu_lsurpt_ldxa_data_out,
spu_lsurpt_ldst_pckt_out,
spu_lsurpt_cpx_data_out,
/*inputs*/
spu_lsurpt_ldxa_data_in,
spu_lsurpt_ldst_pckt_in,
spu_lsurpt_cpx_data_in);
// ---------------------------------------------------------------------
input [63:0] spu_lsurpt_ldxa_data_in;
input [122:0] spu_lsurpt_ldst_pckt_in;
input [134:0] spu_lsurpt_cpx_data_in;
// ---------------------------------------------------------------------
output [63:0] spu_lsurpt_ldxa_data_out;
output [122:0] spu_lsurpt_ldst_pckt_out;
output [134:0] spu_lsurpt_cpx_data_out;
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
// port postion should be: input on the TOP and output on BOTTOM.
assign spu_lsurpt_ldxa_data_out[63:0] = spu_lsurpt_ldxa_data_in[63:0];
// ---------------------------------------------------------------------
// port postion should be: input on the TOP and output on BOTTOM.
assign spu_lsurpt_ldst_pckt_out[122:0] = spu_lsurpt_ldst_pckt_in[122:0];
// ---------------------------------------------------------------------
// port postion should be: input on the BOTTOM and output on TOP.
assign spu_lsurpt_cpx_data_out[134:0] = spu_lsurpt_cpx_data_in[134:0];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File : des_comp_gen.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_comp_gen
(
input clk,
input rstn,
input [31:0] dx_fx, // 16.16
input [31:0] dy_fx, // 16.16
input [95:0] cmp_i,
output [31:0] curr_i
);
wire [31:0] ix;
wire [31:0] iy;
wire [31:0] ixy;
flt_fx1616_mult u_flt_fx_mult_dx
(
.clk (clk),
.rstn (rstn),
.fx (dx_fx),
.bfl (cmp_i[63:32]),
.fl (ix)
);
flt_fx1616_mult u_flt_fx_mult_dy
(
.clk (clk),
.rstn (rstn),
.fx (dy_fx),
.bfl (cmp_i[31:0]),
.fl (iy)
);
flt_add_sub u_flt_add_subf_xy
(
.clk (clk),
.sub (1'b0),
.afl (ix),
.bfl (iy),
.fl (ixy)
);
flt_add_sub u_flt_add_subf_curr
(
.clk (clk),
.sub (1'b0),
.afl (cmp_i[95:64]),
.bfl (ixy),
.fl (curr_i)
);
endmodule
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSHIFT_TAPS
// ============================================================
// File Name: delay_5.v
// Megafunction Name(s):
// ALTSHIFT_TAPS
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module delay_5 (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [39:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [39:0] sub_wire1;
wire [7:0] shiftout = sub_wire0[7:0];
wire [39:0] taps = sub_wire1[39:0];
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.clken (clken),
.shiftin (shiftin),
.shiftout (sub_wire0),
.taps (sub_wire1)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone II",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 5,
ALTSHIFT_TAPS_component.tap_distance = 640,
ALTSHIFT_TAPS_component.width = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "5"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "640"
// Retrieval info: PRIVATE: WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "5"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "640"
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: shiftin 0 0 8 0 INPUT NODEFVAL "shiftin[7..0]"
// Retrieval info: USED_PORT: shiftout 0 0 8 0 OUTPUT NODEFVAL "shiftout[7..0]"
// Retrieval info: USED_PORT: taps 0 0 40 0 OUTPUT NODEFVAL "taps[39..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @shiftin 0 0 8 0 shiftin 0 0 8 0
// Retrieval info: CONNECT: shiftout 0 0 8 0 @shiftout 0 0 8 0
// Retrieval info: CONNECT: taps 0 0 40 0 @taps 0 0 40 0
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* $Date: 2012-09-08 20:51:57 -0400 (Sat, 08 Sep 2012) $ *)
Require Export x02Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** So far, only lists of numbers. But want lists of strings, booleans,
lists of lists, etc. Bad: define new inductive datatype for each: *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** Bad: would need new versions of list functions ([length], [rev], etc.)
for each new type. *)
(** Instead, use _polymorphic_ inductive type definitions: *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** Exactly like [natlist] definition except
- [nat] arg to [cons] replaced by arbitrary type [X],
- binding for [X] added to header,
- occurrences of [natlist] in constructor types replaced by [list X]. *)
(** [list] is a _function_ from [Type]s to [Inductive] definitions, or
[list] is a function from [Type]s to [Type]s.
For any type [X], the type [list X] is an [Inductive]ly defined
set of lists whose elements are of type [X]. *)
(** Observe types of these constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** "[forall X]" means : additional arg to constructors that
determines expected types of args that follow.
Type args supplied in same way as other args. *)
(** When using constructors [nil] / [cons] must pass type. *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(* ===> cons nat 2 (cons nat 1 (nil nat)) : list nat *)
(** Polymorphic (aka "generic") [length]. *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** [nil] and [cons] in [match] do not need type annotations:
already know that list contains elements of type [X].
Type [X] is parameter of whole definition of [list],
not individual constructors.
Use [length] by giving type then list arg: *)
Example test_length1 : length nat (cons nat 1 (cons nat 2 (nil nat ))) = 2.
Proof. reflexivity. Qed.
Example test_length2 : length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** More polymorphic list functions: *)
Fixpoint app (X : Type) (l1 l2 : list X) : (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat))) =
(cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2: rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** [app] without specifying types of args to [app]. *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
Check app'.
(* ===> app' : forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> app : forall X : Type, list X -> list X -> list X *)
(** [app'] same type as [app].
Uses _type inference_.
Since [X] is an argument to [cons], it must be a [Type]
since [cons] expects a [Type] as its first arg;
Matching [l1] with [nil] and [cons] means [l1] must be a [list]; etc.
No need to write explicit type annotations.
But useful as documentation.
Find balance to avoid readers doing type inference in their heads. *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Since second arg to poly [length] is list of [X]s then first arg
can only be [X].
In place of type argument can write "implicit argument" [_].
[_] uses _unification_ to determine concrete type
using all locally available information:
- type of function applied,
- types of other args,
- and type expected by context in which application appears
Type inference of function args:
app' (X : _) (l1 l2 : _) : list X :=
[length] with implicit arguments: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** [_] instead of [X] : not much saving.
But can be significant: *)
Definition list123 := cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _ ))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** Avoid [_].
To _always_ infer type arg(s) of given function: *)
Implicit Arguments nil [[X]].
Implicit Arguments cons [[X]].
Implicit Arguments length [[X]].
Implicit Arguments app [[X]].
Implicit Arguments rev [[X]].
Implicit Arguments snoc [[X]].
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check list123''.
(* ===> list123'' : list nat *)
Check (length list123'').
(* ===> length list123'' : nat *)
(** Alternate syntax:
Declare implicit argument by surrounding argument in curly braces.
Then not necessary to provide type arg to recursive call. *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** Style:
- curlies whenever possible;
- explicit [Implicit Argument] declarations for [Inductive] constructors. *)
(** Problem with declaring arguments [Implicit] :
When not enough local information, give arg explicitly "this" time,
even though declared globally to be [Implicit]: *)
(* Definition mynil := nil. *)
(** Uncomment [mynil] def and see error, since not known what type
arg to supply to [nil]. So give explicit type declaration to be
used during "application" of [nil]): *)
Definition mynil : list nat := nil.
(** Alternate: force implicit arguments to be explicit by prefixing
function name with [@]. *)
Check @nil.
(* ===> @nil : forall X : Type, list X *)
Definition mynil' := @nil nat.
Check mynil'.
(* ===> mynil' : list nat *)
(** Via arg synthesis + implicit args, can now define notation for lists.
Since constructor type arguments implicit, automatically infer types when notations used. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x , .. , y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
Definition list123''' := [1, 2, 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Fill in definitions and complete proofs. *)
Fixpoint repeat (X : Type) (n : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => n :: (repeat X n count')
end.
Example test_repeat1: repeat bool true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Fixpoint hc_repeat' {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => []
| S count' => n :: (hc_repeat' n count')
end.
Example test_hc_repeat2: hc_repeat' true 2 = [true, true].
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros X l. (* [] ++ l = l *)
simpl. (* l = l *)
reflexivity.
Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s. induction s as [| v' s'].
Case "s is []". (* rev (snoc [] v) = v :: rev [] *)
simpl. (* [v] = [v] *)
reflexivity.
Case "s is v'::s'". (* IHs' : rev (snoc s' v) = v :: rev s' *)
(* rev (snoc (v' :: s') v) = v :: rev (v' :: s') *)
simpl. (* snoc (rev (snoc s' v)) v' = v :: snoc (rev s') v' *)
rewrite -> IHs'. (* snoc (v :: rev s') v' = v :: snoc (rev s') v' *)
simpl. (* v :: snoc (rev s') v' = v :: snoc (rev s') v' *)
reflexivity.
Qed.
Theorem rev_involutive : forall (X : Type) (l : list X),
rev (rev l) = l.
Proof.
intros X l. induction l as [|n l'].
Case "l is []". simpl. reflexivity.
Case "l is n::l'". (* IHl' : rev (rev l') = l' *)
(* rev (rev (n :: l')) = n :: l' *)
simpl. (* rev (snoc (rev l') n) = n :: l' *)
rewrite -> rev_snoc. (* n :: rev (rev l') = n :: l' *)
rewrite -> IHl'. (* n :: l' = n :: l' *)
reflexivity.
Qed.
Theorem snoc_with_append : forall (X : Type) (l1 l2 : list X) (v : X),
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v. induction l1 as [| v' l1'].
Case "l1 is []". simpl. reflexivity.
Case "l1 is v'::l1'". (* IHl1' : snoc (l1' ++ l2) v = l1' ++ snoc l2 v *)
(* snoc ((v' :: l1') ++ l2) v = (v' :: l1') ++ snoc l2 v *)
simpl. (* v' :: snoc (l1' ++ l2) v = v' :: l1' ++ snoc l2 v *)
rewrite -> IHl1'. (* v' :: l1' ++ snoc l2 v = v' :: l1' ++ snoc l2 v *)
reflexivity.
Qed.
(* ###################################################### *)
(** ** Polymorphic Pairs *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Implicit Arguments pair [[X] [Y]].
Notation "( x , y )" := (pair x y).
(** Standard notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** [: type_scope] says: use abbrev when parsing types
(avoids clash with multiplication symbol). *)
(** Caution: can confuse [(x,y)] and [X*Y].
[(x,y)] is _value_ built from two other values;
[X*Y] is _type_ built from two other types.
Given [x : X] and [y : Y], [(x,y)] has type [X*Y]. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** [zip] : called [combine] for consistency with Coq's standard library. *)
(** Note pair notation used in exprs and patterns. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y) : list (X*Y) :=
match (lx,ly) with
| ( [], _) => []
| ( _, []) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** Can drop parens when no ambiguity: *)
Fixpoint combine' {X Y : Type} (lx : list X) (ly : list Y) : list (X*Y) :=
match lx,ly with
| [], _ => []
| _, [] => []
| x::tx, y::ty => (x,y) :: (combine' tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Answering on paper, check with coq:
- What is the type of [combine]
i.e., what does [Check @combine] print?
Paper:
combine : forall X : Type, forall Y : Type, list X -> list Y -> list(X*Y)
*)
Check @combine.
(* ===> combine : forall X Y : Type, list X -> list Y -> list (X * Y) *)
(**
- What does
Eval simpl in (combine [1,2] [false,false,true,true]).
print?
Paper: [(1,false), (2,false)]
*)
Eval simpl in (combine [1,2] [false,false,true,true]).
(* ===> = [(1, false), (2, false)] : list (nat * bool) *)
(** **** Exercise: 2 stars, recommended (split) *)
(** Define/test [split] (aka [unzip]) :
right inverse of combine: takes list of pairs, returns pair of lists. *)
Fixpoint split' {X Y : Type} (lxy : list (X*Y)) (lx : list X) (ly : list Y) : list X*list Y :=
match lxy with
| [] => pair (rev lx) (rev ly)
| (x,y)::lxy' => split' lxy' (x::lx) (y::ly)
end.
Definition split {X Y : Type} (lxy : list (X*Y)) : list X*list Y := split' lxy [] [].
Check @split'.
Check @split.
Eval compute in (split [(1,false),(2,false),(3,true)]).
(* ===> = ([1, 2, 3], [false, false, true]) : list nat * list bool *)
Example test_split: split [(1,false),(2,false)] = ([1,2],[false,false]).
Proof. reflexivity. Qed.
(* HC: Definition of split from coq stdlib (except A B type variables defined in Section/Variables).
Avoids the two accumulators and reverses
http://coq.inria.fr/V8.2pl1/stdlib/Coq.Lists.List.html
*)
Fixpoint coq_split {A B : Type} (l:list (A*B)) { struct l }: list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (g,d) := coq_split tl in (x::g, y::d)
end.
Example test_coq_split: coq_split [(1,false),(2,false)] = ([1,2],[false,false]).
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Polymorphic Options *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Implicit Arguments Some [[X]].
Implicit Arguments None [[X]].
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4,5,6,7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1],[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Write/test polymorphic version of [hd_opt] function. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| h::t => Some h
| _ => None
end.
(** Reminder: to force implicit arguments to be explicit, use [@]: *)
Check @hd_opt.
(* ===> hd_opt : forall X : Type, list X -> option X *)
Example test_hd_opt1 : hd_opt [1,2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1],[2]] = Some [1].
Proof. reflexivity. Qed.
Example test_hd_opt3 : hd_opt mynil' = None.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** _higher-order_ functions:
- functions passed as arguments,
- returned as results,
- stored in data structures,
-etc. *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** Multi-arg functions are examples of passing functions as data.
See type of [plus]: *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] is a _binary_ operator on types.
Coq only supports one-arg functions.
[->] is _right-associative_, so [plus] is really
[nat -> (nat -> nat)],
read as : [plus] is one-arg function that takes a [nat] and
returns a one-arg function that takes a [nat] and returns a [nat].
_partial application_ : supply only the first arg: *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, optional (currying) *)
(** Processing list of args with functions that return functions is
called _currying_, for logician Haskell Curry.
[f : A -> B -> C] has type [A -> (B -> C)].
[f] given a value of type [A] returns function [f' : B -> C].
[f'] given a value of type [B] returns a value of type [C].
Enables partial application.
_Uncurrying_. reinterpret type [A -> B -> C] as [(A * B) -> C].
With uncurried binary function, both args given at once as a pair;
there is no partial application. *)
(** Can define currying as: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z)
(x : X)
(y : Y) : Z := f (x, y).
(** Define inverse, [prod_uncurry].
Prove theorems to show the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z)
(p : X * Y) : Z := f (fst p) (snd p).
(** Thought exercise: before using coq,
calculate types of [prod_curry] and [prod_uncurry]. *)
(* HC: prod_curry : forall X Y Z : Type, f : X*Y->Z -> x:X -> y:Y -> Z *)
Check @prod_curry.
(* prod_curry : forall X Y Z : Type, (X * Y -> Z) -> X -> Y -> Z *)
(* HC: prod_uncurry : forall X Y Z : Type, (X->Y->Z) -> (X*Y) -> Z *)
Check @prod_uncurry.
(* prod_uncurry : forall X Y Z : Type, (X -> Y -> Z) -> X * Y -> Z *)
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros. (* prod_curry (prod_uncurry f) x y = f x y *)
unfold prod_curry. (* prod_uncurry f (x, y) = f x y *)
unfold prod_uncurry. (* f (fst (x, y)) (snd (x, y)) = f x y *)
simpl. (* f x y = f x y *)
reflexivity.
Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. (* prod_uncurry (prod_curry f) p = f p *)
unfold prod_curry. (* prod_uncurry (fun (x : X) (y : Y) => f (x, y)) p = f p *)
unfold prod_uncurry. (* f (fst p, snd p) = f p *)
destruct p as (n, m). (* f (fst (n, m), snd (n, m)) = f (n, m) *)
simpl. (* f (n, m) = f (n, m) *)
reflexivity.
Qed.
(* ###################################################### *)
(** ** Filter *)
(** higher-order function: given list of [X]s and _predicate_ on [X].
Returns new list containing elements for which predicate is [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
Example test_filter1: filter evenb [1,2,3,4] = [2,4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** [filter] version of [countoddmembers] from [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1,0,3,1,4,5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0,2,4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
Example test_anon_fun': doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Write [filter_even_gt7] (using [filter]) :
given list of nats
returns list of nats > 7 and even. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun x => andb (ble_nat 7 x) (evenb x)) l.
Eval compute in (filter_even_gt7 [1,2,6,9,10,3,12,8]).
Example test_filter_even_gt7_1 :
filter_even_gt7 [1,2,6,9,10,3,12,8] = [10,12,8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5,2,6,19,129] = [].
Proof. reflexivity. Qed.
(** **** Exercise: 3 stars (partition) *)
(** Using [filter], write:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given type [X], test predicate [X -> bool], and [list X].
Returns a pair of lists.
Fst has elements that satisfy test, Snd those that don't.
Order of elements in returned lists should be same as original.
*)
(* O(2n) version *)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1,2,3,4,5] = ([1,3,5], [2,4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5,9,0] = ([], [5,9,0]).
Proof. reflexivity. Qed.
(* HC: O(n) version *)
Fixpoint hc_partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
match l with
| [] => ([], [])
| h :: t => match test h with
| true => let (p,f) := hc_partition test t in (h::p, f)
| false => let (p,f) := hc_partition test t in ( p, h::f)
end
end.
Example test_hc_partition1: hc_partition oddb [1,2,3,4,5] = ([1,3,5], [2,4]).
Proof. reflexivity. Qed.
Example test_hc_partition2: hc_partition (fun x => false) [5,9,0] = ([], [5,9,0]).
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Map *)
(** Given [f] and [ l = [n1, n2, n3, ...] ]
returns [ [f n1, f n2, f n3,...] ]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
Example test_map1: map (plus 3) [2,0,2] = [5,3,5].
Proof. reflexivity. Qed.
(** Types of input/output need not be same (i.e., [map] has _two_ type arguments). *)
Example test_map2: map oddb [2,1,2,5] = [false,true,false,true].
Proof. reflexivity. Qed.
Example test_map3:
map (fun n => [evenb n,oddb n]) [2,1,2,5]
= [[true,false],[false,true],[true,false],[false,true]].
Proof. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (map_rev) *)
(** Prove [map] and [rev] commute (using auxiliary lemma). *)
(**
map o rev: [1, 2, 3] / [f1, f2, f3] / [f3, f2, f1]
rev o map: [1, 2, 3] / [ 3, 2, 1] / [f3, f2, f1]
*)
Lemma hc_map_lemma1_not_used : forall (X Y : Type) (f : X -> Y) (l : list X) (x : X),
(f x)::map f l = map f (x::l).
Proof.
intros. simpl. reflexivity. Qed.
(** from
https://github.com/joshcough/software-foundations/blob/master/Poly.v
*)
Lemma map_rev_helper : forall (X Y : Type) (f : X -> Y) (l : list X)(x : X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros X Y f l x. induction l as [| x' l'].
Case "l is []". simpl. reflexivity.
Case "l is x'::l'". (* IHl' : map f (snoc l' x) = snoc (map f l') (f x) *)
(* map f (snoc (x' :: l') x) = snoc (map f (x' :: l')) (f x) *)
simpl. (* f x' :: map f (snoc l' x) = f x' :: snoc (map f l') (f x) *)
rewrite -> IHl'. (* f x' :: snoc (map f l') (f x) = f x' :: snoc (map f l') (f x) *)
reflexivity.
Qed.
(** Given above, I did this myself. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros. induction l as [|n l'].
Case "l is []". simpl. reflexivity.
Case "l is n::l'". (* IHl' : map f (rev l') = rev (map f l') *)
(* map f (rev (n :: l')) = rev (map f (n :: l')) *)
simpl. (* map f (snoc (rev l') n) = snoc (rev (map f l')) (f n) *)
rewrite -> map_rev_helper. (* snoc (map f (rev l')) (f n) = snoc (rev (map f l')) (f n) *)
rewrite -> IHl'. (* snoc (rev (map f l')) (f n) = snoc (rev (map f l')) (f n) *)
reflexivity.
Qed.
(** **** Exercise: 2 stars, recommended (flat_map) *)
(** Write [flat_map]:
maps a [list X] to a [list Y] using [f] of type [X -> list Y].
Definition should flatten results of [f]:
flat_map (fun n => [n,n+1,n+2]) [1,5,10] = [1, 2, 3, 5, 6, 7, 10, 11, 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) ++ flat_map f t
end.
Example test_flat_map1:
flat_map (fun n => [n,n,n]) [1,5,4]
= [1, 1, 1, 5, 5, 5, 4, 4, 4].
Proof. reflexivity. Qed.
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(* TODO *)
(** Above definitions/uses of [filter]/[map] use implicit arguments in many places.
- Replace the curly braces around the implicit arguments with parentheses.
- Fill in explicit type parameters where necessary.
- Use Coq to check that you've done so correctly.
Do it on a _copy_ of this file. *)
(* ###################################################### *)
(** ** Fold *)
(** [fold]. Inspiration for "[reduce]" at heart of Google's map/reduce. *)
(** [fold] inserts binary operator [f] between every pair of elements.
[ fold plus [1,2,3,4] ] = [1+2+3+4].
Need starting element to be a second input to [f] at end of list.
fold plus [1,2,3,4] 0 = 1 + (2 + (3 + (4 + 0))).
*)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| [] => b
| h :: t => f h (fold f t b)
end.
Check (fold plus). (* fold plus : list nat -> nat -> nat *)
Eval simpl in (fold plus [1,2,3,4] 0). (* 10 : n *)
Example fold_example1 : fold mult [1,2,3,4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true,true,false,true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1],[],[2,3],[4]] [] = [1,2,3,4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (fold_types_different) *)
(** [fold] has _two_ type variables: operator [f] takes [X], [Y] returns [Y].
Describe use-case for [X] and [Y] to be different. *)
(**
fold f [x0, x1, x2] b = f x0 (f x1 (f x2 b))
where f = plus
f 0 (f 1 (f 2 [[0,0,0]]))
f 0 (f 1 [[2,0,2],[0,0,0]])
f 0 [[1,2,3],[2,0,2],[0,0,0]]
[[0,1,1],[1,2,3],[2,0,2],[0,0,0]]
TODO: the following should really use list nat*nat*nat.
*)
Definition hc_f_t_d (x : nat) (y : list (list nat)) : list (list nat) :=
match y with
| [y', _, _]::t => [x,y',x+y']::y
| _ => []
end.
Example test_hc_f_t_d1 : hc_f_t_d 2 [[0,0,0]] = [[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example test_hc_f_t_d2 : hc_f_t_d 1 [[2,0,2],[0,0,0]] = [[1,2,3],[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example test_hc_f_t_d3 : hc_f_t_d 0 [[1,2,3],[2,0,2],[0,0,0]] = [[0,1,1],[1,2,3],[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example hc_fold_types_different :
fold (fun x y => (hc_f_t_d x y))
[0,1,2]
[[0,0,0]] = [[0,1,1],[1,2,3],[2,0,2],[0,0,0]].
Proof. unfold fold. simpl. reflexivity. Qed.
Definition hc_f_t_d_g (X Y : Type) (f : X -> X -> X) (x : X) (y : list (list X))
: list (list X) :=
match y with
| [y', _, _]::t => [x,y',f x y']::y
| _ => []
end.
Example test_hc_f_t_d_g1 : hc_f_t_d_g nat (list (list nat)) plus 2 [[0,0,0]] = [[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example test_hc_f_t_d_g2 : hc_f_t_d_g nat (list (list nat)) plus 1 [[2,0,2],[0,0,0]] = [[1,2,3],[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example test_hc_f_t_d_g3 : hc_f_t_d_g nat (list (list nat)) plus 0 [[1,2,3],[2,0,2],[0,0,0]] = [[0,1,1],[1,2,3],[2,0,2],[0,0,0]].
Proof. simpl. reflexivity. Qed.
Example hc_fold_types_different_g1 :
fold (fun x y => (hc_f_t_d_g nat (list (list nat)) plus x y))
[0,1,2]
[[0,0,0]] = [[0,1,1],[1,2,3],[2,0,2],[0,0,0]].
Proof. unfold fold. simpl. reflexivity. Qed.
Example hc_fold_types_different_g3 :
fold (fun x y => (hc_f_t_d_g nat (list (list nat)) mult x y))
[1,2,3]
[[10,0,0]] = [[1,2,2],[2,3,6],[3,10,30],[10,0,0]].
Proof. unfold fold. unfold hc_f_t_d_g. simpl. reflexivity. Qed.
Example hc_fold_types_different_g4 :
fold (fun x y => (hc_f_t_d_g nat (list (list nat)) exp x y))
[1,2,3]
[[2,0,0]] = [[1,2,1],[2,3,8],[3,2,9],[2,0,0]].
Proof. unfold fold. unfold hc_f_t_d_g. simpl. reflexivity. Qed.
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Above: functions as _arguments_.
Now: _returning_ functions as results.
E.G.: given [x : X] returns function [nat->X].
Returned functions ignores its arg and always returns [x]. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** Returns function that behaves like [f]
except when called with arg [k] it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X :=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** E.G.: apply [override] twice gives function that
returns [false] on [1] and [3],
[true] otherwise. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star (override_example) *)
(** Paraphrase following theorem then prove.
Function constructed from [constfun] :
forall (b:bool) returns b.
Function constructed from [override] :
forall (n:nat) (b:bool) returns b except given 3 returns true.
Application : forall (b:bool) returns b because applied to 2 not equal to 3.
*)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. destruct b. reflexivity. reflexivity. Qed.
Theorem override_example_applied_to_3 : forall (b:bool),
(override (constfun b) 3 true) 3 = true.
Proof.
intros. destruct b. reflexivity. reflexivity. Qed.
(** Use overriding alot.
Need to know its properties.
To prove properties need to know more Coq tactics.
Main topic of the rest of chapter. *)
(* ##################################################### *)
(* ##################################################### *)
(** * Optional Material *)
(** ** Non-Uniform Inductive Families (GADTs) *)
(** Recall definition:
Inductive boollist : Type :=
boolnil : boollist
| boolcons : bool -> boollist -> boollist.
*)
(** That was generalized above to "polymorphic lists".
Another way of generalizing:
inductive family of "length-indexed" lists of booleans
(Note: names add additional 'l'): *)
Inductive boolllist : nat -> Type :=
boollnil : boolllist O
| boollcons : forall n, bool -> boolllist n -> boolllist (S n).
Implicit Arguments boollcons [[n]].
Check (boollcons true (boollcons false (boollcons true boollnil))).
Fixpoint blapp {n1} (l1: boolllist n1)
{n2} (l2: boolllist n2)
: boolllist (n1 + n2) :=
match l1 with
| boollnil => l2
| boollcons _ h t => boollcons h (blapp t l2)
end.
(** Generalizions can be combined: length-indexed polymorphic version: *)
Inductive llist (X:Type) : nat -> Type :=
lnil : llist X O
| lcons : forall n, X -> llist X n -> llist X (S n).
Implicit Arguments lnil [[X]].
Implicit Arguments lcons [[X] [n]].
Check (lcons true (lcons false (lcons true lnil))).
Fixpoint lapp (X:Type)
{n1} (l1: llist X n1)
{n2} (l2: llist X n2)
: llist X (n1 + n2) :=
match l1 with
| lnil => l2
| lcons _ h t => lcons h (lapp X t l2)
end.
(* ###################################################### *)
(** * More About Coq *)
(* ###################################################### *)
(** ** The [apply] Tactic *)
(** When goal to be proved is same as a hypothesis in context
or previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n,o] = [n,p] ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2. (* [n, o] = [m, p] *)
rewrite <- eq1. (* [n, o] = [n, p] *)
(* Could finish by: *)
(* rewrite -> eq2. [n, p] = [n, p]
reflexivity.
Same effect in single step using [apply]: *)
apply eq2.
Qed.
(** When [apply] used with _conditional_ hypotheses and lemmas,
premises added as subgoals. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q,o] = [r,p]) ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2. (* [n, o] = [m, p] *) (* QUESTION *)
apply eq2. (* n = m *)
apply eq1.
Qed.
(** Version with [rewrite]: *)
(** TODO: is it possible?
Theorem hc_silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q,o] = [r,p]) ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2.
rewrite -> eq1.
*)
(** Often in [apply H], [H] begins with [forall].
To match current goal with conclusion of [H]
must find values for quantified variables.
E.G: [apply eq2] in following,
[q] in [eq2] gets instantiated with [n] and
[r] gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2. (* [n] = [m] *)
apply eq2. (* (n, n) = (m, m) *)
apply eq1.
Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete without using [simpl]: *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros eq1 eq2. (* oddb 4 = true *)
apply eq1. (* evenb 3 = true *)
apply eq2.
Qed.
(** To use [apply], conclusion of the fact being applied must match the goal.
E.G.: [apply] no good if left and right sides of equality are swapped: *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H. (* beq_nat (S (S n)) 7 = true *)
simpl. (* beq_nat n 5 = true *)
(* Here we cannot use [apply] directly *)
Admitted.
(** Use [symmetry] tactic to switch left/right sides of an equality in goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H. (* beq_nat (S (S n)) 7 = true *)
symmetry. (* true = beq_nat (S (S n)) 7 *)
(* [simpl] not necessary. [apply] will do a [simpl] step first. *)
simpl. (* true = beq_nat n 5 *)
apply H.
Qed.
(** **** Exercise: 3 stars, recommended (apply_exercise1) *)
(* Hint: use [apply] with previously defined lemmas besides
hypotheses in the context. Remember [SearchAbout]. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' -> l' = rev l.
Proof.
intros l l' H. (* l' = rev l *)
symmetry. (* rev l = l' *)
rewrite -> H. (* rev (rev l') = l' *)
(* rewrite -> rev_involutive. l' = l' *)
apply rev_involutive.
Qed.
(** **** Exercise: 1 star (apply_rewrite) *)
(** Explain the difference between [apply] and [rewrite].
HC:
- [apply] does several steps: [simpl], [rewrite], [reflexivity]
- [rewrite] does not involve other steps
Are there situations where both can usefully be applied?
Yes: see rev_exercise1 above.
*)
(* ###################################################### *)
(** ** The [unfold] Tactic *)
(* RIGHT HERE JULY *)
(** In proof process, not all function calls expanded into definitions
(so proofs do not become unwieldy and slow). *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* Want [rewrite -> H] here since [plus3 n] is definitionally equal to [3 + n].
But [plus3 n] not expanded automatically. *)
Admitted.
(** [unfold] tactic replaces defined name with definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H. (* plus3 n + 1 = m + 1 *)
unfold plus3. (* 3 + n + 1 = m + 1 *)
rewrite -> H. (* m + 1 = m + 1 *)
reflexivity.
Qed.
(** Proof (using [unfold]) of property of [override]:
If we override a function at some argument [k] to return [x]
and then look up [k],
we get back [x]. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f. (* override f k x k = x *)
unfold override. (* (if beq_nat k k then x else f k) = x *)
rewrite <- beq_nat_refl. (* x = x *)
reflexivity.
Qed.
(** **** Exercise: 2 stars (override_neq) *)
(** When the function returned from override is given a [k] that is
NOT the overriden number it returns [f] applied to [k]. *)
Theorem override_neq : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros. (* override f k2 x2 k1 = x1 *)
unfold override. (* (if beq_nat k2 k1 then x2 else f k1) = x1 *)
rewrite -> H. (* (if beq_nat k2 k1 then x2 else x1) = x1 *)
rewrite -> H0. (* x1 = x1 *)
reflexivity.
Qed.
(** Inverse of [unfold] is [fold]. Used less often. *)
(* ###################################################### *)
(** ** Inversion *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
Every number has one of two forms.
Implicit in definition are two other facts:
- Constructor [S] is _injective_: [S n = S m] iff [n = m].
- Constructors [O] and [S] are _disjoint_: [O] not equal to [S n] for any [n]. *)
(** Principles apply to all inductively defined types:
- all constructors are injective
- values built from distinct constructors are never equal.
E.G.:
[cons] is injective and [nil] is different from every non-empty list.
[true] and [false] are unequal. (Since neither [true] nor [false]
take any arguments, their injectivity is not an issue.) *)
(** [inversion] tactic exploits these principles.
Suppose [H] is hypothesis in context or a previously proven lemma
of the form
c a1 a2 ... an = d b1 b2 ... bm
for constructors [c], [d] and args [a1 ... an], [b1 ... bm].
Then [inversion H] says "invert" this equality to extract
information it contains about terms:
- If [c], [d] same constructor, then, by injectivity of constructor,
[a1 = b1], [a2 = b2], etc.;
[inversion H] adds these facts to context, and tries to use them
to rewrite goal.
- If [c], [d] different constructors, then hypothesis [H] is contradictory.
A false assumption has crept into context, meaning any goal provable!
In this case, [inversion H] marks current goal as completed
and pops it off goal stack. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. (* n = m *)
inversion eq. (* m = m ; adds and uses H0 : n = m *)
reflexivity.
Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. (* n = o *)
inversion eq. (* o = o ; adds and uses H0 : n = o *)
reflexivity.
Qed.
(** [inversion] can also destruct equalities between complex values,
binding multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n,m] = [o,o] ->
[n] = [m].
Proof.
intros n m o eq. (* [n] = [m] *)
inversion eq. (* [o] = [o] ; adds and uses H0 : n = o H1 : m = o *)
reflexivity.
Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros. (* x = y *)
inversion H0. (* x = x ; add and uses H2 : y = x H3 : l = j *)
reflexivity.
Qed.
(* TODO: since this is proved, you could accidently use it? *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
Eval simpl in (@nil nat :: @nil nat :: []).
(* ===> = [[], []] : list (list nat) *)
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros X x y z l j contra eq2.
inversion contra.
Qed.
(** Injectivity of constructors proves [forall (n m : nat), S n = S m -> n = m].
Reverse direction (provable by standard equational reasoning) is a useful fact. *)
Lemma eq_remove_S : forall n m,
n = m -> S n = S m.
Proof.
intros n m eq. (* S n = S m *)
rewrite -> eq. (* S m = S m *)
reflexivity.
Qed.
(** Another way of proving length_snoc (from Lists).
Extra equalities force more equational reasoning and use of tactics. *)
(** TODO: understand this better *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l']. (* IHl' : forall n : nat, length l' = n -> length (snoc l' v) = S n *)
Case "l = []". (* forall n : nat, length [] = n -> length (snoc [] v) = S n *)
intros n eq. (* length (snoc [] v) = S n *)
rewrite <- eq. (* length (snoc [] v) = S (length []) *)
simpl. (* 1 = 1 *)
reflexivity.
Case "l = v' :: l'".
intros n eq. (* length (snoc (v' :: l') v) = S n *)
simpl. (* S (length (snoc l' v)) = S n *)
destruct n as [| n'].
SCase "n = 0". (* S (length (snoc l' v)) = 1 *)
inversion eq.
SCase "n = S n'". (* S (length (snoc l' v)) = S (S n') *)
apply eq_remove_S. (* length (snoc l' v) = S n' *)
apply IHl'. (* length l' = n' *)
inversion eq. (* length l' = length l' *)
reflexivity.
Qed.
(* ###################################################### *)
(** ** Varying the Induction Hypothesis *)
(** Use of inversion useful in many places: *)
Theorem beq_nat_eq_FAILED : forall n m,
true = beq_nat n m -> n = m.
Proof.
intros n m H. (* This is the BAD step - too much intros *)
induction n as [| n'].
Case "n = 0". (* 0 = m *)
destruct m as [| m'].
SCase "m = 0". (* 0 = 0 *)
reflexivity.
SCase "m = S m'". (* 0 = S m' *)
simpl in H. (* H : true = beq_nat 0 (S m') changes to: H : true = false *)
inversion H.
Case "n = S n'". (* S n' = m *)
destruct m as [| m'].
SCase "m = 0". (* S n' = 0 *)
simpl in H. (* H : true = beq_nat (S n') 0 changes to: H : true = false *)
inversion H.
SCase "m = S m'". (* S n' = S m' *)
apply eq_remove_S. (* n' = m' *)
(* stuck here because the induction hypothesis
talks about an extremely specific m *)
Admitted.
(** Inductive proof above fails because proof set up
induction hypothesis as
[ true = beq_nat n' m -> n' = m ].
Hypothesis talks about [n'] and _particular_ natural number [m] --
the number [m] is "held constant" in the induction hypothesis. This
induction hypothesis not strong enough to work.
Solution: set up proof differently: introduce just [n].
Then we get stronger induction hypothesis :
[ forall m : nat, true = beq_nat n' m -> n' = m ]
Now proof of [beq_nat_eq] goes through: *)
Theorem beq_nat_eq : forall n m,
true = beq_nat n m -> n = m.
Proof.
intros n. (* This is the GOOD step - only intro [n] now, [m] later *)
induction n as [| n']. (* IHn' : forall m : nat, true = beq_nat n' m -> n' = m *)
Case "n = 0". (* forall m : nat, true = beq_nat 0 m -> 0 = m *)
intros m. (* true = beq_nat 0 m -> 0 = m *)
destruct m as [| m'].
SCase "m = 0". (* true = beq_nat 0 0 -> 0 = 0 *)
simpl. (* true = true -> 0 = 0 *)
reflexivity.
SCase "m = S m'". (* true = beq_nat 0 (S m') -> 0 = S m' *)
simpl. (* true = false -> 0 = S m' *)
intros contra. (* 0 = S m' ; contra: true = false *)
inversion contra.
Case "n = S n'". (* forall m : nat, true = beq_nat (S n') m -> S n' = m *)
intros m. (* true = beq_nat (S n') m -> S n' = m *)
destruct m as [| m'].
SCase "m = 0". (* true = beq_nat (S n') 0 -> S n' = 0 *)
simpl. (* true = false -> S n' = 0 *)
intros contra. (* S n' = 0 ; contra: true = false *)
inversion contra.
SCase "m = S m'". (* true = beq_nat (S n') (S m') -> S n' = S m' *)
simpl. (* true = beq_nat n' m' -> S n' = S m' *)
intros H. (* S n' = S m' ; H : true = beq_nat n' m' *)
apply eq_remove_S. (* n' = m' *)
apply IHn'. (* true = beq_nat n' m' *)
apply H.
Qed.
(** Similar issues in _many_ of proofs below.
When in situation where induction hypothesis is insufficient to establish goal,
consider going back and doing fewer [intros] to make the IH stronger. *)
(* TODO *)
(** **** Exercise: 2 stars (beq_nat_eq_informal) *)
(** Give an informal proof of [beq_nat_eq]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (beq_nat_eq') *)
(** Prove beq_nat_eq by induction on [m].
Be careful about when and order of [intro] of variables to get a general enough induction hypothesis.
Try to prove without looking back at one above. *)
Theorem beq_nat_eq' : forall m n,
beq_nat n m = true -> n = m.
Proof.
intros m. (* forall n : nat, beq_nat n m = true -> n = m *)
induction m as [| m'].
Case "m is 0". (* forall n : nat, beq_nat n 0 = true -> n = 0 *)
intros n. (* beq_nat n 0 = true -> n = 0 *)
destruct n as [| n'].
SCase "n is 0". (* beq_nat 0 0 = true -> 0 = 0 *)
reflexivity.
SCase "n is S n'". (* beq_nat (S n') 0 = true -> S n' = 0 *)
simpl. (* false = true -> S n' = 0 *)
intro contra. (* S n' = 0 ; contra : false = true *)
inversion contra.
Case "m is S m'". (* forall n : nat, beq_nat n (S m') = true -> n = S m' *)
intros n. (* beq_nat n (S m') = true -> n = S m' *)
destruct n as [| n'].
SCase "n is 0". (* beq_nat 0 (S m') = true -> 0 = S m' *)
simpl. (* false = true -> 0 = S m' *)
intro contra. (* 0 = S m' ; contra : false = true *)
inversion contra.
SCase "n is S n'". (* beq_nat (S n') (S m') = true -> S n' = S m' *)
simpl. (* beq_nat n' m' = true -> S n' = S m' *)
intros H. (* S n' = S m' ; H : beq_nat n' m' = true *)
apply eq_remove_S. (* n' = m' *)
apply IHm'. (* beq_nat n' m' = true *)
apply H.
Qed.
(* ###################################################### *)
(** *** Practice Session *)
(** **** Exercise: 2 stars, optional (practice) *)
(** May involve applying lemmas from earlier lectures or homeworks. *)
Theorem beq_nat_0_l : forall n,
true = beq_nat 0 n -> 0 = n.
Proof.
intros n H. destruct n as [| n'].
Case "n is 0". reflexivity.
Case "n is S n'". (* 0 = S n' ; H : true = beq_nat 0 (S n') *)
simpl in H. (* 0 = S n' ; H : true = false *)
inversion H.
Qed.
Theorem beq_nat_0_r : forall n,
(* true = beq_nat 0 n -> 0 = n. file originally contained this, but probably means: *)
true = beq_nat n 0 -> n = 0.
Proof.
intros n H. destruct n as [| n'].
Case "n is 0". reflexivity.
Case "n is S n'". (* S n' = 0 ; H : true = beq_nat (S n') 0 *)
simpl in H. (* S n' = 0 ; H : true = false *)
inversion H.
Qed.
(** **** Exercise: 3 stars (apply_exercise2) *)
(** Next don't introduce [m] before [induction].
This makes IH general : does not specify a particular [m], pick later.
Finish proof. *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n. induction n as [| n']. (* IHn' : forall m : nat, beq_nat n' m = beq_nat m n' *)
Case "n is 0". (* forall m : nat, beq_nat 0 m = beq_nat m 0 *)
intro m. (* beq_nat 0 m = beq_nat m 0 *)
destruct m as [| m'].
SCase "m is 0". reflexivity.
SCase "m is S m'". (* beq_nat 0 (S m') = beq_nat (S m') 0 *)
simpl. (* false = false *)
reflexivity.
Case "n is S n'". (* forall m : nat, beq_nat (S n') m = beq_nat m (S n') *)
intro m. (* beq_nat (S n') m = beq_nat m (S n') *)
destruct m as [| m'].
SCase "m is 0". (* beq_nat (S n') 0 = beq_nat 0 (S n') *)
simpl. (* false = false *)
reflexivity.
SCase "m is S m'". (* beq_nat (S n') (S m') = beq_nat (S m') (S n') *)
simpl. (* beq_nat n' m' = beq_nat m' n' *)
rewrite IHn'. (* beq_nat m' n' = beq_nat m' n' *)
reflexivity.
Qed.
(** **** Exercise: 3 stars (beq_nat_sym_informal) *)
(* TODO *)
(** Give informal proof following (corresponds to formal proof above):
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(* ###################################################### *)
(** ** Using Tactics on Hypotheses *)
(** Default: most tactics work on goal.
Most tactics have variant that work on statement in the context.
E.G., tactic [simpl in H] does simplification of hypothesis named
[H] in context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. (* beq_nat n m = b ; H : beq_nat (S n) (S m) = b *)
simpl in H. (* beq_nat n m = b ; H : beq_nat n m = b *)
apply H.
Qed.
(** Tactic [apply L in H] matches conditional statement [L]
(of the form [L1 -> L2], say) against [H] in the context.
[apply L in H] matches [H] against [L1] and replaces it [L2] if successful.
[apply L in H] gives form of "forward reasoning":
from [L1 -> L2] and hypothesis matching [L1]
gives hypothesis matching [L2].
Ordinary [apply] rewrites a goal matching [L2] into a subgoal [L1].
[apply L] is "backward reasoning":
if [L1->L2] known and trying to prove [L2], suffices to prove [L1].
Variant of previous proof using forward reasoning throughout: *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H. (* true = beq_nat (S (S n)) 7 ; H : true = beq_nat n 5 *)
symmetry in H. (* true = beq_nat (S (S n)) 7 ; H : beq_nat n 5 = true *)
apply eq in H. (* true = beq_nat (S (S n)) 7 ; H : beq_nat (S (S n)) 7 = true *)
symmetry in H. (* true = beq_nat (S (S n)) 7 ; H : true = beq_nat (S (S n)) 7 *)
apply H.
Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached.
Backward reasoning starts from the _goal_, and iteratively reasons
about what would imply the goal, until premises or previously
proven theorems are reached.
Most informal proofs in math or CS class use forward reasoning.
Coq tends to favor backward reasoning, but sometimes forward style
easier to use/think about. *)
(** **** Exercise: 3 stars, recommended (plus_n_n_injective) *)
(** You can practice using the "in" variants in this exercise.
Hint: use [plus_n_Sm: forall n m : nat, S (n + m) = n + S m]. *)
(* TODO *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n is 0". (* forall m : nat, 0 + 0 = m + m -> 0 = m *)
intros m.
simpl.
destruct m as [| m'].
SCase "m is 0". reflexivity.
SCase "m is S m'". (* 0 = S m' + S m' -> 0 = S m' *)
intro contra.
simpl in contra.
inversion contra.
Case "n is S n'". (* forall m : nat, S n' + S n' = m + m -> S n' = m *)
intros m.
destruct m as [| m'].
SCase "m is 0".
intros contra.
simpl in contra.
inversion contra.
SCase "m is S m'". (* S n' + S n' = S m' + S m' -> S n' = S m' *)
intros H.
rewrite <- IHn'.
rewrite <- plus_n_Sm in H.
rewrite <- plus_n_Sm in H at 1.
apply eq_remove_S in H.
simpl in H.
Admitted.
(* ###################################################### *)
(** ** Using [destruct] on Compound Expressions *)
(** [destruct] used above for case analysis of value of a variable.
Can use [destruct] to reason by cases on result of an _expression_ too. *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false".
destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity.
Qed.
(** Above, unfold [sillyfun] resulting in [if (beq_nat n 3) then ... else ...].
Use [destruct (beq_nat n 3)] to reason about two cases:
[n] is equal to [3] or not equal. *)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros. unfold override.
destruct (beq_nat k1 k2).
Case "beq_nat k1 k2 = true". reflexivity.
Case "beq_nat k1 k2 = false". reflexivity.
Qed.
(** **** Exercise: 3 stars, recommended (combine_split) *)
(* RIGHT HERE *)
(* combine == zip; split == unzip *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l. induction l as [| [x y] l'].
Case "l is []".
destruct l1.
SCase "l1 is []".
simpl.
destruct l2.
SSCase "l2 is []".
reflexivity.
SSCase "l2 is y::l2".
Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (split_combine) *)
(** Thought exercise: We have just proven that for all lists of pairs,
[combine] is the inverse of [split]. How would you state the
theorem showing that [split] is the inverse of [combine]?
Hint: what property do you need of [l1] and [l2] for [split]
[combine l1 l2 = (l1,l2)] to be true?
State this theorem in Coq, and prove it. (Be sure to leave your
induction hypothesis general by not doing [intros] on more things
than necessary.) *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################### *)
(** ** The [remember] Tactic *)
(** (Note: the [remember] tactic is not strictly needed until a
bit later, so if necessary this section can be skipped and
returned to when needed.) *)
(** We have seen how the [destruct] tactic can be used to
perform case analysis of the results of arbitrary computations.
If [e] is an expression whose type is some inductively defined
type [T], then, for each constructor [c] of [T], [destruct e]
generates a subgoal in which all occurrences of [e] (in the goal
and in the context) are replaced by [c].
Sometimes, however, this substitution process loses information
that we need in order to complete the proof. For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Admitted.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep at
least one of these because we need to be able to reason that
since, in this branch of the case analysis, [beq_nat n 3 = true],
it must be that [n = 3], from which it follows that [n] is odd.
What we would really like is not to use [destruct] directly on
[beq_nat n 3] and substitute away all occurrences of this
expression, but rather to use [destruct] on something else that is
_equal_ to [beq_nat n 3]. For example, if we had a variable that
we knew was equal to [beq_nat n 3], we could [destruct] this
variable instead.
The [remember] tactic allows us to introduce such a variable. *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
remember (beq_nat n 3) as e3.
(* At this point, the context has been enriched with a new
variable [e3] and an assumption that [e3 = beq_nat n 3].
Now if we do [destruct e3]... *)
destruct e3.
(* ... the variable [e3] gets substituted away (it
disappears completely) and we are left with the same
state as at the point where we got stuck above, except
that the context still contains the extra equality
assumption -- now with [true] substituted for [e3] --
which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_eq in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the
body of the function we are reasoning about, we can
use [remember] again in the same way, allowing us
to finish the proof. *)
remember (beq_nat n 5) as e5. destruct e5.
SCase "e5 = true".
apply beq_nat_eq in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall {X:Type} x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (filter_exercise) *)
(** This one is a bit challenging. Be sure your initial [intros] go
only up through the parameter on which you want to do
induction! *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall {X:Type} (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c,d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: apply trans_eq with [c,d]. *)
(** **** Exercise: 3 stars, recommended (apply_exercises) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_trans : forall n m p,
true = beq_nat n m ->
true = beq_nat m p ->
true = beq_nat n p.
Proof.
(* FILL IN HERE *) Admitted.
Theorem override_permute : forall {X:Type} x1 x2 k1 k2 k3 (f : nat->X),
false = beq_nat k2 k1 ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics -- enough to
do pretty much everything we'll want for a while. We'll introduce
one or two more as we go along through the next few lectures, and
later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [remember (e) as x]:
give a name ([x]) to an expression ([e]) so that we can
destruct [x] without "losing" [e]
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternate definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4,7,0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
(* FILL IN HERE *) admit.
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
(* FILL IN HERE *)
(** [] *)
Module MumbleBaz.
(** **** Exercise: 2 stars, optional (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
[] *)
(** **** Exercise: 2 stars, optional (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
[] *)
End MumbleBaz.
(** **** Exercise: 4 stars, recommended (forall_exists_challenge) *)
(** Challenge problem: Define two recursive [Fixpoints],
[forallb] and [existsb]. The first checks whether every
element in a list satisfies a given predicate:
forallb oddb [1,3,5,7,9] = true
forallb negb [false,false] = true
forallb evenb [0,2,4,5] = false
forallb (beq_nat 5) [] = true
The function [existsb] checks whether there exists an element in
the list that satisfies a given predicate:
existsb (beq_nat 5) [0,2,3,6] = false
existsb (andb true) [true,true,false] = true
existsb oddb [1,0,0,0,0,3] = true
existsb evenb [] = false
Next, create a _nonrecursive_ [Definition], [existsb'], using
[forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X (S n) l = None.
(* FILL IN HERE *)
*)
(** [] *)
|
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// IP VLNV: xilinx.com:hls:set:1.0
// IP Revision: 1602022136
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_set_0_0 (
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
ap_return,
m_axi_gmem_AWADDR,
m_axi_gmem_AWLEN,
m_axi_gmem_AWSIZE,
m_axi_gmem_AWBURST,
m_axi_gmem_AWLOCK,
m_axi_gmem_AWREGION,
m_axi_gmem_AWCACHE,
m_axi_gmem_AWPROT,
m_axi_gmem_AWQOS,
m_axi_gmem_AWVALID,
m_axi_gmem_AWREADY,
m_axi_gmem_WDATA,
m_axi_gmem_WSTRB,
m_axi_gmem_WLAST,
m_axi_gmem_WVALID,
m_axi_gmem_WREADY,
m_axi_gmem_BRESP,
m_axi_gmem_BVALID,
m_axi_gmem_BREADY,
m_axi_gmem_ARADDR,
m_axi_gmem_ARLEN,
m_axi_gmem_ARSIZE,
m_axi_gmem_ARBURST,
m_axi_gmem_ARLOCK,
m_axi_gmem_ARREGION,
m_axi_gmem_ARCACHE,
m_axi_gmem_ARPROT,
m_axi_gmem_ARQOS,
m_axi_gmem_ARVALID,
m_axi_gmem_ARREADY,
m_axi_gmem_RDATA,
m_axi_gmem_RRESP,
m_axi_gmem_RLAST,
m_axi_gmem_RVALID,
m_axi_gmem_RREADY,
data,
key,
val_r
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl start" *)
input wire ap_start;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl done" *)
output wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl idle" *)
output wire ap_idle;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl ready" *)
output wire ap_ready;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 ap_return DATA" *)
output wire [31 : 0] ap_return;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWADDR" *)
output wire [31 : 0] m_axi_gmem_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWLEN" *)
output wire [7 : 0] m_axi_gmem_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWSIZE" *)
output wire [2 : 0] m_axi_gmem_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWBURST" *)
output wire [1 : 0] m_axi_gmem_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWLOCK" *)
output wire [1 : 0] m_axi_gmem_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWREGION" *)
output wire [3 : 0] m_axi_gmem_AWREGION;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWCACHE" *)
output wire [3 : 0] m_axi_gmem_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWPROT" *)
output wire [2 : 0] m_axi_gmem_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWQOS" *)
output wire [3 : 0] m_axi_gmem_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWVALID" *)
output wire m_axi_gmem_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWREADY" *)
input wire m_axi_gmem_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WDATA" *)
output wire [31 : 0] m_axi_gmem_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WSTRB" *)
output wire [3 : 0] m_axi_gmem_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WLAST" *)
output wire m_axi_gmem_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WVALID" *)
output wire m_axi_gmem_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WREADY" *)
input wire m_axi_gmem_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BRESP" *)
input wire [1 : 0] m_axi_gmem_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BVALID" *)
input wire m_axi_gmem_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BREADY" *)
output wire m_axi_gmem_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARADDR" *)
output wire [31 : 0] m_axi_gmem_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARLEN" *)
output wire [7 : 0] m_axi_gmem_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARSIZE" *)
output wire [2 : 0] m_axi_gmem_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARBURST" *)
output wire [1 : 0] m_axi_gmem_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARLOCK" *)
output wire [1 : 0] m_axi_gmem_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARREGION" *)
output wire [3 : 0] m_axi_gmem_ARREGION;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARCACHE" *)
output wire [3 : 0] m_axi_gmem_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARPROT" *)
output wire [2 : 0] m_axi_gmem_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARQOS" *)
output wire [3 : 0] m_axi_gmem_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARVALID" *)
output wire m_axi_gmem_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARREADY" *)
input wire m_axi_gmem_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RDATA" *)
input wire [31 : 0] m_axi_gmem_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RRESP" *)
input wire [1 : 0] m_axi_gmem_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RLAST" *)
input wire m_axi_gmem_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RVALID" *)
input wire m_axi_gmem_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RREADY" *)
output wire m_axi_gmem_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 data DATA" *)
input wire [31 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 key DATA" *)
input wire [31 : 0] key;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 val_r DATA" *)
input wire [31 : 0] val_r;
set #(
.C_M_AXI_GMEM_ID_WIDTH(1),
.C_M_AXI_GMEM_ADDR_WIDTH(32),
.C_M_AXI_GMEM_DATA_WIDTH(32),
.C_M_AXI_GMEM_AWUSER_WIDTH(1),
.C_M_AXI_GMEM_ARUSER_WIDTH(1),
.C_M_AXI_GMEM_WUSER_WIDTH(1),
.C_M_AXI_GMEM_RUSER_WIDTH(1),
.C_M_AXI_GMEM_BUSER_WIDTH(1),
.C_M_AXI_GMEM_USER_VALUE('H00000000),
.C_M_AXI_GMEM_PROT_VALUE('B000),
.C_M_AXI_GMEM_CACHE_VALUE('B0011)
) inst (
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.ap_return(ap_return),
.m_axi_gmem_AWID(),
.m_axi_gmem_AWADDR(m_axi_gmem_AWADDR),
.m_axi_gmem_AWLEN(m_axi_gmem_AWLEN),
.m_axi_gmem_AWSIZE(m_axi_gmem_AWSIZE),
.m_axi_gmem_AWBURST(m_axi_gmem_AWBURST),
.m_axi_gmem_AWLOCK(m_axi_gmem_AWLOCK),
.m_axi_gmem_AWREGION(m_axi_gmem_AWREGION),
.m_axi_gmem_AWCACHE(m_axi_gmem_AWCACHE),
.m_axi_gmem_AWPROT(m_axi_gmem_AWPROT),
.m_axi_gmem_AWQOS(m_axi_gmem_AWQOS),
.m_axi_gmem_AWUSER(),
.m_axi_gmem_AWVALID(m_axi_gmem_AWVALID),
.m_axi_gmem_AWREADY(m_axi_gmem_AWREADY),
.m_axi_gmem_WID(),
.m_axi_gmem_WDATA(m_axi_gmem_WDATA),
.m_axi_gmem_WSTRB(m_axi_gmem_WSTRB),
.m_axi_gmem_WLAST(m_axi_gmem_WLAST),
.m_axi_gmem_WUSER(),
.m_axi_gmem_WVALID(m_axi_gmem_WVALID),
.m_axi_gmem_WREADY(m_axi_gmem_WREADY),
.m_axi_gmem_BID(1'B0),
.m_axi_gmem_BRESP(m_axi_gmem_BRESP),
.m_axi_gmem_BUSER(1'B0),
.m_axi_gmem_BVALID(m_axi_gmem_BVALID),
.m_axi_gmem_BREADY(m_axi_gmem_BREADY),
.m_axi_gmem_ARID(),
.m_axi_gmem_ARADDR(m_axi_gmem_ARADDR),
.m_axi_gmem_ARLEN(m_axi_gmem_ARLEN),
.m_axi_gmem_ARSIZE(m_axi_gmem_ARSIZE),
.m_axi_gmem_ARBURST(m_axi_gmem_ARBURST),
.m_axi_gmem_ARLOCK(m_axi_gmem_ARLOCK),
.m_axi_gmem_ARREGION(m_axi_gmem_ARREGION),
.m_axi_gmem_ARCACHE(m_axi_gmem_ARCACHE),
.m_axi_gmem_ARPROT(m_axi_gmem_ARPROT),
.m_axi_gmem_ARQOS(m_axi_gmem_ARQOS),
.m_axi_gmem_ARUSER(),
.m_axi_gmem_ARVALID(m_axi_gmem_ARVALID),
.m_axi_gmem_ARREADY(m_axi_gmem_ARREADY),
.m_axi_gmem_RID(1'B0),
.m_axi_gmem_RDATA(m_axi_gmem_RDATA),
.m_axi_gmem_RRESP(m_axi_gmem_RRESP),
.m_axi_gmem_RLAST(m_axi_gmem_RLAST),
.m_axi_gmem_RUSER(1'B0),
.m_axi_gmem_RVALID(m_axi_gmem_RVALID),
.m_axi_gmem_RREADY(m_axi_gmem_RREADY),
.data(data),
.key(key),
.val_r(val_r)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_b.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
`ifdef insert_emu_mux_inst_ba
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ba = 1'b0;
`endif
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
`ifdef insert_emu_mux_inst_bb
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_bb = 1'b0;
`endif
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`default_nettype none
`include "core.h"
module execute_mul(
input wire [4:0] iCMD,
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [31:0] oDATA,
output wire [4:0] oFLAGS
);
wire [63:0] mul_tmp;
wire mul_sf_l;
wire mul_cf_l;
wire mul_of_l;
wire mul_pf_l;
wire mul_zf_l;
wire mul_sf_h;
wire mul_cf_h;
wire mul_of_h;
wire mul_pf_h;
wire mul_zf_h;
assign mul_tmp = iDATA_0 * iDATA_1;
assign mul_sf_l = mul_tmp[31];
assign mul_cf_l = mul_tmp[32];
assign mul_of_l = mul_tmp[31] ^ mul_tmp[32];
assign mul_pf_l = mul_tmp[0];
assign mul_zf_l = (mul_tmp == {64{1'b0}})? 1'b1 : 1'b0;
assign mul_sf_h = mul_tmp[63];
assign mul_cf_h = 1'b0;
assign mul_of_h = 1'b0;
assign mul_pf_h = mul_tmp[32];
assign mul_zf_h = (mul_tmp == {64{1'b0}})? 1'b1 : 1'b0;
assign oFLAGS = (iCMD == `EXE_MUL_MULH || iCMD == `EXE_MUL_UMULH)? {mul_sf_h, mul_of_h, mul_cf_h, mul_pf_h, mul_zf_h} : {mul_sf_l, mul_of_l, mul_cf_l, mul_pf_l, mul_zf_l};
assign oDATA = (iCMD == `EXE_MUL_MULH || iCMD == `EXE_MUL_UMULH)? mul_tmp[63:32] : mul_tmp[31:0];
endmodule
`default_nettype wire
|
module lcd
(
input wire clk,
output reg [4:0] ctl,
output reg [7:0] data
);
localparam RW = 0;
localparam RS = 1;
localparam ON = 2;
localparam EN = 3;
localparam BLON = 4;
localparam INITIAL = 0;
localparam LINE1 = 5;
localparam CHLINE = LINE1 + 16;
localparam LINE2 = CHLINE + 1;
localparam SIZE = LINE2 + 16;
reg [8:0] chr[SIZE];
reg [63:0] cnt;
integer pos, state, i;
initial begin
for (i = 0; i < SIZE; i = i + 1)
chr[i] = 9'h141 - LINE1 + i;
chr[CHLINE] = 9'h0C0;
chr[INITIAL+0] = 9'h038;
chr[INITIAL+1] = 9'h00C;
chr[INITIAL+2] = 9'h001;
chr[INITIAL+3] = 9'h006;
chr[INITIAL+4] = 9'h080;
cnt <= 0;
pos <= 0;
state <= 0;
end
always @* begin
ctl[RW] <= 0;
ctl[ON] <= 1;
ctl[BLON] <= 1;
end
always @ (posedge clk) begin
if (pos < SIZE) begin
case (state)
0: begin
ctl[EN] <= 1;
ctl[RS] <= chr[pos][8];
data <= chr[pos][7:0];
cnt <= 0;
state <= 1;
end
1: begin
if (cnt < 16)
cnt <= cnt + 1;
else begin
ctl[EN] <= 0;
cnt <= 0;
state <= 2;
end
end
2: begin
if (cnt < 'h3FFFE)
cnt <= cnt + 1;
else begin
pos <= pos + 1;
state <= 0;
end
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [7:0] saveram_base_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// REG (generic)
output [7:0] reg_group_out,
output [7:0] reg_index_out,
output [7:0] reg_value_out,
output [7:0] reg_invmask_out,
output reg_we_out,
output [7:0] reg_read_out,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [10:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// feature enable
output reg [15:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [9:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 10'b0000000000;
dspx_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] group_out_buf; initial group_out_buf = 8'hFF;
reg [7:0] index_out_buf; initial index_out_buf = 8'hFF;
reg [7:0] value_out_buf; initial value_out_buf = 8'hFF;
reg [7:0] invmask_out_buf; initial invmask_out_buf = 8'hFF;
reg [7:0] group_read_buf; initial group_read_buf = 8'hFF;
reg [7:0] index_read_buf; initial index_read_buf = 8'hFF;
reg [7:0] temp_read_buf; initial temp_read_buf = 8'hFF;
reg reg_we_buf; initial reg_we_buf = 0;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
reg [7:0] feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [7:0] SAVERAM_BASE; initial SAVERAM_BASE = 0;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
if (cmd_data[0]) SAVERAM_BASE[7:0] <= param_data;
else SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[9:8] <= param_data[1:0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
dspx_pgm_addr_out <= 11'b00000000000;
dspx_dat_addr_out <= 10'b0000000000;
end
endcase
end
8'he9:// write DSPx PGM w/ increment
case (spi_byte_cnt)
32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
32'h5: dspx_pgm_we_out <= 1'b1;
32'h6: begin
dspx_pgm_we_out <= 1'b0;
dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
end
endcase
8'hea:// write DSPx DAT w/ increment
case (spi_byte_cnt)
32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
32'h4: dspx_dat_we_out <= 1'b1;
32'h5: begin
dspx_dat_we_out <= 1'b0;
dspx_dat_addr_out <= dspx_dat_addr_out + 1;
end
endcase
8'heb: // control DSPx reset
dspx_reset_out <= param_data[0];
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
case (spi_byte_cnt)
32'h2: feat_tmp <= param_data;
32'h3: featurebits_out <= {feat_tmp, param_data};
endcase
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
8'hfa: // handles all group, index, value, invmask writes. unit is responsible for decoding group for match
case (spi_byte_cnt)
32'h2: begin
group_out_buf <= param_data;
end
32'h3: begin
index_out_buf <= param_data;
end
32'h4: begin
value_out_buf <= param_data;
end
32'h5: begin
invmask_out_buf <= param_data;
reg_we_buf <= 1;
end
32'h6: begin
reg_we_buf <= 0;
group_out_buf <= 8'hFF;
index_out_buf <= 8'hFF;
value_out_buf <= 8'hFF;
invmask_out_buf <= 8'hFF;
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
else if (cmd_data[7:0] == 8'hF9)
case (spi_byte_cnt)
32'h2: begin
group_read_buf <= param_data;
end
32'h3: begin
index_read_buf <= param_data;
end
32'h4: begin
//if (group_read_buf == 8'h01) MCU_DATA_IN_BUF <= trc_config_data_in;
//else
MCU_DATA_IN_BUF <= 0;
end
endcase
else if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign saveram_base_out = SAVERAM_BASE;
assign reg_group_out = group_out_buf;
assign reg_index_out = index_out_buf;
assign reg_value_out = value_out_buf;
assign reg_invmask_out = invmask_out_buf;
assign reg_we_out = reg_we_buf;
assign reg_read_out = index_read_buf;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
module top(
input rx,
input [15:0] sw,
output [15:0] led,
output tx
);
wire [0:0] LIOB33_SING_X0Y0_IOB_X0Y0_O;
wire [0:0] LIOB33_X0Y111_IOB_X0Y111_O;
wire [0:0] LIOB33_X0Y111_IOB_X0Y112_I;
wire [0:0] LIOB33_X0Y11_IOB_X0Y11_I;
wire [0:0] LIOB33_X0Y11_IOB_X0Y12_I;
wire [0:0] LIOB33_X0Y17_IOB_X0Y18_O;
wire [0:0] LIOB33_X0Y19_IOB_X0Y19_O;
wire [0:0] LIOB33_X0Y19_IOB_X0Y20_O;
wire [0:0] LIOB33_X0Y1_IOB_X0Y1_O;
wire [0:0] LIOB33_X0Y1_IOB_X0Y2_O;
wire [0:0] LIOB33_X0Y3_IOB_X0Y3_O;
wire [0:0] LIOB33_X0Y3_IOB_X0Y4_O;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_O;
wire [0:0] LIOB33_X0Y5_IOB_X0Y5_I;
wire [0:0] LIOB33_X0Y5_IOB_X0Y6_I;
wire [0:0] LIOB33_X0Y7_IOB_X0Y7_I;
wire [0:0] LIOB33_X0Y7_IOB_X0Y8_I;
wire [0:0] LIOB33_X0Y9_IOB_X0Y10_I;
wire [0:0] LIOB33_X0Y9_IOB_X0Y9_I;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_D1;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_OQ;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_T1;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_D;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_O;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_D;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_O;
wire [0:0] LIOI3_X0Y111_ILOGIC_X0Y112_D;
wire [0:0] LIOI3_X0Y111_ILOGIC_X0Y112_O;
wire [0:0] LIOI3_X0Y111_OLOGIC_X0Y111_D1;
wire [0:0] LIOI3_X0Y111_OLOGIC_X0Y111_OQ;
wire [0:0] LIOI3_X0Y111_OLOGIC_X0Y111_T1;
wire [0:0] LIOI3_X0Y111_OLOGIC_X0Y111_TQ;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y11_D;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y11_O;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y12_D;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y12_O;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_D1;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_OQ;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_T1;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_TQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_D1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_OQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_T1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_TQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_D1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_OQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_T1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_TQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_D1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_OQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_T1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_TQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_D1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_OQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_T1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_TQ;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y5_D;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y5_O;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y6_D;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y6_O;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y10_D;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y10_O;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y9_D;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y9_O;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERECRCCHECKEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERECRCGENEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRCORRERRRECEIVED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRCORRERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRFATALERRRECEIVED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRFATALERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRNONFATALERRRECEIVED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRNONFATALERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGBRIDGESERREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDBUSMASTERENABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDINTERRUPTDISABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDIOENABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDMEMENABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDSERREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ARIFORWARDEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ATOMICEGRESSBLOCK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ATOMICREQUESTEREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTDIS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2IDOCPLEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2IDOREQEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2LTREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2TLPPREFIXBLOCK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLAUXPOWEREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLCORRERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLENABLERO;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLEXTTAGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLFATALERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLNONFATALREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLNOSNOOPEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLPHANTOMEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLURERRREPORTINGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSCORRERRDETECTED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSFATALERRDETECTED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSNONFATALERRDETECTED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSURDETECTED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRACSN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG100;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG101;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG102;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG103;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG104;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG105;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG106;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG107;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG108;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG109;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG110;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG111;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG112;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG113;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG114;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG115;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG116;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG117;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG118;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG119;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG120;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG121;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG122;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG123;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG124;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG125;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG126;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG127;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG68;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG69;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG70;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG71;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG72;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG73;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG74;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG75;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG76;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG77;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG78;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG79;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG80;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG81;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG82;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG83;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG84;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG85;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG86;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG87;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG88;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG89;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG90;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG91;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG92;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG93;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG94;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG95;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG96;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG97;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG98;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG99;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOGSETN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRATOMICEGRESSBLOCKEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCORN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLABORTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLRDYN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLTIMEOUTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLUNEXPECTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRECRCN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRINTERNALCORN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRINTERNALUNCORN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRLOCKEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRMALFORMEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRMCBLOCKEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRNORECOVERYN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRPOISONEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRPOSTEDN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRURN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCECOMMONCLOCKOFF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEEXTENDEDSYNCON;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTASSERTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIENABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIXENABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIXFM;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTRDYN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTSTATN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLASPMCONTROL0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLASPMCONTROL1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLAUTOBANDWIDTHINTEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLBANDWIDTHINTEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLCLOCKPMEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLCOMMONCLOCK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLEXTENDEDSYNC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLHWAUTOWIDTHDIS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLLINKDISABLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLRCB;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLRETRAINLINK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSBANDWIDTHSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSCURRENTSPEED0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSCURRENTSPEED1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSDLLACTIVE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSLINKTRAINING;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTRDENN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTRDWRDONEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRENN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRREADONLYN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRRW1CASRWN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTA;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTB;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTA;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTB;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRCOR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRFATAL;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRNONFATAL;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMASNAK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMETO;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMETOACK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMPME;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDUNLOCK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPMEEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPMESTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPOWERSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPOWERSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATEENN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMHALTASPML0SN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMHALTASPML1N;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVASREQL1N;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVENTERL1N;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVENTERL23N;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVREQACKN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMSENDPMETON;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMTURNOFFOKN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMWAKEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLPMEINTEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRCORRERREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRFATALERREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRNONFATALERREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSLOTCONTROLELECTROMECHILCTLPULSE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTION;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONTYPE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRNPENDINGN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CMRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_CMSTICKYRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGMODE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGMODE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRA;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRB;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRG;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRH;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRI;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRJ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSUBMODE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DLRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPCLK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_DRPWE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_FUNCLVLRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2BADDLLPERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2BADTLPERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2PROTOCOLERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2RECEIVERERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2REPLAYROERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2REPLAYTOERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDASREQL1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDENTERL1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDENTERL23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDPMACK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SUSPENDNOW;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SUSPENDOK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TFCINIT1SEQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TFCINIT2SEQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TLPRCV;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TXIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_LNKCLKEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA68;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXREN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA68;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPECLK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHANISALIGNED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7PHYSTATUS;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7POLARITY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7VALID;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7CHARISK0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7CHARISK1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7COMPLIANCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7ELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7POWERDOWN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7POWERDOWN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXDEEMPH;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRATE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRCVRDET;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRESET;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2L0REQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2LINKUP;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RECEIVERERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RECOVERY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXELECIDLE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXPMSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXPMSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PL2SUSPENDOK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDCHANGEDONE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKAUTON;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKCHANGE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKCHANGE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKSPEED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKWIDTH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKWIDTH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEWVLD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMSTALL;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLDOWNSTREAMDEEMPHSOURCE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLANEREVERSALMODE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLANEREVERSALMODE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKGEN2CAP;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKPARTNERGEN2SUPPORTED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKUPCFGCAP;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLPHYLNKUPN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLRECEIVEDHOTRST;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLRXPMSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLRXPMSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKRATE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKWIDTH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKWIDTH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLTRANSMITHOTRST;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_PLUPSTREAMPREFERDEEMPH;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_RECEIVEDFUNCLVLRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_SYSRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDCREDITCHECK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDCREDITCHECKOK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDREQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRFCPE;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRMALFORMED;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRRXOVERFLOW;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2PPMSUSPENDOK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TL2PPMSUSPENDREQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TLRSTN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNLNKUP;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD100;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD101;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD102;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD103;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD104;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD105;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD106;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD107;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD108;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD109;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD110;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD111;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD112;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD113;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD114;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD115;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD116;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD117;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD118;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD119;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD120;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD121;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD122;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD123;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD124;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD125;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD126;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD127;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD68;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD69;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD70;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD71;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD72;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD73;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD74;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD75;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD76;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD77;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD78;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD79;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD80;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD81;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD82;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD83;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD84;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD85;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD86;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD87;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD88;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD89;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD90;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD91;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD92;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD93;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD94;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD95;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD96;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD97;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD98;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD99;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPSRCRDY0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPSRCRDY1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDSTRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRECRCERR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNREOF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRERRFWD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRFCPRET;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRNPOK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRNPREQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRREM0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRREM1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSOF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSRCDSC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSRCRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTCFGGNT;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTCFGREQ;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD100;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD101;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD102;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD103;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD104;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD105;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD106;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD107;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD108;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD109;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD110;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD111;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD112;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD113;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD114;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD115;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD116;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD117;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD118;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD119;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD120;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD121;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD122;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD123;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD124;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD125;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD126;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD127;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD32;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD33;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD34;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD35;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD36;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD37;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD38;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD39;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD40;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD41;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD42;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD43;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD44;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD45;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD46;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD47;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD48;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD49;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD50;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD51;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD52;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD53;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD54;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD55;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD56;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD57;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD58;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD59;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD60;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD61;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD62;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD63;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD64;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD65;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD66;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD67;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD68;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD69;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD70;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD71;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD72;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD73;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD74;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD75;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD76;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD77;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD78;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD79;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD80;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD81;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD82;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD83;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD84;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD85;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD86;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD87;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD88;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD89;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD90;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD91;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD92;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD93;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD94;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD95;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD96;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD97;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD98;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD99;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA10;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA11;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA12;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA13;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA14;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA15;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA16;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA17;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA18;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA19;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA20;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA21;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA22;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA23;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA24;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA25;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA26;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA27;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA28;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA29;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA30;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA31;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA4;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA5;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA6;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA7;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA8;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA9;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDSTRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPSRCRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY3;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTECRCGEN;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTEOF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTERRDROP;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTERRFWD;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTREM0;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTREM1;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSOF;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSRCDSC;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSRCRDY;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSTR;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_USERCLK;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_USERCLK2;
wire [0:0] PCIE_BOT_X71Y115_PCIE_X0Y0_USERRSTN;
wire [0:0] RIOB33_X43Y31_IOB_X1Y32_O;
wire [0:0] RIOB33_X43Y37_IOB_X1Y37_O;
wire [0:0] RIOB33_X43Y37_IOB_X1Y38_O;
wire [0:0] RIOB33_X43Y39_IOB_X1Y39_I;
wire [0:0] RIOB33_X43Y39_IOB_X1Y40_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y43_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y44_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y45_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y46_I;
wire [0:0] RIOB33_X43Y47_IOB_X1Y47_I;
wire [0:0] RIOB33_X43Y47_IOB_X1Y48_I;
wire [0:0] RIOB33_X43Y61_IOB_X1Y61_O;
wire [0:0] RIOB33_X43Y75_IOB_X1Y75_O;
wire [0:0] RIOB33_X43Y75_IOB_X1Y76_O;
wire [0:0] RIOB33_X43Y87_IOB_X1Y87_O;
wire [0:0] RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_D1;
wire [0:0] RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_OQ;
wire [0:0] RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_T1;
wire [0:0] RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_TQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_D1;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_OQ;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_T1;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_TQ;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_D1;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_OQ;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_T1;
wire [0:0] RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_TQ;
wire [0:0] RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_D1;
wire [0:0] RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_OQ;
wire [0:0] RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_T1;
wire [0:0] RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_TQ;
wire [0:0] RIOI3_X43Y39_ILOGIC_X1Y39_D;
wire [0:0] RIOI3_X43Y39_ILOGIC_X1Y39_O;
wire [0:0] RIOI3_X43Y39_ILOGIC_X1Y40_D;
wire [0:0] RIOI3_X43Y39_ILOGIC_X1Y40_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_O;
wire [0:0] RIOI3_X43Y47_ILOGIC_X1Y47_D;
wire [0:0] RIOI3_X43Y47_ILOGIC_X1Y47_O;
wire [0:0] RIOI3_X43Y47_ILOGIC_X1Y48_D;
wire [0:0] RIOI3_X43Y47_ILOGIC_X1Y48_O;
wire [0:0] RIOI3_X43Y61_OLOGIC_X1Y61_D1;
wire [0:0] RIOI3_X43Y61_OLOGIC_X1Y61_OQ;
wire [0:0] RIOI3_X43Y61_OLOGIC_X1Y61_T1;
wire [0:0] RIOI3_X43Y61_OLOGIC_X1Y61_TQ;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y75_D1;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y75_OQ;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y75_T1;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y75_TQ;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y76_D1;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y76_OQ;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y76_T1;
wire [0:0] RIOI3_X43Y75_OLOGIC_X1Y76_TQ;
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y1_IOB_X0Y1_OBUF (
.I(LIOB33_X0Y5_IOB_X0Y6_I),
.O(led[7])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y1_IOB_X0Y2_OBUF (
.I(RIOB33_X43Y39_IOB_X1Y40_I),
.O(led[8])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y3_IOB_X0Y3_OBUF (
.I(PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY),
.O(led[0])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y3_IOB_X0Y4_OBUF (
.I(LIOB33_X0Y7_IOB_X0Y8_I),
.O(led[5])
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y5_IOB_X0Y5_IBUF (
.I(sw[6]),
.O(LIOB33_X0Y5_IOB_X0Y5_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y5_IOB_X0Y6_IBUF (
.I(sw[7]),
.O(LIOB33_X0Y5_IOB_X0Y6_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y7_IOB_X0Y7_IBUF (
.I(sw[4]),
.O(LIOB33_X0Y7_IOB_X0Y7_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y7_IOB_X0Y8_IBUF (
.I(sw[5]),
.O(LIOB33_X0Y7_IOB_X0Y8_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y9_IOB_X0Y9_IBUF (
.I(sw[3]),
.O(LIOB33_X0Y9_IOB_X0Y9_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y9_IOB_X0Y10_IBUF (
.I(sw[2]),
.O(LIOB33_X0Y9_IOB_X0Y10_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y11_IOB_X0Y11_IBUF (
.I(sw[0]),
.O(LIOB33_X0Y11_IOB_X0Y11_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y11_IOB_X0Y12_IBUF (
.I(sw[1]),
.O(LIOB33_X0Y11_IOB_X0Y12_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y17_IOB_X0Y18_OBUF (
.I(LIOB33_X0Y7_IOB_X0Y7_I),
.O(led[4])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y19_IOB_X0Y19_OBUF (
.I(LIOB33_X0Y9_IOB_X0Y9_I),
.O(led[3])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y19_IOB_X0Y20_OBUF (
.I(LIOB33_X0Y9_IOB_X0Y10_I),
.O(led[2])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y43_IOB_X0Y43_OBUF (
.I(LIOB33_X0Y11_IOB_X0Y12_I),
.O(led[1])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y111_IOB_X0Y111_OBUF (
.I(LIOB33_X0Y111_IOB_X0Y112_I),
.O(tx)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y111_IOB_X0Y112_IBUF (
.I(rx),
.O(LIOB33_X0Y111_IOB_X0Y112_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_SING_X0Y0_IOB_X0Y0_OBUF (
.I(LIOB33_X0Y5_IOB_X0Y5_I),
.O(led[6])
);
(* KEEP, DONT_TOUCH, BEL = "PCIE_2_1" *)
PCIE_2_1 #(
.AER_BASE_PTR(12'b000000000000),
.AER_CAP_ECRC_CHECK_CAPABLE("FALSE"),
.AER_CAP_ECRC_GEN_CAPABLE("FALSE"),
.AER_CAP_ID(16'b0000000000000000),
.AER_CAP_MULTIHEADER("FALSE"),
.AER_CAP_NEXTPTR(12'b000000000000),
.AER_CAP_ON("FALSE"),
.AER_CAP_OPTIONAL_ERR_SUPPORT(24'b000000000000000000000000),
.AER_CAP_PERMIT_ROOTERR_UPDATE("FALSE"),
.AER_CAP_VERSION(4'b0000),
.ALLOW_X8_GEN2("FALSE"),
.BAR0(32'b00000000000000000000000000000000),
.BAR1(32'b00000000000000000000000000000000),
.BAR2(32'b00000000000000000000000000000000),
.BAR3(32'b00000000000000000000000000000000),
.BAR4(32'b00000000000000000000000000000000),
.BAR5(32'b00000000000000000000000000000000),
.CAPABILITIES_PTR(8'b00000000),
.CARDBUS_CIS_POINTER(32'b00000000000000000000000000000000),
.CFG_ECRC_ERR_CPLSTAT(2'b00),
.CLASS_CODE(24'b000000000000000000000000),
.CMD_INTX_IMPLEMENTED("FALSE"),
.CPL_TIMEOUT_DISABLE_SUPPORTED("FALSE"),
.CPL_TIMEOUT_RANGES_SUPPORTED(4'b0000),
.CRM_MODULE_RSTS(7'b0000000),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED("FALSE"),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED("FALSE"),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED("FALSE"),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED("FALSE"),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(2'b00),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING("FALSE"),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED(2'b00),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE("FALSE"),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE("FALSE"),
.DEV_CAP_ENDPOINT_L0S_LATENCY(3'b000),
.DEV_CAP_ENDPOINT_L1_LATENCY(3'b000),
.DEV_CAP_EXT_TAG_SUPPORTED("FALSE"),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE("FALSE"),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(3'b000),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(2'b00),
.DEV_CAP_ROLE_BASED_ERROR("FALSE"),
.DEV_CAP_RSVD_14_12(3'b000),
.DEV_CAP_RSVD_17_16(2'b00),
.DEV_CAP_RSVD_31_29(3'b000),
.DEV_CONTROL_AUX_POWER_SUPPORTED("FALSE"),
.DEV_CONTROL_EXT_TAG_DEFAULT("FALSE"),
.DISABLE_ASPM_L1_TIMER("FALSE"),
.DISABLE_BAR_FILTERING("FALSE"),
.DISABLE_ERR_MSG("FALSE"),
.DISABLE_ID_CHECK("FALSE"),
.DISABLE_LANE_REVERSAL("FALSE"),
.DISABLE_LOCKED_FILTER("FALSE"),
.DISABLE_PPM_FILTER("FALSE"),
.DISABLE_RX_POISONED_RESP("FALSE"),
.DISABLE_RX_TC_FILTER("FALSE"),
.DISABLE_SCRAMBLING("FALSE"),
.DNSTREAM_LINK_NUM(8'b00000000),
.DSN_BASE_PTR(12'b000000000000),
.DSN_CAP_ID(16'b0000000000000000),
.DSN_CAP_NEXTPTR(12'b000000000000),
.DSN_CAP_ON("FALSE"),
.DSN_CAP_VERSION(4'b0000),
.ENABLE_MSG_ROUTE(11'b00000000000),
.ENABLE_RX_TD_ECRC_TRIM("FALSE"),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED("FALSE"),
.ENTER_RVRY_EI_L0("FALSE"),
.EXIT_LOOPBACK_ON_EI("FALSE"),
.EXPANSION_ROM(32'b00000000000000000000000000000000),
.EXT_CFG_CAP_PTR(6'b000000),
.EXT_CFG_XP_CAP_PTR(10'b0000000000),
.HEADER_TYPE(8'b00000000),
.INFER_EI(5'b00000),
.INTERRUPT_PIN(8'b00000000),
.INTERRUPT_STAT_AUTO("FALSE"),
.IS_SWITCH("FALSE"),
.LAST_CONFIG_DWORD(10'b0000000000),
.LINK_CAP_ASPM_OPTIONALITY("FALSE"),
.LINK_CAP_ASPM_SUPPORT(2'b00),
.LINK_CAP_CLOCK_POWER_MANAGEMENT("FALSE"),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP("FALSE"),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(3'b000),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(3'b000),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1(3'b000),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2(3'b000),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(3'b000),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(3'b000),
.LINK_CAP_L1_EXIT_LATENCY_GEN1(3'b000),
.LINK_CAP_L1_EXIT_LATENCY_GEN2(3'b000),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP("FALSE"),
.LINK_CAP_MAX_LINK_SPEED(4'b0000),
.LINK_CAP_MAX_LINK_WIDTH(6'b001000),
.LINK_CAP_RSVD_23(1'b0),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE("FALSE"),
.LINK_CONTROL_RCB(1'b0),
.LINK_CTRL2_DEEMPHASIS("FALSE"),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE("FALSE"),
.LINK_CTRL2_TARGET_LINK_SPEED(4'b0000),
.LINK_STATUS_SLOT_CLOCK_CONFIG("FALSE"),
.LL_ACK_TIMEOUT(15'b000000000000000),
.LL_ACK_TIMEOUT_EN("FALSE"),
.LL_ACK_TIMEOUT_FUNC(2'b00),
.LL_REPLAY_TIMEOUT(15'b000000000000000),
.LL_REPLAY_TIMEOUT_EN("FALSE"),
.LL_REPLAY_TIMEOUT_FUNC(2'b00),
.LTSSM_MAX_LINK_WIDTH(6'b000000),
.MPS_FORCE("FALSE"),
.MSIX_BASE_PTR(8'b00000000),
.MSIX_CAP_ID(8'b00000000),
.MSIX_CAP_NEXTPTR(8'b00000000),
.MSIX_CAP_ON("FALSE"),
.MSIX_CAP_PBA_BIR(3'b000),
.MSIX_CAP_PBA_OFFSET(29'b00000000000000000000000000000),
.MSIX_CAP_TABLE_BIR(3'b000),
.MSIX_CAP_TABLE_OFFSET(29'b00000000000000000000000000000),
.MSIX_CAP_TABLE_SIZE(11'b00000000000),
.MSI_BASE_PTR(8'b00000000),
.MSI_CAP_64_BIT_ADDR_CAPABLE("FALSE"),
.MSI_CAP_ID(8'b00000000),
.MSI_CAP_MULTIMSGCAP(3'b000),
.MSI_CAP_MULTIMSG_EXTENSION(1'b0),
.MSI_CAP_NEXTPTR(8'b00000000),
.MSI_CAP_ON("FALSE"),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE("FALSE"),
.N_FTS_COMCLK_GEN1(8'b11111111),
.N_FTS_COMCLK_GEN2(8'b11111111),
.N_FTS_GEN1(8'b11111111),
.N_FTS_GEN2(8'b11111111),
.PCIE_BASE_PTR(8'b00000000),
.PCIE_CAP_CAPABILITY_ID(8'b00000000),
.PCIE_CAP_CAPABILITY_VERSION(4'b0000),
.PCIE_CAP_DEVICE_PORT_TYPE(4'b0000),
.PCIE_CAP_NEXTPTR(8'b00000000),
.PCIE_CAP_ON("FALSE"),
.PCIE_CAP_RSVD_15_14(2'b00),
.PCIE_CAP_SLOT_IMPLEMENTED("FALSE"),
.PCIE_REVISION(4'b0010),
.PL_AUTO_CONFIG(3'b000),
.PL_FAST_TRAIN("FALSE"),
.PM_ASPML0S_TIMEOUT(15'b000000000000000),
.PM_ASPML0S_TIMEOUT_EN("FALSE"),
.PM_ASPML0S_TIMEOUT_FUNC(2'b00),
.PM_ASPM_FASTEXIT("FALSE"),
.PM_BASE_PTR(8'b00000000),
.PM_CAP_AUXCURRENT(3'b000),
.PM_CAP_D1SUPPORT("FALSE"),
.PM_CAP_D2SUPPORT("FALSE"),
.PM_CAP_DSI("FALSE"),
.PM_CAP_ID(8'b00000000),
.PM_CAP_NEXTPTR(8'b00000000),
.PM_CAP_ON("FALSE"),
.PM_CAP_PMESUPPORT(5'b00000),
.PM_CAP_PME_CLOCK("FALSE"),
.PM_CAP_RSVD_04(1'b0),
.PM_CAP_VERSION(3'b011),
.PM_CSR_B2B3("FALSE"),
.PM_CSR_BPCCEN("FALSE"),
.PM_CSR_NOSOFTRST("FALSE"),
.PM_DATA0(8'b00000000),
.PM_DATA1(8'b00000000),
.PM_DATA2(8'b00000000),
.PM_DATA3(8'b00000000),
.PM_DATA4(8'b00000000),
.PM_DATA5(8'b00000000),
.PM_DATA6(8'b00000000),
.PM_DATA7(8'b00000000),
.PM_DATA_SCALE0(2'b00),
.PM_DATA_SCALE1(2'b00),
.PM_DATA_SCALE2(2'b00),
.PM_DATA_SCALE3(2'b00),
.PM_DATA_SCALE4(2'b00),
.PM_DATA_SCALE5(2'b00),
.PM_DATA_SCALE6(2'b00),
.PM_DATA_SCALE7(2'b00),
.PM_MF("FALSE"),
.RBAR_BASE_PTR(12'b000000000000),
.RBAR_CAP_CONTROL_ENCODEDBAR0(5'b00000),
.RBAR_CAP_CONTROL_ENCODEDBAR1(5'b00000),
.RBAR_CAP_CONTROL_ENCODEDBAR2(5'b00000),
.RBAR_CAP_CONTROL_ENCODEDBAR3(5'b00000),
.RBAR_CAP_CONTROL_ENCODEDBAR4(5'b00000),
.RBAR_CAP_CONTROL_ENCODEDBAR5(5'b00000),
.RBAR_CAP_ID(16'b0000000000000000),
.RBAR_CAP_INDEX0(3'b000),
.RBAR_CAP_INDEX1(3'b000),
.RBAR_CAP_INDEX2(3'b000),
.RBAR_CAP_INDEX3(3'b000),
.RBAR_CAP_INDEX4(3'b000),
.RBAR_CAP_INDEX5(3'b000),
.RBAR_CAP_NEXTPTR(12'b000000000000),
.RBAR_CAP_ON("FALSE"),
.RBAR_CAP_SUP0(32'b00000000000000000000000000000000),
.RBAR_CAP_SUP1(32'b00000000000000000000000000000000),
.RBAR_CAP_SUP2(32'b00000000000000000000000000000000),
.RBAR_CAP_SUP3(32'b00000000000000000000000000000000),
.RBAR_CAP_SUP4(32'b00000000000000000000000000000000),
.RBAR_CAP_SUP5(32'b00000000000000000000000000000000),
.RBAR_CAP_VERSION(4'b0000),
.RBAR_NUM(3'b000),
.RECRC_CHK(2'b00),
.RECRC_CHK_TRIM("FALSE"),
.ROOT_CAP_CRS_SW_VISIBILITY("FALSE"),
.RP_AUTO_SPD(2'b00),
.RP_AUTO_SPD_LOOPCNT(5'b00000),
.SELECT_DLL_IF("FALSE"),
.SLOT_CAP_ATT_BUTTON_PRESENT("FALSE"),
.SLOT_CAP_ATT_INDICATOR_PRESENT("FALSE"),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT("FALSE"),
.SLOT_CAP_HOTPLUG_CAPABLE("FALSE"),
.SLOT_CAP_HOTPLUG_SURPRISE("FALSE"),
.SLOT_CAP_MRL_SENSOR_PRESENT("FALSE"),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT("FALSE"),
.SLOT_CAP_PHYSICAL_SLOT_NUM(13'b0000000000000),
.SLOT_CAP_POWER_CONTROLLER_PRESENT("FALSE"),
.SLOT_CAP_POWER_INDICATOR_PRESENT("FALSE"),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE(2'b00),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE(8'b00000000),
.SPARE_BIT0(1'b0),
.SPARE_BIT1(1'b0),
.SPARE_BIT2(1'b0),
.SPARE_BIT3(1'b0),
.SPARE_BIT4(1'b0),
.SPARE_BIT5(1'b0),
.SPARE_BIT6(1'b0),
.SPARE_BIT7(1'b0),
.SPARE_BIT8(1'b0),
.SPARE_BYTE0(8'b00000000),
.SPARE_BYTE1(8'b00000000),
.SPARE_BYTE2(8'b00000000),
.SPARE_BYTE3(8'b00000000),
.SPARE_WORD0(32'b00000000000000000000000000000000),
.SPARE_WORD1(32'b00000000000000000000000000000000),
.SPARE_WORD2(32'b00000000000000000000000000000000),
.SPARE_WORD3(32'b00000000000000000000000000000000),
.SSL_MESSAGE_AUTO("FALSE"),
.TECRC_EP_INV("FALSE"),
.TL_RBYPASS("FALSE"),
.TL_RX_RAM_RADDR_LATENCY(1'b0),
.TL_RX_RAM_RDATA_LATENCY(2'b01),
.TL_RX_RAM_WRITE_LATENCY(1'b0),
.TL_TFC_DISABLE("FALSE"),
.TL_TX_CHECKS_DISABLE("FALSE"),
.TL_TX_RAM_RADDR_LATENCY(1'b0),
.TL_TX_RAM_RDATA_LATENCY(2'b01),
.TL_TX_RAM_WRITE_LATENCY(1'b0),
.TRN_DW("FALSE"),
.TRN_NP_FC("FALSE"),
.UPCONFIG_CAPABLE("FALSE"),
.UPSTREAM_FACING("FALSE"),
.UR_ATOMIC("FALSE"),
.UR_CFG1("FALSE"),
.UR_INV_REQ("FALSE"),
.UR_PRS_RESPONSE("FALSE"),
.USER_CLK2_DIV2("FALSE"),
.USER_CLK_FREQ(3'b000),
.USE_RID_PINS("FALSE"),
.VC0_CPL_INFINITE("FALSE"),
.VC0_RX_RAM_LIMIT(13'b0000000000000),
.VC0_TOTAL_CREDITS_CD(11'b00000000000),
.VC0_TOTAL_CREDITS_CH(7'b0100100),
.VC0_TOTAL_CREDITS_NPD(11'b00000000000),
.VC0_TOTAL_CREDITS_NPH(7'b0001100),
.VC0_TOTAL_CREDITS_PD(11'b00000000000),
.VC0_TOTAL_CREDITS_PH(7'b0100000),
.VC0_TX_LASTPACKET(5'b00000),
.VC_BASE_PTR(12'b000000000000),
.VC_CAP_ID(16'b0000000000000000),
.VC_CAP_NEXTPTR(12'b000000000000),
.VC_CAP_ON("FALSE"),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS("FALSE"),
.VC_CAP_VERSION(4'b0000),
.VSEC_BASE_PTR(12'b000000000000),
.VSEC_CAP_HDR_ID(16'b0000000000000000),
.VSEC_CAP_HDR_LENGTH(12'b000000000000),
.VSEC_CAP_HDR_REVISION(4'b0000),
.VSEC_CAP_ID(16'b0000000000000000),
.VSEC_CAP_IS_LINK_VISIBLE("FALSE"),
.VSEC_CAP_NEXTPTR(12'b000000000000),
.VSEC_CAP_ON("FALSE"),
.VSEC_CAP_VERSION(4'b0000)
) PCIE_BOT_X71Y115_PCIE_X0Y0_PCIE_2_1 (
.CFGAERECRCCHECKEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERECRCCHECKEN),
.CFGAERECRCGENEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERECRCGENEN),
.CFGAERINTERRUPTMSGNUM({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGAERROOTERRCORRERRRECEIVED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRCORRERRRECEIVED),
.CFGAERROOTERRCORRERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRCORRERRREPORTINGEN),
.CFGAERROOTERRFATALERRRECEIVED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRFATALERRRECEIVED),
.CFGAERROOTERRFATALERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRFATALERRREPORTINGEN),
.CFGAERROOTERRNONFATALERRRECEIVED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRNONFATALERRRECEIVED),
.CFGAERROOTERRNONFATALERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERROOTERRNONFATALERRREPORTINGEN),
.CFGBRIDGESERREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGBRIDGESERREN),
.CFGCOMMANDBUSMASTERENABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDBUSMASTERENABLE),
.CFGCOMMANDINTERRUPTDISABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDINTERRUPTDISABLE),
.CFGCOMMANDIOENABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDIOENABLE),
.CFGCOMMANDMEMENABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDMEMENABLE),
.CFGCOMMANDSERREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGCOMMANDSERREN),
.CFGDEVCONTROL2ARIFORWARDEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ARIFORWARDEN),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ATOMICEGRESSBLOCK),
.CFGDEVCONTROL2ATOMICREQUESTEREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2ATOMICREQUESTEREN),
.CFGDEVCONTROL2CPLTIMEOUTDIS(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTDIS),
.CFGDEVCONTROL2CPLTIMEOUTVAL({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2CPLTIMEOUTVAL0}),
.CFGDEVCONTROL2IDOCPLEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2IDOCPLEN),
.CFGDEVCONTROL2IDOREQEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2IDOREQEN),
.CFGDEVCONTROL2LTREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2LTREN),
.CFGDEVCONTROL2TLPPREFIXBLOCK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROL2TLPPREFIXBLOCK),
.CFGDEVCONTROLAUXPOWEREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLAUXPOWEREN),
.CFGDEVCONTROLCORRERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLCORRERRREPORTINGEN),
.CFGDEVCONTROLENABLERO(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLENABLERO),
.CFGDEVCONTROLEXTTAGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLEXTTAGEN),
.CFGDEVCONTROLFATALERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLFATALERRREPORTINGEN),
.CFGDEVCONTROLMAXPAYLOAD({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXPAYLOAD0}),
.CFGDEVCONTROLMAXREADREQ({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLMAXREADREQ0}),
.CFGDEVCONTROLNONFATALREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLNONFATALREPORTINGEN),
.CFGDEVCONTROLNOSNOOPEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLNOSNOOPEN),
.CFGDEVCONTROLPHANTOMEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLPHANTOMEN),
.CFGDEVCONTROLURERRREPORTINGEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVCONTROLURERRREPORTINGEN),
.CFGDEVID({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGDEVSTATUSCORRERRDETECTED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSCORRERRDETECTED),
.CFGDEVSTATUSFATALERRDETECTED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSFATALERRDETECTED),
.CFGDEVSTATUSNONFATALERRDETECTED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSNONFATALERRDETECTED),
.CFGDEVSTATUSURDETECTED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVSTATUSURDETECTED),
.CFGDSBUSNUMBER({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGDSDEVICENUMBER({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGDSFUNCTIONNUMBER({1'b0, 1'b0, 1'b0}),
.CFGDSN({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGERRACSN(1'b0),
.CFGERRAERHEADERLOG({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGERRAERHEADERLOGSETN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOGSETN),
.CFGERRATOMICEGRESSBLOCKEDN(1'b0),
.CFGERRCORN(1'b0),
.CFGERRCPLABORTN(1'b0),
.CFGERRCPLRDYN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLRDYN),
.CFGERRCPLTIMEOUTN(1'b0),
.CFGERRCPLUNEXPECTN(1'b0),
.CFGERRECRCN(1'b0),
.CFGERRINTERNALCORN(1'b0),
.CFGERRINTERNALUNCORN(1'b0),
.CFGERRLOCKEDN(1'b0),
.CFGERRMALFORMEDN(1'b0),
.CFGERRMCBLOCKEDN(1'b0),
.CFGERRNORECOVERYN(1'b0),
.CFGERRPOISONEDN(1'b0),
.CFGERRPOSTEDN(1'b0),
.CFGERRTLPCPLHEADER({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGERRURN(1'b0),
.CFGFORCECOMMONCLOCKOFF(1'b0),
.CFGFORCEEXTENDEDSYNCON(1'b0),
.CFGFORCEMPS({1'b0, 1'b0, 1'b0}),
.CFGINTERRUPTASSERTN(1'b0),
.CFGINTERRUPTDI({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGINTERRUPTDO({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO7, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO6, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO5, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO4, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDO0}),
.CFGINTERRUPTMMENABLE({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMMENABLE0}),
.CFGINTERRUPTMSIENABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIXENABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFM(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTMSIXFM),
.CFGINTERRUPTN(1'b0),
.CFGINTERRUPTRDYN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTRDYN),
.CFGINTERRUPTSTATN(1'b0),
.CFGLINKCONTROLASPMCONTROL({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLASPMCONTROL1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLASPMCONTROL0}),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLAUTOBANDWIDTHINTEN),
.CFGLINKCONTROLBANDWIDTHINTEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLBANDWIDTHINTEN),
.CFGLINKCONTROLCLOCKPMEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLCLOCKPMEN),
.CFGLINKCONTROLCOMMONCLOCK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLCOMMONCLOCK),
.CFGLINKCONTROLEXTENDEDSYNC(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLEXTENDEDSYNC),
.CFGLINKCONTROLHWAUTOWIDTHDIS(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLHWAUTOWIDTHDIS),
.CFGLINKCONTROLLINKDISABLE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLLINKDISABLE),
.CFGLINKCONTROLRCB(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLRCB),
.CFGLINKCONTROLRETRAINLINK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKCONTROLRETRAINLINK),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSAUTOBANDWIDTHSTATUS),
.CFGLINKSTATUSBANDWIDTHSTATUS(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSBANDWIDTHSTATUS),
.CFGLINKSTATUSCURRENTSPEED({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSCURRENTSPEED1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSCURRENTSPEED0}),
.CFGLINKSTATUSDLLACTIVE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSDLLACTIVE),
.CFGLINKSTATUSLINKTRAINING(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSLINKTRAINING),
.CFGLINKSTATUSNEGOTIATEDWIDTH({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGLINKSTATUSNEGOTIATEDWIDTH0}),
.CFGMGMTBYTEENN({1'b0, 1'b0, 1'b0, 1'b0}),
.CFGMGMTDI({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGMGMTDO({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO31, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO30, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO29, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO28, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO27, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO26, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO25, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO24, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO23, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO22, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO21, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO20, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO19, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO18, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO17, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO16, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO15, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO14, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO13, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO12, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO11, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO10, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO9, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO8, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO7, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO6, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO5, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO4, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDO0}),
.CFGMGMTDWADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGMGMTRDENN(1'b0),
.CFGMGMTRDWRDONEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTRDWRDONEN),
.CFGMGMTWRENN(1'b0),
.CFGMGMTWRREADONLYN(1'b0),
.CFGMGMTWRRW1CASRWN(1'b0),
.CFGMSGDATA({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGDATA0}),
.CFGMSGRECEIVED(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVED),
.CFGMSGRECEIVEDASSERTINTA(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTA),
.CFGMSGRECEIVEDASSERTINTB(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTB),
.CFGMSGRECEIVEDASSERTINTC(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTC),
.CFGMSGRECEIVEDASSERTINTD(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDASSERTINTD),
.CFGMSGRECEIVEDDEASSERTINTA(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTA),
.CFGMSGRECEIVEDDEASSERTINTB(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTB),
.CFGMSGRECEIVEDDEASSERTINTC(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTC),
.CFGMSGRECEIVEDDEASSERTINTD(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDDEASSERTINTD),
.CFGMSGRECEIVEDERRCOR(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRCOR),
.CFGMSGRECEIVEDERRFATAL(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRFATAL),
.CFGMSGRECEIVEDERRNONFATAL(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDERRNONFATAL),
.CFGMSGRECEIVEDPMASNAK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMASNAK),
.CFGMSGRECEIVEDPMETO(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMETO),
.CFGMSGRECEIVEDPMETOACK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMETOACK),
.CFGMSGRECEIVEDPMPME(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDPMPME),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDSETSLOTPOWERLIMIT),
.CFGMSGRECEIVEDUNLOCK(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMSGRECEIVEDUNLOCK),
.CFGPCIECAPINTERRUPTMSGNUM({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGPCIELINKSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIELINKSTATE0}),
.CFGPMCSRPMEEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPMEEN),
.CFGPMCSRPMESTATUS(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPMESTATUS),
.CFGPMCSRPOWERSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPOWERSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMCSRPOWERSTATE0}),
.CFGPMFORCESTATE({1'b0, 1'b0}),
.CFGPMFORCESTATEENN(1'b0),
.CFGPMHALTASPML0SN(1'b0),
.CFGPMHALTASPML1N(1'b0),
.CFGPMRCVASREQL1N(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVASREQL1N),
.CFGPMRCVENTERL1N(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVENTERL1N),
.CFGPMRCVENTERL23N(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVENTERL23N),
.CFGPMRCVREQACKN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMRCVREQACKN),
.CFGPMSENDPMETON(1'b0),
.CFGPMTURNOFFOKN(1'b0),
.CFGPMWAKEN(1'b0),
.CFGPORTNUMBER({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGREVID({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGROOTCONTROLPMEINTEN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLPMEINTEN),
.CFGROOTCONTROLSYSERRCORRERREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRCORRERREN),
.CFGROOTCONTROLSYSERRFATALERREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRFATALERREN),
.CFGROOTCONTROLSYSERRNONFATALERREN(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGROOTCONTROLSYSERRNONFATALERREN),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSLOTCONTROLELECTROMECHILCTLPULSE),
.CFGSUBSYSID({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGSUBSYSVENDID({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CFGTRANSACTION(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTION),
.CFGTRANSACTIONADDR({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONADDR0}),
.CFGTRANSACTIONTYPE(PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRANSACTIONTYPE),
.CFGTRNPENDINGN(1'b0),
.CFGVCTCVCMAP({PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP6, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP5, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP4, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP3, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP2, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP1, PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVCTCVCMAP0}),
.CFGVENDID({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.CMRSTN(1'b0),
.CMSTICKYRSTN(1'b0),
.DBGMODE({1'b0, 1'b0}),
.DBGSCLRA(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRA),
.DBGSCLRB(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRB),
.DBGSCLRC(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRC),
.DBGSCLRD(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRD),
.DBGSCLRE(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRE),
.DBGSCLRF(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRF),
.DBGSCLRG(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRG),
.DBGSCLRH(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRH),
.DBGSCLRI(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRI),
.DBGSCLRJ(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRJ),
.DBGSCLRK(PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSCLRK),
.DBGSUBMODE(1'b0),
.DBGVECA({PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA63, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA62, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA61, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA60, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA59, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA58, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA57, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA56, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA55, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA54, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA53, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA52, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA51, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA50, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA49, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA48, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA47, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA46, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA45, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA44, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA43, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA42, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA41, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA40, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA39, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA38, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA37, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA36, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA35, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA34, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA33, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA32, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA31, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA30, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA29, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA28, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA27, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA26, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA25, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA24, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA23, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA22, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA21, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA20, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA19, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA18, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA17, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA16, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA15, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA14, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA13, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA12, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA11, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA10, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA9, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA8, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA7, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA6, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA5, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA4, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA3, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA2, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA1, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECA0}),
.DBGVECB({PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB63, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB62, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB61, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB60, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB59, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB58, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB57, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB56, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB55, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB54, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB53, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB52, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB51, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB50, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB49, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB48, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB47, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB46, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB45, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB44, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB43, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB42, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB41, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB40, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB39, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB38, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB37, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB36, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB35, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB34, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB33, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB32, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB31, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB30, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB29, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB28, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB27, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB26, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB25, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB24, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB23, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB22, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB21, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB20, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB19, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB18, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB17, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB16, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB15, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB14, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB13, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB12, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB11, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB10, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB9, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB8, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB7, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB6, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB5, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB4, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB3, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB2, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB1, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECB0}),
.DBGVECC({PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC11, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC10, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC9, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC8, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC7, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC6, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC5, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC4, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC3, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC2, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC1, PCIE_BOT_X71Y115_PCIE_X0Y0_DBGVECC0}),
.DLRSTN(1'b0),
.DRPADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DRPCLK(1'b0),
.DRPDI({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DRPDO({PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO15, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO14, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO13, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO12, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO11, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO10, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO9, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO8, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO7, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO6, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO5, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO4, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO3, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO2, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO1, PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDO0}),
.DRPEN(1'b0),
.DRPRDY(PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY),
.DRPWE(1'b0),
.FUNCLVLRSTN(1'b0),
.LL2BADDLLPERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2BADDLLPERR),
.LL2BADTLPERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2BADTLPERR),
.LL2LINKSTATUS({PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS4, PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS3, PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS2, PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS1, PCIE_BOT_X71Y115_PCIE_X0Y0_LL2LINKSTATUS0}),
.LL2PROTOCOLERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2PROTOCOLERR),
.LL2RECEIVERERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2RECEIVERERR),
.LL2REPLAYROERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2REPLAYROERR),
.LL2REPLAYTOERR(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2REPLAYTOERR),
.LL2SENDASREQL1(1'b0),
.LL2SENDENTERL1(1'b0),
.LL2SENDENTERL23(1'b0),
.LL2SENDPMACK(1'b0),
.LL2SUSPENDNOW(1'b0),
.LL2SUSPENDOK(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SUSPENDOK),
.LL2TFCINIT1SEQ(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TFCINIT1SEQ),
.LL2TFCINIT2SEQ(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TFCINIT2SEQ),
.LL2TLPRCV(1'b0),
.LL2TXIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TXIDLE),
.LNKCLKEN(PCIE_BOT_X71Y115_PCIE_X0Y0_LNKCLKEN),
.MIMRXRADDR({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRADDR0}),
.MIMRXRDATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.MIMRXREN(PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXREN),
.MIMRXWADDR({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWADDR0}),
.MIMRXWDATA({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA67, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA66, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA65, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA64, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA63, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA62, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA61, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA60, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA59, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA58, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA57, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA56, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA55, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA54, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA53, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA52, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA51, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA50, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA49, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA48, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA47, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA46, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA45, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA44, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA43, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA42, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA41, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA40, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA39, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA38, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA37, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA36, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA35, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA34, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA33, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA32, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA31, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA30, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA29, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA28, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA27, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA26, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA25, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA24, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA23, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA22, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA21, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA20, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA19, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA18, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA17, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA16, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWDATA0}),
.MIMRXWEN(PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXWEN),
.MIMTXRADDR({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRADDR0}),
.MIMTXRDATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.MIMTXREN(PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXREN),
.MIMTXWADDR({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWADDR0}),
.MIMTXWDATA({PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA68, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA67, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA66, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA65, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA64, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA63, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA62, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA61, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA60, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA59, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA58, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA57, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA56, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA55, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA54, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA53, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA52, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA51, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA50, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA49, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA48, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA47, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA46, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA45, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA44, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA43, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA42, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA41, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA40, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA39, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA38, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA37, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA36, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA35, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA34, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA33, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA32, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA31, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA30, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA29, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA28, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA27, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA26, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA25, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA24, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA23, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA22, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA21, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA20, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA19, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA18, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA17, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA16, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWDATA0}),
.MIMTXWEN(PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXWEN),
.PIPECLK(1'b0),
.PIPERX0CHANISALIGNED(1'b0),
.PIPERX0CHARISK({1'b0, 1'b0}),
.PIPERX0DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX0ELECIDLE(1'b0),
.PIPERX0PHYSTATUS(1'b0),
.PIPERX0POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0POLARITY),
.PIPERX0STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX0VALID(1'b0),
.PIPERX1CHANISALIGNED(1'b0),
.PIPERX1CHARISK({1'b0, 1'b0}),
.PIPERX1DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX1ELECIDLE(1'b0),
.PIPERX1PHYSTATUS(1'b0),
.PIPERX1POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1POLARITY),
.PIPERX1STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX1VALID(1'b0),
.PIPERX2CHANISALIGNED(1'b0),
.PIPERX2CHARISK({1'b0, 1'b0}),
.PIPERX2DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX2ELECIDLE(1'b0),
.PIPERX2PHYSTATUS(1'b0),
.PIPERX2POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2POLARITY),
.PIPERX2STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX2VALID(1'b0),
.PIPERX3CHANISALIGNED(1'b0),
.PIPERX3CHARISK({1'b0, 1'b0}),
.PIPERX3DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX3ELECIDLE(1'b0),
.PIPERX3PHYSTATUS(1'b0),
.PIPERX3POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3POLARITY),
.PIPERX3STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX3VALID(1'b0),
.PIPERX4CHANISALIGNED(1'b0),
.PIPERX4CHARISK({1'b0, 1'b0}),
.PIPERX4DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX4ELECIDLE(1'b0),
.PIPERX4PHYSTATUS(1'b0),
.PIPERX4POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4POLARITY),
.PIPERX4STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX4VALID(1'b0),
.PIPERX5CHANISALIGNED(1'b0),
.PIPERX5CHARISK({1'b0, 1'b0}),
.PIPERX5DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX5ELECIDLE(1'b0),
.PIPERX5PHYSTATUS(1'b0),
.PIPERX5POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5POLARITY),
.PIPERX5STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX5VALID(1'b0),
.PIPERX6CHANISALIGNED(1'b0),
.PIPERX6CHARISK({1'b0, 1'b0}),
.PIPERX6DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX6ELECIDLE(1'b0),
.PIPERX6PHYSTATUS(1'b0),
.PIPERX6POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6POLARITY),
.PIPERX6STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX6VALID(1'b0),
.PIPERX7CHANISALIGNED(1'b0),
.PIPERX7CHARISK({1'b0, 1'b0}),
.PIPERX7DATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PIPERX7ELECIDLE(1'b0),
.PIPERX7PHYSTATUS(1'b0),
.PIPERX7POLARITY(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7POLARITY),
.PIPERX7STATUS({1'b0, 1'b0, 1'b0}),
.PIPERX7VALID(1'b0),
.PIPETX0CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0CHARISK0}),
.PIPETX0COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0COMPLIANCE),
.PIPETX0DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0DATA0}),
.PIPETX0ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0ELECIDLE),
.PIPETX0POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX0POWERDOWN0}),
.PIPETX1CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1CHARISK0}),
.PIPETX1COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1COMPLIANCE),
.PIPETX1DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1DATA0}),
.PIPETX1ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1ELECIDLE),
.PIPETX1POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX1POWERDOWN0}),
.PIPETX2CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2CHARISK0}),
.PIPETX2COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2COMPLIANCE),
.PIPETX2DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2DATA0}),
.PIPETX2ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2ELECIDLE),
.PIPETX2POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX2POWERDOWN0}),
.PIPETX3CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3CHARISK0}),
.PIPETX3COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3COMPLIANCE),
.PIPETX3DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3DATA0}),
.PIPETX3ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3ELECIDLE),
.PIPETX3POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX3POWERDOWN0}),
.PIPETX4CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4CHARISK0}),
.PIPETX4COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4COMPLIANCE),
.PIPETX4DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4DATA0}),
.PIPETX4ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4ELECIDLE),
.PIPETX4POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX4POWERDOWN0}),
.PIPETX5CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5CHARISK0}),
.PIPETX5COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5COMPLIANCE),
.PIPETX5DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5DATA0}),
.PIPETX5ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5ELECIDLE),
.PIPETX5POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX5POWERDOWN0}),
.PIPETX6CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6CHARISK0}),
.PIPETX6COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6COMPLIANCE),
.PIPETX6DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6DATA0}),
.PIPETX6ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6ELECIDLE),
.PIPETX6POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX6POWERDOWN0}),
.PIPETX7CHARISK({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7CHARISK1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7CHARISK0}),
.PIPETX7COMPLIANCE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7COMPLIANCE),
.PIPETX7DATA({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7DATA0}),
.PIPETX7ELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7ELECIDLE),
.PIPETX7POWERDOWN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7POWERDOWN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETX7POWERDOWN0}),
.PIPETXDEEMPH(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXDEEMPH),
.PIPETXMARGIN({PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN2, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN1, PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXMARGIN0}),
.PIPETXRATE(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRATE),
.PIPETXRCVRDET(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRCVRDET),
.PIPETXRESET(PCIE_BOT_X71Y115_PCIE_X0Y0_PIPETXRESET),
.PL2DIRECTEDLSTATE({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PL2L0REQ(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2L0REQ),
.PL2LINKUP(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2LINKUP),
.PL2RECEIVERERR(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RECEIVERERR),
.PL2RECOVERY(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RECOVERY),
.PL2RXELECIDLE(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXELECIDLE),
.PL2RXPMSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXPMSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_PL2RXPMSTATE0}),
.PL2SUSPENDOK(PCIE_BOT_X71Y115_PCIE_X0Y0_PL2SUSPENDOK),
.PLDBGMODE({1'b0, 1'b0, 1'b0}),
.PLDBGVEC({PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC11, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC10, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC9, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC8, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC7, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC6, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC5, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC4, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC3, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC2, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGVEC0}),
.PLDIRECTEDCHANGEDONE(PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDCHANGEDONE),
.PLDIRECTEDLINKAUTON(1'b0),
.PLDIRECTEDLINKCHANGE({1'b0, 1'b0}),
.PLDIRECTEDLINKSPEED(1'b0),
.PLDIRECTEDLINKWIDTH({1'b0, 1'b0}),
.PLDIRECTEDLTSSMNEW({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.PLDIRECTEDLTSSMNEWVLD(1'b0),
.PLDIRECTEDLTSSMSTALL(1'b0),
.PLDOWNSTREAMDEEMPHSOURCE(1'b0),
.PLINITIALLINKWIDTH({PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH2, PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLINITIALLINKWIDTH0}),
.PLLANEREVERSALMODE({PCIE_BOT_X71Y115_PCIE_X0Y0_PLLANEREVERSALMODE1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLANEREVERSALMODE0}),
.PLLINKGEN2CAP(PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKGEN2CAP),
.PLLINKPARTNERGEN2SUPPORTED(PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKPARTNERGEN2SUPPORTED),
.PLLINKUPCFGCAP(PCIE_BOT_X71Y115_PCIE_X0Y0_PLLINKUPCFGCAP),
.PLLTSSMSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE5, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE4, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE3, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE2, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLLTSSMSTATE0}),
.PLPHYLNKUPN(PCIE_BOT_X71Y115_PCIE_X0Y0_PLPHYLNKUPN),
.PLRECEIVEDHOTRST(PCIE_BOT_X71Y115_PCIE_X0Y0_PLRECEIVEDHOTRST),
.PLRSTN(1'b0),
.PLRXPMSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_PLRXPMSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLRXPMSTATE0}),
.PLSELLNKRATE(PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKRATE),
.PLSELLNKWIDTH({PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKWIDTH1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLSELLNKWIDTH0}),
.PLTRANSMITHOTRST(1'b0),
.PLTXPMSTATE({PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE2, PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE1, PCIE_BOT_X71Y115_PCIE_X0Y0_PLTXPMSTATE0}),
.PLUPSTREAMPREFERDEEMPH(1'b0),
.RECEIVEDFUNCLVLRSTN(PCIE_BOT_X71Y115_PCIE_X0Y0_RECEIVEDFUNCLVLRSTN),
.SYSRSTN(LIOB33_X0Y11_IOB_X0Y11_I),
.TL2ASPMSUSPENDCREDITCHECK(1'b0),
.TL2ASPMSUSPENDCREDITCHECKOK(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDCREDITCHECKOK),
.TL2ASPMSUSPENDREQ(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDREQ),
.TL2ERRFCPE(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRFCPE),
.TL2ERRHDR({PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR63, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR62, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR61, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR60, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR59, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR58, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR57, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR56, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR55, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR54, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR53, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR52, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR51, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR50, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR49, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR48, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR47, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR46, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR45, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR44, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR43, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR42, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR41, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR40, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR39, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR38, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR37, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR36, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR35, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR34, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR33, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR32, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR31, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR30, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR29, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR28, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR27, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR26, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR25, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR24, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR23, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR22, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR21, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR20, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR19, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR18, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR17, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR16, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR15, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR14, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR13, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR12, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR11, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR10, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR9, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR8, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR7, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR6, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR5, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR4, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR3, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR2, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR1, PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRHDR0}),
.TL2ERRMALFORMED(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRMALFORMED),
.TL2ERRRXOVERFLOW(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ERRRXOVERFLOW),
.TL2PPMSUSPENDOK(PCIE_BOT_X71Y115_PCIE_X0Y0_TL2PPMSUSPENDOK),
.TL2PPMSUSPENDREQ(1'b0),
.TLRSTN(1'b0),
.TRNFCCPLD({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD11, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD10, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD9, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD8, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLD0}),
.TRNFCCPLH({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCCPLH0}),
.TRNFCNPD({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD11, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD10, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD9, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD8, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPD0}),
.TRNFCNPH({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCNPH0}),
.TRNFCPD({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD11, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD10, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD9, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD8, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPD0}),
.TRNFCPH({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCPH0}),
.TRNFCSEL({1'b0, 1'b0, 1'b0}),
.TRNLNKUP(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNLNKUP),
.TRNRBARHIT({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRBARHIT0}),
.TRNRD({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD127, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD126, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD125, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD124, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD123, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD122, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD121, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD120, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD119, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD118, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD117, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD116, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD115, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD114, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD113, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD112, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD111, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD110, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD109, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD108, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD107, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD106, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD105, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD104, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD103, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD102, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD101, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD100, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD99, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD98, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD97, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD96, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD95, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD94, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD93, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD92, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD91, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD90, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD89, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD88, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD87, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD86, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD85, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD84, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD83, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD82, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD81, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD80, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD79, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD78, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD77, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD76, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD75, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD74, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD73, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD72, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD71, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD70, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD69, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD68, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD67, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD66, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD65, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD64, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD63, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD62, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD61, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD60, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD59, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD58, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD57, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD56, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD55, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD54, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD53, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD52, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD51, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD50, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD49, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD48, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD47, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD46, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD45, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD44, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD43, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD42, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD41, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD40, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD39, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD38, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD37, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD36, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD35, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD34, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD33, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD32, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD31, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD30, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD29, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD28, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD27, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD26, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD25, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD24, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD23, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD22, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD21, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD20, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD19, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD18, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD17, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD16, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD15, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD14, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD13, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD12, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD11, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD10, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD9, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD8, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRD0}),
.TRNRDLLPDATA({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA63, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA62, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA61, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA60, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA59, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA58, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA57, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA56, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA55, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA54, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA53, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA52, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA51, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA50, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA49, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA48, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA47, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA46, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA45, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA44, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA43, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA42, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA41, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA40, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA39, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA38, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA37, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA36, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA35, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA34, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA33, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA32, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA31, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA30, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA29, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA28, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA27, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA26, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA25, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA24, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA23, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA22, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA21, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA20, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA19, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA18, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA17, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA16, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA15, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA14, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA13, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA12, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA11, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA10, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA9, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA8, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA7, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA6, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPDATA0}),
.TRNRDLLPSRCRDY({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPSRCRDY1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDLLPSRCRDY0}),
.TRNRDSTRDY(1'b0),
.TRNRECRCERR(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRECRCERR),
.TRNREOF(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNREOF),
.TRNRERRFWD(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRERRFWD),
.TRNRFCPRET(1'b0),
.TRNRNPOK(1'b0),
.TRNRNPREQ(1'b0),
.TRNRREM({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRREM1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRREM0}),
.TRNRSOF(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSOF),
.TRNRSRCDSC(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSRCDSC),
.TRNRSRCRDY(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRSRCRDY),
.TRNTBUFAV({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV5, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV4, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTBUFAV0}),
.TRNTCFGGNT(1'b0),
.TRNTCFGREQ(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTCFGREQ),
.TRNTD({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.TRNTDLLPDATA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.TRNTDLLPDSTRDY(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDSTRDY),
.TRNTDLLPSRCRDY(1'b0),
.TRNTDSTRDY({PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY3, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY2, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY1, PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDSTRDY0}),
.TRNTECRCGEN(1'b0),
.TRNTEOF(1'b0),
.TRNTERRDROP(PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTERRDROP),
.TRNTERRFWD(1'b0),
.TRNTREM({1'b0, 1'b0}),
.TRNTSOF(1'b0),
.TRNTSRCDSC(1'b0),
.TRNTSRCRDY(1'b0),
.TRNTSTR(1'b0),
.USERCLK(1'b0),
.USERCLK2(1'b0),
.USERRSTN(PCIE_BOT_X71Y115_PCIE_X0Y0_USERRSTN)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y31_IOB_X1Y32_OBUF (
.I(RIOB33_X43Y45_IOB_X1Y46_I),
.O(led[11])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y37_IOB_X1Y37_OBUF (
.I(RIOB33_X43Y47_IOB_X1Y47_I),
.O(led[10])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y37_IOB_X1Y38_OBUF (
.I(RIOB33_X43Y45_IOB_X1Y45_I),
.O(led[9])
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y39_IOB_X1Y39_IBUF (
.I(sw[12]),
.O(RIOB33_X43Y39_IOB_X1Y39_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y39_IOB_X1Y40_IBUF (
.I(sw[8]),
.O(RIOB33_X43Y39_IOB_X1Y40_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y43_IBUF (
.I(sw[13]),
.O(RIOB33_X43Y43_IOB_X1Y43_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y44_IBUF (
.I(sw[14]),
.O(RIOB33_X43Y43_IOB_X1Y44_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y45_IBUF (
.I(sw[9]),
.O(RIOB33_X43Y45_IOB_X1Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y46_IBUF (
.I(sw[11]),
.O(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y47_IOB_X1Y47_IBUF (
.I(sw[10]),
.O(RIOB33_X43Y47_IOB_X1Y47_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y47_IOB_X1Y48_IBUF (
.I(sw[15]),
.O(RIOB33_X43Y47_IOB_X1Y48_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y61_IOB_X1Y61_OBUF (
.I(RIOB33_X43Y43_IOB_X1Y44_I),
.O(led[14])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y75_IOB_X1Y75_OBUF (
.I(RIOB33_X43Y39_IOB_X1Y39_I),
.O(led[12])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y75_IOB_X1Y76_OBUF (
.I(RIOB33_X43Y43_IOB_X1Y43_I),
.O(led[13])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y87_IOB_X1Y87_OBUF (
.I(RIOB33_X43Y47_IOB_X1Y48_I),
.O(led[15])
);
assign LIOI3_X0Y1_OLOGIC_X0Y2_OQ = RIOB33_X43Y39_IOB_X1Y40_I;
assign LIOI3_X0Y1_OLOGIC_X0Y2_TQ = 1'b1;
assign LIOI3_X0Y1_OLOGIC_X0Y1_OQ = LIOB33_X0Y5_IOB_X0Y6_I;
assign LIOI3_X0Y1_OLOGIC_X0Y1_TQ = 1'b1;
assign LIOI3_X0Y3_OLOGIC_X0Y4_OQ = LIOB33_X0Y7_IOB_X0Y8_I;
assign LIOI3_X0Y3_OLOGIC_X0Y4_TQ = 1'b1;
assign LIOI3_X0Y3_OLOGIC_X0Y3_OQ = PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY;
assign LIOI3_X0Y3_OLOGIC_X0Y3_TQ = 1'b1;
assign LIOI3_X0Y5_ILOGIC_X0Y6_O = LIOB33_X0Y5_IOB_X0Y6_I;
assign LIOI3_X0Y5_ILOGIC_X0Y5_O = LIOB33_X0Y5_IOB_X0Y5_I;
assign LIOI3_X0Y9_ILOGIC_X0Y10_O = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOI3_X0Y9_ILOGIC_X0Y9_O = LIOB33_X0Y9_IOB_X0Y9_I;
assign LIOI3_X0Y11_ILOGIC_X0Y12_O = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_X0Y11_ILOGIC_X0Y11_O = LIOB33_X0Y11_IOB_X0Y11_I;
assign LIOI3_X0Y17_OLOGIC_X0Y18_OQ = LIOB33_X0Y7_IOB_X0Y7_I;
assign LIOI3_X0Y17_OLOGIC_X0Y18_TQ = 1'b1;
assign LIOI3_X0Y111_ILOGIC_X0Y112_O = LIOB33_X0Y111_IOB_X0Y112_I;
assign LIOI3_X0Y111_OLOGIC_X0Y111_OQ = LIOB33_X0Y111_IOB_X0Y112_I;
assign LIOI3_X0Y111_OLOGIC_X0Y111_TQ = 1'b1;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_OQ = LIOB33_X0Y5_IOB_X0Y5_I;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_O = LIOB33_X0Y7_IOB_X0Y8_I;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_O = LIOB33_X0Y7_IOB_X0Y7_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_OQ = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_OQ = LIOB33_X0Y9_IOB_X0Y9_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ = 1'b1;
assign RIOI3_X43Y39_ILOGIC_X1Y40_O = RIOB33_X43Y39_IOB_X1Y40_I;
assign RIOI3_X43Y39_ILOGIC_X1Y39_O = RIOB33_X43Y39_IOB_X1Y39_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_X43Y47_ILOGIC_X1Y48_O = RIOB33_X43Y47_IOB_X1Y48_I;
assign RIOI3_X43Y47_ILOGIC_X1Y47_O = RIOB33_X43Y47_IOB_X1Y47_I;
assign RIOI3_X43Y61_OLOGIC_X1Y61_OQ = RIOB33_X43Y43_IOB_X1Y44_I;
assign RIOI3_X43Y61_OLOGIC_X1Y61_TQ = 1'b1;
assign RIOI3_X43Y75_OLOGIC_X1Y76_OQ = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_X43Y75_OLOGIC_X1Y76_TQ = 1'b1;
assign RIOI3_X43Y75_OLOGIC_X1Y75_OQ = RIOB33_X43Y39_IOB_X1Y39_I;
assign RIOI3_X43Y75_OLOGIC_X1Y75_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_OQ = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O = RIOB33_X43Y43_IOB_X1Y44_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_OQ = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_TQ = 1'b1;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_OQ = RIOB33_X43Y47_IOB_X1Y47_I;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_TQ = 1'b1;
assign RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_OQ = RIOB33_X43Y47_IOB_X1Y48_I;
assign RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_TQ = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPECLK = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX0VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX1VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX2VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_FUNCLVLRSTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX3VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX4VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA13 = 1'b0;
assign LIOI3_X0Y5_ILOGIC_X0Y6_D = LIOB33_X0Y5_IOB_X0Y6_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5ELECIDLE = 1'b0;
assign LIOI3_X0Y5_ILOGIC_X0Y5_D = LIOB33_X0Y5_IOB_X0Y5_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX5VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX6VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHANISALIGNED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHARISK0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7CHARISK1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7DATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7ELECIDLE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7PHYSTATUS = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7STATUS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PIPERX7VALID = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PL2DIRECTEDLSTATE4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDBGMODE2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKAUTON = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKCHANGE0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKCHANGE1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKSPEED = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKWIDTH0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLINKWIDTH1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEW5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMNEWVLD = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDIRECTEDLTSSMSTALL = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLDOWNSTREAMDEEMPHSOURCE = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLRSTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLTRANSMITHOTRST = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_PLUPSTREAMPREFERDEEMPH = 1'b0;
assign LIOB33_X0Y43_IOB_X0Y43_O = LIOB33_X0Y11_IOB_X0Y12_I;
assign RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_D1 = RIOB33_X43Y47_IOB_X1Y48_I;
assign RIOI3_TBYTETERM_X43Y87_OLOGIC_X1Y87_T1 = 1'b1;
assign LIOI3_X0Y9_ILOGIC_X0Y10_D = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOI3_X0Y9_ILOGIC_X0Y9_D = LIOB33_X0Y9_IOB_X0Y9_I;
assign RIOI3_X43Y61_OLOGIC_X1Y61_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_SYSRSTN = LIOB33_X0Y11_IOB_X0Y11_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TL2ASPMSUSPENDCREDITCHECK = 1'b0;
assign RIOI3_X43Y61_OLOGIC_X1Y61_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TL2PPMSUSPENDREQ = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TLRSTN = 1'b0;
assign RIOI3_X43Y75_OLOGIC_X1Y76_D1 = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_X43Y75_OLOGIC_X1Y76_T1 = 1'b1;
assign RIOI3_X43Y75_OLOGIC_X1Y75_D1 = RIOB33_X43Y39_IOB_X1Y39_I;
assign RIOI3_X43Y75_OLOGIC_X1Y75_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNFCSEL2 = 1'b0;
assign LIOB33_X0Y17_IOB_X0Y18_O = LIOB33_X0Y7_IOB_X0Y7_I;
assign RIOB33_X43Y87_IOB_X1Y87_O = RIOB33_X43Y47_IOB_X1Y48_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_D = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_D = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOB33_X43Y37_IOB_X1Y38_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOB33_X43Y37_IOB_X1Y37_O = RIOB33_X43Y47_IOB_X1Y47_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRDSTRDY = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRFCPRET = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRNPOK = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNRNPREQ = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTCFGGNT = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD34 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD36 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD45 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD47 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD48 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD49 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD50 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD51 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD52 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD53 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD54 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD55 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD56 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD57 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD58 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD59 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD60 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD61 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD62 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD63 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD64 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD65 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD66 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD67 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD68 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD69 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD70 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD71 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD72 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD73 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD74 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD75 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD76 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD77 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD78 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD79 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD80 = 1'b0;
assign LIOB33_X0Y19_IOB_X0Y20_O = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOB33_X0Y19_IOB_X0Y19_O = LIOB33_X0Y9_IOB_X0Y9_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD81 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD82 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD83 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD84 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD85 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD86 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD87 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD88 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD89 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD90 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD91 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD92 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD93 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD94 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD95 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD96 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD97 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD98 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD99 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD100 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD101 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD102 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD103 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD104 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD105 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD106 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD107 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD108 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD109 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD110 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD111 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD112 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD113 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD114 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD115 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD116 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD117 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD118 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD119 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD120 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD121 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD122 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD123 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD124 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD125 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD126 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTD127 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPDATA31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTDLLPSRCRDY = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTECRCGEN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTEOF = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTERRFWD = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTREM0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTREM1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSOF = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSRCDSC = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSRCRDY = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_TRNTSTR = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_USERCLK = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_USERCLK2 = 1'b0;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_T1 = 1'b1;
assign RIOB33_X43Y61_IOB_X1Y61_O = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOB33_X0Y111_IOB_X0Y111_O = LIOB33_X0Y111_IOB_X0Y112_I;
assign LIOI3_X0Y11_ILOGIC_X0Y12_D = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_X0Y11_ILOGIC_X0Y11_D = LIOB33_X0Y11_IOB_X0Y11_I;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_D = LIOB33_X0Y7_IOB_X0Y8_I;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_D = LIOB33_X0Y7_IOB_X0Y7_I;
assign RIOB33_X43Y31_IOB_X1Y32_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y47_ILOGIC_X1Y48_D = RIOB33_X43Y47_IOB_X1Y48_I;
assign RIOI3_X43Y47_ILOGIC_X1Y47_D = RIOB33_X43Y47_IOB_X1Y47_I;
assign LIOB33_SING_X0Y0_IOB_X0Y0_O = LIOB33_X0Y5_IOB_X0Y5_I;
assign RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_D1 = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_D1 = LIOB33_X0Y9_IOB_X0Y10_I;
assign RIOI3_TBYTESRC_X43Y31_OLOGIC_X1Y32_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_D1 = LIOB33_X0Y9_IOB_X0Y9_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGAERINTERRUPTMSGNUM4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDASREQL1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDENTERL1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDENTERL23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SENDPMACK = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2SUSPENDNOW = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDEVID15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSBUSNUMBER7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSDEVICENUMBER4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSFUNCTIONNUMBER2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN34 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN36 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN45 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN47 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN48 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN49 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN50 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN51 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN52 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN53 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN54 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN55 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN56 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN57 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN58 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN59 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN60 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN61 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN62 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGDSN63 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRACSN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG34 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG36 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG45 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG47 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG48 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG49 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG50 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG51 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG52 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG53 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG54 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG55 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG56 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG57 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG58 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG59 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG60 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG61 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG62 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG63 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG64 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG65 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG66 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG67 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG68 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG69 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG70 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG71 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG72 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG73 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG74 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG75 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG76 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG77 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG78 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG79 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG80 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG81 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG82 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG83 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG84 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG85 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG86 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG87 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG88 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG89 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG90 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG91 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG92 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG93 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG94 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG95 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG96 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG97 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG98 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG99 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG100 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG101 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG102 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG103 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG104 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG105 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG106 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG107 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG108 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG109 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG110 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG111 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG112 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG113 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG114 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG115 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG116 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG117 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG118 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG119 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG120 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG121 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG122 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG123 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG124 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG125 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG126 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRAERHEADERLOG127 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRATOMICEGRESSBLOCKEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCORN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLABORTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLTIMEOUTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRCPLUNEXPECTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRECRCN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRINTERNALCORN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRINTERNALUNCORN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRLOCKEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRMALFORMEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRMCBLOCKEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRNORECOVERYN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRPOISONEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRPOSTEDN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER23 = 1'b0;
assign LIOI3_X0Y1_OLOGIC_X0Y2_D1 = RIOB33_X43Y39_IOB_X1Y40_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER34 = 1'b0;
assign LIOI3_X0Y1_OLOGIC_X0Y2_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER36 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER45 = 1'b0;
assign LIOI3_X0Y1_OLOGIC_X0Y1_D1 = LIOB33_X0Y5_IOB_X0Y6_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRTLPCPLHEADER47 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGERRURN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCECOMMONCLOCKOFF = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEEXTENDEDSYNCON = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGFORCEMPS2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTASSERTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI1 = 1'b0;
assign LIOI3_X0Y1_OLOGIC_X0Y1_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTDI7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGINTERRUPTSTATN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTBYTEENN3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDI31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTDWADDR9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTRDENN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRENN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRREADONLYN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGMGMTWRRW1CASRWN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPCIECAPINTERRUPTMSGNUM4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATE0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATE1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMFORCESTATEENN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMHALTASPML0SN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMHALTASPML1N = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMSENDPMETON = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMTURNOFFOKN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPMWAKEN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGPORTNUMBER7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGREVID7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSID15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGSUBSYSVENDID15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGTRNPENDINGN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CFGVENDID15 = 1'b0;
assign LIOI3_X0Y17_OLOGIC_X0Y18_D1 = LIOB33_X0Y7_IOB_X0Y7_I;
assign LIOI3_X0Y17_OLOGIC_X0Y18_T1 = 1'b1;
assign LIOB33_X0Y1_IOB_X0Y2_O = RIOB33_X43Y39_IOB_X1Y40_I;
assign LIOB33_X0Y1_IOB_X0Y1_O = LIOB33_X0Y5_IOB_X0Y6_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CMRSTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_CMSTICKYRSTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DBGMODE0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DBGMODE1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DBGSUBMODE = 1'b0;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_D1 = LIOB33_X0Y5_IOB_X0Y5_I;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_LL2TLPRCV = 1'b0;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D = RIOB33_X43Y43_IOB_X1Y44_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D = RIOB33_X43Y43_IOB_X1Y43_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DLRSTN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPADDR8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPCLK = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPDI15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPEN = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_DRPWE = 1'b0;
assign LIOB33_X0Y3_IOB_X0Y4_O = LIOB33_X0Y7_IOB_X0Y8_I;
assign LIOB33_X0Y3_IOB_X0Y3_O = PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA34 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA36 = 1'b0;
assign LIOI3_X0Y3_OLOGIC_X0Y4_D1 = LIOB33_X0Y7_IOB_X0Y8_I;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA45 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA47 = 1'b0;
assign LIOI3_X0Y3_OLOGIC_X0Y4_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA48 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA49 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA50 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA51 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA52 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA53 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA54 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA55 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA56 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA57 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA58 = 1'b0;
assign LIOI3_X0Y3_OLOGIC_X0Y3_D1 = PCIE_BOT_X71Y115_PCIE_X0Y0_DRPRDY;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA59 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA60 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA61 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA62 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA63 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA64 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA65 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA66 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMRXRDATA67 = 1'b0;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_D1 = RIOB33_X43Y47_IOB_X1Y47_I;
assign LIOI3_X0Y3_OLOGIC_X0Y3_T1 = 1'b1;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y37_T1 = 1'b1;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA0 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA1 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA2 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA3 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA4 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA5 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA6 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA7 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA8 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA9 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA10 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA11 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA12 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA13 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA14 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA15 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA16 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA17 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA18 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA19 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA20 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA21 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA22 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA23 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA24 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA25 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA26 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA27 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA28 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA29 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA30 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA31 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA32 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA33 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA34 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA35 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA36 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA37 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA38 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA39 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA40 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA41 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA42 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA43 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA44 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA45 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA46 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA47 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA48 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA49 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA50 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA51 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA52 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA53 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA54 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA55 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA56 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA57 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA58 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA59 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA60 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA61 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA62 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA63 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA64 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA65 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA66 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA67 = 1'b0;
assign PCIE_BOT_X71Y115_PCIE_X0Y0_MIMTXRDATA68 = 1'b0;
assign RIOI3_TBYTETERM_X43Y37_OLOGIC_X1Y38_D1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOB33_X43Y75_IOB_X1Y76_O = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOB33_X43Y75_IOB_X1Y75_O = RIOB33_X43Y39_IOB_X1Y39_I;
assign LIOI3_X0Y111_OLOGIC_X0Y111_D1 = LIOB33_X0Y111_IOB_X0Y112_I;
assign LIOI3_X0Y111_OLOGIC_X0Y111_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1 = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1 = 1'b1;
assign LIOI3_X0Y111_ILOGIC_X0Y112_D = LIOB33_X0Y111_IOB_X0Y112_I;
assign RIOI3_X43Y39_ILOGIC_X1Y40_D = RIOB33_X43Y39_IOB_X1Y40_I;
assign RIOI3_X43Y39_ILOGIC_X1Y39_D = RIOB33_X43Y39_IOB_X1Y39_I;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: whoosh_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module whoosh_new (
address,
clock,
q);
input [12:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../audio_mifs/whoosh_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../audio_mifs/whoosh_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM512x16_2RW.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAM512x16_2RW (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input [1:0] byteena_a;
input [1:0] byteena_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 [1:0] byteena_b;
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.byteena_b (byteena_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 2,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "2"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]"
// Retrieval info: USED_PORT: byteena_b 0 0 2 0 INPUT VCC "byteena_b[1..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
// Retrieval info: CONNECT: @byteena_b 0 0 2 0 byteena_b 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM512x16_2RW_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// MMCM with DRP and device specific
`timescale 1ns/100ps
module ad_mmcm_drp (
// clocks
clk,
mmcm_rst,
mmcm_clk_0,
mmcm_clk_1,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter MMCM_DEVICE_TYPE = 0;
localparam MMCM_DEVICE_7SERIES = 0;
localparam MMCM_DEVICE_VIRTEX6 = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clocks
input clk;
input mmcm_rst;
output mmcm_clk_0;
output mmcm_clk_1;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
endgenerate
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_TB_V
`define SKY130_FD_SC_HS__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 B1 = 1'b0;
#380 B2 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B2 = 1'b1;
#500 B1 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B2 = 1'bx;
#640 B1 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D, DE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel Buffers
* =======================
*
* Instantiates 'N' FIFOs in parallel, if 'push' is asserted
* data_in is sent to FIFO[vc_id].
*
* The output is determined by an external 'select' input.
*
* if 'pop' is asserted by the end of the clock cycle, the
* FIFO that was read (indicated by 'select') recieves a
* pop command.
*
* - flags[] provides access to all FIFO status flags.
* - output_port[] provides access to 'output_port' field of flits at head of FIFOs
*
* Assumptions:
* - 'vc_id' is binary encoded (select is one-hot) //and 'select' are binary encoded.
*
*/
module NW_vc_buffers (push, pop, data_in, vc_id, select,
data_out, output_port, data_in_reg,
flags, buf_finished_empty,
head_is_tail, flit_buffer_out,
clk, rst_n);
`include "NW_functions.v"
// length of VC FIFOs
parameter size = 3;
// number of virtual channels
parameter n = 4;
// what does each FIFO hold?
//parameter type fifo_elements_t = flit_t;
// optimize FIFO parameters for different fields of flit
parameter optimize_fifo_fields = 0;
// export output of each VC buffer
parameter output_all_head_flits = 0;
input push;
input [n-1:0] pop;
input fifo_elements_t data_in;
input [clogb2(n)-1:0] vc_id;
// input [clogb2(n)-1:0] select;
input [n-1:0] select;
output fifo_elements_t data_out;
output fifov_flags_t flags [n-1:0];
output output_port_t output_port [n-1:0];
output flit_t data_in_reg;
output fifo_elements_t flit_buffer_out [n-1:0];
output [n-1:0] head_is_tail;
// at the end of the last clock cycle was vc_buffer[i] empty?
// - i.e. is the next flit entering an empty FIFO
// used for various things, e.g. abort detection
output [n-1:0] buf_finished_empty;
input clk, rst_n;
// logic [clogb2(n)-1:0] select_bin;
fifo_elements_t sel_fifo_out;
// single input register
fifo_elements_t in_reg;
// fifo outputs
fifo_elements_t fifo_out [n-1:0];
// fifo push/pop control
logic [n-1:0] push_fifo, pop_fifo;
// need to bypass FIFO and output contents of input register?
logic [n-1:0] fifo_bypass;
logic [n-1:0] fifo_bypass2;
output_port_t op_fifo_out [n-1:0];
control_flit_t control_fifo_out [n-1:0];
genvar i;
integer j;
assign data_in_reg = in_reg;
assign buf_finished_empty = fifo_bypass;
// assign select_bin = vc_index_t'(oh2bin(select));
generate
for (i=0; i<n; i++) begin:vcbufs
if (optimize_fifo_fields) begin
//
// use multiple FIFOs for different fields of flit so there
// parameters can be optimized individually. Allows us to
// move logic from start to end of clock cycle and vice-versa -
// depending on what is on critical path.
//
//
// break down into control and data fields
//
// *** CONTROL FIFO ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(control_flit_t),
.size(size),
.output_reg(0),
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_c
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.control),
.data_out(control_fifo_out[i]),
.flags(flags[i]),
.clk, .rst_n);
// *** OUTPUT PORT REQUEST ONLY ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(output_port_t),
.size(size),
.output_reg(1),
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_op
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.control.output_port),
.data_out(op_fifo_out[i]),
// .flags(flags[i]),
.clk, .rst_n);
always_comb
begin
fifo_out[i].control = control_fifo_out[i];
fifo_out[i].control.output_port = op_fifo_out[i];
end
// *** DATA FIFO ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(data_t),
.size(size),
.output_reg(0), // remove FIFO output register ****
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_d
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.data),
.data_out(fifo_out[i].data),
// .flags(flags[i]), only need one set of flags (obviously identical to control FIFO's)
.clk, .rst_n);
`ifdef DEBUG
// need FIFO for debug too
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(debug_flit_t),
.size(size),
.output_reg(1),
.input_reg(1)
) vc_fifo
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
//.data_in(in_reg.debug),
//.data_out(fifo_out[i].debug),
// .flags(flags[i]),
.clk, .rst_n);
`endif
end else begin
// **********************************
// SINGLE FIFO holds complete flit
// **********************************
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(fifo_elements_t),
.size(size),
.output_reg(0),
.input_reg(1)
) vc_fifo
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg),
.data_out(fifo_out[i]),
.flags(flags[i]),
.clk, .rst_n);
end
always@(posedge clk) begin
if (!rst_n) begin
fifo_bypass[i] <= 1'b1;
fifo_bypass2[i] <= 1'b1; // duplicate
end else begin
fifo_bypass[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);
fifo_bypass2[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]); // duplicate
end
end
assign push_fifo[i] = push & (vc_id==i);
assign pop_fifo[i] = pop[i]; //pop & (select==i);
assign head_is_tail[i] = fifo_out[i].control.tail; // && !flags[i].empty;
// we need to know which output port is required by all packets, in order to make
// virtual-channel and switch allocation requests.
assign output_port[i] =
fifo_bypass2[i] ? in_reg.control.output_port : fifo_out[i].control.output_port;
end
endgenerate
//
// assign data_out = (fifo_bypass[select]) ? in_reg : fifo_out[select];
//
NW_mux_oh_select #( .n(n))
fifosel (.data_in(fifo_out), .select(select), .data_out(sel_fifo_out));
assign sel_fifo_bypass = |(fifo_bypass & select);
assign data_out = sel_fifo_bypass ? in_reg : sel_fifo_out; //fifo_out[select_bin];
//
// some architectures require access to head of all VC buffers
//
generate
if (output_all_head_flits) begin
for (i=0; i<n; i++) begin:allvcs
assign flit_buffer_out[i] = (fifo_bypass[i]) ? in_reg : fifo_out[i];
end
end
endgenerate
//
// in_reg
//
always@(posedge clk) begin
if (!rst_n) begin
in_reg.control.valid <= 1'b0;
in_reg.control.tail <= 1'b1;
in_reg.control.output_port <='0;
end else begin
if (push) begin
in_reg <= data_in;
end else begin
in_reg.control.valid<=1'b0;
in_reg.control.output_port<='0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:31:02 05/20/2014
// Design Name: mips32
// Module Name: F:/mips32/mips32test.v
// Project Name: mips32
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mips32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mips32test;
// Inputs
reg rst;
reg clk;
reg [4:0] interrupts;
// Outputs
wire [31:0] port_PC;
wire [31:0] port_inst;
wire [31:0] port_alu;
// Instantiate the Unit Under Test (UUT)
mips32 uut (
.port_PC(port_PC),
.port_inst(port_inst),
.port_alu(port_alu),
.rst(rst),
.clk(clk),
.interrupts(interrupts)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
interrupts = 0;
// Wait 100 ns for global reset to finish
#100 rst = 1;
#20 rst = 0;
// Add stimulus here
end
initial begin
forever #20 clk = ~clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_LP_V
`define SKY130_FD_SC_LP__NOR3B_LP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_lp (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_lp (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_LP_V
|
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