text
stringlengths 938
1.05M
|
|---|
///////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.5
// \ \ Description :
// / /
// /__/ /\ Filename : ICAPE3.v
// \ \ / \
// \__\/\__ \
//
// Revision:
// 10/31/12 - Initial version.
// 02/10/14 - Fixed GSR deassertion (CR 772626).
// 02/28/14 - Updated timing (CR 778416).
// 05/28/14 - New simulation library message format.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ICAPE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] DEVICE_ID = 32'h03628093,
parameter ICAP_AUTO_SWITCH = "DISABLE",
parameter SIM_CFG_FILE_NAME = "NONE"
)(
output AVAIL,
output [31:0] O,
output PRDONE,
output PRERROR,
input CLK,
input CSIB,
input [31:0] I,
input RDWRB
);
localparam ICAP_WIDTH = "X32";
wire cso_b;
reg prog_b;
reg init_b;
reg [3:0] bw = 4'b0000;
wire busy_out;
reg cs_bi = 0, rdwr_bi = 0;
wire cs_b_t;
wire clk_in;
wire rdwr_b_t;
wire [31:0] dix;
wire dangle;
reg [31:0] di;
reg [31:0] data_rbt;
reg [7:0] tmp_byte0;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg icap_idone = 0;
reg clk_osc = 0;
reg sim_file_flag;
integer icap_fd;
reg notifier;
reg AVAIL_reg = 1'b0;
wire delay_CLK;
wire delay_CSIB;
wire delay_RDWRB;
wire [31:0] delay_I;
tri1 p_up;
tri init_tri = (icap_idone == 0) ? init_b : p_up;
tri (weak1, strong0) done_o = p_up;
tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix;
localparam MODULE_NAME = "ICAPE3";
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_RDWRB = RDWRB;
assign delay_CLK = CLK;
assign delay_CSIB = CSIB;
`endif
assign dix = (icap_idone == 1) ? delay_I : di;
assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi;
assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc;
assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi;
assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0;
assign AVAIL = AVAIL_reg;
always @(posedge icap_idone)
AVAIL_reg = 1'b1;
always
// if (icap_idone == 0)
#1000 clk_osc <= ~clk_osc;
always @(delay_CSIB or delay_RDWRB)
if ($time > 1 && icap_idone == 0) begin
$display ("Warning: [Unisim %s-1] ICAPE3 at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that. Instance: %m", MODULE_NAME, $time);
end
SIM_CONFIGE3 #(
.DEVICE_ID(DEVICE_ID),
.ICAP_SUPPORT("TRUE"),
.ICAP_WIDTH(ICAP_WIDTH)
)
SIM_CONFIGE3_INST (
.AVAIL(dangle),
.PRDONE(PRDONE),
.PRERROR(PRERROR),
.CSOB(cso_b),
.DONE(done_o),
.CCLK(clk_in),
.CSB(cs_b_t),
.D(di_t),
.INITB(init_tri),
.M(3'b110),
.PROGB(prog_b),
.RDWRB(rdwr_b_t)
);
initial begin
case (ICAP_AUTO_SWITCH)
"DISABLE", "ENABLE" : ;
default : begin
$display("Error: [Unisim %s-102] ICAP_AUTO_SWITCH attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, ICAP_AUTO_SWITCH);
#1 $finish;
end
endcase
icap_idone = 0;
sim_file_flag = 0;
if (SIM_CFG_FILE_NAME == "NONE") begin
sim_file_flag = 1;
end
else begin
icap_fd = $fopen(SIM_CFG_FILE_NAME, "r");
if (icap_fd == 0)
begin
$display("Error: [Unisim %s-2] The configure rbt data file %s was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name. Instance: %m", MODULE_NAME, SIM_CFG_FILE_NAME);
sim_file_flag = 1;
end
end
init_b = 1;
prog_b = 1;
rdwr_bi = 0;
cs_bi = 1;
#600000;
@(posedge clk_in)
prog_b = 0;
@(negedge clk_in)
init_b = 0;
#600000;
@(posedge clk_in)
prog_b = 1;
@(negedge clk_in) begin
init_b = 1;
cs_bi = 0;
end
if (sim_file_flag == 0) begin
while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin
if (done_o == 0) begin
tmp_byte3 = bit_revers8(data_rbt[31:24]);
tmp_byte2 = bit_revers8(data_rbt[23:16]);
tmp_byte1 = bit_revers8(data_rbt[15:8]);
tmp_byte0 = bit_revers8(data_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tmp_byte3};
@(negedge clk_in)
di = {24'b0, tmp_byte2};
@(negedge clk_in)
di = {24'b0, tmp_byte1};
@(negedge clk_in)
di = {24'b0, tmp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tmp_byte3, tmp_byte2};
@(negedge clk_in)
di = {16'b0, tmp_byte1, tmp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0};
end
end
else begin
@(negedge clk_in);
di = 32'hFFFFFFFF;
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display ("Info: [Unisim %s-3] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time);
icap_idone = 1;
end
end
end
$fclose(icap_fd);
#1000;
end
else begin
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'h000000DD;
@(negedge clk_in) begin
if (bw == 4'b0000)
di = 32'h00000088;
else if (bw == 4'b0010)
di = 32'h00000044;
else if (bw == 4'b0011)
di = 32'h00000022;
end
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hAA995566);
rbt_data_wr(32'h30008001);
rbt_data_wr(32'h00000005);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display ("Info: [Unisim %s-4] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time);
icap_idone = 1;
end
#1000;
end
end
task rbt_data_wr;
input [31:0] dat_rbt;
reg [7:0] tp_byte3;
reg [7:0] tp_byte2;
reg [7:0] tp_byte1;
reg [7:0] tp_byte0;
begin
tp_byte3 = bit_revers8(dat_rbt[31:24]);
tp_byte2 = bit_revers8(dat_rbt[23:16]);
tp_byte1 = bit_revers8(dat_rbt[15:8]);
tp_byte0 = bit_revers8(dat_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tp_byte3};
@(negedge clk_in)
di = {24'b0, tp_byte2};
@(negedge clk_in)
di = {24'b0, tp_byte1};
@(negedge clk_in)
di = {24'b0, tp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tp_byte3, tp_byte2};
@(negedge clk_in)
di = {16'b0, tp_byte1, tp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0};
end
end
endtask
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
specify
(CLK *> O) = (100:100:100, 100:100:100);
(CLK => PRDONE) = (100:100:100, 100:100:100);
(CLK => PRERROR) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
$setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
`endif //
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_top.v
// Version : 1.11
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// (c) 2010 NedoPC
//
// MUXes mouse and kbd data in two single databusses for zports
`include "../include/tune.v"
module zkbdmus(
input wire fclk,
input wire rst_n,
input wire [39:0] kbd_in, // key bits
input wire kbd_stb, // and strobe
input wire [ 7:0] mus_in,
input wire mus_xstb,
input wire mus_ystb,
input wire mus_btnstb,
input wire kj_stb,
input wire [7:0] zah,
output wire [ 4:0] kbd_data,
output wire [ 7:0] mus_data,
output reg [ 4:0] kj_data
);
reg [39:0] kbd;
reg [ 7:0] musx,musy,musbtn;
wire [4:0] keys [0:7]; // key matrix
reg [4:0] kout; // wire AND
`ifdef SIMULATE
initial
begin
// force kbd_data = 5'b11111;
force mus_data = 8'hFF;
force kj_data = 5'b00000;
kbd = 40'd0;
end
`endif
// store data from slavespi
//
always @(posedge fclk)
begin
if( kbd_stb )
kbd <= kbd_in;
if( mus_xstb )
musx <= mus_in;
if( mus_ystb )
musy <= mus_in;
if( mus_btnstb )
musbtn <= mus_in;
if( kj_stb )
kj_data <= mus_in[4:0];
end
// make keys
//
assign keys[0]={kbd[00],kbd[08],kbd[16],kbd[24],kbd[32]};// v c x z CS
assign keys[1]={kbd[01],kbd[09],kbd[17],kbd[25],kbd[33]};// g f d s a
assign keys[2]={kbd[02],kbd[10],kbd[18],kbd[26],kbd[34]};// t r e w q
assign keys[3]={kbd[03],kbd[11],kbd[19],kbd[27],kbd[35]};// 5 4 3 2 1
assign keys[4]={kbd[04],kbd[12],kbd[20],kbd[28],kbd[36]};// 6 7 8 9 0
assign keys[5]={kbd[05],kbd[13],kbd[21],kbd[29],kbd[37]};// y u i o p
assign keys[6]={kbd[06],kbd[14],kbd[22],kbd[30],kbd[38]};// h j k l EN
assign keys[7]={kbd[07],kbd[15],kbd[23],kbd[31],kbd[39]};// b n m SS SP
//
always @*
begin
kout = 5'b11111;
kout = kout & ({5{zah[0]}} | (~keys[0]));
kout = kout & ({5{zah[1]}} | (~keys[1]));
kout = kout & ({5{zah[2]}} | (~keys[2]));
kout = kout & ({5{zah[3]}} | (~keys[3]));
kout = kout & ({5{zah[4]}} | (~keys[4]));
kout = kout & ({5{zah[5]}} | (~keys[5]));
kout = kout & ({5{zah[6]}} | (~keys[6]));
kout = kout & ({5{zah[7]}} | (~keys[7]));
end
//
assign kbd_data = kout;
// make mouse
// FADF - buttons, FBDF - x, FFDF - y
//
assign mus_data = zah[0] ? ( zah[2] ? musy : musx ) : musbtn;
endmodule
|
module ID_01_Handler (ISin, CWout, literal);
input [13:0] ISin;
output reg [15:0] literal;
output reg [18:0] CWout;
always @(ISin) begin
case (ISin[13:9])
5'b10000: begin CWout = {6'b100001,ISin[8:6],ISin[5:3],7'b0000100}; //Increment
literal = 16'b1111111111111111; end
5'b10100: begin CWout = {6'b101001,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //Add
literal = 16'b1111111111111111; end
5'b10110: begin CWout = {6'b101101,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //Subtract
literal = 16'b1111111111111111; end
5'b10010: begin CWout = {6'b100101,ISin[8:6],ISin[5:3],7'b0000100}; //Decrement
literal = 16'b1111111111111111; end
5'b10001: begin CWout = {6'b100011,ISin[8:6],ISin[5:3],7'b0000100}; //Negative
literal = 16'b1111111111111111; end
5'b01100: begin CWout = {6'b011001,ISin[8:6],ISin[5:3],7'b0000100}; //Move A
literal = 16'b1111111111111111; end
5'b01010: begin CWout = {6'b010101,ISin[8:6],3'b000,ISin[2:0],4'b1100}; //Move B
literal = 16'b1111111111111111; end
5'b11001: begin CWout = {6'b110011,ISin[8:6],ISin[5:3],7'b0000100}; //Shift Right
literal = 16'b1111111111111111; end
5'b11000: begin CWout = {6'b110001,ISin[8:6],ISin[5:3],7'b0000100}; //Shift Left
literal = 16'b1111111111111111; end
5'b00000: begin CWout = {6'b000001,ISin[8:6],ISin[8:6],ISin[8:6],4'b0100}; //Clear
literal = 16'b1111111111111111; end
5'b01111: begin CWout = {6'b011111,ISin[8:6],ISin[8:6],ISin[8:6],4'b0100}; //Set
literal = 16'b1111111111111111; end
5'b00011: begin CWout = {6'b000111,ISin[8:6],ISin[5:3],7'b0000100}; //NOT
literal = 16'b1111111111111111; end
5'b01000: begin CWout = {6'b010001,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //AND
literal = 16'b1111111111111111; end
5'b01110: begin CWout = {6'b011101,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //OR
literal = 16'b1111111111111111; end
5'b00110: begin CWout = {6'b001101,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //XOR
literal = 16'b1111111111111111; end
5'b10111: begin CWout = {6'b110101,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //Multiply
literal = 16'b1111111111111111; end
5'b10101: begin CWout = {6'b110111,ISin[8:6],ISin[5:3],ISin[2:0],4'b1100}; //Add with Carry
literal = 16'b1111111111111111; end
5'b11011: begin CWout = {6'b111001,ISin[8:6],ISin[5:3],7'b0000100}; //Arithmetic Shift Right
literal = 16'b1111111111111111; end
endcase
end
endmodule |
module PIO16(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_gpio_writedata,
output [31:0] avs_gpio_readdata,
input [2:0] avs_gpio_address,
input [3:0] avs_gpio_byteenable,
input avs_gpio_write,
input avs_gpio_read,
output avs_gpio_waitrequest,
inout coe_P0,
inout coe_P1,
inout coe_P2,
inout coe_P3,
inout coe_P4,
inout coe_P5,
inout coe_P6,
inout coe_P7,
inout coe_P8,
inout coe_P9,
inout coe_P10,
inout coe_P11,
inout coe_P12,
inout coe_P13,
inout coe_P14,
inout coe_P15,
inout coe_P16
);
reg [15:0] io_data;
reg [15:0] io_out_en;
reg [15:0] read_data;
assign avs_gpio_readdata = read_data;
assign avs_gpio_waitrequest = 1'b0;
assign coe_P0 = (io_out_en[0]) ? io_data[0] : 1'bz;
assign coe_P1 = (io_out_en[1]) ? io_data[1] : 1'bz;
assign coe_P2 = (io_out_en[2]) ? io_data[2] : 1'bz;
assign coe_P3 = (io_out_en[3]) ? io_data[3] : 1'bz;
assign coe_P4 = (io_out_en[4]) ? io_data[4] : 1'bz;
assign coe_P5 = (io_out_en[5]) ? io_data[5] : 1'bz;
assign coe_P6 = (io_out_en[6]) ? io_data[6] : 1'bz;
assign coe_P7 = (io_out_en[7]) ? io_data[7] : 1'bz;
assign coe_P8 = (io_out_en[8]) ? io_data[8] : 1'bz;
assign coe_P9 = (io_out_en[9]) ? io_data[9] : 1'bz;
assign coe_P10 = (io_out_en[10]) ? io_data[10] : 1'bz;
assign coe_P11 = (io_out_en[11]) ? io_data[11] : 1'bz;
assign coe_P12 = (io_out_en[12]) ? io_data[12] : 1'bz;
assign coe_P13 = (io_out_en[13]) ? io_data[13] : 1'bz;
assign coe_P14 = (io_out_en[14]) ? io_data[14] : 1'bz;
assign coe_P15 = (io_out_en[15]) ? io_data[15] : 1'bz;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_gpio_address)
// 0: read_data <= 8;
// 1: read_data <= 32'hEA680001;
2: read_data <= {16'b0, coe_P15, coe_P14, coe_P13, coe_P12, coe_P11, coe_P10, coe_P9, coe_P8, coe_P7, coe_P6, coe_P5, coe_P4, coe_P3, coe_P2, coe_P1, coe_P0};
4: read_data <= {16'b0, io_out_en};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_data <= 0;
io_out_en <= 0;
end
else begin
if(avs_gpio_write) begin
case(avs_gpio_address)
2: begin
io_data <= avs_gpio_writedata[15:0];
end
4: begin
io_out_en <= avs_gpio_writedata[15:0];
end
default: begin end
endcase
end
end
end
endmodule
|
/*
* gpio.v
*
* Created on: 27.12.2017
* Author: Alexander Antonov <[email protected]>
* License: See LICENSE file for details
*/
module gpio
(
input [0:0] clk_i
, input [0:0] rst_i
, input [0:0] bus_req
, input [0:0] bus_we
, input [31:0] bus_addr
, input [3:0] bus_be
, input [31:0] bus_wdata
, output [0:0] bus_ack
, output reg [0:0] bus_resp
, output reg [31:0] bus_rdata
, input [15:0] gpio_bi
, output [15:0] gpio_bo
);
reg [3:0] led_register [3:0];
assign gpio_bo = {led_register[3], led_register[2], led_register[1], led_register[0]};
always @(posedge clk_i)
begin
if (rst_i) bus_resp <= 1'b0;
else bus_resp <= bus_req & !bus_we;
end
always @(posedge clk_i)
begin
if (rst_i) bus_rdata <= 32'h0;
else
begin
if (bus_addr[7:0] < 8'h10) bus_rdata <= led_register[bus_addr[3:2]];
else bus_rdata <= gpio_bi;
end
end
always @(posedge clk_i)
begin
if (rst_i) begin led_register[0] <= 8'h0; led_register[1] <= 8'h0; led_register[2] <= 8'h0; led_register[3] <= 8'h0; end
if (bus_req && bus_we && (bus_addr[7:0] < 8'h10)) led_register[bus_addr[3:2]] <= bus_wdata;
end
assign bus_ack = bus_req;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p4(/*AUTOARG*/
// Outputs
pcx_spc7_grant_bufp4_pa, spc6_pcx_req_bufp4_pq,
spc6_pcx_atom_bufp4_pq, spc7_pcx_req_bufp4_pq,
spc7_pcx_atom_bufp4_pq,
// Inputs
spc6_pcx_req_bufpt_pq_l, spc6_pcx_atom_bufpt_pq_l,
spc7_pcx_req_bufpt_pq_l, spc7_pcx_atom_bufpt_pq_l,
pcx_spc7_grant_bufp3_pa_l
);
output [4:0] pcx_spc7_grant_bufp4_pa;
output [4:0] spc6_pcx_req_bufp4_pq;
output spc6_pcx_atom_bufp4_pq;
output [4:0] spc7_pcx_req_bufp4_pq;
output spc7_pcx_atom_bufp4_pq;
input [4:0] spc6_pcx_req_bufpt_pq_l;
input spc6_pcx_atom_bufpt_pq_l;
input [4:0] spc7_pcx_req_bufpt_pq_l;
input spc7_pcx_atom_bufpt_pq_l;
input [4:0] pcx_spc7_grant_bufp3_pa_l;
assign pcx_spc7_grant_bufp4_pa = ~pcx_spc7_grant_bufp3_pa_l;
assign spc6_pcx_req_bufp4_pq[4:0] = ~spc6_pcx_req_bufpt_pq_l[4:0];
assign spc6_pcx_atom_bufp4_pq = ~spc6_pcx_atom_bufpt_pq_l;
assign spc7_pcx_req_bufp4_pq[4:0] = ~spc7_pcx_req_bufpt_pq_l[4:0];
assign spc7_pcx_atom_bufp4_pq = ~spc7_pcx_atom_bufpt_pq_l;
endmodule
|
// megafunction wizard: %ALTCLKLOCK%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: Sdram_PLL.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_PLL (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.locked (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "-3000",
altpll_component.clk2_divide_by = 1350,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 931,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "FAST",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_extclkena0 = "PORT_UNUSED",
altpll_component.port_extclkena1 = "PORT_UNUSED",
altpll_component.port_extclkena2 = "PORT_UNUSED",
altpll_component.port_extclkena3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "0.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING ""
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "0.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "18.62000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1350"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "931"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_PLL.ppf TRUE FALSE
|
// Issue-Execute Pipeline Register
module ex_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire valid_ex_pipe_reg_i,
input wire[5:0] op_ex_pipe_reg_i,
input wire jump_ex_pipe_reg_i,
input wire branch_ex_pipe_reg_i,
input wire reg_wr_ex_pipe_reg_i,
input wire mem_to_reg_ex_pipe_reg_i,
input wire mem_wr_ex_pipe_reg_i,
input wire[5:0] alu_op_ex_pipe_reg_i,
input wire[2:0] alu_src_ex_pipe_reg_i,
input wire reg_dst_ex_pipe_reg_i,
input wire[4:0] rt_ex_pipe_reg_i,
input wire[4:0] rs_ex_pipe_reg_i,
input wire[4:0] rd_ex_pipe_reg_i,
input wire[31:0] r_data_p1_ex_pipe_reg_i,
input wire[31:0] r_data_p2_ex_pipe_reg_i,
input wire[31:0] brn_eq_pc_ex_pipe_reg_i,
input wire[31:0] sign_imm_ex_pipe_reg_i,
input wire[4:0] shamt_ex_pipe_reg_i,
input wire brn_pred_ex_pipe_reg_i,
input wire[31:0] curr_pc_ex_pipe_reg_i,
input wire[31:0] next_pred_pc_ex_pipe_reg_i,
input wire[31:0] next_seq_pc_ex_pipe_reg_i,
input wire is_lw_ex_pipe_reg_i,
input wire use_link_reg_ex_pipe_reg_i,
output wire valid_ex_pipe_reg_o,
output wire[5:0] op_ex_pipe_reg_o,
output wire jump_ex_pipe_reg_o,
output wire branch_ex_pipe_reg_o,
output wire reg_wr_ex_pipe_reg_o,
output wire mem_to_reg_ex_pipe_reg_o,
output wire mem_wr_ex_pipe_reg_o,
output wire[5:0] alu_op_ex_pipe_reg_o,
output wire[2:0] alu_src_ex_pipe_reg_o,
output wire reg_dst_ex_pipe_reg_o,
output wire[4:0] rt_ex_pipe_reg_o,
output wire[4:0] rs_ex_pipe_reg_o,
output wire[4:0] rd_ex_pipe_reg_o,
output wire[31:0] r_data_p1_ex_pipe_reg_o,
output wire[31:0] r_data_p2_ex_pipe_reg_o,
output wire[31:0] brn_eq_pc_ex_pipe_reg_o,
output wire[31:0] sign_imm_ex_pipe_reg_o,
output wire[4:0] shamt_ex_pipe_reg_o,
output wire brn_pred_ex_pipe_reg_o,
output wire[31:0] curr_pc_ex_pipe_reg_o,
output wire[31:0] next_pred_pc_ex_pipe_reg_o,
output wire[31:0] next_seq_pc_ex_pipe_reg_o,
output wire is_lw_ex_pipe_reg_o,
output wire use_link_reg_ex_pipe_reg_o
);
reg valid_ex_pipe_reg;
reg[5:0] op_ex_pipe_reg;
reg jump_ex_pipe_reg;
reg branch_ex_pipe_reg;
reg reg_wr_ex_pipe_reg;
reg mem_to_reg_ex_pipe_reg;
reg mem_wr_ex_pipe_reg;
reg[5:0] alu_op_ex_pipe_reg;
reg[2:0] alu_src_ex_pipe_reg;
reg reg_dst_ex_pipe_reg;
reg[4:0] rt_ex_pipe_reg;
reg[4:0] rs_ex_pipe_reg;
reg[4:0] rd_ex_pipe_reg;
reg[31:0] r_data_p1_ex_pipe_reg;
reg[31:0] r_data_p2_ex_pipe_reg;
reg[31:0] brn_eq_pc_ex_pipe_reg;
reg[31:0] sign_imm_ex_pipe_reg;
reg[5:0] shamt_ex_pipe_reg;
reg brn_pred_ex_pipe_reg;
reg[31:0] curr_pc_ex_pipe_reg;
reg[31:0] next_pred_pc_ex_pipe_reg;
reg[31:0] next_seq_pc_ex_pipe_reg;
reg is_lw_ex_pipe_reg;
reg use_link_reg_ex_pipe_reg;
assign valid_ex_pipe_reg_o = valid_ex_pipe_reg;
assign op_ex_pipe_reg_o = op_ex_pipe_reg;
assign branch_ex_pipe_reg_o = branch_ex_pipe_reg;
assign jump_ex_pipe_reg_o = jump_ex_pipe_reg;
assign reg_wr_ex_pipe_reg_o = reg_wr_ex_pipe_reg;
assign mem_to_reg_ex_pipe_reg_o = mem_to_reg_ex_pipe_reg;
assign mem_wr_ex_pipe_reg_o = mem_wr_ex_pipe_reg;
assign alu_op_ex_pipe_reg_o = alu_op_ex_pipe_reg;
assign alu_src_ex_pipe_reg_o = alu_src_ex_pipe_reg;
assign reg_dst_ex_pipe_reg_o = reg_dst_ex_pipe_reg;
assign rt_ex_pipe_reg_o = rt_ex_pipe_reg;
assign rs_ex_pipe_reg_o = rs_ex_pipe_reg;
assign rd_ex_pipe_reg_o = rd_ex_pipe_reg;
assign r_data_p1_ex_pipe_reg_o = r_data_p1_ex_pipe_reg;
assign r_data_p2_ex_pipe_reg_o = r_data_p2_ex_pipe_reg;
assign brn_eq_pc_ex_pipe_reg_o = brn_eq_pc_ex_pipe_reg;
assign sign_imm_ex_pipe_reg_o = sign_imm_ex_pipe_reg;
assign shamt_ex_pipe_reg_o = shamt_ex_pipe_reg;
assign brn_pred_ex_pipe_reg_o = brn_pred_ex_pipe_reg;
assign curr_pc_ex_pipe_reg_o = curr_pc_ex_pipe_reg;
assign next_pred_pc_ex_pipe_reg_o = next_pred_pc_ex_pipe_reg;
assign next_seq_pc_ex_pipe_reg_o = next_seq_pc_ex_pipe_reg;
assign is_lw_ex_pipe_reg_o = is_lw_ex_pipe_reg;
assign use_link_reg_ex_pipe_reg_o = use_link_reg_ex_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
valid_ex_pipe_reg <= 0;
op_ex_pipe_reg <= 0;
branch_ex_pipe_reg <= 0;
jump_ex_pipe_reg <= 0;
reg_wr_ex_pipe_reg <= 0;
mem_to_reg_ex_pipe_reg <= 0;
mem_wr_ex_pipe_reg <= 0;
alu_op_ex_pipe_reg <= 0;
alu_src_ex_pipe_reg <= 0;
reg_dst_ex_pipe_reg <= 0;
rt_ex_pipe_reg <= 0;
rs_ex_pipe_reg <= 0;
rd_ex_pipe_reg <= 0;
r_data_p1_ex_pipe_reg <= 0;
r_data_p2_ex_pipe_reg <= 0;
brn_eq_pc_ex_pipe_reg <= 0;
sign_imm_ex_pipe_reg <= 0;
shamt_ex_pipe_reg <= 0;
brn_pred_ex_pipe_reg <= 0;
curr_pc_ex_pipe_reg <= 0;
next_pred_pc_ex_pipe_reg <= 0;
next_seq_pc_ex_pipe_reg <= 0;
is_lw_ex_pipe_reg <= 0;
use_link_reg_ex_pipe_reg <= 0;
end
else
begin
valid_ex_pipe_reg <= valid_ex_pipe_reg_i;
op_ex_pipe_reg <= op_ex_pipe_reg_i;
branch_ex_pipe_reg <= branch_ex_pipe_reg_i;
jump_ex_pipe_reg <= jump_ex_pipe_reg_i;
reg_wr_ex_pipe_reg <= reg_wr_ex_pipe_reg_i;
mem_to_reg_ex_pipe_reg <= mem_to_reg_ex_pipe_reg_i;
mem_wr_ex_pipe_reg <= mem_wr_ex_pipe_reg_i;
alu_op_ex_pipe_reg <= alu_op_ex_pipe_reg_i;
alu_src_ex_pipe_reg <= alu_src_ex_pipe_reg_i;
reg_dst_ex_pipe_reg <= reg_dst_ex_pipe_reg_i;
rt_ex_pipe_reg <= rt_ex_pipe_reg_i;
rs_ex_pipe_reg <= rs_ex_pipe_reg_i;
rd_ex_pipe_reg <= rd_ex_pipe_reg_i;
r_data_p1_ex_pipe_reg <= r_data_p1_ex_pipe_reg_i;
r_data_p2_ex_pipe_reg <= r_data_p2_ex_pipe_reg_i;
brn_eq_pc_ex_pipe_reg <= brn_eq_pc_ex_pipe_reg_i;
sign_imm_ex_pipe_reg <= sign_imm_ex_pipe_reg_i;
shamt_ex_pipe_reg <= shamt_ex_pipe_reg_i;
brn_pred_ex_pipe_reg <= brn_pred_ex_pipe_reg_i;
curr_pc_ex_pipe_reg <= curr_pc_ex_pipe_reg_i;
next_pred_pc_ex_pipe_reg <= next_pred_pc_ex_pipe_reg_i;
next_seq_pc_ex_pipe_reg <= next_seq_pc_ex_pipe_reg_i;
is_lw_ex_pipe_reg <= is_lw_ex_pipe_reg_i;
use_link_reg_ex_pipe_reg <= use_link_reg_ex_pipe_reg_i;
end
endmodule
|
//oob_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module oob_controller (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output reg linkup, //link is finished
output reg tx_comm_reset, //send a init OOB signal
output reg tx_comm_wake, //send a wake OOB signal
input comm_init_detect, //detected an init
input comm_wake_detect, //detected a wake on the rx lines
input [31:0] rx_din,
input [3:0] rx_isk,
input rx_is_elec_idle,
input rx_byte_is_aligned,
output reg [31:0] tx_dout,
output reg tx_isk,
output reg tx_set_elec_idle,
output [3:0] lax_state
);
//platform signals
//Parameters
//States
parameter IDLE = 4'h0;
parameter SEND_RESET = 4'h1;
parameter WAIT_FOR_INIT = 4'h2;
parameter WAIT_FOR_NO_INIT = 4'h3;
parameter WAIT_FOR_CONFIGURE_END = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter WAIT_FOR_WAKE = 4'h6;
parameter WAIT_FOR_NO_WAKE = 4'h7;
parameter WAIT_FOR_ALIGN = 4'h8;
parameter SEND_ALIGN = 4'h9;
parameter DETECT_SYNC = 4'hA;
parameter READY = 4'hB;
//Registers/Wires
reg [3:0] state;
reg [31:0] timer;
reg [1:0] no_align_count;
//timer used to send 'INITs', WAKEs' and read them
wire timeout;
wire align_detected;
wire sync_detected;
//Submodules
//Asynchronous Logic
assign timeout = (timer == 0);
assign align_detected = ((rx_isk > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
assign sync_detected = ((rx_isk > 0) && (rx_din == `PRIM_SYNC));
assign lax_state = state;
//Synchronous Logic
initial begin
tx_set_elec_idle <= 1;
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
linkup <= 0;
timer <= 0;
tx_comm_reset <= 1;
tx_comm_wake <= 0;
tx_dout <= 0;
tx_isk <= 0;
tx_set_elec_idle <= 1;
no_align_count <= 0;
end
else begin
//to support strobes, continuously reset the following signals
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_isk <= 0;
//timer (when reache 0 timeout has occured)
if (timer > 0) begin
timer <= timer - 1;
end
//main state machine, if this reaches ready an initialization sequence has completed
case (state)
IDLE: begin
linkup <= 0;
tx_set_elec_idle <= 1;
if (platform_ready) begin
$display ("oob_controller: send RESET");
//the platform is ready
// PLL has locked onto a clock
// DCM has generated the correct clocks
timer <= 32'h000000A2;
state <= SEND_RESET;
end
end
SEND_RESET: begin
//XXX: In the groundhog COMM RESET was continuously issued for a long period of time
//send the INIT sequence, this will initiate a communication with the
//SATA hard drive, or reset it so that it can be initiated to state
//strobe the comm init so that the platform will send an INIT OOB signal
tx_comm_reset <= 1;
if (timeout) begin
timer <= 32'd`INITIALIZE_TIMEOUT;
state <= WAIT_FOR_INIT;
$display ("oob_controller: wait for INIT");
end
end
WAIT_FOR_INIT: begin
//wait for a response from the SATA harddrive, if the timeout occurs
//go back to the SEND_RESET state
if (comm_init_detect) begin
//HD said 'sup' go to a wake
timer <= 0;
state <= WAIT_FOR_NO_INIT;
$display ("oob_controller: wait for INIT to go low");
end
if (timeout) begin
$display ("oob_controller: timed out while waiting for INIT");
state <= IDLE;
end
end
WAIT_FOR_NO_INIT: begin
//wait for the init signal to go low from the device
if (!comm_init_detect) begin
$display ("oob_controller: INIT deasserted");
$display ("oob_controller: start configuration");
state <= WAIT_FOR_CONFIGURE_END;
end
end
WAIT_FOR_CONFIGURE_END: begin
$display ("oob_controller: System is configured");
state <= SEND_WAKE;
timer <= 32'h0000009B;
//end
end
SEND_WAKE: begin
//XXX: In the groundhog COMM WAKE was continuously send for a long period of time
//Send the WAKE sequence to the hard drive to initiate a wakeup sequence
tx_comm_wake <= 1;
//XXX: Is this timeout correct?
//880uS
if (timeout) begin
//timer <= 32'd`INITIALIZE_TIMEOUT;
timer <= 32'h000203AD;
state <= WAIT_FOR_WAKE;
end
end
WAIT_FOR_WAKE: begin
//Wait for the device to send a COMM Wake
if (comm_wake_detect) begin
//Found a comm wake, now wait for the device to stop sending WAKE
timer <= 0;
state <= WAIT_FOR_NO_WAKE;
$display ("oob_controller: WAKE detected");
end
if (timeout) begin
//Timeout occured before reading WAKE
state <= IDLE;
$display ("oob_controller: timed out while waiting for WAKE to be asserted");
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
//The device stopped sending comm wake
//XXX: Is this timeout correct?
//880uS
$display ("oob_controller: detected WAKE deasserted");
$display ("oob_controller: Send Dialtone, wait for ALIGN");
//Going to add more timeout
timer <= 32'h203AD;
state <= WAIT_FOR_ALIGN;
end
end
WAIT_FOR_ALIGN: begin
//transmit the 'dialtone' continuously
//since we need to start sending actual data (not OOB signals, get out
// of tx idle)
tx_set_elec_idle <= 0;
//a sequence of 0's and 1's
tx_dout <= `DIALTONE;
tx_isk <= 0;
if (align_detected) begin
//we got something from the device!
timer <= 0;
//now send an align from my side
state <= SEND_ALIGN;
no_align_count <= 0;
$display ("oob_controller: ALIGN detected");
$display ("oob_controller: Send out my ALIGNs");
end
if (timeout) begin
//didn't read an align in time :( reset
$display ("oob_controller: timed out while waiting for AIGN");
state <= IDLE;
end
end
SEND_ALIGN: begin
tx_dout <= `PRIM_ALIGN;
tx_isk <= 1;
if (!align_detected) begin
$display ("oob_controller: detected ALIGN deasserted");
//XXX: Groundhog detects the SYNC primitve before declaring linkup
if (no_align_count == 3) begin
$display ("oob_controller: ready");
state <= READY;
end
else begin
no_align_count <= no_align_count + 1;
end
end
end
DETECT_SYNC: begin
if (sync_detected) begin
state <= READY;
end
end
READY: begin
linkup <= 1;
if (comm_init_detect) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
// soc_system_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.01.07.15:39:58
`timescale 1 ps / 1 ps
module soc_system_hps_0 #(
parameter F2S_Width = 3,
parameter S2F_Width = 2
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_cold_rst_req_n, // f2h_cold_reset_req.reset_n
input wire f2h_dbg_rst_req_n, // f2h_debug_reset_req.reset_n
input wire f2h_warm_rst_req_n, // f2h_warm_reset_req.reset_n
input wire [27:0] f2h_stm_hwevents, // f2h_stm_hw_events.stm_hwevents
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [127:0] f2h_WDATA, // .wdata
input wire [15:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [127:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [63:0] h2f_WDATA, // .wdata
output wire [7:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [63:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_cold_rst_req_n (f2h_cold_rst_req_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (f2h_dbg_rst_req_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (f2h_warm_rst_req_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (f2h_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
soc_system_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A211OI_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pipemem.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A memory unit to support a CPU, this time one supporting
// pipelined wishbone memory accesses. The goal is to be able
// to issue one pipelined wishbone access per clock, and (given the memory
// is fast enough) to be able to read the results back at one access per
// clock. This renders on-chip memory fast enough to handle single cycle
// (pipelined) access.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=30;
parameter [0:0] IMPLEMENT_LOCK=1'b0,
WITH_LOCAL_BUS=1'b1;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst;
input wire i_pipe_stb, i_lock;
// CPU interface
input wire [2:0] i_op;
input wire [31:0] i_addr;
input wire [31:0] i_data;
input wire [4:0] i_oreg;
// CPU outputs
output wire o_busy;
output wire o_pipe_stalled;
output reg o_valid;
output reg o_err;
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
output reg [3:0] o_wb_sel;
// Wishbone inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
reg cyc;
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
reg [3:0] rdaddr, wraddr;
wire [3:0] nxt_rdaddr;
reg [(4+5-1):0] fifo_oreg [0:15];
initial rdaddr = 0;
initial wraddr = 0;
always @(posedge i_clk)
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] };
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
wraddr <= 0;
else if (i_pipe_stb)
wraddr <= wraddr + 1'b1;
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
rdaddr <= 0;
else if ((i_wb_ack)&&(cyc))
rdaddr <= rdaddr + 1'b1;
assign nxt_rdaddr = rdaddr + 1'b1;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_addr[31:24]==8'hff)&&(WITH_LOCAL_BUS);
assign gbl_stb = (!lcl_stb)||(!WITH_LOCAL_BUS);
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
initial cyc = 0;
initial r_wb_cyc_lcl = 0;
initial r_wb_cyc_gbl = 0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
cyc <= 1'b0;
end else if (cyc)
begin
if ((~i_wb_stall)&&(~i_pipe_stb))
begin
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
// end else if ((i_pipe_stb)&&(~i_wb_stall))
// begin
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
end
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
cyc <= 1'b0;
end
end else if (i_pipe_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_stb_lcl <= lcl_stb;
o_wb_stb_gbl <= gbl_stb;
cyc <= 1'b1;
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
// o_wb_we <= i_op
end
always @(posedge i_clk)
if ((!cyc)||(!i_wb_stall))
begin
o_wb_addr <= i_addr[(AW+1):2];
if (!i_op[0]) // Always select everything on reads
o_wb_sel <= 4'b1111; // Op is even
else casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_sel <= 4'b1100; // Op = 5
4'b101?: o_wb_sel <= 4'b0011; // Op = 5
4'b1100: o_wb_sel <= 4'b1000; // Op = 5
4'b1101: o_wb_sel <= 4'b0100; // Op = 7
4'b1110: o_wb_sel <= 4'b0010; // Op = 7
4'b1111: o_wb_sel <= 4'b0001; // Op = 7
default: o_wb_sel <= 4'b1111; // Op = 7
endcase
casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
default: o_wb_data <= i_data;
endcase
end
always @(posedge i_clk)
if ((i_pipe_stb)&&(~cyc))
o_wb_we <= i_op[0];
initial o_valid = 1'b0;
always @(posedge i_clk)
o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
initial o_err = 1'b0;
always @(posedge i_clk)
o_err <= (cyc)&&(i_wb_err);
assign o_busy = cyc;
wire [8:0] w_wreg;
assign w_wreg = fifo_oreg[rdaddr];
always @(posedge i_clk)
o_wreg <= w_wreg[8:4];
always @(posedge i_clk)
casez(w_wreg[3:0])
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
default: o_result <= i_wb_data[31:0];
endcase
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
// Make verilator happy
// verilator lint_off UNUSED
wire unused;
assign unused = i_lock;
// verilator lint_on UNUSED
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cache_d.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cache_d (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [10:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [15:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cache_d_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk1_divide_by=10000 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK1" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=frame_rate" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_UNUSED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="counter_frame_rate_display_clk0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module frame_rate_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk1_divide_by = 10000,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk1",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //frame_rate_altpll
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_16_V
`define SKY130_FD_SC_HS__CLKBUF_16_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21bai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V |
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:33:00 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 128 reg
// wsiM0_MByteEn O 16 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 128
// wsiS0_MByteEn I 16
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFrameGate16B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [31 : 0] fgCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [127 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [15 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [127 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [15 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [127 : 0] wsiM0_MData;
wire [31 : 0] wciS0_SData;
wire [15 : 0] wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [168 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [127 : 0] wsi_Es_mData_w$wget;
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [71 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget;
wire [15 : 0] wsi_Es_mByteEn_w$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register byteCount
reg [31 : 0] byteCount;
wire [31 : 0] byteCount$D_IN;
wire byteCount$EN;
// register frameGateCtrl
reg [31 : 0] frameGateCtrl;
wire [31 : 0] frameGateCtrl$D_IN;
wire frameGateCtrl$EN;
// register frameSize
reg [31 : 0] frameSize;
wire [31 : 0] frameSize$D_IN;
wire frameSize$EN;
// register gateSize
reg [31 : 0] gateSize;
wire [31 : 0] gateSize$D_IN;
wire gateSize$EN;
// register gated
reg gated;
wire gated$D_IN, gated$EN;
// register op0MesgCnt
reg [31 : 0] op0MesgCnt;
wire [31 : 0] op0MesgCnt$D_IN;
wire op0MesgCnt$EN;
// register otherMesgCnt
reg [31 : 0] otherMesgCnt;
wire [31 : 0] otherMesgCnt$D_IN;
wire otherMesgCnt$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [168 : 0] wsiM_reqFifo_q_0;
reg [168 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [168 : 0] wsiM_reqFifo_q_1;
reg [168 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsiS_reqFifo
wire [168 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsipass_doMessagePush;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [168 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h11217, v__h3701, v__h3876, v__h4020;
reg [31 : 0] g_data__h10929;
wire [31 : 0] frameGateStatus__h10551,
rdat__h10963,
rdat__h11063,
rdat__h11077,
rdat__h11085,
rdat__h11091,
rdat__h11105,
rdat__h11113,
rdat__h11119,
rdat__h11130,
x__h10327;
wire [15 : 0] x__h10967;
wire NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439,
wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd169),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_wsipass_doMessagePush
assign WILL_FIRE_RL_wsipass_doMessagePush =
wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 &&
wci_cState == 3'd2 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[168:166] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsipass_doMessagePush ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h10929 } ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
wsiS_reqFifo$D_OUT :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
wsiS_reqFifo$D_OUT :
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_cState == 3'd2 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_wsipass_doMessagePush &&
(frameGateCtrl[3:0] == 4'h0 ||
frameGateCtrl[3:0] == 4'h1 && !gated) ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register byteCount
assign byteCount$D_IN =
NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ?
32'd16 :
x__h10327 ;
assign byteCount$EN = WILL_FIRE_RL_wsipass_doMessagePush ;
// register frameGateCtrl
assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign frameGateCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000004 ;
// register frameSize
assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ;
assign frameSize$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000008 ;
// register gateSize
assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ;
assign gateSize$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h0000000C ;
// register gated
assign gated$D_IN = !gated && byteCount == frameSize ;
assign gated$EN =
WILL_FIRE_RL_wsipass_doMessagePush &&
NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ;
// register op0MesgCnt
assign op0MesgCnt$D_IN = 32'h0 ;
assign op0MesgCnt$EN = 1'b0 ;
// register otherMesgCnt
assign otherMesgCnt$D_IN = 32'h0 ;
assign otherMesgCnt$EN = 1'b0 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset$D_IN = 1'd0 ;
assign wci_isReset_isInReset$EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN =
(wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_incCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_0
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[165]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
wsiS_reqFifo$D_OUT or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN =
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[165]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'b0 ;
assign wsiS_errorSticky$EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[165] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[165] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[165] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
WILL_FIRE_RL_wsipass_doMessagePush ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[165] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 =
!gated && byteCount == frameSize ||
gated && byteCount == gateSize ;
assign frameGateStatus__h10551 = { 31'd0, hasDebugLogic } ;
assign rdat__h10963 = hasDebugLogic ? { 16'd0, x__h10967 } : 32'd0 ;
assign rdat__h11063 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h11077 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h11085 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h11091 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h11105 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h11113 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h11119 = hasDebugLogic ? op0MesgCnt : 32'd0 ;
assign rdat__h11130 = hasDebugLogic ? otherMesgCnt : 32'd0 ;
assign wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 =
wsiS_reqFifo$EMPTY_N &&
(frameGateCtrl[3:0] != 4'h0 &&
(frameGateCtrl[3:0] != 4'h1 || gated) ||
wsiM_reqFifo_c_r != 2'd2) ;
assign x__h10327 = byteCount + 32'd16 ;
assign x__h10967 = { wsiS_statusR, wsiM_statusR } ;
always@(wci_reqF$D_OUT or
frameGateStatus__h10551 or
frameGateCtrl or
frameSize or
gateSize or
rdat__h10963 or
rdat__h11063 or
rdat__h11077 or
rdat__h11085 or
rdat__h11091 or
rdat__h11105 or rdat__h11113 or rdat__h11119 or rdat__h11130)
begin
case (wci_reqF$D_OUT[63:32])
32'h0: g_data__h10929 = frameGateStatus__h10551;
32'h00000004: g_data__h10929 = frameGateCtrl;
32'h00000008: g_data__h10929 = frameSize;
32'h0000000C: g_data__h10929 = gateSize;
32'h00000010: g_data__h10929 = rdat__h10963;
32'h00000014: g_data__h10929 = rdat__h11063;
32'h00000018: g_data__h10929 = rdat__h11077;
32'h0000001C: g_data__h10929 = rdat__h11085;
32'h00000020: g_data__h10929 = rdat__h11091;
32'h00000024: g_data__h10929 = rdat__h11105;
32'h00000028: g_data__h10929 = rdat__h11113;
32'h0000002C: g_data__h10929 = rdat__h11119;
32'h00000030: g_data__h10929 = rdat__h11130;
default: g_data__h10929 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
byteCount <= `BSV_ASSIGNMENT_DELAY 32'd16;
frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit;
frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0;
gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0;
gated <= `BSV_ASSIGNMENT_DELAY 1'd0;
op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN;
if (frameGateCtrl$EN)
frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN;
if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN;
if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN;
if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN;
if (op0MesgCnt$EN)
op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN;
if (otherMesgCnt$EN)
otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset$EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
if (wsiS_isReset_isInReset$EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
byteCount = 32'hAAAAAAAA;
frameGateCtrl = 32'hAAAAAAAA;
frameSize = 32'hAAAAAAAA;
gateSize = 32'hAAAAAAAA;
gated = 1'h0;
op0MesgCnt = 32'hAAAAAAAA;
otherMesgCnt = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3701 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3701,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h11217 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x",
v__h11217,
frameGateCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h4020 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4020,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h3876 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3876,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkFrameGate16B
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:30 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_fe1.v,v 1.8 2005/12/14 15:43:55 lutscher Exp $
// $Date: 2005/12/14 15:43:55 $
// $Log: rs_fe1.v,v $
// Revision 1.8 2005/12/14 15:43:55 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_fe1
//
// No user `defines in this module
module rs_fe1
//
// Generated module rs_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire mreset_n_i,
input wire [2:0] mcmd_i,
input wire [13:0] maddr_i,
input wire [31:0] mdata_i,
input wire mrespaccept_i,
output wire scmdaccept_o,
output wire [1:0] sresp_o,
output wire [31:0] sdata_o,
input wire clk_a,
input wire res_a_n_i,
input wire test_i,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output wire usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output wire [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output wire usr_rw_test_rd_p_o,
output wire usr_rw_test_wr_p_o,
output wire [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i,
output wire [3:0] dgatel_par_o,
output wire [4:0] dgates_par_o,
output wire [2:0] dummy_fe_par_o,
output wire [3:0] usr_w_test_par_o,
input wire usr_w_test_trans_done_p_i,
output wire usr_w_test_wr_p_o,
output wire [3:0] w_test_par_o,
output wire [3:0] sha_w_test_par_o,
input wire [2:0] r_test_par_i,
input wire upd_w_en_i,
input wire upd_w_force_i,
input wire upd_w_i
);
// Module parameters:
parameter P_TOCNT_WIDTH = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [13:0] addr;
wire [31:0] rd_data;
wire [63:0] rd_data_vec;
wire rd_err;
wire [1:0] rd_err_vec;
wire rd_wr;
wire trans_done;
wire [1:0] trans_done_vec;
wire trans_start;
wire [31:0] wr_data;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for rs_cfg_fe1_clk_a_i
rs_cfg_fe1_clk_a #(
.sync(1)
) rs_cfg_fe1_clk_a_i ( // Config register module for clock domain 'clk_a'
.addr_i(addr),
.clk_a(clk_a),
.dgatel_par_o(dgatel_par_o),
.dgates_par_o(dgates_par_o),
.dummy_fe_par_o(dummy_fe_par_o),
.r_test_par_i(r_test_par_i),
.rd_data_o(rd_data_vec[31:0]),
.rd_err_o(rd_err_vec[0]),
.rd_wr_i(rd_wr),
.res_a_n_i(res_a_n_i),
.sha_w_test_par_o(sha_w_test_par_o),
.test_i(test_i),
.trans_done_o(trans_done_vec[0]),
.trans_start(trans_start),
.upd_w_en_i(upd_w_en_i),
.upd_w_force_i(upd_w_force_i),
.upd_w_i(upd_w_i),
.usr_w_test_par_o(usr_w_test_par_o),
.usr_w_test_trans_done_p_i(usr_w_test_trans_done_p_i),
.usr_w_test_wr_p_o(usr_w_test_wr_p_o),
.w_test_par_o(w_test_par_o),
.wr_data_i(wr_data)
);
// End of Generated Instance Port Map for rs_cfg_fe1_clk_a_i
// Generated Instance Port Map for rs_cfg_fe1_i
rs_cfg_fe1 #(
.sync(0)
) rs_cfg_fe1_i ( // Config register module
.Cvbsdetect_par_o(Cvbsdetect_par_o),
.Cvbsdetect_set_p_i(Cvbsdetect_set_p_i),
.addr_i(addr),
.clk_f20(clk_f20),
.mvstart_par_o(mvstart_par_o),
.mvstop_par_o(mvstop_par_o),
.rd_data_o(rd_data_vec[63:32]),
.rd_err_o(rd_err_vec[1]),
.rd_wr_i(rd_wr),
.res_f20_n_i(res_f20_n_i),
.sha_r_test_par_i(sha_r_test_par_i),
.sha_rw2_par_o(sha_rw2_par_o),
.test_i(test_i),
.trans_done_o(trans_done_vec[1]),
.trans_start(trans_start),
.upd_r_en_i(upd_r_en_i),
.upd_r_force_i(upd_r_force_i),
.upd_r_i(upd_r_i),
.upd_rw_en_i(upd_rw_en_i),
.upd_rw_force_i(upd_rw_force_i),
.upd_rw_i(upd_rw_i),
.usr_r_test_par_i(usr_r_test_par_i),
.usr_r_test_rd_p_o(usr_r_test_rd_p_o),
.usr_r_test_trans_done_p_i(usr_r_test_trans_done_p_i),
.usr_rw_test_par_i(usr_rw_test_par_i),
.usr_rw_test_par_o(usr_rw_test_par_o),
.usr_rw_test_rd_p_o(usr_rw_test_rd_p_o),
.usr_rw_test_trans_done_p_i(usr_rw_test_trans_done_p_i),
.usr_rw_test_wr_p_o(usr_rw_test_wr_p_o),
.wd_16_test2_par_o(wd_16_test2_par_o),
.wd_16_test_par_o(wd_16_test_par_o),
.wr_data_i(wr_data),
.ycdetect_par_i(ycdetect_par_i)
);
// End of Generated Instance Port Map for rs_cfg_fe1_i
// Generated Instance Port Map for u0_ocp_target_i
ocp_target #(
.P_AWIDTH(14),
.P_DWIDTH(32),
.P_TOCNT_WIDTH(P_TOCNT_WIDTH), // __W_ILLEGAL_PARAM
.sync(0)
) u0_ocp_target_i ( // OCP target module
.addr_o(addr),
.clk_i(clk_f20),
.maddr_i(maddr_i),
.mcmd_i(mcmd_i),
.mdata_i(mdata_i),
.mreset_n_i(mreset_n_i),
.mrespaccept_i(mrespaccept_i),
.rd_data_i(rd_data),
.rd_err_i(rd_err),
.rd_wr_o(rd_wr),
.reset_n_i(res_f20_n_i),
.scmdaccept_o(scmdaccept_o),
.sdata_o(sdata_o),
.sresp_o(sresp_o),
.trans_done_i(trans_done),
.trans_start_o(trans_start),
.wr_data_o(wr_data)
);
// End of Generated Instance Port Map for u0_ocp_target_i
// Generated Instance Port Map for u1_rs_mcda_i
rs_mcda #(
.N_DOMAINS(2),
.N_SYNCDOM(1),
.P_DWIDTH(32)
) u1_rs_mcda_i ( // Multi-clock-domain Adapter
.clk_ocp(clk_f20),
.mreset_n_i(mreset_n_i),
.rd_data_o(rd_data),
.rd_data_vec_i(rd_data_vec),
.rd_err_o(rd_err),
.rd_err_vec_i(rd_err_vec),
.rst_ocp_n_i(res_f20_n_i),
.trans_done_o(trans_done),
.trans_done_vec_i(trans_done_vec),
.trans_start_i(trans_start)
);
// End of Generated Instance Port Map for u1_rs_mcda_i
endmodule
//
// End of Generated Module rtl of rs_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_SYMBOL_V
`define SKY130_FD_SC_HS__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy ([email protected])
* Description: Common Card Control Registers (CCCR)
* Controls many aspects of the card.
* Define values are values that do not change with implementation, for
* for example: CCCR version number and SDIO version number
* Parameter values change with every implementation, examples include
* Buffer depth and function numbers
*
* Changes:
*/
`include "sdio_cia_defines.v"
module sdio_cccr #(
parameter BUFFER_DEPTH = 8,
parameter EN_8BIT_BUS = 1'b0
)(
input clk,
input rst,
input i_activate,
input i_ready,
output reg o_ready,
output reg o_finished,
input i_write_flag,
input i_inc_addr,
input [17:0] i_address,
input i_data_stb,
input [17:0] i_data_count,
input [7:0] i_data_in,
output [7:0] o_data_out,
output reg o_data_stb, //If reading, this strobes a new piece of data in, if writing strobes data out
//Function Interface
output reg [7:0] o_func_enable,
input [7:0] i_func_ready,
output reg [7:0] o_func_int_enable,
input [7:0] i_func_int_pending,
output reg o_soft_reset,
output reg [2:0] o_func_abort_stb,
output reg o_en_card_detect_n,
output reg o_en_4bit_block_int, /* Enable interrupts durring 4-bit block data mode */
input i_func_active,
output reg o_bus_release_req_stb,
output reg [3:0] o_func_select,
input i_data_txrx_in_progress_flag,
input [7:0] i_func_exec_status,
input [7:0] i_func_ready_for_data,
output reg [15:0] o_max_f0_block_size,
output o_1_bit_mode,
output o_4_bit_mode,
output o_8_bit_mode,
output o_sdr_12,
output o_sdr_25,
output o_sdr_50,
output o_ddr_50,
output o_sdr_104,
output o_driver_type_a,
output o_driver_type_b,
output o_driver_type_c,
output o_driver_type_d,
output reg o_enable_async_interrupt
);
//local parameters
localparam IDLE = 4'h0;
localparam READ = 4'h1;
localparam WRITE = 4'h2;
//registes/wires
reg [17:0] data_count;
reg [1:0] driver_type;
reg [3:0] state;
wire [7:0] cccr_map [0:22];
output reg [1:0] bus_width;
reg [2:0] bus_speed_select;
reg [2:0] abort_sel;
wire [17:0] reg_addr;
wire [17:0] main_cis_addr;
//submodules
//asynchronous logic
assign main_cis_addr = `MAIN_CIS_START_ADDR;
assign reg_addr = i_inc_addr ? (i_address + data_count): i_address;
assign o_1_bit_mode = (bus_width == `D1_BIT_MODE);
assign o_4_bit_mode = (bus_width == `D4_BIT_MODE);
assign o_8_bit_mode = (bus_width == `D8_BIT_MODE);
assign o_sdr_12 = (bus_speed_select == `SDR12);
assign o_sdr_25 = (bus_speed_select == `SDR25);
assign o_sdr_50 = (bus_speed_select == `SDR50);
assign o_ddr_50 = (bus_speed_select == `DDR50);
assign o_sdr_104 = (bus_speed_select == `SDR104);
assign o_driver_type_a = (driver_type == `DRIVER_TYPE_A);
assign o_driver_type_b = (driver_type == `DRIVER_TYPE_B);
assign o_driver_type_c = (driver_type == `DRIVER_TYPE_C);
assign o_driver_type_d = (driver_type == `DRIVER_TYPE_D);
//Read Only
assign cccr_map[`CCCR_SDIO_REV_ADDR ] = {`SDIO_VERSION, `CCCR_FORMAT};
assign cccr_map[`SD_SPEC_ADDR ] = {4'h0, `SD_PHY_VERSION};
assign cccr_map[`IO_FUNC_ENABLE_ADDR ] = o_func_enable;
assign cccr_map[`IO_FUNC_READY_ADDR ] = i_func_ready;
assign cccr_map[`INT_ENABLE_ADDR ] = o_func_int_enable;
assign cccr_map[`INT_PENDING_ADDR ] = i_func_int_pending;
assign cccr_map[`IO_ABORT_ADDR ] = {4'h0, o_soft_reset, abort_sel};
assign cccr_map[`BUS_IF_CONTROL_ADDR ] = {o_en_card_detect_n, `SCSI, `ECSI, EN_8BIT_BUS, bus_width};
assign cccr_map[`CARD_COMPAT_ADDR ] = {`S4BLS, `LSC, o_en_4bit_block_int, `S4MI, `SBS, `SRW, `SMB, `SDC};
assign cccr_map[`CARD_CIS_LOW_ADDR ] = main_cis_addr[7:0];
assign cccr_map[`CARD_CIS_MID_ADDR ] = main_cis_addr[15:8];
assign cccr_map[`CARD_CIS_HIGH_ADDR ] = {6'b000000, main_cis_addr[17:16]};
assign cccr_map[`BUS_SUSPEND_ADDR ] = {6'b000000, o_bus_release_req_stb, i_func_active};
assign cccr_map[`FUNC_SELECT_ADDR ] = {i_data_txrx_in_progress_flag, 3'b000, o_func_select};
assign cccr_map[`EXEC_SELECT_ADDR ] = {i_func_exec_status};
assign cccr_map[`READY_SELECT_ADDR ] = {i_func_ready_for_data};
assign cccr_map[`FN0_BLOCK_SIZE_0_ADDR] = {o_max_f0_block_size[15:8]};
assign cccr_map[`FN0_BLOCK_SIZE_1_ADDR] = {o_max_f0_block_size[7:0]};
assign cccr_map[`POWER_CONTROL_ADDR ] = {4'h0, `TPC,`EMPC, SMPC};
assign cccr_map[`BUS_SPD_SELECT_ADDR ] = {4'h0, bus_speed_select, `SHS};
assign cccr_map[`UHS_I_SUPPORT_ADDR ] = {5'h0, `SSDR50, `SSDR104, `SSDR50};
assign cccr_map[`DRIVE_STRENGTH_ADDR ] = {2'b00, driver_type, 1'b0, `SDTC, `SDTC, `SDTA};
assign cccr_map[`INTERRUPT_EXT_ADDR ] = {6'h00, o_enable_async_interrupt, `SAI};
//synchronous logic
always @ (posedge clk) begin
//De-assert strobes
o_data_stb <= 0;
o_soft_reset <= 0;
o_func_abort_stb <= 8'h0;
abort_sel <= 0;
o_bus_release_req_stb <= 0;
o_ready <= 0;
bus_width <= 0;
if (rst) begin
data_count <= 0;
state <= IDLE;
o_func_enable <= 8'h0; //No functions are enabled
o_func_int_enable <= 8'h0; //No function interrupts are enabled
o_en_4bit_block_int <= 0;
o_en_card_detect_n <= 0;
o_en_4bit_block_int <= 0;
o_en_4bit_block_int <= 0; //Do not enable this in SDR50, SDR104, DDR50 modes
o_func_select <= 0;
o_max_f0_block_size <= 0; //Max Block Size is set by host
bus_speed_select <= 0;
driver_type <= 0;
o_enable_async_interrupt<= 0;
o_ready <= 0;
o_finished <= 0;
end
else begin
o_func_abort_stb[abort_sel] <= 1;
case (state)
IDLE: begin
data_count <= 0;
o_ready <= 0;
o_finished <= 0;
if (i_activate) begin
if (i_write_flag) begin
state <= WRITE_ACTIVATE;
end
else begin
state <= READ_ACTIVATE;
end
end
end
WRITE_ACTIVATE: begin
//Data From Host Comming into this device
if (data_count >= i_data_count)begin
state <= FINISHED;
end
else begin
o_ready <= 1;
if (i_data_stb) begin
case (i_address + data_count)
`IO_FUNC_ENABLE_ADDR:
o_func_enable <= i_data;
`INT_ENABLE_ADDR:
o_func_int_enable <= i_data;
`IO_ABORT_ADDR: begin
o_soft_reset <= i_data[3];
abort_sel <= i_data[2:0];
end
`BUS_IF_CONTROL_ADDR: begin
o_en_card_detect_n <= i_data[7];
bus_width <= i_data[1:0];
end
`BUS_SUSPEND_ADDR:
o_bus_release_req_stb <= i_data[1];
`FUNC_SELECT_ADDR:
o_func_select <= i_data[3:0];
`FN0_BLOCK_SIZE_0_ADDR:
o_max_f0_block_size[15:8] <= i_data;
`FN0_BLOCK_SIZE_1_ADDR:
o_max_f0_block_size[7:0] <= i_data;
`BUS_SPD_SELECT_ADDR:
bus_select <= i_data[3:1];
`DRIVE_STRENGTH_ADDR:
driver_type <= i_data[6:4];
`INTERRUPT_EXT_ADDR:
o_enable_async_interrupt <= i_data[1];
default: begin
end
endcase
data_count <= data_count + 1;
end
end
end
READ_ACTIVATE: begin
if (data_count >= i_data_count) begin
state <= FINISHED;
end
else if (i_ready) begin
o_data <= cccr_map[i_address + data_count];
o_data_stb <= 1;
data_count <= data_count + 1;
end
end
FINISHED: begin
o_finished <= 1;
if (!i_activate) begin
state <= IDLE;
end
end
default: begin
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_4_V
`define SKY130_FD_SC_LP__INVKAPWR_4_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog wrapper for invkapwr with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_4 (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_4_V
|
module top_string(char, clk, new, btn1, string, completeOut, changeOut);
input [6:0] char;
input clk, new, btn1;
output [76:0] string;
output completeOut, changeOut;
wire complete, change;
wire wCenter, wCene, wCvirgul, wCdelete, wCnum, wDelete, wAdd, wCcounter, wAddEnhe, wLoad, wEnter, wVirgul, wchangeVirgul;
wire [6:0] wMuxOut;
wire [3:0] wCounter;
control control1 (.clk(clk), .cEnter(wCenter), .cEne(wCene), .cDelete(wCdelete), .cCounter(wCcounter), .new(new), .reset(btn1), .cNum(wCnum), .complete(complete), .enter(wEnter), .delete(wDelete), .add(wAdd), .load(wLoad), .addEnhe(wAddEnhe), .change(change), .virgul(wVirgul), .changeVirgul(wchangeVirgul));
charComp charComp1 (.enter(wEnter), .char(char), .cEnter(wCenter), .cEne(wCene), .cVirgul(wCvirgul), .cDelete(wCdelete), .cNum(wCnum));
countComp countComp1 (.counter(wCounter), .cCounter(wCcounter));
counter counter1 (.delete(wDelete), .add(wAdd), .clk(clk), .counter(wCounter), .load(wLoad));
mux mux1 (.char(char), .addEnhe(wAddEnhe), .muxOut(wMuxOut));
shiftString shiftString1 (.load(wLoad), .add(wAdd), .clk(clk), .delete(wDelete), .muxOut(wMuxOut), .string(string));
memory memory1 (.cEnter(wCenter), .cVirgul(wCvirgul), .clk(clk), .enter(wEnter), .virgul(wVirgul), .load(wLoad), .changeVirgul(wchangeVirgul), .addEnhe(wAddEnhe));
adapter adapter1 (.change(change), .complete(complete), .clk(clk), .changeOut(changeOut), .completeOut(completeOut));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_TB_V
`define SKY130_FD_SC_HD__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd2 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-need to work on dual mode for pn sequence
`timescale 1ns/100ps
module axi_ad9361_rx_channel (
// adc interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
adc_data_q,
adc_or,
dac_data,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_valid,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input adc_valid;
input [11:0] adc_data;
input [11:0] adc_data_q;
input adc_or;
input [11:0] dac_data;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output adc_iqcor_valid;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [11:0] adc_data_s;
wire adc_dfmt_valid_s;
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilter_valid_s;
wire [15:0] adc_dcfilter_data_i_s;
wire [15:0] adc_dcfilter_data_q_s;
wire adc_iqcor_enb_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
wire [ 3:0] adc_pnseq_sel_s;
wire [ 3:0] adc_data_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out;
assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
axi_ad9361_rx_pnmon #(.IQSEL (IQSEL), .PRBS_SEL (CHID)) i_rx_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data_i (adc_data),
.adc_data_q (adc_data_q),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_valid_s = adc_valid;
assign adc_dfmt_data_s = {4'd0, adc_data_s};
end else begin
ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data_s),
.valid_out (adc_dfmt_valid_s),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (adc_dfmt_valid_s),
.data (adc_dfmt_data_s),
.valid_out (adc_dcfilter_valid_s),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_iqcor_valid = adc_dcfilter_valid_s;
assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
end else begin
ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s),
.data_i (adc_dcfilter_data_i_s),
.data_q (adc_dcfilter_data_q_s),
.valid_out (adc_iqcor_valid),
.data_out (adc_iqcor_data),
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID (CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (adc_data_sel_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module top (
input clk,
input RXD,
output TXD,
inout LED0,
inout LED1,
inout LED2,
inout LED3,
inout LED4,
inout LED5,
inout LED6,
inout LED7,
inout PORTB0,
inout PORTB1,
inout PORTB2,
inout PORTB3,
inout PORTB4,
inout PORTB5,
inout PORTB6,
inout PORTB7,
output CDCLK,
output SCK,
output SDAT,
output LRCK,
input G_RST,
inout D0,
inout D1,
inout D2,
inout D3,
inout D4,
inout D5,
inout D6,
inout D7,
inout D8,
inout D9,
inout D10,
inout D11,
inout D12,
inout D13,
inout D14,
inout D15,
inout DMARQ,
input WRn,
input RDn,
inout IORDY,
input DMACKn,
inout INTRQ,
input CS0n,
input CS1n,
input A0,
input A1,
input A2
);
localparam REFCLK_FREQ = 11289600;
localparam CDCLK_FREQ = 33868800;
localparam CPU_FREQ = 39513600;
localparam CLKOUT_FREQ = CPU_FREQ*2;
wire clkout, lock, lock_cdclk;
wire [15:0] sram_a;
wire [31:0] d_to_ide_or_cdda_or_sdcard, d_from_ide;
wire [15:0] d_from_sdcard;
wire [7:0] d_from_cdda;
wire sram_cs, sram_oe, sram_wait_ide, sram_wait_cdda, sram_wait_sdcard;
wire [3:0] sram_wstrb;
wire ide_irq;
reg ide_irq_sync;
wire cs_gate, sram_cs_ide, sram_cs_cdda, sram_cs_sdcard;
wire sdcard_sck, sdcard_miso, sdcard_mosi;
wire [7:0] sdcard_dma_data;
wire [8:0] sdcard_dma_addr;
wire sdcard_dma_strobe;
wire rv32_reset;
assign cs_gate = ~clkout_cpu;
assign sram_cs_ide = sram_cs & sram_a[12] & cs_gate;
assign sram_cs_sdcard = sram_cs & ~sram_a[12] & ~sram_a[11] & cs_gate;
assign sram_cs_cdda = sram_cs & ~sram_a[12] & sram_a[11] & cs_gate;
generate
if(REFCLK_FREQ != CLKOUT_FREQ) begin : use_clkgen
clkgen #(.INCLOCK_FREQ(REFCLK_FREQ),
.OUTCLOCK_FREQ(CLKOUT_FREQ))
clkgen_inst(.clkin(clk), .clkout(clkout), .lock(lock));
end
else begin : use_refclk
assign clkout = clk;
assign lock = 1'b1;
end
endgenerate
clkgen #(.INCLOCK_FREQ(REFCLK_FREQ),
.OUTCLOCK_FREQ(CDCLK_FREQ))
clkgen_cdclk_inst(.clkin(clk), .clkout(CDCLK), .lock(lock_cdclk));
reg clkout_cpu;
always @(posedge clkout) begin
clkout_cpu <= ~clkout_cpu;
if (~clkout_cpu)
ide_irq_sync <= ide_irq;
end
ide_interface #(.drv(1'b0), .add_read_ws(0))
ide_inst(.dd({D15,D14,D13,D12,D11,D10,D9,D8,D7,D6,D5,D4,D3,D2,D1,D0}),
.da({A2,A1,A0}), .cs1fx_(CS0n), .cs3fx_(CS1n), .dasp_(),
.dior_(RDn), .diow_(WRn), .dmack_(DMACKn), .dmarq(DMARQ),
.intrq(INTRQ), .iocs16_(), .iordy(IORDY), .pdiag_(),
.reset_(G_RST), .csel(1'b0), .clk(clkout), .sram_a(sram_a),
.sram_d_in(d_to_ide_or_cdda_or_sdcard), .sram_d_out(d_from_ide),
.sram_cs(sram_cs_ide), .sram_oe(sram_oe), .sram_wstrb(sram_wstrb),
.sram_wait(sram_wait_ide), .cpu_irq(ide_irq),
.sdcard_dma_data(sdcard_dma_data), .sdcard_dma_addr(sdcard_dma_addr),
.sdcard_dma_strobe(sdcard_dma_strobe));
cdda_interface #(.CLK_FREQUENCY(CLKOUT_FREQ))
cdda_inst(.bck(SCK), .sd(SDAT), .lrck(LRCK),
.clk(clkout), .rst(rv32_reset),
.sram_a(sram_a),
.sram_d_in(d_to_ide_or_cdda_or_sdcard), .sram_d_out(d_from_cdda),
.sram_cs(sram_cs_cdda), .sram_oe(sram_oe), .sram_wstrb(sram_wstrb),
.sram_wait(sram_wait_cdda), .sdcard_dma_data(sdcard_dma_data),
.sdcard_dma_addr(sdcard_dma_addr), .sdcard_dma_strobe(sdcard_dma_strobe));
sdcard_interface
sdcard_inst(.sclk(sdcard_sck), .mosi(sdcard_mosi), .miso(sdcard_miso),
.clk(clkout), .rst(rv32_reset),
.sram_a(sram_a), .sram_d_in(d_to_ide_or_cdda_or_sdcard[15:0]),
.sram_d_out(d_from_sdcard), .sram_cs(sram_cs_sdcard),
.sram_oe(sram_oe), .sram_wstrb(sram_wstrb[1:0]), .sram_wait(sram_wait_sdcard),
.dma_data(sdcard_dma_data), .dma_addr(sdcard_dma_addr), .dma_strobe(sdcard_dma_strobe));
vexriscv_wrapper #(.mem_size(12),
.CLK_FREQUENCY(CPU_FREQ),
.AVR109_BAUD_RATE(115200),
`ifdef PM_INIT
.mem_init(`PM_INIT),
`endif
)
vexrv_inst(.clk(clkout_cpu), .rst_out(rv32_reset),
.porta({LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0}),
.portb({PORTB7, PORTB6, PORTB5, PORTB4, PORTB3, PORTB2, PORTB1, PORTB0}),
.sdcard_sck(sdcard_sck), .sdcard_mosi(sdcard_mosi),
.sdcard_miso(sdcard_miso), .rxd(RXD), .txd(TXD),
.extram_a(sram_a),
.extram_d_in(sram_a[12]? d_from_ide :
{16'h0000, (sram_a[11]? {8'h00, d_from_cdda} : d_from_sdcard)}),
.extram_d_out(d_to_ide_or_cdda_or_sdcard),
.extram_cs(sram_cs), .extram_oe(sram_oe), .extram_wstrb(sram_wstrb),
.ext_irq3(ide_irq_sync));
endmodule // top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_4_V
`define SKY130_FD_SC_HD__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_4_V
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtwiz_buffbypass_tx #(
parameter integer P_BUFFER_BYPASS_MODE = 0,
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
parameter integer P_MASTER_CHANNEL_POINTER = 0
)(
// User interface ports
input wire gtwiz_buffbypass_tx_clk_in,
input wire gtwiz_buffbypass_tx_reset_in,
input wire gtwiz_buffbypass_tx_start_user_in,
input wire gtwiz_buffbypass_tx_resetdone_in,
output reg gtwiz_buffbypass_tx_done_out = 1'b0,
output reg gtwiz_buffbypass_tx_error_out = 1'b0,
// Transceiver interface ports
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphaligndone_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinitdone_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysresetdone_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncout_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncdone_in,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlyreset_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalign_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalignen_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlypd_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinit_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphovrden_out,
output reg [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlybypass_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyen_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyovrden_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlytstclk_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyhold_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyupdown_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncmode_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncallin_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncin_out
);
// -------------------------------------------------------------------------------------------------------------------
// Transmitter buffer bypass conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
localparam [1:0] ST_BUFFBYPASS_TX_IDLE = 2'd0;
localparam [1:0] ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET = 2'd1;
localparam [1:0] ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE = 2'd2;
localparam [1:0] ST_BUFFBYPASS_TX_DONE = 2'd3;
generate if (1) begin: gen_gtwiz_buffbypass_tx_main
// Use auto mode buffer bypass
if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
// For single-lane auto mode buffer bypass, perform specified input port tie-offs
if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
assign txphdlyreset_out = 1'b0;
assign txphalign_out = 1'b0;
assign txphalignen_out = 1'b0;
assign txphdlypd_out = 1'b0;
assign txphinit_out = 1'b0;
assign txphovrden_out = 1'b0;
assign txdlybypass_out = 1'b0;
assign txdlyen_out = 1'b0;
assign txdlyovrden_out = 1'b0;
assign txphdlytstclk_out = 1'b0;
assign txdlyhold_out = 1'b0;
assign txdlyupdown_out = 1'b0;
assign txsyncmode_out = 1'b1;
assign txsyncallin_out = txphaligndone_in;
assign txsyncin_out = 1'b0;
end
// For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
else begin : gen_assign_multi_chan
assign txphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphalign_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphalignen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphdlypd_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphinit_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txdlybypass_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txdlyen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txdlyovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txphdlytstclk_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txdlyhold_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign txdlyupdown_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
genvar gi;
for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_txsyncmode
if (gi == P_MASTER_CHANNEL_POINTER)
assign txsyncmode_out[gi] = 1'b1;
else
assign txsyncmode_out[gi] = 1'b0;
end
assign txsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&txphaligndone_in}};
assign txsyncin_out = {P_TOTAL_NUMBER_OF_CHANNELS{txsyncout_in[P_MASTER_CHANNEL_POINTER]}};
end
// Detect the rising edge of the transmitter reset done re-synchronized input. Assign an internal buffer bypass
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
wire gtwiz_buffbypass_tx_resetdone_sync_int;
gtwizard_ultrascale_v1_7_1_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.rst_in (gtwiz_buffbypass_tx_resetdone_in),
.rst_out (gtwiz_buffbypass_tx_resetdone_sync_int)
);
reg gtwiz_buffbypass_tx_resetdone_reg = 1'b0;
wire gtwiz_buffbypass_tx_start_int;
always @(posedge gtwiz_buffbypass_tx_clk_in) begin
if (gtwiz_buffbypass_tx_reset_in)
gtwiz_buffbypass_tx_resetdone_reg <= 1'b0;
else
gtwiz_buffbypass_tx_resetdone_reg <= gtwiz_buffbypass_tx_resetdone_sync_int;
end
assign gtwiz_buffbypass_tx_start_int = (gtwiz_buffbypass_tx_resetdone_sync_int &&
~gtwiz_buffbypass_tx_resetdone_reg) || gtwiz_buffbypass_tx_start_user_in;
// Synchronize the master channel's buffer bypass completion output (TXSYNCDONE) into the local clock domain
// and detect its rising edge for purposes of safe state machine transitions
reg gtwiz_buffbypass_tx_master_syncdone_sync_reg = 1'b0;
wire gtwiz_buffbypass_tx_master_syncdone_sync_int;
wire gtwiz_buffbypass_tx_master_syncdone_sync_re;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_master_syncdone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.i_in (txsyncdone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_tx_master_syncdone_sync_int)
);
always @(posedge gtwiz_buffbypass_tx_clk_in)
gtwiz_buffbypass_tx_master_syncdone_sync_reg <= gtwiz_buffbypass_tx_master_syncdone_sync_int;
assign gtwiz_buffbypass_tx_master_syncdone_sync_re = gtwiz_buffbypass_tx_master_syncdone_sync_int &&
~gtwiz_buffbypass_tx_master_syncdone_sync_reg;
// Synchronize the master channel's phase alignment completion output (TXPHALIGNDONE) into the local clock domain
wire gtwiz_buffbypass_tx_master_phaligndone_sync_int;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_master_phaligndone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.i_in (txphaligndone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_tx_master_phaligndone_sync_int)
);
// Implement a simple state machine to perform the transmitter auto mode buffer bypass procedure
reg [1:0] sm_buffbypass_tx = ST_BUFFBYPASS_TX_IDLE;
always @(posedge gtwiz_buffbypass_tx_clk_in) begin
if (gtwiz_buffbypass_tx_reset_in) begin
gtwiz_buffbypass_tx_done_out <= 1'b0;
gtwiz_buffbypass_tx_error_out <= 1'b0;
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE;
end
else begin
case (sm_buffbypass_tx)
// Upon assertion of the internal buffer bypass start signal, assert TXDLYSRESET output(s)
default: begin
if (gtwiz_buffbypass_tx_start_int) begin
gtwiz_buffbypass_tx_done_out <= 1'b0;
gtwiz_buffbypass_tx_error_out <= 1'b0;
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET;
end
end
// De-assert the TXDLYSRESET output(s)
ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET: begin
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE;
end
// Upon assertion of the synchronized TXSYNCDONE indicator, transition to the final state
ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE: begin
if (gtwiz_buffbypass_tx_master_syncdone_sync_re)
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DONE;
end
// Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
// synchronized TXPHALIGNDONE indicator is not high
ST_BUFFBYPASS_TX_DONE: begin
gtwiz_buffbypass_tx_done_out <= 1'b1;
gtwiz_buffbypass_tx_error_out <= ~gtwiz_buffbypass_tx_master_phaligndone_sync_int;
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE;
end
endcase
end
end
end
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2; //Deepak
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
/*
cin = 15'b110101100000011;
$display(cin[1]," << b1 b2 >>",cin[2]);
$display(cin[3]," << b1 b2 >>",cin[4]);
// @ t=0,
#1;
cin = 15'b111000111000011;
#1;
cin = 15'b110011101010011;
#1;
cin = 15'b111101110010011;
#1;
cin = 15'b111110000100011;
#20;
*/
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 02:51:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.v
// Design : system_vga_sync_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_0_0,vga_sync,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_0_0_vga_sync U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
(* ORIG_REF_NAME = "vga_sync" *)
module system_vga_sync_0_0_vga_sync
(xaddr,
active,
hsync,
vsync,
yaddr,
clk,
rst);
output [9:0]xaddr;
output active;
output hsync;
output vsync;
output [9:0]yaddr;
input clk;
input rst;
wire active;
wire active0;
wire active_i_2_n_0;
wire active_i_3_n_0;
wire clk;
wire \h_count_reg[8]_i_1_n_0 ;
wire \h_count_reg[9]_i_2_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire [9:0]p_0_in;
wire [9:0]p_0_in__0;
wire rst;
wire sel;
wire \v_count_reg[9]_i_3_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire \v_count_reg[9]_i_6_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT5 #(
.INIT(32'h00000A2A))
active_i_1
(.I0(active_i_3_n_0),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[7]),
.I4(yaddr[9]),
.O(active0));
LUT1 #(
.INIT(2'h1))
active_i_2
(.I0(rst),
.O(active_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_3
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.O(active_i_3_n_0));
FDCE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(active0),
.Q(active));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[3]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\h_count_reg[4]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h33332333CCCCCCCC))
\h_count_reg[5]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h6A))
\h_count_reg[6]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[7]_i_1
(.I0(xaddr[7]),
.I1(\h_count_reg[9]_i_2_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h3FFFFFF7C0000000))
\h_count_reg[8]_i_1
(.I0(xaddr[9]),
.I1(\h_count_reg[9]_i_2_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[7]),
.I4(xaddr[6]),
.I5(xaddr[8]),
.O(\h_count_reg[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7F80EF00FF00FF00))
\h_count_reg[9]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[9]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h80000000))
\h_count_reg[9]_i_2
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.I3(xaddr[4]),
.I4(xaddr[3]),
.O(\h_count_reg[9]_i_2_n_0 ));
FDCE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[0]),
.Q(xaddr[0]));
FDCE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[1]),
.Q(xaddr[1]));
FDCE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[2]),
.Q(xaddr[2]));
FDCE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[3]),
.Q(xaddr[3]));
FDCE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[4]),
.Q(xaddr[4]));
FDCE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[5]),
.Q(xaddr[5]));
FDCE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[6]),
.Q(xaddr[6]));
FDCE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[7]),
.Q(xaddr[7]));
FDCE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(\h_count_reg[8]_i_1_n_0 ),
.Q(xaddr[8]));
FDCE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(p_0_in[9]),
.Q(xaddr[9]));
LUT6 #(
.INIT(64'hFFBFBFBFBFBFBFFF))
hsync_i_1
(.I0(xaddr[8]),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(hsync_i_2_n_0),
.I4(xaddr[5]),
.I5(xaddr[6]),
.O(hsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
hsync_i_2
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[3]),
.I3(xaddr[1]),
.I4(xaddr[0]),
.O(hsync_i_2_n_0));
FDCE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(hsync_i_1_n_0),
.Q(hsync));
LUT6 #(
.INIT(64'h5555555555555554))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[7]),
.I3(yaddr[4]),
.I4(yaddr[8]),
.I5(yaddr[6]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h78007878))
\v_count_reg[2]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.I2(yaddr[2]),
.I3(\v_count_reg[9]_i_4_n_0 ),
.I4(\v_count_reg[9]_i_3_n_0 ),
.O(p_0_in__0[2]));
LUT6 #(
.INIT(64'h7F8000007F807F80))
\v_count_reg[3]_i_1
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[2]),
.I3(yaddr[3]),
.I4(\v_count_reg[9]_i_4_n_0 ),
.I5(\v_count_reg[9]_i_3_n_0 ),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[4]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\v_count_reg[5]_i_1
(.I0(yaddr[5]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[3]),
.I4(yaddr[2]),
.I5(yaddr[4]),
.O(p_0_in__0[5]));
LUT3 #(
.INIT(8'h6A))
\v_count_reg[6]_i_1
(.I0(yaddr[6]),
.I1(\v_count_reg[9]_i_6_n_0 ),
.I2(yaddr[5]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6AAA))
\v_count_reg[7]_i_1
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(\v_count_reg[9]_i_6_n_0 ),
.I3(yaddr[6]),
.O(p_0_in__0[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[8]_i_1
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(\v_count_reg[9]_i_6_n_0 ),
.O(p_0_in__0[8]));
LUT6 #(
.INIT(64'h0000000000002000))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[5]),
.I5(xaddr[6]),
.O(sel));
LUT6 #(
.INIT(64'hD00DD0D0D0D0D0D0))
\v_count_reg[9]_i_2
(.I0(\v_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(\v_count_reg[9]_i_5_n_0 ),
.I4(yaddr[8]),
.I5(\v_count_reg[9]_i_6_n_0 ),
.O(p_0_in__0[9]));
LUT4 #(
.INIT(16'h0001))
\v_count_reg[9]_i_3
(.I0(yaddr[7]),
.I1(yaddr[4]),
.I2(yaddr[8]),
.I3(yaddr[6]),
.O(\v_count_reg[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFFFFFFFFFFFF))
\v_count_reg[9]_i_4
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[5]),
.I3(yaddr[9]),
.I4(yaddr[2]),
.I5(yaddr[3]),
.O(\v_count_reg[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h7F))
\v_count_reg[9]_i_5
(.I0(yaddr[6]),
.I1(yaddr[5]),
.I2(yaddr[7]),
.O(\v_count_reg[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\v_count_reg[9]_i_6
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(\v_count_reg[9]_i_6_n_0 ));
FDCE \v_count_reg_reg[0]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[0]),
.Q(yaddr[0]));
FDCE \v_count_reg_reg[1]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[1]),
.Q(yaddr[1]));
FDCE \v_count_reg_reg[2]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[2]),
.Q(yaddr[2]));
FDCE \v_count_reg_reg[3]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[3]),
.Q(yaddr[3]));
FDCE \v_count_reg_reg[4]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[4]),
.Q(yaddr[4]));
FDCE \v_count_reg_reg[5]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[5]),
.Q(yaddr[5]));
FDCE \v_count_reg_reg[6]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[6]),
.Q(yaddr[6]));
FDCE \v_count_reg_reg[7]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[7]),
.Q(yaddr[7]));
FDCE \v_count_reg_reg[8]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[8]),
.Q(yaddr[8]));
FDCE \v_count_reg_reg[9]
(.C(clk),
.CE(sel),
.CLR(active_i_2_n_0),
.D(p_0_in__0[9]),
.Q(yaddr[9]));
LUT6 #(
.INIT(64'hFFFFFFEFFFFFFFFF))
vsync_i_1
(.I0(active_i_3_n_0),
.I1(yaddr[9]),
.I2(yaddr[3]),
.I3(yaddr[4]),
.I4(yaddr[2]),
.I5(yaddr[1]),
.O(vsync_i_1_n_0));
FDCE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.CLR(active_i_2_n_0),
.D(vsync_i_1_n_0),
.Q(vsync));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: paddles.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************
* Joystick to CoCo compatable
******************************************************************************/
assign PADDLE_MCLK = MCLOCK[10];
always @(negedge MCLOCK[10] or negedge RESET_N)
begin
if(~RESET_N)
begin
JOY_CLK <= 13'h000;
JOY_TRIGGER <= 1'b0;
end
else
case(JOY_CLK)
13'd0000:
begin
JOY_CLK <= 13'd0001;
JOY_TRIGGER <= 1'b0;
end
13'd5883:
begin
JOY_CLK <= 13'd5884;
JOY_TRIGGER <= 1'b1;
end
13'd8191:
begin
JOY_CLK <= 13'd0000;
JOY_TRIGGER <= 1'b0;
end
default:
JOY_CLK <= JOY_CLK + 1'b1;
endcase
end
always @(negedge PADDLE_CLK[0] or negedge RESET_N)
begin
if(~RESET_N)
begin
PADDLE_ZERO_0 <= 10'd0000;
PADDLE_VAL_0 <= 12'd0000;
PADDLE_STATE_0 <= 2'b00;
JOY1_COUNT <= 6'h00;
end
else
begin
case(PADDLE_STATE_0)
2'b00:
begin
PADDLE_ZERO_0 <= PADDLE_ZERO_0 + 1'b1;
PADDLE_VAL_0 <= 12'd0000;
if(PADDLE_ZERO_0 == 10'd611)
PADDLE_STATE_0 <= 2'b01;
end
2'b01:
begin
PADDLE_ZERO_0 <= 10'd000;
PADDLE_VAL_0 <= PADDLE_VAL_0 + 1'b1;
if(PADDLE_VAL_0 == 12'd4094)
PADDLE_STATE_0 <= 2'b10;
else
begin
if(JOY_TRIGGER)
PADDLE_STATE_0 <= 2'b10;
else
PADDLE_STATE_0 <= 2'b01;
end
end
2'b10:
begin
JOY1_COUNT <= PADDLE_VAL_0[11:6];
PADDLE_LATCH_0 <= PADDLE_VAL_0;
if(JOY_TRIGGER)
PADDLE_STATE_0 <= 2'b11;
end
2'b11:
begin
if(!JOY_TRIGGER)
PADDLE_STATE_0 <= 2'b00;
end
endcase
end
end
always @(negedge PADDLE_CLK[1] or negedge RESET_N)
begin
if(~RESET_N)
begin
PADDLE_ZERO_1 <= 10'd0000;
PADDLE_VAL_1 <= 12'd0000;
PADDLE_STATE_1 <= 2'b00;
JOY2_COUNT <= 6'h00;
end
else
begin
case(PADDLE_STATE_1)
2'b00:
begin
PADDLE_ZERO_1 <= PADDLE_ZERO_1 + 1'b1;
PADDLE_VAL_1 <= 12'd0000;
if(PADDLE_ZERO_1 == 10'd611)
PADDLE_STATE_1 <= 2'b01;
end
2'b01:
begin
PADDLE_ZERO_1 <= 10'd000;
PADDLE_VAL_1 <= PADDLE_VAL_1 + 1'b1;
if(PADDLE_VAL_1 == 12'd4094)
PADDLE_STATE_1 <= 2'b10;
else
begin
if(JOY_TRIGGER)
PADDLE_STATE_1 <= 2'b10;
else
PADDLE_STATE_1 <= 2'b01;
end
end
2'b10:
begin
JOY2_COUNT <= PADDLE_VAL_1[11:6];
PADDLE_LATCH_1 <= PADDLE_VAL_1;
if(JOY_TRIGGER)
PADDLE_STATE_1 <= 2'b11;
end
2'b11:
begin
if(!JOY_TRIGGER)
PADDLE_STATE_1 <= 2'b00;
end
endcase
end
end
always @(negedge PADDLE_CLK[2] or negedge RESET_N)
begin
if(~RESET_N)
begin
PADDLE_ZERO_2 <= 10'd0000;
PADDLE_VAL_2 <= 12'd0000;
PADDLE_STATE_2 <= 2'b00;
JOY3_COUNT <= 6'h00;
end
else
begin
case(PADDLE_STATE_2)
2'b00:
begin
PADDLE_ZERO_2 <= PADDLE_ZERO_2 + 1'b1;
PADDLE_VAL_2 <= 12'd0000;
if(PADDLE_ZERO_2 == 10'd611)
PADDLE_STATE_2 <= 2'b01;
end
2'b01:
begin
PADDLE_ZERO_2 <= 10'd000;
PADDLE_VAL_2 <= PADDLE_VAL_2 + 1'b1;
if(PADDLE_VAL_2 == 12'd4094)
PADDLE_STATE_2 <= 2'b10;
else
begin
if(JOY_TRIGGER)
PADDLE_STATE_2 <= 2'b10;
else
PADDLE_STATE_2 <= 2'b01;
end
end
2'b10:
begin
JOY3_COUNT <= PADDLE_VAL_2[11:6];
PADDLE_LATCH_2 <= PADDLE_VAL_2;
if(JOY_TRIGGER)
PADDLE_STATE_2 <= 2'b11;
end
2'b11:
begin
if(!JOY_TRIGGER)
PADDLE_STATE_2 <= 2'b00;
end
endcase
end
end
always @(negedge PADDLE_CLK[3] or negedge RESET_N)
begin
if(~RESET_N)
begin
PADDLE_ZERO_3 <= 10'd0000;
PADDLE_VAL_3 <= 12'd0000;
PADDLE_STATE_3 <= 2'b00;
JOY4_COUNT <= 6'h00;
end
else
begin
case(PADDLE_STATE_3)
2'b00:
begin
PADDLE_ZERO_3 <= PADDLE_ZERO_3 + 1'b1;
PADDLE_VAL_3 <= 12'd0000;
if(PADDLE_ZERO_3 == 10'd611)
PADDLE_STATE_3 <= 2'b01;
end
2'b01:
begin
PADDLE_ZERO_3 <= 10'd000;
PADDLE_VAL_3 <= PADDLE_VAL_3 + 1'b1;
if(PADDLE_VAL_3 == 12'd4094)
PADDLE_STATE_3 <= 2'b10;
else
begin
if(JOY_TRIGGER)
PADDLE_STATE_3 <= 2'b10;
else
PADDLE_STATE_3 <= 2'b01;
end
end
2'b10:
begin
JOY4_COUNT <= PADDLE_VAL_3[11:6];
PADDLE_LATCH_3 <= PADDLE_VAL_3;
if(JOY_TRIGGER)
PADDLE_STATE_3 <= 2'b11;
end
2'b11:
begin
if(!JOY_TRIGGER)
PADDLE_STATE_3 <= 2'b00;
end
endcase
end
end
assign JSTICK = (SEL == 2'b11) ? JOY3: // Left Y
(SEL == 2'b10) ? JOY4: // Left X
(SEL == 2'b01) ? JOY1: // Right Y
// (SEL == 2'b000) ? JOY2: // Right X
// (SEL == 2'b111) ? JOY1: // Right Y
// (SEL == 2'b110) ? JOY2: // Right X
// (SEL == 2'b101) ? JOY3: // Left Y
// JOY4; // Left X
JOY2; // Right X
assign JOY1 = (JOY1_COUNT >= DTOA_CODE) ? 1'b1:
1'b0;
assign JOY2 = (JOY2_COUNT >= DTOA_CODE) ? 1'b1:
1'b0;
assign JOY3 = (JOY3_COUNT >= DTOA_CODE) ? 1'b1:
1'b0;
assign JOY4 = (JOY4_COUNT >= DTOA_CODE) ? 1'b1:
1'b0;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_TB_V
`define SKY130_FD_SC_MS__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_TB_V
|
// $Id: vcr_ivc_ctrl.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// input VC controller
//==============================================================================
module vcr_ivc_ctrl
(clk, reset, router_address, flit_valid_in, flit_head_in, flit_tail_in,
flit_sel_in, header_info_in, fb_pop_tail, fb_pop_next_header_info,
almost_full_op_ovc, full_op_ovc, route_op, route_orc, vc_gnt, vc_sel_ovc,
sw_gnt, sw_sel, sw_gnt_op, flit_valid, flit_head, flit_tail, next_lar_info,
fb_almost_empty, fb_empty, allocated, free_nonspec, free_spec, errors);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs available for each class
parameter num_vcs_per_class = 1;
// number of VCs available for each message class
localparam num_vcs_per_message_class
= num_resource_classes * num_vcs_per_class;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// maximum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter max_payload_length = 4;
// minimum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter min_payload_length = 1;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// width of counter for remaining flits
localparam flit_ctr_width = clogb(max_payload_length);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// total number of bits required for routing-related information
localparam route_info_width = lar_info_width + dest_info_width;
// total number of bits of header information encoded in header flit payload
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
route_info_width :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
route_info_width :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(route_info_width + payload_length_width) :
-1;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
// VC allocation is atomic
localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
// enable speculative switch allocation
parameter sw_alloc_spec = 1;
// select flit buffer management scheme
parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
// use explicit pipeline register between flit buffer and crossbar?
parameter explicit_pipeline_register = 0;
// ID of current input VC
parameter vc_id = 0;
// message class to which this VC belongs
localparam message_class
= (vc_id / num_vcs_per_message_class) % num_message_classes;
// resource class to which this VC belongs
localparam resource_class
= (vc_id / num_vcs_per_class) % num_resource_classes;
// ID of current input port
parameter port_id = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// incoming flit valid
input flit_valid_in;
// incoming flit is head flit
input flit_head_in;
// incoming flit is tail
input flit_tail_in;
// incoming flit is for current VC
input flit_sel_in;
// header info for incoming flit
// (NOTE: only valid if flit_head_in=1)
input [0:header_info_width-1] header_info_in;
// tail indicator for frontmost flit in buffer (if any)
input fb_pop_tail;
// header info from next flit in buffer
// (NOTE: only valid if buffer contains at least two entries)
input [0:header_info_width-1] fb_pop_next_header_info;
// which output VC have only a single credit left?
input [0:num_ports*num_vcs-1] almost_full_op_ovc;
// which output VC have no credit left?
input [0:num_ports*num_vcs-1] full_op_ovc;
// destination port (1-hot)
output [0:num_ports-1] route_op;
wire [0:num_ports-1] route_op;
// select next resource class
output [0:num_resource_classes-1] route_orc;
wire [0:num_resource_classes-1] route_orc;
// VC allocation successful
input vc_gnt;
// granted output VC
input [0:num_vcs-1] vc_sel_ovc;
// switch allocator grants
input sw_gnt;
// switch allocator grant is for this VC
input sw_sel;
// switch grant for output ports
input [0:num_ports-1] sw_gnt_op;
// outgoing flit is available
output flit_valid;
wire flit_valid;
// outgoing flit is head flit
output flit_head;
wire flit_head;
// outgoing flit is tail flit
output flit_tail;
wire flit_tail;
// updated lookahead routing info
// (NOTE: only valid if the current flit is a head flit)
output [0:lar_info_width-1] next_lar_info;
wire [0:lar_info_width-1] next_lar_info;
// flit buffer has a single valid entry left
input fb_almost_empty;
// flit buffer does not have any valid entries
input fb_empty;
// has an output VC been assigned to this input VC?
output allocated;
wire allocated;
// credit availability if VC has been assigned
output free_nonspec;
wire free_nonspec;
// credit availability if no VC has been assigned yet
output free_spec;
wire free_spec;
// internal error condition detected
output [0:2] errors;
wire [0:2] errors;
//---------------------------------------------------------------------------
// keep track of VC allocation status
//---------------------------------------------------------------------------
wire flit_valid_sel_in;
assign flit_valid_sel_in = flit_valid_in & flit_sel_in;
assign flit_valid = flit_valid_sel_in | ~fb_empty;
wire pop_active;
assign pop_active = flit_valid_in | ~fb_empty;
wire flit_sent;
wire flit_sent_tail;
assign flit_sent_tail = flit_sent & flit_tail;
wire flit_valid_sel_head_in;
assign flit_valid_sel_head_in = flit_valid_sel_in & flit_head_in;
wire vc_allocated_s, vc_allocated_q;
generate
if(atomic_vc_allocation)
begin
assign vc_allocated_s
= (vc_allocated_q & ~flit_valid_sel_head_in) | vc_gnt;
assign allocated = vc_allocated_q & ~flit_valid_sel_head_in;
end
else
begin
assign vc_allocated_s = (vc_allocated_q | vc_gnt) & ~flit_sent_tail;
assign allocated = vc_allocated_q;
end
endgenerate
c_dff
#(.width(1),
.reset_type(reset_type))
vc_allocatedq
(.clk(clk),
.reset(reset),
.active(pop_active),
.d(vc_allocated_s),
.q(vc_allocated_q));
wire [0:num_vcs_per_message_class-1] vc_allocated_next_orc_ocvc;
generate
if(num_vcs_per_message_class == 1)
assign vc_allocated_next_orc_ocvc = 1'b1;
else if(num_vcs_per_message_class > 1)
begin
wire [0:num_vcs_per_message_class-1] vc_sel_orc_ocvc;
assign vc_sel_orc_ocvc
= vc_sel_ovc[message_class*num_vcs_per_message_class:
(message_class+1)*num_vcs_per_message_class-1];
wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_q;
assign vc_allocated_next_orc_ocvc
= allocated ? vc_allocated_orc_ocvc_q : vc_sel_orc_ocvc;
wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_s;
assign vc_allocated_orc_ocvc_s = vc_allocated_next_orc_ocvc;
c_dff
#(.width(num_vcs_per_message_class),
.reset_type(reset_type))
vc_allocated_orc_ocvcq
(.clk(clk),
.reset(1'b0),
.active(pop_active),
.d(vc_allocated_orc_ocvc_s),
.q(vc_allocated_orc_ocvc_q));
end
endgenerate
wire [0:num_vcs-1] vc_allocated_next_ovc;
c_align
#(.in_width(num_vcs_per_message_class),
.out_width(num_vcs),
.offset(message_class*num_vcs_per_message_class))
vc_allocated_next_ovc_agn
(.data_in(vc_allocated_next_orc_ocvc),
.dest_in({num_vcs{1'b0}}),
.data_out(vc_allocated_next_ovc));
//---------------------------------------------------------------------------
// generate head and tail indicators
//---------------------------------------------------------------------------
assign flit_tail = fb_empty ? flit_tail_in : fb_pop_tail;
wire htr_flit_head_s, htr_flit_head_q;
assign htr_flit_head_s = flit_sent ? flit_tail : htr_flit_head_q;
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
htr_flit_headq
(.clk(clk),
.reset(reset),
.active(pop_active),
.d(htr_flit_head_s),
.q(htr_flit_head_q));
assign flit_head = fb_empty ? flit_head_in : htr_flit_head_q;
//---------------------------------------------------------------------------
// header info register
//---------------------------------------------------------------------------
wire [0:route_info_width-1] route_info_in;
assign route_info_in = header_info_in[0:route_info_width-1];
wire hdr_active;
wire hdr_capture;
generate
if(atomic_vc_allocation)
begin
assign hdr_active = flit_valid_in & flit_head_in;
assign hdr_capture = flit_valid_sel_head_in;
end
else
begin
assign hdr_active = ~fb_empty | (flit_valid_in & flit_head_in);
assign hdr_capture = (fb_empty & flit_valid_sel_head_in) |
flit_sent_tail;
end
endgenerate
wire two_plus_flits;
assign two_plus_flits = ~fb_empty & ~fb_almost_empty;
wire [0:route_info_width-1] fb_pop_next_route_info;
assign fb_pop_next_route_info
= fb_pop_next_header_info[0:route_info_width-1];
wire [0:lar_info_width-1] lar_info_in;
assign lar_info_in = route_info_in[0:lar_info_width-1];
wire [0:lar_info_width-1] hdr_lar_info_s, hdr_lar_info_q;
generate
if(atomic_vc_allocation)
assign hdr_lar_info_s = hdr_capture ? lar_info_in : hdr_lar_info_q;
else
begin
wire [0:lar_info_width-1] fb_pop_next_lar_info;
assign fb_pop_next_lar_info
= fb_pop_next_route_info[0:lar_info_width-1];
assign hdr_lar_info_s
= hdr_capture ?
(two_plus_flits ? fb_pop_next_lar_info : lar_info_in) :
hdr_lar_info_q;
end
endgenerate
c_dff
#(.width(lar_info_width),
.reset_type(reset_type))
hdr_lar_infoq
(.clk(clk),
.reset(1'b0),
.active(hdr_active),
.d(hdr_lar_info_s),
.q(hdr_lar_info_q));
wire [0:dest_info_width-1] dest_info_in;
assign dest_info_in = route_info_in[lar_info_width:
lar_info_width+dest_info_width-1];
wire [0:dest_info_width-1] hdr_dest_info_s, hdr_dest_info_q;
generate
if(atomic_vc_allocation)
assign hdr_dest_info_s = hdr_capture ? dest_info_in : hdr_dest_info_q;
else
begin
wire [0:dest_info_width-1] fb_pop_next_dest_info;
assign fb_pop_next_dest_info
= fb_pop_next_route_info[lar_info_width:
lar_info_width+dest_info_width-1];
assign hdr_dest_info_s
= hdr_capture ?
(two_plus_flits ? fb_pop_next_dest_info : dest_info_in) :
hdr_dest_info_q;
end
endgenerate
c_dff
#(.width(dest_info_width),
.reset_type(reset_type))
hdr_dest_infoq
(.clk(clk),
.reset(1'b0),
.active(hdr_active),
.d(hdr_dest_info_s),
.q(hdr_dest_info_q));
//---------------------------------------------------------------------------
// decode lookahead routing information
//---------------------------------------------------------------------------
wire [0:port_idx_width-1] route_port_in;
assign route_port_in = lar_info_in[0:port_idx_width-1];
wire [0:num_ports-1] route_in_op;
c_decode
#(.num_ports(num_ports))
route_in_op_dec
(.data_in(route_port_in),
.data_out(route_in_op));
wire [0:port_idx_width-1] hdr_route_port;
assign hdr_route_port = hdr_lar_info_q[0:port_idx_width-1];
wire [0:num_ports-1] hdr_route_op;
c_decode
#(.num_ports(num_ports))
hdr_route_op_dec
(.data_in(hdr_route_port),
.data_out(hdr_route_op));
wire bypass_route_info;
generate
if(atomic_vc_allocation)
assign bypass_route_info = flit_valid_sel_head_in;
else
assign bypass_route_info = fb_empty & flit_valid_sel_head_in;
endgenerate
wire [0:num_ports-1] route_unmasked_op;
assign route_unmasked_op = bypass_route_info ? route_in_op : hdr_route_op;
wire [0:num_resource_classes-1] route_unmasked_orc;
generate
if(num_resource_classes == 1)
assign route_unmasked_orc = 1'b1;
else if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel_in;
assign route_rcsel_in
= lar_info_in[port_idx_width:
port_idx_width+resource_class_idx_width-1];
wire [0:num_resource_classes-1] route_in_orc;
c_decode
#(.num_ports(num_resource_classes))
route_in_orc_dec
(.data_in(route_rcsel_in),
.data_out(route_in_orc));
wire [0:resource_class_idx_width-1] hdr_route_rcsel;
assign hdr_route_rcsel
= hdr_lar_info_q[port_idx_width:
port_idx_width+resource_class_idx_width-1];
wire [0:num_resource_classes-1] hdr_route_orc;
c_decode
#(.num_ports(num_resource_classes))
hdr_route_orc_dec
(.data_in(hdr_route_rcsel),
.data_out(hdr_route_orc));
assign route_unmasked_orc
= bypass_route_info ? route_in_orc : hdr_route_orc;
end
endgenerate
wire [0:1] rf_errors;
rtr_route_filter
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.num_neighbors_per_dim(num_neighbors_per_dim),
.num_nodes_per_router(num_nodes_per_router),
.restrict_turns(restrict_turns),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order),
.port_id(port_id),
.vc_id(vc_id))
rf
(.clk(clk),
.route_valid(flit_valid),
.route_in_op(route_unmasked_op),
.route_in_orc(route_unmasked_orc),
.route_out_op(route_op),
.route_out_orc(route_orc),
.errors(rf_errors));
wire error_invalid_port;
assign error_invalid_port = rf_errors[0];
wire error_invalid_class;
assign error_invalid_class = rf_errors[1];
//---------------------------------------------------------------------------
// update lookahead routing information for next hop
//---------------------------------------------------------------------------
wire [0:dest_info_width-1] dest_info;
assign dest_info = bypass_route_info ? dest_info_in : hdr_dest_info_q;
wire [0:lar_info_width-1] lar_info;
assign lar_info = bypass_route_info ? lar_info_in : hdr_lar_info_q;
wire [0:router_addr_width-1] next_router_address;
rtr_next_hop_addr
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type))
nha
(.router_address(router_address),
.dest_info(dest_info),
.lar_info(lar_info),
.next_router_address(next_router_address));
wire [0:num_message_classes-1] sel_mc;
c_align
#(.in_width(1),
.out_width(num_message_classes),
.offset(message_class))
sel_mc_agn
(.data_in(1'b1),
.dest_in({num_message_classes{1'b0}}),
.data_out(sel_mc));
wire [0:num_ports-1] next_route_op;
wire [0:num_resource_classes-1] next_route_orc;
rtr_routing_logic
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
rtl
(.router_address(next_router_address),
.sel_mc(sel_mc),
.sel_irc(route_orc),
.dest_info(dest_info),
.route_op(next_route_op),
.route_orc(next_route_orc));
wire [0:port_idx_width-1] next_route_port;
c_encode
#(.num_ports(num_ports))
next_route_port_enc
(.data_in(next_route_op),
.data_out(next_route_port));
assign next_lar_info[0:port_idx_width-1] = next_route_port;
generate
if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] next_route_rcsel;
c_encode
#(.num_ports(num_resource_classes))
next_route_rcsel_enc
(.data_in(next_route_orc),
.data_out(next_route_rcsel));
assign next_lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1]
= next_route_rcsel;
end
endgenerate
//---------------------------------------------------------------------------
// credit tracking
//---------------------------------------------------------------------------
wire cred_track_active;
assign cred_track_active = pop_active | allocated;
wire [0:num_vcs-1] almost_full_ovc;
c_select_1ofn
#(.num_ports(num_ports),
.width(num_vcs))
almost_full_ovc_sel
(.select(route_op),
.data_in(almost_full_op_ovc),
.data_out(almost_full_ovc));
wire [0:num_vcs-1] full_ovc;
c_select_1ofn
#(.num_ports(num_ports),
.width(num_vcs))
full_ovc_sel
(.select(route_op),
.data_in(full_op_ovc),
.data_out(full_ovc));
wire reduce;
generate
if(fb_mgmt_type == `FB_MGMT_TYPE_STATIC)
assign reduce = flit_sent;
else
begin
c_select_1ofn
#(.num_ports(num_ports),
.width(1))
reduce_sel
(.select(route_op),
.data_in(sw_gnt_op),
.data_out(reduce));
end
endgenerate
wire [0:num_vcs-1] next_free_ovc;
assign next_free_ovc = ~full_ovc & ~(almost_full_ovc & {num_vcs{reduce}});
wire [0:num_vcs_per_message_class-1] next_free_orc_ocvc;
assign next_free_orc_ocvc
= next_free_ovc[message_class*num_vcs_per_message_class:
(message_class+1)*num_vcs_per_message_class-1];
wire free_nonspec_muxed;
c_select_1ofn
#(.num_ports(num_vcs_per_message_class),
.width(1))
free_nonspec_muxed_sel
(.select(vc_allocated_next_orc_ocvc),
.data_in(next_free_orc_ocvc),
.data_out(free_nonspec_muxed));
wire free_nonspec_s, free_nonspec_q;
assign free_nonspec_s = free_nonspec_muxed;
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
free_nonspecq
(.clk(clk),
.reset(1'b0),
.active(cred_track_active),
.d(free_nonspec_s),
.q(free_nonspec_q));
assign free_nonspec = free_nonspec_q;
wire [0:num_vcs-1] free_spec_ovc;
assign free_spec_ovc = ~full_ovc;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
free_spec_sel
(.select(vc_sel_ovc),
.data_in(free_spec_ovc),
.data_out(free_spec));
wire sw_gnt_sel;
assign sw_gnt_sel = sw_gnt & sw_sel;
generate
if(sw_alloc_spec)
begin
if(elig_mask == `ELIG_MASK_NONE)
assign flit_sent = sw_gnt_sel & ((vc_gnt & free_spec) | allocated);
else
assign flit_sent = sw_gnt_sel & (vc_gnt | allocated);
end
else
assign flit_sent = sw_gnt_sel;
endgenerate
//---------------------------------------------------------------------------
// error checking
//---------------------------------------------------------------------------
wire ftc_active;
assign ftc_active = flit_valid_in;
wire error_invalid_flit_type;
rtr_flit_type_check
#(.reset_type(reset_type))
ftc
(.clk(clk),
.reset(reset),
.active(ftc_active),
.flit_valid(flit_valid_sel_in),
.flit_head(flit_head_in),
.flit_tail(flit_tail_in),
.error(error_invalid_flit_type));
assign errors[0] = error_invalid_port;
assign errors[1] = error_invalid_class;
assign errors[2] = error_invalid_flit_type;
endmodule
|
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module simple_biclk_bidir_ram
#(parameter width = 1,
parameter widthad = 1)
(
input clk,
input [widthad-1:0] address_a,
input wren_a,
input [width-1:0] data_a,
output reg [width-1:0] q_a,
input clk2,
input [widthad-1:0] address_b,
output reg [width-1:0] q_b
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren_a) mem[address_a] <= data_a;
q_a <= mem[address_a];
end
always @(posedge clk2) begin
q_b <= mem[address_b];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:25:19 11/02/2015
// Design Name:
// Module Name: MainBoard
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MainBoard(
`ifndef SIMULATION
//clk
input clk,
input clk_50M,
//for debug
input[4:0] RegNum,
`endif
output[31:0] RegData,
output[31:0] ProgramCounter,
output[31:0] ExtraOut,
output[31:0] IR,
//vga
output hsync, //ÐÐͬ²½ÐźÅ
output vsync, //³¡Í¬²½ÐźÅ
output vga_r,
output vga_g,
output vga_b,
`ifndef SIMULATION
//KeyBoard
input PS2C,
input PS2D,
`endif
//Serial Port
input RxD,
output TxD
);
`ifdef SIMULATION
reg clk;
reg clk_50M;
reg[4:0] RegNum;
reg PS2C;
reg PS2D;
initial begin
// Initialize Inputs
RegNum = 8;
clk = 0;
clk_50M = 0;
clk = 0;
PS2C = 0;
PS2D = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always#10 begin
clk_50M = ~clk_50M;
end
always#10 begin
clk = ~clk;
end
always #200 begin
PS2C = ~PS2C;
end
always #330 begin
PS2D = ~PS2D;
end
`endif
//Multicycle CPU
reg[31:0] MemReadData;
reg MemOK;
initial begin
MemReadData <= 0;
MemOK <= 0;
end
wire OutINTE;
wire[31:0] OutCause;
wire[31:0] RequestedMemAddr;
wire RequestedMemWrite;
wire RequestedMemRead;
wire RequestedSaveHalf;
wire RequestedLoadHalf;
wire[31:0] RequestedMemWriteData;
wire InteAccept;
wire[31:0] MMCExtraOut;
MultiCycleCpu MCC (
//input
.clk(clk),
// .clk_50M(clk_50M),
.MemOK(MemOK),
.MemReadData(MemReadData),
.OutINTE(OutINTE),
.OutCause(OutCause),
//output
.MemAddr(RequestedMemAddr),
.MemWrite(RequestedMemWrite),
.MemRead(RequestedMemRead),
.SaveHalf(RequestedSaveHalf),
.LoadHalf(RequestedLoadHalf),
.MemWriteData(RequestedMemWriteData),
.InteAccept(InteAccept),
//for debug
.RegNum(RegNum),
.ProgramCounter(ProgramCounter),
.IR(IR),
.ExtraOut(MMCExtraOut),
.RegData(RegData)
);
reg[31:0] MemAddr;
reg MemWrite;
reg MemRead;
reg SaveHalf;
reg LoadHalf;
reg[31:0] MemWriteData;
reg[1:0] state;
initial begin
MemAddr <= 0;
MemWrite <= 0;
MemRead <= 0;
SaveHalf <= 0;
LoadHalf <= 0;
MemWriteData <= 0;
state <= 0;
end
assign ExtraOut = MemAddr;
//Block Memory
wire BlockMemChipSelect;
wire BlockMemOK;
wire[31:0] BlockMemReadData;
assign BlockMemChipSelect = (0 <= MemAddr) && (MemAddr < 16'h5000);
MemoryManagerUnit MMU (
.clk(clk),
.clk_50M(clk_50M),
.MemAddr(MemAddr[14:0]),
.MemWrite(MemWrite),
.MemRead(MemRead),
.SaveHalf(SaveHalf),
.LoadHalf(LoadHalf),
.MemWriteData(MemWriteData),
.ChipSelect(BlockMemChipSelect),
.MemReadData(BlockMemReadData),
.MemOK(BlockMemOK),
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
//VHDControler
wire VHDChipSelect;
wire VHDMemOK;
wire[31:0] VHDMemReadData;
assign VHDChipSelect = (MemAddr >= 32'h50FC) && (MemAddr < 32'h5200);
VHDControler vhd (
.clk(clk),
.RxD(RxD),
.TxD(TxD),
.VHDControlerAddr(MemAddr[8:0]), //[8:0]
.ChipSelect(VHDChipSelect),
.WriteData(MemWriteData), //[31:0]
.SaveHalf(SaveHalf),
.LoadHalf(LoadHalf),
.MemWrite(MemWrite),
.MemRead(MemRead),
.MemReadData(VHDMemReadData), //[31:0]
.MemOK(VHDMemOK)
);
wire TimerInte;
Timer t(
.clk(clk_50M),
.TimerInte(TimerInte)
);
//KeyBoard
wire[15:0] KeyBoardReadData;
wire KeyBoardChipSelect;
wire KeyBoardOK;
wire KeyBoardInte;
wire KeyBoardInteAccept;
assign KeyBoardChipSelect = (MemAddr==32'h5000);
assign KeyBoardOK = 1;
KeyBoardControler kbc (
.clk(clk_50M),
.PS2C(PS2C),
.PS2D(PS2D),
.InteAccept(KeyBoardInteAccept),
.scanCode(KeyBoardReadData),
.KeyBoardInte(KeyBoardInte)
);
assign OutINTE = KeyBoardInte | TimerInte;
assign OutCause= {32{KeyBoardInte}} & 32'h1 | {32{(~KeyBoardInte) & TimerInte}} & 32'h2;
assign KeyBoardInteAccept = InteAccept & KeyBoardInte;
always@(posedge clk) begin
case(state)
0: begin
if(RequestedMemRead | RequestedMemWrite) begin
state <= 1;
MemAddr <= RequestedMemAddr;
MemWrite <= RequestedMemWrite;
MemRead <= RequestedMemRead;
SaveHalf <= RequestedSaveHalf;
LoadHalf <= RequestedLoadHalf;
MemWriteData <= RequestedMemWriteData;
end
else begin
state <= 0;
end
end
1: begin
if( BlockMemOK & BlockMemChipSelect |
KeyBoardChipSelect & KeyBoardOK |
VHDChipSelect & VHDMemOK
) begin
state <= 2;
MemOK <= 1;
MemReadData <=
{32{BlockMemChipSelect}} & BlockMemReadData |
{32{KeyBoardChipSelect}} & {16'h0,KeyBoardReadData} |
{32{VHDChipSelect}} & VHDMemReadData ;
MemWrite <= 0;
MemRead <= 0;
end
end
2: begin
state <= 0;
MemOK <= 0;
end
default: begin
MemAddr <= 0;
MemWrite <= 0;
MemRead <= 0;
SaveHalf <= 0;
LoadHalf <= 0;
MemWriteData <= 0;
state <= 0;
end
endcase
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_96x512.v
// /___/ /\ Timestamp: Thu Nov 8 18:57:43 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_96x512.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_96x512.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_96x512.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_96x512.v
// # of Modules : 1
// Design Name : fifo_96x512
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_96x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [95 : 0] dout;
input [95 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB18SDP #(
.DO_REG ( 0 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.SRVAL ( 36'h000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (
.RDCLK(clk),
.WRCLK(clk),
.RDEN(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WREN(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.REGCE(N0),
.SSR(srst),
.RDADDR({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]}),
.WRADDR({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]}),
.DI({din[34], din[33], din[32], din[31], din[30], din[29], din[28], din[27], din[25], din[24], din[23], din[22], din[21], din[20], din[19],
din[18], din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({din[35], din[26], din[17], din[8]}),
.DO({dout[34], dout[33], dout[32], dout[31], dout[30], dout[29], dout[28], dout[27], dout[25], dout[24], dout[23], dout[22], dout[21], dout[20],
dout[19], dout[18], dout[16], dout[15], dout[14], dout[13], dout[12], dout[11], dout[10], dout[9], dout[7], dout[6], dout[5], dout[4], dout[3],
dout[2], dout[1], dout[0]}),
.DOP({dout[35], dout[26], dout[17], dout[8]}),
.WE({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en })
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({N0, din[95], din[94], din[93], din[92], din[91], din[90], din[89], din[88], din[87], din[86], din[85], din[84], din[83], din[82], din[81], N0
, din[80], din[79], din[78], din[77], din[76], din[75], din[74], din[73], din[72], din[71], din[70], din[69], din[68], din[67], din[66], N0, din[65],
din[64], din[63], din[62], din[61], din[60], din[59], din[58], din[57], din[56], din[55], din[54], din[53], din[52], din[51], N0, din[50], din[49],
din[48], din[47], din[46], din[45], din[44], din[43], din[42], din[41], din[40], din[39], din[38], din[37], din[36]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED
, dout[95], dout[94], dout[93], dout[92], dout[91], dout[90], dout[89], dout[88], dout[87], dout[86], dout[85], dout[84], dout[83], dout[82], dout[81]
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED
, dout[80], dout[79], dout[78], dout[77], dout[76], dout[75], dout[74], dout[73], dout[72], dout[71], dout[70], dout[69], dout[68], dout[67], dout[66]
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED
, dout[65], dout[64], dout[63], dout[62], dout[61], dout[60], dout[59], dout[58], dout[57], dout[56], dout[55], dout[54], dout[53], dout[52], dout[51]
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED
, dout[50], dout[49], dout[48], dout[47], dout[46], dout[45], dout[44], dout[43], dout[42], dout[41], dout[40], dout[39], dout[38], dout[37], dout[36]
}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics Register Decoder
// File : grap_reg_dec.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module consists of the io registers and its decodes.
// The graphic registers gr00 to gr08, are assigned in this module.
// The graphic ready signal is also generated in this module.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module grap_reg_dec
(
input h_reset_n,
input h_iord,
input h_iowr,
input h_io_16,
input h_dec_3cx,
input [15:0] h_io_addr,
input [15:8] h_io_dbus,
input h_hclk,
input c_gr_ext_en,
input [7:0] c_ext_index,
input c_misc_b0,
output [7:0] g_reg_gr0,
output [7:0] g_reg_gr1,
output [7:0] g_reg_gr2,
output [7:0] g_reg_gr3,
output [7:0] g_reg_gr4,
output [7:0] g_reg_gr5,
output [7:0] g_reg_gr6,
output [7:0] g_reg_gr7,
output [7:0] g_reg_gr8,
output [5:0] g_t_ctl_bit,
output gr5_b0,
output gr5_b1,
output read_mode_0,
output read_mode_1,
output gr4_b0,
output gr4_b1,
output g_gr05_b4,
output g_gr05_b5,
output g_gr05_b6,
output g_gr06_b0,
output g_gr06_b1,
output gr6_b2,
output gr6_b3,
output [3:0] reg_gr0_qout,
output [3:0] reg_gr1_qout,
output [3:0] reg_gr2_qout,
output [4:0] reg_gr3_qout, // only two bits are used, the rest are RESERVED
output [3:0] reg_gr7_qout,
output [7:0] reg_gr8_qout,
output g_ready_n,
output gra_mod_rd_en
);
reg [3:0] store0_reg;
reg [3:0] store1_reg;
reg [3:0] store2_reg;
reg [4:0] store3_reg;
reg [1:0] store4_reg;
reg [5:0] store5_reg;
reg [3:0] store6_reg;
reg [3:0] store7_reg;
reg [7:0] store8_reg;
reg h_iowr_d;
reg delay_rdorwr;
wire [7:0] int_reg_gr0_qout;
wire [7:0] int_reg_gr1_qout;
wire [7:0] int_reg_gr2_qout;
wire [7:0] int_reg_gr3_qout;
wire [7:0] int_reg_gr7_qout;
wire [7:0] reg_gr5_qout;
wire [7:0] reg_gr4_qout;
wire [7:0] reg_gr6_qout;
wire [7:0] reg_grx_qout;
wire graph_range;
wire graph_data_dec;
wire h_io_rdwr;
wire graphic_io_hit;
wire grap_mod_addr_hit;
// ASsigns for h_io_dbus readback path
assign g_reg_gr0 = int_reg_gr0_qout;
assign g_reg_gr1 = int_reg_gr1_qout;
assign g_reg_gr2 = int_reg_gr2_qout;
assign g_reg_gr3 = int_reg_gr3_qout;
assign g_reg_gr4 = reg_gr4_qout;
assign g_reg_gr5 = reg_gr5_qout;
assign g_reg_gr6 = reg_gr6_qout;
assign g_reg_gr7 = int_reg_gr7_qout;
assign g_reg_gr8 = reg_gr8_qout;
assign reg_gr0_qout = int_reg_gr0_qout[3:0];
assign reg_gr1_qout = int_reg_gr1_qout[3:0];
assign reg_gr2_qout = int_reg_gr2_qout[3:0];
assign reg_gr3_qout = int_reg_gr3_qout[4:0];
assign reg_gr7_qout = int_reg_gr7_qout[3:0];
assign gr5_b0 = reg_gr5_qout[0];
assign gr5_b1 = reg_gr5_qout[1];
assign gr6_b2 = reg_gr6_qout[2];
assign gr6_b3 = reg_gr6_qout[3];
assign read_mode_1 = reg_gr5_qout[3];
assign read_mode_0 = ~reg_gr5_qout[3];
assign g_gr05_b4 = reg_gr5_qout[4];
assign g_gr05_b5 = reg_gr5_qout[5];
assign g_gr05_b6 = reg_gr5_qout[6];
assign g_gr06_b0 = reg_gr6_qout[0];
assign g_gr06_b1 = reg_gr6_qout[1];
assign gr4_b0 = reg_gr4_qout[0];
assign gr4_b1 = reg_gr4_qout[1];
assign g_t_ctl_bit[3] = 1'b0;
assign g_t_ctl_bit[2] = 1'b0;
assign g_t_ctl_bit[5] = c_misc_b0;
assign g_t_ctl_bit[4] = 1'b0;
assign g_t_ctl_bit[1] = gr6_b3;
assign g_t_ctl_bit[0] = gr6_b2;
//
// Instantiating grap index and extension index registers
//
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
h_iowr_d <= 1'b0;
delay_rdorwr <= 1'b0;
end else begin
h_iowr_d <= h_iowr;
delay_rdorwr <= h_io_rdwr;
end
//
// Infering Graphic Register (GR0 - GR8).
//
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
store0_reg <= 4'b0;
store1_reg <= 4'b0;
store2_reg <= 4'b0;
store3_reg <= 5'b0;
store4_reg <= 2'b0;
store5_reg <= 6'b0;
store6_reg <= 4'b0;
store7_reg <= 4'b0;
store8_reg <= 8'b0;
end else if (h_iowr & h_iowr_d) begin
case (h_io_addr)
// Extension Index
16'h03ce: begin
if (h_io_16) begin
case (c_ext_index)
8'h0: store0_reg <= h_io_dbus[11:8];
8'h1: store1_reg <= h_io_dbus[11:8];
8'h2: store2_reg <= h_io_dbus[11:8];
8'h3: store3_reg <= h_io_dbus[12:8];
8'h4: store4_reg <= h_io_dbus[9:8];
8'h5: store5_reg <= {h_io_dbus[14:11], h_io_dbus[9:8]};
8'h6: store6_reg <= h_io_dbus[11:8];
8'h7: store7_reg <= h_io_dbus[11:8];
8'h8: store8_reg <= h_io_dbus[15:8];
endcase // case(c_ext_index)
end
end
// Extension Data
16'h03cf: begin
case (c_ext_index)
8'h0: store0_reg <= h_io_dbus[11:8];
8'h1: store1_reg <= h_io_dbus[11:8];
8'h2: store2_reg <= h_io_dbus[11:8];
8'h3: store3_reg <= h_io_dbus[12:8];
8'h4: store4_reg <= h_io_dbus[9:8];
8'h5: store5_reg <= {h_io_dbus[14:11], h_io_dbus[9:8]};
8'h6: store6_reg <= h_io_dbus[11:8];
8'h7: store7_reg <= h_io_dbus[11:8];
8'h8: store8_reg <= h_io_dbus[15:8];
endcase // case(c_ext_index)
end
endcase // case(h_addr)
end
assign int_reg_gr0_qout = {4'b0, store0_reg};
assign int_reg_gr1_qout = {4'b0, store1_reg};
assign int_reg_gr2_qout = {4'b0, store2_reg};
assign int_reg_gr3_qout = {3'b0, store3_reg};
assign reg_gr4_qout = {6'b0, store4_reg};
assign reg_gr5_qout = {1'b0, store5_reg[5:2], 1'b0, store5_reg[1:0]};
assign reg_gr6_qout = {4'b0, store6_reg};
assign int_reg_gr7_qout = {4'b0, store7_reg};
assign reg_gr8_qout = store8_reg;
//
// Evaluating the graphic address range and generating g_ready_n.
//
assign graph_range = ((c_ext_index >= 8'h00) & (c_ext_index <= 8'h08));
assign graph_data_dec = (h_dec_3cx & (h_io_addr[3:0] == 4'hf)) |
(h_dec_3cx & (h_io_addr[3:0] == 4'he)) ;
assign h_io_rdwr = h_iord | h_iowr;
assign graphic_io_hit = (graph_range & graph_data_dec &
h_io_rdwr & c_gr_ext_en);
assign grap_mod_addr_hit = graphic_io_hit;
assign g_ready_n = ~(grap_mod_addr_hit & delay_rdorwr);
assign gra_mod_rd_en = grap_mod_addr_hit & h_iord;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvpwrvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_HS__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_adder_subtractor_0_0 -prefix
// affine_block_ieee754_fp_adder_subtractor_0_0_ affine_block_ieee754_fp_adder_subtractor_0_1_stub.v
// Design : affine_block_ieee754_fp_adder_subtractor_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_adder_subtractor,Vivado 2016.4" *)
module affine_block_ieee754_fp_adder_subtractor_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2016 Dmitry Murzinov ([email protected]) //
/////////////////////////////////////////////////////////////////////
module sbox_ram (
input wire CLK, // Clock
input wire CEN, // ChipEnable
input wire WEN, // Write (otherwise read)
input wire INIT, // 0 - normal mode, 1 - loading S-box
input wire [31:0] SA, // SBox Individual Addresses
input wire [3:0] CA, // Common Address for All rams
input wire [31:0] SI, // Data Input
output reg [31:0] SO // Data output
);
///////////////////////////////////////////////////
wire [3:0] AMUX [7:0]; // for address multiplexer
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: sbox_ram
ram16x4bit
sbox_ram_u0
(.CLK(CLK ),
.CEN(CEN ),
.WEN(WEN ),
.A( AMUX[i] ),
.D( SI[i*4+3:i*4]),
.Q( SO[i*4+3:i*4])
);
assign AMUX[i] = INIT ? CA : SA[i*4+3:i*4];
end
endgenerate
endmodule
//EOF
|
/***************************************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* Retrived from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html *
***************************************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block
// File : dex_reg.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_reg
(
input de_clk, /* drawing engine clock input */
input de_rstn, /* reset input */
input [159:0] xydat_1, /* parameter registers */
input load_actvn_in, /* load active command parameters */
input load_actv_3d, /* load active 3D parameters */
input line_actv_1, /* Line command is active */
input line_actv_3d_1, /* Line command is active */
input line_actv_2, /* Line command is active */
input blt_actv_1, /* blt command is active */
input blt_actv_2, /* blt command is active */
input [4:0] aad, /* A port register address */
input [4:0] bad, /* B port register address */
input [3:0] wad, /* write port register address */
input [1:0] wen, /* register write enables */
input ldmajor, /* load major direction bit */
input ldminor, /* load minor direction bit */
input incpat, /* increment line pattern pointer */
input l3_incpat, /* increment 3D line pattern pointer */
input prst, /* pattern reset bit */
input [3:0] src_cntrl, /* source counter control bits. */
input [1:0] dst_cntrl, /* destination counter control bits. */
input w_chgx, /* working counter control bits. */
input [15:0] fx, /* input from the ALU X output */
input [15:0] fy, /* input from the ALU Y output */
input [31:0] lpat_1, /* line pattern register output */
input [15:0] pctrl_1, /* line pattern control register output */
input [1:0] clp_2, /* clipping control */
input [31:0] clptl_1, /* clipping top left corner register input */
input [31:0] clpbr_1, /* clipping bottom right corner register input */
input [31:0] de_sorg_2, /* source origin register output */
input [31:0] de_dorg_2, /* destination origin register output */
input set_sol, /* set the start of line flag. */
input set_eol, /* set the end of line flag. */
input mem_req, /* memory request signal. */
input mem_read, /* memory read signal. */
input [1:0] ps_1, /* pixel size level one signal. */
input ps16_2, /* pixel size is 16. */
input ps32_2, /* pixel size is 32. */
input eline_actv_1, /* eline active level one signal. */
input pline_actv_1, /* poly line active level one signal. */
input pline_actv_2, /* poly line active level one signal. */
input mul, /* mul the srx, dstx, and sizex by 1,2, or 4. */
input stpl_2, /* packed stipple bit level two. */
input tx_clr_seol, /* text mode clear sol and eol. */
input edi_2, /* triangle edge include bit. */
input inc_err, /* line increment error reg. */
input rst_err, /* line decrement error reg. */
input stpl_1, /* packed stipple level one signal. */
input src_upd, /* Update source at end of line. */
input b_clr_ld_disab, /* Clear the rd_eq_wr load disable bit. */
input next_x, /* Nexxt X for triangle scanning. */
output reg [2:0] dir, /* direction register output. */
output wrk0_eqz, /* working register/counter equals zero. */
output wrk5_eqz, /* working register/counter equals zero. */
output reg [15:0] ax, /* ax output to alu */
output reg [15:0] bx, /* bx output to alu */
output reg [15:0] ay, /* ay output to alu */
output reg [15:0] by, /* by output to alu */
output clip, /* clipping output */
output [15:0] srcx,
output [15:0] srcy,
output [15:0] dstx,
output [15:0] dsty,
output fg_bgn, /* foreground=1, background=0, line patterns */
output [15:0] lpat_state, /* read back path for line pattern state */
output [31:0] clpx_bus_2, /* clipping X values. */
output reg sol_2, /* start of line flag output. */
output reg eol_2, /* start of line flag output. */
output y_clip_2, /* current y is (ymin < y > ymax) */
output reg rd_eq_wr, /* read words is equal to write words. */
output wr_gt_8, /* write words is greater than eight. */
output wr_gt_16, /* write words is greater than sixteen. */
output reg [4:0] xpat_ofs,
output reg [4:0] ypat_ofs,
output [15:0] real_dstx,
output [15:0] real_dsty,
output xchng,
output ychng,
output reg eneg, /* Error term is negative. */
output reg eeqz, /* Error term is equal to zero. */
output reg [2:0] clp_status,
output reg [31:0] clptl_r, // clipping Top Left, for 3D core.
output reg [31:0] clpbr_r // clipping Bottom Right for 3D core.
);
// `include "de_param.h"
parameter SRC = 4'h0,
DST = 4'h1,
WRK0 = 4'h2,
WRK1 = 4'h3,
WRK2 = 4'h4,
WRK3 = 4'h5,
WRK4 = 4'h6,
WRK5 = 4'h7,
WRK6X = 4'h8,
DST_WRK1Y = 4'h9,
SRC_WRK1 = 4'ha,
WRK3_WRK5 = 4'hb,
WRK4_WRK6X = 4'hc,
WRK7X = 4'hd, // pipeline address.
SORGL = 4'he, // src org address low nibble
DORGL = 4'hf, // src org address low nibble.
xend_pc = 5'h09,
xmin_pc = 5'h0a,
e1s_se = 5'h09,
e2s_se = 5'h0a,
e3s_se = 5'h0b,
e1x_se = 5'h0c,
e2x_se = 5'h0e,
e3x_se = 5'h0f;
reg v3_flag; /* flag indicating a third verticy. */
reg load_actvn; /* X zoom enable signal. */
always @(posedge de_clk)load_actvn <= load_actvn_in;
/**************************************************************************/
/* split up the source counter control bits. */
wire s_chgx, /* source change the X position counter.*/
s_rht, /* source x direction is right. */
s_chgy, /* source change the Y position counter.*/
s_dwn; /* source y direction is down. */
assign {s_chgx,s_rht,s_chgy,s_dwn}= src_cntrl;
/**************************************************************************/
/* split up the destination counter control bits. */
wire d_chgy, /* destination change the Y position counter. */
d_dwn; /* destination y direction is down. */
assign {d_chgy,d_dwn}= dst_cntrl;
assign ychng = s_chgy | d_chgy;
assign xchng = s_chgx;
/**************************************************************************/
/* split up the xy input bus. */
wire [31:0] xy0_1,xy1_1,xy2_1,xy3_1,xy4_1;
assign {xy0_1,xy1_1,xy2_1,xy3_1,xy4_1} = xydat_1;
/****************************************************************************************/
/* split up the xy input bus. */
reg wehn,weln;
always @(wen) {wehn,weln} = wen;
/****************************************************************************************/
/* create the ps16_1 and ps32_1 signals. */
wire ps16_1 = ps_1[0]; /* pixel size equals sixteen.*/
wire ps32_1 = (ps_1 == 2'b10); /* pixel size equals thirtytwo.*/
/****************************************************************************************/
wire [15:0] de_sorgx_2;
wire [15:0] de_dorgx_2;
wire [15:0] de_sorgy_2;
wire [15:0] de_dorgy_2;
assign de_sorgx_2 = (ps32_2) ? de_sorg_2[31:16] << 2:
(ps16_2) ? de_sorg_2[31:16] << 1: de_sorg_2[31:16];
assign de_dorgx_2 = (ps32_2) ? de_dorg_2[31:16] << 2:
(ps16_2) ? de_dorg_2[31:16] << 1: de_dorg_2[31:16];
assign de_sorgy_2 = (ps32_2) ? de_sorg_2[15:0] << 2:
(ps16_2) ? de_sorg_2[15:0] << 1: de_sorg_2[15:0];
assign de_dorgy_2 = (ps32_2) ? de_dorg_2[15:0] << 2:
(ps16_2) ? de_dorg_2[15:0] << 1: de_dorg_2[15:0];
/********************************************************************************/
/* DEFINE ALL SECOND LEVEL REGISTERS IN THE DRAWING ENGINE */
/********************************************************************************/
reg [15:0] clip_dstx_end;
reg [4:0] new_xpat_ofs;
reg [4:0] new_ypat_ofs;
reg [31:0] new_lpat_r; /* line pattern register */
reg [15:0] new_pctrl_r; /* line pattern control register */
reg [31:0] new_clptl_r; /* clipping top left corner register */
reg [31:0] new_clpbr_r; /* clipping bottom right corner register*/
reg [15:0] new_clptll_r; /* clipping top left corner register */
reg [15:0] new_clptlh_r; /* clipping top left corner register */
reg [15:0] new_clpbrl_r; /* clipping bottom right corner register*/
reg [15:0] new_clpbrh_r; /* clipping bottom right corner register*/
/* noop | bitblt | line | eline | trian | rxfer | wxfer */
/* | | | | | | */
reg [31:0] new_src_r; /* NA | src | src | src | pptr | offset| offset*/
reg [15:0] new_dsth_r; /* trig | dst | dst | dst | p0 | width | width */
reg [15:0] new_dstl_r; /* trig | dst | dst | dst | p0 | width | width */
reg [31:0] new_wrk0_r; /* NA | W/H |DX/DY | DX/DY | p3 | | */
reg [31:0] new_wrk1_r; /* | | | | p2 | | */
reg [31:0] new_wrk2_r; /* | | | | p1 | | */
reg [31:0] new_wrk3_r; /* | | | | p1 | | */
reg [31:0] new_wrk4_r; /* | | | | | | */
reg [15:0] new_wrk5h_r; /* | | | | | | */
reg [15:0] new_wrk5l_r; /* | | | | | | */
reg [15:0] new_wrk6x_r; /* | | | | | | */
reg [15:0] new_wrk7x_r; /* | | | | | | */
reg [31:0] lpat_r; /* line pattern register */
reg [15:0] pctrl_r; /* line pattern control register */
reg [15:0] srcx_r; /* working register source */
reg [15:0] srcy_r; /* working register source */
reg [15:0] dstx_r; /* working register destination */
reg [15:0] dsty_r; /* working register destination */
reg [15:0] wrk0x_r; /* working register zero */
reg [15:0] wrk0y_r; /* working register zero */
reg [15:0] wrk1x_r; /* working register one */
reg [15:0] wrk1y_r; /* working register one */
reg [15:0] wrk2x_r; /* working register two */
reg [15:0] wrk2y_r; /* working register two */
reg [15:0] wrk3x_r; /* working register three */
reg [15:0] wrk3y_r; /* working register three */
reg [15:0] wrk4x_r; /* working register four */
reg [15:0] wrk4y_r; /* working register four */
reg [15:0] wrk5x_r; /* working register five */
reg [15:0] wrk5y_r; /* working register five */
reg [15:0] wrk6x_r; /* working register six X */
reg [15:0] wrk7x_r; /* working register seven X */
/********************************************************************************/
/* DEFINE ALL LOAD SIGNALS */
/********************************************************************************/
reg iload_pat_ofs;
reg ild_src_h; /* working register source load high. */
reg ild_src_l; /* working register source load low. */
reg ild_dst_h; /* working register dest load high. */
reg ild_dst_l; /* working register dest load low. */
reg ild_wrk0_h; /* working register zero load high. */
reg ild_wrk0_l; /* working register zero load low. */
reg ild_wrk1_h; /* working register one load high. */
reg ild_wrk1_l; /* working register one load low. */
reg ild_wrk2_h; /* working register two load high. */
reg ild_wrk2_l; /* working register two load low. */
reg ild_wrk3_h; /* working register three load high. */
reg ild_wrk3_l; /* working register three load low. */
reg ild_wrk4_h; /* working register four load high. */
reg ild_wrk4_l; /* working register four load low. */
reg ild_wrk5_h; /* working register five load high. */
reg ild_wrk5_l; /* working register five load low. */
reg ild_wrk6x_h; /* working register six X load high. */
reg ild_wrk7x_h; /* working register seven X load high. */
wire load_pat_ofs;
wire ld_src_h; /* working register source load high. */
wire ld_src_l; /* working register source load low. */
wire ld_dst_h; /* working register dest load high. */
wire ld_dst_l; /* working register dest load low. */
wire ld_wrk0_h; /* working register zero load high. */
wire ld_wrk0_l; /* working register zero load low. */
wire ld_wrk1_h; /* working register one load high. */
wire ld_wrk1_l; /* working register one load low. */
wire ld_wrk2_h; /* working register two load high. */
wire ld_wrk2_l; /* working register two load low. */
wire ld_wrk3_h; /* working register three load high. */
wire ld_wrk3_l; /* working register three load low. */
wire ld_wrk4_h; /* working register four load high. */
wire ld_wrk4_l; /* working register four load low. */
wire ld_wrk5_h; /* working register five load high. */
wire ld_wrk5_l; /* working register five load low. */
wire ld_wrk6x_h; /* working register six X load high. */
wire ld_wrk7x_h; /* working register seven X load high. */
assign load_pat_ofs = iload_pat_ofs;
assign ld_src_h = ild_src_h;
assign ld_src_l = ild_src_l;
assign ld_dst_h = ild_dst_h;
assign ld_dst_l = ild_dst_l;
assign ld_wrk0_h = ild_wrk0_h;
assign ld_wrk0_l = ild_wrk0_l;
assign ld_wrk1_h = ild_wrk1_h;
assign ld_wrk1_l = ild_wrk1_l;
assign ld_wrk2_h = ild_wrk2_h;
assign ld_wrk2_l = ild_wrk2_l;
assign ld_wrk3_h = ild_wrk3_h;
assign ld_wrk3_l = ild_wrk3_l;
assign ld_wrk4_h = ild_wrk4_h;
assign ld_wrk4_l = ild_wrk4_l;
assign ld_wrk5_h = ild_wrk5_h;
assign ld_wrk5_l = ild_wrk5_l;
assign ld_wrk6x_h = ild_wrk6x_h;
assign ld_wrk7x_h = ild_wrk7x_h;
/********************************************************************************/
/* DEFINE OTHER REGISTERS */
/********************************************************************************/
reg xl_xmin; /* X is less than Xmin */
reg xmaxl_x; /* Xmax is less than X */
reg ymaxl_y; /* Ymax is less than Y */
reg yl_ymin; /* Y is less than Ymin */
/********************************************************************************/
/* */
/* ASSIGN OUTPUTS TO REGISTERS */
/* */
/********************************************************************************/
wire [15:0] clip_dstx; /* destination X wire */
wire [15:0] clip_dsty; /* destination Y wire */
wire [15:0] xmin; /* clipping X min */
wire [15:0] xmax; /* clipping X max */
wire [15:0] ymin; /* clipping Y min */
wire [15:0] ymax; /* clipping Y max */
wire [3:0] out_code; /* clipping out code register */
assign srcx = srcx_r;
assign srcy = srcy_r;
assign dstx = dstx_r;
assign dsty = dsty_r;
assign clip_dstx = (line_actv_2) ? srcx_r : dstx_r;
assign clip_dsty = (line_actv_2) ? srcy_r : dsty_r;
assign real_dstx = (!line_actv_2 && ps32_2) ? clip_dstx << 2 :
(!line_actv_2 && ps16_2) ? clip_dstx << 1 : clip_dstx;
assign real_dsty = clip_dsty;
assign xmin = clptl_r[31:16]; /* clipping X min */
assign ymin = clptl_r[15:0]; /* clipping X max */
assign xmax = clpbr_r[31:16]; /* clipping Y min */
assign ymax = clpbr_r[15:0]; /* clipping Y max */
assign out_code = {xl_xmin,xmaxl_x,ymaxl_y,yl_ymin};
assign clip=(((clp_2==2'b10) && (out_code != 4'b0000))
|| ((clp_2==2'b11) && (out_code == 4'b0000)));
assign y_clip_2 =(((clp_2==2'b10) && (ymaxl_y | yl_ymin))
|| ((clp_2==2'b11) && !(ymaxl_y | yl_ymin)));
assign clpx_bus_2 = {xmax,xmin};
/**********************************************************************/
/* */
/* REGISTER WRITE FUNCTION */
/* DATA INPUT SELECTION */
/* */
/* */
/**********************************************************************/
/* if load active select the input data as follows to the registers. */
always @*
if(!load_actvn)
begin
new_src_r = xy0_1;
if(eline_actv_1) new_wrk0_r = xy2_1;
else new_wrk0_r = xy2_1;
end
else begin
new_src_r = {fx,fy};
new_wrk0_r = {fx,fy};
end
/**************************************************************************/
/* Destination register input MUX. */
always @*
if (!load_actvn) new_dsth_r = xy1_1[31:16];
else new_dsth_r = fx;
always @*
if (!load_actvn) new_dstl_r = xy1_1[15:0];
else new_dstl_r = fy;
always @*
if (!load_actvn)
if (eline_actv_1) new_wrk1_r = xy2_1; // {error,NA}
else new_wrk1_r = xy3_1;
else new_wrk1_r = {fx,fy};
always @*
if (!load_actvn)
if (eline_actv_1) new_wrk2_r = xy3_1; // {errinc1,errinc2}
else new_wrk2_r = xy4_1;
else new_wrk2_r = {fx,fy};
always @* new_wrk3_r = {fx,fy};
/**************************************************************************/
/* WRK5 register input MUX. */
always @* new_wrk5h_r = fx;
always @*
if (!load_actvn) new_wrk5l_r = {13'b0,xy3_1[2:0]};
else new_wrk5l_r = fy;
/**************************************************************************/
/* Hardwired Second level registers. */
always @* begin
new_lpat_r = lpat_1;
new_pctrl_r = pctrl_1;
new_wrk4_r[31:16] = fx;
new_wrk4_r[15:0] = fy;
new_wrk6x_r[15:0] = fx;
new_wrk7x_r[15:0] = fx;
end
/* Second level clip top left and bottom right. */
always @*
if (load_actv_3d) new_clptlh_r = clptl_1[31:16];
else if (ps16_1) new_clptlh_r = clptl_1[31:16] << 1;
else if( ps32_1) new_clptlh_r = clptl_1[31:16] << 2;
else new_clptlh_r = clptl_1[31:16];
/* Second level clip top left and bottom right. */
always @*
if (load_actv_3d) new_clpbrh_r = clpbr_1[31:16];
else if (ps16_1) new_clpbrh_r = clpbr_1[31:16] << 1;
else if (ps32_1) new_clpbrh_r = clpbr_1[31:16] << 2;
else new_clpbrh_r = clpbr_1[31:16];
/* Second level clip top left and bottom right. */
always @* new_clptll_r = clptl_1[15:0];
/* Second level clip top left and bottom right. */
always @* new_clpbrl_r = clpbr_1[15:0];
always @*
begin
new_xpat_ofs = xy3_1[20:16];
new_ypat_ofs = xy3_1[4:0];
end
always @(posedge de_clk) begin
if (load_pat_ofs) xpat_ofs <= new_xpat_ofs;
if (load_pat_ofs) ypat_ofs <= new_ypat_ofs;
end
/**************************************************************************/
/* REGISTER WRITE STROBE DECODER */
/**************************************************************************/
always @(posedge de_clk)iload_pat_ofs <= ~load_actvn_in;
always @(posedge de_clk) begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
if(!load_actvn_in) begin
ild_src_h <= ~pline_actv_1;
ild_src_l <= ~pline_actv_1;
ild_dst_h <= 1'b1;
ild_dst_l <= 1'b1;
ild_wrk0_h <= 1'b1;
ild_wrk0_l <= 1'b1;
ild_wrk1_h <= 1'b1;
ild_wrk1_l <= 1'b1;
ild_wrk2_h <= 1'b1;
ild_wrk2_l <= 1'b1;
ild_wrk3_h <= 1'b1;
ild_wrk3_l <= 1'b1;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b1;
ild_wrk5_l <= 1'b1;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end else begin
case(wad) // synopsys parallel_case
SRC: begin
ild_src_h <= ~wehn;
ild_src_l <= ~weln;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
DST: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= ~wehn;
ild_dst_l <= ~weln;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK0: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= ~wehn;
ild_wrk0_l <= ~weln;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK1: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= ~wehn;
ild_wrk1_l <= ~weln;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK2: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= ~wehn;
ild_wrk2_l <= ~weln;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK3: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= ~wehn;
ild_wrk3_l <= ~weln;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK4: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= ~wehn;
ild_wrk4_l <= ~weln;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK5: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= ~wehn;
ild_wrk5_l <= ~weln;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK6X: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= ~wehn;
ild_wrk7x_h <= 1'b0;
end
WRK7X: begin
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= ~wehn;
end
DST_WRK1Y: begin /* load both the dst and wrk2 registers. */
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= ~wehn;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= ~weln;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
SRC_WRK1: begin /* load both the src and wrk1 registers. */
ild_src_h <= ~wehn;
ild_src_l <= ~weln;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= ~wehn;
ild_wrk1_l <= ~weln;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK3_WRK5: begin /* load both the wrk3 and wrk5 registers. */
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= ~wehn;
ild_wrk3_l <= ~weln;
ild_wrk4_h <= 1'b0;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= ~wehn;
ild_wrk5_l <= ~weln;
ild_wrk6x_h <= 1'b0;
ild_wrk7x_h <= 1'b0;
end
WRK4_WRK6X: begin /* load both the wrk4 and wrk6x registers. */
ild_src_h <= 1'b0;
ild_src_l <= 1'b0;
ild_dst_h <= 1'b0;
ild_dst_l <= 1'b0;
ild_wrk0_h <= 1'b0;
ild_wrk0_l <= 1'b0;
ild_wrk1_h <= 1'b0;
ild_wrk1_l <= 1'b0;
ild_wrk2_h <= 1'b0;
ild_wrk2_l <= 1'b0;
ild_wrk3_h <= 1'b0;
ild_wrk3_l <= 1'b0;
ild_wrk4_h <= ~wehn;
ild_wrk4_l <= 1'b0;
ild_wrk5_h <= 1'b0;
ild_wrk5_l <= 1'b0;
ild_wrk6x_h <= ~wehn;
ild_wrk7x_h <= 1'b0;
end
endcase
end
end
/********************************************************************************/
/* REGISTER A ADDRESS OUTPUT SELECTOR */
/********************************************************************************/
reg [13:0] a_sel;
always @(posedge de_clk)
begin
case(aad) // synopsys parallel_case
SRC: a_sel <= 14'b00000000000001;
DST: a_sel <= 14'b00000000000010;
WRK0: a_sel <= 14'b00000000000100;
WRK1: a_sel <= 14'b00000000001000;
WRK2: a_sel <= 14'b00000000010000;
WRK3: a_sel <= 14'b00000000100000;
WRK4: a_sel <= 14'b00000001000000;
WRK5: a_sel <= 14'b00000010000000;
WRK6X: a_sel <= 14'b00000100000000;
WRK7X: a_sel <= 14'b00001000000000;
SORGL: a_sel <= 14'b00010000000000;
DORGL: a_sel <= 14'b00100000000000;
xend_pc:a_sel <= 14'b01000000000000;
xmin_pc:a_sel <= 14'b10000000000000;
default: a_sel <= 12'b000000000000;
endcase
end
always @* begin
ax=fx;
ay=fy;
if (a_sel[0]) begin
ax=srcx_r;
ay=srcy_r;
end
if (a_sel[1]) begin
ax=dstx_r;
ay=dsty_r;
end
if (a_sel[2]) begin
ax=wrk0x_r;
ay=wrk0y_r;
end
if (a_sel[3]) begin
ax=wrk1x_r;
ay=wrk1y_r;
end
if (a_sel[4]) begin
ax=wrk2x_r;
ay=wrk2y_r;
end
if (a_sel[5]) begin
ax=wrk3x_r;
ay=wrk3y_r;
end
if (a_sel[6]) begin
ax=wrk4x_r;
ay=wrk4y_r;
end
if (a_sel[7]) begin
ax=wrk5x_r;
ay=wrk5y_r;
end
if (a_sel[8]) ax=wrk6x_r;
if (a_sel[9]) ax=wrk7x_r;
if (a_sel[12]) ax=clip_dstx_end;
if (a_sel[13]) ax=xmin;
if (a_sel[10]) begin
ax=de_sorgx_2;
ay=de_sorgy_2;
// ax=16'b1;
// ay=16'b1;
end
if(a_sel[11]) begin
ax=de_dorgx_2;
ay=de_dorgy_2;
// ax=16'b1;
// ay=16'b1;
end
end
/**************************************************************************/
/* REGISTER B ADDRESS OUTPUT SELECTOR */
/**************************************************************************/
reg [17:0] b_sel;
always @(posedge de_clk) begin
case(bad) // synopsys parallel_case
SRC: b_sel <= 18'b000000000000000001; // 5'h0
DST: b_sel <= 18'b000000000000000010; // 5'h1
WRK0: b_sel <= 18'b000000000000000100; // 5'h2
WRK1: b_sel <= 18'b000000000000001000; // 5'h3
WRK2: b_sel <= 18'b000000000000010000; // 5'h4
WRK3: b_sel <= 18'b000000000000100000; // 5'h5
WRK4: b_sel <= 18'b000000000001000000; // 5'h6
WRK5: b_sel <= 18'b000000000010000000; // 5'h7
WRK6X: b_sel <= 18'b000000000100000000; // 5'h8
WRK7X: b_sel <= 18'b000000001000000000; // 5'hd
e1s_se: b_sel <= 18'b000000010000000000; // 5'h9
e2s_se: b_sel <= 18'b010000100000000000; // 5'ha
e3s_se: b_sel <= 18'b100001000000000000; // 5'hb
e1x_se: b_sel <= 18'b000010000000000000; // 5'hc
e2x_se: b_sel <= 18'b000100000000000000; // 5'he
e3x_se: b_sel <= 18'b001000000000000000; // 5'hf
default: b_sel <= 10'b0000000000;
endcase
end
always @* begin
bx=fx;
by=fy;
if (b_sel[0]) begin
bx=srcx_r;
by=srcy_r;
end
if (b_sel[1]) begin
bx=dstx_r;
by=dsty_r;
end
if (b_sel[2]) begin
bx=wrk0x_r;
by=wrk0y_r;
end
if (b_sel[3]) begin
bx=wrk1x_r;
by=wrk1y_r;
end
if (b_sel[4]) begin
bx=wrk2x_r;
by=wrk2y_r;
end
if (b_sel[5]) begin
bx=wrk3x_r;
by=wrk3y_r;
end
if (b_sel[6]) begin
bx=wrk4x_r;
by=wrk4y_r;
end
if (b_sel[7]) begin
bx=wrk5x_r;
by=wrk5y_r;
end
if (b_sel[8]) bx=wrk6x_r;
if (b_sel[9]) bx=wrk7x_r;
if (b_sel[16]) bx=xmin;
if (b_sel[17]) bx=xmax;
end
/**************************************************************************/
/* PRE CLIPPING COMPARATORS */
/**************************************************************************/
reg xel_xmin,xmaxl_xe;
wire [2:0] clp_adj;
assign clp_adj = (ps32_2) ? 3'b100 : (ps16_2) ? 3'b010 : 3'b001;
// always @* clip_dstx_end = clip_dstx + wrk0x_r - clp_adj;
always @(posedge de_clk) clip_dstx_end <= clip_dstx + wrk0x_r - clp_adj;
always @* begin
if(clip_dstx_end[15] & !xmin[15])xel_xmin=1;
else if(!clip_dstx_end[15] & xmin[15])xel_xmin=0;
else if(clip_dstx_end[14:4] < xmin[14:4])xel_xmin=1;
else if(clip_dstx_end < xmin)xel_xmin=1;
else xel_xmin=0;
if(clip_dstx_end[15] & !xmax[15])xmaxl_xe=0;
else if(!clip_dstx_end[15] & xmax[15])xmaxl_xe=1;
else if(xmax[14:4] < clip_dstx_end[14:4])xmaxl_xe=1;
else if(xmax < clip_dstx_end)xmaxl_xe=1;
else xmaxl_xe=0;
end
// always @*
always @(posedge de_clk)
case({clp_2[1],xl_xmin,xmaxl_x,xel_xmin,xmaxl_xe})
5'b10101: clp_status <= 3'b100; // trivial reject
5'b11010: clp_status <= 3'b100; // trivial reject
5'b11000: clp_status <= 3'b001; // case 1
5'b11001: clp_status <= 3'b010; // case 2
5'b10001: clp_status <= 3'b011; // case 4
default: clp_status <= 3'b000; // no clipping applied
endcase
/**************************************************************************/
/* CLIPPING COMPARATORS */
/**************************************************************************/
always @* begin
if( clip_dstx[15] & !xmin[15]) xl_xmin=1; // -dstx & +xmin
else if(!clip_dstx[15] & xmin[15]) xl_xmin=0; // +dstx & -xmin
else if((clip_dstx[14:4] < xmin[14:4]) & (blt_actv_2))xl_xmin=1; //
else if( clip_dstx < xmin) xl_xmin=1; // dstx < xmin
else xl_xmin=0;
if( clip_dstx[15] & !xmax[15]) xmaxl_x=0;
else if(!clip_dstx[15] & xmax[15]) xmaxl_x=1;
else if((xmax[14:4] < clip_dstx[14:4]) & (blt_actv_2))xmaxl_x=1;
else if(xmax < clip_dstx) xmaxl_x=1;
else xmaxl_x=0;
if(clip_dsty[15] & !ymin[15]) yl_ymin=1;
else if(!clip_dsty[15] & ymin[15]) yl_ymin=0;
else if(clip_dsty < ymin) yl_ymin=1;
else yl_ymin=0;
if( clip_dsty[15] & !ymax[15]) ymaxl_y=0;
else if(!clip_dsty[15] & ymax[15]) ymaxl_y=1;
else if(ymax < clip_dsty) ymaxl_y=1;
else ymaxl_y=0;
end
/**************************************************************************/
/* SOURCE X COUNTER */
/**************************************************************************/
always @(posedge de_clk) begin
if (ld_src_h && !src_upd) srcx_r <= new_src_r[31:16];
else if (ld_src_h && src_upd && ps16_2) srcx_r <= new_src_r[31:16] >>1;
else if (ld_src_h && src_upd && ps32_2) srcx_r <= new_src_r[31:16] >>2;
else if (mul && ps16_2) srcx_r <= srcx_r<<1;
else if (mul && ps32_2) srcx_r <= srcx_r<<2;
else if (s_chgx && s_rht && ps16_2) srcx_r <= srcx_r+16'h2;
else if (s_chgx && s_rht && ps32_2) srcx_r <= srcx_r+16'h4;
else if (s_chgx && s_rht) srcx_r <= srcx_r+16'h1;
else if (s_chgx && !s_rht && ps16_2) srcx_r <= srcx_r-16'h2;
else if (s_chgx && !s_rht && ps32_2) srcx_r <= srcx_r-16'h4;
else if (s_chgx && !s_rht) srcx_r <= srcx_r-16'h1;
end
/**************************************************************************/
/* SOURCE Y COUNTER */
/**************************************************************************/
always @(posedge de_clk) begin
if (ld_src_l) srcy_r <= new_src_r[15:0];
else if (s_chgy && s_dwn) srcy_r <= srcy_r+16'h1;
else if (s_chgy && !s_dwn) srcy_r <= srcy_r-16'h1;
end
/**************************************************************************/
/* DESTINATION X REGISTER */
/**************************************************************************/
always @(posedge de_clk)
begin
if (ld_dst_h) dstx_r <= new_dsth_r;
else if (mul && ps16_2) dstx_r <= dstx_r<<1;
else if (mul && ps32_2) dstx_r <= dstx_r<<2;
end
/*************************************************************************/
/* DESTINATION Y COUNTER */
/*************************************************************************/
always @(posedge de_clk) begin
if(ld_dst_l) dsty_r <= new_dstl_r;
else if(d_chgy && d_dwn) dsty_r <= dsty_r+16'h1;
else if(d_chgy && !d_dwn) dsty_r <= dsty_r-16'h1;
end
/*************************************************************************/
/* WORKING ZERO X COUNTER */
/*************************************************************************/
always @(posedge de_clk) begin
if(ld_wrk0_h) wrk0x_r <= new_wrk0_r[31:16];
else if(mul && ps16_2) wrk0x_r <= wrk0x_r<<1;
else if(mul && ps32_2) wrk0x_r <= wrk0x_r<<2;
else if(w_chgx && ps16_2 && !line_actv_2) wrk0x_r <= wrk0x_r-16'h2;
else if(w_chgx && ps32_2 && !line_actv_2) wrk0x_r <= wrk0x_r-16'h4;
else if(w_chgx) wrk0x_r <= wrk0x_r-16'h1;
end
/*************************************************************************/
/* REMAINING REGISTERS */
/*************************************************************************/
always @(posedge de_clk) begin
if (ld_wrk0_l) wrk0y_r <= new_wrk0_r[15:0];
if(!load_actvn_in && (line_actv_1 | line_actv_3d_1) && prst) begin
lpat_r <= new_lpat_r;
pctrl_r <= new_pctrl_r;
end
if(!load_actvn_in) begin
clptl_r <= {new_clptlh_r,new_clptll_r};
clpbr_r <= {new_clpbrh_r,new_clpbrl_r};
end
end
/**************************************************************************/
/* ERROR REGISTER. */
reg [15:0] ei_in;
reg [15:0] new_error_r;
reg cin;
always @(posedge de_clk) begin
if(ld_wrk1_h) wrk1x_r <= new_wrk1_r[31:16]; /* load the register */
else if(inc_err | rst_err) wrk1x_r <= new_error_r; /* load the next error. */
end
always @*
if (inc_err) begin
ei_in = wrk2y_r;
cin = 0;
end else if(rst_err) begin
ei_in = ~wrk2x_r;
cin = 1;
end else begin
ei_in = 0;
cin = 0;
end
always @(ei_in or wrk1x_r or cin) new_error_r = ei_in + wrk1x_r + cin;
always @(wrk1x_r) eneg = wrk1x_r[15];
always @(wrk1x_r) eeqz = ~|wrk1x_r;
/************************************************************************************************/
always @(posedge de_clk) if(ld_wrk1_l) wrk1y_r <= new_wrk1_r[15:0];
always @(posedge de_clk) if(ld_wrk2_h) wrk2x_r <= new_wrk2_r[31:16];
always @(posedge de_clk) if(ld_wrk2_l) wrk2y_r <= new_wrk2_r[15:0];
always @(posedge de_clk) if(ld_wrk3_h) wrk3x_r <= new_wrk3_r[31:16];
always @(posedge de_clk) if(ld_wrk3_l) wrk3y_r <= new_wrk3_r[15:0];
always @(posedge de_clk) if(ld_wrk4_h) wrk4x_r <= new_wrk4_r[31:16];
always @(posedge de_clk) if(ld_wrk4_l) wrk4y_r <= new_wrk4_r[15:0];
always @(posedge de_clk) if(ld_wrk5_h) wrk5x_r <= new_wrk5h_r;
always @(posedge de_clk) if(ld_wrk5_l) wrk5y_r <= new_wrk5l_r;
always @(posedge de_clk) if(ld_wrk6x_h) wrk6x_r <= new_wrk6x_r[15:0];
always @(posedge de_clk) if(ld_wrk7x_h) wrk7x_r <= new_wrk7x_r[15:0];
/********************************************************************************/
reg load_disab;
wire load_disab_d;
assign load_disab_d = load_disab; /* dummy delay for hdl simulation. */
wire ird_eq_wr;
assign ird_eq_wr = (wrk3x_r[11:0] == wrk4x_r[11:0]);
/********************************************************************************/
wire cmd_rstn;
assign cmd_rstn = de_rstn & load_actvn;
wire ld_wrk4d_h;
assign ld_wrk4d_h = ld_wrk4_h; /* dummy delay for hdl simulation. */
/* delay the load by one clock and if load_disab is set block the load. */
reg ld_wrk4dd_h;
always @(posedge de_clk or negedge cmd_rstn)
begin
if(!cmd_rstn) ld_wrk4dd_h <= 1'b0;
else if(ld_wrk4d_h & ~load_disab_d)ld_wrk4dd_h <= 1'b1;
else if(ld_wrk4d_h & ~load_disab_d)ld_wrk4dd_h <= 1'b1;
else ld_wrk4dd_h <= 1'b0;
end
wire ld_wrk4ddd_h;
assign ld_wrk4ddd_h = ld_wrk4dd_h;
always @(posedge de_clk or negedge cmd_rstn)
begin
if(!cmd_rstn) rd_eq_wr <= 1'b0;
else if(ld_wrk4ddd_h)rd_eq_wr <= ird_eq_wr;
end
/* This signal allows the rd_eq_wr flag to be loaded only once per command. */
always @(posedge de_clk or negedge cmd_rstn)
begin
if(!cmd_rstn) load_disab <= 1'b0;
else if(b_clr_ld_disab)load_disab <= 1'b0;
else if(ld_wrk4ddd_h) load_disab <= 1'b1;
end
/********************************************************************************/
/* LINE DIRECTION REGISTER */
/********************************************************************************/
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn) dir <= 3'b0;
else if(ldmajor) dir[2] <= fx[15];
else if(ldminor) dir[1:0] <= {fy[15],fx[15]};
else if(!load_actvn_in && !stpl_1)dir <= {1'b0,xy3_1[1:0]};
else if(!load_actvn_in) dir <= 3'b0;
end
/********************************************************************************/
/* DELAY MEMORY REQUEST */
/********************************************************************************/
reg del_mem_req;
always @(posedge de_clk)del_mem_req <= mem_req;
reg del_mem_read;
always @(posedge de_clk)del_mem_read <= mem_read;
/********************************************************************************/
/* START OF LINE FLAG */
/********************************************************************************/
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn) sol_2 <= 1'b0;
else if(set_sol) sol_2 <= 1'b1;
else if(del_mem_req & !del_mem_read)sol_2 <= 1'b0;
else if(tx_clr_seol) sol_2 <= 1'b0;
end
/********************************************************************************/
/* END OF LINE FLAG */
/********************************************************************************/
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn) eol_2 <= 1'b0;
else if(set_eol) eol_2 <= 1'b1;
else if(del_mem_req)eol_2 <= 1'b0;
else if(tx_clr_seol)eol_2 <= 1'b0;
end
/********************************************************************************/
/* Line Pattern Control */
/********************************************************************************/
wire end_scl; /* end of scale factor. */
wire end_pat; /* end of pattern signal. */
wire [4:0] plen; /* pattern length. */
wire [2:0] pscl; /* pattern scale. */
wire [4:0] sptr; /* pattern initial start point. */
wire [2:0] sscl; /* pattern initial scale factor. */
assign {sscl,sptr,pscl,plen} = pctrl_r;
reg [4:0] pptr_r;
reg [2:0] scl;
reg load_pat;
always @(posedge de_clk)load_pat <= (prst && (line_actv_1 | line_actv_3d_1) && !load_actvn_in);
/* PATTERN CONTROL DEFAULT VALUES */
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)
begin
pptr_r <= 5'b0;
scl <= 3'b0;
end
else if(load_pat)
begin
pptr_r <= sptr;
scl <= pscl - sscl;
end
else if((l3_incpat | incpat) && end_scl)
begin
scl <= pscl;
if(end_pat)pptr_r <= 5'b0;
else pptr_r <= pptr_r+5'b1;
end
else if(l3_incpat | incpat) scl <= scl-3'b1;
end
/* ASSIGN TEST BITS */
assign end_pat = ((plen-1) == pptr_r);
assign end_scl = (scl == 0);
/* ASSIGN PATTERN MULTIPLEXER */
assign fg_bgn = lpat_r[pptr_r];
/* CREATE THE READ BACK STATE OF THE LINE PATTERN */
assign lpat_state = {(pscl-scl),pptr_r,pscl,plen};
/********************************************************************************/
/* Status comparators */
/* */
/* CREATE THE WRK_EQZ SIGNAL */
assign wrk0_eqz = ~|wrk0x_r;
/* CREATE THE WRK_EQZ SIGNAL */
assign wrk5_eqz = ~|wrk5y_r;
/* CREATE THE WRITE WORDS GREATER THAN EIGHT SIGNAL */
assign wr_gt_8 = (|wrk4x_r[15:4]) | (wrk4x_r[3] & |wrk4x_r[2:0]);
assign wr_gt_16 = (|wrk4x_r[15:5]) | (wrk4x_r[4] & |wrk4x_r[3:0]);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Electrical_Velocity_To_Position.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Electrical_Velocity_To_Position
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Electrical_Velocity_To_Position
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
EV,
EP
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] EV; // sfix18_En6
output signed [17:0] EP; // sfix18_En14
wire signed [35:0] Gain_out1; // sfix36_En37
wire signed [31:0] Data_Type_Conversion2_out1; // sfix32_En27
wire signed [31:0] Reset_Delay_out1; // sfix32_En27
wire signed [31:0] Add3_out1; // sfix32_En27
wire signed [31:0] Wrap_2pi_Once_out1; // sfix32_En27
wire signed [17:0] Data_Type_Conversion1_out1; // sfix18_En14
// Electrical Velocity To Position
// <S20>/Gain
assign Gain_out1 = 85899 * EV;
// <S20>/Data Type Conversion2
assign Data_Type_Conversion2_out1 = {{6{Gain_out1[35]}}, Gain_out1[35:10]};
// <S20>/Add3
assign Add3_out1 = Data_Type_Conversion2_out1 + Reset_Delay_out1;
// <S20>/Wrap_2pi_Once
controllerHdl_Wrap_2pi_Once u_Wrap_2pi_Once (.x(Add3_out1), // sfix32_En27
.wrap(Wrap_2pi_Once_out1) // sfix32_En27
);
// <S20>/Reset_Delay
controllerHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.In(Wrap_2pi_Once_out1), // sfix32_En27
.Out(Reset_Delay_out1) // sfix32_En27
);
// <S20>/Data Type Conversion1
assign Data_Type_Conversion1_out1 = Reset_Delay_out1[30:13];
assign EP = Data_Type_Conversion1_out1;
endmodule // controllerHdl_Electrical_Velocity_To_Position
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO-based PL Free Pool
* ============-==========
*
* Serves next free PL id. Tail flits sent on output link replenish free PL pool
*
* One free PL pool per output port
*
*/
module LAG_pl_free_pool (flits_tail, flits_valid,
// Unrestricted free pool
pl_alloc_status, // PL allocation status
pl_allocated, // which PLs were allocated on this cycle?
pl_empty, // is downstream FIFO associated with PL empty?
clk, rst_n);
parameter num_pls = 4;
parameter fifo_free_pool = 0; // organise free pool as FIFO (offer at most one PL per output port per cycle)
// only applicable if fifo_free_pool = 0
parameter only_allocate_pl_when_empty = 0; // only allow a PL to be allocated when it is empty
//-------
input [num_pls-1:0] flits_tail;
input [num_pls-1:0] flits_valid;
input [num_pls-1:0] pl_allocated;
output [num_pls-1:0] pl_alloc_status;
input [num_pls-1:0] pl_empty;
input clk, rst_n;
logic [num_pls-1:0] pl_alloc_status_reg;
pl_t fifo_out;
fifov_flags_t fifo_flags;
logic push;
integer i;
generate
// =============================================================
// Unrestricted PL allocation
// =============================================================
always@(posedge clk) begin
if (!rst_n) begin
for (i=0; i<num_pls; i++) begin:forpls2
pl_alloc_status_reg[i] <= 1'b1;
end
end else begin
for (i=0; i<num_pls; i++) begin:forpls
//
// PL consumed, mark PL as allocated
//
if (pl_allocated[i])
pl_alloc_status_reg[i]<=1'b0;
/*if(flits_valid[i])
$stop;
if(flits_tail[i])
$stop;*/
if (flits_valid[i] && flits_tail[i]) begin
//
// Tail flit departs, packets PL is ready to be used again
//
// what about single flit packets - test
assert (!pl_alloc_status_reg[i]);
pl_alloc_status_reg[i]<=1'b1;
end
end //for
end
end // always@ (posedge clk)
if (only_allocate_pl_when_empty) begin
assign pl_alloc_status = pl_alloc_status_reg & pl_empty;
end else begin
assign pl_alloc_status = pl_alloc_status_reg;
end
endgenerate
endmodule // LAG_pl_free_pool
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_LP_V
`define SKY130_FD_SC_LP__SDFXTP_LP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_lp (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_LP_V
|
/**
# SmallHpf2nd - 2-pole IIR High-Pass Filter #
Small 2-Pole IIR high-pass filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down
by strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired cutoff frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor.
```
s^2
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)--->(SUB)------------------------------+--> dataOut
^ ^ |
| | |
| +----[2^-K0_SHIFT]<---[ACCUM]<---/
| |
| \--------------------------------\
| |
\-------------[2^-K1_SHIFT]<---[ACCUM]<---/
```
*/
module SmallHpf2nd #(
parameter K0_SHIFT = 8, ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 8, ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16, ///< Width of data path
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous & active high
input en, ///< Filter strobe
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter input
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH-1:0] forwardPath;
wire signed [WIDTH-1:0] acc0Out;
wire signed [WIDTH-1:0] acc1Out;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + dataOut;
assign acc1In = acc1 + acc0Out;
always @(posedge clk) begin
if (rst) begin
forwardPath <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardPath <= dataIn - acc0Out - acc1Out;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign dataOut = forwardPath;
assign acc0Out = acc0 >>> K0_SHIFT;
assign acc1Out = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_SYMBOL_V
`define SKY130_FD_SC_HD__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_SYMBOL_V
|
// -*- Mode: Verilog -*-
// Filename : ram_axi4_lite.v
// Description : Simple RAM with AXI4 Lite Interface
// Author : Philip Tracton
// Created On : Fri Nov 25 22:12:00 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Nov 25 22:12:00 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module ram_axi4_lite (/*AUTOARG*/ ) ;
input wire hclk;
input wire hresetn; //Active LOW
input wire [14:0] haddr;
input wire hwrite;
input wire [3:0] hsize;
input wire [1:0] htrans;
input wire [31:0] hwdata;
input wire hsel;
output reg [31:0] hrdata;
output reg hready;
output reg hresp;
reg [31:0] memory [0:4095]; //4kx32 memory
reg [14:0] addr;
reg active;
always @(posedge hclk)
if (~hresetn) begin
addr <= 15'b0;
active <= 1'b0;
end else begin
addr <= haddr;
active <= htrans[1] & hsel;
end
reg [31:0] temp;
always @(posedge hclk)
if (~hresetn) begin
temp <= 0;
end else begin
temp <= memory[addr];
if (hwrite) begin
case (hsize)
3'b000: memory[addr] <= {temp[31:8}, hwdata[7:0]};
3'b001: memory[addr] <= {temp[31:16}, hwdata[15:0]};
3'b010: memory[addr] <= hwdata;
default: $display("SIZE ERROR @ %d", $time)
endcase
memory[addr] <= hwdata;
end
end
endmodule // ram_axi4_lite
|
// system_acl_iface_acl_kernel_interface.v
// Generated using ACDS version 14.0 200 at 2015.04.26.20:39:57
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire kernel_cntrl_waitrequest, // kernel_cntrl.waitrequest
output wire [31:0] kernel_cntrl_readdata, // .readdata
output wire kernel_cntrl_readdatavalid, // .readdatavalid
input wire [0:0] kernel_cntrl_burstcount, // .burstcount
input wire [31:0] kernel_cntrl_writedata, // .writedata
input wire [13:0] kernel_cntrl_address, // .address
input wire kernel_cntrl_write, // .write
input wire kernel_cntrl_read, // .read
input wire [3:0] kernel_cntrl_byteenable, // .byteenable
input wire kernel_cntrl_debugaccess, // .debugaccess
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
input wire [0:0] kernel_irq_from_kernel_irq, // kernel_irq_from_kernel.irq
output wire [1:0] acl_bsp_memorg_kernel_mode, // acl_bsp_memorg_kernel.mode
output wire [1:0] acl_bsp_memorg_host_mode, // acl_bsp_memorg_host.mode
input wire sw_reset_in_reset, // sw_reset_in.reset
input wire kernel_clk_clk, // kernel_clk.clk
output wire sw_reset_export_reset_n, // sw_reset_export.reset_n
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_irq_to_host_irq // kernel_irq_to_host.irq
);
wire reset_controller_sw_reset_out_reset; // reset_controller_sw:reset_out -> [irq_bridge_0:reset, kernel_cra:reset, mm_interconnect_0:kernel_cra_reset_reset_bridge_in_reset_reset, reset_controller_sw_reset_out_reset:in]
wire [0:0] address_span_extender_0_expanded_master_burstcount; // address_span_extender_0:avm_m0_burstcount -> mm_interconnect_0:address_span_extender_0_expanded_master_burstcount
wire address_span_extender_0_expanded_master_waitrequest; // mm_interconnect_0:address_span_extender_0_expanded_master_waitrequest -> address_span_extender_0:avm_m0_waitrequest
wire [31:0] address_span_extender_0_expanded_master_writedata; // address_span_extender_0:avm_m0_writedata -> mm_interconnect_0:address_span_extender_0_expanded_master_writedata
wire [29:0] address_span_extender_0_expanded_master_address; // address_span_extender_0:avm_m0_address -> mm_interconnect_0:address_span_extender_0_expanded_master_address
wire address_span_extender_0_expanded_master_write; // address_span_extender_0:avm_m0_write -> mm_interconnect_0:address_span_extender_0_expanded_master_write
wire address_span_extender_0_expanded_master_read; // address_span_extender_0:avm_m0_read -> mm_interconnect_0:address_span_extender_0_expanded_master_read
wire [31:0] address_span_extender_0_expanded_master_readdata; // mm_interconnect_0:address_span_extender_0_expanded_master_readdata -> address_span_extender_0:avm_m0_readdata
wire [3:0] address_span_extender_0_expanded_master_byteenable; // address_span_extender_0:avm_m0_byteenable -> mm_interconnect_0:address_span_extender_0_expanded_master_byteenable
wire address_span_extender_0_expanded_master_readdatavalid; // mm_interconnect_0:address_span_extender_0_expanded_master_readdatavalid -> address_span_extender_0:avm_m0_readdatavalid
wire mm_interconnect_0_kernel_cra_s0_waitrequest; // kernel_cra:s0_waitrequest -> mm_interconnect_0:kernel_cra_s0_waitrequest
wire [0:0] mm_interconnect_0_kernel_cra_s0_burstcount; // mm_interconnect_0:kernel_cra_s0_burstcount -> kernel_cra:s0_burstcount
wire [63:0] mm_interconnect_0_kernel_cra_s0_writedata; // mm_interconnect_0:kernel_cra_s0_writedata -> kernel_cra:s0_writedata
wire [29:0] mm_interconnect_0_kernel_cra_s0_address; // mm_interconnect_0:kernel_cra_s0_address -> kernel_cra:s0_address
wire mm_interconnect_0_kernel_cra_s0_write; // mm_interconnect_0:kernel_cra_s0_write -> kernel_cra:s0_write
wire mm_interconnect_0_kernel_cra_s0_read; // mm_interconnect_0:kernel_cra_s0_read -> kernel_cra:s0_read
wire [63:0] mm_interconnect_0_kernel_cra_s0_readdata; // kernel_cra:s0_readdata -> mm_interconnect_0:kernel_cra_s0_readdata
wire mm_interconnect_0_kernel_cra_s0_debugaccess; // mm_interconnect_0:kernel_cra_s0_debugaccess -> kernel_cra:s0_debugaccess
wire mm_interconnect_0_kernel_cra_s0_readdatavalid; // kernel_cra:s0_readdatavalid -> mm_interconnect_0:kernel_cra_s0_readdatavalid
wire [7:0] mm_interconnect_0_kernel_cra_s0_byteenable; // mm_interconnect_0:kernel_cra_s0_byteenable -> kernel_cra:s0_byteenable
wire [0:0] kernel_cntrl_m0_burstcount; // kernel_cntrl:m0_burstcount -> mm_interconnect_1:kernel_cntrl_m0_burstcount
wire kernel_cntrl_m0_waitrequest; // mm_interconnect_1:kernel_cntrl_m0_waitrequest -> kernel_cntrl:m0_waitrequest
wire [13:0] kernel_cntrl_m0_address; // kernel_cntrl:m0_address -> mm_interconnect_1:kernel_cntrl_m0_address
wire [31:0] kernel_cntrl_m0_writedata; // kernel_cntrl:m0_writedata -> mm_interconnect_1:kernel_cntrl_m0_writedata
wire kernel_cntrl_m0_write; // kernel_cntrl:m0_write -> mm_interconnect_1:kernel_cntrl_m0_write
wire kernel_cntrl_m0_read; // kernel_cntrl:m0_read -> mm_interconnect_1:kernel_cntrl_m0_read
wire [31:0] kernel_cntrl_m0_readdata; // mm_interconnect_1:kernel_cntrl_m0_readdata -> kernel_cntrl:m0_readdata
wire kernel_cntrl_m0_debugaccess; // kernel_cntrl:m0_debugaccess -> mm_interconnect_1:kernel_cntrl_m0_debugaccess
wire [3:0] kernel_cntrl_m0_byteenable; // kernel_cntrl:m0_byteenable -> mm_interconnect_1:kernel_cntrl_m0_byteenable
wire kernel_cntrl_m0_readdatavalid; // mm_interconnect_1:kernel_cntrl_m0_readdatavalid -> kernel_cntrl:m0_readdatavalid
wire mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest; // address_span_extender_0:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_0_windowed_slave_waitrequest
wire [0:0] mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_0_windowed_slave_burstcount -> address_span_extender_0:avs_s0_burstcount
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_0_windowed_slave_writedata -> address_span_extender_0:avs_s0_writedata
wire [9:0] mm_interconnect_1_address_span_extender_0_windowed_slave_address; // mm_interconnect_1:address_span_extender_0_windowed_slave_address -> address_span_extender_0:avs_s0_address
wire mm_interconnect_1_address_span_extender_0_windowed_slave_write; // mm_interconnect_1:address_span_extender_0_windowed_slave_write -> address_span_extender_0:avs_s0_write
wire mm_interconnect_1_address_span_extender_0_windowed_slave_read; // mm_interconnect_1:address_span_extender_0_windowed_slave_read -> address_span_extender_0:avs_s0_read
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_readdata; // address_span_extender_0:avs_s0_readdata -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid; // address_span_extender_0:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdatavalid
wire [3:0] mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_0_windowed_slave_byteenable -> address_span_extender_0:avs_s0_byteenable
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_writedata; // mm_interconnect_1:address_span_extender_0_cntl_writedata -> address_span_extender_0:avs_cntl_writedata
wire mm_interconnect_1_address_span_extender_0_cntl_write; // mm_interconnect_1:address_span_extender_0_cntl_write -> address_span_extender_0:avs_cntl_write
wire mm_interconnect_1_address_span_extender_0_cntl_read; // mm_interconnect_1:address_span_extender_0_cntl_read -> address_span_extender_0:avs_cntl_read
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_readdata; // address_span_extender_0:avs_cntl_readdata -> mm_interconnect_1:address_span_extender_0_cntl_readdata
wire [7:0] mm_interconnect_1_address_span_extender_0_cntl_byteenable; // mm_interconnect_1:address_span_extender_0_cntl_byteenable -> address_span_extender_0:avs_cntl_byteenable
wire [63:0] mm_interconnect_1_sys_description_rom_s1_writedata; // mm_interconnect_1:sys_description_rom_s1_writedata -> sys_description_rom:writedata
wire [8:0] mm_interconnect_1_sys_description_rom_s1_address; // mm_interconnect_1:sys_description_rom_s1_address -> sys_description_rom:address
wire mm_interconnect_1_sys_description_rom_s1_chipselect; // mm_interconnect_1:sys_description_rom_s1_chipselect -> sys_description_rom:chipselect
wire mm_interconnect_1_sys_description_rom_s1_clken; // mm_interconnect_1:sys_description_rom_s1_clken -> sys_description_rom:clken
wire mm_interconnect_1_sys_description_rom_s1_write; // mm_interconnect_1:sys_description_rom_s1_write -> sys_description_rom:write
wire [63:0] mm_interconnect_1_sys_description_rom_s1_readdata; // sys_description_rom:readdata -> mm_interconnect_1:sys_description_rom_s1_readdata
wire mm_interconnect_1_sys_description_rom_s1_debugaccess; // mm_interconnect_1:sys_description_rom_s1_debugaccess -> sys_description_rom:debugaccess
wire [7:0] mm_interconnect_1_sys_description_rom_s1_byteenable; // mm_interconnect_1:sys_description_rom_s1_byteenable -> sys_description_rom:byteenable
wire mm_interconnect_1_sw_reset_s_waitrequest; // sw_reset:slave_waitrequest -> mm_interconnect_1:sw_reset_s_waitrequest
wire [63:0] mm_interconnect_1_sw_reset_s_writedata; // mm_interconnect_1:sw_reset_s_writedata -> sw_reset:slave_writedata
wire mm_interconnect_1_sw_reset_s_write; // mm_interconnect_1:sw_reset_s_write -> sw_reset:slave_write
wire mm_interconnect_1_sw_reset_s_read; // mm_interconnect_1:sw_reset_s_read -> sw_reset:slave_read
wire [63:0] mm_interconnect_1_sw_reset_s_readdata; // sw_reset:slave_readdata -> mm_interconnect_1:sw_reset_s_readdata
wire [7:0] mm_interconnect_1_sw_reset_s_byteenable; // mm_interconnect_1:sw_reset_s_byteenable -> sw_reset:slave_byteenable
wire mm_interconnect_1_mem_org_mode_s_waitrequest; // mem_org_mode:slave_waitrequest -> mm_interconnect_1:mem_org_mode_s_waitrequest
wire [31:0] mm_interconnect_1_mem_org_mode_s_writedata; // mm_interconnect_1:mem_org_mode_s_writedata -> mem_org_mode:slave_writedata
wire mm_interconnect_1_mem_org_mode_s_write; // mm_interconnect_1:mem_org_mode_s_write -> mem_org_mode:slave_write
wire mm_interconnect_1_mem_org_mode_s_read; // mm_interconnect_1:mem_org_mode_s_read -> mem_org_mode:slave_read
wire [31:0] mm_interconnect_1_mem_org_mode_s_readdata; // mem_org_mode:slave_readdata -> mm_interconnect_1:mem_org_mode_s_readdata
wire mm_interconnect_1_version_id_0_s_read; // mm_interconnect_1:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_1_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_1:version_id_0_s_readdata
wire mm_interconnect_1_irq_ena_0_s_waitrequest; // irq_ena_0:slave_waitrequest -> mm_interconnect_1:irq_ena_0_s_waitrequest
wire [31:0] mm_interconnect_1_irq_ena_0_s_writedata; // mm_interconnect_1:irq_ena_0_s_writedata -> irq_ena_0:slave_writedata
wire mm_interconnect_1_irq_ena_0_s_write; // mm_interconnect_1:irq_ena_0_s_write -> irq_ena_0:slave_write
wire mm_interconnect_1_irq_ena_0_s_read; // mm_interconnect_1:irq_ena_0_s_read -> irq_ena_0:slave_read
wire [31:0] mm_interconnect_1_irq_ena_0_s_readdata; // irq_ena_0:slave_readdata -> mm_interconnect_1:irq_ena_0_s_readdata
wire [3:0] mm_interconnect_1_irq_ena_0_s_byteenable; // mm_interconnect_1:irq_ena_0_s_byteenable -> irq_ena_0:slave_byteenable
wire irq_mapper_receiver0_irq; // irq_bridge_0:sender0_irq -> irq_mapper:receiver0_irq
wire irq_ena_0_my_irq_in_irq; // irq_mapper:sender_irq -> irq_ena_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_ena_0:resetn, kernel_cntrl:reset, mem_org_mode:resetn, mm_interconnect_1:kernel_cntrl_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sys_description_rom:reset, version_id_0:resetn]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [rst_translator:reset_req_in, sys_description_rom:reset_req]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_0:reset, mm_interconnect_0:address_span_extender_0_reset_reset_bridge_in_reset_reset, mm_interconnect_1:address_span_extender_0_reset_reset_bridge_in_reset_reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_1:sw_reset_clk_reset_reset_bridge_in_reset_reset, sw_reset:resetn]
system_acl_iface_acl_kernel_interface_sys_description_rom sys_description_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_1_sys_description_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (64),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cra (
.clk (kernel_clk_clk), // clk.clk
.reset (reset_controller_sw_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_kernel_cra_s0_address), // .address
.s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cra_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cra_readdata), // .readdata
.m0_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cra_burstcount), // .burstcount
.m0_writedata (kernel_cra_writedata), // .writedata
.m0_address (kernel_cra_address), // .address
.m0_write (kernel_cra_write), // .write
.m0_read (kernel_cra_read), // .read
.m0_byteenable (kernel_cra_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_debugaccess) // .debugaccess
);
altera_address_span_extender #(
.DATA_WIDTH (32),
.BYTEENABLE_WIDTH (4),
.MASTER_ADDRESS_WIDTH (30),
.SLAVE_ADDRESS_WIDTH (10),
.SLAVE_ADDRESS_SHIFT (2),
.BURSTCOUNT_WIDTH (1),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_0 (
.clk (kernel_clk_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_0_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_0_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_0_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.avs_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // cntl.read
.avs_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.avs_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // .write
.avs_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.avs_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.avs_cntl_address (1'b0) // (terminated)
);
sw_reset #(
.WIDTH (64),
.LOG2_RESET_CYCLES (10)
) sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (sw_reset_export_reset_n) // sw_reset.reset_n
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (14),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cntrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (kernel_cntrl_waitrequest), // s0.waitrequest
.s0_readdata (kernel_cntrl_readdata), // .readdata
.s0_readdatavalid (kernel_cntrl_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_cntrl_burstcount), // .burstcount
.s0_writedata (kernel_cntrl_writedata), // .writedata
.s0_address (kernel_cntrl_address), // .address
.s0_write (kernel_cntrl_write), // .write
.s0_read (kernel_cntrl_read), // .read
.s0_byteenable (kernel_cntrl_byteenable), // .byteenable
.s0_debugaccess (kernel_cntrl_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cntrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.m0_address (kernel_cntrl_m0_address), // .address
.m0_write (kernel_cntrl_m0_write), // .write
.m0_read (kernel_cntrl_m0_read), // .read
.m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cntrl_m0_debugaccess) // .debugaccess
);
mem_org_mode #(
.WIDTH (32)
) mem_org_mode (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_mem_org_mode_s_write), // s.write
.slave_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.slave_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.slave_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.mem_organization_kernel (acl_bsp_memorg_kernel_mode), // mem_organization_kernel.mode
.mem_organization_host (acl_bsp_memorg_host_mode) // mem_organization_host.mode
);
altera_irq_bridge #(
.IRQ_WIDTH (1)
) irq_bridge_0 (
.clk (kernel_clk_clk), // clk.clk
.receiver_irq (kernel_irq_from_kernel_irq), // receiver_irq.irq
.reset (reset_controller_sw_reset_out_reset), // clk_reset.reset
.sender0_irq (irq_mapper_receiver0_irq), // sender0_irq.irq
.sender1_irq (), // (terminated)
.sender2_irq (), // (terminated)
.sender3_irq (), // (terminated)
.sender4_irq (), // (terminated)
.sender5_irq (), // (terminated)
.sender6_irq (), // (terminated)
.sender7_irq (), // (terminated)
.sender8_irq (), // (terminated)
.sender9_irq (), // (terminated)
.sender10_irq (), // (terminated)
.sender11_irq (), // (terminated)
.sender12_irq (), // (terminated)
.sender13_irq (), // (terminated)
.sender14_irq (), // (terminated)
.sender15_irq (), // (terminated)
.sender16_irq (), // (terminated)
.sender17_irq (), // (terminated)
.sender18_irq (), // (terminated)
.sender19_irq (), // (terminated)
.sender20_irq (), // (terminated)
.sender21_irq (), // (terminated)
.sender22_irq (), // (terminated)
.sender23_irq (), // (terminated)
.sender24_irq (), // (terminated)
.sender25_irq (), // (terminated)
.sender26_irq (), // (terminated)
.sender27_irq (), // (terminated)
.sender28_irq (), // (terminated)
.sender29_irq (), // (terminated)
.sender30_irq (), // (terminated)
.sender31_irq () // (terminated)
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_1_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_sw (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~sw_reset_export_reset_n), // reset_in1.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (reset_controller_sw_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
irq_ena irq_ena_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_irq_ena_0_s_write), // s.write
.slave_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.slave_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.irq (irq_ena_0_my_irq_in_irq), // my_irq_in.irq
.irq_out (kernel_irq_to_host_irq) // my_irq_out.irq
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0 mm_interconnect_0 (
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cra_reset_reset_bridge_in_reset_reset (reset_controller_sw_reset_out_reset), // kernel_cra_reset_reset_bridge_in_reset.reset
.address_span_extender_0_expanded_master_address (address_span_extender_0_expanded_master_address), // address_span_extender_0_expanded_master.address
.address_span_extender_0_expanded_master_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.address_span_extender_0_expanded_master_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.address_span_extender_0_expanded_master_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.address_span_extender_0_expanded_master_read (address_span_extender_0_expanded_master_read), // .read
.address_span_extender_0_expanded_master_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.address_span_extender_0_expanded_master_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_0_expanded_master_write (address_span_extender_0_expanded_master_write), // .write
.address_span_extender_0_expanded_master_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.kernel_cra_s0_address (mm_interconnect_0_kernel_cra_s0_address), // kernel_cra_s0.address
.kernel_cra_s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.kernel_cra_s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.kernel_cra_s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.kernel_cra_s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.kernel_cra_s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.kernel_cra_s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.kernel_cra_s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.kernel_cra_s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // .waitrequest
.kernel_cra_s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess) // .debugaccess
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1 mm_interconnect_1 (
.clk_reset_clk_clk (clk_clk), // clk_reset_clk.clk
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cntrl_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // kernel_cntrl_reset_reset_bridge_in_reset.reset
.sw_reset_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sw_reset_clk_reset_reset_bridge_in_reset.reset
.kernel_cntrl_m0_address (kernel_cntrl_m0_address), // kernel_cntrl_m0.address
.kernel_cntrl_m0_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.kernel_cntrl_m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.kernel_cntrl_m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.kernel_cntrl_m0_read (kernel_cntrl_m0_read), // .read
.kernel_cntrl_m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.kernel_cntrl_m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.kernel_cntrl_m0_write (kernel_cntrl_m0_write), // .write
.kernel_cntrl_m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.kernel_cntrl_m0_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.address_span_extender_0_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // address_span_extender_0_cntl.write
.address_span_extender_0_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // .read
.address_span_extender_0_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.address_span_extender_0_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.address_span_extender_0_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // address_span_extender_0_windowed_slave.address
.address_span_extender_0_windowed_slave_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.address_span_extender_0_windowed_slave_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.address_span_extender_0_windowed_slave_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.address_span_extender_0_windowed_slave_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.address_span_extender_0_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.address_span_extender_0_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_0_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.irq_ena_0_s_write (mm_interconnect_1_irq_ena_0_s_write), // irq_ena_0_s.write
.irq_ena_0_s_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.irq_ena_0_s_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.irq_ena_0_s_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.irq_ena_0_s_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.irq_ena_0_s_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.mem_org_mode_s_write (mm_interconnect_1_mem_org_mode_s_write), // mem_org_mode_s.write
.mem_org_mode_s_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.mem_org_mode_s_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.mem_org_mode_s_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.mem_org_mode_s_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.sw_reset_s_write (mm_interconnect_1_sw_reset_s_write), // sw_reset_s.write
.sw_reset_s_read (mm_interconnect_1_sw_reset_s_read), // .read
.sw_reset_s_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.sw_reset_s_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.sw_reset_s_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.sw_reset_s_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sys_description_rom_s1_address (mm_interconnect_1_sys_description_rom_s1_address), // sys_description_rom_s1.address
.sys_description_rom_s1_write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.sys_description_rom_s1_readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.sys_description_rom_s1_writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.sys_description_rom_s1_byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.sys_description_rom_s1_chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.sys_description_rom_s1_clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.sys_description_rom_s1_debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.version_id_0_s_read (mm_interconnect_1_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (irq_ena_0_my_irq_in_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (sw_reset_in_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_reset_reset_n = ~reset_controller_sw_reset_out_reset;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_streaming #(
parameter PURPOSE = 0,
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// JTAG Signals
input wire tck,
input wire tdi,
output reg tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire reset_n,
// Source Signals
output wire [7:0] source_data,
output wire source_valid,
// Sink Signals
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
// Clock Debug Signals
input wire clock_to_sample,
input wire reset_to_sample,
// Resetrequest signal
output reg resetrequest,
// Debug reset and management channel
output wire debug_reset,
output reg mgmt_valid,
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output reg mgmt_data
);
// function to calculate log2, floored.
function integer flog2;
input [31:0] Depth;
integer i;
begin
i = Depth;
if ( i <= 0 ) flog2 = 0;
else begin
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// IR values determine the operating modes
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
// Operating Modes:
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
// Loopback - To become a JTAG loopback with a bypass register
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
// Control - To set the offset of bit-padding and to do a reset request
// Mgmt - Send management commands (resets mostly) to agents
localparam IRWIDTH = 3;
// State machine encoding for write_state
localparam ST_BYPASS = 'h0;
localparam ST_HEADER_1 = 'h1;
localparam ST_HEADER_2 = 'h2;
localparam ST_WRITE_DATA = 'h3;
// State machine encoding for read_state
localparam ST_HEADER = 'h0;
localparam ST_PADDED = 'h1;
localparam ST_READ_DATA = 'h2;
reg [1:0] write_state = ST_BYPASS;
reg [1:0] read_state = ST_HEADER;
reg [ 7:0] dr_data_in = 'b0;
reg [ 7:0] dr_data_out = 'b0;
reg dr_loopback = 'b0;
reg [ 2:0] dr_debug = 'b0;
reg [10:0] dr_info = 'b0;
reg [ 8:0] dr_control = 'b0;
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
reg [ 8:0] padded_bit_counter = 'b0;
reg [ 7:0] bypass_bit_counter = 'b0;
reg [ 2:0] write_data_bit_counter = 'b0;
reg [ 2:0] read_data_bit_counter = 'b0;
reg [ 3:0] header_in_bit_counter = 'b0;
reg [ 3:0] header_out_bit_counter = 'b0;
reg [18:0] scan_length_byte_counter = 'b0;
reg [18:0] valid_write_data_length_byte_counter = 'b0;
reg write_data_valid = 'b0;
reg read_data_valid = 'b0;
reg read_data_all_valid = 'b0;
reg decode_header_1 = 'b0;
reg decode_header_2 = 'b0;
wire write_data_byte_aligned;
wire read_data_byte_aligned;
wire padded_bit_byte_aligned;
wire bytestream_end;
assign write_data_byte_aligned = (write_data_bit_counter == 1);
assign read_data_byte_aligned = (read_data_bit_counter == 1);
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
assign bytestream_end = (scan_length_byte_counter == 'b0);
reg [ 7:0] offset = 'b0;
reg [15:0] header_in = 'b0;
reg [9:0] scan_length = 'b0;
reg [2:0] read_data_length = 'b0;
reg [2:0] write_data_length = 'b0;
wire [7:0] idle_inserter_sink_data;
wire idle_inserter_sink_valid;
wire idle_inserter_sink_ready;
wire [7:0] idle_inserter_source_data;
reg idle_inserter_source_ready = 'b0;
reg [7:0] idle_remover_sink_data = 'b0;
reg idle_remover_sink_valid = 'b0;
wire [7:0] idle_remover_source_data;
wire idle_remover_source_valid;
assign source_data = idle_remover_source_data;
assign source_valid = idle_remover_source_valid;
assign sink_ready = idle_inserter_sink_ready;
assign idle_inserter_sink_data = sink_data;
assign idle_inserter_sink_valid = sink_valid;
reg clock_sensor = 'b0;
reg clock_to_sample_div2 = 'b0;
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
wire data_available;
assign data_available = sink_valid;
wire [18:0] decoded_scan_length;
wire [18:0] decoded_write_data_length;
wire [18:0] decoded_read_data_length;
assign decoded_scan_length = { scan_length, {8{1'b1}} };
// +-------------------+----------------+---------------------+
// | scan_length | Length (bytes) | decoded_scan_length |
// +-------------------+----------------+---------------------+
// | 0x0 | 256 | 0x0ff (255) |
// | 0x1 | 512 | 0x1ff (511) |
// | 0x2 | 768 | 0x2ff (767) |
// | . | . | . |
// | 0x3ff | 256k | 0x3ff (256k-1) |
// +-------------------+----------------+---------------------+
// TODO: use look up table to save LEs?
// Decoded value is correct except for 0x7
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
// +-------------------+---------------+---------------------------+
// | read_data_length | Length | decoded_read_data_length |
// | write_data_length | (bytes) | decoded_write_data_length |
// +-------------------+---------------+---------------------------+
// | 0x0 | 0 | 0x0000 (0) |
// | 0x1 | 256 | 0x0100 (256) |
// | 0x2 | 512 | 0x0200 (512) |
// | 0x3 | 1k | 0x0400 (1024) |
// | 0x4 | 2k | 0x0800 (2048) |
// | 0x5 | 4k | 0x1000 (4096) |
// | 0x6 | 8k | 0x2000 (8192) |
// | 0x7 | scan_length | invalid |
// +-------------------+---------------+---------------------------+
wire clock_sensor_sync;
wire reset_to_sample_sync;
wire clock_to_sample_div2_sync;
wire clock_sense_reset_n_sync;
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_sensor),
.dout(clock_sensor_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(reset_to_sample),
.dout(reset_to_sample_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_to_sample_div2),
.dout(clock_to_sample_div2_sync));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
.clk(clock_to_sample),
.reset_n(clock_sense_reset_n),
.din(1'b1),
.dout(clock_sense_reset_n_sync));
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
if (~clock_sense_reset_n_sync) begin
clock_sensor <= 1'b0;
end else begin
clock_sensor <= 1'b1;
end
end
always @ (posedge clock_to_sample) begin
clock_to_sample_div2 <= ~clock_to_sample_div2;
end
always @ (posedge tck) begin
idle_remover_sink_valid <= 1'b0;
idle_inserter_source_ready <= 1'b0;
// Data mode sourcing (write)
// offset(rounded 8) m-i i 16 offset
// +------------+-----------+------------------+--------+------------+
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
// +------------+-----------+------------------+--------+------------+
// Data mode DR data stream write format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
if (offset == 'b0) begin
write_state <= ST_HEADER_1;
end else begin
write_state <= ST_BYPASS;
end
// 8-bit bypass_bit_counter
bypass_bit_counter <= offset;
// 4-bit header_in_bit_counter
header_in_bit_counter <= 15;
// 3-bit write_data_bit_counter
write_data_bit_counter <= 0;
// Reset the registers
// TODO: not necessarily all, reduce LE
decode_header_1 <= 1'b0;
decode_header_2 <= 1'b0;
read_data_all_valid <= 1'b0;
valid_write_data_length_byte_counter <= 0;
end
if (virtual_state_sdr) begin
// Discard bypass bits, then decode the 16-bit header
// 3 3 10
// +-------------------+------------------+-------------+
// | write_data_length | read_data_length | scan_length |
// +-------------------+------------------+-------------+
// Header format
case (write_state)
ST_BYPASS: begin
// Discard the bypass bit
bypass_bit_counter <= bypass_bit_counter - 1'b1;
if (bypass_bit_counter == 1) begin
write_state <= ST_HEADER_1;
end
end
// Shift the scan_length and read_data_length
ST_HEADER_1: begin
// TODO: header_in can be shorter
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
if (header_in_bit_counter == 3) begin
read_data_length <= {tdi, header_in[15:14]};
scan_length <= header_in[13:4];
write_state <= ST_HEADER_2;
decode_header_1 <= 1'b1;
end
end
// Shift the write_data_length
ST_HEADER_2: begin
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
// Decode read_data_length and scan_length
if (decode_header_1) begin
decode_header_1 <= 1'b0;
// Set read_data_all_valid
if (read_data_length == 3'b111) begin
read_data_all_valid <= 1'b1;
end
// Load scan_length_byte_counter
scan_length_byte_counter <= decoded_scan_length;
end
if (header_in_bit_counter == 0) begin
write_data_length <= {tdi, header_in[15:14]};
write_state <= ST_WRITE_DATA;
decode_header_2 <= 1'b1;
end
end
// Shift the valid_write_data
ST_WRITE_DATA: begin
// Shift into dr_data_in
dr_data_in <= {tdi, dr_data_in[7:1]};
// Decode write_data_length
if (decode_header_2) begin
decode_header_2 <= 1'b0;
// Load valid_write_data_length_byte_counter
case (write_data_length)
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
3'b000: valid_write_data_length_byte_counter <= 'b0;
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
endcase
end
write_data_bit_counter <= write_data_bit_counter - 1'b1;
write_data_valid <= (valid_write_data_length_byte_counter != 0);
// Feed the data to the idle remover
if (write_data_byte_aligned && write_data_valid) begin
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
idle_remover_sink_valid <= 1'b1;
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
end
end
endcase
end
end
// Data mode sinking (read)
// i m-i offset(rounded 8) 16
// +-----------------+-----------+------------+--------+
// | valid_read_data | undefined | padded_bit | header | -> tdo
// +-----------------+-----------+------------+--------+
// Data mode DR data stream read format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
read_state <= ST_HEADER;
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
// 9-bit padded_bit_counter
if (|offset[2:0]) begin
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
padded_bit_counter[2:0] <= 3'b0;
end else begin
padded_bit_counter <= {1'b0, offset};
end
// 4-bit header_out_bit_counter
header_out_bit_counter <= 0;
// 3-bit read_data_bit_counter
read_data_bit_counter <= 0;
// Load the data_available bit into header
dr_data_out <= {{7{1'b0}}, data_available};
read_data_valid <= 0;
end
if (virtual_state_sdr) begin
// 10 1
// +-----------------------------------+----------------+
// | reserved | data_available |
// +-----------------------------------+----------------+
// Header format
dr_data_out <= {1'b0, dr_data_out[7:1]};
case (read_state)
// Shift the scan_length and read_data_length
ST_HEADER: begin
header_out_bit_counter <= header_out_bit_counter - 1'b1;
// Retrieve data from idle inserter for the next shift if no paddded bits
if (header_out_bit_counter == 2) begin
if (padded_bit_counter == 0) begin
idle_inserter_source_ready <= read_data_all_valid;
end
end
if (header_out_bit_counter == 1) begin
if (padded_bit_counter == 0) begin
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end else begin
read_state <= ST_PADDED;
padded_bit_counter <= padded_bit_counter - 1'b1;
idle_inserter_source_ready <= 1'b0;
dr_data_out <= 8'h4a;
end
end
end
ST_PADDED: begin
padded_bit_counter <= padded_bit_counter - 1'b1;
if (padded_bit_byte_aligned) begin
// Load idle character into data register
dr_data_out <= 8'h4a;
end
// Retrieve data from idle inserter for the next shift when padded bits finish
if (padded_bit_counter == 1) begin
idle_inserter_source_ready <= read_data_all_valid;
end
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end
end
ST_READ_DATA: begin
read_data_bit_counter <= read_data_bit_counter - 1'b1;
// Retrieve data from idle inserter just before read_data_byte_aligned
if (read_data_bit_counter == 2) begin
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
end
if (read_data_byte_aligned) begin
// Note that bytestream_end is driven by scan_length_byte_counter
if (~bytestream_end) begin
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
end
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
// Load idle character if bytestream has ended, else get data from the idle inserter
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
end
end
endcase
end
end
// Loopback mode
if (ir_in == LOOPBACK) begin
if (virtual_state_cdr) begin
dr_loopback <= 1'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_loopback
dr_loopback <= tdi;
end
end
// Debug mode
if (ir_in == DEBUG) begin
if (virtual_state_cdr) begin
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
end
if (virtual_state_udr) begin
clock_sense_reset_n <= 1'b0;
end else begin
clock_sense_reset_n <= 1'b1;
end
end
// Info mode
if (ir_in == INFO) begin
if (virtual_state_cdr) begin
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
end
if (virtual_state_sdr) begin
// Shift dr_info
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
end
end
// Control mode
if (ir_in == CONTROL) begin
if (virtual_state_cdr) begin
dr_control <= 'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_control
dr_control <= {tdi, dr_control[8:1]};
end
if (virtual_state_udr) begin
// Update resetrequest and offset
{resetrequest, offset} <= dr_control;
end
end
end
always @ * begin
if (virtual_state_sdr) begin
case (ir_in)
DATA: tdo <= dr_data_out[0];
LOOPBACK: tdo <= dr_loopback;
DEBUG: tdo <= dr_debug[0];
INFO: tdo <= dr_info[0];
CONTROL: tdo <= dr_control[0];
MGMT: tdo <= dr_mgmt[0];
default: tdo <= 1'b0;
endcase
end else begin
tdo <= 1'b0;
end
end
// Idle Remover
altera_avalon_st_idle_remover idle_remover (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (), // left disconnected
.in_valid (idle_remover_sink_valid),
.in_data (idle_remover_sink_data),
// Interface: ST out
.out_ready (1'b1), // downstream is expected to be always ready
.out_valid (idle_remover_source_valid),
.out_data (idle_remover_source_data)
);
// Idle Inserter
altera_avalon_st_idle_inserter idle_inserter (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (idle_inserter_sink_ready),
.in_valid (idle_inserter_sink_valid),
.in_data (idle_inserter_sink_data),
// Interface: ST out
.out_ready (idle_inserter_source_ready),
.out_valid (),
.out_data (idle_inserter_source_data)
);
generate
if (MGMT_CHANNEL_WIDTH > 0)
begin : has_mgmt
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
reg mgmt_toggle = 1'b0;
wire mgmt_toggle_sync;
reg mgmt_toggle_prev;
always @ (posedge tck) begin
// Debug mode
if (ir_in == MGMT) begin
if (virtual_state_cdr) begin
dr_mgmt <= 'b0;
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
end
if (virtual_state_udr) begin
mgmt_out <= dr_mgmt;
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
end
end
end
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
.dout(debug_reset));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_toggle),
.dout(mgmt_toggle_sync));
always @ (posedge clock_to_sample or posedge debug_reset) begin
if (debug_reset) begin
mgmt_valid <= 1'b0;
mgmt_toggle_prev <= 1'b0;
end else begin
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
mgmt_valid <= 1'b1;
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
mgmt_data <= mgmt_out[0];
end else begin
mgmt_valid <= 1'b0;
end
mgmt_toggle_prev <= mgmt_toggle_sync;
end
end
end
else
begin : no_mgmt
always @ (posedge tck) begin
dr_mgmt[0] <= 1'b0;
end
assign debug_reset = 1'b0;
always @ (posedge clock_to_sample) begin
mgmt_valid <= 1'b0;
mgmt_data <= 'b0;
mgmt_channel <= 'b0;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:41:02 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_sim_netlist.v
// Design : zqynq_lab_1_design_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter
(S_AXI_ARREADY,
aa_mi_arvalid,
\gen_axi.s_axi_rid_i_reg[11] ,
Q,
s_axi_rlast_i0,
\m_axi_arqos[15] ,
ADDRESS_HIT_0,
match,
D,
\gen_master_slots[0].r_issuing_cnt_reg[3] ,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\gen_master_slots[3].r_issuing_cnt_reg[27] ,
\gen_master_slots[2].r_issuing_cnt_reg[19] ,
m_axi_arvalid,
p_93_in,
p_39_in,
p_57_in,
p_75_in,
\gen_master_slots[4].r_issuing_cnt_reg[32] ,
E,
aclk,
SR,
mi_arready_4,
p_23_in,
read_cs__0,
\s_axi_arqos[3] ,
r_issuing_cnt,
r_cmd_pop_0__1,
m_axi_arready,
r_cmd_pop_1__1,
r_cmd_pop_3__1,
r_cmd_pop_2__1,
m_valid_i,
r_cmd_pop_4__1,
\s_axi_araddr[24] );
output [0:0]S_AXI_ARREADY;
output aa_mi_arvalid;
output [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
output [0:0]Q;
output s_axi_rlast_i0;
output [68:0]\m_axi_arqos[15] ;
output ADDRESS_HIT_0;
output match;
output [2:0]D;
output [2:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
output [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
output [2:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
output [2:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
output [3:0]m_axi_arvalid;
output p_93_in;
output p_39_in;
output p_57_in;
output p_75_in;
output \gen_master_slots[4].r_issuing_cnt_reg[32] ;
input [0:0]E;
input aclk;
input [0:0]SR;
input mi_arready_4;
input p_23_in;
input read_cs__0;
input [68:0]\s_axi_arqos[3] ;
input [16:0]r_issuing_cnt;
input r_cmd_pop_0__1;
input [3:0]m_axi_arready;
input r_cmd_pop_1__1;
input r_cmd_pop_3__1;
input r_cmd_pop_2__1;
input m_valid_i;
input r_cmd_pop_4__1;
input [0:0]\s_axi_araddr[24] ;
wire ADDRESS_HIT_0;
wire [2:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire [0:0]S_AXI_ARREADY;
wire [3:0]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire aclk;
wire [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_axi.s_axi_rlast_i_i_5_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ;
wire [2:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ;
wire [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0 ;
wire [2:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
wire \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0 ;
wire [2:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
wire \gen_master_slots[4].r_issuing_cnt_reg[32] ;
wire \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_3_n_0 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ;
wire [68:0]\m_axi_arqos[15] ;
wire [3:0]m_axi_arready;
wire [3:0]m_axi_arvalid;
wire m_valid_i;
wire match;
wire mi_arready_4;
wire p_23_in;
wire p_39_in;
wire p_57_in;
wire p_75_in;
wire p_93_in;
wire r_cmd_pop_0__1;
wire r_cmd_pop_1__1;
wire r_cmd_pop_2__1;
wire r_cmd_pop_3__1;
wire r_cmd_pop_4__1;
wire [16:0]r_issuing_cnt;
wire read_cs__0;
wire [0:0]\s_axi_araddr[24] ;
wire [68:0]\s_axi_arqos[3] ;
wire s_axi_rlast_i0;
wire s_ready_i2;
wire [0:0]st_aa_artarget_hot;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0080))
\gen_axi.s_axi_rid_i[11]_i_1
(.I0(Q),
.I1(aa_mi_arvalid),
.I2(mi_arready_4),
.I3(p_23_in),
.O(\gen_axi.s_axi_rid_i_reg[11] ));
LUT5 #(
.INIT(32'h55035500))
\gen_axi.s_axi_rlast_i_i_2
(.I0(read_cs__0),
.I1(\m_axi_arqos[15] [45]),
.I2(\m_axi_arqos[15] [44]),
.I3(p_23_in),
.I4(\gen_axi.s_axi_rlast_i_i_5_n_0 ),
.O(s_axi_rlast_i0));
LUT6 #(
.INIT(64'h0000000000000001))
\gen_axi.s_axi_rlast_i_i_5
(.I0(\m_axi_arqos[15] [46]),
.I1(\m_axi_arqos[15] [47]),
.I2(\m_axi_arqos[15] [48]),
.I3(\m_axi_arqos[15] [49]),
.I4(\m_axi_arqos[15] [51]),
.I5(\m_axi_arqos[15] [50]),
.O(\gen_axi.s_axi_rlast_i_i_5_n_0 ));
LUT6 #(
.INIT(64'h9AAAAAAA65555555))
\gen_master_slots[0].r_issuing_cnt[1]_i_1
(.I0(r_issuing_cnt[0]),
.I1(r_cmd_pop_0__1),
.I2(m_axi_arready[0]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[0]),
.I5(r_issuing_cnt[1]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h69))
\gen_master_slots[0].r_issuing_cnt[2]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I1(r_issuing_cnt[1]),
.I2(r_issuing_cnt[2]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h78E1))
\gen_master_slots[0].r_issuing_cnt[3]_i_2
(.I0(r_issuing_cnt[1]),
.I1(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I2(r_issuing_cnt[3]),
.I3(r_issuing_cnt[2]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[3] [2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[0].r_issuing_cnt[3]_i_4
(.I0(m_axi_arready[0]),
.I1(aa_mi_arvalid),
.I2(aa_mi_artarget_hot[0]),
.O(p_93_in));
LUT6 #(
.INIT(64'h20000000BAAAAAAA))
\gen_master_slots[0].r_issuing_cnt[3]_i_5
(.I0(r_issuing_cnt[0]),
.I1(r_cmd_pop_0__1),
.I2(m_axi_arready[0]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[0]),
.I5(r_issuing_cnt[1]),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h69))
\gen_master_slots[1].r_issuing_cnt[10]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I1(r_issuing_cnt[5]),
.I2(r_issuing_cnt[6]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h78E1))
\gen_master_slots[1].r_issuing_cnt[11]_i_2
(.I0(r_issuing_cnt[5]),
.I1(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I2(r_issuing_cnt[7]),
.I3(r_issuing_cnt[6]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[1].r_issuing_cnt[11]_i_4
(.I0(m_axi_arready[1]),
.I1(aa_mi_arvalid),
.I2(aa_mi_artarget_hot[1]),
.O(p_75_in));
LUT6 #(
.INIT(64'h20000000BAAAAAAA))
\gen_master_slots[1].r_issuing_cnt[11]_i_5
(.I0(r_issuing_cnt[4]),
.I1(r_cmd_pop_1__1),
.I2(m_axi_arready[1]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[1]),
.I5(r_issuing_cnt[5]),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9AAAAAAA65555555))
\gen_master_slots[1].r_issuing_cnt[9]_i_1
(.I0(r_issuing_cnt[4]),
.I1(r_cmd_pop_1__1),
.I2(m_axi_arready[1]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[1]),
.I5(r_issuing_cnt[5]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]));
LUT6 #(
.INIT(64'h9AAAAAAA65555555))
\gen_master_slots[2].r_issuing_cnt[17]_i_1
(.I0(r_issuing_cnt[8]),
.I1(r_cmd_pop_2__1),
.I2(m_axi_arready[2]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[2]),
.I5(r_issuing_cnt[9]),
.O(\gen_master_slots[2].r_issuing_cnt_reg[19] [0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h69))
\gen_master_slots[2].r_issuing_cnt[18]_i_1
(.I0(\gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0 ),
.I1(r_issuing_cnt[9]),
.I2(r_issuing_cnt[10]),
.O(\gen_master_slots[2].r_issuing_cnt_reg[19] [1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h78E1))
\gen_master_slots[2].r_issuing_cnt[19]_i_2
(.I0(r_issuing_cnt[9]),
.I1(\gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0 ),
.I2(r_issuing_cnt[11]),
.I3(r_issuing_cnt[10]),
.O(\gen_master_slots[2].r_issuing_cnt_reg[19] [2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[2].r_issuing_cnt[19]_i_4
(.I0(m_axi_arready[2]),
.I1(aa_mi_arvalid),
.I2(aa_mi_artarget_hot[2]),
.O(p_57_in));
LUT6 #(
.INIT(64'h20000000BAAAAAAA))
\gen_master_slots[2].r_issuing_cnt[19]_i_5
(.I0(r_issuing_cnt[8]),
.I1(r_cmd_pop_2__1),
.I2(m_axi_arready[2]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[2]),
.I5(r_issuing_cnt[9]),
.O(\gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9AAAAAAA65555555))
\gen_master_slots[3].r_issuing_cnt[25]_i_1
(.I0(r_issuing_cnt[12]),
.I1(r_cmd_pop_3__1),
.I2(m_axi_arready[3]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[3]),
.I5(r_issuing_cnt[13]),
.O(\gen_master_slots[3].r_issuing_cnt_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h69))
\gen_master_slots[3].r_issuing_cnt[26]_i_1
(.I0(\gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0 ),
.I1(r_issuing_cnt[13]),
.I2(r_issuing_cnt[14]),
.O(\gen_master_slots[3].r_issuing_cnt_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h78E1))
\gen_master_slots[3].r_issuing_cnt[27]_i_2
(.I0(r_issuing_cnt[13]),
.I1(\gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0 ),
.I2(r_issuing_cnt[15]),
.I3(r_issuing_cnt[14]),
.O(\gen_master_slots[3].r_issuing_cnt_reg[27] [2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[3].r_issuing_cnt[27]_i_4
(.I0(m_axi_arready[3]),
.I1(aa_mi_arvalid),
.I2(aa_mi_artarget_hot[3]),
.O(p_39_in));
LUT6 #(
.INIT(64'h20000000BAAAAAAA))
\gen_master_slots[3].r_issuing_cnt[27]_i_5
(.I0(r_issuing_cnt[12]),
.I1(r_cmd_pop_3__1),
.I2(m_axi_arready[3]),
.I3(aa_mi_arvalid),
.I4(aa_mi_artarget_hot[3]),
.I5(r_issuing_cnt[13]),
.O(\gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0 ));
LUT5 #(
.INIT(32'h807F0080))
\gen_master_slots[4].r_issuing_cnt[32]_i_1
(.I0(Q),
.I1(aa_mi_arvalid),
.I2(mi_arready_4),
.I3(r_cmd_pop_4__1),
.I4(r_issuing_cnt[16]),
.O(\gen_master_slots[4].r_issuing_cnt_reg[32] ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1__0
(.I0(aa_mi_arvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [0]),
.Q(\m_axi_arqos[15] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [10]),
.Q(\m_axi_arqos[15] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [11]),
.Q(\m_axi_arqos[15] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [12]),
.Q(\m_axi_arqos[15] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [13]),
.Q(\m_axi_arqos[15] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [14]),
.Q(\m_axi_arqos[15] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [15]),
.Q(\m_axi_arqos[15] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [16]),
.Q(\m_axi_arqos[15] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [17]),
.Q(\m_axi_arqos[15] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [18]),
.Q(\m_axi_arqos[15] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [19]),
.Q(\m_axi_arqos[15] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [1]),
.Q(\m_axi_arqos[15] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [20]),
.Q(\m_axi_arqos[15] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [21]),
.Q(\m_axi_arqos[15] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [22]),
.Q(\m_axi_arqos[15] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [23]),
.Q(\m_axi_arqos[15] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [24]),
.Q(\m_axi_arqos[15] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [25]),
.Q(\m_axi_arqos[15] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [26]),
.Q(\m_axi_arqos[15] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [27]),
.Q(\m_axi_arqos[15] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [28]),
.Q(\m_axi_arqos[15] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [29]),
.Q(\m_axi_arqos[15] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [2]),
.Q(\m_axi_arqos[15] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [30]),
.Q(\m_axi_arqos[15] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [31]),
.Q(\m_axi_arqos[15] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [32]),
.Q(\m_axi_arqos[15] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [33]),
.Q(\m_axi_arqos[15] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [34]),
.Q(\m_axi_arqos[15] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [35]),
.Q(\m_axi_arqos[15] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [36]),
.Q(\m_axi_arqos[15] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [37]),
.Q(\m_axi_arqos[15] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [38]),
.Q(\m_axi_arqos[15] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [39]),
.Q(\m_axi_arqos[15] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [3]),
.Q(\m_axi_arqos[15] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [40]),
.Q(\m_axi_arqos[15] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [41]),
.Q(\m_axi_arqos[15] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [42]),
.Q(\m_axi_arqos[15] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [43]),
.Q(\m_axi_arqos[15] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [44]),
.Q(\m_axi_arqos[15] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [45]),
.Q(\m_axi_arqos[15] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [46]),
.Q(\m_axi_arqos[15] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [47]),
.Q(\m_axi_arqos[15] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [48]),
.Q(\m_axi_arqos[15] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [49]),
.Q(\m_axi_arqos[15] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [4]),
.Q(\m_axi_arqos[15] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [50]),
.Q(\m_axi_arqos[15] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [51]),
.Q(\m_axi_arqos[15] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [52]),
.Q(\m_axi_arqos[15] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [53]),
.Q(\m_axi_arqos[15] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [54]),
.Q(\m_axi_arqos[15] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [55]),
.Q(\m_axi_arqos[15] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [56]),
.Q(\m_axi_arqos[15] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [57]),
.Q(\m_axi_arqos[15] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [58]),
.Q(\m_axi_arqos[15] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [5]),
.Q(\m_axi_arqos[15] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [59]),
.Q(\m_axi_arqos[15] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [60]),
.Q(\m_axi_arqos[15] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [61]),
.Q(\m_axi_arqos[15] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [62]),
.Q(\m_axi_arqos[15] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [63]),
.Q(\m_axi_arqos[15] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [64]),
.Q(\m_axi_arqos[15] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [6]),
.Q(\m_axi_arqos[15] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [65]),
.Q(\m_axi_arqos[15] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [66]),
.Q(\m_axi_arqos[15] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [67]),
.Q(\m_axi_arqos[15] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [68]),
.Q(\m_axi_arqos[15] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [7]),
.Q(\m_axi_arqos[15] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [8]),
.Q(\m_axi_arqos[15] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [9]),
.Q(\m_axi_arqos[15] [9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.m_target_hot_i[0]_i_1__0
(.I0(ADDRESS_HIT_0),
.I1(match),
.O(st_aa_artarget_hot));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_no_arbiter.m_target_hot_i[0]_i_2__0
(.I0(\s_axi_arqos[3] [29]),
.I1(\s_axi_arqos[3] [28]),
.I2(\s_axi_arqos[3] [31]),
.I3(\s_axi_arqos[3] [30]),
.I4(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I5(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(ADDRESS_HIT_0));
LUT6 #(
.INIT(64'h0000002000000000))
\gen_no_arbiter.m_target_hot_i[1]_i_1__0
(.I0(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\s_axi_arqos[3] [29]),
.I2(\s_axi_arqos[3] [28]),
.I3(\s_axi_arqos[3] [31]),
.I4(\s_axi_arqos[3] [30]),
.I5(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[0]));
LUT6 #(
.INIT(64'h0000001000000000))
\gen_no_arbiter.m_target_hot_i[1]_i_2__0
(.I0(\s_axi_arqos[3] [34]),
.I1(\s_axi_arqos[3] [35]),
.I2(\s_axi_arqos[3] [33]),
.I3(\s_axi_arqos[3] [32]),
.I4(\s_axi_arqos[3] [37]),
.I5(\s_axi_arqos[3] [36]),
.O(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_no_arbiter.m_target_hot_i[2]_i_1__0
(.I0(\s_axi_arqos[3] [29]),
.I1(\s_axi_arqos[3] [28]),
.I2(\s_axi_arqos[3] [31]),
.I3(\s_axi_arqos[3] [30]),
.I4(\gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0 ),
.I5(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[1]));
LUT6 #(
.INIT(64'h0000000200000000))
\gen_no_arbiter.m_target_hot_i[2]_i_2__0
(.I0(\s_axi_arqos[3] [35]),
.I1(\s_axi_arqos[3] [34]),
.I2(\s_axi_arqos[3] [32]),
.I3(\s_axi_arqos[3] [33]),
.I4(\s_axi_arqos[3] [36]),
.I5(\s_axi_arqos[3] [37]),
.O(\gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\gen_no_arbiter.m_target_hot_i[3]_i_1__0
(.I0(\gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0 ),
.I1(\s_axi_arqos[3] [25]),
.I2(\s_axi_arqos[3] [26]),
.I3(\s_axi_arqos[3] [27]),
.I4(\gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0 ),
.I5(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[2]));
LUT6 #(
.INIT(64'h0000000000000001))
\gen_no_arbiter.m_target_hot_i[3]_i_2__0
(.I0(\s_axi_arqos[3] [32]),
.I1(\s_axi_arqos[3] [33]),
.I2(\s_axi_arqos[3] [34]),
.I3(\s_axi_arqos[3] [35]),
.I4(\s_axi_arqos[3] [37]),
.I5(\s_axi_arqos[3] [36]),
.O(\gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h0001))
\gen_no_arbiter.m_target_hot_i[3]_i_3__0
(.I0(\s_axi_arqos[3] [31]),
.I1(\s_axi_arqos[3] [30]),
.I2(\s_axi_arqos[3] [29]),
.I3(\s_axi_arqos[3] [28]),
.O(\gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\gen_no_arbiter.m_target_hot_i[3]_i_4__0
(.I0(\s_axi_arqos[3] [40]),
.I1(\s_axi_arqos[3] [41]),
.I2(\s_axi_arqos[3] [38]),
.I3(\s_axi_arqos[3] [39]),
.I4(\s_axi_arqos[3] [43]),
.I5(\s_axi_arqos[3] [42]),
.O(\gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_no_arbiter.m_target_hot_i[4]_i_2__0
(.I0(D[1]),
.I1(D[2]),
.I2(D[0]),
.I3(ADDRESS_HIT_0),
.O(match));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(E),
.D(st_aa_artarget_hot),
.Q(aa_mi_artarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(E),
.D(D[0]),
.Q(aa_mi_artarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(E),
.D(D[1]),
.Q(aa_mi_artarget_hot[2]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[3]
(.C(aclk),
.CE(E),
.D(D[2]),
.Q(aa_mi_artarget_hot[3]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[4]
(.C(aclk),
.CE(E),
.D(\s_axi_araddr[24] ),
.Q(Q),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hDC))
\gen_no_arbiter.m_valid_i_i_1
(.I0(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I1(m_valid_i),
.I2(aa_mi_arvalid),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFF88800000000))
\gen_no_arbiter.m_valid_i_i_2
(.I0(m_axi_arready[2]),
.I1(aa_mi_artarget_hot[2]),
.I2(m_axi_arready[1]),
.I3(aa_mi_artarget_hot[1]),
.I4(\gen_no_arbiter.m_valid_i_i_3_n_0 ),
.I5(aa_mi_arvalid),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_no_arbiter.m_valid_i_i_3
(.I0(aa_mi_artarget_hot[0]),
.I1(m_axi_arready[0]),
.I2(Q),
.I3(mi_arready_4),
.I4(m_axi_arready[3]),
.I5(aa_mi_artarget_hot[3]),
.O(\gen_no_arbiter.m_valid_i_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(aa_mi_arvalid),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(E),
.Q(S_AXI_ARREADY),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[0]_INST_0
(.I0(aa_mi_artarget_hot[0]),
.I1(aa_mi_arvalid),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[1]_INST_0
(.I0(aa_mi_artarget_hot[1]),
.I1(aa_mi_arvalid),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[2]_INST_0
(.I0(aa_mi_artarget_hot[2]),
.I1(aa_mi_arvalid),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[3]_INST_0
(.I0(aa_mi_artarget_hot[3]),
.I1(aa_mi_arvalid),
.O(m_axi_arvalid[3]));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_addr_arbiter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0
(ss_aa_awready,
aa_sa_awvalid,
mi_awready_mux__3,
s_ready_i0__1,
p_84_in,
Q,
p_66_in,
p_48_in,
p_101_in,
m_axi_awvalid,
write_cs01_out,
ADDRESS_HIT_0,
match,
D,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
sa_wm_awready_mux__3,
\gen_master_slots[4].w_issuing_cnt_reg[32] ,
\m_axi_awqos[15] ,
E,
aclk,
SR,
m_ready_d,
m_valid_i,
m_axi_awready,
mi_awready_4,
\s_axi_awqos[3] ,
s_axi_awvalid,
m_ready_d_0,
s_axi_bready,
p_46_out,
\chosen_reg[4] ,
w_issuing_cnt,
\s_axi_awaddr[24] );
output ss_aa_awready;
output aa_sa_awvalid;
output mi_awready_mux__3;
output [0:0]s_ready_i0__1;
output p_84_in;
output [4:0]Q;
output p_66_in;
output p_48_in;
output p_101_in;
output [3:0]m_axi_awvalid;
output write_cs01_out;
output ADDRESS_HIT_0;
output match;
output [2:0]D;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output sa_wm_awready_mux__3;
output \gen_master_slots[4].w_issuing_cnt_reg[32] ;
output [68:0]\m_axi_awqos[15] ;
input [0:0]E;
input aclk;
input [0:0]SR;
input [1:0]m_ready_d;
input m_valid_i;
input [3:0]m_axi_awready;
input mi_awready_4;
input [68:0]\s_axi_awqos[3] ;
input [0:0]s_axi_awvalid;
input [0:0]m_ready_d_0;
input [0:0]s_axi_bready;
input p_46_out;
input [0:0]\chosen_reg[4] ;
input [0:0]w_issuing_cnt;
input [0:0]\s_axi_awaddr[24] ;
wire ADDRESS_HIT_0;
wire [2:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]SR;
wire aa_sa_awvalid;
wire aclk;
wire [0:0]\chosen_reg[4] ;
wire \gen_master_slots[4].w_issuing_cnt_reg[32] ;
wire \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_1__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ;
wire [68:0]\m_axi_awqos[15] ;
wire [3:0]m_axi_awready;
wire [3:0]m_axi_awvalid;
wire [1:0]m_ready_d;
wire \m_ready_d[1]_i_4_n_0 ;
wire [0:0]m_ready_d_0;
wire m_valid_i;
wire match;
wire mi_awready_4;
wire mi_awready_mux__3;
wire p_101_in;
wire p_46_out;
wire p_48_in;
wire p_66_in;
wire p_84_in;
wire [0:0]\s_axi_awaddr[24] ;
wire [68:0]\s_axi_awqos[3] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_ready_i0__1;
wire s_ready_i2;
wire sa_wm_awready_mux__3;
wire ss_aa_awready;
wire [0:0]st_aa_awtarget_hot;
wire [0:0]w_issuing_cnt;
wire write_cs01_out;
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0080))
\gen_axi.s_axi_wready_i_i_2
(.I0(mi_awready_4),
.I1(Q[4]),
.I2(aa_sa_awvalid),
.I3(m_ready_d[1]),
.O(write_cs01_out));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[0].w_issuing_cnt[3]_i_4
(.I0(m_axi_awready[0]),
.I1(Q[0]),
.I2(aa_sa_awvalid),
.I3(m_ready_d[1]),
.O(p_101_in));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[1].w_issuing_cnt[11]_i_4
(.I0(m_axi_awready[1]),
.I1(Q[1]),
.I2(aa_sa_awvalid),
.I3(m_ready_d[1]),
.O(p_84_in));
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[2].w_issuing_cnt[19]_i_4
(.I0(m_axi_awready[2]),
.I1(Q[2]),
.I2(aa_sa_awvalid),
.I3(m_ready_d[1]),
.O(p_66_in));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[3].w_issuing_cnt[27]_i_4
(.I0(m_axi_awready[3]),
.I1(Q[3]),
.I2(aa_sa_awvalid),
.I3(m_ready_d[1]),
.O(p_48_in));
LUT5 #(
.INIT(32'h95552AAA))
\gen_master_slots[4].w_issuing_cnt[32]_i_1
(.I0(write_cs01_out),
.I1(s_axi_bready),
.I2(p_46_out),
.I3(\chosen_reg[4] ),
.I4(w_issuing_cnt),
.O(\gen_master_slots[4].w_issuing_cnt_reg[32] ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_2
(.I0(aa_sa_awvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [0]),
.Q(\m_axi_awqos[15] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [10]),
.Q(\m_axi_awqos[15] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [11]),
.Q(\m_axi_awqos[15] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [12]),
.Q(\m_axi_awqos[15] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [13]),
.Q(\m_axi_awqos[15] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [14]),
.Q(\m_axi_awqos[15] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [15]),
.Q(\m_axi_awqos[15] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [16]),
.Q(\m_axi_awqos[15] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [17]),
.Q(\m_axi_awqos[15] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [18]),
.Q(\m_axi_awqos[15] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [19]),
.Q(\m_axi_awqos[15] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [1]),
.Q(\m_axi_awqos[15] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [20]),
.Q(\m_axi_awqos[15] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [21]),
.Q(\m_axi_awqos[15] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [22]),
.Q(\m_axi_awqos[15] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [23]),
.Q(\m_axi_awqos[15] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [24]),
.Q(\m_axi_awqos[15] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [25]),
.Q(\m_axi_awqos[15] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [26]),
.Q(\m_axi_awqos[15] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [27]),
.Q(\m_axi_awqos[15] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [28]),
.Q(\m_axi_awqos[15] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [29]),
.Q(\m_axi_awqos[15] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [2]),
.Q(\m_axi_awqos[15] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [30]),
.Q(\m_axi_awqos[15] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [31]),
.Q(\m_axi_awqos[15] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [32]),
.Q(\m_axi_awqos[15] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [33]),
.Q(\m_axi_awqos[15] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [34]),
.Q(\m_axi_awqos[15] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [35]),
.Q(\m_axi_awqos[15] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [36]),
.Q(\m_axi_awqos[15] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [37]),
.Q(\m_axi_awqos[15] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [38]),
.Q(\m_axi_awqos[15] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [39]),
.Q(\m_axi_awqos[15] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [3]),
.Q(\m_axi_awqos[15] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [40]),
.Q(\m_axi_awqos[15] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [41]),
.Q(\m_axi_awqos[15] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [42]),
.Q(\m_axi_awqos[15] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [43]),
.Q(\m_axi_awqos[15] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [44]),
.Q(\m_axi_awqos[15] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [45]),
.Q(\m_axi_awqos[15] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [46]),
.Q(\m_axi_awqos[15] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [47]),
.Q(\m_axi_awqos[15] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [48]),
.Q(\m_axi_awqos[15] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [49]),
.Q(\m_axi_awqos[15] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [4]),
.Q(\m_axi_awqos[15] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [50]),
.Q(\m_axi_awqos[15] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [51]),
.Q(\m_axi_awqos[15] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [52]),
.Q(\m_axi_awqos[15] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [53]),
.Q(\m_axi_awqos[15] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [54]),
.Q(\m_axi_awqos[15] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [55]),
.Q(\m_axi_awqos[15] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [56]),
.Q(\m_axi_awqos[15] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [57]),
.Q(\m_axi_awqos[15] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [58]),
.Q(\m_axi_awqos[15] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [5]),
.Q(\m_axi_awqos[15] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [59]),
.Q(\m_axi_awqos[15] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [60]),
.Q(\m_axi_awqos[15] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [61]),
.Q(\m_axi_awqos[15] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [62]),
.Q(\m_axi_awqos[15] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [63]),
.Q(\m_axi_awqos[15] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [64]),
.Q(\m_axi_awqos[15] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [6]),
.Q(\m_axi_awqos[15] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [65]),
.Q(\m_axi_awqos[15] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [66]),
.Q(\m_axi_awqos[15] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [67]),
.Q(\m_axi_awqos[15] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [68]),
.Q(\m_axi_awqos[15] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [7]),
.Q(\m_axi_awqos[15] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [8]),
.Q(\m_axi_awqos[15] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [9]),
.Q(\m_axi_awqos[15] [9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(ADDRESS_HIT_0),
.I1(match),
.O(st_aa_awtarget_hot));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_no_arbiter.m_target_hot_i[0]_i_2
(.I0(\s_axi_awqos[3] [29]),
.I1(\s_axi_awqos[3] [28]),
.I2(\s_axi_awqos[3] [31]),
.I3(\s_axi_awqos[3] [30]),
.I4(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I5(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(ADDRESS_HIT_0));
LUT6 #(
.INIT(64'h0000002000000000))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\s_axi_awqos[3] [29]),
.I2(\s_axi_awqos[3] [28]),
.I3(\s_axi_awqos[3] [31]),
.I4(\s_axi_awqos[3] [30]),
.I5(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[0]));
LUT6 #(
.INIT(64'h0000001000000000))
\gen_no_arbiter.m_target_hot_i[1]_i_2
(.I0(\s_axi_awqos[3] [34]),
.I1(\s_axi_awqos[3] [35]),
.I2(\s_axi_awqos[3] [33]),
.I3(\s_axi_awqos[3] [32]),
.I4(\s_axi_awqos[3] [37]),
.I5(\s_axi_awqos[3] [36]),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_no_arbiter.m_target_hot_i[2]_i_1
(.I0(\s_axi_awqos[3] [29]),
.I1(\s_axi_awqos[3] [28]),
.I2(\s_axi_awqos[3] [31]),
.I3(\s_axi_awqos[3] [30]),
.I4(\gen_no_arbiter.m_target_hot_i[2]_i_2_n_0 ),
.I5(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[1]));
LUT6 #(
.INIT(64'h0000000200000000))
\gen_no_arbiter.m_target_hot_i[2]_i_2
(.I0(\s_axi_awqos[3] [35]),
.I1(\s_axi_awqos[3] [34]),
.I2(\s_axi_awqos[3] [32]),
.I3(\s_axi_awqos[3] [33]),
.I4(\s_axi_awqos[3] [36]),
.I5(\s_axi_awqos[3] [37]),
.O(\gen_no_arbiter.m_target_hot_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\gen_no_arbiter.m_target_hot_i[3]_i_1
(.I0(\gen_no_arbiter.m_target_hot_i[3]_i_2_n_0 ),
.I1(\s_axi_awqos[3] [25]),
.I2(\s_axi_awqos[3] [26]),
.I3(\s_axi_awqos[3] [27]),
.I4(\gen_no_arbiter.m_target_hot_i[3]_i_3_n_0 ),
.I5(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(D[2]));
LUT6 #(
.INIT(64'h0000000000000001))
\gen_no_arbiter.m_target_hot_i[3]_i_2
(.I0(\s_axi_awqos[3] [32]),
.I1(\s_axi_awqos[3] [33]),
.I2(\s_axi_awqos[3] [34]),
.I3(\s_axi_awqos[3] [35]),
.I4(\s_axi_awqos[3] [37]),
.I5(\s_axi_awqos[3] [36]),
.O(\gen_no_arbiter.m_target_hot_i[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0001))
\gen_no_arbiter.m_target_hot_i[3]_i_3
(.I0(\s_axi_awqos[3] [31]),
.I1(\s_axi_awqos[3] [30]),
.I2(\s_axi_awqos[3] [29]),
.I3(\s_axi_awqos[3] [28]),
.O(\gen_no_arbiter.m_target_hot_i[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\gen_no_arbiter.m_target_hot_i[3]_i_4
(.I0(\s_axi_awqos[3] [40]),
.I1(\s_axi_awqos[3] [41]),
.I2(\s_axi_awqos[3] [38]),
.I3(\s_axi_awqos[3] [39]),
.I4(\s_axi_awqos[3] [43]),
.I5(\s_axi_awqos[3] [42]),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_no_arbiter.m_target_hot_i[4]_i_2
(.I0(D[1]),
.I1(D[2]),
.I2(D[0]),
.I3(ADDRESS_HIT_0),
.O(match));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(E),
.D(st_aa_awtarget_hot),
.Q(Q[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(E),
.D(D[0]),
.Q(Q[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(E),
.D(D[1]),
.Q(Q[2]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[3]
(.C(aclk),
.CE(E),
.D(D[2]),
.Q(Q[3]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[4]
(.C(aclk),
.CE(E),
.D(\s_axi_awaddr[24] ),
.Q(Q[4]),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF1F00))
\gen_no_arbiter.m_valid_i_i_1__0
(.I0(m_ready_d[1]),
.I1(mi_awready_mux__3),
.I2(s_ready_i0__1),
.I3(aa_sa_awvalid),
.I4(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ),
.Q(aa_sa_awvalid),
.R(SR));
LUT3 #(
.INIT(8'h04))
\gen_no_arbiter.s_ready_i[0]_i_34
(.I0(ss_aa_awready),
.I1(s_axi_awvalid),
.I2(m_ready_d_0),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(E),
.Q(ss_aa_awready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h08))
\m_axi_awvalid[0]_INST_0
(.I0(Q[0]),
.I1(aa_sa_awvalid),
.I2(m_ready_d[1]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h08))
\m_axi_awvalid[1]_INST_0
(.I0(Q[1]),
.I1(aa_sa_awvalid),
.I2(m_ready_d[1]),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h08))
\m_axi_awvalid[2]_INST_0
(.I0(Q[2]),
.I1(aa_sa_awvalid),
.I2(m_ready_d[1]),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h08))
\m_axi_awvalid[3]_INST_0
(.I0(Q[3]),
.I1(aa_sa_awvalid),
.I2(m_ready_d[1]),
.O(m_axi_awvalid[3]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_ready_d[0]_i_2
(.I0(Q[4]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(Q[3]),
.O(sa_wm_awready_mux__3));
LUT5 #(
.INIT(32'hFFEAEAEA))
\m_ready_d[1]_i_2
(.I0(\m_ready_d[1]_i_4_n_0 ),
.I1(Q[1]),
.I2(m_axi_awready[1]),
.I3(Q[2]),
.I4(m_axi_awready[2]),
.O(mi_awready_mux__3));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\m_ready_d[1]_i_3
(.I0(m_ready_d[0]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(Q[4]),
.O(s_ready_i0__1));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\m_ready_d[1]_i_4
(.I0(Q[0]),
.I1(m_axi_awready[0]),
.I2(Q[4]),
.I3(mi_awready_4),
.I4(m_axi_awready[3]),
.I5(Q[3]),
.O(\m_ready_d[1]_i_4_n_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp
(E,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
\gen_master_slots[3].w_issuing_cnt_reg[24] ,
\gen_master_slots[0].w_issuing_cnt_reg[0] ,
SR,
\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\s_axi_bvalid[0] ,
resp_select,
s_ready_i_reg,
f_mux4_return,
w_issuing_cnt,
p_84_in,
p_66_in,
p_48_in,
p_101_in,
aresetn_d,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ,
aa_sa_awvalid,
match,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.accept_cnt_reg[0] ,
p_0_out,
s_axi_bready,
Q,
p_46_out,
p_128_out,
p_108_out,
m_valid_i_reg,
st_mr_bid,
st_mr_bmesg,
p_68_out,
p_88_out,
m_valid_i_reg_0,
\s_axi_awaddr[30] ,
ADDRESS_HIT_0,
aclk);
output [0:0]E;
output [0:0]\gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]\gen_master_slots[3].w_issuing_cnt_reg[24] ;
output [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
output [0:0]SR;
output [0:0]\gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \s_axi_bvalid[0] ;
output [0:0]resp_select;
output [4:0]s_ready_i_reg;
output [13:0]f_mux4_return;
input [16:0]w_issuing_cnt;
input p_84_in;
input p_66_in;
input p_48_in;
input p_101_in;
input aresetn_d;
input \gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ;
input \gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ;
input \gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ;
input \gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ;
input aa_sa_awvalid;
input match;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input \gen_multi_thread.accept_cnt_reg[0] ;
input p_0_out;
input [0:0]s_axi_bready;
input [0:0]Q;
input p_46_out;
input p_128_out;
input p_108_out;
input m_valid_i_reg;
input [47:0]st_mr_bid;
input [7:0]st_mr_bmesg;
input p_68_out;
input p_88_out;
input m_valid_i_reg_0;
input [2:0]\s_axi_awaddr[30] ;
input ADDRESS_HIT_0;
input aclk;
wire ADDRESS_HIT_0;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire [13:0]f_mux4_return;
wire [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
wire [0:0]\gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire [0:0]\gen_master_slots[3].w_issuing_cnt_reg[24] ;
wire \gen_multi_thread.accept_cnt_reg[0] ;
wire \gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ;
wire \gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ;
wire \gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ;
wire \gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ;
wire \gen_no_arbiter.s_ready_i[0]_i_24_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_25_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_26_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_36_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_37_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_38_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_39_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6_n_0 ;
wire [0:0]\gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire last_rr_hot;
wire \last_rr_hot[0]_i_2__0_n_0 ;
wire \last_rr_hot[0]_i_3__0_n_0 ;
wire \last_rr_hot[1]_i_2__0_n_0 ;
wire \last_rr_hot[2]_i_3__0_n_0 ;
wire \last_rr_hot[3]_i_2__0_n_0 ;
wire \last_rr_hot[3]_i_3__0_n_0 ;
wire \last_rr_hot[4]_i_4__0_n_0 ;
wire \last_rr_hot[4]_i_5__0_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire m_valid_i;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire match;
wire need_arbitration;
wire [4:0]next_rr_hot;
wire p_0_out;
wire p_101_in;
wire p_108_out;
wire p_128_out;
wire p_46_out;
wire p_48_in;
wire p_5_in6_in;
wire p_66_in;
wire p_68_out;
wire p_6_in;
wire p_7_in9_in;
wire p_84_in;
wire p_88_out;
wire p_8_in;
wire [0:0]resp_select;
wire [1:0]resp_select__0;
wire [2:0]\s_axi_awaddr[30] ;
wire [0:0]s_axi_bready;
wire \s_axi_bvalid[0] ;
wire [4:0]s_ready_i_reg;
wire [47:0]st_mr_bid;
wire [7:0]st_mr_bmesg;
wire w_cmd_pop_0__0;
wire w_cmd_pop_1__0;
wire w_cmd_pop_2__0;
wire w_cmd_pop_3__0;
wire w_cmd_pop_4__0;
wire [16:0]w_issuing_cnt;
LUT6 #(
.INIT(64'hBBBBBBBBBBBBBBB8))
\chosen[4]_i_1
(.I0(s_axi_bready),
.I1(\s_axi_bvalid[0] ),
.I2(p_46_out),
.I3(p_128_out),
.I4(p_108_out),
.I5(m_valid_i_reg),
.O(need_arbitration));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[0]),
.Q(s_ready_i_reg[0]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[1]),
.Q(s_ready_i_reg[1]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[2]),
.Q(s_ready_i_reg[2]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[3]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[3]),
.Q(s_ready_i_reg[3]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[4]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[4]),
.Q(s_ready_i_reg[4]),
.R(SR));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1
(.I0(st_mr_bid[36]),
.I1(st_mr_bid[0]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[24]),
.I5(st_mr_bid[12]),
.O(f_mux4_return[0]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1
(.I0(st_mr_bid[46]),
.I1(st_mr_bid[10]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[34]),
.I5(st_mr_bid[22]),
.O(f_mux4_return[10]));
LUT2 #(
.INIT(4'h8))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1
(.I0(s_ready_i_reg[4]),
.I1(p_46_out),
.O(resp_select));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2
(.I0(st_mr_bid[47]),
.I1(st_mr_bid[11]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[35]),
.I5(st_mr_bid[23]),
.O(f_mux4_return[11]));
(* SOFT_HLUTNM = "soft_lutpair157" *)
LUT4 #(
.INIT(16'hF888))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3
(.I0(p_68_out),
.I1(s_ready_i_reg[3]),
.I2(p_108_out),
.I3(s_ready_i_reg[1]),
.O(resp_select__0[0]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1
(.I0(st_mr_bmesg[6]),
.I1(st_mr_bmesg[0]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bmesg[4]),
.I5(st_mr_bmesg[2]),
.O(f_mux4_return[12]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1
(.I0(st_mr_bmesg[7]),
.I1(st_mr_bmesg[1]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bmesg[5]),
.I5(st_mr_bmesg[3]),
.O(f_mux4_return[13]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1
(.I0(st_mr_bid[37]),
.I1(st_mr_bid[1]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[25]),
.I5(st_mr_bid[13]),
.O(f_mux4_return[1]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1
(.I0(st_mr_bid[38]),
.I1(st_mr_bid[2]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[26]),
.I5(st_mr_bid[14]),
.O(f_mux4_return[2]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1
(.I0(st_mr_bid[39]),
.I1(st_mr_bid[3]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[27]),
.I5(st_mr_bid[15]),
.O(f_mux4_return[3]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1
(.I0(st_mr_bid[40]),
.I1(st_mr_bid[4]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[28]),
.I5(st_mr_bid[16]),
.O(f_mux4_return[4]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1
(.I0(st_mr_bid[41]),
.I1(st_mr_bid[5]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[29]),
.I5(st_mr_bid[17]),
.O(f_mux4_return[5]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1
(.I0(st_mr_bid[42]),
.I1(st_mr_bid[6]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[30]),
.I5(st_mr_bid[18]),
.O(f_mux4_return[6]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1
(.I0(st_mr_bid[43]),
.I1(st_mr_bid[7]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[31]),
.I5(st_mr_bid[19]),
.O(f_mux4_return[7]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1
(.I0(st_mr_bid[44]),
.I1(st_mr_bid[8]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[32]),
.I5(st_mr_bid[20]),
.O(f_mux4_return[8]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1
(.I0(st_mr_bid[45]),
.I1(st_mr_bid[9]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_bid[33]),
.I5(st_mr_bid[21]),
.O(f_mux4_return[9]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[0].w_issuing_cnt[3]_i_1
(.I0(w_issuing_cnt[1]),
.I1(w_issuing_cnt[2]),
.I2(w_issuing_cnt[0]),
.I3(w_issuing_cnt[3]),
.I4(w_cmd_pop_0__0),
.I5(p_101_in),
.O(\gen_master_slots[0].w_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[0].w_issuing_cnt[3]_i_3
(.I0(s_ready_i_reg[0]),
.I1(p_128_out),
.I2(s_axi_bready),
.O(w_cmd_pop_0__0));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[1].w_issuing_cnt[11]_i_1
(.I0(w_issuing_cnt[5]),
.I1(w_issuing_cnt[6]),
.I2(w_issuing_cnt[4]),
.I3(w_issuing_cnt[7]),
.I4(w_cmd_pop_1__0),
.I5(p_84_in),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair157" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[1].w_issuing_cnt[11]_i_3
(.I0(s_ready_i_reg[1]),
.I1(p_108_out),
.I2(s_axi_bready),
.O(w_cmd_pop_1__0));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[2].w_issuing_cnt[19]_i_1
(.I0(w_issuing_cnt[9]),
.I1(w_issuing_cnt[10]),
.I2(w_issuing_cnt[8]),
.I3(w_issuing_cnt[11]),
.I4(w_cmd_pop_2__0),
.I5(p_66_in),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16] ));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[2].w_issuing_cnt[19]_i_3
(.I0(s_ready_i_reg[2]),
.I1(p_88_out),
.I2(s_axi_bready),
.O(w_cmd_pop_2__0));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[3].w_issuing_cnt[27]_i_1
(.I0(w_issuing_cnt[13]),
.I1(w_issuing_cnt[14]),
.I2(w_issuing_cnt[12]),
.I3(w_issuing_cnt[15]),
.I4(w_cmd_pop_3__0),
.I5(p_48_in),
.O(\gen_master_slots[3].w_issuing_cnt_reg[24] ));
(* SOFT_HLUTNM = "soft_lutpair156" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[3].w_issuing_cnt[27]_i_3
(.I0(s_ready_i_reg[3]),
.I1(p_68_out),
.I2(s_axi_bready),
.O(w_cmd_pop_3__0));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1
(.I0(aresetn_d),
.O(SR));
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_no_arbiter.s_ready_i[0]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ),
.I5(aa_sa_awvalid),
.O(m_valid_i));
LUT6 #(
.INIT(64'hA8888888AAAAAAAA))
\gen_no_arbiter.s_ready_i[0]_i_24
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.I1(\gen_multi_thread.accept_cnt_reg[0] ),
.I2(\s_axi_bvalid[0] ),
.I3(p_0_out),
.I4(s_axi_bready),
.I5(Q),
.O(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ));
LUT4 #(
.INIT(16'hF888))
\gen_no_arbiter.s_ready_i[0]_i_25
(.I0(\gen_no_arbiter.s_ready_i[0]_i_36_n_0 ),
.I1(\s_axi_awaddr[30] [0]),
.I2(ADDRESS_HIT_0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_37_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ));
LUT4 #(
.INIT(16'hECA0))
\gen_no_arbiter.s_ready_i[0]_i_26
(.I0(\gen_no_arbiter.s_ready_i[0]_i_38_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_39_n_0 ),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_26_n_0 ));
LUT3 #(
.INIT(8'h80))
\gen_no_arbiter.s_ready_i[0]_i_27
(.I0(s_ready_i_reg[4]),
.I1(p_46_out),
.I2(s_axi_bready),
.O(w_cmd_pop_4__0));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_36
(.I0(w_cmd_pop_1__0),
.I1(w_issuing_cnt[4]),
.I2(w_issuing_cnt[7]),
.I3(w_issuing_cnt[5]),
.I4(w_issuing_cnt[6]),
.O(\gen_no_arbiter.s_ready_i[0]_i_36_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_37
(.I0(w_cmd_pop_0__0),
.I1(w_issuing_cnt[0]),
.I2(w_issuing_cnt[3]),
.I3(w_issuing_cnt[1]),
.I4(w_issuing_cnt[2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_37_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_38
(.I0(w_cmd_pop_2__0),
.I1(w_issuing_cnt[8]),
.I2(w_issuing_cnt[11]),
.I3(w_issuing_cnt[9]),
.I4(w_issuing_cnt[10]),
.O(\gen_no_arbiter.s_ready_i[0]_i_38_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_39
(.I0(w_cmd_pop_3__0),
.I1(w_issuing_cnt[12]),
.I2(w_issuing_cnt[15]),
.I3(w_issuing_cnt[13]),
.I4(w_issuing_cnt[14]),
.O(\gen_no_arbiter.s_ready_i[0]_i_39_n_0 ));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8AAAA))
\gen_no_arbiter.s_ready_i[0]_i_6
(.I0(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_26_n_0 ),
.I3(w_cmd_pop_4__0),
.I4(match),
.I5(w_issuing_cnt[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[0]_i_1__0
(.I0(p_128_out),
.I1(p_68_out),
.I2(p_46_out),
.I3(\last_rr_hot[0]_i_2__0_n_0 ),
.I4(\last_rr_hot[0]_i_3__0_n_0 ),
.I5(p_6_in),
.O(next_rr_hot[0]));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[0]_i_2__0
(.I0(p_5_in6_in),
.I1(\last_rr_hot_reg_n_0_[0] ),
.I2(p_108_out),
.I3(p_88_out),
.O(\last_rr_hot[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair160" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[0]_i_3__0
(.I0(p_46_out),
.I1(p_7_in9_in),
.I2(p_8_in),
.O(\last_rr_hot[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[1]_i_1__0
(.I0(p_108_out),
.I1(p_128_out),
.I2(p_46_out),
.I3(\last_rr_hot[1]_i_2__0_n_0 ),
.I4(\last_rr_hot[4]_i_4__0_n_0 ),
.I5(p_7_in9_in),
.O(next_rr_hot[1]));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[1]_i_2__0
(.I0(p_6_in),
.I1(p_5_in6_in),
.I2(p_88_out),
.I3(p_68_out),
.O(\last_rr_hot[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA2222AAAA0020))
\last_rr_hot[2]_i_1__0
(.I0(p_88_out),
.I1(m_valid_i_reg_0),
.I2(\last_rr_hot[4]_i_5__0_n_0 ),
.I3(p_46_out),
.I4(\last_rr_hot[2]_i_3__0_n_0 ),
.I5(p_8_in),
.O(next_rr_hot[2]));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[2]_i_3__0
(.I0(p_108_out),
.I1(\last_rr_hot_reg_n_0_[0] ),
.I2(p_5_in6_in),
.O(\last_rr_hot[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[3]_i_1__0
(.I0(p_68_out),
.I1(p_108_out),
.I2(p_88_out),
.I3(\last_rr_hot[3]_i_2__0_n_0 ),
.I4(\last_rr_hot[3]_i_3__0_n_0 ),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[3]));
(* SOFT_HLUTNM = "soft_lutpair160" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[3]_i_2__0
(.I0(p_8_in),
.I1(p_7_in9_in),
.I2(p_46_out),
.I3(p_128_out),
.O(\last_rr_hot[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[3]_i_3__0
(.I0(p_88_out),
.I1(p_5_in6_in),
.I2(p_6_in),
.O(\last_rr_hot[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA8))
\last_rr_hot[4]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[3]),
.I2(next_rr_hot[2]),
.I3(next_rr_hot[1]),
.I4(next_rr_hot[0]),
.I5(next_rr_hot[4]),
.O(last_rr_hot));
LUT6 #(
.INIT(64'hAAAA2222AAAA0020))
\last_rr_hot[4]_i_2__0
(.I0(p_46_out),
.I1(m_valid_i_reg),
.I2(\last_rr_hot[4]_i_4__0_n_0 ),
.I3(p_108_out),
.I4(\last_rr_hot[4]_i_5__0_n_0 ),
.I5(p_5_in6_in),
.O(next_rr_hot[4]));
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[4]_i_4__0
(.I0(p_128_out),
.I1(p_8_in),
.I2(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[4]_i_5__0
(.I0(p_68_out),
.I1(p_6_in),
.I2(p_7_in9_in),
.O(\last_rr_hot[4]_i_5__0_n_0 ));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[0]),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[1]),
.Q(p_5_in6_in),
.R(SR));
FDRE \last_rr_hot_reg[2]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[2]),
.Q(p_6_in),
.R(SR));
FDRE \last_rr_hot_reg[3]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[3]),
.Q(p_7_in9_in),
.R(SR));
FDSE \last_rr_hot_reg[4]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[4]),
.Q(p_8_in),
.S(SR));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\s_axi_bvalid[0]_INST_0
(.I0(resp_select),
.I1(p_128_out),
.I2(s_ready_i_reg[0]),
.I3(p_108_out),
.I4(s_ready_i_reg[1]),
.I5(resp_select__0[1]),
.O(\s_axi_bvalid[0] ));
(* SOFT_HLUTNM = "soft_lutpair156" *)
LUT4 #(
.INIT(16'hF888))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(p_68_out),
.I1(s_ready_i_reg[3]),
.I2(p_88_out),
.I3(s_ready_i_reg[2]),
.O(resp_select__0[1]));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_arbiter_resp" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8
(E,
m_valid_i,
\m_payload_i_reg[0] ,
Q,
f_mux4_return,
\s_axi_rvalid[0] ,
resp_select,
\m_payload_i_reg[0]_0 ,
\m_payload_i_reg[34] ,
\m_payload_i_reg[0]_1 ,
\m_payload_i_reg[0]_2 ,
aresetn_d,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ,
aa_mi_arvalid,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
r_cmd_pop_4__1,
match,
r_issuing_cnt,
s_axi_rready,
p_122_out,
st_mr_rid,
st_mr_rmesg,
\m_payload_i_reg[34]_0 ,
\m_payload_i_reg[34]_1 ,
\m_payload_i_reg[34]_2 ,
\m_payload_i_reg[34]_3 ,
p_62_out,
p_102_out,
S_AXI_ARREADY,
s_axi_arvalid,
\gen_multi_thread.accept_cnt_reg[0] ,
\m_payload_i_reg[34]_4 ,
\gen_multi_thread.accept_cnt_reg[3] ,
p_40_out,
m_valid_i_reg,
p_82_out,
m_valid_i_reg_0,
SR,
aclk);
output [0:0]E;
output m_valid_i;
output [0:0]\m_payload_i_reg[0] ;
output [4:0]Q;
output [46:0]f_mux4_return;
output \s_axi_rvalid[0] ;
output [0:0]resp_select;
output [0:0]\m_payload_i_reg[0]_0 ;
output [0:0]\m_payload_i_reg[34] ;
output [0:0]\m_payload_i_reg[0]_1 ;
output [0:0]\m_payload_i_reg[0]_2 ;
input aresetn_d;
input \gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ;
input \gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ;
input \gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ;
input \gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ;
input aa_mi_arvalid;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input r_cmd_pop_4__1;
input match;
input [0:0]r_issuing_cnt;
input [0:0]s_axi_rready;
input p_122_out;
input [47:0]st_mr_rid;
input [135:0]st_mr_rmesg;
input [0:0]\m_payload_i_reg[34]_0 ;
input [0:0]\m_payload_i_reg[34]_1 ;
input [0:0]\m_payload_i_reg[34]_2 ;
input [0:0]\m_payload_i_reg[34]_3 ;
input p_62_out;
input p_102_out;
input [0:0]S_AXI_ARREADY;
input [0:0]s_axi_arvalid;
input \gen_multi_thread.accept_cnt_reg[0] ;
input \m_payload_i_reg[34]_4 ;
input [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
input p_40_out;
input m_valid_i_reg;
input p_82_out;
input m_valid_i_reg_0;
input [0:0]SR;
input aclk;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]SR;
wire [0:0]S_AXI_ARREADY;
wire aa_mi_arvalid;
wire aclk;
wire aresetn_d;
wire [46:0]f_mux4_return;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.accept_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ;
wire \gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ;
wire \gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ;
wire \gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ;
wire \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ;
wire last_rr_hot;
wire \last_rr_hot[0]_i_2_n_0 ;
wire \last_rr_hot[0]_i_3_n_0 ;
wire \last_rr_hot[1]_i_2_n_0 ;
wire \last_rr_hot[2]_i_3_n_0 ;
wire \last_rr_hot[3]_i_2_n_0 ;
wire \last_rr_hot[3]_i_3_n_0 ;
wire \last_rr_hot[4]_i_4_n_0 ;
wire \last_rr_hot[4]_i_5_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[0]_2 ;
wire [0:0]\m_payload_i_reg[34] ;
wire [0:0]\m_payload_i_reg[34]_0 ;
wire [0:0]\m_payload_i_reg[34]_1 ;
wire [0:0]\m_payload_i_reg[34]_2 ;
wire [0:0]\m_payload_i_reg[34]_3 ;
wire \m_payload_i_reg[34]_4 ;
wire m_valid_i;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire match;
wire need_arbitration;
wire [4:0]next_rr_hot;
wire [3:1]p_0_in1_in;
wire p_102_out;
wire p_122_out;
wire p_40_out;
wire p_5_in6_in;
wire p_62_out;
wire p_6_in;
wire p_7_in9_in;
wire p_82_out;
wire p_8_in;
wire r_cmd_pop_4__1;
wire [0:0]r_issuing_cnt;
wire [0:0]resp_select;
wire [1:0]resp_select__0;
wire [0:0]s_axi_arvalid;
wire [0:0]s_axi_rready;
wire \s_axi_rvalid[0] ;
wire [47:0]st_mr_rid;
wire [135:0]st_mr_rmesg;
LUT6 #(
.INIT(64'hBBBBBBBBBBBBBBB8))
\chosen[4]_i_1__0
(.I0(s_axi_rready),
.I1(\s_axi_rvalid[0] ),
.I2(p_40_out),
.I3(p_122_out),
.I4(p_102_out),
.I5(m_valid_i_reg),
.O(need_arbitration));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[0]),
.Q(Q[0]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[1]),
.Q(Q[1]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[2]),
.Q(Q[2]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[3]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[3]),
.Q(Q[3]),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[4]
(.C(aclk),
.CE(need_arbitration),
.D(next_rr_hot[4]),
.Q(Q[4]),
.R(SR));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0
(.I0(st_mr_rid[36]),
.I1(st_mr_rid[0]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[24]),
.I5(st_mr_rid[12]),
.O(f_mux4_return[0]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0
(.I0(st_mr_rid[46]),
.I1(st_mr_rid[10]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[34]),
.I5(st_mr_rid[22]),
.O(f_mux4_return[10]));
LUT2 #(
.INIT(4'h8))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0
(.I0(Q[4]),
.I1(p_40_out),
.O(resp_select));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0
(.I0(st_mr_rid[47]),
.I1(st_mr_rid[11]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[35]),
.I5(st_mr_rid[23]),
.O(f_mux4_return[11]));
LUT4 #(
.INIT(16'hF888))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0
(.I0(p_62_out),
.I1(Q[3]),
.I2(p_102_out),
.I3(Q[1]),
.O(resp_select__0[0]));
LUT4 #(
.INIT(16'hF888))
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4
(.I0(p_62_out),
.I1(Q[3]),
.I2(p_82_out),
.I3(Q[2]),
.O(resp_select__0[1]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0
(.I0(st_mr_rmesg[102]),
.I1(st_mr_rmesg[0]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[68]),
.I5(st_mr_rmesg[34]),
.O(f_mux4_return[12]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0
(.I0(st_mr_rmesg[103]),
.I1(st_mr_rmesg[1]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[69]),
.I5(st_mr_rmesg[35]),
.O(f_mux4_return[13]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1
(.I0(st_mr_rmesg[104]),
.I1(st_mr_rmesg[2]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[70]),
.I5(st_mr_rmesg[36]),
.O(f_mux4_return[14]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1
(.I0(st_mr_rmesg[105]),
.I1(st_mr_rmesg[3]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[71]),
.I5(st_mr_rmesg[37]),
.O(f_mux4_return[15]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1
(.I0(st_mr_rmesg[106]),
.I1(st_mr_rmesg[4]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[72]),
.I5(st_mr_rmesg[38]),
.O(f_mux4_return[16]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1
(.I0(st_mr_rmesg[107]),
.I1(st_mr_rmesg[5]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[73]),
.I5(st_mr_rmesg[39]),
.O(f_mux4_return[17]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1
(.I0(st_mr_rmesg[108]),
.I1(st_mr_rmesg[6]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[74]),
.I5(st_mr_rmesg[40]),
.O(f_mux4_return[18]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0
(.I0(st_mr_rid[37]),
.I1(st_mr_rid[1]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[25]),
.I5(st_mr_rid[13]),
.O(f_mux4_return[1]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1
(.I0(st_mr_rmesg[109]),
.I1(st_mr_rmesg[7]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[75]),
.I5(st_mr_rmesg[41]),
.O(f_mux4_return[19]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1
(.I0(st_mr_rmesg[110]),
.I1(st_mr_rmesg[8]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[76]),
.I5(st_mr_rmesg[42]),
.O(f_mux4_return[20]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1
(.I0(st_mr_rmesg[111]),
.I1(st_mr_rmesg[9]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[77]),
.I5(st_mr_rmesg[43]),
.O(f_mux4_return[21]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1
(.I0(st_mr_rmesg[112]),
.I1(st_mr_rmesg[10]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[78]),
.I5(st_mr_rmesg[44]),
.O(f_mux4_return[22]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1
(.I0(st_mr_rmesg[113]),
.I1(st_mr_rmesg[11]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[79]),
.I5(st_mr_rmesg[45]),
.O(f_mux4_return[23]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1
(.I0(st_mr_rmesg[114]),
.I1(st_mr_rmesg[12]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[80]),
.I5(st_mr_rmesg[46]),
.O(f_mux4_return[24]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1
(.I0(st_mr_rmesg[115]),
.I1(st_mr_rmesg[13]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[81]),
.I5(st_mr_rmesg[47]),
.O(f_mux4_return[25]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1
(.I0(st_mr_rmesg[116]),
.I1(st_mr_rmesg[14]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[82]),
.I5(st_mr_rmesg[48]),
.O(f_mux4_return[26]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1
(.I0(st_mr_rmesg[117]),
.I1(st_mr_rmesg[15]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[83]),
.I5(st_mr_rmesg[49]),
.O(f_mux4_return[27]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1
(.I0(st_mr_rmesg[118]),
.I1(st_mr_rmesg[16]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[84]),
.I5(st_mr_rmesg[50]),
.O(f_mux4_return[28]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0
(.I0(st_mr_rid[38]),
.I1(st_mr_rid[2]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[26]),
.I5(st_mr_rid[14]),
.O(f_mux4_return[2]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1
(.I0(st_mr_rmesg[119]),
.I1(st_mr_rmesg[17]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[85]),
.I5(st_mr_rmesg[51]),
.O(f_mux4_return[29]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1
(.I0(st_mr_rmesg[120]),
.I1(st_mr_rmesg[18]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[86]),
.I5(st_mr_rmesg[52]),
.O(f_mux4_return[30]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1
(.I0(st_mr_rmesg[121]),
.I1(st_mr_rmesg[19]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[87]),
.I5(st_mr_rmesg[53]),
.O(f_mux4_return[31]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1
(.I0(st_mr_rmesg[122]),
.I1(st_mr_rmesg[20]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[88]),
.I5(st_mr_rmesg[54]),
.O(f_mux4_return[32]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1
(.I0(st_mr_rmesg[123]),
.I1(st_mr_rmesg[21]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[89]),
.I5(st_mr_rmesg[55]),
.O(f_mux4_return[33]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1
(.I0(st_mr_rmesg[124]),
.I1(st_mr_rmesg[22]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[90]),
.I5(st_mr_rmesg[56]),
.O(f_mux4_return[34]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1
(.I0(st_mr_rmesg[125]),
.I1(st_mr_rmesg[23]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[91]),
.I5(st_mr_rmesg[57]),
.O(f_mux4_return[35]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1
(.I0(st_mr_rmesg[126]),
.I1(st_mr_rmesg[24]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[92]),
.I5(st_mr_rmesg[58]),
.O(f_mux4_return[36]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1
(.I0(st_mr_rmesg[127]),
.I1(st_mr_rmesg[25]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[93]),
.I5(st_mr_rmesg[59]),
.O(f_mux4_return[37]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1
(.I0(st_mr_rmesg[128]),
.I1(st_mr_rmesg[26]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[94]),
.I5(st_mr_rmesg[60]),
.O(f_mux4_return[38]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0
(.I0(st_mr_rid[39]),
.I1(st_mr_rid[3]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[27]),
.I5(st_mr_rid[15]),
.O(f_mux4_return[3]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1
(.I0(st_mr_rmesg[129]),
.I1(st_mr_rmesg[27]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[95]),
.I5(st_mr_rmesg[61]),
.O(f_mux4_return[39]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1
(.I0(st_mr_rmesg[130]),
.I1(st_mr_rmesg[28]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[96]),
.I5(st_mr_rmesg[62]),
.O(f_mux4_return[40]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1
(.I0(st_mr_rmesg[131]),
.I1(st_mr_rmesg[29]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[97]),
.I5(st_mr_rmesg[63]),
.O(f_mux4_return[41]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1
(.I0(st_mr_rmesg[132]),
.I1(st_mr_rmesg[30]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[98]),
.I5(st_mr_rmesg[64]),
.O(f_mux4_return[42]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1
(.I0(st_mr_rmesg[133]),
.I1(st_mr_rmesg[31]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[99]),
.I5(st_mr_rmesg[65]),
.O(f_mux4_return[43]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1
(.I0(st_mr_rmesg[134]),
.I1(st_mr_rmesg[32]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[100]),
.I5(st_mr_rmesg[66]),
.O(f_mux4_return[44]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1
(.I0(st_mr_rmesg[135]),
.I1(st_mr_rmesg[33]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rmesg[101]),
.I5(st_mr_rmesg[67]),
.O(f_mux4_return[45]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1
(.I0(\m_payload_i_reg[34]_0 ),
.I1(\m_payload_i_reg[34]_1 ),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(\m_payload_i_reg[34]_2 ),
.I5(\m_payload_i_reg[34]_3 ),
.O(f_mux4_return[46]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0
(.I0(st_mr_rid[40]),
.I1(st_mr_rid[4]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[28]),
.I5(st_mr_rid[16]),
.O(f_mux4_return[4]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0
(.I0(st_mr_rid[41]),
.I1(st_mr_rid[5]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[29]),
.I5(st_mr_rid[17]),
.O(f_mux4_return[5]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0
(.I0(st_mr_rid[42]),
.I1(st_mr_rid[6]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[30]),
.I5(st_mr_rid[18]),
.O(f_mux4_return[6]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0
(.I0(st_mr_rid[43]),
.I1(st_mr_rid[7]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[31]),
.I5(st_mr_rid[19]),
.O(f_mux4_return[7]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0
(.I0(st_mr_rid[44]),
.I1(st_mr_rid[8]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[32]),
.I5(st_mr_rid[20]),
.O(f_mux4_return[8]));
LUT6 #(
.INIT(64'hAFFCA0FCAF0CA00C))
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0
(.I0(st_mr_rid[45]),
.I1(st_mr_rid[9]),
.I2(resp_select__0[0]),
.I3(resp_select__0[1]),
.I4(st_mr_rid[33]),
.I5(st_mr_rid[21]),
.O(f_mux4_return[9]));
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1__0
(.I0(m_valid_i),
.I1(aresetn_d),
.O(E));
LUT6 #(
.INIT(64'h4440404044444444))
\gen_no_arbiter.s_ready_i[0]_i_24__0
(.I0(S_AXI_ARREADY),
.I1(s_axi_arvalid),
.I2(\gen_multi_thread.accept_cnt_reg[0] ),
.I3(\s_axi_rvalid[0] ),
.I4(\m_payload_i_reg[34]_4 ),
.I5(\gen_multi_thread.accept_cnt_reg[3] ),
.O(\gen_no_arbiter.s_ready_i[0]_i_24__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_no_arbiter.s_ready_i[0]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] ),
.I5(aa_mi_arvalid),
.O(m_valid_i));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8AAAA))
\gen_no_arbiter.s_ready_i[0]_i_6__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_24__0_n_0 ),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.I2(\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.I3(r_cmd_pop_4__1),
.I4(match),
.I5(r_issuing_cnt),
.O(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[0]_i_1
(.I0(p_122_out),
.I1(p_62_out),
.I2(p_40_out),
.I3(\last_rr_hot[0]_i_2_n_0 ),
.I4(\last_rr_hot[0]_i_3_n_0 ),
.I5(p_6_in),
.O(next_rr_hot[0]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[0]_i_2
(.I0(p_5_in6_in),
.I1(\last_rr_hot_reg_n_0_[0] ),
.I2(p_102_out),
.I3(p_82_out),
.O(\last_rr_hot[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[0]_i_3
(.I0(p_40_out),
.I1(p_7_in9_in),
.I2(p_8_in),
.O(\last_rr_hot[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[1]_i_1
(.I0(p_102_out),
.I1(p_40_out),
.I2(p_122_out),
.I3(\last_rr_hot[1]_i_2_n_0 ),
.I4(\last_rr_hot[4]_i_4_n_0 ),
.I5(p_7_in9_in),
.O(next_rr_hot[1]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[1]_i_2
(.I0(p_6_in),
.I1(p_5_in6_in),
.I2(p_82_out),
.I3(p_62_out),
.O(\last_rr_hot[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAA2222AAAA0020))
\last_rr_hot[2]_i_1
(.I0(p_82_out),
.I1(m_valid_i_reg_0),
.I2(\last_rr_hot[4]_i_5_n_0 ),
.I3(p_40_out),
.I4(\last_rr_hot[2]_i_3_n_0 ),
.I5(p_8_in),
.O(next_rr_hot[2]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[2]_i_3
(.I0(p_102_out),
.I1(\last_rr_hot_reg_n_0_[0] ),
.I2(p_5_in6_in),
.O(\last_rr_hot[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAAA0202AAAA0200))
\last_rr_hot[3]_i_1
(.I0(p_62_out),
.I1(p_102_out),
.I2(p_82_out),
.I3(\last_rr_hot[3]_i_2_n_0 ),
.I4(\last_rr_hot[3]_i_3_n_0 ),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[3]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'h00AE))
\last_rr_hot[3]_i_2
(.I0(p_8_in),
.I1(p_7_in9_in),
.I2(p_40_out),
.I3(p_122_out),
.O(\last_rr_hot[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[3]_i_3
(.I0(p_82_out),
.I1(p_5_in6_in),
.I2(p_6_in),
.O(\last_rr_hot[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA8))
\last_rr_hot[4]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[3]),
.I2(next_rr_hot[2]),
.I3(next_rr_hot[1]),
.I4(next_rr_hot[0]),
.I5(next_rr_hot[4]),
.O(last_rr_hot));
LUT6 #(
.INIT(64'hAAAA2222AAAA0020))
\last_rr_hot[4]_i_2
(.I0(p_40_out),
.I1(m_valid_i_reg),
.I2(\last_rr_hot[4]_i_4_n_0 ),
.I3(p_102_out),
.I4(\last_rr_hot[4]_i_5_n_0 ),
.I5(p_5_in6_in),
.O(next_rr_hot[4]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[4]_i_4
(.I0(p_122_out),
.I1(p_8_in),
.I2(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT3 #(
.INIT(8'hF4))
\last_rr_hot[4]_i_5
(.I0(p_62_out),
.I1(p_6_in),
.I2(p_7_in9_in),
.O(\last_rr_hot[4]_i_5_n_0 ));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[0]),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[1]),
.Q(p_5_in6_in),
.R(SR));
FDRE \last_rr_hot_reg[2]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[2]),
.Q(p_6_in),
.R(SR));
FDRE \last_rr_hot_reg[3]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[3]),
.Q(p_7_in9_in),
.R(SR));
FDSE \last_rr_hot_reg[4]
(.C(aclk),
.CE(last_rr_hot),
.D(next_rr_hot[4]),
.Q(p_8_in),
.S(SR));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1
(.I0(Q[0]),
.I1(s_axi_rready),
.I2(p_122_out),
.O(\m_payload_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__0
(.I0(Q[1]),
.I1(s_axi_rready),
.I2(p_102_out),
.O(\m_payload_i_reg[0]_0 ));
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__1
(.I0(Q[4]),
.I1(s_axi_rready),
.I2(p_40_out),
.O(\m_payload_i_reg[34] ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__2
(.I0(Q[3]),
.I1(s_axi_rready),
.I2(p_62_out),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__3
(.I0(Q[2]),
.I1(s_axi_rready),
.I2(p_82_out),
.O(\m_payload_i_reg[0]_2 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF8))
\s_axi_rvalid[0]_INST_0
(.I0(Q[0]),
.I1(p_122_out),
.I2(p_0_in1_in[2]),
.I3(p_0_in1_in[1]),
.I4(p_0_in1_in[3]),
.I5(resp_select),
.O(\s_axi_rvalid[0] ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0_i_1
(.I0(Q[2]),
.I1(p_82_out),
.O(p_0_in1_in[2]));
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0_i_2
(.I0(Q[1]),
.I1(p_102_out),
.O(p_0_in1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0_i_3
(.I0(Q[3]),
.I1(p_62_out),
.O(p_0_in1_in[3]));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "1" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000" *) (* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "4" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *) (* C_S_AXI_THREAD_ID_WIDTH = "12" *) (* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "4'b1111" *)
(* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [47:0]m_axi_awid;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awuser;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [47:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wuser;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [3:0]m_axi_buser;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [47:0]m_axi_arid;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_aruser;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [47:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_ruser;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [127:96]\^m_axi_araddr ;
wire [7:6]\^m_axi_arburst ;
wire [15:12]\^m_axi_arcache ;
wire [11:0]\^m_axi_arid ;
wire [7:0]\^m_axi_arlen ;
wire [3:3]\^m_axi_arlock ;
wire [11:9]\^m_axi_arprot ;
wire [15:12]\^m_axi_arqos ;
wire [3:0]m_axi_arready;
wire [11:9]\^m_axi_arsize ;
wire [3:0]m_axi_arvalid;
wire [127:96]\^m_axi_awaddr ;
wire [7:6]\^m_axi_awburst ;
wire [15:12]\^m_axi_awcache ;
wire [11:0]\^m_axi_awid ;
wire [31:24]\^m_axi_awlen ;
wire [3:3]\^m_axi_awlock ;
wire [11:9]\^m_axi_awprot ;
wire [15:12]\^m_axi_awqos ;
wire [3:0]m_axi_awready;
wire [11:9]\^m_axi_awsize ;
wire [3:0]m_axi_awvalid;
wire [47:0]m_axi_bid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [47:0]m_axi_rid;
wire [3:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[127:96] = \^m_axi_araddr [127:96];
assign m_axi_araddr[95:64] = \^m_axi_araddr [127:96];
assign m_axi_araddr[63:32] = \^m_axi_araddr [127:96];
assign m_axi_araddr[31:0] = \^m_axi_araddr [127:96];
assign m_axi_arburst[7:6] = \^m_axi_arburst [7:6];
assign m_axi_arburst[5:4] = \^m_axi_arburst [7:6];
assign m_axi_arburst[3:2] = \^m_axi_arburst [7:6];
assign m_axi_arburst[1:0] = \^m_axi_arburst [7:6];
assign m_axi_arcache[15:12] = \^m_axi_arcache [15:12];
assign m_axi_arcache[11:8] = \^m_axi_arcache [15:12];
assign m_axi_arcache[7:4] = \^m_axi_arcache [15:12];
assign m_axi_arcache[3:0] = \^m_axi_arcache [15:12];
assign m_axi_arid[47:36] = \^m_axi_arid [11:0];
assign m_axi_arid[35:24] = \^m_axi_arid [11:0];
assign m_axi_arid[23:12] = \^m_axi_arid [11:0];
assign m_axi_arid[11:0] = \^m_axi_arid [11:0];
assign m_axi_arlen[31:24] = \^m_axi_arlen [7:0];
assign m_axi_arlen[23:16] = \^m_axi_arlen [7:0];
assign m_axi_arlen[15:8] = \^m_axi_arlen [7:0];
assign m_axi_arlen[7:0] = \^m_axi_arlen [7:0];
assign m_axi_arlock[3] = \^m_axi_arlock [3];
assign m_axi_arlock[2] = \^m_axi_arlock [3];
assign m_axi_arlock[1] = \^m_axi_arlock [3];
assign m_axi_arlock[0] = \^m_axi_arlock [3];
assign m_axi_arprot[11:9] = \^m_axi_arprot [11:9];
assign m_axi_arprot[8:6] = \^m_axi_arprot [11:9];
assign m_axi_arprot[5:3] = \^m_axi_arprot [11:9];
assign m_axi_arprot[2:0] = \^m_axi_arprot [11:9];
assign m_axi_arqos[15:12] = \^m_axi_arqos [15:12];
assign m_axi_arqos[11:8] = \^m_axi_arqos [15:12];
assign m_axi_arqos[7:4] = \^m_axi_arqos [15:12];
assign m_axi_arqos[3:0] = \^m_axi_arqos [15:12];
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
assign m_axi_arregion[12] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[11:9] = \^m_axi_arsize [11:9];
assign m_axi_arsize[8:6] = \^m_axi_arsize [11:9];
assign m_axi_arsize[5:3] = \^m_axi_arsize [11:9];
assign m_axi_arsize[2:0] = \^m_axi_arsize [11:9];
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[127:96] = \^m_axi_awaddr [127:96];
assign m_axi_awaddr[95:64] = \^m_axi_awaddr [127:96];
assign m_axi_awaddr[63:32] = \^m_axi_awaddr [127:96];
assign m_axi_awaddr[31:0] = \^m_axi_awaddr [127:96];
assign m_axi_awburst[7:6] = \^m_axi_awburst [7:6];
assign m_axi_awburst[5:4] = \^m_axi_awburst [7:6];
assign m_axi_awburst[3:2] = \^m_axi_awburst [7:6];
assign m_axi_awburst[1:0] = \^m_axi_awburst [7:6];
assign m_axi_awcache[15:12] = \^m_axi_awcache [15:12];
assign m_axi_awcache[11:8] = \^m_axi_awcache [15:12];
assign m_axi_awcache[7:4] = \^m_axi_awcache [15:12];
assign m_axi_awcache[3:0] = \^m_axi_awcache [15:12];
assign m_axi_awid[47:36] = \^m_axi_awid [11:0];
assign m_axi_awid[35:24] = \^m_axi_awid [11:0];
assign m_axi_awid[23:12] = \^m_axi_awid [11:0];
assign m_axi_awid[11:0] = \^m_axi_awid [11:0];
assign m_axi_awlen[31:24] = \^m_axi_awlen [31:24];
assign m_axi_awlen[23:16] = \^m_axi_awlen [31:24];
assign m_axi_awlen[15:8] = \^m_axi_awlen [31:24];
assign m_axi_awlen[7:0] = \^m_axi_awlen [31:24];
assign m_axi_awlock[3] = \^m_axi_awlock [3];
assign m_axi_awlock[2] = \^m_axi_awlock [3];
assign m_axi_awlock[1] = \^m_axi_awlock [3];
assign m_axi_awlock[0] = \^m_axi_awlock [3];
assign m_axi_awprot[11:9] = \^m_axi_awprot [11:9];
assign m_axi_awprot[8:6] = \^m_axi_awprot [11:9];
assign m_axi_awprot[5:3] = \^m_axi_awprot [11:9];
assign m_axi_awprot[2:0] = \^m_axi_awprot [11:9];
assign m_axi_awqos[15:12] = \^m_axi_awqos [15:12];
assign m_axi_awqos[11:8] = \^m_axi_awqos [15:12];
assign m_axi_awqos[7:4] = \^m_axi_awqos [15:12];
assign m_axi_awqos[3:0] = \^m_axi_awqos [15:12];
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
assign m_axi_awregion[12] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[11:9] = \^m_axi_awsize [11:9];
assign m_axi_awsize[8:6] = \^m_axi_awsize [11:9];
assign m_axi_awsize[5:3] = \^m_axi_awsize [11:9];
assign m_axi_awsize[2:0] = \^m_axi_awsize [11:9];
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[127:96] = s_axi_wdata;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[47] = \<const0> ;
assign m_axi_wid[46] = \<const0> ;
assign m_axi_wid[45] = \<const0> ;
assign m_axi_wid[44] = \<const0> ;
assign m_axi_wid[43] = \<const0> ;
assign m_axi_wid[42] = \<const0> ;
assign m_axi_wid[41] = \<const0> ;
assign m_axi_wid[40] = \<const0> ;
assign m_axi_wid[39] = \<const0> ;
assign m_axi_wid[38] = \<const0> ;
assign m_axi_wid[37] = \<const0> ;
assign m_axi_wid[36] = \<const0> ;
assign m_axi_wid[35] = \<const0> ;
assign m_axi_wid[34] = \<const0> ;
assign m_axi_wid[33] = \<const0> ;
assign m_axi_wid[32] = \<const0> ;
assign m_axi_wid[31] = \<const0> ;
assign m_axi_wid[30] = \<const0> ;
assign m_axi_wid[29] = \<const0> ;
assign m_axi_wid[28] = \<const0> ;
assign m_axi_wid[27] = \<const0> ;
assign m_axi_wid[26] = \<const0> ;
assign m_axi_wid[25] = \<const0> ;
assign m_axi_wid[24] = \<const0> ;
assign m_axi_wid[23] = \<const0> ;
assign m_axi_wid[22] = \<const0> ;
assign m_axi_wid[21] = \<const0> ;
assign m_axi_wid[20] = \<const0> ;
assign m_axi_wid[19] = \<const0> ;
assign m_axi_wid[18] = \<const0> ;
assign m_axi_wid[17] = \<const0> ;
assign m_axi_wid[16] = \<const0> ;
assign m_axi_wid[15] = \<const0> ;
assign m_axi_wid[14] = \<const0> ;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[3] = s_axi_wlast;
assign m_axi_wlast[2] = s_axi_wlast;
assign m_axi_wlast[1] = s_axi_wlast;
assign m_axi_wlast[0] = s_axi_wlast;
assign m_axi_wstrb[15:12] = s_axi_wstrb;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar \gen_samd.crossbar_samd
(.D({s_axi_awqos,s_axi_awcache,s_axi_awburst,s_axi_awprot,s_axi_awlock,s_axi_awsize,s_axi_awlen,s_axi_awaddr,s_axi_awid}),
.M_AXI_RREADY(m_axi_rready),
.Q({\^m_axi_awqos ,\^m_axi_awcache ,\^m_axi_awburst ,\^m_axi_awprot ,\^m_axi_awlock ,\^m_axi_awsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_awid }),
.S_AXI_ARREADY(s_axi_arready),
.aclk(aclk),
.aresetn(aresetn),
.\m_axi_arqos[15] ({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_arlen ,\^m_axi_araddr ,\^m_axi_arid }),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.\s_axi_arqos[3] ({s_axi_arqos,s_axi_arcache,s_axi_arburst,s_axi_arprot,s_axi_arlock,s_axi_arsize,s_axi_arlen,s_axi_araddr,s_axi_arid}),
.s_axi_arvalid(s_axi_arvalid),
.\s_axi_awready[0] (s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[0] (s_axi_bid[0]),
.\s_axi_bid[10] (s_axi_bid[10]),
.\s_axi_bid[11] (s_axi_bid[11]),
.\s_axi_bid[1] (s_axi_bid[1]),
.\s_axi_bid[2] (s_axi_bid[2]),
.\s_axi_bid[3] (s_axi_bid[3]),
.\s_axi_bid[4] (s_axi_bid[4]),
.\s_axi_bid[5] (s_axi_bid[5]),
.\s_axi_bid[6] (s_axi_bid[6]),
.\s_axi_bid[7] (s_axi_bid[7]),
.\s_axi_bid[8] (s_axi_bid[8]),
.\s_axi_bid[9] (s_axi_bid[9]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.\s_axi_bvalid[0] (s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rid[0] (s_axi_rid[0]),
.\s_axi_rid[10] (s_axi_rid[10]),
.\s_axi_rid[11] (s_axi_rid[11]),
.\s_axi_rid[1] (s_axi_rid[1]),
.\s_axi_rid[2] (s_axi_rid[2]),
.\s_axi_rid[3] (s_axi_rid[3]),
.\s_axi_rid[4] (s_axi_rid[4]),
.\s_axi_rid[5] (s_axi_rid[5]),
.\s_axi_rid[6] (s_axi_rid[6]),
.\s_axi_rid[7] (s_axi_rid[7]),
.\s_axi_rid[8] (s_axi_rid[8]),
.\s_axi_rid[9] (s_axi_rid[9]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.\s_axi_rvalid[0] (s_axi_rvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar
(M_AXI_RREADY,
Q,
\m_axi_arqos[15] ,
S_AXI_ARREADY,
\s_axi_rid[0] ,
\s_axi_rid[1] ,
\s_axi_rid[2] ,
\s_axi_rid[3] ,
\s_axi_rid[4] ,
\s_axi_rid[5] ,
\s_axi_rid[6] ,
\s_axi_rid[7] ,
\s_axi_rid[8] ,
\s_axi_rid[9] ,
\s_axi_rid[10] ,
\s_axi_rid[11] ,
s_axi_rresp,
s_axi_rdata,
s_axi_rlast,
\s_axi_bid[0] ,
\s_axi_bid[1] ,
\s_axi_bid[2] ,
\s_axi_bid[3] ,
\s_axi_bid[4] ,
\s_axi_bid[5] ,
\s_axi_bid[6] ,
\s_axi_bid[7] ,
\s_axi_bid[8] ,
\s_axi_bid[9] ,
\s_axi_bid[10] ,
\s_axi_bid[11] ,
s_axi_bresp,
m_axi_bready,
m_axi_awvalid,
\s_axi_awready[0] ,
\s_axi_bvalid[0] ,
\s_axi_rvalid[0] ,
m_axi_wvalid,
s_axi_wready,
m_axi_arvalid,
m_axi_bvalid,
s_axi_bready,
s_axi_rready,
m_axi_rvalid,
s_axi_awvalid,
aclk,
D,
\s_axi_arqos[3] ,
m_axi_bid,
m_axi_bresp,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
aresetn,
m_axi_awready,
m_axi_arready,
s_axi_arvalid,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready);
output [3:0]M_AXI_RREADY;
output [68:0]Q;
output [68:0]\m_axi_arqos[15] ;
output [0:0]S_AXI_ARREADY;
output \s_axi_rid[0] ;
output \s_axi_rid[1] ;
output \s_axi_rid[2] ;
output \s_axi_rid[3] ;
output \s_axi_rid[4] ;
output \s_axi_rid[5] ;
output \s_axi_rid[6] ;
output \s_axi_rid[7] ;
output \s_axi_rid[8] ;
output \s_axi_rid[9] ;
output \s_axi_rid[10] ;
output \s_axi_rid[11] ;
output [1:0]s_axi_rresp;
output [31:0]s_axi_rdata;
output [0:0]s_axi_rlast;
output \s_axi_bid[0] ;
output \s_axi_bid[1] ;
output \s_axi_bid[2] ;
output \s_axi_bid[3] ;
output \s_axi_bid[4] ;
output \s_axi_bid[5] ;
output \s_axi_bid[6] ;
output \s_axi_bid[7] ;
output \s_axi_bid[8] ;
output \s_axi_bid[9] ;
output \s_axi_bid[10] ;
output \s_axi_bid[11] ;
output [1:0]s_axi_bresp;
output [3:0]m_axi_bready;
output [3:0]m_axi_awvalid;
output \s_axi_awready[0] ;
output \s_axi_bvalid[0] ;
output \s_axi_rvalid[0] ;
output [3:0]m_axi_wvalid;
output [0:0]s_axi_wready;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_rready;
input [3:0]m_axi_rvalid;
input [0:0]s_axi_awvalid;
input aclk;
input [68:0]D;
input [68:0]\s_axi_arqos[3] ;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [47:0]m_axi_rid;
input [3:0]m_axi_rlast;
input [7:0]m_axi_rresp;
input [127:0]m_axi_rdata;
input aresetn;
input [3:0]m_axi_awready;
input [3:0]m_axi_arready;
input [0:0]s_axi_arvalid;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [3:0]m_axi_wready;
wire [68:0]D;
wire [3:0]M_AXI_RREADY;
wire [68:0]Q;
wire [0:0]S_AXI_ARREADY;
wire [4:4]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire [4:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire addr_arbiter_ar_n_79;
wire addr_arbiter_ar_n_80;
wire addr_arbiter_ar_n_81;
wire addr_arbiter_ar_n_82;
wire addr_arbiter_ar_n_83;
wire addr_arbiter_ar_n_84;
wire addr_arbiter_ar_n_85;
wire addr_arbiter_ar_n_86;
wire addr_arbiter_ar_n_87;
wire addr_arbiter_ar_n_88;
wire addr_arbiter_ar_n_89;
wire addr_arbiter_ar_n_90;
wire addr_arbiter_ar_n_99;
wire addr_arbiter_aw_n_23;
wire addr_arbiter_aw_n_25;
wire aresetn;
wire aresetn_d;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2 ;
wire \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[0].reg_slice_mi_n_4 ;
wire \gen_master_slots[0].reg_slice_mi_n_54 ;
wire \gen_master_slots[0].reg_slice_mi_n_55 ;
wire \gen_master_slots[0].reg_slice_mi_n_6 ;
wire \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[1].reg_slice_mi_n_4 ;
wire \gen_master_slots[1].reg_slice_mi_n_53 ;
wire \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0 ;
wire \gen_master_slots[2].reg_slice_mi_n_4 ;
wire \gen_master_slots[2].reg_slice_mi_n_53 ;
wire \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0 ;
wire \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0 ;
wire \gen_master_slots[3].reg_slice_mi_n_5 ;
wire \gen_master_slots[3].reg_slice_mi_n_55 ;
wire \gen_master_slots[3].reg_slice_mi_n_56 ;
wire \gen_master_slots[3].reg_slice_mi_n_57 ;
wire \gen_master_slots[3].reg_slice_mi_n_7 ;
wire \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0 ;
wire \gen_master_slots[4].reg_slice_mi_n_1 ;
wire \gen_master_slots[4].reg_slice_mi_n_5 ;
wire [4:0]\gen_multi_thread.arbiter_resp_inst/chosen ;
wire [4:0]\gen_multi_thread.arbiter_resp_inst/chosen_9 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21 ;
wire [68:0]\m_axi_arqos[15] ;
wire [3:0]m_axi_arready;
wire [3:0]m_axi_arvalid;
wire [3:0]m_axi_awready;
wire [3:0]m_axi_awvalid;
wire [47:0]m_axi_bid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [47:0]m_axi_rid;
wire [3:0]m_axi_rlast;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:0]m_ready_d_12;
wire m_valid_i;
wire m_valid_i_10;
wire match;
wire match_3;
wire mi_arready_4;
wire mi_awready_4;
wire mi_awready_mux__3;
wire mi_bready_4;
wire mi_rready_4;
wire p_101_in;
wire p_102_out;
wire p_104_out;
wire p_108_out;
wire p_122_out;
wire p_124_out;
wire p_128_out;
wire p_1_in;
wire p_22_in;
wire p_23_in;
wire p_25_in;
wire [11:0]p_28_in;
wire p_29_in;
wire [11:0]p_32_in;
wire p_39_in;
wire p_40_out;
wire p_42_out;
wire p_46_out;
wire p_48_in;
wire p_57_in;
wire p_62_out;
wire p_64_out;
wire p_66_in;
wire p_68_out;
wire p_75_in;
wire p_82_out;
wire p_84_in;
wire p_84_out;
wire p_88_out;
wire p_93_in;
wire r_cmd_pop_0__1;
wire r_cmd_pop_1__1;
wire r_cmd_pop_2__1;
wire r_cmd_pop_3__1;
wire r_cmd_pop_4__1;
wire [32:0]r_issuing_cnt;
wire \r_pipe/p_1_in ;
wire \r_pipe/p_1_in_5 ;
wire \r_pipe/p_1_in_6 ;
wire \r_pipe/p_1_in_7 ;
wire \r_pipe/p_1_in_8 ;
wire read_cs__0;
wire reset;
wire [68:0]\s_axi_arqos[3] ;
wire [0:0]s_axi_arvalid;
wire \s_axi_awready[0] ;
wire [0:0]s_axi_awvalid;
wire \s_axi_bid[0] ;
wire \s_axi_bid[10] ;
wire \s_axi_bid[11] ;
wire \s_axi_bid[1] ;
wire \s_axi_bid[2] ;
wire \s_axi_bid[3] ;
wire \s_axi_bid[4] ;
wire \s_axi_bid[5] ;
wire \s_axi_bid[6] ;
wire \s_axi_bid[7] ;
wire \s_axi_bid[8] ;
wire \s_axi_bid[9] ;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bvalid[0] ;
wire [31:0]s_axi_rdata;
wire \s_axi_rid[0] ;
wire \s_axi_rid[10] ;
wire \s_axi_rid[11] ;
wire \s_axi_rid[1] ;
wire \s_axi_rid[2] ;
wire \s_axi_rid[3] ;
wire \s_axi_rid[4] ;
wire \s_axi_rid[5] ;
wire \s_axi_rid[6] ;
wire \s_axi_rid[7] ;
wire \s_axi_rid[8] ;
wire \s_axi_rid[9] ;
wire [0:0]s_axi_rlast;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire \s_axi_rvalid[0] ;
wire s_axi_rvalid_i;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i0;
wire s_ready_i0_11;
wire [0:0]s_ready_i0__1;
wire sa_wm_awready_mux__3;
wire splitter_aw_mi_n_0;
wire splitter_aw_mi_n_1;
wire splitter_aw_mi_n_10;
wire splitter_aw_mi_n_11;
wire splitter_aw_mi_n_12;
wire splitter_aw_mi_n_2;
wire splitter_aw_mi_n_3;
wire splitter_aw_mi_n_4;
wire splitter_aw_mi_n_5;
wire splitter_aw_mi_n_6;
wire splitter_aw_mi_n_7;
wire splitter_aw_mi_n_8;
wire splitter_aw_mi_n_9;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [1:0]st_aa_awtarget_enc;
wire [59:0]st_mr_bid;
wire [10:0]st_mr_bmesg;
wire [59:0]st_mr_rid;
wire [139:0]st_mr_rmesg;
wire [32:0]w_issuing_cnt;
wire write_cs01_out;
wire write_cs0__0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter addr_arbiter_ar
(.ADDRESS_HIT_0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.D({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 }),
.E(s_ready_i0),
.Q(aa_mi_artarget_hot),
.SR(reset),
.S_AXI_ARREADY(S_AXI_ARREADY),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.\gen_axi.s_axi_rid_i_reg[11] (s_axi_rvalid_i),
.\gen_master_slots[0].r_issuing_cnt_reg[3] ({addr_arbiter_ar_n_79,addr_arbiter_ar_n_80,addr_arbiter_ar_n_81}),
.\gen_master_slots[1].r_issuing_cnt_reg[11] ({addr_arbiter_ar_n_82,addr_arbiter_ar_n_83,addr_arbiter_ar_n_84}),
.\gen_master_slots[2].r_issuing_cnt_reg[19] ({addr_arbiter_ar_n_88,addr_arbiter_ar_n_89,addr_arbiter_ar_n_90}),
.\gen_master_slots[3].r_issuing_cnt_reg[27] ({addr_arbiter_ar_n_85,addr_arbiter_ar_n_86,addr_arbiter_ar_n_87}),
.\gen_master_slots[4].r_issuing_cnt_reg[32] (addr_arbiter_ar_n_99),
.\m_axi_arqos[15] (\m_axi_arqos[15] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_valid_i(m_valid_i),
.match(match),
.mi_arready_4(mi_arready_4),
.p_23_in(p_23_in),
.p_39_in(p_39_in),
.p_57_in(p_57_in),
.p_75_in(p_75_in),
.p_93_in(p_93_in),
.r_cmd_pop_0__1(r_cmd_pop_0__1),
.r_cmd_pop_1__1(r_cmd_pop_1__1),
.r_cmd_pop_2__1(r_cmd_pop_2__1),
.r_cmd_pop_3__1(r_cmd_pop_3__1),
.r_cmd_pop_4__1(r_cmd_pop_4__1),
.r_issuing_cnt({r_issuing_cnt[32],r_issuing_cnt[27:24],r_issuing_cnt[19:16],r_issuing_cnt[11:8],r_issuing_cnt[3:0]}),
.read_cs__0(read_cs__0),
.\s_axi_araddr[24] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49 ),
.\s_axi_arqos[3] (\s_axi_arqos[3] ),
.s_axi_rlast_i0(s_axi_rlast_i0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 addr_arbiter_aw
(.ADDRESS_HIT_0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4 ),
.D({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0 }),
.E(s_ready_i0_11),
.Q(aa_mi_awtarget_hot),
.SR(reset),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.\chosen_reg[4] (\gen_multi_thread.arbiter_resp_inst/chosen_9 [4]),
.\gen_master_slots[4].w_issuing_cnt_reg[32] (addr_arbiter_aw_n_25),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_aw_n_23),
.\m_axi_awqos[15] (Q),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_ready_d(m_ready_d_12),
.m_ready_d_0(m_ready_d[0]),
.m_valid_i(m_valid_i_10),
.match(match_3),
.mi_awready_4(mi_awready_4),
.mi_awready_mux__3(mi_awready_mux__3),
.p_101_in(p_101_in),
.p_46_out(p_46_out),
.p_48_in(p_48_in),
.p_66_in(p_66_in),
.p_84_in(p_84_in),
.\s_axi_awaddr[24] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21 ),
.\s_axi_awqos[3] (D),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_ready_i0__1(s_ready_i0__1),
.sa_wm_awready_mux__3(sa_wm_awready_mux__3),
.ss_aa_awready(ss_aa_awready),
.w_issuing_cnt(w_issuing_cnt[32]),
.write_cs01_out(write_cs01_out));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave \gen_decerr_slave.decerr_slave_inst
(.E(s_axi_rvalid_i),
.Q(aa_mi_awtarget_hot[4]),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.m_mesg_i_reg[11] (Q[11:0]),
.\gen_no_arbiter.m_mesg_i_reg[51] ({\m_axi_arqos[15] [51:44],\m_axi_arqos[15] [11:0]}),
.\gen_no_arbiter.m_target_hot_i_reg[4] (aa_mi_artarget_hot),
.\m_payload_i_reg[13] (p_32_in),
.m_ready_d(m_ready_d_12[1]),
.\m_ready_d_reg[1] (splitter_aw_mi_n_3),
.mi_arready_4(mi_arready_4),
.mi_awready_4(mi_awready_4),
.mi_bready_4(mi_bready_4),
.mi_rready_4(mi_rready_4),
.p_22_in(p_22_in),
.p_23_in(p_23_in),
.p_25_in(p_25_in),
.p_29_in(p_29_in),
.read_cs__0(read_cs__0),
.s_axi_rlast_i0(s_axi_rlast_i0),
.\skid_buffer_reg[46] (p_28_in),
.write_cs01_out(write_cs01_out),
.write_cs0__0(write_cs0__0));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].r_issuing_cnt[0]_i_1
(.I0(r_issuing_cnt[0]),
.O(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[0]
(.C(aclk),
.CE(\gen_master_slots[0].reg_slice_mi_n_4 ),
.D(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ),
.Q(r_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[1]
(.C(aclk),
.CE(\gen_master_slots[0].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_81),
.Q(r_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[2]
(.C(aclk),
.CE(\gen_master_slots[0].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_80),
.Q(r_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[3]
(.C(aclk),
.CE(\gen_master_slots[0].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_79),
.Q(r_issuing_cnt[3]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice \gen_master_slots[0].reg_slice_mi
(.D({m_axi_bid[11:0],m_axi_bresp[1:0]}),
.E(\gen_master_slots[0].reg_slice_mi_n_4 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 [0]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[4].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[4].reg_slice_mi_n_5 ),
.\chosen_reg[0] (\gen_multi_thread.arbiter_resp_inst/chosen [0]),
.\chosen_reg[0]_0 (\r_pipe/p_1_in_8 ),
.\chosen_reg[2] (\gen_master_slots[0].reg_slice_mi_n_54 ),
.\chosen_reg[2]_0 (\gen_master_slots[0].reg_slice_mi_n_55 ),
.\gen_master_slots[0].r_issuing_cnt_reg[3] (r_issuing_cnt[3:0]),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[11:0],p_124_out,st_mr_rmesg[1:0],st_mr_rmesg[34:3]}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_bid[11:0],st_mr_bmesg[1:0]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[0].reg_slice_mi_n_6 ),
.m_axi_bready(m_axi_bready[0]),
.m_axi_bvalid(m_axi_bvalid[0]),
.m_axi_rdata(m_axi_rdata[31:0]),
.m_axi_rid(m_axi_rid[11:0]),
.m_axi_rlast(m_axi_rlast[0]),
.\m_axi_rready[0] (M_AXI_RREADY[0]),
.m_axi_rresp(m_axi_rresp[1:0]),
.m_axi_rvalid(m_axi_rvalid[0]),
.p_102_out(p_102_out),
.p_108_out(p_108_out),
.p_122_out(p_122_out),
.p_128_out(p_128_out),
.p_1_in(p_1_in),
.p_93_in(p_93_in),
.r_cmd_pop_0__1(r_cmd_pop_0__1),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].w_issuing_cnt[0]_i_1
(.I0(w_issuing_cnt[0]),
.O(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ),
.D(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ),
.Q(w_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ),
.D(splitter_aw_mi_n_12),
.Q(w_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ),
.D(splitter_aw_mi_n_11),
.Q(w_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ),
.D(splitter_aw_mi_n_10),
.Q(w_issuing_cnt[3]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].r_issuing_cnt[8]_i_1
(.I0(r_issuing_cnt[8]),
.O(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[10]
(.C(aclk),
.CE(\gen_master_slots[1].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_83),
.Q(r_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[11]
(.C(aclk),
.CE(\gen_master_slots[1].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_82),
.Q(r_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[8]
(.C(aclk),
.CE(\gen_master_slots[1].reg_slice_mi_n_4 ),
.D(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ),
.Q(r_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[9]
(.C(aclk),
.CE(\gen_master_slots[1].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_84),
.Q(r_issuing_cnt[9]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 \gen_master_slots[1].reg_slice_mi
(.ADDRESS_HIT_0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.D(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
.E(\gen_master_slots[1].reg_slice_mi_n_4 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 [1]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[4].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[4].reg_slice_mi_n_5 ),
.\chosen_reg[1] (\gen_multi_thread.arbiter_resp_inst/chosen [1]),
.\chosen_reg[1]_0 (\r_pipe/p_1_in_7 ),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_6 ),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (r_issuing_cnt[11:8]),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[23:12],p_104_out,st_mr_rmesg[36:35],st_mr_rmesg[69:38]}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_bid[23:12],st_mr_bmesg[4:3]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[1].reg_slice_mi_n_53 ),
.\m_axi_bid[23] ({m_axi_bid[23:12],m_axi_bresp[3:2]}),
.m_axi_bready(m_axi_bready[1]),
.m_axi_bvalid(m_axi_bvalid[1]),
.m_axi_rdata(m_axi_rdata[63:32]),
.m_axi_rid(m_axi_rid[23:12]),
.m_axi_rlast(m_axi_rlast[1]),
.\m_axi_rready[1] (M_AXI_RREADY[1]),
.m_axi_rresp(m_axi_rresp[3:2]),
.m_axi_rvalid(m_axi_rvalid[1]),
.p_102_out(p_102_out),
.p_108_out(p_108_out),
.p_1_in(p_1_in),
.p_75_in(p_75_in),
.r_cmd_pop_1__1(r_cmd_pop_1__1),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].w_issuing_cnt[8]_i_1
(.I0(w_issuing_cnt[8]),
.O(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ),
.D(splitter_aw_mi_n_1),
.Q(w_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ),
.D(splitter_aw_mi_n_0),
.Q(w_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ),
.D(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ),
.Q(w_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ),
.D(splitter_aw_mi_n_2),
.Q(w_issuing_cnt[9]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[2].r_issuing_cnt[16]_i_1
(.I0(r_issuing_cnt[16]),
.O(\gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0 ));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[16]
(.C(aclk),
.CE(\gen_master_slots[2].reg_slice_mi_n_4 ),
.D(\gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0 ),
.Q(r_issuing_cnt[16]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[17]
(.C(aclk),
.CE(\gen_master_slots[2].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_90),
.Q(r_issuing_cnt[17]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[18]
(.C(aclk),
.CE(\gen_master_slots[2].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_89),
.Q(r_issuing_cnt[18]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[19]
(.C(aclk),
.CE(\gen_master_slots[2].reg_slice_mi_n_4 ),
.D(addr_arbiter_ar_n_88),
.Q(r_issuing_cnt[19]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 \gen_master_slots[2].reg_slice_mi
(.D({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 }),
.E(\gen_master_slots[2].reg_slice_mi_n_4 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 [2]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[4].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[4].reg_slice_mi_n_5 ),
.\chosen_reg[2] (\gen_multi_thread.arbiter_resp_inst/chosen [2]),
.\chosen_reg[2]_0 (\r_pipe/p_1_in ),
.\gen_master_slots[2].r_issuing_cnt_reg[19] (r_issuing_cnt[19:16]),
.\gen_master_slots[3].r_issuing_cnt_reg[24] (\gen_master_slots[3].reg_slice_mi_n_7 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[35:24],p_84_out,st_mr_rmesg[71:70],st_mr_rmesg[104:73]}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_bid[35:24],st_mr_bmesg[7:6]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[2].reg_slice_mi_n_53 ),
.\m_axi_bid[35] ({m_axi_bid[35:24],m_axi_bresp[5:4]}),
.m_axi_bready(m_axi_bready[2]),
.m_axi_bvalid(m_axi_bvalid[2]),
.m_axi_rdata(m_axi_rdata[95:64]),
.m_axi_rid(m_axi_rid[35:24]),
.m_axi_rlast(m_axi_rlast[2]),
.\m_axi_rready[2] (M_AXI_RREADY[2]),
.m_axi_rresp(m_axi_rresp[5:4]),
.m_axi_rvalid(m_axi_rvalid[2]),
.p_1_in(p_1_in),
.p_57_in(p_57_in),
.p_82_out(p_82_out),
.p_88_out(p_88_out),
.r_cmd_pop_2__1(r_cmd_pop_2__1),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[2].w_issuing_cnt[16]_i_1
(.I0(w_issuing_cnt[16]),
.O(\gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0 ));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[16]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ),
.D(\gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0 ),
.Q(w_issuing_cnt[16]),
.R(reset));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[17]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ),
.D(splitter_aw_mi_n_6),
.Q(w_issuing_cnt[17]),
.R(reset));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[18]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ),
.D(splitter_aw_mi_n_5),
.Q(w_issuing_cnt[18]),
.R(reset));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[19]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ),
.D(splitter_aw_mi_n_4),
.Q(w_issuing_cnt[19]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[3].r_issuing_cnt[24]_i_1
(.I0(r_issuing_cnt[24]),
.O(\gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0 ));
FDRE \gen_master_slots[3].r_issuing_cnt_reg[24]
(.C(aclk),
.CE(\gen_master_slots[3].reg_slice_mi_n_5 ),
.D(\gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0 ),
.Q(r_issuing_cnt[24]),
.R(reset));
FDRE \gen_master_slots[3].r_issuing_cnt_reg[25]
(.C(aclk),
.CE(\gen_master_slots[3].reg_slice_mi_n_5 ),
.D(addr_arbiter_ar_n_87),
.Q(r_issuing_cnt[25]),
.R(reset));
FDRE \gen_master_slots[3].r_issuing_cnt_reg[26]
(.C(aclk),
.CE(\gen_master_slots[3].reg_slice_mi_n_5 ),
.D(addr_arbiter_ar_n_86),
.Q(r_issuing_cnt[26]),
.R(reset));
FDRE \gen_master_slots[3].r_issuing_cnt_reg[27]
(.C(aclk),
.CE(\gen_master_slots[3].reg_slice_mi_n_5 ),
.D(addr_arbiter_ar_n_85),
.Q(r_issuing_cnt[27]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 \gen_master_slots[3].reg_slice_mi
(.D({m_axi_bid[47:36],m_axi_bresp[7:6]}),
.E(\gen_master_slots[3].reg_slice_mi_n_5 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 [3]),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\gen_master_slots[3].reg_slice_mi_n_57 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[4].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_1 (\gen_master_slots[4].reg_slice_mi_n_5 ),
.\chosen_reg[3] (\gen_multi_thread.arbiter_resp_inst/chosen [3]),
.\chosen_reg[3]_0 (\r_pipe/p_1_in_5 ),
.\chosen_reg[4] (\gen_master_slots[3].reg_slice_mi_n_55 ),
.\chosen_reg[4]_0 (\gen_master_slots[3].reg_slice_mi_n_56 ),
.\gen_master_slots[3].r_issuing_cnt_reg[27] (r_issuing_cnt[27:24]),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[47:36],p_64_out,st_mr_rmesg[106:105],st_mr_rmesg[139:108]}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_bid[47:36],st_mr_bmesg[10:9]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[3].reg_slice_mi_n_7 ),
.m_axi_bready(m_axi_bready[3]),
.m_axi_bvalid(m_axi_bvalid[3]),
.m_axi_rdata(m_axi_rdata[127:96]),
.m_axi_rid(m_axi_rid[47:36]),
.m_axi_rlast(m_axi_rlast[3]),
.\m_axi_rready[3] (M_AXI_RREADY[3]),
.m_axi_rresp(m_axi_rresp[7:6]),
.m_axi_rvalid(m_axi_rvalid[3]),
.p_1_in(p_1_in),
.p_39_in(p_39_in),
.p_62_out(p_62_out),
.p_68_out(p_68_out),
.p_82_out(p_82_out),
.p_88_out(p_88_out),
.r_cmd_pop_3__1(r_cmd_pop_3__1),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[3].w_issuing_cnt[24]_i_1
(.I0(w_issuing_cnt[24]),
.O(\gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0 ));
FDRE \gen_master_slots[3].w_issuing_cnt_reg[24]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ),
.D(\gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0 ),
.Q(w_issuing_cnt[24]),
.R(reset));
FDRE \gen_master_slots[3].w_issuing_cnt_reg[25]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ),
.D(splitter_aw_mi_n_9),
.Q(w_issuing_cnt[25]),
.R(reset));
FDRE \gen_master_slots[3].w_issuing_cnt_reg[26]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ),
.D(splitter_aw_mi_n_8),
.Q(w_issuing_cnt[26]),
.R(reset));
FDRE \gen_master_slots[3].w_issuing_cnt_reg[27]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ),
.D(splitter_aw_mi_n_7),
.Q(w_issuing_cnt[27]),
.R(reset));
FDRE \gen_master_slots[4].r_issuing_cnt_reg[32]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_ar_n_99),
.Q(r_issuing_cnt[32]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 \gen_master_slots[4].reg_slice_mi
(.D(p_32_in),
.E(\r_pipe/p_1_in_6 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 [4]),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_master_slots[3].reg_slice_mi_n_57 ),
.\chosen_reg[4] (\gen_multi_thread.arbiter_resp_inst/chosen [4]),
.\gen_axi.s_axi_rid_i_reg[11] (p_28_in),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[59:48],p_42_out}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 (st_mr_bid[59:48]),
.m_valid_i_reg(\gen_master_slots[4].reg_slice_mi_n_1 ),
.mi_bready_4(mi_bready_4),
.mi_rready_4(mi_rready_4),
.p_1_in(p_1_in),
.p_23_in(p_23_in),
.p_25_in(p_25_in),
.p_29_in(p_29_in),
.p_40_out(p_40_out),
.p_46_out(p_46_out),
.r_cmd_pop_4__1(r_cmd_pop_4__1),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready),
.s_ready_i_reg(\gen_master_slots[4].reg_slice_mi_n_5 ));
FDRE \gen_master_slots[4].w_issuing_cnt_reg[32]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_aw_n_25),
.Q(w_issuing_cnt[32]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor \gen_slave_slots[0].gen_si_read.si_transactor_ar
(.ADDRESS_HIT_0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.D(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49 ),
.E(s_ready_i0),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen ),
.SR(reset),
.S_AXI_ARREADY(S_AXI_ARREADY),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_53 ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_53 ),
.\m_payload_i_reg[0] (\r_pipe/p_1_in_8 ),
.\m_payload_i_reg[0]_0 (\r_pipe/p_1_in_7 ),
.\m_payload_i_reg[0]_1 (\r_pipe/p_1_in_5 ),
.\m_payload_i_reg[0]_2 (\r_pipe/p_1_in ),
.\m_payload_i_reg[34] (\r_pipe/p_1_in_6 ),
.\m_payload_i_reg[34]_0 (p_42_out),
.\m_payload_i_reg[34]_1 (p_64_out),
.\m_payload_i_reg[34]_2 (p_124_out),
.\m_payload_i_reg[34]_3 (p_84_out),
.\m_payload_i_reg[34]_4 (p_104_out),
.m_valid_i(m_valid_i),
.m_valid_i_reg(\gen_master_slots[3].reg_slice_mi_n_55 ),
.m_valid_i_reg_0(\gen_master_slots[0].reg_slice_mi_n_54 ),
.match(match),
.p_102_out(p_102_out),
.p_122_out(p_122_out),
.p_40_out(p_40_out),
.p_62_out(p_62_out),
.p_82_out(p_82_out),
.r_cmd_pop_4__1(r_cmd_pop_4__1),
.r_issuing_cnt(r_issuing_cnt[32]),
.\s_axi_araddr[30] ({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 }),
.\s_axi_arid[11] (\s_axi_arqos[3] [11:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.\s_axi_rid[10] (\s_axi_rid[10] ),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.\s_axi_rid[1] (\s_axi_rid[1] ),
.\s_axi_rid[2] (\s_axi_rid[2] ),
.\s_axi_rid[3] (\s_axi_rid[3] ),
.\s_axi_rid[4] (\s_axi_rid[4] ),
.\s_axi_rid[5] (\s_axi_rid[5] ),
.\s_axi_rid[6] (\s_axi_rid[6] ),
.\s_axi_rid[7] (\s_axi_rid[7] ),
.\s_axi_rid[8] (\s_axi_rid[8] ),
.\s_axi_rid[9] (\s_axi_rid[9] ),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.\s_axi_rvalid[0] (\s_axi_rvalid[0] ),
.st_mr_rid(st_mr_rid),
.st_mr_rmesg({st_mr_rmesg[139:108],st_mr_rmesg[106:73],st_mr_rmesg[71:38],st_mr_rmesg[36:3],st_mr_rmesg[1:0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0 \gen_slave_slots[0].gen_si_write.si_transactor_aw
(.ADDRESS_HIT_0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4 ),
.D({\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21 ,st_aa_awtarget_enc}),
.E(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14 ),
.Q(\gen_multi_thread.arbiter_resp_inst/chosen_9 ),
.SR(reset),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_master_slots[0].w_issuing_cnt_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15 ),
.\gen_master_slots[3].w_issuing_cnt_reg[24] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16 ),
.\gen_no_arbiter.s_ready_i_reg[0] (s_ready_i0_11),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_aw_n_23),
.\m_ready_d_reg[1] (\s_axi_awready[0] ),
.m_valid_i(m_valid_i_10),
.m_valid_i_reg(\gen_master_slots[3].reg_slice_mi_n_56 ),
.m_valid_i_reg_0(\gen_master_slots[0].reg_slice_mi_n_55 ),
.match(match_3),
.p_101_in(p_101_in),
.p_108_out(p_108_out),
.p_128_out(p_128_out),
.p_46_out(p_46_out),
.p_48_in(p_48_in),
.p_66_in(p_66_in),
.p_68_out(p_68_out),
.p_84_in(p_84_in),
.p_88_out(p_88_out),
.\s_axi_awaddr[30] ({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0 }),
.\s_axi_awid[11] (D[11:0]),
.\s_axi_bid[0] (\s_axi_bid[0] ),
.\s_axi_bid[10] (\s_axi_bid[10] ),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.\s_axi_bid[1] (\s_axi_bid[1] ),
.\s_axi_bid[2] (\s_axi_bid[2] ),
.\s_axi_bid[3] (\s_axi_bid[3] ),
.\s_axi_bid[4] (\s_axi_bid[4] ),
.\s_axi_bid[5] (\s_axi_bid[5] ),
.\s_axi_bid[6] (\s_axi_bid[6] ),
.\s_axi_bid[7] (\s_axi_bid[7] ),
.\s_axi_bid[8] (\s_axi_bid[8] ),
.\s_axi_bid[9] (\s_axi_bid[9] ),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.\s_axi_bvalid[0] (\s_axi_bvalid[0] ),
.st_mr_bid(st_mr_bid),
.st_mr_bmesg({st_mr_bmesg[10:9],st_mr_bmesg[7:6],st_mr_bmesg[4:3],st_mr_bmesg[1:0]}),
.w_issuing_cnt({w_issuing_cnt[32],w_issuing_cnt[27:24],w_issuing_cnt[19:16],w_issuing_cnt[11:8],w_issuing_cnt[3:0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter \gen_slave_slots[0].gen_si_write.splitter_aw_si
(.aclk(aclk),
.aresetn_d(aresetn_d),
.m_ready_d(m_ready_d),
.\s_axi_awready[0] (\s_axi_awready[0] ),
.s_axi_awvalid(s_axi_awvalid),
.ss_aa_awready(ss_aa_awready),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router \gen_slave_slots[0].gen_si_write.wdata_router_w
(.D({\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21 ,st_aa_awtarget_enc}),
.SR(reset),
.aclk(aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d[1]),
.match(match_3),
.p_22_in(p_22_in),
.\s_axi_awaddr[30] ({\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1 ,\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0 }),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.write_cs0__0(write_cs0__0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 splitter_aw_mi
(.D({splitter_aw_mi_n_0,splitter_aw_mi_n_1,splitter_aw_mi_n_2}),
.Q(aa_mi_awtarget_hot[3:0]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\chosen_reg[3] (\gen_multi_thread.arbiter_resp_inst/chosen_9 [3:0]),
.\gen_axi.s_axi_awready_i_reg (splitter_aw_mi_n_3),
.\gen_master_slots[0].w_issuing_cnt_reg[3] ({splitter_aw_mi_n_10,splitter_aw_mi_n_11,splitter_aw_mi_n_12}),
.\gen_master_slots[2].w_issuing_cnt_reg[19] ({splitter_aw_mi_n_4,splitter_aw_mi_n_5,splitter_aw_mi_n_6}),
.\gen_master_slots[3].w_issuing_cnt_reg[27] ({splitter_aw_mi_n_7,splitter_aw_mi_n_8,splitter_aw_mi_n_9}),
.m_axi_awready(m_axi_awready),
.m_ready_d(m_ready_d_12),
.mi_awready_mux__3(mi_awready_mux__3),
.p_108_out(p_108_out),
.p_128_out(p_128_out),
.p_68_out(p_68_out),
.p_88_out(p_88_out),
.s_axi_bready(s_axi_bready),
.s_ready_i0__1(s_ready_i0__1),
.sa_wm_awready_mux__3(sa_wm_awready_mux__3),
.w_issuing_cnt({w_issuing_cnt[27:24],w_issuing_cnt[19:16],w_issuing_cnt[11:8],w_issuing_cnt[3:0]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
(mi_awready_4,
p_22_in,
p_29_in,
p_23_in,
p_25_in,
read_cs__0,
mi_arready_4,
\m_payload_i_reg[13] ,
\skid_buffer_reg[46] ,
SR,
aclk,
m_ready_d,
aa_sa_awvalid,
Q,
mi_rready_4,
aa_mi_arvalid,
\gen_no_arbiter.m_target_hot_i_reg[4] ,
\gen_no_arbiter.m_mesg_i_reg[51] ,
\m_ready_d_reg[1] ,
mi_bready_4,
write_cs0__0,
write_cs01_out,
s_axi_rlast_i0,
E,
\gen_no_arbiter.m_mesg_i_reg[11] ,
aresetn_d);
output mi_awready_4;
output p_22_in;
output p_29_in;
output p_23_in;
output p_25_in;
output read_cs__0;
output mi_arready_4;
output [11:0]\m_payload_i_reg[13] ;
output [11:0]\skid_buffer_reg[46] ;
input [0:0]SR;
input aclk;
input [0:0]m_ready_d;
input aa_sa_awvalid;
input [0:0]Q;
input mi_rready_4;
input aa_mi_arvalid;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[4] ;
input [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
input \m_ready_d_reg[1] ;
input mi_bready_4;
input write_cs0__0;
input write_cs01_out;
input s_axi_rlast_i0;
input [0:0]E;
input [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
input aresetn_d;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire aa_mi_arvalid;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_axi.read_cnt[4]_i_2_n_0 ;
wire \gen_axi.read_cnt[5]_i_2_n_0 ;
wire \gen_axi.read_cnt[7]_i_1_n_0 ;
wire \gen_axi.read_cnt[7]_i_3_n_0 ;
wire [7:1]\gen_axi.read_cnt_reg ;
wire [0:0]\gen_axi.read_cnt_reg__0 ;
wire \gen_axi.read_cs[0]_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_3_n_0 ;
wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
wire \gen_axi.s_axi_bid_i[11]_i_1_n_0 ;
wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_3_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
wire \gen_axi.write_cs[0]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_1_n_0 ;
wire [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
wire [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[4] ;
wire [11:0]\m_payload_i_reg[13] ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire mi_arready_4;
wire mi_awready_4;
wire mi_bready_4;
wire mi_rready_4;
wire [7:0]p_0_in;
wire p_22_in;
wire p_23_in;
wire p_25_in;
wire p_29_in;
wire read_cs__0;
wire s_axi_rlast_i0;
wire [11:0]\skid_buffer_reg[46] ;
wire [1:0]write_cs;
wire write_cs01_out;
wire write_cs0__0;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h74))
\gen_axi.read_cnt[0]_i_1
(.I0(\gen_axi.read_cnt_reg__0 ),
.I1(p_23_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [12]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'hE22E))
\gen_axi.read_cnt[1]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [13]),
.I1(p_23_in),
.I2(\gen_axi.read_cnt_reg__0 ),
.I3(\gen_axi.read_cnt_reg [1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFCAA03AA))
\gen_axi.read_cnt[2]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [14]),
.I1(\gen_axi.read_cnt_reg [1]),
.I2(\gen_axi.read_cnt_reg__0 ),
.I3(p_23_in),
.I4(\gen_axi.read_cnt_reg [2]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'hFFFCAAAA0003AAAA))
\gen_axi.read_cnt[3]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [15]),
.I1(\gen_axi.read_cnt_reg__0 ),
.I2(\gen_axi.read_cnt_reg [1]),
.I3(\gen_axi.read_cnt_reg [2]),
.I4(p_23_in),
.I5(\gen_axi.read_cnt_reg [3]),
.O(p_0_in[3]));
LUT6 #(
.INIT(64'hFFFCAAAA0003AAAA))
\gen_axi.read_cnt[4]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [16]),
.I1(\gen_axi.read_cnt_reg [2]),
.I2(\gen_axi.read_cnt[4]_i_2_n_0 ),
.I3(\gen_axi.read_cnt_reg [3]),
.I4(p_23_in),
.I5(\gen_axi.read_cnt_reg [4]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hE))
\gen_axi.read_cnt[4]_i_2
(.I0(\gen_axi.read_cnt_reg [1]),
.I1(\gen_axi.read_cnt_reg__0 ),
.O(\gen_axi.read_cnt[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hCA3A))
\gen_axi.read_cnt[5]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [17]),
.I1(\gen_axi.read_cnt[5]_i_2_n_0 ),
.I2(p_23_in),
.I3(\gen_axi.read_cnt_reg [5]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_axi.read_cnt[5]_i_2
(.I0(\gen_axi.read_cnt_reg [3]),
.I1(\gen_axi.read_cnt_reg__0 ),
.I2(\gen_axi.read_cnt_reg [1]),
.I3(\gen_axi.read_cnt_reg [2]),
.I4(\gen_axi.read_cnt_reg [4]),
.O(\gen_axi.read_cnt[5]_i_2_n_0 ));
LUT4 #(
.INIT(16'hCA3A))
\gen_axi.read_cnt[6]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [18]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(p_23_in),
.I3(\gen_axi.read_cnt_reg [6]),
.O(p_0_in[6]));
LUT6 #(
.INIT(64'h4F40404040404040))
\gen_axi.read_cnt[7]_i_1
(.I0(read_cs__0),
.I1(mi_rready_4),
.I2(p_23_in),
.I3(mi_arready_4),
.I4(aa_mi_arvalid),
.I5(\gen_no_arbiter.m_target_hot_i_reg[4] ),
.O(\gen_axi.read_cnt[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFCAA03AA))
\gen_axi.read_cnt[7]_i_2
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [19]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(\gen_axi.read_cnt_reg [6]),
.I3(p_23_in),
.I4(\gen_axi.read_cnt_reg [7]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_axi.read_cnt[7]_i_3
(.I0(\gen_axi.read_cnt_reg [4]),
.I1(\gen_axi.read_cnt_reg [2]),
.I2(\gen_axi.read_cnt_reg [1]),
.I3(\gen_axi.read_cnt_reg__0 ),
.I4(\gen_axi.read_cnt_reg [3]),
.I5(\gen_axi.read_cnt_reg [5]),
.O(\gen_axi.read_cnt[7]_i_3_n_0 ));
FDRE \gen_axi.read_cnt_reg[0]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(\gen_axi.read_cnt_reg__0 ),
.R(SR));
FDRE \gen_axi.read_cnt_reg[1]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(\gen_axi.read_cnt_reg [1]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[2]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(\gen_axi.read_cnt_reg [2]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[3]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(\gen_axi.read_cnt_reg [3]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[4]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(\gen_axi.read_cnt_reg [4]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[5]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(\gen_axi.read_cnt_reg [5]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[6]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(\gen_axi.read_cnt_reg [6]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[7]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[7]),
.Q(\gen_axi.read_cnt_reg [7]),
.R(SR));
LUT6 #(
.INIT(64'h7F70707070707070))
\gen_axi.read_cs[0]_i_1
(.I0(read_cs__0),
.I1(mi_rready_4),
.I2(p_23_in),
.I3(mi_arready_4),
.I4(aa_mi_arvalid),
.I5(\gen_no_arbiter.m_target_hot_i_reg[4] ),
.O(\gen_axi.read_cs[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.read_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.read_cs[0]_i_1_n_0 ),
.Q(p_23_in),
.R(SR));
LUT6 #(
.INIT(64'h00000000FBBB0000))
\gen_axi.s_axi_arready_i_i_1
(.I0(mi_arready_4),
.I1(p_23_in),
.I2(read_cs__0),
.I3(mi_rready_4),
.I4(aresetn_d),
.I5(E),
.O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_axi.s_axi_arready_i_i_2
(.I0(\gen_axi.read_cnt[4]_i_2_n_0 ),
.I1(\gen_axi.read_cnt_reg [6]),
.I2(\gen_axi.read_cnt_reg [7]),
.I3(\gen_axi.s_axi_arready_i_i_3_n_0 ),
.I4(\gen_axi.read_cnt_reg [2]),
.I5(\gen_axi.read_cnt_reg [3]),
.O(read_cs__0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\gen_axi.s_axi_arready_i_i_3
(.I0(\gen_axi.read_cnt_reg [4]),
.I1(\gen_axi.read_cnt_reg [5]),
.O(\gen_axi.s_axi_arready_i_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready_4),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFBB0000F0FF))
\gen_axi.s_axi_awready_i_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(Q),
.I2(mi_bready_4),
.I3(write_cs[1]),
.I4(write_cs[0]),
.I5(mi_awready_4),
.O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
.Q(mi_awready_4),
.R(SR));
LUT6 #(
.INIT(64'h0100000000000000))
\gen_axi.s_axi_bid_i[11]_i_1
(.I0(write_cs[1]),
.I1(write_cs[0]),
.I2(m_ready_d),
.I3(aa_sa_awvalid),
.I4(Q),
.I5(mi_awready_4),
.O(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ));
FDRE \gen_axi.s_axi_bid_i_reg[0]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [0]),
.Q(\m_payload_i_reg[13] [0]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[10]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [10]),
.Q(\m_payload_i_reg[13] [10]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[11]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [11]),
.Q(\m_payload_i_reg[13] [11]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[1]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [1]),
.Q(\m_payload_i_reg[13] [1]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[2]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [2]),
.Q(\m_payload_i_reg[13] [2]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[3]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [3]),
.Q(\m_payload_i_reg[13] [3]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[4]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [4]),
.Q(\m_payload_i_reg[13] [4]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[5]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [5]),
.Q(\m_payload_i_reg[13] [5]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[6]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [6]),
.Q(\m_payload_i_reg[13] [6]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[7]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [7]),
.Q(\m_payload_i_reg[13] [7]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[8]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [8]),
.Q(\m_payload_i_reg[13] [8]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[9]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [9]),
.Q(\m_payload_i_reg[13] [9]),
.R(SR));
LUT5 #(
.INIT(32'hDDFF00C0))
\gen_axi.s_axi_bvalid_i_i_1
(.I0(mi_bready_4),
.I1(write_cs[0]),
.I2(write_cs0__0),
.I3(write_cs[1]),
.I4(p_29_in),
.O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
.Q(p_29_in),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[0]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [0]),
.Q(\skid_buffer_reg[46] [0]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[10]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [10]),
.Q(\skid_buffer_reg[46] [10]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[11]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [11]),
.Q(\skid_buffer_reg[46] [11]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[1]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [1]),
.Q(\skid_buffer_reg[46] [1]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[2]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [2]),
.Q(\skid_buffer_reg[46] [2]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[3]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [3]),
.Q(\skid_buffer_reg[46] [3]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[4]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [4]),
.Q(\skid_buffer_reg[46] [4]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[5]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [5]),
.Q(\skid_buffer_reg[46] [5]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[6]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [6]),
.Q(\skid_buffer_reg[46] [6]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[7]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [7]),
.Q(\skid_buffer_reg[46] [7]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[8]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [8]),
.Q(\skid_buffer_reg[46] [8]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[9]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [9]),
.Q(\skid_buffer_reg[46] [9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAFBFFAAAA0800))
\gen_axi.s_axi_rlast_i_i_1
(.I0(s_axi_rlast_i0),
.I1(\gen_axi.s_axi_rlast_i_i_3_n_0 ),
.I2(\gen_axi.read_cnt_reg [1]),
.I3(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
.I4(E),
.I5(p_25_in),
.O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h1))
\gen_axi.s_axi_rlast_i_i_3
(.I0(\gen_axi.read_cnt_reg [2]),
.I1(\gen_axi.read_cnt_reg [3]),
.O(\gen_axi.s_axi_rlast_i_i_3_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_axi.s_axi_rlast_i_i_4
(.I0(\gen_axi.read_cnt_reg [4]),
.I1(\gen_axi.read_cnt_reg [5]),
.I2(\gen_axi.read_cnt_reg [6]),
.I3(\gen_axi.read_cnt_reg [7]),
.I4(mi_rready_4),
.I5(p_23_in),
.O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
FDRE \gen_axi.s_axi_rlast_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
.Q(p_25_in),
.R(SR));
LUT5 #(
.INIT(32'hFF5F000C))
\gen_axi.s_axi_wready_i_i_1
(.I0(write_cs0__0),
.I1(write_cs01_out),
.I2(write_cs[0]),
.I3(write_cs[1]),
.I4(p_22_in),
.O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_wready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
.Q(p_22_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h4522))
\gen_axi.write_cs[0]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(write_cs[1]),
.I2(write_cs0__0),
.I3(write_cs[0]),
.O(\gen_axi.write_cs[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFE00FE44))
\gen_axi.write_cs[1]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(write_cs[1]),
.I2(write_cs0__0),
.I3(write_cs[0]),
.I4(mi_bready_4),
.O(\gen_axi.write_cs[1]_i_1_n_0 ));
FDRE \gen_axi.write_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[0]_i_1_n_0 ),
.Q(write_cs[0]),
.R(SR));
FDRE \gen_axi.write_cs_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[1]_i_1_n_0 ),
.Q(write_cs[1]),
.R(SR));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor
(\s_axi_rid[0] ,
\s_axi_rid[1] ,
\s_axi_rid[2] ,
\s_axi_rid[3] ,
\s_axi_rid[4] ,
\s_axi_rid[5] ,
\s_axi_rid[6] ,
\s_axi_rid[7] ,
\s_axi_rid[8] ,
\s_axi_rid[9] ,
\s_axi_rid[10] ,
\s_axi_rid[11] ,
s_axi_rresp,
s_axi_rdata,
s_axi_rlast,
E,
m_valid_i,
D,
\m_payload_i_reg[0] ,
Q,
\s_axi_rvalid[0] ,
\m_payload_i_reg[0]_0 ,
\m_payload_i_reg[34] ,
\m_payload_i_reg[0]_1 ,
\m_payload_i_reg[0]_2 ,
st_mr_rid,
\m_payload_i_reg[34]_0 ,
aresetn_d,
aa_mi_arvalid,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
r_cmd_pop_4__1,
match,
r_issuing_cnt,
ADDRESS_HIT_0,
\s_axi_araddr[30] ,
S_AXI_ARREADY,
s_axi_rready,
p_122_out,
st_mr_rmesg,
\m_payload_i_reg[34]_1 ,
\m_payload_i_reg[34]_2 ,
\m_payload_i_reg[34]_3 ,
\m_payload_i_reg[34]_4 ,
p_62_out,
p_102_out,
s_axi_arvalid,
p_40_out,
m_valid_i_reg,
p_82_out,
m_valid_i_reg_0,
\s_axi_arid[11] ,
SR,
aclk);
output \s_axi_rid[0] ;
output \s_axi_rid[1] ;
output \s_axi_rid[2] ;
output \s_axi_rid[3] ;
output \s_axi_rid[4] ;
output \s_axi_rid[5] ;
output \s_axi_rid[6] ;
output \s_axi_rid[7] ;
output \s_axi_rid[8] ;
output \s_axi_rid[9] ;
output \s_axi_rid[10] ;
output \s_axi_rid[11] ;
output [1:0]s_axi_rresp;
output [31:0]s_axi_rdata;
output [0:0]s_axi_rlast;
output [0:0]E;
output m_valid_i;
output [0:0]D;
output [0:0]\m_payload_i_reg[0] ;
output [4:0]Q;
output \s_axi_rvalid[0] ;
output [0:0]\m_payload_i_reg[0]_0 ;
output [0:0]\m_payload_i_reg[34] ;
output [0:0]\m_payload_i_reg[0]_1 ;
output [0:0]\m_payload_i_reg[0]_2 ;
input [59:0]st_mr_rid;
input [0:0]\m_payload_i_reg[34]_0 ;
input aresetn_d;
input aa_mi_arvalid;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input r_cmd_pop_4__1;
input match;
input [0:0]r_issuing_cnt;
input ADDRESS_HIT_0;
input [2:0]\s_axi_araddr[30] ;
input [0:0]S_AXI_ARREADY;
input [0:0]s_axi_rready;
input p_122_out;
input [135:0]st_mr_rmesg;
input [0:0]\m_payload_i_reg[34]_1 ;
input [0:0]\m_payload_i_reg[34]_2 ;
input [0:0]\m_payload_i_reg[34]_3 ;
input [0:0]\m_payload_i_reg[34]_4 ;
input p_62_out;
input p_102_out;
input [0:0]s_axi_arvalid;
input p_40_out;
input m_valid_i_reg;
input p_82_out;
input m_valid_i_reg_0;
input [11:0]\s_axi_arid[11] ;
input [0:0]SR;
input aclk;
wire ADDRESS_HIT_0;
wire [0:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]SR;
wire [0:0]S_AXI_ARREADY;
wire aa_mi_arvalid;
wire accum_push_5__0;
wire aclk;
wire [59:0]active_cnt;
wire [58:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1_n_0;
wire aid_match_00_carry_i_2_n_0;
wire aid_match_00_carry_i_3_n_0;
wire aid_match_00_carry_i_4_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_0__0;
wire aid_match_10;
wire aid_match_10_carry_i_1_n_0;
wire aid_match_10_carry_i_2_n_0;
wire aid_match_10_carry_i_3_n_0;
wire aid_match_10_carry_i_4_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_1__0;
wire aid_match_20;
wire aid_match_20_carry_i_1_n_0;
wire aid_match_20_carry_i_2_n_0;
wire aid_match_20_carry_i_3_n_0;
wire aid_match_20_carry_i_4_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_2__0;
wire aid_match_30;
wire aid_match_30_carry_i_1_n_0;
wire aid_match_30_carry_i_2_n_0;
wire aid_match_30_carry_i_3_n_0;
wire aid_match_30_carry_i_4_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_3__0;
wire aid_match_40;
wire aid_match_40_carry_i_1_n_0;
wire aid_match_40_carry_i_2_n_0;
wire aid_match_40_carry_i_3_n_0;
wire aid_match_40_carry_i_4_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_4__0;
wire aid_match_50;
wire aid_match_50_carry_i_1_n_0;
wire aid_match_50_carry_i_2_n_0;
wire aid_match_50_carry_i_3_n_0;
wire aid_match_50_carry_i_4_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_5__0;
wire aid_match_60;
wire aid_match_60_carry_i_1_n_0;
wire aid_match_60_carry_i_2_n_0;
wire aid_match_60_carry_i_3_n_0;
wire aid_match_60_carry_i_4_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_6__0;
wire aid_match_70;
wire aid_match_70_carry_i_1_n_0;
wire aid_match_70_carry_i_2_n_0;
wire aid_match_70_carry_i_3_n_0;
wire aid_match_70_carry_i_4_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aid_match_7__0;
wire aresetn_d;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire [47:0]f_mux4_return;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.accept_cnt[0]_i_1_n_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_47 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_48 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_49 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_50 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_51 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_52 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_53 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_54 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_55 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_56 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_57 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_58 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_59 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_60 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_61 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_62 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_63 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_64 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_65 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_66 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_67 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_68 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_69 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_70 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_71 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_72 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_73 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_74 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_75 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_76 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_77 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_78 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_79 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_80 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_81 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_82 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_83 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_84 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_85 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_86 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_87 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_88 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_89 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_90 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_91 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_28_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_31_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[0]_2 ;
wire [0:0]\m_payload_i_reg[34] ;
wire [0:0]\m_payload_i_reg[34]_0 ;
wire [0:0]\m_payload_i_reg[34]_1 ;
wire [0:0]\m_payload_i_reg[34]_2 ;
wire [0:0]\m_payload_i_reg[34]_3 ;
wire [0:0]\m_payload_i_reg[34]_4 ;
wire m_valid_i;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire match;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_102_out;
wire p_10_out;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_122_out;
wire p_12_out;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_40_out;
wire p_4_out;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_62_out;
wire p_6_out;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_82_out;
wire p_8_out;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire r_cmd_pop_4__1;
wire [0:0]r_issuing_cnt;
wire [2:2]resp_select;
wire [2:0]\s_axi_araddr[30] ;
wire [11:0]\s_axi_arid[11] ;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire \s_axi_rid[0] ;
wire \s_axi_rid[10] ;
wire \s_axi_rid[11] ;
wire \s_axi_rid[1] ;
wire \s_axi_rid[2] ;
wire \s_axi_rid[3] ;
wire \s_axi_rid[4] ;
wire \s_axi_rid[5] ;
wire \s_axi_rid[6] ;
wire \s_axi_rid[7] ;
wire \s_axi_rid[8] ;
wire \s_axi_rid[9] ;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire \s_axi_rvalid[0] ;
wire [59:0]st_mr_rid;
wire [135:0]st_mr_rmesg;
wire thread_valid_0__2;
wire thread_valid_1__2;
wire thread_valid_2__2;
wire thread_valid_3__2;
wire thread_valid_4__2;
wire thread_valid_5__2;
wire thread_valid_6__2;
wire thread_valid_7__2;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1_n_0,aid_match_00_carry_i_2_n_0,aid_match_00_carry_i_3_n_0,aid_match_00_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.O(aid_match_00_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.O(aid_match_00_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.O(aid_match_00_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.O(aid_match_00_carry_i_4_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1_n_0,aid_match_10_carry_i_2_n_0,aid_match_10_carry_i_3_n_0,aid_match_10_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.I5(\s_axi_arid[11] [11]),
.O(aid_match_10_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.I5(\s_axi_arid[11] [8]),
.O(aid_match_10_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.I5(\s_axi_arid[11] [5]),
.O(aid_match_10_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.I5(\s_axi_arid[11] [2]),
.O(aid_match_10_carry_i_4_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1_n_0,aid_match_20_carry_i_2_n_0,aid_match_20_carry_i_3_n_0,aid_match_20_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.O(aid_match_20_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.O(aid_match_20_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.O(aid_match_20_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.O(aid_match_20_carry_i_4_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1_n_0,aid_match_30_carry_i_2_n_0,aid_match_30_carry_i_3_n_0,aid_match_30_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.O(aid_match_30_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.O(aid_match_30_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.O(aid_match_30_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.O(aid_match_30_carry_i_4_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1_n_0,aid_match_40_carry_i_2_n_0,aid_match_40_carry_i_3_n_0,aid_match_40_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.O(aid_match_40_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.O(aid_match_40_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.O(aid_match_40_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.O(aid_match_40_carry_i_4_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1_n_0,aid_match_50_carry_i_2_n_0,aid_match_50_carry_i_3_n_0,aid_match_50_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.O(aid_match_50_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.O(aid_match_50_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.O(aid_match_50_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.O(aid_match_50_carry_i_4_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1_n_0,aid_match_60_carry_i_2_n_0,aid_match_60_carry_i_3_n_0,aid_match_60_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.O(aid_match_60_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.O(aid_match_60_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.O(aid_match_60_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.O(aid_match_60_carry_i_4_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1_n_0,aid_match_70_carry_i_2_n_0,aid_match_70_carry_i_3_n_0,aid_match_70_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1
(.I0(\s_axi_arid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.I2(\s_axi_arid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.I4(\s_axi_arid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.O(aid_match_70_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2
(.I0(\s_axi_arid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.I2(\s_axi_arid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.I4(\s_axi_arid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.O(aid_match_70_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3
(.I0(\s_axi_arid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.I2(\s_axi_arid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.I4(\s_axi_arid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.O(aid_match_70_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4
(.I0(\s_axi_arid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.I2(\s_axi_arid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.I4(\s_axi_arid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.O(aid_match_70_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair155" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1
(.I0(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_55 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_55 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_58 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_55 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_57 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_55 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_56 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [3]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 \gen_multi_thread.arbiter_resp_inst
(.E(E),
.Q(Q),
.SR(SR),
.S_AXI_ARREADY(S_AXI_ARREADY),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.f_mux4_return({f_mux4_return[47:15],f_mux4_return[13:0]}),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.\gen_multi_thread.accept_cnt_reg[0] (\gen_no_arbiter.s_ready_i[0]_i_33__0_n_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.accept_cnt_reg__0 [3]),
.\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] (\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] (\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] (\gen_no_arbiter.s_ready_i[0]_i_7__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] (\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (\m_payload_i_reg[0]_1 ),
.\m_payload_i_reg[0]_2 (\m_payload_i_reg[0]_2 ),
.\m_payload_i_reg[34] (\m_payload_i_reg[34] ),
.\m_payload_i_reg[34]_0 (\m_payload_i_reg[34]_1 ),
.\m_payload_i_reg[34]_1 (\m_payload_i_reg[34]_2 ),
.\m_payload_i_reg[34]_2 (\m_payload_i_reg[34]_3 ),
.\m_payload_i_reg[34]_3 (\m_payload_i_reg[34]_4 ),
.\m_payload_i_reg[34]_4 (\gen_multi_thread.mux_resp_multi_thread_n_59 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(m_valid_i_reg),
.m_valid_i_reg_0(m_valid_i_reg_0),
.match(match),
.p_102_out(p_102_out),
.p_122_out(p_122_out),
.p_40_out(p_40_out),
.p_62_out(p_62_out),
.p_82_out(p_82_out),
.r_cmd_pop_4__1(r_cmd_pop_4__1),
.r_issuing_cnt(r_issuing_cnt),
.resp_select(resp_select),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\s_axi_rvalid[0] (\s_axi_rvalid[0] ),
.st_mr_rid(st_mr_rid[47:0]),
.st_mr_rmesg(st_mr_rmesg));
(* SOFT_HLUTNM = "soft_lutpair147" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair147" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0
(.I0(active_cnt[0]),
.I1(cmd_push_0),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[2]),
.I3(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0
(.I0(active_cnt[1]),
.I1(cmd_push_0),
.I2(active_cnt[0]),
.I3(active_cnt[3]),
.I4(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_47 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_47 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_47 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_47 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.R(SR));
LUT4 #(
.INIT(16'hE222))
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I1(thread_valid_0__2),
.I2(aid_match_00),
.I3(S_AXI_ARREADY),
.O(cmd_push_0));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(D),
.Q(active_target[2]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0
(.I0(cmd_push_1),
.I1(active_cnt[8]),
.I2(active_cnt[10]),
.I3(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0
(.I0(active_cnt[9]),
.I1(cmd_push_1),
.I2(active_cnt[8]),
.I3(active_cnt[11]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0
(.I0(active_cnt[8]),
.I1(cmd_push_1),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_54 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_54 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_54 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_54 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'hF8080808))
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I1(thread_valid_0__2),
.I2(thread_valid_1__2),
.I3(aid_match_10),
.I4(S_AXI_ARREADY),
.O(cmd_push_1));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[10]
(.C(aclk),
.CE(cmd_push_1),
.D(D),
.Q(active_target[10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0
(.I0(active_cnt[16]),
.I1(cmd_push_2),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0
(.I0(cmd_push_2),
.I1(active_cnt[16]),
.I2(active_cnt[18]),
.I3(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0
(.I0(active_cnt[17]),
.I1(cmd_push_2),
.I2(active_cnt[16]),
.I3(active_cnt[19]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_53 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_53 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_53 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_53 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF80008000800080))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I1(thread_valid_0__2),
.I2(thread_valid_1__2),
.I3(thread_valid_2__2),
.I4(aid_match_20),
.I5(S_AXI_ARREADY),
.O(cmd_push_2));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0
(.I0(active_cnt[2]),
.I1(active_cnt[3]),
.I2(active_cnt[1]),
.I3(active_cnt[0]),
.O(thread_valid_0__2));
(* SOFT_HLUTNM = "soft_lutpair143" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.O(thread_valid_1__2));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.O(thread_valid_2__2));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[17]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[18]
(.C(aclk),
.CE(cmd_push_2),
.D(D),
.Q(active_target[18]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0
(.I0(active_cnt[24]),
.I1(cmd_push_3),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[26]),
.I3(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0
(.I0(active_cnt[25]),
.I1(cmd_push_3),
.I2(active_cnt[24]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_48 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_48 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_48 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_48 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'hF4040404))
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I2(thread_valid_3__2),
.I3(aid_match_30),
.I4(S_AXI_ARREADY),
.O(cmd_push_3));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[25]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[26]
(.C(aclk),
.CE(cmd_push_3),
.D(D),
.Q(active_target[26]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0
(.I0(active_cnt[32]),
.I1(cmd_push_4),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0
(.I0(cmd_push_4),
.I1(active_cnt[32]),
.I2(active_cnt[34]),
.I3(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0
(.I0(active_cnt[33]),
.I1(cmd_push_4),
.I2(active_cnt[32]),
.I3(active_cnt[35]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_49 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_49 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_49 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_49 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF40004000400040))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0 ),
.I1(thread_valid_3__2),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I3(thread_valid_4__2),
.I4(aid_match_40),
.I5(S_AXI_ARREADY),
.O(cmd_push_4));
LUT6 #(
.INIT(64'h55555557FFFFFFFF))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0
(.I0(thread_valid_0__2),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.I5(thread_valid_2__2),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair145" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.O(thread_valid_3__2));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0
(.I0(active_cnt[34]),
.I1(active_cnt[35]),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.O(thread_valid_4__2));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[33]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[34]
(.C(aclk),
.CE(cmd_push_4),
.D(D),
.Q(active_target[34]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0
(.I0(active_cnt[40]),
.I1(cmd_push_5),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0
(.I0(cmd_push_5),
.I1(active_cnt[40]),
.I2(active_cnt[42]),
.I3(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0
(.I0(active_cnt[41]),
.I1(cmd_push_5),
.I2(active_cnt[40]),
.I3(active_cnt[43]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_52 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_52 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_52 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_52 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'hF4040404))
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0
(.I0(accum_push_5__0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I2(thread_valid_5__2),
.I3(aid_match_50),
.I4(S_AXI_ARREADY),
.O(cmd_push_5));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[41]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[42]
(.C(aclk),
.CE(cmd_push_5),
.D(D),
.Q(active_target[42]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair148" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair148" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0
(.I0(active_cnt[48]),
.I1(cmd_push_6),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0
(.I0(cmd_push_6),
.I1(active_cnt[48]),
.I2(active_cnt[50]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0
(.I0(active_cnt[49]),
.I1(cmd_push_6),
.I2(active_cnt[48]),
.I3(active_cnt[51]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_51 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_51 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_51 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_51 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF40004000400040))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0
(.I0(accum_push_5__0),
.I1(thread_valid_5__2),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I3(thread_valid_6__2),
.I4(aid_match_60),
.I5(S_AXI_ARREADY),
.O(cmd_push_6));
(* SOFT_HLUTNM = "soft_lutpair146" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.O(thread_valid_5__2));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0
(.I0(active_cnt[50]),
.I1(active_cnt[51]),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.O(thread_valid_6__2));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[49]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[50]
(.C(aclk),
.CE(cmd_push_6),
.D(D),
.Q(active_target[50]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0
(.I0(active_cnt[56]),
.I1(cmd_push_7),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0
(.I0(cmd_push_7),
.I1(active_cnt[56]),
.I2(active_cnt[58]),
.I3(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0
(.I0(active_cnt[57]),
.I1(cmd_push_7),
.I2(active_cnt[56]),
.I3(active_cnt[59]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0
(.I0(active_cnt[58]),
.I1(active_cnt[59]),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.O(thread_valid_7__2));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_50 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_50 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_50 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_50 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_arid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0
(.I0(\s_axi_araddr[30] [2]),
.I1(\s_axi_araddr[30] [0]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0
(.I0(\s_axi_araddr[30] [2]),
.I1(\s_axi_araddr[30] [1]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hFF404040))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0
(.I0(accum_push_5__0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ),
.I3(aid_match_7__0),
.I4(S_AXI_ARREADY),
.O(cmd_push_7));
LUT6 #(
.INIT(64'hFFFFFFFF55555557))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0
(.I0(thread_valid_3__2),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0 ),
.O(accum_push_5__0));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0
(.I0(active_cnt[58]),
.I1(active_cnt[59]),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(thread_valid_6__2),
.I5(thread_valid_5__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000002))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0
(.I0(S_AXI_ARREADY),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0 ),
.I4(aid_match_6__0),
.I5(aid_match_7__0),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.I4(aid_match_70),
.O(aid_match_7__0));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0
(.I0(aid_match_00),
.I1(thread_valid_0__2),
.I2(aid_match_10),
.I3(thread_valid_1__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0 ));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0
(.I0(aid_match_20),
.I1(thread_valid_2__2),
.I2(aid_match_30),
.I3(thread_valid_3__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0 ));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0
(.I0(aid_match_40),
.I1(thread_valid_4__2),
.I2(aid_match_50),
.I3(thread_valid_5__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0
(.I0(active_cnt[48]),
.I1(active_cnt[49]),
.I2(active_cnt[51]),
.I3(active_cnt[50]),
.I4(aid_match_60),
.O(aid_match_6__0));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0 ),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0 ),
.Q(active_target[57]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[58]
(.C(aclk),
.CE(cmd_push_7),
.D(D),
.Q(active_target[58]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc \gen_multi_thread.mux_resp_multi_thread
(.CO(p_14_out),
.D({\gen_multi_thread.mux_resp_multi_thread_n_56 ,\gen_multi_thread.mux_resp_multi_thread_n_57 ,\gen_multi_thread.mux_resp_multi_thread_n_58 }),
.E(\gen_multi_thread.mux_resp_multi_thread_n_47 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 ),
.S({\gen_multi_thread.mux_resp_multi_thread_n_60 ,\gen_multi_thread.mux_resp_multi_thread_n_61 ,\gen_multi_thread.mux_resp_multi_thread_n_62 ,\gen_multi_thread.mux_resp_multi_thread_n_63 }),
.S_AXI_ARREADY(S_AXI_ARREADY),
.\chosen_reg[0] (\s_axi_rvalid[0] ),
.cmd_push_0(cmd_push_0),
.cmd_push_1(cmd_push_1),
.cmd_push_2(cmd_push_2),
.cmd_push_3(cmd_push_3),
.cmd_push_4(cmd_push_4),
.cmd_push_5(cmd_push_5),
.cmd_push_6(cmd_push_6),
.cmd_push_7(cmd_push_7),
.f_mux4_return({f_mux4_return[47:15],f_mux4_return[13:0]}),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.mux_resp_multi_thread_n_55 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ({\gen_multi_thread.mux_resp_multi_thread_n_88 ,\gen_multi_thread.mux_resp_multi_thread_n_89 ,\gen_multi_thread.mux_resp_multi_thread_n_90 ,\gen_multi_thread.mux_resp_multi_thread_n_91 }),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] (\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.mux_resp_multi_thread_n_54 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_84 ,\gen_multi_thread.mux_resp_multi_thread_n_85 ,\gen_multi_thread.mux_resp_multi_thread_n_86 ,\gen_multi_thread.mux_resp_multi_thread_n_87 }),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] (\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.mux_resp_multi_thread_n_53 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_80 ,\gen_multi_thread.mux_resp_multi_thread_n_81 ,\gen_multi_thread.mux_resp_multi_thread_n_82 ,\gen_multi_thread.mux_resp_multi_thread_n_83 }),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] (\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.mux_resp_multi_thread_n_48 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_76 ,\gen_multi_thread.mux_resp_multi_thread_n_77 ,\gen_multi_thread.mux_resp_multi_thread_n_78 ,\gen_multi_thread.mux_resp_multi_thread_n_79 }),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] (p_8_out),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] (\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.mux_resp_multi_thread_n_49 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_72 ,\gen_multi_thread.mux_resp_multi_thread_n_73 ,\gen_multi_thread.mux_resp_multi_thread_n_74 ,\gen_multi_thread.mux_resp_multi_thread_n_75 }),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] (\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.mux_resp_multi_thread_n_52 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_68 ,\gen_multi_thread.mux_resp_multi_thread_n_69 ,\gen_multi_thread.mux_resp_multi_thread_n_70 ,\gen_multi_thread.mux_resp_multi_thread_n_71 }),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] (\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.mux_resp_multi_thread_n_51 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_64 ,\gen_multi_thread.mux_resp_multi_thread_n_65 ,\gen_multi_thread.mux_resp_multi_thread_n_66 ,\gen_multi_thread.mux_resp_multi_thread_n_67 }),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] (\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.mux_resp_multi_thread_n_50 ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] (p_0_out),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] (\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_multi_thread.mux_resp_multi_thread_n_59 ),
.\m_payload_i_reg[34] (\m_payload_i_reg[34]_0 ),
.resp_select(resp_select),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.\s_axi_rid[10] (\s_axi_rid[10] ),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.\s_axi_rid[1] (\s_axi_rid[1] ),
.\s_axi_rid[2] (\s_axi_rid[2] ),
.\s_axi_rid[3] (\s_axi_rid[3] ),
.\s_axi_rid[4] (\s_axi_rid[4] ),
.\s_axi_rid[5] (\s_axi_rid[5] ),
.\s_axi_rid[6] (\s_axi_rid[6] ),
.\s_axi_rid[7] (\s_axi_rid[7] ),
.\s_axi_rid[8] (\s_axi_rid[8] ),
.\s_axi_rid[9] (\s_axi_rid[9] ),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.st_mr_rid(st_mr_rid[59:48]),
.thread_valid_0__2(thread_valid_0__2),
.thread_valid_1__2(thread_valid_1__2),
.thread_valid_2__2(thread_valid_2__2),
.thread_valid_3__2(thread_valid_3__2),
.thread_valid_4__2(thread_valid_4__2),
.thread_valid_5__2(thread_valid_5__2),
.thread_valid_6__2(thread_valid_6__2),
.thread_valid_7__2(thread_valid_7__2));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_target_hot_i[4]_i_1__0
(.I0(match),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair145" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_10__0
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.I4(aid_match_30),
.O(aid_match_3__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_11__0
(.I0(active_target[17]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_12__0
(.I0(active_target[18]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_13__0
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.I4(aid_match_20),
.O(aid_match_2__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_14__0
(.I0(active_target[9]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[8]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_15__0
(.I0(active_target[10]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair143" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_16__0
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.I4(aid_match_10),
.O(aid_match_1__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_17__0
(.I0(active_target[1]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_18__0
(.I0(active_target[2]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_19__0
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.I4(aid_match_00),
.O(aid_match_0__0));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_20__0
(.I0(active_target[49]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[48]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_21__0
(.I0(active_target[50]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_22__0
(.I0(active_target[57]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[56]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_23__0
(.I0(active_target[58]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_23__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_27__0
(.I0(active_target[41]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[40]),
.O(\gen_no_arbiter.s_ready_i[0]_i_27__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_28
(.I0(active_target[42]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair146" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_29__0
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.I4(aid_match_50),
.O(aid_match_5__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_30__0
(.I0(active_target[33]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[32]),
.O(\gen_no_arbiter.s_ready_i[0]_i_30__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_31
(.I0(active_target[34]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_31_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_32__0
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.I4(aid_match_40),
.O(aid_match_4__0));
(* SOFT_HLUTNM = "soft_lutpair155" *)
LUT3 #(
.INIT(8'hFE))
\gen_no_arbiter.s_ready_i[0]_i_33__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [0]),
.I1(\gen_multi_thread.accept_cnt_reg__0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg__0 [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_33__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ),
.I2(aid_match_3__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ),
.I5(aid_match_2__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_4__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ),
.I2(aid_match_1__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ),
.I5(aid_match_0__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_5__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ),
.I2(aid_match_6__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_23__0_n_0 ),
.I5(aid_match_7__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_7__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_27__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ),
.I2(aid_match_5__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_30__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_31_n_0 ),
.I5(aid_match_4__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_8__0
(.I0(active_target[25]),
.I1(\s_axi_araddr[30] [2]),
.I2(\s_axi_araddr[30] [1]),
.I3(\s_axi_araddr[30] [0]),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_9__0
(.I0(active_target[26]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_araddr[30] [0]),
.I3(\s_axi_araddr[30] [2]),
.I4(\s_axi_araddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_60 ,\gen_multi_thread.mux_resp_multi_thread_n_61 ,\gen_multi_thread.mux_resp_multi_thread_n_62 ,\gen_multi_thread.mux_resp_multi_thread_n_63 }));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_80 ,\gen_multi_thread.mux_resp_multi_thread_n_81 ,\gen_multi_thread.mux_resp_multi_thread_n_82 ,\gen_multi_thread.mux_resp_multi_thread_n_83 }));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_84 ,\gen_multi_thread.mux_resp_multi_thread_n_85 ,\gen_multi_thread.mux_resp_multi_thread_n_86 ,\gen_multi_thread.mux_resp_multi_thread_n_87 }));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_88 ,\gen_multi_thread.mux_resp_multi_thread_n_89 ,\gen_multi_thread.mux_resp_multi_thread_n_90 ,\gen_multi_thread.mux_resp_multi_thread_n_91 }));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_64 ,\gen_multi_thread.mux_resp_multi_thread_n_65 ,\gen_multi_thread.mux_resp_multi_thread_n_66 ,\gen_multi_thread.mux_resp_multi_thread_n_67 }));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_68 ,\gen_multi_thread.mux_resp_multi_thread_n_69 ,\gen_multi_thread.mux_resp_multi_thread_n_70 ,\gen_multi_thread.mux_resp_multi_thread_n_71 }));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_72 ,\gen_multi_thread.mux_resp_multi_thread_n_73 ,\gen_multi_thread.mux_resp_multi_thread_n_74 ,\gen_multi_thread.mux_resp_multi_thread_n_75 }));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_76 ,\gen_multi_thread.mux_resp_multi_thread_n_77 ,\gen_multi_thread.mux_resp_multi_thread_n_78 ,\gen_multi_thread.mux_resp_multi_thread_n_79 }));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_si_transactor" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0
(\s_axi_bid[0] ,
\s_axi_bid[1] ,
\s_axi_bid[2] ,
\s_axi_bid[3] ,
\s_axi_bid[4] ,
\s_axi_bid[5] ,
\s_axi_bid[6] ,
\s_axi_bid[7] ,
\s_axi_bid[8] ,
\s_axi_bid[9] ,
\s_axi_bid[10] ,
\s_axi_bid[11] ,
s_axi_bresp,
E,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
\gen_master_slots[3].w_issuing_cnt_reg[24] ,
\gen_master_slots[0].w_issuing_cnt_reg[0] ,
SR,
\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
D,
\s_axi_bvalid[0] ,
Q,
st_mr_bid,
w_issuing_cnt,
p_84_in,
p_66_in,
p_48_in,
p_101_in,
aresetn_d,
aa_sa_awvalid,
match,
ADDRESS_HIT_0,
\s_axi_awaddr[30] ,
\m_ready_d_reg[1] ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
s_axi_bready,
p_46_out,
p_128_out,
p_108_out,
m_valid_i_reg,
st_mr_bmesg,
p_68_out,
p_88_out,
m_valid_i_reg_0,
\s_axi_awid[11] ,
aclk);
output \s_axi_bid[0] ;
output \s_axi_bid[1] ;
output \s_axi_bid[2] ;
output \s_axi_bid[3] ;
output \s_axi_bid[4] ;
output \s_axi_bid[5] ;
output \s_axi_bid[6] ;
output \s_axi_bid[7] ;
output \s_axi_bid[8] ;
output \s_axi_bid[9] ;
output \s_axi_bid[10] ;
output \s_axi_bid[11] ;
output [1:0]s_axi_bresp;
output [0:0]E;
output [0:0]\gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]\gen_master_slots[3].w_issuing_cnt_reg[24] ;
output [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
output [0:0]SR;
output [0:0]\gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output [2:0]D;
output \s_axi_bvalid[0] ;
output [4:0]Q;
input [59:0]st_mr_bid;
input [16:0]w_issuing_cnt;
input p_84_in;
input p_66_in;
input p_48_in;
input p_101_in;
input aresetn_d;
input aa_sa_awvalid;
input match;
input ADDRESS_HIT_0;
input [2:0]\s_axi_awaddr[30] ;
input \m_ready_d_reg[1] ;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input [0:0]s_axi_bready;
input p_46_out;
input p_128_out;
input p_108_out;
input m_valid_i_reg;
input [7:0]st_mr_bmesg;
input p_68_out;
input p_88_out;
input m_valid_i_reg_0;
input [11:0]\s_axi_awid[11] ;
input aclk;
wire ADDRESS_HIT_0;
wire [2:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]SR;
wire aa_sa_awvalid;
wire accum_push_5__0;
wire aclk;
wire [59:0]active_cnt;
wire [58:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1__0_n_0;
wire aid_match_00_carry_i_2__0_n_0;
wire aid_match_00_carry_i_3__0_n_0;
wire aid_match_00_carry_i_4__0_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_0__0;
wire aid_match_10;
wire aid_match_10_carry_i_1__0_n_0;
wire aid_match_10_carry_i_2__0_n_0;
wire aid_match_10_carry_i_3__0_n_0;
wire aid_match_10_carry_i_4__0_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_1__0;
wire aid_match_20;
wire aid_match_20_carry_i_1__0_n_0;
wire aid_match_20_carry_i_2__0_n_0;
wire aid_match_20_carry_i_3__0_n_0;
wire aid_match_20_carry_i_4__0_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_2__0;
wire aid_match_30;
wire aid_match_30_carry_i_1__0_n_0;
wire aid_match_30_carry_i_2__0_n_0;
wire aid_match_30_carry_i_3__0_n_0;
wire aid_match_30_carry_i_4__0_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_3__0;
wire aid_match_40;
wire aid_match_40_carry_i_1__0_n_0;
wire aid_match_40_carry_i_2__0_n_0;
wire aid_match_40_carry_i_3__0_n_0;
wire aid_match_40_carry_i_4__0_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_4__0;
wire aid_match_50;
wire aid_match_50_carry_i_1__0_n_0;
wire aid_match_50_carry_i_2__0_n_0;
wire aid_match_50_carry_i_3__0_n_0;
wire aid_match_50_carry_i_4__0_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_5__0;
wire aid_match_60;
wire aid_match_60_carry_i_1__0_n_0;
wire aid_match_60_carry_i_2__0_n_0;
wire aid_match_60_carry_i_3__0_n_0;
wire aid_match_60_carry_i_4__0_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_6__0;
wire aid_match_70;
wire aid_match_70_carry_i_1__0_n_0;
wire aid_match_70_carry_i_2__0_n_0;
wire aid_match_70_carry_i_3__0_n_0;
wire aid_match_70_carry_i_4__0_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aid_match_7__0;
wire aresetn_d;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire [13:0]f_mux4_return;
wire [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
wire [0:0]\gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire [0:0]\gen_master_slots[3].w_issuing_cnt_reg[24] ;
wire \gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_15 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_16 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_17 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_18 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_19 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_20 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_21 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_22 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_23 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_24 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_25 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_26 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_27 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_28 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_29 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_30 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_31 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_32 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_33 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_34 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_35 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_36 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_37 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_38 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_39 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_40 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_41 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_42 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_43 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_44 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_45 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_46 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_47 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_48 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_49 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_50 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_51 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_52 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_53 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_54 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_55 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_56 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_57 ;
wire \gen_multi_thread.mux_resp_multi_thread_n_58 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_23_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_29_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_32_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_35_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_7_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9_n_0 ;
wire [0:0]\gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire match;
wire p_0_out;
wire p_0_out_0;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_101_in;
wire p_108_out;
wire p_10_out;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_128_out;
wire p_12_out;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_46_out;
wire p_48_in;
wire p_4_out;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_66_in;
wire p_68_out;
wire p_6_out;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_84_in;
wire p_88_out;
wire p_8_out;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [2:2]resp_select;
wire [2:0]\s_axi_awaddr[30] ;
wire [11:0]\s_axi_awid[11] ;
wire \s_axi_bid[0] ;
wire \s_axi_bid[10] ;
wire \s_axi_bid[11] ;
wire \s_axi_bid[1] ;
wire \s_axi_bid[2] ;
wire \s_axi_bid[3] ;
wire \s_axi_bid[4] ;
wire \s_axi_bid[5] ;
wire \s_axi_bid[6] ;
wire \s_axi_bid[7] ;
wire \s_axi_bid[8] ;
wire \s_axi_bid[9] ;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bvalid[0] ;
wire [59:0]st_mr_bid;
wire [7:0]st_mr_bmesg;
wire thread_valid_0__2;
wire thread_valid_1__2;
wire thread_valid_2__2;
wire thread_valid_3__2;
wire thread_valid_4__2;
wire thread_valid_5__2;
wire thread_valid_6__2;
wire thread_valid_7__2;
wire [16:0]w_issuing_cnt;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1__0_n_0,aid_match_00_carry_i_2__0_n_0,aid_match_00_carry_i_3__0_n_0,aid_match_00_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.O(aid_match_00_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [8]),
.O(aid_match_00_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.O(aid_match_00_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.O(aid_match_00_carry_i_4__0_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1__0_n_0,aid_match_10_carry_i_2__0_n_0,aid_match_10_carry_i_3__0_n_0,aid_match_10_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\s_axi_awid[11] [11]),
.O(aid_match_10_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg [6]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [8]),
.I5(\s_axi_awid[11] [8]),
.O(aid_match_10_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\s_axi_awid[11] [5]),
.O(aid_match_10_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I5(\s_axi_awid[11] [2]),
.O(aid_match_10_carry_i_4__0_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1__0_n_0,aid_match_20_carry_i_2__0_n_0,aid_match_20_carry_i_3__0_n_0,aid_match_20_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.O(aid_match_20_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [8]),
.O(aid_match_20_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.O(aid_match_20_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.O(aid_match_20_carry_i_4__0_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1__0_n_0,aid_match_30_carry_i_2__0_n_0,aid_match_30_carry_i_3__0_n_0,aid_match_30_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.O(aid_match_30_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [8]),
.O(aid_match_30_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.O(aid_match_30_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.O(aid_match_30_carry_i_4__0_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1__0_n_0,aid_match_40_carry_i_2__0_n_0,aid_match_40_carry_i_3__0_n_0,aid_match_40_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.O(aid_match_40_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [8]),
.O(aid_match_40_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.O(aid_match_40_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.O(aid_match_40_carry_i_4__0_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1__0_n_0,aid_match_50_carry_i_2__0_n_0,aid_match_50_carry_i_3__0_n_0,aid_match_50_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.O(aid_match_50_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [8]),
.O(aid_match_50_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.O(aid_match_50_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.O(aid_match_50_carry_i_4__0_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1__0_n_0,aid_match_60_carry_i_2__0_n_0,aid_match_60_carry_i_3__0_n_0,aid_match_60_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.O(aid_match_60_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [8]),
.O(aid_match_60_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.O(aid_match_60_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.O(aid_match_60_carry_i_4__0_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1__0_n_0,aid_match_70_carry_i_2__0_n_0,aid_match_70_carry_i_3__0_n_0,aid_match_70_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1__0
(.I0(\s_axi_awid[11] [10]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I2(\s_axi_awid[11] [9]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I4(\s_axi_awid[11] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.O(aid_match_70_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2__0
(.I0(\s_axi_awid[11] [7]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [7]),
.I2(\s_axi_awid[11] [6]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [6]),
.I4(\s_axi_awid[11] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [8]),
.O(aid_match_70_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3__0
(.I0(\s_axi_awid[11] [4]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I2(\s_axi_awid[11] [3]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.I4(\s_axi_awid[11] [5]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.O(aid_match_70_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4__0
(.I0(\s_axi_awid[11] [1]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I2(\s_axi_awid[11] [0]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.I4(\s_axi_awid[11] [2]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.O(aid_match_70_carry_i_4__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_23 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_23 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_26 ),
.Q(\gen_multi_thread.accept_cnt_reg [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_23 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_25 ),
.Q(\gen_multi_thread.accept_cnt_reg [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_23 ),
.D(\gen_multi_thread.mux_resp_multi_thread_n_24 ),
.Q(\gen_multi_thread.accept_cnt_reg [3]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp \gen_multi_thread.arbiter_resp_inst
(.ADDRESS_HIT_0(ADDRESS_HIT_0),
.E(E),
.Q(\gen_multi_thread.accept_cnt_reg [3]),
.SR(SR),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.f_mux4_return(f_mux4_return),
.\gen_master_slots[0].w_issuing_cnt_reg[0] (\gen_master_slots[0].w_issuing_cnt_reg[0] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.\gen_master_slots[3].w_issuing_cnt_reg[24] (\gen_master_slots[3].w_issuing_cnt_reg[24] ),
.\gen_multi_thread.accept_cnt_reg[0] (\gen_no_arbiter.s_ready_i[0]_i_35_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_target_reg[9] (\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_target_reg[25] (\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_target_reg[41] (\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_target_reg[49] (\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(m_valid_i_reg),
.m_valid_i_reg_0(m_valid_i_reg_0),
.match(match),
.p_0_out(p_0_out_0),
.p_101_in(p_101_in),
.p_108_out(p_108_out),
.p_128_out(p_128_out),
.p_46_out(p_46_out),
.p_48_in(p_48_in),
.p_66_in(p_66_in),
.p_68_out(p_68_out),
.p_84_in(p_84_in),
.p_88_out(p_88_out),
.resp_select(resp_select),
.\s_axi_awaddr[30] (\s_axi_awaddr[30] ),
.s_axi_bready(s_axi_bready),
.\s_axi_bvalid[0] (\s_axi_bvalid[0] ),
.s_ready_i_reg(Q),
.st_mr_bid(st_mr_bid[47:0]),
.st_mr_bmesg(st_mr_bmesg),
.w_issuing_cnt(w_issuing_cnt));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1
(.I0(active_cnt[0]),
.I1(cmd_push_0),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[2]),
.I3(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2
(.I0(active_cnt[1]),
.I1(cmd_push_0),
.I2(active_cnt[0]),
.I3(active_cnt[3]),
.I4(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.R(SR));
LUT4 #(
.INIT(16'hE222))
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I1(thread_valid_0__2),
.I2(aid_match_00),
.I3(\m_ready_d_reg[1] ),
.O(cmd_push_0));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(D[0]),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(D[1]),
.Q(active_target[1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(D[2]),
.Q(active_target[2]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1
(.I0(cmd_push_1),
.I1(active_cnt[8]),
.I2(active_cnt[10]),
.I3(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2
(.I0(active_cnt[9]),
.I1(cmd_push_1),
.I2(active_cnt[8]),
.I3(active_cnt[11]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair184" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair184" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1
(.I0(active_cnt[8]),
.I1(cmd_push_1),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_22 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_22 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_22 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_22 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'hF8080808))
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I1(thread_valid_0__2),
.I2(thread_valid_1__2),
.I3(aid_match_10),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_1));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[10]
(.C(aclk),
.CE(cmd_push_1),
.D(D[2]),
.Q(active_target[10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(D[0]),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(D[1]),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1
(.I0(active_cnt[16]),
.I1(cmd_push_2),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1
(.I0(cmd_push_2),
.I1(active_cnt[16]),
.I2(active_cnt[18]),
.I3(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2
(.I0(active_cnt[17]),
.I1(cmd_push_2),
.I2(active_cnt[16]),
.I3(active_cnt[19]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_21 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_21 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_21 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_21 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF80008000800080))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I1(thread_valid_0__2),
.I2(thread_valid_1__2),
.I3(thread_valid_2__2),
.I4(aid_match_20),
.I5(\m_ready_d_reg[1] ),
.O(cmd_push_2));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2
(.I0(active_cnt[2]),
.I1(active_cnt[3]),
.I2(active_cnt[1]),
.I3(active_cnt[0]),
.O(thread_valid_0__2));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.O(thread_valid_1__2));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.O(thread_valid_2__2));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(D[0]),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(D[1]),
.Q(active_target[17]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[18]
(.C(aclk),
.CE(cmd_push_2),
.D(D[2]),
.Q(active_target[18]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1
(.I0(active_cnt[24]),
.I1(cmd_push_3),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[26]),
.I3(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2
(.I0(active_cnt[25]),
.I1(cmd_push_3),
.I2(active_cnt[24]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'hF4040404))
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I2(thread_valid_3__2),
.I3(aid_match_30),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_3));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(D[0]),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(D[1]),
.Q(active_target[25]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[26]
(.C(aclk),
.CE(cmd_push_3),
.D(D[2]),
.Q(active_target[26]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1
(.I0(active_cnt[32]),
.I1(cmd_push_4),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1
(.I0(cmd_push_4),
.I1(active_cnt[32]),
.I2(active_cnt[34]),
.I3(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2
(.I0(active_cnt[33]),
.I1(cmd_push_4),
.I2(active_cnt[32]),
.I3(active_cnt[35]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_17 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_17 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_17 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_17 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF40004000400040))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0 ),
.I1(thread_valid_3__2),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I3(thread_valid_4__2),
.I4(aid_match_40),
.I5(\m_ready_d_reg[1] ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'h55555557FFFFFFFF))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2
(.I0(thread_valid_0__2),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.I5(thread_valid_2__2),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.O(thread_valid_3__2));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4
(.I0(active_cnt[34]),
.I1(active_cnt[35]),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.O(thread_valid_4__2));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(D[0]),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(D[1]),
.Q(active_target[33]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[34]
(.C(aclk),
.CE(cmd_push_4),
.D(D[2]),
.Q(active_target[34]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair185" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair185" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1
(.I0(active_cnt[40]),
.I1(cmd_push_5),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1
(.I0(cmd_push_5),
.I1(active_cnt[40]),
.I2(active_cnt[42]),
.I3(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2
(.I0(active_cnt[41]),
.I1(cmd_push_5),
.I2(active_cnt[40]),
.I3(active_cnt[43]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_20 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_20 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_20 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_20 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'hF4040404))
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1
(.I0(accum_push_5__0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I2(thread_valid_5__2),
.I3(aid_match_50),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_5));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(D[0]),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(D[1]),
.Q(active_target[41]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[42]
(.C(aclk),
.CE(cmd_push_5),
.D(D[2]),
.Q(active_target[42]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1
(.I0(active_cnt[48]),
.I1(cmd_push_6),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1
(.I0(cmd_push_6),
.I1(active_cnt[48]),
.I2(active_cnt[50]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2
(.I0(active_cnt[49]),
.I1(cmd_push_6),
.I2(active_cnt[48]),
.I3(active_cnt[51]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_19 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_19 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_19 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_19 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'hFF40004000400040))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1
(.I0(accum_push_5__0),
.I1(thread_valid_5__2),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I3(thread_valid_6__2),
.I4(aid_match_60),
.I5(\m_ready_d_reg[1] ),
.O(cmd_push_6));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.O(thread_valid_5__2));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3
(.I0(active_cnt[50]),
.I1(active_cnt[51]),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.O(thread_valid_6__2));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(D[0]),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(D[1]),
.Q(active_target[49]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[50]
(.C(aclk),
.CE(cmd_push_6),
.D(D[2]),
.Q(active_target[50]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair186" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair186" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1
(.I0(active_cnt[56]),
.I1(cmd_push_7),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT4 #(
.INIT(16'h78E1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1
(.I0(cmd_push_7),
.I1(active_cnt[56]),
.I2(active_cnt[58]),
.I3(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2
(.I0(active_cnt[57]),
.I1(cmd_push_7),
.I2(active_cnt[56]),
.I3(active_cnt[59]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4
(.I0(active_cnt[58]),
.I1(active_cnt[59]),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.O(thread_valid_7__2));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_18 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_18 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_18 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.mux_resp_multi_thread_n_18 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awid[11] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1
(.I0(\s_axi_awaddr[30] [2]),
.I1(\s_axi_awaddr[30] [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1
(.I0(\s_axi_awaddr[30] [2]),
.I1(\s_axi_awaddr[30] [1]),
.O(D[1]));
LUT5 #(
.INIT(32'hFF404040))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1
(.I0(accum_push_5__0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ),
.I3(aid_match_7__0),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_7));
LUT6 #(
.INIT(64'hFFFFFFFF55555557))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2
(.I0(thread_valid_3__2),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0 ),
.O(accum_push_5__0));
LUT6 #(
.INIT(64'h0001000000000000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3
(.I0(active_cnt[58]),
.I1(active_cnt[59]),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(thread_valid_6__2),
.I5(thread_valid_5__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000002))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0 ),
.I4(aid_match_6__0),
.I5(aid_match_7__0),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.I4(aid_match_70),
.O(aid_match_7__0));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6
(.I0(aid_match_00),
.I1(thread_valid_0__2),
.I2(aid_match_10),
.I3(thread_valid_1__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0 ));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7
(.I0(aid_match_20),
.I1(thread_valid_2__2),
.I2(aid_match_30),
.I3(thread_valid_3__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0 ));
LUT4 #(
.INIT(16'hF888))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8
(.I0(aid_match_40),
.I1(thread_valid_4__2),
.I2(aid_match_50),
.I3(thread_valid_5__2),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9
(.I0(active_cnt[48]),
.I1(active_cnt[49]),
.I2(active_cnt[51]),
.I3(active_cnt[50]),
.I4(aid_match_60),
.O(aid_match_6__0));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(D[0]),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(D[1]),
.Q(active_target[57]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[58]
(.C(aclk),
.CE(cmd_push_7),
.D(D[2]),
.Q(active_target[58]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0 \gen_multi_thread.mux_resp_multi_thread
(.CO(p_14_out),
.D({\gen_multi_thread.mux_resp_multi_thread_n_24 ,\gen_multi_thread.mux_resp_multi_thread_n_25 ,\gen_multi_thread.mux_resp_multi_thread_n_26 }),
.E(\gen_multi_thread.mux_resp_multi_thread_n_15 ),
.Q(\gen_multi_thread.accept_cnt_reg ),
.S({\gen_multi_thread.mux_resp_multi_thread_n_27 ,\gen_multi_thread.mux_resp_multi_thread_n_28 ,\gen_multi_thread.mux_resp_multi_thread_n_29 ,\gen_multi_thread.mux_resp_multi_thread_n_30 }),
.cmd_push_0(cmd_push_0),
.cmd_push_1(cmd_push_1),
.cmd_push_2(cmd_push_2),
.cmd_push_3(cmd_push_3),
.cmd_push_4(cmd_push_4),
.cmd_push_5(cmd_push_5),
.cmd_push_6(cmd_push_6),
.cmd_push_7(cmd_push_7),
.f_mux4_return(f_mux4_return),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.mux_resp_multi_thread_n_23 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ({\gen_multi_thread.mux_resp_multi_thread_n_55 ,\gen_multi_thread.mux_resp_multi_thread_n_56 ,\gen_multi_thread.mux_resp_multi_thread_n_57 ,\gen_multi_thread.mux_resp_multi_thread_n_58 }),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] (\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.mux_resp_multi_thread_n_22 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_51 ,\gen_multi_thread.mux_resp_multi_thread_n_52 ,\gen_multi_thread.mux_resp_multi_thread_n_53 ,\gen_multi_thread.mux_resp_multi_thread_n_54 }),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.mux_resp_multi_thread_n_21 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_47 ,\gen_multi_thread.mux_resp_multi_thread_n_48 ,\gen_multi_thread.mux_resp_multi_thread_n_49 ,\gen_multi_thread.mux_resp_multi_thread_n_50 }),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.mux_resp_multi_thread_n_16 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_43 ,\gen_multi_thread.mux_resp_multi_thread_n_44 ,\gen_multi_thread.mux_resp_multi_thread_n_45 ,\gen_multi_thread.mux_resp_multi_thread_n_46 }),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] (p_8_out),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.mux_resp_multi_thread_n_17 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_39 ,\gen_multi_thread.mux_resp_multi_thread_n_40 ,\gen_multi_thread.mux_resp_multi_thread_n_41 ,\gen_multi_thread.mux_resp_multi_thread_n_42 }),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.mux_resp_multi_thread_n_20 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_35 ,\gen_multi_thread.mux_resp_multi_thread_n_36 ,\gen_multi_thread.mux_resp_multi_thread_n_37 ,\gen_multi_thread.mux_resp_multi_thread_n_38 }),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.mux_resp_multi_thread_n_19 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ({\gen_multi_thread.mux_resp_multi_thread_n_31 ,\gen_multi_thread.mux_resp_multi_thread_n_32 ,\gen_multi_thread.mux_resp_multi_thread_n_33 ,\gen_multi_thread.mux_resp_multi_thread_n_34 }),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.mux_resp_multi_thread_n_18 ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] (p_0_out),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\m_ready_d_reg[1] (\m_ready_d_reg[1] ),
.m_valid_i_reg(\s_axi_bvalid[0] ),
.p_0_out(p_0_out_0),
.resp_select(resp_select),
.\s_axi_bid[0] (\s_axi_bid[0] ),
.\s_axi_bid[10] (\s_axi_bid[10] ),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.\s_axi_bid[1] (\s_axi_bid[1] ),
.\s_axi_bid[2] (\s_axi_bid[2] ),
.\s_axi_bid[3] (\s_axi_bid[3] ),
.\s_axi_bid[4] (\s_axi_bid[4] ),
.\s_axi_bid[5] (\s_axi_bid[5] ),
.\s_axi_bid[6] (\s_axi_bid[6] ),
.\s_axi_bid[7] (\s_axi_bid[7] ),
.\s_axi_bid[8] (\s_axi_bid[8] ),
.\s_axi_bid[9] (\s_axi_bid[9] ),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.st_mr_bid(st_mr_bid[59:48]),
.thread_valid_0__2(thread_valid_0__2),
.thread_valid_1__2(thread_valid_1__2),
.thread_valid_2__2(thread_valid_2__2),
.thread_valid_3__2(thread_valid_3__2),
.thread_valid_4__2(thread_valid_4__2),
.thread_valid_5__2(thread_valid_5__2),
.thread_valid_6__2(thread_valid_6__2),
.thread_valid_7__2(thread_valid_7__2));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_target_hot_i[4]_i_1
(.I0(match),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_10
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.I4(aid_match_30),
.O(aid_match_3__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_11
(.I0(active_target[17]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_12
(.I0(active_target[18]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_13
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.I4(aid_match_20),
.O(aid_match_2__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_14
(.I0(active_target[9]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[8]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_15
(.I0(active_target[10]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_16
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.I4(aid_match_10),
.O(aid_match_1__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_17
(.I0(active_target[1]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_18
(.I0(active_target[2]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_19
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.I4(aid_match_00),
.O(aid_match_0__0));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_20
(.I0(active_target[49]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[48]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_21
(.I0(active_target[50]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_22
(.I0(active_target[57]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[56]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_23
(.I0(active_target[58]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_28__0
(.I0(active_target[41]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[40]),
.O(\gen_no_arbiter.s_ready_i[0]_i_28__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_29
(.I0(active_target[42]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_29_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_3
(.I0(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ),
.I2(aid_match_3__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ),
.I5(aid_match_2__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_30
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.I4(aid_match_50),
.O(aid_match_5__0));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_31__0
(.I0(active_target[33]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[32]),
.O(\gen_no_arbiter.s_ready_i[0]_i_31__0_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_32
(.I0(active_target[34]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_32_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT5 #(
.INIT(32'hFFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_33
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.I4(aid_match_40),
.O(aid_match_4__0));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT3 #(
.INIT(8'hFE))
\gen_no_arbiter.s_ready_i[0]_i_35
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.I1(\gen_multi_thread.accept_cnt_reg [2]),
.I2(\gen_multi_thread.accept_cnt_reg [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_35_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_4
(.I0(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ),
.I2(aid_match_1__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ),
.I5(aid_match_0__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_5
(.I0(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ),
.I2(aid_match_6__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ),
.I5(aid_match_7__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFE0E0E0E0E0))
\gen_no_arbiter.s_ready_i[0]_i_7
(.I0(\gen_no_arbiter.s_ready_i[0]_i_28__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_29_n_0 ),
.I2(aid_match_5__0),
.I3(\gen_no_arbiter.s_ready_i[0]_i_31__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_32_n_0 ),
.I5(aid_match_4__0),
.O(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'h5677FFDE))
\gen_no_arbiter.s_ready_i[0]_i_8
(.I0(active_target[25]),
.I1(\s_axi_awaddr[30] [2]),
.I2(\s_axi_awaddr[30] [1]),
.I3(\s_axi_awaddr[30] [0]),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_no_arbiter.s_ready_i[0]_i_9
(.I0(active_target[26]),
.I1(ADDRESS_HIT_0),
.I2(\s_axi_awaddr[30] [0]),
.I3(\s_axi_awaddr[30] [2]),
.I4(\s_axi_awaddr[30] [1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_27 ,\gen_multi_thread.mux_resp_multi_thread_n_28 ,\gen_multi_thread.mux_resp_multi_thread_n_29 ,\gen_multi_thread.mux_resp_multi_thread_n_30 }));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_47 ,\gen_multi_thread.mux_resp_multi_thread_n_48 ,\gen_multi_thread.mux_resp_multi_thread_n_49 ,\gen_multi_thread.mux_resp_multi_thread_n_50 }));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_51 ,\gen_multi_thread.mux_resp_multi_thread_n_52 ,\gen_multi_thread.mux_resp_multi_thread_n_53 ,\gen_multi_thread.mux_resp_multi_thread_n_54 }));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_55 ,\gen_multi_thread.mux_resp_multi_thread_n_56 ,\gen_multi_thread.mux_resp_multi_thread_n_57 ,\gen_multi_thread.mux_resp_multi_thread_n_58 }));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_31 ,\gen_multi_thread.mux_resp_multi_thread_n_32 ,\gen_multi_thread.mux_resp_multi_thread_n_33 ,\gen_multi_thread.mux_resp_multi_thread_n_34 }));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_35 ,\gen_multi_thread.mux_resp_multi_thread_n_36 ,\gen_multi_thread.mux_resp_multi_thread_n_37 ,\gen_multi_thread.mux_resp_multi_thread_n_38 }));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_39 ,\gen_multi_thread.mux_resp_multi_thread_n_40 ,\gen_multi_thread.mux_resp_multi_thread_n_41 ,\gen_multi_thread.mux_resp_multi_thread_n_42 }));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.mux_resp_multi_thread_n_43 ,\gen_multi_thread.mux_resp_multi_thread_n_44 ,\gen_multi_thread.mux_resp_multi_thread_n_45 ,\gen_multi_thread.mux_resp_multi_thread_n_46 }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
(\s_axi_awready[0] ,
m_ready_d,
ss_wr_awvalid,
ss_wr_awready,
ss_aa_awready,
s_axi_awvalid,
aresetn_d,
aclk);
output \s_axi_awready[0] ;
output [1:0]m_ready_d;
output ss_wr_awvalid;
input ss_wr_awready;
input ss_aa_awready;
input [0:0]s_axi_awvalid;
input aresetn_d;
input aclk;
wire aclk;
wire aresetn_d;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \s_axi_awready[0] ;
wire [0:0]s_axi_awvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
LUT6 #(
.INIT(64'h000C0008000C0000))
\m_ready_d[0]_i_1
(.I0(s_axi_awvalid),
.I1(aresetn_d),
.I2(m_ready_d[1]),
.I3(ss_wr_awready),
.I4(m_ready_d[0]),
.I5(ss_aa_awready),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000000C8C0))
\m_ready_d[1]_i_1
(.I0(s_axi_awvalid),
.I1(aresetn_d),
.I2(m_ready_d[1]),
.I3(ss_wr_awready),
.I4(m_ready_d[0]),
.I5(ss_aa_awready),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT2 #(
.INIT(4'h2))
m_valid_i_i_2__0
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.O(ss_wr_awvalid));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT4 #(
.INIT(16'hEEE0))
\s_axi_awready[0]_INST_0
(.I0(m_ready_d[1]),
.I1(ss_wr_awready),
.I2(m_ready_d[0]),
.I3(ss_aa_awready),
.O(\s_axi_awready[0] ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5
(D,
\gen_axi.s_axi_awready_i_reg ,
\gen_master_slots[2].w_issuing_cnt_reg[19] ,
\gen_master_slots[3].w_issuing_cnt_reg[27] ,
\gen_master_slots[0].w_issuing_cnt_reg[3] ,
m_ready_d,
w_issuing_cnt,
Q,
m_axi_awready,
s_axi_bready,
p_108_out,
\chosen_reg[3] ,
p_88_out,
p_68_out,
p_128_out,
aa_sa_awvalid,
aresetn_d,
mi_awready_mux__3,
s_ready_i0__1,
sa_wm_awready_mux__3,
aclk);
output [2:0]D;
output \gen_axi.s_axi_awready_i_reg ;
output [2:0]\gen_master_slots[2].w_issuing_cnt_reg[19] ;
output [2:0]\gen_master_slots[3].w_issuing_cnt_reg[27] ;
output [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
output [1:0]m_ready_d;
input [15:0]w_issuing_cnt;
input [3:0]Q;
input [3:0]m_axi_awready;
input [0:0]s_axi_bready;
input p_108_out;
input [3:0]\chosen_reg[3] ;
input p_88_out;
input p_68_out;
input p_128_out;
input aa_sa_awvalid;
input aresetn_d;
input mi_awready_mux__3;
input [0:0]s_ready_i0__1;
input sa_wm_awready_mux__3;
input aclk;
wire [2:0]D;
wire [3:0]Q;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire [3:0]\chosen_reg[3] ;
wire \gen_axi.s_axi_awready_i_reg ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ;
wire [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ;
wire \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0 ;
wire [2:0]\gen_master_slots[2].w_issuing_cnt_reg[19] ;
wire \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0 ;
wire [2:0]\gen_master_slots[3].w_issuing_cnt_reg[27] ;
wire [3:0]m_axi_awready;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire mi_awready_mux__3;
wire p_108_out;
wire p_128_out;
wire p_68_out;
wire p_88_out;
wire [0:0]s_axi_bready;
wire [0:0]s_ready_i0__1;
wire sa_wm_awready_mux__3;
wire [15:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT2 #(
.INIT(4'hB))
\gen_axi.s_axi_awready_i_i_2
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.O(\gen_axi.s_axi_awready_i_reg ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[0].w_issuing_cnt[1]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I2(w_issuing_cnt[1]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].w_issuing_cnt[2]_i_1
(.I0(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I1(w_issuing_cnt[0]),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_master_slots[0].w_issuing_cnt[3]_i_2
(.I0(w_issuing_cnt[1]),
.I1(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I2(w_issuing_cnt[0]),
.I3(w_issuing_cnt[3]),
.I4(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]));
LUT6 #(
.INIT(64'h0040404040404040))
\gen_master_slots[0].w_issuing_cnt[3]_i_5
(.I0(\gen_axi.s_axi_awready_i_reg ),
.I1(Q[0]),
.I2(m_axi_awready[0]),
.I3(s_axi_bready),
.I4(p_128_out),
.I5(\chosen_reg[3] [0]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].w_issuing_cnt[10]_i_1
(.I0(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I1(w_issuing_cnt[4]),
.I2(w_issuing_cnt[5]),
.I3(w_issuing_cnt[6]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_master_slots[1].w_issuing_cnt[11]_i_2
(.I0(w_issuing_cnt[5]),
.I1(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I2(w_issuing_cnt[4]),
.I3(w_issuing_cnt[7]),
.I4(w_issuing_cnt[6]),
.O(D[2]));
LUT6 #(
.INIT(64'h0040404040404040))
\gen_master_slots[1].w_issuing_cnt[11]_i_5
(.I0(\gen_axi.s_axi_awready_i_reg ),
.I1(Q[1]),
.I2(m_axi_awready[1]),
.I3(s_axi_bready),
.I4(p_108_out),
.I5(\chosen_reg[3] [1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[1].w_issuing_cnt[9]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I2(w_issuing_cnt[5]),
.O(D[0]));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[2].w_issuing_cnt[17]_i_1
(.I0(w_issuing_cnt[8]),
.I1(\gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0 ),
.I2(w_issuing_cnt[9]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[19] [0]));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[2].w_issuing_cnt[18]_i_1
(.I0(\gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0 ),
.I1(w_issuing_cnt[8]),
.I2(w_issuing_cnt[9]),
.I3(w_issuing_cnt[10]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[19] [1]));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_master_slots[2].w_issuing_cnt[19]_i_2
(.I0(w_issuing_cnt[9]),
.I1(\gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0 ),
.I2(w_issuing_cnt[8]),
.I3(w_issuing_cnt[11]),
.I4(w_issuing_cnt[10]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[19] [2]));
LUT6 #(
.INIT(64'h0040404040404040))
\gen_master_slots[2].w_issuing_cnt[19]_i_5
(.I0(\gen_axi.s_axi_awready_i_reg ),
.I1(Q[2]),
.I2(m_axi_awready[2]),
.I3(s_axi_bready),
.I4(p_88_out),
.I5(\chosen_reg[3] [2]),
.O(\gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[3].w_issuing_cnt[25]_i_1
(.I0(w_issuing_cnt[12]),
.I1(\gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0 ),
.I2(w_issuing_cnt[13]),
.O(\gen_master_slots[3].w_issuing_cnt_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[3].w_issuing_cnt[26]_i_1
(.I0(\gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0 ),
.I1(w_issuing_cnt[12]),
.I2(w_issuing_cnt[13]),
.I3(w_issuing_cnt[14]),
.O(\gen_master_slots[3].w_issuing_cnt_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT5 #(
.INIT(32'h7F80FE01))
\gen_master_slots[3].w_issuing_cnt[27]_i_2
(.I0(w_issuing_cnt[13]),
.I1(\gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0 ),
.I2(w_issuing_cnt[12]),
.I3(w_issuing_cnt[15]),
.I4(w_issuing_cnt[14]),
.O(\gen_master_slots[3].w_issuing_cnt_reg[27] [2]));
LUT6 #(
.INIT(64'h0040404040404040))
\gen_master_slots[3].w_issuing_cnt[27]_i_5
(.I0(\gen_axi.s_axi_awready_i_reg ),
.I1(Q[3]),
.I2(m_axi_awready[3]),
.I3(s_axi_bready),
.I4(p_68_out),
.I5(\chosen_reg[3] [3]),
.O(\gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0 ));
LUT6 #(
.INIT(64'h000C0008000C0000))
\m_ready_d[0]_i_1
(.I0(aa_sa_awvalid),
.I1(aresetn_d),
.I2(m_ready_d[1]),
.I3(mi_awready_mux__3),
.I4(m_ready_d[0]),
.I5(sa_wm_awready_mux__3),
.O(\m_ready_d[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT5 #(
.INIT(32'h0000C8C0))
\m_ready_d[1]_i_1
(.I0(aa_sa_awvalid),
.I1(aresetn_d),
.I2(m_ready_d[1]),
.I3(mi_awready_mux__3),
.I4(s_ready_i0__1),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router
(ss_wr_awready,
m_axi_wvalid,
s_axi_wready,
write_cs0__0,
D,
aclk,
SR,
match,
m_ready_d,
s_axi_awvalid,
\s_axi_awaddr[30] ,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready,
p_22_in,
ss_wr_awvalid);
output ss_wr_awready;
output [3:0]m_axi_wvalid;
output [0:0]s_axi_wready;
output write_cs0__0;
input [2:0]D;
input aclk;
input [0:0]SR;
input match;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [2:0]\s_axi_awaddr[30] ;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [3:0]m_axi_wready;
input p_22_in;
input ss_wr_awvalid;
wire [2:0]D;
wire [0:0]SR;
wire aclk;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire match;
wire p_22_in;
wire [2:0]\s_axi_awaddr[30] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire write_cs0__0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo wrouter_aw_fifo
(.D(D),
.SR(SR),
.aclk(aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d),
.match(match),
.p_22_in(p_22_in),
.\s_axi_awaddr[30] (\s_axi_awaddr[30] ),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.write_cs0__0(write_cs0__0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
(ss_wr_awready,
m_axi_wvalid,
s_axi_wready,
write_cs0__0,
D,
aclk,
SR,
match,
m_ready_d,
s_axi_awvalid,
\s_axi_awaddr[30] ,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready,
p_22_in,
ss_wr_awvalid);
output ss_wr_awready;
output [3:0]m_axi_wvalid;
output [0:0]s_axi_wready;
output write_cs0__0;
input [2:0]D;
input aclk;
input [0:0]SR;
input match;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [2:0]\s_axi_awaddr[30] ;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [3:0]m_axi_wready;
input p_22_in;
input ss_wr_awvalid;
wire \/FSM_onehot_state[1]_i_1_n_0 ;
wire \/FSM_onehot_state[2]_i_1_n_0 ;
wire [2:0]D;
wire \FSM_onehot_state[0]_i_1_n_0 ;
wire \FSM_onehot_state[3]_i_2_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire [2:0]fifoaddr;
wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[2]_i_1_n_0 ;
wire \gen_srls[0].gen_rep[0].srl_nx1_n_0 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_0 ;
wire \gen_srls[0].gen_rep[2].srl_nx1_n_1 ;
wire load_s1;
wire m_aready0__3;
wire m_aready__1;
wire m_avalid;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire [2:0]m_select_enc;
wire m_valid_i__0;
wire m_valid_i_n_0;
wire match;
wire p_0_in5_out;
(* RTL_KEEP = "yes" *) wire p_0_in8_in;
wire p_22_in;
(* RTL_KEEP = "yes" *) wire p_9_in;
wire push;
wire [2:0]\s_axi_awaddr[30] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i1__4;
wire s_ready_i_i_1__9_n_0;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire write_cs0__0;
LUT5 #(
.INIT(32'h20202F20))
\/FSM_onehot_state[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB0B0B0BF))
\/FSM_onehot_state[2]_i_1
(.I0(m_ready_d),
.I1(s_axi_awvalid),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h008A0000))
\FSM_onehot_state[0]_i_1
(.I0(m_aready__1),
.I1(m_ready_d),
.I2(s_axi_awvalid),
.I3(p_9_in),
.I4(p_0_in8_in),
.O(\FSM_onehot_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFF488F488F488))
\FSM_onehot_state[3]_i_1
(.I0(m_aready__1),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i__0));
LUT5 #(
.INIT(32'h00007500))
\FSM_onehot_state[3]_i_2
(.I0(m_aready__1),
.I1(m_ready_d),
.I2(s_axi_awvalid),
.I3(p_0_in8_in),
.I4(p_9_in),
.O(\FSM_onehot_state[3]_i_2_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(aclk),
.CE(m_valid_i__0),
.D(\FSM_onehot_state[0]_i_1_n_0 ),
.Q(p_9_in),
.S(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(aclk),
.CE(m_valid_i__0),
.D(\/FSM_onehot_state[1]_i_1_n_0 ),
.Q(p_0_in8_in),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(aclk),
.CE(m_valid_i__0),
.D(\/FSM_onehot_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[2] ),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(aclk),
.CE(m_valid_i__0),
.D(\FSM_onehot_state[3]_i_2_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(areset_d1));
FDRE areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(SR),
.Q(areset_d1),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000800000))
\gen_axi.write_cs[1]_i_2
(.I0(s_axi_wlast),
.I1(m_avalid),
.I2(s_axi_wvalid),
.I3(m_select_enc[0]),
.I4(m_select_enc[2]),
.I5(m_select_enc[1]),
.O(write_cs0__0));
LUT4 #(
.INIT(16'h8778))
\gen_rep[0].fifoaddr[0]_i_1
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(push),
.I3(fifoaddr[0]),
.O(\gen_rep[0].fifoaddr[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8FF77008))
\gen_rep[0].fifoaddr[1]_i_1
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(fifoaddr[0]),
.I3(push),
.I4(fifoaddr[1]),
.O(\gen_rep[0].fifoaddr[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8FFFFFF770000008))
\gen_rep[0].fifoaddr[2]_i_1
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(fifoaddr[0]),
.I3(fifoaddr[1]),
.I4(push),
.I5(fifoaddr[2]),
.O(\gen_rep[0].fifoaddr[2]_i_1_n_0 ));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ),
.Q(fifoaddr[0]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ),
.Q(fifoaddr[1]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[2]_i_1_n_0 ),
.Q(fifoaddr[2]),
.S(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0 \gen_srls[0].gen_rep[0].srl_nx1
(.D(D[0]),
.aclk(aclk),
.fifoaddr(fifoaddr),
.load_s1(load_s1),
.m_select_enc(m_select_enc[0]),
.out0(\FSM_onehot_state_reg_n_0_[3] ),
.push(push),
.\s_axi_awaddr[30] ({\s_axi_awaddr[30] [2],\s_axi_awaddr[30] [0]}),
.\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6 \gen_srls[0].gen_rep[1].srl_nx1
(.D(D[1]),
.aclk(aclk),
.fifoaddr(fifoaddr),
.load_s1(load_s1),
.m_select_enc(m_select_enc[1]),
.out0(\FSM_onehot_state_reg_n_0_[3] ),
.push(push),
.\s_axi_awaddr[30] (\s_axi_awaddr[30] [2:1]),
.\storage_data1_reg[1] (\gen_srls[0].gen_rep[1].srl_nx1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7 \gen_srls[0].gen_rep[2].srl_nx1
(.D(D[2]),
.aclk(aclk),
.fifoaddr(fifoaddr),
.load_s1(load_s1),
.m_aready0__3(m_aready0__3),
.m_aready__1(m_aready__1),
.m_avalid(m_avalid),
.m_axi_wready(m_axi_wready),
.m_ready_d(m_ready_d),
.m_select_enc(m_select_enc),
.match(match),
.out0({p_0_in8_in,\FSM_onehot_state_reg_n_0_[3] }),
.p_22_in(p_22_in),
.push(push),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.\storage_data1_reg[2] (\gen_srls[0].gen_rep[2].srl_nx1_n_1 ));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT5 #(
.INIT(32'h00000008))
\m_axi_wvalid[0]_INST_0
(.I0(s_axi_wvalid),
.I1(m_avalid),
.I2(m_select_enc[0]),
.I3(m_select_enc[1]),
.I4(m_select_enc[2]),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT5 #(
.INIT(32'h00000080))
\m_axi_wvalid[1]_INST_0
(.I0(s_axi_wvalid),
.I1(m_avalid),
.I2(m_select_enc[0]),
.I3(m_select_enc[1]),
.I4(m_select_enc[2]),
.O(m_axi_wvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[2]_INST_0
(.I0(s_axi_wvalid),
.I1(m_avalid),
.I2(m_select_enc[0]),
.I3(m_select_enc[1]),
.I4(m_select_enc[2]),
.O(m_axi_wvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT5 #(
.INIT(32'h00008000))
\m_axi_wvalid[3]_INST_0
(.I0(s_axi_wvalid),
.I1(m_avalid),
.I2(m_select_enc[0]),
.I3(m_select_enc[1]),
.I4(m_select_enc[2]),
.O(m_axi_wvalid[3]));
LUT6 #(
.INIT(64'hFFFFF400F400F400))
m_valid_i
(.I0(m_aready__1),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i_n_0));
LUT6 #(
.INIT(64'h0000000000000008))
m_valid_i_i_3
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(fifoaddr[1]),
.I3(fifoaddr[0]),
.I4(fifoaddr[2]),
.I5(push),
.O(p_0_in5_out));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(m_valid_i__0),
.D(m_valid_i_n_0),
.Q(m_avalid),
.R(areset_d1));
LUT2 #(
.INIT(4'h8))
\s_axi_wready[0]_INST_0
(.I0(m_avalid),
.I1(m_aready0__3),
.O(s_axi_wready));
LUT5 #(
.INIT(32'hF0FFF0F8))
s_ready_i_i_1__9
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(areset_d1),
.I3(s_ready_i1__4),
.I4(ss_wr_awready),
.O(s_ready_i_i_1__9_n_0));
LUT6 #(
.INIT(64'h0000700000000000))
s_ready_i_i_2__0
(.I0(m_aready__1),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(fifoaddr[2]),
.I3(fifoaddr[1]),
.I4(fifoaddr[0]),
.I5(push),
.O(s_ready_i1__4));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__9_n_0),
.Q(ss_wr_awready),
.R(SR));
LUT6 #(
.INIT(64'hA0FCA0A0A0ECA0A0))
\storage_data1[2]_i_2
(.I0(\FSM_onehot_state_reg_n_0_[3] ),
.I1(p_9_in),
.I2(m_aready__1),
.I3(m_ready_d),
.I4(s_axi_awvalid),
.I5(p_0_in8_in),
.O(load_s1));
FDRE \storage_data1_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[0].srl_nx1_n_0 ),
.Q(m_select_enc[0]),
.R(1'b0));
FDRE \storage_data1_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[1].srl_nx1_n_0 ),
.Q(m_select_enc[1]),
.R(1'b0));
FDRE \storage_data1_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[2].srl_nx1_n_1 ),
.Q(m_select_enc[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0
(\storage_data1_reg[0] ,
push,
D,
fifoaddr,
aclk,
\s_axi_awaddr[30] ,
out0,
load_s1,
m_select_enc);
output \storage_data1_reg[0] ;
input push;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input [1:0]\s_axi_awaddr[30] ;
input [0:0]out0;
input load_s1;
input [0:0]m_select_enc;
wire [0:0]D;
wire aclk;
wire [2:0]fifoaddr;
wire \gen_primitive_shifter.gen_srls[0].srl_inst_n_0 ;
wire load_s1;
wire [0:0]m_select_enc;
wire [0:0]out0;
wire push;
wire [1:0]\s_axi_awaddr[30] ;
wire \storage_data1_reg[0] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(\gen_primitive_shifter.gen_srls[0].srl_inst_n_0 ),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hF0EEFFFFF0EE0000))
\storage_data1[0]_i_1
(.I0(\s_axi_awaddr[30] [1]),
.I1(\s_axi_awaddr[30] [0]),
.I2(\gen_primitive_shifter.gen_srls[0].srl_inst_n_0 ),
.I3(out0),
.I4(load_s1),
.I5(m_select_enc),
.O(\storage_data1_reg[0] ));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6
(\storage_data1_reg[1] ,
push,
D,
fifoaddr,
aclk,
\s_axi_awaddr[30] ,
out0,
load_s1,
m_select_enc);
output \storage_data1_reg[1] ;
input push;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input [1:0]\s_axi_awaddr[30] ;
input [0:0]out0;
input load_s1;
input [0:0]m_select_enc;
wire [0:0]D;
wire aclk;
wire [2:0]fifoaddr;
wire load_s1;
wire [0:0]m_select_enc;
wire [0:0]out0;
wire p_2_out;
wire push;
wire [1:0]\s_axi_awaddr[30] ;
wire \storage_data1_reg[1] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(p_2_out),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hF0EEFFFFF0EE0000))
\storage_data1[1]_i_1
(.I0(\s_axi_awaddr[30] [1]),
.I1(\s_axi_awaddr[30] [0]),
.I2(p_2_out),
.I3(out0),
.I4(load_s1),
.I5(m_select_enc),
.O(\storage_data1_reg[1] ));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7
(push,
\storage_data1_reg[2] ,
m_aready__1,
m_aready0__3,
D,
fifoaddr,
aclk,
match,
out0,
load_s1,
m_select_enc,
ss_wr_awready,
m_ready_d,
s_axi_awvalid,
s_axi_wlast,
m_avalid,
s_axi_wvalid,
m_axi_wready,
p_22_in);
output push;
output \storage_data1_reg[2] ;
output m_aready__1;
output m_aready0__3;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input match;
input [1:0]out0;
input load_s1;
input [2:0]m_select_enc;
input ss_wr_awready;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wlast;
input m_avalid;
input [0:0]s_axi_wvalid;
input [3:0]m_axi_wready;
input p_22_in;
wire [0:0]D;
wire aclk;
wire [2:0]fifoaddr;
wire load_s1;
wire m_aready0__3;
wire m_aready__1;
wire m_avalid;
wire [3:0]m_axi_wready;
wire [0:0]m_ready_d;
wire [2:0]m_select_enc;
wire match;
wire [1:0]out0;
wire p_22_in;
wire p_3_out;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire \s_axi_wready[0]_INST_0_i_2_n_0 ;
wire [0:0]s_axi_wvalid;
wire ss_wr_awready;
wire \storage_data1_reg[2] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(p_3_out),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h0088000000F80000))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1
(.I0(ss_wr_awready),
.I1(out0[0]),
.I2(out0[1]),
.I3(m_ready_d),
.I4(s_axi_awvalid),
.I5(m_aready__1),
.O(push));
LUT4 #(
.INIT(16'h8000))
m_valid_i_i_1__8
(.I0(s_axi_wlast),
.I1(m_avalid),
.I2(s_axi_wvalid),
.I3(m_aready0__3),
.O(m_aready__1));
LUT6 #(
.INIT(64'hAAAAAFEAAAAAAAEA))
\s_axi_wready[0]_INST_0_i_1
(.I0(\s_axi_wready[0]_INST_0_i_2_n_0 ),
.I1(m_axi_wready[1]),
.I2(m_select_enc[0]),
.I3(m_select_enc[1]),
.I4(m_select_enc[2]),
.I5(m_axi_wready[2]),
.O(m_aready0__3));
LUT6 #(
.INIT(64'h0F0000CA000000CA))
\s_axi_wready[0]_INST_0_i_2
(.I0(m_axi_wready[0]),
.I1(p_22_in),
.I2(m_select_enc[2]),
.I3(m_select_enc[1]),
.I4(m_select_enc[0]),
.I5(m_axi_wready[3]),
.O(\s_axi_wready[0]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hC5FFC500))
\storage_data1[2]_i_1
(.I0(match),
.I1(p_3_out),
.I2(out0[0]),
.I3(load_s1),
.I4(m_select_enc[2]),
.O(\storage_data1_reg[2] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
(p_128_out,
m_axi_bready,
p_122_out,
\m_axi_rready[0] ,
E,
r_cmd_pop_0__1,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\chosen_reg[2] ,
\chosen_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
s_axi_rready,
\chosen_reg[0] ,
m_axi_rvalid,
\gen_master_slots[0].r_issuing_cnt_reg[3] ,
p_93_in,
p_102_out,
p_108_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
\chosen_reg[0]_0 );
output p_128_out;
output [0:0]m_axi_bready;
output p_122_out;
output \m_axi_rready[0] ;
output [0:0]E;
output r_cmd_pop_0__1;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \chosen_reg[2] ;
output \chosen_reg[2]_0 ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[0] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
input p_93_in;
input p_102_out;
input p_108_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
input [0:0]\chosen_reg[0]_0 ;
wire [13:0]D;
wire [0:0]E;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]\chosen_reg[0] ;
wire [0:0]\chosen_reg[0]_0 ;
wire \chosen_reg[2] ;
wire \chosen_reg[2]_0 ;
wire [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_102_out;
wire p_108_out;
wire p_122_out;
wire p_128_out;
wire p_1_in;
wire p_93_in;
wire r_cmd_pop_0__1;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\chosen_reg[2] (\chosen_reg[2]_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_128_out),
.p_108_out(p_108_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\chosen_reg[0] (\chosen_reg[0] ),
.\chosen_reg[0]_0 (\chosen_reg[0]_0 ),
.\chosen_reg[2] (\chosen_reg[2] ),
.\gen_master_slots[0].r_issuing_cnt_reg[3] (\gen_master_slots[0].r_issuing_cnt_reg[3] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[0] (\m_axi_rready[0] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_122_out),
.p_102_out(p_102_out),
.p_1_in(p_1_in),
.p_93_in(p_93_in),
.r_cmd_pop_0__1(r_cmd_pop_0__1),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1
(p_108_out,
m_axi_bready,
p_102_out,
\m_axi_rready[1] ,
E,
r_cmd_pop_1__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
s_axi_rready,
\chosen_reg[1] ,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
p_75_in,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
ADDRESS_HIT_0,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\m_axi_bid[23] ,
\chosen_reg[1]_0 );
output p_108_out;
output [0:0]m_axi_bready;
output p_102_out;
output \m_axi_rready[1] ;
output [0:0]E;
output r_cmd_pop_1__1;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[1] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
input p_75_in;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]D;
input ADDRESS_HIT_0;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input [13:0]\m_axi_bid[23] ;
input [0:0]\chosen_reg[1]_0 ;
wire ADDRESS_HIT_0;
wire [0:0]D;
wire [0:0]E;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]\chosen_reg[1] ;
wire [0:0]\chosen_reg[1]_0 ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [13:0]\m_axi_bid[23] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_102_out;
wire p_108_out;
wire p_1_in;
wire p_75_in;
wire r_cmd_pop_1__1;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13 b_pipe
(.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\m_axi_bid[23] (\m_axi_bid[23] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_108_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14 r_pipe
(.ADDRESS_HIT_0(ADDRESS_HIT_0),
.D(D),
.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\chosen_reg[1] (\chosen_reg[1] ),
.\chosen_reg[1]_0 (\chosen_reg[1]_0 ),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].r_issuing_cnt_reg[11] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[1] (\m_axi_rready[1] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_102_out),
.p_1_in(p_1_in),
.p_75_in(p_75_in),
.r_cmd_pop_1__1(r_cmd_pop_1__1),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2
(p_88_out,
m_axi_bready,
p_82_out,
\m_axi_rready[2] ,
E,
r_cmd_pop_2__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
s_axi_rready,
\chosen_reg[2] ,
m_axi_rvalid,
\gen_master_slots[2].r_issuing_cnt_reg[19] ,
p_57_in,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
\gen_master_slots[3].r_issuing_cnt_reg[24] ,
D,
\m_axi_bid[35] ,
\chosen_reg[2]_0 );
output p_88_out;
output [0:0]m_axi_bready;
output p_82_out;
output \m_axi_rready[2] ;
output [0:0]E;
output r_cmd_pop_2__1;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[2] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
input p_57_in;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input \gen_master_slots[3].r_issuing_cnt_reg[24] ;
input [1:0]D;
input [13:0]\m_axi_bid[35] ;
input [0:0]\chosen_reg[2]_0 ;
wire [1:0]D;
wire [0:0]E;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]\chosen_reg[2] ;
wire [0:0]\chosen_reg[2]_0 ;
wire [3:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
wire \gen_master_slots[3].r_issuing_cnt_reg[24] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [13:0]\m_axi_bid[35] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[2] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_1_in;
wire p_57_in;
wire p_82_out;
wire p_88_out;
wire r_cmd_pop_2__1;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11 b_pipe
(.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\m_axi_bid[35] (\m_axi_bid[35] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_88_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12 r_pipe
(.D(D),
.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\chosen_reg[2] (\chosen_reg[2] ),
.\chosen_reg[2]_0 (\chosen_reg[2]_0 ),
.\gen_master_slots[2].r_issuing_cnt_reg[19] (\gen_master_slots[2].r_issuing_cnt_reg[19] ),
.\gen_master_slots[3].r_issuing_cnt_reg[24] (\gen_master_slots[3].r_issuing_cnt_reg[24] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[2] (\m_axi_rready[2] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_82_out),
.p_1_in(p_1_in),
.p_57_in(p_57_in),
.r_cmd_pop_2__1(r_cmd_pop_2__1),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3
(p_68_out,
m_axi_bready,
p_1_in,
p_62_out,
\m_axi_rready[3] ,
E,
r_cmd_pop_3__1,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\chosen_reg[4] ,
\chosen_reg[4]_0 ,
\aresetn_d_reg[1] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_1 ,
s_axi_rready,
\chosen_reg[3] ,
m_axi_rvalid,
\gen_master_slots[3].r_issuing_cnt_reg[27] ,
p_39_in,
p_82_out,
p_88_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
\chosen_reg[3]_0 );
output p_68_out;
output [0:0]m_axi_bready;
output p_1_in;
output p_62_out;
output \m_axi_rready[3] ;
output [0:0]E;
output r_cmd_pop_3__1;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \chosen_reg[4] ;
output \chosen_reg[4]_0 ;
output \aresetn_d_reg[1] ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_1 ;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[3] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
input p_39_in;
input p_82_out;
input p_88_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
input [0:0]\chosen_reg[3]_0 ;
wire [13:0]D;
wire [0:0]E;
wire [0:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [0:0]\chosen_reg[3] ;
wire [0:0]\chosen_reg[3]_0 ;
wire \chosen_reg[4] ;
wire \chosen_reg[4]_0 ;
wire [3:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[3] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_1_in;
wire p_39_in;
wire p_62_out;
wire p_68_out;
wire p_82_out;
wire p_88_out;
wire r_cmd_pop_3__1;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\aresetn_d_reg[1]_1 (\aresetn_d_reg[1]_1 ),
.\chosen_reg[4] (\chosen_reg[4]_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_68_out),
.p_1_in(p_1_in),
.p_88_out(p_88_out),
.s_axi_bready(s_axi_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1]_0 ),
.\chosen_reg[3] (\chosen_reg[3] ),
.\chosen_reg[3]_0 (\chosen_reg[3]_0 ),
.\chosen_reg[4] (\chosen_reg[4] ),
.\gen_master_slots[3].r_issuing_cnt_reg[27] (\gen_master_slots[3].r_issuing_cnt_reg[27] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[3] (\m_axi_rready[3] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_62_out),
.p_1_in(p_1_in),
.p_39_in(p_39_in),
.p_82_out(p_82_out),
.r_cmd_pop_3__1(r_cmd_pop_3__1),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4
(p_46_out,
m_valid_i_reg,
mi_bready_4,
p_40_out,
mi_rready_4,
s_ready_i_reg,
r_cmd_pop_4__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_29_in,
s_axi_bready,
Q,
s_axi_rready,
\chosen_reg[4] ,
p_23_in,
\gen_axi.s_axi_rid_i_reg[11] ,
p_25_in,
D,
E);
output p_46_out;
output m_valid_i_reg;
output mi_bready_4;
output p_40_out;
output mi_rready_4;
output s_ready_i_reg;
output r_cmd_pop_4__1;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [11:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_29_in;
input [0:0]s_axi_bready;
input [0:0]Q;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[4] ;
input p_23_in;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_25_in;
input [11:0]D;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]\chosen_reg[4] ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire m_valid_i_reg;
wire mi_bready_4;
wire mi_rready_4;
wire p_1_in;
wire p_23_in;
wire p_25_in;
wire p_29_in;
wire p_40_out;
wire p_46_out;
wire r_cmd_pop_4__1;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
wire s_ready_i_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\m_payload_i_reg[2]_0 (p_46_out),
.m_valid_i_reg_0(m_valid_i_reg),
.mi_bready_4(mi_bready_4),
.p_1_in(p_1_in),
.p_29_in(p_29_in),
.s_axi_bready(s_axi_bready),
.s_ready_i_reg_0(s_ready_i_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (m_valid_i_reg),
.\chosen_reg[4] (\chosen_reg[4] ),
.\gen_axi.s_axi_rid_i_reg[11] (\gen_axi.s_axi_rid_i_reg[11] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.m_valid_i_reg_0(p_40_out),
.p_1_in(p_1_in),
.p_23_in(p_23_in),
.p_25_in(p_25_in),
.r_cmd_pop_4__1(r_cmd_pop_4__1),
.s_axi_rready(s_axi_rready),
.\skid_buffer_reg[34]_0 (mi_rready_4));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(\m_payload_i_reg[2]_0 ,
m_valid_i_reg_0,
mi_bready_4,
s_ready_i_reg_0,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_29_in,
s_axi_bready,
Q,
D);
output \m_payload_i_reg[2]_0 ;
output m_valid_i_reg_0;
output mi_bready_4;
output s_ready_i_reg_0;
output [11:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_29_in;
input [0:0]s_axi_bready;
input [0:0]Q;
input [11:0]D;
wire [11:0]D;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ;
wire \m_payload_i_reg[2]_0 ;
wire m_valid_i_i_1__0_n_0;
wire m_valid_i_reg_0;
wire mi_bready_4;
wire p_1_in;
wire p_29_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__2_n_0;
wire s_ready_i_reg_0;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0] ),
.Q(s_ready_i_reg_0),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1
(.I0(\m_payload_i_reg[2]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__0
(.I0(p_29_in),
.I1(mi_bready_4),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[2]_0 ),
.I4(Q),
.O(m_valid_i_i_1__0_n_0));
LUT1 #(
.INIT(2'h1))
m_valid_i_i_1__9
(.I0(s_ready_i_reg_0),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(\m_payload_i_reg[2]_0 ),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__2
(.I0(\m_payload_i_reg[2]_0 ),
.I1(p_29_in),
.I2(s_axi_bready),
.I3(Q),
.I4(s_ready_i_reg_0),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(mi_bready_4),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
\m_axi_bid[35] );
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input [13:0]\m_axi_bid[35] ;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ;
wire [13:0]\m_axi_bid[35] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__3_n_0;
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__3
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in ),
.D(\m_axi_bid[35] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__2
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(Q),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__3
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(Q),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__3_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__3_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
\m_axi_bid[23] );
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input [13:0]\m_axi_bid[23] ;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ;
wire [13:0]\m_axi_bid[23] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_1_n_0;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__1_n_0;
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in ),
.D(\m_axi_bid[23] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(Q),
.O(m_valid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(Q),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__1_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\chosen_reg[2] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_0 ,
p_108_out,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output \chosen_reg[2] ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_0 ;
input p_108_out;
input [13:0]D;
wire [13:0]D;
wire [0:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \chosen_reg[2] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_2_n_0;
wire p_108_out;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__0_n_0;
LUT2 #(
.INIT(4'hE))
\last_rr_hot[2]_i_2__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(p_108_out),
.O(\chosen_reg[2] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__2
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_2
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(Q),
.O(m_valid_i_i_2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_2_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(Q),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__0_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
p_1_in,
\chosen_reg[4] ,
\aresetn_d_reg[1] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
Q,
\aresetn_d_reg[1]_1 ,
p_88_out,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output p_1_in;
output \chosen_reg[4] ;
output \aresetn_d_reg[1] ;
output [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]Q;
input \aresetn_d_reg[1]_1 ;
input p_88_out;
input [13:0]D;
wire [13:0]D;
wire [0:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire \chosen_reg[4] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_1__1_n_0;
wire [1:1]p_0_in;
wire p_1_in;
wire p_88_out;
wire [0:0]s_axi_bready;
wire s_ready_i_i_2_n_0;
LUT2 #(
.INIT(4'h8))
\aresetn_d[1]_i_1
(.I0(p_0_in),
.I1(aresetn),
.O(\aresetn_d_reg[1] ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(p_0_in),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
\last_rr_hot[4]_i_3__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(p_88_out),
.O(\chosen_reg[4] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__0
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__1
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(Q),
.O(m_valid_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1]_0 ));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1
(.I0(p_0_in),
.O(p_1_in));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_2
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(Q),
.I4(\aresetn_d_reg[1]_1 ),
.O(s_ready_i_i_2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_2_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(m_valid_i_reg_0,
\skid_buffer_reg[34]_0 ,
r_cmd_pop_4__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
\chosen_reg[4] ,
p_23_in,
\gen_axi.s_axi_rid_i_reg[11] ,
p_25_in,
E);
output m_valid_i_reg_0;
output \skid_buffer_reg[34]_0 ;
output r_cmd_pop_4__1;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[4] ;
input p_23_in;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_25_in;
input [0:0]E;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]\chosen_reg[4] ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire p_23_in;
wire p_25_in;
wire r_cmd_pop_4__1;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1__6_n_0;
wire [46:34]skid_buffer;
wire \skid_buffer_reg[34]_0 ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[4].r_issuing_cnt[32]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I1(\chosen_reg[4] ),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.O(r_cmd_pop_4__1));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__3
(.I0(p_25_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [0]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [1]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [2]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [3]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [4]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [5]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [6]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [7]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [8]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [9]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [10]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__3
(.I0(\gen_axi.s_axi_rid_i_reg[11] [11]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
LUT5 #(
.INIT(32'hDDFDFDFD))
m_valid_i_i_1__5
(.I0(\skid_buffer_reg[34]_0 ),
.I1(p_23_in),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.I4(\chosen_reg[4] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hD5D5FFD5))
s_ready_i_i_1__6
(.I0(m_valid_i_reg_0),
.I1(s_axi_rready),
.I2(\chosen_reg[4] ),
.I3(\skid_buffer_reg[34]_0 ),
.I4(p_23_in),
.O(s_ready_i_i_1__6_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__6_n_0),
.Q(\skid_buffer_reg[34]_0 ),
.R(p_1_in));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(p_25_in),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10
(m_valid_i_reg_0,
\m_axi_rready[3] ,
E,
r_cmd_pop_3__1,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\chosen_reg[4] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
\chosen_reg[3] ,
m_axi_rvalid,
\gen_master_slots[3].r_issuing_cnt_reg[27] ,
p_39_in,
p_82_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
\chosen_reg[3]_0 );
output m_valid_i_reg_0;
output \m_axi_rready[3] ;
output [0:0]E;
output r_cmd_pop_3__1;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \chosen_reg[4] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[3] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
input p_39_in;
input p_82_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]\chosen_reg[3]_0 ;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]\chosen_reg[3] ;
wire [0:0]\chosen_reg[3]_0 ;
wire \chosen_reg[4] ;
wire [3:0]\gen_master_slots[3].r_issuing_cnt_reg[27] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[3] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire p_39_in;
wire p_82_out;
wire r_cmd_pop_3__1;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1__7_n_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[3].r_issuing_cnt[27]_i_1
(.I0(\gen_master_slots[3].r_issuing_cnt_reg[27] [1]),
.I1(\gen_master_slots[3].r_issuing_cnt_reg[27] [2]),
.I2(\gen_master_slots[3].r_issuing_cnt_reg[27] [0]),
.I3(\gen_master_slots[3].r_issuing_cnt_reg[27] [3]),
.I4(r_cmd_pop_3__1),
.I5(p_39_in),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[3].r_issuing_cnt[27]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(\chosen_reg[3] ),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.O(r_cmd_pop_3__1));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_38__0
(.I0(r_cmd_pop_3__1),
.I1(\gen_master_slots[3].r_issuing_cnt_reg[27] [0]),
.I2(\gen_master_slots[3].r_issuing_cnt_reg[27] [3]),
.I3(\gen_master_slots[3].r_issuing_cnt_reg[27] [1]),
.I4(\gen_master_slots[3].r_issuing_cnt_reg[27] [2]),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'hE))
\last_rr_hot[4]_i_3
(.I0(m_valid_i_reg_0),
.I1(p_82_out),
.O(\chosen_reg[4] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__7
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__2
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__2
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__2
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__2
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__2
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__2
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__2
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__2
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__2
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__2
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__2
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__2
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__2
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__2
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__2
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__2
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__2
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__2
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__2
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__2
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__2
(.I0(m_axi_rlast),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__2
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__2
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__2
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__2
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__2
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__2
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__2
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__2
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__2
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__2
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__2
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__2
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[3] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\chosen_reg[3]_0 ),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hDDFDFDFD))
m_valid_i_i_1__6
(.I0(\m_axi_rready[3] ),
.I1(m_axi_rvalid),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.I4(\chosen_reg[3] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hD5D5FFD5))
s_ready_i_i_1__7
(.I0(m_valid_i_reg_0),
.I1(s_axi_rready),
.I2(\chosen_reg[3] ),
.I3(\m_axi_rready[3] ),
.I4(m_axi_rvalid),
.O(s_ready_i_i_1__7_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__7_n_0),
.Q(\m_axi_rready[3] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[3] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12
(m_valid_i_reg_0,
\m_axi_rready[2] ,
E,
r_cmd_pop_2__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
\chosen_reg[2] ,
m_axi_rvalid,
\gen_master_slots[2].r_issuing_cnt_reg[19] ,
p_57_in,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
\gen_master_slots[3].r_issuing_cnt_reg[24] ,
D,
\chosen_reg[2]_0 );
output m_valid_i_reg_0;
output \m_axi_rready[2] ;
output [0:0]E;
output r_cmd_pop_2__1;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[2] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
input p_57_in;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input \gen_master_slots[3].r_issuing_cnt_reg[24] ;
input [1:0]D;
input [0:0]\chosen_reg[2]_0 ;
wire [1:0]D;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]\chosen_reg[2] ;
wire [0:0]\chosen_reg[2]_0 ;
wire [3:0]\gen_master_slots[2].r_issuing_cnt_reg[19] ;
wire \gen_master_slots[3].r_issuing_cnt_reg[24] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[2] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire p_57_in;
wire r_cmd_pop_2__1;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1__8_n_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[2].r_issuing_cnt[19]_i_1
(.I0(\gen_master_slots[2].r_issuing_cnt_reg[19] [1]),
.I1(\gen_master_slots[2].r_issuing_cnt_reg[19] [2]),
.I2(\gen_master_slots[2].r_issuing_cnt_reg[19] [0]),
.I3(\gen_master_slots[2].r_issuing_cnt_reg[19] [3]),
.I4(r_cmd_pop_2__1),
.I5(p_57_in),
.O(E));
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[2].r_issuing_cnt[19]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(\chosen_reg[2] ),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.O(r_cmd_pop_2__1));
LUT4 #(
.INIT(16'hECA0))
\gen_no_arbiter.s_ready_i[0]_i_26__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_37__0_n_0 ),
.I1(\gen_master_slots[3].r_issuing_cnt_reg[24] ),
.I2(D[0]),
.I3(D[1]),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_37__0
(.I0(r_cmd_pop_2__1),
.I1(\gen_master_slots[2].r_issuing_cnt_reg[19] [0]),
.I2(\gen_master_slots[2].r_issuing_cnt_reg[19] [3]),
.I3(\gen_master_slots[2].r_issuing_cnt_reg[19] [1]),
.I4(\gen_master_slots[2].r_issuing_cnt_reg[19] [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_37__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__6
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(m_axi_rlast),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__1
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__1
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__1
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__1
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__1
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__1
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[2] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\chosen_reg[2]_0 ),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hDDFDFDFD))
m_valid_i_i_1__7
(.I0(\m_axi_rready[2] ),
.I1(m_axi_rvalid),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.I4(\chosen_reg[2] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hD5D5FFD5))
s_ready_i_i_1__8
(.I0(m_valid_i_reg_0),
.I1(s_axi_rready),
.I2(\chosen_reg[2] ),
.I3(\m_axi_rready[2] ),
.I4(m_axi_rvalid),
.O(s_ready_i_i_1__8_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__8_n_0),
.Q(\m_axi_rready[2] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[2] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14
(m_valid_i_reg_0,
\m_axi_rready[1] ,
E,
r_cmd_pop_1__1,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
\chosen_reg[1] ,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
p_75_in,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
ADDRESS_HIT_0,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\chosen_reg[1]_0 );
output m_valid_i_reg_0;
output \m_axi_rready[1] ;
output [0:0]E;
output r_cmd_pop_1__1;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[1] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
input p_75_in;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]D;
input ADDRESS_HIT_0;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input [0:0]\chosen_reg[1]_0 ;
wire ADDRESS_HIT_0;
wire [0:0]D;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]\chosen_reg[1] ;
wire [0:0]\chosen_reg[1]_0 ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire p_75_in;
wire r_cmd_pop_1__1;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1__5_n_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[1].r_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]),
.I2(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]),
.I3(\gen_master_slots[1].r_issuing_cnt_reg[11] [3]),
.I4(r_cmd_pop_1__1),
.I5(p_75_in),
.O(E));
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[1].r_issuing_cnt[11]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(\chosen_reg[1] ),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.O(r_cmd_pop_1__1));
LUT4 #(
.INIT(16'hF888))
\gen_no_arbiter.s_ready_i[0]_i_25__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_35__0_n_0 ),
.I1(D),
.I2(ADDRESS_HIT_0),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_35__0
(.I0(r_cmd_pop_1__1),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]),
.I2(\gen_master_slots[1].r_issuing_cnt_reg[11] [3]),
.I3(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]),
.I4(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_35__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__5
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__0
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(m_axi_rlast),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__0
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__0
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__0
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__0
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__0
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__0
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\chosen_reg[1]_0 ),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hDDFDFDFD))
m_valid_i_i_1__4
(.I0(\m_axi_rready[1] ),
.I1(m_axi_rvalid),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.I4(\chosen_reg[1] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hD5D5FFD5))
s_ready_i_i_1__5
(.I0(m_valid_i_reg_0),
.I1(s_axi_rready),
.I2(\chosen_reg[1] ),
.I3(\m_axi_rready[1] ),
.I4(m_axi_rvalid),
.O(s_ready_i_i_1__5_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__5_n_0),
.Q(\m_axi_rready[1] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16
(m_valid_i_reg_0,
\m_axi_rready[0] ,
E,
r_cmd_pop_0__1,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\chosen_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
\chosen_reg[0] ,
m_axi_rvalid,
\gen_master_slots[0].r_issuing_cnt_reg[3] ,
p_93_in,
p_102_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
\chosen_reg[0]_0 );
output m_valid_i_reg_0;
output \m_axi_rready[0] ;
output [0:0]E;
output r_cmd_pop_0__1;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \chosen_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [0:0]\chosen_reg[0] ;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
input p_93_in;
input p_102_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]\chosen_reg[0]_0 ;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]\chosen_reg[0] ;
wire [0:0]\chosen_reg[0]_0 ;
wire \chosen_reg[2] ;
wire [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_102_out;
wire p_1_in;
wire p_93_in;
wire r_cmd_pop_0__1;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1__4_n_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_master_slots[0].r_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]),
.I1(\gen_master_slots[0].r_issuing_cnt_reg[3] [2]),
.I2(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[3] [3]),
.I4(r_cmd_pop_0__1),
.I5(p_93_in),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[0].r_issuing_cnt[3]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(\chosen_reg[0] ),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.O(r_cmd_pop_0__1));
LUT5 #(
.INIT(32'hFFFFFFEF))
\gen_no_arbiter.s_ready_i[0]_i_36__0
(.I0(r_cmd_pop_0__1),
.I1(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]),
.I2(\gen_master_slots[0].r_issuing_cnt_reg[3] [3]),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]),
.I4(\gen_master_slots[0].r_issuing_cnt_reg[3] [2]),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'hE))
\last_rr_hot[2]_i_2
(.I0(m_valid_i_reg_0),
.I1(p_102_out),
.O(\chosen_reg[2] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__4
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rlast),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\chosen_reg[0]_0 ),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hDDFDFDFD))
m_valid_i_i_1__3
(.I0(\m_axi_rready[0] ),
.I1(m_axi_rvalid),
.I2(m_valid_i_reg_0),
.I3(s_axi_rready),
.I4(\chosen_reg[0] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hD5D5FFD5))
s_ready_i_i_1__4
(.I0(m_valid_i_reg_0),
.I1(s_axi_rready),
.I2(\chosen_reg[0] ),
.I3(\m_axi_rready[0] ),
.I4(m_axi_rvalid),
.O(s_ready_i_i_1__4_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__4_n_0),
.Q(\m_axi_rready[0] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc
(\s_axi_rid[0] ,
\s_axi_rid[1] ,
\s_axi_rid[2] ,
\s_axi_rid[3] ,
\s_axi_rid[4] ,
\s_axi_rid[5] ,
\s_axi_rid[6] ,
\s_axi_rid[7] ,
\s_axi_rid[8] ,
\s_axi_rid[9] ,
\s_axi_rid[10] ,
\s_axi_rid[11] ,
s_axi_rresp,
s_axi_rdata,
s_axi_rlast,
E,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.accept_cnt_reg[3] ,
D,
\gen_no_arbiter.s_ready_i_reg[0] ,
S,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
resp_select,
f_mux4_return,
st_mr_rid,
\m_payload_i_reg[34] ,
cmd_push_0,
thread_valid_0__2,
CO,
cmd_push_3,
thread_valid_3__2,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ,
cmd_push_4,
thread_valid_4__2,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
cmd_push_7,
thread_valid_7__2,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ,
cmd_push_6,
thread_valid_6__2,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
cmd_push_5,
thread_valid_5__2,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
cmd_push_2,
thread_valid_2__2,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
cmd_push_1,
thread_valid_1__2,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
Q,
S_AXI_ARREADY,
s_axi_rready,
\chosen_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] );
output \s_axi_rid[0] ;
output \s_axi_rid[1] ;
output \s_axi_rid[2] ;
output \s_axi_rid[3] ;
output \s_axi_rid[4] ;
output \s_axi_rid[5] ;
output \s_axi_rid[6] ;
output \s_axi_rid[7] ;
output \s_axi_rid[8] ;
output \s_axi_rid[9] ;
output \s_axi_rid[10] ;
output \s_axi_rid[11] ;
output [1:0]s_axi_rresp;
output [31:0]s_axi_rdata;
output [0:0]s_axi_rlast;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output [2:0]D;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [3:0]S;
output [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input [0:0]resp_select;
input [46:0]f_mux4_return;
input [11:0]st_mr_rid;
input [0:0]\m_payload_i_reg[34] ;
input cmd_push_0;
input thread_valid_0__2;
input [0:0]CO;
input cmd_push_3;
input thread_valid_3__2;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
input cmd_push_4;
input thread_valid_4__2;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input cmd_push_7;
input thread_valid_7__2;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
input cmd_push_6;
input thread_valid_6__2;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input cmd_push_5;
input thread_valid_5__2;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input cmd_push_2;
input thread_valid_2__2;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input cmd_push_1;
input thread_valid_1__2;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input [3:0]Q;
input [0:0]S_AXI_ARREADY;
input [0:0]s_axi_rready;
input \chosen_reg[0] ;
input [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
input [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
input [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
input [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
input [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
input [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
input [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
input [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]S;
wire [0:0]S_AXI_ARREADY;
wire any_pop__1;
wire \chosen_reg[0] ;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire [46:0]f_mux4_return;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]\m_payload_i_reg[34] ;
wire [0:0]resp_select;
wire [31:0]s_axi_rdata;
wire \s_axi_rid[0] ;
wire \s_axi_rid[10] ;
wire \s_axi_rid[11] ;
wire \s_axi_rid[1] ;
wire \s_axi_rid[2] ;
wire \s_axi_rid[3] ;
wire \s_axi_rid[4] ;
wire \s_axi_rid[5] ;
wire \s_axi_rid[6] ;
wire \s_axi_rid[7] ;
wire \s_axi_rid[8] ;
wire \s_axi_rid[9] ;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [11:0]st_mr_rid;
wire thread_valid_0__2;
wire thread_valid_1__2;
wire thread_valid_2__2;
wire thread_valid_3__2;
wire thread_valid_4__2;
wire thread_valid_5__2;
wire thread_valid_6__2;
wire thread_valid_7__2;
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[0].mux_s2_inst
(.I0(f_mux4_return[0]),
.I1(st_mr_rid[0]),
.O(\s_axi_rid[0] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[10].mux_s2_inst
(.I0(f_mux4_return[10]),
.I1(st_mr_rid[10]),
.O(\s_axi_rid[10] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[11].mux_s2_inst
(.I0(f_mux4_return[11]),
.I1(st_mr_rid[11]),
.O(\s_axi_rid[11] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[12].mux_s2_inst
(.I0(f_mux4_return[12]),
.I1(1'b1),
.O(s_axi_rresp[0]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[13].mux_s2_inst
(.I0(f_mux4_return[13]),
.I1(1'b1),
.O(s_axi_rresp[1]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[15].mux_s2_inst
(.I0(f_mux4_return[14]),
.I1(1'b0),
.O(s_axi_rdata[0]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[16].mux_s2_inst
(.I0(f_mux4_return[15]),
.I1(1'b0),
.O(s_axi_rdata[1]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[17].mux_s2_inst
(.I0(f_mux4_return[16]),
.I1(1'b0),
.O(s_axi_rdata[2]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[18].mux_s2_inst
(.I0(f_mux4_return[17]),
.I1(1'b0),
.O(s_axi_rdata[3]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[19].mux_s2_inst
(.I0(f_mux4_return[18]),
.I1(1'b0),
.O(s_axi_rdata[4]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[1].mux_s2_inst
(.I0(f_mux4_return[1]),
.I1(st_mr_rid[1]),
.O(\s_axi_rid[1] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[20].mux_s2_inst
(.I0(f_mux4_return[19]),
.I1(1'b0),
.O(s_axi_rdata[5]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[21].mux_s2_inst
(.I0(f_mux4_return[20]),
.I1(1'b0),
.O(s_axi_rdata[6]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[22].mux_s2_inst
(.I0(f_mux4_return[21]),
.I1(1'b0),
.O(s_axi_rdata[7]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[23].mux_s2_inst
(.I0(f_mux4_return[22]),
.I1(1'b0),
.O(s_axi_rdata[8]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[24].mux_s2_inst
(.I0(f_mux4_return[23]),
.I1(1'b0),
.O(s_axi_rdata[9]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[25].mux_s2_inst
(.I0(f_mux4_return[24]),
.I1(1'b0),
.O(s_axi_rdata[10]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[26].mux_s2_inst
(.I0(f_mux4_return[25]),
.I1(1'b0),
.O(s_axi_rdata[11]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[27].mux_s2_inst
(.I0(f_mux4_return[26]),
.I1(1'b0),
.O(s_axi_rdata[12]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[28].mux_s2_inst
(.I0(f_mux4_return[27]),
.I1(1'b0),
.O(s_axi_rdata[13]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[29].mux_s2_inst
(.I0(f_mux4_return[28]),
.I1(1'b0),
.O(s_axi_rdata[14]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[2].mux_s2_inst
(.I0(f_mux4_return[2]),
.I1(st_mr_rid[2]),
.O(\s_axi_rid[2] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[30].mux_s2_inst
(.I0(f_mux4_return[29]),
.I1(1'b0),
.O(s_axi_rdata[15]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[31].mux_s2_inst
(.I0(f_mux4_return[30]),
.I1(1'b0),
.O(s_axi_rdata[16]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[32].mux_s2_inst
(.I0(f_mux4_return[31]),
.I1(1'b0),
.O(s_axi_rdata[17]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[33].mux_s2_inst
(.I0(f_mux4_return[32]),
.I1(1'b0),
.O(s_axi_rdata[18]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[34].mux_s2_inst
(.I0(f_mux4_return[33]),
.I1(1'b0),
.O(s_axi_rdata[19]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[35].mux_s2_inst
(.I0(f_mux4_return[34]),
.I1(1'b0),
.O(s_axi_rdata[20]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[36].mux_s2_inst
(.I0(f_mux4_return[35]),
.I1(1'b0),
.O(s_axi_rdata[21]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[37].mux_s2_inst
(.I0(f_mux4_return[36]),
.I1(1'b0),
.O(s_axi_rdata[22]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[38].mux_s2_inst
(.I0(f_mux4_return[37]),
.I1(1'b0),
.O(s_axi_rdata[23]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[39].mux_s2_inst
(.I0(f_mux4_return[38]),
.I1(1'b0),
.O(s_axi_rdata[24]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[3].mux_s2_inst
(.I0(f_mux4_return[3]),
.I1(st_mr_rid[3]),
.O(\s_axi_rid[3] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[40].mux_s2_inst
(.I0(f_mux4_return[39]),
.I1(1'b0),
.O(s_axi_rdata[25]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[41].mux_s2_inst
(.I0(f_mux4_return[40]),
.I1(1'b0),
.O(s_axi_rdata[26]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[42].mux_s2_inst
(.I0(f_mux4_return[41]),
.I1(1'b0),
.O(s_axi_rdata[27]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[43].mux_s2_inst
(.I0(f_mux4_return[42]),
.I1(1'b0),
.O(s_axi_rdata[28]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[44].mux_s2_inst
(.I0(f_mux4_return[43]),
.I1(1'b0),
.O(s_axi_rdata[29]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[45].mux_s2_inst
(.I0(f_mux4_return[44]),
.I1(1'b0),
.O(s_axi_rdata[30]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[46].mux_s2_inst
(.I0(f_mux4_return[45]),
.I1(1'b0),
.O(s_axi_rdata[31]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[47].mux_s2_inst
(.I0(f_mux4_return[46]),
.I1(\m_payload_i_reg[34] ),
.O(s_axi_rlast),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[4].mux_s2_inst
(.I0(f_mux4_return[4]),
.I1(st_mr_rid[4]),
.O(\s_axi_rid[4] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[5].mux_s2_inst
(.I0(f_mux4_return[5]),
.I1(st_mr_rid[5]),
.O(\s_axi_rid[5] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[6].mux_s2_inst
(.I0(f_mux4_return[6]),
.I1(st_mr_rid[6]),
.O(\s_axi_rid[6] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[7].mux_s2_inst
(.I0(f_mux4_return[7]),
.I1(st_mr_rid[7]),
.O(\s_axi_rid[7] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[8].mux_s2_inst
(.I0(f_mux4_return[8]),
.I1(st_mr_rid[8]),
.O(\s_axi_rid[8] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[9].mux_s2_inst
(.I0(f_mux4_return[9]),
.I1(st_mr_rid[9]),
.O(\s_axi_rid[9] ),
.S(resp_select));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT4 #(
.INIT(16'h9A65))
\gen_multi_thread.accept_cnt[1]_i_1__0
(.I0(Q[0]),
.I1(any_pop__1),
.I2(S_AXI_ARREADY),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hDFF2200D))
\gen_multi_thread.accept_cnt[2]_i_1__0
(.I0(S_AXI_ARREADY),
.I1(any_pop__1),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_multi_thread.accept_cnt[3]_i_1__0
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[3]),
.I4(any_pop__1),
.I5(S_AXI_ARREADY),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hF7FF0800FFAE0051))
\gen_multi_thread.accept_cnt[3]_i_2__0
(.I0(Q[1]),
.I1(S_AXI_ARREADY),
.I2(any_pop__1),
.I3(Q[0]),
.I4(Q[3]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0
(.I0(cmd_push_0),
.I1(any_pop__1),
.I2(thread_valid_0__2),
.I3(CO),
.O(E));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0
(.I0(cmd_push_1),
.I1(any_pop__1),
.I2(thread_valid_1__2),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0
(.I0(cmd_push_2),
.I1(any_pop__1),
.I2(thread_valid_2__2),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0
(.I0(cmd_push_3),
.I1(any_pop__1),
.I2(thread_valid_3__2),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0
(.I0(cmd_push_4),
.I1(any_pop__1),
.I2(thread_valid_4__2),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0
(.I0(cmd_push_5),
.I1(any_pop__1),
.I2(thread_valid_5__2),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0
(.I0(cmd_push_6),
.I1(any_pop__1),
.I2(thread_valid_6__2),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0
(.I0(cmd_push_7),
.I1(any_pop__1),
.I2(thread_valid_7__2),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT3 #(
.INIT(8'h80))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(\chosen_reg[0] ),
.O(any_pop__1));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_34__0
(.I0(s_axi_rlast),
.I1(s_axi_rready),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [9]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [11]),
.I5(\s_axi_rid[11] ),
.O(S[3]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [6]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [8]),
.I5(\s_axi_rid[8] ),
.O(S[2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [3]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [5]),
.I5(\s_axi_rid[5] ),
.O(S[1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [0]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [2]),
.I5(\s_axi_rid[2] ),
.O(S[0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [9]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [6]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [3]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [0]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [6]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [3]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [0]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [9]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [6]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [3]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [0]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [9]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [6]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [3]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [0]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [9]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [6]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [3]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [0]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [9]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [6]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [3]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [0]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_1
(.I0(\s_axi_rid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [10]),
.I2(\s_axi_rid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [9]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [11]),
.I5(\s_axi_rid[11] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_2
(.I0(\s_axi_rid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [7]),
.I2(\s_axi_rid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [6]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [8]),
.I5(\s_axi_rid[8] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_3
(.I0(\s_axi_rid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [4]),
.I2(\s_axi_rid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [3]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [5]),
.I5(\s_axi_rid[5] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_4
(.I0(\s_axi_rid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [1]),
.I2(\s_axi_rid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [0]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [2]),
.I5(\s_axi_rid[2] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [0]));
endmodule
(* ORIG_REF_NAME = "generic_baseblocks_v2_1_0_mux_enc" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0
(\s_axi_bid[0] ,
\s_axi_bid[1] ,
\s_axi_bid[2] ,
\s_axi_bid[3] ,
\s_axi_bid[4] ,
\s_axi_bid[5] ,
\s_axi_bid[6] ,
\s_axi_bid[7] ,
\s_axi_bid[8] ,
\s_axi_bid[9] ,
\s_axi_bid[10] ,
\s_axi_bid[11] ,
s_axi_bresp,
p_0_out,
E,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.accept_cnt_reg[3] ,
D,
S,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
resp_select,
f_mux4_return,
st_mr_bid,
cmd_push_0,
thread_valid_0__2,
CO,
cmd_push_3,
thread_valid_3__2,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ,
cmd_push_4,
thread_valid_4__2,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
cmd_push_7,
thread_valid_7__2,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ,
cmd_push_6,
thread_valid_6__2,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
cmd_push_5,
thread_valid_5__2,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
cmd_push_2,
thread_valid_2__2,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
cmd_push_1,
thread_valid_1__2,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
Q,
\m_ready_d_reg[1] ,
s_axi_bready,
m_valid_i_reg,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] );
output \s_axi_bid[0] ;
output \s_axi_bid[1] ;
output \s_axi_bid[2] ;
output \s_axi_bid[3] ;
output \s_axi_bid[4] ;
output \s_axi_bid[5] ;
output \s_axi_bid[6] ;
output \s_axi_bid[7] ;
output \s_axi_bid[8] ;
output \s_axi_bid[9] ;
output \s_axi_bid[10] ;
output \s_axi_bid[11] ;
output [1:0]s_axi_bresp;
output p_0_out;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output [2:0]D;
output [3:0]S;
output [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input [0:0]resp_select;
input [13:0]f_mux4_return;
input [11:0]st_mr_bid;
input cmd_push_0;
input thread_valid_0__2;
input [0:0]CO;
input cmd_push_3;
input thread_valid_3__2;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
input cmd_push_4;
input thread_valid_4__2;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input cmd_push_7;
input thread_valid_7__2;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
input cmd_push_6;
input thread_valid_6__2;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input cmd_push_5;
input thread_valid_5__2;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input cmd_push_2;
input thread_valid_2__2;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input cmd_push_1;
input thread_valid_1__2;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input [3:0]Q;
input \m_ready_d_reg[1] ;
input [0:0]s_axi_bready;
input m_valid_i_reg;
input [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
input [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
input [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
input [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
input [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
input [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
input [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
input [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]S;
wire any_pop__1;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire [13:0]f_mux4_return;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
wire \m_ready_d_reg[1] ;
wire m_valid_i_reg;
wire p_0_out;
wire [0:0]resp_select;
wire \s_axi_bid[0] ;
wire \s_axi_bid[10] ;
wire \s_axi_bid[11] ;
wire \s_axi_bid[1] ;
wire \s_axi_bid[2] ;
wire \s_axi_bid[3] ;
wire \s_axi_bid[4] ;
wire \s_axi_bid[5] ;
wire \s_axi_bid[6] ;
wire \s_axi_bid[7] ;
wire \s_axi_bid[8] ;
wire \s_axi_bid[9] ;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [11:0]st_mr_bid;
wire thread_valid_0__2;
wire thread_valid_1__2;
wire thread_valid_2__2;
wire thread_valid_3__2;
wire thread_valid_4__2;
wire thread_valid_5__2;
wire thread_valid_6__2;
wire thread_valid_7__2;
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[0].mux_s2_inst
(.I0(f_mux4_return[0]),
.I1(st_mr_bid[0]),
.O(\s_axi_bid[0] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[10].mux_s2_inst
(.I0(f_mux4_return[10]),
.I1(st_mr_bid[10]),
.O(\s_axi_bid[10] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[11].mux_s2_inst
(.I0(f_mux4_return[11]),
.I1(st_mr_bid[11]),
.O(\s_axi_bid[11] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[12].mux_s2_inst
(.I0(f_mux4_return[12]),
.I1(1'b1),
.O(s_axi_bresp[0]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[13].mux_s2_inst
(.I0(f_mux4_return[13]),
.I1(1'b1),
.O(s_axi_bresp[1]),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[15].mux_s2_inst
(.I0(1'b1),
.I1(1'b1),
.O(p_0_out),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[1].mux_s2_inst
(.I0(f_mux4_return[1]),
.I1(st_mr_bid[1]),
.O(\s_axi_bid[1] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[2].mux_s2_inst
(.I0(f_mux4_return[2]),
.I1(st_mr_bid[2]),
.O(\s_axi_bid[2] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[3].mux_s2_inst
(.I0(f_mux4_return[3]),
.I1(st_mr_bid[3]),
.O(\s_axi_bid[3] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[4].mux_s2_inst
(.I0(f_mux4_return[4]),
.I1(st_mr_bid[4]),
.O(\s_axi_bid[4] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[5].mux_s2_inst
(.I0(f_mux4_return[5]),
.I1(st_mr_bid[5]),
.O(\s_axi_bid[5] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[6].mux_s2_inst
(.I0(f_mux4_return[6]),
.I1(st_mr_bid[6]),
.O(\s_axi_bid[6] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[7].mux_s2_inst
(.I0(f_mux4_return[7]),
.I1(st_mr_bid[7]),
.O(\s_axi_bid[7] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[8].mux_s2_inst
(.I0(f_mux4_return[8]),
.I1(st_mr_bid[8]),
.O(\s_axi_bid[8] ),
.S(resp_select));
(* BOX_TYPE = "PRIMITIVE" *)
MUXF7 \gen_fpga.gen_mux_5_8[9].mux_s2_inst
(.I0(f_mux4_return[9]),
.I1(st_mr_bid[9]),
.O(\s_axi_bid[9] ),
.S(resp_select));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT4 #(
.INIT(16'h9A65))
\gen_multi_thread.accept_cnt[1]_i_1
(.I0(Q[0]),
.I1(any_pop__1),
.I2(\m_ready_d_reg[1] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT5 #(
.INIT(32'hDFF2200D))
\gen_multi_thread.accept_cnt[2]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(any_pop__1),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_multi_thread.accept_cnt[3]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[3]),
.I4(any_pop__1),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hF7FF0800FFAE0051))
\gen_multi_thread.accept_cnt[3]_i_2
(.I0(Q[1]),
.I1(\m_ready_d_reg[1] ),
.I2(any_pop__1),
.I3(Q[0]),
.I4(Q[3]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1
(.I0(cmd_push_0),
.I1(any_pop__1),
.I2(thread_valid_0__2),
.I3(CO),
.O(E));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1
(.I0(cmd_push_1),
.I1(any_pop__1),
.I2(thread_valid_1__2),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1
(.I0(cmd_push_2),
.I1(any_pop__1),
.I2(thread_valid_2__2),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1
(.I0(cmd_push_3),
.I1(any_pop__1),
.I2(thread_valid_3__2),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1
(.I0(cmd_push_4),
.I1(any_pop__1),
.I2(thread_valid_4__2),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1
(.I0(cmd_push_5),
.I1(any_pop__1),
.I2(thread_valid_5__2),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1
(.I0(cmd_push_6),
.I1(any_pop__1),
.I2(thread_valid_6__2),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h6AAA))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1
(.I0(cmd_push_7),
.I1(any_pop__1),
.I2(thread_valid_7__2),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
LUT3 #(
.INIT(8'h80))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3
(.I0(s_axi_bready),
.I1(p_0_out),
.I2(m_valid_i_reg),
.O(any_pop__1));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [9]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [11]),
.I5(\s_axi_bid[11] ),
.O(S[3]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [6]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [8]),
.I5(\s_axi_bid[8] ),
.O(S[2]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [3]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [5]),
.I5(\s_axi_bid[5] ),
.O(S[1]));
LUT6 #(
.INIT(64'h9009000000009009))
i__carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [0]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [2]),
.I5(\s_axi_bid[2] ),
.O(S[0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [9]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [6]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [3]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_10_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [0]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [6]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [3]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_12_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [0]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [9]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [6]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [3]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_14_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [0]),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [9]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [6]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [3]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_2_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [0]),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [9]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [6]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [3]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_4_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [0]),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [9]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [6]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [3]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_6_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [0]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_1__0
(.I0(\s_axi_bid[10] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [10]),
.I2(\s_axi_bid[9] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [9]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [11]),
.I5(\s_axi_bid[11] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_2__0
(.I0(\s_axi_bid[7] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [7]),
.I2(\s_axi_bid[6] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [6]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [8]),
.I5(\s_axi_bid[8] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_3__0
(.I0(\s_axi_bid[4] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [4]),
.I2(\s_axi_bid[3] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [3]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [5]),
.I5(\s_axi_bid[5] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
p_8_out_carry_i_4__0
(.I0(\s_axi_bid[1] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [1]),
.I2(\s_axi_bid[0] ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [0]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [2]),
.I5(\s_axi_bid[2] ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0 [0]));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI AWID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI AWID [11:0] [47:36]" *) output [47:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *) output [127:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]" *) output [31:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]" *) output [11:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]" *) output [7:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]" *) output [3:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]" *) output [15:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *) output [11:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]" *) output [15:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]" *) output [15:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *) output [3:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *) input [3:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *) output [127:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *) output [15:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]" *) output [3:0]m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *) output [3:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *) input [3:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI BID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI BID [11:0] [47:36]" *) input [47:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *) input [7:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *) input [3:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *) output [3:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI ARID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI ARID [11:0] [47:36]" *) output [47:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *) output [127:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]" *) output [31:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]" *) output [11:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]" *) output [7:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]" *) output [3:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]" *) output [15:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *) output [11:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]" *) output [15:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]" *) output [15:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *) output [3:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *) input [3:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI RID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI RID [11:0] [47:36]" *) input [47:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *) input [127:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *) input [7:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]" *) input [3:0]m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *) input [3:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *) output [3:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [127:0]m_axi_araddr;
wire [7:0]m_axi_arburst;
wire [15:0]m_axi_arcache;
wire [47:0]m_axi_arid;
wire [31:0]m_axi_arlen;
wire [3:0]m_axi_arlock;
wire [11:0]m_axi_arprot;
wire [15:0]m_axi_arqos;
wire [3:0]m_axi_arready;
wire [15:0]m_axi_arregion;
wire [11:0]m_axi_arsize;
wire [3:0]m_axi_arvalid;
wire [127:0]m_axi_awaddr;
wire [7:0]m_axi_awburst;
wire [15:0]m_axi_awcache;
wire [47:0]m_axi_awid;
wire [31:0]m_axi_awlen;
wire [3:0]m_axi_awlock;
wire [11:0]m_axi_awprot;
wire [15:0]m_axi_awqos;
wire [3:0]m_axi_awready;
wire [15:0]m_axi_awregion;
wire [11:0]m_axi_awsize;
wire [3:0]m_axi_awvalid;
wire [47:0]m_axi_bid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [47:0]m_axi_rid;
wire [3:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire [3:0]m_axi_wlast;
wire [3:0]m_axi_wready;
wire [15:0]m_axi_wstrb;
wire [3:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [3:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [47:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "1" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000" *)
(* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "4" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *)
(* C_S_AXI_THREAD_ID_WIDTH = "12" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "4'b1111" *)
(* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[3:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[3:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[47:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[3:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_ab.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No user `defines in this module
module ent_ab
//
// Generated Module inst_ab
//
(
port_ab_1, // Use internally test1
port_ab_2, // Use internally test2, no port generated
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
input [6:0] sig_14;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_2_V
`define SKY130_FD_SC_HS__A41O_2_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41o_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41o_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_2_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
// IP Revision: 0
(* X_CORE_INFO = "axis_register_slice_v1_1_axis_register_slice,Vivado 2013.3" *)
(* CHECK_LICENSE_TYPE = "daala_zynq_axis_register_slice_0_0,axis_register_slice_v1_1_axis_register_slice,{}" *)
(* CORE_GENERATION_INFO = "daala_zynq_axis_register_slice_0_0,axis_register_slice_v1_1_axis_register_slice,{x_ipProduct=Vivado 2013.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=256,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00011011,C_REG_CONFIG=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_axis_register_slice_0_0 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [255 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input [31 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output [255 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output [31 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output m_axis_tlast;
axis_register_slice_v1_1_axis_register_slice #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(256),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00011011),
.C_REG_CONFIG(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(32'HFFFFFFFF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
|
// EE 471 Lab 3, Beck Pang, Spring 2015
// combine SRAM and ALU together
// @require:
// Instruction formula is formed by 3 bit control, 5 bit for address of A
// 5 bit for address of B
// fetch instructions and data into SRAM, and then move to register file
module DE1_SoCPhaseII (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
reg [2:0] ps, ns;
wire [15:0] data;
reg [7:0] count; // 0~255
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
reg [2:0] control;
wire rst, fetchStart;
reg [4:0] readAdx0, readAdx1, writeAdx;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
wire [2:0] opcode;
wire [4:0] regAdx0, regAdx1;
reg [31:0] busA, busB;
wire [31:0] busOut;
wire zero, overflow, carryout, negative;
assign fetchStart = SW[6]; // fetch starts when SW[6] turns on
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store; // control the tri-state
assign LEDR[3:0] = {zero, overflow, carryout, negative};
SRAM2Kby16 memory(CLOCK_50, adx, WrEn, data);
registerFile regs(CLOCK_50, readAdx0, readAdx1, writeAdx, regWR, writeData, readOutput0, readOutput1);
ALUnit logicUnit(CLOCK_50, control, busA, busB, busOut, zero, overflow, carryout, negative);
InstrucDecoder getInstruc(data, opcode, regAdx0, regAdx1);
parameter loadData = 3'b000, loadInstr = 3'b001, transfer = 3'b010,
fetch = 3'b011, decode = 3'b100, execute = 3'b101, writeBack = 3'b110, nul = 3'bx;
always @(posedge CLOCK_50)
case (SW[6:4])
loadData : begin // write data into SRAM. Active low Write Enable
WrEn = 0;
regWR = 1;
writeAdx = 0;
writeData = 0;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
adx = count[6:0] + 8'h80;
store = 7'b1111111 - count[6:0];
// if (fetchStart)
// ps = fetch;
// else if (count[6:0] == 7'b1111111)
// ps = loadInstr;
// else
// ps = loadData;
end
loadInstr: begin // create instruction and data address using counter
WrEn = 0;
regWR = 1;
adx = count[6:0];
// count[6:4] is opcode, {1'b0, count[3:0]} the address of A, {1'b1, count[3:0]} the address of B,
store = {count[6:4], {1'b0, count[3:0]}, {1'b1, count[3:0]}, 3'b0};
// if (fetchStart)
// ns = fetch;
// else if (count[6:0] == 7'b1111111)
// ns = transfer;
// else
// ns = loadInstr;
end
transfer : begin // write data into register file
WrEn = 1;
regWR = 0;
adx = count[4:0] + 8'h80;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
writeAdx = count[4:0];
writeData= {{16{data[15]}}, data};
// if (fetchStart)
// ns = fetch;
// else
// ns = transfer;
end
fetch : begin // read from register file to ALU
if(count[0]) begin
WrEn = 1;
regWR = 1;
adx = count[7:1];
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
//ns = writeBack;
//end
/*decode : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
ns = execute;
end
execute : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
ns = writeBack;
end*/
//writeBack: begin
end else begin
WrEn = 1;
regWR = 0;
writeAdx = regAdx0;
writeData= busOut;
//if (fetchStart)
//ns= fetch;
//else
//ns= execute;
end
// execute:begin
// WrEn = 1;
// regWR = 0;
// readAdx0 = count[4:0];
// readAdx1 = 5'h10 + count[4:0];
// adx = 8'h80 + count[3:0];
// if(!fetchStart)
// ns = loadData;
// else
// ns = execute;
end
default : begin
WrEn = 1'bx;
regWR = 1'bx;
ns = nul;
end
endcase
always @(posedge CLOCK_50) begin
if (rst) begin
//ps <= loadData;
count <= 8'b0;
end
else begin
//ps <= ns;
count <= count + 1'b1;
end
end
endmodule
// vlog "./sourceCode/DE1_SoCPhaseII.v"
// vlog "./sourceCode/Implementation/mux2_1.sv"
// vlog "./sourceCode/Implementation/mux4_1.sv"
// vlog "./sourceCode/Implementation/mux8_1.sv"
// vlog "./sourceCode/Implementation/mux32_1.sv"
// vlog "./sourceCode/Implementation/register.sv"
// vlog "./sourceCode/Implementation/registerSingle.sv"
// vlog "./sourceCode/Implementation/DFlipFlop.sv"
// vlog "./sourceCode/Implementation/counter.v"
// vlog "./sourceCode/Implementation/decoder5_32.sv"
// vlog "./sourceCode/Implementation/decoder8_256.sv"
// vlog "./sourceCode/Implementation/decoder11_2048.sv"
// vlog "./sourceCode/InstrucDecoder.v"
// vlog "./sourceCode/SRAM2Kby16.v"
// vlog "./sourceCode/registerFile.sv"
// vlog "./sourceCode/ALUnit.sv"
// vlog "./sourceCode/addition.v"
// vlog "./sourceCode/subtract.v"
// vlog "./sourceCode/andGate.v"
// vlog "./sourceCode/orGate.v"
// vlog "./sourceCode/xorGate.v"
// vlog "./sourceCode/setLT.v"
// vlog "./sourceCode/shiftll.v"
// vlog "./sourceCode/adder_subtractor.v"
// vlog "./sourceCode/flag.v"
// vlog "./sourceCode/adder16b.v"
// vlog "./sourceCode/adder4b.v"
// vlog "./sourceCode/fullAdder1b.v"
// vlog "./sourceCode/lookAhead4b.v"
module DE1_SoCPhaseII_Testbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoCPhaseII dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter CLOCK_PERIOD = 100;
initial CLOCK_50 = 1;
always begin
#(CLOCK_PERIOD / 2);
CLOCK_50 = ~CLOCK_50;
end
// Set up the inputs to the design
integer i;
initial begin
@(posedge CLOCK_50);
SW[9] <= 1; @(posedge CLOCK_50);
SW[8:0] <= 9'b0; @(posedge CLOCK_50);
SW[9] <= 0; @(posedge CLOCK_50);
@(posedge CLOCK_50);
for (i = 0; i < 300; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 19; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 18; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 17; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 16; i = i + 1) begin
@(posedge CLOCK_50);
end
$stop;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
Copyright 2016 Cornell University
Copyright 2017 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Websites: http://nuprl.org/html/verification/
http://nuprl.org/html/Nuprl2Coq
https://github.com/vrahli/NuprlInCoq
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export sequents2.
Require Export sequents_lib.
Require Export rules_useful.
Require Export sequents_useful.
Require Export sequents_tacs.
Require Export sequents_tacs2.
Require Export subst_tacs_aeq.
Require Export cequiv_tacs.
(** printing |- $\vdash$ *)
(** printing -> $\rightarrow$ *)
(* begin hide *)
(* end hide *)
(**
We now prove the truth of several structural rules.
*)
(* [1] ============ THIN HYPS ============ *)
(**
The following rule says that we can always thin any tail of a list of hypotheses:
<<
H, J |- C ext t
By thinHyps ()
H |- C ext t
>>
*)
Definition rule_thin_hyps {o}
(H J : @barehypotheses o)
(C t : NTerm) :=
mk_rule
(mk_baresequent (H ++ J) (mk_concl C t))
[ mk_baresequent H (mk_concl C t) ]
[].
Lemma rule_thin_hyps_true {o} :
forall lib (H J : @barehypotheses o)
(C t : NTerm),
rule_true lib (rule_thin_hyps H J C t).
Proof.
intros.
unfold rule_thin_hyps, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
generalize (hyps (mk_baresequent H (mk_concl C t)) (inl eq_refl));
intro hyp1; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl.
proof_irr.
assert (closed_extract (H ++ J) (mk_concl C t)) as ws
by (wfseq; apply covered_app_weak_l; auto).
exists ws.
(* We prove some simple facts on our sequents *)
assert (covered C (vars_hyps H)
# covered t (nh_vars_hyps H)
# disjoint (free_vars C) (vars_hyps J)
# disjoint (free_vars t) (vars_hyps J)) as vhyps.
clear hyp1.
dwfseq; sp;
try (complete (rw fold_subset in ct;
apply subset_disjoint with (l3 := vars_hyps J) in ct; sp)).
try (complete (rw fold_subset in ce;
apply subset_disjoint with (l1 := nh_vars_hyps H) in wfj0; sp;
apply subset_disjoint with (l3 := vars_hyps J) in ce; sp)).
destruct vhyps as [ cch vhyps ].
destruct vhyps as [ cth vhyps ].
destruct vhyps as [ dcj dtj ].
(* done with proving these simple facts *)
(* we can now start proving that the rule is true *)
vr_seq_true.
vr_seq_true in hyp1.
allrw @similarity_app; exrepd; subst.
generalize (hyp1 s1a s2a); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
intros s2 sim.
apply @hyps_functionality_init_seg with (s1b := s1b) (J := J) (s3 := s2b) in sim; auto.
autodimp hyp1 hyp; exrepd.
assert (disjoint (free_vars C) (dom_csub s1b)) as d1
by (allapply @similarity_dom; sp;
rterm (dom_csub s1b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars C) (dom_csub s2b)) as d2
by (allapply @similarity_dom; sp;
rterm (dom_csub s2b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars t) (dom_csub s1b)) as dt1
by (allapply @similarity_dom; sp;
rterm (dom_csub s1b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars t) (dom_csub s2b)) as dt2
by (allapply @similarity_dom; sp;
rterm (dom_csub s2b); rewrite vars_hyps_substitute_hyps; sp).
generalize (subset_free_vars_lsubstc_app_ex C s1a s1b wfct pC1 d1); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex C s2a s2b wfct pC2 d2); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex t s1a s1b wfce pt1 dt1); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex t s2a s2b wfce pt2 dt2); intro; exrepd; clear_irr.
rewrite e0; clear e0.
auto.
Qed.
(* begin hide *)
Lemma rule_thin_hyps_true_ex {o} :
forall lib (H : @bhyps o) J c t,
rule_true_if lib (rule_thin_hyps H J c t).
Proof.
intros.
generalize (rule_thin_hyps_true lib H J c t); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
Lemma rule_thin_hyps_true2 {o} :
forall lib (H : @bhyps o) J c t,
rule_true2 lib (rule_thin_hyps H J c t).
Proof.
intros.
generalize (rule_thin_hyps_true lib H J c t); intro rt.
apply rule_true_iff_rule_true2; sp.
Qed.
Lemma rule_thin_hyps_wf {o} :
forall (H : @bhyps o) J c t,
covered c (vars_hyps H)
-> wf_rule (rule_thin_hyps H J c t).
Proof.
intros.
introv pwf m; allsimpl; repdors; subst; sp.
allunfold @pwf_sequent; wfseq; sp.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app; sp.
allapply @vswf_hypotheses_nil_if; sp.
Qed.
(* end hide *)
(* [2] ============ UNHIDE EQUALITY ============ *)
(**
The following rule says that we can always unhide an hypothesis if
the conclusion is an equality (in general this is true if the
conclusion has a trivial extract):
<<
H [x : A] J |- t1 = t2 in C
By equalityUnhide hyp(i) ()
H x : A J |- t1 = t2 in C
>>
*)
Definition rule_unhide_equality_concl {o} (H J : @bhyps o) x A t1 t2 C :=
mk_baresequent
(snoc H (mk_hhyp x A) ++ J)
(mk_conclax (mk_equality t1 t2 C)).
Definition rule_unhide_equality_hyp {o} (H J : @bhyps o) x A t1 t2 C e :=
mk_baresequent
(snoc H (mk_hyp x A) ++ J)
(mk_concl (mk_equality t1 t2 C) e).
Definition rule_unhide_equality {o}
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar) :=
mk_rule
(rule_unhide_equality_concl H J x A t1 t2 C)
[ rule_unhide_equality_hyp H J x A t1 t2 C e ]
[].
Lemma rule_unhide_equality_true3 {o} :
forall (lib : library)
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar),
rule_true3 lib (rule_unhide_equality H J A C t1 t2 e x).
Proof.
intros.
unfold rule_unhide_equality, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
match goal with
| [ |- sequent_true2 _ ?s ] => assert (wf_csequent s) as wfc
end.
{
clear hyp1.
unfold wf_csequent, wf_sequent, wf_concl; simpl.
dands; auto.
- allrw @vswf_hypotheses_nil_eq.
allrw @wf_hypotheses_app.
allrw @vars_hyps_snoc; simpl in *.
repnd; dands; auto.
- apply wf_axiom.
- unfold closed_extract; simpl; auto.
}
exists wfc.
destseq; simpl in *.
(* We prove some simple facts on our sequents *)
assert (covered (mk_equality t1 t2 C) (snoc (vars_hyps H) x ++ vars_hyps J))
as vhyps.
{
clear hyp1.
dwfseq; sp.
allrw in_app_iff; allrw in_snoc; sp;
apply_in_hyp p; allrw in_app_iff; allrw in_snoc; sp.
}
(* done with proving these simple facts *)
(* we can now start proving that the rule is true *)
vr_seq_true.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp).
{
intros s3 sim3.
rw @similarity_hhyp in sim3; rw @eq_hyps_hhyp.
apply eqh; sp.
}
{ rw @similarity_hhyp; auto. }
exrepd; clear_irr; dands; auto.
lsubst_tac.
apply member_equality.
apply equality_in_mkc_equality in e0; tcsp.
Qed.
Lemma rule_unhide_equality_true {o} :
forall (lib : library)
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar),
rule_true lib (rule_unhide_equality H J A C t1 t2 e x).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_unhide_equality_true3.
Qed.
Lemma rule_unhide_equality_true_ext_lib {o} :
forall (lib : library)
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar),
rule_true_ext_lib lib (rule_unhide_equality H J A C t1 t2 e x).
Proof.
introv.
apply rule_true3_implies_rule_true_ext_lib.
introv.
apply rule_unhide_equality_true3.
Qed.
Lemma rule_unhide_equality_wf2 {o} :
forall (H J : @barehypotheses o) A C t1 t2 e x,
wf_rule2 (rule_unhide_equality H J A C t1 t2 e x).
Proof.
introv wf m; allsimpl.
repndors; subst; tcsp.
allunfold @wf_bseq; allsimpl; repnd; dands; auto.
- allrw @vswf_hypotheses_nil_eq.
allrw @wf_hypotheses_app.
allrw @vars_hyps_snoc; simpl in *.
repnd; dands; auto.
allrw @wf_hypotheses_snoc; simpl in *.
repnd; dands; auto.
- unfold closed_type_baresequent in *; simpl in *.
unfold closed_type in *; simpl in *.
allrw @vars_hyps_app; simpl in *.
allrw @vars_hyps_snoc; simpl in *.
auto.
Qed.
(* begin hide *)
(* end hide *)
(* [4] ============ HYPOTHESIS EQUALITY ============ *)
(**
The following rule is the standard ``hypothesis'' rule:
<<
G, x : A, J |- x = x in A
By hypothesisEquality hyp(i) ()
no subgoals
>>
*)
Definition rule_hypothesis_equality_concl {o} (G J : @bhyps o) A x :=
mk_baresequent
(snoc G (mk_hyp x A) ++ J)
(mk_conclax (mk_equality (mk_var x) (mk_var x) A)).
Definition rule_hypothesis_equality {o}
(G J : @barehypotheses o)
(A : NTerm)
(x : NVar) :=
mk_rule
(rule_hypothesis_equality_concl G J A x)
[]
[].
Lemma rule_hypothesis_equality_true {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true lib (rule_hypothesis_equality G J A x).
Proof.
intros.
unfold rule_hypothesis_equality, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allunfold @closed_type; allunfold @closed_extract; allsimpl.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
allrw @wf_hypotheses_snoc.
destruct wfh as [ ispvg wfh ].
destruct wfh as [ nixg wfg ].
allrw @nh_vars_hyps_snoc; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate cg as ceq.
allrw @covered_equality.
destruct cg as [ cx ct ].
destruct ct as [ cx2 ca ]; GC.
allrw @vars_hyps_app; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate wfct as wfct'.
rw <- @wf_equality_iff in wfct.
destruct wfct as [ wa wtt ].
destruct wtt as [ wb wtA ].
exists (@covered_axiom o (nh_vars_hyps (snoc G (mk_hyp x A) ++ J))).
(* We prove some simple facts on our sequents *)
assert (!LIn x (free_vars A)
# !LIn x (vars_hyps J)
# subset (free_vars A) (vars_hyps G)
# disjoint (free_vars A) (vars_hyps J)) as vhyps.
dwfseq.
sp;
try (complete (apply subset_disjoint with (l1 := free_vars A) in wfj2; auto;
apply subset_snoc_r; sp)).
destruct vhyps as [ nixa vhyps ].
destruct vhyps as [ nixj vhyps ].
destruct vhyps as [ sag daj ].
(* done with proving these simple facts *)
vr_seq_true.
lift_lsubst.
repeat (rewrite fold_mkc_member).
rewrite member_eq.
rw <- @member_member_iff.
rw @tequality_mkc_member.
applydup eqh in sim; clear eqh.
allrw @similarity_app; exrepd; subst; cpx.
allrw @similarity_snoc; exrepd; subst; cpx.
revert c1 cT c0 cT0; rewrite hvar_mk_hyp; intros.
allrw @eq_hyps_app; exrepd; simphyps; cpx.
apply app_split in e; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
apply app_split in e0; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
allrw @eq_hyps_snoc; exrepd; cpx; simphyps; cpx; GC; clear_irr.
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s1b0)) as dxs1
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s2b0)) as dxs2
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s1b0)) as das1
by (allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s2b0)) as das2
by (allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s1a (x, t0)) s1b0
w1 c1 dxs1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s2a (x, t3)) s2b0
w1 c0 dxs2); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s1a (x, t0)) s1b0
wtA cT das1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s2a (x, t3)) s2b0
wtA cT0 das2); intro; exrepd; rewrite e; clear e.
lsubst_tac.
applydup @equality_refl in e3; sp.
split; sp; GC.
apply @tequality_preserving_equality with (A := lsubstc A wtA s1a p); auto.
rewrite member_eq.
apply equality_sym in e3.
apply equality_refl in e3; sp.
Qed.
Lemma rule_hypothesis_equality_true_ext_lib {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true_ext_lib lib (rule_hypothesis_equality G J A x).
Proof.
introv.
apply rule_true_implies_rule_true_ext_lib.
{ unfold wf_extract, wf_extract_goal, wf_extract_seq; simpl; introv wf; apply wf_axiom. }
introv.
apply rule_hypothesis_equality_true.
Qed.
(* [4] ============ HYPOTHESIS EQUALITY ============ *)
(**
The following rule is the standard ``hypothesis'' rule:
<<
G, [x : A], J |- x = x in A
By hypothesisEquality hyp(i) ()
no subgoals
>>
*)
Definition rule_maybe_hidden_hypothesis_equality_concl {o} (G J : @bhyps o) A x b :=
mk_baresequent
(snoc G (mk_nlhyp b x A) ++ J)
(mk_conclax (mk_equality (mk_var x) (mk_var x) A)).
Definition rule_maybe_hidden_hypothesis_equality {o}
(G J : @barehypotheses o)
(A : NTerm)
(x : NVar)
(b : bool):=
mk_rule
(rule_maybe_hidden_hypothesis_equality_concl G J A x b)
[]
[].
Lemma rule_maybe_hidden_hypothesis_equality_true {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar)
(b : bool),
rule_true lib (rule_maybe_hidden_hypothesis_equality G J A x b).
Proof.
intros.
unfold rule_maybe_hidden_hypothesis_equality, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allunfold @closed_type; allunfold @closed_extract; allsimpl.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
allrw @wf_hypotheses_snoc.
destruct wfh as [ ispvg wfh ].
destruct wfh as [ nixg wfg ].
allrw @nh_vars_hyps_snoc; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate cg as ceq.
allrw @covered_equality.
destruct cg as [ cx ct ].
destruct ct as [ cx2 ca ]; GC.
allrw @vars_hyps_app; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate wfct as wfct'.
rw <- @wf_equality_iff in wfct.
destruct wfct as [ wa wtt ].
destruct wtt as [ wb wtA ].
exists (@covered_axiom o (nh_vars_hyps (snoc G (mk_nlhyp b x A) ++ J))).
(* We prove some simple facts on our sequents *)
assert (!LIn x (free_vars A)
# !LIn x (vars_hyps J)
# subset (free_vars A) (vars_hyps G)
# disjoint (free_vars A) (vars_hyps J)) as vhyps.
{
dwfseq.
sp;
try (complete (apply subset_disjoint with (l1 := free_vars A) in wfj2; auto;
apply subset_snoc_r; sp)).
}
destruct vhyps as [ nixa vhyps ].
destruct vhyps as [ nixj vhyps ].
destruct vhyps as [ sag daj ].
(* done with proving these simple facts *)
vr_seq_true.
lift_lsubst.
repeat (rewrite fold_mkc_member).
rewrite member_eq.
rw <- @member_member_iff.
rw @tequality_mkc_member.
applydup eqh in sim; clear eqh.
allrw @similarity_app; exrepd; subst; cpx.
allrw @similarity_snoc; exrepd; subst; cpx.
revert c1 cT c0 cT0.
simpl; intros.
allrw @eq_hyps_app; exrepd; simphyps; cpx.
apply app_split in e; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
apply app_split in e0; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
allrw @eq_hyps_snoc; exrepd; cpx; simphyps; cpx; GC; clear_irr.
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s1b0)) as dxs1
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s2b0)) as dxs2
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s1b0)) as das1
by (allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s2b0)) as das2
by (allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s1a (x, t0)) s1b0
w1 c1 dxs1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s2a (x, t3)) s2b0
w1 c0 dxs2); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s1a (x, t0)) s1b0
wtA cT das1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s2a (x, t3)) s2b0
wtA cT0 das2); intro; exrepd; rewrite e; clear e.
lsubst_tac.
applydup @equality_refl in e3; sp.
split; sp; GC.
apply @tequality_preserving_equality with (A := lsubstc A wtA s1a p); auto.
rewrite member_eq.
apply equality_sym in e3.
apply equality_refl in e3; sp.
Qed.
Lemma rule_maybe_hidden_hypothesis_equality_true_ext_lib {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar)
(b : bool),
rule_true_ext_lib lib (rule_maybe_hidden_hypothesis_equality G J A x b).
Proof.
introv.
apply rule_true_implies_rule_true_ext_lib.
{ unfold wf_extract, wf_extract_goal, wf_extract_seq; simpl; introv wf; apply wf_axiom. }
introv.
apply rule_maybe_hidden_hypothesis_equality_true.
Qed.
(* begin hide *)
(* end hide *)
(* [5] ============ INTRODUCTION ============ *)
(**
The following rule says that to prove a conclusion [C] one can
always provide an evidence [t] for that type and prove instead that
[t] is a member of [C]:
<<
H |- C ext t
By introduction t
H |- t = t in C
>>
*)
Definition rule_introduction_concl {o} (H : @bhyps o) C t :=
mk_baresequent H (mk_concl C t).
Definition rule_introduction_hyp {o} (H : @bhyps o) C t e :=
mk_baresequent H (mk_concl (mk_member t C) e).
Definition rule_introduction {o}
(H : @barehypotheses o)
(C t e : NTerm) :=
mk_rule
(rule_introduction_concl H C t)
[ rule_introduction_hyp H C t e ]
[ sarg_term t ].
Lemma rule_introduction_true3 {o} :
forall lib
(H : @barehypotheses o)
(C t e : NTerm),
rule_true3 lib (rule_introduction H C t e).
Proof.
intros.
unfold rule_introduction, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
unfold args_constraints in cargs; allsimpl.
generalize (cargs (sarg_term t) (inl eq_refl)); clear cargs; intro arg1.
unfold arg_constraints in arg1.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
assert (wf_csequent (rule_introduction_concl H C t)) as wfc.
{ clear hyp1.
unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; auto.
allrw <- @wf_equality_iff; sp. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
autodimp hyp1 h.
autodimp hyp1 h.
exrepd.
lsubst_tac.
apply member_if_inhabited in e0.
applydup @tequality_mkc_member_implies_sp in t0; auto.
dands; auto.
rw @tequality_mkc_member in t0; tcsp.
Qed.
Lemma rule_introduction_true_ext_lib {o} :
forall lib
(H : @barehypotheses o)
(C t e : NTerm),
rule_true_ext_lib lib (rule_introduction H C t e).
Proof.
introv.
apply rule_true3_implies_rule_true_ext_lib.
introv.
apply rule_introduction_true3.
Qed.
Lemma rule_introduction_true {o} :
forall lib
(H : @barehypotheses o)
(C t e : NTerm),
rule_true lib (rule_introduction H C t e).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_introduction_true3.
Qed.
Lemma rule_introduction_wf2 {o} :
forall (H : @barehypotheses o) (C t e : NTerm),
wf_term t
-> covered t (vars_hyps H)
-> wf_rule2 (rule_introduction H C t e).
Proof.
introv wt cov wf m; allsimpl.
repndors; subst; tcsp.
allunfold @wf_bseq; allsimpl; repnd; dands; auto.
- apply wf_equality; auto.
- allunfold @closed_type_baresequent; allsimpl.
allunfold @closed_type; allsimpl.
apply covered_equality; dands; auto.
Qed.
(* begin hide *)
(* end hide *)
(* [6] ============ HYPOTHESIS ============ *)
(**
The following rule is another form of the standard ``hypothesis''
rule:
<<
G, x : A, J |- A ext x
By hypothsis hyp(i) ()
no subgoals
>>
*)
Definition rule_hypothesis_concl {o} (G J : @bhyps o) A x :=
mk_baresequent (snoc G (mk_hyp x A) ++ J) (mk_concl A (mk_var x)).
Definition rule_hypothesis {o}
(G J : @barehypotheses o)
(A : NTerm)
(x : NVar) :=
mk_rule (rule_hypothesis_concl G J A x) [] [].
Lemma rule_hypothesis_true3 {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true3 lib (rule_hypothesis G J A x).
Proof.
intros.
unfold rule_hypothesis, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
clear cargs hyps.
destseq; allsimpl.
assert (wf_csequent (rule_hypothesis_concl G J A x)) as wfc.
{ unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; eauto 3 with slow.
- apply vswf_hypotheses_nil_eq; auto.
- unfold closed_extract; simpl.
rw @nh_vars_hyps_app.
rw @nh_vars_hyps_snoc; simpl.
unfold covered.
rw subvars_eq; simpl.
apply subset_cons_l; dands; auto.
rw in_app_iff; rw in_snoc; tcsp. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
pose proof (eqh s2 sim) as h.
apply eq_hyps_app in h; exrepnd; subst.
apply eq_hyps_snoc in h5; exrepnd; subst.
allrw length_snoc; cpx.
allsimpl.
applydup @wf_hypotheses_disj in wf0; repnd.
assert (disjoint (free_vars A) (dom_csub s1b)) as d1.
{ applydup @sub_eq_hyps_dom in h1; repnd.
rw h5; auto. }
assert (disjoint (free_vars A) (dom_csub s2b)) as d2.
{ applydup @sub_eq_hyps_dom in h1; repnd.
rw h2; auto. }
lsubst_tac.
dands; auto;[].
applydup @eq_hyps_length in h6; repnd.
apply similarity_app in sim; exrepnd.
apply app_split in sim0; allrw length_snoc; auto; try omega.
apply app_split in sim2; allrw length_snoc; auto; try omega.
repnd; subst.
apply similarity_snoc in sim5; exrepnd; cpx; allsimpl.
proof_irr; auto.
Qed.
Lemma rule_hypothesis_true_ext_lib {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true_ext_lib lib (rule_hypothesis G J A x).
Proof.
introv.
apply rule_true3_implies_rule_true_ext_lib.
introv.
apply rule_hypothesis_true3.
Qed.
Lemma rule_hypothesis_true {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true lib (rule_hypothesis G J A x).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_hypothesis_true3.
Qed.
Lemma rule_hypothesis_wf2 {o} :
forall (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
wf_rule (rule_hypothesis G J A x).
Proof.
introv wf i; allsimpl; tcsp.
Qed.
(* begin hide *)
(* end hide *)
(* [7] ============ THIN ============ *)
Definition rule_thin_concl {o} G x (A : @NTerm o) J C t :=
mk_baresequent (snoc G (mk_hyp x A) ++ J) (mk_concl C t).
Definition rule_thin_hyp {o} G J (C t : @NTerm o) :=
mk_baresequent (G ++ J) (mk_concl C t).
(**
The following rule says that one can always delete (or thin) an
hypothesis (as long as [J] does not depend on [x], because [H, J]
has to be well-formed):
<<
H, x : A, J |- C ext t
By thin hyp(i) ()
H, J |- C ext t
>>
*)
Definition rule_thin {o}
(G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar) :=
mk_rule
(rule_thin_concl G x A J C t)
[ rule_thin_hyp G J C t ]
[].
Lemma rule_thin_true3 {o} :
forall lib (G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar),
rule_true3 lib (rule_thin G J A C t x).
Proof.
intros.
unfold rule_thin, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
rename Hyp into hyp1.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl; proof_irr; GC.
assert (wf_csequent (rule_thin_concl G x A J C t)) as wfc.
{
clear hyp1.
unfold wf_csequent, closed_type, closed_extract, wf_sequent, wf_concl; simpl.
prove_seq; eauto 3 with slow.
- allrw @vswf_hypotheses_nil_eq; auto.
- eapply covered_subvars;[|eauto].
rw subvars_eq.
introv i; allrw in_app_iff; allrw in_snoc; tcsp.
}
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; allsimpl; repnd; proof_irr; GC.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars C)
# ! LIn x (free_vars t)
# ! LIn x (vars_hyps J)
# ! LIn x (free_vars_hyps J)
# ! LIn x (hyps_free_vars J)) as vhyps.
clear hyp1.
dwfseq.
sp;
try (complete (apply ct in X; allrw in_app_iff; sp));
try (complete (apply ce in X; allrw in_app_iff; sp;
generalize (subvars_hs_vars_hyps G); intro sv1; allrw subvars_prop;
generalize (subvars_hs_vars_hyps J); intro sv2; allrw subvars_prop; sp));
try (complete (apply wfh in X; allrw in_app_iff; sp)).
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixt vhyps ].
destruct vhyps as [ nixj1 vhyps ].
destruct vhyps as [ nixj2 nixj3 ].
(* done with proving these simple facts *)
vr_seq_true.
rw @similarity_app in sim; exrepd; subst; cpx.
rw @similarity_snoc in s; exrepd; subst; allsimpl; cpx.
vr_seq_true in hyp1.
generalize (hyp1 (s1a0 ++ s1b) (s2a0 ++ s2b)); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
intros s3 sim3.
rw @similarity_app in sim3; exrepnd; subst.
apply app_split in sim0; sp; subst;
try (complete (allapply @similarity_length; sp; omega)).
generalize (eqh (snoc s2a (x, t1) ++ s2b0)); intro h.
autodimp h hyp.
rw @similarity_app.
exists (snoc s1a (x, t1)) s1b0 (snoc s2a (x, t1)) s2b0; simpl; sp;
allrewrite length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a s2a t1 t1 w p; sp.
rewrite member_eq.
allapply @equality_refl; sp.
rewrite substitute_hyps_snoc_sub_weak; sp.
rw @eq_hyps_app in h; exrepnd.
apply app_split in h0; apply app_split in h2; sp; subst;
allrewrite length_snoc; sp;
try (complete (allapply @similarity_length; sp; omega)).
allrw @eq_hyps_snoc; exrepnd; allsimpl; cpx; GC.
rw @eq_hyps_app.
exists s1a0 s1b s2a1 s2b1; sp.
apply sub_eq_hyps_snoc_weak_iff in h1; sp.
clear_irr.
autodimp hyp1 hyp.
rw @similarity_app.
exists s1a0 s1b s2a0 s2b; sp.
rewrite substitute_hyps_snoc_sub_weak in s0; sp.
exrepd; clear_irr.
assert (lsubstc C wf1 (snoc s1a0 (x, t1) ++ s1b) pC1
= lsubstc C wf1 (s1a0 ++ s1b) pC0) as eq1;
try (rewrite eq1).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc C wf1 (snoc s2a0 (x, t2) ++ s2b) pC2
= lsubstc C wf1 (s2a0 ++ s2b) pC3) as eq2;
try (rewrite eq2).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc t wfce (snoc s1a0 (x, t1) ++ s1b) pt1
= lsubstc t wfce (s1a0 ++ s1b) pt0) as eq3;
try (rewrite eq3).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc t wfce (snoc s2a0 (x, t2) ++ s2b) pt2
= lsubstc t wfce (s2a0 ++ s2b) pt3) as eq4;
try (rewrite eq4).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
sp.
Qed.
Lemma rule_thin_true {o} :
forall lib (G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar),
rule_true lib (rule_thin G J A C t x).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_thin_true3.
Qed.
Lemma rule_thin_true_ext_lib {o} :
forall lib (G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar),
rule_true_ext_lib lib (rule_thin G J A C t x).
Proof.
introv.
apply rule_true3_implies_rule_true_ext_lib.
introv.
apply rule_thin_true3.
Qed.
Lemma vs_wf_hypotheses_snoc_vs_implies {o} :
forall (H : @bhyps o) vs x,
! LIn x (free_vars_hyps H)
-> vs_wf_hypotheses (snoc vs x) H
-> vs_wf_hypotheses vs H.
Proof.
induction H using rev_list_indT; introv nixH vswf; auto.
inversion vswf as [|? ? ? isp ni vwf]; subst; ginv.
match goal with
| [ H : snoc _ _ = snoc _ _ |- _ ] => apply snoc_inj in H; repnd; subst
end.
allrw @free_vars_hyps_snoc.
allrw in_app_iff.
allrw in_snoc.
allrw not_over_or; repnd.
allrw in_remove_nvars.
constructor; tcsp.
- allrw @isprog_vars_eq; repnd; dands; auto.
allrw subvars_eq.
introv i.
applydup isp0 in i.
allrw in_app_iff; allrw in_snoc.
repndors; subst; tcsp.
destruct (in_deq _ deq_nvar x (vars_hyps H)) as [d|d]; tcsp.
destruct nixH; dands; auto.
- allrw in_app_iff; allrw not_over_or.
dands; auto.
- eapply IHlist; eauto.
Qed.
Lemma rule_thin_wf2 {o} :
forall (G J : @barehypotheses o) A C t x,
!LIn x (free_vars_hyps J)
-> !LIn x (free_vars C)
-> wf_rule2 (rule_thin G J A C t x).
Proof.
introv nixJ nixC wf j.
allsimpl; repdors; sp; subst; allunfold @wf_bseq; wfseq;
allrw <- @wf_approx_iff; repnd; auto;
allrw @covered_approx; repnd; auto; eauto 4 with slow.
- allrw @vswf_hypotheses_nil_eq.
allrw @wf_hypotheses_app; repnd.
allrw @wf_hypotheses_snoc; repnd.
dands; auto; simpl in *.
allrw @vars_hyps_snoc; simpl in *.
eapply vs_wf_hypotheses_snoc_vs_implies; eauto.
- unfold covered in *.
allrw subvars_eq.
introv i; applydup wf in i.
allrw in_app_iff; allrw in_snoc; repndors; subst; tcsp.
Qed.
(* begin hide *)
(* end hide *)
(* [13] ============ WIDENING ============ *)
(**
The following rule state that if we are trying to prove a goal under
the assumption that [x] has type [T], then it suffices to prove the
goal under the hypothesis that [x] has type [U], as long as we can
prove that [T] is a subtype of [U], and [T] respects the equality of
[U] on the elements of [T]:
<<
H, x : T, J |- C ext t
By widening y z i
H, x : U, J |- C ext t
H, x : T, y : U, z : x = y in U |- x = y in T
H, x : T |- x in U
>>
*)
Definition rule_widening {o}
(T U C t : @NTerm o)
(x y z : NVar)
(i : nat)
(H J : barehypotheses) :=
mk_rule
(mk_baresequent
(snoc H (mk_hyp x T) ++ J)
(mk_concl C t))
[ mk_baresequent (snoc H (mk_hyp x U) ++ J)
(mk_concl C t),
mk_baresequent (snoc (snoc (snoc H (mk_hyp x T))
(mk_hyp y U))
(mk_hyp z (mk_equality (mk_var x) (mk_var y) U)))
(mk_conclax (mk_equality (mk_var x) (mk_var y) T)),
mk_baresequent (snoc H (mk_hyp x T))
(mk_conclax (mk_member (mk_var x) U))
]
[sarg_var y, sarg_var z].
Lemma rule_widening_true {o} :
forall lib (T U C t : NTerm)
(x y z : NVar)
(i : nat)
(H J : @barehypotheses o),
rule_true lib
(rule_widening
T U C t
x y z
i
H J).
Proof.
unfold rule_widening, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent
(snoc H (mk_hyp x U) ++ J)
(mk_concl C t))
(inl eq_refl))
(hyps (mk_baresequent
(snoc (snoc (snoc H (mk_hyp x T)) (mk_hyp y U))
(mk_hyp z (mk_equality (mk_var x) (mk_var y) U)))
(mk_conclax (mk_equality (mk_var x) (mk_var y) T)))
(inr (inl eq_refl)))
(hyps (mk_baresequent
(snoc H (mk_hyp x T))
(mk_conclax (mk_member (mk_var x) U)))
(inr (inr (inl eq_refl))));
simpl; intros hyp1 hyp2 hyp3.
destruct hyp1 as [ ws1 hyp1 ].
destruct hyp2 as [ ws2 hyp2 ].
destruct hyp3 as [ ws3 hyp3 ].
destseq; allsimpl; proof_irr; GC.
clear hyps.
assert (covered t (nh_vars_hyps (snoc H (mk_hyp x T) ++ J)))
as co
by (duplicate ce1 as ce2;
allrw @nh_vars_hyps_app;
allrw @nh_vars_hyps_snoc;
allsimpl; sp).
exists co; GC.
(* We prove some simple facts on our sequents *)
assert (!LIn x (vars_hyps H)
# !LIn x (free_vars T)
# !LIn x (free_vars U)
# !(x = y)
# !LIn y (vars_hyps H)
# !LIn y (free_vars T)
# !LIn y (free_vars U)
# !LIn z (vars_hyps H)
# !LIn z (free_vars T)
# !LIn z (free_vars U)
# wf_term U
# covered T (vars_hyps H)
# covered U (vars_hyps H)) as vhyps.
clear hyp1 hyp2 hyp3.
dwfseq.
sp; try (complete (unfold covered; rw subvars_prop; sp)).
destruct vhyps as [ nixH vhyps ].
destruct vhyps as [ nixT vhyps ].
destruct vhyps as [ nixU vhyps ].
destruct vhyps as [ nixy vhyps ].
destruct vhyps as [ niyH vhyps ].
destruct vhyps as [ niyT vhyps ].
destruct vhyps as [ niyU vhyps ].
destruct vhyps as [ nizH vhyps ].
destruct vhyps as [ nizT vhyps ].
destruct vhyps as [ nizU vhyps ].
destruct vhyps as [ wfu vhyps ].
destruct vhyps as [ covTH covUH ].
(* done with proving these simple facts *)
(* we now start proving the sequent *)
vr_seq_true.
(* we split s1 and s2 *)
allrw @similarity_app; exrepd; subst; cpx.
allrw @similarity_snoc; exrepd; subst; cpx.
allsimpl.
(* we use our 1st subgoal to prove that tequality *)
vr_seq_true in hyp1.
generalize (hyp1 (snoc s1a0 (x, t1) ++ s1b)
(snoc s2a0 (x, t2) ++ s2b));
clear hyp1; intro hyp1.
autodimp hyp1 h.
introv sim.
allrw @similarity_app; exrepd; subst; allsimpl; cpx.
apply app_split in e; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
repeat (allrw @similarity_snoc; exrepd; subst; allsimpl; cpx; GC).
rw @eq_hyps_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t3)) s2b0;
allrw length_snoc; allrw; sp.
assert (cover_vars U s2a1)
as c2
by (apply @cover_vars_dom_csub_eq with (s1 := s1a); sp;
allrw @dom_csub_snoc; simpl;
allapply @similarity_dom; repd; allrw; sp).
rw @eq_hyps_snoc; simpl.
exists s1a s2a1 t0 t3 w0 p0 c2; sp.
generalize (eqh (snoc s2a1 (x, t2) ++ s2b)); intro imp.
autodimp imp hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t2)) s2b; repeat (rw length_snoc); sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t2 w p; sp.
rw @eq_hyps_app in imp; exrepnd.
apply app_split in imp0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in imp2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
rw @eq_hyps_snoc in imp5; exrepnd; sp; cpx.
generalize (eqh (snoc s2a1 (x, t2) ++ s2b)); intro imp.
autodimp imp hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t2)) s2b; repeat (rw length_snoc); sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t2 w p; sp.
rw @eq_hyps_app in imp; exrepnd.
apply app_split in imp0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in imp2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
rw @eq_hyps_snoc in imp5; exrepnd; sp; cpx; allsimpl; cpx; clear_irr.
(* from imp0 and sequent 3 *)
generalize (subtype_tequality lib s1a0 s2a H T U x t1 t4 w w0 p p0 c2 (wfh0, (wfct0, wfce1), (ct, ce)));
intro j; repeat (autodimp j hyp).
apply hyps_functionality_init_seg with (s3 := s2b1) in eqh; sp.
assert (cover_vars T s2a1)
as c2
by (apply @cover_vars_dom_csub_eq with (s1 := s1a); sp;
allrw @dom_csub_snoc; simpl;
allapply @similarity_dom; repd; allrw; sp).
generalize (eqh (snoc s2a1 (x, t3) ++ s2b0)); intro j; autodimp j hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t3)) s2b0; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t3 w p; sp.
generalize (strong_subtype_equality lib s1a s2a1 t0 t2 t3 T U w w0 p p0 c2 H x y z
(wfh0, (wfct0, wfce1), (ct, ce))
(wfh1, (wfct1, wfce1), (ct0, ce0)));
intro q; repeat (destimp q hyp).
repnd.
apply hyps_functionality_init_seg with (s3 := s2b) in eqh; sp.
apply @equality_commutes4 with (U := lsubstc T w s2a1 c2) (a2 := t0) (a3 := t2); sp.
rw @eq_hyps_app in j; exrepnd.
apply app_split in j0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in j2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
(* we're done proving the hyps_functionality part for sequent 1 *)
(* we now have to prove the similarity part *)
autodimp hyp1 h.
rw @similarity_app; simpl.
exists (snoc s1a0 (x, t1)) s1b (snoc s2a0 (x, t2)) s2b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
assert (cover_vars U s1a0)
as c1 by (allrw @cover_vars_covered; allapply @similarity_dom; exrepnd; allrw; sp).
exists s1a0 s2a0 t1 t2 wfu c1; sp.
generalize (subtype_equality lib t1 t2 T U s1a0 s2a0 w wfu p c1 H x
(wfh0, (wfct0, wfce1), (ct, ce)));
intro j; repeat (autodimp j hyp).
apply hyps_functionality_init_seg with (s3 := s2b) in eqh; sp.
exrepnd; clear_irr; sp.
Qed.
(* begin hide *)
(* end hide *)
(* [18] ============ CUT ============ *)
(**
The following rule is the standard cut rule:
<<
H |- C ext t[x\u]
By cut x B
H |- B ext u
H, x : B |- C ext t
>>
*)
Definition rule_cut_concl {o} (H : @bhyps o) C t x u :=
mk_baresequent H (mk_concl C (subst t x u)).
Definition rule_cut_hyp1 {o} (H : @bhyps o) B u :=
mk_baresequent H (mk_concl B u).
Definition rule_cut_hyp2 {o} (H : @bhyps o) x B C t :=
mk_baresequent (snoc H (mk_hyp x B)) (mk_concl C t).
Definition rule_cut {o}
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar) :=
mk_rule
(rule_cut_concl H C t x u)
[ rule_cut_hyp1 H B u,
rule_cut_hyp2 H x B C t
]
[sarg_var x].
Lemma rule_cut_true3 {o} :
forall lib (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true3 lib (rule_cut H B C t u x).
Proof.
unfold rule_cut, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros; repnd.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
rename Hyp into hyp1.
rename Hyp0 into hyp2.
destruct hyp1 as [ws1 hyp1].
destruct hyp2 as [ws2 hyp2].
destseq; allsimpl; clear_irr; GC.
assert (covered (subst t x u) (vars_hyps (filter is_nh H))) as cv.
{ clear hyp1 hyp2.
dwfseq.
introv i.
pose proof (eqvars_free_vars_disjoint t [(x,u)]) as eqv.
rw eqvars_prop in eqv.
rw @fold_subst in eqv.
rw eqv in i.
rw in_app_iff in i; rw in_remove_nvars in i; allsimpl; sp.
- apply not_over_or in p; sp.
apply ce in p0.
apply in_snoc in p0; sp.
- allapply @in_sub_free_vars; sp.
destruct (memvar x (free_vars t)); allsimpl; sp; cpx.
}
assert (wf_csequent (rule_cut_concl H C t x u)) as wfc.
{ unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; auto.
apply wf_term_subst; auto.
}
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; allsimpl; repnd; proof_irr; GC.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars B)
# ! LIn x (free_vars C)
# ! LIn x (free_vars u)
# ! LIn x (vars_hyps H)
# wf_term u
# wf_term B
# covered u (nh_vars_hyps H)
# covered B (vars_hyps H)) as vhyps.
{ clear hyp1 hyp2.
dwfseq.
sp;
try (complete (generalize (ce0 x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (rw subvars_eq; unfold subset; sp)).
}
destruct vhyps as [ nixb vhyps ].
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixu vhyps ].
destruct vhyps as [ nixh vhyps ].
destruct vhyps as [ wu vhyps ].
destruct vhyps as [ wb vhyps ].
destruct vhyps as [ cuh cbh ].
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp2.
assert (cover_vars u s1)
as cu1
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
assert (cover_vars u s2)
as cu2
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
generalize (hyp2
(snoc s1 (x, lsubstc u wfce0 s1 cu1))
(snoc s2 (x, lsubstc u wfce0 s2 cu2))); clear hyp2; intro hyp2.
autodimp hyp2 hyp.
{ apply hyps_functionality_snoc2; simpl; auto.
introv eq sim'; allsimpl.
vr_seq_true in hyp1.
generalize (hyp1 s1 s'); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
}
assert (cover_vars B s1) as cvbs1 by (rw @cover_vars_eq; insub).
autodimp hyp2 hyp.
{ sim_snoc; dands; auto.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
}
exrepnd.
lsubst_tac.
dands; auto.
repeat lsubstc_subst_aeq2.
repeat substc_lsubstc_vars3.
proof_irr.
pose proof (lsubstc_snoc_move t s1 [] x (lsubstc u wfce0 s1 cu1) wfce) as e1.
pose proof (lsubstc_snoc_move t s2 [] x (lsubstc u wfce0 s2 cu2) wfce) as e2.
allrw app_nil_r.
pose proof (e1 pt0) as k1; clear e1.
pose proof (e2 pt3) as k2; clear e2.
autodimp k1 hyp.
{ apply similarity_dom in sim; repnd; rw sim0; auto. }
autodimp k2 hyp.
{ apply similarity_dom in sim; repnd; rw sim; auto. }
exrepnd.
proof_irr.
rw <- k2; rw <- k0; auto.
Qed.
Lemma rule_cut_true_ext_lib {o} :
forall lib (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true_ext_lib lib (rule_cut H B C t u x).
Proof.
introv.
apply rule_true3_implies_rule_true_ext_lib.
introv.
apply rule_cut_true3.
Qed.
(* begin hide *)
Lemma rule_cut_true {o} :
forall lib (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true lib (rule_cut H B C t u x).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_cut_true3.
Qed.
Lemma rule_cut_true_ex {o} :
forall lib (H : @bhyps o) B C t u x,
rule_true_if lib (rule_cut H B C t u x).
Proof.
intros.
generalize (rule_cut_true lib H B C t u x); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
Lemma rule_cut_true2 {o} :
forall lib (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true2 lib (rule_cut H B C t u x).
Proof.
introv.
apply rule_true_iff_rule_true2; sp.
apply rule_cut_true.
Qed.
Lemma rule_cut_wf {o} :
forall (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
wf_term B
-> wf_term u
-> covered B (vars_hyps H)
-> !LIn x (vars_hyps H)
-> wf_rule (rule_cut H B C t u x).
Proof.
introv wB wu covB nixH pwf m; allsimpl; repndors; subst; tcsp;
allunfold @pwf_sequent; wfseq; tcsp.
- apply vswf_hypotheses_snoc; dands; simpl; auto.
apply isprog_vars_eq; dands; auto.
apply nt_wf_eq; auto.
- apply lsubst_wf_term in pwf0; auto.
- apply covered_snoc_weak; auto.
Qed.
Lemma rule_cut_wf2 {o} :
forall (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
wf_term B
-> covered B (vars_hyps H)
-> !LIn x (vars_hyps H)
-> wf_rule2 (rule_cut H B C t u x).
Proof.
introv wB covB nixH pwf m; allsimpl; repndors; subst; tcsp;
allunfold @wf_bseq; wfseq; tcsp.
- apply vswf_hypotheses_snoc; dands; simpl; auto.
apply isprog_vars_eq; dands; auto.
apply nt_wf_eq; auto.
- apply covered_snoc_weak; auto.
Qed.
(* end hide *)
(* [19] ============ CUTH ============ *)
(**
This rule is similar to the cut rule, but is valid only if [x] is
not free in the extract:
<<
H |- C ext t
By cutH x B
H |- B ext u
H, [x : B] |- C ext t
>>
*)
Definition rule_cutH {o}
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent H (mk_concl C t))
[ mk_baresequent H (mk_concl B u),
mk_baresequent (snoc H (mk_hhyp x B)) (mk_concl C t)
]
[sarg_var x].
Lemma rule_cutH_true {o} :
forall lib (H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true lib (rule_cutH H B C t u x).
Proof.
unfold rule_cutH, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent H (mk_concl B u))
(inl eq_refl))
(hyps (mk_baresequent (snoc H (mk_hhyp x B)) (mk_concl C t))
(inr (inl eq_refl)));
simpl; intros hyp1 hyp2; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destruct hyp2 as [ ws2 hyp2 ].
destseq; allsimpl; proof_irr; GC.
assert (covered t (vars_hyps (filter is_nh H))) as cv.
clear hyp1 hyp2.
dwfseq.
introv i.
apply ce in i; sp.
exists cv.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars B)
/\ ! LIn x (free_vars C)
/\ ! LIn x (free_vars u)
/\ ! LIn x (vars_hyps H)
/\ ! LIn x (free_vars t)
/\ wf_term u
/\ wf_term B
/\ covered u (nh_vars_hyps H)
/\ covered B (vars_hyps H)) as vhyps.
clear hyp1 hyp2.
dwfseq.
sp;
try (complete (generalize (ce0 x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (generalize (ce x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (rw subvars_eq; unfold subset; sp)).
destruct vhyps as [ nixb vhyps ].
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixu vhyps ].
destruct vhyps as [ nixh vhyps ].
destruct vhyps as [ nixt vhyps ].
destruct vhyps as [ wu vhyps ].
destruct vhyps as [ wb vhyps ].
destruct vhyps as [ cuh cbh ].
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp2.
assert (cover_vars u s1)
as cu1
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
assert (cover_vars u s2)
as cu2
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
generalize (hyp2
(snoc s1 (x, lsubstc u wfce1 s1 cu1))
(snoc s2 (x, lsubstc u wfce1 s2 cu2))); clear hyp2; intro hyp2.
autodimp hyp2 hyp.
generalize (hyps_functionality_snoc lib H (mk_hhyp x B) s1 (lsubstc u wfce1 s1 cu1)).
intro imp; apply imp; thin imp; try (complete auto).
introv eq sim'; allsimpl.
vr_seq_true in hyp1.
generalize (hyp1 s1 s'); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
assert (cover_vars B s1) as cvbs1 by (rw @cover_vars_eq; insub).
autodimp hyp2 hyp.
rw @similarity_snoc; simpl.
exists s1 s2 (lsubstc u wfce1 s1 cu1) (lsubstc u wfce1 s2 cu2) wfct1 cvbs1; sp.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
exrepnd.
lsubst_tac; sp.
Qed.
(* begin hide *)
Lemma rule_cutH_true_ex {o} :
forall lib (H : @bhyps o) B C t u x,
rule_true_if lib (rule_cutH H B C t u x).
Proof.
intros.
generalize (rule_cutH_true lib H B C t u x); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
(* end hide *)
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 , n2161 , n2162 , n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 , n2171 , n2172 , n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 , n2181 , n2182 , n2183 , n2184 , n2185 , n2186 , n2187 , n2188 , n2189 , n2190 , n2191 , n2192 , n2193 , n2194 , n2195 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 , n2161 , n2162 , n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 , n2171 , n2172 , n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 , n2181 , n2182 , n2183 , n2184 , n2185 ;
output n2186 , n2187 , n2188 , n2189 , n2190 , n2191 , n2192 , n2193 , n2194 , n2195 ;
wire n4394 , n4395 , n4396 , n4397 , n4398 , n4399 , n4400 ,
n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 , n4409 , n4410 ,
n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 , n4419 , n4420 ,
n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 , n4429 , n4430 ,
n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 , n4439 , n4440 ,
n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 , n4449 , n4450 ,
n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 , n4459 , n4460 ,
n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 , n4469 , n4470 ,
n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 , n4479 , n4480 ,
n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 , n4489 , n4490 ,
n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 , n4499 , n4500 ,
n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 , n4509 , n4510 ,
n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 , n4519 , n4520 ,
n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 , n4529 , n4530 ,
n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 , n4539 , n4540 ,
n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 , n4549 , n4550 ,
n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 , n4559 , n4560 ,
n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 , n4569 , n4570 ,
n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 , n4579 , n4580 ,
n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 , n4589 , n4590 ,
n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 , n4599 , n4600 ,
n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 , n4609 , n4610 ,
n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 , n4619 , n4620 ,
n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 , n4629 , n4630 ,
n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 , n4639 , n4640 ,
n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 , n4649 , n4650 ,
n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 , n4659 , n4660 ,
n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 , n4669 , n4670 ,
n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 , n4679 , n4680 ,
n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 , n4689 , n4690 ,
n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 , n4699 , n4700 ,
n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 , n4709 , n4710 ,
n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 , n4719 , n4720 ,
n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 , n4729 , n4730 ,
n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 , n4739 , n4740 ,
n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 , n4749 , n4750 ,
n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 , n4759 , n4760 ,
n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 , n4769 , n4770 ,
n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 , n4779 , n4780 ,
n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 , n4789 , n4790 ,
n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 , n4799 , n4800 ,
n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 , n4809 , n4810 ,
n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 , n4819 , n4820 ,
n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 , n4829 , n4830 ,
n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 , n4839 , n4840 ,
n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 , n4849 , n4850 ,
n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 , n4859 , n4860 ,
n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 , n4869 , n4870 ,
n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 , n4879 , n4880 ,
n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 , n4889 , n4890 ,
n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 , n4899 , n4900 ,
n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 , n4909 , n4910 ,
n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 , n4919 , n4920 ,
n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 , n4929 , n4930 ,
n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 , n4939 , n4940 ,
n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 , n4949 , n4950 ,
n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 , n4959 , n4960 ,
n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 , n4969 , n4970 ,
n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 , n4979 , n4980 ,
n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 , n4989 , n4990 ,
n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 , n4999 , n5000 ,
n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 , n5009 , n5010 ,
n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 , n5019 , n5020 ,
n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 , n5029 , n5030 ,
n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 , n5039 , n5040 ,
n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 , n5049 , n5050 ,
n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 , n5059 , n5060 ,
n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 , n5069 , n5070 ,
n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 , n5079 , n5080 ,
n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 , n5089 , n5090 ,
n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 , n5099 , n5100 ,
n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 , n5109 , n5110 ,
n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 , n5119 , n5120 ,
n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 , n5129 , n5130 ,
n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 , n5139 , n5140 ,
n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 , n5149 , n5150 ,
n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 , n5159 , n5160 ,
n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 , n5169 , n5170 ,
n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 , n5179 , n5180 ,
n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 , n5189 , n5190 ,
n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 , n5199 , n5200 ,
n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 , n5209 , n5210 ,
n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 , n5219 , n5220 ,
n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 , n5229 , n5230 ,
n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 , n5239 , n5240 ,
n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 , n5249 , n5250 ,
n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 , n5259 , n5260 ,
n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 , n5269 , n5270 ,
n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 , n5279 , n5280 ,
n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 , n5289 , n5290 ,
n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 , n5299 , n5300 ,
n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 , n5309 , n5310 ,
n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 , n5319 , n5320 ,
n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 , n5329 , n5330 ,
n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 , n5339 , n5340 ,
n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 , n5349 , n5350 ,
n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 , n5359 , n5360 ,
n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 , n5369 , n5370 ,
n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 , n5379 , n5380 ,
n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 , n5389 , n5390 ,
n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 , n5399 , n5400 ,
n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 , n5409 , n5410 ,
n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 , n5419 , n5420 ,
n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 , n5429 , n5430 ,
n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 , n5439 , n5440 ,
n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 , n5449 , n5450 ,
n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 , n5459 , n5460 ,
n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 , n5469 , n5470 ,
n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 , n5479 , n5480 ,
n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 , n5489 , n5490 ,
n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 , n5499 , n5500 ,
n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 , n5509 , n5510 ,
n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 , n5519 , n5520 ,
n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 , n5529 , n5530 ,
n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 , n5539 , n5540 ,
n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 , n5549 , n5550 ,
n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 , n5559 , n5560 ,
n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 , n5569 , n5570 ,
n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 , n5579 , n5580 ,
n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 , n5589 , n5590 ,
n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 , n5599 , n5600 ,
n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 , n5609 , n5610 ,
n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 , n5619 , n5620 ,
n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 , n5629 , n5630 ,
n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 , n5639 , n5640 ,
n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 , n5649 , n5650 ,
n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 , n5659 , n5660 ,
n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 , n5669 , n5670 ,
n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 , n5679 , n5680 ,
n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 , n5689 , n5690 ,
n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 , n5699 , n5700 ,
n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 , n5709 , n5710 ,
n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 , n5719 , n5720 ,
n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 , n5729 , n5730 ,
n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 , n5739 , n5740 ,
n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 , n5749 , n5750 ,
n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 , n5759 , n5760 ,
n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 , n5769 , n5770 ,
n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 , n5779 , n5780 ,
n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 , n5789 , n5790 ,
n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 , n5799 , n5800 ,
n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 , n5809 , n5810 ,
n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 , n5819 , n5820 ,
n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 , n5829 , n5830 ,
n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 , n5839 , n5840 ,
n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 , n5849 , n5850 ,
n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 , n5859 , n5860 ,
n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 , n5869 , n5870 ,
n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 , n5879 , n5880 ,
n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 , n5889 , n5890 ,
n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 , n5899 , n5900 ,
n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 , n5909 , n5910 ,
n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 , n5919 , n5920 ,
n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 , n5929 , n5930 ,
n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 , n5939 , n5940 ,
n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 , n5949 , n5950 ,
n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 , n5959 , n5960 ,
n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 , n5969 , n5970 ,
n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 , n5979 , n5980 ,
n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 , n5989 , n5990 ,
n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 , n5999 , n6000 ,
n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 , n6009 , n6010 ,
n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 , n6019 , n6020 ,
n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 , n6029 , n6030 ,
n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 , n6039 , n6040 ,
n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 , n6049 , n6050 ,
n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 , n6059 , n6060 ,
n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 , n6069 , n6070 ,
n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 , n6079 , n6080 ,
n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 , n6089 , n6090 ,
n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 , n6099 , n6100 ,
n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 , n6109 , n6110 ,
n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 , n6119 , n6120 ,
n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 , n6129 , n6130 ,
n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 , n6139 , n6140 ,
n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 , n6149 , n6150 ,
n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 , n6159 , n6160 ,
n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 , n6169 , n6170 ,
n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 , n6179 , n6180 ,
n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 , n6189 , n6190 ,
n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 , n6199 , n6200 ,
n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 , n6209 , n6210 ,
n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 , n6219 , n6220 ,
n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 , n6229 , n6230 ,
n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 , n6239 , n6240 ,
n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 , n6249 , n6250 ,
n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 , n6259 , n6260 ,
n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 , n6269 , n6270 ,
n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 , n6279 , n6280 ,
n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 , n6289 , n6290 ,
n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 , n6299 , n6300 ,
n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 , n6309 , n6310 ,
n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 , n6319 , n6320 ,
n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 , n6329 , n6330 ,
n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 , n6339 , n6340 ,
n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 , n6349 , n6350 ,
n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 , n6359 , n6360 ,
n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 , n6369 , n6370 ,
n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 , n6379 , n6380 ,
n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 , n6389 , n6390 ,
n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 , n6399 , n6400 ,
n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 , n6409 , n6410 ,
n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 , n6419 , n6420 ,
n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 , n6429 , n6430 ,
n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 , n6439 , n6440 ,
n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 , n6449 , n6450 ,
n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 , n6459 , n6460 ,
n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 , n6469 , n6470 ,
n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 , n6479 , n6480 ,
n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 , n6489 , n6490 ,
n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 , n6499 , n6500 ,
n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 , n6509 , n6510 ,
n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 , n6519 , n6520 ,
n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 , n6529 , n6530 ,
n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 , n6539 , n6540 ,
n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 , n6549 , n6550 ,
n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 , n6559 , n6560 ,
n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 , n6569 , n6570 ,
n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 , n6579 , n6580 ,
n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 , n6589 , n6590 ,
n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 , n6599 , n6600 ,
n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 , n6609 , n6610 ,
n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 , n6619 , n6620 ,
n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 , n6629 , n6630 ,
n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 , n6639 , n6640 ,
n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 , n6649 , n6650 ,
n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 , n6659 , n6660 ,
n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 , n6669 , n6670 ,
n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 , n6679 , n6680 ,
n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 , n6689 , n6690 ,
n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 , n6699 , n6700 ,
n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 , n6709 , n6710 ,
n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 , n6719 , n6720 ,
n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 , n6729 , n6730 ,
n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 , n6739 , n6740 ,
n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 , n6749 , n6750 ,
n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 , n6759 , n6760 ,
n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 , n6769 , n6770 ,
n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 , n6779 , n6780 ,
n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 , n6789 , n6790 ,
n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 , n6799 , n6800 ,
n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 , n6809 , n6810 ,
n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 , n6819 , n6820 ,
n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 , n6829 , n6830 ,
n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 , n6839 , n6840 ,
n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 , n6849 , n6850 ,
n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 , n6859 , n6860 ,
n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 , n6869 , n6870 ,
n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 , n6879 , n6880 ,
n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 , n6889 , n6890 ,
n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 , n6899 , n6900 ,
n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 , n6909 , n6910 ,
n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 , n6919 , n6920 ,
n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 , n6929 , n6930 ,
n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 , n6939 , n6940 ,
n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 , n6949 , n6950 ,
n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 , n6959 , n6960 ,
n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 , n6969 , n6970 ,
n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 , n6979 , n6980 ,
n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 , n6989 , n6990 ,
n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 , n6999 , n7000 ,
n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 , n7009 , n7010 ,
n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 , n7019 , n7020 ,
n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 , n7029 , n7030 ,
n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 , n7039 , n7040 ,
n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 , n7049 , n7050 ,
n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 , n7059 , n7060 ,
n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 , n7069 , n7070 ,
n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 , n7079 , n7080 ,
n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 , n7089 , n7090 ,
n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 , n7099 , n7100 ,
n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 , n7109 , n7110 ,
n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 , n7119 , n7120 ,
n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 , n7129 , n7130 ,
n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 , n7139 , n7140 ,
n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 , n7149 , n7150 ,
n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 , n7159 , n7160 ,
n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 , n7169 , n7170 ,
n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 , n7179 , n7180 ,
n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 , n7189 , n7190 ,
n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 , n7199 , n7200 ,
n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 , n7209 , n7210 ,
n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 , n7219 , n7220 ,
n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 , n7229 , n7230 ,
n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 , n7239 , n7240 ,
n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 , n7249 , n7250 ,
n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 , n7259 , n7260 ,
n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 , n7269 , n7270 ,
n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 , n7279 , n7280 ,
n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 , n7289 , n7290 ,
n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 , n7299 , n7300 ,
n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 , n7309 , n7310 ,
n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 , n7319 , n7320 ,
n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 , n7329 , n7330 ,
n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 , n7339 , n7340 ,
n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 , n7349 , n7350 ,
n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 , n7359 , n7360 ,
n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 , n7369 , n7370 ,
n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 , n7379 , n7380 ,
n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 , n7389 , n7390 ,
n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 , n7399 , n7400 ,
n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 , n7409 , n7410 ,
n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 , n7419 , n7420 ,
n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 , n7429 , n7430 ,
n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 , n7439 , n7440 ,
n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 , n7449 , n7450 ,
n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 , n7459 , n7460 ,
n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 , n7469 , n7470 ,
n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 , n7479 , n7480 ,
n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 , n7489 , n7490 ,
n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 , n7499 , n7500 ,
n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 , n7509 , n7510 ,
n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 , n7519 , n7520 ,
n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 , n7529 , n7530 ,
n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 , n7539 , n7540 ,
n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 , n7549 , n7550 ,
n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 , n7559 , n7560 ,
n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 , n7569 , n7570 ,
n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 , n7579 , n7580 ,
n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 , n7589 , n7590 ,
n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 , n7599 , n7600 ,
n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 , n7609 , n7610 ,
n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 , n7619 , n7620 ,
n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 , n7629 , n7630 ,
n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 , n7639 , n7640 ,
n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 , n7649 , n7650 ,
n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 , n7659 , n7660 ,
n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 , n7669 , n7670 ,
n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 , n7679 , n7680 ,
n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 , n7689 , n7690 ,
n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 , n7699 , n7700 ,
n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 , n7709 , n7710 ,
n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 , n7719 , n7720 ,
n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 , n7729 , n7730 ,
n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 , n7739 , n7740 ,
n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 , n7749 , n7750 ,
n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 , n7759 , n7760 ,
n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 , n7769 , n7770 ,
n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 , n7779 , n7780 ,
n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 , n7789 , n7790 ,
n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 , n7799 , n7800 ,
n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 , n7809 , n7810 ,
n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 , n7819 , n7820 ,
n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 , n7829 , n7830 ,
n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 , n7839 , n7840 ,
n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 , n7849 , n7850 ,
n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 , n7859 , n7860 ,
n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 , n7869 , n7870 ,
n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 , n7879 , n7880 ,
n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 , n7889 , n7890 ,
n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 , n7899 , n7900 ,
n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 , n7909 , n7910 ,
n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 , n7919 , n7920 ,
n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 , n7929 , n7930 ,
n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 , n7939 , n7940 ,
n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 , n7949 , n7950 ,
n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 , n7959 , n7960 ,
n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 , n7969 , n7970 ,
n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 , n7979 , n7980 ,
n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 , n7989 , n7990 ,
n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 , n7999 , n8000 ,
n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 , n8009 , n8010 ,
n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 , n8019 , n8020 ,
n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 , n8029 , n8030 ,
n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 , n8039 , n8040 ,
n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 , n8049 , n8050 ,
n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 , n8059 , n8060 ,
n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 , n8069 , n8070 ,
n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 , n8079 , n8080 ,
n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 , n8089 , n8090 ,
n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 , n8099 , n8100 ,
n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 , n8109 , n8110 ,
n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 , n8119 , n8120 ,
n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 , n8129 , n8130 ,
n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 , n8139 , n8140 ,
n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 , n8149 , n8150 ,
n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 , n8159 , n8160 ,
n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 , n8169 , n8170 ,
n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 , n8179 , n8180 ,
n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 , n8189 , n8190 ,
n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 , n8199 , n8200 ,
n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 , n8209 , n8210 ,
n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 , n8219 , n8220 ,
n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 , n8229 , n8230 ,
n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 , n8239 , n8240 ,
n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 , n8249 , n8250 ,
n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 , n8259 , n8260 ,
n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 , n8269 , n8270 ,
n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 , n8279 , n8280 ,
n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 , n8289 , n8290 ,
n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 , n8299 , n8300 ,
n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 , n8309 , n8310 ,
n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 , n8319 , n8320 ,
n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 , n8329 , n8330 ,
n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 , n8339 , n8340 ,
n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 , n8349 , n8350 ,
n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 , n8359 , n8360 ,
n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 , n8369 , n8370 ,
n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 , n8379 , n8380 ,
n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 , n8389 , n8390 ,
n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 , n8399 , n8400 ,
n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 , n8409 , n8410 ,
n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 , n8419 , n8420 ,
n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 , n8429 , n8430 ,
n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 , n8439 , n8440 ,
n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 , n8449 , n8450 ,
n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 , n8459 , n8460 ,
n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 , n8469 , n8470 ,
n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 , n8479 , n8480 ,
n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 , n8489 , n8490 ,
n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 , n8499 , n8500 ,
n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 , n8509 , n8510 ,
n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 , n8519 , n8520 ,
n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 , n8529 , n8530 ,
n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 , n8539 , n8540 ,
n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 , n8549 , n8550 ,
n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 , n8559 , n8560 ,
n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 , n8569 , n8570 ,
n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 , n8579 , n8580 ,
n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 , n8589 , n8590 ,
n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 , n8599 , n8600 ,
n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 , n8609 , n8610 ,
n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 , n8619 , n8620 ,
n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 , n8629 , n8630 ,
n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 , n8639 , n8640 ,
n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 , n8649 , n8650 ,
n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 , n8659 , n8660 ,
n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 , n8669 , n8670 ,
n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 , n8679 , n8680 ,
n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 , n8689 , n8690 ,
n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 , n8699 , n8700 ,
n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 , n8709 , n8710 ,
n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 , n8719 , n8720 ,
n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 , n8729 , n8730 ,
n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 , n8739 , n8740 ,
n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 , n8749 , n8750 ,
n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 , n8759 , n8760 ,
n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 , n8769 , n8770 ,
n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 , n8779 , n8780 ,
n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 , n8789 , n8790 ,
n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 , n8799 , n8800 ,
n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 , n8809 , n8810 ,
n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 , n8819 , n8820 ,
n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 , n8829 , n8830 ,
n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 , n8838 , n8839 , n8840 ,
n8841 , n8842 , n8843 , n8844 , n8845 , n8846 , n8847 , n8848 , n8849 , n8850 ,
n8851 , n8852 , n8853 , n8854 , n8855 , n8856 , n8857 , n8858 , n8859 , n8860 ,
n8861 , n8862 , n8863 , n8864 , n8865 , n8866 , n8867 , n8868 , n8869 , n8870 ,
n8871 , n8872 , n8873 , n8874 , n8875 , n8876 , n8877 , n8878 , n8879 , n8880 ,
n8881 , n8882 , n8883 , n8884 , n8885 , n8886 , n8887 , n8888 , n8889 , n8890 ,
n8891 , n8892 , n8893 , n8894 , n8895 , n8896 , n8897 , n8898 , n8899 , n8900 ,
n8901 , n8902 , n8903 , n8904 , n8905 , n8906 , n8907 , n8908 , n8909 , n8910 ,
n8911 , n8912 , n8913 , n8914 , n8915 , n8916 , n8917 , n8918 , n8919 , n8920 ,
n8921 , n8922 , n8923 , n8924 , n8925 , n8926 , n8927 , n8928 , n8929 , n8930 ,
n8931 , n8932 , n8933 , n8934 , n8935 , n8936 , n8937 , n8938 , n8939 , n8940 ,
n8941 , n8942 , n8943 , n8944 , n8945 , n8946 , n8947 , n8948 , n8949 , n8950 ,
n8951 , n8952 , n8953 , n8954 , n8955 , n8956 , n8957 , n8958 , n8959 , n8960 ,
n8961 , n8962 , n8963 , n8964 , n8965 , n8966 , n8967 , n8968 , n8969 , n8970 ,
n8971 , n8972 , n8973 , n8974 , n8975 , n8976 , n8977 , n8978 , n8979 , n8980 ,
n8981 , n8982 , n8983 , n8984 , n8985 , n8986 , n8987 , n8988 , n8989 , n8990 ,
n8991 , n8992 , n8993 , n8994 , n8995 , n8996 , n8997 , n8998 , n8999 , n9000 ,
n9001 , n9002 , n9003 , n9004 , n9005 , n9006 , n9007 , n9008 , n9009 , n9010 ,
n9011 , n9012 , n9013 , n9014 , n9015 , n9016 , n9017 , n9018 , n9019 , n9020 ,
n9021 , n9022 , n9023 , n9024 , n9025 , n9026 , n9027 , n9028 , n9029 , n9030 ,
n9031 , n9032 , n9033 , n9034 , n9035 , n9036 , n9037 , n9038 , n9039 , n9040 ,
n9041 , n9042 , n9043 , n9044 , n9045 , n9046 , n9047 , n9048 , n9049 , n9050 ,
n9051 , n9052 , n9053 , n9054 , n9055 , n9056 , n9057 , n9058 , n9059 , n9060 ,
n9061 , n9062 , n9063 , n9064 , n9065 , n9066 , n9067 , n9068 , n9069 , n9070 ,
n9071 , n9072 , n9073 , n9074 , n9075 , n9076 , n9077 , n9078 , n9079 , n9080 ,
n9081 , n9082 , n9083 , n9084 , n9085 , n9086 , n9087 , n9088 , n9089 , n9090 ,
n9091 , n9092 , n9093 , n9094 , n9095 , n9096 , n9097 , n9098 , n9099 , n9100 ,
n9101 , n9102 , n9103 , n9104 , n9105 , n9106 , n9107 , n9108 , n9109 , n9110 ,
n9111 , n9112 , n9113 , n9114 , n9115 , n9116 , n9117 , n9118 , n9119 , n9120 ,
n9121 , n9122 , n9123 , n9124 , n9125 , n9126 , n9127 , n9128 , n9129 , n9130 ,
n9131 , n9132 , n9133 , n9134 , n9135 , n9136 , n9137 , n9138 , n9139 , n9140 ,
n9141 , n9142 , n9143 , n9144 , n9145 , n9146 , n9147 , n9148 , n9149 , n9150 ,
n9151 , n9152 , n9153 , n9154 , n9155 , n9156 , n9157 , n9158 , n9159 , n9160 ,
n9161 , n9162 , n9163 , n9164 , n9165 , n9166 , n9167 , n9168 , n9169 , n9170 ,
n9171 , n9172 , n9173 , n9174 , n9175 , n9176 , n9177 , n9178 , n9179 , n9180 ,
n9181 , n9182 , n9183 , n9184 , n9185 , n9186 , n9187 , n9188 , n9189 , n9190 ,
n9191 , n9192 , n9193 , n9194 , n9195 , n9196 , n9197 , n9198 , n9199 , n9200 ,
n9201 , n9202 , n9203 , n9204 , n9205 , n9206 , n9207 , n9208 , n9209 , n9210 ,
n9211 , n9212 , n9213 , n9214 , n9215 , n9216 , n9217 , n9218 , n9219 , n9220 ,
n9221 , n9222 , n9223 , n9224 , n9225 , n9226 , n9227 , n9228 , n9229 , n9230 ,
n9231 , n9232 , n9233 , n9234 , n9235 , n9236 , n9237 , n9238 , n9239 , n9240 ,
n9241 , n9242 , n9243 , n9244 , n9245 , n9246 , n9247 , n9248 , n9249 , n9250 ,
n9251 , n9252 , n9253 , n9254 , n9255 , n9256 , n9257 , n9258 , n9259 , n9260 ,
n9261 , n9262 , n9263 , n9264 , n9265 , n9266 , n9267 , n9268 , n9269 , n9270 ,
n9271 , n9272 , n9273 , n9274 , n9275 , n9276 , n9277 , n9278 , n9279 , n9280 ,
n9281 , n9282 , n9283 , n9284 , n9285 , n9286 , n9287 , n9288 , n9289 , n9290 ,
n9291 , n9292 , n9293 , n9294 , n9295 , n9296 , n9297 , n9298 , n9299 , n9300 ,
n9301 , n9302 , n9303 , n9304 , n9305 , n9306 , n9307 , n9308 , n9309 , n9310 ,
n9311 , n9312 , n9313 , n9314 , n9315 , n9316 , n9317 , n9318 , n9319 , n9320 ,
n9321 , n9322 , n9323 , n9324 , n9325 , n9326 , n9327 , n9328 , n9329 , n9330 ,
n9331 , n9332 , n9333 , n9334 , n9335 , n9336 , n9337 , n9338 , n9339 , n9340 ,
n9341 , n9342 , n9343 , n9344 , n9345 , n9346 , n9347 , n9348 , n9349 , n9350 ,
n9351 , n9352 , n9353 , n9354 , n9355 , n9356 , n9357 , n9358 , n9359 , n9360 ,
n9361 , n9362 , n9363 , n9364 , n9365 , n9366 , n9367 , n9368 , n9369 , n9370 ,
n9371 , n9372 , n9373 , n9374 , n9375 , n9376 , n9377 , n9378 , n9379 , n9380 ,
n9381 , n9382 , n9383 , n9384 , n9385 , n9386 , n9387 , n9388 , n9389 , n9390 ,
n9391 , n9392 , n9393 , n9394 , n9395 , n9396 , n9397 , n9398 , n9399 , n9400 ,
n9401 , n9402 , n9403 , n9404 , n9405 , n9406 , n9407 , n9408 , n9409 , n9410 ,
n9411 , n9412 , n9413 , n9414 , n9415 , n9416 , n9417 , n9418 , n9419 , n9420 ,
n9421 , n9422 , n9423 , n9424 , n9425 , n9426 , n9427 , n9428 , n9429 , n9430 ,
n9431 , n9432 , n9433 , n9434 , n9435 , n9436 , n9437 , n9438 , n9439 , n9440 ,
n9441 , n9442 , n9443 , n9444 , n9445 , n9446 , n9447 , n9448 , n9449 , n9450 ,
n9451 , n9452 , n9453 , n9454 , n9455 , n9456 , n9457 , n9458 , n9459 , n9460 ,
n9461 , n9462 , n9463 , n9464 , n9465 , n9466 , n9467 , n9468 , n9469 , n9470 ,
n9471 , n9472 , n9473 , n9474 , n9475 , n9476 , n9477 , n9478 , n9479 , n9480 ,
n9481 , n9482 , n9483 , n9484 , n9485 , n9486 , n9487 , n9488 , n9489 , n9490 ,
n9491 , n9492 , n9493 , n9494 , n9495 , n9496 , n9497 , n9498 , n9499 , n9500 ,
n9501 , n9502 , n9503 , n9504 , n9505 , n9506 , n9507 , n9508 , n9509 , n9510 ,
n9511 , n9512 , n9513 , n9514 , n9515 , n9516 , n9517 , n9518 , n9519 , n9520 ,
n9521 , n9522 , n9523 , n9524 , n9525 , n9526 , n9527 , n9528 , n9529 , n9530 ,
n9531 , n9532 , n9533 , n9534 , n9535 , n9536 , n9537 , n9538 , n9539 , n9540 ,
n9541 , n9542 , n9543 , n9544 , n9545 , n9546 , n9547 , n9548 , n9549 , n9550 ,
n9551 , n9552 , n9553 , n9554 , n9555 , n9556 , n9557 , n9558 , n9559 , n9560 ,
n9561 , n9562 , n9563 , n9564 , n9565 , n9566 , n9567 , n9568 , n9569 , n9570 ,
n9571 , n9572 , n9573 , n9574 , n9575 , n9576 , n9577 , n9578 , n9579 , n9580 ,
n9581 , n9582 , n9583 , n9584 , n9585 , n9586 , n9587 , n9588 , n9589 , n9590 ,
n9591 , n9592 , n9593 , n9594 , n9595 , n9596 , n9597 , n9598 , n9599 , n9600 ,
n9601 , n9602 , n9603 , n9604 , n9605 , n9606 , n9607 , n9608 , n9609 , n9610 ,
n9611 , n9612 , n9613 , n9614 , n9615 , n9616 , n9617 , n9618 , n9619 , n9620 ,
n9621 , n9622 , n9623 , n9624 , n9625 , n9626 , n9627 , n9628 , n9629 , n9630 ,
n9631 , n9632 , n9633 , n9634 , n9635 , n9636 , n9637 , n9638 , n9639 , n9640 ,
n9641 , n9642 , n9643 , n9644 , n9645 , n9646 , n9647 , n9648 , n9649 , n9650 ,
n9651 , n9652 , n9653 , n9654 , n9655 , n9656 , n9657 , n9658 , n9659 , n9660 ,
n9661 , n9662 , n9663 , n9664 , n9665 , n9666 , n9667 , n9668 , n9669 , n9670 ,
n9671 , n9672 , n9673 , n9674 , n9675 , n9676 , n9677 , n9678 , n9679 , n9680 ,
n9681 , n9682 , n9683 , n9684 , n9685 , n9686 , n9687 , n9688 , n9689 , n9690 ,
n9691 , n9692 , n9693 , n9694 , n9695 , n9696 , n9697 , n9698 , n9699 , n9700 ,
n9701 , n9702 , n9703 , n9704 , n9705 , n9706 , n9707 , n9708 , n9709 , n9710 ,
n9711 , n9712 , n9713 , n9714 , n9715 , n9716 , n9717 , n9718 , n9719 , n9720 ,
n9721 , n9722 , n9723 , n9724 , n9725 , n9726 , n9727 , n9728 , n9729 , n9730 ,
n9731 , n9732 , n9733 , n9734 , n9735 , n9736 , n9737 , n9738 , n9739 , n9740 ,
n9741 , n9742 , n9743 , n9744 , n9745 , n9746 , n9747 , n9748 , n9749 , n9750 ,
n9751 , n9752 , n9753 , n9754 , n9755 , n9756 , n9757 , n9758 , n9759 , n9760 ,
n9761 , n9762 , n9763 , n9764 , n9765 , n9766 , n9767 , n9768 , n9769 , n9770 ,
n9771 , n9772 , n9773 , n9774 , n9775 , n9776 , n9777 , n9778 , n9779 , n9780 ,
n9781 , n9782 , n9783 , n9784 , n9785 , n9786 , n9787 , n9788 , n9789 , n9790 ,
n9791 , n9792 , n9793 , n9794 , n9795 , n9796 , n9797 , n9798 , n9799 , n9800 ,
n9801 , n9802 , n9803 , n9804 , n9805 , n9806 , n9807 , n9808 , n9809 , n9810 ,
n9811 , n9812 , n9813 , n9814 , n9815 , n9816 , n9817 , n9818 , n9819 , n9820 ,
n9821 , n9822 , n9823 , n9824 , n9825 , n9826 , n9827 , n9828 , n9829 , n9830 ,
n9831 , n9832 , n9833 , n9834 , n9835 , n9836 , n9837 , n9838 , n9839 , n9840 ,
n9841 , n9842 , n9843 , n9844 , n9845 , n9846 , n9847 , n9848 , n9849 , n9850 ,
n9851 , n9852 , n9853 , n9854 , n9855 , n9856 , n9857 , n9858 , n9859 , n9860 ,
n9861 , n9862 , n9863 , n9864 , n9865 , n9866 , n9867 , n9868 , n9869 , n9870 ,
n9871 , n9872 , n9873 , n9874 , n9875 , n9876 , n9877 , n9878 , n9879 , n9880 ,
n9881 , n9882 , n9883 , n9884 , n9885 , n9886 , n9887 , n9888 , n9889 , n9890 ,
n9891 , n9892 , n9893 , n9894 , n9895 , n9896 , n9897 , n9898 , n9899 , n9900 ,
n9901 , n9902 , n9903 , n9904 , n9905 , n9906 , n9907 , n9908 , n9909 , n9910 ,
n9911 , n9912 , n9913 , n9914 , n9915 , n9916 , n9917 , n9918 , n9919 , n9920 ,
n9921 , n9922 , n9923 , n9924 , n9925 , n9926 , n9927 , n9928 , n9929 , n9930 ,
n9931 , n9932 , n9933 , n9934 , n9935 , n9936 , n9937 , n9938 , n9939 , n9940 ,
n9941 , n9942 , n9943 , n9944 , n9945 , n9946 , n9947 , n9948 , n9949 , n9950 ,
n9951 , n9952 , n9953 , n9954 , n9955 , n9956 , n9957 , n9958 , n9959 , n9960 ,
n9961 , n9962 , n9963 , n9964 , n9965 , n9966 , n9967 , n9968 , n9969 , n9970 ,
n9971 , n9972 , n9973 , n9974 , n9975 , n9976 , n9977 , n9978 , n9979 , n9980 ,
n9981 , n9982 , n9983 , n9984 , n9985 , n9986 , n9987 , n9988 , n9989 , n9990 ,
n9991 , n9992 , n9993 , n9994 , n9995 , n9996 , n9997 , n9998 , n9999 , n10000 ,
n10001 , n10002 , n10003 , n10004 , n10005 , n10006 , n10007 , n10008 , n10009 , n10010 ,
n10011 , n10012 , n10013 , n10014 , n10015 , n10016 , n10017 , n10018 , n10019 , n10020 ,
n10021 , n10022 , n10023 , n10024 , n10025 , n10026 , n10027 , n10028 , n10029 , n10030 ,
n10031 , n10032 , n10033 , n10034 , n10035 , n10036 , n10037 , n10038 , n10039 , n10040 ,
n10041 , n10042 , n10043 , n10044 , n10045 , n10046 , n10047 , n10048 , n10049 , n10050 ,
n10051 , n10052 , n10053 , n10054 , n10055 , n10056 , n10057 , n10058 , n10059 , n10060 ,
n10061 , n10062 , n10063 , n10064 , n10065 , n10066 , n10067 , n10068 , n10069 , n10070 ,
n10071 , n10072 , n10073 , n10074 , n10075 , n10076 , n10077 , n10078 , n10079 , n10080 ,
n10081 , n10082 , n10083 , n10084 , n10085 , n10086 , n10087 , n10088 , n10089 , n10090 ,
n10091 , n10092 , n10093 , n10094 , n10095 , n10096 , n10097 , n10098 , n10099 , n10100 ,
n10101 , n10102 , n10103 , n10104 , n10105 , n10106 , n10107 , n10108 , n10109 , n10110 ,
n10111 , n10112 , n10113 , n10114 , n10115 , n10116 , n10117 , n10118 , n10119 , n10120 ,
n10121 , n10122 , n10123 , n10124 , n10125 , n10126 , n10127 , n10128 , n10129 , n10130 ,
n10131 , n10132 , n10133 , n10134 , n10135 , n10136 , n10137 , n10138 , n10139 , n10140 ,
n10141 , n10142 , n10143 , n10144 , n10145 , n10146 , n10147 , n10148 , n10149 , n10150 ,
n10151 , n10152 , n10153 , n10154 , n10155 , n10156 , n10157 , n10158 , n10159 , n10160 ,
n10161 , n10162 , n10163 , n10164 , n10165 , n10166 , n10167 , n10168 , n10169 , n10170 ,
n10171 , n10172 , n10173 , n10174 , n10175 , n10176 , n10177 , n10178 , n10179 , n10180 ,
n10181 , n10182 , n10183 , n10184 , n10185 , n10186 , n10187 , n10188 , n10189 , n10190 ,
n10191 , n10192 , n10193 , n10194 , n10195 , n10196 , n10197 , n10198 , n10199 , n10200 ,
n10201 , n10202 , n10203 , n10204 , n10205 , n10206 , n10207 , n10208 , n10209 , n10210 ,
n10211 , n10212 , n10213 , n10214 , n10215 , n10216 , n10217 , n10218 , n10219 , n10220 ,
n10221 , n10222 , n10223 , n10224 , n10225 , n10226 , n10227 , n10228 , n10229 , n10230 ,
n10231 , n10232 , n10233 , n10234 , n10235 , n10236 , n10237 , n10238 , n10239 , n10240 ,
n10241 , n10242 , n10243 , n10244 , n10245 , n10246 , n10247 , n10248 , n10249 , n10250 ,
n10251 , n10252 , n10253 , n10254 , n10255 , n10256 , n10257 , n10258 , n10259 , n10260 ,
n10261 , n10262 , n10263 , n10264 , n10265 , n10266 , n10267 , n10268 , n10269 , n10270 ,
n10271 , n10272 , n10273 , n10274 , n10275 , n10276 , n10277 , n10278 , n10279 , n10280 ,
n10281 , n10282 , n10283 , n10284 , n10285 , n10286 , n10287 , n10288 , n10289 , n10290 ,
n10291 , n10292 , n10293 , n10294 , n10295 , n10296 , n10297 , n10298 , n10299 , n10300 ,
n10301 , n10302 , n10303 , n10304 , n10305 , n10306 , n10307 , n10308 , n10309 , n10310 ,
n10311 , n10312 , n10313 , n10314 , n10315 , n10316 , n10317 , n10318 , n10319 , n10320 ,
n10321 , n10322 , n10323 , n10324 , n10325 , n10326 , n10327 , n10328 , n10329 , n10330 ,
n10331 , n10332 , n10333 , n10334 , n10335 , n10336 , n10337 , n10338 , n10339 , n10340 ,
n10341 , n10342 , n10343 , n10344 , n10345 , n10346 , n10347 , n10348 , n10349 , n10350 ,
n10351 , n10352 , n10353 , n10354 , n10355 , n10356 , n10357 , n10358 , n10359 , n10360 ,
n10361 , n10362 , n10363 , n10364 , n10365 , n10366 , n10367 , n10368 , n10369 , n10370 ,
n10371 , n10372 , n10373 , n10374 , n10375 , n10376 , n10377 , n10378 , n10379 , n10380 ,
n10381 , n10382 , n10383 , n10384 , n10385 , n10386 , n10387 , n10388 , n10389 , n10390 ,
n10391 , n10392 , n10393 , n10394 , n10395 , n10396 , n10397 , n10398 , n10399 , n10400 ,
n10401 , n10402 , n10403 , n10404 , n10405 , n10406 , n10407 , n10408 , n10409 , n10410 ,
n10411 , n10412 , n10413 , n10414 , n10415 , n10416 , n10417 , n10418 , n10419 , n10420 ,
n10421 , n10422 , n10423 , n10424 , n10425 , n10426 , n10427 , n10428 , n10429 , n10430 ,
n10431 , n10432 , n10433 , n10434 , n10435 , n10436 , n10437 , n10438 , n10439 , n10440 ,
n10441 , n10442 , n10443 , n10444 , n10445 , n10446 , n10447 , n10448 , n10449 , n10450 ,
n10451 , n10452 , n10453 , n10454 , n10455 , n10456 , n10457 , n10458 , n10459 , n10460 ,
n10461 , n10462 , n10463 , n10464 , n10465 , n10466 , n10467 , n10468 , n10469 , n10470 ,
n10471 , n10472 , n10473 , n10474 , n10475 , n10476 , n10477 , n10478 , n10479 , n10480 ,
n10481 , n10482 , n10483 , n10484 , n10485 , n10486 , n10487 , n10488 , n10489 , n10490 ,
n10491 , n10492 , n10493 , n10494 , n10495 , n10496 , n10497 , n10498 , n10499 , n10500 ,
n10501 , n10502 , n10503 , n10504 , n10505 , n10506 , n10507 , n10508 , n10509 , n10510 ,
n10511 , n10512 , n10513 , n10514 , n10515 , n10516 , n10517 , n10518 , n10519 , n10520 ,
n10521 , n10522 , n10523 , n10524 , n10525 , n10526 , n10527 , n10528 , n10529 , n10530 ,
n10531 , n10532 , n10533 , n10534 , n10535 , n10536 , n10537 , n10538 , n10539 , n10540 ,
n10541 , n10542 , n10543 , n10544 , n10545 , n10546 , n10547 , n10548 , n10549 , n10550 ,
n10551 , n10552 , n10553 , n10554 , n10555 , n10556 , n10557 , n10558 , n10559 , n10560 ,
n10561 , n10562 , n10563 , n10564 , n10565 , n10566 , n10567 , n10568 , n10569 , n10570 ,
n10571 , n10572 , n10573 , n10574 , n10575 , n10576 , n10577 , n10578 , n10579 , n10580 ,
n10581 , n10582 , n10583 , n10584 , n10585 , n10586 , n10587 , n10588 , n10589 , n10590 ,
n10591 , n10592 , n10593 , n10594 , n10595 , n10596 , n10597 , n10598 , n10599 , n10600 ,
n10601 , n10602 , n10603 , n10604 , n10605 , n10606 , n10607 , n10608 , n10609 , n10610 ,
n10611 , n10612 , n10613 , n10614 , n10615 , n10616 , n10617 , n10618 , n10619 , n10620 ,
n10621 , n10622 , n10623 , n10624 , n10625 , n10626 , n10627 , n10628 , n10629 , n10630 ,
n10631 , n10632 , n10633 , n10634 , n10635 , n10636 , n10637 , n10638 , n10639 , n10640 ,
n10641 , n10642 , n10643 , n10644 , n10645 , n10646 , n10647 , n10648 , n10649 , n10650 ,
n10651 , n10652 , n10653 , n10654 , n10655 , n10656 , n10657 , n10658 , n10659 , n10660 ,
n10661 , n10662 , n10663 , n10664 , n10665 , n10666 , n10667 , n10668 , n10669 , n10670 ,
n10671 , n10672 , n10673 , n10674 , n10675 , n10676 , n10677 , n10678 , n10679 , n10680 ,
n10681 , n10682 , n10683 , n10684 , n10685 , n10686 , n10687 , n10688 , n10689 , n10690 ,
n10691 , n10692 , n10693 , n10694 , n10695 , n10696 , n10697 , n10698 , n10699 , n10700 ,
n10701 , n10702 , n10703 , n10704 , n10705 , n10706 , n10707 , n10708 , n10709 , n10710 ,
n10711 , n10712 , n10713 , n10714 , n10715 , n10716 , n10717 , n10718 , n10719 , n10720 ,
n10721 , n10722 , n10723 , n10724 , n10725 , n10726 , n10727 , n10728 , n10729 , n10730 ,
n10731 , n10732 , n10733 , n10734 , n10735 , n10736 , n10737 , n10738 , n10739 , n10740 ,
n10741 , n10742 , n10743 , n10744 , n10745 , n10746 , n10747 , n10748 , n10749 , n10750 ,
n10751 , n10752 , n10753 , n10754 , n10755 , n10756 , n10757 , n10758 , n10759 , n10760 ,
n10761 , n10762 , n10763 , n10764 , n10765 , n10766 , n10767 , n10768 , n10769 , n10770 ,
n10771 , n10772 , n10773 , n10774 , n10775 , n10776 , n10777 , n10778 , n10779 , n10780 ,
n10781 , n10782 , n10783 , n10784 , n10785 , n10786 , n10787 , n10788 , n10789 , n10790 ,
n10791 , n10792 , n10793 , n10794 , n10795 , n10796 , n10797 , n10798 , n10799 , n10800 ,
n10801 , n10802 , n10803 , n10804 , n10805 , n10806 , n10807 , n10808 , n10809 , n10810 ,
n10811 , n10812 , n10813 , n10814 , n10815 , n10816 , n10817 , n10818 , n10819 , n10820 ,
n10821 , n10822 , n10823 , n10824 , n10825 , n10826 , n10827 , n10828 , n10829 , n10830 ,
n10831 , n10832 , n10833 , n10834 , n10835 , n10836 , n10837 , n10838 , n10839 , n10840 ,
n10841 , n10842 , n10843 , n10844 , n10845 , n10846 , n10847 , n10848 , n10849 , n10850 ,
n10851 , n10852 , n10853 , n10854 , n10855 , n10856 , n10857 , n10858 , n10859 , n10860 ,
n10861 , n10862 , n10863 , n10864 , n10865 , n10866 , n10867 , n10868 , n10869 , n10870 ,
n10871 , n10872 , n10873 , n10874 , n10875 , n10876 , n10877 , n10878 , n10879 , n10880 ,
n10881 , n10882 , n10883 , n10884 , n10885 , n10886 , n10887 , n10888 , n10889 , n10890 ,
n10891 , n10892 , n10893 , n10894 , n10895 , n10896 , n10897 , n10898 , n10899 , n10900 ,
n10901 , n10902 , n10903 , n10904 , n10905 , n10906 , n10907 , n10908 , n10909 , n10910 ,
n10911 , n10912 , n10913 , n10914 , n10915 , n10916 , n10917 , n10918 , n10919 , n10920 ,
n10921 , n10922 , n10923 , n10924 , n10925 , n10926 , n10927 , n10928 , n10929 , n10930 ,
n10931 , n10932 , n10933 , n10934 , n10935 , n10936 , n10937 , n10938 , n10939 , n10940 ,
n10941 , n10942 , n10943 , n10944 , n10945 , n10946 , n10947 , n10948 , n10949 , n10950 ,
n10951 , n10952 , n10953 , n10954 , n10955 , n10956 , n10957 , n10958 , n10959 , n10960 ,
n10961 , n10962 , n10963 , n10964 , n10965 , n10966 , n10967 , n10968 , n10969 , n10970 ,
n10971 , n10972 , n10973 , n10974 , n10975 , n10976 , n10977 , n10978 , n10979 , n10980 ,
n10981 , n10982 , n10983 , n10984 , n10985 , n10986 , n10987 , n10988 , n10989 , n10990 ,
n10991 , n10992 , n10993 , n10994 , n10995 , n10996 , n10997 , n10998 , n10999 , n11000 ,
n11001 , n11002 , n11003 , n11004 , n11005 , n11006 , n11007 , n11008 , n11009 , n11010 ,
n11011 , n11012 , n11013 , n11014 , n11015 , n11016 , n11017 , n11018 , n11019 , n11020 ,
n11021 , n11022 , n11023 , n11024 , n11025 , n11026 , n11027 , n11028 , n11029 , n11030 ,
n11031 , n11032 , n11033 , n11034 , n11035 , n11036 , n11037 , n11038 , n11039 , n11040 ,
n11041 , n11042 , n11043 , n11044 , n11045 , n11046 , n11047 , n11048 , n11049 , n11050 ,
n11051 , n11052 , n11053 , n11054 , n11055 , n11056 , n11057 , n11058 , n11059 , n11060 ,
n11061 , n11062 , n11063 , n11064 , n11065 , n11066 , n11067 , n11068 , n11069 , n11070 ,
n11071 , n11072 , n11073 , n11074 , n11075 , n11076 , n11077 , n11078 , n11079 , n11080 ,
n11081 , n11082 , n11083 , n11084 , n11085 , n11086 , n11087 , n11088 , n11089 , n11090 ,
n11091 , n11092 , n11093 , n11094 , n11095 , n11096 , n11097 , n11098 , n11099 , n11100 ,
n11101 , n11102 , n11103 , n11104 , n11105 , n11106 , n11107 , n11108 , n11109 , n11110 ,
n11111 , n11112 , n11113 , n11114 , n11115 , n11116 , n11117 , n11118 , n11119 , n11120 ,
n11121 , n11122 , n11123 , n11124 , n11125 , n11126 , n11127 , n11128 , n11129 , n11130 ,
n11131 , n11132 , n11133 , n11134 , n11135 , n11136 , n11137 , n11138 , n11139 , n11140 ,
n11141 , n11142 , n11143 , n11144 , n11145 , n11146 , n11147 , n11148 , n11149 , n11150 ,
n11151 , n11152 , n11153 , n11154 , n11155 , n11156 , n11157 , n11158 , n11159 , n11160 ,
n11161 , n11162 , n11163 , n11164 , n11165 , n11166 , n11167 , n11168 , n11169 , n11170 ,
n11171 , n11172 , n11173 , n11174 , n11175 , n11176 , n11177 , n11178 , n11179 , n11180 ,
n11181 , n11182 , n11183 , n11184 , n11185 , n11186 , n11187 , n11188 , n11189 , n11190 ,
n11191 , n11192 , n11193 , n11194 , n11195 , n11196 , n11197 , n11198 , n11199 , n11200 ,
n11201 , n11202 , n11203 , n11204 , n11205 , n11206 , n11207 , n11208 , n11209 , n11210 ,
n11211 , n11212 , n11213 , n11214 , n11215 , n11216 , n11217 , n11218 , n11219 , n11220 ,
n11221 , n11222 , n11223 , n11224 , n11225 , n11226 , n11227 , n11228 , n11229 , n11230 ,
n11231 , n11232 , n11233 , n11234 , n11235 , n11236 , n11237 , n11238 , n11239 , n11240 ,
n11241 , n11242 , n11243 , n11244 , n11245 , n11246 , n11247 , n11248 , n11249 , n11250 ,
n11251 , n11252 , n11253 , n11254 , n11255 , n11256 , n11257 , n11258 , n11259 , n11260 ,
n11261 , n11262 , n11263 , n11264 , n11265 , n11266 , n11267 , n11268 , n11269 , n11270 ,
n11271 , n11272 , n11273 , n11274 , n11275 , n11276 , n11277 , n11278 , n11279 , n11280 ,
n11281 , n11282 , n11283 , n11284 , n11285 , n11286 , n11287 , n11288 , n11289 , n11290 ,
n11291 , n11292 , n11293 , n11294 , n11295 , n11296 , n11297 , n11298 , n11299 , n11300 ,
n11301 , n11302 , n11303 , n11304 , n11305 , n11306 , n11307 , n11308 , n11309 , n11310 ,
n11311 , n11312 , n11313 , n11314 , n11315 , n11316 , n11317 , n11318 , n11319 , n11320 ,
n11321 , n11322 , n11323 , n11324 , n11325 , n11326 , n11327 , n11328 , n11329 , n11330 ,
n11331 , n11332 , n11333 , n11334 , n11335 , n11336 , n11337 , n11338 , n11339 , n11340 ,
n11341 , n11342 , n11343 , n11344 , n11345 , n11346 , n11347 , n11348 , n11349 , n11350 ,
n11351 , n11352 , n11353 , n11354 , n11355 , n11356 , n11357 , n11358 , n11359 , n11360 ,
n11361 , n11362 , n11363 , n11364 , n11365 , n11366 , n11367 , n11368 , n11369 , n11370 ,
n11371 , n11372 , n11373 , n11374 , n11375 , n11376 , n11377 , n11378 , n11379 , n11380 ,
n11381 , n11382 , n11383 , n11384 , n11385 , n11386 , n11387 , n11388 , n11389 , n11390 ,
n11391 , n11392 , n11393 , n11394 , n11395 , n11396 , n11397 , n11398 , n11399 , n11400 ,
n11401 , n11402 , n11403 , n11404 , n11405 , n11406 , n11407 , n11408 , n11409 , n11410 ,
n11411 , n11412 , n11413 , n11414 , n11415 , n11416 , n11417 , n11418 , n11419 , n11420 ,
n11421 , n11422 , n11423 , n11424 , n11425 , n11426 , n11427 , n11428 , n11429 , n11430 ,
n11431 , n11432 , n11433 , n11434 , n11435 , n11436 , n11437 , n11438 , n11439 , n11440 ,
n11441 , n11442 , n11443 , n11444 , n11445 , n11446 , n11447 , n11448 , n11449 , n11450 ,
n11451 , n11452 , n11453 , n11454 , n11455 , n11456 , n11457 , n11458 , n11459 , n11460 ,
n11461 , n11462 , n11463 , n11464 , n11465 , n11466 , n11467 , n11468 , n11469 , n11470 ,
n11471 , n11472 , n11473 , n11474 , n11475 , n11476 , n11477 , n11478 , n11479 , n11480 ,
n11481 , n11482 , n11483 , n11484 , n11485 , n11486 , n11487 , n11488 , n11489 , n11490 ,
n11491 , n11492 , n11493 , n11494 , n11495 , n11496 , n11497 , n11498 , n11499 , n11500 ,
n11501 , n11502 , n11503 , n11504 , n11505 , n11506 , n11507 , n11508 , n11509 , n11510 ,
n11511 , n11512 , n11513 , n11514 , n11515 , n11516 , n11517 , n11518 , n11519 , n11520 ,
n11521 , n11522 , n11523 , n11524 , n11525 , n11526 , n11527 , n11528 , n11529 , n11530 ,
n11531 , n11532 , n11533 , n11534 , n11535 , n11536 , n11537 , n11538 , n11539 , n11540 ,
n11541 , n11542 , n11543 , n11544 , n11545 , n11546 , n11547 , n11548 , n11549 , n11550 ,
n11551 , n11552 , n11553 , n11554 , n11555 , n11556 , n11557 , n11558 , n11559 , n11560 ,
n11561 , n11562 , n11563 , n11564 , n11565 , n11566 , n11567 , n11568 , n11569 , n11570 ,
n11571 , n11572 , n11573 , n11574 , n11575 , n11576 , n11577 , n11578 , n11579 , n11580 ,
n11581 , n11582 , n11583 , n11584 , n11585 , n11586 , n11587 , n11588 , n11589 , n11590 ,
n11591 , n11592 , n11593 , n11594 , n11595 , n11596 , n11597 , n11598 , n11599 , n11600 ,
n11601 , n11602 , n11603 , n11604 , n11605 , n11606 , n11607 , n11608 , n11609 , n11610 ,
n11611 , n11612 , n11613 , n11614 , n11615 , n11616 , n11617 , n11618 , n11619 , n11620 ,
n11621 , n11622 , n11623 , n11624 , n11625 , n11626 , n11627 , n11628 , n11629 , n11630 ,
n11631 , n11632 , n11633 , n11634 , n11635 , n11636 , n11637 , n11638 , n11639 , n11640 ,
n11641 , n11642 , n11643 , n11644 , n11645 , n11646 , n11647 , n11648 , n11649 , n11650 ,
n11651 , n11652 , n11653 , n11654 , n11655 , n11656 , n11657 , n11658 , n11659 , n11660 ,
n11661 , n11662 , n11663 , n11664 , n11665 , n11666 , n11667 , n11668 , n11669 , n11670 ,
n11671 , n11672 , n11673 , n11674 , n11675 , n11676 , n11677 , n11678 , n11679 , n11680 ,
n11681 , n11682 , n11683 , n11684 , n11685 , n11686 , n11687 , n11688 , n11689 , n11690 ,
n11691 , n11692 , n11693 , n11694 , n11695 , n11696 , n11697 , n11698 , n11699 , n11700 ,
n11701 , n11702 , n11703 , n11704 , n11705 , n11706 , n11707 , n11708 , n11709 , n11710 ,
n11711 , n11712 , n11713 , n11714 , n11715 , n11716 , n11717 , n11718 , n11719 , n11720 ,
n11721 , n11722 , n11723 , n11724 , n11725 , n11726 , n11727 , n11728 , n11729 , n11730 ,
n11731 , n11732 , n11733 , n11734 , n11735 , n11736 , n11737 , n11738 , n11739 , n11740 ,
n11741 , n11742 , n11743 , n11744 , n11745 , n11746 , n11747 , n11748 , n11749 , n11750 ,
n11751 , n11752 , n11753 , n11754 , n11755 , n11756 , n11757 , n11758 , n11759 , n11760 ,
n11761 , n11762 , n11763 , n11764 , n11765 , n11766 , n11767 , n11768 , n11769 , n11770 ,
n11771 , n11772 , n11773 , n11774 , n11775 , n11776 , n11777 , n11778 , n11779 , n11780 ,
n11781 , n11782 , n11783 , n11784 , n11785 , n11786 , n11787 , n11788 , n11789 , n11790 ,
n11791 , n11792 , n11793 , n11794 , n11795 , n11796 , n11797 , n11798 , n11799 , n11800 ,
n11801 , n11802 , n11803 , n11804 , n11805 , n11806 , n11807 , n11808 , n11809 , n11810 ,
n11811 , n11812 , n11813 , n11814 , n11815 , n11816 , n11817 , n11818 , n11819 , n11820 ,
n11821 , n11822 , n11823 , n11824 , n11825 , n11826 , n11827 , n11828 , n11829 , n11830 ,
n11831 , n11832 , n11833 , n11834 , n11835 , n11836 , n11837 , n11838 , n11839 , n11840 ,
n11841 , n11842 , n11843 , n11844 , n11845 , n11846 , n11847 , n11848 , n11849 , n11850 ,
n11851 , n11852 , n11853 , n11854 , n11855 , n11856 , n11857 , n11858 , n11859 , n11860 ,
n11861 , n11862 , n11863 , n11864 , n11865 , n11866 , n11867 , n11868 , n11869 , n11870 ,
n11871 , n11872 , n11873 , n11874 , n11875 , n11876 , n11877 , n11878 , n11879 , n11880 ,
n11881 , n11882 , n11883 , n11884 , n11885 , n11886 , n11887 , n11888 , n11889 , n11890 ,
n11891 , n11892 , n11893 , n11894 , n11895 , n11896 , n11897 , n11898 , n11899 , n11900 ,
n11901 , n11902 , n11903 , n11904 , n11905 , n11906 , n11907 , n11908 , n11909 , n11910 ,
n11911 , n11912 , n11913 , n11914 , n11915 , n11916 , n11917 , n11918 , n11919 , n11920 ,
n11921 , n11922 , n11923 , n11924 , n11925 , n11926 , n11927 , n11928 , n11929 , n11930 ,
n11931 , n11932 , n11933 , n11934 , n11935 , n11936 , n11937 , n11938 , n11939 , n11940 ,
n11941 , n11942 , n11943 , n11944 , n11945 , n11946 , n11947 , n11948 , n11949 , n11950 ,
n11951 , n11952 , n11953 , n11954 , n11955 , n11956 , n11957 , n11958 , n11959 , n11960 ,
n11961 , n11962 , n11963 , n11964 , n11965 , n11966 , n11967 , n11968 , n11969 , n11970 ,
n11971 , n11972 , n11973 , n11974 , n11975 , n11976 , n11977 , n11978 , n11979 , n11980 ,
n11981 , n11982 , n11983 , n11984 , n11985 , n11986 , n11987 , n11988 , n11989 , n11990 ,
n11991 , n11992 , n11993 , n11994 , n11995 , n11996 , n11997 , n11998 , n11999 , n12000 ,
n12001 , n12002 , n12003 , n12004 , n12005 , n12006 , n12007 , n12008 , n12009 , n12010 ,
n12011 , n12012 , n12013 , n12014 , n12015 , n12016 , n12017 , n12018 , n12019 , n12020 ,
n12021 , n12022 , n12023 , n12024 , n12025 , n12026 , n12027 , n12028 , n12029 , n12030 ,
n12031 , n12032 , n12033 , n12034 , n12035 , n12036 , n12037 , n12038 , n12039 , n12040 ,
n12041 , n12042 , n12043 , n12044 , n12045 , n12046 , n12047 , n12048 , n12049 , n12050 ,
n12051 , n12052 , n12053 , n12054 , n12055 , n12056 , n12057 , n12058 , n12059 , n12060 ,
n12061 , n12062 , n12063 , n12064 , n12065 , n12066 , n12067 , n12068 , n12069 , n12070 ,
n12071 , n12072 , n12073 , n12074 , n12075 , n12076 , n12077 , n12078 , n12079 , n12080 ,
n12081 , n12082 , n12083 , n12084 , n12085 , n12086 , n12087 , n12088 , n12089 , n12090 ,
n12091 , n12092 , n12093 , n12094 , n12095 , n12096 , n12097 , n12098 , n12099 , n12100 ,
n12101 , n12102 , n12103 , n12104 , n12105 , n12106 , n12107 , n12108 , n12109 , n12110 ,
n12111 , n12112 , n12113 , n12114 , n12115 , n12116 , n12117 , n12118 , n12119 , n12120 ,
n12121 , n12122 , n12123 , n12124 , n12125 , n12126 , n12127 , n12128 , n12129 , n12130 ,
n12131 , n12132 , n12133 , n12134 , n12135 , n12136 , n12137 , n12138 , n12139 , n12140 ,
n12141 , n12142 , n12143 , n12144 , n12145 , n12146 , n12147 , n12148 , n12149 , n12150 ,
n12151 , n12152 , n12153 , n12154 , n12155 , n12156 , n12157 , n12158 , n12159 , n12160 ,
n12161 , n12162 , n12163 , n12164 , n12165 , n12166 , n12167 , n12168 , n12169 , n12170 ,
n12171 , n12172 , n12173 , n12174 , n12175 , n12176 , n12177 , n12178 , n12179 , n12180 ,
n12181 , n12182 , n12183 , n12184 , n12185 , n12186 , n12187 , n12188 , n12189 , n12190 ,
n12191 , n12192 , n12193 , n12194 , n12195 , n12196 , n12197 , n12198 , n12199 , n12200 ,
n12201 , n12202 , n12203 , n12204 , n12205 , n12206 , n12207 , n12208 , n12209 , n12210 ,
n12211 , n12212 , n12213 , n12214 , n12215 , n12216 , n12217 , n12218 , n12219 , n12220 ,
n12221 , n12222 , n12223 , n12224 , n12225 , n12226 , n12227 , n12228 , n12229 , n12230 ,
n12231 , n12232 , n12233 , n12234 , n12235 , n12236 , n12237 , n12238 , n12239 , n12240 ,
n12241 , n12242 , n12243 , n12244 , n12245 , n12246 , n12247 , n12248 , n12249 , n12250 ,
n12251 , n12252 , n12253 , n12254 , n12255 , n12256 , n12257 , n12258 , n12259 , n12260 ,
n12261 , n12262 , n12263 , n12264 , n12265 , n12266 , n12267 , n12268 , n12269 , n12270 ,
n12271 , n12272 , n12273 , n12274 , n12275 , n12276 , n12277 , n12278 , n12279 , n12280 ,
n12281 , n12282 , n12283 , n12284 , n12285 , n12286 , n12287 , n12288 , n12289 , n12290 ,
n12291 , n12292 , n12293 , n12294 , n12295 , n12296 , n12297 , n12298 , n12299 , n12300 ,
n12301 , n12302 , n12303 , n12304 , n12305 , n12306 , n12307 , n12308 , n12309 , n12310 ,
n12311 , n12312 , n12313 , n12314 , n12315 , n12316 , n12317 , n12318 , n12319 , n12320 ,
n12321 , n12322 , n12323 , n12324 , n12325 , n12326 , n12327 , n12328 , n12329 , n12330 ,
n12331 , n12332 , n12333 , n12334 , n12335 , n12336 , n12337 , n12338 , n12339 , n12340 ,
n12341 , n12342 , n12343 , n12344 , n12345 , n12346 , n12347 , n12348 , n12349 , n12350 ,
n12351 , n12352 , n12353 , n12354 , n12355 , n12356 , n12357 , n12358 , n12359 , n12360 ,
n12361 , n12362 , n12363 , n12364 , n12365 , n12366 , n12367 , n12368 , n12369 , n12370 ,
n12371 , n12372 , n12373 , n12374 , n12375 , n12376 , n12377 , n12378 , n12379 , n12380 ,
n12381 , n12382 , n12383 , n12384 , n12385 , n12386 , n12387 , n12388 , n12389 , n12390 ,
n12391 , n12392 , n12393 , n12394 , n12395 , n12396 , n12397 , n12398 , n12399 , n12400 ,
n12401 , n12402 , n12403 , n12404 , n12405 , n12406 , n12407 , n12408 , n12409 , n12410 ,
n12411 , n12412 , n12413 , n12414 , n12415 , n12416 , n12417 , n12418 , n12419 , n12420 ,
n12421 , n12422 , n12423 , n12424 , n12425 , n12426 , n12427 , n12428 , n12429 , n12430 ,
n12431 , n12432 , n12433 , n12434 , n12435 , n12436 , n12437 , n12438 , n12439 , n12440 ,
n12441 , n12442 , n12443 , n12444 , n12445 , n12446 , n12447 , n12448 , n12449 , n12450 ,
n12451 , n12452 , n12453 , n12454 , n12455 , n12456 , n12457 , n12458 , n12459 , n12460 ,
n12461 , n12462 , n12463 , n12464 , n12465 , n12466 , n12467 , n12468 , n12469 , n12470 ,
n12471 , n12472 , n12473 , n12474 , n12475 , n12476 , n12477 , n12478 , n12479 , n12480 ,
n12481 , n12482 , n12483 , n12484 , n12485 , n12486 , n12487 , n12488 , n12489 , n12490 ,
n12491 , n12492 , n12493 , n12494 , n12495 , n12496 , n12497 , n12498 , n12499 , n12500 ,
n12501 , n12502 , n12503 , n12504 , n12505 , n12506 , n12507 , n12508 , n12509 , n12510 ,
n12511 , n12512 , n12513 , n12514 , n12515 , n12516 , n12517 , n12518 , n12519 , n12520 ,
n12521 , n12522 , n12523 , n12524 , n12525 , n12526 , n12527 , n12528 , n12529 , n12530 ,
n12531 , n12532 , n12533 , n12534 , n12535 , n12536 , n12537 , n12538 , n12539 , n12540 ,
n12541 , n12542 , n12543 , n12544 , n12545 , n12546 , n12547 , n12548 , n12549 , n12550 ,
n12551 , n12552 , n12553 , n12554 , n12555 , n12556 , n12557 , n12558 , n12559 , n12560 ,
n12561 , n12562 , n12563 , n12564 , n12565 , n12566 , n12567 , n12568 , n12569 , n12570 ,
n12571 , n12572 , n12573 , n12574 , n12575 , n12576 , n12577 , n12578 , n12579 , n12580 ,
n12581 , n12582 , n12583 , n12584 , n12585 , n12586 , n12587 , n12588 , n12589 , n12590 ,
n12591 , n12592 , n12593 , n12594 , n12595 , n12596 , n12597 , n12598 , n12599 , n12600 ,
n12601 , n12602 , n12603 , n12604 , n12605 , n12606 , n12607 , n12608 , n12609 , n12610 ,
n12611 , n12612 , n12613 , n12614 , n12615 , n12616 , n12617 , n12618 , n12619 , n12620 ,
n12621 , n12622 , n12623 , n12624 , n12625 , n12626 , n12627 , n12628 , n12629 , n12630 ,
n12631 , n12632 , n12633 , n12634 , n12635 , n12636 , n12637 , n12638 , n12639 , n12640 ,
n12641 , n12642 , n12643 , n12644 , n12645 , n12646 , n12647 , n12648 , n12649 , n12650 ,
n12651 , n12652 , n12653 , n12654 , n12655 , n12656 , n12657 , n12658 , n12659 , n12660 ,
n12661 , n12662 , n12663 , n12664 , n12665 , n12666 , n12667 , n12668 , n12669 , n12670 ,
n12671 , n12672 , n12673 , n12674 , n12675 , n12676 , n12677 , n12678 , n12679 , n12680 ,
n12681 , n12682 , n12683 , n12684 , n12685 , n12686 , n12687 , n12688 , n12689 , n12690 ,
n12691 , n12692 , n12693 , n12694 , n12695 , n12696 , n12697 , n12698 , n12699 , n12700 ,
n12701 , n12702 , n12703 , n12704 , n12705 , n12706 , n12707 , n12708 , n12709 , n12710 ,
n12711 , n12712 , n12713 , n12714 , n12715 , n12716 , n12717 , n12718 , n12719 , n12720 ,
n12721 , n12722 , n12723 , n12724 , n12725 , n12726 , n12727 , n12728 , n12729 , n12730 ,
n12731 , n12732 , n12733 , n12734 , n12735 , n12736 , n12737 , n12738 , n12739 , n12740 ,
n12741 , n12742 , n12743 , n12744 , n12745 , n12746 , n12747 , n12748 , n12749 , n12750 ,
n12751 , n12752 , n12753 , n12754 , n12755 , n12756 , n12757 , n12758 , n12759 , n12760 ,
n12761 , n12762 , n12763 , n12764 , n12765 , n12766 , n12767 , n12768 , n12769 , n12770 ,
n12771 , n12772 , n12773 , n12774 , n12775 , n12776 , n12777 , n12778 , n12779 , n12780 ,
n12781 , n12782 , n12783 , n12784 , n12785 , n12786 , n12787 , n12788 , n12789 , n12790 ,
n12791 , n12792 , n12793 , n12794 , n12795 , n12796 , n12797 , n12798 , n12799 , n12800 ,
n12801 , n12802 , n12803 , n12804 , n12805 , n12806 , n12807 , n12808 , n12809 , n12810 ,
n12811 , n12812 , n12813 , n12814 , n12815 , n12816 , n12817 , n12818 , n12819 , n12820 ,
n12821 , n12822 , n12823 , n12824 , n12825 , n12826 , n12827 , n12828 , n12829 , n12830 ,
n12831 , n12832 , n12833 , n12834 , n12835 , n12836 , n12837 , n12838 , n12839 , n12840 ,
n12841 , n12842 , n12843 , n12844 , n12845 , n12846 , n12847 , n12848 , n12849 , n12850 ,
n12851 , n12852 , n12853 , n12854 , n12855 , n12856 , n12857 , n12858 , n12859 , n12860 ,
n12861 , n12862 , n12863 , n12864 , n12865 , n12866 , n12867 , n12868 , n12869 , n12870 ,
n12871 , n12872 , n12873 , n12874 , n12875 , n12876 , n12877 , n12878 , n12879 , n12880 ,
n12881 , n12882 , n12883 , n12884 , n12885 , n12886 , n12887 , n12888 , n12889 , n12890 ,
n12891 , n12892 , n12893 , n12894 , n12895 , n12896 , n12897 , n12898 , n12899 , n12900 ,
n12901 , n12902 , n12903 , n12904 , n12905 , n12906 , n12907 , n12908 , n12909 , n12910 ,
n12911 , n12912 , n12913 , n12914 , n12915 , n12916 , n12917 , n12918 , n12919 , n12920 ,
n12921 , n12922 , n12923 , n12924 , n12925 , n12926 , n12927 , n12928 , n12929 , n12930 ,
n12931 , n12932 , n12933 , n12934 , n12935 , n12936 , n12937 , n12938 , n12939 , n12940 ,
n12941 , n12942 , n12943 , n12944 , n12945 , n12946 , n12947 , n12948 , n12949 , n12950 ,
n12951 , n12952 , n12953 , n12954 , n12955 , n12956 , n12957 , n12958 , n12959 , n12960 ,
n12961 , n12962 , n12963 , n12964 , n12965 , n12966 , n12967 , n12968 , n12969 , n12970 ,
n12971 , n12972 , n12973 , n12974 , n12975 , n12976 , n12977 , n12978 , n12979 , n12980 ,
n12981 , n12982 , n12983 , n12984 , n12985 , n12986 , n12987 , n12988 , n12989 , n12990 ,
n12991 , n12992 , n12993 , n12994 , n12995 , n12996 , n12997 , n12998 , n12999 , n13000 ,
n13001 , n13002 , n13003 , n13004 , n13005 , n13006 , n13007 , n13008 , n13009 , n13010 ,
n13011 , n13012 , n13013 , n13014 , n13015 , n13016 , n13017 , n13018 , n13019 , n13020 ,
n13021 , n13022 , n13023 , n13024 , n13025 , n13026 , n13027 , n13028 , n13029 , n13030 ,
n13031 , n13032 , n13033 , n13034 , n13035 , n13036 , n13037 , n13038 , n13039 , n13040 ,
n13041 , n13042 , n13043 , n13044 , n13045 , n13046 , n13047 , n13048 , n13049 , n13050 ,
n13051 , n13052 , n13053 , n13054 , n13055 , n13056 , n13057 , n13058 , n13059 , n13060 ,
n13061 , n13062 , n13063 , n13064 , n13065 , n13066 , n13067 , n13068 , n13069 , n13070 ,
n13071 , n13072 , n13073 , n13074 , n13075 , n13076 , n13077 , n13078 , n13079 , n13080 ,
n13081 , n13082 , n13083 , n13084 , n13085 , n13086 , n13087 , n13088 , n13089 , n13090 ,
n13091 , n13092 , n13093 , n13094 , n13095 , n13096 , n13097 , n13098 , n13099 , n13100 ,
n13101 , n13102 , n13103 , n13104 , n13105 , n13106 , n13107 , n13108 , n13109 , n13110 ,
n13111 , n13112 , n13113 , n13114 , n13115 , n13116 , n13117 , n13118 , n13119 , n13120 ,
n13121 , n13122 , n13123 , n13124 , n13125 , n13126 , n13127 , n13128 , n13129 , n13130 ,
n13131 , n13132 , n13133 , n13134 , n13135 , n13136 , n13137 , n13138 , n13139 , n13140 ,
n13141 , n13142 , n13143 , n13144 , n13145 , n13146 , n13147 , n13148 , n13149 , n13150 ,
n13151 , n13152 , n13153 , n13154 , n13155 , n13156 , n13157 , n13158 , n13159 , n13160 ,
n13161 , n13162 , n13163 , n13164 , n13165 , n13166 , n13167 , n13168 , n13169 , n13170 ,
n13171 , n13172 , n13173 , n13174 , n13175 , n13176 , n13177 , n13178 , n13179 , n13180 ,
n13181 , n13182 , n13183 , n13184 , n13185 , n13186 , n13187 , n13188 , n13189 , n13190 ,
n13191 , n13192 , n13193 , n13194 , n13195 , n13196 , n13197 , n13198 , n13199 , n13200 ,
n13201 , n13202 , n13203 , n13204 , n13205 , n13206 , n13207 , n13208 , n13209 , n13210 ,
n13211 , n13212 , n13213 , n13214 , n13215 , n13216 , n13217 , n13218 , n13219 , n13220 ,
n13221 , n13222 , n13223 , n13224 , n13225 , n13226 , n13227 , n13228 , n13229 , n13230 ,
n13231 , n13232 , n13233 , n13234 , n13235 , n13236 , n13237 , n13238 , n13239 , n13240 ,
n13241 , n13242 , n13243 , n13244 , n13245 , n13246 , n13247 , n13248 , n13249 , n13250 ,
n13251 , n13252 , n13253 , n13254 , n13255 , n13256 , n13257 , n13258 , n13259 , n13260 ,
n13261 , n13262 , n13263 , n13264 , n13265 , n13266 , n13267 , n13268 , n13269 , n13270 ,
n13271 , n13272 , n13273 , n13274 , n13275 , n13276 , n13277 , n13278 , n13279 , n13280 ,
n13281 , n13282 , n13283 , n13284 , n13285 , n13286 , n13287 , n13288 , n13289 , n13290 ,
n13291 , n13292 , n13293 , n13294 , n13295 , n13296 , n13297 , n13298 , n13299 , n13300 ,
n13301 , n13302 , n13303 , n13304 , n13305 , n13306 , n13307 , n13308 , n13309 , n13310 ,
n13311 , n13312 , n13313 , n13314 , n13315 , n13316 , n13317 , n13318 , n13319 , n13320 ,
n13321 , n13322 , n13323 , n13324 , n13325 , n13326 , n13327 , n13328 , n13329 , n13330 ,
n13331 , n13332 , n13333 , n13334 , n13335 , n13336 , n13337 , n13338 , n13339 , n13340 ,
n13341 , n13342 , n13343 , n13344 , n13345 , n13346 , n13347 , n13348 , n13349 , n13350 ,
n13351 , n13352 , n13353 , n13354 , n13355 , n13356 , n13357 , n13358 , n13359 , n13360 ,
n13361 , n13362 , n13363 , n13364 , n13365 , n13366 , n13367 , n13368 , n13369 , n13370 ,
n13371 , n13372 , n13373 , n13374 , n13375 , n13376 , n13377 , n13378 , n13379 , n13380 ,
n13381 , n13382 , n13383 , n13384 , n13385 , n13386 , n13387 , n13388 , n13389 , n13390 ,
n13391 , n13392 , n13393 , n13394 , n13395 , n13396 , n13397 , n13398 , n13399 , n13400 ,
n13401 , n13402 , n13403 , n13404 , n13405 , n13406 , n13407 , n13408 , n13409 , n13410 ,
n13411 , n13412 , n13413 , n13414 , n13415 , n13416 , n13417 , n13418 , n13419 , n13420 ,
n13421 , n13422 , n13423 , n13424 , n13425 , n13426 , n13427 , n13428 , n13429 , n13430 ,
n13431 , n13432 , n13433 , n13434 , n13435 , n13436 , n13437 , n13438 , n13439 , n13440 ,
n13441 , n13442 , n13443 , n13444 , n13445 , n13446 , n13447 , n13448 , n13449 , n13450 ,
n13451 , n13452 , n13453 , n13454 , n13455 , n13456 , n13457 , n13458 , n13459 , n13460 ,
n13461 , n13462 , n13463 , n13464 , n13465 , n13466 , n13467 , n13468 , n13469 , n13470 ,
n13471 , n13472 , n13473 , n13474 , n13475 , n13476 , n13477 , n13478 , n13479 , n13480 ,
n13481 , n13482 , n13483 , n13484 , n13485 , n13486 , n13487 , n13488 , n13489 , n13490 ,
n13491 , n13492 , n13493 , n13494 , n13495 , n13496 , n13497 , n13498 , n13499 , n13500 ,
n13501 , n13502 , n13503 , n13504 , n13505 , n13506 , n13507 , n13508 , n13509 , n13510 ,
n13511 , n13512 , n13513 , n13514 , n13515 , n13516 , n13517 , n13518 , n13519 , n13520 ,
n13521 , n13522 , n13523 , n13524 , n13525 , n13526 , n13527 , n13528 , n13529 , n13530 ,
n13531 , n13532 , n13533 , n13534 , n13535 , n13536 , n13537 , n13538 , n13539 , n13540 ,
n13541 , n13542 , n13543 , n13544 , n13545 , n13546 , n13547 , n13548 , n13549 , n13550 ,
n13551 , n13552 , n13553 , n13554 , n13555 , n13556 , n13557 , n13558 , n13559 , n13560 ,
n13561 , n13562 , n13563 , n13564 , n13565 , n13566 , n13567 , n13568 , n13569 , n13570 ,
n13571 , n13572 , n13573 , n13574 , n13575 , n13576 , n13577 , n13578 , n13579 , n13580 ,
n13581 , n13582 , n13583 , n13584 , n13585 , n13586 , n13587 , n13588 , n13589 , n13590 ,
n13591 , n13592 , n13593 , n13594 , n13595 , n13596 , n13597 , n13598 , n13599 , n13600 ,
n13601 , n13602 , n13603 , n13604 , n13605 , n13606 , n13607 , n13608 , n13609 , n13610 ,
n13611 , n13612 , n13613 , n13614 , n13615 , n13616 , n13617 , n13618 , n13619 , n13620 ,
n13621 , n13622 , n13623 , n13624 , n13625 , n13626 , n13627 , n13628 , n13629 , n13630 ,
n13631 , n13632 , n13633 , n13634 , n13635 , n13636 , n13637 , n13638 , n13639 , n13640 ,
n13641 , n13642 , n13643 , n13644 , n13645 , n13646 , n13647 , n13648 , n13649 , n13650 ,
n13651 , n13652 , n13653 , n13654 , n13655 , n13656 , n13657 , n13658 , n13659 , n13660 ,
n13661 , n13662 , n13663 , n13664 , n13665 , n13666 , n13667 , n13668 , n13669 , n13670 ,
n13671 , n13672 , n13673 , n13674 , n13675 , n13676 , n13677 , n13678 , n13679 , n13680 ,
n13681 , n13682 , n13683 , n13684 , n13685 , n13686 , n13687 , n13688 , n13689 , n13690 ,
n13691 , n13692 , n13693 , n13694 , n13695 , n13696 , n13697 , n13698 , n13699 , n13700 ,
n13701 , n13702 , n13703 , n13704 , n13705 , n13706 , n13707 , n13708 , n13709 , n13710 ,
n13711 , n13712 , n13713 , n13714 , n13715 , n13716 , n13717 , n13718 , n13719 , n13720 ,
n13721 , n13722 , n13723 , n13724 , n13725 , n13726 , n13727 , n13728 , n13729 , n13730 ,
n13731 , n13732 , n13733 , n13734 , n13735 , n13736 , n13737 , n13738 , n13739 , n13740 ,
n13741 , n13742 , n13743 , n13744 , n13745 , n13746 , n13747 , n13748 , n13749 , n13750 ,
n13751 , n13752 , n13753 , n13754 , n13755 , n13756 , n13757 , n13758 , n13759 , n13760 ,
n13761 , n13762 , n13763 , n13764 , n13765 , n13766 , n13767 , n13768 , n13769 , n13770 ,
n13771 , n13772 , n13773 , n13774 , n13775 , n13776 , n13777 , n13778 , n13779 , n13780 ,
n13781 , n13782 , n13783 , n13784 , n13785 , n13786 , n13787 , n13788 , n13789 , n13790 ,
n13791 , n13792 , n13793 , n13794 , n13795 , n13796 , n13797 , n13798 , n13799 , n13800 ,
n13801 , n13802 , n13803 , n13804 , n13805 , n13806 , n13807 , n13808 , n13809 , n13810 ,
n13811 , n13812 , n13813 , n13814 , n13815 , n13816 , n13817 , n13818 , n13819 , n13820 ,
n13821 , n13822 , n13823 , n13824 , n13825 , n13826 , n13827 , n13828 , n13829 , n13830 ,
n13831 , n13832 , n13833 , n13834 , n13835 , n13836 , n13837 , n13838 , n13839 , n13840 ,
n13841 , n13842 , n13843 , n13844 , n13845 , n13846 , n13847 , n13848 , n13849 , n13850 ,
n13851 , n13852 , n13853 , n13854 , n13855 , n13856 , n13857 , n13858 , n13859 , n13860 ,
n13861 , n13862 , n13863 , n13864 , n13865 , n13866 , n13867 , n13868 , n13869 , n13870 ,
n13871 , n13872 , n13873 , n13874 , n13875 , n13876 , n13877 , n13878 , n13879 , n13880 ,
n13881 , n13882 , n13883 , n13884 , n13885 , n13886 , n13887 , n13888 , n13889 , n13890 ,
n13891 , n13892 , n13893 , n13894 , n13895 , n13896 , n13897 , n13898 , n13899 , n13900 ,
n13901 , n13902 , n13903 , n13904 , n13905 , n13906 , n13907 , n13908 , n13909 , n13910 ,
n13911 , n13912 , n13913 , n13914 , n13915 , n13916 , n13917 , n13918 , n13919 , n13920 ,
n13921 , n13922 , n13923 , n13924 , n13925 , n13926 , n13927 , n13928 , n13929 , n13930 ,
n13931 , n13932 , n13933 , n13934 , n13935 , n13936 , n13937 , n13938 , n13939 , n13940 ,
n13941 , n13942 , n13943 , n13944 , n13945 , n13946 , n13947 , n13948 , n13949 , n13950 ,
n13951 , n13952 , n13953 , n13954 , n13955 , n13956 , n13957 , n13958 , n13959 , n13960 ,
n13961 , n13962 , n13963 , n13964 , n13965 , n13966 , n13967 , n13968 , n13969 , n13970 ,
n13971 , n13972 , n13973 , n13974 , n13975 , n13976 , n13977 , n13978 , n13979 , n13980 ,
n13981 , n13982 , n13983 , n13984 , n13985 , n13986 , n13987 , n13988 , n13989 , n13990 ,
n13991 , n13992 , n13993 , n13994 , n13995 , n13996 , n13997 , n13998 , n13999 , n14000 ,
n14001 , n14002 , n14003 , n14004 , n14005 , n14006 , n14007 , n14008 , n14009 , n14010 ,
n14011 , n14012 , n14013 , n14014 , n14015 , n14016 , n14017 , n14018 , n14019 , n14020 ,
n14021 , n14022 , n14023 , n14024 , n14025 , n14026 , n14027 , n14028 , n14029 , n14030 ,
n14031 , n14032 , n14033 , n14034 , n14035 , n14036 , n14037 , n14038 , n14039 , n14040 ,
n14041 , n14042 , n14043 , n14044 , n14045 , n14046 , n14047 , n14048 , n14049 , n14050 ,
n14051 , n14052 , n14053 , n14054 , n14055 , n14056 , n14057 , n14058 , n14059 , n14060 ,
n14061 , n14062 , n14063 , n14064 , n14065 , n14066 , n14067 , n14068 , n14069 , n14070 ,
n14071 , n14072 , n14073 , n14074 , n14075 , n14076 , n14077 , n14078 , n14079 , n14080 ,
n14081 , n14082 , n14083 , n14084 , n14085 , n14086 , n14087 , n14088 , n14089 , n14090 ,
n14091 , n14092 , n14093 , n14094 , n14095 , n14096 , n14097 , n14098 , n14099 , n14100 ,
n14101 , n14102 , n14103 , n14104 , n14105 , n14106 , n14107 , n14108 , n14109 , n14110 ,
n14111 , n14112 , n14113 , n14114 , n14115 , n14116 , n14117 , n14118 , n14119 , n14120 ,
n14121 , n14122 , n14123 , n14124 , n14125 , n14126 , n14127 , n14128 , n14129 , n14130 ,
n14131 , n14132 , n14133 , n14134 , n14135 , n14136 , n14137 , n14138 , n14139 , n14140 ,
n14141 , n14142 , n14143 , n14144 , n14145 , n14146 , n14147 , n14148 , n14149 , n14150 ,
n14151 , n14152 , n14153 , n14154 , n14155 , n14156 , n14157 , n14158 , n14159 , n14160 ,
n14161 , n14162 , n14163 , n14164 , n14165 , n14166 , n14167 , n14168 , n14169 , n14170 ,
n14171 , n14172 , n14173 , n14174 , n14175 , n14176 , n14177 , n14178 , n14179 , n14180 ,
n14181 , n14182 , n14183 , n14184 , n14185 , n14186 , n14187 , n14188 , n14189 , n14190 ,
n14191 , n14192 , n14193 , n14194 , n14195 , n14196 , n14197 , n14198 , n14199 , n14200 ,
n14201 , n14202 , n14203 , n14204 , n14205 , n14206 , n14207 , n14208 , n14209 , n14210 ,
n14211 , n14212 , n14213 , n14214 , n14215 , n14216 , n14217 , n14218 , n14219 , n14220 ,
n14221 , n14222 , n14223 , n14224 , n14225 , n14226 , n14227 , n14228 , n14229 , n14230 ,
n14231 , n14232 , n14233 , n14234 , n14235 , n14236 , n14237 , n14238 , n14239 , n14240 ,
n14241 , n14242 , n14243 , n14244 , n14245 , n14246 , n14247 , n14248 , n14249 , n14250 ,
n14251 , n14252 , n14253 , n14254 , n14255 , n14256 , n14257 , n14258 , n14259 , n14260 ,
n14261 , n14262 , n14263 , n14264 , n14265 , n14266 , n14267 , n14268 , n14269 , n14270 ,
n14271 , n14272 , n14273 , n14274 , n14275 , n14276 , n14277 , n14278 , n14279 , n14280 ,
n14281 , n14282 , n14283 , n14284 , n14285 , n14286 , n14287 , n14288 , n14289 , n14290 ,
n14291 , n14292 , n14293 , n14294 , n14295 , n14296 , n14297 , n14298 , n14299 , n14300 ,
n14301 , n14302 , n14303 , n14304 , n14305 , n14306 , n14307 , n14308 , n14309 , n14310 ,
n14311 , n14312 , n14313 , n14314 , n14315 , n14316 , n14317 , n14318 , n14319 , n14320 ,
n14321 , n14322 , n14323 , n14324 , n14325 , n14326 , n14327 , n14328 , n14329 , n14330 ,
n14331 , n14332 , n14333 , n14334 , n14335 , n14336 , n14337 , n14338 , n14339 , n14340 ,
n14341 , n14342 , n14343 , n14344 , n14345 , n14346 , n14347 , n14348 , n14349 , n14350 ,
n14351 , n14352 , n14353 , n14354 , n14355 , n14356 , n14357 , n14358 , n14359 , n14360 ,
n14361 , n14362 , n14363 , n14364 , n14365 , n14366 , n14367 , n14368 , n14369 , n14370 ,
n14371 , n14372 , n14373 , n14374 , n14375 , n14376 , n14377 , n14378 , n14379 , n14380 ,
n14381 , n14382 , n14383 , n14384 , n14385 , n14386 , n14387 , n14388 , n14389 , n14390 ,
n14391 , n14392 , n14393 , n14394 , n14395 , n14396 , n14397 , n14398 , n14399 , n14400 ,
n14401 , n14402 , n14403 , n14404 , n14405 , n14406 , n14407 , n14408 , n14409 , n14410 ,
n14411 , n14412 , n14413 , n14414 , n14415 , n14416 , n14417 , n14418 , n14419 , n14420 ,
n14421 , n14422 , n14423 , n14424 , n14425 , n14426 , n14427 , n14428 , n14429 , n14430 ,
n14431 , n14432 , n14433 , n14434 , n14435 , n14436 , n14437 , n14438 , n14439 , n14440 ,
n14441 , n14442 , n14443 , n14444 , n14445 , n14446 , n14447 , n14448 , n14449 , n14450 ,
n14451 , n14452 , n14453 , n14454 , n14455 , n14456 , n14457 , n14458 , n14459 , n14460 ,
n14461 , n14462 , n14463 , n14464 , n14465 , n14466 , n14467 , n14468 , n14469 , n14470 ,
n14471 , n14472 , n14473 , n14474 , n14475 , n14476 , n14477 , n14478 , n14479 , n14480 ,
n14481 , n14482 , n14483 , n14484 , n14485 , n14486 , n14487 , n14488 , n14489 , n14490 ,
n14491 , n14492 , n14493 , n14494 , n14495 , n14496 , n14497 , n14498 , n14499 , n14500 ,
n14501 , n14502 , n14503 , n14504 , n14505 , n14506 , n14507 , n14508 , n14509 , n14510 ,
n14511 , n14512 , n14513 , n14514 , n14515 , n14516 , n14517 , n14518 , n14519 , n14520 ,
n14521 , n14522 , n14523 , n14524 , n14525 , n14526 , n14527 , n14528 , n14529 , n14530 ,
n14531 , n14532 , n14533 , n14534 , n14535 , n14536 , n14537 , n14538 , n14539 , n14540 ,
n14541 , n14542 , n14543 , n14544 , n14545 , n14546 , n14547 , n14548 , n14549 , n14550 ,
n14551 , n14552 , n14553 , n14554 , n14555 , n14556 , n14557 , n14558 , n14559 , n14560 ,
n14561 , n14562 , n14563 , n14564 , n14565 , n14566 , n14567 , n14568 , n14569 , n14570 ,
n14571 , n14572 , n14573 , n14574 , n14575 , n14576 , n14577 , n14578 , n14579 , n14580 ,
n14581 , n14582 , n14583 , n14584 , n14585 , n14586 , n14587 , n14588 , n14589 , n14590 ,
n14591 , n14592 , n14593 , n14594 , n14595 , n14596 , n14597 , n14598 , n14599 , n14600 ,
n14601 , n14602 , n14603 , n14604 , n14605 , n14606 , n14607 , n14608 , n14609 , n14610 ,
n14611 , n14612 , n14613 , n14614 , n14615 , n14616 , n14617 , n14618 , n14619 , n14620 ,
n14621 , n14622 , n14623 , n14624 , n14625 , n14626 , n14627 , n14628 , n14629 , n14630 ,
n14631 , n14632 , n14633 , n14634 , n14635 , n14636 , n14637 , n14638 , n14639 , n14640 ,
n14641 , n14642 , n14643 , n14644 , n14645 , n14646 , n14647 , n14648 , n14649 , n14650 ,
n14651 , n14652 , n14653 , n14654 , n14655 , n14656 , n14657 , n14658 , n14659 , n14660 ,
n14661 , n14662 , n14663 , n14664 , n14665 , n14666 , n14667 , n14668 , n14669 , n14670 ,
n14671 , n14672 , n14673 , n14674 , n14675 , n14676 , n14677 , n14678 , n14679 , n14680 ,
n14681 , n14682 , n14683 , n14684 , n14685 , n14686 , n14687 , n14688 , n14689 , n14690 ,
n14691 , n14692 , n14693 , n14694 , n14695 , n14696 , n14697 , n14698 , n14699 , n14700 ,
n14701 , n14702 , n14703 , n14704 , n14705 , n14706 , n14707 , n14708 , n14709 , n14710 ,
n14711 , n14712 , n14713 , n14714 , n14715 , n14716 , n14717 , n14718 , n14719 , n14720 ,
n14721 , n14722 , n14723 , n14724 , n14725 , n14726 , n14727 , n14728 , n14729 , n14730 ,
n14731 , n14732 , n14733 , n14734 , n14735 , n14736 , n14737 , n14738 , n14739 , n14740 ,
n14741 , n14742 , n14743 , n14744 , n14745 , n14746 , n14747 , n14748 , n14749 , n14750 ,
n14751 , n14752 , n14753 , n14754 , n14755 , n14756 , n14757 , n14758 , n14759 , n14760 ,
n14761 , n14762 , n14763 , n14764 , n14765 , n14766 , n14767 , n14768 , n14769 , n14770 ,
n14771 , n14772 , n14773 , n14774 , n14775 , n14776 , n14777 , n14778 , n14779 , n14780 ,
n14781 , n14782 , n14783 , n14784 , n14785 , n14786 , n14787 , n14788 , n14789 , n14790 ,
n14791 , n14792 , n14793 , n14794 , n14795 , n14796 , n14797 , n14798 , n14799 , n14800 ,
n14801 , n14802 , n14803 , n14804 , n14805 , n14806 , n14807 , n14808 , n14809 , n14810 ,
n14811 , n14812 , n14813 , n14814 , n14815 , n14816 , n14817 , n14818 , n14819 , n14820 ,
n14821 , n14822 , n14823 , n14824 , n14825 , n14826 , n14827 , n14828 , n14829 , n14830 ,
n14831 , n14832 , n14833 , n14834 , n14835 , n14836 , n14837 , n14838 , n14839 , n14840 ,
n14841 , n14842 , n14843 , n14844 , n14845 , n14846 , n14847 , n14848 , n14849 , n14850 ,
n14851 , n14852 , n14853 , n14854 , n14855 , n14856 , n14857 , n14858 , n14859 , n14860 ,
n14861 , n14862 , n14863 , n14864 , n14865 , n14866 , n14867 , n14868 , n14869 , n14870 ,
n14871 , n14872 , n14873 , n14874 , n14875 , n14876 , n14877 , n14878 , n14879 , n14880 ,
n14881 , n14882 , n14883 , n14884 , n14885 , n14886 , n14887 , n14888 , n14889 , n14890 ,
n14891 , n14892 , n14893 , n14894 , n14895 , n14896 , n14897 , n14898 , n14899 , n14900 ,
n14901 , n14902 , n14903 , n14904 , n14905 , n14906 , n14907 , n14908 , n14909 , n14910 ,
n14911 , n14912 , n14913 , n14914 , n14915 , n14916 , n14917 , n14918 , n14919 , n14920 ,
n14921 , n14922 , n14923 , n14924 , n14925 , n14926 , n14927 , n14928 , n14929 , n14930 ,
n14931 , n14932 , n14933 , n14934 , n14935 , n14936 , n14937 , n14938 , n14939 , n14940 ,
n14941 , n14942 , n14943 , n14944 , n14945 , n14946 , n14947 , n14948 , n14949 , n14950 ,
n14951 , n14952 , n14953 , n14954 , n14955 , n14956 , n14957 , n14958 , n14959 , n14960 ,
n14961 , n14962 , n14963 , n14964 , n14965 , n14966 , n14967 , n14968 , n14969 , n14970 ,
n14971 , n14972 , n14973 , n14974 , n14975 , n14976 , n14977 , n14978 , n14979 , n14980 ,
n14981 , n14982 , n14983 , n14984 , n14985 , n14986 , n14987 , n14988 , n14989 , n14990 ,
n14991 , n14992 , n14993 , n14994 , n14995 , n14996 , n14997 , n14998 , n14999 , n15000 ,
n15001 , n15002 , n15003 , n15004 , n15005 , n15006 , n15007 , n15008 , n15009 , n15010 ,
n15011 , n15012 , n15013 , n15014 , n15015 , n15016 , n15017 , n15018 , n15019 , n15020 ,
n15021 , n15022 , n15023 , n15024 , n15025 , n15026 , n15027 , n15028 , n15029 , n15030 ,
n15031 , n15032 , n15033 , n15034 , n15035 , n15036 , n15037 , n15038 , n15039 , n15040 ,
n15041 , n15042 , n15043 , n15044 , n15045 , n15046 , n15047 , n15048 , n15049 , n15050 ,
n15051 , n15052 , n15053 , n15054 , n15055 , n15056 , n15057 , n15058 , n15059 , n15060 ,
n15061 , n15062 , n15063 , n15064 , n15065 , n15066 , n15067 , n15068 , n15069 , n15070 ,
n15071 , n15072 , n15073 , n15074 , n15075 , n15076 , n15077 , n15078 , n15079 , n15080 ,
n15081 , n15082 , n15083 , n15084 , n15085 , n15086 , n15087 , n15088 , n15089 , n15090 ,
n15091 , n15092 , n15093 , n15094 , n15095 , n15096 , n15097 , n15098 , n15099 , n15100 ,
n15101 , n15102 , n15103 , n15104 , n15105 , n15106 , n15107 , n15108 , n15109 , n15110 ,
n15111 , n15112 , n15113 , n15114 , n15115 , n15116 , n15117 , n15118 , n15119 , n15120 ,
n15121 , n15122 , n15123 , n15124 , n15125 , n15126 , n15127 , n15128 , n15129 , n15130 ,
n15131 , n15132 , n15133 , n15134 , n15135 , n15136 , n15137 , n15138 , n15139 , n15140 ,
n15141 , n15142 , n15143 , n15144 , n15145 , n15146 , n15147 , n15148 , n15149 , n15150 ,
n15151 , n15152 , n15153 , n15154 , n15155 , n15156 , n15157 , n15158 , n15159 , n15160 ,
n15161 , n15162 , n15163 , n15164 , n15165 , n15166 , n15167 , n15168 , n15169 , n15170 ,
n15171 , n15172 , n15173 , n15174 , n15175 , n15176 , n15177 , n15178 , n15179 , n15180 ,
n15181 , n15182 , n15183 , n15184 , n15185 , n15186 , n15187 , n15188 , n15189 , n15190 ,
n15191 , n15192 , n15193 , n15194 , n15195 , n15196 , n15197 , n15198 , n15199 , n15200 ,
n15201 , n15202 , n15203 , n15204 , n15205 , n15206 , n15207 , n15208 , n15209 , n15210 ,
n15211 , n15212 , n15213 , n15214 , n15215 , n15216 , n15217 , n15218 , n15219 , n15220 ,
n15221 , n15222 , n15223 , n15224 , n15225 , n15226 , n15227 , n15228 , n15229 , n15230 ,
n15231 , n15232 , n15233 , n15234 , n15235 , n15236 , n15237 , n15238 , n15239 , n15240 ,
n15241 , n15242 , n15243 , n15244 , n15245 , n15246 , n15247 , n15248 , n15249 , n15250 ,
n15251 , n15252 , n15253 , n15254 , n15255 , n15256 , n15257 , n15258 , n15259 , n15260 ,
n15261 , n15262 , n15263 , n15264 , n15265 , n15266 , n15267 , n15268 , n15269 , n15270 ,
n15271 , n15272 , n15273 , n15274 , n15275 , n15276 , n15277 , n15278 , n15279 , n15280 ,
n15281 , n15282 , n15283 , n15284 , n15285 , n15286 , n15287 , n15288 , n15289 , n15290 ,
n15291 , n15292 , n15293 , n15294 , n15295 , n15296 , n15297 , n15298 , n15299 , n15300 ,
n15301 , n15302 , n15303 , n15304 , n15305 , n15306 , n15307 , n15308 , n15309 , n15310 ,
n15311 , n15312 , n15313 , n15314 , n15315 , n15316 , n15317 , n15318 , n15319 , n15320 ,
n15321 , n15322 , n15323 , n15324 , n15325 , n15326 , n15327 , n15328 , n15329 , n15330 ,
n15331 , n15332 , n15333 , n15334 , n15335 , n15336 , n15337 , n15338 , n15339 , n15340 ,
n15341 , n15342 , n15343 , n15344 , n15345 , n15346 , n15347 , n15348 , n15349 , n15350 ,
n15351 , n15352 , n15353 , n15354 , n15355 , n15356 , n15357 , n15358 , n15359 , n15360 ,
n15361 , n15362 , n15363 , n15364 , n15365 , n15366 , n15367 , n15368 , n15369 , n15370 ,
n15371 , n15372 , n15373 , n15374 , n15375 , n15376 , n15377 , n15378 , n15379 , n15380 ,
n15381 , n15382 , n15383 , n15384 , n15385 , n15386 , n15387 , n15388 , n15389 , n15390 ,
n15391 , n15392 , n15393 , n15394 , n15395 , n15396 , n15397 , n15398 , n15399 , n15400 ,
n15401 , n15402 , n15403 , n15404 , n15405 , n15406 , n15407 , n15408 , n15409 , n15410 ,
n15411 , n15412 ;
buf ( n2187 , n9985 );
buf ( n2195 , n10744 );
buf ( n2192 , n12250 );
buf ( n2188 , n13433 );
buf ( n2190 , n13909 );
buf ( n2186 , n14368 );
buf ( n2191 , n14705 );
buf ( n2194 , n14946 );
buf ( n2193 , n15224 );
buf ( n2189 , n15412 );
buf ( n4394 , n1825 );
buf ( n4395 , n1584 );
buf ( n4396 , n1052 );
buf ( n4397 , n1350 );
buf ( n4398 , n746 );
buf ( n4399 , n1213 );
buf ( n4400 , n1132 );
buf ( n4401 , n420 );
buf ( n4402 , n85 );
buf ( n4403 , n1176 );
buf ( n4404 , n962 );
buf ( n4405 , n542 );
buf ( n4406 , n68 );
buf ( n4407 , n313 );
buf ( n4408 , n1070 );
buf ( n4409 , n719 );
buf ( n4410 , n980 );
buf ( n4411 , n251 );
buf ( n4412 , n295 );
buf ( n4413 , n1998 );
buf ( n4414 , n2091 );
buf ( n4415 , n733 );
buf ( n4416 , n678 );
buf ( n4417 , n13 );
buf ( n4418 , n2176 );
buf ( n4419 , n1534 );
buf ( n4420 , n1378 );
buf ( n4421 , n728 );
buf ( n4422 , n1100 );
buf ( n4423 , n1880 );
buf ( n4424 , n2152 );
buf ( n4425 , n1432 );
buf ( n4426 , n1708 );
buf ( n4427 , n135 );
buf ( n4428 , n2029 );
buf ( n4429 , n1431 );
buf ( n4430 , n1777 );
buf ( n4431 , n1757 );
buf ( n4432 , n1075 );
buf ( n4433 , n1450 );
buf ( n4434 , n455 );
buf ( n4435 , n266 );
buf ( n4436 , n1666 );
buf ( n4437 , n1412 );
buf ( n4438 , n859 );
buf ( n4439 , n548 );
buf ( n4440 , n1812 );
buf ( n4441 , n1937 );
buf ( n4442 , n1877 );
buf ( n4443 , n205 );
buf ( n4444 , n93 );
buf ( n4445 , n1460 );
buf ( n4446 , n370 );
buf ( n4447 , n1591 );
buf ( n4448 , n876 );
buf ( n4449 , n616 );
buf ( n4450 , n1603 );
buf ( n4451 , n682 );
buf ( n4452 , n288 );
buf ( n4453 , n2054 );
buf ( n4454 , n1376 );
buf ( n4455 , n1572 );
buf ( n4456 , n1047 );
buf ( n4457 , n139 );
buf ( n4458 , n901 );
buf ( n4459 , n764 );
buf ( n4460 , n1821 );
buf ( n4461 , n2130 );
buf ( n4462 , n908 );
buf ( n4463 , n587 );
buf ( n4464 , n187 );
buf ( n4465 , n75 );
buf ( n4466 , n924 );
buf ( n4467 , n2094 );
buf ( n4468 , n439 );
buf ( n4469 , n970 );
buf ( n4470 , n1272 );
buf ( n4471 , n1745 );
buf ( n4472 , n844 );
buf ( n4473 , n1719 );
buf ( n4474 , n430 );
buf ( n4475 , n1965 );
buf ( n4476 , n644 );
buf ( n4477 , n21 );
buf ( n4478 , n869 );
buf ( n4479 , n1927 );
buf ( n4480 , n1478 );
buf ( n4481 , n175 );
buf ( n4482 , n1867 );
buf ( n4483 , n1425 );
buf ( n4484 , n322 );
buf ( n4485 , n2083 );
buf ( n4486 , n1306 );
buf ( n4487 , n235 );
buf ( n4488 , n1638 );
buf ( n4489 , n1140 );
buf ( n4490 , n1333 );
buf ( n4491 , n1893 );
buf ( n4492 , n327 );
buf ( n4493 , n37 );
buf ( n4494 , n1182 );
buf ( n4495 , n1489 );
buf ( n4496 , n218 );
buf ( n4497 , n1314 );
buf ( n4498 , n372 );
buf ( n4499 , n656 );
buf ( n4500 , n1039 );
buf ( n4501 , n1889 );
buf ( n4502 , n1630 );
buf ( n4503 , n742 );
buf ( n4504 , n1096 );
buf ( n4505 , n181 );
buf ( n4506 , n1852 );
buf ( n4507 , n1801 );
buf ( n4508 , n811 );
buf ( n4509 , n2024 );
buf ( n4510 , n1293 );
buf ( n4511 , n243 );
buf ( n4512 , n630 );
buf ( n4513 , n515 );
buf ( n4514 , n131 );
buf ( n4515 , n735 );
buf ( n4516 , n423 );
buf ( n4517 , n2040 );
buf ( n4518 , n710 );
buf ( n4519 , n240 );
buf ( n4520 , n1267 );
buf ( n4521 , n592 );
buf ( n4522 , n2075 );
buf ( n4523 , n1384 );
buf ( n4524 , n722 );
buf ( n4525 , n1678 );
buf ( n4526 , n2071 );
buf ( n4527 , n957 );
buf ( n4528 , n76 );
buf ( n4529 , n1305 );
buf ( n4530 , n1410 );
buf ( n4531 , n1466 );
buf ( n4532 , n675 );
buf ( n4533 , n1448 );
buf ( n4534 , n98 );
buf ( n4535 , n1495 );
buf ( n4536 , n1086 );
buf ( n4537 , n1838 );
buf ( n4538 , n1308 );
buf ( n4539 , n407 );
buf ( n4540 , n711 );
buf ( n4541 , n726 );
buf ( n4542 , n2137 );
buf ( n4543 , n473 );
buf ( n4544 , n681 );
buf ( n4545 , n195 );
buf ( n4546 , n1637 );
buf ( n4547 , n427 );
buf ( n4548 , n1320 );
buf ( n4549 , n659 );
buf ( n4550 , n1659 );
buf ( n4551 , n263 );
buf ( n4552 , n586 );
buf ( n4553 , n43 );
buf ( n4554 , n461 );
buf ( n4555 , n2185 );
buf ( n4556 , n1715 );
buf ( n4557 , n2115 );
buf ( n4558 , n2148 );
buf ( n4559 , n1628 );
buf ( n4560 , n867 );
buf ( n4561 , n1179 );
buf ( n4562 , n578 );
buf ( n4563 , n1728 );
buf ( n4564 , n835 );
buf ( n4565 , n781 );
buf ( n4566 , n995 );
buf ( n4567 , n1536 );
buf ( n4568 , n484 );
buf ( n4569 , n1598 );
buf ( n4570 , n921 );
buf ( n4571 , n1918 );
buf ( n4572 , n519 );
buf ( n4573 , n415 );
buf ( n4574 , n1555 );
buf ( n4575 , n824 );
buf ( n4576 , n1463 );
buf ( n4577 , n1142 );
buf ( n4578 , n1675 );
buf ( n4579 , n1321 );
buf ( n4580 , n851 );
buf ( n4581 , n854 );
buf ( n4582 , n1740 );
buf ( n4583 , n1667 );
buf ( n4584 , n1133 );
buf ( n4585 , n1241 );
buf ( n4586 , n1519 );
buf ( n4587 , n2132 );
buf ( n4588 , n1170 );
buf ( n4589 , n353 );
buf ( n4590 , n1670 );
buf ( n4591 , n527 );
buf ( n4592 , n514 );
buf ( n4593 , n1967 );
buf ( n4594 , n513 );
buf ( n4595 , n1787 );
buf ( n4596 , n808 );
buf ( n4597 , n1741 );
buf ( n4598 , n716 );
buf ( n4599 , n2061 );
buf ( n4600 , n1917 );
buf ( n4601 , n308 );
buf ( n4602 , n123 );
buf ( n4603 , n17 );
buf ( n4604 , n1188 );
buf ( n4605 , n1767 );
buf ( n4606 , n137 );
buf ( n4607 , n701 );
buf ( n4608 , n1610 );
buf ( n4609 , n541 );
buf ( n4610 , n299 );
buf ( n4611 , n409 );
buf ( n4612 , n1077 );
buf ( n4613 , n516 );
buf ( n4614 , n1831 );
buf ( n4615 , n418 );
buf ( n4616 , n121 );
buf ( n4617 , n291 );
buf ( n4618 , n1749 );
buf ( n4619 , n2144 );
buf ( n4620 , n790 );
buf ( n4621 , n294 );
buf ( n4622 , n618 );
buf ( n4623 , n470 );
buf ( n4624 , n1229 );
buf ( n4625 , n853 );
buf ( n4626 , n2087 );
buf ( n4627 , n2039 );
buf ( n4628 , n890 );
buf ( n4629 , n1703 );
buf ( n4630 , n2033 );
buf ( n4631 , n1768 );
buf ( n4632 , n1313 );
buf ( n4633 , n302 );
buf ( n4634 , n1023 );
buf ( n4635 , n387 );
buf ( n4636 , n668 );
buf ( n4637 , n1428 );
buf ( n4638 , n1298 );
buf ( n4639 , n1566 );
buf ( n4640 , n483 );
buf ( n4641 , n2022 );
buf ( n4642 , n366 );
buf ( n4643 , n151 );
buf ( n4644 , n1562 );
buf ( n4645 , n1085 );
buf ( n4646 , n936 );
buf ( n4647 , n884 );
buf ( n4648 , n530 );
buf ( n4649 , n720 );
buf ( n4650 , n686 );
buf ( n4651 , n1351 );
buf ( n4652 , n2107 );
buf ( n4653 , n862 );
buf ( n4654 , n687 );
buf ( n4655 , n1597 );
buf ( n4656 , n42 );
buf ( n4657 , n1000 );
buf ( n4658 , n1158 );
buf ( n4659 , n1806 );
buf ( n4660 , n1149 );
buf ( n4661 , n989 );
buf ( n4662 , n1494 );
buf ( n4663 , n1307 );
buf ( n4664 , n2105 );
buf ( n4665 , n1058 );
buf ( n4666 , n839 );
buf ( n4667 , n310 );
buf ( n4668 , n1316 );
buf ( n4669 , n451 );
buf ( n4670 , n1884 );
buf ( n4671 , n880 );
buf ( n4672 , n1533 );
buf ( n4673 , n1003 );
buf ( n4674 , n1586 );
buf ( n4675 , n1035 );
buf ( n4676 , n1726 );
buf ( n4677 , n1711 );
buf ( n4678 , n624 );
buf ( n4679 , n805 );
buf ( n4680 , n569 );
buf ( n4681 , n1447 );
buf ( n4682 , n1166 );
buf ( n4683 , n614 );
buf ( n4684 , n55 );
buf ( n4685 , n1205 );
buf ( n4686 , n1248 );
buf ( n4687 , n1765 );
buf ( n4688 , n1512 );
buf ( n4689 , n1021 );
buf ( n4690 , n1727 );
buf ( n4691 , n1932 );
buf ( n4692 , n1007 );
buf ( n4693 , n1287 );
buf ( n4694 , n1413 );
buf ( n4695 , n1357 );
buf ( n4696 , n236 );
buf ( n4697 , n622 );
buf ( n4698 , n1582 );
buf ( n4699 , n1712 );
buf ( n4700 , n130 );
buf ( n4701 , n1243 );
buf ( n4702 , n1976 );
buf ( n4703 , n1090 );
buf ( n4704 , n388 );
buf ( n4705 , n964 );
buf ( n4706 , n1049 );
buf ( n4707 , n1850 );
buf ( n4708 , n1291 );
buf ( n4709 , n413 );
buf ( n4710 , n1441 );
buf ( n4711 , n1265 );
buf ( n4712 , n296 );
buf ( n4713 , n2066 );
buf ( n4714 , n1702 );
buf ( n4715 , n2182 );
buf ( n4716 , n1315 );
buf ( n4717 , n1554 );
buf ( n4718 , n341 );
buf ( n4719 , n1330 );
buf ( n4720 , n143 );
buf ( n4721 , n600 );
buf ( n4722 , n505 );
buf ( n4723 , n2150 );
buf ( n4724 , n1988 );
buf ( n4725 , n206 );
buf ( n4726 , n1289 );
buf ( n4727 , n1285 );
buf ( n4728 , n1589 );
buf ( n4729 , n1558 );
buf ( n4730 , n18 );
buf ( n4731 , n1946 );
buf ( n4732 , n1508 );
buf ( n4733 , n2073 );
buf ( n4734 , n1421 );
buf ( n4735 , n1110 );
buf ( n4736 , n1464 );
buf ( n4737 , n1046 );
buf ( n4738 , n99 );
buf ( n4739 , n1762 );
buf ( n4740 , n749 );
buf ( n4741 , n1802 );
buf ( n4742 , n1846 );
buf ( n4743 , n197 );
buf ( n4744 , n621 );
buf ( n4745 , n1922 );
buf ( n4746 , n159 );
buf ( n4747 , n1340 );
buf ( n4748 , n765 );
buf ( n4749 , n792 );
buf ( n4750 , n813 );
buf ( n4751 , n1861 );
buf ( n4752 , n886 );
buf ( n4753 , n1290 );
buf ( n4754 , n1575 );
buf ( n4755 , n499 );
buf ( n4756 , n545 );
buf ( n4757 , n665 );
buf ( n4758 , n1177 );
buf ( n4759 , n2168 );
buf ( n4760 , n1405 );
buf ( n4761 , n167 );
buf ( n4762 , n1948 );
buf ( n4763 , n1153 );
buf ( n4764 , n359 );
buf ( n4765 , n494 );
buf ( n4766 , n1300 );
buf ( n4767 , n628 );
buf ( n4768 , n1989 );
buf ( n4769 , n1012 );
buf ( n4770 , n588 );
buf ( n4771 , n1963 );
buf ( n4772 , n1004 );
buf ( n4773 , n1528 );
buf ( n4774 , n761 );
buf ( n4775 , n1337 );
buf ( n4776 , n31 );
buf ( n4777 , n250 );
buf ( n4778 , n1362 );
buf ( n4779 , n597 );
buf ( n4780 , n1420 );
buf ( n4781 , n814 );
buf ( n4782 , n1226 );
buf ( n4783 , n1548 );
buf ( n4784 , n392 );
buf ( n4785 , n400 );
buf ( n4786 , n504 );
buf ( n4787 , n2012 );
buf ( n4788 , n1601 );
buf ( n4789 , n657 );
buf ( n4790 , n399 );
buf ( n4791 , n1203 );
buf ( n4792 , n1266 );
buf ( n4793 , n1430 );
buf ( n4794 , n2076 );
buf ( n4795 , n1953 );
buf ( n4796 , n1234 );
buf ( n4797 , n257 );
buf ( n4798 , n2085 );
buf ( n4799 , n510 );
buf ( n4800 , n1923 );
buf ( n4801 , n2155 );
buf ( n4802 , n1629 );
buf ( n4803 , n39 );
buf ( n4804 , n830 );
buf ( n4805 , n1576 );
buf ( n4806 , n625 );
buf ( n4807 , n1418 );
buf ( n4808 , n1634 );
buf ( n4809 , n1855 );
buf ( n4810 , n1982 );
buf ( n4811 , n271 );
buf ( n4812 , n1286 );
buf ( n4813 , n396 );
buf ( n4814 , n405 );
buf ( n4815 , n1113 );
buf ( n4816 , n1843 );
buf ( n4817 , n672 );
buf ( n4818 , n2003 );
buf ( n4819 , n2088 );
buf ( n4820 , n317 );
buf ( n4821 , n727 );
buf ( n4822 , n603 );
buf ( n4823 , n1786 );
buf ( n4824 , n1688 );
buf ( n4825 , n67 );
buf ( n4826 , n2099 );
buf ( n4827 , n339 );
buf ( n4828 , n1553 );
buf ( n4829 , n180 );
buf ( n4830 , n1736 );
buf ( n4831 , n691 );
buf ( n4832 , n1792 );
buf ( n4833 , n1274 );
buf ( n4834 , n436 );
buf ( n4835 , n715 );
buf ( n4836 , n154 );
buf ( n4837 , n705 );
buf ( n4838 , n2042 );
buf ( n4839 , n1909 );
buf ( n4840 , n191 );
buf ( n4841 , n2001 );
buf ( n4842 , n1108 );
buf ( n4843 , n1006 );
buf ( n4844 , n589 );
buf ( n4845 , n1244 );
buf ( n4846 , n2013 );
buf ( n4847 , n369 );
buf ( n4848 , n2124 );
buf ( n4849 , n1636 );
buf ( n4850 , n1525 );
buf ( n4851 , n1198 );
buf ( n4852 , n4 );
buf ( n4853 , n1820 );
buf ( n4854 , n1644 );
buf ( n4855 , n583 );
buf ( n4856 , n356 );
buf ( n4857 , n1978 );
buf ( n4858 , n949 );
buf ( n4859 , n1024 );
buf ( n4860 , n1201 );
buf ( n4861 , n562 );
buf ( n4862 , n633 );
buf ( n4863 , n350 );
buf ( n4864 , n1643 );
buf ( n4865 , n651 );
buf ( n4866 , n882 );
buf ( n4867 , n2036 );
buf ( n4868 , n397 );
buf ( n4869 , n2175 );
buf ( n4870 , n15 );
buf ( n4871 , n390 );
buf ( n4872 , n897 );
buf ( n4873 , n1277 );
buf ( n4874 , n971 );
buf ( n4875 , n3 );
buf ( n4876 , n1185 );
buf ( n4877 , n1853 );
buf ( n4878 , n2134 );
buf ( n4879 , n1841 );
buf ( n4880 , n54 );
buf ( n4881 , n769 );
buf ( n4882 , n1474 );
buf ( n4883 , n1327 );
buf ( n4884 , n332 );
buf ( n4885 , n690 );
buf ( n4886 , n1453 );
buf ( n4887 , n2139 );
buf ( n4888 , n368 );
buf ( n4889 , n2110 );
buf ( n4890 , n2121 );
buf ( n4891 , n645 );
buf ( n4892 , n1294 );
buf ( n4893 , n1936 );
buf ( n4894 , n211 );
buf ( n4895 , n1099 );
buf ( n4896 , n1763 );
buf ( n4897 , n785 );
buf ( n4898 , n108 );
buf ( n4899 , n703 );
buf ( n4900 , n1310 );
buf ( n4901 , n1399 );
buf ( n4902 , n1184 );
buf ( n4903 , n609 );
buf ( n4904 , n275 );
buf ( n4905 , n1619 );
buf ( n4906 , n1117 );
buf ( n4907 , n903 );
buf ( n4908 , n1839 );
buf ( n4909 , n907 );
buf ( n4910 , n1128 );
buf ( n4911 , n926 );
buf ( n4912 , n1623 );
buf ( n4913 , n1939 );
buf ( n4914 , n1661 );
buf ( n4915 , n10 );
buf ( n4916 , n462 );
buf ( n4917 , n1393 );
buf ( n4918 , n1774 );
buf ( n4919 , n2177 );
buf ( n4920 , n525 );
buf ( n4921 , n756 );
buf ( n4922 , n343 );
buf ( n4923 , n28 );
buf ( n4924 , n1124 );
buf ( n4925 , n1523 );
buf ( n4926 , n1772 );
buf ( n4927 , n2170 );
buf ( n4928 , n1750 );
buf ( n4929 , n1050 );
buf ( n4930 , n596 );
buf ( n4931 , n741 );
buf ( n4932 , n344 );
buf ( n4933 , n1960 );
buf ( n4934 , n1088 );
buf ( n4935 , n1183 );
buf ( n4936 , n1511 );
buf ( n4937 , n1779 );
buf ( n4938 , n1089 );
buf ( n4939 , n655 );
buf ( n4940 , n2045 );
buf ( n4941 , n573 );
buf ( n4942 , n1473 );
buf ( n4943 , n736 );
buf ( n4944 , n1349 );
buf ( n4945 , n2055 );
buf ( n4946 , n977 );
buf ( n4947 , n1613 );
buf ( n4948 , n920 );
buf ( n4949 , n311 );
buf ( n4950 , n414 );
buf ( n4951 , n1235 );
buf ( n4952 , n1156 );
buf ( n4953 , n1367 );
buf ( n4954 , n684 );
buf ( n4955 , n1181 );
buf ( n4956 , n33 );
buf ( n4957 , n2147 );
buf ( n4958 , n885 );
buf ( n4959 , n112 );
buf ( n4960 , n658 );
buf ( n4961 , n721 );
buf ( n4962 , n918 );
buf ( n4963 , n373 );
buf ( n4964 , n1284 );
buf ( n4965 , n531 );
buf ( n4966 , n2097 );
buf ( n4967 , n283 );
buf ( n4968 , n739 );
buf ( n4969 , n1723 );
buf ( n4970 , n1172 );
buf ( n4971 , n1627 );
buf ( n4972 , n1251 );
buf ( n4973 , n2031 );
buf ( n4974 , n1196 );
buf ( n4975 , n606 );
buf ( n4976 , n836 );
buf ( n4977 , n988 );
buf ( n4978 , n2002 );
buf ( n4979 , n996 );
buf ( n4980 , n393 );
buf ( n4981 , n2164 );
buf ( n4982 , n2172 );
buf ( n4983 , n491 );
buf ( n4984 , n745 );
buf ( n4985 , n1498 );
buf ( n4986 , n928 );
buf ( n4987 , n1390 );
buf ( n4988 , n1514 );
buf ( n4989 , n265 );
buf ( n4990 , n454 );
buf ( n4991 , n1220 );
buf ( n4992 , n899 );
buf ( n4993 , n300 );
buf ( n4994 , n227 );
buf ( n4995 , n2092 );
buf ( n4996 , n1633 );
buf ( n4997 , n750 );
buf ( n4998 , n245 );
buf ( n4999 , n1782 );
buf ( n5000 , n930 );
buf ( n5001 , n2116 );
buf ( n5002 , n1747 );
buf ( n5003 , n772 );
buf ( n5004 , n538 );
buf ( n5005 , n1987 );
buf ( n5006 , n26 );
buf ( n5007 , n917 );
buf ( n5008 , n1479 );
buf ( n5009 , n643 );
buf ( n5010 , n789 );
buf ( n5011 , n1858 );
buf ( n5012 , n1370 );
buf ( n5013 , n1535 );
buf ( n5014 , n87 );
buf ( n5015 , n156 );
buf ( n5016 , n1397 );
buf ( n5017 , n1790 );
buf ( n5018 , n342 );
buf ( n5019 , n837 );
buf ( n5020 , n446 );
buf ( n5021 , n1914 );
buf ( n5022 , n1452 );
buf ( n5023 , n1232 );
buf ( n5024 , n161 );
buf ( n5025 , n1053 );
buf ( n5026 , n186 );
buf ( n5027 , n304 );
buf ( n5028 , n779 );
buf ( n5029 , n2023 );
buf ( n5030 , n239 );
buf ( n5031 , n258 );
buf ( n5032 , n1257 );
buf ( n5033 , n2010 );
buf ( n5034 , n340 );
buf ( n5035 , n432 );
buf ( n5036 , n693 );
buf ( n5037 , n1130 );
buf ( n5038 , n558 );
buf ( n5039 , n636 );
buf ( n5040 , n2006 );
buf ( n5041 , n1022 );
buf ( n5042 , n1301 );
buf ( n5043 , n1374 );
buf ( n5044 , n1904 );
buf ( n5045 , n1549 );
buf ( n5046 , n226 );
buf ( n5047 , n5 );
buf ( n5048 , n489 );
buf ( n5049 , n685 );
buf ( n5050 , n394 );
buf ( n5051 , n1326 );
buf ( n5052 , n249 );
buf ( n5053 , n916 );
buf ( n5054 , n65 );
buf ( n5055 , n1694 );
buf ( n5056 , n314 );
buf ( n5057 , n1335 );
buf ( n5058 , n1336 );
buf ( n5059 , n1258 );
buf ( n5060 , n1093 );
buf ( n5061 , n570 );
buf ( n5062 , n1766 );
buf ( n5063 , n1458 );
buf ( n5064 , n1137 );
buf ( n5065 , n817 );
buf ( n5066 , n581 );
buf ( n5067 , n911 );
buf ( n5068 , n2070 );
buf ( n5069 , n563 );
buf ( n5070 , n820 );
buf ( n5071 , n941 );
buf ( n5072 , n1202 );
buf ( n5073 , n80 );
buf ( n5074 , n708 );
buf ( n5075 , n1513 );
buf ( n5076 , n367 );
buf ( n5077 , n416 );
buf ( n5078 , n162 );
buf ( n5079 , n1119 );
buf ( n5080 , n555 );
buf ( n5081 , n648 );
buf ( n5082 , n860 );
buf ( n5083 , n334 );
buf ( n5084 , n165 );
buf ( n5085 , n838 );
buf ( n5086 , n1173 );
buf ( n5087 , n1187 );
buf ( n5088 , n1488 );
buf ( n5089 , n307 );
buf ( n5090 , n1552 );
buf ( n5091 , n1828 );
buf ( n5092 , n892 );
buf ( n5093 , n1868 );
buf ( n5094 , n1219 );
buf ( n5095 , n2142 );
buf ( n5096 , n8 );
buf ( n5097 , n371 );
buf ( n5098 , n153 );
buf ( n5099 , n1123 );
buf ( n5100 , n1343 );
buf ( n5101 , n1994 );
buf ( n5102 , n1738 );
buf ( n5103 , n0 );
buf ( n5104 , n1255 );
buf ( n5105 , n463 );
buf ( n5106 , n612 );
buf ( n5107 , n1118 );
buf ( n5108 , n200 );
buf ( n5109 , n301 );
buf ( n5110 , n476 );
buf ( n5111 , n1168 );
buf ( n5112 , n244 );
buf ( n5113 , n1876 );
buf ( n5114 , n138 );
buf ( n5115 , n1700 );
buf ( n5116 , n1484 );
buf ( n5117 , n1217 );
buf ( n5118 , n883 );
buf ( n5119 , n401 );
buf ( n5120 , n1863 );
buf ( n5121 , n896 );
buf ( n5122 , n149 );
buf ( n5123 , n1596 );
buf ( n5124 , n1592 );
buf ( n5125 , n652 );
buf ( n5126 , n352 );
buf ( n5127 , n203 );
buf ( n5128 , n744 );
buf ( n5129 , n986 );
buf ( n5130 , n1121 );
buf ( n5131 , n1773 );
buf ( n5132 , n966 );
buf ( n5133 , n386 );
buf ( n5134 , n2145 );
buf ( n5135 , n582 );
buf ( n5136 , n1721 );
buf ( n5137 , n1455 );
buf ( n5138 , n1561 );
buf ( n5139 , n747 );
buf ( n5140 , n475 );
buf ( n5141 , n142 );
buf ( n5142 , n1568 );
buf ( n5143 , n1073 );
buf ( n5144 , n2112 );
buf ( n5145 , n2044 );
buf ( n5146 , n2181 );
buf ( n5147 , n176 );
buf ( n5148 , n1483 );
buf ( n5149 , n492 );
buf ( n5150 , n83 );
buf ( n5151 , n1268 );
buf ( n5152 , n472 );
buf ( n5153 , n723 );
buf ( n5154 , n613 );
buf ( n5155 , n101 );
buf ( n5156 , n1769 );
buf ( n5157 , n1363 );
buf ( n5158 , n554 );
buf ( n5159 , n1192 );
buf ( n5160 , n1709 );
buf ( n5161 , n1152 );
buf ( n5162 , n450 );
buf ( n5163 , n1583 );
buf ( n5164 , n1364 );
buf ( n5165 , n1911 );
buf ( n5166 , n459 );
buf ( n5167 , n2106 );
buf ( n5168 , n242 );
buf ( n5169 , n1887 );
buf ( n5170 , n169 );
buf ( n5171 , n1794 );
buf ( n5172 , n654 );
buf ( n5173 , n469 );
buf ( n5174 , n823 );
buf ( n5175 , n1710 );
buf ( n5176 , n788 );
buf ( n5177 , n1467 );
buf ( n5178 , n889 );
buf ( n5179 , n1279 );
buf ( n5180 , n1873 );
buf ( n5181 , n782 );
buf ( n5182 , n1764 );
buf ( n5183 , n1866 );
buf ( n5184 , n1197 );
buf ( n5185 , n1107 );
buf ( n5186 , n1574 );
buf ( n5187 , n1459 );
buf ( n5188 , n848 );
buf ( n5189 , n1322 );
buf ( n5190 , n841 );
buf ( n5191 , n768 );
buf ( n5192 , n1296 );
buf ( n5193 , n365 );
buf ( n5194 , n653 );
buf ( n5195 , n428 );
buf ( n5196 , n1865 );
buf ( n5197 , n1369 );
buf ( n5198 , n2032 );
buf ( n5199 , n133 );
buf ( n5200 , n1814 );
buf ( n5201 , n1817 );
buf ( n5202 , n2133 );
buf ( n5203 , n972 );
buf ( n5204 , n1943 );
buf ( n5205 , n1888 );
buf ( n5206 , n1423 );
buf ( n5207 , n757 );
buf ( n5208 , n480 );
buf ( n5209 , n937 );
buf ( n5210 , n1354 );
buf ( n5211 , n1446 );
buf ( n5212 , n1 );
buf ( n5213 , n919 );
buf ( n5214 , n679 );
buf ( n5215 , n113 );
buf ( n5216 , n1395 );
buf ( n5217 , n1391 );
buf ( n5218 , n2065 );
buf ( n5219 , n1078 );
buf ( n5220 , n1245 );
buf ( n5221 , n117 );
buf ( n5222 , n1571 );
buf ( n5223 , n1684 );
buf ( n5224 , n424 );
buf ( n5225 , n1016 );
buf ( n5226 , n1730 );
buf ( n5227 , n1465 );
buf ( n5228 , n2005 );
buf ( n5229 , n791 );
buf ( n5230 , n994 );
buf ( n5231 , n417 );
buf ( n5232 , n1557 );
buf ( n5233 , n536 );
buf ( n5234 , n947 );
buf ( n5235 , n696 );
buf ( n5236 , n755 );
buf ( n5237 , n1499 );
buf ( n5238 , n1756 );
buf ( n5239 , n1328 );
buf ( n5240 , n1338 );
buf ( n5241 , n496 );
buf ( n5242 , n282 );
buf ( n5243 , n1486 );
buf ( n5244 , n1503 );
buf ( n5245 , n2162 );
buf ( n5246 , n1869 );
buf ( n5247 , n1444 );
buf ( n5248 , n1303 );
buf ( n5249 , n700 );
buf ( n5250 , n992 );
buf ( n5251 , n1160 );
buf ( n5252 , n1585 );
buf ( n5253 , n238 );
buf ( n5254 , n11 );
buf ( n5255 , n1951 );
buf ( n5256 , n2016 );
buf ( n5257 , n349 );
buf ( n5258 , n1950 );
buf ( n5259 , n895 );
buf ( n5260 , n1577 );
buf ( n5261 , n1416 );
buf ( n5262 , n1388 );
buf ( n5263 , n929 );
buf ( n5264 , n1018 );
buf ( n5265 , n106 );
buf ( n5266 , n1346 );
buf ( n5267 , n1231 );
buf ( n5268 , n758 );
buf ( n5269 , n448 );
buf ( n5270 , n1510 );
buf ( n5271 , n213 );
buf ( n5272 , n443 );
buf ( n5273 , n1655 );
buf ( n5274 , n1036 );
buf ( n5275 , n751 );
buf ( n5276 , n1674 );
buf ( n5277 , n1811 );
buf ( n5278 , n1208 );
buf ( n5279 , n1230 );
buf ( n5280 , n601 );
buf ( n5281 , n697 );
buf ( n5282 , n1045 );
buf ( n5283 , n1332 );
buf ( n5284 , n29 );
buf ( n5285 , n997 );
buf ( n5286 , n1797 );
buf ( n5287 , n1031 );
buf ( n5288 , n1681 );
buf ( n5289 , n171 );
buf ( n5290 , n2146 );
buf ( n5291 , n894 );
buf ( n5292 , n207 );
buf ( n5293 , n223 );
buf ( n5294 , n1539 );
buf ( n5295 , n840 );
buf ( n5296 , n1968 );
buf ( n5297 , n224 );
buf ( n5298 , n978 );
buf ( n5299 , n1938 );
buf ( n5300 , n1680 );
buf ( n5301 , n1966 );
buf ( n5302 , n210 );
buf ( n5303 , n498 );
buf ( n5304 , n351 );
buf ( n5305 , n676 );
buf ( n5306 , n406 );
buf ( n5307 , n194 );
buf ( n5308 , n1347 );
buf ( n5309 , n1457 );
buf ( n5310 , n437 );
buf ( n5311 , n855 );
buf ( n5312 , n752 );
buf ( n5313 , n1622 );
buf ( n5314 , n19 );
buf ( n5315 , n1614 );
buf ( n5316 , n961 );
buf ( n5317 , n260 );
buf ( n5318 , n1072 );
buf ( n5319 , n1040 );
buf ( n5320 , n1141 );
buf ( n5321 , n1426 );
buf ( n5322 , n1057 );
buf ( n5323 , n2159 );
buf ( n5324 , n95 );
buf ( n5325 , n114 );
buf ( n5326 , n1477 );
buf ( n5327 , n1106 );
buf ( n5328 , n466 );
buf ( n5329 , n783 );
buf ( n5330 , n1263 );
buf ( n5331 , n255 );
buf ( n5332 , n46 );
buf ( n5333 , n1945 );
buf ( n5334 , n1706 );
buf ( n5335 , n20 );
buf ( n5336 , n585 );
buf ( n5337 , n259 );
buf ( n5338 , n477 );
buf ( n5339 , n64 );
buf ( n5340 , n269 );
buf ( n5341 , n1329 );
buf ( n5342 , n1081 );
buf ( n5343 , n1944 );
buf ( n5344 , n1605 );
buf ( n5345 , n1309 );
buf ( n5346 , n2038 );
buf ( n5347 , n1974 );
buf ( n5348 , n1758 );
buf ( n5349 , n1908 );
buf ( n5350 , n1456 );
buf ( n5351 , n1295 );
buf ( n5352 , n1240 );
buf ( n5353 , n1720 );
buf ( n5354 , n1990 );
buf ( n5355 , n464 );
buf ( n5356 , n2120 );
buf ( n5357 , n1207 );
buf ( n5358 , n599 );
buf ( n5359 , n533 );
buf ( n5360 , n802 );
buf ( n5361 , n1092 );
buf ( n5362 , n1879 );
buf ( n5363 , n584 );
buf ( n5364 , n780 );
buf ( n5365 , n1299 );
buf ( n5366 , n1631 );
buf ( n5367 , n952 );
buf ( n5368 , n1564 );
buf ( n5369 , n1414 );
buf ( n5370 , n361 );
buf ( n5371 , n1729 );
buf ( n5372 , n1451 );
buf ( n5373 , n831 );
buf ( n5374 , n660 );
buf ( n5375 , n826 );
buf ( n5376 , n2020 );
buf ( n5377 , n922 );
buf ( n5378 , n1754 );
buf ( n5379 , n1515 );
buf ( n5380 , n1317 );
buf ( n5381 , n2127 );
buf ( n5382 , n118 );
buf ( n5383 , n1030 );
buf ( n5384 , n440 );
buf ( n5385 , n1250 );
buf ( n5386 , n979 );
buf ( n5387 , n1001 );
buf ( n5388 , n640 );
buf ( n5389 , n1135 );
buf ( n5390 , n821 );
buf ( n5391 , n550 );
buf ( n5392 , n189 );
buf ( n5393 , n1237 );
buf ( n5394 , n453 );
buf ( n5395 , n1928 );
buf ( n5396 , n873 );
buf ( n5397 , n1606 );
buf ( n5398 , n794 );
buf ( n5399 , n888 );
buf ( n5400 , n1621 );
buf ( n5401 , n385 );
buf ( n5402 , n1983 );
buf ( n5403 , n1902 );
buf ( n5404 , n1212 );
buf ( n5405 , n184 );
buf ( n5406 , n102 );
buf ( n5407 , n422 );
buf ( n5408 , n1407 );
buf ( n5409 , n285 );
buf ( n5410 , n1952 );
buf ( n5411 , n1429 );
buf ( n5412 , n1827 );
buf ( n5413 , n712 );
buf ( n5414 , n674 );
buf ( n5415 , n912 );
buf ( n5416 , n875 );
buf ( n5417 , n887 );
buf ( n5418 , n1929 );
buf ( n5419 , n278 );
buf ( n5420 , n1408 );
buf ( n5421 , n1481 );
buf ( n5422 , n1496 );
buf ( n5423 , n246 );
buf ( n5424 , n2119 );
buf ( n5425 , n1999 );
buf ( n5426 , n2117 );
buf ( n5427 , n338 );
buf ( n5428 , n1699 );
buf ( n5429 , n2135 );
buf ( n5430 , n1755 );
buf ( n5431 , n1358 );
buf ( n5432 , n287 );
buf ( n5433 , n2050 );
buf ( n5434 , n1312 );
buf ( n5435 , n1716 );
buf ( n5436 , n1587 );
buf ( n5437 , n1246 );
buf ( n5438 , n1249 );
buf ( n5439 , n384 );
buf ( n5440 , n1262 );
buf ( n5441 , n408 );
buf ( n5442 , n680 );
buf ( n5443 , n2174 );
buf ( n5444 , n1051 );
buf ( n5445 , n2118 );
buf ( n5446 , n1803 );
buf ( n5447 , n560 );
buf ( n5448 , n1278 );
buf ( n5449 , n1344 );
buf ( n5450 , n1996 );
buf ( n5451 , n2053 );
buf ( n5452 , n1878 );
buf ( n5453 , n999 );
buf ( n5454 , n1651 );
buf ( n5455 , n374 );
buf ( n5456 , n1903 );
buf ( n5457 , n946 );
buf ( n5458 , n395 );
buf ( n5459 , n1013 );
buf ( n5460 , n286 );
buf ( n5461 , n872 );
buf ( n5462 , n1043 );
buf ( n5463 , n1546 );
buf ( n5464 , n1506 );
buf ( n5465 , n934 );
buf ( n5466 , n2101 );
buf ( n5467 , n1403 );
buf ( n5468 , n1912 );
buf ( n5469 , n730 );
buf ( n5470 , n567 );
buf ( n5471 , n1832 );
buf ( n5472 , n150 );
buf ( n5473 , n702 );
buf ( n5474 , n1609 );
buf ( n5475 , n276 );
buf ( n5476 , n1462 );
buf ( n5477 , n232 );
buf ( n5478 , n62 );
buf ( n5479 , n1657 );
buf ( n5480 , n215 );
buf ( n5481 , n1521 );
buf ( n5482 , n48 );
buf ( n5483 , n798 );
buf ( n5484 , n71 );
buf ( n5485 , n1771 );
buf ( n5486 , n1044 );
buf ( n5487 , n965 );
buf ( n5488 , n1224 );
buf ( n5489 , n1886 );
buf ( n5490 , n1526 );
buf ( n5491 , n1835 );
buf ( n5492 , n553 );
buf ( n5493 , n650 );
buf ( n5494 , n1162 );
buf ( n5495 , n2184 );
buf ( n5496 , n160 );
buf ( n5497 , n1848 );
buf ( n5498 , n991 );
buf ( n5499 , n1784 );
buf ( n5500 , n360 );
buf ( n5501 , n281 );
buf ( n5502 , n1981 );
buf ( n5503 , n1063 );
buf ( n5504 , n1804 );
buf ( n5505 , n1897 );
buf ( n5506 , n219 );
buf ( n5507 , n1696 );
buf ( n5508 , n1150 );
buf ( n5509 , n140 );
buf ( n5510 , n506 );
buf ( n5511 , n1002 );
buf ( n5512 , n481 );
buf ( n5513 , n445 );
buf ( n5514 , n319 );
buf ( n5515 , n974 );
buf ( n5516 , n92 );
buf ( n5517 , n635 );
buf ( n5518 , n1037 );
buf ( n5519 , n1578 );
buf ( n5520 , n1180 );
buf ( n5521 , n1143 );
buf ( n5522 , n482 );
buf ( n5523 , n900 );
buf ( n5524 , n767 );
buf ( n5525 , n1664 );
buf ( n5526 , n144 );
buf ( n5527 , n60 );
buf ( n5528 , n69 );
buf ( n5529 , n2096 );
buf ( n5530 , n1611 );
buf ( n5531 , n677 );
buf ( n5532 , n1079 );
buf ( n5533 , n1288 );
buf ( n5534 , n345 );
buf ( n5535 , n40 );
buf ( n5536 , n2156 );
buf ( n5537 , n228 );
buf ( n5538 , n833 );
buf ( n5539 , n1163 );
buf ( n5540 , n297 );
buf ( n5541 , n664 );
buf ( n5542 , n192 );
buf ( n5543 , n50 );
buf ( n5544 , n1147 );
buf ( n5545 , n2047 );
buf ( n5546 , n254 );
buf ( n5547 , n923 );
buf ( n5548 , n1958 );
buf ( n5549 , n623 );
buf ( n5550 , n27 );
buf ( n5551 , n104 );
buf ( n5552 , n523 );
buf ( n5553 , n927 );
buf ( n5554 , n1672 );
buf ( n5555 , n438 );
buf ( n5556 , n718 );
buf ( n5557 , n500 );
buf ( n5558 , n766 );
buf ( n5559 , n1104 );
buf ( n5560 , n552 );
buf ( n5561 , n1472 );
buf ( n5562 , n1746 );
buf ( n5563 , n1642 );
buf ( n5564 , n1435 );
buf ( n5565 , n1253 );
buf ( n5566 , n2161 );
buf ( n5567 , n1824 );
buf ( n5568 , n1926 );
buf ( n5569 , n1891 );
buf ( n5570 , n905 );
buf ( n5571 , n1901 );
buf ( n5572 , n2122 );
buf ( n5573 , n1516 );
buf ( n5574 , n2166 );
buf ( n5575 , n1870 );
buf ( n5576 , n429 );
buf ( n5577 , n379 );
buf ( n5578 , n465 );
buf ( n5579 , n933 );
buf ( n5580 , n1693 );
buf ( n5581 , n1930 );
buf ( n5582 , n1146 );
buf ( n5583 , n1341 );
buf ( n5584 , n1404 );
buf ( n5585 , n2058 );
buf ( n5586 , n1134 );
buf ( n5587 , n274 );
buf ( n5588 , n898 );
buf ( n5589 , n1658 );
buf ( n5590 , n1084 );
buf ( n5591 , n25 );
buf ( n5592 , n717 );
buf ( n5593 , n1076 );
buf ( n5594 , n816 );
buf ( n5595 , n732 );
buf ( n5596 , n1256 );
buf ( n5597 , n669 );
buf ( n5598 , n471 );
buf ( n5599 , n595 );
buf ( n5600 , n1669 );
buf ( n5601 , n1713 );
buf ( n5602 , n1190 );
buf ( n5603 , n212 );
buf ( n5604 , n1618 );
buf ( n5605 , n576 );
buf ( n5606 , n1480 );
buf ( n5607 , n1214 );
buf ( n5608 , n1984 );
buf ( n5609 , n753 );
buf ( n5610 , n1379 );
buf ( n5611 , n1238 );
buf ( n5612 , n1437 );
buf ( n5613 , n174 );
buf ( n5614 , n1890 );
buf ( n5615 , n535 );
buf ( n5616 , n136 );
buf ( n5617 , n2163 );
buf ( n5618 , n177 );
buf ( n5619 , n1579 );
buf ( n5620 , n1973 );
buf ( n5621 , n709 );
buf ( n5622 , n1417 );
buf ( n5623 , n1394 );
buf ( n5624 , n692 );
buf ( n5625 , n1154 );
buf ( n5626 , n1373 );
buf ( n5627 , n479 );
buf ( n5628 , n1676 );
buf ( n5629 , n1954 );
buf ( n5630 , n202 );
buf ( n5631 , n1471 );
buf ( n5632 , n1685 );
buf ( n5633 , n842 );
buf ( n5634 , n1590 );
buf ( n5635 , n1748 );
buf ( n5636 , n1259 );
buf ( n5637 , n458 );
buf ( n5638 , n981 );
buf ( n5639 , n1461 );
buf ( n5640 , n2151 );
buf ( n5641 , n557 );
buf ( n5642 , n843 );
buf ( n5643 , n893 );
buf ( n5644 , n748 );
buf ( n5645 , n431 );
buf ( n5646 , n145 );
buf ( n5647 , n1550 );
buf ( n5648 , n2100 );
buf ( n5649 , n88 );
buf ( n5650 , n1324 );
buf ( n5651 , n2046 );
buf ( n5652 , n2077 );
buf ( n5653 , n1325 );
buf ( n5654 , n293 );
buf ( n5655 , n1705 );
buf ( n5656 , n1476 );
buf ( n5657 , n2138 );
buf ( n5658 , n2141 );
buf ( n5659 , n488 );
buf ( n5660 , n1485 );
buf ( n5661 , n1737 );
buf ( n5662 , n2149 );
buf ( n5663 , n615 );
buf ( n5664 , n1080 );
buf ( n5665 , n1872 );
buf ( n5666 , n925 );
buf ( n5667 , n762 );
buf ( n5668 , n631 );
buf ( n5669 , n2179 );
buf ( n5670 , n1805 );
buf ( n5671 , n626 );
buf ( n5672 , n51 );
buf ( n5673 , n1385 );
buf ( n5674 , n738 );
buf ( n5675 , n1221 );
buf ( n5676 , n1302 );
buf ( n5677 , n115 );
buf ( n5678 , n2143 );
buf ( n5679 , n412 );
buf ( n5680 , n507 );
buf ( n5681 , n1164 );
buf ( n5682 , n1282 );
buf ( n5683 , n94 );
buf ( n5684 , n1862 );
buf ( n5685 , n607 );
buf ( n5686 , n521 );
buf ( n5687 , n1541 );
buf ( n5688 , n1647 );
buf ( n5689 , n1438 );
buf ( n5690 , n1895 );
buf ( n5691 , n641 );
buf ( n5692 , n604 );
buf ( n5693 , n673 );
buf ( n5694 , n1334 );
buf ( n5695 , n1735 );
buf ( n5696 , n1751 );
buf ( n5697 , n629 );
buf ( n5698 , n1034 );
buf ( n5699 , n1439 );
buf ( n5700 , n1522 );
buf ( n5701 , n273 );
buf ( n5702 , n1167 );
buf ( n5703 , n1972 );
buf ( n5704 , n444 );
buf ( n5705 , n1011 );
buf ( n5706 , n280 );
buf ( n5707 , n323 );
buf ( n5708 , n59 );
buf ( n5709 , n2111 );
buf ( n5710 , n1283 );
buf ( n5711 , n256 );
buf ( n5712 , n326 );
buf ( n5713 , n829 );
buf ( n5714 , n1789 );
buf ( n5715 , n1353 );
buf ( n5716 , n857 );
buf ( n5717 , n1816 );
buf ( n5718 , n2049 );
buf ( n5719 , n610 );
buf ( n5720 , n1701 );
buf ( n5721 , n847 );
buf ( n5722 , n1612 );
buf ( n5723 , n493 );
buf ( n5724 , n1645 );
buf ( n5725 , n1991 );
buf ( n5726 , n1704 );
buf ( n5727 , n1743 );
buf ( n5728 , n2067 );
buf ( n5729 , n619 );
buf ( n5730 , n874 );
buf ( n5731 , n976 );
buf ( n5732 , n1906 );
buf ( n5733 , n2014 );
buf ( n5734 , n328 );
buf ( n5735 , n1355 );
buf ( n5736 , n942 );
buf ( n5737 , n1993 );
buf ( n5738 , n1010 );
buf ( n5739 , n540 );
buf ( n5740 , n23 );
buf ( n5741 , n948 );
buf ( n5742 , n1380 );
buf ( n5743 , n1776 );
buf ( n5744 , n1372 );
buf ( n5745 , n148 );
buf ( n5746 , n819 );
buf ( n5747 , n511 );
buf ( n5748 , n6 );
buf ( n5749 , n526 );
buf ( n5750 , n1433 );
buf ( n5751 , n803 );
buf ( n5752 , n1697 );
buf ( n5753 , n773 );
buf ( n5754 , n503 );
buf ( n5755 , n1781 );
buf ( n5756 , n1098 );
buf ( n5757 , n1112 );
buf ( n5758 , n1138 );
buf ( n5759 , n1199 );
buf ( n5760 , n1157 );
buf ( n5761 , n456 );
buf ( n5762 , n944 );
buf ( n5763 , n754 );
buf ( n5764 , n247 );
buf ( n5765 , n985 );
buf ( n5766 , n982 );
buf ( n5767 , n666 );
buf ( n5768 , n1588 );
buf ( n5769 , n760 );
buf ( n5770 , n574 );
buf ( n5771 , n58 );
buf ( n5772 , n534 );
buf ( n5773 , n2034 );
buf ( n5774 , n2008 );
buf ( n5775 , n529 );
buf ( n5776 , n1992 );
buf ( n5777 , n163 );
buf ( n5778 , n134 );
buf ( n5779 , n868 );
buf ( n5780 , n1915 );
buf ( n5781 , n2028 );
buf ( n5782 , n594 );
buf ( n5783 , n694 );
buf ( n5784 , n1942 );
buf ( n5785 , n671 );
buf ( n5786 , n1560 );
buf ( n5787 , n1348 );
buf ( n5788 , n1103 );
buf ( n5789 , n667 );
buf ( n5790 , n1071 );
buf ( n5791 , n447 );
buf ( n5792 , n1191 );
buf ( n5793 , n1371 );
buf ( n5794 , n279 );
buf ( n5795 , n1707 );
buf ( n5796 , n1844 );
buf ( n5797 , n1544 );
buf ( n5798 , n1345 );
buf ( n5799 , n1066 );
buf ( n5800 , n591 );
buf ( n5801 , n363 );
buf ( n5802 , n335 );
buf ( n5803 , n787 );
buf ( n5804 , n2079 );
buf ( n5805 , n1065 );
buf ( n5806 , n891 );
buf ( n5807 , n1650 );
buf ( n5808 , n45 );
buf ( n5809 , n1823 );
buf ( n5810 , n1881 );
buf ( n5811 , n797 );
buf ( n5812 , n1626 );
buf ( n5813 , n402 );
buf ( n5814 , n1833 );
buf ( n5815 , n2000 );
buf ( n5816 , n955 );
buf ( n5817 , n714 );
buf ( n5818 , n30 );
buf ( n5819 , n1091 );
buf ( n5820 , n954 );
buf ( n5821 , n1599 );
buf ( n5822 , n960 );
buf ( n5823 , n1542 );
buf ( n5824 , n774 );
buf ( n5825 , n795 );
buf ( n5826 , n1518 );
buf ( n5827 , n1527 );
buf ( n5828 , n1087 );
buf ( n5829 , n193 );
buf ( n5830 , n141 );
buf ( n5831 , n1594 );
buf ( n5832 , n1500 );
buf ( n5833 , n1826 );
buf ( n5834 , n1041 );
buf ( n5835 , n1925 );
buf ( n5836 , n2030 );
buf ( n5837 , n1493 );
buf ( n5838 , n1005 );
buf ( n5839 , n225 );
buf ( n5840 , n77 );
buf ( n5841 , n2109 );
buf ( n5842 , n1482 );
buf ( n5843 , n14 );
buf ( n5844 , n434 );
buf ( n5845 , n1662 );
buf ( n5846 , n1311 );
buf ( n5847 , n376 );
buf ( n5848 , n1261 );
buf ( n5849 , n1019 );
buf ( n5850 , n2015 );
buf ( n5851 , n78 );
buf ( n5852 , n637 );
buf ( n5853 , n1964 );
buf ( n5854 , n1174 );
buf ( n5855 , n442 );
buf ( n5856 , n1434 );
buf ( n5857 , n1061 );
buf ( n5858 , n1490 );
buf ( n5859 , n329 );
buf ( n5860 , n810 );
buf ( n5861 , n850 );
buf ( n5862 , n1377 );
buf ( n5863 , n2167 );
buf ( n5864 , n846 );
buf ( n5865 , n315 );
buf ( n5866 , n1687 );
buf ( n5867 , n1864 );
buf ( n5868 , n1122 );
buf ( n5869 , n2108 );
buf ( n5870 , n956 );
buf ( n5871 , n1829 );
buf ( n5872 , n1671 );
buf ( n5873 , n852 );
buf ( n5874 , n1686 );
buf ( n5875 , n544 );
buf ( n5876 , n35 );
buf ( n5877 , n2078 );
buf ( n5878 , n7 );
buf ( n5879 , n357 );
buf ( n5880 , n1215 );
buf ( n5881 , n2169 );
buf ( n5882 , n1025 );
buf ( n5883 , n1856 );
buf ( n5884 , n1607 );
buf ( n5885 , n321 );
buf ( n5886 , n166 );
buf ( n5887 , n939 );
buf ( n5888 , n602 );
buf ( n5889 , n914 );
buf ( n5890 , n2104 );
buf ( n5891 , n1048 );
buf ( n5892 , n849 );
buf ( n5893 , n1360 );
buf ( n5894 , n1356 );
buf ( n5895 , n66 );
buf ( n5896 , n1885 );
buf ( n5897 , n1724 );
buf ( n5898 , n1392 );
buf ( n5899 , n1949 );
buf ( n5900 , n1673 );
buf ( n5901 , n1770 );
buf ( n5902 , n1725 );
buf ( n5903 , n879 );
buf ( n5904 , n1114 );
buf ( n5905 , n1148 );
buf ( n5906 , n270 );
buf ( n5907 , n2154 );
buf ( n5908 , n870 );
buf ( n5909 , n1193 );
buf ( n5910 , n1175 );
buf ( n5911 , n575 );
buf ( n5912 , n125 );
buf ( n5913 , n398 );
buf ( n5914 , n1778 );
buf ( n5915 , n871 );
buf ( n5916 , n1656 );
buf ( n5917 , n449 );
buf ( n5918 , n1382 );
buf ( n5919 , n950 );
buf ( n5920 , n264 );
buf ( n5921 , n1808 );
buf ( n5922 , n1731 );
buf ( n5923 , n347 );
buf ( n5924 , n559 );
buf ( n5925 , n1401 );
buf ( n5926 , n1898 );
buf ( n5927 , n1859 );
buf ( n5928 , n1038 );
buf ( n5929 , n1529 );
buf ( n5930 , n337 );
buf ( n5931 , n565 );
buf ( n5932 , n1910 );
buf ( n5933 , n120 );
buf ( n5934 , n801 );
buf ( n5935 , n1186 );
buf ( n5936 , n1331 );
buf ( n5937 , n1632 );
buf ( n5938 , n318 );
buf ( n5939 , n277 );
buf ( n5940 , n953 );
buf ( n5941 , n147 );
buf ( n5942 , n96 );
buf ( n5943 , n512 );
buf ( n5944 , n580 );
buf ( n5945 , n1242 );
buf ( n5946 , n1342 );
buf ( n5947 , n959 );
buf ( n5948 , n173 );
buf ( n5949 , n1264 );
buf ( n5950 , n1900 );
buf ( n5951 , n2069 );
buf ( n5952 , n983 );
buf ( n5953 , n22 );
buf ( n5954 , n1620 );
buf ( n5955 , n943 );
buf ( n5956 , n910 );
buf ( n5957 , n1292 );
buf ( n5958 , n627 );
buf ( n5959 , n1366 );
buf ( n5960 , n1892 );
buf ( n5961 , n1559 );
buf ( n5962 , n1698 );
buf ( n5963 , n1419 );
buf ( n5964 , n2171 );
buf ( n5965 , n190 );
buf ( n5966 , n122 );
buf ( n5967 , n1236 );
buf ( n5968 , n1468 );
buf ( n5969 , n222 );
buf ( n5970 , n1753 );
buf ( n5971 , n132 );
buf ( n5972 , n1874 );
buf ( n5973 , n647 );
buf ( n5974 , n725 );
buf ( n5975 , n182 );
buf ( n5976 , n877 );
buf ( n5977 , n348 );
buf ( n5978 , n63 );
buf ( n5979 , n289 );
buf ( n5980 , n1055 );
buf ( n5981 , n1540 );
buf ( n5982 , n1744 );
buf ( n5983 , n2113 );
buf ( n5984 , n1837 );
buf ( n5985 , n198 );
buf ( n5986 , n214 );
buf ( n5987 , n1815 );
buf ( n5988 , n1491 );
buf ( n5989 , n818 );
buf ( n5990 , n1204 );
buf ( n5991 , n551 );
buf ( n5992 , n320 );
buf ( n5993 , n2048 );
buf ( n5994 , n825 );
buf ( n5995 , n501 );
buf ( n5996 , n1691 );
buf ( n5997 , n1275 );
buf ( n5998 , n1008 );
buf ( n5999 , n968 );
buf ( n6000 , n1959 );
buf ( n6001 , n178 );
buf ( n6002 , n1986 );
buf ( n6003 , n382 );
buf ( n6004 , n129 );
buf ( n6005 , n1977 );
buf ( n6006 , n1504 );
buf ( n6007 , n649 );
buf ( n6008 , n800 );
buf ( n6009 , n639 );
buf ( n6010 , n1127 );
buf ( n6011 , n303 );
buf ( n6012 , n1424 );
buf ( n6013 , n1155 );
buf ( n6014 , n425 );
buf ( n6015 , n346 );
buf ( n6016 , n1505 );
buf ( n6017 , n642 );
buf ( n6018 , n82 );
buf ( n6019 , n2103 );
buf ( n6020 , n572 );
buf ( n6021 , n743 );
buf ( n6022 , n2026 );
buf ( n6023 , n771 );
buf ( n6024 , n2153 );
buf ( n6025 , n1082 );
buf ( n6026 , n41 );
buf ( n6027 , n1126 );
buf ( n6028 , n298 );
buf ( n6029 , n1151 );
buf ( n6030 , n79 );
buf ( n6031 , n1975 );
buf ( n6032 , n605 );
buf ( n6033 , n1159 );
buf ( n6034 , n248 );
buf ( n6035 , n1570 );
buf ( n6036 , n1969 );
buf ( n6037 , n906 );
buf ( n6038 , n2062 );
buf ( n6039 , n549 );
buf ( n6040 , n1365 );
buf ( n6041 , n441 );
buf ( n6042 , n306 );
buf ( n6043 , n158 );
buf ( n6044 , n1304 );
buf ( n6045 , n617 );
buf ( n6046 , n1116 );
buf ( n6047 , n2025 );
buf ( n6048 , n740 );
buf ( n6049 , n1062 );
buf ( n6050 , n699 );
buf ( n6051 , n1222 );
buf ( n6052 , n706 );
buf ( n6053 , n1136 );
buf ( n6054 , n1492 );
buf ( n6055 , n1860 );
buf ( n6056 , n495 );
buf ( n6057 , n53 );
buf ( n6058 , n262 );
buf ( n6059 , n1718 );
buf ( n6060 , n1109 );
buf ( n6061 , n157 );
buf ( n6062 , n1543 );
buf ( n6063 , n632 );
buf ( n6064 , n1573 );
buf ( n6065 , n188 );
buf ( n6066 , n2004 );
buf ( n6067 , n713 );
buf ( n6068 , n1567 );
buf ( n6069 , n1029 );
buf ( n6070 , n1169 );
buf ( n6071 , n1595 );
buf ( n6072 , n1524 );
buf ( n6073 , n201 );
buf ( n6074 , n2074 );
buf ( n6075 , n866 );
buf ( n6076 , n1102 );
buf ( n6077 , n107 );
buf ( n6078 , n2 );
buf ( n6079 , n931 );
buf ( n6080 , n598 );
buf ( n6081 , n663 );
buf ( n6082 , n2037 );
buf ( n6083 , n179 );
buf ( n6084 , n2160 );
buf ( n6085 , n1775 );
buf ( n6086 , n2180 );
buf ( n6087 , n2052 );
buf ( n6088 , n777 );
buf ( n6089 , n845 );
buf ( n6090 , n1520 );
buf ( n6091 , n2063 );
buf ( n6092 , n1947 );
buf ( n6093 , n1145 );
buf ( n6094 , n1683 );
buf ( n6095 , n1375 );
buf ( n6096 , n1129 );
buf ( n6097 , n209 );
buf ( n6098 , n47 );
buf ( n6099 , n1760 );
buf ( n6100 , n1115 );
buf ( n6101 , n1682 );
buf ( n6102 , n1247 );
buf ( n6103 , n1067 );
buf ( n6104 , n146 );
buf ( n6105 , n1997 );
buf ( n6106 , n973 );
buf ( n6107 , n1830 );
buf ( n6108 , n520 );
buf ( n6109 , n1101 );
buf ( n6110 , n1807 );
buf ( n6111 , n793 );
buf ( n6112 , n662 );
buf ( n6113 , n290 );
buf ( n6114 , n127 );
buf ( n6115 , n1359 );
buf ( n6116 , n1095 );
buf ( n6117 , n776 );
buf ( n6118 , n1161 );
buf ( n6119 , n1689 );
buf ( n6120 , n940 );
buf ( n6121 , n116 );
buf ( n6122 , n2098 );
buf ( n6123 , n1083 );
buf ( n6124 , n109 );
buf ( n6125 , n1854 );
buf ( n6126 , n938 );
buf ( n6127 , n863 );
buf ( n6128 , n1813 );
buf ( n6129 , n38 );
buf ( n6130 , n1962 );
buf ( n6131 , n695 );
buf ( n6132 , n646 );
buf ( n6133 , n1060 );
buf ( n6134 , n1616 );
buf ( n6135 , n1111 );
buf ( n6136 , n634 );
buf ( n6137 , n1894 );
buf ( n6138 , n1899 );
buf ( n6139 , n1233 );
buf ( n6140 , n1097 );
buf ( n6141 , n987 );
buf ( n6142 , n1252 );
buf ( n6143 , n1396 );
buf ( n6144 , n856 );
buf ( n6145 , n2129 );
buf ( n6146 , n220 );
buf ( n6147 , n1921 );
buf ( n6148 , n1069 );
buf ( n6149 , n1042 );
buf ( n6150 , n2035 );
buf ( n6151 , n204 );
buf ( n6152 , n2019 );
buf ( n6153 , n61 );
buf ( n6154 , n1270 );
buf ( n6155 , n2095 );
buf ( n6156 , n775 );
buf ( n6157 , n1449 );
buf ( n6158 , n485 );
buf ( n6159 , n1795 );
buf ( n6160 , n1547 );
buf ( n6161 , n1639 );
buf ( n6162 , n490 );
buf ( n6163 , n2128 );
buf ( n6164 , n2080 );
buf ( n6165 , n1361 );
buf ( n6166 , n1602 );
buf ( n6167 , n689 );
buf ( n6168 , n2059 );
buf ( n6169 , n474 );
buf ( n6170 , n1352 );
buf ( n6171 , n528 );
buf ( n6172 , n1228 );
buf ( n6173 , n1985 );
buf ( n6174 , n1026 );
buf ( n6175 , n2158 );
buf ( n6176 , n1648 );
buf ( n6177 , n1276 );
buf ( n6178 , n128 );
buf ( n6179 , n1617 );
buf ( n6180 , n539 );
buf ( n6181 , n1905 );
buf ( n6182 , n1800 );
buf ( n6183 , n1014 );
buf ( n6184 , n2183 );
buf ( n6185 , n734 );
buf ( n6186 , n1931 );
buf ( n6187 , n1970 );
buf ( n6188 , n1759 );
buf ( n6189 , n1280 );
buf ( n6190 , n759 );
buf ( n6191 , n1941 );
buf ( n6192 , n608 );
buf ( n6193 , n358 );
buf ( n6194 , n497 );
buf ( n6195 , n1339 );
buf ( n6196 , n2068 );
buf ( n6197 , n2057 );
buf ( n6198 , n1842 );
buf ( n6199 , n170 );
buf ( n6200 , n1980 );
buf ( n6201 , n292 );
buf ( n6202 , n185 );
buf ( n6203 , n502 );
buf ( n6204 , n707 );
buf ( n6205 , n126 );
buf ( n6206 , n2131 );
buf ( n6207 , n1920 );
buf ( n6208 , n1593 );
buf ( n6209 , n389 );
buf ( n6210 , n1798 );
buf ( n6211 , n518 );
buf ( n6212 , n508 );
buf ( n6213 , n331 );
buf ( n6214 , n1961 );
buf ( n6215 , n822 );
buf ( n6216 , n611 );
buf ( n6217 , n704 );
buf ( n6218 , n1940 );
buf ( n6219 , n1195 );
buf ( n6220 , n1934 );
buf ( n6221 , n1059 );
buf ( n6222 , n253 );
buf ( n6223 , n1545 );
buf ( n6224 , n2043 );
buf ( n6225 , n1615 );
buf ( n6226 , n1714 );
buf ( n6227 , n1502 );
buf ( n6228 , n1094 );
buf ( n6229 , n234 );
buf ( n6230 , n74 );
buf ( n6231 , n111 );
buf ( n6232 , n1260 );
buf ( n6233 , n183 );
buf ( n6234 , n796 );
buf ( n6235 , n362 );
buf ( n6236 , n784 );
buf ( n6237 , n1131 );
buf ( n6238 , n375 );
buf ( n6239 , n355 );
buf ( n6240 , n828 );
buf ( n6241 , n2081 );
buf ( n6242 , n865 );
buf ( n6243 , n124 );
buf ( n6244 , n670 );
buf ( n6245 , n1445 );
buf ( n6246 , n932 );
buf ( n6247 , n1625 );
buf ( n6248 , n1793 );
buf ( n6249 , n1847 );
buf ( n6250 , n199 );
buf ( n6251 , n364 );
buf ( n6252 , n330 );
buf ( n6253 , n1383 );
buf ( n6254 , n815 );
buf ( n6255 , n509 );
buf ( n6256 , n155 );
buf ( n6257 , n1028 );
buf ( n6258 , n1487 );
buf ( n6259 , n1068 );
buf ( n6260 , n1565 );
buf ( n6261 , n568 );
buf ( n6262 , n468 );
buf ( n6263 , n2072 );
buf ( n6264 , n1531 );
buf ( n6265 , n1254 );
buf ( n6266 , n1387 );
buf ( n6267 , n208 );
buf ( n6268 , n1791 );
buf ( n6269 , n958 );
buf ( n6270 , n990 );
buf ( n6271 , n1845 );
buf ( n6272 , n1653 );
buf ( n6273 , n1517 );
buf ( n6274 , n196 );
buf ( n6275 , n1995 );
buf ( n6276 , n1470 );
buf ( n6277 , n168 );
buf ( n6278 , n105 );
buf ( n6279 , n1381 );
buf ( n6280 , n2123 );
buf ( n6281 , n1799 );
buf ( n6282 , n806 );
buf ( n6283 , n904 );
buf ( n6284 , n119 );
buf ( n6285 , n1875 );
buf ( n6286 , n1297 );
buf ( n6287 , n1663 );
buf ( n6288 , n1469 );
buf ( n6289 , n1624 );
buf ( n6290 , n1015 );
buf ( n6291 , n2125 );
buf ( n6292 , n1211 );
buf ( n6293 , n1027 );
buf ( n6294 , n786 );
buf ( n6295 , n1635 );
buf ( n6296 , n963 );
buf ( n6297 , n1507 );
buf ( n6298 , n52 );
buf ( n6299 , n84 );
buf ( n6300 , n915 );
buf ( n6301 , n1386 );
buf ( n6302 , n1882 );
buf ( n6303 , n164 );
buf ( n6304 , n305 );
buf ( n6305 , n1165 );
buf ( n6306 , n316 );
buf ( n6307 , n1822 );
buf ( n6308 , n998 );
buf ( n6309 , n2064 );
buf ( n6310 , n812 );
buf ( n6311 , n638 );
buf ( n6312 , n1271 );
buf ( n6313 , n1225 );
buf ( n6314 , n807 );
buf ( n6315 , n1415 );
buf ( n6316 , n1406 );
buf ( n6317 , n1020 );
buf ( n6318 , n241 );
buf ( n6319 , n864 );
buf ( n6320 , n683 );
buf ( n6321 , n1411 );
buf ( n6322 , n1440 );
buf ( n6323 , n435 );
buf ( n6324 , n86 );
buf ( n6325 , n1398 );
buf ( n6326 , n403 );
buf ( n6327 , n1600 );
buf ( n6328 , n620 );
buf ( n6329 , n378 );
buf ( n6330 , n1979 );
buf ( n6331 , n1851 );
buf ( n6332 , n1056 );
buf ( n6333 , n2021 );
buf ( n6334 , n1722 );
buf ( n6335 , n2082 );
buf ( n6336 , n967 );
buf ( n6337 , n1971 );
buf ( n6338 , n861 );
buf ( n6339 , n460 );
buf ( n6340 , n70 );
buf ( n6341 , n834 );
buf ( n6342 , n1422 );
buf ( n6343 , n2136 );
buf ( n6344 , n1227 );
buf ( n6345 , n2009 );
buf ( n6346 , n577 );
buf ( n6347 , n2140 );
buf ( n6348 , n1871 );
buf ( n6349 , n1319 );
buf ( n6350 , n537 );
buf ( n6351 , n1641 );
buf ( n6352 , n561 );
buf ( n6353 , n1389 );
buf ( n6354 , n1665 );
buf ( n6355 , n517 );
buf ( n6356 , n1956 );
buf ( n6357 , n1442 );
buf ( n6358 , n1752 );
buf ( n6359 , n1475 );
buf ( n6360 , n391 );
buf ( n6361 , n1032 );
buf ( n6362 , n1532 );
buf ( n6363 , n1538 );
buf ( n6364 , n1677 );
buf ( n6365 , n272 );
buf ( n6366 , n1896 );
buf ( n6367 , n267 );
buf ( n6368 , n404 );
buf ( n6369 , n1368 );
buf ( n6370 , n1933 );
buf ( n6371 , n1785 );
buf ( n6372 , n411 );
buf ( n6373 , n1563 );
buf ( n6374 , n1935 );
buf ( n6375 , n172 );
buf ( n6376 , n1033 );
buf ( n6377 , n1216 );
buf ( n6378 , n1537 );
buf ( n6379 , n1144 );
buf ( n6380 , n522 );
buf ( n6381 , n1840 );
buf ( n6382 , n532 );
buf ( n6383 , n1223 );
buf ( n6384 , n878 );
buf ( n6385 , n724 );
buf ( n6386 , n2114 );
buf ( n6387 , n354 );
buf ( n6388 , n309 );
buf ( n6389 , n100 );
buf ( n6390 , n89 );
buf ( n6391 , n731 );
buf ( n6392 , n467 );
buf ( n6393 , n229 );
buf ( n6394 , n827 );
buf ( n6395 , n913 );
buf ( n6396 , n1717 );
buf ( n6397 , n1402 );
buf ( n6398 , n935 );
buf ( n6399 , n2157 );
buf ( n6400 , n1551 );
buf ( n6401 , n2093 );
buf ( n6402 , n1646 );
buf ( n6403 , n324 );
buf ( n6404 , n2051 );
buf ( n6405 , n1556 );
buf ( n6406 , n381 );
buf ( n6407 , n1957 );
buf ( n6408 , n221 );
buf ( n6409 , n1323 );
buf ( n6410 , n556 );
buf ( n6411 , n419 );
buf ( n6412 , n1105 );
buf ( n6413 , n2056 );
buf ( n6414 , n421 );
buf ( n6415 , n858 );
buf ( n6416 , n73 );
buf ( n6417 , n1660 );
buf ( n6418 , n49 );
buf ( n6419 , n1654 );
buf ( n6420 , n2086 );
buf ( n6421 , n1810 );
buf ( n6422 , n1400 );
buf ( n6423 , n1171 );
buf ( n6424 , n698 );
buf ( n6425 , n1569 );
buf ( n6426 , n1849 );
buf ( n6427 , n312 );
buf ( n6428 , n478 );
buf ( n6429 , n16 );
buf ( n6430 , n284 );
buf ( n6431 , n2090 );
buf ( n6432 , n233 );
buf ( n6433 , n1818 );
buf ( n6434 , n1125 );
buf ( n6435 , n103 );
buf ( n6436 , n951 );
buf ( n6437 , n1640 );
buf ( n6438 , n1732 );
buf ( n6439 , n799 );
buf ( n6440 , n1218 );
buf ( n6441 , n1530 );
buf ( n6442 , n56 );
buf ( n6443 , n590 );
buf ( n6444 , n2017 );
buf ( n6445 , n1269 );
buf ( n6446 , n1454 );
buf ( n6447 , n426 );
buf ( n6448 , n12 );
buf ( n6449 , n1695 );
buf ( n6450 , n546 );
buf ( n6451 , n1009 );
buf ( n6452 , n593 );
buf ( n6453 , n34 );
buf ( n6454 , n564 );
buf ( n6455 , n1139 );
buf ( n6456 , n1497 );
buf ( n6457 , n90 );
buf ( n6458 , n1907 );
buf ( n6459 , n688 );
buf ( n6460 , n377 );
buf ( n6461 , n1608 );
buf ( n6462 , n91 );
buf ( n6463 , n1239 );
buf ( n6464 , n1739 );
buf ( n6465 , n1692 );
buf ( n6466 , n237 );
buf ( n6467 , n1734 );
buf ( n6468 , n1054 );
buf ( n6469 , n325 );
buf ( n6470 , n1919 );
buf ( n6471 , n1924 );
buf ( n6472 , n524 );
buf ( n6473 , n36 );
buf ( n6474 , n2178 );
buf ( n6475 , n1668 );
buf ( n6476 , n2089 );
buf ( n6477 , n881 );
buf ( n6478 , n1834 );
buf ( n6479 , n1604 );
buf ( n6480 , n832 );
buf ( n6481 , n902 );
buf ( n6482 , n1796 );
buf ( n6483 , n2041 );
buf ( n6484 , n487 );
buf ( n6485 , n1501 );
buf ( n6486 , n57 );
buf ( n6487 , n1916 );
buf ( n6488 , n975 );
buf ( n6489 , n2165 );
buf ( n6490 , n97 );
buf ( n6491 , n547 );
buf ( n6492 , n566 );
buf ( n6493 , n543 );
buf ( n6494 , n1788 );
buf ( n6495 , n230 );
buf ( n6496 , n1857 );
buf ( n6497 , n152 );
buf ( n6498 , n252 );
buf ( n6499 , n778 );
buf ( n6500 , n380 );
buf ( n6501 , n770 );
buf ( n6502 , n1690 );
buf ( n6503 , n1913 );
buf ( n6504 , n763 );
buf ( n6505 , n1017 );
buf ( n6506 , n1580 );
buf ( n6507 , n969 );
buf ( n6508 , n1742 );
buf ( n6509 , n336 );
buf ( n6510 , n945 );
buf ( n6511 , n486 );
buf ( n6512 , n571 );
buf ( n6513 , n1064 );
buf ( n6514 , n1679 );
buf ( n6515 , n217 );
buf ( n6516 , n1509 );
buf ( n6517 , n1189 );
buf ( n6518 , n1436 );
buf ( n6519 , n1819 );
buf ( n6520 , n72 );
buf ( n6521 , n231 );
buf ( n6522 , n1733 );
buf ( n6523 , n1809 );
buf ( n6524 , n1209 );
buf ( n6525 , n1427 );
buf ( n6526 , n1780 );
buf ( n6527 , n2173 );
buf ( n6528 , n984 );
buf ( n6529 , n383 );
buf ( n6530 , n661 );
buf ( n6531 , n32 );
buf ( n6532 , n452 );
buf ( n6533 , n24 );
buf ( n6534 , n1883 );
buf ( n6535 , n2060 );
buf ( n6536 , n1443 );
buf ( n6537 , n110 );
buf ( n6538 , n1836 );
buf ( n6539 , n1206 );
buf ( n6540 , n1409 );
buf ( n6541 , n2007 );
buf ( n6542 , n2084 );
buf ( n6543 , n1074 );
buf ( n6544 , n2102 );
buf ( n6545 , n457 );
buf ( n6546 , n410 );
buf ( n6547 , n433 );
buf ( n6548 , n9 );
buf ( n6549 , n261 );
buf ( n6550 , n729 );
buf ( n6551 , n333 );
buf ( n6552 , n804 );
buf ( n6553 , n2126 );
buf ( n6554 , n268 );
buf ( n6555 , n1318 );
buf ( n6556 , n737 );
buf ( n6557 , n909 );
buf ( n6558 , n1761 );
buf ( n6559 , n2027 );
buf ( n6560 , n1783 );
buf ( n6561 , n1210 );
buf ( n6562 , n1273 );
buf ( n6563 , n1281 );
buf ( n6564 , n1955 );
buf ( n6565 , n1178 );
buf ( n6566 , n579 );
buf ( n6567 , n1652 );
buf ( n6568 , n2018 );
buf ( n6569 , n44 );
buf ( n6570 , n1581 );
buf ( n6571 , n2011 );
buf ( n6572 , n1649 );
buf ( n6573 , n993 );
buf ( n6574 , n216 );
buf ( n6575 , n1194 );
buf ( n6576 , n1200 );
buf ( n6577 , n4394 );
buf ( n6578 , n6577 );
not ( n6579 , n6578 );
buf ( n6580 , n4395 );
buf ( n6581 , n4396 );
not ( n6582 , n6580 );
and ( n6583 , n6581 , n6582 );
or ( n6584 , n6580 , n6583 );
not ( n6585 , n6584 );
buf ( n6586 , n4397 );
and ( n6587 , n6585 , n6586 );
not ( n6588 , n6583 );
buf ( n6589 , n4398 );
and ( n6590 , n6588 , n6589 );
buf ( n6591 , n4399 );
xor ( n6592 , n6591 , n6589 );
and ( n6593 , n6592 , n6583 );
or ( n6594 , n6590 , n6593 );
not ( n6595 , n6583 );
buf ( n6596 , n4400 );
and ( n6597 , n6595 , n6596 );
buf ( n6598 , n4401 );
xor ( n6599 , n6598 , n6596 );
and ( n6600 , n6599 , n6583 );
or ( n6601 , n6597 , n6600 );
not ( n6602 , n6583 );
buf ( n6603 , n4402 );
and ( n6604 , n6602 , n6603 );
buf ( n6605 , n4403 );
xor ( n6606 , n6605 , n6603 );
and ( n6607 , n6606 , n6583 );
or ( n6608 , n6604 , n6607 );
xor ( n6609 , n6601 , n6608 );
buf ( n6610 , n4404 );
xor ( n6611 , n6609 , n6610 );
buf ( n6612 , n4405 );
xor ( n6613 , n6611 , n6612 );
buf ( n6614 , n4406 );
xor ( n6615 , n6613 , n6614 );
xor ( n6616 , n6594 , n6615 );
not ( n6617 , n6583 );
buf ( n6618 , n4407 );
and ( n6619 , n6617 , n6618 );
buf ( n6620 , n4408 );
xor ( n6621 , n6620 , n6618 );
and ( n6622 , n6621 , n6583 );
or ( n6623 , n6619 , n6622 );
not ( n6624 , n6583 );
buf ( n6625 , n4409 );
and ( n6626 , n6624 , n6625 );
buf ( n6627 , n4410 );
xor ( n6628 , n6627 , n6625 );
and ( n6629 , n6628 , n6583 );
or ( n6630 , n6626 , n6629 );
xor ( n6631 , n6623 , n6630 );
buf ( n6632 , n4411 );
xor ( n6633 , n6631 , n6632 );
buf ( n6634 , n4412 );
xor ( n6635 , n6633 , n6634 );
not ( n6636 , n6635 );
xor ( n6637 , n6616 , n6636 );
not ( n6638 , n6583 );
buf ( n6639 , n4413 );
and ( n6640 , n6638 , n6639 );
buf ( n6641 , n4414 );
xor ( n6642 , n6641 , n6639 );
and ( n6643 , n6642 , n6583 );
or ( n6644 , n6640 , n6643 );
not ( n6645 , n6583 );
buf ( n6646 , n4415 );
and ( n6647 , n6645 , n6646 );
buf ( n6648 , n4416 );
xor ( n6649 , n6648 , n6646 );
and ( n6650 , n6649 , n6583 );
or ( n6651 , n6647 , n6650 );
buf ( n6652 , n4417 );
xor ( n6653 , n6651 , n6652 );
buf ( n6654 , n4418 );
xor ( n6655 , n6653 , n6654 );
buf ( n6656 , n4419 );
xor ( n6657 , n6655 , n6656 );
buf ( n6658 , n4420 );
xor ( n6659 , n6657 , n6658 );
xor ( n6660 , n6644 , n6659 );
not ( n6661 , n6583 );
buf ( n6662 , n4421 );
and ( n6663 , n6661 , n6662 );
buf ( n6664 , n4422 );
xor ( n6665 , n6664 , n6662 );
and ( n6666 , n6665 , n6583 );
or ( n6667 , n6663 , n6666 );
not ( n6668 , n6583 );
buf ( n6669 , n4423 );
and ( n6670 , n6668 , n6669 );
buf ( n6671 , n4424 );
xor ( n6672 , n6671 , n6669 );
and ( n6673 , n6672 , n6583 );
or ( n6674 , n6670 , n6673 );
xor ( n6675 , n6667 , n6674 );
buf ( n6676 , n4425 );
xor ( n6677 , n6675 , n6676 );
buf ( n6678 , n4426 );
xor ( n6679 , n6677 , n6678 );
buf ( n6680 , n4427 );
xor ( n6681 , n6679 , n6680 );
xor ( n6682 , n6660 , n6681 );
not ( n6683 , n6682 );
buf ( n6684 , n4428 );
not ( n6685 , n6583 );
buf ( n6686 , n4429 );
and ( n6687 , n6685 , n6686 );
buf ( n6688 , n4430 );
xor ( n6689 , n6688 , n6686 );
and ( n6690 , n6689 , n6583 );
or ( n6691 , n6687 , n6690 );
not ( n6692 , n6583 );
buf ( n6693 , n4431 );
and ( n6694 , n6692 , n6693 );
buf ( n6695 , n4432 );
xor ( n6696 , n6695 , n6693 );
and ( n6697 , n6696 , n6583 );
or ( n6698 , n6694 , n6697 );
xor ( n6699 , n6691 , n6698 );
buf ( n6700 , n4433 );
xor ( n6701 , n6699 , n6700 );
buf ( n6702 , n4434 );
xor ( n6703 , n6701 , n6702 );
buf ( n6704 , n4435 );
xor ( n6705 , n6703 , n6704 );
xor ( n6706 , n6684 , n6705 );
not ( n6707 , n6583 );
buf ( n6708 , n4436 );
and ( n6709 , n6707 , n6708 );
buf ( n6710 , n4437 );
xor ( n6711 , n6710 , n6708 );
and ( n6712 , n6711 , n6583 );
or ( n6713 , n6709 , n6712 );
not ( n6714 , n6583 );
buf ( n6715 , n4438 );
and ( n6716 , n6714 , n6715 );
buf ( n6717 , n4439 );
xor ( n6718 , n6717 , n6715 );
and ( n6719 , n6718 , n6583 );
or ( n6720 , n6716 , n6719 );
xor ( n6721 , n6713 , n6720 );
buf ( n6722 , n4440 );
xor ( n6723 , n6721 , n6722 );
buf ( n6724 , n4441 );
xor ( n6725 , n6723 , n6724 );
buf ( n6726 , n4442 );
xor ( n6727 , n6725 , n6726 );
xor ( n6728 , n6706 , n6727 );
and ( n6729 , n6683 , n6728 );
xor ( n6730 , n6637 , n6729 );
buf ( n6731 , n4443 );
not ( n6732 , n6583 );
buf ( n6733 , n4444 );
and ( n6734 , n6732 , n6733 );
buf ( n6735 , n4445 );
xor ( n6736 , n6735 , n6733 );
and ( n6737 , n6736 , n6583 );
or ( n6738 , n6734 , n6737 );
not ( n6739 , n6583 );
buf ( n6740 , n4446 );
and ( n6741 , n6739 , n6740 );
buf ( n6742 , n4447 );
xor ( n6743 , n6742 , n6740 );
and ( n6744 , n6743 , n6583 );
or ( n6745 , n6741 , n6744 );
xor ( n6746 , n6738 , n6745 );
buf ( n6747 , n4448 );
xor ( n6748 , n6746 , n6747 );
buf ( n6749 , n4449 );
xor ( n6750 , n6748 , n6749 );
buf ( n6751 , n4450 );
xor ( n6752 , n6750 , n6751 );
xor ( n6753 , n6731 , n6752 );
not ( n6754 , n6583 );
buf ( n6755 , n4451 );
and ( n6756 , n6754 , n6755 );
buf ( n6757 , n4452 );
xor ( n6758 , n6757 , n6755 );
and ( n6759 , n6758 , n6583 );
or ( n6760 , n6756 , n6759 );
not ( n6761 , n6583 );
buf ( n6762 , n4453 );
and ( n6763 , n6761 , n6762 );
buf ( n6764 , n4454 );
xor ( n6765 , n6764 , n6762 );
and ( n6766 , n6765 , n6583 );
or ( n6767 , n6763 , n6766 );
xor ( n6768 , n6760 , n6767 );
buf ( n6769 , n4455 );
xor ( n6770 , n6768 , n6769 );
buf ( n6771 , n4456 );
xor ( n6772 , n6770 , n6771 );
buf ( n6773 , n4457 );
xor ( n6774 , n6772 , n6773 );
xor ( n6775 , n6753 , n6774 );
not ( n6776 , n6583 );
buf ( n6777 , n4458 );
and ( n6778 , n6776 , n6777 );
buf ( n6779 , n4459 );
xor ( n6780 , n6779 , n6777 );
and ( n6781 , n6780 , n6583 );
or ( n6782 , n6778 , n6781 );
not ( n6783 , n6583 );
buf ( n6784 , n4460 );
and ( n6785 , n6783 , n6784 );
buf ( n6786 , n4461 );
xor ( n6787 , n6786 , n6784 );
and ( n6788 , n6787 , n6583 );
or ( n6789 , n6785 , n6788 );
buf ( n6790 , n4462 );
xor ( n6791 , n6789 , n6790 );
buf ( n6792 , n4463 );
xor ( n6793 , n6791 , n6792 );
buf ( n6794 , n4464 );
xor ( n6795 , n6793 , n6794 );
buf ( n6796 , n4465 );
xor ( n6797 , n6795 , n6796 );
xor ( n6798 , n6782 , n6797 );
not ( n6799 , n6583 );
buf ( n6800 , n4466 );
and ( n6801 , n6799 , n6800 );
buf ( n6802 , n4467 );
xor ( n6803 , n6802 , n6800 );
and ( n6804 , n6803 , n6583 );
or ( n6805 , n6801 , n6804 );
not ( n6806 , n6583 );
buf ( n6807 , n4468 );
and ( n6808 , n6806 , n6807 );
buf ( n6809 , n4469 );
xor ( n6810 , n6809 , n6807 );
and ( n6811 , n6810 , n6583 );
or ( n6812 , n6808 , n6811 );
xor ( n6813 , n6805 , n6812 );
buf ( n6814 , n4470 );
xor ( n6815 , n6813 , n6814 );
buf ( n6816 , n4471 );
xor ( n6817 , n6815 , n6816 );
buf ( n6818 , n4472 );
xor ( n6819 , n6817 , n6818 );
xor ( n6820 , n6798 , n6819 );
not ( n6821 , n6820 );
not ( n6822 , n6583 );
buf ( n6823 , n4473 );
and ( n6824 , n6822 , n6823 );
buf ( n6825 , n4474 );
xor ( n6826 , n6825 , n6823 );
and ( n6827 , n6826 , n6583 );
or ( n6828 , n6824 , n6827 );
not ( n6829 , n6583 );
buf ( n6830 , n4475 );
and ( n6831 , n6829 , n6830 );
buf ( n6832 , n4476 );
xor ( n6833 , n6832 , n6830 );
and ( n6834 , n6833 , n6583 );
or ( n6835 , n6831 , n6834 );
not ( n6836 , n6583 );
buf ( n6837 , n4477 );
and ( n6838 , n6836 , n6837 );
buf ( n6839 , n4478 );
xor ( n6840 , n6839 , n6837 );
and ( n6841 , n6840 , n6583 );
or ( n6842 , n6838 , n6841 );
xor ( n6843 , n6835 , n6842 );
buf ( n6844 , n4479 );
xor ( n6845 , n6843 , n6844 );
buf ( n6846 , n4480 );
xor ( n6847 , n6845 , n6846 );
buf ( n6848 , n4481 );
xor ( n6849 , n6847 , n6848 );
xor ( n6850 , n6828 , n6849 );
not ( n6851 , n6583 );
buf ( n6852 , n4482 );
and ( n6853 , n6851 , n6852 );
buf ( n6854 , n4483 );
xor ( n6855 , n6854 , n6852 );
and ( n6856 , n6855 , n6583 );
or ( n6857 , n6853 , n6856 );
not ( n6858 , n6583 );
buf ( n6859 , n4484 );
and ( n6860 , n6858 , n6859 );
buf ( n6861 , n4485 );
xor ( n6862 , n6861 , n6859 );
and ( n6863 , n6862 , n6583 );
or ( n6864 , n6860 , n6863 );
xor ( n6865 , n6857 , n6864 );
buf ( n6866 , n4486 );
xor ( n6867 , n6865 , n6866 );
buf ( n6868 , n4487 );
xor ( n6869 , n6867 , n6868 );
buf ( n6870 , n4488 );
xor ( n6871 , n6869 , n6870 );
xor ( n6872 , n6850 , n6871 );
and ( n6873 , n6821 , n6872 );
xor ( n6874 , n6775 , n6873 );
buf ( n6875 , n4489 );
not ( n6876 , n6583 );
buf ( n6877 , n4490 );
and ( n6878 , n6876 , n6877 );
buf ( n6879 , n4491 );
xor ( n6880 , n6879 , n6877 );
and ( n6881 , n6880 , n6583 );
or ( n6882 , n6878 , n6881 );
not ( n6883 , n6583 );
buf ( n6884 , n4492 );
and ( n6885 , n6883 , n6884 );
buf ( n6886 , n4493 );
xor ( n6887 , n6886 , n6884 );
and ( n6888 , n6887 , n6583 );
or ( n6889 , n6885 , n6888 );
xor ( n6890 , n6882 , n6889 );
buf ( n6891 , n4494 );
xor ( n6892 , n6890 , n6891 );
buf ( n6893 , n4495 );
xor ( n6894 , n6892 , n6893 );
buf ( n6895 , n4496 );
xor ( n6896 , n6894 , n6895 );
xor ( n6897 , n6875 , n6896 );
not ( n6898 , n6583 );
buf ( n6899 , n4497 );
and ( n6900 , n6898 , n6899 );
buf ( n6901 , n4498 );
xor ( n6902 , n6901 , n6899 );
and ( n6903 , n6902 , n6583 );
or ( n6904 , n6900 , n6903 );
not ( n6905 , n6583 );
buf ( n6906 , n4499 );
and ( n6907 , n6905 , n6906 );
buf ( n6908 , n4500 );
xor ( n6909 , n6908 , n6906 );
and ( n6910 , n6909 , n6583 );
or ( n6911 , n6907 , n6910 );
xor ( n6912 , n6904 , n6911 );
buf ( n6913 , n4501 );
xor ( n6914 , n6912 , n6913 );
buf ( n6915 , n4502 );
xor ( n6916 , n6914 , n6915 );
buf ( n6917 , n4503 );
xor ( n6918 , n6916 , n6917 );
xor ( n6919 , n6897 , n6918 );
not ( n6920 , n6583 );
buf ( n6921 , n4504 );
and ( n6922 , n6920 , n6921 );
buf ( n6923 , n4505 );
xor ( n6924 , n6923 , n6921 );
and ( n6925 , n6924 , n6583 );
or ( n6926 , n6922 , n6925 );
not ( n6927 , n6583 );
buf ( n6928 , n4506 );
and ( n6929 , n6927 , n6928 );
buf ( n6930 , n4507 );
xor ( n6931 , n6930 , n6928 );
and ( n6932 , n6931 , n6583 );
or ( n6933 , n6929 , n6932 );
not ( n6934 , n6583 );
buf ( n6935 , n4508 );
and ( n6936 , n6934 , n6935 );
buf ( n6937 , n4509 );
xor ( n6938 , n6937 , n6935 );
and ( n6939 , n6938 , n6583 );
or ( n6940 , n6936 , n6939 );
xor ( n6941 , n6933 , n6940 );
buf ( n6942 , n4510 );
xor ( n6943 , n6941 , n6942 );
buf ( n6944 , n4511 );
xor ( n6945 , n6943 , n6944 );
buf ( n6946 , n4512 );
xor ( n6947 , n6945 , n6946 );
xor ( n6948 , n6926 , n6947 );
not ( n6949 , n6583 );
buf ( n6950 , n4513 );
and ( n6951 , n6949 , n6950 );
buf ( n6952 , n4514 );
xor ( n6953 , n6952 , n6950 );
and ( n6954 , n6953 , n6583 );
or ( n6955 , n6951 , n6954 );
buf ( n6956 , n4515 );
xor ( n6957 , n6955 , n6956 );
buf ( n6958 , n4516 );
xor ( n6959 , n6957 , n6958 );
buf ( n6960 , n4517 );
xor ( n6961 , n6959 , n6960 );
buf ( n6962 , n4518 );
xor ( n6963 , n6961 , n6962 );
xor ( n6964 , n6948 , n6963 );
not ( n6965 , n6964 );
buf ( n6966 , n4519 );
not ( n6967 , n6583 );
buf ( n6968 , n4520 );
and ( n6969 , n6967 , n6968 );
buf ( n6970 , n4521 );
xor ( n6971 , n6970 , n6968 );
and ( n6972 , n6971 , n6583 );
or ( n6973 , n6969 , n6972 );
not ( n6974 , n6583 );
buf ( n6975 , n4522 );
and ( n6976 , n6974 , n6975 );
buf ( n6977 , n4523 );
xor ( n6978 , n6977 , n6975 );
and ( n6979 , n6978 , n6583 );
or ( n6980 , n6976 , n6979 );
xor ( n6981 , n6973 , n6980 );
buf ( n6982 , n4524 );
xor ( n6983 , n6981 , n6982 );
buf ( n6984 , n4525 );
xor ( n6985 , n6983 , n6984 );
buf ( n6986 , n4526 );
xor ( n6987 , n6985 , n6986 );
xor ( n6988 , n6966 , n6987 );
not ( n6989 , n6583 );
buf ( n6990 , n4527 );
and ( n6991 , n6989 , n6990 );
buf ( n6992 , n4528 );
xor ( n6993 , n6992 , n6990 );
and ( n6994 , n6993 , n6583 );
or ( n6995 , n6991 , n6994 );
not ( n6996 , n6583 );
buf ( n6997 , n4529 );
and ( n6998 , n6996 , n6997 );
buf ( n6999 , n4530 );
xor ( n7000 , n6999 , n6997 );
and ( n7001 , n7000 , n6583 );
or ( n7002 , n6998 , n7001 );
xor ( n7003 , n6995 , n7002 );
buf ( n7004 , n4531 );
xor ( n7005 , n7003 , n7004 );
buf ( n7006 , n4532 );
xor ( n7007 , n7005 , n7006 );
buf ( n7008 , n4533 );
xor ( n7009 , n7007 , n7008 );
xor ( n7010 , n6988 , n7009 );
and ( n7011 , n6965 , n7010 );
xor ( n7012 , n6919 , n7011 );
xor ( n7013 , n6874 , n7012 );
buf ( n7014 , n4534 );
not ( n7015 , n6583 );
buf ( n7016 , n4535 );
and ( n7017 , n7015 , n7016 );
buf ( n7018 , n4536 );
xor ( n7019 , n7018 , n7016 );
and ( n7020 , n7019 , n6583 );
or ( n7021 , n7017 , n7020 );
buf ( n7022 , n4537 );
xor ( n7023 , n7021 , n7022 );
buf ( n7024 , n4538 );
xor ( n7025 , n7023 , n7024 );
buf ( n7026 , n4539 );
xor ( n7027 , n7025 , n7026 );
buf ( n7028 , n4540 );
xor ( n7029 , n7027 , n7028 );
xor ( n7030 , n7014 , n7029 );
not ( n7031 , n6583 );
buf ( n7032 , n4541 );
and ( n7033 , n7031 , n7032 );
buf ( n7034 , n4542 );
xor ( n7035 , n7034 , n7032 );
and ( n7036 , n7035 , n6583 );
or ( n7037 , n7033 , n7036 );
not ( n7038 , n6583 );
buf ( n7039 , n4543 );
and ( n7040 , n7038 , n7039 );
buf ( n7041 , n4544 );
xor ( n7042 , n7041 , n7039 );
and ( n7043 , n7042 , n6583 );
or ( n7044 , n7040 , n7043 );
xor ( n7045 , n7037 , n7044 );
buf ( n7046 , n4545 );
xor ( n7047 , n7045 , n7046 );
buf ( n7048 , n4546 );
xor ( n7049 , n7047 , n7048 );
buf ( n7050 , n4547 );
xor ( n7051 , n7049 , n7050 );
xor ( n7052 , n7030 , n7051 );
not ( n7053 , n6583 );
buf ( n7054 , n4548 );
and ( n7055 , n7053 , n7054 );
buf ( n7056 , n4549 );
xor ( n7057 , n7056 , n7054 );
and ( n7058 , n7057 , n6583 );
or ( n7059 , n7055 , n7058 );
not ( n7060 , n6583 );
buf ( n7061 , n4550 );
and ( n7062 , n7060 , n7061 );
buf ( n7063 , n4551 );
xor ( n7064 , n7063 , n7061 );
and ( n7065 , n7064 , n6583 );
or ( n7066 , n7062 , n7065 );
xor ( n7067 , n7059 , n7066 );
buf ( n7068 , n4552 );
xor ( n7069 , n7067 , n7068 );
buf ( n7070 , n4553 );
xor ( n7071 , n7069 , n7070 );
buf ( n7072 , n4554 );
xor ( n7073 , n7071 , n7072 );
xor ( n7074 , n6805 , n7073 );
not ( n7075 , n6583 );
buf ( n7076 , n4555 );
and ( n7077 , n7075 , n7076 );
buf ( n7078 , n4556 );
xor ( n7079 , n7078 , n7076 );
and ( n7080 , n7079 , n6583 );
or ( n7081 , n7077 , n7080 );
not ( n7082 , n6583 );
buf ( n7083 , n4557 );
and ( n7084 , n7082 , n7083 );
buf ( n7085 , n4558 );
xor ( n7086 , n7085 , n7083 );
and ( n7087 , n7086 , n6583 );
or ( n7088 , n7084 , n7087 );
xor ( n7089 , n7081 , n7088 );
buf ( n7090 , n4559 );
xor ( n7091 , n7089 , n7090 );
buf ( n7092 , n4560 );
xor ( n7093 , n7091 , n7092 );
buf ( n7094 , n4561 );
xor ( n7095 , n7093 , n7094 );
xor ( n7096 , n7074 , n7095 );
not ( n7097 , n7096 );
not ( n7098 , n6583 );
buf ( n7099 , n4562 );
and ( n7100 , n7098 , n7099 );
buf ( n7101 , n4563 );
xor ( n7102 , n7101 , n7099 );
and ( n7103 , n7102 , n6583 );
or ( n7104 , n7100 , n7103 );
not ( n7105 , n6583 );
buf ( n7106 , n4564 );
and ( n7107 , n7105 , n7106 );
buf ( n7108 , n4565 );
xor ( n7109 , n7108 , n7106 );
and ( n7110 , n7109 , n6583 );
or ( n7111 , n7107 , n7110 );
not ( n7112 , n6583 );
buf ( n7113 , n4566 );
and ( n7114 , n7112 , n7113 );
buf ( n7115 , n4567 );
xor ( n7116 , n7115 , n7113 );
and ( n7117 , n7116 , n6583 );
or ( n7118 , n7114 , n7117 );
xor ( n7119 , n7111 , n7118 );
buf ( n7120 , n4568 );
xor ( n7121 , n7119 , n7120 );
buf ( n7122 , n4569 );
xor ( n7123 , n7121 , n7122 );
buf ( n7124 , n4570 );
xor ( n7125 , n7123 , n7124 );
xor ( n7126 , n7104 , n7125 );
not ( n7127 , n6583 );
buf ( n7128 , n4571 );
and ( n7129 , n7127 , n7128 );
buf ( n7130 , n4572 );
xor ( n7131 , n7130 , n7128 );
and ( n7132 , n7131 , n6583 );
or ( n7133 , n7129 , n7132 );
not ( n7134 , n6583 );
buf ( n7135 , n4573 );
and ( n7136 , n7134 , n7135 );
buf ( n7137 , n4574 );
xor ( n7138 , n7137 , n7135 );
and ( n7139 , n7138 , n6583 );
or ( n7140 , n7136 , n7139 );
xor ( n7141 , n7133 , n7140 );
buf ( n7142 , n4575 );
xor ( n7143 , n7141 , n7142 );
buf ( n7144 , n4576 );
xor ( n7145 , n7143 , n7144 );
buf ( n7146 , n4577 );
xor ( n7147 , n7145 , n7146 );
xor ( n7148 , n7126 , n7147 );
and ( n7149 , n7097 , n7148 );
xor ( n7150 , n7052 , n7149 );
xor ( n7151 , n7013 , n7150 );
buf ( n7152 , n4578 );
not ( n7153 , n6583 );
buf ( n7154 , n4579 );
and ( n7155 , n7153 , n7154 );
buf ( n7156 , n4580 );
xor ( n7157 , n7156 , n7154 );
and ( n7158 , n7157 , n6583 );
or ( n7159 , n7155 , n7158 );
not ( n7160 , n6583 );
buf ( n7161 , n4581 );
and ( n7162 , n7160 , n7161 );
buf ( n7163 , n4582 );
xor ( n7164 , n7163 , n7161 );
and ( n7165 , n7164 , n6583 );
or ( n7166 , n7162 , n7165 );
xor ( n7167 , n7159 , n7166 );
buf ( n7168 , n4583 );
xor ( n7169 , n7167 , n7168 );
buf ( n7170 , n4584 );
xor ( n7171 , n7169 , n7170 );
buf ( n7172 , n4585 );
xor ( n7173 , n7171 , n7172 );
xor ( n7174 , n7152 , n7173 );
not ( n7175 , n6583 );
buf ( n7176 , n4586 );
and ( n7177 , n7175 , n7176 );
buf ( n7178 , n4587 );
xor ( n7179 , n7178 , n7176 );
and ( n7180 , n7179 , n6583 );
or ( n7181 , n7177 , n7180 );
buf ( n7182 , n4588 );
xor ( n7183 , n7181 , n7182 );
buf ( n7184 , n4589 );
xor ( n7185 , n7183 , n7184 );
buf ( n7186 , n4590 );
xor ( n7187 , n7185 , n7186 );
buf ( n7188 , n4591 );
xor ( n7189 , n7187 , n7188 );
xor ( n7190 , n7174 , n7189 );
not ( n7191 , n6637 );
and ( n7192 , n7191 , n6682 );
xor ( n7193 , n7190 , n7192 );
xor ( n7194 , n7151 , n7193 );
buf ( n7195 , n4592 );
not ( n7196 , n6583 );
buf ( n7197 , n4593 );
and ( n7198 , n7196 , n7197 );
buf ( n7199 , n4594 );
xor ( n7200 , n7199 , n7197 );
and ( n7201 , n7200 , n6583 );
or ( n7202 , n7198 , n7201 );
not ( n7203 , n6583 );
buf ( n7204 , n4595 );
and ( n7205 , n7203 , n7204 );
buf ( n7206 , n4596 );
xor ( n7207 , n7206 , n7204 );
and ( n7208 , n7207 , n6583 );
or ( n7209 , n7205 , n7208 );
xor ( n7210 , n7202 , n7209 );
buf ( n7211 , n4597 );
xor ( n7212 , n7210 , n7211 );
buf ( n7213 , n4598 );
xor ( n7214 , n7212 , n7213 );
buf ( n7215 , n4599 );
xor ( n7216 , n7214 , n7215 );
xor ( n7217 , n7195 , n7216 );
not ( n7218 , n6583 );
buf ( n7219 , n4600 );
and ( n7220 , n7218 , n7219 );
buf ( n7221 , n4601 );
xor ( n7222 , n7221 , n7219 );
and ( n7223 , n7222 , n6583 );
or ( n7224 , n7220 , n7223 );
not ( n7225 , n6583 );
buf ( n7226 , n4602 );
and ( n7227 , n7225 , n7226 );
buf ( n7228 , n4603 );
xor ( n7229 , n7228 , n7226 );
and ( n7230 , n7229 , n6583 );
or ( n7231 , n7227 , n7230 );
xor ( n7232 , n7224 , n7231 );
buf ( n7233 , n4604 );
xor ( n7234 , n7232 , n7233 );
buf ( n7235 , n4605 );
xor ( n7236 , n7234 , n7235 );
buf ( n7237 , n4606 );
xor ( n7238 , n7236 , n7237 );
xor ( n7239 , n7217 , n7238 );
not ( n7240 , n6583 );
buf ( n7241 , n4607 );
and ( n7242 , n7240 , n7241 );
buf ( n7243 , n4608 );
xor ( n7244 , n7243 , n7241 );
and ( n7245 , n7244 , n6583 );
or ( n7246 , n7242 , n7245 );
not ( n7247 , n6583 );
buf ( n7248 , n4609 );
and ( n7249 , n7247 , n7248 );
buf ( n7250 , n4610 );
xor ( n7251 , n7250 , n7248 );
and ( n7252 , n7251 , n6583 );
or ( n7253 , n7249 , n7252 );
not ( n7254 , n6583 );
buf ( n7255 , n4611 );
and ( n7256 , n7254 , n7255 );
buf ( n7257 , n4612 );
xor ( n7258 , n7257 , n7255 );
and ( n7259 , n7258 , n6583 );
or ( n7260 , n7256 , n7259 );
xor ( n7261 , n7253 , n7260 );
buf ( n7262 , n4613 );
xor ( n7263 , n7261 , n7262 );
buf ( n7264 , n4614 );
xor ( n7265 , n7263 , n7264 );
buf ( n7266 , n4615 );
xor ( n7267 , n7265 , n7266 );
xor ( n7268 , n7246 , n7267 );
not ( n7269 , n6583 );
buf ( n7270 , n4616 );
and ( n7271 , n7269 , n7270 );
buf ( n7272 , n4617 );
xor ( n7273 , n7272 , n7270 );
and ( n7274 , n7273 , n6583 );
or ( n7275 , n7271 , n7274 );
not ( n7276 , n6583 );
buf ( n7277 , n4618 );
and ( n7278 , n7276 , n7277 );
buf ( n7279 , n4619 );
xor ( n7280 , n7279 , n7277 );
and ( n7281 , n7280 , n6583 );
or ( n7282 , n7278 , n7281 );
xor ( n7283 , n7275 , n7282 );
buf ( n7284 , n4620 );
xor ( n7285 , n7283 , n7284 );
buf ( n7286 , n4621 );
xor ( n7287 , n7285 , n7286 );
buf ( n7288 , n4622 );
xor ( n7289 , n7287 , n7288 );
xor ( n7290 , n7268 , n7289 );
not ( n7291 , n7290 );
not ( n7292 , n6583 );
buf ( n7293 , n4623 );
and ( n7294 , n7292 , n7293 );
buf ( n7295 , n4624 );
xor ( n7296 , n7295 , n7293 );
and ( n7297 , n7296 , n6583 );
or ( n7298 , n7294 , n7297 );
not ( n7299 , n6583 );
buf ( n7300 , n4625 );
and ( n7301 , n7299 , n7300 );
buf ( n7302 , n4626 );
xor ( n7303 , n7302 , n7300 );
and ( n7304 , n7303 , n6583 );
or ( n7305 , n7301 , n7304 );
not ( n7306 , n6583 );
buf ( n7307 , n4627 );
and ( n7308 , n7306 , n7307 );
buf ( n7309 , n4628 );
xor ( n7310 , n7309 , n7307 );
and ( n7311 , n7310 , n6583 );
or ( n7312 , n7308 , n7311 );
xor ( n7313 , n7305 , n7312 );
buf ( n7314 , n4629 );
xor ( n7315 , n7313 , n7314 );
buf ( n7316 , n4630 );
xor ( n7317 , n7315 , n7316 );
buf ( n7318 , n4631 );
xor ( n7319 , n7317 , n7318 );
xor ( n7320 , n7298 , n7319 );
not ( n7321 , n6583 );
buf ( n7322 , n4632 );
and ( n7323 , n7321 , n7322 );
buf ( n7324 , n4633 );
xor ( n7325 , n7324 , n7322 );
and ( n7326 , n7325 , n6583 );
or ( n7327 , n7323 , n7326 );
buf ( n7328 , n4634 );
xor ( n7329 , n7327 , n7328 );
buf ( n7330 , n4635 );
xor ( n7331 , n7329 , n7330 );
buf ( n7332 , n4636 );
xor ( n7333 , n7331 , n7332 );
buf ( n7334 , n4637 );
xor ( n7335 , n7333 , n7334 );
xor ( n7336 , n7320 , n7335 );
and ( n7337 , n7291 , n7336 );
xor ( n7338 , n7239 , n7337 );
xor ( n7339 , n7194 , n7338 );
xor ( n7340 , n6730 , n7339 );
not ( n7341 , n6583 );
buf ( n7342 , n4638 );
and ( n7343 , n7341 , n7342 );
buf ( n7344 , n4639 );
xor ( n7345 , n7344 , n7342 );
and ( n7346 , n7345 , n6583 );
or ( n7347 , n7343 , n7346 );
not ( n7348 , n6583 );
buf ( n7349 , n4640 );
and ( n7350 , n7348 , n7349 );
buf ( n7351 , n4641 );
xor ( n7352 , n7351 , n7349 );
and ( n7353 , n7352 , n6583 );
or ( n7354 , n7350 , n7353 );
not ( n7355 , n6583 );
buf ( n7356 , n4642 );
and ( n7357 , n7355 , n7356 );
buf ( n7358 , n4643 );
xor ( n7359 , n7358 , n7356 );
and ( n7360 , n7359 , n6583 );
or ( n7361 , n7357 , n7360 );
xor ( n7362 , n7354 , n7361 );
buf ( n7363 , n4644 );
xor ( n7364 , n7362 , n7363 );
buf ( n7365 , n4645 );
xor ( n7366 , n7364 , n7365 );
buf ( n7367 , n4646 );
xor ( n7368 , n7366 , n7367 );
xor ( n7369 , n7347 , n7368 );
not ( n7370 , n6583 );
buf ( n7371 , n4647 );
and ( n7372 , n7370 , n7371 );
buf ( n7373 , n4648 );
xor ( n7374 , n7373 , n7371 );
and ( n7375 , n7374 , n6583 );
or ( n7376 , n7372 , n7375 );
not ( n7377 , n6583 );
buf ( n7378 , n4649 );
and ( n7379 , n7377 , n7378 );
buf ( n7380 , n4650 );
xor ( n7381 , n7380 , n7378 );
and ( n7382 , n7381 , n6583 );
or ( n7383 , n7379 , n7382 );
xor ( n7384 , n7376 , n7383 );
buf ( n7385 , n4651 );
xor ( n7386 , n7384 , n7385 );
buf ( n7387 , n4652 );
xor ( n7388 , n7386 , n7387 );
buf ( n7389 , n4653 );
xor ( n7390 , n7388 , n7389 );
xor ( n7391 , n7369 , n7390 );
buf ( n7392 , n4654 );
not ( n7393 , n6583 );
buf ( n7394 , n4655 );
and ( n7395 , n7393 , n7394 );
buf ( n7396 , n4656 );
xor ( n7397 , n7396 , n7394 );
and ( n7398 , n7397 , n6583 );
or ( n7399 , n7395 , n7398 );
xor ( n7400 , n7399 , n6828 );
buf ( n7401 , n4657 );
xor ( n7402 , n7400 , n7401 );
buf ( n7403 , n4658 );
xor ( n7404 , n7402 , n7403 );
buf ( n7405 , n4659 );
xor ( n7406 , n7404 , n7405 );
xor ( n7407 , n7392 , n7406 );
not ( n7408 , n6583 );
buf ( n7409 , n4660 );
and ( n7410 , n7408 , n7409 );
buf ( n7411 , n4661 );
xor ( n7412 , n7411 , n7409 );
and ( n7413 , n7412 , n6583 );
or ( n7414 , n7410 , n7413 );
not ( n7415 , n6583 );
buf ( n7416 , n4662 );
and ( n7417 , n7415 , n7416 );
buf ( n7418 , n4663 );
xor ( n7419 , n7418 , n7416 );
and ( n7420 , n7419 , n6583 );
or ( n7421 , n7417 , n7420 );
xor ( n7422 , n7414 , n7421 );
buf ( n7423 , n4664 );
xor ( n7424 , n7422 , n7423 );
buf ( n7425 , n4665 );
xor ( n7426 , n7424 , n7425 );
buf ( n7427 , n4666 );
xor ( n7428 , n7426 , n7427 );
xor ( n7429 , n7407 , n7428 );
not ( n7430 , n7429 );
buf ( n7431 , n4667 );
not ( n7432 , n6583 );
buf ( n7433 , n4668 );
and ( n7434 , n7432 , n7433 );
buf ( n7435 , n4669 );
xor ( n7436 , n7435 , n7433 );
and ( n7437 , n7436 , n6583 );
or ( n7438 , n7434 , n7437 );
not ( n7439 , n6583 );
buf ( n7440 , n4670 );
and ( n7441 , n7439 , n7440 );
buf ( n7442 , n4671 );
xor ( n7443 , n7442 , n7440 );
and ( n7444 , n7443 , n6583 );
or ( n7445 , n7441 , n7444 );
xor ( n7446 , n7438 , n7445 );
buf ( n7447 , n4672 );
xor ( n7448 , n7446 , n7447 );
buf ( n7449 , n4673 );
xor ( n7450 , n7448 , n7449 );
buf ( n7451 , n4674 );
xor ( n7452 , n7450 , n7451 );
xor ( n7453 , n7431 , n7452 );
not ( n7454 , n6583 );
buf ( n7455 , n4675 );
and ( n7456 , n7454 , n7455 );
buf ( n7457 , n4676 );
xor ( n7458 , n7457 , n7455 );
and ( n7459 , n7458 , n6583 );
or ( n7460 , n7456 , n7459 );
buf ( n7461 , n4677 );
xor ( n7462 , n7460 , n7461 );
buf ( n7463 , n4678 );
xor ( n7464 , n7462 , n7463 );
buf ( n7465 , n4679 );
xor ( n7466 , n7464 , n7465 );
buf ( n7467 , n4680 );
buf ( n7468 , n7467 );
xor ( n7469 , n7466 , n7468 );
xor ( n7470 , n7453 , n7469 );
and ( n7471 , n7430 , n7470 );
xor ( n7472 , n7391 , n7471 );
buf ( n7473 , n4681 );
not ( n7474 , n6583 );
buf ( n7475 , n4682 );
and ( n7476 , n7474 , n7475 );
buf ( n7477 , n4683 );
xor ( n7478 , n7477 , n7475 );
and ( n7479 , n7478 , n6583 );
or ( n7480 , n7476 , n7479 );
not ( n7481 , n6583 );
buf ( n7482 , n4684 );
and ( n7483 , n7481 , n7482 );
buf ( n7484 , n4685 );
xor ( n7485 , n7484 , n7482 );
and ( n7486 , n7485 , n6583 );
or ( n7487 , n7483 , n7486 );
xor ( n7488 , n7480 , n7487 );
buf ( n7489 , n4686 );
xor ( n7490 , n7488 , n7489 );
buf ( n7491 , n4687 );
xor ( n7492 , n7490 , n7491 );
buf ( n7493 , n4688 );
xor ( n7494 , n7492 , n7493 );
xor ( n7495 , n7473 , n7494 );
not ( n7496 , n6583 );
buf ( n7497 , n4689 );
and ( n7498 , n7496 , n7497 );
buf ( n7499 , n4690 );
xor ( n7500 , n7499 , n7497 );
and ( n7501 , n7500 , n6583 );
or ( n7502 , n7498 , n7501 );
not ( n7503 , n6583 );
buf ( n7504 , n4691 );
and ( n7505 , n7503 , n7504 );
buf ( n7506 , n4692 );
xor ( n7507 , n7506 , n7504 );
and ( n7508 , n7507 , n6583 );
or ( n7509 , n7505 , n7508 );
xor ( n7510 , n7502 , n7509 );
buf ( n7511 , n4693 );
xor ( n7512 , n7510 , n7511 );
buf ( n7513 , n4694 );
xor ( n7514 , n7512 , n7513 );
buf ( n7515 , n4695 );
xor ( n7516 , n7514 , n7515 );
xor ( n7517 , n7495 , n7516 );
buf ( n7518 , n4696 );
not ( n7519 , n6583 );
buf ( n7520 , n4697 );
and ( n7521 , n7519 , n7520 );
buf ( n7522 , n4698 );
xor ( n7523 , n7522 , n7520 );
and ( n7524 , n7523 , n6583 );
or ( n7525 , n7521 , n7524 );
buf ( n7526 , n4699 );
xor ( n7527 , n7525 , n7526 );
buf ( n7528 , n4700 );
xor ( n7529 , n7527 , n7528 );
buf ( n7530 , n4701 );
xor ( n7531 , n7529 , n7530 );
buf ( n7532 , n4702 );
xor ( n7533 , n7531 , n7532 );
xor ( n7534 , n7518 , n7533 );
not ( n7535 , n6583 );
buf ( n7536 , n4703 );
and ( n7537 , n7535 , n7536 );
buf ( n7538 , n4704 );
xor ( n7539 , n7538 , n7536 );
and ( n7540 , n7539 , n6583 );
or ( n7541 , n7537 , n7540 );
not ( n7542 , n6583 );
buf ( n7543 , n4705 );
and ( n7544 , n7542 , n7543 );
buf ( n7545 , n4706 );
xor ( n7546 , n7545 , n7543 );
and ( n7547 , n7546 , n6583 );
or ( n7548 , n7544 , n7547 );
xor ( n7549 , n7541 , n7548 );
buf ( n7550 , n4707 );
xor ( n7551 , n7549 , n7550 );
buf ( n7552 , n4708 );
xor ( n7553 , n7551 , n7552 );
buf ( n7554 , n4709 );
xor ( n7555 , n7553 , n7554 );
xor ( n7556 , n7534 , n7555 );
not ( n7557 , n7556 );
buf ( n7558 , n4710 );
not ( n7559 , n6583 );
buf ( n7560 , n4711 );
and ( n7561 , n7559 , n7560 );
buf ( n7562 , n4712 );
xor ( n7563 , n7562 , n7560 );
and ( n7564 , n7563 , n6583 );
or ( n7565 , n7561 , n7564 );
not ( n7566 , n6583 );
buf ( n7567 , n4713 );
and ( n7568 , n7566 , n7567 );
buf ( n7569 , n4714 );
xor ( n7570 , n7569 , n7567 );
and ( n7571 , n7570 , n6583 );
or ( n7572 , n7568 , n7571 );
xor ( n7573 , n7565 , n7572 );
buf ( n7574 , n4715 );
xor ( n7575 , n7573 , n7574 );
buf ( n7576 , n4716 );
xor ( n7577 , n7575 , n7576 );
buf ( n7578 , n4717 );
xor ( n7579 , n7577 , n7578 );
xor ( n7580 , n7558 , n7579 );
not ( n7581 , n6583 );
buf ( n7582 , n4718 );
and ( n7583 , n7581 , n7582 );
buf ( n7584 , n4719 );
xor ( n7585 , n7584 , n7582 );
and ( n7586 , n7585 , n6583 );
or ( n7587 , n7583 , n7586 );
not ( n7588 , n6583 );
buf ( n7589 , n4720 );
and ( n7590 , n7588 , n7589 );
buf ( n7591 , n4721 );
xor ( n7592 , n7591 , n7589 );
and ( n7593 , n7592 , n6583 );
or ( n7594 , n7590 , n7593 );
xor ( n7595 , n7587 , n7594 );
buf ( n7596 , n7595 );
buf ( n7597 , n4722 );
xor ( n7598 , n7596 , n7597 );
buf ( n7599 , n4723 );
xor ( n7600 , n7598 , n7599 );
xor ( n7601 , n7580 , n7600 );
and ( n7602 , n7557 , n7601 );
xor ( n7603 , n7517 , n7602 );
xor ( n7604 , n7472 , n7603 );
not ( n7605 , n6583 );
buf ( n7606 , n4724 );
and ( n7607 , n7605 , n7606 );
buf ( n7608 , n4725 );
xor ( n7609 , n7608 , n7606 );
and ( n7610 , n7609 , n6583 );
or ( n7611 , n7607 , n7610 );
not ( n7612 , n6583 );
buf ( n7613 , n4726 );
and ( n7614 , n7612 , n7613 );
buf ( n7615 , n4727 );
xor ( n7616 , n7615 , n7613 );
and ( n7617 , n7616 , n6583 );
or ( n7618 , n7614 , n7617 );
not ( n7619 , n6583 );
buf ( n7620 , n4728 );
and ( n7621 , n7619 , n7620 );
buf ( n7622 , n4729 );
xor ( n7623 , n7622 , n7620 );
and ( n7624 , n7623 , n6583 );
or ( n7625 , n7621 , n7624 );
xor ( n7626 , n7618 , n7625 );
buf ( n7627 , n4730 );
xor ( n7628 , n7626 , n7627 );
buf ( n7629 , n4731 );
xor ( n7630 , n7628 , n7629 );
buf ( n7631 , n4732 );
xor ( n7632 , n7630 , n7631 );
xor ( n7633 , n7611 , n7632 );
not ( n7634 , n6583 );
buf ( n7635 , n4733 );
and ( n7636 , n7634 , n7635 );
buf ( n7637 , n4734 );
xor ( n7638 , n7637 , n7635 );
and ( n7639 , n7638 , n6583 );
or ( n7640 , n7636 , n7639 );
not ( n7641 , n6583 );
buf ( n7642 , n4735 );
and ( n7643 , n7641 , n7642 );
buf ( n7644 , n4736 );
xor ( n7645 , n7644 , n7642 );
and ( n7646 , n7645 , n6583 );
or ( n7647 , n7643 , n7646 );
xor ( n7648 , n7640 , n7647 );
buf ( n7649 , n4737 );
xor ( n7650 , n7648 , n7649 );
buf ( n7651 , n4738 );
xor ( n7652 , n7650 , n7651 );
buf ( n7653 , n4739 );
xor ( n7654 , n7652 , n7653 );
xor ( n7655 , n7633 , n7654 );
buf ( n7656 , n4740 );
not ( n7657 , n6583 );
buf ( n7658 , n4741 );
and ( n7659 , n7657 , n7658 );
buf ( n7660 , n4742 );
xor ( n7661 , n7660 , n7658 );
and ( n7662 , n7661 , n6583 );
or ( n7663 , n7659 , n7662 );
not ( n7664 , n6583 );
buf ( n7665 , n4743 );
and ( n7666 , n7664 , n7665 );
buf ( n7667 , n4744 );
xor ( n7668 , n7667 , n7665 );
and ( n7669 , n7668 , n6583 );
or ( n7670 , n7666 , n7669 );
xor ( n7671 , n7663 , n7670 );
buf ( n7672 , n4745 );
xor ( n7673 , n7671 , n7672 );
buf ( n7674 , n4746 );
xor ( n7675 , n7673 , n7674 );
buf ( n7676 , n4747 );
xor ( n7677 , n7675 , n7676 );
xor ( n7678 , n7656 , n7677 );
buf ( n7679 , n4748 );
xor ( n7680 , n6594 , n7679 );
buf ( n7681 , n4749 );
xor ( n7682 , n7680 , n7681 );
buf ( n7683 , n4750 );
xor ( n7684 , n7682 , n7683 );
buf ( n7685 , n4751 );
xor ( n7686 , n7684 , n7685 );
xor ( n7687 , n7678 , n7686 );
not ( n7688 , n7687 );
buf ( n7689 , n4752 );
not ( n7690 , n6583 );
buf ( n7691 , n4753 );
and ( n7692 , n7690 , n7691 );
buf ( n7693 , n4754 );
xor ( n7694 , n7693 , n7691 );
and ( n7695 , n7694 , n6583 );
or ( n7696 , n7692 , n7695 );
not ( n7697 , n6583 );
buf ( n7698 , n4755 );
and ( n7699 , n7697 , n7698 );
buf ( n7700 , n4756 );
xor ( n7701 , n7700 , n7698 );
and ( n7702 , n7701 , n6583 );
or ( n7703 , n7699 , n7702 );
xor ( n7704 , n7696 , n7703 );
buf ( n7705 , n4757 );
xor ( n7706 , n7704 , n7705 );
buf ( n7707 , n4758 );
xor ( n7708 , n7706 , n7707 );
buf ( n7709 , n4759 );
xor ( n7710 , n7708 , n7709 );
xor ( n7711 , n7689 , n7710 );
xor ( n7712 , n7711 , n6705 );
and ( n7713 , n7688 , n7712 );
xor ( n7714 , n7655 , n7713 );
xor ( n7715 , n7604 , n7714 );
not ( n7716 , n6583 );
buf ( n7717 , n4760 );
and ( n7718 , n7716 , n7717 );
buf ( n7719 , n4761 );
xor ( n7720 , n7719 , n7717 );
and ( n7721 , n7720 , n6583 );
or ( n7722 , n7718 , n7721 );
not ( n7723 , n6583 );
buf ( n7724 , n4762 );
and ( n7725 , n7723 , n7724 );
buf ( n7726 , n4763 );
xor ( n7727 , n7726 , n7724 );
and ( n7728 , n7727 , n6583 );
or ( n7729 , n7725 , n7728 );
buf ( n7730 , n4764 );
xor ( n7731 , n7729 , n7730 );
buf ( n7732 , n4765 );
xor ( n7733 , n7731 , n7732 );
buf ( n7734 , n4766 );
xor ( n7735 , n7733 , n7734 );
buf ( n7736 , n4767 );
xor ( n7737 , n7735 , n7736 );
xor ( n7738 , n7722 , n7737 );
not ( n7739 , n6583 );
buf ( n7740 , n4768 );
and ( n7741 , n7739 , n7740 );
buf ( n7742 , n4769 );
xor ( n7743 , n7742 , n7740 );
and ( n7744 , n7743 , n6583 );
or ( n7745 , n7741 , n7744 );
not ( n7746 , n6583 );
buf ( n7747 , n4770 );
and ( n7748 , n7746 , n7747 );
buf ( n7749 , n4771 );
xor ( n7750 , n7749 , n7747 );
and ( n7751 , n7750 , n6583 );
or ( n7752 , n7748 , n7751 );
xor ( n7753 , n7745 , n7752 );
buf ( n7754 , n4772 );
xor ( n7755 , n7753 , n7754 );
buf ( n7756 , n4773 );
xor ( n7757 , n7755 , n7756 );
buf ( n7758 , n4774 );
xor ( n7759 , n7757 , n7758 );
xor ( n7760 , n7738 , n7759 );
buf ( n7761 , n4775 );
not ( n7762 , n6583 );
buf ( n7763 , n4776 );
and ( n7764 , n7762 , n7763 );
buf ( n7765 , n4777 );
xor ( n7766 , n7765 , n7763 );
and ( n7767 , n7766 , n6583 );
or ( n7768 , n7764 , n7767 );
not ( n7769 , n6583 );
buf ( n7770 , n4778 );
and ( n7771 , n7769 , n7770 );
buf ( n7772 , n4779 );
xor ( n7773 , n7772 , n7770 );
and ( n7774 , n7773 , n6583 );
or ( n7775 , n7771 , n7774 );
xor ( n7776 , n7768 , n7775 );
buf ( n7777 , n4780 );
xor ( n7778 , n7776 , n7777 );
buf ( n7779 , n4781 );
xor ( n7780 , n7778 , n7779 );
buf ( n7781 , n4782 );
xor ( n7782 , n7780 , n7781 );
xor ( n7783 , n7761 , n7782 );
not ( n7784 , n6583 );
buf ( n7785 , n4783 );
and ( n7786 , n7784 , n7785 );
buf ( n7787 , n4784 );
xor ( n7788 , n7787 , n7785 );
and ( n7789 , n7788 , n6583 );
or ( n7790 , n7786 , n7789 );
not ( n7791 , n6583 );
buf ( n7792 , n4785 );
and ( n7793 , n7791 , n7792 );
buf ( n7794 , n4786 );
xor ( n7795 , n7794 , n7792 );
and ( n7796 , n7795 , n6583 );
or ( n7797 , n7793 , n7796 );
xor ( n7798 , n7790 , n7797 );
buf ( n7799 , n4787 );
xor ( n7800 , n7798 , n7799 );
buf ( n7801 , n4788 );
xor ( n7802 , n7800 , n7801 );
buf ( n7803 , n4789 );
xor ( n7804 , n7802 , n7803 );
xor ( n7805 , n7783 , n7804 );
not ( n7806 , n7805 );
buf ( n7807 , n4790 );
not ( n7808 , n6583 );
buf ( n7809 , n4791 );
and ( n7810 , n7808 , n7809 );
buf ( n7811 , n4792 );
xor ( n7812 , n7811 , n7809 );
and ( n7813 , n7812 , n6583 );
or ( n7814 , n7810 , n7813 );
not ( n7815 , n6583 );
buf ( n7816 , n4793 );
and ( n7817 , n7815 , n7816 );
buf ( n7818 , n4794 );
xor ( n7819 , n7818 , n7816 );
and ( n7820 , n7819 , n6583 );
or ( n7821 , n7817 , n7820 );
xor ( n7822 , n7814 , n7821 );
buf ( n7823 , n4795 );
xor ( n7824 , n7822 , n7823 );
buf ( n7825 , n4796 );
xor ( n7826 , n7824 , n7825 );
buf ( n7827 , n4797 );
xor ( n7828 , n7826 , n7827 );
xor ( n7829 , n7807 , n7828 );
not ( n7830 , n6583 );
buf ( n7831 , n4798 );
and ( n7832 , n7830 , n7831 );
buf ( n7833 , n4799 );
xor ( n7834 , n7833 , n7831 );
and ( n7835 , n7834 , n6583 );
or ( n7836 , n7832 , n7835 );
not ( n7837 , n6583 );
buf ( n7838 , n4800 );
and ( n7839 , n7837 , n7838 );
buf ( n7840 , n4801 );
xor ( n7841 , n7840 , n7838 );
and ( n7842 , n7841 , n6583 );
or ( n7843 , n7839 , n7842 );
xor ( n7844 , n7836 , n7843 );
buf ( n7845 , n4802 );
buf ( n7846 , n7845 );
xor ( n7847 , n7844 , n7846 );
buf ( n7848 , n4803 );
xor ( n7849 , n7847 , n7848 );
buf ( n7850 , n4804 );
xor ( n7851 , n7849 , n7850 );
xor ( n7852 , n7829 , n7851 );
and ( n7853 , n7806 , n7852 );
xor ( n7854 , n7760 , n7853 );
xor ( n7855 , n7715 , n7854 );
not ( n7856 , n6583 );
buf ( n7857 , n4805 );
and ( n7858 , n7856 , n7857 );
buf ( n7859 , n4806 );
xor ( n7860 , n7859 , n7857 );
and ( n7861 , n7860 , n6583 );
or ( n7862 , n7858 , n7861 );
xor ( n7863 , n7862 , n7173 );
xor ( n7864 , n7863 , n7189 );
buf ( n7865 , n4807 );
not ( n7866 , n6583 );
buf ( n7867 , n4808 );
and ( n7868 , n7866 , n7867 );
buf ( n7869 , n4809 );
xor ( n7870 , n7869 , n7867 );
and ( n7871 , n7870 , n6583 );
or ( n7872 , n7868 , n7871 );
not ( n7873 , n6583 );
buf ( n7874 , n4810 );
and ( n7875 , n7873 , n7874 );
buf ( n7876 , n4811 );
xor ( n7877 , n7876 , n7874 );
and ( n7878 , n7877 , n6583 );
or ( n7879 , n7875 , n7878 );
xor ( n7880 , n7872 , n7879 );
buf ( n7881 , n4812 );
xor ( n7882 , n7880 , n7881 );
buf ( n7883 , n4813 );
xor ( n7884 , n7882 , n7883 );
buf ( n7885 , n4814 );
xor ( n7886 , n7884 , n7885 );
xor ( n7887 , n7865 , n7886 );
not ( n7888 , n6583 );
buf ( n7889 , n4815 );
and ( n7890 , n7888 , n7889 );
buf ( n7891 , n4816 );
xor ( n7892 , n7891 , n7889 );
and ( n7893 , n7892 , n6583 );
or ( n7894 , n7890 , n7893 );
not ( n7895 , n6583 );
buf ( n7896 , n4817 );
and ( n7897 , n7895 , n7896 );
buf ( n7898 , n4818 );
xor ( n7899 , n7898 , n7896 );
and ( n7900 , n7899 , n6583 );
or ( n7901 , n7897 , n7900 );
xor ( n7902 , n7894 , n7901 );
buf ( n7903 , n4819 );
xor ( n7904 , n7902 , n7903 );
buf ( n7905 , n4820 );
xor ( n7906 , n7904 , n7905 );
buf ( n7907 , n4821 );
xor ( n7908 , n7906 , n7907 );
xor ( n7909 , n7887 , n7908 );
not ( n7910 , n7909 );
buf ( n7911 , n4822 );
not ( n7912 , n6583 );
buf ( n7913 , n4823 );
and ( n7914 , n7912 , n7913 );
buf ( n7915 , n4824 );
xor ( n7916 , n7915 , n7913 );
and ( n7917 , n7916 , n6583 );
or ( n7918 , n7914 , n7917 );
buf ( n7919 , n4825 );
xor ( n7920 , n7918 , n7919 );
buf ( n7921 , n4826 );
xor ( n7922 , n7920 , n7921 );
buf ( n7923 , n4827 );
xor ( n7924 , n7922 , n7923 );
buf ( n7925 , n4828 );
xor ( n7926 , n7924 , n7925 );
xor ( n7927 , n7911 , n7926 );
not ( n7928 , n6583 );
buf ( n7929 , n4829 );
and ( n7930 , n7928 , n7929 );
buf ( n7931 , n4830 );
xor ( n7932 , n7931 , n7929 );
and ( n7933 , n7932 , n6583 );
or ( n7934 , n7930 , n7933 );
not ( n7935 , n6583 );
buf ( n7936 , n4831 );
and ( n7937 , n7935 , n7936 );
buf ( n7938 , n4832 );
xor ( n7939 , n7938 , n7936 );
and ( n7940 , n7939 , n6583 );
or ( n7941 , n7937 , n7940 );
xor ( n7942 , n7934 , n7941 );
buf ( n7943 , n4833 );
xor ( n7944 , n7942 , n7943 );
buf ( n7945 , n4834 );
xor ( n7946 , n7944 , n7945 );
buf ( n7947 , n4835 );
xor ( n7948 , n7946 , n7947 );
xor ( n7949 , n7927 , n7948 );
and ( n7950 , n7910 , n7949 );
xor ( n7951 , n7864 , n7950 );
xor ( n7952 , n7855 , n7951 );
xor ( n7953 , n7340 , n7952 );
not ( n7954 , n6583 );
buf ( n7955 , n4836 );
and ( n7956 , n7954 , n7955 );
buf ( n7957 , n4837 );
xor ( n7958 , n7957 , n7955 );
and ( n7959 , n7958 , n6583 );
or ( n7960 , n7956 , n7959 );
not ( n7961 , n6583 );
buf ( n7962 , n4838 );
and ( n7963 , n7961 , n7962 );
buf ( n7964 , n4839 );
xor ( n7965 , n7964 , n7962 );
and ( n7966 , n7965 , n6583 );
or ( n7967 , n7963 , n7966 );
not ( n7968 , n6583 );
buf ( n7969 , n4840 );
and ( n7970 , n7968 , n7969 );
buf ( n7971 , n4841 );
xor ( n7972 , n7971 , n7969 );
and ( n7973 , n7972 , n6583 );
or ( n7974 , n7970 , n7973 );
xor ( n7975 , n7967 , n7974 );
buf ( n7976 , n4842 );
xor ( n7977 , n7975 , n7976 );
xor ( n7978 , n7977 , n7807 );
buf ( n7979 , n4843 );
xor ( n7980 , n7978 , n7979 );
xor ( n7981 , n7960 , n7980 );
not ( n7982 , n6583 );
buf ( n7983 , n4844 );
and ( n7984 , n7982 , n7983 );
buf ( n7985 , n4845 );
xor ( n7986 , n7985 , n7983 );
and ( n7987 , n7986 , n6583 );
or ( n7988 , n7984 , n7987 );
buf ( n7989 , n4846 );
xor ( n7990 , n7988 , n7989 );
buf ( n7991 , n4847 );
xor ( n7992 , n7990 , n7991 );
buf ( n7993 , n4848 );
xor ( n7994 , n7992 , n7993 );
buf ( n7995 , n4849 );
xor ( n7996 , n7994 , n7995 );
xor ( n7997 , n7981 , n7996 );
not ( n7998 , n6583 );
buf ( n7999 , n4850 );
and ( n8000 , n7998 , n7999 );
buf ( n8001 , n4851 );
xor ( n8002 , n8001 , n7999 );
and ( n8003 , n8002 , n6583 );
or ( n8004 , n8000 , n8003 );
not ( n8005 , n6583 );
buf ( n8006 , n4852 );
and ( n8007 , n8005 , n8006 );
buf ( n8008 , n4853 );
xor ( n8009 , n8008 , n8006 );
and ( n8010 , n8009 , n6583 );
or ( n8011 , n8007 , n8010 );
xor ( n8012 , n8004 , n8011 );
buf ( n8013 , n4854 );
xor ( n8014 , n8012 , n8013 );
buf ( n8015 , n4855 );
xor ( n8016 , n8014 , n8015 );
buf ( n8017 , n4856 );
xor ( n8018 , n8016 , n8017 );
xor ( n8019 , n6792 , n8018 );
xor ( n8020 , n8019 , n7073 );
not ( n8021 , n8020 );
not ( n8022 , n6583 );
buf ( n8023 , n4857 );
and ( n8024 , n8022 , n8023 );
buf ( n8025 , n4858 );
xor ( n8026 , n8025 , n8023 );
and ( n8027 , n8026 , n6583 );
or ( n8028 , n8024 , n8027 );
buf ( n8029 , n4859 );
xor ( n8030 , n8028 , n8029 );
buf ( n8031 , n4860 );
xor ( n8032 , n8030 , n8031 );
buf ( n8033 , n4861 );
xor ( n8034 , n8032 , n8033 );
buf ( n8035 , n4862 );
xor ( n8036 , n8034 , n8035 );
xor ( n8037 , n7213 , n8036 );
not ( n8038 , n6583 );
buf ( n8039 , n4863 );
and ( n8040 , n8038 , n8039 );
buf ( n8041 , n4864 );
xor ( n8042 , n8041 , n8039 );
and ( n8043 , n8042 , n6583 );
or ( n8044 , n8040 , n8043 );
not ( n8045 , n6583 );
buf ( n8046 , n4865 );
and ( n8047 , n8045 , n8046 );
buf ( n8048 , n4866 );
xor ( n8049 , n8048 , n8046 );
and ( n8050 , n8049 , n6583 );
or ( n8051 , n8047 , n8050 );
xor ( n8052 , n8044 , n8051 );
buf ( n8053 , n4867 );
xor ( n8054 , n8052 , n8053 );
buf ( n8055 , n4868 );
xor ( n8056 , n8054 , n8055 );
buf ( n8057 , n4869 );
xor ( n8058 , n8056 , n8057 );
xor ( n8059 , n8037 , n8058 );
and ( n8060 , n8021 , n8059 );
xor ( n8061 , n7997 , n8060 );
not ( n8062 , n6583 );
buf ( n8063 , n4870 );
and ( n8064 , n8062 , n8063 );
buf ( n8065 , n4871 );
xor ( n8066 , n8065 , n8063 );
and ( n8067 , n8066 , n6583 );
or ( n8068 , n8064 , n8067 );
not ( n8069 , n6583 );
buf ( n8070 , n4872 );
and ( n8071 , n8069 , n8070 );
buf ( n8072 , n4873 );
xor ( n8073 , n8072 , n8070 );
and ( n8074 , n8073 , n6583 );
or ( n8075 , n8071 , n8074 );
buf ( n8076 , n4874 );
xor ( n8077 , n8075 , n8076 );
buf ( n8078 , n4875 );
xor ( n8079 , n8077 , n8078 );
buf ( n8080 , n4876 );
xor ( n8081 , n8079 , n8080 );
buf ( n8082 , n4877 );
xor ( n8083 , n8081 , n8082 );
xor ( n8084 , n8068 , n8083 );
not ( n8085 , n6583 );
buf ( n8086 , n4878 );
and ( n8087 , n8085 , n8086 );
buf ( n8088 , n4879 );
xor ( n8089 , n8088 , n8086 );
and ( n8090 , n8089 , n6583 );
or ( n8091 , n8087 , n8090 );
not ( n8092 , n6583 );
buf ( n8093 , n4880 );
and ( n8094 , n8092 , n8093 );
buf ( n8095 , n4881 );
xor ( n8096 , n8095 , n8093 );
and ( n8097 , n8096 , n6583 );
or ( n8098 , n8094 , n8097 );
xor ( n8099 , n8091 , n8098 );
buf ( n8100 , n4882 );
xor ( n8101 , n8099 , n8100 );
buf ( n8102 , n4883 );
xor ( n8103 , n8101 , n8102 );
buf ( n8104 , n4884 );
xor ( n8105 , n8103 , n8104 );
xor ( n8106 , n8084 , n8105 );
not ( n8107 , n6583 );
buf ( n8108 , n4885 );
and ( n8109 , n8107 , n8108 );
buf ( n8110 , n4886 );
xor ( n8111 , n8110 , n8108 );
and ( n8112 , n8111 , n6583 );
or ( n8113 , n8109 , n8112 );
not ( n8114 , n6583 );
buf ( n8115 , n4887 );
and ( n8116 , n8114 , n8115 );
buf ( n8117 , n4888 );
xor ( n8118 , n8117 , n8115 );
and ( n8119 , n8118 , n6583 );
or ( n8120 , n8116 , n8119 );
xor ( n8121 , n8113 , n8120 );
buf ( n8122 , n4889 );
xor ( n8123 , n8121 , n8122 );
buf ( n8124 , n4890 );
xor ( n8125 , n8123 , n8124 );
buf ( n8126 , n4891 );
xor ( n8127 , n8125 , n8126 );
xor ( n8128 , n7548 , n8127 );
not ( n8129 , n6583 );
buf ( n8130 , n4892 );
and ( n8131 , n8129 , n8130 );
buf ( n8132 , n4893 );
xor ( n8133 , n8132 , n8130 );
and ( n8134 , n8133 , n6583 );
or ( n8135 , n8131 , n8134 );
xor ( n8136 , n8135 , n7104 );
buf ( n8137 , n4894 );
xor ( n8138 , n8136 , n8137 );
buf ( n8139 , n4895 );
xor ( n8140 , n8138 , n8139 );
buf ( n8141 , n4896 );
xor ( n8142 , n8140 , n8141 );
xor ( n8143 , n8128 , n8142 );
not ( n8144 , n8143 );
buf ( n8145 , n4897 );
not ( n8146 , n6583 );
buf ( n8147 , n4898 );
and ( n8148 , n8146 , n8147 );
buf ( n8149 , n4899 );
xor ( n8150 , n8149 , n8147 );
and ( n8151 , n8150 , n6583 );
or ( n8152 , n8148 , n8151 );
not ( n8153 , n6583 );
buf ( n8154 , n4900 );
and ( n8155 , n8153 , n8154 );
buf ( n8156 , n4901 );
xor ( n8157 , n8156 , n8154 );
and ( n8158 , n8157 , n6583 );
or ( n8159 , n8155 , n8158 );
xor ( n8160 , n8152 , n8159 );
buf ( n8161 , n4902 );
xor ( n8162 , n8160 , n8161 );
buf ( n8163 , n4903 );
xor ( n8164 , n8162 , n8163 );
buf ( n8165 , n4904 );
buf ( n8166 , n8165 );
xor ( n8167 , n8164 , n8166 );
xor ( n8168 , n8145 , n8167 );
not ( n8169 , n6583 );
buf ( n8170 , n4905 );
and ( n8171 , n8169 , n8170 );
buf ( n8172 , n4906 );
xor ( n8173 , n8172 , n8170 );
and ( n8174 , n8173 , n6583 );
or ( n8175 , n8171 , n8174 );
not ( n8176 , n6583 );
buf ( n8177 , n4907 );
and ( n8178 , n8176 , n8177 );
buf ( n8179 , n4908 );
xor ( n8180 , n8179 , n8177 );
and ( n8181 , n8180 , n6583 );
or ( n8182 , n8178 , n8181 );
xor ( n8183 , n8175 , n8182 );
buf ( n8184 , n4909 );
xor ( n8185 , n8183 , n8184 );
buf ( n8186 , n4910 );
xor ( n8187 , n8185 , n8186 );
buf ( n8188 , n4911 );
xor ( n8189 , n8187 , n8188 );
xor ( n8190 , n8168 , n8189 );
and ( n8191 , n8144 , n8190 );
xor ( n8192 , n8106 , n8191 );
buf ( n8193 , n4912 );
buf ( n8194 , n4913 );
or ( n8195 , n8193 , n8194 );
buf ( n8196 , n4914 );
or ( n8197 , n8195 , n8196 );
buf ( n8198 , n4915 );
or ( n8199 , n8197 , n8198 );
buf ( n8200 , n4916 );
or ( n8201 , n8199 , n8200 );
buf ( n8202 , n4917 );
or ( n8203 , n8201 , n8202 );
buf ( n8204 , n4918 );
or ( n8205 , n8203 , n8204 );
xor ( n8206 , n8192 , n8205 );
not ( n8207 , n6583 );
buf ( n8208 , n4919 );
and ( n8209 , n8207 , n8208 );
buf ( n8210 , n4920 );
xor ( n8211 , n8210 , n8208 );
and ( n8212 , n8211 , n6583 );
or ( n8213 , n8209 , n8212 );
not ( n8214 , n6583 );
buf ( n8215 , n4921 );
and ( n8216 , n8214 , n8215 );
buf ( n8217 , n4922 );
xor ( n8218 , n8217 , n8215 );
and ( n8219 , n8218 , n6583 );
or ( n8220 , n8216 , n8219 );
not ( n8221 , n6583 );
buf ( n8222 , n4923 );
and ( n8223 , n8221 , n8222 );
buf ( n8224 , n4924 );
xor ( n8225 , n8224 , n8222 );
and ( n8226 , n8225 , n6583 );
or ( n8227 , n8223 , n8226 );
xor ( n8228 , n8220 , n8227 );
buf ( n8229 , n4925 );
xor ( n8230 , n8228 , n8229 );
buf ( n8231 , n4926 );
xor ( n8232 , n8230 , n8231 );
buf ( n8233 , n4927 );
xor ( n8234 , n8232 , n8233 );
xor ( n8235 , n8213 , n8234 );
not ( n8236 , n6583 );
buf ( n8237 , n4928 );
and ( n8238 , n8236 , n8237 );
buf ( n8239 , n4929 );
xor ( n8240 , n8239 , n8237 );
and ( n8241 , n8240 , n6583 );
or ( n8242 , n8238 , n8241 );
buf ( n8243 , n4930 );
xor ( n8244 , n8242 , n8243 );
buf ( n8245 , n4931 );
xor ( n8246 , n8244 , n8245 );
buf ( n8247 , n4932 );
xor ( n8248 , n8246 , n8247 );
buf ( n8249 , n4933 );
xor ( n8250 , n8248 , n8249 );
xor ( n8251 , n8235 , n8250 );
buf ( n8252 , n4934 );
xor ( n8253 , n8252 , n7428 );
xor ( n8254 , n8253 , n7579 );
not ( n8255 , n8254 );
not ( n8256 , n6583 );
buf ( n8257 , n4935 );
and ( n8258 , n8256 , n8257 );
buf ( n8259 , n4936 );
xor ( n8260 , n8259 , n8257 );
and ( n8261 , n8260 , n6583 );
or ( n8262 , n8258 , n8261 );
buf ( n8263 , n4937 );
xor ( n8264 , n8262 , n8263 );
buf ( n8265 , n4938 );
xor ( n8266 , n8264 , n8265 );
buf ( n8267 , n4939 );
xor ( n8268 , n8266 , n8267 );
buf ( n8269 , n4940 );
xor ( n8270 , n8268 , n8269 );
xor ( n8271 , n6632 , n8270 );
not ( n8272 , n6583 );
buf ( n8273 , n4941 );
and ( n8274 , n8272 , n8273 );
buf ( n8275 , n4942 );
xor ( n8276 , n8275 , n8273 );
and ( n8277 , n8276 , n6583 );
or ( n8278 , n8274 , n8277 );
not ( n8279 , n6583 );
buf ( n8280 , n4943 );
and ( n8281 , n8279 , n8280 );
buf ( n8282 , n4944 );
xor ( n8283 , n8282 , n8280 );
and ( n8284 , n8283 , n6583 );
or ( n8285 , n8281 , n8284 );
xor ( n8286 , n8278 , n8285 );
buf ( n8287 , n4945 );
xor ( n8288 , n8286 , n8287 );
buf ( n8289 , n4946 );
xor ( n8290 , n8288 , n8289 );
buf ( n8291 , n4947 );
xor ( n8292 , n8290 , n8291 );
xor ( n8293 , n8271 , n8292 );
and ( n8294 , n8255 , n8293 );
xor ( n8295 , n8251 , n8294 );
xor ( n8296 , n8206 , n8295 );
not ( n8297 , n6583 );
buf ( n8298 , n4948 );
and ( n8299 , n8297 , n8298 );
buf ( n8300 , n4949 );
xor ( n8301 , n8300 , n8298 );
and ( n8302 , n8301 , n6583 );
or ( n8303 , n8299 , n8302 );
not ( n8304 , n6583 );
buf ( n8305 , n4950 );
and ( n8306 , n8304 , n8305 );
buf ( n8307 , n4951 );
xor ( n8308 , n8307 , n8305 );
and ( n8309 , n8308 , n6583 );
or ( n8310 , n8306 , n8309 );
xor ( n8311 , n8303 , n8310 );
buf ( n8312 , n4952 );
xor ( n8313 , n8311 , n8312 );
buf ( n8314 , n4953 );
xor ( n8315 , n8313 , n8314 );
buf ( n8316 , n4954 );
buf ( n8317 , n8316 );
xor ( n8318 , n8315 , n8317 );
xor ( n8319 , n8091 , n8318 );
not ( n8320 , n6583 );
buf ( n8321 , n4955 );
and ( n8322 , n8320 , n8321 );
buf ( n8323 , n4956 );
xor ( n8324 , n8323 , n8321 );
and ( n8325 , n8324 , n6583 );
or ( n8326 , n8322 , n8325 );
not ( n8327 , n6583 );
buf ( n8328 , n4957 );
and ( n8329 , n8327 , n8328 );
buf ( n8330 , n4958 );
xor ( n8331 , n8330 , n8328 );
and ( n8332 , n8331 , n6583 );
or ( n8333 , n8329 , n8332 );
xor ( n8334 , n8326 , n8333 );
buf ( n8335 , n4959 );
xor ( n8336 , n8334 , n8335 );
buf ( n8337 , n4960 );
xor ( n8338 , n8336 , n8337 );
buf ( n8339 , n4961 );
xor ( n8340 , n8338 , n8339 );
xor ( n8341 , n8319 , n8340 );
not ( n8342 , n6583 );
buf ( n8343 , n4962 );
and ( n8344 , n8342 , n8343 );
buf ( n8345 , n4963 );
xor ( n8346 , n8345 , n8343 );
and ( n8347 , n8346 , n6583 );
or ( n8348 , n8344 , n8347 );
not ( n8349 , n6583 );
buf ( n8350 , n4964 );
and ( n8351 , n8349 , n8350 );
buf ( n8352 , n4965 );
xor ( n8353 , n8352 , n8350 );
and ( n8354 , n8353 , n6583 );
or ( n8355 , n8351 , n8354 );
not ( n8356 , n6583 );
buf ( n8357 , n4966 );
and ( n8358 , n8356 , n8357 );
buf ( n8359 , n4967 );
xor ( n8360 , n8359 , n8357 );
and ( n8361 , n8360 , n6583 );
or ( n8362 , n8358 , n8361 );
xor ( n8363 , n8355 , n8362 );
buf ( n8364 , n4968 );
xor ( n8365 , n8363 , n8364 );
buf ( n8366 , n4969 );
xor ( n8367 , n8365 , n8366 );
buf ( n8368 , n4970 );
xor ( n8369 , n8367 , n8368 );
xor ( n8370 , n8348 , n8369 );
not ( n8371 , n6583 );
buf ( n8372 , n4971 );
and ( n8373 , n8371 , n8372 );
buf ( n8374 , n8373 );
not ( n8375 , n6583 );
buf ( n8376 , n4972 );
and ( n8377 , n8375 , n8376 );
buf ( n8378 , n4973 );
xor ( n8379 , n8378 , n8376 );
and ( n8380 , n8379 , n6583 );
or ( n8381 , n8377 , n8380 );
xor ( n8382 , n8374 , n8381 );
buf ( n8383 , n4974 );
xor ( n8384 , n8382 , n8383 );
buf ( n8385 , n4975 );
xor ( n8386 , n8384 , n8385 );
buf ( n8387 , n4976 );
xor ( n8388 , n8386 , n8387 );
xor ( n8389 , n8370 , n8388 );
not ( n8390 , n8389 );
buf ( n8391 , n4977 );
not ( n8392 , n6583 );
buf ( n8393 , n4978 );
and ( n8394 , n8392 , n8393 );
buf ( n8395 , n4979 );
xor ( n8396 , n8395 , n8393 );
and ( n8397 , n8396 , n6583 );
or ( n8398 , n8394 , n8397 );
not ( n8399 , n6583 );
buf ( n8400 , n4980 );
and ( n8401 , n8399 , n8400 );
buf ( n8402 , n4981 );
xor ( n8403 , n8402 , n8400 );
and ( n8404 , n8403 , n6583 );
or ( n8405 , n8401 , n8404 );
xor ( n8406 , n8398 , n8405 );
buf ( n8407 , n4982 );
xor ( n8408 , n8406 , n8407 );
buf ( n8409 , n4983 );
xor ( n8410 , n8408 , n8409 );
buf ( n8411 , n4984 );
xor ( n8412 , n8410 , n8411 );
xor ( n8413 , n8391 , n8412 );
not ( n8414 , n6583 );
buf ( n8415 , n4985 );
and ( n8416 , n8414 , n8415 );
buf ( n8417 , n4986 );
xor ( n8418 , n8417 , n8415 );
and ( n8419 , n8418 , n6583 );
or ( n8420 , n8416 , n8419 );
buf ( n8421 , n4987 );
xor ( n8422 , n8420 , n8421 );
buf ( n8423 , n4988 );
xor ( n8424 , n8422 , n8423 );
buf ( n8425 , n4989 );
xor ( n8426 , n8424 , n8425 );
buf ( n8427 , n4990 );
xor ( n8428 , n8426 , n8427 );
xor ( n8429 , n8413 , n8428 );
and ( n8430 , n8390 , n8429 );
xor ( n8431 , n8341 , n8430 );
xor ( n8432 , n8296 , n8431 );
not ( n8433 , n6583 );
buf ( n8434 , n4991 );
and ( n8435 , n8433 , n8434 );
buf ( n8436 , n4992 );
xor ( n8437 , n8436 , n8434 );
and ( n8438 , n8437 , n6583 );
or ( n8439 , n8435 , n8438 );
not ( n8440 , n6583 );
buf ( n8441 , n4993 );
and ( n8442 , n8440 , n8441 );
buf ( n8443 , n4994 );
xor ( n8444 , n8443 , n8441 );
and ( n8445 , n8444 , n6583 );
or ( n8446 , n8442 , n8445 );
not ( n8447 , n6583 );
buf ( n8448 , n4995 );
and ( n8449 , n8447 , n8448 );
buf ( n8450 , n4996 );
xor ( n8451 , n8450 , n8448 );
and ( n8452 , n8451 , n6583 );
or ( n8453 , n8449 , n8452 );
xor ( n8454 , n8446 , n8453 );
buf ( n8455 , n4997 );
xor ( n8456 , n8454 , n8455 );
buf ( n8457 , n4998 );
xor ( n8458 , n8456 , n8457 );
buf ( n8459 , n4999 );
xor ( n8460 , n8458 , n8459 );
xor ( n8461 , n8439 , n8460 );
not ( n8462 , n6583 );
buf ( n8463 , n5000 );
and ( n8464 , n8462 , n8463 );
buf ( n8465 , n5001 );
xor ( n8466 , n8465 , n8463 );
and ( n8467 , n8466 , n6583 );
or ( n8468 , n8464 , n8467 );
not ( n8469 , n6583 );
buf ( n8470 , n5002 );
and ( n8471 , n8469 , n8470 );
buf ( n8472 , n5003 );
xor ( n8473 , n8472 , n8470 );
and ( n8474 , n8473 , n6583 );
or ( n8475 , n8471 , n8474 );
xor ( n8476 , n8468 , n8475 );
buf ( n8477 , n5004 );
xor ( n8478 , n8476 , n8477 );
buf ( n8479 , n5005 );
xor ( n8480 , n8478 , n8479 );
buf ( n8481 , n5006 );
xor ( n8482 , n8480 , n8481 );
xor ( n8483 , n8461 , n8482 );
not ( n8484 , n6583 );
buf ( n8485 , n5007 );
and ( n8486 , n8484 , n8485 );
buf ( n8487 , n5008 );
xor ( n8488 , n8487 , n8485 );
and ( n8489 , n8488 , n6583 );
or ( n8490 , n8486 , n8489 );
not ( n8491 , n6583 );
buf ( n8492 , n5009 );
and ( n8493 , n8491 , n8492 );
buf ( n8494 , n5010 );
xor ( n8495 , n8494 , n8492 );
and ( n8496 , n8495 , n6583 );
or ( n8497 , n8493 , n8496 );
buf ( n8498 , n5011 );
xor ( n8499 , n8497 , n8498 );
buf ( n8500 , n5012 );
xor ( n8501 , n8499 , n8500 );
buf ( n8502 , n5013 );
xor ( n8503 , n8501 , n8502 );
buf ( n8504 , n5014 );
xor ( n8505 , n8503 , n8504 );
xor ( n8506 , n8490 , n8505 );
xor ( n8507 , n8506 , n7267 );
not ( n8508 , n8507 );
buf ( n8509 , n5015 );
not ( n8510 , n6583 );
buf ( n8511 , n5016 );
and ( n8512 , n8510 , n8511 );
buf ( n8513 , n5017 );
xor ( n8514 , n8513 , n8511 );
and ( n8515 , n8514 , n6583 );
or ( n8516 , n8512 , n8515 );
not ( n8517 , n6583 );
buf ( n8518 , n5018 );
and ( n8519 , n8517 , n8518 );
buf ( n8520 , n5019 );
xor ( n8521 , n8520 , n8518 );
and ( n8522 , n8521 , n6583 );
or ( n8523 , n8519 , n8522 );
xor ( n8524 , n8516 , n8523 );
buf ( n8525 , n5020 );
xor ( n8526 , n8524 , n8525 );
buf ( n8527 , n5021 );
xor ( n8528 , n8526 , n8527 );
buf ( n8529 , n5022 );
xor ( n8530 , n8528 , n8529 );
xor ( n8531 , n8509 , n8530 );
not ( n8532 , n6583 );
buf ( n8533 , n5023 );
and ( n8534 , n8532 , n8533 );
buf ( n8535 , n5024 );
xor ( n8536 , n8535 , n8533 );
and ( n8537 , n8536 , n6583 );
or ( n8538 , n8534 , n8537 );
not ( n8539 , n6583 );
buf ( n8540 , n5025 );
and ( n8541 , n8539 , n8540 );
buf ( n8542 , n5026 );
xor ( n8543 , n8542 , n8540 );
and ( n8544 , n8543 , n6583 );
or ( n8545 , n8541 , n8544 );
xor ( n8546 , n8538 , n8545 );
buf ( n8547 , n5027 );
xor ( n8548 , n8546 , n8547 );
buf ( n8549 , n5028 );
xor ( n8550 , n8548 , n8549 );
buf ( n8551 , n5029 );
xor ( n8552 , n8550 , n8551 );
xor ( n8553 , n8531 , n8552 );
and ( n8554 , n8508 , n8553 );
xor ( n8555 , n8483 , n8554 );
xor ( n8556 , n8432 , n8555 );
not ( n8557 , n6583 );
buf ( n8558 , n5030 );
and ( n8559 , n8557 , n8558 );
buf ( n8560 , n5031 );
xor ( n8561 , n8560 , n8558 );
and ( n8562 , n8561 , n6583 );
or ( n8563 , n8559 , n8562 );
not ( n8564 , n6583 );
buf ( n8565 , n5032 );
and ( n8566 , n8564 , n8565 );
buf ( n8567 , n5033 );
xor ( n8568 , n8567 , n8565 );
and ( n8569 , n8568 , n6583 );
or ( n8570 , n8566 , n8569 );
not ( n8571 , n6583 );
buf ( n8572 , n5034 );
and ( n8573 , n8571 , n8572 );
buf ( n8574 , n5035 );
xor ( n8575 , n8574 , n8572 );
and ( n8576 , n8575 , n6583 );
or ( n8577 , n8573 , n8576 );
xor ( n8578 , n8570 , n8577 );
buf ( n8579 , n5036 );
xor ( n8580 , n8578 , n8579 );
buf ( n8581 , n5037 );
xor ( n8582 , n8580 , n8581 );
buf ( n8583 , n5038 );
xor ( n8584 , n8582 , n8583 );
xor ( n8585 , n8563 , n8584 );
not ( n8586 , n6583 );
buf ( n8587 , n5039 );
and ( n8588 , n8586 , n8587 );
buf ( n8589 , n5040 );
xor ( n8590 , n8589 , n8587 );
and ( n8591 , n8590 , n6583 );
or ( n8592 , n8588 , n8591 );
not ( n8593 , n6583 );
buf ( n8594 , n5041 );
and ( n8595 , n8593 , n8594 );
buf ( n8596 , n5042 );
xor ( n8597 , n8596 , n8594 );
and ( n8598 , n8597 , n6583 );
or ( n8599 , n8595 , n8598 );
xor ( n8600 , n8592 , n8599 );
buf ( n8601 , n5043 );
xor ( n8602 , n8600 , n8601 );
buf ( n8603 , n5044 );
xor ( n8604 , n8602 , n8603 );
buf ( n8605 , n5045 );
xor ( n8606 , n8604 , n8605 );
xor ( n8607 , n8585 , n8606 );
not ( n8608 , n7997 );
and ( n8609 , n8608 , n8020 );
xor ( n8610 , n8607 , n8609 );
xor ( n8611 , n8556 , n8610 );
xor ( n8612 , n8061 , n8611 );
buf ( n8613 , n5046 );
xor ( n8614 , n8613 , n7555 );
not ( n8615 , n6583 );
buf ( n8616 , n5047 );
and ( n8617 , n8615 , n8616 );
buf ( n8618 , n5048 );
xor ( n8619 , n8618 , n8616 );
and ( n8620 , n8619 , n6583 );
or ( n8621 , n8617 , n8620 );
not ( n8622 , n6583 );
buf ( n8623 , n5049 );
and ( n8624 , n8622 , n8623 );
buf ( n8625 , n5050 );
xor ( n8626 , n8625 , n8623 );
and ( n8627 , n8626 , n6583 );
or ( n8628 , n8624 , n8627 );
xor ( n8629 , n8621 , n8628 );
buf ( n8630 , n5051 );
xor ( n8631 , n8629 , n8630 );
buf ( n8632 , n5052 );
xor ( n8633 , n8631 , n8632 );
buf ( n8634 , n5053 );
xor ( n8635 , n8633 , n8634 );
xor ( n8636 , n8614 , n8635 );
buf ( n8637 , n5054 );
xor ( n8638 , n8637 , n7600 );
not ( n8639 , n6583 );
buf ( n8640 , n5055 );
and ( n8641 , n8639 , n8640 );
buf ( n8642 , n5056 );
xor ( n8643 , n8642 , n8640 );
and ( n8644 , n8643 , n6583 );
or ( n8645 , n8641 , n8644 );
buf ( n8646 , n5057 );
xor ( n8647 , n8645 , n8646 );
buf ( n8648 , n5058 );
xor ( n8649 , n8647 , n8648 );
buf ( n8650 , n5059 );
xor ( n8651 , n8649 , n8650 );
buf ( n8652 , n5060 );
xor ( n8653 , n8651 , n8652 );
xor ( n8654 , n8638 , n8653 );
not ( n8655 , n8654 );
buf ( n8656 , n5061 );
xor ( n8657 , n8656 , n7886 );
xor ( n8658 , n8657 , n7908 );
and ( n8659 , n8655 , n8658 );
xor ( n8660 , n8636 , n8659 );
buf ( n8661 , n5062 );
xor ( n8662 , n8661 , n6963 );
not ( n8663 , n6583 );
buf ( n8664 , n5063 );
and ( n8665 , n8663 , n8664 );
buf ( n8666 , n5064 );
xor ( n8667 , n8666 , n8664 );
and ( n8668 , n8667 , n6583 );
or ( n8669 , n8665 , n8668 );
not ( n8670 , n6583 );
buf ( n8671 , n5065 );
and ( n8672 , n8670 , n8671 );
buf ( n8673 , n5066 );
xor ( n8674 , n8673 , n8671 );
and ( n8675 , n8674 , n6583 );
or ( n8676 , n8672 , n8675 );
xor ( n8677 , n8669 , n8676 );
buf ( n8678 , n5067 );
xor ( n8679 , n8677 , n8678 );
buf ( n8680 , n5068 );
xor ( n8681 , n8679 , n8680 );
buf ( n8682 , n5069 );
xor ( n8683 , n8681 , n8682 );
xor ( n8684 , n8662 , n8683 );
not ( n8685 , n6583 );
buf ( n8686 , n5070 );
and ( n8687 , n8685 , n8686 );
buf ( n8688 , n5071 );
xor ( n8689 , n8688 , n8686 );
and ( n8690 , n8689 , n6583 );
or ( n8691 , n8687 , n8690 );
not ( n8692 , n6583 );
buf ( n8693 , n5072 );
and ( n8694 , n8692 , n8693 );
buf ( n8695 , n5073 );
xor ( n8696 , n8695 , n8693 );
and ( n8697 , n8696 , n6583 );
or ( n8698 , n8694 , n8697 );
xor ( n8699 , n8691 , n8698 );
buf ( n8700 , n5074 );
xor ( n8701 , n8699 , n8700 );
buf ( n8702 , n5075 );
xor ( n8703 , n8701 , n8702 );
buf ( n8704 , n5076 );
xor ( n8705 , n8703 , n8704 );
xor ( n8706 , n7629 , n8705 );
not ( n8707 , n6583 );
buf ( n8708 , n5077 );
and ( n8709 , n8707 , n8708 );
buf ( n8710 , n5078 );
xor ( n8711 , n8710 , n8708 );
and ( n8712 , n8711 , n6583 );
or ( n8713 , n8709 , n8712 );
not ( n8714 , n6583 );
buf ( n8715 , n5079 );
and ( n8716 , n8714 , n8715 );
buf ( n8717 , n5080 );
xor ( n8718 , n8717 , n8715 );
and ( n8719 , n8718 , n6583 );
or ( n8720 , n8716 , n8719 );
xor ( n8721 , n8713 , n8720 );
buf ( n8722 , n5081 );
xor ( n8723 , n8721 , n8722 );
buf ( n8724 , n5082 );
xor ( n8725 , n8723 , n8724 );
buf ( n8726 , n5083 );
xor ( n8727 , n8725 , n8726 );
xor ( n8728 , n8706 , n8727 );
not ( n8729 , n8728 );
buf ( n8730 , n5084 );
xor ( n8731 , n8730 , n8584 );
xor ( n8732 , n8731 , n8606 );
and ( n8733 , n8729 , n8732 );
xor ( n8734 , n8684 , n8733 );
xor ( n8735 , n8660 , n8734 );
buf ( n8736 , n5085 );
not ( n8737 , n6583 );
buf ( n8738 , n5086 );
and ( n8739 , n8737 , n8738 );
buf ( n8740 , n5087 );
xor ( n8741 , n8740 , n8738 );
and ( n8742 , n8741 , n6583 );
or ( n8743 , n8739 , n8742 );
not ( n8744 , n6583 );
buf ( n8745 , n5088 );
and ( n8746 , n8744 , n8745 );
buf ( n8747 , n5089 );
xor ( n8748 , n8747 , n8745 );
and ( n8749 , n8748 , n6583 );
or ( n8750 , n8746 , n8749 );
xor ( n8751 , n8743 , n8750 );
buf ( n8752 , n5090 );
xor ( n8753 , n8751 , n8752 );
buf ( n8754 , n5091 );
xor ( n8755 , n8753 , n8754 );
buf ( n8756 , n5092 );
xor ( n8757 , n8755 , n8756 );
xor ( n8758 , n8736 , n8757 );
buf ( n8759 , n5093 );
xor ( n8760 , n8439 , n8759 );
buf ( n8761 , n5094 );
xor ( n8762 , n8760 , n8761 );
buf ( n8763 , n5095 );
xor ( n8764 , n8762 , n8763 );
buf ( n8765 , n5096 );
xor ( n8766 , n8764 , n8765 );
xor ( n8767 , n8758 , n8766 );
buf ( n8768 , n5097 );
not ( n8769 , n6583 );
buf ( n8770 , n5098 );
and ( n8771 , n8769 , n8770 );
buf ( n8772 , n5099 );
xor ( n8773 , n8772 , n8770 );
and ( n8774 , n8773 , n6583 );
or ( n8775 , n8771 , n8774 );
not ( n8776 , n6583 );
buf ( n8777 , n5100 );
and ( n8778 , n8776 , n8777 );
buf ( n8779 , n5101 );
xor ( n8780 , n8779 , n8777 );
and ( n8781 , n8780 , n6583 );
or ( n8782 , n8778 , n8781 );
xor ( n8783 , n8775 , n8782 );
buf ( n8784 , n5102 );
xor ( n8785 , n8783 , n8784 );
buf ( n8786 , n5103 );
xor ( n8787 , n8785 , n8786 );
buf ( n8788 , n5104 );
xor ( n8789 , n8787 , n8788 );
xor ( n8790 , n8768 , n8789 );
xor ( n8791 , n8790 , n8530 );
not ( n8792 , n8791 );
not ( n8793 , n6583 );
buf ( n8794 , n5105 );
and ( n8795 , n8793 , n8794 );
buf ( n8796 , n5106 );
xor ( n8797 , n8796 , n8794 );
and ( n8798 , n8797 , n6583 );
or ( n8799 , n8795 , n8798 );
buf ( n8800 , n5107 );
xor ( n8801 , n8799 , n8800 );
buf ( n8802 , n5108 );
xor ( n8803 , n8801 , n8802 );
buf ( n8804 , n5109 );
xor ( n8805 , n8803 , n8804 );
buf ( n8806 , n5110 );
xor ( n8807 , n8805 , n8806 );
xor ( n8808 , n6848 , n8807 );
not ( n8809 , n6583 );
buf ( n8810 , n5111 );
and ( n8811 , n8809 , n8810 );
buf ( n8812 , n5112 );
xor ( n8813 , n8812 , n8810 );
and ( n8814 , n8813 , n6583 );
or ( n8815 , n8811 , n8814 );
xor ( n8816 , n8815 , n7347 );
buf ( n8817 , n5113 );
xor ( n8818 , n8816 , n8817 );
buf ( n8819 , n5114 );
xor ( n8820 , n8818 , n8819 );
buf ( n8821 , n5115 );
xor ( n8822 , n8820 , n8821 );
xor ( n8823 , n8808 , n8822 );
and ( n8824 , n8792 , n8823 );
xor ( n8825 , n8767 , n8824 );
xor ( n8826 , n8735 , n8825 );
buf ( n8827 , n5116 );
not ( n8828 , n6583 );
buf ( n8829 , n5117 );
and ( n8830 , n8828 , n8829 );
buf ( n8831 , n5118 );
xor ( n8832 , n8831 , n8829 );
and ( n8833 , n8832 , n6583 );
or ( n8834 , n8830 , n8833 );
xor ( n8835 , n8834 , n6644 );
buf ( n8836 , n5119 );
xor ( n8837 , n8835 , n8836 );
buf ( n8838 , n5120 );
xor ( n8839 , n8837 , n8838 );
buf ( n8840 , n5121 );
xor ( n8841 , n8839 , n8840 );
xor ( n8842 , n8827 , n8841 );
not ( n8843 , n6583 );
buf ( n8844 , n5122 );
and ( n8845 , n8843 , n8844 );
buf ( n8846 , n5123 );
xor ( n8847 , n8846 , n8844 );
and ( n8848 , n8847 , n6583 );
or ( n8849 , n8845 , n8848 );
not ( n8850 , n6583 );
buf ( n8851 , n5124 );
and ( n8852 , n8850 , n8851 );
buf ( n8853 , n5125 );
xor ( n8854 , n8853 , n8851 );
and ( n8855 , n8854 , n6583 );
or ( n8856 , n8852 , n8855 );
xor ( n8857 , n8849 , n8856 );
buf ( n8858 , n5126 );
xor ( n8859 , n8857 , n8858 );
buf ( n8860 , n5127 );
xor ( n8861 , n8859 , n8860 );
buf ( n8862 , n5128 );
xor ( n8863 , n8861 , n8862 );
xor ( n8864 , n8842 , n8863 );
buf ( n8865 , n5129 );
not ( n8866 , n6583 );
buf ( n8867 , n5130 );
and ( n8868 , n8866 , n8867 );
buf ( n8869 , n5131 );
xor ( n8870 , n8869 , n8867 );
and ( n8871 , n8870 , n6583 );
or ( n8872 , n8868 , n8871 );
not ( n8873 , n6583 );
buf ( n8874 , n5132 );
and ( n8875 , n8873 , n8874 );
buf ( n8876 , n5133 );
xor ( n8877 , n8876 , n8874 );
and ( n8878 , n8877 , n6583 );
or ( n8879 , n8875 , n8878 );
xor ( n8880 , n8872 , n8879 );
buf ( n8881 , n5134 );
xor ( n8882 , n8880 , n8881 );
buf ( n8883 , n5135 );
xor ( n8884 , n8882 , n8883 );
buf ( n8885 , n5136 );
xor ( n8886 , n8884 , n8885 );
xor ( n8887 , n8865 , n8886 );
not ( n8888 , n6583 );
buf ( n8889 , n5137 );
and ( n8890 , n8888 , n8889 );
buf ( n8891 , n5138 );
xor ( n8892 , n8891 , n8889 );
and ( n8893 , n8892 , n6583 );
or ( n8894 , n8890 , n8893 );
not ( n8895 , n6583 );
buf ( n8896 , n5139 );
and ( n8897 , n8895 , n8896 );
buf ( n8898 , n5140 );
xor ( n8899 , n8898 , n8896 );
and ( n8900 , n8899 , n6583 );
or ( n8901 , n8897 , n8900 );
xor ( n8902 , n8894 , n8901 );
buf ( n8903 , n5141 );
xor ( n8904 , n8902 , n8903 );
buf ( n8905 , n5142 );
xor ( n8906 , n8904 , n8905 );
buf ( n8907 , n5143 );
xor ( n8908 , n8906 , n8907 );
xor ( n8909 , n8887 , n8908 );
not ( n8910 , n8909 );
buf ( n8911 , n5144 );
not ( n8912 , n6583 );
buf ( n8913 , n5145 );
and ( n8914 , n8912 , n8913 );
buf ( n8915 , n5146 );
xor ( n8916 , n8915 , n8913 );
and ( n8917 , n8916 , n6583 );
or ( n8918 , n8914 , n8917 );
not ( n8919 , n6583 );
buf ( n8920 , n5147 );
and ( n8921 , n8919 , n8920 );
buf ( n8922 , n5148 );
xor ( n8923 , n8922 , n8920 );
and ( n8924 , n8923 , n6583 );
or ( n8925 , n8921 , n8924 );
xor ( n8926 , n8918 , n8925 );
buf ( n8927 , n5149 );
xor ( n8928 , n8926 , n8927 );
buf ( n8929 , n5150 );
xor ( n8930 , n8928 , n8929 );
buf ( n8931 , n5151 );
xor ( n8932 , n8930 , n8931 );
xor ( n8933 , n8911 , n8932 );
not ( n8934 , n6583 );
buf ( n8935 , n5152 );
and ( n8936 , n8934 , n8935 );
buf ( n8937 , n5153 );
xor ( n8938 , n8937 , n8935 );
and ( n8939 , n8938 , n6583 );
or ( n8940 , n8936 , n8939 );
buf ( n8941 , n5154 );
xor ( n8942 , n8940 , n8941 );
buf ( n8943 , n5155 );
xor ( n8944 , n8942 , n8943 );
buf ( n8945 , n5156 );
xor ( n8946 , n8944 , n8945 );
buf ( n8947 , n5157 );
xor ( n8948 , n8946 , n8947 );
xor ( n8949 , n8933 , n8948 );
and ( n8950 , n8910 , n8949 );
xor ( n8951 , n8864 , n8950 );
xor ( n8952 , n8826 , n8951 );
buf ( n8953 , n5158 );
not ( n8954 , n6583 );
buf ( n8955 , n5159 );
and ( n8956 , n8954 , n8955 );
buf ( n8957 , n5160 );
xor ( n8958 , n8957 , n8955 );
and ( n8959 , n8958 , n6583 );
or ( n8960 , n8956 , n8959 );
not ( n8961 , n6583 );
buf ( n8962 , n5161 );
and ( n8963 , n8961 , n8962 );
buf ( n8964 , n5162 );
xor ( n8965 , n8964 , n8962 );
and ( n8966 , n8965 , n6583 );
or ( n8967 , n8963 , n8966 );
xor ( n8968 , n8960 , n8967 );
buf ( n8969 , n5163 );
xor ( n8970 , n8968 , n8969 );
buf ( n8971 , n5164 );
xor ( n8972 , n8970 , n8971 );
buf ( n8973 , n5165 );
xor ( n8974 , n8972 , n8973 );
xor ( n8975 , n8953 , n8974 );
xor ( n8976 , n8975 , n7216 );
buf ( n8977 , n5166 );
not ( n8978 , n6583 );
buf ( n8979 , n5167 );
and ( n8980 , n8978 , n8979 );
buf ( n8981 , n5168 );
xor ( n8982 , n8981 , n8979 );
and ( n8983 , n8982 , n6583 );
or ( n8984 , n8980 , n8983 );
buf ( n8985 , n5169 );
xor ( n8986 , n8984 , n8985 );
buf ( n8987 , n5170 );
xor ( n8988 , n8986 , n8987 );
buf ( n8989 , n5171 );
xor ( n8990 , n8988 , n8989 );
buf ( n8991 , n5172 );
xor ( n8992 , n8990 , n8991 );
xor ( n8993 , n8977 , n8992 );
xor ( n8994 , n8993 , n8167 );
not ( n8995 , n8994 );
buf ( n8996 , n5173 );
xor ( n8997 , n8996 , n6636 );
not ( n8998 , n6583 );
buf ( n8999 , n5174 );
and ( n9000 , n8998 , n8999 );
buf ( n9001 , n5175 );
xor ( n9002 , n9001 , n8999 );
and ( n9003 , n9002 , n6583 );
or ( n9004 , n9000 , n9003 );
not ( n9005 , n6583 );
buf ( n9006 , n5176 );
and ( n9007 , n9005 , n9006 );
buf ( n9008 , n5177 );
xor ( n9009 , n9008 , n9006 );
and ( n9010 , n9009 , n6583 );
or ( n9011 , n9007 , n9010 );
xor ( n9012 , n9004 , n9011 );
buf ( n9013 , n5178 );
xor ( n9014 , n9012 , n9013 );
buf ( n9015 , n5179 );
xor ( n9016 , n9014 , n9015 );
buf ( n9017 , n5180 );
xor ( n9018 , n9016 , n9017 );
xor ( n9019 , n8997 , n9018 );
and ( n9020 , n8995 , n9019 );
xor ( n9021 , n8976 , n9020 );
xor ( n9022 , n8952 , n9021 );
xor ( n9023 , n8612 , n9022 );
not ( n9024 , n9023 );
buf ( n9025 , n5181 );
not ( n9026 , n6583 );
buf ( n9027 , n5182 );
and ( n9028 , n9026 , n9027 );
buf ( n9029 , n5183 );
xor ( n9030 , n9029 , n9027 );
and ( n9031 , n9030 , n6583 );
or ( n9032 , n9028 , n9031 );
not ( n9033 , n6583 );
buf ( n9034 , n5184 );
and ( n9035 , n9033 , n9034 );
buf ( n9036 , n5185 );
xor ( n9037 , n9036 , n9034 );
and ( n9038 , n9037 , n6583 );
or ( n9039 , n9035 , n9038 );
xor ( n9040 , n9032 , n9039 );
buf ( n9041 , n5186 );
xor ( n9042 , n9040 , n9041 );
buf ( n9043 , n5187 );
xor ( n9044 , n9042 , n9043 );
buf ( n9045 , n5188 );
xor ( n9046 , n9044 , n9045 );
xor ( n9047 , n9025 , n9046 );
xor ( n9048 , n9047 , n8974 );
not ( n9049 , n6583 );
buf ( n9050 , n5189 );
and ( n9051 , n9049 , n9050 );
buf ( n9052 , n5190 );
xor ( n9053 , n9052 , n9050 );
and ( n9054 , n9053 , n6583 );
or ( n9055 , n9051 , n9054 );
not ( n9056 , n6583 );
buf ( n9057 , n5191 );
and ( n9058 , n9056 , n9057 );
buf ( n9059 , n5192 );
xor ( n9060 , n9059 , n9057 );
and ( n9061 , n9060 , n6583 );
or ( n9062 , n9058 , n9061 );
xor ( n9063 , n9055 , n9062 );
buf ( n9064 , n5193 );
xor ( n9065 , n9063 , n9064 );
buf ( n9066 , n5194 );
xor ( n9067 , n9065 , n9066 );
buf ( n9068 , n5195 );
xor ( n9069 , n9067 , n9068 );
xor ( n9070 , n8905 , n9069 );
not ( n9071 , n6583 );
buf ( n9072 , n5196 );
and ( n9073 , n9071 , n9072 );
buf ( n9074 , n5197 );
xor ( n9075 , n9074 , n9072 );
and ( n9076 , n9075 , n6583 );
or ( n9077 , n9073 , n9076 );
buf ( n9078 , n5198 );
xor ( n9079 , n9077 , n9078 );
buf ( n9080 , n5199 );
xor ( n9081 , n9079 , n9080 );
buf ( n9082 , n5200 );
xor ( n9083 , n9081 , n9082 );
buf ( n9084 , n5201 );
xor ( n9085 , n9083 , n9084 );
xor ( n9086 , n9070 , n9085 );
not ( n9087 , n9086 );
buf ( n9088 , n5202 );
not ( n9089 , n6583 );
buf ( n9090 , n5203 );
and ( n9091 , n9089 , n9090 );
buf ( n9092 , n5204 );
xor ( n9093 , n9092 , n9090 );
and ( n9094 , n9093 , n6583 );
or ( n9095 , n9091 , n9094 );
not ( n9096 , n6583 );
buf ( n9097 , n5205 );
and ( n9098 , n9096 , n9097 );
buf ( n9099 , n5206 );
xor ( n9100 , n9099 , n9097 );
and ( n9101 , n9100 , n6583 );
or ( n9102 , n9098 , n9101 );
xor ( n9103 , n9095 , n9102 );
buf ( n9104 , n5207 );
xor ( n9105 , n9103 , n9104 );
buf ( n9106 , n5208 );
xor ( n9107 , n9105 , n9106 );
buf ( n9108 , n5209 );
xor ( n9109 , n9107 , n9108 );
xor ( n9110 , n9088 , n9109 );
xor ( n9111 , n9110 , n8841 );
and ( n9112 , n9087 , n9111 );
xor ( n9113 , n9048 , n9112 );
xor ( n9114 , n6812 , n7073 );
xor ( n9115 , n9114 , n7095 );
not ( n9116 , n9048 );
and ( n9117 , n9116 , n9086 );
xor ( n9118 , n9115 , n9117 );
buf ( n9119 , n5210 );
not ( n9120 , n6583 );
buf ( n9121 , n5211 );
and ( n9122 , n9120 , n9121 );
buf ( n9123 , n5212 );
xor ( n9124 , n9123 , n9121 );
and ( n9125 , n9124 , n6583 );
or ( n9126 , n9122 , n9125 );
not ( n9127 , n6583 );
buf ( n9128 , n5213 );
and ( n9129 , n9127 , n9128 );
buf ( n9130 , n5214 );
xor ( n9131 , n9130 , n9128 );
and ( n9132 , n9131 , n6583 );
or ( n9133 , n9129 , n9132 );
xor ( n9134 , n9126 , n9133 );
buf ( n9135 , n5215 );
xor ( n9136 , n9134 , n9135 );
buf ( n9137 , n5216 );
xor ( n9138 , n9136 , n9137 );
buf ( n9139 , n5217 );
xor ( n9140 , n9138 , n9139 );
xor ( n9141 , n9119 , n9140 );
not ( n9142 , n6583 );
buf ( n9143 , n5218 );
and ( n9144 , n9142 , n9143 );
buf ( n9145 , n5219 );
xor ( n9146 , n9145 , n9143 );
and ( n9147 , n9146 , n6583 );
or ( n9148 , n9144 , n9147 );
not ( n9149 , n6583 );
buf ( n9150 , n5220 );
and ( n9151 , n9149 , n9150 );
buf ( n9152 , n5221 );
xor ( n9153 , n9152 , n9150 );
and ( n9154 , n9153 , n6583 );
or ( n9155 , n9151 , n9154 );
xor ( n9156 , n9148 , n9155 );
buf ( n9157 , n5222 );
xor ( n9158 , n9156 , n9157 );
xor ( n9159 , n9158 , n7911 );
buf ( n9160 , n5223 );
xor ( n9161 , n9159 , n9160 );
xor ( n9162 , n9141 , n9161 );
buf ( n9163 , n5224 );
not ( n9164 , n6583 );
buf ( n9165 , n5225 );
and ( n9166 , n9164 , n9165 );
buf ( n9167 , n5226 );
xor ( n9168 , n9167 , n9165 );
and ( n9169 , n9168 , n6583 );
or ( n9170 , n9166 , n9169 );
buf ( n9171 , n5227 );
xor ( n9172 , n9170 , n9171 );
buf ( n9173 , n5228 );
xor ( n9174 , n9172 , n9173 );
buf ( n9175 , n5229 );
xor ( n9176 , n9174 , n9175 );
buf ( n9177 , n5230 );
xor ( n9178 , n9176 , n9177 );
xor ( n9179 , n9163 , n9178 );
not ( n9180 , n6583 );
buf ( n9181 , n5231 );
and ( n9182 , n9180 , n9181 );
buf ( n9183 , n5232 );
xor ( n9184 , n9183 , n9181 );
and ( n9185 , n9184 , n6583 );
or ( n9186 , n9182 , n9185 );
not ( n9187 , n6583 );
buf ( n9188 , n5233 );
and ( n9189 , n9187 , n9188 );
buf ( n9190 , n5234 );
xor ( n9191 , n9190 , n9188 );
and ( n9192 , n9191 , n6583 );
or ( n9193 , n9189 , n9192 );
xor ( n9194 , n9186 , n9193 );
buf ( n9195 , n5235 );
xor ( n9196 , n9194 , n9195 );
buf ( n9197 , n5236 );
xor ( n9198 , n9196 , n9197 );
buf ( n9199 , n5237 );
xor ( n9200 , n9198 , n9199 );
xor ( n9201 , n9179 , n9200 );
not ( n9202 , n9201 );
buf ( n9203 , n5238 );
xor ( n9204 , n9203 , n7216 );
xor ( n9205 , n9204 , n7238 );
and ( n9206 , n9202 , n9205 );
xor ( n9207 , n9162 , n9206 );
xor ( n9208 , n9118 , n9207 );
not ( n9209 , n6583 );
buf ( n9210 , n5239 );
and ( n9211 , n9209 , n9210 );
buf ( n9212 , n5240 );
xor ( n9213 , n9212 , n9210 );
and ( n9214 , n9213 , n6583 );
or ( n9215 , n9211 , n9214 );
not ( n9216 , n6583 );
buf ( n9217 , n5241 );
and ( n9218 , n9216 , n9217 );
buf ( n9219 , n5242 );
xor ( n9220 , n9219 , n9217 );
and ( n9221 , n9220 , n6583 );
or ( n9222 , n9218 , n9221 );
xor ( n9223 , n9215 , n9222 );
buf ( n9224 , n5243 );
xor ( n9225 , n9223 , n9224 );
buf ( n9226 , n5244 );
xor ( n9227 , n9225 , n9226 );
buf ( n9228 , n5245 );
xor ( n9229 , n9227 , n9228 );
xor ( n9230 , n8333 , n9229 );
not ( n9231 , n6583 );
buf ( n9232 , n5246 );
and ( n9233 , n9231 , n9232 );
buf ( n9234 , n5247 );
xor ( n9235 , n9234 , n9232 );
and ( n9236 , n9235 , n6583 );
or ( n9237 , n9233 , n9236 );
xor ( n9238 , n6926 , n9237 );
buf ( n9239 , n5248 );
xor ( n9240 , n9238 , n9239 );
buf ( n9241 , n5249 );
xor ( n9242 , n9240 , n9241 );
buf ( n9243 , n5250 );
xor ( n9244 , n9242 , n9243 );
xor ( n9245 , n9230 , n9244 );
buf ( n9246 , n5251 );
xor ( n9247 , n9246 , n7390 );
not ( n9248 , n6583 );
buf ( n9249 , n5252 );
and ( n9250 , n9248 , n9249 );
buf ( n9251 , n5253 );
xor ( n9252 , n9251 , n9249 );
and ( n9253 , n9252 , n6583 );
or ( n9254 , n9250 , n9253 );
buf ( n9255 , n5254 );
xor ( n9256 , n9254 , n9255 );
buf ( n9257 , n5255 );
xor ( n9258 , n9256 , n9257 );
buf ( n9259 , n5256 );
xor ( n9260 , n9258 , n9259 );
buf ( n9261 , n5257 );
xor ( n9262 , n9260 , n9261 );
xor ( n9263 , n9247 , n9262 );
not ( n9264 , n9263 );
not ( n9265 , n6583 );
buf ( n9266 , n5258 );
and ( n9267 , n9265 , n9266 );
buf ( n9268 , n5259 );
xor ( n9269 , n9268 , n9266 );
and ( n9270 , n9269 , n6583 );
or ( n9271 , n9267 , n9270 );
not ( n9272 , n6583 );
buf ( n9273 , n5260 );
and ( n9274 , n9272 , n9273 );
buf ( n9275 , n5261 );
xor ( n9276 , n9275 , n9273 );
and ( n9277 , n9276 , n6583 );
or ( n9278 , n9274 , n9277 );
xor ( n9279 , n9271 , n9278 );
buf ( n9280 , n5262 );
xor ( n9281 , n9279 , n9280 );
buf ( n9282 , n5263 );
xor ( n9283 , n9281 , n9282 );
buf ( n9284 , n5264 );
xor ( n9285 , n9283 , n9284 );
xor ( n9286 , n6960 , n9285 );
not ( n9287 , n6583 );
buf ( n9288 , n5265 );
and ( n9289 , n9287 , n9288 );
buf ( n9290 , n5266 );
xor ( n9291 , n9290 , n9288 );
and ( n9292 , n9291 , n6583 );
or ( n9293 , n9289 , n9292 );
not ( n9294 , n6583 );
buf ( n9295 , n5267 );
and ( n9296 , n9294 , n9295 );
buf ( n9297 , n5268 );
xor ( n9298 , n9297 , n9295 );
and ( n9299 , n9298 , n6583 );
or ( n9300 , n9296 , n9299 );
xor ( n9301 , n9293 , n9300 );
buf ( n9302 , n5269 );
xor ( n9303 , n9301 , n9302 );
buf ( n9304 , n5270 );
xor ( n9305 , n9303 , n9304 );
buf ( n9306 , n5271 );
xor ( n9307 , n9305 , n9306 );
xor ( n9308 , n9286 , n9307 );
and ( n9309 , n9264 , n9308 );
xor ( n9310 , n9245 , n9309 );
xor ( n9311 , n9208 , n9310 );
not ( n9312 , n6583 );
buf ( n9313 , n5272 );
and ( n9314 , n9312 , n9313 );
buf ( n9315 , n5273 );
xor ( n9316 , n9315 , n9313 );
and ( n9317 , n9316 , n6583 );
or ( n9318 , n9314 , n9317 );
xor ( n9319 , n9318 , n7189 );
not ( n9320 , n6583 );
buf ( n9321 , n5274 );
and ( n9322 , n9320 , n9321 );
buf ( n9323 , n5275 );
xor ( n9324 , n9323 , n9321 );
and ( n9325 , n9324 , n6583 );
or ( n9326 , n9322 , n9325 );
not ( n9327 , n6583 );
buf ( n9328 , n5276 );
and ( n9329 , n9327 , n9328 );
buf ( n9330 , n5277 );
xor ( n9331 , n9330 , n9328 );
and ( n9332 , n9331 , n6583 );
or ( n9333 , n9329 , n9332 );
xor ( n9334 , n9326 , n9333 );
buf ( n9335 , n5278 );
xor ( n9336 , n9334 , n9335 );
buf ( n9337 , n5279 );
xor ( n9338 , n9336 , n9337 );
buf ( n9339 , n5280 );
xor ( n9340 , n9338 , n9339 );
xor ( n9341 , n9319 , n9340 );
not ( n9342 , n6583 );
buf ( n9343 , n5281 );
and ( n9344 , n9342 , n9343 );
buf ( n9345 , n5282 );
xor ( n9346 , n9345 , n9343 );
and ( n9347 , n9346 , n6583 );
or ( n9348 , n9344 , n9347 );
not ( n9349 , n6583 );
buf ( n9350 , n5283 );
and ( n9351 , n9349 , n9350 );
buf ( n9352 , n5284 );
xor ( n9353 , n9352 , n9350 );
and ( n9354 , n9353 , n6583 );
or ( n9355 , n9351 , n9354 );
xor ( n9356 , n9348 , n9355 );
buf ( n9357 , n5285 );
xor ( n9358 , n9356 , n9357 );
buf ( n9359 , n5286 );
xor ( n9360 , n9358 , n9359 );
buf ( n9361 , n5287 );
xor ( n9362 , n9360 , n9361 );
xor ( n9363 , n8364 , n9362 );
not ( n9364 , n6583 );
buf ( n9365 , n5288 );
and ( n9366 , n9364 , n9365 );
buf ( n9367 , n5289 );
xor ( n9368 , n9367 , n9365 );
and ( n9369 , n9368 , n6583 );
or ( n9370 , n9366 , n9369 );
not ( n9371 , n6583 );
buf ( n9372 , n5290 );
and ( n9373 , n9371 , n9372 );
buf ( n9374 , n5291 );
xor ( n9375 , n9374 , n9372 );
and ( n9376 , n9375 , n6583 );
or ( n9377 , n9373 , n9376 );
xor ( n9378 , n9370 , n9377 );
buf ( n9379 , n5292 );
xor ( n9380 , n9378 , n9379 );
buf ( n9381 , n5293 );
xor ( n9382 , n9380 , n9381 );
buf ( n9383 , n5294 );
xor ( n9384 , n9382 , n9383 );
xor ( n9385 , n9363 , n9384 );
not ( n9386 , n9385 );
not ( n9387 , n6583 );
buf ( n9388 , n5295 );
and ( n9389 , n9387 , n9388 );
buf ( n9390 , n5296 );
xor ( n9391 , n9390 , n9388 );
and ( n9392 , n9391 , n6583 );
or ( n9393 , n9389 , n9392 );
not ( n9394 , n6583 );
buf ( n9395 , n5297 );
and ( n9396 , n9394 , n9395 );
buf ( n9397 , n5298 );
xor ( n9398 , n9397 , n9395 );
and ( n9399 , n9398 , n6583 );
or ( n9400 , n9396 , n9399 );
xor ( n9401 , n9393 , n9400 );
xor ( n9402 , n9401 , n8827 );
buf ( n9403 , n5299 );
xor ( n9404 , n9402 , n9403 );
buf ( n9405 , n5300 );
xor ( n9406 , n9404 , n9405 );
xor ( n9407 , n8549 , n9406 );
not ( n9408 , n6583 );
buf ( n9409 , n5301 );
and ( n9410 , n9408 , n9409 );
buf ( n9411 , n5302 );
xor ( n9412 , n9411 , n9409 );
and ( n9413 , n9412 , n6583 );
or ( n9414 , n9410 , n9413 );
not ( n9415 , n6583 );
buf ( n9416 , n5303 );
and ( n9417 , n9415 , n9416 );
buf ( n9418 , n5304 );
xor ( n9419 , n9418 , n9416 );
and ( n9420 , n9419 , n6583 );
or ( n9421 , n9417 , n9420 );
xor ( n9422 , n9414 , n9421 );
buf ( n9423 , n5305 );
xor ( n9424 , n9422 , n9423 );
buf ( n9425 , n5306 );
xor ( n9426 , n9424 , n9425 );
buf ( n9427 , n5307 );
xor ( n9428 , n9426 , n9427 );
xor ( n9429 , n9407 , n9428 );
and ( n9430 , n9386 , n9429 );
xor ( n9431 , n9341 , n9430 );
xor ( n9432 , n9311 , n9431 );
not ( n9433 , n6583 );
buf ( n9434 , n5308 );
and ( n9435 , n9433 , n9434 );
buf ( n9436 , n5309 );
xor ( n9437 , n9436 , n9434 );
and ( n9438 , n9437 , n6583 );
or ( n9439 , n9435 , n9438 );
xor ( n9440 , n9439 , n7804 );
not ( n9441 , n6583 );
buf ( n9442 , n5310 );
and ( n9443 , n9441 , n9442 );
buf ( n9444 , n5311 );
xor ( n9445 , n9444 , n9442 );
and ( n9446 , n9445 , n6583 );
or ( n9447 , n9443 , n9446 );
buf ( n9448 , n5312 );
xor ( n9449 , n9447 , n9448 );
buf ( n9450 , n5313 );
xor ( n9451 , n9449 , n9450 );
buf ( n9452 , n5314 );
xor ( n9453 , n9451 , n9452 );
buf ( n9454 , n5315 );
xor ( n9455 , n9453 , n9454 );
xor ( n9456 , n9440 , n9455 );
buf ( n9457 , n5316 );
not ( n9458 , n6583 );
buf ( n9459 , n5317 );
and ( n9460 , n9458 , n9459 );
buf ( n9461 , n5318 );
xor ( n9462 , n9461 , n9459 );
and ( n9463 , n9462 , n6583 );
or ( n9464 , n9460 , n9463 );
not ( n9465 , n6583 );
buf ( n9466 , n5319 );
and ( n9467 , n9465 , n9466 );
buf ( n9468 , n5320 );
xor ( n9469 , n9468 , n9466 );
and ( n9470 , n9469 , n6583 );
or ( n9471 , n9467 , n9470 );
xor ( n9472 , n9464 , n9471 );
buf ( n9473 , n5321 );
xor ( n9474 , n9472 , n9473 );
buf ( n9475 , n5322 );
xor ( n9476 , n9474 , n9475 );
buf ( n9477 , n5323 );
xor ( n9478 , n9476 , n9477 );
xor ( n9479 , n9457 , n9478 );
not ( n9480 , n6583 );
buf ( n9481 , n5324 );
and ( n9482 , n9480 , n9481 );
buf ( n9483 , n5325 );
xor ( n9484 , n9483 , n9481 );
and ( n9485 , n9484 , n6583 );
or ( n9486 , n9482 , n9485 );
xor ( n9487 , n9486 , n8490 );
buf ( n9488 , n5326 );
xor ( n9489 , n9487 , n9488 );
buf ( n9490 , n5327 );
xor ( n9491 , n9489 , n9490 );
buf ( n9492 , n5328 );
xor ( n9493 , n9491 , n9492 );
xor ( n9494 , n9479 , n9493 );
not ( n9495 , n9494 );
buf ( n9496 , n5329 );
not ( n9497 , n6583 );
buf ( n9498 , n5330 );
and ( n9499 , n9497 , n9498 );
buf ( n9500 , n5331 );
xor ( n9501 , n9500 , n9498 );
and ( n9502 , n9501 , n6583 );
or ( n9503 , n9499 , n9502 );
buf ( n9504 , n5332 );
xor ( n9505 , n9503 , n9504 );
buf ( n9506 , n5333 );
xor ( n9507 , n9505 , n9506 );
buf ( n9508 , n5334 );
xor ( n9509 , n9507 , n9508 );
buf ( n9510 , n5335 );
xor ( n9511 , n9509 , n9510 );
xor ( n9512 , n9496 , n9511 );
not ( n9513 , n6583 );
buf ( n9514 , n5336 );
and ( n9515 , n9513 , n9514 );
buf ( n9516 , n5337 );
xor ( n9517 , n9516 , n9514 );
and ( n9518 , n9517 , n6583 );
or ( n9519 , n9515 , n9518 );
not ( n9520 , n6583 );
buf ( n9521 , n5338 );
and ( n9522 , n9520 , n9521 );
buf ( n9523 , n5339 );
xor ( n9524 , n9523 , n9521 );
and ( n9525 , n9524 , n6583 );
or ( n9526 , n9522 , n9525 );
xor ( n9527 , n9519 , n9526 );
buf ( n9528 , n5340 );
xor ( n9529 , n9527 , n9528 );
buf ( n9530 , n5341 );
xor ( n9531 , n9529 , n9530 );
buf ( n9532 , n5342 );
xor ( n9533 , n9531 , n9532 );
xor ( n9534 , n9512 , n9533 );
and ( n9535 , n9495 , n9534 );
xor ( n9536 , n9456 , n9535 );
xor ( n9537 , n9432 , n9536 );
xor ( n9538 , n9113 , n9537 );
buf ( n9539 , n5343 );
not ( n9540 , n6583 );
buf ( n9541 , n5344 );
and ( n9542 , n9540 , n9541 );
buf ( n9543 , n5345 );
xor ( n9544 , n9543 , n9541 );
and ( n9545 , n9544 , n6583 );
or ( n9546 , n9542 , n9545 );
not ( n9547 , n6583 );
buf ( n9548 , n5346 );
and ( n9549 , n9547 , n9548 );
buf ( n9550 , n5347 );
xor ( n9551 , n9550 , n9548 );
and ( n9552 , n9551 , n6583 );
or ( n9553 , n9549 , n9552 );
xor ( n9554 , n9546 , n9553 );
buf ( n9555 , n5348 );
xor ( n9556 , n9554 , n9555 );
buf ( n9557 , n5349 );
xor ( n9558 , n9556 , n9557 );
buf ( n9559 , n5350 );
xor ( n9560 , n9558 , n9559 );
xor ( n9561 , n9539 , n9560 );
xor ( n9562 , n9561 , n8807 );
not ( n9563 , n6583 );
buf ( n9564 , n5351 );
and ( n9565 , n9563 , n9564 );
buf ( n9566 , n5352 );
xor ( n9567 , n9566 , n9564 );
and ( n9568 , n9567 , n6583 );
or ( n9569 , n9565 , n9568 );
not ( n9570 , n6583 );
buf ( n9571 , n5353 );
and ( n9572 , n9570 , n9571 );
buf ( n9573 , n5354 );
xor ( n9574 , n9573 , n9571 );
and ( n9575 , n9574 , n6583 );
or ( n9576 , n9572 , n9575 );
xor ( n9577 , n9569 , n9576 );
buf ( n9578 , n5355 );
xor ( n9579 , n9577 , n9578 );
buf ( n9580 , n5356 );
xor ( n9581 , n9579 , n9580 );
buf ( n9582 , n5357 );
xor ( n9583 , n9581 , n9582 );
xor ( n9584 , n6658 , n9583 );
not ( n9585 , n6583 );
buf ( n9586 , n5358 );
and ( n9587 , n9585 , n9586 );
buf ( n9588 , n5359 );
xor ( n9589 , n9588 , n9586 );
and ( n9590 , n9589 , n6583 );
or ( n9591 , n9587 , n9590 );
xor ( n9592 , n9591 , n7722 );
buf ( n9593 , n5360 );
xor ( n9594 , n9592 , n9593 );
buf ( n9595 , n5361 );
xor ( n9596 , n9594 , n9595 );
buf ( n9597 , n5362 );
xor ( n9598 , n9596 , n9597 );
xor ( n9599 , n9584 , n9598 );
not ( n9600 , n9599 );
not ( n9601 , n6583 );
buf ( n9602 , n5363 );
and ( n9603 , n9601 , n9602 );
buf ( n9604 , n5364 );
xor ( n9605 , n9604 , n9602 );
and ( n9606 , n9605 , n6583 );
or ( n9607 , n9603 , n9606 );
buf ( n9608 , n5365 );
xor ( n9609 , n9607 , n9608 );
buf ( n9610 , n5366 );
xor ( n9611 , n9609 , n9610 );
buf ( n9612 , n5367 );
xor ( n9613 , n9611 , n9612 );
buf ( n9614 , n5368 );
xor ( n9615 , n9613 , n9614 );
xor ( n9616 , n7502 , n9615 );
xor ( n9617 , n9616 , n8584 );
and ( n9618 , n9600 , n9617 );
xor ( n9619 , n9562 , n9618 );
not ( n9620 , n6583 );
buf ( n9621 , n5369 );
and ( n9622 , n9620 , n9621 );
buf ( n9623 , n5370 );
xor ( n9624 , n9623 , n9621 );
and ( n9625 , n9624 , n6583 );
or ( n9626 , n9622 , n9625 );
not ( n9627 , n6583 );
buf ( n9628 , n5371 );
and ( n9629 , n9627 , n9628 );
buf ( n9630 , n5372 );
xor ( n9631 , n9630 , n9628 );
and ( n9632 , n9631 , n6583 );
or ( n9633 , n9629 , n9632 );
xor ( n9634 , n9626 , n9633 );
buf ( n9635 , n5373 );
xor ( n9636 , n9634 , n9635 );
xor ( n9637 , n9636 , n8977 );
buf ( n9638 , n5374 );
xor ( n9639 , n9637 , n9638 );
xor ( n9640 , n8055 , n9639 );
not ( n9641 , n6583 );
buf ( n9642 , n5375 );
and ( n9643 , n9641 , n9642 );
buf ( n9644 , n5376 );
xor ( n9645 , n9644 , n9642 );
and ( n9646 , n9645 , n6583 );
or ( n9647 , n9643 , n9646 );
not ( n9648 , n6583 );
buf ( n9649 , n5377 );
and ( n9650 , n9648 , n9649 );
buf ( n9651 , n5378 );
xor ( n9652 , n9651 , n9649 );
and ( n9653 , n9652 , n6583 );
or ( n9654 , n9650 , n9653 );
xor ( n9655 , n9647 , n9654 );
xor ( n9656 , n9655 , n8145 );
buf ( n9657 , n5379 );
xor ( n9658 , n9656 , n9657 );
buf ( n9659 , n5380 );
xor ( n9660 , n9658 , n9659 );
xor ( n9661 , n9640 , n9660 );
buf ( n9662 , n5381 );
xor ( n9663 , n9662 , n7051 );
xor ( n9664 , n9663 , n6987 );
not ( n9665 , n9664 );
not ( n9666 , n6583 );
buf ( n9667 , n5382 );
and ( n9668 , n9666 , n9667 );
buf ( n9669 , n5383 );
xor ( n9670 , n9669 , n9667 );
and ( n9671 , n9670 , n6583 );
or ( n9672 , n9668 , n9671 );
xor ( n9673 , n9672 , n8412 );
xor ( n9674 , n9673 , n8428 );
and ( n9675 , n9665 , n9674 );
xor ( n9676 , n9661 , n9675 );
xor ( n9677 , n9619 , n9676 );
buf ( n9678 , n5384 );
not ( n9679 , n6583 );
buf ( n9680 , n5385 );
and ( n9681 , n9679 , n9680 );
buf ( n9682 , n5386 );
xor ( n9683 , n9682 , n9680 );
and ( n9684 , n9683 , n6583 );
or ( n9685 , n9681 , n9684 );
not ( n9686 , n6583 );
buf ( n9687 , n5387 );
and ( n9688 , n9686 , n9687 );
buf ( n9689 , n5388 );
xor ( n9690 , n9689 , n9687 );
and ( n9691 , n9690 , n6583 );
or ( n9692 , n9688 , n9691 );
xor ( n9693 , n9685 , n9692 );
buf ( n9694 , n5389 );
xor ( n9695 , n9693 , n9694 );
buf ( n9696 , n5390 );
xor ( n9697 , n9695 , n9696 );
buf ( n9698 , n5391 );
xor ( n9699 , n9697 , n9698 );
xor ( n9700 , n9678 , n9699 );
xor ( n9701 , n9700 , n9362 );
buf ( n9702 , n5392 );
not ( n9703 , n6583 );
buf ( n9704 , n5393 );
and ( n9705 , n9703 , n9704 );
buf ( n9706 , n5394 );
xor ( n9707 , n9706 , n9704 );
and ( n9708 , n9707 , n6583 );
or ( n9709 , n9705 , n9708 );
buf ( n9710 , n5395 );
xor ( n9711 , n9709 , n9710 );
xor ( n9712 , n9711 , n7865 );
buf ( n9713 , n5396 );
xor ( n9714 , n9712 , n9713 );
xor ( n9715 , n9714 , n8656 );
xor ( n9716 , n9702 , n9715 );
xor ( n9717 , n9716 , n8886 );
not ( n9718 , n9717 );
not ( n9719 , n6583 );
buf ( n9720 , n5397 );
and ( n9721 , n9719 , n9720 );
buf ( n9722 , n5398 );
xor ( n9723 , n9722 , n9720 );
and ( n9724 , n9723 , n6583 );
or ( n9725 , n9721 , n9724 );
not ( n9726 , n6583 );
buf ( n9727 , n5399 );
and ( n9728 , n9726 , n9727 );
buf ( n9729 , n5400 );
xor ( n9730 , n9729 , n9727 );
and ( n9731 , n9730 , n6583 );
or ( n9732 , n9728 , n9731 );
xor ( n9733 , n9725 , n9732 );
buf ( n9734 , n5401 );
xor ( n9735 , n9733 , n9734 );
buf ( n9736 , n5402 );
xor ( n9737 , n9735 , n9736 );
buf ( n9738 , n5403 );
xor ( n9739 , n9737 , n9738 );
xor ( n9740 , n8570 , n9739 );
not ( n9741 , n6583 );
buf ( n9742 , n5404 );
and ( n9743 , n9741 , n9742 );
buf ( n9744 , n5405 );
xor ( n9745 , n9744 , n9742 );
and ( n9746 , n9745 , n6583 );
or ( n9747 , n9743 , n9746 );
not ( n9748 , n6583 );
buf ( n9749 , n5406 );
and ( n9750 , n9748 , n9749 );
buf ( n9751 , n5407 );
xor ( n9752 , n9751 , n9749 );
and ( n9753 , n9752 , n6583 );
or ( n9754 , n9750 , n9753 );
xor ( n9755 , n9747 , n9754 );
buf ( n9756 , n5408 );
xor ( n9757 , n9755 , n9756 );
buf ( n9758 , n5409 );
xor ( n9759 , n9757 , n9758 );
buf ( n9760 , n5410 );
xor ( n9761 , n9759 , n9760 );
xor ( n9762 , n9740 , n9761 );
and ( n9763 , n9718 , n9762 );
xor ( n9764 , n9701 , n9763 );
xor ( n9765 , n9677 , n9764 );
xor ( n9766 , n8860 , n6681 );
not ( n9767 , n6583 );
buf ( n9768 , n5411 );
and ( n9769 , n9767 , n9768 );
buf ( n9770 , n5412 );
xor ( n9771 , n9770 , n9768 );
and ( n9772 , n9771 , n6583 );
or ( n9773 , n9769 , n9772 );
not ( n9774 , n6583 );
buf ( n9775 , n5413 );
and ( n9776 , n9774 , n9775 );
buf ( n9777 , n5414 );
xor ( n9778 , n9777 , n9775 );
and ( n9779 , n9778 , n6583 );
or ( n9780 , n9776 , n9779 );
xor ( n9781 , n9773 , n9780 );
buf ( n9782 , n5415 );
xor ( n9783 , n9781 , n9782 );
buf ( n9784 , n5416 );
xor ( n9785 , n9783 , n9784 );
buf ( n9786 , n5417 );
xor ( n9787 , n9785 , n9786 );
xor ( n9788 , n9766 , n9787 );
not ( n9789 , n6583 );
buf ( n9790 , n5418 );
and ( n9791 , n9789 , n9790 );
buf ( n9792 , n5419 );
xor ( n9793 , n9792 , n9790 );
and ( n9794 , n9793 , n6583 );
or ( n9795 , n9791 , n9794 );
not ( n9796 , n6583 );
buf ( n9797 , n5420 );
and ( n9798 , n9796 , n9797 );
buf ( n9799 , n5421 );
xor ( n9800 , n9799 , n9797 );
and ( n9801 , n9800 , n6583 );
or ( n9802 , n9798 , n9801 );
xor ( n9803 , n9795 , n9802 );
buf ( n9804 , n5422 );
xor ( n9805 , n9803 , n9804 );
buf ( n9806 , n5423 );
xor ( n9807 , n9805 , n9806 );
buf ( n9808 , n5424 );
xor ( n9809 , n9807 , n9808 );
xor ( n9810 , n6751 , n9809 );
not ( n9811 , n6583 );
buf ( n9812 , n5425 );
and ( n9813 , n9811 , n9812 );
buf ( n9814 , n5426 );
xor ( n9815 , n9814 , n9812 );
and ( n9816 , n9815 , n6583 );
or ( n9817 , n9813 , n9816 );
buf ( n9818 , n5427 );
xor ( n9819 , n9817 , n9818 );
buf ( n9820 , n5428 );
xor ( n9821 , n9819 , n9820 );
buf ( n9822 , n5429 );
xor ( n9823 , n9821 , n9822 );
buf ( n9824 , n5430 );
xor ( n9825 , n9823 , n9824 );
xor ( n9826 , n9810 , n9825 );
not ( n9827 , n9826 );
not ( n9828 , n6583 );
buf ( n9829 , n5431 );
and ( n9830 , n9828 , n9829 );
buf ( n9831 , n5432 );
xor ( n9832 , n9831 , n9829 );
and ( n9833 , n9832 , n6583 );
or ( n9834 , n9830 , n9833 );
not ( n9835 , n6583 );
buf ( n9836 , n5433 );
and ( n9837 , n9835 , n9836 );
buf ( n9838 , n5434 );
xor ( n9839 , n9838 , n9836 );
and ( n9840 , n9839 , n6583 );
or ( n9841 , n9837 , n9840 );
not ( n9842 , n6583 );
buf ( n9843 , n5435 );
and ( n9844 , n9842 , n9843 );
buf ( n9845 , n5436 );
xor ( n9846 , n9845 , n9843 );
and ( n9847 , n9846 , n6583 );
or ( n9848 , n9844 , n9847 );
xor ( n9849 , n9841 , n9848 );
buf ( n9850 , n5437 );
xor ( n9851 , n9849 , n9850 );
buf ( n9852 , n5438 );
xor ( n9853 , n9851 , n9852 );
buf ( n9854 , n5439 );
xor ( n9855 , n9853 , n9854 );
xor ( n9856 , n9834 , n9855 );
not ( n9857 , n6583 );
buf ( n9858 , n5440 );
and ( n9859 , n9857 , n9858 );
buf ( n9860 , n5441 );
xor ( n9861 , n9860 , n9858 );
and ( n9862 , n9861 , n6583 );
or ( n9863 , n9859 , n9862 );
not ( n9864 , n6583 );
buf ( n9865 , n5442 );
and ( n9866 , n9864 , n9865 );
buf ( n9867 , n5443 );
xor ( n9868 , n9867 , n9865 );
and ( n9869 , n9868 , n6583 );
or ( n9870 , n9866 , n9869 );
xor ( n9871 , n9863 , n9870 );
buf ( n9872 , n5444 );
xor ( n9873 , n9871 , n9872 );
buf ( n9874 , n5445 );
xor ( n9875 , n9873 , n9874 );
buf ( n9876 , n5446 );
xor ( n9877 , n9875 , n9876 );
xor ( n9878 , n9856 , n9877 );
and ( n9879 , n9827 , n9878 );
xor ( n9880 , n9788 , n9879 );
xor ( n9881 , n9765 , n9880 );
buf ( n9882 , n5447 );
not ( n9883 , n6583 );
buf ( n9884 , n5448 );
and ( n9885 , n9883 , n9884 );
buf ( n9886 , n5449 );
xor ( n9887 , n9886 , n9884 );
and ( n9888 , n9887 , n6583 );
or ( n9889 , n9885 , n9888 );
buf ( n9890 , n5450 );
xor ( n9891 , n9889 , n9890 );
buf ( n9892 , n5451 );
xor ( n9893 , n9891 , n9892 );
buf ( n9894 , n5452 );
xor ( n9895 , n9893 , n9894 );
buf ( n9896 , n5453 );
xor ( n9897 , n9895 , n9896 );
xor ( n9898 , n9882 , n9897 );
xor ( n9899 , n9898 , n9046 );
buf ( n9900 , n5454 );
not ( n9901 , n6583 );
buf ( n9902 , n5455 );
and ( n9903 , n9901 , n9902 );
buf ( n9904 , n5456 );
xor ( n9905 , n9904 , n9902 );
and ( n9906 , n9905 , n6583 );
or ( n9907 , n9903 , n9906 );
not ( n9908 , n6583 );
buf ( n9909 , n5457 );
and ( n9910 , n9908 , n9909 );
buf ( n9911 , n5458 );
xor ( n9912 , n9911 , n9909 );
and ( n9913 , n9912 , n6583 );
or ( n9914 , n9910 , n9913 );
xor ( n9915 , n9907 , n9914 );
xor ( n9916 , n9915 , n9163 );
buf ( n9917 , n5459 );
xor ( n9918 , n9916 , n9917 );
buf ( n9919 , n5460 );
xor ( n9920 , n9918 , n9919 );
xor ( n9921 , n9900 , n9920 );
not ( n9922 , n6583 );
buf ( n9923 , n5461 );
and ( n9924 , n9922 , n9923 );
buf ( n9925 , n5462 );
xor ( n9926 , n9925 , n9923 );
and ( n9927 , n9926 , n6583 );
or ( n9928 , n9924 , n9927 );
not ( n9929 , n6583 );
buf ( n9930 , n5463 );
and ( n9931 , n9929 , n9930 );
buf ( n9932 , n5464 );
xor ( n9933 , n9932 , n9930 );
and ( n9934 , n9933 , n6583 );
or ( n9935 , n9931 , n9934 );
xor ( n9936 , n9928 , n9935 );
buf ( n9937 , n5465 );
xor ( n9938 , n9936 , n9937 );
buf ( n9939 , n5466 );
xor ( n9940 , n9938 , n9939 );
buf ( n9941 , n5467 );
xor ( n9942 , n9940 , n9941 );
xor ( n9943 , n9921 , n9942 );
not ( n9944 , n9943 );
not ( n9945 , n6583 );
buf ( n9946 , n5468 );
and ( n9947 , n9945 , n9946 );
buf ( n9948 , n5469 );
xor ( n9949 , n9948 , n9946 );
and ( n9950 , n9949 , n6583 );
or ( n9951 , n9947 , n9950 );
not ( n9952 , n6583 );
buf ( n9953 , n5470 );
and ( n9954 , n9952 , n9953 );
buf ( n9955 , n5471 );
xor ( n9956 , n9955 , n9953 );
and ( n9957 , n9956 , n6583 );
or ( n9958 , n9954 , n9957 );
not ( n9959 , n6583 );
buf ( n9960 , n5472 );
and ( n9961 , n9959 , n9960 );
buf ( n9962 , n5473 );
xor ( n9963 , n9962 , n9960 );
and ( n9964 , n9963 , n6583 );
or ( n9965 , n9961 , n9964 );
xor ( n9966 , n9958 , n9965 );
buf ( n9967 , n5474 );
xor ( n9968 , n9966 , n9967 );
buf ( n9969 , n5475 );
xor ( n9970 , n9968 , n9969 );
buf ( n9971 , n5476 );
xor ( n9972 , n9970 , n9971 );
xor ( n9973 , n9951 , n9972 );
xor ( n9974 , n9973 , n7494 );
and ( n9975 , n9944 , n9974 );
xor ( n9976 , n9899 , n9975 );
xor ( n9977 , n9881 , n9976 );
xor ( n9978 , n9538 , n9977 );
and ( n9979 , n9024 , n9978 );
xor ( n9980 , n7953 , n9979 );
and ( n9981 , n9980 , n6584 );
or ( n9982 , n6587 , n9981 );
and ( n9983 , n6579 , n9982 );
buf ( n9984 , n9983 );
buf ( n9985 , n9984 );
buf ( n9986 , n6577 );
not ( n9987 , n9986 );
not ( n9988 , n6584 );
and ( n9989 , n9988 , n7467 );
not ( n9990 , n9978 );
buf ( n9991 , n5477 );
not ( n9992 , n6583 );
buf ( n9993 , n5478 );
and ( n9994 , n9992 , n9993 );
buf ( n9995 , n5479 );
xor ( n9996 , n9995 , n9993 );
and ( n9997 , n9996 , n6583 );
or ( n9998 , n9994 , n9997 );
not ( n9999 , n6583 );
buf ( n10000 , n5480 );
and ( n10001 , n9999 , n10000 );
buf ( n10002 , n5481 );
xor ( n10003 , n10002 , n10000 );
and ( n10004 , n10003 , n6583 );
or ( n10005 , n10001 , n10004 );
xor ( n10006 , n9998 , n10005 );
buf ( n10007 , n5482 );
xor ( n10008 , n10006 , n10007 );
buf ( n10009 , n5483 );
xor ( n10010 , n10008 , n10009 );
buf ( n10011 , n5484 );
xor ( n10012 , n10010 , n10011 );
xor ( n10013 , n9991 , n10012 );
not ( n10014 , n6583 );
buf ( n10015 , n5485 );
and ( n10016 , n10014 , n10015 );
buf ( n10017 , n5486 );
xor ( n10018 , n10017 , n10015 );
and ( n10019 , n10018 , n6583 );
or ( n10020 , n10016 , n10019 );
not ( n10021 , n6583 );
buf ( n10022 , n5487 );
and ( n10023 , n10021 , n10022 );
buf ( n10024 , n5488 );
xor ( n10025 , n10024 , n10022 );
and ( n10026 , n10025 , n6583 );
or ( n10027 , n10023 , n10026 );
xor ( n10028 , n10020 , n10027 );
buf ( n10029 , n5489 );
xor ( n10030 , n10028 , n10029 );
buf ( n10031 , n5490 );
xor ( n10032 , n10030 , n10031 );
buf ( n10033 , n5491 );
xor ( n10034 , n10032 , n10033 );
xor ( n10035 , n10013 , n10034 );
not ( n10036 , n6583 );
buf ( n10037 , n5492 );
and ( n10038 , n10036 , n10037 );
buf ( n10039 , n5493 );
xor ( n10040 , n10039 , n10037 );
and ( n10041 , n10040 , n6583 );
or ( n10042 , n10038 , n10041 );
not ( n10043 , n6583 );
buf ( n10044 , n5494 );
and ( n10045 , n10043 , n10044 );
buf ( n10046 , n5495 );
xor ( n10047 , n10046 , n10044 );
and ( n10048 , n10047 , n6583 );
or ( n10049 , n10045 , n10048 );
xor ( n10050 , n10042 , n10049 );
xor ( n10051 , n10050 , n7761 );
buf ( n10052 , n5496 );
xor ( n10053 , n10051 , n10052 );
buf ( n10054 , n5497 );
xor ( n10055 , n10053 , n10054 );
xor ( n10056 , n6726 , n10055 );
not ( n10057 , n6583 );
buf ( n10058 , n5498 );
and ( n10059 , n10057 , n10058 );
buf ( n10060 , n5499 );
xor ( n10061 , n10060 , n10058 );
and ( n10062 , n10061 , n6583 );
or ( n10063 , n10059 , n10062 );
xor ( n10064 , n10063 , n9439 );
buf ( n10065 , n5500 );
xor ( n10066 , n10064 , n10065 );
buf ( n10067 , n5501 );
xor ( n10068 , n10066 , n10067 );
buf ( n10069 , n5502 );
xor ( n10070 , n10068 , n10069 );
xor ( n10071 , n10056 , n10070 );
not ( n10072 , n10071 );
xor ( n10073 , n8894 , n9069 );
xor ( n10074 , n10073 , n9085 );
and ( n10075 , n10072 , n10074 );
xor ( n10076 , n10035 , n10075 );
buf ( n10077 , n5503 );
not ( n10078 , n6583 );
buf ( n10079 , n5504 );
and ( n10080 , n10078 , n10079 );
buf ( n10081 , n5505 );
xor ( n10082 , n10081 , n10079 );
and ( n10083 , n10082 , n6583 );
or ( n10084 , n10080 , n10083 );
not ( n10085 , n6583 );
buf ( n10086 , n5506 );
and ( n10087 , n10085 , n10086 );
buf ( n10088 , n5507 );
xor ( n10089 , n10088 , n10086 );
and ( n10090 , n10089 , n6583 );
or ( n10091 , n10087 , n10090 );
xor ( n10092 , n10084 , n10091 );
buf ( n10093 , n5508 );
xor ( n10094 , n10092 , n10093 );
buf ( n10095 , n5509 );
xor ( n10096 , n10094 , n10095 );
buf ( n10097 , n5510 );
xor ( n10098 , n10096 , n10097 );
xor ( n10099 , n10077 , n10098 );
not ( n10100 , n6583 );
buf ( n10101 , n5511 );
and ( n10102 , n10100 , n10101 );
buf ( n10103 , n5512 );
xor ( n10104 , n10103 , n10101 );
and ( n10105 , n10104 , n6583 );
or ( n10106 , n10102 , n10105 );
not ( n10107 , n6583 );
buf ( n10108 , n5513 );
and ( n10109 , n10107 , n10108 );
buf ( n10110 , n5514 );
xor ( n10111 , n10110 , n10108 );
and ( n10112 , n10111 , n6583 );
or ( n10113 , n10109 , n10112 );
xor ( n10114 , n10106 , n10113 );
buf ( n10115 , n5515 );
xor ( n10116 , n10114 , n10115 );
buf ( n10117 , n5516 );
xor ( n10118 , n10116 , n10117 );
buf ( n10119 , n5517 );
xor ( n10120 , n10118 , n10119 );
xor ( n10121 , n10099 , n10120 );
not ( n10122 , n6583 );
buf ( n10123 , n5518 );
and ( n10124 , n10122 , n10123 );
buf ( n10125 , n5519 );
xor ( n10126 , n10125 , n10123 );
and ( n10127 , n10126 , n6583 );
or ( n10128 , n10124 , n10127 );
not ( n10129 , n6583 );
buf ( n10130 , n5520 );
and ( n10131 , n10129 , n10130 );
buf ( n10132 , n5521 );
xor ( n10133 , n10132 , n10130 );
and ( n10134 , n10133 , n6583 );
or ( n10135 , n10131 , n10134 );
xor ( n10136 , n10128 , n10135 );
buf ( n10137 , n5522 );
xor ( n10138 , n10136 , n10137 );
buf ( n10139 , n5523 );
xor ( n10140 , n10138 , n10139 );
buf ( n10141 , n5524 );
xor ( n10142 , n10140 , n10141 );
xor ( n10143 , n9106 , n10142 );
xor ( n10144 , n10143 , n6659 );
not ( n10145 , n10144 );
xor ( n10146 , n8269 , n9244 );
not ( n10147 , n6583 );
buf ( n10148 , n5525 );
and ( n10149 , n10147 , n10148 );
buf ( n10150 , n5526 );
xor ( n10151 , n10150 , n10148 );
and ( n10152 , n10151 , n6583 );
or ( n10153 , n10149 , n10152 );
not ( n10154 , n6583 );
buf ( n10155 , n5527 );
and ( n10156 , n10154 , n10155 );
buf ( n10157 , n5528 );
xor ( n10158 , n10157 , n10155 );
and ( n10159 , n10158 , n6583 );
or ( n10160 , n10156 , n10159 );
xor ( n10161 , n10153 , n10160 );
xor ( n10162 , n10161 , n8661 );
buf ( n10163 , n5529 );
xor ( n10164 , n10162 , n10163 );
buf ( n10165 , n5530 );
xor ( n10166 , n10164 , n10165 );
xor ( n10167 , n10146 , n10166 );
and ( n10168 , n10145 , n10167 );
xor ( n10169 , n10121 , n10168 );
buf ( n10170 , n5531 );
xor ( n10171 , n10170 , n7996 );
not ( n10172 , n6583 );
buf ( n10173 , n5532 );
and ( n10174 , n10172 , n10173 );
buf ( n10175 , n5533 );
xor ( n10176 , n10175 , n10173 );
and ( n10177 , n10176 , n6583 );
or ( n10178 , n10174 , n10177 );
not ( n10179 , n6583 );
buf ( n10180 , n5534 );
and ( n10181 , n10179 , n10180 );
buf ( n10182 , n5535 );
xor ( n10183 , n10182 , n10180 );
and ( n10184 , n10183 , n6583 );
or ( n10185 , n10181 , n10184 );
xor ( n10186 , n10178 , n10185 );
buf ( n10187 , n5536 );
xor ( n10188 , n10186 , n10187 );
buf ( n10189 , n5537 );
xor ( n10190 , n10188 , n10189 );
buf ( n10191 , n5538 );
xor ( n10192 , n10190 , n10191 );
xor ( n10193 , n10171 , n10192 );
not ( n10194 , n10035 );
and ( n10195 , n10194 , n10071 );
xor ( n10196 , n10193 , n10195 );
xor ( n10197 , n10169 , n10196 );
buf ( n10198 , n5539 );
not ( n10199 , n6583 );
buf ( n10200 , n5540 );
and ( n10201 , n10199 , n10200 );
buf ( n10202 , n5541 );
xor ( n10203 , n10202 , n10200 );
and ( n10204 , n10203 , n6583 );
or ( n10205 , n10201 , n10204 );
not ( n10206 , n6583 );
buf ( n10207 , n5542 );
and ( n10208 , n10206 , n10207 );
buf ( n10209 , n5543 );
xor ( n10210 , n10209 , n10207 );
and ( n10211 , n10210 , n6583 );
or ( n10212 , n10208 , n10211 );
xor ( n10213 , n10205 , n10212 );
buf ( n10214 , n5544 );
xor ( n10215 , n10213 , n10214 );
buf ( n10216 , n5545 );
xor ( n10217 , n10215 , n10216 );
buf ( n10218 , n5546 );
xor ( n10219 , n10217 , n10218 );
xor ( n10220 , n10198 , n10219 );
xor ( n10221 , n10220 , n9715 );
not ( n10222 , n6583 );
buf ( n10223 , n5547 );
and ( n10224 , n10222 , n10223 );
buf ( n10225 , n5548 );
xor ( n10226 , n10225 , n10223 );
and ( n10227 , n10226 , n6583 );
or ( n10228 , n10224 , n10227 );
not ( n10229 , n6583 );
buf ( n10230 , n5549 );
and ( n10231 , n10229 , n10230 );
buf ( n10232 , n5550 );
xor ( n10233 , n10232 , n10230 );
and ( n10234 , n10233 , n6583 );
or ( n10235 , n10231 , n10234 );
xor ( n10236 , n10228 , n10235 );
buf ( n10237 , n5551 );
xor ( n10238 , n10236 , n10237 );
xor ( n10239 , n10238 , n7431 );
buf ( n10240 , n5552 );
xor ( n10241 , n10239 , n10240 );
xor ( n10242 , n9612 , n10241 );
xor ( n10243 , n10242 , n9739 );
not ( n10244 , n10243 );
buf ( n10245 , n5553 );
not ( n10246 , n6583 );
buf ( n10247 , n5554 );
and ( n10248 , n10246 , n10247 );
buf ( n10249 , n5555 );
xor ( n10250 , n10249 , n10247 );
and ( n10251 , n10250 , n6583 );
or ( n10252 , n10248 , n10251 );
buf ( n10253 , n5556 );
xor ( n10254 , n10252 , n10253 );
buf ( n10255 , n5557 );
xor ( n10256 , n10254 , n10255 );
buf ( n10257 , n5558 );
xor ( n10258 , n10256 , n10257 );
buf ( n10259 , n5559 );
xor ( n10260 , n10258 , n10259 );
xor ( n10261 , n10245 , n10260 );
not ( n10262 , n6583 );
buf ( n10263 , n5560 );
and ( n10264 , n10262 , n10263 );
buf ( n10265 , n5561 );
xor ( n10266 , n10265 , n10263 );
and ( n10267 , n10266 , n6583 );
or ( n10268 , n10264 , n10267 );
not ( n10269 , n6583 );
buf ( n10270 , n5562 );
and ( n10271 , n10269 , n10270 );
buf ( n10272 , n5563 );
xor ( n10273 , n10272 , n10270 );
and ( n10274 , n10273 , n6583 );
or ( n10275 , n10271 , n10274 );
xor ( n10276 , n10268 , n10275 );
buf ( n10277 , n5564 );
xor ( n10278 , n10276 , n10277 );
buf ( n10279 , n5565 );
xor ( n10280 , n10278 , n10279 );
buf ( n10281 , n5566 );
xor ( n10282 , n10280 , n10281 );
xor ( n10283 , n10261 , n10282 );
and ( n10284 , n10244 , n10283 );
xor ( n10285 , n10221 , n10284 );
xor ( n10286 , n10197 , n10285 );
buf ( n10287 , n5567 );
xor ( n10288 , n10287 , n9920 );
xor ( n10289 , n10288 , n9942 );
xor ( n10290 , n9015 , n8292 );
xor ( n10291 , n10290 , n9699 );
not ( n10292 , n10291 );
xor ( n10293 , n8634 , n8142 );
not ( n10294 , n6583 );
buf ( n10295 , n5568 );
and ( n10296 , n10294 , n10295 );
buf ( n10297 , n5569 );
xor ( n10298 , n10297 , n10295 );
and ( n10299 , n10298 , n6583 );
or ( n10300 , n10296 , n10299 );
buf ( n10301 , n5570 );
xor ( n10302 , n10300 , n10301 );
buf ( n10303 , n5571 );
xor ( n10304 , n10302 , n10303 );
buf ( n10305 , n5572 );
xor ( n10306 , n10304 , n10305 );
buf ( n10307 , n5573 );
xor ( n10308 , n10306 , n10307 );
xor ( n10309 , n10293 , n10308 );
and ( n10310 , n10292 , n10309 );
xor ( n10311 , n10289 , n10310 );
xor ( n10312 , n10286 , n10311 );
buf ( n10313 , n5574 );
not ( n10314 , n6583 );
buf ( n10315 , n5575 );
and ( n10316 , n10314 , n10315 );
buf ( n10317 , n5576 );
xor ( n10318 , n10317 , n10315 );
and ( n10319 , n10318 , n6583 );
or ( n10320 , n10316 , n10319 );
xor ( n10321 , n8213 , n10320 );
buf ( n10322 , n5577 );
xor ( n10323 , n10321 , n10322 );
buf ( n10324 , n5578 );
xor ( n10325 , n10323 , n10324 );
buf ( n10326 , n5579 );
xor ( n10327 , n10325 , n10326 );
xor ( n10328 , n10313 , n10327 );
not ( n10329 , n6583 );
buf ( n10330 , n5580 );
and ( n10331 , n10329 , n10330 );
buf ( n10332 , n5581 );
xor ( n10333 , n10332 , n10330 );
and ( n10334 , n10333 , n6583 );
or ( n10335 , n10331 , n10334 );
not ( n10336 , n6583 );
buf ( n10337 , n5582 );
and ( n10338 , n10336 , n10337 );
buf ( n10339 , n5583 );
xor ( n10340 , n10339 , n10337 );
and ( n10341 , n10340 , n6583 );
or ( n10342 , n10338 , n10341 );
xor ( n10343 , n10335 , n10342 );
buf ( n10344 , n5584 );
xor ( n10345 , n10343 , n10344 );
buf ( n10346 , n5585 );
xor ( n10347 , n10345 , n10346 );
buf ( n10348 , n5586 );
xor ( n10349 , n10347 , n10348 );
xor ( n10350 , n10328 , n10349 );
buf ( n10351 , n5587 );
not ( n10352 , n6583 );
buf ( n10353 , n5588 );
and ( n10354 , n10352 , n10353 );
buf ( n10355 , n5589 );
xor ( n10356 , n10355 , n10353 );
and ( n10357 , n10356 , n6583 );
or ( n10358 , n10354 , n10357 );
buf ( n10359 , n5590 );
xor ( n10360 , n10358 , n10359 );
buf ( n10361 , n5591 );
xor ( n10362 , n10360 , n10361 );
buf ( n10363 , n5592 );
xor ( n10364 , n10362 , n10363 );
buf ( n10365 , n5593 );
xor ( n10366 , n10364 , n10365 );
xor ( n10367 , n10351 , n10366 );
not ( n10368 , n6583 );
buf ( n10369 , n5594 );
and ( n10370 , n10368 , n10369 );
buf ( n10371 , n5595 );
xor ( n10372 , n10371 , n10369 );
and ( n10373 , n10372 , n6583 );
or ( n10374 , n10370 , n10373 );
not ( n10375 , n6583 );
buf ( n10376 , n5596 );
and ( n10377 , n10375 , n10376 );
buf ( n10378 , n5597 );
xor ( n10379 , n10378 , n10376 );
and ( n10380 , n10379 , n6583 );
or ( n10381 , n10377 , n10380 );
xor ( n10382 , n10374 , n10381 );
buf ( n10383 , n5598 );
xor ( n10384 , n10382 , n10383 );
buf ( n10385 , n5599 );
xor ( n10386 , n10384 , n10385 );
buf ( n10387 , n5600 );
xor ( n10388 , n10386 , n10387 );
xor ( n10389 , n10367 , n10388 );
not ( n10390 , n10389 );
not ( n10391 , n6583 );
buf ( n10392 , n5601 );
and ( n10393 , n10391 , n10392 );
buf ( n10394 , n5602 );
xor ( n10395 , n10394 , n10392 );
and ( n10396 , n10395 , n6583 );
or ( n10397 , n10393 , n10396 );
not ( n10398 , n6583 );
buf ( n10399 , n5603 );
and ( n10400 , n10398 , n10399 );
buf ( n10401 , n5604 );
xor ( n10402 , n10401 , n10399 );
and ( n10403 , n10402 , n6583 );
or ( n10404 , n10400 , n10403 );
xor ( n10405 , n10397 , n10404 );
buf ( n10406 , n5605 );
xor ( n10407 , n10405 , n10406 );
buf ( n10408 , n5606 );
xor ( n10409 , n10407 , n10408 );
buf ( n10410 , n5607 );
xor ( n10411 , n10409 , n10410 );
xor ( n10412 , n7827 , n10411 );
not ( n10413 , n6583 );
buf ( n10414 , n5608 );
and ( n10415 , n10413 , n10414 );
buf ( n10416 , n5609 );
xor ( n10417 , n10416 , n10414 );
and ( n10418 , n10417 , n6583 );
or ( n10419 , n10415 , n10418 );
not ( n10420 , n6583 );
buf ( n10421 , n5610 );
and ( n10422 , n10420 , n10421 );
buf ( n10423 , n5611 );
xor ( n10424 , n10423 , n10421 );
and ( n10425 , n10424 , n6583 );
or ( n10426 , n10422 , n10425 );
xor ( n10427 , n10419 , n10426 );
buf ( n10428 , n5612 );
xor ( n10429 , n10427 , n10428 );
buf ( n10430 , n5613 );
xor ( n10431 , n10429 , n10430 );
buf ( n10432 , n5614 );
xor ( n10433 , n10431 , n10432 );
xor ( n10434 , n10412 , n10433 );
and ( n10435 , n10390 , n10434 );
xor ( n10436 , n10350 , n10435 );
xor ( n10437 , n10312 , n10436 );
xor ( n10438 , n10076 , n10437 );
xor ( n10439 , n6962 , n9285 );
xor ( n10440 , n10439 , n9307 );
xor ( n10441 , n6760 , n9825 );
xor ( n10442 , n10441 , n7828 );
not ( n10443 , n10442 );
not ( n10444 , n6583 );
buf ( n10445 , n5615 );
and ( n10446 , n10444 , n10445 );
buf ( n10447 , n5616 );
xor ( n10448 , n10447 , n10445 );
and ( n10449 , n10448 , n6583 );
or ( n10450 , n10446 , n10449 );
xor ( n10451 , n10450 , n10012 );
xor ( n10452 , n10451 , n10034 );
and ( n10453 , n10443 , n10452 );
xor ( n10454 , n10440 , n10453 );
not ( n10455 , n6583 );
buf ( n10456 , n5617 );
and ( n10457 , n10455 , n10456 );
buf ( n10458 , n5618 );
xor ( n10459 , n10458 , n10456 );
and ( n10460 , n10459 , n6583 );
or ( n10461 , n10457 , n10460 );
not ( n10462 , n6583 );
buf ( n10463 , n5619 );
and ( n10464 , n10462 , n10463 );
buf ( n10465 , n5620 );
xor ( n10466 , n10465 , n10463 );
and ( n10467 , n10466 , n6583 );
or ( n10468 , n10464 , n10467 );
xor ( n10469 , n10461 , n10468 );
buf ( n10470 , n5621 );
xor ( n10471 , n10469 , n10470 );
buf ( n10472 , n5622 );
xor ( n10473 , n10471 , n10472 );
buf ( n10474 , n5623 );
xor ( n10475 , n10473 , n10474 );
xor ( n10476 , n7803 , n10475 );
not ( n10477 , n6583 );
buf ( n10478 , n5624 );
and ( n10479 , n10477 , n10478 );
buf ( n10480 , n5625 );
xor ( n10481 , n10480 , n10478 );
and ( n10482 , n10481 , n6583 );
or ( n10483 , n10479 , n10482 );
not ( n10484 , n6583 );
buf ( n10485 , n5626 );
and ( n10486 , n10484 , n10485 );
buf ( n10487 , n5627 );
xor ( n10488 , n10487 , n10485 );
and ( n10489 , n10488 , n6583 );
or ( n10490 , n10486 , n10489 );
xor ( n10491 , n10483 , n10490 );
buf ( n10492 , n5628 );
xor ( n10493 , n10491 , n10492 );
buf ( n10494 , n5629 );
xor ( n10495 , n10493 , n10494 );
buf ( n10496 , n5630 );
xor ( n10497 , n10495 , n10496 );
xor ( n10498 , n10476 , n10497 );
not ( n10499 , n6583 );
buf ( n10500 , n5631 );
and ( n10501 , n10499 , n10500 );
buf ( n10502 , n5632 );
xor ( n10503 , n10502 , n10500 );
and ( n10504 , n10503 , n6583 );
or ( n10505 , n10501 , n10504 );
xor ( n10506 , n10505 , n9560 );
xor ( n10507 , n10506 , n8807 );
not ( n10508 , n10507 );
buf ( n10509 , n5633 );
xor ( n10510 , n10509 , n9109 );
xor ( n10511 , n10510 , n8841 );
and ( n10512 , n10508 , n10511 );
xor ( n10513 , n10498 , n10512 );
xor ( n10514 , n10454 , n10513 );
buf ( n10515 , n5634 );
not ( n10516 , n6583 );
buf ( n10517 , n5635 );
and ( n10518 , n10516 , n10517 );
buf ( n10519 , n5636 );
xor ( n10520 , n10519 , n10517 );
and ( n10521 , n10520 , n6583 );
or ( n10522 , n10518 , n10521 );
buf ( n10523 , n5637 );
xor ( n10524 , n10522 , n10523 );
buf ( n10525 , n5638 );
xor ( n10526 , n10524 , n10525 );
buf ( n10527 , n5639 );
xor ( n10528 , n10526 , n10527 );
buf ( n10529 , n5640 );
xor ( n10530 , n10528 , n10529 );
xor ( n10531 , n10515 , n10530 );
not ( n10532 , n6583 );
buf ( n10533 , n5641 );
and ( n10534 , n10532 , n10533 );
buf ( n10535 , n5642 );
xor ( n10536 , n10535 , n10533 );
and ( n10537 , n10536 , n6583 );
or ( n10538 , n10534 , n10537 );
not ( n10539 , n6583 );
buf ( n10540 , n5643 );
and ( n10541 , n10539 , n10540 );
buf ( n10542 , n5644 );
xor ( n10543 , n10542 , n10540 );
and ( n10544 , n10543 , n6583 );
or ( n10545 , n10541 , n10544 );
xor ( n10546 , n10538 , n10545 );
buf ( n10547 , n5645 );
xor ( n10548 , n10546 , n10547 );
buf ( n10549 , n5646 );
xor ( n10550 , n10548 , n10549 );
buf ( n10551 , n5647 );
xor ( n10552 , n10550 , n10551 );
xor ( n10553 , n10531 , n10552 );
xor ( n10554 , n7814 , n10411 );
xor ( n10555 , n10554 , n10433 );
not ( n10556 , n10555 );
not ( n10557 , n6583 );
buf ( n10558 , n5648 );
and ( n10559 , n10557 , n10558 );
buf ( n10560 , n5649 );
xor ( n10561 , n10560 , n10558 );
and ( n10562 , n10561 , n6583 );
or ( n10563 , n10559 , n10562 );
not ( n10564 , n6583 );
buf ( n10565 , n5650 );
and ( n10566 , n10564 , n10565 );
buf ( n10567 , n5651 );
xor ( n10568 , n10567 , n10565 );
and ( n10569 , n10568 , n6583 );
or ( n10570 , n10566 , n10569 );
not ( n10571 , n6583 );
buf ( n10572 , n5652 );
and ( n10573 , n10571 , n10572 );
buf ( n10574 , n5653 );
xor ( n10575 , n10574 , n10572 );
and ( n10576 , n10575 , n6583 );
or ( n10577 , n10573 , n10576 );
xor ( n10578 , n10570 , n10577 );
buf ( n10579 , n5654 );
xor ( n10580 , n10578 , n10579 );
buf ( n10581 , n5655 );
xor ( n10582 , n10580 , n10581 );
buf ( n10583 , n5656 );
xor ( n10584 , n10582 , n10583 );
xor ( n10585 , n10563 , n10584 );
xor ( n10586 , n10585 , n10241 );
and ( n10587 , n10556 , n10586 );
xor ( n10588 , n10553 , n10587 );
xor ( n10589 , n10514 , n10588 );
not ( n10590 , n6583 );
buf ( n10591 , n5657 );
and ( n10592 , n10590 , n10591 );
buf ( n10593 , n5658 );
xor ( n10594 , n10593 , n10591 );
and ( n10595 , n10594 , n6583 );
or ( n10596 , n10592 , n10595 );
xor ( n10597 , n10596 , n7611 );
buf ( n10598 , n5659 );
xor ( n10599 , n10597 , n10598 );
buf ( n10600 , n5660 );
xor ( n10601 , n10599 , n10600 );
buf ( n10602 , n5661 );
xor ( n10603 , n10601 , n10602 );
xor ( n10604 , n7146 , n10603 );
not ( n10605 , n6583 );
buf ( n10606 , n5662 );
and ( n10607 , n10605 , n10606 );
buf ( n10608 , n5663 );
xor ( n10609 , n10608 , n10606 );
and ( n10610 , n10609 , n6583 );
or ( n10611 , n10607 , n10610 );
buf ( n10612 , n5664 );
xor ( n10613 , n10611 , n10612 );
buf ( n10614 , n5665 );
xor ( n10615 , n10613 , n10614 );
buf ( n10616 , n5666 );
xor ( n10617 , n10615 , n10616 );
buf ( n10618 , n5667 );
xor ( n10619 , n10617 , n10618 );
xor ( n10620 , n10604 , n10619 );
xor ( n10621 , n7918 , n8908 );
not ( n10622 , n6583 );
buf ( n10623 , n5668 );
and ( n10624 , n10622 , n10623 );
buf ( n10625 , n5669 );
xor ( n10626 , n10625 , n10623 );
and ( n10627 , n10626 , n6583 );
or ( n10628 , n10624 , n10627 );
not ( n10629 , n6583 );
buf ( n10630 , n5670 );
and ( n10631 , n10629 , n10630 );
buf ( n10632 , n5671 );
xor ( n10633 , n10632 , n10630 );
and ( n10634 , n10633 , n6583 );
or ( n10635 , n10631 , n10634 );
xor ( n10636 , n10628 , n10635 );
buf ( n10637 , n5672 );
xor ( n10638 , n10636 , n10637 );
buf ( n10639 , n5673 );
xor ( n10640 , n10638 , n10639 );
buf ( n10641 , n5674 );
xor ( n10642 , n10640 , n10641 );
xor ( n10643 , n10621 , n10642 );
not ( n10644 , n10643 );
not ( n10645 , n6583 );
buf ( n10646 , n5675 );
and ( n10647 , n10645 , n10646 );
buf ( n10648 , n5676 );
xor ( n10649 , n10648 , n10646 );
and ( n10650 , n10649 , n6583 );
or ( n10651 , n10647 , n10650 );
xor ( n10652 , n10651 , n8428 );
not ( n10653 , n6583 );
buf ( n10654 , n5677 );
and ( n10655 , n10653 , n10654 );
buf ( n10656 , n5678 );
xor ( n10657 , n10656 , n10654 );
and ( n10658 , n10657 , n6583 );
or ( n10659 , n10655 , n10658 );
not ( n10660 , n6583 );
buf ( n10661 , n5679 );
and ( n10662 , n10660 , n10661 );
buf ( n10663 , n5680 );
xor ( n10664 , n10663 , n10661 );
and ( n10665 , n10664 , n6583 );
or ( n10666 , n10662 , n10665 );
xor ( n10667 , n10659 , n10666 );
buf ( n10668 , n5681 );
xor ( n10669 , n10667 , n10668 );
buf ( n10670 , n5682 );
xor ( n10671 , n10669 , n10670 );
buf ( n10672 , n5683 );
xor ( n10673 , n10671 , n10672 );
xor ( n10674 , n10652 , n10673 );
and ( n10675 , n10644 , n10674 );
xor ( n10676 , n10620 , n10675 );
xor ( n10677 , n10589 , n10676 );
buf ( n10678 , n5684 );
not ( n10679 , n6583 );
buf ( n10680 , n5685 );
and ( n10681 , n10679 , n10680 );
buf ( n10682 , n5686 );
xor ( n10683 , n10682 , n10680 );
and ( n10684 , n10683 , n6583 );
or ( n10685 , n10681 , n10684 );
not ( n10686 , n6583 );
buf ( n10687 , n5687 );
and ( n10688 , n10686 , n10687 );
buf ( n10689 , n5688 );
xor ( n10690 , n10689 , n10687 );
and ( n10691 , n10690 , n6583 );
or ( n10692 , n10688 , n10691 );
xor ( n10693 , n10685 , n10692 );
xor ( n10694 , n10693 , n10170 );
buf ( n10695 , n5689 );
xor ( n10696 , n10694 , n10695 );
buf ( n10697 , n5690 );
xor ( n10698 , n10696 , n10697 );
xor ( n10699 , n10678 , n10698 );
xor ( n10700 , n10699 , n8932 );
not ( n10701 , n6583 );
buf ( n10702 , n5691 );
and ( n10703 , n10701 , n10702 );
buf ( n10704 , n5692 );
xor ( n10705 , n10704 , n10702 );
and ( n10706 , n10705 , n6583 );
or ( n10707 , n10703 , n10706 );
not ( n10708 , n6583 );
buf ( n10709 , n5693 );
and ( n10710 , n10708 , n10709 );
buf ( n10711 , n5694 );
xor ( n10712 , n10711 , n10709 );
and ( n10713 , n10712 , n6583 );
or ( n10714 , n10710 , n10713 );
not ( n10715 , n6583 );
buf ( n10716 , n5695 );
and ( n10717 , n10715 , n10716 );
buf ( n10718 , n5696 );
xor ( n10719 , n10718 , n10716 );
and ( n10720 , n10719 , n6583 );
or ( n10721 , n10717 , n10720 );
xor ( n10722 , n10714 , n10721 );
buf ( n10723 , n5697 );
xor ( n10724 , n10722 , n10723 );
buf ( n10725 , n5698 );
xor ( n10726 , n10724 , n10725 );
buf ( n10727 , n5699 );
xor ( n10728 , n10726 , n10727 );
xor ( n10729 , n10707 , n10728 );
xor ( n10730 , n10729 , n6752 );
not ( n10731 , n10730 );
xor ( n10732 , n8628 , n8142 );
xor ( n10733 , n10732 , n10308 );
and ( n10734 , n10731 , n10733 );
xor ( n10735 , n10700 , n10734 );
xor ( n10736 , n10677 , n10735 );
xor ( n10737 , n10438 , n10736 );
and ( n10738 , n9990 , n10737 );
xor ( n10739 , n9023 , n10738 );
and ( n10740 , n10739 , n6584 );
or ( n10741 , n9989 , n10740 );
and ( n10742 , n9987 , n10741 );
buf ( n10743 , n10742 );
buf ( n10744 , n10743 );
not ( n10745 , n6578 );
not ( n10746 , n6584 );
and ( n10747 , n10746 , n7845 );
xor ( n10748 , n7850 , n10433 );
xor ( n10749 , n10748 , n7029 );
not ( n10750 , n8483 );
and ( n10751 , n10750 , n8507 );
xor ( n10752 , n10749 , n10751 );
buf ( n10753 , n5700 );
xor ( n10754 , n10753 , n7390 );
xor ( n10755 , n10754 , n9262 );
buf ( n10756 , n5701 );
not ( n10757 , n6583 );
buf ( n10758 , n5702 );
and ( n10759 , n10757 , n10758 );
buf ( n10760 , n5703 );
xor ( n10761 , n10760 , n10758 );
and ( n10762 , n10761 , n6583 );
or ( n10763 , n10759 , n10762 );
not ( n10764 , n6583 );
buf ( n10765 , n5704 );
and ( n10766 , n10764 , n10765 );
buf ( n10767 , n5705 );
xor ( n10768 , n10767 , n10765 );
and ( n10769 , n10768 , n6583 );
or ( n10770 , n10766 , n10769 );
xor ( n10771 , n10763 , n10770 );
xor ( n10772 , n10771 , n10198 );
buf ( n10773 , n5706 );
xor ( n10774 , n10772 , n10773 );
buf ( n10775 , n5707 );
xor ( n10776 , n10774 , n10775 );
xor ( n10777 , n10756 , n10776 );
not ( n10778 , n6583 );
buf ( n10779 , n5708 );
and ( n10780 , n10778 , n10779 );
buf ( n10781 , n5709 );
xor ( n10782 , n10781 , n10779 );
and ( n10783 , n10782 , n6583 );
or ( n10784 , n10780 , n10783 );
not ( n10785 , n6583 );
buf ( n10786 , n5710 );
and ( n10787 , n10785 , n10786 );
buf ( n10788 , n5711 );
xor ( n10789 , n10788 , n10786 );
and ( n10790 , n10789 , n6583 );
or ( n10791 , n10787 , n10790 );
xor ( n10792 , n10784 , n10791 );
buf ( n10793 , n5712 );
xor ( n10794 , n10792 , n10793 );
buf ( n10795 , n5713 );
xor ( n10796 , n10794 , n10795 );
xor ( n10797 , n10796 , n9702 );
xor ( n10798 , n10777 , n10797 );
not ( n10799 , n10798 );
and ( n10800 , n10799 , n8106 );
xor ( n10801 , n10755 , n10800 );
not ( n10802 , n6583 );
buf ( n10803 , n5714 );
and ( n10804 , n10802 , n10803 );
buf ( n10805 , n5715 );
xor ( n10806 , n10805 , n10803 );
and ( n10807 , n10806 , n6583 );
or ( n10808 , n10804 , n10807 );
not ( n10809 , n6583 );
buf ( n10810 , n5716 );
and ( n10811 , n10809 , n10810 );
buf ( n10812 , n5717 );
xor ( n10813 , n10812 , n10810 );
and ( n10814 , n10813 , n6583 );
or ( n10815 , n10811 , n10814 );
xor ( n10816 , n10808 , n10815 );
buf ( n10817 , n5718 );
xor ( n10818 , n10816 , n10817 );
buf ( n10819 , n5719 );
xor ( n10820 , n10818 , n10819 );
buf ( n10821 , n5720 );
xor ( n10822 , n10820 , n10821 );
xor ( n10823 , n7122 , n10822 );
xor ( n10824 , n10823 , n10603 );
not ( n10825 , n6583 );
buf ( n10826 , n5721 );
and ( n10827 , n10825 , n10826 );
buf ( n10828 , n5722 );
xor ( n10829 , n10828 , n10826 );
and ( n10830 , n10829 , n6583 );
or ( n10831 , n10827 , n10830 );
not ( n10832 , n6583 );
buf ( n10833 , n5723 );
and ( n10834 , n10832 , n10833 );
buf ( n10835 , n5724 );
xor ( n10836 , n10835 , n10833 );
and ( n10837 , n10836 , n6583 );
or ( n10838 , n10834 , n10837 );
xor ( n10839 , n10831 , n10838 );
buf ( n10840 , n5725 );
xor ( n10841 , n10839 , n10840 );
buf ( n10842 , n5726 );
xor ( n10843 , n10841 , n10842 );
buf ( n10844 , n5727 );
xor ( n10845 , n10843 , n10844 );
xor ( n10846 , n7451 , n10845 );
not ( n10847 , n6583 );
buf ( n10848 , n5728 );
and ( n10849 , n10847 , n10848 );
buf ( n10850 , n5729 );
xor ( n10851 , n10850 , n10848 );
and ( n10852 , n10851 , n6583 );
or ( n10853 , n10849 , n10852 );
not ( n10854 , n6583 );
buf ( n10855 , n5730 );
and ( n10856 , n10854 , n10855 );
buf ( n10857 , n5731 );
xor ( n10858 , n10857 , n10855 );
and ( n10859 , n10858 , n6583 );
or ( n10860 , n10856 , n10859 );
xor ( n10861 , n10853 , n10860 );
buf ( n10862 , n5732 );
xor ( n10863 , n10861 , n10862 );
buf ( n10864 , n5733 );
xor ( n10865 , n10863 , n10864 );
buf ( n10866 , n6586 );
xor ( n10867 , n10865 , n10866 );
xor ( n10868 , n10846 , n10867 );
not ( n10869 , n10868 );
and ( n10870 , n10869 , n8251 );
xor ( n10871 , n10824 , n10870 );
xor ( n10872 , n10801 , n10871 );
not ( n10873 , n6583 );
buf ( n10874 , n5734 );
and ( n10875 , n10873 , n10874 );
buf ( n10876 , n5735 );
xor ( n10877 , n10876 , n10874 );
and ( n10878 , n10877 , n6583 );
or ( n10879 , n10875 , n10878 );
not ( n10880 , n6583 );
buf ( n10881 , n5736 );
and ( n10882 , n10880 , n10881 );
buf ( n10883 , n5737 );
xor ( n10884 , n10883 , n10881 );
and ( n10885 , n10884 , n6583 );
or ( n10886 , n10882 , n10885 );
xor ( n10887 , n10879 , n10886 );
buf ( n10888 , n5738 );
xor ( n10889 , n10887 , n10888 );
buf ( n10890 , n5739 );
xor ( n10891 , n10889 , n10890 );
buf ( n10892 , n5740 );
xor ( n10893 , n10891 , n10892 );
xor ( n10894 , n10527 , n10893 );
not ( n10895 , n6583 );
buf ( n10896 , n5741 );
and ( n10897 , n10895 , n10896 );
buf ( n10898 , n5742 );
xor ( n10899 , n10898 , n10896 );
and ( n10900 , n10899 , n6583 );
or ( n10901 , n10897 , n10900 );
not ( n10902 , n6583 );
buf ( n10903 , n5743 );
and ( n10904 , n10902 , n10903 );
buf ( n10905 , n5744 );
xor ( n10906 , n10905 , n10903 );
and ( n10907 , n10906 , n6583 );
or ( n10908 , n10904 , n10907 );
xor ( n10909 , n10901 , n10908 );
buf ( n10910 , n5745 );
xor ( n10911 , n10909 , n10910 );
buf ( n10912 , n5746 );
xor ( n10913 , n10911 , n10912 );
buf ( n10914 , n5747 );
xor ( n10915 , n10913 , n10914 );
xor ( n10916 , n10894 , n10915 );
xor ( n10917 , n10641 , n9085 );
xor ( n10918 , n10917 , n7406 );
not ( n10919 , n10918 );
and ( n10920 , n10919 , n8341 );
xor ( n10921 , n10916 , n10920 );
xor ( n10922 , n10872 , n10921 );
buf ( n10923 , n5748 );
not ( n10924 , n6583 );
buf ( n10925 , n5749 );
and ( n10926 , n10924 , n10925 );
buf ( n10927 , n5750 );
xor ( n10928 , n10927 , n10925 );
and ( n10929 , n10928 , n6583 );
or ( n10930 , n10926 , n10929 );
not ( n10931 , n6583 );
buf ( n10932 , n5751 );
and ( n10933 , n10931 , n10932 );
buf ( n10934 , n5752 );
xor ( n10935 , n10934 , n10932 );
and ( n10936 , n10935 , n6583 );
or ( n10937 , n10933 , n10936 );
xor ( n10938 , n10930 , n10937 );
buf ( n10939 , n5753 );
xor ( n10940 , n10938 , n10939 );
buf ( n10941 , n5754 );
xor ( n10942 , n10940 , n10941 );
buf ( n10943 , n5755 );
xor ( n10944 , n10942 , n10943 );
xor ( n10945 , n10923 , n10944 );
xor ( n10946 , n10945 , n9140 );
not ( n10947 , n10749 );
and ( n10948 , n10947 , n8483 );
xor ( n10949 , n10946 , n10948 );
xor ( n10950 , n10922 , n10949 );
not ( n10951 , n6583 );
buf ( n10952 , n5756 );
and ( n10953 , n10951 , n10952 );
buf ( n10954 , n5757 );
xor ( n10955 , n10954 , n10952 );
and ( n10956 , n10955 , n6583 );
or ( n10957 , n10953 , n10956 );
not ( n10958 , n6583 );
buf ( n10959 , n5758 );
and ( n10960 , n10958 , n10959 );
buf ( n10961 , n5759 );
xor ( n10962 , n10961 , n10959 );
and ( n10963 , n10962 , n6583 );
or ( n10964 , n10960 , n10963 );
xor ( n10965 , n10957 , n10964 );
buf ( n10966 , n5760 );
xor ( n10967 , n10965 , n10966 );
buf ( n10968 , n5761 );
xor ( n10969 , n10967 , n10968 );
buf ( n10970 , n5762 );
xor ( n10971 , n10969 , n10970 );
xor ( n10972 , n9228 , n10971 );
xor ( n10973 , n10972 , n6947 );
not ( n10974 , n10973 );
and ( n10975 , n10974 , n8607 );
xor ( n10976 , n8059 , n10975 );
xor ( n10977 , n10950 , n10976 );
xor ( n10978 , n10752 , n10977 );
not ( n10979 , n6583 );
buf ( n10980 , n5763 );
and ( n10981 , n10979 , n10980 );
buf ( n10982 , n5764 );
xor ( n10983 , n10982 , n10980 );
and ( n10984 , n10983 , n6583 );
or ( n10985 , n10981 , n10984 );
buf ( n10986 , n5765 );
xor ( n10987 , n10985 , n10986 );
buf ( n10988 , n5766 );
xor ( n10989 , n10987 , n10988 );
buf ( n10990 , n5767 );
xor ( n10991 , n10989 , n10990 );
buf ( n10992 , n5768 );
xor ( n10993 , n10991 , n10992 );
xor ( n10994 , n8303 , n10993 );
xor ( n10995 , n10994 , n9229 );
xor ( n10996 , n7118 , n10822 );
xor ( n10997 , n10996 , n10603 );
not ( n10998 , n10997 );
and ( n10999 , n10998 , n8636 );
xor ( n11000 , n10995 , n10999 );
not ( n11001 , n6583 );
buf ( n11002 , n5769 );
and ( n11003 , n11001 , n11002 );
buf ( n11004 , n5770 );
xor ( n11005 , n11004 , n11002 );
and ( n11006 , n11005 , n6583 );
or ( n11007 , n11003 , n11006 );
not ( n11008 , n6583 );
buf ( n11009 , n5771 );
and ( n11010 , n11008 , n11009 );
buf ( n11011 , n5772 );
xor ( n11012 , n11011 , n11009 );
and ( n11013 , n11012 , n6583 );
or ( n11014 , n11010 , n11013 );
not ( n11015 , n6583 );
buf ( n11016 , n5773 );
and ( n11017 , n11015 , n11016 );
buf ( n11018 , n5774 );
xor ( n11019 , n11018 , n11016 );
and ( n11020 , n11019 , n6583 );
or ( n11021 , n11017 , n11020 );
xor ( n11022 , n11014 , n11021 );
buf ( n11023 , n5775 );
xor ( n11024 , n11022 , n11023 );
buf ( n11025 , n5776 );
xor ( n11026 , n11024 , n11025 );
buf ( n11027 , n5777 );
xor ( n11028 , n11026 , n11027 );
xor ( n11029 , n11007 , n11028 );
xor ( n11030 , n11029 , n10366 );
buf ( n11031 , n5778 );
not ( n11032 , n6583 );
buf ( n11033 , n5779 );
and ( n11034 , n11032 , n11033 );
buf ( n11035 , n5780 );
xor ( n11036 , n11035 , n11033 );
and ( n11037 , n11036 , n6583 );
or ( n11038 , n11034 , n11037 );
not ( n11039 , n6583 );
buf ( n11040 , n5781 );
and ( n11041 , n11039 , n11040 );
buf ( n11042 , n5782 );
xor ( n11043 , n11042 , n11040 );
and ( n11044 , n11043 , n6583 );
or ( n11045 , n11041 , n11044 );
xor ( n11046 , n11038 , n11045 );
xor ( n11047 , n11046 , n9246 );
xor ( n11048 , n11047 , n10753 );
buf ( n11049 , n5783 );
xor ( n11050 , n11048 , n11049 );
xor ( n11051 , n11031 , n11050 );
not ( n11052 , n6583 );
buf ( n11053 , n5784 );
and ( n11054 , n11052 , n11053 );
buf ( n11055 , n5785 );
xor ( n11056 , n11055 , n11053 );
and ( n11057 , n11056 , n6583 );
or ( n11058 , n11054 , n11057 );
not ( n11059 , n6583 );
buf ( n11060 , n5786 );
and ( n11061 , n11059 , n11060 );
buf ( n11062 , n5787 );
xor ( n11063 , n11062 , n11060 );
and ( n11064 , n11063 , n6583 );
or ( n11065 , n11061 , n11064 );
xor ( n11066 , n11058 , n11065 );
buf ( n11067 , n5788 );
xor ( n11068 , n11066 , n11067 );
buf ( n11069 , n5789 );
xor ( n11070 , n11068 , n11069 );
buf ( n11071 , n5790 );
xor ( n11072 , n11070 , n11071 );
xor ( n11073 , n11051 , n11072 );
not ( n11074 , n11073 );
and ( n11075 , n11074 , n8684 );
xor ( n11076 , n11030 , n11075 );
xor ( n11077 , n11000 , n11076 );
xor ( n11078 , n9215 , n10971 );
xor ( n11079 , n11078 , n6947 );
not ( n11080 , n6583 );
buf ( n11081 , n5791 );
and ( n11082 , n11080 , n11081 );
buf ( n11083 , n5792 );
xor ( n11084 , n11083 , n11081 );
and ( n11085 , n11084 , n6583 );
or ( n11086 , n11082 , n11085 );
not ( n11087 , n6583 );
buf ( n11088 , n5793 );
and ( n11089 , n11087 , n11088 );
buf ( n11090 , n5794 );
xor ( n11091 , n11090 , n11088 );
and ( n11092 , n11091 , n6583 );
or ( n11093 , n11089 , n11092 );
xor ( n11094 , n11086 , n11093 );
buf ( n11095 , n5795 );
xor ( n11096 , n11094 , n11095 );
buf ( n11097 , n5796 );
xor ( n11098 , n11096 , n11097 );
buf ( n11099 , n5797 );
xor ( n11100 , n11098 , n11099 );
xor ( n11101 , n9377 , n11100 );
xor ( n11102 , n11101 , n10893 );
not ( n11103 , n11102 );
and ( n11104 , n11103 , n8767 );
xor ( n11105 , n11079 , n11104 );
xor ( n11106 , n11077 , n11105 );
not ( n11107 , n6583 );
buf ( n11108 , n5798 );
and ( n11109 , n11107 , n11108 );
buf ( n11110 , n5799 );
xor ( n11111 , n11110 , n11108 );
and ( n11112 , n11111 , n6583 );
or ( n11113 , n11109 , n11112 );
xor ( n11114 , n11113 , n10327 );
xor ( n11115 , n11114 , n10349 );
not ( n11116 , n6583 );
buf ( n11117 , n5800 );
and ( n11118 , n11116 , n11117 );
buf ( n11119 , n5801 );
xor ( n11120 , n11119 , n11117 );
and ( n11121 , n11120 , n6583 );
or ( n11122 , n11118 , n11121 );
xor ( n11123 , n11122 , n9511 );
xor ( n11124 , n11123 , n9533 );
not ( n11125 , n11124 );
and ( n11126 , n11125 , n8864 );
xor ( n11127 , n11115 , n11126 );
xor ( n11128 , n11106 , n11127 );
not ( n11129 , n6583 );
buf ( n11130 , n5802 );
and ( n11131 , n11129 , n11130 );
buf ( n11132 , n5803 );
xor ( n11133 , n11132 , n11130 );
and ( n11134 , n11133 , n6583 );
or ( n11135 , n11131 , n11134 );
not ( n11136 , n6583 );
buf ( n11137 , n5804 );
and ( n11138 , n11136 , n11137 );
buf ( n11139 , n5805 );
xor ( n11140 , n11139 , n11137 );
and ( n11141 , n11140 , n6583 );
or ( n11142 , n11138 , n11141 );
xor ( n11143 , n11135 , n11142 );
xor ( n11144 , n11143 , n10287 );
buf ( n11145 , n5806 );
xor ( n11146 , n11144 , n11145 );
xor ( n11147 , n11146 , n9900 );
xor ( n11148 , n9747 , n11147 );
not ( n11149 , n6583 );
buf ( n11150 , n5807 );
and ( n11151 , n11149 , n11150 );
buf ( n11152 , n5808 );
xor ( n11153 , n11152 , n11150 );
and ( n11154 , n11153 , n6583 );
or ( n11155 , n11151 , n11154 );
not ( n11156 , n6583 );
buf ( n11157 , n5809 );
and ( n11158 , n11156 , n11157 );
buf ( n11159 , n5810 );
xor ( n11160 , n11159 , n11157 );
and ( n11161 , n11160 , n6583 );
or ( n11162 , n11158 , n11161 );
xor ( n11163 , n11155 , n11162 );
buf ( n11164 , n5811 );
xor ( n11165 , n11163 , n11164 );
buf ( n11166 , n5812 );
xor ( n11167 , n11165 , n11166 );
buf ( n11168 , n5813 );
xor ( n11169 , n11167 , n11168 );
xor ( n11170 , n11148 , n11169 );
xor ( n11171 , n7843 , n10433 );
xor ( n11172 , n11171 , n7029 );
not ( n11173 , n11172 );
and ( n11174 , n11173 , n8976 );
xor ( n11175 , n11170 , n11174 );
xor ( n11176 , n11128 , n11175 );
xor ( n11177 , n10978 , n11176 );
not ( n11178 , n6583 );
buf ( n11179 , n5814 );
and ( n11180 , n11178 , n11179 );
buf ( n11181 , n5815 );
xor ( n11182 , n11181 , n11179 );
and ( n11183 , n11182 , n6583 );
or ( n11184 , n11180 , n11183 );
xor ( n11185 , n11184 , n10282 );
xor ( n11186 , n11185 , n8789 );
not ( n11187 , n6583 );
buf ( n11188 , n5816 );
and ( n11189 , n11187 , n11188 );
buf ( n11190 , n5817 );
xor ( n11191 , n11190 , n11188 );
and ( n11192 , n11191 , n6583 );
or ( n11193 , n11189 , n11192 );
xor ( n11194 , n11193 , n7677 );
xor ( n11195 , n11194 , n7686 );
not ( n11196 , n11195 );
buf ( n11197 , n5818 );
not ( n11198 , n6583 );
buf ( n11199 , n5819 );
and ( n11200 , n11198 , n11199 );
buf ( n11201 , n5820 );
xor ( n11202 , n11201 , n11199 );
and ( n11203 , n11202 , n6583 );
or ( n11204 , n11200 , n11203 );
not ( n11205 , n6583 );
buf ( n11206 , n5821 );
and ( n11207 , n11205 , n11206 );
buf ( n11208 , n5822 );
xor ( n11209 , n11208 , n11206 );
and ( n11210 , n11209 , n6583 );
or ( n11211 , n11207 , n11210 );
xor ( n11212 , n11204 , n11211 );
buf ( n11213 , n5823 );
xor ( n11214 , n11212 , n11213 );
buf ( n11215 , n5824 );
xor ( n11216 , n11214 , n11215 );
buf ( n11217 , n5825 );
xor ( n11218 , n11216 , n11217 );
xor ( n11219 , n11197 , n11218 );
xor ( n11220 , n11219 , n7782 );
and ( n11221 , n11196 , n11220 );
xor ( n11222 , n11186 , n11221 );
buf ( n11223 , n5826 );
xor ( n11224 , n11223 , n9855 );
xor ( n11225 , n11224 , n9877 );
not ( n11226 , n6583 );
buf ( n11227 , n5827 );
and ( n11228 , n11226 , n11227 );
buf ( n11229 , n5828 );
xor ( n11230 , n11229 , n11227 );
and ( n11231 , n11230 , n6583 );
or ( n11232 , n11228 , n11231 );
xor ( n11233 , n11232 , n10509 );
buf ( n11234 , n5829 );
xor ( n11235 , n11233 , n11234 );
buf ( n11236 , n5830 );
xor ( n11237 , n11235 , n11236 );
xor ( n11238 , n11237 , n9088 );
xor ( n11239 , n8516 , n11238 );
xor ( n11240 , n11239 , n9406 );
not ( n11241 , n11240 );
not ( n11242 , n6583 );
buf ( n11243 , n5831 );
and ( n11244 , n11242 , n11243 );
buf ( n11245 , n5832 );
xor ( n11246 , n11245 , n11243 );
and ( n11247 , n11246 , n6583 );
or ( n11248 , n11244 , n11247 );
xor ( n11249 , n11248 , n6774 );
xor ( n11250 , n11249 , n7980 );
and ( n11251 , n11241 , n11250 );
xor ( n11252 , n11225 , n11251 );
xor ( n11253 , n9383 , n11100 );
xor ( n11254 , n11253 , n10893 );
not ( n11255 , n6583 );
buf ( n11256 , n5833 );
and ( n11257 , n11255 , n11256 );
buf ( n11258 , n5834 );
xor ( n11259 , n11258 , n11256 );
and ( n11260 , n11259 , n6583 );
or ( n11261 , n11257 , n11260 );
not ( n11262 , n6583 );
buf ( n11263 , n5835 );
and ( n11264 , n11262 , n11263 );
buf ( n11265 , n5836 );
xor ( n11266 , n11265 , n11263 );
and ( n11267 , n11266 , n6583 );
or ( n11268 , n11264 , n11267 );
xor ( n11269 , n11261 , n11268 );
buf ( n11270 , n5837 );
xor ( n11271 , n11269 , n11270 );
buf ( n11272 , n5838 );
xor ( n11273 , n11271 , n11272 );
buf ( n11274 , n5839 );
xor ( n11275 , n11273 , n11274 );
xor ( n11276 , n7275 , n11275 );
xor ( n11277 , n11276 , n6797 );
not ( n11278 , n11277 );
not ( n11279 , n6583 );
buf ( n11280 , n5840 );
and ( n11281 , n11279 , n11280 );
buf ( n11282 , n5841 );
xor ( n11283 , n11282 , n11280 );
and ( n11284 , n11283 , n6583 );
or ( n11285 , n11281 , n11284 );
xor ( n11286 , n11285 , n7298 );
buf ( n11287 , n5842 );
xor ( n11288 , n11286 , n11287 );
buf ( n11289 , n5843 );
xor ( n11290 , n11288 , n11289 );
buf ( n11291 , n5844 );
xor ( n11292 , n11290 , n11291 );
xor ( n11293 , n10359 , n11292 );
not ( n11294 , n6583 );
buf ( n11295 , n5845 );
and ( n11296 , n11294 , n11295 );
buf ( n11297 , n5846 );
xor ( n11298 , n11297 , n11295 );
and ( n11299 , n11298 , n6583 );
or ( n11300 , n11296 , n11299 );
not ( n11301 , n6583 );
buf ( n11302 , n5847 );
and ( n11303 , n11301 , n11302 );
buf ( n11304 , n5848 );
xor ( n11305 , n11304 , n11302 );
and ( n11306 , n11305 , n6583 );
or ( n11307 , n11303 , n11306 );
xor ( n11308 , n11300 , n11307 );
buf ( n11309 , n5849 );
xor ( n11310 , n11308 , n11309 );
buf ( n11311 , n5850 );
xor ( n11312 , n11310 , n11311 );
buf ( n11313 , n5851 );
xor ( n11314 , n11312 , n11313 );
xor ( n11315 , n11293 , n11314 );
and ( n11316 , n11278 , n11315 );
xor ( n11317 , n11254 , n11316 );
xor ( n11318 , n11252 , n11317 );
buf ( n11319 , n5852 );
xor ( n11320 , n11113 , n11319 );
xor ( n11321 , n11320 , n10313 );
buf ( n11322 , n5853 );
xor ( n11323 , n11321 , n11322 );
buf ( n11324 , n5854 );
xor ( n11325 , n11323 , n11324 );
xor ( n11326 , n8481 , n11325 );
not ( n11327 , n6583 );
buf ( n11328 , n5855 );
and ( n11329 , n11327 , n11328 );
buf ( n11330 , n5856 );
xor ( n11331 , n11330 , n11328 );
and ( n11332 , n11331 , n6583 );
or ( n11333 , n11329 , n11332 );
not ( n11334 , n6583 );
buf ( n11335 , n5857 );
and ( n11336 , n11334 , n11335 );
buf ( n11337 , n5858 );
xor ( n11338 , n11337 , n11335 );
and ( n11339 , n11338 , n6583 );
or ( n11340 , n11336 , n11339 );
xor ( n11341 , n11333 , n11340 );
buf ( n11342 , n5859 );
xor ( n11343 , n11341 , n11342 );
buf ( n11344 , n5860 );
xor ( n11345 , n11343 , n11344 );
buf ( n11346 , n5861 );
xor ( n11347 , n11345 , n11346 );
xor ( n11348 , n11326 , n11347 );
xor ( n11349 , n9393 , n8841 );
xor ( n11350 , n11349 , n8863 );
not ( n11351 , n11350 );
not ( n11352 , n6583 );
buf ( n11353 , n5862 );
and ( n11354 , n11352 , n11353 );
buf ( n11355 , n5863 );
xor ( n11356 , n11355 , n11353 );
and ( n11357 , n11356 , n6583 );
or ( n11358 , n11354 , n11357 );
xor ( n11359 , n11358 , n8886 );
xor ( n11360 , n11359 , n8908 );
and ( n11361 , n11351 , n11360 );
xor ( n11362 , n11348 , n11361 );
xor ( n11363 , n11318 , n11362 );
xor ( n11364 , n6614 , n8340 );
xor ( n11365 , n11364 , n8270 );
xor ( n11366 , n9503 , n6918 );
not ( n11367 , n6583 );
buf ( n11368 , n5864 );
and ( n11369 , n11367 , n11368 );
buf ( n11370 , n5865 );
xor ( n11371 , n11370 , n11368 );
and ( n11372 , n11371 , n6583 );
or ( n11373 , n11369 , n11372 );
not ( n11374 , n6583 );
buf ( n11375 , n5866 );
and ( n11376 , n11374 , n11375 );
buf ( n11377 , n5867 );
xor ( n11378 , n11377 , n11375 );
and ( n11379 , n11378 , n6583 );
or ( n11380 , n11376 , n11379 );
xor ( n11381 , n11373 , n11380 );
buf ( n11382 , n5868 );
xor ( n11383 , n11381 , n11382 );
xor ( n11384 , n11383 , n9882 );
buf ( n11385 , n5869 );
xor ( n11386 , n11384 , n11385 );
xor ( n11387 , n11366 , n11386 );
not ( n11388 , n11387 );
xor ( n11389 , n8698 , n10308 );
not ( n11390 , n6583 );
buf ( n11391 , n5870 );
and ( n11392 , n11390 , n11391 );
buf ( n11393 , n5871 );
xor ( n11394 , n11393 , n11391 );
and ( n11395 , n11394 , n6583 );
or ( n11396 , n11392 , n11395 );
not ( n11397 , n6583 );
buf ( n11398 , n5872 );
and ( n11399 , n11397 , n11398 );
buf ( n11400 , n5873 );
xor ( n11401 , n11400 , n11398 );
and ( n11402 , n11401 , n6583 );
or ( n11403 , n11399 , n11402 );
xor ( n11404 , n11396 , n11403 );
buf ( n11405 , n5874 );
xor ( n11406 , n11404 , n11405 );
buf ( n11407 , n5875 );
xor ( n11408 , n11406 , n11407 );
buf ( n11409 , n5876 );
xor ( n11410 , n11408 , n11409 );
xor ( n11411 , n11389 , n11410 );
and ( n11412 , n11388 , n11411 );
xor ( n11413 , n11365 , n11412 );
xor ( n11414 , n11363 , n11413 );
xor ( n11415 , n6680 , n9598 );
not ( n11416 , n6583 );
buf ( n11417 , n5877 );
and ( n11418 , n11416 , n11417 );
buf ( n11419 , n5878 );
xor ( n11420 , n11419 , n11417 );
and ( n11421 , n11420 , n6583 );
or ( n11422 , n11418 , n11421 );
not ( n11423 , n6583 );
buf ( n11424 , n5879 );
and ( n11425 , n11423 , n11424 );
buf ( n11426 , n5880 );
xor ( n11427 , n11426 , n11424 );
and ( n11428 , n11427 , n6583 );
or ( n11429 , n11425 , n11428 );
xor ( n11430 , n11422 , n11429 );
buf ( n11431 , n5881 );
xor ( n11432 , n11430 , n11431 );
buf ( n11433 , n5882 );
xor ( n11434 , n11432 , n11433 );
buf ( n11435 , n5883 );
xor ( n11436 , n11434 , n11435 );
xor ( n11437 , n11415 , n11436 );
not ( n11438 , n11186 );
and ( n11439 , n11438 , n11195 );
xor ( n11440 , n11437 , n11439 );
xor ( n11441 , n11414 , n11440 );
xor ( n11442 , n11222 , n11441 );
xor ( n11443 , n7821 , n10411 );
xor ( n11444 , n11443 , n10433 );
buf ( n11445 , n5884 );
not ( n11446 , n6583 );
buf ( n11447 , n5885 );
and ( n11448 , n11446 , n11447 );
buf ( n11449 , n5886 );
xor ( n11450 , n11449 , n11447 );
and ( n11451 , n11450 , n6583 );
or ( n11452 , n11448 , n11451 );
xor ( n11453 , n11452 , n11248 );
buf ( n11454 , n5887 );
xor ( n11455 , n11453 , n11454 );
buf ( n11456 , n5888 );
xor ( n11457 , n11455 , n11456 );
buf ( n11458 , n5889 );
xor ( n11459 , n11457 , n11458 );
xor ( n11460 , n11445 , n11459 );
not ( n11461 , n6583 );
buf ( n11462 , n5890 );
and ( n11463 , n11461 , n11462 );
buf ( n11464 , n5891 );
xor ( n11465 , n11464 , n11462 );
and ( n11466 , n11465 , n6583 );
or ( n11467 , n11463 , n11466 );
xor ( n11468 , n11467 , n7960 );
buf ( n11469 , n5892 );
xor ( n11470 , n11468 , n11469 );
buf ( n11471 , n5893 );
xor ( n11472 , n11470 , n11471 );
buf ( n11473 , n5894 );
xor ( n11474 , n11472 , n11473 );
xor ( n11475 , n11460 , n11474 );
not ( n11476 , n11475 );
buf ( n11477 , n5895 );
not ( n11478 , n6583 );
buf ( n11479 , n5896 );
and ( n11480 , n11478 , n11479 );
buf ( n11481 , n5897 );
xor ( n11482 , n11481 , n11479 );
and ( n11483 , n11482 , n6583 );
or ( n11484 , n11480 , n11483 );
not ( n11485 , n6583 );
buf ( n11486 , n5898 );
and ( n11487 , n11485 , n11486 );
buf ( n11488 , n5899 );
xor ( n11489 , n11488 , n11486 );
and ( n11490 , n11489 , n6583 );
or ( n11491 , n11487 , n11490 );
xor ( n11492 , n11484 , n11491 );
xor ( n11493 , n11492 , n10077 );
buf ( n11494 , n5900 );
xor ( n11495 , n11493 , n11494 );
buf ( n11496 , n5901 );
xor ( n11497 , n11495 , n11496 );
xor ( n11498 , n11477 , n11497 );
not ( n11499 , n6583 );
buf ( n11500 , n5902 );
and ( n11501 , n11499 , n11500 );
buf ( n11502 , n5903 );
xor ( n11503 , n11502 , n11500 );
and ( n11504 , n11503 , n6583 );
or ( n11505 , n11501 , n11504 );
buf ( n11506 , n5904 );
xor ( n11507 , n11505 , n11506 );
buf ( n11508 , n5905 );
xor ( n11509 , n11507 , n11508 );
buf ( n11510 , n5906 );
xor ( n11511 , n11509 , n11510 );
buf ( n11512 , n5907 );
xor ( n11513 , n11511 , n11512 );
xor ( n11514 , n11498 , n11513 );
and ( n11515 , n11476 , n11514 );
xor ( n11516 , n11444 , n11515 );
not ( n11517 , n6583 );
buf ( n11518 , n5908 );
and ( n11519 , n11517 , n11518 );
buf ( n11520 , n5909 );
xor ( n11521 , n11520 , n11518 );
and ( n11522 , n11521 , n6583 );
or ( n11523 , n11519 , n11522 );
xor ( n11524 , n11523 , n7862 );
buf ( n11525 , n5910 );
xor ( n11526 , n11524 , n11525 );
buf ( n11527 , n5911 );
xor ( n11528 , n11526 , n11527 );
xor ( n11529 , n11528 , n7152 );
xor ( n11530 , n7328 , n11529 );
not ( n11531 , n6583 );
buf ( n11532 , n5912 );
and ( n11533 , n11531 , n11532 );
buf ( n11534 , n5913 );
xor ( n11535 , n11534 , n11532 );
and ( n11536 , n11535 , n6583 );
or ( n11537 , n11533 , n11536 );
xor ( n11538 , n11537 , n9318 );
buf ( n11539 , n5914 );
xor ( n11540 , n11538 , n11539 );
buf ( n11541 , n5915 );
xor ( n11542 , n11540 , n11541 );
buf ( n11543 , n5916 );
xor ( n11544 , n11542 , n11543 );
xor ( n11545 , n11530 , n11544 );
buf ( n11546 , n5917 );
not ( n11547 , n6583 );
buf ( n11548 , n5918 );
and ( n11549 , n11547 , n11548 );
buf ( n11550 , n5919 );
xor ( n11551 , n11550 , n11548 );
and ( n11552 , n11551 , n6583 );
or ( n11553 , n11549 , n11552 );
buf ( n11554 , n5920 );
xor ( n11555 , n11553 , n11554 );
buf ( n11556 , n5921 );
xor ( n11557 , n11555 , n11556 );
buf ( n11558 , n5922 );
xor ( n11559 , n11557 , n11558 );
xor ( n11560 , n11559 , n10756 );
xor ( n11561 , n11546 , n11560 );
xor ( n11562 , n11561 , n10944 );
not ( n11563 , n11562 );
buf ( n11564 , n5923 );
xor ( n11565 , n11564 , n10698 );
xor ( n11566 , n11565 , n8932 );
and ( n11567 , n11563 , n11566 );
xor ( n11568 , n11545 , n11567 );
xor ( n11569 , n11516 , n11568 );
not ( n11570 , n6583 );
buf ( n11571 , n5924 );
and ( n11572 , n11570 , n11571 );
buf ( n11573 , n5925 );
xor ( n11574 , n11573 , n11571 );
and ( n11575 , n11574 , n6583 );
or ( n11576 , n11572 , n11575 );
not ( n11577 , n6583 );
buf ( n11578 , n5926 );
and ( n11579 , n11577 , n11578 );
buf ( n11580 , n5927 );
xor ( n11581 , n11580 , n11578 );
and ( n11582 , n11581 , n6583 );
or ( n11583 , n11579 , n11582 );
xor ( n11584 , n11576 , n11583 );
buf ( n11585 , n5928 );
xor ( n11586 , n11584 , n11585 );
buf ( n11587 , n5929 );
xor ( n11588 , n11586 , n11587 );
buf ( n11589 , n5930 );
xor ( n11590 , n11588 , n11589 );
xor ( n11591 , n9062 , n11590 );
not ( n11592 , n6583 );
buf ( n11593 , n5931 );
and ( n11594 , n11592 , n11593 );
buf ( n11595 , n5932 );
xor ( n11596 , n11595 , n11593 );
and ( n11597 , n11596 , n6583 );
or ( n11598 , n11594 , n11597 );
xor ( n11599 , n10505 , n11598 );
buf ( n11600 , n5933 );
xor ( n11601 , n11599 , n11600 );
xor ( n11602 , n11601 , n9539 );
buf ( n11603 , n5934 );
xor ( n11604 , n11602 , n11603 );
xor ( n11605 , n11591 , n11604 );
buf ( n11606 , n5935 );
not ( n11607 , n6583 );
buf ( n11608 , n5936 );
and ( n11609 , n11607 , n11608 );
buf ( n11610 , n5937 );
xor ( n11611 , n11610 , n11608 );
and ( n11612 , n11611 , n6583 );
or ( n11613 , n11609 , n11612 );
not ( n11614 , n6583 );
buf ( n11615 , n5938 );
and ( n11616 , n11614 , n11615 );
buf ( n11617 , n5939 );
xor ( n11618 , n11617 , n11615 );
and ( n11619 , n11618 , n6583 );
or ( n11620 , n11616 , n11619 );
xor ( n11621 , n11613 , n11620 );
buf ( n11622 , n5940 );
xor ( n11623 , n11621 , n11622 );
buf ( n11624 , n5941 );
xor ( n11625 , n11623 , n11624 );
xor ( n11626 , n11625 , n6875 );
xor ( n11627 , n11606 , n11626 );
xor ( n11628 , n11627 , n9511 );
not ( n11629 , n11628 );
not ( n11630 , n6583 );
buf ( n11631 , n5942 );
and ( n11632 , n11630 , n11631 );
buf ( n11633 , n5943 );
xor ( n11634 , n11633 , n11631 );
and ( n11635 , n11634 , n6583 );
or ( n11636 , n11632 , n11635 );
not ( n11637 , n6583 );
buf ( n11638 , n5944 );
and ( n11639 , n11637 , n11638 );
buf ( n11640 , n5945 );
xor ( n11641 , n11640 , n11638 );
and ( n11642 , n11641 , n6583 );
or ( n11643 , n11639 , n11642 );
xor ( n11644 , n11636 , n11643 );
buf ( n11645 , n5946 );
xor ( n11646 , n11644 , n11645 );
buf ( n11647 , n5947 );
xor ( n11648 , n11646 , n11647 );
buf ( n11649 , n5948 );
xor ( n11650 , n11648 , n11649 );
xor ( n11651 , n8804 , n11650 );
xor ( n11652 , n11651 , n7368 );
and ( n11653 , n11629 , n11652 );
xor ( n11654 , n11605 , n11653 );
xor ( n11655 , n11569 , n11654 );
not ( n11656 , n6583 );
buf ( n11657 , n5949 );
and ( n11658 , n11656 , n11657 );
buf ( n11659 , n5950 );
xor ( n11660 , n11659 , n11657 );
and ( n11661 , n11660 , n6583 );
or ( n11662 , n11658 , n11661 );
xor ( n11663 , n11662 , n10619 );
not ( n11664 , n6583 );
buf ( n11665 , n5951 );
and ( n11666 , n11664 , n11665 );
buf ( n11667 , n5952 );
xor ( n11668 , n11667 , n11665 );
and ( n11669 , n11668 , n6583 );
or ( n11670 , n11666 , n11669 );
not ( n11671 , n6583 );
buf ( n11672 , n5953 );
and ( n11673 , n11671 , n11672 );
buf ( n11674 , n5954 );
xor ( n11675 , n11674 , n11672 );
and ( n11676 , n11675 , n6583 );
or ( n11677 , n11673 , n11676 );
xor ( n11678 , n11670 , n11677 );
buf ( n11679 , n5955 );
xor ( n11680 , n11678 , n11679 );
buf ( n11681 , n5956 );
xor ( n11682 , n11680 , n11681 );
buf ( n11683 , n5957 );
xor ( n11684 , n11682 , n11683 );
xor ( n11685 , n11663 , n11684 );
buf ( n11686 , n5958 );
xor ( n11687 , n11686 , n7579 );
xor ( n11688 , n11687 , n7600 );
not ( n11689 , n11688 );
not ( n11690 , n6583 );
buf ( n11691 , n5959 );
and ( n11692 , n11690 , n11691 );
buf ( n11693 , n5960 );
xor ( n11694 , n11693 , n11691 );
and ( n11695 , n11694 , n6583 );
or ( n11696 , n11692 , n11695 );
not ( n11697 , n6583 );
buf ( n11698 , n5961 );
and ( n11699 , n11697 , n11698 );
buf ( n11700 , n5962 );
xor ( n11701 , n11700 , n11698 );
and ( n11702 , n11701 , n6583 );
or ( n11703 , n11699 , n11702 );
xor ( n11704 , n11696 , n11703 );
buf ( n11705 , n5963 );
xor ( n11706 , n11704 , n11705 );
buf ( n11707 , n5964 );
xor ( n11708 , n11706 , n11707 );
buf ( n11709 , n5965 );
xor ( n11710 , n11708 , n11709 );
xor ( n11711 , n8754 , n11710 );
xor ( n11712 , n11711 , n8460 );
and ( n11713 , n11689 , n11712 );
xor ( n11714 , n11685 , n11713 );
xor ( n11715 , n11655 , n11714 );
xor ( n11716 , n6608 , n8340 );
xor ( n11717 , n11716 , n8270 );
buf ( n11718 , n5966 );
not ( n11719 , n6583 );
buf ( n11720 , n5967 );
and ( n11721 , n11719 , n11720 );
buf ( n11722 , n5968 );
xor ( n11723 , n11722 , n11720 );
and ( n11724 , n11723 , n6583 );
or ( n11725 , n11721 , n11724 );
not ( n11726 , n6583 );
buf ( n11727 , n5969 );
and ( n11728 , n11726 , n11727 );
buf ( n11729 , n5970 );
xor ( n11730 , n11729 , n11727 );
and ( n11731 , n11730 , n6583 );
or ( n11732 , n11728 , n11731 );
xor ( n11733 , n11725 , n11732 );
buf ( n11734 , n5971 );
xor ( n11735 , n11733 , n11734 );
buf ( n11736 , n5972 );
xor ( n11737 , n11735 , n11736 );
buf ( n11738 , n5973 );
xor ( n11739 , n11737 , n11738 );
xor ( n11740 , n11718 , n11739 );
not ( n11741 , n6583 );
buf ( n11742 , n5974 );
and ( n11743 , n11741 , n11742 );
buf ( n11744 , n5975 );
xor ( n11745 , n11744 , n11742 );
and ( n11746 , n11745 , n6583 );
or ( n11747 , n11743 , n11746 );
not ( n11748 , n6583 );
buf ( n11749 , n5976 );
and ( n11750 , n11748 , n11749 );
buf ( n11751 , n5977 );
xor ( n11752 , n11751 , n11749 );
and ( n11753 , n11752 , n6583 );
or ( n11754 , n11750 , n11753 );
xor ( n11755 , n11747 , n11754 );
buf ( n11756 , n5978 );
xor ( n11757 , n11755 , n11756 );
buf ( n11758 , n5979 );
xor ( n11759 , n11757 , n11758 );
buf ( n11760 , n5980 );
xor ( n11761 , n11759 , n11760 );
xor ( n11762 , n11740 , n11761 );
not ( n11763 , n11762 );
buf ( n11764 , n5981 );
xor ( n11765 , n11764 , n9455 );
not ( n11766 , n6583 );
buf ( n11767 , n5982 );
and ( n11768 , n11766 , n11767 );
buf ( n11769 , n5983 );
xor ( n11770 , n11769 , n11767 );
and ( n11771 , n11770 , n6583 );
or ( n11772 , n11768 , n11771 );
not ( n11773 , n6583 );
buf ( n11774 , n5984 );
and ( n11775 , n11773 , n11774 );
buf ( n11776 , n5985 );
xor ( n11777 , n11776 , n11774 );
and ( n11778 , n11777 , n6583 );
or ( n11779 , n11775 , n11778 );
xor ( n11780 , n11772 , n11779 );
buf ( n11781 , n5986 );
xor ( n11782 , n11780 , n11781 );
buf ( n11783 , n5987 );
xor ( n11784 , n11782 , n11783 );
buf ( n11785 , n5988 );
xor ( n11786 , n11784 , n11785 );
xor ( n11787 , n11765 , n11786 );
and ( n11788 , n11763 , n11787 );
xor ( n11789 , n11717 , n11788 );
xor ( n11790 , n11715 , n11789 );
xor ( n11791 , n11442 , n11790 );
not ( n11792 , n11791 );
not ( n11793 , n6583 );
buf ( n11794 , n5989 );
and ( n11795 , n11793 , n11794 );
buf ( n11796 , n5990 );
xor ( n11797 , n11796 , n11794 );
and ( n11798 , n11797 , n6583 );
or ( n11799 , n11795 , n11798 );
xor ( n11800 , n11799 , n11122 );
buf ( n11801 , n5991 );
xor ( n11802 , n11800 , n11801 );
xor ( n11803 , n11802 , n9496 );
buf ( n11804 , n5992 );
xor ( n11805 , n11803 , n11804 );
xor ( n11806 , n7260 , n11805 );
xor ( n11807 , n11806 , n11275 );
xor ( n11808 , n11622 , n6896 );
xor ( n11809 , n11808 , n6918 );
not ( n11810 , n11809 );
xor ( n11811 , n10773 , n10219 );
xor ( n11812 , n11811 , n9715 );
and ( n11813 , n11810 , n11812 );
xor ( n11814 , n11807 , n11813 );
not ( n11815 , n6583 );
buf ( n11816 , n5993 );
and ( n11817 , n11815 , n11816 );
buf ( n11818 , n5994 );
xor ( n11819 , n11818 , n11816 );
and ( n11820 , n11819 , n6583 );
or ( n11821 , n11817 , n11820 );
xor ( n11822 , n11821 , n7029 );
xor ( n11823 , n11822 , n7051 );
not ( n11824 , n11807 );
and ( n11825 , n11824 , n11809 );
xor ( n11826 , n11823 , n11825 );
xor ( n11827 , n11038 , n7390 );
xor ( n11828 , n11827 , n9262 );
buf ( n11829 , n5995 );
xor ( n11830 , n11829 , n9787 );
not ( n11831 , n6583 );
buf ( n11832 , n5996 );
and ( n11833 , n11831 , n11832 );
buf ( n11834 , n5997 );
xor ( n11835 , n11834 , n11832 );
and ( n11836 , n11835 , n6583 );
or ( n11837 , n11833 , n11836 );
not ( n11838 , n6583 );
buf ( n11839 , n5998 );
and ( n11840 , n11838 , n11839 );
buf ( n11841 , n5999 );
xor ( n11842 , n11841 , n11839 );
and ( n11843 , n11842 , n6583 );
or ( n11844 , n11840 , n11843 );
xor ( n11845 , n11837 , n11844 );
xor ( n11846 , n11845 , n11546 );
buf ( n11847 , n6000 );
xor ( n11848 , n11846 , n11847 );
buf ( n11849 , n6001 );
xor ( n11850 , n11848 , n11849 );
xor ( n11851 , n11830 , n11850 );
not ( n11852 , n11851 );
not ( n11853 , n6583 );
buf ( n11854 , n6002 );
and ( n11855 , n11853 , n11854 );
buf ( n11856 , n6003 );
xor ( n11857 , n11856 , n11854 );
and ( n11858 , n11857 , n6583 );
or ( n11859 , n11855 , n11858 );
xor ( n11860 , n11859 , n7473 );
buf ( n11861 , n6004 );
xor ( n11862 , n11860 , n11861 );
buf ( n11863 , n6005 );
xor ( n11864 , n11862 , n11863 );
buf ( n11865 , n6006 );
xor ( n11866 , n11864 , n11865 );
xor ( n11867 , n7004 , n11866 );
xor ( n11868 , n11867 , n10845 );
and ( n11869 , n11852 , n11868 );
xor ( n11870 , n11828 , n11869 );
xor ( n11871 , n11826 , n11870 );
not ( n11872 , n6583 );
buf ( n11873 , n6007 );
and ( n11874 , n11872 , n11873 );
buf ( n11875 , n6008 );
xor ( n11876 , n11875 , n11873 );
and ( n11877 , n11876 , n6583 );
or ( n11878 , n11874 , n11877 );
not ( n11879 , n6583 );
buf ( n11880 , n6009 );
and ( n11881 , n11879 , n11880 );
buf ( n11882 , n6010 );
xor ( n11883 , n11882 , n11880 );
and ( n11884 , n11883 , n6583 );
or ( n11885 , n11881 , n11884 );
xor ( n11886 , n11878 , n11885 );
buf ( n11887 , n6011 );
xor ( n11888 , n11886 , n11887 );
buf ( n11889 , n6012 );
xor ( n11890 , n11888 , n11889 );
buf ( n11891 , n6013 );
xor ( n11892 , n11890 , n11891 );
xor ( n11893 , n7037 , n11892 );
not ( n11894 , n6583 );
buf ( n11895 , n6014 );
and ( n11896 , n11894 , n11895 );
buf ( n11897 , n6015 );
xor ( n11898 , n11897 , n11895 );
and ( n11899 , n11898 , n6583 );
or ( n11900 , n11896 , n11899 );
xor ( n11901 , n9951 , n11900 );
buf ( n11902 , n6016 );
xor ( n11903 , n11901 , n11902 );
buf ( n11904 , n6017 );
xor ( n11905 , n11903 , n11904 );
buf ( n11906 , n6018 );
xor ( n11907 , n11905 , n11906 );
xor ( n11908 , n11893 , n11907 );
xor ( n11909 , n9754 , n11147 );
xor ( n11910 , n11909 , n11169 );
not ( n11911 , n11910 );
xor ( n11912 , n11600 , n9560 );
xor ( n11913 , n11912 , n8807 );
and ( n11914 , n11911 , n11913 );
xor ( n11915 , n11908 , n11914 );
xor ( n11916 , n11871 , n11915 );
not ( n11917 , n6583 );
buf ( n11918 , n6019 );
and ( n11919 , n11917 , n11918 );
buf ( n11920 , n6020 );
xor ( n11921 , n11920 , n11918 );
and ( n11922 , n11921 , n6583 );
or ( n11923 , n11919 , n11922 );
xor ( n11924 , n11923 , n7428 );
xor ( n11925 , n11924 , n7579 );
xor ( n11926 , n10342 , n8250 );
not ( n11927 , n6583 );
buf ( n11928 , n6021 );
and ( n11929 , n11927 , n11928 );
buf ( n11930 , n6022 );
xor ( n11931 , n11930 , n11928 );
and ( n11932 , n11931 , n6583 );
or ( n11933 , n11929 , n11932 );
not ( n11934 , n6583 );
buf ( n11935 , n6023 );
and ( n11936 , n11934 , n11935 );
buf ( n11937 , n6024 );
xor ( n11938 , n11937 , n11935 );
and ( n11939 , n11938 , n6583 );
or ( n11940 , n11936 , n11939 );
xor ( n11941 , n11933 , n11940 );
buf ( n11942 , n6025 );
xor ( n11943 , n11941 , n11942 );
buf ( n11944 , n6026 );
xor ( n11945 , n11943 , n11944 );
buf ( n11946 , n6027 );
xor ( n11947 , n11945 , n11946 );
xor ( n11948 , n11926 , n11947 );
not ( n11949 , n11948 );
buf ( n11950 , n6028 );
xor ( n11951 , n11950 , n6636 );
xor ( n11952 , n11951 , n9018 );
and ( n11953 , n11949 , n11952 );
xor ( n11954 , n11925 , n11953 );
xor ( n11955 , n11916 , n11954 );
xor ( n11956 , n7967 , n7828 );
xor ( n11957 , n11956 , n7851 );
not ( n11958 , n6583 );
buf ( n11959 , n6029 );
and ( n11960 , n11958 , n11959 );
buf ( n11961 , n6030 );
xor ( n11962 , n11961 , n11959 );
and ( n11963 , n11962 , n6583 );
or ( n11964 , n11960 , n11963 );
not ( n11965 , n6583 );
buf ( n11966 , n6031 );
and ( n11967 , n11965 , n11966 );
buf ( n11968 , n6032 );
xor ( n11969 , n11968 , n11966 );
and ( n11970 , n11969 , n6583 );
or ( n11971 , n11967 , n11970 );
xor ( n11972 , n11964 , n11971 );
buf ( n11973 , n6033 );
xor ( n11974 , n11972 , n11973 );
buf ( n11975 , n6034 );
xor ( n11976 , n11974 , n11975 );
buf ( n11977 , n6035 );
xor ( n11978 , n11976 , n11977 );
xor ( n11979 , n7703 , n11978 );
not ( n11980 , n6583 );
buf ( n11981 , n6036 );
and ( n11982 , n11980 , n11981 );
buf ( n11983 , n6037 );
xor ( n11984 , n11983 , n11981 );
and ( n11985 , n11984 , n6583 );
or ( n11986 , n11982 , n11985 );
buf ( n11987 , n6038 );
xor ( n11988 , n11986 , n11987 );
xor ( n11989 , n11988 , n11197 );
buf ( n11990 , n6039 );
xor ( n11991 , n11989 , n11990 );
buf ( n11992 , n6040 );
xor ( n11993 , n11991 , n11992 );
xor ( n11994 , n11979 , n11993 );
not ( n11995 , n11994 );
not ( n11996 , n6583 );
buf ( n11997 , n6041 );
and ( n11998 , n11996 , n11997 );
buf ( n11999 , n6042 );
xor ( n12000 , n11999 , n11997 );
and ( n12001 , n12000 , n6583 );
or ( n12002 , n11998 , n12001 );
not ( n12003 , n6583 );
buf ( n12004 , n6043 );
and ( n12005 , n12003 , n12004 );
buf ( n12006 , n6044 );
xor ( n12007 , n12006 , n12004 );
and ( n12008 , n12007 , n6583 );
or ( n12009 , n12005 , n12008 );
xor ( n12010 , n12002 , n12009 );
buf ( n12011 , n6045 );
xor ( n12012 , n12010 , n12011 );
xor ( n12013 , n12012 , n11477 );
buf ( n12014 , n6046 );
xor ( n12015 , n12013 , n12014 );
xor ( n12016 , n7184 , n12015 );
not ( n12017 , n6583 );
buf ( n12018 , n6047 );
and ( n12019 , n12017 , n12018 );
buf ( n12020 , n6048 );
xor ( n12021 , n12020 , n12018 );
and ( n12022 , n12021 , n6583 );
or ( n12023 , n12019 , n12022 );
not ( n12024 , n6583 );
buf ( n12025 , n6049 );
and ( n12026 , n12024 , n12025 );
buf ( n12027 , n6050 );
xor ( n12028 , n12027 , n12025 );
and ( n12029 , n12028 , n6583 );
or ( n12030 , n12026 , n12029 );
xor ( n12031 , n12023 , n12030 );
buf ( n12032 , n6051 );
xor ( n12033 , n12031 , n12032 );
buf ( n12034 , n6052 );
xor ( n12035 , n12033 , n12034 );
buf ( n12036 , n6053 );
xor ( n12037 , n12035 , n12036 );
xor ( n12038 , n12016 , n12037 );
and ( n12039 , n11995 , n12038 );
xor ( n12040 , n11957 , n12039 );
xor ( n12041 , n11955 , n12040 );
xor ( n12042 , n11814 , n12041 );
buf ( n12043 , n6054 );
xor ( n12044 , n12043 , n7267 );
xor ( n12045 , n12044 , n7289 );
not ( n12046 , n6583 );
buf ( n12047 , n6055 );
and ( n12048 , n12046 , n12047 );
buf ( n12049 , n6056 );
xor ( n12050 , n12049 , n12047 );
and ( n12051 , n12050 , n6583 );
or ( n12052 , n12048 , n12051 );
not ( n12053 , n6583 );
buf ( n12054 , n6057 );
and ( n12055 , n12053 , n12054 );
buf ( n12056 , n6058 );
xor ( n12057 , n12056 , n12054 );
and ( n12058 , n12057 , n6583 );
or ( n12059 , n12055 , n12058 );
xor ( n12060 , n12052 , n12059 );
buf ( n12061 , n6059 );
xor ( n12062 , n12060 , n12061 );
xor ( n12063 , n12062 , n10923 );
buf ( n12064 , n6060 );
xor ( n12065 , n12063 , n12064 );
xor ( n12066 , n7883 , n12065 );
not ( n12067 , n6583 );
buf ( n12068 , n6061 );
and ( n12069 , n12067 , n12068 );
buf ( n12070 , n6062 );
xor ( n12071 , n12070 , n12068 );
and ( n12072 , n12071 , n6583 );
or ( n12073 , n12069 , n12072 );
xor ( n12074 , n12073 , n9119 );
buf ( n12075 , n6063 );
xor ( n12076 , n12074 , n12075 );
buf ( n12077 , n6064 );
xor ( n12078 , n12076 , n12077 );
buf ( n12079 , n6065 );
xor ( n12080 , n12078 , n12079 );
xor ( n12081 , n12066 , n12080 );
not ( n12082 , n12081 );
xor ( n12083 , n10529 , n10893 );
xor ( n12084 , n12083 , n10915 );
and ( n12085 , n12082 , n12084 );
xor ( n12086 , n12045 , n12085 );
xor ( n12087 , n7511 , n9615 );
xor ( n12088 , n12087 , n8584 );
not ( n12089 , n6583 );
buf ( n12090 , n6066 );
and ( n12091 , n12089 , n12090 );
buf ( n12092 , n6067 );
xor ( n12093 , n12092 , n12090 );
and ( n12094 , n12093 , n6583 );
or ( n12095 , n12091 , n12094 );
xor ( n12096 , n6782 , n12095 );
buf ( n12097 , n6068 );
xor ( n12098 , n12096 , n12097 );
buf ( n12099 , n6069 );
xor ( n12100 , n12098 , n12099 );
buf ( n12101 , n6070 );
xor ( n12102 , n12100 , n12101 );
xor ( n12103 , n9043 , n12102 );
not ( n12104 , n6583 );
buf ( n12105 , n6071 );
and ( n12106 , n12104 , n12105 );
buf ( n12107 , n6072 );
xor ( n12108 , n12107 , n12105 );
and ( n12109 , n12108 , n6583 );
or ( n12110 , n12106 , n12109 );
not ( n12111 , n6583 );
buf ( n12112 , n6073 );
and ( n12113 , n12111 , n12112 );
buf ( n12114 , n6074 );
xor ( n12115 , n12114 , n12112 );
and ( n12116 , n12115 , n6583 );
or ( n12117 , n12113 , n12116 );
xor ( n12118 , n12110 , n12117 );
buf ( n12119 , n6075 );
buf ( n12120 , n12119 );
xor ( n12121 , n12118 , n12120 );
buf ( n12122 , n6076 );
xor ( n12123 , n12121 , n12122 );
buf ( n12124 , n6077 );
xor ( n12125 , n12123 , n12124 );
xor ( n12126 , n12103 , n12125 );
not ( n12127 , n12126 );
xor ( n12128 , n7979 , n7828 );
xor ( n12129 , n12128 , n7851 );
and ( n12130 , n12127 , n12129 );
xor ( n12131 , n12088 , n12130 );
xor ( n12132 , n12086 , n12131 );
not ( n12133 , n6583 );
buf ( n12134 , n6078 );
and ( n12135 , n12133 , n12134 );
buf ( n12136 , n6079 );
xor ( n12137 , n12136 , n12134 );
and ( n12138 , n12137 , n6583 );
or ( n12139 , n12135 , n12138 );
not ( n12140 , n6583 );
buf ( n12141 , n6080 );
and ( n12142 , n12140 , n12141 );
buf ( n12143 , n6081 );
xor ( n12144 , n12143 , n12141 );
and ( n12145 , n12144 , n6583 );
or ( n12146 , n12142 , n12145 );
xor ( n12147 , n12139 , n12146 );
xor ( n12148 , n12147 , n7392 );
buf ( n12149 , n6082 );
xor ( n12150 , n12148 , n12149 );
buf ( n12151 , n6083 );
xor ( n12152 , n12150 , n12151 );
xor ( n12153 , n11645 , n12152 );
xor ( n12154 , n11923 , n8252 );
buf ( n12155 , n6084 );
xor ( n12156 , n12154 , n12155 );
buf ( n12157 , n6085 );
xor ( n12158 , n12156 , n12157 );
buf ( n12159 , n6086 );
xor ( n12160 , n12158 , n12159 );
xor ( n12161 , n12153 , n12160 );
xor ( n12162 , n7683 , n6615 );
xor ( n12163 , n12162 , n6636 );
not ( n12164 , n12163 );
xor ( n12165 , n9597 , n7737 );
xor ( n12166 , n12165 , n7759 );
and ( n12167 , n12164 , n12166 );
xor ( n12168 , n12161 , n12167 );
xor ( n12169 , n12132 , n12168 );
xor ( n12170 , n8287 , n10166 );
not ( n12171 , n6583 );
buf ( n12172 , n6087 );
and ( n12173 , n12171 , n12172 );
buf ( n12174 , n6088 );
xor ( n12175 , n12174 , n12172 );
and ( n12176 , n12175 , n6583 );
or ( n12177 , n12173 , n12176 );
not ( n12178 , n6583 );
buf ( n12179 , n6089 );
and ( n12180 , n12178 , n12179 );
buf ( n12181 , n6090 );
xor ( n12182 , n12181 , n12179 );
and ( n12183 , n12182 , n6583 );
or ( n12184 , n12180 , n12183 );
xor ( n12185 , n12177 , n12184 );
buf ( n12186 , n6091 );
xor ( n12187 , n12185 , n12186 );
buf ( n12188 , n6092 );
xor ( n12189 , n12187 , n12188 );
buf ( n12190 , n6093 );
xor ( n12191 , n12189 , n12190 );
xor ( n12192 , n12170 , n12191 );
buf ( n12193 , n6094 );
buf ( n12194 , n12193 );
xor ( n12195 , n12194 , n10552 );
xor ( n12196 , n12195 , n9109 );
not ( n12197 , n12196 );
xor ( n12198 , n11738 , n6727 );
not ( n12199 , n6583 );
buf ( n12200 , n6095 );
and ( n12201 , n12199 , n12200 );
buf ( n12202 , n6096 );
xor ( n12203 , n12202 , n12200 );
and ( n12204 , n12203 , n6583 );
or ( n12205 , n12201 , n12204 );
buf ( n12206 , n6097 );
xor ( n12207 , n12205 , n12206 );
buf ( n12208 , n6098 );
xor ( n12209 , n12207 , n12208 );
buf ( n12210 , n6099 );
xor ( n12211 , n12209 , n12210 );
buf ( n12212 , n6100 );
xor ( n12213 , n12211 , n12212 );
xor ( n12214 , n12198 , n12213 );
and ( n12215 , n12197 , n12214 );
xor ( n12216 , n12192 , n12215 );
xor ( n12217 , n12169 , n12216 );
xor ( n12218 , n11508 , n10120 );
xor ( n12219 , n12218 , n10012 );
buf ( n12220 , n6101 );
not ( n12221 , n6583 );
buf ( n12222 , n6102 );
and ( n12223 , n12221 , n12222 );
buf ( n12224 , n6103 );
xor ( n12225 , n12224 , n12222 );
and ( n12226 , n12225 , n6583 );
or ( n12227 , n12223 , n12226 );
buf ( n12228 , n6104 );
xor ( n12229 , n12227 , n12228 );
xor ( n12230 , n12229 , n9457 );
buf ( n12231 , n6105 );
xor ( n12232 , n12230 , n12231 );
buf ( n12233 , n6106 );
xor ( n12234 , n12232 , n12233 );
xor ( n12235 , n12220 , n12234 );
xor ( n12236 , n12235 , n6896 );
not ( n12237 , n12236 );
xor ( n12238 , n10583 , n7009 );
xor ( n12239 , n12238 , n7452 );
and ( n12240 , n12237 , n12239 );
xor ( n12241 , n12219 , n12240 );
xor ( n12242 , n12217 , n12241 );
xor ( n12243 , n12042 , n12242 );
and ( n12244 , n11792 , n12243 );
xor ( n12245 , n11177 , n12244 );
and ( n12246 , n12245 , n6584 );
or ( n12247 , n10747 , n12246 );
and ( n12248 , n10745 , n12247 );
buf ( n12249 , n12248 );
buf ( n12250 , n12249 );
not ( n12251 , n6578 );
not ( n12252 , n6584 );
buf ( n12253 , n6107 );
and ( n12254 , n12252 , n12253 );
not ( n12255 , n6583 );
buf ( n12256 , n6108 );
and ( n12257 , n12255 , n12256 );
buf ( n12258 , n6109 );
xor ( n12259 , n12258 , n12256 );
and ( n12260 , n12259 , n6583 );
or ( n12261 , n12257 , n12260 );
xor ( n12262 , n12261 , n8482 );
xor ( n12263 , n12262 , n11028 );
not ( n12264 , n6583 );
buf ( n12265 , n6110 );
and ( n12266 , n12264 , n12265 );
buf ( n12267 , n6111 );
xor ( n12268 , n12267 , n12265 );
and ( n12269 , n12268 , n6583 );
or ( n12270 , n12266 , n12269 );
xor ( n12271 , n12270 , n9340 );
not ( n12272 , n6583 );
buf ( n12273 , n6112 );
and ( n12274 , n12272 , n12273 );
buf ( n12275 , n6113 );
xor ( n12276 , n12275 , n12273 );
and ( n12277 , n12276 , n6583 );
or ( n12278 , n12274 , n12277 );
not ( n12279 , n6583 );
buf ( n12280 , n6114 );
and ( n12281 , n12279 , n12280 );
buf ( n12282 , n6115 );
xor ( n12283 , n12282 , n12280 );
and ( n12284 , n12283 , n6583 );
or ( n12285 , n12281 , n12284 );
xor ( n12286 , n12278 , n12285 );
buf ( n12287 , n6116 );
xor ( n12288 , n12286 , n12287 );
buf ( n12289 , n6117 );
xor ( n12290 , n12288 , n12289 );
buf ( n12291 , n6118 );
xor ( n12292 , n12290 , n12291 );
xor ( n12293 , n12271 , n12292 );
not ( n12294 , n12293 );
not ( n12295 , n6583 );
buf ( n12296 , n6119 );
and ( n12297 , n12295 , n12296 );
buf ( n12298 , n6120 );
xor ( n12299 , n12298 , n12296 );
and ( n12300 , n12299 , n6583 );
or ( n12301 , n12297 , n12300 );
xor ( n12302 , n10707 , n12301 );
buf ( n12303 , n6121 );
xor ( n12304 , n12302 , n12303 );
buf ( n12305 , n6122 );
xor ( n12306 , n12304 , n12305 );
buf ( n12307 , n6123 );
xor ( n12308 , n12306 , n12307 );
xor ( n12309 , n10492 , n12308 );
not ( n12310 , n6583 );
buf ( n12311 , n6124 );
and ( n12312 , n12310 , n12311 );
buf ( n12313 , n6125 );
xor ( n12314 , n12313 , n12311 );
and ( n12315 , n12314 , n6583 );
or ( n12316 , n12312 , n12315 );
buf ( n12317 , n6126 );
xor ( n12318 , n12316 , n12317 );
buf ( n12319 , n6127 );
xor ( n12320 , n12318 , n12319 );
buf ( n12321 , n6128 );
xor ( n12322 , n12320 , n12321 );
xor ( n12323 , n12322 , n6731 );
xor ( n12324 , n12309 , n12323 );
and ( n12325 , n12294 , n12324 );
xor ( n12326 , n12263 , n12325 );
not ( n12327 , n6583 );
buf ( n12328 , n6129 );
and ( n12329 , n12327 , n12328 );
buf ( n12330 , n6130 );
xor ( n12331 , n12330 , n12328 );
and ( n12332 , n12331 , n6583 );
or ( n12333 , n12329 , n12332 );
not ( n12334 , n6583 );
buf ( n12335 , n6131 );
and ( n12336 , n12334 , n12335 );
buf ( n12337 , n6132 );
xor ( n12338 , n12337 , n12335 );
and ( n12339 , n12338 , n6583 );
or ( n12340 , n12336 , n12339 );
xor ( n12341 , n12333 , n12340 );
buf ( n12342 , n6133 );
xor ( n12343 , n12341 , n12342 );
buf ( n12344 , n6134 );
xor ( n12345 , n12343 , n12344 );
buf ( n12346 , n6135 );
xor ( n12347 , n12345 , n12346 );
xor ( n12348 , n8035 , n12347 );
xor ( n12349 , n12348 , n9639 );
not ( n12350 , n6583 );
buf ( n12351 , n6136 );
and ( n12352 , n12350 , n12351 );
buf ( n12353 , n6137 );
xor ( n12354 , n12353 , n12351 );
and ( n12355 , n12354 , n6583 );
or ( n12356 , n12352 , n12355 );
xor ( n12357 , n12356 , n8766 );
not ( n12358 , n6583 );
buf ( n12359 , n6138 );
and ( n12360 , n12358 , n12359 );
buf ( n12361 , n6139 );
xor ( n12362 , n12361 , n12359 );
and ( n12363 , n12362 , n6583 );
or ( n12364 , n12360 , n12363 );
xor ( n12365 , n12261 , n12364 );
buf ( n12366 , n6140 );
xor ( n12367 , n12365 , n12366 );
buf ( n12368 , n6141 );
xor ( n12369 , n12367 , n12368 );
buf ( n12370 , n6142 );
xor ( n12371 , n12369 , n12370 );
xor ( n12372 , n12357 , n12371 );
not ( n12373 , n12372 );
not ( n12374 , n6583 );
buf ( n12375 , n6143 );
and ( n12376 , n12374 , n12375 );
buf ( n12377 , n6144 );
xor ( n12378 , n12377 , n12375 );
and ( n12379 , n12378 , n6583 );
or ( n12380 , n12376 , n12379 );
not ( n12381 , n6583 );
buf ( n12382 , n6145 );
and ( n12383 , n12381 , n12382 );
buf ( n12384 , n6146 );
xor ( n12385 , n12384 , n12382 );
and ( n12386 , n12385 , n6583 );
or ( n12387 , n12383 , n12386 );
xor ( n12388 , n12380 , n12387 );
buf ( n12389 , n6147 );
xor ( n12390 , n12388 , n12389 );
buf ( n12391 , n6148 );
xor ( n12392 , n12390 , n12391 );
xor ( n12393 , n12392 , n10245 );
xor ( n12394 , n11093 , n12393 );
not ( n12395 , n6583 );
buf ( n12396 , n6149 );
and ( n12397 , n12395 , n12396 );
buf ( n12398 , n6150 );
xor ( n12399 , n12398 , n12396 );
and ( n12400 , n12399 , n6583 );
or ( n12401 , n12397 , n12400 );
xor ( n12402 , n11184 , n12401 );
buf ( n12403 , n6151 );
xor ( n12404 , n12402 , n12403 );
buf ( n12405 , n6152 );
xor ( n12406 , n12404 , n12405 );
buf ( n12407 , n6153 );
xor ( n12408 , n12406 , n12407 );
xor ( n12409 , n12394 , n12408 );
and ( n12410 , n12373 , n12409 );
xor ( n12411 , n12349 , n12410 );
buf ( n12412 , n6154 );
not ( n12413 , n6583 );
buf ( n12414 , n6155 );
and ( n12415 , n12413 , n12414 );
buf ( n12416 , n6156 );
xor ( n12417 , n12416 , n12414 );
and ( n12418 , n12417 , n6583 );
or ( n12419 , n12415 , n12418 );
not ( n12420 , n6583 );
buf ( n12421 , n6157 );
and ( n12422 , n12420 , n12421 );
buf ( n12423 , n6158 );
xor ( n12424 , n12423 , n12421 );
and ( n12425 , n12424 , n6583 );
or ( n12426 , n12422 , n12425 );
xor ( n12427 , n12419 , n12426 );
buf ( n12428 , n6159 );
xor ( n12429 , n12427 , n12428 );
buf ( n12430 , n6160 );
xor ( n12431 , n12429 , n12430 );
buf ( n12432 , n6161 );
xor ( n12433 , n12431 , n12432 );
xor ( n12434 , n12412 , n12433 );
not ( n12435 , n6583 );
buf ( n12436 , n6162 );
and ( n12437 , n12435 , n12436 );
buf ( n12438 , n6163 );
xor ( n12439 , n12438 , n12436 );
and ( n12440 , n12439 , n6583 );
or ( n12441 , n12437 , n12440 );
xor ( n12442 , n9672 , n12441 );
xor ( n12443 , n12442 , n8391 );
buf ( n12444 , n6164 );
xor ( n12445 , n12443 , n12444 );
buf ( n12446 , n6165 );
xor ( n12447 , n12445 , n12446 );
xor ( n12448 , n12434 , n12447 );
xor ( n12449 , n11467 , n7980 );
xor ( n12450 , n12449 , n7996 );
not ( n12451 , n12450 );
xor ( n12452 , n10612 , n7654 );
not ( n12453 , n6583 );
buf ( n12454 , n6166 );
and ( n12455 , n12453 , n12454 );
buf ( n12456 , n6167 );
xor ( n12457 , n12456 , n12454 );
and ( n12458 , n12457 , n6583 );
or ( n12459 , n12455 , n12458 );
not ( n12460 , n6583 );
buf ( n12461 , n6168 );
and ( n12462 , n12460 , n12461 );
buf ( n12463 , n6169 );
xor ( n12464 , n12463 , n12461 );
and ( n12465 , n12464 , n6583 );
or ( n12466 , n12462 , n12465 );
xor ( n12467 , n12459 , n12466 );
buf ( n12468 , n6170 );
xor ( n12469 , n12467 , n12468 );
buf ( n12470 , n6171 );
xor ( n12471 , n12469 , n12470 );
buf ( n12472 , n6172 );
xor ( n12473 , n12471 , n12472 );
xor ( n12474 , n12452 , n12473 );
and ( n12475 , n12451 , n12474 );
xor ( n12476 , n12448 , n12475 );
xor ( n12477 , n12411 , n12476 );
not ( n12478 , n6583 );
buf ( n12479 , n6173 );
and ( n12480 , n12478 , n12479 );
buf ( n12481 , n6174 );
xor ( n12482 , n12481 , n12479 );
and ( n12483 , n12482 , n6583 );
or ( n12484 , n12480 , n12483 );
buf ( n12485 , n6175 );
xor ( n12486 , n12484 , n12485 );
buf ( n12487 , n6176 );
xor ( n12488 , n12486 , n12487 );
buf ( n12489 , n6177 );
xor ( n12490 , n12488 , n12489 );
buf ( n12491 , n6178 );
xor ( n12492 , n12490 , n12491 );
xor ( n12493 , n10821 , n12492 );
xor ( n12494 , n12493 , n7632 );
not ( n12495 , n12263 );
and ( n12496 , n12495 , n12293 );
xor ( n12497 , n12494 , n12496 );
xor ( n12498 , n12477 , n12497 );
xor ( n12499 , n11649 , n12152 );
xor ( n12500 , n12499 , n12160 );
not ( n12501 , n6583 );
buf ( n12502 , n6179 );
and ( n12503 , n12501 , n12502 );
buf ( n12504 , n6180 );
xor ( n12505 , n12504 , n12502 );
and ( n12506 , n12505 , n6583 );
or ( n12507 , n12503 , n12506 );
not ( n12508 , n6583 );
buf ( n12509 , n6181 );
and ( n12510 , n12508 , n12509 );
buf ( n12511 , n6182 );
xor ( n12512 , n12511 , n12509 );
and ( n12513 , n12512 , n6583 );
or ( n12514 , n12510 , n12513 );
xor ( n12515 , n12507 , n12514 );
buf ( n12516 , n6183 );
xor ( n12517 , n12515 , n12516 );
buf ( n12518 , n6184 );
xor ( n12519 , n12517 , n12518 );
buf ( n12520 , n6185 );
xor ( n12521 , n12519 , n12520 );
xor ( n12522 , n9817 , n12521 );
xor ( n12523 , n12522 , n10411 );
not ( n12524 , n12523 );
xor ( n12525 , n9914 , n9178 );
xor ( n12526 , n12525 , n9200 );
and ( n12527 , n12524 , n12526 );
xor ( n12528 , n12500 , n12527 );
xor ( n12529 , n12498 , n12528 );
xor ( n12530 , n11346 , n10349 );
xor ( n12531 , n12530 , n7319 );
not ( n12532 , n6583 );
buf ( n12533 , n6186 );
and ( n12534 , n12532 , n12533 );
buf ( n12535 , n6187 );
xor ( n12536 , n12535 , n12533 );
and ( n12537 , n12536 , n6583 );
or ( n12538 , n12534 , n12537 );
not ( n12539 , n6583 );
buf ( n12540 , n6188 );
and ( n12541 , n12539 , n12540 );
buf ( n12542 , n6189 );
xor ( n12543 , n12542 , n12540 );
and ( n12544 , n12543 , n6583 );
or ( n12545 , n12541 , n12544 );
xor ( n12546 , n12538 , n12545 );
buf ( n12547 , n6190 );
xor ( n12548 , n12546 , n12547 );
buf ( n12549 , n6191 );
xor ( n12550 , n12548 , n12549 );
buf ( n12551 , n6192 );
xor ( n12552 , n12550 , n12551 );
xor ( n12553 , n8398 , n12552 );
not ( n12554 , n6583 );
buf ( n12555 , n6193 );
and ( n12556 , n12554 , n12555 );
buf ( n12557 , n6194 );
xor ( n12558 , n12557 , n12555 );
and ( n12559 , n12558 , n6583 );
or ( n12560 , n12556 , n12559 );
not ( n12561 , n6583 );
buf ( n12562 , n6195 );
and ( n12563 , n12561 , n12562 );
buf ( n12564 , n6196 );
xor ( n12565 , n12564 , n12562 );
and ( n12566 , n12565 , n6583 );
or ( n12567 , n12563 , n12566 );
xor ( n12568 , n12560 , n12567 );
xor ( n12569 , n12568 , n8736 );
buf ( n12570 , n6197 );
xor ( n12571 , n12569 , n12570 );
buf ( n12572 , n6198 );
xor ( n12573 , n12571 , n12572 );
xor ( n12574 , n12553 , n12573 );
not ( n12575 , n12574 );
xor ( n12576 , n11598 , n9560 );
xor ( n12577 , n12576 , n8807 );
and ( n12578 , n12575 , n12577 );
xor ( n12579 , n12531 , n12578 );
xor ( n12580 , n12529 , n12579 );
xor ( n12581 , n12326 , n12580 );
not ( n12582 , n6583 );
buf ( n12583 , n6199 );
and ( n12584 , n12582 , n12583 );
buf ( n12585 , n6200 );
xor ( n12586 , n12585 , n12583 );
and ( n12587 , n12586 , n6583 );
or ( n12588 , n12584 , n12587 );
not ( n12589 , n6583 );
buf ( n12590 , n6201 );
and ( n12591 , n12589 , n12590 );
buf ( n12592 , n6202 );
xor ( n12593 , n12592 , n12590 );
and ( n12594 , n12593 , n6583 );
or ( n12595 , n12591 , n12594 );
xor ( n12596 , n12588 , n12595 );
buf ( n12597 , n6203 );
xor ( n12598 , n12596 , n12597 );
buf ( n12599 , n6204 );
xor ( n12600 , n12598 , n12599 );
xor ( n12601 , n12600 , n10515 );
xor ( n12602 , n10275 , n12601 );
not ( n12603 , n6583 );
buf ( n12604 , n6205 );
and ( n12605 , n12603 , n12604 );
buf ( n12606 , n6206 );
xor ( n12607 , n12606 , n12604 );
and ( n12608 , n12607 , n6583 );
or ( n12609 , n12605 , n12608 );
not ( n12610 , n6583 );
buf ( n12611 , n6207 );
and ( n12612 , n12610 , n12611 );
buf ( n12613 , n6208 );
xor ( n12614 , n12613 , n12611 );
and ( n12615 , n12614 , n6583 );
or ( n12616 , n12612 , n12615 );
xor ( n12617 , n12609 , n12616 );
buf ( n12618 , n6209 );
xor ( n12619 , n12617 , n12618 );
xor ( n12620 , n12619 , n12194 );
buf ( n12621 , n6210 );
xor ( n12622 , n12620 , n12621 );
xor ( n12623 , n12602 , n12622 );
xor ( n12624 , n9379 , n11100 );
xor ( n12625 , n12624 , n10893 );
not ( n12626 , n12625 );
not ( n12627 , n6583 );
buf ( n12628 , n6211 );
and ( n12629 , n12627 , n12628 );
buf ( n12630 , n6212 );
xor ( n12631 , n12630 , n12628 );
and ( n12632 , n12631 , n6583 );
or ( n12633 , n12629 , n12632 );
not ( n12634 , n6583 );
buf ( n12635 , n6213 );
and ( n12636 , n12634 , n12635 );
buf ( n12637 , n6214 );
xor ( n12638 , n12637 , n12635 );
and ( n12639 , n12638 , n6583 );
or ( n12640 , n12636 , n12639 );
xor ( n12641 , n12633 , n12640 );
buf ( n12642 , n6215 );
xor ( n12643 , n12641 , n12642 );
buf ( n12644 , n6216 );
xor ( n12645 , n12643 , n12644 );
buf ( n12646 , n6217 );
xor ( n12647 , n12645 , n12646 );
xor ( n12648 , n11215 , n12647 );
not ( n12649 , n6583 );
buf ( n12650 , n6218 );
and ( n12651 , n12649 , n12650 );
buf ( n12652 , n6219 );
xor ( n12653 , n12652 , n12650 );
and ( n12654 , n12653 , n6583 );
or ( n12655 , n12651 , n12654 );
buf ( n12656 , n6220 );
xor ( n12657 , n12655 , n12656 );
xor ( n12658 , n12657 , n11718 );
buf ( n12659 , n6221 );
xor ( n12660 , n12658 , n12659 );
buf ( n12661 , n6222 );
xor ( n12662 , n12660 , n12661 );
xor ( n12663 , n12648 , n12662 );
and ( n12664 , n12626 , n12663 );
xor ( n12665 , n12623 , n12664 );
buf ( n12666 , n6223 );
xor ( n12667 , n12666 , n7710 );
xor ( n12668 , n12667 , n6705 );
xor ( n12669 , n11309 , n7335 );
xor ( n12670 , n12669 , n10098 );
not ( n12671 , n12670 );
xor ( n12672 , n10549 , n10915 );
xor ( n12673 , n12672 , n10142 );
and ( n12674 , n12671 , n12673 );
xor ( n12675 , n12668 , n12674 );
xor ( n12676 , n12665 , n12675 );
not ( n12677 , n6583 );
buf ( n12678 , n6224 );
and ( n12679 , n12677 , n12678 );
buf ( n12680 , n6225 );
xor ( n12681 , n12680 , n12678 );
and ( n12682 , n12681 , n6583 );
or ( n12683 , n12679 , n12682 );
not ( n12684 , n6583 );
buf ( n12685 , n6226 );
and ( n12686 , n12684 , n12685 );
buf ( n12687 , n6227 );
xor ( n12688 , n12687 , n12685 );
and ( n12689 , n12688 , n6583 );
or ( n12690 , n12686 , n12689 );
xor ( n12691 , n12690 , n10450 );
buf ( n12692 , n6228 );
xor ( n12693 , n12691 , n12692 );
xor ( n12694 , n12693 , n9991 );
buf ( n12695 , n6229 );
xor ( n12696 , n12694 , n12695 );
xor ( n12697 , n12683 , n12696 );
xor ( n12698 , n12697 , n9478 );
xor ( n12699 , n6747 , n9809 );
xor ( n12700 , n12699 , n9825 );
not ( n12701 , n12700 );
not ( n12702 , n6583 );
buf ( n12703 , n6230 );
and ( n12704 , n12702 , n12703 );
buf ( n12705 , n6231 );
xor ( n12706 , n12705 , n12703 );
and ( n12707 , n12706 , n6583 );
or ( n12708 , n12704 , n12707 );
not ( n12709 , n6583 );
buf ( n12710 , n6232 );
and ( n12711 , n12709 , n12710 );
buf ( n12712 , n6233 );
xor ( n12713 , n12712 , n12710 );
and ( n12714 , n12713 , n6583 );
or ( n12715 , n12711 , n12714 );
xor ( n12716 , n12708 , n12715 );
xor ( n12717 , n12716 , n11606 );
buf ( n12718 , n6234 );
xor ( n12719 , n12717 , n12718 );
buf ( n12720 , n6235 );
xor ( n12721 , n12719 , n12720 );
xor ( n12722 , n8502 , n12721 );
xor ( n12723 , n12722 , n11805 );
and ( n12724 , n12701 , n12723 );
xor ( n12725 , n12698 , n12724 );
xor ( n12726 , n12676 , n12725 );
not ( n12727 , n6583 );
buf ( n12728 , n6236 );
and ( n12729 , n12727 , n12728 );
buf ( n12730 , n6237 );
xor ( n12731 , n12730 , n12728 );
and ( n12732 , n12731 , n6583 );
or ( n12733 , n12729 , n12732 );
xor ( n12734 , n12733 , n8083 );
xor ( n12735 , n12734 , n8105 );
xor ( n12736 , n9528 , n11386 );
not ( n12737 , n6583 );
buf ( n12738 , n6238 );
and ( n12739 , n12737 , n12738 );
buf ( n12740 , n6239 );
xor ( n12741 , n12740 , n12738 );
and ( n12742 , n12741 , n6583 );
or ( n12743 , n12739 , n12742 );
not ( n12744 , n6583 );
buf ( n12745 , n6240 );
and ( n12746 , n12744 , n12745 );
buf ( n12747 , n6241 );
xor ( n12748 , n12747 , n12745 );
and ( n12749 , n12748 , n6583 );
or ( n12750 , n12746 , n12749 );
xor ( n12751 , n12743 , n12750 );
xor ( n12752 , n12751 , n9025 );
buf ( n12753 , n6242 );
xor ( n12754 , n12752 , n12753 );
buf ( n12755 , n6243 );
xor ( n12756 , n12754 , n12755 );
xor ( n12757 , n12736 , n12756 );
not ( n12758 , n12757 );
xor ( n12759 , n9657 , n8167 );
xor ( n12760 , n12759 , n8189 );
and ( n12761 , n12758 , n12760 );
xor ( n12762 , n12735 , n12761 );
xor ( n12763 , n12726 , n12762 );
xor ( n12764 , n11643 , n12152 );
xor ( n12765 , n12764 , n12160 );
xor ( n12766 , n8265 , n9244 );
xor ( n12767 , n12766 , n10166 );
not ( n12768 , n12767 );
not ( n12769 , n6583 );
buf ( n12770 , n6244 );
and ( n12771 , n12769 , n12770 );
buf ( n12772 , n6245 );
xor ( n12773 , n12772 , n12770 );
and ( n12774 , n12773 , n6583 );
or ( n12775 , n12771 , n12774 );
buf ( n12776 , n6246 );
xor ( n12777 , n12775 , n12776 );
buf ( n12778 , n6247 );
xor ( n12779 , n12777 , n12778 );
xor ( n12780 , n12779 , n9678 );
buf ( n12781 , n6248 );
xor ( n12782 , n12780 , n12781 );
xor ( n12783 , n9304 , n12782 );
xor ( n12784 , n12783 , n8369 );
and ( n12785 , n12768 , n12784 );
xor ( n12786 , n12765 , n12785 );
xor ( n12787 , n12763 , n12786 );
xor ( n12788 , n12581 , n12787 );
xor ( n12789 , n7209 , n8036 );
xor ( n12790 , n12789 , n8058 );
xor ( n12791 , n10939 , n10797 );
not ( n12792 , n6583 );
buf ( n12793 , n6249 );
and ( n12794 , n12792 , n12793 );
buf ( n12795 , n6250 );
xor ( n12796 , n12795 , n12793 );
and ( n12797 , n12796 , n6583 );
or ( n12798 , n12794 , n12797 );
xor ( n12799 , n12798 , n11358 );
buf ( n12800 , n6251 );
xor ( n12801 , n12799 , n12800 );
xor ( n12802 , n12801 , n8865 );
buf ( n12803 , n6252 );
xor ( n12804 , n12802 , n12803 );
xor ( n12805 , n12791 , n12804 );
not ( n12806 , n12805 );
xor ( n12807 , n6868 , n8822 );
xor ( n12808 , n12807 , n11050 );
and ( n12809 , n12806 , n12808 );
xor ( n12810 , n12790 , n12809 );
xor ( n12811 , n9293 , n12782 );
xor ( n12812 , n12811 , n8369 );
not ( n12813 , n6583 );
buf ( n12814 , n6253 );
and ( n12815 , n12813 , n12814 );
buf ( n12816 , n6254 );
xor ( n12817 , n12816 , n12814 );
and ( n12818 , n12817 , n6583 );
or ( n12819 , n12815 , n12818 );
xor ( n12820 , n12819 , n6705 );
xor ( n12821 , n12820 , n6727 );
not ( n12822 , n12821 );
xor ( n12823 , n11973 , n11684 );
xor ( n12824 , n12823 , n11218 );
and ( n12825 , n12822 , n12824 );
xor ( n12826 , n12812 , n12825 );
not ( n12827 , n6583 );
buf ( n12828 , n6255 );
and ( n12829 , n12827 , n12828 );
buf ( n12830 , n6256 );
xor ( n12831 , n12830 , n12828 );
and ( n12832 , n12831 , n6583 );
or ( n12833 , n12829 , n12832 );
xor ( n12834 , n12833 , n12270 );
buf ( n12835 , n6257 );
xor ( n12836 , n12834 , n12835 );
buf ( n12837 , n6258 );
xor ( n12838 , n12836 , n12837 );
buf ( n12839 , n6259 );
xor ( n12840 , n12838 , n12839 );
xor ( n12841 , n10106 , n12840 );
not ( n12842 , n6583 );
buf ( n12843 , n6260 );
and ( n12844 , n12842 , n12843 );
buf ( n12845 , n6261 );
xor ( n12846 , n12845 , n12843 );
and ( n12847 , n12846 , n6583 );
or ( n12848 , n12844 , n12847 );
buf ( n12849 , n6262 );
xor ( n12850 , n12848 , n12849 );
buf ( n12851 , n6263 );
xor ( n12852 , n12850 , n12851 );
buf ( n12853 , n6264 );
xor ( n12854 , n12852 , n12853 );
buf ( n12855 , n6265 );
xor ( n12856 , n12854 , n12855 );
xor ( n12857 , n12841 , n12856 );
buf ( n12858 , n6266 );
xor ( n12859 , n12858 , n12447 );
not ( n12860 , n6583 );
buf ( n12861 , n6267 );
and ( n12862 , n12860 , n12861 );
buf ( n12863 , n6268 );
xor ( n12864 , n12863 , n12861 );
and ( n12865 , n12864 , n6583 );
or ( n12866 , n12862 , n12865 );
xor ( n12867 , n12866 , n10651 );
buf ( n12868 , n6269 );
xor ( n12869 , n12867 , n12868 );
buf ( n12870 , n6270 );
xor ( n12871 , n12869 , n12870 );
buf ( n12872 , n6271 );
xor ( n12873 , n12871 , n12872 );
xor ( n12874 , n12859 , n12873 );
not ( n12875 , n12874 );
xor ( n12876 , n12597 , n10530 );
xor ( n12877 , n12876 , n10552 );
and ( n12878 , n12875 , n12877 );
xor ( n12879 , n12857 , n12878 );
xor ( n12880 , n12826 , n12879 );
xor ( n12881 , n8355 , n9362 );
xor ( n12882 , n12881 , n9384 );
xor ( n12883 , n8545 , n9406 );
xor ( n12884 , n12883 , n9428 );
not ( n12885 , n12884 );
xor ( n12886 , n11287 , n7319 );
xor ( n12887 , n12886 , n7335 );
and ( n12888 , n12885 , n12887 );
xor ( n12889 , n12882 , n12888 );
xor ( n12890 , n12880 , n12889 );
xor ( n12891 , n7181 , n12015 );
xor ( n12892 , n12891 , n12037 );
not ( n12893 , n12790 );
and ( n12894 , n12893 , n12805 );
xor ( n12895 , n12892 , n12894 );
xor ( n12896 , n12890 , n12895 );
not ( n12897 , n6583 );
buf ( n12898 , n6272 );
and ( n12899 , n12897 , n12898 );
buf ( n12900 , n6273 );
xor ( n12901 , n12900 , n12898 );
and ( n12902 , n12901 , n6583 );
or ( n12903 , n12899 , n12902 );
not ( n12904 , n6583 );
buf ( n12905 , n6274 );
and ( n12906 , n12904 , n12905 );
buf ( n12907 , n6275 );
xor ( n12908 , n12907 , n12905 );
and ( n12909 , n12908 , n6583 );
or ( n12910 , n12906 , n12909 );
xor ( n12911 , n12903 , n12910 );
xor ( n12912 , n12911 , n11950 );
buf ( n12913 , n6276 );
xor ( n12914 , n12912 , n12913 );
xor ( n12915 , n12914 , n8996 );
xor ( n12916 , n6933 , n12915 );
xor ( n12917 , n12916 , n9285 );
not ( n12918 , n6583 );
buf ( n12919 , n6277 );
and ( n12920 , n12918 , n12919 );
buf ( n12921 , n6278 );
xor ( n12922 , n12921 , n12919 );
and ( n12923 , n12922 , n6583 );
or ( n12924 , n12920 , n12923 );
xor ( n12925 , n12924 , n10563 );
buf ( n12926 , n6279 );
xor ( n12927 , n12925 , n12926 );
buf ( n12928 , n6280 );
xor ( n12929 , n12927 , n12928 );
buf ( n12930 , n6281 );
xor ( n12931 , n12929 , n12930 );
xor ( n12932 , n7487 , n12931 );
xor ( n12933 , n12932 , n9615 );
not ( n12934 , n12933 );
buf ( n12935 , n6282 );
xor ( n12936 , n12935 , n8189 );
xor ( n12937 , n12936 , n10822 );
and ( n12938 , n12934 , n12937 );
xor ( n12939 , n12917 , n12938 );
xor ( n12940 , n12896 , n12939 );
xor ( n12941 , n12810 , n12940 );
not ( n12942 , n6583 );
buf ( n12943 , n6283 );
and ( n12944 , n12942 , n12943 );
buf ( n12945 , n6284 );
xor ( n12946 , n12945 , n12943 );
and ( n12947 , n12946 , n6583 );
or ( n12948 , n12944 , n12947 );
xor ( n12949 , n12948 , n12819 );
xor ( n12950 , n12949 , n6684 );
buf ( n12951 , n6285 );
xor ( n12952 , n12950 , n12951 );
buf ( n12953 , n6286 );
xor ( n12954 , n12952 , n12953 );
xor ( n12955 , n12642 , n12954 );
xor ( n12956 , n12955 , n11739 );
not ( n12957 , n6583 );
buf ( n12958 , n6287 );
and ( n12959 , n12957 , n12958 );
buf ( n12960 , n6288 );
xor ( n12961 , n12960 , n12958 );
and ( n12962 , n12961 , n6583 );
or ( n12963 , n12959 , n12962 );
not ( n12964 , n6583 );
buf ( n12965 , n6289 );
and ( n12966 , n12964 , n12965 );
buf ( n12967 , n6290 );
xor ( n12968 , n12967 , n12965 );
and ( n12969 , n12968 , n6583 );
or ( n12970 , n12966 , n12969 );
xor ( n12971 , n12963 , n12970 );
buf ( n12972 , n6291 );
xor ( n12973 , n12971 , n12972 );
buf ( n12974 , n6292 );
buf ( n12975 , n12974 );
xor ( n12976 , n12973 , n12975 );
buf ( n12977 , n6293 );
xor ( n12978 , n12976 , n12977 );
xor ( n12979 , n8457 , n12978 );
xor ( n12980 , n12979 , n11325 );
not ( n12981 , n12980 );
xor ( n12982 , n12159 , n7428 );
xor ( n12983 , n12982 , n7579 );
and ( n12984 , n12981 , n12983 );
xor ( n12985 , n12956 , n12984 );
not ( n12986 , n6583 );
buf ( n12987 , n6294 );
and ( n12988 , n12986 , n12987 );
buf ( n12989 , n6295 );
xor ( n12990 , n12989 , n12987 );
and ( n12991 , n12990 , n6583 );
or ( n12992 , n12988 , n12991 );
buf ( n12993 , n6296 );
xor ( n12994 , n12992 , n12993 );
buf ( n12995 , n6297 );
xor ( n12996 , n12994 , n12995 );
xor ( n12997 , n12996 , n8768 );
buf ( n12998 , n6298 );
xor ( n12999 , n12997 , n12998 );
xor ( n13000 , n10910 , n12999 );
not ( n13001 , n6583 );
buf ( n13002 , n6299 );
and ( n13003 , n13001 , n13002 );
buf ( n13004 , n6300 );
xor ( n13005 , n13004 , n13002 );
and ( n13006 , n13005 , n6583 );
or ( n13007 , n13003 , n13006 );
not ( n13008 , n6583 );
buf ( n13009 , n6301 );
and ( n13010 , n13008 , n13009 );
buf ( n13011 , n6302 );
xor ( n13012 , n13011 , n13009 );
and ( n13013 , n13012 , n6583 );
or ( n13014 , n13010 , n13013 );
xor ( n13015 , n13007 , n13014 );
xor ( n13016 , n13015 , n8509 );
buf ( n13017 , n6303 );
xor ( n13018 , n13016 , n13017 );
buf ( n13019 , n6304 );
xor ( n13020 , n13018 , n13019 );
xor ( n13021 , n13000 , n13020 );
xor ( n13022 , n10472 , n11761 );
xor ( n13023 , n13022 , n12308 );
not ( n13024 , n13023 );
xor ( n13025 , n6946 , n12915 );
xor ( n13026 , n13025 , n9285 );
and ( n13027 , n13024 , n13026 );
xor ( n13028 , n13021 , n13027 );
xor ( n13029 , n12985 , n13028 );
xor ( n13030 , n11525 , n7173 );
xor ( n13031 , n13030 , n7189 );
xor ( n13032 , n11558 , n10776 );
xor ( n13033 , n13032 , n10797 );
not ( n13034 , n13033 );
buf ( n13035 , n6305 );
buf ( n13036 , n6306 );
xor ( n13037 , n9834 , n13036 );
buf ( n13038 , n6307 );
xor ( n13039 , n13037 , n13038 );
buf ( n13040 , n6308 );
xor ( n13041 , n13039 , n13040 );
xor ( n13042 , n13041 , n11223 );
xor ( n13043 , n13035 , n13042 );
xor ( n13044 , n13043 , n12552 );
and ( n13045 , n13034 , n13044 );
xor ( n13046 , n13031 , n13045 );
xor ( n13047 , n13029 , n13046 );
xor ( n13048 , n8881 , n7908 );
xor ( n13049 , n13048 , n9069 );
not ( n13050 , n6583 );
buf ( n13051 , n6309 );
and ( n13052 , n13050 , n13051 );
buf ( n13053 , n6310 );
xor ( n13054 , n13053 , n13051 );
and ( n13055 , n13054 , n6583 );
or ( n13056 , n13052 , n13055 );
not ( n13057 , n6583 );
buf ( n13058 , n6311 );
and ( n13059 , n13057 , n13058 );
buf ( n13060 , n6312 );
xor ( n13061 , n13060 , n13058 );
and ( n13062 , n13061 , n6583 );
or ( n13063 , n13059 , n13062 );
xor ( n13064 , n13056 , n13063 );
xor ( n13065 , n13064 , n11686 );
xor ( n13066 , n13065 , n7558 );
buf ( n13067 , n6313 );
xor ( n13068 , n13066 , n13067 );
xor ( n13069 , n7387 , n13068 );
not ( n13070 , n6583 );
buf ( n13071 , n6314 );
and ( n13072 , n13070 , n13071 );
buf ( n13073 , n6315 );
xor ( n13074 , n13073 , n13071 );
and ( n13075 , n13074 , n6583 );
or ( n13076 , n13072 , n13075 );
not ( n13077 , n6583 );
buf ( n13078 , n6316 );
and ( n13079 , n13077 , n13078 );
buf ( n13080 , n6317 );
xor ( n13081 , n13080 , n13078 );
and ( n13082 , n13081 , n6583 );
or ( n13083 , n13079 , n13082 );
xor ( n13084 , n13076 , n13083 );
buf ( n13085 , n6318 );
xor ( n13086 , n13084 , n13085 );
xor ( n13087 , n13086 , n8637 );
buf ( n13088 , n6319 );
xor ( n13089 , n13087 , n13088 );
xor ( n13090 , n13069 , n13089 );
not ( n13091 , n13090 );
not ( n13092 , n6583 );
buf ( n13093 , n6320 );
and ( n13094 , n13092 , n13093 );
buf ( n13095 , n6321 );
xor ( n13096 , n13095 , n13093 );
and ( n13097 , n13096 , n6583 );
or ( n13098 , n13094 , n13097 );
xor ( n13099 , n8563 , n13098 );
buf ( n13100 , n6322 );
xor ( n13101 , n13099 , n13100 );
buf ( n13102 , n6323 );
xor ( n13103 , n13101 , n13102 );
xor ( n13104 , n13103 , n8730 );
xor ( n13105 , n10866 , n13104 );
xor ( n13106 , n13105 , n9178 );
and ( n13107 , n13091 , n13106 );
xor ( n13108 , n13049 , n13107 );
xor ( n13109 , n13047 , n13108 );
xor ( n13110 , n12487 , n8635 );
xor ( n13111 , n13110 , n8705 );
buf ( n13112 , n6324 );
xor ( n13113 , n13112 , n10619 );
xor ( n13114 , n13113 , n11684 );
not ( n13115 , n13114 );
xor ( n13116 , n10281 , n12601 );
xor ( n13117 , n13116 , n12622 );
and ( n13118 , n13115 , n13117 );
xor ( n13119 , n13111 , n13118 );
xor ( n13120 , n13109 , n13119 );
xor ( n13121 , n12941 , n13120 );
not ( n13122 , n13121 );
xor ( n13123 , n11861 , n7494 );
xor ( n13124 , n13123 , n7516 );
xor ( n13125 , n9736 , n7469 );
xor ( n13126 , n13125 , n11147 );
not ( n13127 , n13126 );
buf ( n13128 , n6325 );
not ( n13129 , n6583 );
buf ( n13130 , n6326 );
and ( n13131 , n13129 , n13130 );
buf ( n13132 , n6327 );
xor ( n13133 , n13132 , n13130 );
and ( n13134 , n13133 , n6583 );
or ( n13135 , n13131 , n13134 );
not ( n13136 , n6583 );
buf ( n13137 , n6328 );
and ( n13138 , n13136 , n13137 );
buf ( n13139 , n6329 );
xor ( n13140 , n13139 , n13137 );
and ( n13141 , n13140 , n6583 );
or ( n13142 , n13138 , n13141 );
xor ( n13143 , n13135 , n13142 );
buf ( n13144 , n6330 );
xor ( n13145 , n13143 , n13144 );
buf ( n13146 , n6331 );
xor ( n13147 , n13145 , n13146 );
buf ( n13148 , n6332 );
xor ( n13149 , n13147 , n13148 );
xor ( n13150 , n13128 , n13149 );
not ( n13151 , n6583 );
buf ( n13152 , n6333 );
and ( n13153 , n13151 , n13152 );
buf ( n13154 , n6334 );
xor ( n13155 , n13154 , n13152 );
and ( n13156 , n13155 , n6583 );
or ( n13157 , n13153 , n13156 );
not ( n13158 , n6583 );
and ( n13159 , n13158 , n12253 );
buf ( n13160 , n6335 );
xor ( n13161 , n13160 , n12253 );
and ( n13162 , n13161 , n6583 );
or ( n13163 , n13159 , n13162 );
xor ( n13164 , n13157 , n13163 );
buf ( n13165 , n6336 );
xor ( n13166 , n13164 , n13165 );
buf ( n13167 , n6337 );
xor ( n13168 , n13166 , n13167 );
xor ( n13169 , n13168 , n12412 );
xor ( n13170 , n13150 , n13169 );
and ( n13171 , n13127 , n13170 );
xor ( n13172 , n13124 , n13171 );
xor ( n13173 , n8098 , n8318 );
xor ( n13174 , n13173 , n8340 );
xor ( n13175 , n9937 , n9200 );
not ( n13176 , n6583 );
buf ( n13177 , n6338 );
and ( n13178 , n13176 , n13177 );
buf ( n13179 , n6339 );
xor ( n13180 , n13179 , n13177 );
and ( n13181 , n13180 , n6583 );
or ( n13182 , n13178 , n13181 );
xor ( n13183 , n13182 , n11193 );
xor ( n13184 , n13183 , n7656 );
buf ( n13185 , n6340 );
xor ( n13186 , n13184 , n13185 );
buf ( n13187 , n6341 );
xor ( n13188 , n13186 , n13187 );
xor ( n13189 , n13175 , n13188 );
not ( n13190 , n13189 );
buf ( n13191 , n6342 );
xor ( n13192 , n13191 , n7238 );
xor ( n13193 , n13192 , n7533 );
and ( n13194 , n13190 , n13193 );
xor ( n13195 , n13174 , n13194 );
xor ( n13196 , n8029 , n12347 );
xor ( n13197 , n13196 , n9639 );
buf ( n13198 , n6343 );
xor ( n13199 , n13198 , n13042 );
xor ( n13200 , n13199 , n12552 );
not ( n13201 , n13200 );
xor ( n13202 , n9226 , n10971 );
xor ( n13203 , n13202 , n6947 );
and ( n13204 , n13201 , n13203 );
xor ( n13205 , n13197 , n13204 );
xor ( n13206 , n13195 , n13205 );
xor ( n13207 , n12970 , n10673 );
xor ( n13208 , n13207 , n10327 );
xor ( n13209 , n7142 , n10603 );
xor ( n13210 , n13209 , n10619 );
not ( n13211 , n13210 );
not ( n13212 , n6583 );
buf ( n13213 , n6344 );
and ( n13214 , n13212 , n13213 );
buf ( n13215 , n6345 );
xor ( n13216 , n13215 , n13213 );
and ( n13217 , n13216 , n6583 );
or ( n13218 , n13214 , n13217 );
xor ( n13219 , n11007 , n13218 );
buf ( n13220 , n6346 );
xor ( n13221 , n13219 , n13220 );
buf ( n13222 , n6347 );
xor ( n13223 , n13221 , n13222 );
buf ( n13224 , n6348 );
xor ( n13225 , n13223 , n13224 );
xor ( n13226 , n8247 , n13225 );
not ( n13227 , n6583 );
buf ( n13228 , n6349 );
and ( n13229 , n13227 , n13228 );
buf ( n13230 , n6350 );
xor ( n13231 , n13230 , n13228 );
and ( n13232 , n13231 , n6583 );
or ( n13233 , n13229 , n13232 );
not ( n13234 , n6583 );
buf ( n13235 , n6351 );
and ( n13236 , n13234 , n13235 );
buf ( n13237 , n6352 );
xor ( n13238 , n13237 , n13235 );
and ( n13239 , n13238 , n6583 );
or ( n13240 , n13236 , n13239 );
xor ( n13241 , n13233 , n13240 );
buf ( n13242 , n6353 );
xor ( n13243 , n13241 , n13242 );
xor ( n13244 , n13243 , n10351 );
buf ( n13245 , n6354 );
xor ( n13246 , n13244 , n13245 );
xor ( n13247 , n13226 , n13246 );
and ( n13248 , n13211 , n13247 );
xor ( n13249 , n13208 , n13248 );
xor ( n13250 , n13206 , n13249 );
not ( n13251 , n6583 );
buf ( n13252 , n6355 );
and ( n13253 , n13251 , n13252 );
buf ( n13254 , n6356 );
xor ( n13255 , n13254 , n13252 );
and ( n13256 , n13255 , n6583 );
or ( n13257 , n13253 , n13256 );
xor ( n13258 , n13257 , n7029 );
xor ( n13259 , n13258 , n7051 );
xor ( n13260 , n10383 , n11314 );
xor ( n13261 , n13260 , n11497 );
not ( n13262 , n13261 );
xor ( n13263 , n11624 , n6896 );
xor ( n13264 , n13263 , n6918 );
and ( n13265 , n13262 , n13264 );
xor ( n13266 , n13259 , n13265 );
xor ( n13267 , n13250 , n13266 );
xor ( n13268 , n9421 , n8863 );
not ( n13269 , n6583 );
buf ( n13270 , n6357 );
and ( n13271 , n13269 , n13270 );
buf ( n13272 , n6358 );
xor ( n13273 , n13272 , n13270 );
and ( n13274 , n13273 , n6583 );
or ( n13275 , n13271 , n13274 );
xor ( n13276 , n13275 , n11829 );
buf ( n13277 , n6359 );
xor ( n13278 , n13276 , n13277 );
buf ( n13279 , n6360 );
xor ( n13280 , n13278 , n13279 );
buf ( n13281 , n6361 );
xor ( n13282 , n13280 , n13281 );
xor ( n13283 , n13268 , n13282 );
not ( n13284 , n13124 );
and ( n13285 , n13284 , n13126 );
xor ( n13286 , n13283 , n13285 );
xor ( n13287 , n13267 , n13286 );
xor ( n13288 , n13172 , n13287 );
buf ( n13289 , n6362 );
xor ( n13290 , n13289 , n9660 );
not ( n13291 , n6583 );
buf ( n13292 , n6363 );
and ( n13293 , n13291 , n13292 );
buf ( n13294 , n6364 );
xor ( n13295 , n13294 , n13292 );
and ( n13296 , n13295 , n6583 );
or ( n13297 , n13293 , n13296 );
buf ( n13298 , n6365 );
xor ( n13299 , n13297 , n13298 );
xor ( n13300 , n13299 , n12935 );
buf ( n13301 , n6366 );
xor ( n13302 , n13300 , n13301 );
buf ( n13303 , n6367 );
xor ( n13304 , n13302 , n13303 );
xor ( n13305 , n13290 , n13304 );
xor ( n13306 , n8504 , n12721 );
xor ( n13307 , n13306 , n11805 );
not ( n13308 , n13307 );
xor ( n13309 , n11058 , n9262 );
not ( n13310 , n6583 );
buf ( n13311 , n6368 );
and ( n13312 , n13310 , n13311 );
buf ( n13313 , n6369 );
xor ( n13314 , n13313 , n13311 );
and ( n13315 , n13314 , n6583 );
or ( n13316 , n13312 , n13315 );
not ( n13317 , n6583 );
buf ( n13318 , n6370 );
and ( n13319 , n13317 , n13318 );
buf ( n13320 , n6371 );
xor ( n13321 , n13320 , n13318 );
and ( n13322 , n13321 , n6583 );
or ( n13323 , n13319 , n13322 );
xor ( n13324 , n13316 , n13323 );
buf ( n13325 , n6372 );
xor ( n13326 , n13324 , n13325 );
buf ( n13327 , n6373 );
xor ( n13328 , n13326 , n13327 );
xor ( n13329 , n13328 , n13128 );
xor ( n13330 , n13309 , n13329 );
and ( n13331 , n13308 , n13330 );
xor ( n13332 , n13305 , n13331 );
xor ( n13333 , n12913 , n6636 );
xor ( n13334 , n13333 , n9018 );
xor ( n13335 , n12151 , n7406 );
xor ( n13336 , n13335 , n7428 );
not ( n13337 , n13336 );
xor ( n13338 , n11725 , n6727 );
xor ( n13339 , n13338 , n12213 );
and ( n13340 , n13337 , n13339 );
xor ( n13341 , n13334 , n13340 );
xor ( n13342 , n13332 , n13341 );
xor ( n13343 , n10363 , n11292 );
xor ( n13344 , n13343 , n11314 );
not ( n13345 , n6583 );
buf ( n13346 , n6374 );
and ( n13347 , n13345 , n13346 );
buf ( n13348 , n6375 );
xor ( n13349 , n13348 , n13346 );
and ( n13350 , n13349 , n6583 );
or ( n13351 , n13347 , n13350 );
buf ( n13352 , n6376 );
xor ( n13353 , n13351 , n13352 );
xor ( n13354 , n13353 , n8953 );
buf ( n13355 , n6377 );
xor ( n13356 , n13354 , n13355 );
buf ( n13357 , n6378 );
xor ( n13358 , n13356 , n13357 );
xor ( n13359 , n7072 , n13358 );
not ( n13360 , n6583 );
buf ( n13361 , n6379 );
and ( n13362 , n13360 , n13361 );
buf ( n13363 , n6380 );
xor ( n13364 , n13363 , n13361 );
and ( n13365 , n13364 , n6583 );
or ( n13366 , n13362 , n13365 );
not ( n13367 , n6583 );
buf ( n13368 , n6381 );
and ( n13369 , n13367 , n13368 );
buf ( n13370 , n6382 );
xor ( n13371 , n13370 , n13368 );
and ( n13372 , n13371 , n6583 );
or ( n13373 , n13369 , n13372 );
xor ( n13374 , n13366 , n13373 );
buf ( n13375 , n6383 );
xor ( n13376 , n13374 , n13375 );
xor ( n13377 , n13376 , n9203 );
xor ( n13378 , n13377 , n7195 );
xor ( n13379 , n13359 , n13378 );
not ( n13380 , n13379 );
xor ( n13381 , n13316 , n13149 );
xor ( n13382 , n13381 , n13169 );
and ( n13383 , n13380 , n13382 );
xor ( n13384 , n13344 , n13383 );
xor ( n13385 , n13342 , n13384 );
buf ( n13386 , n6384 );
xor ( n13387 , n13386 , n7267 );
xor ( n13388 , n13387 , n7289 );
xor ( n13389 , n10775 , n10219 );
xor ( n13390 , n13389 , n9715 );
not ( n13391 , n13390 );
xor ( n13392 , n11986 , n11218 );
xor ( n13393 , n13392 , n7782 );
and ( n13394 , n13391 , n13393 );
xor ( n13395 , n13388 , n13394 );
xor ( n13396 , n13385 , n13395 );
xor ( n13397 , n9917 , n9178 );
xor ( n13398 , n13397 , n9200 );
not ( n13399 , n6583 );
buf ( n13400 , n6385 );
and ( n13401 , n13399 , n13400 );
buf ( n13402 , n6386 );
xor ( n13403 , n13402 , n13400 );
and ( n13404 , n13403 , n6583 );
or ( n13405 , n13401 , n13404 );
not ( n13406 , n6583 );
buf ( n13407 , n6387 );
and ( n13408 , n13406 , n13407 );
buf ( n13409 , n6388 );
xor ( n13410 , n13409 , n13407 );
and ( n13411 , n13410 , n6583 );
or ( n13412 , n13408 , n13411 );
xor ( n13413 , n13405 , n13412 );
xor ( n13414 , n13413 , n13198 );
buf ( n13415 , n6389 );
xor ( n13416 , n13414 , n13415 );
xor ( n13417 , n13416 , n13035 );
xor ( n13418 , n12432 , n13417 );
xor ( n13419 , n13418 , n8412 );
not ( n13420 , n13419 );
xor ( n13421 , n6857 , n8822 );
xor ( n13422 , n13421 , n11050 );
and ( n13423 , n13420 , n13422 );
xor ( n13424 , n13398 , n13423 );
xor ( n13425 , n13396 , n13424 );
xor ( n13426 , n13288 , n13425 );
and ( n13427 , n13122 , n13426 );
xor ( n13428 , n12788 , n13427 );
and ( n13429 , n13428 , n6584 );
or ( n13430 , n12254 , n13429 );
and ( n13431 , n12251 , n13430 );
buf ( n13432 , n13431 );
buf ( n13433 , n13432 );
not ( n13434 , n6578 );
not ( n13435 , n6584 );
and ( n13436 , n13435 , n9621 );
xor ( n13437 , n9626 , n8992 );
xor ( n13438 , n13437 , n8167 );
not ( n13439 , n6583 );
buf ( n13440 , n6390 );
and ( n13441 , n13439 , n13440 );
buf ( n13442 , n6391 );
xor ( n13443 , n13442 , n13440 );
and ( n13444 , n13443 , n6583 );
or ( n13445 , n13441 , n13444 );
xor ( n13446 , n13445 , n11072 );
not ( n13447 , n6583 );
buf ( n13448 , n6392 );
and ( n13449 , n13447 , n13448 );
buf ( n13450 , n6393 );
xor ( n13451 , n13450 , n13448 );
and ( n13452 , n13451 , n6583 );
or ( n13453 , n13449 , n13452 );
not ( n13454 , n6583 );
buf ( n13455 , n6394 );
and ( n13456 , n13454 , n13455 );
buf ( n13457 , n6395 );
xor ( n13458 , n13457 , n13455 );
and ( n13459 , n13458 , n6583 );
or ( n13460 , n13456 , n13459 );
xor ( n13461 , n13453 , n13460 );
buf ( n13462 , n6396 );
xor ( n13463 , n13461 , n13462 );
buf ( n13464 , n6397 );
xor ( n13465 , n13463 , n13464 );
buf ( n13466 , n6398 );
xor ( n13467 , n13465 , n13466 );
xor ( n13468 , n13446 , n13467 );
not ( n13469 , n13468 );
xor ( n13470 , n7385 , n13068 );
xor ( n13471 , n13470 , n13089 );
and ( n13472 , n13469 , n13471 );
xor ( n13473 , n13438 , n13472 );
xor ( n13474 , n7995 , n7851 );
xor ( n13475 , n11821 , n13257 );
buf ( n13476 , n6399 );
xor ( n13477 , n13475 , n13476 );
buf ( n13478 , n6400 );
xor ( n13479 , n13477 , n13478 );
xor ( n13480 , n13479 , n7014 );
xor ( n13481 , n13474 , n13480 );
not ( n13482 , n13438 );
and ( n13483 , n13482 , n13468 );
xor ( n13484 , n13481 , n13483 );
xor ( n13485 , n12755 , n9046 );
xor ( n13486 , n13485 , n8974 );
not ( n13487 , n6583 );
buf ( n13488 , n6401 );
and ( n13489 , n13487 , n13488 );
buf ( n13490 , n6402 );
xor ( n13491 , n13490 , n13488 );
and ( n13492 , n13491 , n6583 );
or ( n13493 , n13489 , n13492 );
not ( n13494 , n6583 );
buf ( n13495 , n6403 );
and ( n13496 , n13494 , n13495 );
buf ( n13497 , n6404 );
xor ( n13498 , n13497 , n13495 );
and ( n13499 , n13498 , n6583 );
or ( n13500 , n13496 , n13499 );
xor ( n13501 , n13500 , n8348 );
buf ( n13502 , n6405 );
xor ( n13503 , n13501 , n13502 );
buf ( n13504 , n6406 );
xor ( n13505 , n13503 , n13504 );
buf ( n13506 , n6407 );
xor ( n13507 , n13505 , n13506 );
xor ( n13508 , n13493 , n13507 );
xor ( n13509 , n13508 , n10260 );
not ( n13510 , n13509 );
xor ( n13511 , n7461 , n10867 );
xor ( n13512 , n13511 , n9920 );
and ( n13513 , n13510 , n13512 );
xor ( n13514 , n13486 , n13513 );
xor ( n13515 , n13484 , n13514 );
xor ( n13516 , n7008 , n11866 );
xor ( n13517 , n13516 , n10845 );
not ( n13518 , n6583 );
buf ( n13519 , n6408 );
and ( n13520 , n13518 , n13519 );
buf ( n13521 , n6409 );
xor ( n13522 , n13521 , n13519 );
and ( n13523 , n13522 , n6583 );
or ( n13524 , n13520 , n13523 );
not ( n13525 , n6583 );
buf ( n13526 , n6410 );
and ( n13527 , n13525 , n13526 );
buf ( n13528 , n6411 );
xor ( n13529 , n13528 , n13526 );
and ( n13530 , n13529 , n6583 );
or ( n13531 , n13527 , n13530 );
xor ( n13532 , n13524 , n13531 );
xor ( n13533 , n13532 , n7518 );
buf ( n13534 , n6412 );
xor ( n13535 , n13533 , n13534 );
buf ( n13536 , n6413 );
xor ( n13537 , n13535 , n13536 );
xor ( n13538 , n8152 , n13537 );
not ( n13539 , n6583 );
buf ( n13540 , n6414 );
and ( n13541 , n13539 , n13540 );
buf ( n13542 , n6415 );
xor ( n13543 , n13542 , n13540 );
and ( n13544 , n13543 , n6583 );
or ( n13545 , n13541 , n13544 );
not ( n13546 , n6583 );
buf ( n13547 , n6416 );
and ( n13548 , n13546 , n13547 );
buf ( n13549 , n6417 );
xor ( n13550 , n13549 , n13547 );
and ( n13551 , n13550 , n6583 );
or ( n13552 , n13548 , n13551 );
xor ( n13553 , n13545 , n13552 );
xor ( n13554 , n13553 , n8613 );
buf ( n13555 , n6418 );
xor ( n13556 , n13554 , n13555 );
buf ( n13557 , n6419 );
xor ( n13558 , n13556 , n13557 );
xor ( n13559 , n13538 , n13558 );
not ( n13560 , n13559 );
xor ( n13561 , n11971 , n11684 );
xor ( n13562 , n13561 , n11218 );
and ( n13563 , n13560 , n13562 );
xor ( n13564 , n13517 , n13563 );
xor ( n13565 , n13515 , n13564 );
not ( n13566 , n6583 );
buf ( n13567 , n6420 );
and ( n13568 , n13566 , n13567 );
buf ( n13569 , n6421 );
xor ( n13570 , n13569 , n13567 );
and ( n13571 , n13570 , n6583 );
or ( n13572 , n13568 , n13571 );
xor ( n13573 , n13572 , n12683 );
buf ( n13574 , n6422 );
xor ( n13575 , n13573 , n13574 );
buf ( n13576 , n6423 );
xor ( n13577 , n13575 , n13576 );
buf ( n13578 , n6424 );
xor ( n13579 , n13577 , n13578 );
xor ( n13580 , n12291 , n13579 );
xor ( n13581 , n13580 , n12234 );
xor ( n13582 , n12775 , n9699 );
xor ( n13583 , n13582 , n9362 );
not ( n13584 , n13583 );
xor ( n13585 , n11844 , n11560 );
xor ( n13586 , n13585 , n10944 );
and ( n13587 , n13584 , n13586 );
xor ( n13588 , n13581 , n13587 );
xor ( n13589 , n13565 , n13588 );
xor ( n13590 , n7554 , n8127 );
xor ( n13591 , n13590 , n8142 );
xor ( n13592 , n12110 , n6819 );
xor ( n13593 , n13592 , n12347 );
not ( n13594 , n13593 );
xor ( n13595 , n10113 , n12840 );
xor ( n13596 , n13595 , n12856 );
and ( n13597 , n13594 , n13596 );
xor ( n13598 , n13591 , n13597 );
xor ( n13599 , n13589 , n13598 );
xor ( n13600 , n13473 , n13599 );
xor ( n13601 , n13323 , n13149 );
xor ( n13602 , n13601 , n13169 );
not ( n13603 , n6583 );
buf ( n13604 , n6425 );
and ( n13605 , n13603 , n13604 );
buf ( n13606 , n6426 );
xor ( n13607 , n13606 , n13604 );
and ( n13608 , n13607 , n6583 );
or ( n13609 , n13605 , n13608 );
xor ( n13610 , n13609 , n13445 );
buf ( n13611 , n6427 );
xor ( n13612 , n13610 , n13611 );
buf ( n13613 , n6428 );
xor ( n13614 , n13612 , n13613 );
buf ( n13615 , n6429 );
xor ( n13616 , n13614 , n13615 );
buf ( n13617 , n13616 );
not ( n13618 , n6583 );
buf ( n13619 , n6430 );
and ( n13620 , n13618 , n13619 );
buf ( n13621 , n6431 );
xor ( n13622 , n13621 , n13619 );
and ( n13623 , n13622 , n6583 );
or ( n13624 , n13620 , n13623 );
not ( n13625 , n6583 );
buf ( n13626 , n6432 );
and ( n13627 , n13625 , n13626 );
buf ( n13628 , n6433 );
xor ( n13629 , n13628 , n13626 );
and ( n13630 , n13629 , n6583 );
or ( n13631 , n13627 , n13630 );
xor ( n13632 , n13624 , n13631 );
buf ( n13633 , n6434 );
xor ( n13634 , n13632 , n13633 );
buf ( n13635 , n6435 );
xor ( n13636 , n13634 , n13635 );
buf ( n13637 , n6436 );
xor ( n13638 , n13636 , n13637 );
xor ( n13639 , n13617 , n13638 );
not ( n13640 , n13639 );
xor ( n13641 , n11166 , n9942 );
xor ( n13642 , n13641 , n10993 );
and ( n13643 , n13640 , n13642 );
xor ( n13644 , n13602 , n13643 );
xor ( n13645 , n9171 , n8606 );
xor ( n13646 , n8068 , n12733 );
buf ( n13647 , n6437 );
xor ( n13648 , n13646 , n13647 );
buf ( n13649 , n6438 );
xor ( n13650 , n13648 , n13649 );
buf ( n13651 , n6439 );
xor ( n13652 , n13650 , n13651 );
xor ( n13653 , n13645 , n13652 );
xor ( n13654 , n8700 , n10308 );
xor ( n13655 , n13654 , n11410 );
not ( n13656 , n13655 );
xor ( n13657 , n12430 , n13417 );
xor ( n13658 , n13657 , n8412 );
and ( n13659 , n13656 , n13658 );
xor ( n13660 , n13653 , n13659 );
xor ( n13661 , n13644 , n13660 );
xor ( n13662 , n12640 , n12954 );
xor ( n13663 , n13662 , n11739 );
xor ( n13664 , n9280 , n9018 );
xor ( n13665 , n13664 , n12782 );
not ( n13666 , n13665 );
xor ( n13667 , n12210 , n10070 );
not ( n13668 , n6583 );
buf ( n13669 , n6440 );
and ( n13670 , n13668 , n13669 );
buf ( n13671 , n6441 );
xor ( n13672 , n13671 , n13669 );
and ( n13673 , n13672 , n6583 );
or ( n13674 , n13670 , n13673 );
not ( n13675 , n6583 );
buf ( n13676 , n6442 );
and ( n13677 , n13675 , n13676 );
buf ( n13678 , n6443 );
xor ( n13679 , n13678 , n13676 );
and ( n13680 , n13679 , n6583 );
or ( n13681 , n13677 , n13680 );
xor ( n13682 , n13674 , n13681 );
buf ( n13683 , n6444 );
xor ( n13684 , n13682 , n13683 );
xor ( n13685 , n13684 , n11764 );
buf ( n13686 , n6445 );
xor ( n13687 , n13685 , n13686 );
xor ( n13688 , n13667 , n13687 );
and ( n13689 , n13666 , n13688 );
xor ( n13690 , n13663 , n13689 );
xor ( n13691 , n13661 , n13690 );
xor ( n13692 , n10791 , n9715 );
xor ( n13693 , n13692 , n8886 );
not ( n13694 , n6583 );
buf ( n13695 , n6446 );
and ( n13696 , n13694 , n13695 );
buf ( n13697 , n6447 );
xor ( n13698 , n13697 , n13695 );
and ( n13699 , n13698 , n6583 );
or ( n13700 , n13696 , n13699 );
not ( n13701 , n6583 );
buf ( n13702 , n6448 );
and ( n13703 , n13701 , n13702 );
buf ( n13704 , n6449 );
xor ( n13705 , n13704 , n13702 );
and ( n13706 , n13705 , n6583 );
or ( n13707 , n13703 , n13706 );
xor ( n13708 , n13700 , n13707 );
buf ( n13709 , n6450 );
xor ( n13710 , n13708 , n13709 );
buf ( n13711 , n6451 );
xor ( n13712 , n13710 , n13711 );
buf ( n13713 , n6452 );
xor ( n13714 , n13712 , n13713 );
xor ( n13715 , n11781 , n13714 );
not ( n13716 , n6583 );
buf ( n13717 , n6453 );
and ( n13718 , n13716 , n13717 );
buf ( n13719 , n6454 );
xor ( n13720 , n13719 , n13717 );
and ( n13721 , n13720 , n6583 );
or ( n13722 , n13718 , n13721 );
not ( n13723 , n6583 );
buf ( n13724 , n6455 );
and ( n13725 , n13723 , n13724 );
buf ( n13726 , n6456 );
xor ( n13727 , n13726 , n13724 );
and ( n13728 , n13727 , n6583 );
or ( n13729 , n13725 , n13728 );
xor ( n13730 , n13722 , n13729 );
xor ( n13731 , n13730 , n11445 );
buf ( n13732 , n6457 );
xor ( n13733 , n13731 , n13732 );
buf ( n13734 , n6458 );
xor ( n13735 , n13733 , n13734 );
xor ( n13736 , n13715 , n13735 );
not ( n13737 , n13736 );
buf ( n13738 , n6459 );
xor ( n13739 , n13738 , n7051 );
xor ( n13740 , n13739 , n6987 );
and ( n13741 , n13737 , n13740 );
xor ( n13742 , n13693 , n13741 );
xor ( n13743 , n13691 , n13742 );
xor ( n13744 , n12285 , n13579 );
xor ( n13745 , n13744 , n12234 );
xor ( n13746 , n9080 , n11604 );
xor ( n13747 , n13746 , n6849 );
not ( n13748 , n13747 );
xor ( n13749 , n7365 , n12160 );
xor ( n13750 , n13749 , n13068 );
and ( n13751 , n13748 , n13750 );
xor ( n13752 , n13745 , n13751 );
xor ( n13753 , n13743 , n13752 );
xor ( n13754 , n13600 , n13753 );
not ( n13755 , n6583 );
buf ( n13756 , n6460 );
and ( n13757 , n13755 , n13756 );
buf ( n13758 , n6461 );
xor ( n13759 , n13758 , n13756 );
and ( n13760 , n13759 , n6583 );
or ( n13761 , n13757 , n13760 );
not ( n13762 , n6583 );
buf ( n13763 , n6462 );
and ( n13764 , n13762 , n13763 );
buf ( n13765 , n6463 );
xor ( n13766 , n13765 , n13763 );
and ( n13767 , n13766 , n6583 );
or ( n13768 , n13764 , n13767 );
xor ( n13769 , n13761 , n13768 );
buf ( n13770 , n6464 );
xor ( n13771 , n13769 , n13770 );
xor ( n13772 , n13771 , n13191 );
buf ( n13773 , n6465 );
xor ( n13774 , n13772 , n13773 );
xor ( n13775 , n8985 , n13774 );
xor ( n13776 , n13775 , n13537 );
not ( n13777 , n6583 );
buf ( n13778 , n6466 );
and ( n13779 , n13777 , n13778 );
buf ( n13780 , n6467 );
xor ( n13781 , n13780 , n13778 );
and ( n13782 , n13781 , n6583 );
or ( n13783 , n13779 , n13782 );
xor ( n13784 , n13783 , n12858 );
buf ( n13785 , n6468 );
xor ( n13786 , n13784 , n13785 );
buf ( n13787 , n6469 );
xor ( n13788 , n13786 , n13787 );
buf ( n13789 , n6470 );
xor ( n13790 , n13788 , n13789 );
xor ( n13791 , n9872 , n13790 );
xor ( n13792 , n13791 , n11710 );
not ( n13793 , n13792 );
and ( n13794 , n13793 , n13334 );
xor ( n13795 , n13776 , n13794 );
xor ( n13796 , n9222 , n10971 );
xor ( n13797 , n13796 , n6947 );
not ( n13798 , n13797 );
xor ( n13799 , n7672 , n8105 );
xor ( n13800 , n13799 , n6615 );
and ( n13801 , n13798 , n13800 );
xor ( n13802 , n13330 , n13801 );
not ( n13803 , n13776 );
and ( n13804 , n13803 , n13792 );
xor ( n13805 , n13339 , n13804 );
xor ( n13806 , n13802 , n13805 );
xor ( n13807 , n8227 , n12371 );
xor ( n13808 , n13807 , n13225 );
not ( n13809 , n13808 );
xor ( n13810 , n7649 , n8727 );
not ( n13811 , n6583 );
buf ( n13812 , n6471 );
and ( n13813 , n13811 , n13812 );
buf ( n13814 , n6472 );
xor ( n13815 , n13814 , n13812 );
and ( n13816 , n13815 , n6583 );
or ( n13817 , n13813 , n13816 );
xor ( n13818 , n13817 , n12666 );
buf ( n13819 , n6473 );
xor ( n13820 , n13818 , n13819 );
xor ( n13821 , n13820 , n7689 );
buf ( n13822 , n6474 );
xor ( n13823 , n13821 , n13822 );
xor ( n13824 , n13810 , n13823 );
and ( n13825 , n13809 , n13824 );
xor ( n13826 , n13382 , n13825 );
xor ( n13827 , n13806 , n13826 );
xor ( n13828 , n11885 , n8948 );
xor ( n13829 , n13828 , n9972 );
not ( n13830 , n13829 );
xor ( n13831 , n10093 , n11544 );
xor ( n13832 , n13831 , n12840 );
and ( n13833 , n13830 , n13832 );
xor ( n13834 , n13393 , n13833 );
xor ( n13835 , n13827 , n13834 );
xor ( n13836 , n9780 , n11436 );
xor ( n13837 , n13836 , n11560 );
not ( n13838 , n13837 );
xor ( n13839 , n9610 , n10241 );
xor ( n13840 , n13839 , n9739 );
and ( n13841 , n13838 , n13840 );
xor ( n13842 , n13422 , n13841 );
xor ( n13843 , n13835 , n13842 );
xor ( n13844 , n13795 , n13843 );
xor ( n13845 , n8335 , n9229 );
xor ( n13846 , n13845 , n9244 );
xor ( n13847 , n8186 , n13558 );
xor ( n13848 , n13847 , n12492 );
not ( n13849 , n13848 );
xor ( n13850 , n9510 , n6918 );
xor ( n13851 , n13850 , n11386 );
and ( n13852 , n13849 , n13851 );
xor ( n13853 , n13846 , n13852 );
xor ( n13854 , n12868 , n8428 );
xor ( n13855 , n13854 , n10673 );
xor ( n13856 , n8289 , n10166 );
xor ( n13857 , n13856 , n12191 );
not ( n13858 , n13857 );
xor ( n13859 , n6870 , n8822 );
xor ( n13860 , n13859 , n11050 );
and ( n13861 , n13858 , n13860 );
xor ( n13862 , n13855 , n13861 );
xor ( n13863 , n13853 , n13862 );
xor ( n13864 , n7705 , n11978 );
xor ( n13865 , n13864 , n11993 );
xor ( n13866 , n7332 , n11529 );
xor ( n13867 , n13866 , n11544 );
not ( n13868 , n13867 );
xor ( n13869 , n7215 , n8036 );
xor ( n13870 , n13869 , n8058 );
and ( n13871 , n13868 , n13870 );
xor ( n13872 , n13865 , n13871 );
xor ( n13873 , n13863 , n13872 );
xor ( n13874 , n9335 , n12037 );
xor ( n13875 , n13874 , n13579 );
xor ( n13876 , n11272 , n9533 );
xor ( n13877 , n13876 , n8018 );
not ( n13878 , n13877 );
xor ( n13879 , n7885 , n12065 );
xor ( n13880 , n13879 , n12080 );
and ( n13881 , n13878 , n13880 );
xor ( n13882 , n13875 , n13881 );
xor ( n13883 , n13873 , n13882 );
xor ( n13884 , n7463 , n10867 );
xor ( n13885 , n13884 , n9920 );
xor ( n13886 , n13649 , n8083 );
xor ( n13887 , n13886 , n8105 );
not ( n13888 , n13887 );
xor ( n13889 , n12551 , n9877 );
xor ( n13890 , n13889 , n8757 );
and ( n13891 , n13888 , n13890 );
xor ( n13892 , n13885 , n13891 );
xor ( n13893 , n13883 , n13892 );
xor ( n13894 , n13844 , n13893 );
not ( n13895 , n13894 );
not ( n13896 , n13247 );
xor ( n13897 , n12101 , n6797 );
xor ( n13898 , n13897 , n6819 );
and ( n13899 , n13896 , n13898 );
xor ( n13900 , n13210 , n13899 );
xor ( n13901 , n13900 , n13287 );
xor ( n13902 , n13901 , n13425 );
and ( n13903 , n13895 , n13902 );
xor ( n13904 , n13754 , n13903 );
and ( n13905 , n13904 , n6584 );
or ( n13906 , n13436 , n13905 );
and ( n13907 , n13434 , n13906 );
buf ( n13908 , n13907 );
buf ( n13909 , n13908 );
not ( n13910 , n6578 );
not ( n13911 , n6584 );
and ( n13912 , n13911 , n12193 );
xor ( n13913 , n8405 , n12552 );
xor ( n13914 , n13913 , n12573 );
xor ( n13915 , n8184 , n13558 );
xor ( n13916 , n13915 , n12492 );
not ( n13917 , n13916 );
xor ( n13918 , n8763 , n8460 );
xor ( n13919 , n13918 , n8482 );
and ( n13920 , n13917 , n13919 );
xor ( n13921 , n13914 , n13920 );
xor ( n13922 , n6835 , n8807 );
xor ( n13923 , n13922 , n8822 );
xor ( n13924 , n11142 , n9920 );
xor ( n13925 , n13924 , n9942 );
not ( n13926 , n13925 );
xor ( n13927 , n13100 , n8584 );
xor ( n13928 , n13927 , n8606 );
and ( n13929 , n13926 , n13928 );
xor ( n13930 , n13923 , n13929 );
xor ( n13931 , n7640 , n8727 );
xor ( n13932 , n13931 , n13823 );
xor ( n13933 , n6790 , n8018 );
xor ( n13934 , n13933 , n7073 );
not ( n13935 , n13934 );
xor ( n13936 , n11067 , n9262 );
xor ( n13937 , n13936 , n13329 );
and ( n13938 , n13935 , n13937 );
xor ( n13939 , n13932 , n13938 );
xor ( n13940 , n13930 , n13939 );
xor ( n13941 , n8815 , n7368 );
xor ( n13942 , n13941 , n7390 );
not ( n13943 , n13914 );
and ( n13944 , n13943 , n13916 );
xor ( n13945 , n13942 , n13944 );
xor ( n13946 , n13940 , n13945 );
xor ( n13947 , n10300 , n7147 );
not ( n13948 , n6583 );
buf ( n13949 , n6475 );
and ( n13950 , n13948 , n13949 );
buf ( n13951 , n6476 );
xor ( n13952 , n13951 , n13949 );
and ( n13953 , n13952 , n6583 );
or ( n13954 , n13950 , n13953 );
xor ( n13955 , n13954 , n11662 );
buf ( n13956 , n6477 );
xor ( n13957 , n13955 , n13956 );
xor ( n13958 , n13957 , n13112 );
buf ( n13959 , n6478 );
xor ( n13960 , n13958 , n13959 );
xor ( n13961 , n13947 , n13960 );
not ( n13962 , n6583 );
buf ( n13963 , n6479 );
and ( n13964 , n13962 , n13963 );
buf ( n13965 , n6480 );
xor ( n13966 , n13965 , n13963 );
and ( n13967 , n13966 , n6583 );
or ( n13968 , n13964 , n13967 );
buf ( n13969 , n6481 );
xor ( n13970 , n13968 , n13969 );
buf ( n13971 , n6482 );
xor ( n13972 , n13970 , n13971 );
buf ( n13973 , n6483 );
xor ( n13974 , n13972 , n13973 );
buf ( n13975 , n6484 );
xor ( n13976 , n13974 , n13975 );
xor ( n13977 , n10404 , n13976 );
not ( n13978 , n6583 );
buf ( n13979 , n6485 );
and ( n13980 , n13978 , n13979 );
buf ( n13981 , n6486 );
xor ( n13982 , n13981 , n13979 );
and ( n13983 , n13982 , n6583 );
or ( n13984 , n13980 , n13983 );
not ( n13985 , n6583 );
buf ( n13986 , n6487 );
and ( n13987 , n13985 , n13986 );
buf ( n13988 , n6488 );
xor ( n13989 , n13988 , n13986 );
and ( n13990 , n13989 , n6583 );
or ( n13991 , n13987 , n13990 );
xor ( n13992 , n13984 , n13991 );
buf ( n13993 , n6489 );
xor ( n13994 , n13992 , n13993 );
xor ( n13995 , n13994 , n11564 );
xor ( n13996 , n13995 , n10678 );
xor ( n13997 , n13977 , n13996 );
not ( n13998 , n13997 );
xor ( n13999 , n11342 , n10349 );
xor ( n14000 , n13999 , n7319 );
and ( n14001 , n13998 , n14000 );
xor ( n14002 , n13961 , n14001 );
xor ( n14003 , n13946 , n14002 );
xor ( n14004 , n9055 , n11590 );
xor ( n14005 , n14004 , n11604 );
xor ( n14006 , n9102 , n10142 );
xor ( n14007 , n14006 , n6659 );
not ( n14008 , n14007 );
not ( n14009 , n6583 );
buf ( n14010 , n6490 );
and ( n14011 , n14009 , n14010 );
buf ( n14012 , n6491 );
xor ( n14013 , n14012 , n14010 );
and ( n14014 , n14013 , n6583 );
or ( n14015 , n14011 , n14014 );
not ( n14016 , n6583 );
buf ( n14017 , n6492 );
and ( n14018 , n14016 , n14017 );
buf ( n14019 , n6493 );
xor ( n14020 , n14019 , n14017 );
and ( n14021 , n14020 , n6583 );
or ( n14022 , n14018 , n14021 );
xor ( n14023 , n14015 , n14022 );
buf ( n14024 , n6494 );
xor ( n14025 , n14023 , n14024 );
buf ( n14026 , n6495 );
xor ( n14027 , n14025 , n14026 );
buf ( n14028 , n6496 );
xor ( n14029 , n14027 , n14028 );
xor ( n14030 , n8943 , n14029 );
not ( n14031 , n6583 );
buf ( n14032 , n6497 );
and ( n14033 , n14031 , n14032 );
buf ( n14034 , n6498 );
xor ( n14035 , n14034 , n14032 );
and ( n14036 , n14035 , n6583 );
or ( n14037 , n14033 , n14036 );
not ( n14038 , n6583 );
buf ( n14039 , n6499 );
and ( n14040 , n14038 , n14039 );
buf ( n14041 , n6500 );
xor ( n14042 , n14041 , n14039 );
and ( n14043 , n14042 , n6583 );
or ( n14044 , n14040 , n14043 );
xor ( n14045 , n14037 , n14044 );
buf ( n14046 , n6501 );
xor ( n14047 , n14045 , n14046 );
buf ( n14048 , n6502 );
xor ( n14049 , n14047 , n14048 );
buf ( n14050 , n6503 );
xor ( n14051 , n14049 , n14050 );
xor ( n14052 , n14030 , n14051 );
and ( n14053 , n14008 , n14052 );
xor ( n14054 , n14005 , n14053 );
xor ( n14055 , n14003 , n14054 );
xor ( n14056 , n13921 , n14055 );
xor ( n14057 , n9756 , n11147 );
xor ( n14058 , n14057 , n11169 );
xor ( n14059 , n12344 , n7095 );
xor ( n14060 , n14059 , n8992 );
not ( n14061 , n14060 );
xor ( n14062 , n12855 , n12292 );
not ( n14063 , n6583 );
buf ( n14064 , n6504 );
and ( n14065 , n14063 , n14064 );
buf ( n14066 , n6505 );
xor ( n14067 , n14066 , n14064 );
and ( n14068 , n14067 , n6583 );
or ( n14069 , n14065 , n14068 );
not ( n14070 , n6583 );
buf ( n14071 , n6506 );
and ( n14072 , n14070 , n14071 );
buf ( n14073 , n6507 );
xor ( n14074 , n14073 , n14071 );
and ( n14075 , n14074 , n6583 );
or ( n14076 , n14072 , n14075 );
xor ( n14077 , n14069 , n14076 );
buf ( n14078 , n6508 );
xor ( n14079 , n14077 , n14078 );
xor ( n14080 , n14079 , n12220 );
buf ( n14081 , n6509 );
xor ( n14082 , n14080 , n14081 );
xor ( n14083 , n14062 , n14082 );
and ( n14084 , n14061 , n14083 );
xor ( n14085 , n14058 , n14084 );
xor ( n14086 , n13144 , n8653 );
xor ( n14087 , n14086 , n12433 );
xor ( n14088 , n8102 , n8318 );
xor ( n14089 , n14088 , n8340 );
not ( n14090 , n14089 );
xor ( n14091 , n9068 , n11590 );
xor ( n14092 , n14091 , n11604 );
and ( n14093 , n14090 , n14092 );
xor ( n14094 , n14087 , n14093 );
xor ( n14095 , n14085 , n14094 );
xor ( n14096 , n8630 , n8142 );
xor ( n14097 , n14096 , n10308 );
xor ( n14098 , n11322 , n10327 );
xor ( n14099 , n14098 , n10349 );
not ( n14100 , n14099 );
xor ( n14101 , n11385 , n9897 );
xor ( n14102 , n14101 , n9046 );
and ( n14103 , n14100 , n14102 );
xor ( n14104 , n14097 , n14103 );
xor ( n14105 , n14095 , n14104 );
xor ( n14106 , n11942 , n13246 );
xor ( n14107 , n14106 , n7173 );
not ( n14108 , n6583 );
buf ( n14109 , n6510 );
and ( n14110 , n14108 , n14109 );
buf ( n14111 , n6511 );
xor ( n14112 , n14111 , n14109 );
and ( n14113 , n14112 , n6583 );
or ( n14114 , n14110 , n14113 );
not ( n14115 , n6583 );
buf ( n14116 , n6512 );
and ( n14117 , n14115 , n14116 );
buf ( n14118 , n6513 );
xor ( n14119 , n14118 , n14116 );
and ( n14120 , n14119 , n6583 );
or ( n14121 , n14117 , n14120 );
xor ( n14122 , n14114 , n14121 );
buf ( n14123 , n6514 );
xor ( n14124 , n14122 , n14123 );
buf ( n14125 , n6515 );
xor ( n14126 , n14124 , n14125 );
buf ( n14127 , n6516 );
xor ( n14128 , n14126 , n14127 );
xor ( n14129 , n10031 , n14128 );
xor ( n14130 , n14129 , n12721 );
not ( n14131 , n14130 );
xor ( n14132 , n9427 , n8863 );
xor ( n14133 , n14132 , n13282 );
and ( n14134 , n14131 , n14133 );
xor ( n14135 , n14107 , n14134 );
xor ( n14136 , n14105 , n14135 );
buf ( n14137 , n6517 );
xor ( n14138 , n14137 , n6987 );
xor ( n14139 , n14138 , n7009 );
xor ( n14140 , n7513 , n9615 );
xor ( n14141 , n14140 , n8584 );
not ( n14142 , n14141 );
xor ( n14143 , n13615 , n11072 );
xor ( n14144 , n14143 , n13467 );
and ( n14145 , n14142 , n14144 );
xor ( n14146 , n14139 , n14145 );
xor ( n14147 , n14136 , n14146 );
xor ( n14148 , n14056 , n14147 );
xor ( n14149 , n12692 , n10012 );
xor ( n14150 , n14149 , n10034 );
xor ( n14151 , n12753 , n9046 );
xor ( n14152 , n14151 , n8974 );
not ( n14153 , n14152 );
xor ( n14154 , n9139 , n12804 );
xor ( n14155 , n14154 , n7926 );
and ( n14156 , n14153 , n14155 );
xor ( n14157 , n14150 , n14156 );
xor ( n14158 , n8285 , n10166 );
xor ( n14159 , n14158 , n12191 );
xor ( n14160 , n6942 , n12915 );
xor ( n14161 , n14160 , n9285 );
not ( n14162 , n14161 );
xor ( n14163 , n8632 , n8142 );
xor ( n14164 , n14163 , n10308 );
and ( n14165 , n14162 , n14164 );
xor ( n14166 , n14159 , n14165 );
xor ( n14167 , n13298 , n8189 );
xor ( n14168 , n14167 , n10822 );
buf ( n14169 , n6518 );
xor ( n14170 , n14169 , n8766 );
xor ( n14171 , n14170 , n12371 );
not ( n14172 , n14171 );
xor ( n14173 , n8680 , n9307 );
xor ( n14174 , n14173 , n13507 );
and ( n14175 , n14172 , n14174 );
xor ( n14176 , n14168 , n14175 );
xor ( n14177 , n14166 , n14176 );
xor ( n14178 , n7312 , n11947 );
xor ( n14179 , n14178 , n11529 );
xor ( n14180 , n11213 , n12647 );
xor ( n14181 , n14180 , n12662 );
not ( n14182 , n14181 );
xor ( n14183 , n7186 , n12015 );
xor ( n14184 , n14183 , n12037 );
and ( n14185 , n14182 , n14184 );
xor ( n14186 , n14179 , n14185 );
xor ( n14187 , n14177 , n14186 );
xor ( n14188 , n7002 , n11866 );
xor ( n14189 , n14188 , n10845 );
not ( n14190 , n14150 );
and ( n14191 , n14190 , n14152 );
xor ( n14192 , n14189 , n14191 );
xor ( n14193 , n14187 , n14192 );
xor ( n14194 , n7879 , n12065 );
xor ( n14195 , n14194 , n12080 );
xor ( n14196 , n9173 , n8606 );
xor ( n14197 , n14196 , n13652 );
not ( n14198 , n14197 );
xor ( n14199 , n8314 , n10993 );
xor ( n14200 , n14199 , n9229 );
and ( n14201 , n14198 , n14200 );
xor ( n14202 , n14195 , n14201 );
xor ( n14203 , n14193 , n14202 );
xor ( n14204 , n14157 , n14203 );
xor ( n14205 , n7144 , n10603 );
xor ( n14206 , n14205 , n10619 );
xor ( n14207 , n6796 , n8018 );
xor ( n14208 , n14207 , n7073 );
not ( n14209 , n14208 );
xor ( n14210 , n9863 , n13790 );
xor ( n14211 , n14210 , n11710 );
and ( n14212 , n14209 , n14211 );
xor ( n14213 , n14206 , n14212 );
xor ( n14214 , n8366 , n9362 );
xor ( n14215 , n14214 , n9384 );
xor ( n14216 , n7599 , n13616 );
xor ( n14217 , n14216 , n13638 );
not ( n14218 , n14217 );
xor ( n14219 , n6738 , n9809 );
xor ( n14220 , n14219 , n9825 );
and ( n14221 , n14218 , n14220 );
xor ( n14222 , n14215 , n14221 );
xor ( n14223 , n14213 , n14222 );
xor ( n14224 , n11510 , n10120 );
xor ( n14225 , n14224 , n10012 );
xor ( n14226 , n13536 , n7533 );
xor ( n14227 , n14226 , n7555 );
not ( n14228 , n14227 );
xor ( n14229 , n11696 , n12873 );
xor ( n14230 , n14229 , n12978 );
and ( n14231 , n14228 , n14230 );
xor ( n14232 , n14225 , n14231 );
xor ( n14233 , n14223 , n14232 );
xor ( n14234 , n12122 , n6819 );
xor ( n14235 , n14234 , n12347 );
xor ( n14236 , n8907 , n9069 );
xor ( n14237 , n14236 , n9085 );
not ( n14238 , n14237 );
xor ( n14239 , n9447 , n10497 );
xor ( n14240 , n14239 , n13714 );
and ( n14241 , n14238 , n14240 );
xor ( n14242 , n14235 , n14241 );
xor ( n14243 , n14233 , n14242 );
xor ( n14244 , n10968 , n7686 );
xor ( n14245 , n14244 , n12915 );
not ( n14246 , n6583 );
buf ( n14247 , n6519 );
and ( n14248 , n14246 , n14247 );
buf ( n14249 , n6520 );
xor ( n14250 , n14249 , n14247 );
and ( n14251 , n14250 , n6583 );
or ( n14252 , n14248 , n14251 );
xor ( n14253 , n12356 , n14252 );
xor ( n14254 , n14253 , n14169 );
buf ( n14255 , n6521 );
xor ( n14256 , n14254 , n14255 );
buf ( n14257 , n6522 );
xor ( n14258 , n14256 , n14257 );
xor ( n14259 , n10672 , n14258 );
xor ( n14260 , n14259 , n8234 );
not ( n14261 , n14260 );
xor ( n14262 , n13453 , n13329 );
xor ( n14263 , n14262 , n9855 );
and ( n14264 , n14261 , n14263 );
xor ( n14265 , n14245 , n14264 );
xor ( n14266 , n14243 , n14265 );
xor ( n14267 , n14204 , n14266 );
not ( n14268 , n14267 );
not ( n14269 , n9019 );
and ( n14270 , n14269 , n11170 );
xor ( n14271 , n8994 , n14270 );
xor ( n14272 , n14271 , n9022 );
xor ( n14273 , n12079 , n9140 );
xor ( n14274 , n14273 , n9161 );
xor ( n14275 , n10957 , n7686 );
xor ( n14276 , n14275 , n12915 );
not ( n14277 , n14276 );
xor ( n14278 , n7625 , n8705 );
xor ( n14279 , n14278 , n8727 );
and ( n14280 , n14277 , n14279 );
xor ( n14281 , n14274 , n14280 );
xor ( n14282 , n9760 , n11147 );
xor ( n14283 , n14282 , n11169 );
xor ( n14284 , n11285 , n7319 );
xor ( n14285 , n14284 , n7335 );
not ( n14286 , n14285 );
xor ( n14287 , n9255 , n13089 );
xor ( n14288 , n14287 , n13149 );
and ( n14289 , n14286 , n14288 );
xor ( n14290 , n14283 , n14289 );
xor ( n14291 , n14281 , n14290 );
xor ( n14292 , n7367 , n12160 );
xor ( n14293 , n14292 , n13068 );
xor ( n14294 , n12903 , n6636 );
xor ( n14295 , n14294 , n9018 );
not ( n14296 , n14295 );
xor ( n14297 , n12401 , n10282 );
xor ( n14298 , n14297 , n8789 );
and ( n14299 , n14296 , n14298 );
xor ( n14300 , n14293 , n14299 );
xor ( n14301 , n14291 , n14300 );
not ( n14302 , n6583 );
buf ( n14303 , n6523 );
and ( n14304 , n14302 , n14303 );
buf ( n14305 , n6524 );
xor ( n14306 , n14305 , n14303 );
and ( n14307 , n14306 , n6583 );
or ( n14308 , n14304 , n14307 );
not ( n14309 , n6583 );
buf ( n14310 , n6525 );
and ( n14311 , n14309 , n14310 );
buf ( n14312 , n6526 );
xor ( n14313 , n14312 , n14310 );
and ( n14314 , n14313 , n6583 );
or ( n14315 , n14311 , n14314 );
xor ( n14316 , n14308 , n14315 );
buf ( n14317 , n6527 );
xor ( n14318 , n14316 , n14317 );
xor ( n14319 , n14318 , n13738 );
xor ( n14320 , n14319 , n9662 );
xor ( n14321 , n14028 , n14320 );
not ( n14322 , n6583 );
buf ( n14323 , n6528 );
and ( n14324 , n14322 , n14323 );
buf ( n14325 , n6529 );
xor ( n14326 , n14325 , n14323 );
and ( n14327 , n14326 , n6583 );
or ( n14328 , n14324 , n14327 );
xor ( n14329 , n14328 , n6966 );
xor ( n14330 , n14329 , n14137 );
buf ( n14331 , n6530 );
xor ( n14332 , n14330 , n14331 );
buf ( n14333 , n6531 );
xor ( n14334 , n14332 , n14333 );
xor ( n14335 , n14321 , n14334 );
xor ( n14336 , n8242 , n13225 );
xor ( n14337 , n14336 , n13246 );
not ( n14338 , n14337 );
xor ( n14339 , n11380 , n9897 );
xor ( n14340 , n14339 , n9046 );
and ( n14341 , n14338 , n14340 );
xor ( n14342 , n14335 , n14341 );
xor ( n14343 , n14301 , n14342 );
xor ( n14344 , n8291 , n10166 );
xor ( n14345 , n14344 , n12191 );
xor ( n14346 , n9928 , n9200 );
xor ( n14347 , n14346 , n13188 );
not ( n14348 , n14347 );
not ( n14349 , n6583 );
buf ( n14350 , n6532 );
and ( n14351 , n14349 , n14350 );
buf ( n14352 , n6533 );
xor ( n14353 , n14352 , n14350 );
and ( n14354 , n14353 , n6583 );
or ( n14355 , n14351 , n14354 );
xor ( n14356 , n14355 , n8932 );
xor ( n14357 , n14356 , n8948 );
and ( n14358 , n14348 , n14357 );
xor ( n14359 , n14345 , n14358 );
xor ( n14360 , n14343 , n14359 );
xor ( n14361 , n14272 , n14360 );
and ( n14362 , n14268 , n14361 );
xor ( n14363 , n14148 , n14362 );
and ( n14364 , n14363 , n6584 );
or ( n14365 , n13912 , n14364 );
and ( n14366 , n13910 , n14365 );
buf ( n14367 , n14366 );
buf ( n14368 , n14367 );
not ( n14369 , n6578 );
not ( n14370 , n6584 );
and ( n14371 , n14370 , n8316 );
xor ( n14372 , n7233 , n8058 );
not ( n14373 , n6583 );
buf ( n14374 , n6534 );
and ( n14375 , n14373 , n14374 );
buf ( n14376 , n6535 );
xor ( n14377 , n14376 , n14374 );
and ( n14378 , n14377 , n6583 );
or ( n14379 , n14375 , n14378 );
not ( n14380 , n6583 );
buf ( n14381 , n6536 );
and ( n14382 , n14380 , n14381 );
buf ( n14383 , n6537 );
xor ( n14384 , n14383 , n14381 );
and ( n14385 , n14384 , n6583 );
or ( n14386 , n14382 , n14385 );
xor ( n14387 , n14379 , n14386 );
buf ( n14388 , n6538 );
xor ( n14389 , n14387 , n14388 );
xor ( n14390 , n14389 , n13289 );
buf ( n14391 , n6539 );
xor ( n14392 , n14390 , n14391 );
xor ( n14393 , n14372 , n14392 );
xor ( n14394 , n7425 , n6871 );
not ( n14395 , n6583 );
buf ( n14396 , n6540 );
and ( n14397 , n14395 , n14396 );
buf ( n14398 , n6541 );
xor ( n14399 , n14398 , n14396 );
and ( n14400 , n14399 , n6583 );
or ( n14401 , n14397 , n14400 );
xor ( n14402 , n14401 , n11031 );
buf ( n14403 , n6542 );
xor ( n14404 , n14402 , n14403 );
buf ( n14405 , n6543 );
xor ( n14406 , n14404 , n14405 );
buf ( n14407 , n6544 );
xor ( n14408 , n14406 , n14407 );
xor ( n14409 , n14394 , n14408 );
not ( n14410 , n14409 );
xor ( n14411 , n13281 , n9787 );
xor ( n14412 , n14411 , n11850 );
and ( n14413 , n14410 , n14412 );
xor ( n14414 , n14393 , n14413 );
xor ( n14415 , n8159 , n13537 );
xor ( n14416 , n14415 , n13558 );
not ( n14417 , n14393 );
and ( n14418 , n14417 , n14409 );
xor ( n14419 , n14416 , n14418 );
xor ( n14420 , n8800 , n11650 );
xor ( n14421 , n14420 , n7368 );
xor ( n14422 , n10966 , n7686 );
xor ( n14423 , n14422 , n12915 );
not ( n14424 , n14423 );
xor ( n14425 , n7552 , n8127 );
xor ( n14426 , n14425 , n8142 );
and ( n14427 , n14424 , n14426 );
xor ( n14428 , n14421 , n14427 );
xor ( n14429 , n14419 , n14428 );
xor ( n14430 , n12184 , n8683 );
not ( n14431 , n6583 );
buf ( n14432 , n6545 );
and ( n14433 , n14431 , n14432 );
buf ( n14434 , n6546 );
xor ( n14435 , n14434 , n14432 );
and ( n14436 , n14435 , n6583 );
or ( n14437 , n14433 , n14436 );
xor ( n14438 , n13493 , n14437 );
buf ( n14439 , n6547 );
xor ( n14440 , n14438 , n14439 );
buf ( n14441 , n6548 );
xor ( n14442 , n14440 , n14441 );
buf ( n14443 , n6549 );
xor ( n14444 , n14442 , n14443 );
xor ( n14445 , n14430 , n14444 );
xor ( n14446 , n9850 , n13169 );
xor ( n14447 , n14446 , n13790 );
not ( n14448 , n14447 );
xor ( n14449 , n10257 , n8388 );
xor ( n14450 , n14449 , n12601 );
and ( n14451 , n14448 , n14450 );
xor ( n14452 , n14445 , n14451 );
xor ( n14453 , n14429 , n14452 );
xor ( n14454 , n14076 , n12234 );
xor ( n14455 , n14454 , n6896 );
xor ( n14456 , n10547 , n10915 );
xor ( n14457 , n14456 , n10142 );
not ( n14458 , n14457 );
not ( n14459 , n6583 );
buf ( n14460 , n6550 );
and ( n14461 , n14459 , n14460 );
buf ( n14462 , n6551 );
xor ( n14463 , n14462 , n14460 );
and ( n14464 , n14463 , n6583 );
or ( n14465 , n14461 , n14464 );
not ( n14466 , n6583 );
buf ( n14467 , n6552 );
and ( n14468 , n14466 , n14467 );
buf ( n14469 , n6553 );
xor ( n14470 , n14469 , n14467 );
and ( n14471 , n14470 , n6583 );
or ( n14472 , n14468 , n14471 );
xor ( n14473 , n14465 , n14472 );
buf ( n14474 , n6554 );
xor ( n14475 , n14473 , n14474 );
buf ( n14476 , n6555 );
xor ( n14477 , n14475 , n14476 );
buf ( n14478 , n6556 );
xor ( n14479 , n14477 , n14478 );
xor ( n14480 , n10216 , n14479 );
xor ( n14481 , n14480 , n7886 );
and ( n14482 , n14458 , n14481 );
xor ( n14483 , n14455 , n14482 );
xor ( n14484 , n14453 , n14483 );
xor ( n14485 , n12514 , n13735 );
xor ( n14486 , n14485 , n13976 );
xor ( n14487 , n9892 , n7289 );
xor ( n14488 , n14487 , n12102 );
not ( n14489 , n14488 );
xor ( n14490 , n7070 , n13358 );
xor ( n14491 , n14490 , n13378 );
and ( n14492 , n14489 , n14491 );
xor ( n14493 , n14486 , n14492 );
xor ( n14494 , n14484 , n14493 );
xor ( n14495 , n14414 , n14494 );
xor ( n14496 , n14495 , n10977 );
xor ( n14497 , n7264 , n11805 );
xor ( n14498 , n14497 , n11275 );
xor ( n14499 , n9808 , n11786 );
xor ( n14500 , n14499 , n12521 );
not ( n14501 , n14500 );
xor ( n14502 , n7414 , n6871 );
xor ( n14503 , n14502 , n14408 );
and ( n14504 , n14501 , n14503 );
xor ( n14505 , n14498 , n14504 );
xor ( n14506 , n10029 , n14128 );
xor ( n14507 , n14506 , n12721 );
xor ( n14508 , n9784 , n11436 );
xor ( n14509 , n14508 , n11560 );
not ( n14510 , n14509 );
buf ( n14511 , n6557 );
xor ( n14512 , n14511 , n14444 );
xor ( n14513 , n14512 , n12393 );
and ( n14514 , n14510 , n14513 );
xor ( n14515 , n14507 , n14514 );
xor ( n14516 , n14046 , n14334 );
xor ( n14517 , n14516 , n10584 );
not ( n14518 , n14498 );
and ( n14519 , n14518 , n14500 );
xor ( n14520 , n14517 , n14519 );
xor ( n14521 , n14515 , n14520 );
xor ( n14522 , n8903 , n9069 );
xor ( n14523 , n14522 , n9085 );
xor ( n14524 , n8080 , n11169 );
xor ( n14525 , n14524 , n8318 );
not ( n14526 , n14525 );
xor ( n14527 , n8529 , n11238 );
xor ( n14528 , n14527 , n9406 );
and ( n14529 , n14526 , n14528 );
xor ( n14530 , n14523 , n14529 );
xor ( n14531 , n14521 , n14530 );
xor ( n14532 , n9224 , n10971 );
xor ( n14533 , n14532 , n6947 );
xor ( n14534 , n9381 , n11100 );
xor ( n14535 , n14534 , n10893 );
not ( n14536 , n14535 );
xor ( n14537 , n7709 , n11978 );
xor ( n14538 , n14537 , n11993 );
and ( n14539 , n14536 , n14538 );
xor ( n14540 , n14533 , n14539 );
xor ( n14541 , n14531 , n14540 );
xor ( n14542 , n7330 , n11529 );
xor ( n14543 , n14542 , n11544 );
xor ( n14544 , n12034 , n11513 );
xor ( n14545 , n14544 , n12696 );
not ( n14546 , n14545 );
xor ( n14547 , n7050 , n11892 );
xor ( n14548 , n14547 , n11907 );
and ( n14549 , n14546 , n14548 );
xor ( n14550 , n14543 , n14549 );
xor ( n14551 , n14541 , n14550 );
xor ( n14552 , n14505 , n14551 );
xor ( n14553 , n10259 , n8388 );
xor ( n14554 , n14553 , n12601 );
not ( n14555 , n11823 );
and ( n14556 , n14555 , n11807 );
xor ( n14557 , n14554 , n14556 );
xor ( n14558 , n13734 , n11459 );
xor ( n14559 , n14558 , n11474 );
not ( n14560 , n11828 );
and ( n14561 , n14560 , n11851 );
xor ( n14562 , n14559 , n14561 );
xor ( n14563 , n14557 , n14562 );
xor ( n14564 , n8840 , n6659 );
xor ( n14565 , n14564 , n6681 );
not ( n14566 , n11908 );
and ( n14567 , n14566 , n11910 );
xor ( n14568 , n14565 , n14567 );
xor ( n14569 , n14563 , n14568 );
xor ( n14570 , n11217 , n12647 );
xor ( n14571 , n14570 , n12662 );
not ( n14572 , n11925 );
and ( n14573 , n14572 , n11948 );
xor ( n14574 , n14571 , n14573 );
xor ( n14575 , n14569 , n14574 );
xor ( n14576 , n9971 , n14051 );
xor ( n14577 , n14576 , n12931 );
not ( n14578 , n11957 );
and ( n14579 , n14578 , n11994 );
xor ( n14580 , n14577 , n14579 );
xor ( n14581 , n14575 , n14580 );
xor ( n14582 , n14552 , n14581 );
not ( n14583 , n14582 );
xor ( n14584 , n11891 , n8948 );
xor ( n14585 , n14584 , n9972 );
xor ( n14586 , n13366 , n7216 );
xor ( n14587 , n14586 , n7238 );
not ( n14588 , n14587 );
and ( n14589 , n14588 , n7655 );
xor ( n14590 , n14585 , n14589 );
xor ( n14591 , n9824 , n12521 );
xor ( n14592 , n14591 , n10411 );
not ( n14593 , n14592 );
xor ( n14594 , n7059 , n13358 );
xor ( n14595 , n14594 , n13378 );
and ( n14596 , n14593 , n14595 );
xor ( n14597 , n7470 , n14596 );
buf ( n14598 , n6558 );
xor ( n14599 , n14598 , n7267 );
xor ( n14600 , n14599 , n7289 );
not ( n14601 , n14600 );
xor ( n14602 , n9271 , n9018 );
xor ( n14603 , n14602 , n12782 );
and ( n14604 , n14601 , n14603 );
xor ( n14605 , n7601 , n14604 );
xor ( n14606 , n14597 , n14605 );
not ( n14607 , n14585 );
and ( n14608 , n14607 , n14587 );
xor ( n14609 , n7712 , n14608 );
xor ( n14610 , n14606 , n14609 );
xor ( n14611 , n12014 , n11497 );
xor ( n14612 , n14611 , n11513 );
not ( n14613 , n14612 );
xor ( n14614 , n8262 , n9244 );
xor ( n14615 , n14614 , n10166 );
and ( n14616 , n14613 , n14615 );
xor ( n14617 , n7852 , n14616 );
xor ( n14618 , n14610 , n14617 );
xor ( n14619 , n8057 , n9639 );
xor ( n14620 , n14619 , n9660 );
not ( n14621 , n14620 );
xor ( n14622 , n11261 , n9533 );
xor ( n14623 , n14622 , n8018 );
and ( n14624 , n14621 , n14623 );
xor ( n14625 , n7949 , n14624 );
xor ( n14626 , n14618 , n14625 );
xor ( n14627 , n14590 , n14626 );
xor ( n14628 , n7202 , n8036 );
xor ( n14629 , n14628 , n8058 );
xor ( n14630 , n13063 , n7579 );
xor ( n14631 , n14630 , n7600 );
not ( n14632 , n14631 );
xor ( n14633 , n6866 , n8822 );
xor ( n14634 , n14633 , n11050 );
and ( n14635 , n14632 , n14634 );
xor ( n14636 , n14629 , n14635 );
xor ( n14637 , n9685 , n12191 );
not ( n14638 , n6583 );
buf ( n14639 , n6559 );
and ( n14640 , n14638 , n14639 );
buf ( n14641 , n6560 );
xor ( n14642 , n14641 , n14639 );
and ( n14643 , n14642 , n6583 );
or ( n14644 , n14640 , n14643 );
buf ( n14645 , n6561 );
xor ( n14646 , n14644 , n14645 );
buf ( n14647 , n6562 );
xor ( n14648 , n14646 , n14647 );
buf ( n14649 , n6563 );
xor ( n14650 , n14648 , n14649 );
xor ( n14651 , n14650 , n14511 );
xor ( n14652 , n14637 , n14651 );
xor ( n14653 , n9608 , n10241 );
xor ( n14654 , n14653 , n9739 );
not ( n14655 , n14654 );
xor ( n14656 , n8122 , n13304 );
xor ( n14657 , n14656 , n7125 );
and ( n14658 , n14655 , n14657 );
xor ( n14659 , n14652 , n14658 );
xor ( n14660 , n14636 , n14659 );
xor ( n14661 , n8044 , n9639 );
xor ( n14662 , n14661 , n9660 );
xor ( n14663 , n8720 , n11410 );
xor ( n14664 , n14663 , n7710 );
not ( n14665 , n14664 );
xor ( n14666 , n6610 , n8340 );
xor ( n14667 , n14666 , n8270 );
and ( n14668 , n14665 , n14667 );
xor ( n14669 , n14662 , n14668 );
xor ( n14670 , n14660 , n14669 );
xor ( n14671 , n6955 , n9285 );
xor ( n14672 , n14671 , n9307 );
not ( n14673 , n6583 );
buf ( n14674 , n6564 );
and ( n14675 , n14673 , n14674 );
buf ( n14676 , n6565 );
xor ( n14677 , n14676 , n14674 );
and ( n14678 , n14677 , n6583 );
or ( n14679 , n14675 , n14678 );
xor ( n14680 , n14679 , n13282 );
xor ( n14681 , n14680 , n14479 );
not ( n14682 , n14681 );
xor ( n14683 , n10470 , n11761 );
xor ( n14684 , n14683 , n12308 );
and ( n14685 , n14682 , n14684 );
xor ( n14686 , n14672 , n14685 );
xor ( n14687 , n14670 , n14686 );
xor ( n14688 , n12743 , n9046 );
xor ( n14689 , n14688 , n8974 );
xor ( n14690 , n12009 , n11497 );
xor ( n14691 , n14690 , n11513 );
not ( n14692 , n14691 );
xor ( n14693 , n12075 , n9140 );
xor ( n14694 , n14693 , n9161 );
and ( n14695 , n14692 , n14694 );
xor ( n14696 , n14689 , n14695 );
xor ( n14697 , n14687 , n14696 );
xor ( n14698 , n14627 , n14697 );
and ( n14699 , n14583 , n14698 );
xor ( n14700 , n14496 , n14699 );
and ( n14701 , n14700 , n6584 );
or ( n14702 , n14371 , n14701 );
and ( n14703 , n14369 , n14702 );
buf ( n14704 , n14703 );
buf ( n14705 , n14704 );
not ( n14706 , n6578 );
not ( n14707 , n6584 );
and ( n14708 , n14707 , n12119 );
not ( n14709 , n8823 );
and ( n14710 , n14709 , n11079 );
xor ( n14711 , n8791 , n14710 );
xor ( n14712 , n14711 , n9022 );
xor ( n14713 , n14712 , n14360 );
xor ( n14714 , n8973 , n12125 );
xor ( n14715 , n14714 , n8036 );
xor ( n14716 , n6651 , n9583 );
xor ( n14717 , n14716 , n9598 );
not ( n14718 , n14717 );
xor ( n14719 , n7361 , n12160 );
xor ( n14720 , n14719 , n13068 );
and ( n14721 , n14718 , n14720 );
xor ( n14722 , n14715 , n14721 );
xor ( n14723 , n9696 , n12191 );
xor ( n14724 , n14723 , n14651 );
xor ( n14725 , n7468 , n10867 );
xor ( n14726 , n14725 , n9920 );
not ( n14727 , n14726 );
xor ( n14728 , n12459 , n13823 );
xor ( n14729 , n14728 , n12954 );
and ( n14730 , n14727 , n14729 );
xor ( n14731 , n14724 , n14730 );
xor ( n14732 , n11344 , n10349 );
xor ( n14733 , n14732 , n7319 );
xor ( n14734 , n8141 , n7125 );
xor ( n14735 , n14734 , n7147 );
not ( n14736 , n14735 );
xor ( n14737 , n9414 , n8863 );
xor ( n14738 , n14737 , n13282 );
and ( n14739 , n14736 , n14738 );
xor ( n14740 , n14733 , n14739 );
xor ( n14741 , n14731 , n14740 );
xor ( n14742 , n7993 , n7851 );
xor ( n14743 , n14742 , n13480 );
xor ( n14744 , n10970 , n7686 );
xor ( n14745 , n14744 , n12915 );
not ( n14746 , n14745 );
xor ( n14747 , n12948 , n6705 );
xor ( n14748 , n14747 , n6727 );
and ( n14749 , n14746 , n14748 );
xor ( n14750 , n14743 , n14749 );
xor ( n14751 , n14741 , n14750 );
xor ( n14752 , n9758 , n11147 );
xor ( n14753 , n14752 , n11169 );
not ( n14754 , n14715 );
and ( n14755 , n14754 , n14717 );
xor ( n14756 , n14753 , n14755 );
xor ( n14757 , n14751 , n14756 );
xor ( n14758 , n9874 , n13790 );
xor ( n14759 , n14758 , n11710 );
xor ( n14760 , n10054 , n7782 );
xor ( n14761 , n14760 , n7804 );
not ( n14762 , n14761 );
xor ( n14763 , n10596 , n7632 );
xor ( n14764 , n14763 , n7654 );
and ( n14765 , n14762 , n14764 );
xor ( n14766 , n14759 , n14765 );
xor ( n14767 , n14757 , n14766 );
xor ( n14768 , n14722 , n14767 );
xor ( n14769 , n6691 , n11993 );
xor ( n14770 , n14769 , n10055 );
xor ( n14771 , n11340 , n10349 );
xor ( n14772 , n14771 , n7319 );
not ( n14773 , n14772 );
xor ( n14774 , n8229 , n12371 );
xor ( n14775 , n14774 , n13225 );
and ( n14776 , n14773 , n14775 );
xor ( n14777 , n14770 , n14776 );
xor ( n14778 , n9773 , n11436 );
xor ( n14779 , n14778 , n11560 );
xor ( n14780 , n12776 , n9699 );
xor ( n14781 , n14780 , n9362 );
not ( n14782 , n14781 );
xor ( n14783 , n13683 , n9455 );
xor ( n14784 , n14783 , n11786 );
and ( n14785 , n14782 , n14784 );
xor ( n14786 , n14779 , n14785 );
xor ( n14787 , n14777 , n14786 );
xor ( n14788 , n10042 , n7782 );
xor ( n14789 , n14788 , n7804 );
xor ( n14790 , n7974 , n7828 );
xor ( n14791 , n14790 , n7851 );
not ( n14792 , n14791 );
xor ( n14793 , n9104 , n10142 );
xor ( n14794 , n14793 , n6659 );
and ( n14795 , n14792 , n14794 );
xor ( n14796 , n14789 , n14795 );
xor ( n14797 , n14787 , n14796 );
xor ( n14798 , n7729 , n9428 );
not ( n14799 , n6583 );
buf ( n14800 , n6566 );
and ( n14801 , n14799 , n14800 );
buf ( n14802 , n6567 );
xor ( n14803 , n14802 , n14800 );
and ( n14804 , n14803 , n6583 );
or ( n14805 , n14801 , n14804 );
xor ( n14806 , n14805 , n14679 );
buf ( n14807 , n6568 );
xor ( n14808 , n14806 , n14807 );
buf ( n14809 , n6569 );
xor ( n14810 , n14808 , n14809 );
buf ( n14811 , n6570 );
xor ( n14812 , n14810 , n14811 );
xor ( n14813 , n14798 , n14812 );
xor ( n14814 , n7572 , n14408 );
xor ( n14815 , n14814 , n13616 );
not ( n14816 , n14815 );
xor ( n14817 , n9967 , n14051 );
xor ( n14818 , n14817 , n12931 );
and ( n14819 , n14816 , n14818 );
xor ( n14820 , n14813 , n14819 );
xor ( n14821 , n14797 , n14820 );
xor ( n14822 , n8713 , n11410 );
xor ( n14823 , n14822 , n7710 );
xor ( n14824 , n8967 , n12125 );
xor ( n14825 , n14824 , n8036 );
not ( n14826 , n14825 );
xor ( n14827 , n13038 , n9855 );
xor ( n14828 , n14827 , n9877 );
and ( n14829 , n14826 , n14828 );
xor ( n14830 , n14823 , n14829 );
xor ( n14831 , n14821 , n14830 );
xor ( n14832 , n14768 , n14831 );
not ( n14833 , n14832 );
xor ( n14834 , n10419 , n13996 );
not ( n14835 , n6583 );
buf ( n14836 , n6571 );
and ( n14837 , n14835 , n14836 );
buf ( n14838 , n6572 );
xor ( n14839 , n14838 , n14836 );
and ( n14840 , n14839 , n6583 );
or ( n14841 , n14837 , n14840 );
xor ( n14842 , n14841 , n14355 );
buf ( n14843 , n6573 );
xor ( n14844 , n14842 , n14843 );
buf ( n14845 , n6574 );
xor ( n14846 , n14844 , n14845 );
xor ( n14847 , n14846 , n8911 );
xor ( n14848 , n14834 , n14847 );
xor ( n14849 , n11211 , n12647 );
xor ( n14850 , n14849 , n12662 );
not ( n14851 , n14850 );
and ( n14852 , n14851 , n12219 );
xor ( n14853 , n14848 , n14852 );
xor ( n14854 , n11878 , n8948 );
xor ( n14855 , n14854 , n9972 );
not ( n14856 , n14855 );
xor ( n14857 , n9526 , n11386 );
xor ( n14858 , n14857 , n12756 );
and ( n14859 , n14856 , n14858 );
xor ( n14860 , n12084 , n14859 );
xor ( n14861 , n13076 , n7600 );
xor ( n14862 , n14861 , n8653 );
not ( n14863 , n14862 );
xor ( n14864 , n11554 , n10776 );
xor ( n14865 , n14864 , n10797 );
and ( n14866 , n14863 , n14865 );
xor ( n14867 , n12129 , n14866 );
xor ( n14868 , n14860 , n14867 );
xor ( n14869 , n9958 , n14051 );
xor ( n14870 , n14869 , n12931 );
not ( n14871 , n14870 );
xor ( n14872 , n9935 , n9200 );
xor ( n14873 , n14872 , n13188 );
and ( n14874 , n14871 , n14873 );
xor ( n14875 , n12166 , n14874 );
xor ( n14876 , n14868 , n14875 );
xor ( n14877 , n14401 , n11050 );
xor ( n14878 , n14877 , n11072 );
not ( n14879 , n14878 );
xor ( n14880 , n13240 , n10366 );
xor ( n14881 , n14880 , n10388 );
and ( n14882 , n14879 , n14881 );
xor ( n14883 , n12214 , n14882 );
xor ( n14884 , n14876 , n14883 );
not ( n14885 , n14848 );
and ( n14886 , n14885 , n14850 );
xor ( n14887 , n12239 , n14886 );
xor ( n14888 , n14884 , n14887 );
xor ( n14889 , n14853 , n14888 );
xor ( n14890 , n9039 , n12102 );
xor ( n14891 , n14890 , n12125 );
xor ( n14892 , n11270 , n9533 );
xor ( n14893 , n14892 , n8018 );
not ( n14894 , n14893 );
xor ( n14895 , n9137 , n12804 );
xor ( n14896 , n14895 , n7926 );
and ( n14897 , n14894 , n14896 );
xor ( n14898 , n14891 , n14897 );
xor ( n14899 , n9710 , n7886 );
xor ( n14900 , n14899 , n7908 );
xor ( n14901 , n9734 , n7469 );
xor ( n14902 , n14901 , n11147 );
not ( n14903 , n14902 );
xor ( n14904 , n6816 , n7073 );
xor ( n14905 , n14904 , n7095 );
and ( n14906 , n14903 , n14905 );
xor ( n14907 , n14900 , n14906 );
xor ( n14908 , n14898 , n14907 );
xor ( n14909 , n7670 , n8105 );
xor ( n14910 , n14909 , n6615 );
xor ( n14911 , n7423 , n6871 );
xor ( n14912 , n14911 , n14408 );
not ( n14913 , n14912 );
xor ( n14914 , n8267 , n9244 );
xor ( n14915 , n14914 , n10166 );
and ( n14916 , n14913 , n14915 );
xor ( n14917 , n14910 , n14916 );
xor ( n14918 , n14908 , n14917 );
xor ( n14919 , n11307 , n7335 );
xor ( n14920 , n14919 , n10098 );
xor ( n14921 , n8678 , n9307 );
xor ( n14922 , n14921 , n13507 );
not ( n14923 , n14922 );
xor ( n14924 , n10139 , n13020 );
xor ( n14925 , n14924 , n9583 );
and ( n14926 , n14923 , n14925 );
xor ( n14927 , n14920 , n14926 );
xor ( n14928 , n14918 , n14927 );
xor ( n14929 , n11732 , n6727 );
xor ( n14930 , n14929 , n12213 );
xor ( n14931 , n12851 , n12292 );
xor ( n14932 , n14931 , n14082 );
not ( n14933 , n14932 );
xor ( n14934 , n9490 , n8505 );
xor ( n14935 , n14934 , n7267 );
and ( n14936 , n14933 , n14935 );
xor ( n14937 , n14930 , n14936 );
xor ( n14938 , n14928 , n14937 );
xor ( n14939 , n14889 , n14938 );
and ( n14940 , n14833 , n14939 );
xor ( n14941 , n14713 , n14940 );
and ( n14942 , n14941 , n6584 );
or ( n14943 , n14708 , n14942 );
and ( n14944 , n14706 , n14943 );
buf ( n14945 , n14944 );
buf ( n14946 , n14945 );
not ( n14947 , n6578 );
not ( n14948 , n6584 );
and ( n14949 , n14948 , n12974 );
xor ( n14950 , n9654 , n8167 );
xor ( n14951 , n14950 , n8189 );
xor ( n14952 , n10862 , n13104 );
xor ( n14953 , n14952 , n9178 );
not ( n14954 , n14953 );
xor ( n14955 , n12489 , n8635 );
xor ( n14956 , n14955 , n8705 );
and ( n14957 , n14954 , n14956 );
xor ( n14958 , n14951 , n14957 );
xor ( n14959 , n11799 , n9511 );
xor ( n14960 , n14959 , n9533 );
xor ( n14961 , n11583 , n9161 );
xor ( n14962 , n14961 , n9560 );
not ( n14963 , n14962 );
xor ( n14964 , n12800 , n8886 );
xor ( n14965 , n14964 , n8908 );
and ( n14966 , n14963 , n14965 );
xor ( n14967 , n14960 , n14966 );
xor ( n14968 , n13182 , n7677 );
xor ( n14969 , n14968 , n7686 );
xor ( n14970 , n7022 , n14847 );
xor ( n14971 , n14970 , n11892 );
not ( n14972 , n14971 );
xor ( n14973 , n7068 , n13358 );
xor ( n14974 , n14973 , n13378 );
and ( n14975 , n14972 , n14974 );
xor ( n14976 , n14969 , n14975 );
xor ( n14977 , n14967 , n14976 );
xor ( n14978 , n9519 , n11386 );
xor ( n14979 , n14978 , n12756 );
not ( n14980 , n14951 );
and ( n14981 , n14980 , n14953 );
xor ( n14982 , n14979 , n14981 );
xor ( n14983 , n14977 , n14982 );
xor ( n14984 , n8075 , n11169 );
xor ( n14985 , n14984 , n8318 );
xor ( n14986 , n10908 , n12999 );
xor ( n14987 , n14986 , n13020 );
not ( n14988 , n14987 );
xor ( n14989 , n11405 , n13960 );
xor ( n14990 , n14989 , n11978 );
and ( n14991 , n14988 , n14990 );
xor ( n14992 , n14985 , n14991 );
xor ( n14993 , n14983 , n14992 );
xor ( n14994 , n10020 , n14128 );
xor ( n14995 , n14994 , n12721 );
xor ( n14996 , n10320 , n8234 );
xor ( n14997 , n14996 , n8250 );
not ( n14998 , n14997 );
xor ( n14999 , n7732 , n9428 );
xor ( n15000 , n14999 , n14812 );
and ( n15001 , n14998 , n15000 );
xor ( n15002 , n14995 , n15001 );
xor ( n15003 , n14993 , n15002 );
xor ( n15004 , n14958 , n15003 );
xor ( n15005 , n9064 , n11590 );
xor ( n15006 , n15005 , n11604 );
xor ( n15007 , n6984 , n11907 );
xor ( n15008 , n15007 , n11866 );
not ( n15009 , n15008 );
xor ( n15010 , n9454 , n10497 );
xor ( n15011 , n15010 , n13714 );
and ( n15012 , n15009 , n15011 );
xor ( n15013 , n15006 , n15012 );
xor ( n15014 , n7211 , n8036 );
xor ( n15015 , n15014 , n8058 );
xor ( n15016 , n7403 , n6849 );
xor ( n15017 , n15016 , n6871 );
not ( n15018 , n15017 );
xor ( n15019 , n10033 , n14128 );
xor ( n15020 , n15019 , n12721 );
and ( n15021 , n15018 , n15020 );
xor ( n15022 , n15015 , n15021 );
xor ( n15023 , n15013 , n15022 );
xor ( n15024 , n8601 , n9761 );
xor ( n15025 , n15024 , n8083 );
xor ( n15026 , n10305 , n7147 );
xor ( n15027 , n15026 , n13960 );
not ( n15028 , n15027 );
xor ( n15029 , n10697 , n7996 );
xor ( n15030 , n15029 , n10192 );
and ( n15031 , n15028 , n15030 );
xor ( n15032 , n15025 , n15031 );
xor ( n15033 , n15023 , n15032 );
xor ( n15034 , n11679 , n12473 );
xor ( n15035 , n15034 , n12647 );
xor ( n15036 , n9806 , n11786 );
xor ( n15037 , n15036 , n12521 );
not ( n15038 , n15037 );
xor ( n15039 , n11291 , n7319 );
xor ( n15040 , n15039 , n7335 );
and ( n15041 , n15038 , n15040 );
xor ( n15042 , n15035 , n15041 );
xor ( n15043 , n15033 , n15042 );
xor ( n15044 , n13277 , n9787 );
xor ( n15045 , n15044 , n11850 );
xor ( n15046 , n10795 , n9715 );
xor ( n15047 , n15046 , n8886 );
not ( n15048 , n15047 );
xor ( n15049 , n6818 , n7073 );
xor ( n15050 , n15049 , n7095 );
and ( n15051 , n15048 , n15050 );
xor ( n15052 , n15045 , n15051 );
xor ( n15053 , n15043 , n15052 );
xor ( n15054 , n15004 , n15053 );
xor ( n15055 , n10723 , n13687 );
xor ( n15056 , n15055 , n9809 );
xor ( n15057 , n8929 , n10192 );
xor ( n15058 , n15057 , n14029 );
not ( n15059 , n15058 );
and ( n15060 , n15059 , n13581 );
xor ( n15061 , n15056 , n15060 );
not ( n15062 , n13471 );
xor ( n15063 , n8603 , n9761 );
xor ( n15064 , n15063 , n8083 );
and ( n15065 , n15062 , n15064 );
xor ( n15066 , n13468 , n15065 );
xor ( n15067 , n10817 , n12492 );
xor ( n15068 , n15067 , n7632 );
not ( n15069 , n15068 );
xor ( n15070 , n13327 , n13149 );
xor ( n15071 , n15070 , n13169 );
and ( n15072 , n15069 , n15071 );
xor ( n15073 , n13512 , n15072 );
xor ( n15074 , n15066 , n15073 );
xor ( n15075 , n9239 , n6947 );
xor ( n15076 , n15075 , n6963 );
not ( n15077 , n15076 );
xor ( n15078 , n12659 , n11739 );
xor ( n15079 , n15078 , n11761 );
and ( n15080 , n15077 , n15079 );
xor ( n15081 , n13562 , n15080 );
xor ( n15082 , n15074 , n15081 );
not ( n15083 , n15056 );
and ( n15084 , n15083 , n15058 );
xor ( n15085 , n13586 , n15084 );
xor ( n15086 , n15082 , n15085 );
xor ( n15087 , n7921 , n8908 );
xor ( n15088 , n15087 , n10642 );
not ( n15089 , n15088 );
xor ( n15090 , n6846 , n8807 );
xor ( n15091 , n15090 , n8822 );
and ( n15092 , n15089 , n15091 );
xor ( n15093 , n13596 , n15092 );
xor ( n15094 , n15086 , n15093 );
xor ( n15095 , n15061 , n15094 );
xor ( n15096 , n7028 , n14847 );
xor ( n15097 , n15096 , n11892 );
not ( n15098 , n15097 );
xor ( n15099 , n13524 , n7533 );
xor ( n15100 , n15099 , n7555 );
and ( n15101 , n15098 , n15100 );
xor ( n15102 , n13642 , n15101 );
xor ( n15103 , n12124 , n6819 );
xor ( n15104 , n15103 , n12347 );
not ( n15105 , n15104 );
xor ( n15106 , n8374 , n9384 );
xor ( n15107 , n15106 , n10530 );
and ( n15108 , n15105 , n15107 );
xor ( n15109 , n13658 , n15108 );
xor ( n15110 , n15102 , n15109 );
xor ( n15111 , n7515 , n9615 );
xor ( n15112 , n15111 , n8584 );
not ( n15113 , n15112 );
xor ( n15114 , n7541 , n8127 );
xor ( n15115 , n15114 , n8142 );
and ( n15116 , n15113 , n15115 );
xor ( n15117 , n13688 , n15116 );
xor ( n15118 , n15110 , n15117 );
xor ( n15119 , n9477 , n10034 );
xor ( n15120 , n15119 , n8505 );
not ( n15121 , n15120 );
xor ( n15122 , n14644 , n14444 );
xor ( n15123 , n15122 , n12393 );
and ( n15124 , n15121 , n15123 );
xor ( n15125 , n13740 , n15124 );
xor ( n15126 , n15118 , n15125 );
xor ( n15127 , n7124 , n10822 );
xor ( n15128 , n15127 , n10603 );
not ( n15129 , n15128 );
xor ( n15130 , n7081 , n13378 );
xor ( n15131 , n15130 , n13774 );
and ( n15132 , n15129 , n15131 );
xor ( n15133 , n13750 , n15132 );
xor ( n15134 , n15126 , n15133 );
xor ( n15135 , n15095 , n15134 );
not ( n15136 , n15135 );
xor ( n15137 , n7006 , n11866 );
xor ( n15138 , n15137 , n10845 );
xor ( n15139 , n13067 , n7579 );
xor ( n15140 , n15139 , n7600 );
not ( n15141 , n15140 );
and ( n15142 , n15141 , n14005 );
xor ( n15143 , n15138 , n15142 );
xor ( n15144 , n8971 , n12125 );
xor ( n15145 , n15144 , n8036 );
not ( n15146 , n15145 );
xor ( n15147 , n11512 , n10120 );
xor ( n15148 , n15147 , n10012 );
and ( n15149 , n15146 , n15148 );
xor ( n15150 , n13928 , n15149 );
xor ( n15151 , n9197 , n13652 );
xor ( n15152 , n15151 , n7677 );
not ( n15153 , n15152 );
xor ( n15154 , n12803 , n8886 );
xor ( n15155 , n15154 , n8908 );
and ( n15156 , n15153 , n15155 );
xor ( n15157 , n13937 , n15156 );
xor ( n15158 , n15150 , n15157 );
not ( n15159 , n13919 );
xor ( n15160 , n11804 , n9511 );
xor ( n15161 , n15160 , n9533 );
and ( n15162 , n15159 , n15161 );
xor ( n15163 , n13916 , n15162 );
xor ( n15164 , n15158 , n15163 );
xor ( n15165 , n13576 , n12696 );
xor ( n15166 , n15165 , n9478 );
not ( n15167 , n15166 );
xor ( n15168 , n9582 , n8552 );
xor ( n15169 , n15168 , n7737 );
and ( n15170 , n15167 , n15169 );
xor ( n15171 , n14000 , n15170 );
xor ( n15172 , n15164 , n15171 );
not ( n15173 , n15138 );
and ( n15174 , n15173 , n15140 );
xor ( n15175 , n14052 , n15174 );
xor ( n15176 , n15172 , n15175 );
xor ( n15177 , n15143 , n15176 );
xor ( n15178 , n7354 , n12160 );
xor ( n15179 , n15178 , n13068 );
not ( n15180 , n15179 );
xor ( n15181 , n9193 , n13652 );
xor ( n15182 , n15181 , n7677 );
and ( n15183 , n15180 , n15182 );
xor ( n15184 , n14083 , n15183 );
xor ( n15185 , n7696 , n11978 );
xor ( n15186 , n15185 , n11993 );
not ( n15187 , n15186 );
xor ( n15188 , n13352 , n8974 );
xor ( n15189 , n15188 , n7216 );
and ( n15190 , n15187 , n15189 );
xor ( n15191 , n14092 , n15190 );
xor ( n15192 , n15184 , n15191 );
xor ( n15193 , n13056 , n7579 );
xor ( n15194 , n15193 , n7600 );
not ( n15195 , n15194 );
xor ( n15196 , n8750 , n11710 );
xor ( n15197 , n15196 , n8460 );
and ( n15198 , n15195 , n15197 );
xor ( n15199 , n14102 , n15198 );
xor ( n15200 , n15192 , n15199 );
xor ( n15201 , n10611 , n7654 );
xor ( n15202 , n15201 , n12473 );
not ( n15203 , n15202 );
xor ( n15204 , n10692 , n7996 );
xor ( n15205 , n15204 , n10192 );
and ( n15206 , n15203 , n15205 );
xor ( n15207 , n14133 , n15206 );
xor ( n15208 , n15200 , n15207 );
xor ( n15209 , n9546 , n7948 );
xor ( n15210 , n15209 , n11650 );
not ( n15211 , n15210 );
xor ( n15212 , n9576 , n8552 );
xor ( n15213 , n15212 , n7737 );
and ( n15214 , n15211 , n15213 );
xor ( n15215 , n14144 , n15214 );
xor ( n15216 , n15208 , n15215 );
xor ( n15217 , n15177 , n15216 );
and ( n15218 , n15136 , n15217 );
xor ( n15219 , n15054 , n15218 );
and ( n15220 , n15219 , n6584 );
or ( n15221 , n14949 , n15220 );
and ( n15222 , n14947 , n15221 );
buf ( n15223 , n15222 );
buf ( n15224 , n15223 );
not ( n15225 , n6578 );
not ( n15226 , n6584 );
and ( n15227 , n15226 , n8165 );
xor ( n15228 , n10941 , n10797 );
xor ( n15229 , n15228 , n12804 );
xor ( n15230 , n7172 , n10388 );
xor ( n15231 , n15230 , n12015 );
not ( n15232 , n15231 );
xor ( n15233 , n10853 , n13104 );
xor ( n15234 , n15233 , n9178 );
and ( n15235 , n15232 , n15234 );
xor ( n15236 , n15229 , n15235 );
xor ( n15237 , n11431 , n7759 );
xor ( n15238 , n15237 , n10776 );
xor ( n15239 , n11471 , n7980 );
xor ( n15240 , n15239 , n7996 );
not ( n15241 , n15240 );
xor ( n15242 , n13822 , n7710 );
xor ( n15243 , n15242 , n6705 );
and ( n15244 , n15241 , n15243 );
xor ( n15245 , n15238 , n15244 );
xor ( n15246 , n11801 , n9511 );
xor ( n15247 , n15246 , n9533 );
not ( n15248 , n15229 );
and ( n15249 , n15248 , n15231 );
xor ( n15250 , n15247 , n15249 );
xor ( n15251 , n15245 , n15250 );
xor ( n15252 , n6982 , n11907 );
xor ( n15253 , n15252 , n11866 );
xor ( n15254 , n8989 , n13774 );
xor ( n15255 , n15254 , n13537 );
not ( n15256 , n15255 );
xor ( n15257 , n13686 , n9455 );
xor ( n15258 , n15257 , n11786 );
and ( n15259 , n15256 , n15258 );
xor ( n15260 , n15253 , n15259 );
xor ( n15261 , n15251 , n15260 );
xor ( n15262 , n7550 , n8127 );
xor ( n15263 , n15262 , n8142 );
xor ( n15264 , n12644 , n12954 );
xor ( n15265 , n15264 , n11739 );
not ( n15266 , n15265 );
xor ( n15267 , n12572 , n8757 );
xor ( n15268 , n15267 , n8766 );
and ( n15269 , n15266 , n15268 );
xor ( n15270 , n15263 , n15269 );
xor ( n15271 , n15261 , n15270 );
xor ( n15272 , n12995 , n8789 );
xor ( n15273 , n15272 , n8530 );
xor ( n15274 , n8838 , n6659 );
xor ( n15275 , n15274 , n6681 );
not ( n15276 , n15275 );
xor ( n15277 , n6895 , n9493 );
not ( n15278 , n6583 );
buf ( n15279 , n6575 );
and ( n15280 , n15278 , n15279 );
buf ( n15281 , n6576 );
xor ( n15282 , n15281 , n15279 );
and ( n15283 , n15282 , n6583 );
or ( n15284 , n15280 , n15283 );
xor ( n15285 , n7246 , n15284 );
xor ( n15286 , n15285 , n12043 );
xor ( n15287 , n15286 , n13386 );
xor ( n15288 , n15287 , n14598 );
xor ( n15289 , n15277 , n15288 );
and ( n15290 , n15276 , n15289 );
xor ( n15291 , n15273 , n15290 );
xor ( n15292 , n15271 , n15291 );
xor ( n15293 , n15236 , n15292 );
xor ( n15294 , n11992 , n11218 );
xor ( n15295 , n15294 , n7782 );
xor ( n15296 , n14069 , n12234 );
xor ( n15297 , n15296 , n6896 );
not ( n15298 , n15297 );
xor ( n15299 , n10937 , n10797 );
xor ( n15300 , n15299 , n12804 );
and ( n15301 , n15298 , n15300 );
xor ( n15302 , n15295 , n15301 );
xor ( n15303 , n11496 , n10098 );
xor ( n15304 , n15303 , n10120 );
xor ( n15305 , n8592 , n9761 );
xor ( n15306 , n15305 , n8083 );
not ( n15307 , n15306 );
xor ( n15308 , n13969 , n11474 );
xor ( n15309 , n15308 , n10698 );
and ( n15310 , n15307 , n15309 );
xor ( n15311 , n15304 , n15310 );
xor ( n15312 , n15302 , n15311 );
xor ( n15313 , n13713 , n12323 );
xor ( n15314 , n15313 , n11459 );
xor ( n15315 , n6882 , n9493 );
xor ( n15316 , n15315 , n15288 );
not ( n15317 , n15316 );
xor ( n15318 , n7088 , n13378 );
xor ( n15319 , n15318 , n13774 );
and ( n15320 , n15317 , n15319 );
xor ( n15321 , n15314 , n15320 );
xor ( n15322 , n15312 , n15321 );
xor ( n15323 , n8459 , n12978 );
xor ( n15324 , n15323 , n11325 );
xor ( n15325 , n7460 , n10867 );
xor ( n15326 , n15325 , n9920 );
not ( n15327 , n15326 );
xor ( n15328 , n12387 , n10260 );
xor ( n15329 , n15328 , n10282 );
and ( n15330 , n15327 , n15329 );
xor ( n15331 , n15324 , n15330 );
xor ( n15332 , n15322 , n15331 );
xor ( n15333 , n7266 , n11805 );
xor ( n15334 , n15333 , n11275 );
xor ( n15335 , n12833 , n9340 );
xor ( n15336 , n15335 , n12292 );
not ( n15337 , n15336 );
xor ( n15338 , n12567 , n8757 );
xor ( n15339 , n15338 , n8766 );
and ( n15340 , n15337 , n15339 );
xor ( n15341 , n15334 , n15340 );
xor ( n15342 , n15332 , n15341 );
xor ( n15343 , n15293 , n15342 );
xor ( n15344 , n9492 , n8505 );
xor ( n15345 , n15344 , n7267 );
xor ( n15346 , n7399 , n6849 );
xor ( n15347 , n15346 , n6871 );
not ( n15348 , n15347 );
xor ( n15349 , n13163 , n12433 );
xor ( n15350 , n15349 , n12447 );
and ( n15351 , n15348 , n15350 );
xor ( n15352 , n15345 , n15351 );
xor ( n15353 , n8015 , n12756 );
xor ( n15354 , n15353 , n13358 );
xor ( n15355 , n7188 , n12015 );
xor ( n15356 , n15355 , n12037 );
not ( n15357 , n15356 );
xor ( n15358 , n10628 , n9085 );
xor ( n15359 , n15358 , n7406 );
and ( n15360 , n15357 , n15359 );
xor ( n15361 , n15354 , n15360 );
xor ( n15362 , n11145 , n9920 );
xor ( n15363 , n15362 , n9942 );
xor ( n15364 , n12064 , n10944 );
xor ( n15365 , n15364 , n9140 );
not ( n15366 , n15365 );
xor ( n15367 , n7133 , n10603 );
xor ( n15368 , n15367 , n10619 );
and ( n15369 , n15366 , n15368 );
xor ( n15370 , n15363 , n15369 );
xor ( n15371 , n15361 , n15370 );
xor ( n15372 , n8425 , n12573 );
xor ( n15373 , n15372 , n14258 );
not ( n15374 , n15345 );
and ( n15375 , n15374 , n15347 );
xor ( n15376 , n15373 , n15375 );
xor ( n15377 , n15371 , n15376 );
xor ( n15378 , n12837 , n9340 );
xor ( n15379 , n15378 , n12292 );
xor ( n15380 , n9108 , n10142 );
xor ( n15381 , n15380 , n6659 );
not ( n15382 , n15381 );
xor ( n15383 , n12484 , n8635 );
xor ( n15384 , n15383 , n8705 );
and ( n15385 , n15382 , n15384 );
xor ( n15386 , n15379 , n15385 );
xor ( n15387 , n15377 , n15386 );
xor ( n15388 , n14048 , n14334 );
xor ( n15389 , n15388 , n10584 );
xor ( n15390 , n8821 , n7368 );
xor ( n15391 , n15390 , n7390 );
not ( n15392 , n15391 );
xor ( n15393 , n12798 , n8886 );
xor ( n15394 , n15393 , n8908 );
and ( n15395 , n15392 , n15394 );
xor ( n15396 , n15389 , n15395 );
xor ( n15397 , n15387 , n15396 );
xor ( n15398 , n15352 , n15397 );
xor ( n15399 , n15398 , n14055 );
not ( n15400 , n15399 );
not ( n15401 , n15205 );
and ( n15402 , n15401 , n14107 );
xor ( n15403 , n15202 , n15402 );
xor ( n15404 , n15403 , n15216 );
xor ( n15405 , n15404 , n13287 );
and ( n15406 , n15400 , n15405 );
xor ( n15407 , n15343 , n15406 );
and ( n15408 , n15407 , n6584 );
or ( n15409 , n15227 , n15408 );
and ( n15410 , n15225 , n15409 );
buf ( n15411 , n15410 );
buf ( n15412 , n15411 );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_TB_V
`define SKY130_FD_SC_HS__CLKINV_TB_V
/**
* clkinv: Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_TB_V
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`include "config.vh"
`ifndef SIM
module pcie_core_wrap
(
// IO pins
output [`NLANES-1:0] pci_exp_txp,
output [`NLANES-1:0] pci_exp_txn,
input [`NLANES-1:0] pci_exp_rxp,
input [`NLANES-1:0] pci_exp_rxn,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n,
//
output [15:0] pci_id,
input interrupt,
output interrupt_rdy,
output reg pci_reset = 1,
output clock,
// DRP
input [9*`NLANES-1:0] gt_drp_address,
input [`NLANES-1:0] gt_drp_en,
input [16*`NLANES-1:0] gt_drp_di,
output [16*`NLANES-1:0] gt_drp_do,
output [`NLANES-1:0] gt_drp_ready,
input [`NLANES-1:0] gt_drp_we,
output gt_drp_clock,
// AXI to core
output s_axis_tx_tready,
input [63:0] s_axis_tx_tdata,
input s_axis_tx_1dw,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
// AXI from core
output m_axis_rx_tvalid,
output m_axis_rx_tlast,
output [63:0] m_axis_rx_tdata
);
wire user_reset;
wire user_lnk_up;
wire cfg_to_turnoff;
wire sys_rst_n_c;
wire sys_clk;
reg cfg_turnoff_ok = 0;
always @(posedge clock)
begin
pci_reset <= user_reset | ~user_lnk_up;
// fix this
cfg_turnoff_ok <= cfg_to_turnoff; // not if a completion is pending
end
IBUF pci_reset_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk),
.ODIV2(),
.I(sys_clk_p),
.CEB(1'b0),
.IB(sys_clk_n));
pcie_7x_0 pcie_7x_0_i
(
// PCI express data pairs
.pci_exp_txn(pci_exp_txn), .pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn), .pci_exp_rxp(pci_exp_rxp),
// AXI
.user_clk_out(clock),
.user_reset_out(user_reset),
.user_lnk_up(user_lnk_up),
.user_app_rdy(),
.s_axis_tx_tready(s_axis_tx_tready),
.s_axis_tx_tdata(s_axis_tx_tdata),
.s_axis_tx_tkeep(s_axis_tx_1dw ? 8'h0F : 8'hFF),
.s_axis_tx_tuser(4'd0), // may want to assert 2 for cut through
.s_axis_tx_tlast(s_axis_tx_tlast),
.s_axis_tx_tvalid(s_axis_tx_tvalid),
.m_axis_rx_tdata(m_axis_rx_tdata),
.m_axis_rx_tkeep(),
.m_axis_rx_tlast(m_axis_rx_tlast),
.m_axis_rx_tvalid(m_axis_rx_tvalid),
.m_axis_rx_tready(1'b1), // always ready
.m_axis_rx_tuser(),
.tx_cfg_gnt(1'b1), .rx_np_ok(1'b1), .rx_np_req(1'b1),
.cfg_trn_pending(1'b0),
.cfg_pm_halt_aspm_l0s(1'b0), .cfg_pm_halt_aspm_l1(1'b0),
.cfg_pm_force_state_en(1'b0), .cfg_pm_force_state(2'd0),
.cfg_dsn(64'h0),
.cfg_turnoff_ok(cfg_turnoff_ok),
.cfg_pm_wake(1'b0), .cfg_pm_send_pme_to(1'b0),
.cfg_ds_bus_number(8'b0),
.cfg_ds_device_number(5'b0),
.cfg_ds_function_number(3'b0),
// flow control
.fc_cpld(), .fc_cplh(), .fc_npd(), .fc_nph(),
.fc_pd(), .fc_ph(), .fc_sel(3'd0),
// configuration
.cfg_dcommand2(), .cfg_pmcsr_pme_status(),
.cfg_status(), .cfg_to_turnoff(cfg_to_turnoff),
.cfg_received_func_lvl_rst(),
.cfg_dcommand(),
.cfg_bus_number(pci_id[15:8]),
.cfg_device_number(pci_id[7:3]),
.cfg_function_number(pci_id[2:0]),
.cfg_command(),
.cfg_dstatus(),
.cfg_lstatus(),
.cfg_pcie_link_state(),
.cfg_lcommand(),
.cfg_pmcsr_pme_en(),
.cfg_pmcsr_powerstate(),
.tx_buf_av(),
.tx_err_drop(),
.tx_cfg_req(),
// root port only
.cfg_bridge_serr_en(),
.cfg_slot_control_electromech_il_ctl_pulse(),
.cfg_root_control_syserr_corr_err_en(),
.cfg_root_control_syserr_non_fatal_err_en(),
.cfg_root_control_syserr_fatal_err_en(),
.cfg_root_control_pme_int_en(),
.cfg_aer_rooterr_corr_err_reporting_en(),
.cfg_aer_rooterr_non_fatal_err_reporting_en(),
.cfg_aer_rooterr_fatal_err_reporting_en(),
.cfg_aer_rooterr_corr_err_received(),
.cfg_aer_rooterr_non_fatal_err_received(),
.cfg_aer_rooterr_fatal_err_received(),
// both
.cfg_vc_tcvc_map(),
// Management Interface
.cfg_mgmt_di(32'h0),
.cfg_mgmt_byte_en(4'h0),
.cfg_mgmt_dwaddr(10'h0),
.cfg_mgmt_wr_en(1'b0),
.cfg_mgmt_rd_en(1'b0),
.cfg_mgmt_wr_readonly(1'b0),
.cfg_mgmt_wr_rw1c_as_rw(1'b0),
.cfg_mgmt_do(),
.cfg_mgmt_rd_wr_done(),
// Error Reporting Interface
.cfg_err_ecrc(1'b0),
.cfg_err_ur(1'b0),
.cfg_err_cpl_timeout(1'b0),
.cfg_err_cpl_unexpect(1'b0),
.cfg_err_cpl_abort(1'b0),
.cfg_err_posted(1'b0),
.cfg_err_cor(1'b0),
.cfg_err_atomic_egress_blocked(1'b0),
.cfg_err_internal_cor(1'b0),
.cfg_err_malformed(1'b0),
.cfg_err_mc_blocked(1'b0),
.cfg_err_poisoned(1'b0),
.cfg_err_norecovery(1'b0),
.cfg_err_tlp_cpl_header(48'h0),
.cfg_err_cpl_rdy(),
.cfg_err_locked(1'b0),
.cfg_err_acs(1'b0),
.cfg_err_internal_uncor(1'b0),
.cfg_err_aer_headerlog(128'h0), .cfg_aer_interrupt_msgnum(5'h0),
.cfg_err_aer_headerlog_set(), .cfg_aer_ecrc_check_en(),
.cfg_aer_ecrc_gen_en(),
.cfg_interrupt(interrupt),
.cfg_interrupt_rdy(interrupt_rdy),
.cfg_interrupt_assert(1'b0),
.cfg_interrupt_di(8'h0),
.cfg_interrupt_do(),
.cfg_interrupt_mmenable(),
.cfg_interrupt_msienable(),
.cfg_interrupt_msixenable(),
.cfg_interrupt_msixfm(),
.cfg_interrupt_stat(1'b0),
.cfg_pciecap_interrupt_msgnum(5'h0),
.cfg_msg_received_err_cor(),
.cfg_msg_received_err_non_fatal(),
.cfg_msg_received_err_fatal(),
.cfg_msg_received_pm_as_nak(),
.cfg_msg_received_pme_to_ack(),
.cfg_msg_received_assert_int_a(), .cfg_msg_received_assert_int_b(),
.cfg_msg_received_assert_int_c(), .cfg_msg_received_assert_int_d(),
.cfg_msg_received_deassert_int_a(), .cfg_msg_received_deassert_int_b(),
.cfg_msg_received_deassert_int_c(), .cfg_msg_received_deassert_int_d(),
.cfg_msg_received_pm_pme(),
.cfg_msg_received_setslotpowerlimit(),
.cfg_msg_received(),
.cfg_msg_data(),
.pl_directed_link_change(2'd0), .pl_directed_link_width(2'd0),
.pl_directed_link_speed(1'b0), .pl_directed_link_auton(1'b0),
.pl_upstream_prefer_deemph(1'b1), .pl_sel_lnk_rate(), .pl_sel_lnk_width(),
.pl_ltssm_state(), .pl_lane_reversal_mode(), .pl_phy_lnk_up(),
.pl_tx_pm_state(), .pl_rx_pm_state(), .pl_link_upcfg_cap(),
.pl_link_gen2_cap(), .pl_link_partner_gen2_supported(),
.pl_initial_link_width(), .pl_directed_change_done(),
.pl_received_hot_rst(), .pl_transmit_hot_rst(1'b0),
.pl_downstream_deemph_source(1'b0),
.pcie_drp_clk(1'b1), .pcie_drp_en(1'b0), .pcie_drp_we(1'b0),
.pcie_drp_addr(9'h0), .pcie_drp_di(16'h0),
.pcie_drp_rdy(), .pcie_drp_do(),
// DRP
.ext_ch_gt_drpaddr(gt_drp_address),
.ext_ch_gt_drpen(gt_drp_en),
.ext_ch_gt_drpdi(gt_drp_di),
.ext_ch_gt_drpdo(gt_drp_do),
.ext_ch_gt_drprdy(gt_drp_ready),
.ext_ch_gt_drpwe(gt_drp_we),
.ext_ch_gt_drpclk(gt_drp_clock),
// these are the clock and reset from the card edge connector
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n_c )
);
endmodule
`endif
`ifdef SIM
module pcie_core_wrap
(
// IO pins
output [`NLANES-1:0] pci_exp_txp,
output [`NLANES-1:0] pci_exp_txn,
input [`NLANES-1:0] pci_exp_rxp,
input [`NLANES-1:0] pci_exp_rxn,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n,
output reg [15:0] pci_id = 16'hDEAD,
input interrupt,
output reg interrupt_rdy = 0,
output reg pci_reset = 0,
output reg clock = 0,
// DRP
input [9*`NLANES-1:0] gt_drp_address,
input [`NLANES-1:0] gt_drp_en,
input [16*`NLANES-1:0] gt_drp_di,
output [16*`NLANES-1:0] gt_drp_do,
output [`NLANES-1:0] gt_drp_ready,
input [`NLANES-1:0] gt_drp_we,
output gt_drp_clock,
// AXI to core
output reg s_axis_tx_tready = 0,
input [63:0] s_axis_tx_tdata,
input s_axis_tx_1dw,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
// AXI from core
output reg m_axis_rx_tvalid = 0,
output reg m_axis_rx_tlast = 0,
output reg [63:0] m_axis_rx_tdata = 0
);
always @ (posedge clock)
interrupt_rdy <= interrupt;
endmodule
`endif |
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 4, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output reg [575:0] out; /* to "f_permutation" module */
output out_ready; /* to "f_permutation" module */
input f_ack; /* from "f_permutation" module */
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
reg done; /* == 1: out_ready should be 0 */
reg [17:0] i; /* length of "out" buffer */
wire [31:0] v0; /* output of module "padder1" */
reg [31:0] v1; /* to be shifted into register "out" */
wire accept, /* accept user input? */
update;
assign buffer_full = i[17];
assign out_ready = buffer_full;
assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= {out[575-32:0], v1};
always @ (posedge clk)
if (reset)
i <= 0;
else if (f_ack | update)
i <= {i[16:0], 1'b1} & {18{~ f_ack}};
/* if (f_ack) i <= 0; */
/* if (update) i <= {i[16:0], 1'b1}; // increase length */
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
always @ (posedge clk)
if (reset)
done <= 0;
else if (state & out_ready)
done <= 1;
padder1 p0 (in, byte_num, v0);
always @ (*)
begin
if (state)
begin
v1 = 0;
v1[7] = v1[7] | i[16]; // "v1[7]" is the MSB of the last byte of "v1"
end
else if (is_last == 0)
v1 = in;
else
begin
v1 = v0;
v1[7] = v1[7] | i[16];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_1_V
`define SKY130_FD_SC_LP__NOR4BB_1_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_1 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_1 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_1_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory Controller Cache block
// File : mc_cache.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This block converts the 128 bit data path of the graphics controller to the
// 256 bit memory bus.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module mc_cache
(
input mclock,
input mc_rstn,
input [3:0] mc_dev_sel,
// to/from mc
input mc_local_write_req,
input mc_local_read_req,
input mc_local_burstbegin,
input [23:0] mc_local_address,
input [127:0] mc_local_wdata,
input [15:0] mc_local_be,
input [5:0] mc_local_size,
output mc_local_ready,
output reg [127:0] mc_local_rdata,
output reg mc_local_rdata_valid,
//
// to/from ddr3
//
input ddr3_ready,
input ddr3_rdata_valid,
input [255:0] ddr3_rdata,
output reg ddr3_write_req,
output reg ddr3_read_req,
output reg ddr3_burstbegin,
output reg [23:0] ddr3_address,
output reg [4:0] ddr3_size,
output reg [255:0] ddr3_wdata,
output reg [31:0] ddr3_be,
output reg ff_rdata_pop,
output local_read_empty,
output [7:0] data_fifo_used,
output [3:0] read_cmd_used,
output read_adr_0,
output [5:0] read_count_128
);
`define B31 [255:248]
`define B30 [247:240]
`define B29 [239:232]
`define B28 [231:224]
`define B27 [223:216]
`define B26 [215:208]
`define B25 [207:200]
`define B24 [199:192]
`define B23 [191:184]
`define B22 [183:176]
`define B21 [175:168]
`define B20 [167:160]
`define B19 [159:152]
`define B18 [151:144]
`define B17 [143:136]
`define B16 [135:128]
`define B15 [127:120]
`define B14 [119:112]
`define B13 [111:104]
`define B12 [103:96]
`define B11 [95:88]
`define B10 [87:80]
`define B9 [79:72]
`define B8 [71:64]
`define B7 [63:56]
`define B6 [55:48]
`define B5 [47:40]
`define B4 [39:32]
`define B3 [31:24]
`define B2 [23:16]
`define B1 [15:8]
`define B0 [7:0]
parameter READ_IDLE = 2'b00,
READ_FIRST = 2'b01,
READ_SECOND = 2'b10;
// reg ff_rdata_pop;
// wire local_read_empty;
// wire read_adr_0;
// wire [5:0] read_count_128;
reg [1:0] read_state;
reg local_word;
reg [5:0] local_size_128;
reg [5:0] read_size;
reg read_start;
reg bb_hold;
reg ddr3_burstbegin_wr;
reg [23:1] ddr3_address_wr;
reg [4:0] ddr3_size_wr;
wire [255:0] local_rdata;
wire one_word;
wire read_cmd_empty;
reg pop_read_128;
wire z_hit;
wire z_miss;
// reg z_valid;
// reg [22:0] z_address;
reg z_addr_0;
reg z_rdata_valid;
reg [255:0] z_cache;
wire z_load;
wire last_word;
assign last_word = ~|local_size_128[5:1] & local_size_128[0];
assign one_word = ~|mc_local_size[5:1] & mc_local_size[0];
// Pack Data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
local_size_128 <= 6'h0;
local_word <= 1'b0;
end
else begin
ddr3_address_wr <= mc_local_address[23:1];
ddr3_size_wr <= (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
if(mc_local_burstbegin) begin
local_size_128 <= mc_local_size - 6'h1;
local_word <= ~mc_local_address[0];
end
else if(mc_local_write_req) begin
local_size_128 <= local_size_128 - 6'h1;
local_word <= ~local_word;
end
bb_hold <= 1'b0;
casex({mc_local_write_req, mc_local_burstbegin, one_word, last_word, mc_local_address[0], local_word})
// Write one word low.
6'b111x0x: begin // Mask Hi, Write Lo, We, BB.
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= |(mc_local_be); // 1'b1;
ddr3_burstbegin_wr <= |(mc_local_be); // 1'b1;
end
// Write one word high
6'b111x1x: begin // Write Hi, Mask Lo, We, BB.
ddr3_be[15:0] <= 16'h0;
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= |(mc_local_be); // 1'b1;
ddr3_burstbegin_wr <= |(mc_local_be); // 1'b1;
end
// Write first word low
6'b110x0x: begin // Write Lo, Mask hi. No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
bb_hold <= 1'b1;
end
// Write first word high
6'b110x1x: begin // Write Hi, Mask lo. We, BB
ddr3_be[31:16] <= mc_local_be;
ddr3_be[15:0] <= 16'h0;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Normal Write Low
6'b10x0x0: begin // Mask Hi, Write Lo, No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
// Normal Write High, now push.
6'b10xxx1: begin
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= bb_hold;
end
// Write last word low
6'b10x1x0: begin // Mask Hi, Write Lo, We, BB
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b0;
end
default: begin
ddr3_be <= 32'hffffffff;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
endcase
end
end
// Chech for Z in the cache.
// assign z_hit = (mc_dev_sel == 4'h8) & ({z_valid, z_address} == {1'b1, mc_local_address[23:1]});
// assign z_miss = (mc_dev_sel == 4'h8) & ({z_valid, z_address} != {1'b1, mc_local_address[23:1]});
assign z_hit = 1'b0;
assign z_miss = 1'b1;
// Read Request.
// Don't request read if there is a Z hit.
always @* begin
if(mc_local_read_req & ddr3_ready & ~z_hit) begin
ddr3_read_req = 1'b1;
ddr3_burstbegin = 1'b1;
ddr3_address = mc_local_address[23:1];
ddr3_size = (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
end
else begin
ddr3_read_req = 1'b0;
ddr3_burstbegin = ddr3_burstbegin_wr;
ddr3_address = ddr3_address_wr;
ddr3_size = ddr3_size_wr;
end
end
assign mc_local_ready = ddr3_ready;
/* Z Cache.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
z_valid <= 1'b0;
z_address <= 23'h0;;
end
// Z miss, load the address, valid, and enable data load..
else if(~z_hit & mc_local_read_req & (mc_dev_sel == 4'h8)) begin
z_valid <= 1'b1;
z_address <= mc_local_address[23:1];
end
end
*/
mc_cache_fifo_256 u0_read_fifo_la
(
.clock (mclock),
.aclr (~mc_rstn),
.wrreq (ddr3_rdata_valid),
.data (ddr3_rdata),
.rdreq (ff_rdata_pop),
.almost_full (),
.empty (local_read_empty),
.full (),
.usedw (data_fifo_used),
.q (local_rdata)
);
sfifo_8x16_la u_read_128
(
.aclr (~mc_rstn),
.clock (mclock),
.wrreq (mc_local_read_req & ddr3_ready),
.data ({z_miss, mc_local_address[0], {6{~z_hit}} & mc_local_size}),
.rdreq (pop_read_128),
.q ({z_load, read_adr_0, read_count_128}),
.full (),
.empty (read_cmd_empty),
.usedw (read_cmd_used),
.almost_full ()
);
// Register to hold the Z.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) z_cache <= 256'h0;
else if(ddr3_write_req & (mc_dev_sel == 4'h8)) begin
if(ddr3_be[31]) z_cache`B31 <= ddr3_wdata`B31;
if(ddr3_be[30]) z_cache`B30 <= ddr3_wdata`B30;
if(ddr3_be[29]) z_cache`B29 <= ddr3_wdata`B29;
if(ddr3_be[28]) z_cache`B28 <= ddr3_wdata`B28;
if(ddr3_be[27]) z_cache`B27 <= ddr3_wdata`B27;
if(ddr3_be[26]) z_cache`B26 <= ddr3_wdata`B26;
if(ddr3_be[25]) z_cache`B25 <= ddr3_wdata`B25;
if(ddr3_be[24]) z_cache`B24 <= ddr3_wdata`B24;
if(ddr3_be[23]) z_cache`B23 <= ddr3_wdata`B23;
if(ddr3_be[22]) z_cache`B22 <= ddr3_wdata`B22;
if(ddr3_be[21]) z_cache`B21 <= ddr3_wdata`B21;
if(ddr3_be[20]) z_cache`B20 <= ddr3_wdata`B20;
if(ddr3_be[19]) z_cache`B19 <= ddr3_wdata`B19;
if(ddr3_be[18]) z_cache`B18 <= ddr3_wdata`B18;
if(ddr3_be[17]) z_cache`B17 <= ddr3_wdata`B17;
if(ddr3_be[16]) z_cache`B16 <= ddr3_wdata`B16;
if(ddr3_be[15]) z_cache`B15 <= ddr3_wdata`B15;
if(ddr3_be[14]) z_cache`B14 <= ddr3_wdata`B14;
if(ddr3_be[13]) z_cache`B13 <= ddr3_wdata`B13;
if(ddr3_be[12]) z_cache`B12 <= ddr3_wdata`B12;
if(ddr3_be[11]) z_cache`B11 <= ddr3_wdata`B11;
if(ddr3_be[10]) z_cache`B10 <= ddr3_wdata`B10;
if(ddr3_be[9]) z_cache`B9 <= ddr3_wdata`B9;
if(ddr3_be[8]) z_cache`B8 <= ddr3_wdata`B8;
if(ddr3_be[7]) z_cache`B7 <= ddr3_wdata`B7;
if(ddr3_be[6]) z_cache`B6 <= ddr3_wdata`B6;
if(ddr3_be[5]) z_cache`B5 <= ddr3_wdata`B5;
if(ddr3_be[4]) z_cache`B4 <= ddr3_wdata`B4;
if(ddr3_be[3]) z_cache`B3 <= ddr3_wdata`B3;
if(ddr3_be[2]) z_cache`B2 <= ddr3_wdata`B2;
if(ddr3_be[1]) z_cache`B1 <= ddr3_wdata`B1;
if(ddr3_be[0]) z_cache`B0 <= ddr3_wdata`B0;
end
else if(z_load & ddr3_rdata_valid) z_cache <= ddr3_rdata;
end
// Unpack data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
read_state <= READ_FIRST;
read_size <= 6'h0;
read_start <= 1'b0;
z_rdata_valid <= 1'b0;
z_addr_0 <= 1'b0;
end
else begin
z_rdata_valid <= 1'b0;
case(read_state)
READ_IDLE: begin
read_start <= read_adr_0;
if(!read_cmd_empty & (read_count_128 == 6'h0)) begin // This is a Z cache hit.
read_state <= READ_IDLE;
z_rdata_valid <= 1'b1;
z_addr_0 <= read_adr_0;
end
else if(~local_read_empty) begin
if(read_adr_0) read_state <= READ_SECOND;
else read_state <= READ_FIRST;
read_size <= read_count_128;
end
else read_state <= READ_IDLE;
end
READ_FIRST: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_SECOND;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_FIRST;
end
// Done.
else read_state <= READ_IDLE;
end
READ_SECOND: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_FIRST;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_SECOND;
end
// Done.
else read_state <= READ_IDLE;
end
endcase
end
end
always @* pop_read_128 = ((((read_state == READ_FIRST) | (read_state == READ_SECOND)) & (read_size == 6'h1)) & ~local_read_empty) |
((read_state == READ_IDLE) & (!read_cmd_empty & (read_count_128 == 6'h0))); // This is a Z cache hit.
always @* ff_rdata_pop = (((read_state == READ_FIRST) & (read_size == 6'h1)) | (read_state == READ_SECOND)) & ~local_read_empty;
always @* mc_local_rdata = (z_rdata_valid & z_addr_0) ? z_cache[255:128] :
(z_rdata_valid & ~z_addr_0) ? z_cache[127:0] :
(read_start) ? local_rdata[255:128] : local_rdata[127:0];
always @* mc_local_rdata_valid = (((read_state == READ_FIRST) | (read_state == READ_SECOND)) & ((read_size != 6'h0) & ~local_read_empty)) | z_rdata_valid;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:00:00 04/02/2016
// Design Name:
// Module Name: font_rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module font_rom
(
input wire Clk,
input wire [10:0] addr,
output reg [7:0] data
);
// signal declaration
reg [10:0] addr_reg;
// body
always @(posedge Clk)
addr_reg <= addr;
always @*
case (addr_reg)
//code x00
11'h000: data = 8'b00000000; //
11'h001: data = 8'b00000000; //
11'h002: data = 8'b00000000; //
11'h003: data = 8'b00000000; //
11'h004: data = 8'b00000000; //
11'h005: data = 8'b00000000; //
11'h006: data = 8'b00000000; //
11'h007: data = 8'b00000000; //
11'h008: data = 8'b00000000; //
11'h009: data = 8'b00000000; //
11'h00a: data = 8'b00000000; //
11'h00b: data = 8'b00000000; //
11'h00c: data = 8'b00000000; //
11'h00d: data = 8'b00000000; //
11'h00e: data = 8'b00000000; //
11'h00f: data = 8'b00000000; //
//code x01
11'h010: data = 8'b00000000; //
11'h011: data = 8'b00000000; //
11'h012: data = 8'b01111110; // ******
11'h013: data = 8'b10000001; // * *
11'h014: data = 8'b10100101; // * * * *
11'h015: data = 8'b10000001; // * *
11'h016: data = 8'b10000001; // * *
11'h017: data = 8'b10111101; // * **** *
11'h018: data = 8'b10011001; // * ** *
11'h019: data = 8'b10000001; // * *
11'h01a: data = 8'b10000001; // * *
11'h01b: data = 8'b01111110; // ******
11'h01c: data = 8'b00000000; //
11'h01d: data = 8'b00000000; //
11'h01e: data = 8'b00000000; //
11'h01f: data = 8'b00000000; //
//code x02
11'h020: data = 8'b00000000; //
11'h021: data = 8'b00000000; //
11'h022: data = 8'b01111110; // ******
11'h023: data = 8'b11111111; // ********
11'h024: data = 8'b11011011; // ** ** **
11'h025: data = 8'b11111111; // ********
11'h026: data = 8'b11111111; // ********
11'h027: data = 8'b11000011; // ** **
11'h028: data = 8'b11100111; // *** ***
11'h029: data = 8'b11111111; // ********
11'h02a: data = 8'b11111111; // ********
11'h02b: data = 8'b01111110; // ******
11'h02c: data = 8'b00000000; //
11'h02d: data = 8'b00000000; //
11'h02e: data = 8'b00000000; //
11'h02f: data = 8'b00000000; //
//code x03
11'h030: data = 8'b00000000; //
11'h031: data = 8'b00000000; //
11'h032: data = 8'b00000000; //
11'h033: data = 8'b00000000; //
11'h034: data = 8'b01101100; // ** **
11'h035: data = 8'b11111110; // *******
11'h036: data = 8'b11111110; // *******
11'h037: data = 8'b11111110; // *******
11'h038: data = 8'b11111110; // *******
11'h039: data = 8'b01111100; // *****
11'h03a: data = 8'b00111000; // ***
11'h03b: data = 8'b00010000; // *
11'h03c: data = 8'b00000000; //
11'h03d: data = 8'b00000000; //
11'h03e: data = 8'b00000000; //
11'h03f: data = 8'b00000000; //
//code x04
11'h040: data = 8'b00000000; //
11'h041: data = 8'b00000000; //
11'h042: data = 8'b00000000; //
11'h043: data = 8'b00000000; //
11'h044: data = 8'b00010000; // *
11'h045: data = 8'b00111000; // ***
11'h046: data = 8'b01111100; // *****
11'h047: data = 8'b11111110; // *******
11'h048: data = 8'b01111100; // *****
11'h049: data = 8'b00111000; // ***
11'h04a: data = 8'b00010000; // *
11'h04b: data = 8'b00000000; //
11'h04c: data = 8'b00000000; //
11'h04d: data = 8'b00000000; //
11'h04e: data = 8'b00000000; //
11'h04f: data = 8'b00000000; //
//code x05
11'h050: data = 8'b00000000; //
11'h051: data = 8'b00000000; //
11'h052: data = 8'b00000000; //
11'h053: data = 8'b00011000; // **
11'h054: data = 8'b00111100; // ****
11'h055: data = 8'b00111100; // ****
11'h056: data = 8'b11100111; // *** ***
11'h057: data = 8'b11100111; // *** ***
11'h058: data = 8'b11100111; // *** ***
11'h059: data = 8'b00011000; // **
11'h05a: data = 8'b00011000; // **
11'h05b: data = 8'b00111100; // ****
11'h05c: data = 8'b00000000; //
11'h05d: data = 8'b00000000; //
11'h05e: data = 8'b00000000; //
11'h05f: data = 8'b00000000; //
//code x06
11'h060: data = 8'b00000000; //
11'h061: data = 8'b00000000; //
11'h062: data = 8'b00000000; //
11'h063: data = 8'b00011000; // **
11'h064: data = 8'b00111100; // ****
11'h065: data = 8'b01111110; // ******
11'h066: data = 8'b11111111; // ********
11'h067: data = 8'b11111111; // ********
11'h068: data = 8'b01111110; // ******
11'h069: data = 8'b00011000; // **
11'h06a: data = 8'b00011000; // **
11'h06b: data = 8'b00111100; // ****
11'h06c: data = 8'b00000000; //
11'h06d: data = 8'b00000000; //
11'h06e: data = 8'b00000000; //
11'h06f: data = 8'b00000000; //
//code x07
11'h070: data = 8'b00000000; //
11'h071: data = 8'b00000000; //
11'h072: data = 8'b00000000; //
11'h073: data = 8'b00000000; //
11'h074: data = 8'b00000000; //
11'h075: data = 8'b00000000; //
11'h076: data = 8'b00011000; // **
11'h077: data = 8'b00111100; // ****
11'h078: data = 8'b00111100; // ****
11'h079: data = 8'b00011000; // **
11'h07a: data = 8'b00000000; //
11'h07b: data = 8'b00000000; //
11'h07c: data = 8'b00000000; //
11'h07d: data = 8'b00000000; //
11'h07e: data = 8'b00000000; //
11'h07f: data = 8'b00000000; //
//code x08
11'h080: data = 8'b11111111; // ********
11'h081: data = 8'b11111111; // ********
11'h082: data = 8'b11111111; // ********
11'h083: data = 8'b11111111; // ********
11'h084: data = 8'b11111111; // ********
11'h085: data = 8'b11111111; // ********
11'h086: data = 8'b11100111; // *** ***
11'h087: data = 8'b11000011; // ** **
11'h088: data = 8'b11000011; // ** **
11'h089: data = 8'b11100111; // *** ***
11'h08a: data = 8'b11111111; // ********
11'h08b: data = 8'b11111111; // ********
11'h08c: data = 8'b11111111; // ********
11'h08d: data = 8'b11111111; // ********
11'h08e: data = 8'b11111111; // ********
11'h08f: data = 8'b11111111; // ********
//code x09
11'h090: data = 8'b00000000; //
11'h091: data = 8'b00000000; //
11'h092: data = 8'b00000000; //
11'h093: data = 8'b00000000; //
11'h094: data = 8'b00000000; //
11'h095: data = 8'b00111100; // ****
11'h096: data = 8'b01100110; // ** **
11'h097: data = 8'b01000010; // * *
11'h098: data = 8'b01000010; // * *
11'h099: data = 8'b01100110; // ** **
11'h09a: data = 8'b00111100; // ****
11'h09b: data = 8'b00000000; //
11'h09c: data = 8'b00000000; //
11'h09d: data = 8'b00000000; //
11'h09e: data = 8'b00000000; //
11'h09f: data = 8'b00000000; //
//code x0a
11'h0a0: data = 8'b11111111; // ********
11'h0a1: data = 8'b11111111; // ********
11'h0a2: data = 8'b11111111; // ********
11'h0a3: data = 8'b11111111; // ********
11'h0a4: data = 8'b11111111; // ********
11'h0a5: data = 8'b11000011; // ** **
11'h0a6: data = 8'b10011001; // * ** *
11'h0a7: data = 8'b10111101; // * **** *
11'h0a8: data = 8'b10111101; // * **** *
11'h0a9: data = 8'b10011001; // * ** *
11'h0aa: data = 8'b11000011; // ** **
11'h0ab: data = 8'b11111111; // ********
11'h0ac: data = 8'b11111111; // ********
11'h0ad: data = 8'b11111111; // ********
11'h0ae: data = 8'b11111111; // ********
11'h0af: data = 8'b11111111; // ********
//code x0b
11'h0b0: data = 8'b00000000; //
11'h0b1: data = 8'b00000000; //
11'h0b2: data = 8'b00011110; // ****
11'h0b3: data = 8'b00001110; // ***
11'h0b4: data = 8'b00011010; // ** *
11'h0b5: data = 8'b00110010; // ** *
11'h0b6: data = 8'b01111000; // ****
11'h0b7: data = 8'b11001100; // ** **
11'h0b8: data = 8'b11001100; // ** **
11'h0b9: data = 8'b11001100; // ** **
11'h0ba: data = 8'b11001100; // ** **
11'h0bb: data = 8'b01111000; // ****
11'h0bc: data = 8'b00000000; //
11'h0bd: data = 8'b00000000; //
11'h0be: data = 8'b00000000; //
11'h0bf: data = 8'b00000000; //
//code x0c
11'h0c0: data = 8'b00000000; //
11'h0c1: data = 8'b00000000; //
11'h0c2: data = 8'b00111100; // ****
11'h0c3: data = 8'b01100110; // ** **
11'h0c4: data = 8'b01100110; // ** **
11'h0c5: data = 8'b01100110; // ** **
11'h0c6: data = 8'b01100110; // ** **
11'h0c7: data = 8'b00111100; // ****
11'h0c8: data = 8'b00011000; // **
11'h0c9: data = 8'b01111110; // ******
11'h0ca: data = 8'b00011000; // **
11'h0cb: data = 8'b00011000; // **
11'h0cc: data = 8'b00000000; //
11'h0cd: data = 8'b00000000; //
11'h0ce: data = 8'b00000000; //
11'h0cf: data = 8'b00000000; //
//code x0d
11'h0d0: data = 8'b00000000; //
11'h0d1: data = 8'b00000000; //
11'h0d2: data = 8'b00111111; // ******
11'h0d3: data = 8'b00110011; // ** **
11'h0d4: data = 8'b00111111; // ******
11'h0d5: data = 8'b00110000; // **
11'h0d6: data = 8'b00110000; // **
11'h0d7: data = 8'b00110000; // **
11'h0d8: data = 8'b00110000; // **
11'h0d9: data = 8'b01110000; // ***
11'h0da: data = 8'b11110000; // ****
11'h0db: data = 8'b11100000; // ***
11'h0dc: data = 8'b00000000; //
11'h0dd: data = 8'b00000000; //
11'h0de: data = 8'b00000000; //
11'h0df: data = 8'b00000000; //
//code x0e
11'h0e0: data = 8'b00000000; //
11'h0e1: data = 8'b00000000; //
11'h0e2: data = 8'b01111111; // *******
11'h0e3: data = 8'b01100011; // ** **
11'h0e4: data = 8'b01111111; // *******
11'h0e5: data = 8'b01100011; // ** **
11'h0e6: data = 8'b01100011; // ** **
11'h0e7: data = 8'b01100011; // ** **
11'h0e8: data = 8'b01100011; // ** **
11'h0e9: data = 8'b01100111; // ** ***
11'h0ea: data = 8'b11100111; // *** ***
11'h0eb: data = 8'b11100110; // *** **
11'h0ec: data = 8'b11000000; // **
11'h0ed: data = 8'b00000000; //
11'h0ee: data = 8'b00000000; //
11'h0ef: data = 8'b00000000; //
//code x0f
11'h0f0: data = 8'b00000000; //
11'h0f1: data = 8'b00000000; //
11'h0f2: data = 8'b00000000; //
11'h0f3: data = 8'b00011000; // **
11'h0f4: data = 8'b00011000; // **
11'h0f5: data = 8'b11011011; // ** ** **
11'h0f6: data = 8'b00111100; // ****
11'h0f7: data = 8'b11100111; // *** ***
11'h0f8: data = 8'b00111100; // ****
11'h0f9: data = 8'b11011011; // ** ** **
11'h0fa: data = 8'b00011000; // **
11'h0fb: data = 8'b00011000; // **
11'h0fc: data = 8'b00000000; //
11'h0fd: data = 8'b00000000; //
11'h0fe: data = 8'b00000000; //
11'h0ff: data = 8'b00000000; //
//code x10
11'h100: data = 8'b00000000; //
11'h101: data = 8'b10000000; // *
11'h102: data = 8'b11000000; // **
11'h103: data = 8'b11100000; // ***
11'h104: data = 8'b11110000; // ****
11'h105: data = 8'b11111000; // *****
11'h106: data = 8'b11111110; // *******
11'h107: data = 8'b11111000; // *****
11'h108: data = 8'b11110000; // ****
11'h109: data = 8'b11100000; // ***
11'h10a: data = 8'b11000000; // **
11'h10b: data = 8'b10000000; // *
11'h10c: data = 8'b00000000; //
11'h10d: data = 8'b00000000; //
11'h10e: data = 8'b00000000; //
11'h10f: data = 8'b00000000; //
//code x11
11'h110: data = 8'b00000000; //
11'h111: data = 8'b00000010; // *
11'h112: data = 8'b00000110; // **
11'h113: data = 8'b00001110; // ***
11'h114: data = 8'b00011110; // ****
11'h115: data = 8'b00111110; // *****
11'h116: data = 8'b11111110; // *******
11'h117: data = 8'b00111110; // *****
11'h118: data = 8'b00011110; // ****
11'h119: data = 8'b00001110; // ***
11'h11a: data = 8'b00000110; // **
11'h11b: data = 8'b00000010; // *
11'h11c: data = 8'b00000000; //
11'h11d: data = 8'b00000000; //
11'h11e: data = 8'b00000000; //
11'h11f: data = 8'b00000000; //
//code x12
11'h120: data = 8'b00000000; //
11'h121: data = 8'b00000000; //
11'h122: data = 8'b00011000; // **
11'h123: data = 8'b00111100; // ****
11'h124: data = 8'b01111110; // ******
11'h125: data = 8'b00011000; // **
11'h126: data = 8'b00011000; // **
11'h127: data = 8'b00011000; // **
11'h128: data = 8'b01111110; // ******
11'h129: data = 8'b00111100; // ****
11'h12a: data = 8'b00011000; // **
11'h12b: data = 8'b00000000; //
11'h12c: data = 8'b00000000; //
11'h12d: data = 8'b00000000; //
11'h12e: data = 8'b00000000; //
11'h12f: data = 8'b00000000; //
//code x13
11'h130: data = 8'b00000000; //
11'h131: data = 8'b00000000; //
11'h132: data = 8'b01100110; // ** **
11'h133: data = 8'b01100110; // ** **
11'h134: data = 8'b01100110; // ** **
11'h135: data = 8'b01100110; // ** **
11'h136: data = 8'b01100110; // ** **
11'h137: data = 8'b01100110; // ** **
11'h138: data = 8'b01100110; // ** **
11'h139: data = 8'b00000000; //
11'h13a: data = 8'b01100110; // ** **
11'h13b: data = 8'b01100110; // ** **
11'h13c: data = 8'b00000000; //
11'h13d: data = 8'b00000000; //
11'h13e: data = 8'b00000000; //
11'h13f: data = 8'b00000000; //
//code x14
11'h140: data = 8'b00000000; //
11'h141: data = 8'b00000000; //
11'h142: data = 8'b01111111; // *******
11'h143: data = 8'b11011011; // ** ** **
11'h144: data = 8'b11011011; // ** ** **
11'h145: data = 8'b11011011; // ** ** **
11'h146: data = 8'b01111011; // **** **
11'h147: data = 8'b00011011; // ** **
11'h148: data = 8'b00011011; // ** **
11'h149: data = 8'b00011011; // ** **
11'h14a: data = 8'b00011011; // ** **
11'h14b: data = 8'b00011011; // ** **
11'h14c: data = 8'b00000000; //
11'h14d: data = 8'b00000000; //
11'h14e: data = 8'b00000000; //
11'h14f: data = 8'b00000000; //
//code x15
11'h150: data = 8'b00000000; //
11'h151: data = 8'b01111100; // *****
11'h152: data = 8'b11000110; // ** **
11'h153: data = 8'b01100000; // **
11'h154: data = 8'b00111000; // ***
11'h155: data = 8'b01101100; // ** **
11'h156: data = 8'b11000110; // ** **
11'h157: data = 8'b11000110; // ** **
11'h158: data = 8'b01101100; // ** **
11'h159: data = 8'b00111000; // ***
11'h15a: data = 8'b00001100; // **
11'h15b: data = 8'b11000110; // ** **
11'h15c: data = 8'b01111100; // *****
11'h15d: data = 8'b00000000; //
11'h15e: data = 8'b00000000; //
11'h15f: data = 8'b00000000; //
//code x16
11'h160: data = 8'b00000000; //
11'h161: data = 8'b00000000; //
11'h162: data = 8'b00000000; //
11'h163: data = 8'b00000000; //
11'h164: data = 8'b00000000; //
11'h165: data = 8'b00000000; //
11'h166: data = 8'b00000000; //
11'h167: data = 8'b00000000; //
11'h168: data = 8'b11111110; // *******
11'h169: data = 8'b11111110; // *******
11'h16a: data = 8'b11111110; // *******
11'h16b: data = 8'b11111110; // *******
11'h16c: data = 8'b00000000; //
11'h16d: data = 8'b00000000; //
11'h16e: data = 8'b00000000; //
11'h16f: data = 8'b00000000; //
//code x17
11'h170: data = 8'b00000000; //
11'h171: data = 8'b00000000; //
11'h172: data = 8'b00011000; // **
11'h173: data = 8'b00111100; // ****
11'h174: data = 8'b01111110; // ******
11'h175: data = 8'b00011000; // **
11'h176: data = 8'b00011000; // **
11'h177: data = 8'b00011000; // **
11'h178: data = 8'b01111110; // ******
11'h179: data = 8'b00111100; // ****
11'h17a: data = 8'b00011000; // **
11'h17b: data = 8'b01111110; // ******
11'h17c: data = 8'b00110000; //
11'h17d: data = 8'b00000000; //
11'h17e: data = 8'b00000000; //
11'h17f: data = 8'b00000000; //
//code x18
11'h180: data = 8'b00000000; //
11'h181: data = 8'b00000000; //
11'h182: data = 8'b00011000; // **
11'h183: data = 8'b00111100; // ****
11'h184: data = 8'b01111110; // ******
11'h185: data = 8'b00011000; // **
11'h186: data = 8'b00011000; // **
11'h187: data = 8'b00011000; // **
11'h188: data = 8'b00011000; // **
11'h189: data = 8'b00011000; // **
11'h18a: data = 8'b00011000; // **
11'h18b: data = 8'b00011000; // **
11'h18c: data = 8'b00000000; //
11'h18d: data = 8'b00000000; //
11'h18e: data = 8'b00000000; //
11'h18f: data = 8'b00000000; //
//code x19
11'h190: data = 8'b00000000; //
11'h191: data = 8'b00000000; //
11'h192: data = 8'b00011000; // **
11'h193: data = 8'b00011000; // **
11'h194: data = 8'b00011000; // **
11'h195: data = 8'b00011000; // **
11'h196: data = 8'b00011000; // **
11'h197: data = 8'b00011000; // **
11'h198: data = 8'b00011000; // **
11'h199: data = 8'b01111110; // ******
11'h19a: data = 8'b00111100; // ****
11'h19b: data = 8'b00011000; // **
11'h19c: data = 8'b00000000; //
11'h19d: data = 8'b00000000; //
11'h19e: data = 8'b00000000; //
11'h19f: data = 8'b00000000; //
//code x1a
11'h1a0: data = 8'b00000000; //
11'h1a1: data = 8'b00000000; //
11'h1a2: data = 8'b00000000; //
11'h1a3: data = 8'b00000000; //
11'h1a4: data = 8'b00000000; //
11'h1a5: data = 8'b00011000; // **
11'h1a6: data = 8'b00001100; // **
11'h1a7: data = 8'b11111110; // *******
11'h1a8: data = 8'b00001100; // **
11'h1a9: data = 8'b00011000; // **
11'h1aa: data = 8'b00000000; //
11'h1ab: data = 8'b00000000; //
11'h1ac: data = 8'b00000000; //
11'h1ad: data = 8'b00000000; //
11'h1ae: data = 8'b00000000; //
11'h1af: data = 8'b00000000; //
//code x1b
11'h1b0: data = 8'b00000000; //
11'h1b1: data = 8'b00000000; //
11'h1b2: data = 8'b00000000; //
11'h1b3: data = 8'b00000000; //
11'h1b4: data = 8'b00000000; //
11'h1b5: data = 8'b00110000; // **
11'h1b6: data = 8'b01100000; // **
11'h1b7: data = 8'b11111110; // *******
11'h1b8: data = 8'b01100000; // **
11'h1b9: data = 8'b00110000; // **
11'h1ba: data = 8'b00000000; //
11'h1bb: data = 8'b00000000; //
11'h1bc: data = 8'b00000000; //
11'h1bd: data = 8'b00000000; //
11'h1be: data = 8'b00000000; //
11'h1bf: data = 8'b00000000; //
//code x1c
11'h1c0: data = 8'b00000000; //
11'h1c1: data = 8'b00000000; //
11'h1c2: data = 8'b00000000; //
11'h1c3: data = 8'b00000000; //
11'h1c4: data = 8'b00000000; //
11'h1c5: data = 8'b00000000; //
11'h1c6: data = 8'b11000000; // **
11'h1c7: data = 8'b11000000; // **
11'h1c8: data = 8'b11000000; // **
11'h1c9: data = 8'b11111110; // *******
11'h1ca: data = 8'b00000000; //
11'h1cb: data = 8'b00000000; //
11'h1cc: data = 8'b00000000; //
11'h1cd: data = 8'b00000000; //
11'h1ce: data = 8'b00000000; //
11'h1cf: data = 8'b00000000; //
//code x1d
11'h1d0: data = 8'b00000000; //
11'h1d1: data = 8'b00000000; //
11'h1d2: data = 8'b00000000; //
11'h1d3: data = 8'b00000000; //
11'h1d4: data = 8'b00000000; //
11'h1d5: data = 8'b00100100; // * *
11'h1d6: data = 8'b01100110; // ** **
11'h1d7: data = 8'b11111111; // ********
11'h1d8: data = 8'b01100110; // ** **
11'h1d9: data = 8'b00100100; // * *
11'h1da: data = 8'b00000000; //
11'h1db: data = 8'b00000000; //
11'h1dc: data = 8'b00000000; //
11'h1dd: data = 8'b00000000; //
11'h1de: data = 8'b00000000; //
11'h1df: data = 8'b00000000; //
//code x1e
11'h1e0: data = 8'b00000000; //
11'h1e1: data = 8'b00000000; //
11'h1e2: data = 8'b00000000; //
11'h1e3: data = 8'b00000000; //
11'h1e4: data = 8'b00010000; // *
11'h1e5: data = 8'b00111000; // ***
11'h1e6: data = 8'b00111000; // ***
11'h1e7: data = 8'b01111100; // *****
11'h1e8: data = 8'b01111100; // *****
11'h1e9: data = 8'b11111110; // *******
11'h1ea: data = 8'b11111110; // *******
11'h1eb: data = 8'b00000000; //
11'h1ec: data = 8'b00000000; //
11'h1ed: data = 8'b00000000; //
11'h1ee: data = 8'b00000000; //
11'h1ef: data = 8'b00000000; //
//code x1f
11'h1f0: data = 8'b00000000; //
11'h1f1: data = 8'b00000000; //
11'h1f2: data = 8'b00000000; //
11'h1f3: data = 8'b00000000; //
11'h1f4: data = 8'b11111110; // *******
11'h1f5: data = 8'b11111110; // *******
11'h1f6: data = 8'b01111100; // *****
11'h1f7: data = 8'b01111100; // *****
11'h1f8: data = 8'b00111000; // ***
11'h1f9: data = 8'b00111000; // ***
11'h1fa: data = 8'b00010000; // *
11'h1fb: data = 8'b00000000; //
11'h1fc: data = 8'b00000000; //
11'h1fd: data = 8'b00000000; //
11'h1fe: data = 8'b00000000; //
11'h1ff: data = 8'b00000000; //
//code x20
11'h200: data = 8'b00000000; //
11'h201: data = 8'b00000000; //
11'h202: data = 8'b00000000; //
11'h203: data = 8'b00000000; //
11'h204: data = 8'b00000000; //
11'h205: data = 8'b00000000; //
11'h206: data = 8'b00000000; //
11'h207: data = 8'b00000000; //
11'h208: data = 8'b00000000; //
11'h209: data = 8'b00000000; //
11'h20a: data = 8'b00000000; //
11'h20b: data = 8'b00000000; //
11'h20c: data = 8'b00000000; //
11'h20d: data = 8'b00000000; //
11'h20e: data = 8'b00000000; //
11'h20f: data = 8'b00000000; //
//code x21
11'h210: data = 8'b00000000; //
11'h211: data = 8'b00000000; //
11'h212: data = 8'b00011000; // **
11'h213: data = 8'b00111100; // ****
11'h214: data = 8'b00111100; // ****
11'h215: data = 8'b00111100; // ****
11'h216: data = 8'b00011000; // **
11'h217: data = 8'b00011000; // **
11'h218: data = 8'b00011000; // **
11'h219: data = 8'b00000000; //
11'h21a: data = 8'b00011000; // **
11'h21b: data = 8'b00011000; // **
11'h21c: data = 8'b00000000; //
11'h21d: data = 8'b00000000; //
11'h21e: data = 8'b00000000; //
11'h21f: data = 8'b00000000; //
//code x22
11'h220: data = 8'b00000000; //
11'h221: data = 8'b01100110; // ** **
11'h222: data = 8'b01100110; // ** **
11'h223: data = 8'b01100110; // ** **
11'h224: data = 8'b00100100; // * *
11'h225: data = 8'b00000000; //
11'h226: data = 8'b00000000; //
11'h227: data = 8'b00000000; //
11'h228: data = 8'b00000000; //
11'h229: data = 8'b00000000; //
11'h22a: data = 8'b00000000; //
11'h22b: data = 8'b00000000; //
11'h22c: data = 8'b00000000; //
11'h22d: data = 8'b00000000; //
11'h22e: data = 8'b00000000; //
11'h22f: data = 8'b00000000; //
//code x23
11'h230: data = 8'b00000000; //
11'h231: data = 8'b00000000; //
11'h232: data = 8'b00000000; //
11'h233: data = 8'b01101100; // ** **
11'h234: data = 8'b01101100; // ** **
11'h235: data = 8'b11111110; // *******
11'h236: data = 8'b01101100; // ** **
11'h237: data = 8'b01101100; // ** **
11'h238: data = 8'b01101100; // ** **
11'h239: data = 8'b11111110; // *******
11'h23a: data = 8'b01101100; // ** **
11'h23b: data = 8'b01101100; // ** **
11'h23c: data = 8'b00000000; //
11'h23d: data = 8'b00000000; //
11'h23e: data = 8'b00000000; //
11'h23f: data = 8'b00000000; //
//code x24
11'h240: data = 8'b00011000; // **
11'h241: data = 8'b00011000; // **
11'h242: data = 8'b01111100; // *****
11'h243: data = 8'b11000110; // ** **
11'h244: data = 8'b11000010; // ** *
11'h245: data = 8'b11000000; // **
11'h246: data = 8'b01111100; // *****
11'h247: data = 8'b00000110; // **
11'h248: data = 8'b00000110; // **
11'h249: data = 8'b10000110; // * **
11'h24a: data = 8'b11000110; // ** **
11'h24b: data = 8'b01111100; // *****
11'h24c: data = 8'b00011000; // **
11'h24d: data = 8'b00011000; // **
11'h24e: data = 8'b00000000; //
11'h24f: data = 8'b00000000; //
//code x25
11'h250: data = 8'b00000000; //
11'h251: data = 8'b00000000; //
11'h252: data = 8'b00000000; //
11'h253: data = 8'b00000000; //
11'h254: data = 8'b11000010; // ** *
11'h255: data = 8'b11000110; // ** **
11'h256: data = 8'b00001100; // **
11'h257: data = 8'b00011000; // **
11'h258: data = 8'b00110000; // **
11'h259: data = 8'b01100000; // **
11'h25a: data = 8'b11000110; // ** **
11'h25b: data = 8'b10000110; // * **
11'h25c: data = 8'b00000000; //
11'h25d: data = 8'b00000000; //
11'h25e: data = 8'b00000000; //
11'h25f: data = 8'b00000000; //
//code x26
11'h260: data = 8'b00000000; //
11'h261: data = 8'b00000000; //
11'h262: data = 8'b00111000; // ***
11'h263: data = 8'b01101100; // ** **
11'h264: data = 8'b01101100; // ** **
11'h265: data = 8'b00111000; // ***
11'h266: data = 8'b01110110; // *** **
11'h267: data = 8'b11011100; // ** ***
11'h268: data = 8'b11001100; // ** **
11'h269: data = 8'b11001100; // ** **
11'h26a: data = 8'b11001100; // ** **
11'h26b: data = 8'b01110110; // *** **
11'h26c: data = 8'b00000000; //
11'h26d: data = 8'b00000000; //
11'h26e: data = 8'b00000000; //
11'h26f: data = 8'b00000000; //
//code x27
11'h270: data = 8'b00000000; //
11'h271: data = 8'b00110000; // **
11'h272: data = 8'b00110000; // **
11'h273: data = 8'b00110000; // **
11'h274: data = 8'b01100000; // **
11'h275: data = 8'b00000000; //
11'h276: data = 8'b00000000; //
11'h277: data = 8'b00000000; //
11'h278: data = 8'b00000000; //
11'h279: data = 8'b00000000; //
11'h27a: data = 8'b00000000; //
11'h27b: data = 8'b00000000; //
11'h27c: data = 8'b00000000; //
11'h27d: data = 8'b00000000; //
11'h27e: data = 8'b00000000; //
11'h27f: data = 8'b00000000; //
//code x28
11'h280: data = 8'b00000000; //
11'h281: data = 8'b00000000; //
11'h282: data = 8'b00001100; // **
11'h283: data = 8'b00011000; // **
11'h284: data = 8'b00110000; // **
11'h285: data = 8'b00110000; // **
11'h286: data = 8'b00110000; // **
11'h287: data = 8'b00110000; // **
11'h288: data = 8'b00110000; // **
11'h289: data = 8'b00110000; // **
11'h28a: data = 8'b00011000; // **
11'h28b: data = 8'b00001100; // **
11'h28c: data = 8'b00000000; //
11'h28d: data = 8'b00000000; //
11'h28e: data = 8'b00000000; //
11'h28f: data = 8'b00000000; //
//code x29
11'h290: data = 8'b00000000; //
11'h291: data = 8'b00000000; //
11'h292: data = 8'b00110000; // **
11'h293: data = 8'b00011000; // **
11'h294: data = 8'b00001100; // **
11'h295: data = 8'b00001100; // **
11'h296: data = 8'b00001100; // **
11'h297: data = 8'b00001100; // **
11'h298: data = 8'b00001100; // **
11'h299: data = 8'b00001100; // **
11'h29a: data = 8'b00011000; // **
11'h29b: data = 8'b00110000; // **
11'h29c: data = 8'b00000000; //
11'h29d: data = 8'b00000000; //
11'h29e: data = 8'b00000000; //
11'h29f: data = 8'b00000000; //
//code x2a
11'h2a0: data = 8'b00000000; //
11'h2a1: data = 8'b00000000; //
11'h2a2: data = 8'b00000000; //
11'h2a3: data = 8'b00000000; //
11'h2a4: data = 8'b00000000; //
11'h2a5: data = 8'b01100110; // ** **
11'h2a6: data = 8'b00111100; // ****
11'h2a7: data = 8'b11111111; // ********
11'h2a8: data = 8'b00111100; // ****
11'h2a9: data = 8'b01100110; // ** **
11'h2aa: data = 8'b00000000; //
11'h2ab: data = 8'b00000000; //
11'h2ac: data = 8'b00000000; //
11'h2ad: data = 8'b00000000; //
11'h2ae: data = 8'b00000000; //
11'h2af: data = 8'b00000000; //
//code x2b
11'h2b0: data = 8'b00000000; //
11'h2b1: data = 8'b00000000; //
11'h2b2: data = 8'b00000000; //
11'h2b3: data = 8'b00000000; //
11'h2b4: data = 8'b00000000; //
11'h2b5: data = 8'b00011000; // **
11'h2b6: data = 8'b00011000; // **
11'h2b7: data = 8'b01111110; // ******
11'h2b8: data = 8'b00011000; // **
11'h2b9: data = 8'b00011000; // **
11'h2ba: data = 8'b00000000; //
11'h2bb: data = 8'b00000000; //
11'h2bc: data = 8'b00000000; //
11'h2bd: data = 8'b00000000; //
11'h2be: data = 8'b00000000; //
11'h2bf: data = 8'b00000000; //
//code x2c
11'h2c0: data = 8'b00000000; //
11'h2c1: data = 8'b00000000; //
11'h2c2: data = 8'b00000000; //
11'h2c3: data = 8'b00000000; //
11'h2c4: data = 8'b00000000; //
11'h2c5: data = 8'b00000000; //
11'h2c6: data = 8'b00000000; //
11'h2c7: data = 8'b00000000; //
11'h2c8: data = 8'b00000000; //
11'h2c9: data = 8'b00011000; // **
11'h2ca: data = 8'b00011000; // **
11'h2cb: data = 8'b00011000; // **
11'h2cc: data = 8'b00110000; // **
11'h2cd: data = 8'b00000000; //
11'h2ce: data = 8'b00000000; //
11'h2cf: data = 8'b00000000; //
//code x2d
11'h2d0: data = 8'b00000000; //
11'h2d1: data = 8'b00000000; //
11'h2d2: data = 8'b00000000; //
11'h2d3: data = 8'b00000000; //
11'h2d4: data = 8'b00000000; //
11'h2d5: data = 8'b00000000; //
11'h2d6: data = 8'b00000000; //
11'h2d7: data = 8'b01111110; // ******
11'h2d8: data = 8'b00000000; //
11'h2d9: data = 8'b00000000; //
11'h2da: data = 8'b00000000; //
11'h2db: data = 8'b00000000; //
11'h2dc: data = 8'b00000000; //
11'h2dd: data = 8'b00000000; //
11'h2de: data = 8'b00000000; //
11'h2df: data = 8'b00000000; //
//code x2e
11'h2e0: data = 8'b00000000; //
11'h2e1: data = 8'b00000000; //
11'h2e2: data = 8'b00000000; //
11'h2e3: data = 8'b00000000; //
11'h2e4: data = 8'b00000000; //
11'h2e5: data = 8'b00000000; //
11'h2e6: data = 8'b00000000; //
11'h2e7: data = 8'b00000000; //
11'h2e8: data = 8'b00000000; //
11'h2e9: data = 8'b00000000; //
11'h2ea: data = 8'b00011000; // **
11'h2eb: data = 8'b00011000; // **
11'h2ec: data = 8'b00000000; //
11'h2ed: data = 8'b00000000; //
11'h2ee: data = 8'b00000000; //
11'h2ef: data = 8'b00000000; //
//code x2f
11'h2f0: data = 8'b00000000; //
11'h2f1: data = 8'b00000000; //
11'h2f2: data = 8'b00000000; //
11'h2f3: data = 8'b00000000; //
11'h2f4: data = 8'b00000010; // *
11'h2f5: data = 8'b00000110; // **
11'h2f6: data = 8'b00001100; // **
11'h2f7: data = 8'b00011000; // **
11'h2f8: data = 8'b00110000; // **
11'h2f9: data = 8'b01100000; // **
11'h2fa: data = 8'b11000000; // **
11'h2fb: data = 8'b10000000; // *
11'h2fc: data = 8'b00000000; //
11'h2fd: data = 8'b00000000; //
11'h2fe: data = 8'b00000000; //
11'h2ff: data = 8'b00000000; //
//code x30
11'h300: data = 8'b00000000; //
11'h301: data = 8'b00000000; //
11'h302: data = 8'b01111100; // *****
11'h303: data = 8'b11000110; // ** **
11'h304: data = 8'b11000110; // ** **
11'h305: data = 8'b11001110; // ** ***
11'h306: data = 8'b11011110; // ** ****
11'h307: data = 8'b11110110; // **** **
11'h308: data = 8'b11100110; // *** **
11'h309: data = 8'b11000110; // ** **
11'h30a: data = 8'b11000110; // ** **
11'h30b: data = 8'b01111100; // *****
11'h30c: data = 8'b00000000; //
11'h30d: data = 8'b00000000; //
11'h30e: data = 8'b00000000; //
11'h30f: data = 8'b00000000; //
//code x31
11'h310: data = 8'b00000000; //
11'h311: data = 8'b00000000; //
11'h312: data = 8'b00011000; //
11'h313: data = 8'b00111000; //
11'h314: data = 8'b01111000; // **
11'h315: data = 8'b00011000; // ***
11'h316: data = 8'b00011000; // ****
11'h317: data = 8'b00011000; // **
11'h318: data = 8'b00011000; // **
11'h319: data = 8'b00011000; // **
11'h31a: data = 8'b00011000; // **
11'h31b: data = 8'b01111110; // **
11'h31c: data = 8'b00000000; // **
11'h31d: data = 8'b00000000; // ******
11'h31e: data = 8'b00000000; //
11'h31f: data = 8'b00000000; //
//code x32
11'h320: data = 8'b00000000; //
11'h321: data = 8'b00000000; //
11'h322: data = 8'b01111100; // *****
11'h323: data = 8'b11000110; // ** **
11'h324: data = 8'b00000110; // **
11'h325: data = 8'b00001100; // **
11'h326: data = 8'b00011000; // **
11'h327: data = 8'b00110000; // **
11'h328: data = 8'b01100000; // **
11'h329: data = 8'b11000000; // **
11'h32a: data = 8'b11000110; // ** **
11'h32b: data = 8'b11111110; // *******
11'h32c: data = 8'b00000000; //
11'h32d: data = 8'b00000000; //
11'h32e: data = 8'b00000000; //
11'h32f: data = 8'b00000000; //
//code x33
11'h330: data = 8'b00000000; //
11'h331: data = 8'b00000000; //
11'h332: data = 8'b01111100; // *****
11'h333: data = 8'b11000110; // ** **
11'h334: data = 8'b00000110; // **
11'h335: data = 8'b00000110; // **
11'h336: data = 8'b00111100; // ****
11'h337: data = 8'b00000110; // **
11'h338: data = 8'b00000110; // **
11'h339: data = 8'b00000110; // **
11'h33a: data = 8'b11000110; // ** **
11'h33b: data = 8'b01111100; // *****
11'h33c: data = 8'b00000000; //
11'h33d: data = 8'b00000000; //
11'h33e: data = 8'b00000000; //
11'h33f: data = 8'b00000000; //
//code x34
11'h340: data = 8'b00000000; //
11'h341: data = 8'b00000000; //
11'h342: data = 8'b00001100; // **
11'h343: data = 8'b00011100; // ***
11'h344: data = 8'b00111100; // ****
11'h345: data = 8'b01101100; // ** **
11'h346: data = 8'b11001100; // ** **
11'h347: data = 8'b11111110; // *******
11'h348: data = 8'b00001100; // **
11'h349: data = 8'b00001100; // **
11'h34a: data = 8'b00001100; // **
11'h34b: data = 8'b00011110; // ****
11'h34c: data = 8'b00000000; //
11'h34d: data = 8'b00000000; //
11'h34e: data = 8'b00000000; //
11'h34f: data = 8'b00000000; //
//code x35
11'h350: data = 8'b00000000; //
11'h351: data = 8'b00000000; //
11'h352: data = 8'b11111110; // *******
11'h353: data = 8'b11000000; // **
11'h354: data = 8'b11000000; // **
11'h355: data = 8'b11000000; // **
11'h356: data = 8'b11111100; // ******
11'h357: data = 8'b00000110; // **
11'h358: data = 8'b00000110; // **
11'h359: data = 8'b00000110; // **
11'h35a: data = 8'b11000110; // ** **
11'h35b: data = 8'b01111100; // *****
11'h35c: data = 8'b00000000; //
11'h35d: data = 8'b00000000; //
11'h35e: data = 8'b00000000; //
11'h35f: data = 8'b00000000; //
//code x36
11'h360: data = 8'b00000000; //
11'h361: data = 8'b00000000; //
11'h362: data = 8'b00111000; // ***
11'h363: data = 8'b01100000; // **
11'h364: data = 8'b11000000; // **
11'h365: data = 8'b11000000; // **
11'h366: data = 8'b11111100; // ******
11'h367: data = 8'b11000110; // ** **
11'h368: data = 8'b11000110; // ** **
11'h369: data = 8'b11000110; // ** **
11'h36a: data = 8'b11000110; // ** **
11'h36b: data = 8'b01111100; // *****
11'h36c: data = 8'b00000000; //
11'h36d: data = 8'b00000000; //
11'h36e: data = 8'b00000000; //
11'h36f: data = 8'b00000000; //
//code x37
11'h370: data = 8'b00000000; //
11'h371: data = 8'b00000000; //
11'h372: data = 8'b11111110; // *******
11'h373: data = 8'b11000110; // ** **
11'h374: data = 8'b00000110; // **
11'h375: data = 8'b00000110; // **
11'h376: data = 8'b00001100; // **
11'h377: data = 8'b00011000; // **
11'h378: data = 8'b00110000; // **
11'h379: data = 8'b00110000; // **
11'h37a: data = 8'b00110000; // **
11'h37b: data = 8'b00110000; // **
11'h37c: data = 8'b00000000; //
11'h37d: data = 8'b00000000; //
11'h37e: data = 8'b00000000; //
11'h37f: data = 8'b00000000; //
//code x38
11'h380: data = 8'b00000000; //
11'h381: data = 8'b00000000; //
11'h382: data = 8'b01111100; // *****
11'h383: data = 8'b11000110; // ** **
11'h384: data = 8'b11000110; // ** **
11'h385: data = 8'b11000110; // ** **
11'h386: data = 8'b01111100; // *****
11'h387: data = 8'b11000110; // ** **
11'h388: data = 8'b11000110; // ** **
11'h389: data = 8'b11000110; // ** **
11'h38a: data = 8'b11000110; // ** **
11'h38b: data = 8'b01111100; // *****
11'h38c: data = 8'b00000000; //
11'h38d: data = 8'b00000000; //
11'h38e: data = 8'b00000000; //
11'h38f: data = 8'b00000000; //
//code x39
11'h390: data = 8'b00000000; //
11'h391: data = 8'b00000000; //
11'h392: data = 8'b01111100; // *****
11'h393: data = 8'b11000110; // ** **
11'h394: data = 8'b11000110; // ** **
11'h395: data = 8'b11000110; // ** **
11'h396: data = 8'b01111110; // ******
11'h397: data = 8'b00000110; // **
11'h398: data = 8'b00000110; // **
11'h399: data = 8'b00000110; // **
11'h39a: data = 8'b00001100; // **
11'h39b: data = 8'b01111000; // ****
11'h39c: data = 8'b00000000; //
11'h39d: data = 8'b00000000; //
11'h39e: data = 8'b00000000; //
11'h39f: data = 8'b00000000; //
//code x3a
11'h3a0: data = 8'b00000000; //
11'h3a1: data = 8'b00000000; //
11'h3a2: data = 8'b00000000; //
11'h3a3: data = 8'b00000000; //
11'h3a4: data = 8'b00011000; // **
11'h3a5: data = 8'b00011000; // **
11'h3a6: data = 8'b00000000; //
11'h3a7: data = 8'b00000000; //
11'h3a8: data = 8'b00000000; //
11'h3a9: data = 8'b00011000; // **
11'h3aa: data = 8'b00011000; // **
11'h3ab: data = 8'b00000000; //
11'h3ac: data = 8'b00000000; //
11'h3ad: data = 8'b00000000; //
11'h3ae: data = 8'b00000000; //
11'h3af: data = 8'b00000000; //
//code x3b
11'h3b0: data = 8'b00000000; //
11'h3b1: data = 8'b00000000; //
11'h3b2: data = 8'b00000000; //
11'h3b3: data = 8'b00000000; //
11'h3b4: data = 8'b00011000; // **
11'h3b5: data = 8'b00011000; // **
11'h3b6: data = 8'b00000000; //
11'h3b7: data = 8'b00000000; //
11'h3b8: data = 8'b00000000; //
11'h3b9: data = 8'b00011000; // **
11'h3ba: data = 8'b00011000; // **
11'h3bb: data = 8'b00110000; // **
11'h3bc: data = 8'b00000000; //
11'h3bd: data = 8'b00000000; //
11'h3be: data = 8'b00000000; //
11'h3bf: data = 8'b00000000; //
//code x3c
11'h3c0: data = 8'b00000000; //
11'h3c1: data = 8'b00000000; //
11'h3c2: data = 8'b00000000; //
11'h3c3: data = 8'b00000110; // **
11'h3c4: data = 8'b00001100; // **
11'h3c5: data = 8'b00011000; // **
11'h3c6: data = 8'b00110000; // **
11'h3c7: data = 8'b01100000; // **
11'h3c8: data = 8'b00110000; // **
11'h3c9: data = 8'b00011000; // **
11'h3ca: data = 8'b00001100; // **
11'h3cb: data = 8'b00000110; // **
11'h3cc: data = 8'b00000000; //
11'h3cd: data = 8'b00000000; //
11'h3ce: data = 8'b00000000; //
11'h3cf: data = 8'b00000000; //
//code x3d
11'h3d0: data = 8'b00000000; //
11'h3d1: data = 8'b00000000; //
11'h3d2: data = 8'b00000000; //
11'h3d3: data = 8'b00000000; //
11'h3d4: data = 8'b00000000; //
11'h3d5: data = 8'b01111110; // ******
11'h3d6: data = 8'b00000000; //
11'h3d7: data = 8'b00000000; //
11'h3d8: data = 8'b01111110; // ******
11'h3d9: data = 8'b00000000; //
11'h3da: data = 8'b00000000; //
11'h3db: data = 8'b00000000; //
11'h3dc: data = 8'b00000000; //
11'h3dd: data = 8'b00000000; //
11'h3de: data = 8'b00000000; //
11'h3df: data = 8'b00000000; //
//code x3e
11'h3e0: data = 8'b00000000; //
11'h3e1: data = 8'b00000000; //
11'h3e2: data = 8'b00000000; //
11'h3e3: data = 8'b01100000; // **
11'h3e4: data = 8'b00110000; // **
11'h3e5: data = 8'b00011000; // **
11'h3e6: data = 8'b00001100; // **
11'h3e7: data = 8'b00000110; // **
11'h3e8: data = 8'b00001100; // **
11'h3e9: data = 8'b00011000; // **
11'h3ea: data = 8'b00110000; // **
11'h3eb: data = 8'b01100000; // **
11'h3ec: data = 8'b00000000; //
11'h3ed: data = 8'b00000000; //
11'h3ee: data = 8'b00000000; //
11'h3ef: data = 8'b00000000; //
//code x3f
11'h3f0: data = 8'b00000000; //
11'h3f1: data = 8'b00000000; //
11'h3f2: data = 8'b01111100; // *****
11'h3f3: data = 8'b11000110; // ** **
11'h3f4: data = 8'b11000110; // ** **
11'h3f5: data = 8'b00001100; // **
11'h3f6: data = 8'b00011000; // **
11'h3f7: data = 8'b00011000; // **
11'h3f8: data = 8'b00011000; // **
11'h3f9: data = 8'b00000000; //
11'h3fa: data = 8'b00011000; // **
11'h3fb: data = 8'b00011000; // **
11'h3fc: data = 8'b00000000; //
11'h3fd: data = 8'b00000000; //
11'h3fe: data = 8'b00000000; //
11'h3ff: data = 8'b00000000; //
//code x40
11'h400: data = 8'b00000000; //
11'h401: data = 8'b00000000; //
11'h402: data = 8'b01111100; // *****
11'h403: data = 8'b11000110; // ** **
11'h404: data = 8'b11000110; // ** **
11'h405: data = 8'b11000110; // ** **
11'h406: data = 8'b11011110; // ** ****
11'h407: data = 8'b11011110; // ** ****
11'h408: data = 8'b11011110; // ** ****
11'h409: data = 8'b11011100; // ** ***
11'h40a: data = 8'b11000000; // **
11'h40b: data = 8'b01111100; // *****
11'h40c: data = 8'b00000000; //
11'h40d: data = 8'b00000000; //
11'h40e: data = 8'b00000000; //
11'h40f: data = 8'b00000000; //
//code x41
11'h410: data = 8'b00000000; //
11'h411: data = 8'b00000000; //
11'h412: data = 8'b00010000; // *
11'h413: data = 8'b00111000; // ***
11'h414: data = 8'b01101100; // ** **
11'h415: data = 8'b11000110; // ** **
11'h416: data = 8'b11000110; // ** **
11'h417: data = 8'b11111110; // *******
11'h418: data = 8'b11000110; // ** **
11'h419: data = 8'b11000110; // ** **
11'h41a: data = 8'b11000110; // ** **
11'h41b: data = 8'b11000110; // ** **
11'h41c: data = 8'b00000000; //
11'h41d: data = 8'b00000000; //
11'h41e: data = 8'b00000000; //
11'h41f: data = 8'b00000000; //
//code x42
11'h420: data = 8'b00000000; //
11'h421: data = 8'b00000000; //
11'h422: data = 8'b11111100; // ******
11'h423: data = 8'b01100110; // ** **
11'h424: data = 8'b01100110; // ** **
11'h425: data = 8'b01100110; // ** **
11'h426: data = 8'b01111100; // *****
11'h427: data = 8'b01100110; // ** **
11'h428: data = 8'b01100110; // ** **
11'h429: data = 8'b01100110; // ** **
11'h42a: data = 8'b01100110; // ** **
11'h42b: data = 8'b11111100; // ******
11'h42c: data = 8'b00000000; //
11'h42d: data = 8'b00000000; //
11'h42e: data = 8'b00000000; //
11'h42f: data = 8'b00000000; //
//code x43
11'h430: data = 8'b00000000; //
11'h431: data = 8'b00000000; //
11'h432: data = 8'b00111100; // ****
11'h433: data = 8'b01100110; // ** **
11'h434: data = 8'b11000010; // ** *
11'h435: data = 8'b11000000; // **
11'h436: data = 8'b11000000; // **
11'h437: data = 8'b11000000; // **
11'h438: data = 8'b11000000; // **
11'h439: data = 8'b11000010; // ** *
11'h43a: data = 8'b01100110; // ** **
11'h43b: data = 8'b00111100; // ****
11'h43c: data = 8'b00000000; //
11'h43d: data = 8'b00000000; //
11'h43e: data = 8'b00000000; //
11'h43f: data = 8'b00000000; //
//code x44
11'h440: data = 8'b00000000; //
11'h441: data = 8'b00000000; //
11'h442: data = 8'b11111000; // *****
11'h443: data = 8'b01101100; // ** **
11'h444: data = 8'b01100110; // ** **
11'h445: data = 8'b01100110; // ** **
11'h446: data = 8'b01100110; // ** **
11'h447: data = 8'b01100110; // ** **
11'h448: data = 8'b01100110; // ** **
11'h449: data = 8'b01100110; // ** **
11'h44a: data = 8'b01101100; // ** **
11'h44b: data = 8'b11111000; // *****
11'h44c: data = 8'b00000000; //
11'h44d: data = 8'b00000000; //
11'h44e: data = 8'b00000000; //
11'h44f: data = 8'b00000000; //
//code x45
11'h450: data = 8'b00000000; //
11'h451: data = 8'b00000000; //
11'h452: data = 8'b11111110; // *******
11'h453: data = 8'b01100110; // ** **
11'h454: data = 8'b01100010; // ** *
11'h455: data = 8'b01101000; // ** *
11'h456: data = 8'b01111000; // ****
11'h457: data = 8'b01101000; // ** *
11'h458: data = 8'b01100000; // **
11'h459: data = 8'b01100010; // ** *
11'h45a: data = 8'b01100110; // ** **
11'h45b: data = 8'b11111110; // *******
11'h45c: data = 8'b00000000; //
11'h45d: data = 8'b00000000; //
11'h45e: data = 8'b00000000; //
11'h45f: data = 8'b00000000; //
//code x46
11'h460: data = 8'b00000000; //
11'h461: data = 8'b00000000; //
11'h462: data = 8'b11111110; // *******
11'h463: data = 8'b01100110; // ** **
11'h464: data = 8'b01100010; // ** *
11'h465: data = 8'b01101000; // ** *
11'h466: data = 8'b01111000; // ****
11'h467: data = 8'b01101000; // ** *
11'h468: data = 8'b01100000; // **
11'h469: data = 8'b01100000; // **
11'h46a: data = 8'b01100000; // **
11'h46b: data = 8'b11110000; // ****
11'h46c: data = 8'b00000000; //
11'h46d: data = 8'b00000000; //
11'h46e: data = 8'b00000000; //
11'h46f: data = 8'b00000000; //
//code x47
11'h470: data = 8'b00000000; //
11'h471: data = 8'b00000000; //
11'h472: data = 8'b00111100; // ****
11'h473: data = 8'b01100110; // ** **
11'h474: data = 8'b11000010; // ** *
11'h475: data = 8'b11000000; // **
11'h476: data = 8'b11000000; // **
11'h477: data = 8'b11011110; // ** ****
11'h478: data = 8'b11000110; // ** **
11'h479: data = 8'b11000110; // ** **
11'h47a: data = 8'b01100110; // ** **
11'h47b: data = 8'b00111010; // *** *
11'h47c: data = 8'b00000000; //
11'h47d: data = 8'b00000000; //
11'h47e: data = 8'b00000000; //
11'h47f: data = 8'b00000000; //
//code x48
11'h480: data = 8'b00000000; //
11'h481: data = 8'b00000000; //
11'h482: data = 8'b11000110; // ** **
11'h483: data = 8'b11000110; // ** **
11'h484: data = 8'b11000110; // ** **
11'h485: data = 8'b11000110; // ** **
11'h486: data = 8'b11111110; // *******
11'h487: data = 8'b11000110; // ** **
11'h488: data = 8'b11000110; // ** **
11'h489: data = 8'b11000110; // ** **
11'h48a: data = 8'b11000110; // ** **
11'h48b: data = 8'b11000110; // ** **
11'h48c: data = 8'b00000000; //
11'h48d: data = 8'b00000000; //
11'h48e: data = 8'b00000000; //
11'h48f: data = 8'b00000000; //
//code x49
11'h490: data = 8'b00000000; //
11'h491: data = 8'b00000000; //
11'h492: data = 8'b00111100; // ****
11'h493: data = 8'b00011000; // **
11'h494: data = 8'b00011000; // **
11'h495: data = 8'b00011000; // **
11'h496: data = 8'b00011000; // **
11'h497: data = 8'b00011000; // **
11'h498: data = 8'b00011000; // **
11'h499: data = 8'b00011000; // **
11'h49a: data = 8'b00011000; // **
11'h49b: data = 8'b00111100; // ****
11'h49c: data = 8'b00000000; //
11'h49d: data = 8'b00000000; //
11'h49e: data = 8'b00000000; //
11'h49f: data = 8'b00000000; //
//code x4a
11'h4a0: data = 8'b00000000; //
11'h4a1: data = 8'b00000000; //
11'h4a2: data = 8'b00011110; // ****
11'h4a3: data = 8'b00001100; // **
11'h4a4: data = 8'b00001100; // **
11'h4a5: data = 8'b00001100; // **
11'h4a6: data = 8'b00001100; // **
11'h4a7: data = 8'b00001100; // **
11'h4a8: data = 8'b11001100; // ** **
11'h4a9: data = 8'b11001100; // ** **
11'h4aa: data = 8'b11001100; // ** **
11'h4ab: data = 8'b01111000; // ****
11'h4ac: data = 8'b00000000; //
11'h4ad: data = 8'b00000000; //
11'h4ae: data = 8'b00000000; //
11'h4af: data = 8'b00000000; //
//code x4b
11'h4b0: data = 8'b00000000; //
11'h4b1: data = 8'b00000000; //
11'h4b2: data = 8'b11100110; // *** **
11'h4b3: data = 8'b01100110; // ** **
11'h4b4: data = 8'b01100110; // ** **
11'h4b5: data = 8'b01101100; // ** **
11'h4b6: data = 8'b01111000; // ****
11'h4b7: data = 8'b01111000; // ****
11'h4b8: data = 8'b01101100; // ** **
11'h4b9: data = 8'b01100110; // ** **
11'h4ba: data = 8'b01100110; // ** **
11'h4bb: data = 8'b11100110; // *** **
11'h4bc: data = 8'b00000000; //
11'h4bd: data = 8'b00000000; //
11'h4be: data = 8'b00000000; //
11'h4bf: data = 8'b00000000; //
//code x4c
11'h4c0: data = 8'b00000000; //
11'h4c1: data = 8'b00000000; //
11'h4c2: data = 8'b11110000; // ****
11'h4c3: data = 8'b01100000; // **
11'h4c4: data = 8'b01100000; // **
11'h4c5: data = 8'b01100000; // **
11'h4c6: data = 8'b01100000; // **
11'h4c7: data = 8'b01100000; // **
11'h4c8: data = 8'b01100000; // **
11'h4c9: data = 8'b01100010; // ** *
11'h4ca: data = 8'b01100110; // ** **
11'h4cb: data = 8'b11111110; // *******
11'h4cc: data = 8'b00000000; //
11'h4cd: data = 8'b00000000; //
11'h4ce: data = 8'b00000000; //
11'h4cf: data = 8'b00000000; //
//code x4d
11'h4d0: data = 8'b00000000; //
11'h4d1: data = 8'b00000000; //
11'h4d2: data = 8'b11000011; // ** **
11'h4d3: data = 8'b11100111; // *** ***
11'h4d4: data = 8'b11111111; // ********
11'h4d5: data = 8'b11111111; // ********
11'h4d6: data = 8'b11011011; // ** ** **
11'h4d7: data = 8'b11000011; // ** **
11'h4d8: data = 8'b11000011; // ** **
11'h4d9: data = 8'b11000011; // ** **
11'h4da: data = 8'b11000011; // ** **
11'h4db: data = 8'b11000011; // ** **
11'h4dc: data = 8'b00000000; //
11'h4dd: data = 8'b00000000; //
11'h4de: data = 8'b00000000; //
11'h4df: data = 8'b00000000; //
//code x4e
11'h4e0: data = 8'b00000000; //
11'h4e1: data = 8'b00000000; //
11'h4e2: data = 8'b11000110; // ** **
11'h4e3: data = 8'b11100110; // *** **
11'h4e4: data = 8'b11110110; // **** **
11'h4e5: data = 8'b11111110; // *******
11'h4e6: data = 8'b11011110; // ** ****
11'h4e7: data = 8'b11001110; // ** ***
11'h4e8: data = 8'b11000110; // ** **
11'h4e9: data = 8'b11000110; // ** **
11'h4ea: data = 8'b11000110; // ** **
11'h4eb: data = 8'b11000110; // ** **
11'h4ec: data = 8'b00000000; //
11'h4ed: data = 8'b00000000; //
11'h4ee: data = 8'b00000000; //
11'h4ef: data = 8'b00000000; //
//code x4f
11'h4f0: data = 8'b00000000; //
11'h4f1: data = 8'b00000000; //
11'h4f2: data = 8'b01111100; // *****
11'h4f3: data = 8'b11000110; // ** **
11'h4f4: data = 8'b11000110; // ** **
11'h4f5: data = 8'b11000110; // ** **
11'h4f6: data = 8'b11000110; // ** **
11'h4f7: data = 8'b11000110; // ** **
11'h4f8: data = 8'b11000110; // ** **
11'h4f9: data = 8'b11000110; // ** **
11'h4fa: data = 8'b11000110; // ** **
11'h4fb: data = 8'b01111100; // *****
11'h4fc: data = 8'b00000000; //
11'h4fd: data = 8'b00000000; //
11'h4fe: data = 8'b00000000; //
11'h4ff: data = 8'b00000000; //
//code x50
11'h500: data = 8'b00000000; //
11'h501: data = 8'b00000000; //
11'h502: data = 8'b11111100; // ******
11'h503: data = 8'b01100110; // ** **
11'h504: data = 8'b01100110; // ** **
11'h505: data = 8'b01100110; // ** **
11'h506: data = 8'b01111100; // *****
11'h507: data = 8'b01100000; // **
11'h508: data = 8'b01100000; // **
11'h509: data = 8'b01100000; // **
11'h50a: data = 8'b01100000; // **
11'h50b: data = 8'b11110000; // ****
11'h50c: data = 8'b00000000; //
11'h50d: data = 8'b00000000; //
11'h50e: data = 8'b00000000; //
11'h50f: data = 8'b00000000; //
//code x510f
11'h510: data = 8'b00000000; //
11'h511: data = 8'b00000000; //
11'h512: data = 8'b01111100; // *****
11'h513: data = 8'b11000110; // ** **
11'h514: data = 8'b11000110; // ** **
11'h515: data = 8'b11000110; // ** **
11'h516: data = 8'b11000110; // ** **
11'h517: data = 8'b11000110; // ** **
11'h518: data = 8'b11000110; // ** **
11'h519: data = 8'b11010110; // ** * **
11'h51a: data = 8'b11011110; // ** ****
11'h51b: data = 8'b01111100; // *****
11'h51c: data = 8'b00001100; // **
11'h51d: data = 8'b00001110; // ***
11'h51e: data = 8'b00000000; //
11'h51f: data = 8'b00000000; //
//code x52
11'h520: data = 8'b00000000; //
11'h521: data = 8'b00000000; //
11'h522: data = 8'b11111100; // ******
11'h523: data = 8'b01100110; // ** **
11'h524: data = 8'b01100110; // ** **
11'h525: data = 8'b01100110; // ** **
11'h526: data = 8'b01111100; // *****
11'h527: data = 8'b01101100; // ** **
11'h528: data = 8'b01100110; // ** **
11'h529: data = 8'b01100110; // ** **
11'h52a: data = 8'b01100110; // ** **
11'h52b: data = 8'b11100110; // *** **
11'h52c: data = 8'b00000000; //
11'h52d: data = 8'b00000000; //
11'h52e: data = 8'b00000000; //
11'h52f: data = 8'b00000000; //
//code x53
11'h530: data = 8'b00000000; //
11'h531: data = 8'b00000000; //
11'h532: data = 8'b01111100; // *****
11'h533: data = 8'b11000110; // ** **
11'h534: data = 8'b11000110; // ** **
11'h535: data = 8'b01100000; // **
11'h536: data = 8'b00111000; // ***
11'h537: data = 8'b00001100; // **
11'h538: data = 8'b00000110; // **
11'h539: data = 8'b11000110; // ** **
11'h53a: data = 8'b11000110; // ** **
11'h53b: data = 8'b01111100; // *****
11'h53c: data = 8'b00000000; //
11'h53d: data = 8'b00000000; //
11'h53e: data = 8'b00000000; //
11'h53f: data = 8'b00000000; //
//code x54
11'h540: data = 8'b00000000; //
11'h541: data = 8'b00000000; //
11'h542: data = 8'b11111111; // ********
11'h543: data = 8'b11011011; // ** ** **
11'h544: data = 8'b10011001; // * ** *
11'h545: data = 8'b00011000; // **
11'h546: data = 8'b00011000; // **
11'h547: data = 8'b00011000; // **
11'h548: data = 8'b00011000; // **
11'h549: data = 8'b00011000; // **
11'h54a: data = 8'b00011000; // **
11'h54b: data = 8'b00111100; // ****
11'h54c: data = 8'b00000000; //
11'h54d: data = 8'b00000000; //
11'h54e: data = 8'b00000000; //
11'h54f: data = 8'b00000000; //
//code x55
11'h550: data = 8'b00000000; //
11'h551: data = 8'b00000000; //
11'h552: data = 8'b11000110; // ** **
11'h553: data = 8'b11000110; // ** **
11'h554: data = 8'b11000110; // ** **
11'h555: data = 8'b11000110; // ** **
11'h556: data = 8'b11000110; // ** **
11'h557: data = 8'b11000110; // ** **
11'h558: data = 8'b11000110; // ** **
11'h559: data = 8'b11000110; // ** **
11'h55a: data = 8'b11000110; // ** **
11'h55b: data = 8'b01111100; // *****
11'h55c: data = 8'b00000000; //
11'h55d: data = 8'b00000000; //
11'h55e: data = 8'b00000000; //
11'h55f: data = 8'b00000000; //
//code x56
11'h560: data = 8'b00000000; //
11'h561: data = 8'b00000000; //
11'h562: data = 8'b11000011; // ** **
11'h563: data = 8'b11000011; // ** **
11'h564: data = 8'b11000011; // ** **
11'h565: data = 8'b11000011; // ** **
11'h566: data = 8'b11000011; // ** **
11'h567: data = 8'b11000011; // ** **
11'h568: data = 8'b11000011; // ** **
11'h569: data = 8'b01100110; // ** **
11'h56a: data = 8'b00111100; // ****
11'h56b: data = 8'b00011000; // **
11'h56c: data = 8'b00000000; //
11'h56d: data = 8'b00000000; //
11'h56e: data = 8'b00000000; //
11'h56f: data = 8'b00000000; //
//code x57
11'h570: data = 8'b00000000; //
11'h571: data = 8'b00000000; //
11'h572: data = 8'b11000011; // ** **
11'h573: data = 8'b11000011; // ** **
11'h574: data = 8'b11000011; // ** **
11'h575: data = 8'b11000011; // ** **
11'h576: data = 8'b11000011; // ** **
11'h577: data = 8'b11011011; // ** ** **
11'h578: data = 8'b11011011; // ** ** **
11'h579: data = 8'b11111111; // ********
11'h57a: data = 8'b01100110; // ** **
11'h57b: data = 8'b01100110; // ** **
11'h57c: data = 8'b00000000; //
11'h57d: data = 8'b00000000; //
11'h57e: data = 8'b00000000; //
11'h57f: data = 8'b00000000; //
//code x58
11'h580: data = 8'b00000000; //
11'h581: data = 8'b00000000; //
11'h582: data = 8'b11000011; // ** **
11'h583: data = 8'b11000011; // ** **
11'h584: data = 8'b01100110; // ** **
11'h585: data = 8'b00111100; // ****
11'h586: data = 8'b00011000; // **
11'h587: data = 8'b00011000; // **
11'h588: data = 8'b00111100; // ****
11'h589: data = 8'b01100110; // ** **
11'h58a: data = 8'b11000011; // ** **
11'h58b: data = 8'b11000011; // ** **
11'h58c: data = 8'b00000000; //
11'h58d: data = 8'b00000000; //
11'h58e: data = 8'b00000000; //
11'h58f: data = 8'b00000000; //
//code x59
11'h590: data = 8'b00000000; //
11'h591: data = 8'b00000000; //
11'h592: data = 8'b11000011; // ** **
11'h593: data = 8'b11000011; // ** **
11'h594: data = 8'b11000011; // ** **
11'h595: data = 8'b01100110; // ** **
11'h596: data = 8'b00111100; // ****
11'h597: data = 8'b00011000; // **
11'h598: data = 8'b00011000; // **
11'h599: data = 8'b00011000; // **
11'h59a: data = 8'b00011000; // **
11'h59b: data = 8'b00111100; // ****
11'h59c: data = 8'b00000000; //
11'h59d: data = 8'b00000000; //
11'h59e: data = 8'b00000000; //
11'h59f: data = 8'b00000000; //
//code x5a
11'h5a0: data = 8'b00000000; //
11'h5a1: data = 8'b00000000; //
11'h5a2: data = 8'b11111111; // ********
11'h5a3: data = 8'b11000011; // ** **
11'h5a4: data = 8'b10000110; // * **
11'h5a5: data = 8'b00001100; // **
11'h5a6: data = 8'b00011000; // **
11'h5a7: data = 8'b00110000; // **
11'h5a8: data = 8'b01100000; // **
11'h5a9: data = 8'b11000001; // ** *
11'h5aa: data = 8'b11000011; // ** **
11'h5ab: data = 8'b11111111; // ********
11'h5ac: data = 8'b00000000; //
11'h5ad: data = 8'b00000000; //
11'h5ae: data = 8'b00000000; //
11'h5af: data = 8'b00000000; //
//code x5b
11'h5b0: data = 8'b00000000; //
11'h5b1: data = 8'b00000000; //
11'h5b2: data = 8'b00111100; // ****
11'h5b3: data = 8'b00110000; // **
11'h5b4: data = 8'b00110000; // **
11'h5b5: data = 8'b00110000; // **
11'h5b6: data = 8'b00110000; // **
11'h5b7: data = 8'b00110000; // **
11'h5b8: data = 8'b00110000; // **
11'h5b9: data = 8'b00110000; // **
11'h5ba: data = 8'b00110000; // **
11'h5bb: data = 8'b00111100; // ****
11'h5bc: data = 8'b00000000; //
11'h5bd: data = 8'b00000000; //
11'h5be: data = 8'b00000000; //
11'h5bf: data = 8'b00000000; //
//code x5c
11'h5c0: data = 8'b00000000; //
11'h5c1: data = 8'b00000000; //
11'h5c2: data = 8'b00000000; //
11'h5c3: data = 8'b10000000; // *
11'h5c4: data = 8'b11000000; // **
11'h5c5: data = 8'b11100000; // ***
11'h5c6: data = 8'b01110000; // ***
11'h5c7: data = 8'b00111000; // ***
11'h5c8: data = 8'b00011100; // ***
11'h5c9: data = 8'b00001110; // ***
11'h5ca: data = 8'b00000110; // **
11'h5cb: data = 8'b00000010; // *
11'h5cc: data = 8'b00000000; //
11'h5cd: data = 8'b00000000; //
11'h5ce: data = 8'b00000000; //
11'h5cf: data = 8'b00000000; //
//code x5d
11'h5d0: data = 8'b00000000; //
11'h5d1: data = 8'b00000000; //
11'h5d2: data = 8'b00111100; // ****
11'h5d3: data = 8'b00001100; // **
11'h5d4: data = 8'b00001100; // **
11'h5d5: data = 8'b00001100; // **
11'h5d6: data = 8'b00001100; // **
11'h5d7: data = 8'b00001100; // **
11'h5d8: data = 8'b00001100; // **
11'h5d9: data = 8'b00001100; // **
11'h5da: data = 8'b00001100; // **
11'h5db: data = 8'b00111100; // ****
11'h5dc: data = 8'b00000000; //
11'h5dd: data = 8'b00000000; //
11'h5de: data = 8'b00000000; //
11'h5df: data = 8'b00000000; //
//code x5e
11'h5e0: data = 8'b00010000; // *
11'h5e1: data = 8'b00111000; // ***
11'h5e2: data = 8'b01101100; // ** **
11'h5e3: data = 8'b11000110; // ** **
11'h5e4: data = 8'b00000000; //
11'h5e5: data = 8'b00000000; //
11'h5e6: data = 8'b00000000; //
11'h5e7: data = 8'b00000000; //
11'h5e8: data = 8'b00000000; //
11'h5e9: data = 8'b00000000; //
11'h5ea: data = 8'b00000000; //
11'h5eb: data = 8'b00000000; //
11'h5ec: data = 8'b00000000; //
11'h5ed: data = 8'b00000000; //
11'h5ee: data = 8'b00000000; //
11'h5ef: data = 8'b00000000; //
//code x5f
11'h5f0: data = 8'b00000000; //
11'h5f1: data = 8'b00000000; //
11'h5f2: data = 8'b00000000; //
11'h5f3: data = 8'b00000000; //
11'h5f4: data = 8'b00000000; //
11'h5f5: data = 8'b00000000; //
11'h5f6: data = 8'b00000000; //
11'h5f7: data = 8'b00000000; //
11'h5f8: data = 8'b00000000; //
11'h5f9: data = 8'b00000000; //
11'h5fa: data = 8'b00000000; //
11'h5fb: data = 8'b00000000; //
11'h5fc: data = 8'b00000000; //
11'h5fd: data = 8'b11111111; // ********
11'h5fe: data = 8'b00000000; //
11'h5ff: data = 8'b00000000; //
//code x60
11'h600: data = 8'b00110000; // **
11'h601: data = 8'b00110000; // **
11'h602: data = 8'b00011000; // **
11'h603: data = 8'b00000000; //
11'h604: data = 8'b00000000; //
11'h605: data = 8'b00000000; //
11'h606: data = 8'b00000000; //
11'h607: data = 8'b00000000; //
11'h608: data = 8'b00000000; //
11'h609: data = 8'b00000000; //
11'h60a: data = 8'b00000000; //
11'h60b: data = 8'b00000000; //
11'h60c: data = 8'b00000000; //
11'h60d: data = 8'b00000000; //
11'h60e: data = 8'b00000000; //
11'h60f: data = 8'b00000000; //
//code x61
11'h610: data = 8'b00000000; //
11'h611: data = 8'b00000000; //
11'h612: data = 8'b00000000; //
11'h613: data = 8'b00000000; //
11'h614: data = 8'b00000000; //
11'h615: data = 8'b01111000; // ****
11'h616: data = 8'b00001100; // **
11'h617: data = 8'b01111100; // *****
11'h618: data = 8'b11001100; // ** **
11'h619: data = 8'b11001100; // ** **
11'h61a: data = 8'b11001100; // ** **
11'h61b: data = 8'b01110110; // *** **
11'h61c: data = 8'b00000000; //
11'h61d: data = 8'b00000000; //
11'h61e: data = 8'b00000000; //
11'h61f: data = 8'b00000000; //
//code x62
11'h620: data = 8'b00000000; //
11'h621: data = 8'b00000000; //
11'h622: data = 8'b11100000; // ***
11'h623: data = 8'b01100000; // **
11'h624: data = 8'b01100000; // **
11'h625: data = 8'b01111000; // ****
11'h626: data = 8'b01101100; // ** **
11'h627: data = 8'b01100110; // ** **
11'h628: data = 8'b01100110; // ** **
11'h629: data = 8'b01100110; // ** **
11'h62a: data = 8'b01100110; // ** **
11'h62b: data = 8'b01111100; // *****
11'h62c: data = 8'b00000000; //
11'h62d: data = 8'b00000000; //
11'h62e: data = 8'b00000000; //
11'h62f: data = 8'b00000000; //
//code x63
11'h630: data = 8'b00000000; //
11'h631: data = 8'b00000000; //
11'h632: data = 8'b00000000; //
11'h633: data = 8'b00000000; //
11'h634: data = 8'b00000000; //
11'h635: data = 8'b01111100; // *****
11'h636: data = 8'b11000110; // ** **
11'h637: data = 8'b11000000; // **
11'h638: data = 8'b11000000; // **
11'h639: data = 8'b11000000; // **
11'h63a: data = 8'b11000110; // ** **
11'h63b: data = 8'b01111100; // *****
11'h63c: data = 8'b00000000; //
11'h63d: data = 8'b00000000; //
11'h63e: data = 8'b00000000; //
11'h63f: data = 8'b00000000; //
//code x64
11'h640: data = 8'b00000000; //
11'h641: data = 8'b00000000; //
11'h642: data = 8'b00011100; // ***
11'h643: data = 8'b00001100; // **
11'h644: data = 8'b00001100; // **
11'h645: data = 8'b00111100; // ****
11'h646: data = 8'b01101100; // ** **
11'h647: data = 8'b11001100; // ** **
11'h648: data = 8'b11001100; // ** **
11'h649: data = 8'b11001100; // ** **
11'h64a: data = 8'b11001100; // ** **
11'h64b: data = 8'b01110110; // *** **
11'h64c: data = 8'b00000000; //
11'h64d: data = 8'b00000000; //
11'h64e: data = 8'b00000000; //
11'h64f: data = 8'b00000000; //
//code x65
11'h650: data = 8'b00000000; //
11'h651: data = 8'b00000000; //
11'h652: data = 8'b00000000; //
11'h653: data = 8'b00000000; //
11'h654: data = 8'b00000000; //
11'h655: data = 8'b01111100; // *****
11'h656: data = 8'b11000110; // ** **
11'h657: data = 8'b11111110; // *******
11'h658: data = 8'b11000000; // **
11'h659: data = 8'b11000000; // **
11'h65a: data = 8'b11000110; // ** **
11'h65b: data = 8'b01111100; // *****
11'h65c: data = 8'b00000000; //
11'h65d: data = 8'b00000000; //
11'h65e: data = 8'b00000000; //
11'h65f: data = 8'b00000000; //
//code x66
11'h660: data = 8'b00000000; //
11'h661: data = 8'b00000000; //
11'h662: data = 8'b00111000; // ***
11'h663: data = 8'b01101100; // ** **
11'h664: data = 8'b01100100; // ** *
11'h665: data = 8'b01100000; // **
11'h666: data = 8'b11110000; // ****
11'h667: data = 8'b01100000; // **
11'h668: data = 8'b01100000; // **
11'h669: data = 8'b01100000; // **
11'h66a: data = 8'b01100000; // **
11'h66b: data = 8'b11110000; // ****
11'h66c: data = 8'b00000000; //
11'h66d: data = 8'b00000000; //
11'h66e: data = 8'b00000000; //
11'h66f: data = 8'b00000000; //
//code x67
11'h670: data = 8'b00000000; //
11'h671: data = 8'b00000000; //
11'h672: data = 8'b00000000; //
11'h673: data = 8'b00000000; //
11'h674: data = 8'b00000000; //
11'h675: data = 8'b01110110; // *** **
11'h676: data = 8'b11001100; // ** **
11'h677: data = 8'b11001100; // ** **
11'h678: data = 8'b11001100; // ** **
11'h679: data = 8'b11001100; // ** **
11'h67a: data = 8'b11001100; // ** **
11'h67b: data = 8'b01111100; // *****
11'h67c: data = 8'b00001100; // **
11'h67d: data = 8'b11001100; // ** **
11'h67e: data = 8'b01111000; // ****
11'h67f: data = 8'b00000000; //
//code x68
11'h680: data = 8'b00000000; //
11'h681: data = 8'b00000000; //
11'h682: data = 8'b11100000; // ***
11'h683: data = 8'b01100000; // **
11'h684: data = 8'b01100000; // **
11'h685: data = 8'b01101100; // ** **
11'h686: data = 8'b01110110; // *** **
11'h687: data = 8'b01100110; // ** **
11'h688: data = 8'b01100110; // ** **
11'h689: data = 8'b01100110; // ** **
11'h68a: data = 8'b01100110; // ** **
11'h68b: data = 8'b11100110; // *** **
11'h68c: data = 8'b00000000; //
11'h68d: data = 8'b00000000; //
11'h68e: data = 8'b00000000; //
11'h68f: data = 8'b00000000; //
//code x69
11'h690: data = 8'b00000000; //
11'h691: data = 8'b00000000; //
11'h692: data = 8'b00011000; // **
11'h693: data = 8'b00011000; // **
11'h694: data = 8'b00000000; //
11'h695: data = 8'b00111000; // ***
11'h696: data = 8'b00011000; // **
11'h697: data = 8'b00011000; // **
11'h698: data = 8'b00011000; // **
11'h699: data = 8'b00011000; // **
11'h69a: data = 8'b00011000; // **
11'h69b: data = 8'b00111100; // ****
11'h69c: data = 8'b00000000; //
11'h69d: data = 8'b00000000; //
11'h69e: data = 8'b00000000; //
11'h69f: data = 8'b00000000; //
//code x6a
11'h6a0: data = 8'b00000000; //
11'h6a1: data = 8'b00000000; //
11'h6a2: data = 8'b00000110; // **
11'h6a3: data = 8'b00000110; // **
11'h6a4: data = 8'b00000000; //
11'h6a5: data = 8'b00001110; // ***
11'h6a6: data = 8'b00000110; // **
11'h6a7: data = 8'b00000110; // **
11'h6a8: data = 8'b00000110; // **
11'h6a9: data = 8'b00000110; // **
11'h6aa: data = 8'b00000110; // **
11'h6ab: data = 8'b00000110; // **
11'h6ac: data = 8'b01100110; // ** **
11'h6ad: data = 8'b01100110; // ** **
11'h6ae: data = 8'b00111100; // ****
11'h6af: data = 8'b00000000; //
//code x6b
11'h6b0: data = 8'b00000000; //
11'h6b1: data = 8'b00000000; //
11'h6b2: data = 8'b11100000; // ***
11'h6b3: data = 8'b01100000; // **
11'h6b4: data = 8'b01100000; // **
11'h6b5: data = 8'b01100110; // ** **
11'h6b6: data = 8'b01101100; // ** **
11'h6b7: data = 8'b01111000; // ****
11'h6b8: data = 8'b01111000; // ****
11'h6b9: data = 8'b01101100; // ** **
11'h6ba: data = 8'b01100110; // ** **
11'h6bb: data = 8'b11100110; // *** **
11'h6bc: data = 8'b00000000; //
11'h6bd: data = 8'b00000000; //
11'h6be: data = 8'b00000000; //
11'h6bf: data = 8'b00000000; //
//code x6c
11'h6c0: data = 8'b00000000; //
11'h6c1: data = 8'b00000000; //
11'h6c2: data = 8'b00111000; // ***
11'h6c3: data = 8'b00011000; // **
11'h6c4: data = 8'b00011000; // **
11'h6c5: data = 8'b00011000; // **
11'h6c6: data = 8'b00011000; // **
11'h6c7: data = 8'b00011000; // **
11'h6c8: data = 8'b00011000; // **
11'h6c9: data = 8'b00011000; // **
11'h6ca: data = 8'b00011000; // **
11'h6cb: data = 8'b00111100; // ****
11'h6cc: data = 8'b00000000; //
11'h6cd: data = 8'b00000000; //
11'h6ce: data = 8'b00000000; //
11'h6cf: data = 8'b00000000; //
//code x6d
11'h6d0: data = 8'b00000000; //
11'h6d1: data = 8'b00000000; //
11'h6d2: data = 8'b00000000; //
11'h6d3: data = 8'b00000000; //
11'h6d4: data = 8'b00000000; //
11'h6d5: data = 8'b11100110; // *** **
11'h6d6: data = 8'b11111111; // ********
11'h6d7: data = 8'b11011011; // ** ** **
11'h6d8: data = 8'b11011011; // ** ** **
11'h6d9: data = 8'b11011011; // ** ** **
11'h6da: data = 8'b11011011; // ** ** **
11'h6db: data = 8'b11011011; // ** ** **
11'h6dc: data = 8'b00000000; //
11'h6dd: data = 8'b00000000; //
11'h6de: data = 8'b00000000; //
11'h6df: data = 8'b00000000; //
//code x6e
11'h6e0: data = 8'b00000000; //
11'h6e1: data = 8'b00000000; //
11'h6e2: data = 8'b00000000; //
11'h6e3: data = 8'b00000000; //
11'h6e4: data = 8'b00000000; //
11'h6e5: data = 8'b11011100; // ** ***
11'h6e6: data = 8'b01100110; // ** **
11'h6e7: data = 8'b01100110; // ** **
11'h6e8: data = 8'b01100110; // ** **
11'h6e9: data = 8'b01100110; // ** **
11'h6ea: data = 8'b01100110; // ** **
11'h6eb: data = 8'b01100110; // ** **
11'h6ec: data = 8'b00000000; //
11'h6ed: data = 8'b00000000; //
11'h6ee: data = 8'b00000000; //
11'h6ef: data = 8'b00000000; //
//code x6f
11'h6f0: data = 8'b00000000; //
11'h6f1: data = 8'b00000000; //
11'h6f2: data = 8'b00000000; //
11'h6f3: data = 8'b00000000; //
11'h6f4: data = 8'b00000000; //
11'h6f5: data = 8'b01111100; // *****
11'h6f6: data = 8'b11000110; // ** **
11'h6f7: data = 8'b11000110; // ** **
11'h6f8: data = 8'b11000110; // ** **
11'h6f9: data = 8'b11000110; // ** **
11'h6fa: data = 8'b11000110; // ** **
11'h6fb: data = 8'b01111100; // *****
11'h6fc: data = 8'b00000000; //
11'h6fd: data = 8'b00000000; //
11'h6fe: data = 8'b00000000; //
11'h6ff: data = 8'b00000000; //
//code x70
11'h700: data = 8'b00000000; //
11'h701: data = 8'b00000000; //
11'h702: data = 8'b00000000; //
11'h703: data = 8'b00000000; //
11'h704: data = 8'b00000000; //
11'h705: data = 8'b11011100; // ** ***
11'h706: data = 8'b01100110; // ** **
11'h707: data = 8'b01100110; // ** **
11'h708: data = 8'b01100110; // ** **
11'h709: data = 8'b01100110; // ** **
11'h70a: data = 8'b01100110; // ** **
11'h70b: data = 8'b01111100; // *****
11'h70c: data = 8'b01100000; // **
11'h70d: data = 8'b01100000; // **
11'h70e: data = 8'b11110000; // ****
11'h70f: data = 8'b00000000; //
//code x71
11'h710: data = 8'b00000000; //
11'h711: data = 8'b00000000; //
11'h712: data = 8'b00000000; //
11'h713: data = 8'b00000000; //
11'h714: data = 8'b00000000; //
11'h715: data = 8'b01110110; // *** **
11'h716: data = 8'b11001100; // ** **
11'h717: data = 8'b11001100; // ** **
11'h718: data = 8'b11001100; // ** **
11'h719: data = 8'b11001100; // ** **
11'h71a: data = 8'b11001100; // ** **
11'h71b: data = 8'b01111100; // *****
11'h71c: data = 8'b00001100; // **
11'h71d: data = 8'b00001100; // **
11'h71e: data = 8'b00011110; // ****
11'h71f: data = 8'b00000000; //
//code x72
11'h720: data = 8'b00000000; //
11'h721: data = 8'b00000000; //
11'h722: data = 8'b00000000; //
11'h723: data = 8'b00000000; //
11'h724: data = 8'b00000000; //
11'h725: data = 8'b11011100; // ** ***
11'h726: data = 8'b01110110; // *** **
11'h727: data = 8'b01100110; // ** **
11'h728: data = 8'b01100000; // **
11'h729: data = 8'b01100000; // **
11'h72a: data = 8'b01100000; // **
11'h72b: data = 8'b11110000; // ****
11'h72c: data = 8'b00000000; //
11'h72d: data = 8'b00000000; //
11'h72e: data = 8'b00000000; //
11'h72f: data = 8'b00000000; //
//code x73
11'h730: data = 8'b00000000; //
11'h731: data = 8'b00000000; //
11'h732: data = 8'b00000000; //
11'h733: data = 8'b00000000; //
11'h734: data = 8'b00000000; //
11'h735: data = 8'b01111100; // *****
11'h736: data = 8'b11000110; // ** **
11'h737: data = 8'b01100000; // **
11'h738: data = 8'b00111000; // ***
11'h739: data = 8'b00001100; // **
11'h73a: data = 8'b11000110; // ** **
11'h73b: data = 8'b01111100; // *****
11'h73c: data = 8'b00000000; //
11'h73d: data = 8'b00000000; //
11'h73e: data = 8'b00000000; //
11'h73f: data = 8'b00000000; //
//code x74
11'h740: data = 8'b00000000; //
11'h741: data = 8'b00000000; //
11'h742: data = 8'b00010000; // *
11'h743: data = 8'b00110000; // **
11'h744: data = 8'b00110000; // **
11'h745: data = 8'b11111100; // ******
11'h746: data = 8'b00110000; // **
11'h747: data = 8'b00110000; // **
11'h748: data = 8'b00110000; // **
11'h749: data = 8'b00110000; // **
11'h74a: data = 8'b00110110; // ** **
11'h74b: data = 8'b00011100; // ***
11'h74c: data = 8'b00000000; //
11'h74d: data = 8'b00000000; //
11'h74e: data = 8'b00000000; //
11'h74f: data = 8'b00000000; //
//code x75
11'h750: data = 8'b00000000; //
11'h751: data = 8'b00000000; //
11'h752: data = 8'b00000000; //
11'h753: data = 8'b00000000; //
11'h754: data = 8'b00000000; //
11'h755: data = 8'b11001100; // ** **
11'h756: data = 8'b11001100; // ** **
11'h757: data = 8'b11001100; // ** **
11'h758: data = 8'b11001100; // ** **
11'h759: data = 8'b11001100; // ** **
11'h75a: data = 8'b11001100; // ** **
11'h75b: data = 8'b01110110; // *** **
11'h75c: data = 8'b00000000; //
11'h75d: data = 8'b00000000; //
11'h75e: data = 8'b00000000; //
11'h75f: data = 8'b00000000; //
//code x76
11'h760: data = 8'b00000000; //
11'h761: data = 8'b00000000; //
11'h762: data = 8'b00000000; //
11'h763: data = 8'b00000000; //
11'h764: data = 8'b00000000; //
11'h765: data = 8'b11000011; // ** **
11'h766: data = 8'b11000011; // ** **
11'h767: data = 8'b11000011; // ** **
11'h768: data = 8'b11000011; // ** **
11'h769: data = 8'b01100110; // ** **
11'h76a: data = 8'b00111100; // ****
11'h76b: data = 8'b00011000; // **
11'h76c: data = 8'b00000000; //
11'h76d: data = 8'b00000000; //
11'h76e: data = 8'b00000000; //
11'h76f: data = 8'b00000000; //
//code x77
11'h770: data = 8'b00000000; //
11'h771: data = 8'b00000000; //
11'h772: data = 8'b00000000; //
11'h773: data = 8'b00000000; //
11'h774: data = 8'b00000000; //
11'h775: data = 8'b11000011; // ** **
11'h776: data = 8'b11000011; // ** **
11'h777: data = 8'b11000011; // ** **
11'h778: data = 8'b11011011; // ** ** **
11'h779: data = 8'b11011011; // ** ** **
11'h77a: data = 8'b11111111; // ********
11'h77b: data = 8'b01100110; // ** **
11'h77c: data = 8'b00000000; //
11'h77d: data = 8'b00000000; //
11'h77e: data = 8'b00000000; //
11'h77f: data = 8'b00000000; //
//code x78
11'h780: data = 8'b00000000; //
11'h781: data = 8'b00000000; //
11'h782: data = 8'b00000000; //
11'h783: data = 8'b00000000; //
11'h784: data = 8'b00000000; //
11'h785: data = 8'b11000011; // ** **
11'h786: data = 8'b01100110; // ** **
11'h787: data = 8'b00111100; // ****
11'h788: data = 8'b00011000; // **
11'h789: data = 8'b00111100; // ****
11'h78a: data = 8'b01100110; // ** **
11'h78b: data = 8'b11000011; // ** **
11'h78c: data = 8'b00000000; //
11'h78d: data = 8'b00000000; //
11'h78e: data = 8'b00000000; //
11'h78f: data = 8'b00000000; //
//code x79
11'h790: data = 8'b00000000; //
11'h791: data = 8'b00000000; //
11'h792: data = 8'b00000000; //
11'h793: data = 8'b00000000; //
11'h794: data = 8'b00000000; //
11'h795: data = 8'b11000110; // ** **
11'h796: data = 8'b11000110; // ** **
11'h797: data = 8'b11000110; // ** **
11'h798: data = 8'b11000110; // ** **
11'h799: data = 8'b11000110; // ** **
11'h79a: data = 8'b11000110; // ** **
11'h79b: data = 8'b01111110; // ******
11'h79c: data = 8'b00000110; // **
11'h79d: data = 8'b00001100; // **
11'h79e: data = 8'b11111000; // *****
11'h79f: data = 8'b00000000; //
//code x7a
11'h7a0: data = 8'b00000000; //
11'h7a1: data = 8'b00000000; //
11'h7a2: data = 8'b00000000; //
11'h7a3: data = 8'b00000000; //
11'h7a4: data = 8'b00000000; //
11'h7a5: data = 8'b11111110; // *******
11'h7a6: data = 8'b11001100; // ** **
11'h7a7: data = 8'b00011000; // **
11'h7a8: data = 8'b00110000; // **
11'h7a9: data = 8'b01100000; // **
11'h7aa: data = 8'b11000110; // ** **
11'h7ab: data = 8'b11111110; // *******
11'h7ac: data = 8'b00000000; //
11'h7ad: data = 8'b00000000; //
11'h7ae: data = 8'b00000000; //
11'h7af: data = 8'b00000000; //
//code x7b
11'h7b0: data = 8'b00000000; //
11'h7b1: data = 8'b00000000; //
11'h7b2: data = 8'b00001110; // ***
11'h7b3: data = 8'b00011000; // **
11'h7b4: data = 8'b00011000; // **
11'h7b5: data = 8'b00011000; // **
11'h7b6: data = 8'b01110000; // ***
11'h7b7: data = 8'b00011000; // **
11'h7b8: data = 8'b00011000; // **
11'h7b9: data = 8'b00011000; // **
11'h7ba: data = 8'b00011000; // **
11'h7bb: data = 8'b00001110; // ***
11'h7bc: data = 8'b00000000; //
11'h7bd: data = 8'b00000000; //
11'h7be: data = 8'b00000000; //
11'h7bf: data = 8'b00000000; //
//code x7c
11'h7c0: data = 8'b00000000; //
11'h7c1: data = 8'b00000000; //
11'h7c2: data = 8'b00011000; // **
11'h7c3: data = 8'b00011000; // **
11'h7c4: data = 8'b00011000; // **
11'h7c5: data = 8'b00011000; // **
11'h7c6: data = 8'b00000000; //
11'h7c7: data = 8'b00011000; // **
11'h7c8: data = 8'b00011000; // **
11'h7c9: data = 8'b00011000; // **
11'h7ca: data = 8'b00011000; // **
11'h7cb: data = 8'b00011000; // **
11'h7cc: data = 8'b00000000; //
11'h7cd: data = 8'b00000000; //
11'h7ce: data = 8'b00000000; //
11'h7cf: data = 8'b00000000; //
//code x7d
11'h7d0: data = 8'b00000000; //
11'h7d1: data = 8'b00000000; //
11'h7d2: data = 8'b01110000; // ***
11'h7d3: data = 8'b00011000; // **
11'h7d4: data = 8'b00011000; // **
11'h7d5: data = 8'b00011000; // **
11'h7d6: data = 8'b00001110; // ***
11'h7d7: data = 8'b00011000; // **
11'h7d8: data = 8'b00011000; // **
11'h7d9: data = 8'b00011000; // **
11'h7da: data = 8'b00011000; // **
11'h7db: data = 8'b01110000; // ***
11'h7dc: data = 8'b00000000; //
11'h7dd: data = 8'b00000000; //
11'h7de: data = 8'b00000000; //
11'h7df: data = 8'b00000000; //
//code x7e
11'h7e0: data = 8'b00000000; //
11'h7e1: data = 8'b00000000; //
11'h7e2: data = 8'b01110110; // *** **
11'h7e3: data = 8'b11011100; // ** ***
11'h7e4: data = 8'b00000000; //
11'h7e5: data = 8'b00000000; //
11'h7e6: data = 8'b00000000; //
11'h7e7: data = 8'b00000000; //
11'h7e8: data = 8'b00000000; //
11'h7e9: data = 8'b00000000; //
11'h7ea: data = 8'b00000000; //
11'h7eb: data = 8'b00000000; //
11'h7ec: data = 8'b00000000; //
11'h7ed: data = 8'b00000000; //
11'h7ee: data = 8'b00000000; //
11'h7ef: data = 8'b00000000; //
//code x7f
11'h7f0: data = 8'b00000000; //
11'h7f1: data = 8'b00000000; //
11'h7f2: data = 8'b00000000; //
11'h7f3: data = 8'b00000000; //
11'h7f4: data = 8'b00010000; // *
11'h7f5: data = 8'b00111000; // ***
11'h7f6: data = 8'b01101100; // ** **
11'h7f7: data = 8'b11000110; // ** **
11'h7f8: data = 8'b11000110; // ** **
11'h7f9: data = 8'b11000110; // ** **
11'h7fa: data = 8'b11111110; // *******
11'h7fb: data = 8'b00000000; //
11'h7fc: data = 8'b00000000; //
11'h7fd: data = 8'b00000000; //
11'h7fe: data = 8'b00000000; //
11'h7ff: data = 8'b00000000; //
endcase
endmodule |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.633800,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=14,HLS_SYN_FF=5893,HLS_SYN_LUT=3947}" *)
module convolve_kernel (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
bufw_Addr_A,
bufw_EN_A,
bufw_WEN_A,
bufw_Din_A,
bufw_Dout_A,
bufw_Clk_A,
bufw_Rst_A,
bufi_Addr_A,
bufi_EN_A,
bufi_WEN_A,
bufi_Din_A,
bufi_Dout_A,
bufi_Clk_A,
bufi_Rst_A,
bufo_0_Addr_A,
bufo_0_EN_A,
bufo_0_WEN_A,
bufo_0_Din_A,
bufo_0_Dout_A,
bufo_0_Clk_A,
bufo_0_Rst_A,
bufo_1_Addr_A,
bufo_1_EN_A,
bufo_1_WEN_A,
bufo_1_Din_A,
bufo_1_Dout_A,
bufo_1_Clk_A,
bufo_1_Rst_A,
bufo_2_Addr_A,
bufo_2_EN_A,
bufo_2_WEN_A,
bufo_2_Din_A,
bufo_2_Dout_A,
bufo_2_Clk_A,
bufo_2_Rst_A,
bufo_3_Addr_A,
bufo_3_EN_A,
bufo_3_WEN_A,
bufo_3_Din_A,
bufo_3_Dout_A,
bufo_3_Clk_A,
bufo_3_Rst_A,
bufo_4_Addr_A,
bufo_4_EN_A,
bufo_4_WEN_A,
bufo_4_Din_A,
bufo_4_Dout_A,
bufo_4_Clk_A,
bufo_4_Rst_A,
bufo_5_Addr_A,
bufo_5_EN_A,
bufo_5_WEN_A,
bufo_5_Din_A,
bufo_5_Dout_A,
bufo_5_Clk_A,
bufo_5_Rst_A,
bufo_6_Addr_A,
bufo_6_EN_A,
bufo_6_WEN_A,
bufo_6_Din_A,
bufo_6_Dout_A,
bufo_6_Clk_A,
bufo_6_Rst_A,
bufo_7_Addr_A,
bufo_7_EN_A,
bufo_7_WEN_A,
bufo_7_Din_A,
bufo_7_Dout_A,
bufo_7_Clk_A,
bufo_7_Rst_A,
bufo_8_Addr_A,
bufo_8_EN_A,
bufo_8_WEN_A,
bufo_8_Din_A,
bufo_8_Dout_A,
bufo_8_Clk_A,
bufo_8_Rst_A,
bufo_9_Addr_A,
bufo_9_EN_A,
bufo_9_WEN_A,
bufo_9_Din_A,
bufo_9_Dout_A,
bufo_9_Clk_A,
bufo_9_Rst_A,
bufo_10_Addr_A,
bufo_10_EN_A,
bufo_10_WEN_A,
bufo_10_Din_A,
bufo_10_Dout_A,
bufo_10_Clk_A,
bufo_10_Rst_A,
bufo_11_Addr_A,
bufo_11_EN_A,
bufo_11_WEN_A,
bufo_11_Din_A,
bufo_11_Dout_A,
bufo_11_Clk_A,
bufo_11_Rst_A,
bufo_12_Addr_A,
bufo_12_EN_A,
bufo_12_WEN_A,
bufo_12_Din_A,
bufo_12_Dout_A,
bufo_12_Clk_A,
bufo_12_Rst_A,
bufo_13_Addr_A,
bufo_13_EN_A,
bufo_13_WEN_A,
bufo_13_Din_A,
bufo_13_Dout_A,
bufo_13_Clk_A,
bufo_13_Rst_A,
bufo_14_Addr_A,
bufo_14_EN_A,
bufo_14_WEN_A,
bufo_14_Din_A,
bufo_14_Dout_A,
bufo_14_Clk_A,
bufo_14_Rst_A,
bufo_15_Addr_A,
bufo_15_EN_A,
bufo_15_WEN_A,
bufo_15_Din_A,
bufo_15_Dout_A,
bufo_15_Clk_A,
bufo_15_Rst_A,
bufo_16_Addr_A,
bufo_16_EN_A,
bufo_16_WEN_A,
bufo_16_Din_A,
bufo_16_Dout_A,
bufo_16_Clk_A,
bufo_16_Rst_A,
bufo_17_Addr_A,
bufo_17_EN_A,
bufo_17_WEN_A,
bufo_17_Din_A,
bufo_17_Dout_A,
bufo_17_Clk_A,
bufo_17_Rst_A,
bufo_18_Addr_A,
bufo_18_EN_A,
bufo_18_WEN_A,
bufo_18_Din_A,
bufo_18_Dout_A,
bufo_18_Clk_A,
bufo_18_Rst_A,
bufo_19_Addr_A,
bufo_19_EN_A,
bufo_19_WEN_A,
bufo_19_Din_A,
bufo_19_Dout_A,
bufo_19_Clk_A,
bufo_19_Rst_A,
bufo_20_Addr_A,
bufo_20_EN_A,
bufo_20_WEN_A,
bufo_20_Din_A,
bufo_20_Dout_A,
bufo_20_Clk_A,
bufo_20_Rst_A,
bufo_21_Addr_A,
bufo_21_EN_A,
bufo_21_WEN_A,
bufo_21_Din_A,
bufo_21_Dout_A,
bufo_21_Clk_A,
bufo_21_Rst_A,
bufo_22_Addr_A,
bufo_22_EN_A,
bufo_22_WEN_A,
bufo_22_Din_A,
bufo_22_Dout_A,
bufo_22_Clk_A,
bufo_22_Rst_A,
bufo_23_Addr_A,
bufo_23_EN_A,
bufo_23_WEN_A,
bufo_23_Din_A,
bufo_23_Dout_A,
bufo_23_Clk_A,
bufo_23_Rst_A,
bufo_24_Addr_A,
bufo_24_EN_A,
bufo_24_WEN_A,
bufo_24_Din_A,
bufo_24_Dout_A,
bufo_24_Clk_A,
bufo_24_Rst_A,
bufo_25_Addr_A,
bufo_25_EN_A,
bufo_25_WEN_A,
bufo_25_Din_A,
bufo_25_Dout_A,
bufo_25_Clk_A,
bufo_25_Rst_A,
bufo_26_Addr_A,
bufo_26_EN_A,
bufo_26_WEN_A,
bufo_26_Din_A,
bufo_26_Dout_A,
bufo_26_Clk_A,
bufo_26_Rst_A,
bufo_27_Addr_A,
bufo_27_EN_A,
bufo_27_WEN_A,
bufo_27_Din_A,
bufo_27_Dout_A,
bufo_27_Clk_A,
bufo_27_Rst_A,
bufo_28_Addr_A,
bufo_28_EN_A,
bufo_28_WEN_A,
bufo_28_Din_A,
bufo_28_Dout_A,
bufo_28_Clk_A,
bufo_28_Rst_A,
bufo_29_Addr_A,
bufo_29_EN_A,
bufo_29_WEN_A,
bufo_29_Din_A,
bufo_29_Dout_A,
bufo_29_Clk_A,
bufo_29_Rst_A,
bufo_30_Addr_A,
bufo_30_EN_A,
bufo_30_WEN_A,
bufo_30_Din_A,
bufo_30_Dout_A,
bufo_30_Clk_A,
bufo_30_Rst_A,
bufo_31_Addr_A,
bufo_31_EN_A,
bufo_31_WEN_A,
bufo_31_Din_A,
bufo_31_Dout_A,
bufo_31_Clk_A,
bufo_31_Rst_A,
bufo_32_Addr_A,
bufo_32_EN_A,
bufo_32_WEN_A,
bufo_32_Din_A,
bufo_32_Dout_A,
bufo_32_Clk_A,
bufo_32_Rst_A,
bufo_33_Addr_A,
bufo_33_EN_A,
bufo_33_WEN_A,
bufo_33_Din_A,
bufo_33_Dout_A,
bufo_33_Clk_A,
bufo_33_Rst_A,
bufo_34_Addr_A,
bufo_34_EN_A,
bufo_34_WEN_A,
bufo_34_Din_A,
bufo_34_Dout_A,
bufo_34_Clk_A,
bufo_34_Rst_A,
bufo_35_Addr_A,
bufo_35_EN_A,
bufo_35_WEN_A,
bufo_35_Din_A,
bufo_35_Dout_A,
bufo_35_Clk_A,
bufo_35_Rst_A,
bufo_36_Addr_A,
bufo_36_EN_A,
bufo_36_WEN_A,
bufo_36_Din_A,
bufo_36_Dout_A,
bufo_36_Clk_A,
bufo_36_Rst_A,
bufo_37_Addr_A,
bufo_37_EN_A,
bufo_37_WEN_A,
bufo_37_Din_A,
bufo_37_Dout_A,
bufo_37_Clk_A,
bufo_37_Rst_A,
bufo_38_Addr_A,
bufo_38_EN_A,
bufo_38_WEN_A,
bufo_38_Din_A,
bufo_38_Dout_A,
bufo_38_Clk_A,
bufo_38_Rst_A,
bufo_39_Addr_A,
bufo_39_EN_A,
bufo_39_WEN_A,
bufo_39_Din_A,
bufo_39_Dout_A,
bufo_39_Clk_A,
bufo_39_Rst_A,
bufo_40_Addr_A,
bufo_40_EN_A,
bufo_40_WEN_A,
bufo_40_Din_A,
bufo_40_Dout_A,
bufo_40_Clk_A,
bufo_40_Rst_A,
bufo_41_Addr_A,
bufo_41_EN_A,
bufo_41_WEN_A,
bufo_41_Din_A,
bufo_41_Dout_A,
bufo_41_Clk_A,
bufo_41_Rst_A,
bufo_42_Addr_A,
bufo_42_EN_A,
bufo_42_WEN_A,
bufo_42_Din_A,
bufo_42_Dout_A,
bufo_42_Clk_A,
bufo_42_Rst_A,
bufo_43_Addr_A,
bufo_43_EN_A,
bufo_43_WEN_A,
bufo_43_Din_A,
bufo_43_Dout_A,
bufo_43_Clk_A,
bufo_43_Rst_A,
bufo_44_Addr_A,
bufo_44_EN_A,
bufo_44_WEN_A,
bufo_44_Din_A,
bufo_44_Dout_A,
bufo_44_Clk_A,
bufo_44_Rst_A,
bufo_45_Addr_A,
bufo_45_EN_A,
bufo_45_WEN_A,
bufo_45_Din_A,
bufo_45_Dout_A,
bufo_45_Clk_A,
bufo_45_Rst_A,
bufo_46_Addr_A,
bufo_46_EN_A,
bufo_46_WEN_A,
bufo_46_Din_A,
bufo_46_Dout_A,
bufo_46_Clk_A,
bufo_46_Rst_A,
bufo_47_Addr_A,
bufo_47_EN_A,
bufo_47_WEN_A,
bufo_47_Din_A,
bufo_47_Dout_A,
bufo_47_Clk_A,
bufo_47_Rst_A,
bufo_48_Addr_A,
bufo_48_EN_A,
bufo_48_WEN_A,
bufo_48_Din_A,
bufo_48_Dout_A,
bufo_48_Clk_A,
bufo_48_Rst_A,
bufo_49_Addr_A,
bufo_49_EN_A,
bufo_49_WEN_A,
bufo_49_Din_A,
bufo_49_Dout_A,
bufo_49_Clk_A,
bufo_49_Rst_A,
bufo_50_Addr_A,
bufo_50_EN_A,
bufo_50_WEN_A,
bufo_50_Din_A,
bufo_50_Dout_A,
bufo_50_Clk_A,
bufo_50_Rst_A,
bufo_51_Addr_A,
bufo_51_EN_A,
bufo_51_WEN_A,
bufo_51_Din_A,
bufo_51_Dout_A,
bufo_51_Clk_A,
bufo_51_Rst_A,
bufo_52_Addr_A,
bufo_52_EN_A,
bufo_52_WEN_A,
bufo_52_Din_A,
bufo_52_Dout_A,
bufo_52_Clk_A,
bufo_52_Rst_A,
bufo_53_Addr_A,
bufo_53_EN_A,
bufo_53_WEN_A,
bufo_53_Din_A,
bufo_53_Dout_A,
bufo_53_Clk_A,
bufo_53_Rst_A,
bufo_54_Addr_A,
bufo_54_EN_A,
bufo_54_WEN_A,
bufo_54_Din_A,
bufo_54_Dout_A,
bufo_54_Clk_A,
bufo_54_Rst_A,
bufo_55_Addr_A,
bufo_55_EN_A,
bufo_55_WEN_A,
bufo_55_Din_A,
bufo_55_Dout_A,
bufo_55_Clk_A,
bufo_55_Rst_A,
bufo_56_Addr_A,
bufo_56_EN_A,
bufo_56_WEN_A,
bufo_56_Din_A,
bufo_56_Dout_A,
bufo_56_Clk_A,
bufo_56_Rst_A,
bufo_57_Addr_A,
bufo_57_EN_A,
bufo_57_WEN_A,
bufo_57_Din_A,
bufo_57_Dout_A,
bufo_57_Clk_A,
bufo_57_Rst_A,
bufo_58_Addr_A,
bufo_58_EN_A,
bufo_58_WEN_A,
bufo_58_Din_A,
bufo_58_Dout_A,
bufo_58_Clk_A,
bufo_58_Rst_A,
bufo_59_Addr_A,
bufo_59_EN_A,
bufo_59_WEN_A,
bufo_59_Din_A,
bufo_59_Dout_A,
bufo_59_Clk_A,
bufo_59_Rst_A,
bufo_60_Addr_A,
bufo_60_EN_A,
bufo_60_WEN_A,
bufo_60_Din_A,
bufo_60_Dout_A,
bufo_60_Clk_A,
bufo_60_Rst_A,
bufo_61_Addr_A,
bufo_61_EN_A,
bufo_61_WEN_A,
bufo_61_Din_A,
bufo_61_Dout_A,
bufo_61_Clk_A,
bufo_61_Rst_A,
bufo_62_Addr_A,
bufo_62_EN_A,
bufo_62_WEN_A,
bufo_62_Din_A,
bufo_62_Dout_A,
bufo_62_Clk_A,
bufo_62_Rst_A,
bufo_63_Addr_A,
bufo_63_EN_A,
bufo_63_WEN_A,
bufo_63_Din_A,
bufo_63_Dout_A,
bufo_63_Clk_A,
bufo_63_Rst_A,
bufo_64_Addr_A,
bufo_64_EN_A,
bufo_64_WEN_A,
bufo_64_Din_A,
bufo_64_Dout_A,
bufo_64_Clk_A,
bufo_64_Rst_A,
bufo_65_Addr_A,
bufo_65_EN_A,
bufo_65_WEN_A,
bufo_65_Din_A,
bufo_65_Dout_A,
bufo_65_Clk_A,
bufo_65_Rst_A,
bufo_66_Addr_A,
bufo_66_EN_A,
bufo_66_WEN_A,
bufo_66_Din_A,
bufo_66_Dout_A,
bufo_66_Clk_A,
bufo_66_Rst_A,
bufo_67_Addr_A,
bufo_67_EN_A,
bufo_67_WEN_A,
bufo_67_Din_A,
bufo_67_Dout_A,
bufo_67_Clk_A,
bufo_67_Rst_A,
bufo_68_Addr_A,
bufo_68_EN_A,
bufo_68_WEN_A,
bufo_68_Din_A,
bufo_68_Dout_A,
bufo_68_Clk_A,
bufo_68_Rst_A,
bufo_69_Addr_A,
bufo_69_EN_A,
bufo_69_WEN_A,
bufo_69_Din_A,
bufo_69_Dout_A,
bufo_69_Clk_A,
bufo_69_Rst_A,
bufo_70_Addr_A,
bufo_70_EN_A,
bufo_70_WEN_A,
bufo_70_Din_A,
bufo_70_Dout_A,
bufo_70_Clk_A,
bufo_70_Rst_A,
bufo_71_Addr_A,
bufo_71_EN_A,
bufo_71_WEN_A,
bufo_71_Din_A,
bufo_71_Dout_A,
bufo_71_Clk_A,
bufo_71_Rst_A,
bufo_72_Addr_A,
bufo_72_EN_A,
bufo_72_WEN_A,
bufo_72_Din_A,
bufo_72_Dout_A,
bufo_72_Clk_A,
bufo_72_Rst_A,
bufo_73_Addr_A,
bufo_73_EN_A,
bufo_73_WEN_A,
bufo_73_Din_A,
bufo_73_Dout_A,
bufo_73_Clk_A,
bufo_73_Rst_A,
bufo_74_Addr_A,
bufo_74_EN_A,
bufo_74_WEN_A,
bufo_74_Din_A,
bufo_74_Dout_A,
bufo_74_Clk_A,
bufo_74_Rst_A,
bufo_75_Addr_A,
bufo_75_EN_A,
bufo_75_WEN_A,
bufo_75_Din_A,
bufo_75_Dout_A,
bufo_75_Clk_A,
bufo_75_Rst_A,
bufo_76_Addr_A,
bufo_76_EN_A,
bufo_76_WEN_A,
bufo_76_Din_A,
bufo_76_Dout_A,
bufo_76_Clk_A,
bufo_76_Rst_A,
bufo_77_Addr_A,
bufo_77_EN_A,
bufo_77_WEN_A,
bufo_77_Din_A,
bufo_77_Dout_A,
bufo_77_Clk_A,
bufo_77_Rst_A,
bufo_78_Addr_A,
bufo_78_EN_A,
bufo_78_WEN_A,
bufo_78_Din_A,
bufo_78_Dout_A,
bufo_78_Clk_A,
bufo_78_Rst_A,
bufo_79_Addr_A,
bufo_79_EN_A,
bufo_79_WEN_A,
bufo_79_Din_A,
bufo_79_Dout_A,
bufo_79_Clk_A,
bufo_79_Rst_A,
bufo_80_Addr_A,
bufo_80_EN_A,
bufo_80_WEN_A,
bufo_80_Din_A,
bufo_80_Dout_A,
bufo_80_Clk_A,
bufo_80_Rst_A,
bufo_81_Addr_A,
bufo_81_EN_A,
bufo_81_WEN_A,
bufo_81_Din_A,
bufo_81_Dout_A,
bufo_81_Clk_A,
bufo_81_Rst_A,
bufo_82_Addr_A,
bufo_82_EN_A,
bufo_82_WEN_A,
bufo_82_Din_A,
bufo_82_Dout_A,
bufo_82_Clk_A,
bufo_82_Rst_A,
bufo_83_Addr_A,
bufo_83_EN_A,
bufo_83_WEN_A,
bufo_83_Din_A,
bufo_83_Dout_A,
bufo_83_Clk_A,
bufo_83_Rst_A,
bufo_84_Addr_A,
bufo_84_EN_A,
bufo_84_WEN_A,
bufo_84_Din_A,
bufo_84_Dout_A,
bufo_84_Clk_A,
bufo_84_Rst_A,
bufo_85_Addr_A,
bufo_85_EN_A,
bufo_85_WEN_A,
bufo_85_Din_A,
bufo_85_Dout_A,
bufo_85_Clk_A,
bufo_85_Rst_A,
bufo_86_Addr_A,
bufo_86_EN_A,
bufo_86_WEN_A,
bufo_86_Din_A,
bufo_86_Dout_A,
bufo_86_Clk_A,
bufo_86_Rst_A,
bufo_87_Addr_A,
bufo_87_EN_A,
bufo_87_WEN_A,
bufo_87_Din_A,
bufo_87_Dout_A,
bufo_87_Clk_A,
bufo_87_Rst_A,
bufo_88_Addr_A,
bufo_88_EN_A,
bufo_88_WEN_A,
bufo_88_Din_A,
bufo_88_Dout_A,
bufo_88_Clk_A,
bufo_88_Rst_A,
bufo_89_Addr_A,
bufo_89_EN_A,
bufo_89_WEN_A,
bufo_89_Din_A,
bufo_89_Dout_A,
bufo_89_Clk_A,
bufo_89_Rst_A,
bufo_90_Addr_A,
bufo_90_EN_A,
bufo_90_WEN_A,
bufo_90_Din_A,
bufo_90_Dout_A,
bufo_90_Clk_A,
bufo_90_Rst_A,
bufo_91_Addr_A,
bufo_91_EN_A,
bufo_91_WEN_A,
bufo_91_Din_A,
bufo_91_Dout_A,
bufo_91_Clk_A,
bufo_91_Rst_A,
bufo_92_Addr_A,
bufo_92_EN_A,
bufo_92_WEN_A,
bufo_92_Din_A,
bufo_92_Dout_A,
bufo_92_Clk_A,
bufo_92_Rst_A,
bufo_93_Addr_A,
bufo_93_EN_A,
bufo_93_WEN_A,
bufo_93_Din_A,
bufo_93_Dout_A,
bufo_93_Clk_A,
bufo_93_Rst_A,
bufo_94_Addr_A,
bufo_94_EN_A,
bufo_94_WEN_A,
bufo_94_Din_A,
bufo_94_Dout_A,
bufo_94_Clk_A,
bufo_94_Rst_A,
bufo_95_Addr_A,
bufo_95_EN_A,
bufo_95_WEN_A,
bufo_95_Din_A,
bufo_95_Dout_A,
bufo_95_Clk_A,
bufo_95_Rst_A,
bufo_96_Addr_A,
bufo_96_EN_A,
bufo_96_WEN_A,
bufo_96_Din_A,
bufo_96_Dout_A,
bufo_96_Clk_A,
bufo_96_Rst_A,
bufo_97_Addr_A,
bufo_97_EN_A,
bufo_97_WEN_A,
bufo_97_Din_A,
bufo_97_Dout_A,
bufo_97_Clk_A,
bufo_97_Rst_A,
bufo_98_Addr_A,
bufo_98_EN_A,
bufo_98_WEN_A,
bufo_98_Din_A,
bufo_98_Dout_A,
bufo_98_Clk_A,
bufo_98_Rst_A,
bufo_99_Addr_A,
bufo_99_EN_A,
bufo_99_WEN_A,
bufo_99_Din_A,
bufo_99_Dout_A,
bufo_99_Clk_A,
bufo_99_Rst_A,
bufo_100_Addr_A,
bufo_100_EN_A,
bufo_100_WEN_A,
bufo_100_Din_A,
bufo_100_Dout_A,
bufo_100_Clk_A,
bufo_100_Rst_A,
bufo_101_Addr_A,
bufo_101_EN_A,
bufo_101_WEN_A,
bufo_101_Din_A,
bufo_101_Dout_A,
bufo_101_Clk_A,
bufo_101_Rst_A,
bufo_102_Addr_A,
bufo_102_EN_A,
bufo_102_WEN_A,
bufo_102_Din_A,
bufo_102_Dout_A,
bufo_102_Clk_A,
bufo_102_Rst_A,
bufo_103_Addr_A,
bufo_103_EN_A,
bufo_103_WEN_A,
bufo_103_Din_A,
bufo_103_Dout_A,
bufo_103_Clk_A,
bufo_103_Rst_A,
bufo_104_Addr_A,
bufo_104_EN_A,
bufo_104_WEN_A,
bufo_104_Din_A,
bufo_104_Dout_A,
bufo_104_Clk_A,
bufo_104_Rst_A,
bufo_105_Addr_A,
bufo_105_EN_A,
bufo_105_WEN_A,
bufo_105_Din_A,
bufo_105_Dout_A,
bufo_105_Clk_A,
bufo_105_Rst_A,
bufo_106_Addr_A,
bufo_106_EN_A,
bufo_106_WEN_A,
bufo_106_Din_A,
bufo_106_Dout_A,
bufo_106_Clk_A,
bufo_106_Rst_A,
bufo_107_Addr_A,
bufo_107_EN_A,
bufo_107_WEN_A,
bufo_107_Din_A,
bufo_107_Dout_A,
bufo_107_Clk_A,
bufo_107_Rst_A,
bufo_108_Addr_A,
bufo_108_EN_A,
bufo_108_WEN_A,
bufo_108_Din_A,
bufo_108_Dout_A,
bufo_108_Clk_A,
bufo_108_Rst_A,
bufo_109_Addr_A,
bufo_109_EN_A,
bufo_109_WEN_A,
bufo_109_Din_A,
bufo_109_Dout_A,
bufo_109_Clk_A,
bufo_109_Rst_A,
bufo_110_Addr_A,
bufo_110_EN_A,
bufo_110_WEN_A,
bufo_110_Din_A,
bufo_110_Dout_A,
bufo_110_Clk_A,
bufo_110_Rst_A,
bufo_111_Addr_A,
bufo_111_EN_A,
bufo_111_WEN_A,
bufo_111_Din_A,
bufo_111_Dout_A,
bufo_111_Clk_A,
bufo_111_Rst_A,
bufo_112_Addr_A,
bufo_112_EN_A,
bufo_112_WEN_A,
bufo_112_Din_A,
bufo_112_Dout_A,
bufo_112_Clk_A,
bufo_112_Rst_A,
bufo_113_Addr_A,
bufo_113_EN_A,
bufo_113_WEN_A,
bufo_113_Din_A,
bufo_113_Dout_A,
bufo_113_Clk_A,
bufo_113_Rst_A,
bufo_114_Addr_A,
bufo_114_EN_A,
bufo_114_WEN_A,
bufo_114_Din_A,
bufo_114_Dout_A,
bufo_114_Clk_A,
bufo_114_Rst_A,
bufo_115_Addr_A,
bufo_115_EN_A,
bufo_115_WEN_A,
bufo_115_Din_A,
bufo_115_Dout_A,
bufo_115_Clk_A,
bufo_115_Rst_A,
bufo_116_Addr_A,
bufo_116_EN_A,
bufo_116_WEN_A,
bufo_116_Din_A,
bufo_116_Dout_A,
bufo_116_Clk_A,
bufo_116_Rst_A,
bufo_117_Addr_A,
bufo_117_EN_A,
bufo_117_WEN_A,
bufo_117_Din_A,
bufo_117_Dout_A,
bufo_117_Clk_A,
bufo_117_Rst_A,
bufo_118_Addr_A,
bufo_118_EN_A,
bufo_118_WEN_A,
bufo_118_Din_A,
bufo_118_Dout_A,
bufo_118_Clk_A,
bufo_118_Rst_A,
bufo_119_Addr_A,
bufo_119_EN_A,
bufo_119_WEN_A,
bufo_119_Din_A,
bufo_119_Dout_A,
bufo_119_Clk_A,
bufo_119_Rst_A,
bufo_120_Addr_A,
bufo_120_EN_A,
bufo_120_WEN_A,
bufo_120_Din_A,
bufo_120_Dout_A,
bufo_120_Clk_A,
bufo_120_Rst_A,
bufo_121_Addr_A,
bufo_121_EN_A,
bufo_121_WEN_A,
bufo_121_Din_A,
bufo_121_Dout_A,
bufo_121_Clk_A,
bufo_121_Rst_A,
bufo_122_Addr_A,
bufo_122_EN_A,
bufo_122_WEN_A,
bufo_122_Din_A,
bufo_122_Dout_A,
bufo_122_Clk_A,
bufo_122_Rst_A,
bufo_123_Addr_A,
bufo_123_EN_A,
bufo_123_WEN_A,
bufo_123_Din_A,
bufo_123_Dout_A,
bufo_123_Clk_A,
bufo_123_Rst_A,
bufo_124_Addr_A,
bufo_124_EN_A,
bufo_124_WEN_A,
bufo_124_Din_A,
bufo_124_Dout_A,
bufo_124_Clk_A,
bufo_124_Rst_A,
bufo_125_Addr_A,
bufo_125_EN_A,
bufo_125_WEN_A,
bufo_125_Din_A,
bufo_125_Dout_A,
bufo_125_Clk_A,
bufo_125_Rst_A,
bufo_126_Addr_A,
bufo_126_EN_A,
bufo_126_WEN_A,
bufo_126_Din_A,
bufo_126_Dout_A,
bufo_126_Clk_A,
bufo_126_Rst_A,
bufo_127_Addr_A,
bufo_127_EN_A,
bufo_127_WEN_A,
bufo_127_Din_A,
bufo_127_Dout_A,
bufo_127_Clk_A,
bufo_127_Rst_A,
bufo_128_Addr_A,
bufo_128_EN_A,
bufo_128_WEN_A,
bufo_128_Din_A,
bufo_128_Dout_A,
bufo_128_Clk_A,
bufo_128_Rst_A,
bufo_128_Addr_B,
bufo_128_EN_B,
bufo_128_WEN_B,
bufo_128_Din_B,
bufo_128_Dout_B,
bufo_128_Clk_B,
bufo_128_Rst_B,
bufo_129_Addr_A,
bufo_129_EN_A,
bufo_129_WEN_A,
bufo_129_Din_A,
bufo_129_Dout_A,
bufo_129_Clk_A,
bufo_129_Rst_A,
bufo_129_Addr_B,
bufo_129_EN_B,
bufo_129_WEN_B,
bufo_129_Din_B,
bufo_129_Dout_B,
bufo_129_Clk_B,
bufo_129_Rst_B,
bufo_130_Addr_A,
bufo_130_EN_A,
bufo_130_WEN_A,
bufo_130_Din_A,
bufo_130_Dout_A,
bufo_130_Clk_A,
bufo_130_Rst_A,
bufo_130_Addr_B,
bufo_130_EN_B,
bufo_130_WEN_B,
bufo_130_Din_B,
bufo_130_Dout_B,
bufo_130_Clk_B,
bufo_130_Rst_B,
bufo_131_Addr_A,
bufo_131_EN_A,
bufo_131_WEN_A,
bufo_131_Din_A,
bufo_131_Dout_A,
bufo_131_Clk_A,
bufo_131_Rst_A,
bufo_131_Addr_B,
bufo_131_EN_B,
bufo_131_WEN_B,
bufo_131_Din_B,
bufo_131_Dout_B,
bufo_131_Clk_B,
bufo_131_Rst_B,
bufo_132_Addr_A,
bufo_132_EN_A,
bufo_132_WEN_A,
bufo_132_Din_A,
bufo_132_Dout_A,
bufo_132_Clk_A,
bufo_132_Rst_A,
bufo_132_Addr_B,
bufo_132_EN_B,
bufo_132_WEN_B,
bufo_132_Din_B,
bufo_132_Dout_B,
bufo_132_Clk_B,
bufo_132_Rst_B,
bufo_133_Addr_A,
bufo_133_EN_A,
bufo_133_WEN_A,
bufo_133_Din_A,
bufo_133_Dout_A,
bufo_133_Clk_A,
bufo_133_Rst_A,
bufo_133_Addr_B,
bufo_133_EN_B,
bufo_133_WEN_B,
bufo_133_Din_B,
bufo_133_Dout_B,
bufo_133_Clk_B,
bufo_133_Rst_B,
bufo_134_Addr_A,
bufo_134_EN_A,
bufo_134_WEN_A,
bufo_134_Din_A,
bufo_134_Dout_A,
bufo_134_Clk_A,
bufo_134_Rst_A,
bufo_134_Addr_B,
bufo_134_EN_B,
bufo_134_WEN_B,
bufo_134_Din_B,
bufo_134_Dout_B,
bufo_134_Clk_B,
bufo_134_Rst_B,
bufo_135_Addr_A,
bufo_135_EN_A,
bufo_135_WEN_A,
bufo_135_Din_A,
bufo_135_Dout_A,
bufo_135_Clk_A,
bufo_135_Rst_A,
bufo_135_Addr_B,
bufo_135_EN_B,
bufo_135_WEN_B,
bufo_135_Din_B,
bufo_135_Dout_B,
bufo_135_Clk_B,
bufo_135_Rst_B,
bufo_136_Addr_A,
bufo_136_EN_A,
bufo_136_WEN_A,
bufo_136_Din_A,
bufo_136_Dout_A,
bufo_136_Clk_A,
bufo_136_Rst_A,
bufo_136_Addr_B,
bufo_136_EN_B,
bufo_136_WEN_B,
bufo_136_Din_B,
bufo_136_Dout_B,
bufo_136_Clk_B,
bufo_136_Rst_B,
bufo_137_Addr_A,
bufo_137_EN_A,
bufo_137_WEN_A,
bufo_137_Din_A,
bufo_137_Dout_A,
bufo_137_Clk_A,
bufo_137_Rst_A,
bufo_137_Addr_B,
bufo_137_EN_B,
bufo_137_WEN_B,
bufo_137_Din_B,
bufo_137_Dout_B,
bufo_137_Clk_B,
bufo_137_Rst_B,
bufo_138_Addr_A,
bufo_138_EN_A,
bufo_138_WEN_A,
bufo_138_Din_A,
bufo_138_Dout_A,
bufo_138_Clk_A,
bufo_138_Rst_A,
bufo_138_Addr_B,
bufo_138_EN_B,
bufo_138_WEN_B,
bufo_138_Din_B,
bufo_138_Dout_B,
bufo_138_Clk_B,
bufo_138_Rst_B,
bufo_139_Addr_A,
bufo_139_EN_A,
bufo_139_WEN_A,
bufo_139_Din_A,
bufo_139_Dout_A,
bufo_139_Clk_A,
bufo_139_Rst_A,
bufo_139_Addr_B,
bufo_139_EN_B,
bufo_139_WEN_B,
bufo_139_Din_B,
bufo_139_Dout_B,
bufo_139_Clk_B,
bufo_139_Rst_B,
bufo_140_Addr_A,
bufo_140_EN_A,
bufo_140_WEN_A,
bufo_140_Din_A,
bufo_140_Dout_A,
bufo_140_Clk_A,
bufo_140_Rst_A,
bufo_140_Addr_B,
bufo_140_EN_B,
bufo_140_WEN_B,
bufo_140_Din_B,
bufo_140_Dout_B,
bufo_140_Clk_B,
bufo_140_Rst_B,
bufo_141_Addr_A,
bufo_141_EN_A,
bufo_141_WEN_A,
bufo_141_Din_A,
bufo_141_Dout_A,
bufo_141_Clk_A,
bufo_141_Rst_A,
bufo_141_Addr_B,
bufo_141_EN_B,
bufo_141_WEN_B,
bufo_141_Din_B,
bufo_141_Dout_B,
bufo_141_Clk_B,
bufo_141_Rst_B,
bufo_142_Addr_A,
bufo_142_EN_A,
bufo_142_WEN_A,
bufo_142_Din_A,
bufo_142_Dout_A,
bufo_142_Clk_A,
bufo_142_Rst_A,
bufo_142_Addr_B,
bufo_142_EN_B,
bufo_142_WEN_B,
bufo_142_Din_B,
bufo_142_Dout_B,
bufo_142_Clk_B,
bufo_142_Rst_B,
bufo_143_Addr_A,
bufo_143_EN_A,
bufo_143_WEN_A,
bufo_143_Din_A,
bufo_143_Dout_A,
bufo_143_Clk_A,
bufo_143_Rst_A,
bufo_143_Addr_B,
bufo_143_EN_B,
bufo_143_WEN_B,
bufo_143_Din_B,
bufo_143_Dout_B,
bufo_143_Clk_B,
bufo_143_Rst_B,
bufo_144_Addr_A,
bufo_144_EN_A,
bufo_144_WEN_A,
bufo_144_Din_A,
bufo_144_Dout_A,
bufo_144_Clk_A,
bufo_144_Rst_A,
bufo_144_Addr_B,
bufo_144_EN_B,
bufo_144_WEN_B,
bufo_144_Din_B,
bufo_144_Dout_B,
bufo_144_Clk_B,
bufo_144_Rst_B,
bufo_145_Addr_A,
bufo_145_EN_A,
bufo_145_WEN_A,
bufo_145_Din_A,
bufo_145_Dout_A,
bufo_145_Clk_A,
bufo_145_Rst_A,
bufo_145_Addr_B,
bufo_145_EN_B,
bufo_145_WEN_B,
bufo_145_Din_B,
bufo_145_Dout_B,
bufo_145_Clk_B,
bufo_145_Rst_B,
bufo_146_Addr_A,
bufo_146_EN_A,
bufo_146_WEN_A,
bufo_146_Din_A,
bufo_146_Dout_A,
bufo_146_Clk_A,
bufo_146_Rst_A,
bufo_146_Addr_B,
bufo_146_EN_B,
bufo_146_WEN_B,
bufo_146_Din_B,
bufo_146_Dout_B,
bufo_146_Clk_B,
bufo_146_Rst_B,
bufo_147_Addr_A,
bufo_147_EN_A,
bufo_147_WEN_A,
bufo_147_Din_A,
bufo_147_Dout_A,
bufo_147_Clk_A,
bufo_147_Rst_A,
bufo_147_Addr_B,
bufo_147_EN_B,
bufo_147_WEN_B,
bufo_147_Din_B,
bufo_147_Dout_B,
bufo_147_Clk_B,
bufo_147_Rst_B,
bufo_148_Addr_A,
bufo_148_EN_A,
bufo_148_WEN_A,
bufo_148_Din_A,
bufo_148_Dout_A,
bufo_148_Clk_A,
bufo_148_Rst_A,
bufo_148_Addr_B,
bufo_148_EN_B,
bufo_148_WEN_B,
bufo_148_Din_B,
bufo_148_Dout_B,
bufo_148_Clk_B,
bufo_148_Rst_B,
bufo_149_Addr_A,
bufo_149_EN_A,
bufo_149_WEN_A,
bufo_149_Din_A,
bufo_149_Dout_A,
bufo_149_Clk_A,
bufo_149_Rst_A,
bufo_149_Addr_B,
bufo_149_EN_B,
bufo_149_WEN_B,
bufo_149_Din_B,
bufo_149_Dout_B,
bufo_149_Clk_B,
bufo_149_Rst_B,
bufo_150_Addr_A,
bufo_150_EN_A,
bufo_150_WEN_A,
bufo_150_Din_A,
bufo_150_Dout_A,
bufo_150_Clk_A,
bufo_150_Rst_A,
bufo_150_Addr_B,
bufo_150_EN_B,
bufo_150_WEN_B,
bufo_150_Din_B,
bufo_150_Dout_B,
bufo_150_Clk_B,
bufo_150_Rst_B,
bufo_151_Addr_A,
bufo_151_EN_A,
bufo_151_WEN_A,
bufo_151_Din_A,
bufo_151_Dout_A,
bufo_151_Clk_A,
bufo_151_Rst_A,
bufo_151_Addr_B,
bufo_151_EN_B,
bufo_151_WEN_B,
bufo_151_Din_B,
bufo_151_Dout_B,
bufo_151_Clk_B,
bufo_151_Rst_B,
bufo_152_Addr_A,
bufo_152_EN_A,
bufo_152_WEN_A,
bufo_152_Din_A,
bufo_152_Dout_A,
bufo_152_Clk_A,
bufo_152_Rst_A,
bufo_152_Addr_B,
bufo_152_EN_B,
bufo_152_WEN_B,
bufo_152_Din_B,
bufo_152_Dout_B,
bufo_152_Clk_B,
bufo_152_Rst_B,
bufo_153_Addr_A,
bufo_153_EN_A,
bufo_153_WEN_A,
bufo_153_Din_A,
bufo_153_Dout_A,
bufo_153_Clk_A,
bufo_153_Rst_A,
bufo_153_Addr_B,
bufo_153_EN_B,
bufo_153_WEN_B,
bufo_153_Din_B,
bufo_153_Dout_B,
bufo_153_Clk_B,
bufo_153_Rst_B,
bufo_154_Addr_A,
bufo_154_EN_A,
bufo_154_WEN_A,
bufo_154_Din_A,
bufo_154_Dout_A,
bufo_154_Clk_A,
bufo_154_Rst_A,
bufo_154_Addr_B,
bufo_154_EN_B,
bufo_154_WEN_B,
bufo_154_Din_B,
bufo_154_Dout_B,
bufo_154_Clk_B,
bufo_154_Rst_B,
bufo_155_Addr_A,
bufo_155_EN_A,
bufo_155_WEN_A,
bufo_155_Din_A,
bufo_155_Dout_A,
bufo_155_Clk_A,
bufo_155_Rst_A,
bufo_155_Addr_B,
bufo_155_EN_B,
bufo_155_WEN_B,
bufo_155_Din_B,
bufo_155_Dout_B,
bufo_155_Clk_B,
bufo_155_Rst_B,
bufo_156_Addr_A,
bufo_156_EN_A,
bufo_156_WEN_A,
bufo_156_Din_A,
bufo_156_Dout_A,
bufo_156_Clk_A,
bufo_156_Rst_A,
bufo_156_Addr_B,
bufo_156_EN_B,
bufo_156_WEN_B,
bufo_156_Din_B,
bufo_156_Dout_B,
bufo_156_Clk_B,
bufo_156_Rst_B,
bufo_157_Addr_A,
bufo_157_EN_A,
bufo_157_WEN_A,
bufo_157_Din_A,
bufo_157_Dout_A,
bufo_157_Clk_A,
bufo_157_Rst_A,
bufo_157_Addr_B,
bufo_157_EN_B,
bufo_157_WEN_B,
bufo_157_Din_B,
bufo_157_Dout_B,
bufo_157_Clk_B,
bufo_157_Rst_B,
bufo_158_Addr_A,
bufo_158_EN_A,
bufo_158_WEN_A,
bufo_158_Din_A,
bufo_158_Dout_A,
bufo_158_Clk_A,
bufo_158_Rst_A,
bufo_158_Addr_B,
bufo_158_EN_B,
bufo_158_WEN_B,
bufo_158_Din_B,
bufo_158_Dout_B,
bufo_158_Clk_B,
bufo_158_Rst_B,
bufo_159_Addr_A,
bufo_159_EN_A,
bufo_159_WEN_A,
bufo_159_Din_A,
bufo_159_Dout_A,
bufo_159_Clk_A,
bufo_159_Rst_A,
bufo_159_Addr_B,
bufo_159_EN_B,
bufo_159_WEN_B,
bufo_159_Din_B,
bufo_159_Dout_B,
bufo_159_Clk_B,
bufo_159_Rst_B,
bufo_160_Addr_A,
bufo_160_EN_A,
bufo_160_WEN_A,
bufo_160_Din_A,
bufo_160_Dout_A,
bufo_160_Clk_A,
bufo_160_Rst_A,
bufo_160_Addr_B,
bufo_160_EN_B,
bufo_160_WEN_B,
bufo_160_Din_B,
bufo_160_Dout_B,
bufo_160_Clk_B,
bufo_160_Rst_B,
bufo_161_Addr_A,
bufo_161_EN_A,
bufo_161_WEN_A,
bufo_161_Din_A,
bufo_161_Dout_A,
bufo_161_Clk_A,
bufo_161_Rst_A,
bufo_161_Addr_B,
bufo_161_EN_B,
bufo_161_WEN_B,
bufo_161_Din_B,
bufo_161_Dout_B,
bufo_161_Clk_B,
bufo_161_Rst_B,
bufo_162_Addr_A,
bufo_162_EN_A,
bufo_162_WEN_A,
bufo_162_Din_A,
bufo_162_Dout_A,
bufo_162_Clk_A,
bufo_162_Rst_A,
bufo_162_Addr_B,
bufo_162_EN_B,
bufo_162_WEN_B,
bufo_162_Din_B,
bufo_162_Dout_B,
bufo_162_Clk_B,
bufo_162_Rst_B,
bufo_163_Addr_A,
bufo_163_EN_A,
bufo_163_WEN_A,
bufo_163_Din_A,
bufo_163_Dout_A,
bufo_163_Clk_A,
bufo_163_Rst_A,
bufo_163_Addr_B,
bufo_163_EN_B,
bufo_163_WEN_B,
bufo_163_Din_B,
bufo_163_Dout_B,
bufo_163_Clk_B,
bufo_163_Rst_B,
bufo_164_Addr_A,
bufo_164_EN_A,
bufo_164_WEN_A,
bufo_164_Din_A,
bufo_164_Dout_A,
bufo_164_Clk_A,
bufo_164_Rst_A,
bufo_164_Addr_B,
bufo_164_EN_B,
bufo_164_WEN_B,
bufo_164_Din_B,
bufo_164_Dout_B,
bufo_164_Clk_B,
bufo_164_Rst_B,
bufo_165_Addr_A,
bufo_165_EN_A,
bufo_165_WEN_A,
bufo_165_Din_A,
bufo_165_Dout_A,
bufo_165_Clk_A,
bufo_165_Rst_A,
bufo_165_Addr_B,
bufo_165_EN_B,
bufo_165_WEN_B,
bufo_165_Din_B,
bufo_165_Dout_B,
bufo_165_Clk_B,
bufo_165_Rst_B,
bufo_166_Addr_A,
bufo_166_EN_A,
bufo_166_WEN_A,
bufo_166_Din_A,
bufo_166_Dout_A,
bufo_166_Clk_A,
bufo_166_Rst_A,
bufo_166_Addr_B,
bufo_166_EN_B,
bufo_166_WEN_B,
bufo_166_Din_B,
bufo_166_Dout_B,
bufo_166_Clk_B,
bufo_166_Rst_B,
bufo_167_Addr_A,
bufo_167_EN_A,
bufo_167_WEN_A,
bufo_167_Din_A,
bufo_167_Dout_A,
bufo_167_Clk_A,
bufo_167_Rst_A,
bufo_167_Addr_B,
bufo_167_EN_B,
bufo_167_WEN_B,
bufo_167_Din_B,
bufo_167_Dout_B,
bufo_167_Clk_B,
bufo_167_Rst_B,
bufo_168_Addr_A,
bufo_168_EN_A,
bufo_168_WEN_A,
bufo_168_Din_A,
bufo_168_Dout_A,
bufo_168_Clk_A,
bufo_168_Rst_A,
bufo_168_Addr_B,
bufo_168_EN_B,
bufo_168_WEN_B,
bufo_168_Din_B,
bufo_168_Dout_B,
bufo_168_Clk_B,
bufo_168_Rst_B,
bufo_169_Addr_A,
bufo_169_EN_A,
bufo_169_WEN_A,
bufo_169_Din_A,
bufo_169_Dout_A,
bufo_169_Clk_A,
bufo_169_Rst_A,
bufo_169_Addr_B,
bufo_169_EN_B,
bufo_169_WEN_B,
bufo_169_Din_B,
bufo_169_Dout_B,
bufo_169_Clk_B,
bufo_169_Rst_B,
bufo_170_Addr_A,
bufo_170_EN_A,
bufo_170_WEN_A,
bufo_170_Din_A,
bufo_170_Dout_A,
bufo_170_Clk_A,
bufo_170_Rst_A,
bufo_170_Addr_B,
bufo_170_EN_B,
bufo_170_WEN_B,
bufo_170_Din_B,
bufo_170_Dout_B,
bufo_170_Clk_B,
bufo_170_Rst_B,
bufo_171_Addr_A,
bufo_171_EN_A,
bufo_171_WEN_A,
bufo_171_Din_A,
bufo_171_Dout_A,
bufo_171_Clk_A,
bufo_171_Rst_A,
bufo_171_Addr_B,
bufo_171_EN_B,
bufo_171_WEN_B,
bufo_171_Din_B,
bufo_171_Dout_B,
bufo_171_Clk_B,
bufo_171_Rst_B,
bufo_172_Addr_A,
bufo_172_EN_A,
bufo_172_WEN_A,
bufo_172_Din_A,
bufo_172_Dout_A,
bufo_172_Clk_A,
bufo_172_Rst_A,
bufo_172_Addr_B,
bufo_172_EN_B,
bufo_172_WEN_B,
bufo_172_Din_B,
bufo_172_Dout_B,
bufo_172_Clk_B,
bufo_172_Rst_B,
bufo_173_Addr_A,
bufo_173_EN_A,
bufo_173_WEN_A,
bufo_173_Din_A,
bufo_173_Dout_A,
bufo_173_Clk_A,
bufo_173_Rst_A,
bufo_173_Addr_B,
bufo_173_EN_B,
bufo_173_WEN_B,
bufo_173_Din_B,
bufo_173_Dout_B,
bufo_173_Clk_B,
bufo_173_Rst_B,
bufo_174_Addr_A,
bufo_174_EN_A,
bufo_174_WEN_A,
bufo_174_Din_A,
bufo_174_Dout_A,
bufo_174_Clk_A,
bufo_174_Rst_A,
bufo_174_Addr_B,
bufo_174_EN_B,
bufo_174_WEN_B,
bufo_174_Din_B,
bufo_174_Dout_B,
bufo_174_Clk_B,
bufo_174_Rst_B,
bufo_175_Addr_A,
bufo_175_EN_A,
bufo_175_WEN_A,
bufo_175_Din_A,
bufo_175_Dout_A,
bufo_175_Clk_A,
bufo_175_Rst_A,
bufo_175_Addr_B,
bufo_175_EN_B,
bufo_175_WEN_B,
bufo_175_Din_B,
bufo_175_Dout_B,
bufo_175_Clk_B,
bufo_175_Rst_B,
bufo_176_Addr_A,
bufo_176_EN_A,
bufo_176_WEN_A,
bufo_176_Din_A,
bufo_176_Dout_A,
bufo_176_Clk_A,
bufo_176_Rst_A,
bufo_176_Addr_B,
bufo_176_EN_B,
bufo_176_WEN_B,
bufo_176_Din_B,
bufo_176_Dout_B,
bufo_176_Clk_B,
bufo_176_Rst_B,
bufo_177_Addr_A,
bufo_177_EN_A,
bufo_177_WEN_A,
bufo_177_Din_A,
bufo_177_Dout_A,
bufo_177_Clk_A,
bufo_177_Rst_A,
bufo_177_Addr_B,
bufo_177_EN_B,
bufo_177_WEN_B,
bufo_177_Din_B,
bufo_177_Dout_B,
bufo_177_Clk_B,
bufo_177_Rst_B,
bufo_178_Addr_A,
bufo_178_EN_A,
bufo_178_WEN_A,
bufo_178_Din_A,
bufo_178_Dout_A,
bufo_178_Clk_A,
bufo_178_Rst_A,
bufo_178_Addr_B,
bufo_178_EN_B,
bufo_178_WEN_B,
bufo_178_Din_B,
bufo_178_Dout_B,
bufo_178_Clk_B,
bufo_178_Rst_B,
bufo_179_Addr_A,
bufo_179_EN_A,
bufo_179_WEN_A,
bufo_179_Din_A,
bufo_179_Dout_A,
bufo_179_Clk_A,
bufo_179_Rst_A,
bufo_179_Addr_B,
bufo_179_EN_B,
bufo_179_WEN_B,
bufo_179_Din_B,
bufo_179_Dout_B,
bufo_179_Clk_B,
bufo_179_Rst_B,
bufo_180_Addr_A,
bufo_180_EN_A,
bufo_180_WEN_A,
bufo_180_Din_A,
bufo_180_Dout_A,
bufo_180_Clk_A,
bufo_180_Rst_A,
bufo_180_Addr_B,
bufo_180_EN_B,
bufo_180_WEN_B,
bufo_180_Din_B,
bufo_180_Dout_B,
bufo_180_Clk_B,
bufo_180_Rst_B,
bufo_181_Addr_A,
bufo_181_EN_A,
bufo_181_WEN_A,
bufo_181_Din_A,
bufo_181_Dout_A,
bufo_181_Clk_A,
bufo_181_Rst_A,
bufo_181_Addr_B,
bufo_181_EN_B,
bufo_181_WEN_B,
bufo_181_Din_B,
bufo_181_Dout_B,
bufo_181_Clk_B,
bufo_181_Rst_B,
bufo_182_Addr_A,
bufo_182_EN_A,
bufo_182_WEN_A,
bufo_182_Din_A,
bufo_182_Dout_A,
bufo_182_Clk_A,
bufo_182_Rst_A,
bufo_182_Addr_B,
bufo_182_EN_B,
bufo_182_WEN_B,
bufo_182_Din_B,
bufo_182_Dout_B,
bufo_182_Clk_B,
bufo_182_Rst_B,
bufo_183_Addr_A,
bufo_183_EN_A,
bufo_183_WEN_A,
bufo_183_Din_A,
bufo_183_Dout_A,
bufo_183_Clk_A,
bufo_183_Rst_A,
bufo_183_Addr_B,
bufo_183_EN_B,
bufo_183_WEN_B,
bufo_183_Din_B,
bufo_183_Dout_B,
bufo_183_Clk_B,
bufo_183_Rst_B,
bufo_184_Addr_A,
bufo_184_EN_A,
bufo_184_WEN_A,
bufo_184_Din_A,
bufo_184_Dout_A,
bufo_184_Clk_A,
bufo_184_Rst_A,
bufo_184_Addr_B,
bufo_184_EN_B,
bufo_184_WEN_B,
bufo_184_Din_B,
bufo_184_Dout_B,
bufo_184_Clk_B,
bufo_184_Rst_B,
bufo_185_Addr_A,
bufo_185_EN_A,
bufo_185_WEN_A,
bufo_185_Din_A,
bufo_185_Dout_A,
bufo_185_Clk_A,
bufo_185_Rst_A,
bufo_185_Addr_B,
bufo_185_EN_B,
bufo_185_WEN_B,
bufo_185_Din_B,
bufo_185_Dout_B,
bufo_185_Clk_B,
bufo_185_Rst_B,
bufo_186_Addr_A,
bufo_186_EN_A,
bufo_186_WEN_A,
bufo_186_Din_A,
bufo_186_Dout_A,
bufo_186_Clk_A,
bufo_186_Rst_A,
bufo_186_Addr_B,
bufo_186_EN_B,
bufo_186_WEN_B,
bufo_186_Din_B,
bufo_186_Dout_B,
bufo_186_Clk_B,
bufo_186_Rst_B,
bufo_187_Addr_A,
bufo_187_EN_A,
bufo_187_WEN_A,
bufo_187_Din_A,
bufo_187_Dout_A,
bufo_187_Clk_A,
bufo_187_Rst_A,
bufo_187_Addr_B,
bufo_187_EN_B,
bufo_187_WEN_B,
bufo_187_Din_B,
bufo_187_Dout_B,
bufo_187_Clk_B,
bufo_187_Rst_B,
bufo_188_Addr_A,
bufo_188_EN_A,
bufo_188_WEN_A,
bufo_188_Din_A,
bufo_188_Dout_A,
bufo_188_Clk_A,
bufo_188_Rst_A,
bufo_188_Addr_B,
bufo_188_EN_B,
bufo_188_WEN_B,
bufo_188_Din_B,
bufo_188_Dout_B,
bufo_188_Clk_B,
bufo_188_Rst_B,
bufo_189_Addr_A,
bufo_189_EN_A,
bufo_189_WEN_A,
bufo_189_Din_A,
bufo_189_Dout_A,
bufo_189_Clk_A,
bufo_189_Rst_A,
bufo_189_Addr_B,
bufo_189_EN_B,
bufo_189_WEN_B,
bufo_189_Din_B,
bufo_189_Dout_B,
bufo_189_Clk_B,
bufo_189_Rst_B,
bufo_190_Addr_A,
bufo_190_EN_A,
bufo_190_WEN_A,
bufo_190_Din_A,
bufo_190_Dout_A,
bufo_190_Clk_A,
bufo_190_Rst_A,
bufo_190_Addr_B,
bufo_190_EN_B,
bufo_190_WEN_B,
bufo_190_Din_B,
bufo_190_Dout_B,
bufo_190_Clk_B,
bufo_190_Rst_B,
bufo_191_Addr_A,
bufo_191_EN_A,
bufo_191_WEN_A,
bufo_191_Din_A,
bufo_191_Dout_A,
bufo_191_Clk_A,
bufo_191_Rst_A,
bufo_191_Addr_B,
bufo_191_EN_B,
bufo_191_WEN_B,
bufo_191_Din_B,
bufo_191_Dout_B,
bufo_191_Clk_B,
bufo_191_Rst_B,
bufo_192_Addr_A,
bufo_192_EN_A,
bufo_192_WEN_A,
bufo_192_Din_A,
bufo_192_Dout_A,
bufo_192_Clk_A,
bufo_192_Rst_A,
bufo_192_Addr_B,
bufo_192_EN_B,
bufo_192_WEN_B,
bufo_192_Din_B,
bufo_192_Dout_B,
bufo_192_Clk_B,
bufo_192_Rst_B,
bufo_193_Addr_A,
bufo_193_EN_A,
bufo_193_WEN_A,
bufo_193_Din_A,
bufo_193_Dout_A,
bufo_193_Clk_A,
bufo_193_Rst_A,
bufo_193_Addr_B,
bufo_193_EN_B,
bufo_193_WEN_B,
bufo_193_Din_B,
bufo_193_Dout_B,
bufo_193_Clk_B,
bufo_193_Rst_B,
bufo_194_Addr_A,
bufo_194_EN_A,
bufo_194_WEN_A,
bufo_194_Din_A,
bufo_194_Dout_A,
bufo_194_Clk_A,
bufo_194_Rst_A,
bufo_194_Addr_B,
bufo_194_EN_B,
bufo_194_WEN_B,
bufo_194_Din_B,
bufo_194_Dout_B,
bufo_194_Clk_B,
bufo_194_Rst_B,
bufo_195_Addr_A,
bufo_195_EN_A,
bufo_195_WEN_A,
bufo_195_Din_A,
bufo_195_Dout_A,
bufo_195_Clk_A,
bufo_195_Rst_A,
bufo_195_Addr_B,
bufo_195_EN_B,
bufo_195_WEN_B,
bufo_195_Din_B,
bufo_195_Dout_B,
bufo_195_Clk_B,
bufo_195_Rst_B,
bufo_196_Addr_A,
bufo_196_EN_A,
bufo_196_WEN_A,
bufo_196_Din_A,
bufo_196_Dout_A,
bufo_196_Clk_A,
bufo_196_Rst_A,
bufo_196_Addr_B,
bufo_196_EN_B,
bufo_196_WEN_B,
bufo_196_Din_B,
bufo_196_Dout_B,
bufo_196_Clk_B,
bufo_196_Rst_B,
bufo_197_Addr_A,
bufo_197_EN_A,
bufo_197_WEN_A,
bufo_197_Din_A,
bufo_197_Dout_A,
bufo_197_Clk_A,
bufo_197_Rst_A,
bufo_197_Addr_B,
bufo_197_EN_B,
bufo_197_WEN_B,
bufo_197_Din_B,
bufo_197_Dout_B,
bufo_197_Clk_B,
bufo_197_Rst_B,
bufo_198_Addr_A,
bufo_198_EN_A,
bufo_198_WEN_A,
bufo_198_Din_A,
bufo_198_Dout_A,
bufo_198_Clk_A,
bufo_198_Rst_A,
bufo_198_Addr_B,
bufo_198_EN_B,
bufo_198_WEN_B,
bufo_198_Din_B,
bufo_198_Dout_B,
bufo_198_Clk_B,
bufo_198_Rst_B,
bufo_199_Addr_A,
bufo_199_EN_A,
bufo_199_WEN_A,
bufo_199_Din_A,
bufo_199_Dout_A,
bufo_199_Clk_A,
bufo_199_Rst_A,
bufo_199_Addr_B,
bufo_199_EN_B,
bufo_199_WEN_B,
bufo_199_Din_B,
bufo_199_Dout_B,
bufo_199_Clk_B,
bufo_199_Rst_B
);
parameter ap_ST_fsm_state1 = 56'd1;
parameter ap_ST_fsm_state2 = 56'd2;
parameter ap_ST_fsm_state3 = 56'd4;
parameter ap_ST_fsm_state4 = 56'd8;
parameter ap_ST_fsm_state5 = 56'd16;
parameter ap_ST_fsm_state6 = 56'd32;
parameter ap_ST_fsm_state7 = 56'd64;
parameter ap_ST_fsm_state8 = 56'd128;
parameter ap_ST_fsm_state9 = 56'd256;
parameter ap_ST_fsm_state10 = 56'd512;
parameter ap_ST_fsm_state11 = 56'd1024;
parameter ap_ST_fsm_state12 = 56'd2048;
parameter ap_ST_fsm_state13 = 56'd4096;
parameter ap_ST_fsm_state14 = 56'd8192;
parameter ap_ST_fsm_state15 = 56'd16384;
parameter ap_ST_fsm_state16 = 56'd32768;
parameter ap_ST_fsm_state17 = 56'd65536;
parameter ap_ST_fsm_state18 = 56'd131072;
parameter ap_ST_fsm_state19 = 56'd262144;
parameter ap_ST_fsm_state20 = 56'd524288;
parameter ap_ST_fsm_state21 = 56'd1048576;
parameter ap_ST_fsm_state22 = 56'd2097152;
parameter ap_ST_fsm_state23 = 56'd4194304;
parameter ap_ST_fsm_state24 = 56'd8388608;
parameter ap_ST_fsm_state25 = 56'd16777216;
parameter ap_ST_fsm_state26 = 56'd33554432;
parameter ap_ST_fsm_state27 = 56'd67108864;
parameter ap_ST_fsm_state28 = 56'd134217728;
parameter ap_ST_fsm_state29 = 56'd268435456;
parameter ap_ST_fsm_state30 = 56'd536870912;
parameter ap_ST_fsm_state31 = 56'd1073741824;
parameter ap_ST_fsm_state32 = 56'd2147483648;
parameter ap_ST_fsm_state33 = 56'd4294967296;
parameter ap_ST_fsm_state34 = 56'd8589934592;
parameter ap_ST_fsm_state35 = 56'd17179869184;
parameter ap_ST_fsm_state36 = 56'd34359738368;
parameter ap_ST_fsm_state37 = 56'd68719476736;
parameter ap_ST_fsm_state38 = 56'd137438953472;
parameter ap_ST_fsm_state39 = 56'd274877906944;
parameter ap_ST_fsm_state40 = 56'd549755813888;
parameter ap_ST_fsm_state41 = 56'd1099511627776;
parameter ap_ST_fsm_state42 = 56'd2199023255552;
parameter ap_ST_fsm_state43 = 56'd4398046511104;
parameter ap_ST_fsm_state44 = 56'd8796093022208;
parameter ap_ST_fsm_state45 = 56'd17592186044416;
parameter ap_ST_fsm_state46 = 56'd35184372088832;
parameter ap_ST_fsm_state47 = 56'd70368744177664;
parameter ap_ST_fsm_state48 = 56'd140737488355328;
parameter ap_ST_fsm_state49 = 56'd281474976710656;
parameter ap_ST_fsm_state50 = 56'd562949953421312;
parameter ap_ST_fsm_state51 = 56'd1125899906842624;
parameter ap_ST_fsm_state52 = 56'd2251799813685248;
parameter ap_ST_fsm_state53 = 56'd4503599627370496;
parameter ap_ST_fsm_state54 = 56'd9007199254740992;
parameter ap_ST_fsm_state55 = 56'd18014398509481984;
parameter ap_ST_fsm_state56 = 56'd36028797018963968;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] bufw_Addr_A;
output bufw_EN_A;
output [15:0] bufw_WEN_A;
output [127:0] bufw_Din_A;
input [127:0] bufw_Dout_A;
output bufw_Clk_A;
output bufw_Rst_A;
output [31:0] bufi_Addr_A;
output bufi_EN_A;
output [15:0] bufi_WEN_A;
output [127:0] bufi_Din_A;
input [127:0] bufi_Dout_A;
output bufi_Clk_A;
output bufi_Rst_A;
output [31:0] bufo_0_Addr_A;
output bufo_0_EN_A;
output [3:0] bufo_0_WEN_A;
output [31:0] bufo_0_Din_A;
input [31:0] bufo_0_Dout_A;
output bufo_0_Clk_A;
output bufo_0_Rst_A;
output [31:0] bufo_1_Addr_A;
output bufo_1_EN_A;
output [3:0] bufo_1_WEN_A;
output [31:0] bufo_1_Din_A;
input [31:0] bufo_1_Dout_A;
output bufo_1_Clk_A;
output bufo_1_Rst_A;
output [31:0] bufo_2_Addr_A;
output bufo_2_EN_A;
output [3:0] bufo_2_WEN_A;
output [31:0] bufo_2_Din_A;
input [31:0] bufo_2_Dout_A;
output bufo_2_Clk_A;
output bufo_2_Rst_A;
output [31:0] bufo_3_Addr_A;
output bufo_3_EN_A;
output [3:0] bufo_3_WEN_A;
output [31:0] bufo_3_Din_A;
input [31:0] bufo_3_Dout_A;
output bufo_3_Clk_A;
output bufo_3_Rst_A;
output [31:0] bufo_4_Addr_A;
output bufo_4_EN_A;
output [3:0] bufo_4_WEN_A;
output [31:0] bufo_4_Din_A;
input [31:0] bufo_4_Dout_A;
output bufo_4_Clk_A;
output bufo_4_Rst_A;
output [31:0] bufo_5_Addr_A;
output bufo_5_EN_A;
output [3:0] bufo_5_WEN_A;
output [31:0] bufo_5_Din_A;
input [31:0] bufo_5_Dout_A;
output bufo_5_Clk_A;
output bufo_5_Rst_A;
output [31:0] bufo_6_Addr_A;
output bufo_6_EN_A;
output [3:0] bufo_6_WEN_A;
output [31:0] bufo_6_Din_A;
input [31:0] bufo_6_Dout_A;
output bufo_6_Clk_A;
output bufo_6_Rst_A;
output [31:0] bufo_7_Addr_A;
output bufo_7_EN_A;
output [3:0] bufo_7_WEN_A;
output [31:0] bufo_7_Din_A;
input [31:0] bufo_7_Dout_A;
output bufo_7_Clk_A;
output bufo_7_Rst_A;
output [31:0] bufo_8_Addr_A;
output bufo_8_EN_A;
output [3:0] bufo_8_WEN_A;
output [31:0] bufo_8_Din_A;
input [31:0] bufo_8_Dout_A;
output bufo_8_Clk_A;
output bufo_8_Rst_A;
output [31:0] bufo_9_Addr_A;
output bufo_9_EN_A;
output [3:0] bufo_9_WEN_A;
output [31:0] bufo_9_Din_A;
input [31:0] bufo_9_Dout_A;
output bufo_9_Clk_A;
output bufo_9_Rst_A;
output [31:0] bufo_10_Addr_A;
output bufo_10_EN_A;
output [3:0] bufo_10_WEN_A;
output [31:0] bufo_10_Din_A;
input [31:0] bufo_10_Dout_A;
output bufo_10_Clk_A;
output bufo_10_Rst_A;
output [31:0] bufo_11_Addr_A;
output bufo_11_EN_A;
output [3:0] bufo_11_WEN_A;
output [31:0] bufo_11_Din_A;
input [31:0] bufo_11_Dout_A;
output bufo_11_Clk_A;
output bufo_11_Rst_A;
output [31:0] bufo_12_Addr_A;
output bufo_12_EN_A;
output [3:0] bufo_12_WEN_A;
output [31:0] bufo_12_Din_A;
input [31:0] bufo_12_Dout_A;
output bufo_12_Clk_A;
output bufo_12_Rst_A;
output [31:0] bufo_13_Addr_A;
output bufo_13_EN_A;
output [3:0] bufo_13_WEN_A;
output [31:0] bufo_13_Din_A;
input [31:0] bufo_13_Dout_A;
output bufo_13_Clk_A;
output bufo_13_Rst_A;
output [31:0] bufo_14_Addr_A;
output bufo_14_EN_A;
output [3:0] bufo_14_WEN_A;
output [31:0] bufo_14_Din_A;
input [31:0] bufo_14_Dout_A;
output bufo_14_Clk_A;
output bufo_14_Rst_A;
output [31:0] bufo_15_Addr_A;
output bufo_15_EN_A;
output [3:0] bufo_15_WEN_A;
output [31:0] bufo_15_Din_A;
input [31:0] bufo_15_Dout_A;
output bufo_15_Clk_A;
output bufo_15_Rst_A;
output [31:0] bufo_16_Addr_A;
output bufo_16_EN_A;
output [3:0] bufo_16_WEN_A;
output [31:0] bufo_16_Din_A;
input [31:0] bufo_16_Dout_A;
output bufo_16_Clk_A;
output bufo_16_Rst_A;
output [31:0] bufo_17_Addr_A;
output bufo_17_EN_A;
output [3:0] bufo_17_WEN_A;
output [31:0] bufo_17_Din_A;
input [31:0] bufo_17_Dout_A;
output bufo_17_Clk_A;
output bufo_17_Rst_A;
output [31:0] bufo_18_Addr_A;
output bufo_18_EN_A;
output [3:0] bufo_18_WEN_A;
output [31:0] bufo_18_Din_A;
input [31:0] bufo_18_Dout_A;
output bufo_18_Clk_A;
output bufo_18_Rst_A;
output [31:0] bufo_19_Addr_A;
output bufo_19_EN_A;
output [3:0] bufo_19_WEN_A;
output [31:0] bufo_19_Din_A;
input [31:0] bufo_19_Dout_A;
output bufo_19_Clk_A;
output bufo_19_Rst_A;
output [31:0] bufo_20_Addr_A;
output bufo_20_EN_A;
output [3:0] bufo_20_WEN_A;
output [31:0] bufo_20_Din_A;
input [31:0] bufo_20_Dout_A;
output bufo_20_Clk_A;
output bufo_20_Rst_A;
output [31:0] bufo_21_Addr_A;
output bufo_21_EN_A;
output [3:0] bufo_21_WEN_A;
output [31:0] bufo_21_Din_A;
input [31:0] bufo_21_Dout_A;
output bufo_21_Clk_A;
output bufo_21_Rst_A;
output [31:0] bufo_22_Addr_A;
output bufo_22_EN_A;
output [3:0] bufo_22_WEN_A;
output [31:0] bufo_22_Din_A;
input [31:0] bufo_22_Dout_A;
output bufo_22_Clk_A;
output bufo_22_Rst_A;
output [31:0] bufo_23_Addr_A;
output bufo_23_EN_A;
output [3:0] bufo_23_WEN_A;
output [31:0] bufo_23_Din_A;
input [31:0] bufo_23_Dout_A;
output bufo_23_Clk_A;
output bufo_23_Rst_A;
output [31:0] bufo_24_Addr_A;
output bufo_24_EN_A;
output [3:0] bufo_24_WEN_A;
output [31:0] bufo_24_Din_A;
input [31:0] bufo_24_Dout_A;
output bufo_24_Clk_A;
output bufo_24_Rst_A;
output [31:0] bufo_25_Addr_A;
output bufo_25_EN_A;
output [3:0] bufo_25_WEN_A;
output [31:0] bufo_25_Din_A;
input [31:0] bufo_25_Dout_A;
output bufo_25_Clk_A;
output bufo_25_Rst_A;
output [31:0] bufo_26_Addr_A;
output bufo_26_EN_A;
output [3:0] bufo_26_WEN_A;
output [31:0] bufo_26_Din_A;
input [31:0] bufo_26_Dout_A;
output bufo_26_Clk_A;
output bufo_26_Rst_A;
output [31:0] bufo_27_Addr_A;
output bufo_27_EN_A;
output [3:0] bufo_27_WEN_A;
output [31:0] bufo_27_Din_A;
input [31:0] bufo_27_Dout_A;
output bufo_27_Clk_A;
output bufo_27_Rst_A;
output [31:0] bufo_28_Addr_A;
output bufo_28_EN_A;
output [3:0] bufo_28_WEN_A;
output [31:0] bufo_28_Din_A;
input [31:0] bufo_28_Dout_A;
output bufo_28_Clk_A;
output bufo_28_Rst_A;
output [31:0] bufo_29_Addr_A;
output bufo_29_EN_A;
output [3:0] bufo_29_WEN_A;
output [31:0] bufo_29_Din_A;
input [31:0] bufo_29_Dout_A;
output bufo_29_Clk_A;
output bufo_29_Rst_A;
output [31:0] bufo_30_Addr_A;
output bufo_30_EN_A;
output [3:0] bufo_30_WEN_A;
output [31:0] bufo_30_Din_A;
input [31:0] bufo_30_Dout_A;
output bufo_30_Clk_A;
output bufo_30_Rst_A;
output [31:0] bufo_31_Addr_A;
output bufo_31_EN_A;
output [3:0] bufo_31_WEN_A;
output [31:0] bufo_31_Din_A;
input [31:0] bufo_31_Dout_A;
output bufo_31_Clk_A;
output bufo_31_Rst_A;
output [31:0] bufo_32_Addr_A;
output bufo_32_EN_A;
output [3:0] bufo_32_WEN_A;
output [31:0] bufo_32_Din_A;
input [31:0] bufo_32_Dout_A;
output bufo_32_Clk_A;
output bufo_32_Rst_A;
output [31:0] bufo_33_Addr_A;
output bufo_33_EN_A;
output [3:0] bufo_33_WEN_A;
output [31:0] bufo_33_Din_A;
input [31:0] bufo_33_Dout_A;
output bufo_33_Clk_A;
output bufo_33_Rst_A;
output [31:0] bufo_34_Addr_A;
output bufo_34_EN_A;
output [3:0] bufo_34_WEN_A;
output [31:0] bufo_34_Din_A;
input [31:0] bufo_34_Dout_A;
output bufo_34_Clk_A;
output bufo_34_Rst_A;
output [31:0] bufo_35_Addr_A;
output bufo_35_EN_A;
output [3:0] bufo_35_WEN_A;
output [31:0] bufo_35_Din_A;
input [31:0] bufo_35_Dout_A;
output bufo_35_Clk_A;
output bufo_35_Rst_A;
output [31:0] bufo_36_Addr_A;
output bufo_36_EN_A;
output [3:0] bufo_36_WEN_A;
output [31:0] bufo_36_Din_A;
input [31:0] bufo_36_Dout_A;
output bufo_36_Clk_A;
output bufo_36_Rst_A;
output [31:0] bufo_37_Addr_A;
output bufo_37_EN_A;
output [3:0] bufo_37_WEN_A;
output [31:0] bufo_37_Din_A;
input [31:0] bufo_37_Dout_A;
output bufo_37_Clk_A;
output bufo_37_Rst_A;
output [31:0] bufo_38_Addr_A;
output bufo_38_EN_A;
output [3:0] bufo_38_WEN_A;
output [31:0] bufo_38_Din_A;
input [31:0] bufo_38_Dout_A;
output bufo_38_Clk_A;
output bufo_38_Rst_A;
output [31:0] bufo_39_Addr_A;
output bufo_39_EN_A;
output [3:0] bufo_39_WEN_A;
output [31:0] bufo_39_Din_A;
input [31:0] bufo_39_Dout_A;
output bufo_39_Clk_A;
output bufo_39_Rst_A;
output [31:0] bufo_40_Addr_A;
output bufo_40_EN_A;
output [3:0] bufo_40_WEN_A;
output [31:0] bufo_40_Din_A;
input [31:0] bufo_40_Dout_A;
output bufo_40_Clk_A;
output bufo_40_Rst_A;
output [31:0] bufo_41_Addr_A;
output bufo_41_EN_A;
output [3:0] bufo_41_WEN_A;
output [31:0] bufo_41_Din_A;
input [31:0] bufo_41_Dout_A;
output bufo_41_Clk_A;
output bufo_41_Rst_A;
output [31:0] bufo_42_Addr_A;
output bufo_42_EN_A;
output [3:0] bufo_42_WEN_A;
output [31:0] bufo_42_Din_A;
input [31:0] bufo_42_Dout_A;
output bufo_42_Clk_A;
output bufo_42_Rst_A;
output [31:0] bufo_43_Addr_A;
output bufo_43_EN_A;
output [3:0] bufo_43_WEN_A;
output [31:0] bufo_43_Din_A;
input [31:0] bufo_43_Dout_A;
output bufo_43_Clk_A;
output bufo_43_Rst_A;
output [31:0] bufo_44_Addr_A;
output bufo_44_EN_A;
output [3:0] bufo_44_WEN_A;
output [31:0] bufo_44_Din_A;
input [31:0] bufo_44_Dout_A;
output bufo_44_Clk_A;
output bufo_44_Rst_A;
output [31:0] bufo_45_Addr_A;
output bufo_45_EN_A;
output [3:0] bufo_45_WEN_A;
output [31:0] bufo_45_Din_A;
input [31:0] bufo_45_Dout_A;
output bufo_45_Clk_A;
output bufo_45_Rst_A;
output [31:0] bufo_46_Addr_A;
output bufo_46_EN_A;
output [3:0] bufo_46_WEN_A;
output [31:0] bufo_46_Din_A;
input [31:0] bufo_46_Dout_A;
output bufo_46_Clk_A;
output bufo_46_Rst_A;
output [31:0] bufo_47_Addr_A;
output bufo_47_EN_A;
output [3:0] bufo_47_WEN_A;
output [31:0] bufo_47_Din_A;
input [31:0] bufo_47_Dout_A;
output bufo_47_Clk_A;
output bufo_47_Rst_A;
output [31:0] bufo_48_Addr_A;
output bufo_48_EN_A;
output [3:0] bufo_48_WEN_A;
output [31:0] bufo_48_Din_A;
input [31:0] bufo_48_Dout_A;
output bufo_48_Clk_A;
output bufo_48_Rst_A;
output [31:0] bufo_49_Addr_A;
output bufo_49_EN_A;
output [3:0] bufo_49_WEN_A;
output [31:0] bufo_49_Din_A;
input [31:0] bufo_49_Dout_A;
output bufo_49_Clk_A;
output bufo_49_Rst_A;
output [31:0] bufo_50_Addr_A;
output bufo_50_EN_A;
output [3:0] bufo_50_WEN_A;
output [31:0] bufo_50_Din_A;
input [31:0] bufo_50_Dout_A;
output bufo_50_Clk_A;
output bufo_50_Rst_A;
output [31:0] bufo_51_Addr_A;
output bufo_51_EN_A;
output [3:0] bufo_51_WEN_A;
output [31:0] bufo_51_Din_A;
input [31:0] bufo_51_Dout_A;
output bufo_51_Clk_A;
output bufo_51_Rst_A;
output [31:0] bufo_52_Addr_A;
output bufo_52_EN_A;
output [3:0] bufo_52_WEN_A;
output [31:0] bufo_52_Din_A;
input [31:0] bufo_52_Dout_A;
output bufo_52_Clk_A;
output bufo_52_Rst_A;
output [31:0] bufo_53_Addr_A;
output bufo_53_EN_A;
output [3:0] bufo_53_WEN_A;
output [31:0] bufo_53_Din_A;
input [31:0] bufo_53_Dout_A;
output bufo_53_Clk_A;
output bufo_53_Rst_A;
output [31:0] bufo_54_Addr_A;
output bufo_54_EN_A;
output [3:0] bufo_54_WEN_A;
output [31:0] bufo_54_Din_A;
input [31:0] bufo_54_Dout_A;
output bufo_54_Clk_A;
output bufo_54_Rst_A;
output [31:0] bufo_55_Addr_A;
output bufo_55_EN_A;
output [3:0] bufo_55_WEN_A;
output [31:0] bufo_55_Din_A;
input [31:0] bufo_55_Dout_A;
output bufo_55_Clk_A;
output bufo_55_Rst_A;
output [31:0] bufo_56_Addr_A;
output bufo_56_EN_A;
output [3:0] bufo_56_WEN_A;
output [31:0] bufo_56_Din_A;
input [31:0] bufo_56_Dout_A;
output bufo_56_Clk_A;
output bufo_56_Rst_A;
output [31:0] bufo_57_Addr_A;
output bufo_57_EN_A;
output [3:0] bufo_57_WEN_A;
output [31:0] bufo_57_Din_A;
input [31:0] bufo_57_Dout_A;
output bufo_57_Clk_A;
output bufo_57_Rst_A;
output [31:0] bufo_58_Addr_A;
output bufo_58_EN_A;
output [3:0] bufo_58_WEN_A;
output [31:0] bufo_58_Din_A;
input [31:0] bufo_58_Dout_A;
output bufo_58_Clk_A;
output bufo_58_Rst_A;
output [31:0] bufo_59_Addr_A;
output bufo_59_EN_A;
output [3:0] bufo_59_WEN_A;
output [31:0] bufo_59_Din_A;
input [31:0] bufo_59_Dout_A;
output bufo_59_Clk_A;
output bufo_59_Rst_A;
output [31:0] bufo_60_Addr_A;
output bufo_60_EN_A;
output [3:0] bufo_60_WEN_A;
output [31:0] bufo_60_Din_A;
input [31:0] bufo_60_Dout_A;
output bufo_60_Clk_A;
output bufo_60_Rst_A;
output [31:0] bufo_61_Addr_A;
output bufo_61_EN_A;
output [3:0] bufo_61_WEN_A;
output [31:0] bufo_61_Din_A;
input [31:0] bufo_61_Dout_A;
output bufo_61_Clk_A;
output bufo_61_Rst_A;
output [31:0] bufo_62_Addr_A;
output bufo_62_EN_A;
output [3:0] bufo_62_WEN_A;
output [31:0] bufo_62_Din_A;
input [31:0] bufo_62_Dout_A;
output bufo_62_Clk_A;
output bufo_62_Rst_A;
output [31:0] bufo_63_Addr_A;
output bufo_63_EN_A;
output [3:0] bufo_63_WEN_A;
output [31:0] bufo_63_Din_A;
input [31:0] bufo_63_Dout_A;
output bufo_63_Clk_A;
output bufo_63_Rst_A;
output [31:0] bufo_64_Addr_A;
output bufo_64_EN_A;
output [3:0] bufo_64_WEN_A;
output [31:0] bufo_64_Din_A;
input [31:0] bufo_64_Dout_A;
output bufo_64_Clk_A;
output bufo_64_Rst_A;
output [31:0] bufo_65_Addr_A;
output bufo_65_EN_A;
output [3:0] bufo_65_WEN_A;
output [31:0] bufo_65_Din_A;
input [31:0] bufo_65_Dout_A;
output bufo_65_Clk_A;
output bufo_65_Rst_A;
output [31:0] bufo_66_Addr_A;
output bufo_66_EN_A;
output [3:0] bufo_66_WEN_A;
output [31:0] bufo_66_Din_A;
input [31:0] bufo_66_Dout_A;
output bufo_66_Clk_A;
output bufo_66_Rst_A;
output [31:0] bufo_67_Addr_A;
output bufo_67_EN_A;
output [3:0] bufo_67_WEN_A;
output [31:0] bufo_67_Din_A;
input [31:0] bufo_67_Dout_A;
output bufo_67_Clk_A;
output bufo_67_Rst_A;
output [31:0] bufo_68_Addr_A;
output bufo_68_EN_A;
output [3:0] bufo_68_WEN_A;
output [31:0] bufo_68_Din_A;
input [31:0] bufo_68_Dout_A;
output bufo_68_Clk_A;
output bufo_68_Rst_A;
output [31:0] bufo_69_Addr_A;
output bufo_69_EN_A;
output [3:0] bufo_69_WEN_A;
output [31:0] bufo_69_Din_A;
input [31:0] bufo_69_Dout_A;
output bufo_69_Clk_A;
output bufo_69_Rst_A;
output [31:0] bufo_70_Addr_A;
output bufo_70_EN_A;
output [3:0] bufo_70_WEN_A;
output [31:0] bufo_70_Din_A;
input [31:0] bufo_70_Dout_A;
output bufo_70_Clk_A;
output bufo_70_Rst_A;
output [31:0] bufo_71_Addr_A;
output bufo_71_EN_A;
output [3:0] bufo_71_WEN_A;
output [31:0] bufo_71_Din_A;
input [31:0] bufo_71_Dout_A;
output bufo_71_Clk_A;
output bufo_71_Rst_A;
output [31:0] bufo_72_Addr_A;
output bufo_72_EN_A;
output [3:0] bufo_72_WEN_A;
output [31:0] bufo_72_Din_A;
input [31:0] bufo_72_Dout_A;
output bufo_72_Clk_A;
output bufo_72_Rst_A;
output [31:0] bufo_73_Addr_A;
output bufo_73_EN_A;
output [3:0] bufo_73_WEN_A;
output [31:0] bufo_73_Din_A;
input [31:0] bufo_73_Dout_A;
output bufo_73_Clk_A;
output bufo_73_Rst_A;
output [31:0] bufo_74_Addr_A;
output bufo_74_EN_A;
output [3:0] bufo_74_WEN_A;
output [31:0] bufo_74_Din_A;
input [31:0] bufo_74_Dout_A;
output bufo_74_Clk_A;
output bufo_74_Rst_A;
output [31:0] bufo_75_Addr_A;
output bufo_75_EN_A;
output [3:0] bufo_75_WEN_A;
output [31:0] bufo_75_Din_A;
input [31:0] bufo_75_Dout_A;
output bufo_75_Clk_A;
output bufo_75_Rst_A;
output [31:0] bufo_76_Addr_A;
output bufo_76_EN_A;
output [3:0] bufo_76_WEN_A;
output [31:0] bufo_76_Din_A;
input [31:0] bufo_76_Dout_A;
output bufo_76_Clk_A;
output bufo_76_Rst_A;
output [31:0] bufo_77_Addr_A;
output bufo_77_EN_A;
output [3:0] bufo_77_WEN_A;
output [31:0] bufo_77_Din_A;
input [31:0] bufo_77_Dout_A;
output bufo_77_Clk_A;
output bufo_77_Rst_A;
output [31:0] bufo_78_Addr_A;
output bufo_78_EN_A;
output [3:0] bufo_78_WEN_A;
output [31:0] bufo_78_Din_A;
input [31:0] bufo_78_Dout_A;
output bufo_78_Clk_A;
output bufo_78_Rst_A;
output [31:0] bufo_79_Addr_A;
output bufo_79_EN_A;
output [3:0] bufo_79_WEN_A;
output [31:0] bufo_79_Din_A;
input [31:0] bufo_79_Dout_A;
output bufo_79_Clk_A;
output bufo_79_Rst_A;
output [31:0] bufo_80_Addr_A;
output bufo_80_EN_A;
output [3:0] bufo_80_WEN_A;
output [31:0] bufo_80_Din_A;
input [31:0] bufo_80_Dout_A;
output bufo_80_Clk_A;
output bufo_80_Rst_A;
output [31:0] bufo_81_Addr_A;
output bufo_81_EN_A;
output [3:0] bufo_81_WEN_A;
output [31:0] bufo_81_Din_A;
input [31:0] bufo_81_Dout_A;
output bufo_81_Clk_A;
output bufo_81_Rst_A;
output [31:0] bufo_82_Addr_A;
output bufo_82_EN_A;
output [3:0] bufo_82_WEN_A;
output [31:0] bufo_82_Din_A;
input [31:0] bufo_82_Dout_A;
output bufo_82_Clk_A;
output bufo_82_Rst_A;
output [31:0] bufo_83_Addr_A;
output bufo_83_EN_A;
output [3:0] bufo_83_WEN_A;
output [31:0] bufo_83_Din_A;
input [31:0] bufo_83_Dout_A;
output bufo_83_Clk_A;
output bufo_83_Rst_A;
output [31:0] bufo_84_Addr_A;
output bufo_84_EN_A;
output [3:0] bufo_84_WEN_A;
output [31:0] bufo_84_Din_A;
input [31:0] bufo_84_Dout_A;
output bufo_84_Clk_A;
output bufo_84_Rst_A;
output [31:0] bufo_85_Addr_A;
output bufo_85_EN_A;
output [3:0] bufo_85_WEN_A;
output [31:0] bufo_85_Din_A;
input [31:0] bufo_85_Dout_A;
output bufo_85_Clk_A;
output bufo_85_Rst_A;
output [31:0] bufo_86_Addr_A;
output bufo_86_EN_A;
output [3:0] bufo_86_WEN_A;
output [31:0] bufo_86_Din_A;
input [31:0] bufo_86_Dout_A;
output bufo_86_Clk_A;
output bufo_86_Rst_A;
output [31:0] bufo_87_Addr_A;
output bufo_87_EN_A;
output [3:0] bufo_87_WEN_A;
output [31:0] bufo_87_Din_A;
input [31:0] bufo_87_Dout_A;
output bufo_87_Clk_A;
output bufo_87_Rst_A;
output [31:0] bufo_88_Addr_A;
output bufo_88_EN_A;
output [3:0] bufo_88_WEN_A;
output [31:0] bufo_88_Din_A;
input [31:0] bufo_88_Dout_A;
output bufo_88_Clk_A;
output bufo_88_Rst_A;
output [31:0] bufo_89_Addr_A;
output bufo_89_EN_A;
output [3:0] bufo_89_WEN_A;
output [31:0] bufo_89_Din_A;
input [31:0] bufo_89_Dout_A;
output bufo_89_Clk_A;
output bufo_89_Rst_A;
output [31:0] bufo_90_Addr_A;
output bufo_90_EN_A;
output [3:0] bufo_90_WEN_A;
output [31:0] bufo_90_Din_A;
input [31:0] bufo_90_Dout_A;
output bufo_90_Clk_A;
output bufo_90_Rst_A;
output [31:0] bufo_91_Addr_A;
output bufo_91_EN_A;
output [3:0] bufo_91_WEN_A;
output [31:0] bufo_91_Din_A;
input [31:0] bufo_91_Dout_A;
output bufo_91_Clk_A;
output bufo_91_Rst_A;
output [31:0] bufo_92_Addr_A;
output bufo_92_EN_A;
output [3:0] bufo_92_WEN_A;
output [31:0] bufo_92_Din_A;
input [31:0] bufo_92_Dout_A;
output bufo_92_Clk_A;
output bufo_92_Rst_A;
output [31:0] bufo_93_Addr_A;
output bufo_93_EN_A;
output [3:0] bufo_93_WEN_A;
output [31:0] bufo_93_Din_A;
input [31:0] bufo_93_Dout_A;
output bufo_93_Clk_A;
output bufo_93_Rst_A;
output [31:0] bufo_94_Addr_A;
output bufo_94_EN_A;
output [3:0] bufo_94_WEN_A;
output [31:0] bufo_94_Din_A;
input [31:0] bufo_94_Dout_A;
output bufo_94_Clk_A;
output bufo_94_Rst_A;
output [31:0] bufo_95_Addr_A;
output bufo_95_EN_A;
output [3:0] bufo_95_WEN_A;
output [31:0] bufo_95_Din_A;
input [31:0] bufo_95_Dout_A;
output bufo_95_Clk_A;
output bufo_95_Rst_A;
output [31:0] bufo_96_Addr_A;
output bufo_96_EN_A;
output [3:0] bufo_96_WEN_A;
output [31:0] bufo_96_Din_A;
input [31:0] bufo_96_Dout_A;
output bufo_96_Clk_A;
output bufo_96_Rst_A;
output [31:0] bufo_97_Addr_A;
output bufo_97_EN_A;
output [3:0] bufo_97_WEN_A;
output [31:0] bufo_97_Din_A;
input [31:0] bufo_97_Dout_A;
output bufo_97_Clk_A;
output bufo_97_Rst_A;
output [31:0] bufo_98_Addr_A;
output bufo_98_EN_A;
output [3:0] bufo_98_WEN_A;
output [31:0] bufo_98_Din_A;
input [31:0] bufo_98_Dout_A;
output bufo_98_Clk_A;
output bufo_98_Rst_A;
output [31:0] bufo_99_Addr_A;
output bufo_99_EN_A;
output [3:0] bufo_99_WEN_A;
output [31:0] bufo_99_Din_A;
input [31:0] bufo_99_Dout_A;
output bufo_99_Clk_A;
output bufo_99_Rst_A;
output [31:0] bufo_100_Addr_A;
output bufo_100_EN_A;
output [3:0] bufo_100_WEN_A;
output [31:0] bufo_100_Din_A;
input [31:0] bufo_100_Dout_A;
output bufo_100_Clk_A;
output bufo_100_Rst_A;
output [31:0] bufo_101_Addr_A;
output bufo_101_EN_A;
output [3:0] bufo_101_WEN_A;
output [31:0] bufo_101_Din_A;
input [31:0] bufo_101_Dout_A;
output bufo_101_Clk_A;
output bufo_101_Rst_A;
output [31:0] bufo_102_Addr_A;
output bufo_102_EN_A;
output [3:0] bufo_102_WEN_A;
output [31:0] bufo_102_Din_A;
input [31:0] bufo_102_Dout_A;
output bufo_102_Clk_A;
output bufo_102_Rst_A;
output [31:0] bufo_103_Addr_A;
output bufo_103_EN_A;
output [3:0] bufo_103_WEN_A;
output [31:0] bufo_103_Din_A;
input [31:0] bufo_103_Dout_A;
output bufo_103_Clk_A;
output bufo_103_Rst_A;
output [31:0] bufo_104_Addr_A;
output bufo_104_EN_A;
output [3:0] bufo_104_WEN_A;
output [31:0] bufo_104_Din_A;
input [31:0] bufo_104_Dout_A;
output bufo_104_Clk_A;
output bufo_104_Rst_A;
output [31:0] bufo_105_Addr_A;
output bufo_105_EN_A;
output [3:0] bufo_105_WEN_A;
output [31:0] bufo_105_Din_A;
input [31:0] bufo_105_Dout_A;
output bufo_105_Clk_A;
output bufo_105_Rst_A;
output [31:0] bufo_106_Addr_A;
output bufo_106_EN_A;
output [3:0] bufo_106_WEN_A;
output [31:0] bufo_106_Din_A;
input [31:0] bufo_106_Dout_A;
output bufo_106_Clk_A;
output bufo_106_Rst_A;
output [31:0] bufo_107_Addr_A;
output bufo_107_EN_A;
output [3:0] bufo_107_WEN_A;
output [31:0] bufo_107_Din_A;
input [31:0] bufo_107_Dout_A;
output bufo_107_Clk_A;
output bufo_107_Rst_A;
output [31:0] bufo_108_Addr_A;
output bufo_108_EN_A;
output [3:0] bufo_108_WEN_A;
output [31:0] bufo_108_Din_A;
input [31:0] bufo_108_Dout_A;
output bufo_108_Clk_A;
output bufo_108_Rst_A;
output [31:0] bufo_109_Addr_A;
output bufo_109_EN_A;
output [3:0] bufo_109_WEN_A;
output [31:0] bufo_109_Din_A;
input [31:0] bufo_109_Dout_A;
output bufo_109_Clk_A;
output bufo_109_Rst_A;
output [31:0] bufo_110_Addr_A;
output bufo_110_EN_A;
output [3:0] bufo_110_WEN_A;
output [31:0] bufo_110_Din_A;
input [31:0] bufo_110_Dout_A;
output bufo_110_Clk_A;
output bufo_110_Rst_A;
output [31:0] bufo_111_Addr_A;
output bufo_111_EN_A;
output [3:0] bufo_111_WEN_A;
output [31:0] bufo_111_Din_A;
input [31:0] bufo_111_Dout_A;
output bufo_111_Clk_A;
output bufo_111_Rst_A;
output [31:0] bufo_112_Addr_A;
output bufo_112_EN_A;
output [3:0] bufo_112_WEN_A;
output [31:0] bufo_112_Din_A;
input [31:0] bufo_112_Dout_A;
output bufo_112_Clk_A;
output bufo_112_Rst_A;
output [31:0] bufo_113_Addr_A;
output bufo_113_EN_A;
output [3:0] bufo_113_WEN_A;
output [31:0] bufo_113_Din_A;
input [31:0] bufo_113_Dout_A;
output bufo_113_Clk_A;
output bufo_113_Rst_A;
output [31:0] bufo_114_Addr_A;
output bufo_114_EN_A;
output [3:0] bufo_114_WEN_A;
output [31:0] bufo_114_Din_A;
input [31:0] bufo_114_Dout_A;
output bufo_114_Clk_A;
output bufo_114_Rst_A;
output [31:0] bufo_115_Addr_A;
output bufo_115_EN_A;
output [3:0] bufo_115_WEN_A;
output [31:0] bufo_115_Din_A;
input [31:0] bufo_115_Dout_A;
output bufo_115_Clk_A;
output bufo_115_Rst_A;
output [31:0] bufo_116_Addr_A;
output bufo_116_EN_A;
output [3:0] bufo_116_WEN_A;
output [31:0] bufo_116_Din_A;
input [31:0] bufo_116_Dout_A;
output bufo_116_Clk_A;
output bufo_116_Rst_A;
output [31:0] bufo_117_Addr_A;
output bufo_117_EN_A;
output [3:0] bufo_117_WEN_A;
output [31:0] bufo_117_Din_A;
input [31:0] bufo_117_Dout_A;
output bufo_117_Clk_A;
output bufo_117_Rst_A;
output [31:0] bufo_118_Addr_A;
output bufo_118_EN_A;
output [3:0] bufo_118_WEN_A;
output [31:0] bufo_118_Din_A;
input [31:0] bufo_118_Dout_A;
output bufo_118_Clk_A;
output bufo_118_Rst_A;
output [31:0] bufo_119_Addr_A;
output bufo_119_EN_A;
output [3:0] bufo_119_WEN_A;
output [31:0] bufo_119_Din_A;
input [31:0] bufo_119_Dout_A;
output bufo_119_Clk_A;
output bufo_119_Rst_A;
output [31:0] bufo_120_Addr_A;
output bufo_120_EN_A;
output [3:0] bufo_120_WEN_A;
output [31:0] bufo_120_Din_A;
input [31:0] bufo_120_Dout_A;
output bufo_120_Clk_A;
output bufo_120_Rst_A;
output [31:0] bufo_121_Addr_A;
output bufo_121_EN_A;
output [3:0] bufo_121_WEN_A;
output [31:0] bufo_121_Din_A;
input [31:0] bufo_121_Dout_A;
output bufo_121_Clk_A;
output bufo_121_Rst_A;
output [31:0] bufo_122_Addr_A;
output bufo_122_EN_A;
output [3:0] bufo_122_WEN_A;
output [31:0] bufo_122_Din_A;
input [31:0] bufo_122_Dout_A;
output bufo_122_Clk_A;
output bufo_122_Rst_A;
output [31:0] bufo_123_Addr_A;
output bufo_123_EN_A;
output [3:0] bufo_123_WEN_A;
output [31:0] bufo_123_Din_A;
input [31:0] bufo_123_Dout_A;
output bufo_123_Clk_A;
output bufo_123_Rst_A;
output [31:0] bufo_124_Addr_A;
output bufo_124_EN_A;
output [3:0] bufo_124_WEN_A;
output [31:0] bufo_124_Din_A;
input [31:0] bufo_124_Dout_A;
output bufo_124_Clk_A;
output bufo_124_Rst_A;
output [31:0] bufo_125_Addr_A;
output bufo_125_EN_A;
output [3:0] bufo_125_WEN_A;
output [31:0] bufo_125_Din_A;
input [31:0] bufo_125_Dout_A;
output bufo_125_Clk_A;
output bufo_125_Rst_A;
output [31:0] bufo_126_Addr_A;
output bufo_126_EN_A;
output [3:0] bufo_126_WEN_A;
output [31:0] bufo_126_Din_A;
input [31:0] bufo_126_Dout_A;
output bufo_126_Clk_A;
output bufo_126_Rst_A;
output [31:0] bufo_127_Addr_A;
output bufo_127_EN_A;
output [3:0] bufo_127_WEN_A;
output [31:0] bufo_127_Din_A;
input [31:0] bufo_127_Dout_A;
output bufo_127_Clk_A;
output bufo_127_Rst_A;
output [31:0] bufo_128_Addr_A;
output bufo_128_EN_A;
output [3:0] bufo_128_WEN_A;
output [31:0] bufo_128_Din_A;
input [31:0] bufo_128_Dout_A;
output bufo_128_Clk_A;
output bufo_128_Rst_A;
output [31:0] bufo_128_Addr_B;
output bufo_128_EN_B;
output [3:0] bufo_128_WEN_B;
output [31:0] bufo_128_Din_B;
input [31:0] bufo_128_Dout_B;
output bufo_128_Clk_B;
output bufo_128_Rst_B;
output [31:0] bufo_129_Addr_A;
output bufo_129_EN_A;
output [3:0] bufo_129_WEN_A;
output [31:0] bufo_129_Din_A;
input [31:0] bufo_129_Dout_A;
output bufo_129_Clk_A;
output bufo_129_Rst_A;
output [31:0] bufo_129_Addr_B;
output bufo_129_EN_B;
output [3:0] bufo_129_WEN_B;
output [31:0] bufo_129_Din_B;
input [31:0] bufo_129_Dout_B;
output bufo_129_Clk_B;
output bufo_129_Rst_B;
output [31:0] bufo_130_Addr_A;
output bufo_130_EN_A;
output [3:0] bufo_130_WEN_A;
output [31:0] bufo_130_Din_A;
input [31:0] bufo_130_Dout_A;
output bufo_130_Clk_A;
output bufo_130_Rst_A;
output [31:0] bufo_130_Addr_B;
output bufo_130_EN_B;
output [3:0] bufo_130_WEN_B;
output [31:0] bufo_130_Din_B;
input [31:0] bufo_130_Dout_B;
output bufo_130_Clk_B;
output bufo_130_Rst_B;
output [31:0] bufo_131_Addr_A;
output bufo_131_EN_A;
output [3:0] bufo_131_WEN_A;
output [31:0] bufo_131_Din_A;
input [31:0] bufo_131_Dout_A;
output bufo_131_Clk_A;
output bufo_131_Rst_A;
output [31:0] bufo_131_Addr_B;
output bufo_131_EN_B;
output [3:0] bufo_131_WEN_B;
output [31:0] bufo_131_Din_B;
input [31:0] bufo_131_Dout_B;
output bufo_131_Clk_B;
output bufo_131_Rst_B;
output [31:0] bufo_132_Addr_A;
output bufo_132_EN_A;
output [3:0] bufo_132_WEN_A;
output [31:0] bufo_132_Din_A;
input [31:0] bufo_132_Dout_A;
output bufo_132_Clk_A;
output bufo_132_Rst_A;
output [31:0] bufo_132_Addr_B;
output bufo_132_EN_B;
output [3:0] bufo_132_WEN_B;
output [31:0] bufo_132_Din_B;
input [31:0] bufo_132_Dout_B;
output bufo_132_Clk_B;
output bufo_132_Rst_B;
output [31:0] bufo_133_Addr_A;
output bufo_133_EN_A;
output [3:0] bufo_133_WEN_A;
output [31:0] bufo_133_Din_A;
input [31:0] bufo_133_Dout_A;
output bufo_133_Clk_A;
output bufo_133_Rst_A;
output [31:0] bufo_133_Addr_B;
output bufo_133_EN_B;
output [3:0] bufo_133_WEN_B;
output [31:0] bufo_133_Din_B;
input [31:0] bufo_133_Dout_B;
output bufo_133_Clk_B;
output bufo_133_Rst_B;
output [31:0] bufo_134_Addr_A;
output bufo_134_EN_A;
output [3:0] bufo_134_WEN_A;
output [31:0] bufo_134_Din_A;
input [31:0] bufo_134_Dout_A;
output bufo_134_Clk_A;
output bufo_134_Rst_A;
output [31:0] bufo_134_Addr_B;
output bufo_134_EN_B;
output [3:0] bufo_134_WEN_B;
output [31:0] bufo_134_Din_B;
input [31:0] bufo_134_Dout_B;
output bufo_134_Clk_B;
output bufo_134_Rst_B;
output [31:0] bufo_135_Addr_A;
output bufo_135_EN_A;
output [3:0] bufo_135_WEN_A;
output [31:0] bufo_135_Din_A;
input [31:0] bufo_135_Dout_A;
output bufo_135_Clk_A;
output bufo_135_Rst_A;
output [31:0] bufo_135_Addr_B;
output bufo_135_EN_B;
output [3:0] bufo_135_WEN_B;
output [31:0] bufo_135_Din_B;
input [31:0] bufo_135_Dout_B;
output bufo_135_Clk_B;
output bufo_135_Rst_B;
output [31:0] bufo_136_Addr_A;
output bufo_136_EN_A;
output [3:0] bufo_136_WEN_A;
output [31:0] bufo_136_Din_A;
input [31:0] bufo_136_Dout_A;
output bufo_136_Clk_A;
output bufo_136_Rst_A;
output [31:0] bufo_136_Addr_B;
output bufo_136_EN_B;
output [3:0] bufo_136_WEN_B;
output [31:0] bufo_136_Din_B;
input [31:0] bufo_136_Dout_B;
output bufo_136_Clk_B;
output bufo_136_Rst_B;
output [31:0] bufo_137_Addr_A;
output bufo_137_EN_A;
output [3:0] bufo_137_WEN_A;
output [31:0] bufo_137_Din_A;
input [31:0] bufo_137_Dout_A;
output bufo_137_Clk_A;
output bufo_137_Rst_A;
output [31:0] bufo_137_Addr_B;
output bufo_137_EN_B;
output [3:0] bufo_137_WEN_B;
output [31:0] bufo_137_Din_B;
input [31:0] bufo_137_Dout_B;
output bufo_137_Clk_B;
output bufo_137_Rst_B;
output [31:0] bufo_138_Addr_A;
output bufo_138_EN_A;
output [3:0] bufo_138_WEN_A;
output [31:0] bufo_138_Din_A;
input [31:0] bufo_138_Dout_A;
output bufo_138_Clk_A;
output bufo_138_Rst_A;
output [31:0] bufo_138_Addr_B;
output bufo_138_EN_B;
output [3:0] bufo_138_WEN_B;
output [31:0] bufo_138_Din_B;
input [31:0] bufo_138_Dout_B;
output bufo_138_Clk_B;
output bufo_138_Rst_B;
output [31:0] bufo_139_Addr_A;
output bufo_139_EN_A;
output [3:0] bufo_139_WEN_A;
output [31:0] bufo_139_Din_A;
input [31:0] bufo_139_Dout_A;
output bufo_139_Clk_A;
output bufo_139_Rst_A;
output [31:0] bufo_139_Addr_B;
output bufo_139_EN_B;
output [3:0] bufo_139_WEN_B;
output [31:0] bufo_139_Din_B;
input [31:0] bufo_139_Dout_B;
output bufo_139_Clk_B;
output bufo_139_Rst_B;
output [31:0] bufo_140_Addr_A;
output bufo_140_EN_A;
output [3:0] bufo_140_WEN_A;
output [31:0] bufo_140_Din_A;
input [31:0] bufo_140_Dout_A;
output bufo_140_Clk_A;
output bufo_140_Rst_A;
output [31:0] bufo_140_Addr_B;
output bufo_140_EN_B;
output [3:0] bufo_140_WEN_B;
output [31:0] bufo_140_Din_B;
input [31:0] bufo_140_Dout_B;
output bufo_140_Clk_B;
output bufo_140_Rst_B;
output [31:0] bufo_141_Addr_A;
output bufo_141_EN_A;
output [3:0] bufo_141_WEN_A;
output [31:0] bufo_141_Din_A;
input [31:0] bufo_141_Dout_A;
output bufo_141_Clk_A;
output bufo_141_Rst_A;
output [31:0] bufo_141_Addr_B;
output bufo_141_EN_B;
output [3:0] bufo_141_WEN_B;
output [31:0] bufo_141_Din_B;
input [31:0] bufo_141_Dout_B;
output bufo_141_Clk_B;
output bufo_141_Rst_B;
output [31:0] bufo_142_Addr_A;
output bufo_142_EN_A;
output [3:0] bufo_142_WEN_A;
output [31:0] bufo_142_Din_A;
input [31:0] bufo_142_Dout_A;
output bufo_142_Clk_A;
output bufo_142_Rst_A;
output [31:0] bufo_142_Addr_B;
output bufo_142_EN_B;
output [3:0] bufo_142_WEN_B;
output [31:0] bufo_142_Din_B;
input [31:0] bufo_142_Dout_B;
output bufo_142_Clk_B;
output bufo_142_Rst_B;
output [31:0] bufo_143_Addr_A;
output bufo_143_EN_A;
output [3:0] bufo_143_WEN_A;
output [31:0] bufo_143_Din_A;
input [31:0] bufo_143_Dout_A;
output bufo_143_Clk_A;
output bufo_143_Rst_A;
output [31:0] bufo_143_Addr_B;
output bufo_143_EN_B;
output [3:0] bufo_143_WEN_B;
output [31:0] bufo_143_Din_B;
input [31:0] bufo_143_Dout_B;
output bufo_143_Clk_B;
output bufo_143_Rst_B;
output [31:0] bufo_144_Addr_A;
output bufo_144_EN_A;
output [3:0] bufo_144_WEN_A;
output [31:0] bufo_144_Din_A;
input [31:0] bufo_144_Dout_A;
output bufo_144_Clk_A;
output bufo_144_Rst_A;
output [31:0] bufo_144_Addr_B;
output bufo_144_EN_B;
output [3:0] bufo_144_WEN_B;
output [31:0] bufo_144_Din_B;
input [31:0] bufo_144_Dout_B;
output bufo_144_Clk_B;
output bufo_144_Rst_B;
output [31:0] bufo_145_Addr_A;
output bufo_145_EN_A;
output [3:0] bufo_145_WEN_A;
output [31:0] bufo_145_Din_A;
input [31:0] bufo_145_Dout_A;
output bufo_145_Clk_A;
output bufo_145_Rst_A;
output [31:0] bufo_145_Addr_B;
output bufo_145_EN_B;
output [3:0] bufo_145_WEN_B;
output [31:0] bufo_145_Din_B;
input [31:0] bufo_145_Dout_B;
output bufo_145_Clk_B;
output bufo_145_Rst_B;
output [31:0] bufo_146_Addr_A;
output bufo_146_EN_A;
output [3:0] bufo_146_WEN_A;
output [31:0] bufo_146_Din_A;
input [31:0] bufo_146_Dout_A;
output bufo_146_Clk_A;
output bufo_146_Rst_A;
output [31:0] bufo_146_Addr_B;
output bufo_146_EN_B;
output [3:0] bufo_146_WEN_B;
output [31:0] bufo_146_Din_B;
input [31:0] bufo_146_Dout_B;
output bufo_146_Clk_B;
output bufo_146_Rst_B;
output [31:0] bufo_147_Addr_A;
output bufo_147_EN_A;
output [3:0] bufo_147_WEN_A;
output [31:0] bufo_147_Din_A;
input [31:0] bufo_147_Dout_A;
output bufo_147_Clk_A;
output bufo_147_Rst_A;
output [31:0] bufo_147_Addr_B;
output bufo_147_EN_B;
output [3:0] bufo_147_WEN_B;
output [31:0] bufo_147_Din_B;
input [31:0] bufo_147_Dout_B;
output bufo_147_Clk_B;
output bufo_147_Rst_B;
output [31:0] bufo_148_Addr_A;
output bufo_148_EN_A;
output [3:0] bufo_148_WEN_A;
output [31:0] bufo_148_Din_A;
input [31:0] bufo_148_Dout_A;
output bufo_148_Clk_A;
output bufo_148_Rst_A;
output [31:0] bufo_148_Addr_B;
output bufo_148_EN_B;
output [3:0] bufo_148_WEN_B;
output [31:0] bufo_148_Din_B;
input [31:0] bufo_148_Dout_B;
output bufo_148_Clk_B;
output bufo_148_Rst_B;
output [31:0] bufo_149_Addr_A;
output bufo_149_EN_A;
output [3:0] bufo_149_WEN_A;
output [31:0] bufo_149_Din_A;
input [31:0] bufo_149_Dout_A;
output bufo_149_Clk_A;
output bufo_149_Rst_A;
output [31:0] bufo_149_Addr_B;
output bufo_149_EN_B;
output [3:0] bufo_149_WEN_B;
output [31:0] bufo_149_Din_B;
input [31:0] bufo_149_Dout_B;
output bufo_149_Clk_B;
output bufo_149_Rst_B;
output [31:0] bufo_150_Addr_A;
output bufo_150_EN_A;
output [3:0] bufo_150_WEN_A;
output [31:0] bufo_150_Din_A;
input [31:0] bufo_150_Dout_A;
output bufo_150_Clk_A;
output bufo_150_Rst_A;
output [31:0] bufo_150_Addr_B;
output bufo_150_EN_B;
output [3:0] bufo_150_WEN_B;
output [31:0] bufo_150_Din_B;
input [31:0] bufo_150_Dout_B;
output bufo_150_Clk_B;
output bufo_150_Rst_B;
output [31:0] bufo_151_Addr_A;
output bufo_151_EN_A;
output [3:0] bufo_151_WEN_A;
output [31:0] bufo_151_Din_A;
input [31:0] bufo_151_Dout_A;
output bufo_151_Clk_A;
output bufo_151_Rst_A;
output [31:0] bufo_151_Addr_B;
output bufo_151_EN_B;
output [3:0] bufo_151_WEN_B;
output [31:0] bufo_151_Din_B;
input [31:0] bufo_151_Dout_B;
output bufo_151_Clk_B;
output bufo_151_Rst_B;
output [31:0] bufo_152_Addr_A;
output bufo_152_EN_A;
output [3:0] bufo_152_WEN_A;
output [31:0] bufo_152_Din_A;
input [31:0] bufo_152_Dout_A;
output bufo_152_Clk_A;
output bufo_152_Rst_A;
output [31:0] bufo_152_Addr_B;
output bufo_152_EN_B;
output [3:0] bufo_152_WEN_B;
output [31:0] bufo_152_Din_B;
input [31:0] bufo_152_Dout_B;
output bufo_152_Clk_B;
output bufo_152_Rst_B;
output [31:0] bufo_153_Addr_A;
output bufo_153_EN_A;
output [3:0] bufo_153_WEN_A;
output [31:0] bufo_153_Din_A;
input [31:0] bufo_153_Dout_A;
output bufo_153_Clk_A;
output bufo_153_Rst_A;
output [31:0] bufo_153_Addr_B;
output bufo_153_EN_B;
output [3:0] bufo_153_WEN_B;
output [31:0] bufo_153_Din_B;
input [31:0] bufo_153_Dout_B;
output bufo_153_Clk_B;
output bufo_153_Rst_B;
output [31:0] bufo_154_Addr_A;
output bufo_154_EN_A;
output [3:0] bufo_154_WEN_A;
output [31:0] bufo_154_Din_A;
input [31:0] bufo_154_Dout_A;
output bufo_154_Clk_A;
output bufo_154_Rst_A;
output [31:0] bufo_154_Addr_B;
output bufo_154_EN_B;
output [3:0] bufo_154_WEN_B;
output [31:0] bufo_154_Din_B;
input [31:0] bufo_154_Dout_B;
output bufo_154_Clk_B;
output bufo_154_Rst_B;
output [31:0] bufo_155_Addr_A;
output bufo_155_EN_A;
output [3:0] bufo_155_WEN_A;
output [31:0] bufo_155_Din_A;
input [31:0] bufo_155_Dout_A;
output bufo_155_Clk_A;
output bufo_155_Rst_A;
output [31:0] bufo_155_Addr_B;
output bufo_155_EN_B;
output [3:0] bufo_155_WEN_B;
output [31:0] bufo_155_Din_B;
input [31:0] bufo_155_Dout_B;
output bufo_155_Clk_B;
output bufo_155_Rst_B;
output [31:0] bufo_156_Addr_A;
output bufo_156_EN_A;
output [3:0] bufo_156_WEN_A;
output [31:0] bufo_156_Din_A;
input [31:0] bufo_156_Dout_A;
output bufo_156_Clk_A;
output bufo_156_Rst_A;
output [31:0] bufo_156_Addr_B;
output bufo_156_EN_B;
output [3:0] bufo_156_WEN_B;
output [31:0] bufo_156_Din_B;
input [31:0] bufo_156_Dout_B;
output bufo_156_Clk_B;
output bufo_156_Rst_B;
output [31:0] bufo_157_Addr_A;
output bufo_157_EN_A;
output [3:0] bufo_157_WEN_A;
output [31:0] bufo_157_Din_A;
input [31:0] bufo_157_Dout_A;
output bufo_157_Clk_A;
output bufo_157_Rst_A;
output [31:0] bufo_157_Addr_B;
output bufo_157_EN_B;
output [3:0] bufo_157_WEN_B;
output [31:0] bufo_157_Din_B;
input [31:0] bufo_157_Dout_B;
output bufo_157_Clk_B;
output bufo_157_Rst_B;
output [31:0] bufo_158_Addr_A;
output bufo_158_EN_A;
output [3:0] bufo_158_WEN_A;
output [31:0] bufo_158_Din_A;
input [31:0] bufo_158_Dout_A;
output bufo_158_Clk_A;
output bufo_158_Rst_A;
output [31:0] bufo_158_Addr_B;
output bufo_158_EN_B;
output [3:0] bufo_158_WEN_B;
output [31:0] bufo_158_Din_B;
input [31:0] bufo_158_Dout_B;
output bufo_158_Clk_B;
output bufo_158_Rst_B;
output [31:0] bufo_159_Addr_A;
output bufo_159_EN_A;
output [3:0] bufo_159_WEN_A;
output [31:0] bufo_159_Din_A;
input [31:0] bufo_159_Dout_A;
output bufo_159_Clk_A;
output bufo_159_Rst_A;
output [31:0] bufo_159_Addr_B;
output bufo_159_EN_B;
output [3:0] bufo_159_WEN_B;
output [31:0] bufo_159_Din_B;
input [31:0] bufo_159_Dout_B;
output bufo_159_Clk_B;
output bufo_159_Rst_B;
output [31:0] bufo_160_Addr_A;
output bufo_160_EN_A;
output [3:0] bufo_160_WEN_A;
output [31:0] bufo_160_Din_A;
input [31:0] bufo_160_Dout_A;
output bufo_160_Clk_A;
output bufo_160_Rst_A;
output [31:0] bufo_160_Addr_B;
output bufo_160_EN_B;
output [3:0] bufo_160_WEN_B;
output [31:0] bufo_160_Din_B;
input [31:0] bufo_160_Dout_B;
output bufo_160_Clk_B;
output bufo_160_Rst_B;
output [31:0] bufo_161_Addr_A;
output bufo_161_EN_A;
output [3:0] bufo_161_WEN_A;
output [31:0] bufo_161_Din_A;
input [31:0] bufo_161_Dout_A;
output bufo_161_Clk_A;
output bufo_161_Rst_A;
output [31:0] bufo_161_Addr_B;
output bufo_161_EN_B;
output [3:0] bufo_161_WEN_B;
output [31:0] bufo_161_Din_B;
input [31:0] bufo_161_Dout_B;
output bufo_161_Clk_B;
output bufo_161_Rst_B;
output [31:0] bufo_162_Addr_A;
output bufo_162_EN_A;
output [3:0] bufo_162_WEN_A;
output [31:0] bufo_162_Din_A;
input [31:0] bufo_162_Dout_A;
output bufo_162_Clk_A;
output bufo_162_Rst_A;
output [31:0] bufo_162_Addr_B;
output bufo_162_EN_B;
output [3:0] bufo_162_WEN_B;
output [31:0] bufo_162_Din_B;
input [31:0] bufo_162_Dout_B;
output bufo_162_Clk_B;
output bufo_162_Rst_B;
output [31:0] bufo_163_Addr_A;
output bufo_163_EN_A;
output [3:0] bufo_163_WEN_A;
output [31:0] bufo_163_Din_A;
input [31:0] bufo_163_Dout_A;
output bufo_163_Clk_A;
output bufo_163_Rst_A;
output [31:0] bufo_163_Addr_B;
output bufo_163_EN_B;
output [3:0] bufo_163_WEN_B;
output [31:0] bufo_163_Din_B;
input [31:0] bufo_163_Dout_B;
output bufo_163_Clk_B;
output bufo_163_Rst_B;
output [31:0] bufo_164_Addr_A;
output bufo_164_EN_A;
output [3:0] bufo_164_WEN_A;
output [31:0] bufo_164_Din_A;
input [31:0] bufo_164_Dout_A;
output bufo_164_Clk_A;
output bufo_164_Rst_A;
output [31:0] bufo_164_Addr_B;
output bufo_164_EN_B;
output [3:0] bufo_164_WEN_B;
output [31:0] bufo_164_Din_B;
input [31:0] bufo_164_Dout_B;
output bufo_164_Clk_B;
output bufo_164_Rst_B;
output [31:0] bufo_165_Addr_A;
output bufo_165_EN_A;
output [3:0] bufo_165_WEN_A;
output [31:0] bufo_165_Din_A;
input [31:0] bufo_165_Dout_A;
output bufo_165_Clk_A;
output bufo_165_Rst_A;
output [31:0] bufo_165_Addr_B;
output bufo_165_EN_B;
output [3:0] bufo_165_WEN_B;
output [31:0] bufo_165_Din_B;
input [31:0] bufo_165_Dout_B;
output bufo_165_Clk_B;
output bufo_165_Rst_B;
output [31:0] bufo_166_Addr_A;
output bufo_166_EN_A;
output [3:0] bufo_166_WEN_A;
output [31:0] bufo_166_Din_A;
input [31:0] bufo_166_Dout_A;
output bufo_166_Clk_A;
output bufo_166_Rst_A;
output [31:0] bufo_166_Addr_B;
output bufo_166_EN_B;
output [3:0] bufo_166_WEN_B;
output [31:0] bufo_166_Din_B;
input [31:0] bufo_166_Dout_B;
output bufo_166_Clk_B;
output bufo_166_Rst_B;
output [31:0] bufo_167_Addr_A;
output bufo_167_EN_A;
output [3:0] bufo_167_WEN_A;
output [31:0] bufo_167_Din_A;
input [31:0] bufo_167_Dout_A;
output bufo_167_Clk_A;
output bufo_167_Rst_A;
output [31:0] bufo_167_Addr_B;
output bufo_167_EN_B;
output [3:0] bufo_167_WEN_B;
output [31:0] bufo_167_Din_B;
input [31:0] bufo_167_Dout_B;
output bufo_167_Clk_B;
output bufo_167_Rst_B;
output [31:0] bufo_168_Addr_A;
output bufo_168_EN_A;
output [3:0] bufo_168_WEN_A;
output [31:0] bufo_168_Din_A;
input [31:0] bufo_168_Dout_A;
output bufo_168_Clk_A;
output bufo_168_Rst_A;
output [31:0] bufo_168_Addr_B;
output bufo_168_EN_B;
output [3:0] bufo_168_WEN_B;
output [31:0] bufo_168_Din_B;
input [31:0] bufo_168_Dout_B;
output bufo_168_Clk_B;
output bufo_168_Rst_B;
output [31:0] bufo_169_Addr_A;
output bufo_169_EN_A;
output [3:0] bufo_169_WEN_A;
output [31:0] bufo_169_Din_A;
input [31:0] bufo_169_Dout_A;
output bufo_169_Clk_A;
output bufo_169_Rst_A;
output [31:0] bufo_169_Addr_B;
output bufo_169_EN_B;
output [3:0] bufo_169_WEN_B;
output [31:0] bufo_169_Din_B;
input [31:0] bufo_169_Dout_B;
output bufo_169_Clk_B;
output bufo_169_Rst_B;
output [31:0] bufo_170_Addr_A;
output bufo_170_EN_A;
output [3:0] bufo_170_WEN_A;
output [31:0] bufo_170_Din_A;
input [31:0] bufo_170_Dout_A;
output bufo_170_Clk_A;
output bufo_170_Rst_A;
output [31:0] bufo_170_Addr_B;
output bufo_170_EN_B;
output [3:0] bufo_170_WEN_B;
output [31:0] bufo_170_Din_B;
input [31:0] bufo_170_Dout_B;
output bufo_170_Clk_B;
output bufo_170_Rst_B;
output [31:0] bufo_171_Addr_A;
output bufo_171_EN_A;
output [3:0] bufo_171_WEN_A;
output [31:0] bufo_171_Din_A;
input [31:0] bufo_171_Dout_A;
output bufo_171_Clk_A;
output bufo_171_Rst_A;
output [31:0] bufo_171_Addr_B;
output bufo_171_EN_B;
output [3:0] bufo_171_WEN_B;
output [31:0] bufo_171_Din_B;
input [31:0] bufo_171_Dout_B;
output bufo_171_Clk_B;
output bufo_171_Rst_B;
output [31:0] bufo_172_Addr_A;
output bufo_172_EN_A;
output [3:0] bufo_172_WEN_A;
output [31:0] bufo_172_Din_A;
input [31:0] bufo_172_Dout_A;
output bufo_172_Clk_A;
output bufo_172_Rst_A;
output [31:0] bufo_172_Addr_B;
output bufo_172_EN_B;
output [3:0] bufo_172_WEN_B;
output [31:0] bufo_172_Din_B;
input [31:0] bufo_172_Dout_B;
output bufo_172_Clk_B;
output bufo_172_Rst_B;
output [31:0] bufo_173_Addr_A;
output bufo_173_EN_A;
output [3:0] bufo_173_WEN_A;
output [31:0] bufo_173_Din_A;
input [31:0] bufo_173_Dout_A;
output bufo_173_Clk_A;
output bufo_173_Rst_A;
output [31:0] bufo_173_Addr_B;
output bufo_173_EN_B;
output [3:0] bufo_173_WEN_B;
output [31:0] bufo_173_Din_B;
input [31:0] bufo_173_Dout_B;
output bufo_173_Clk_B;
output bufo_173_Rst_B;
output [31:0] bufo_174_Addr_A;
output bufo_174_EN_A;
output [3:0] bufo_174_WEN_A;
output [31:0] bufo_174_Din_A;
input [31:0] bufo_174_Dout_A;
output bufo_174_Clk_A;
output bufo_174_Rst_A;
output [31:0] bufo_174_Addr_B;
output bufo_174_EN_B;
output [3:0] bufo_174_WEN_B;
output [31:0] bufo_174_Din_B;
input [31:0] bufo_174_Dout_B;
output bufo_174_Clk_B;
output bufo_174_Rst_B;
output [31:0] bufo_175_Addr_A;
output bufo_175_EN_A;
output [3:0] bufo_175_WEN_A;
output [31:0] bufo_175_Din_A;
input [31:0] bufo_175_Dout_A;
output bufo_175_Clk_A;
output bufo_175_Rst_A;
output [31:0] bufo_175_Addr_B;
output bufo_175_EN_B;
output [3:0] bufo_175_WEN_B;
output [31:0] bufo_175_Din_B;
input [31:0] bufo_175_Dout_B;
output bufo_175_Clk_B;
output bufo_175_Rst_B;
output [31:0] bufo_176_Addr_A;
output bufo_176_EN_A;
output [3:0] bufo_176_WEN_A;
output [31:0] bufo_176_Din_A;
input [31:0] bufo_176_Dout_A;
output bufo_176_Clk_A;
output bufo_176_Rst_A;
output [31:0] bufo_176_Addr_B;
output bufo_176_EN_B;
output [3:0] bufo_176_WEN_B;
output [31:0] bufo_176_Din_B;
input [31:0] bufo_176_Dout_B;
output bufo_176_Clk_B;
output bufo_176_Rst_B;
output [31:0] bufo_177_Addr_A;
output bufo_177_EN_A;
output [3:0] bufo_177_WEN_A;
output [31:0] bufo_177_Din_A;
input [31:0] bufo_177_Dout_A;
output bufo_177_Clk_A;
output bufo_177_Rst_A;
output [31:0] bufo_177_Addr_B;
output bufo_177_EN_B;
output [3:0] bufo_177_WEN_B;
output [31:0] bufo_177_Din_B;
input [31:0] bufo_177_Dout_B;
output bufo_177_Clk_B;
output bufo_177_Rst_B;
output [31:0] bufo_178_Addr_A;
output bufo_178_EN_A;
output [3:0] bufo_178_WEN_A;
output [31:0] bufo_178_Din_A;
input [31:0] bufo_178_Dout_A;
output bufo_178_Clk_A;
output bufo_178_Rst_A;
output [31:0] bufo_178_Addr_B;
output bufo_178_EN_B;
output [3:0] bufo_178_WEN_B;
output [31:0] bufo_178_Din_B;
input [31:0] bufo_178_Dout_B;
output bufo_178_Clk_B;
output bufo_178_Rst_B;
output [31:0] bufo_179_Addr_A;
output bufo_179_EN_A;
output [3:0] bufo_179_WEN_A;
output [31:0] bufo_179_Din_A;
input [31:0] bufo_179_Dout_A;
output bufo_179_Clk_A;
output bufo_179_Rst_A;
output [31:0] bufo_179_Addr_B;
output bufo_179_EN_B;
output [3:0] bufo_179_WEN_B;
output [31:0] bufo_179_Din_B;
input [31:0] bufo_179_Dout_B;
output bufo_179_Clk_B;
output bufo_179_Rst_B;
output [31:0] bufo_180_Addr_A;
output bufo_180_EN_A;
output [3:0] bufo_180_WEN_A;
output [31:0] bufo_180_Din_A;
input [31:0] bufo_180_Dout_A;
output bufo_180_Clk_A;
output bufo_180_Rst_A;
output [31:0] bufo_180_Addr_B;
output bufo_180_EN_B;
output [3:0] bufo_180_WEN_B;
output [31:0] bufo_180_Din_B;
input [31:0] bufo_180_Dout_B;
output bufo_180_Clk_B;
output bufo_180_Rst_B;
output [31:0] bufo_181_Addr_A;
output bufo_181_EN_A;
output [3:0] bufo_181_WEN_A;
output [31:0] bufo_181_Din_A;
input [31:0] bufo_181_Dout_A;
output bufo_181_Clk_A;
output bufo_181_Rst_A;
output [31:0] bufo_181_Addr_B;
output bufo_181_EN_B;
output [3:0] bufo_181_WEN_B;
output [31:0] bufo_181_Din_B;
input [31:0] bufo_181_Dout_B;
output bufo_181_Clk_B;
output bufo_181_Rst_B;
output [31:0] bufo_182_Addr_A;
output bufo_182_EN_A;
output [3:0] bufo_182_WEN_A;
output [31:0] bufo_182_Din_A;
input [31:0] bufo_182_Dout_A;
output bufo_182_Clk_A;
output bufo_182_Rst_A;
output [31:0] bufo_182_Addr_B;
output bufo_182_EN_B;
output [3:0] bufo_182_WEN_B;
output [31:0] bufo_182_Din_B;
input [31:0] bufo_182_Dout_B;
output bufo_182_Clk_B;
output bufo_182_Rst_B;
output [31:0] bufo_183_Addr_A;
output bufo_183_EN_A;
output [3:0] bufo_183_WEN_A;
output [31:0] bufo_183_Din_A;
input [31:0] bufo_183_Dout_A;
output bufo_183_Clk_A;
output bufo_183_Rst_A;
output [31:0] bufo_183_Addr_B;
output bufo_183_EN_B;
output [3:0] bufo_183_WEN_B;
output [31:0] bufo_183_Din_B;
input [31:0] bufo_183_Dout_B;
output bufo_183_Clk_B;
output bufo_183_Rst_B;
output [31:0] bufo_184_Addr_A;
output bufo_184_EN_A;
output [3:0] bufo_184_WEN_A;
output [31:0] bufo_184_Din_A;
input [31:0] bufo_184_Dout_A;
output bufo_184_Clk_A;
output bufo_184_Rst_A;
output [31:0] bufo_184_Addr_B;
output bufo_184_EN_B;
output [3:0] bufo_184_WEN_B;
output [31:0] bufo_184_Din_B;
input [31:0] bufo_184_Dout_B;
output bufo_184_Clk_B;
output bufo_184_Rst_B;
output [31:0] bufo_185_Addr_A;
output bufo_185_EN_A;
output [3:0] bufo_185_WEN_A;
output [31:0] bufo_185_Din_A;
input [31:0] bufo_185_Dout_A;
output bufo_185_Clk_A;
output bufo_185_Rst_A;
output [31:0] bufo_185_Addr_B;
output bufo_185_EN_B;
output [3:0] bufo_185_WEN_B;
output [31:0] bufo_185_Din_B;
input [31:0] bufo_185_Dout_B;
output bufo_185_Clk_B;
output bufo_185_Rst_B;
output [31:0] bufo_186_Addr_A;
output bufo_186_EN_A;
output [3:0] bufo_186_WEN_A;
output [31:0] bufo_186_Din_A;
input [31:0] bufo_186_Dout_A;
output bufo_186_Clk_A;
output bufo_186_Rst_A;
output [31:0] bufo_186_Addr_B;
output bufo_186_EN_B;
output [3:0] bufo_186_WEN_B;
output [31:0] bufo_186_Din_B;
input [31:0] bufo_186_Dout_B;
output bufo_186_Clk_B;
output bufo_186_Rst_B;
output [31:0] bufo_187_Addr_A;
output bufo_187_EN_A;
output [3:0] bufo_187_WEN_A;
output [31:0] bufo_187_Din_A;
input [31:0] bufo_187_Dout_A;
output bufo_187_Clk_A;
output bufo_187_Rst_A;
output [31:0] bufo_187_Addr_B;
output bufo_187_EN_B;
output [3:0] bufo_187_WEN_B;
output [31:0] bufo_187_Din_B;
input [31:0] bufo_187_Dout_B;
output bufo_187_Clk_B;
output bufo_187_Rst_B;
output [31:0] bufo_188_Addr_A;
output bufo_188_EN_A;
output [3:0] bufo_188_WEN_A;
output [31:0] bufo_188_Din_A;
input [31:0] bufo_188_Dout_A;
output bufo_188_Clk_A;
output bufo_188_Rst_A;
output [31:0] bufo_188_Addr_B;
output bufo_188_EN_B;
output [3:0] bufo_188_WEN_B;
output [31:0] bufo_188_Din_B;
input [31:0] bufo_188_Dout_B;
output bufo_188_Clk_B;
output bufo_188_Rst_B;
output [31:0] bufo_189_Addr_A;
output bufo_189_EN_A;
output [3:0] bufo_189_WEN_A;
output [31:0] bufo_189_Din_A;
input [31:0] bufo_189_Dout_A;
output bufo_189_Clk_A;
output bufo_189_Rst_A;
output [31:0] bufo_189_Addr_B;
output bufo_189_EN_B;
output [3:0] bufo_189_WEN_B;
output [31:0] bufo_189_Din_B;
input [31:0] bufo_189_Dout_B;
output bufo_189_Clk_B;
output bufo_189_Rst_B;
output [31:0] bufo_190_Addr_A;
output bufo_190_EN_A;
output [3:0] bufo_190_WEN_A;
output [31:0] bufo_190_Din_A;
input [31:0] bufo_190_Dout_A;
output bufo_190_Clk_A;
output bufo_190_Rst_A;
output [31:0] bufo_190_Addr_B;
output bufo_190_EN_B;
output [3:0] bufo_190_WEN_B;
output [31:0] bufo_190_Din_B;
input [31:0] bufo_190_Dout_B;
output bufo_190_Clk_B;
output bufo_190_Rst_B;
output [31:0] bufo_191_Addr_A;
output bufo_191_EN_A;
output [3:0] bufo_191_WEN_A;
output [31:0] bufo_191_Din_A;
input [31:0] bufo_191_Dout_A;
output bufo_191_Clk_A;
output bufo_191_Rst_A;
output [31:0] bufo_191_Addr_B;
output bufo_191_EN_B;
output [3:0] bufo_191_WEN_B;
output [31:0] bufo_191_Din_B;
input [31:0] bufo_191_Dout_B;
output bufo_191_Clk_B;
output bufo_191_Rst_B;
output [31:0] bufo_192_Addr_A;
output bufo_192_EN_A;
output [3:0] bufo_192_WEN_A;
output [31:0] bufo_192_Din_A;
input [31:0] bufo_192_Dout_A;
output bufo_192_Clk_A;
output bufo_192_Rst_A;
output [31:0] bufo_192_Addr_B;
output bufo_192_EN_B;
output [3:0] bufo_192_WEN_B;
output [31:0] bufo_192_Din_B;
input [31:0] bufo_192_Dout_B;
output bufo_192_Clk_B;
output bufo_192_Rst_B;
output [31:0] bufo_193_Addr_A;
output bufo_193_EN_A;
output [3:0] bufo_193_WEN_A;
output [31:0] bufo_193_Din_A;
input [31:0] bufo_193_Dout_A;
output bufo_193_Clk_A;
output bufo_193_Rst_A;
output [31:0] bufo_193_Addr_B;
output bufo_193_EN_B;
output [3:0] bufo_193_WEN_B;
output [31:0] bufo_193_Din_B;
input [31:0] bufo_193_Dout_B;
output bufo_193_Clk_B;
output bufo_193_Rst_B;
output [31:0] bufo_194_Addr_A;
output bufo_194_EN_A;
output [3:0] bufo_194_WEN_A;
output [31:0] bufo_194_Din_A;
input [31:0] bufo_194_Dout_A;
output bufo_194_Clk_A;
output bufo_194_Rst_A;
output [31:0] bufo_194_Addr_B;
output bufo_194_EN_B;
output [3:0] bufo_194_WEN_B;
output [31:0] bufo_194_Din_B;
input [31:0] bufo_194_Dout_B;
output bufo_194_Clk_B;
output bufo_194_Rst_B;
output [31:0] bufo_195_Addr_A;
output bufo_195_EN_A;
output [3:0] bufo_195_WEN_A;
output [31:0] bufo_195_Din_A;
input [31:0] bufo_195_Dout_A;
output bufo_195_Clk_A;
output bufo_195_Rst_A;
output [31:0] bufo_195_Addr_B;
output bufo_195_EN_B;
output [3:0] bufo_195_WEN_B;
output [31:0] bufo_195_Din_B;
input [31:0] bufo_195_Dout_B;
output bufo_195_Clk_B;
output bufo_195_Rst_B;
output [31:0] bufo_196_Addr_A;
output bufo_196_EN_A;
output [3:0] bufo_196_WEN_A;
output [31:0] bufo_196_Din_A;
input [31:0] bufo_196_Dout_A;
output bufo_196_Clk_A;
output bufo_196_Rst_A;
output [31:0] bufo_196_Addr_B;
output bufo_196_EN_B;
output [3:0] bufo_196_WEN_B;
output [31:0] bufo_196_Din_B;
input [31:0] bufo_196_Dout_B;
output bufo_196_Clk_B;
output bufo_196_Rst_B;
output [31:0] bufo_197_Addr_A;
output bufo_197_EN_A;
output [3:0] bufo_197_WEN_A;
output [31:0] bufo_197_Din_A;
input [31:0] bufo_197_Dout_A;
output bufo_197_Clk_A;
output bufo_197_Rst_A;
output [31:0] bufo_197_Addr_B;
output bufo_197_EN_B;
output [3:0] bufo_197_WEN_B;
output [31:0] bufo_197_Din_B;
input [31:0] bufo_197_Dout_B;
output bufo_197_Clk_B;
output bufo_197_Rst_B;
output [31:0] bufo_198_Addr_A;
output bufo_198_EN_A;
output [3:0] bufo_198_WEN_A;
output [31:0] bufo_198_Din_A;
input [31:0] bufo_198_Dout_A;
output bufo_198_Clk_A;
output bufo_198_Rst_A;
output [31:0] bufo_198_Addr_B;
output bufo_198_EN_B;
output [3:0] bufo_198_WEN_B;
output [31:0] bufo_198_Din_B;
input [31:0] bufo_198_Dout_B;
output bufo_198_Clk_B;
output bufo_198_Rst_B;
output [31:0] bufo_199_Addr_A;
output bufo_199_EN_A;
output [3:0] bufo_199_WEN_A;
output [31:0] bufo_199_Din_A;
input [31:0] bufo_199_Dout_A;
output bufo_199_Clk_A;
output bufo_199_Rst_A;
output [31:0] bufo_199_Addr_B;
output bufo_199_EN_B;
output [3:0] bufo_199_WEN_B;
output [31:0] bufo_199_Din_B;
input [31:0] bufo_199_Dout_B;
output bufo_199_Clk_B;
output bufo_199_Rst_B;
reg ap_idle;
reg bufw_EN_A;
reg bufi_EN_A;
reg bufo_0_EN_A;
reg[3:0] bufo_0_WEN_A;
reg bufo_1_EN_A;
reg[3:0] bufo_1_WEN_A;
reg bufo_2_EN_A;
reg[3:0] bufo_2_WEN_A;
reg bufo_3_EN_A;
reg[3:0] bufo_3_WEN_A;
reg bufo_4_EN_A;
reg[3:0] bufo_4_WEN_A;
reg bufo_5_EN_A;
reg[3:0] bufo_5_WEN_A;
reg bufo_6_EN_A;
reg[3:0] bufo_6_WEN_A;
reg bufo_7_EN_A;
reg[3:0] bufo_7_WEN_A;
reg bufo_8_EN_A;
reg[3:0] bufo_8_WEN_A;
reg bufo_9_EN_A;
reg[3:0] bufo_9_WEN_A;
reg bufo_10_EN_A;
reg[3:0] bufo_10_WEN_A;
reg bufo_11_EN_A;
reg[3:0] bufo_11_WEN_A;
reg bufo_12_EN_A;
reg[3:0] bufo_12_WEN_A;
reg bufo_13_EN_A;
reg[3:0] bufo_13_WEN_A;
reg bufo_14_EN_A;
reg[3:0] bufo_14_WEN_A;
reg bufo_15_EN_A;
reg[3:0] bufo_15_WEN_A;
reg bufo_16_EN_A;
reg[3:0] bufo_16_WEN_A;
reg bufo_17_EN_A;
reg[3:0] bufo_17_WEN_A;
reg bufo_18_EN_A;
reg[3:0] bufo_18_WEN_A;
reg bufo_19_EN_A;
reg[3:0] bufo_19_WEN_A;
reg bufo_20_EN_A;
reg[3:0] bufo_20_WEN_A;
reg bufo_21_EN_A;
reg[3:0] bufo_21_WEN_A;
reg bufo_22_EN_A;
reg[3:0] bufo_22_WEN_A;
reg bufo_23_EN_A;
reg[3:0] bufo_23_WEN_A;
reg bufo_24_EN_A;
reg[3:0] bufo_24_WEN_A;
reg bufo_25_EN_A;
reg[3:0] bufo_25_WEN_A;
reg bufo_26_EN_A;
reg[3:0] bufo_26_WEN_A;
reg bufo_27_EN_A;
reg[3:0] bufo_27_WEN_A;
reg bufo_28_EN_A;
reg[3:0] bufo_28_WEN_A;
reg bufo_29_EN_A;
reg[3:0] bufo_29_WEN_A;
reg bufo_30_EN_A;
reg[3:0] bufo_30_WEN_A;
reg bufo_31_EN_A;
reg[3:0] bufo_31_WEN_A;
reg bufo_32_EN_A;
reg[3:0] bufo_32_WEN_A;
reg bufo_33_EN_A;
reg[3:0] bufo_33_WEN_A;
reg bufo_34_EN_A;
reg[3:0] bufo_34_WEN_A;
reg bufo_35_EN_A;
reg[3:0] bufo_35_WEN_A;
reg bufo_36_EN_A;
reg[3:0] bufo_36_WEN_A;
reg bufo_37_EN_A;
reg[3:0] bufo_37_WEN_A;
reg bufo_38_EN_A;
reg[3:0] bufo_38_WEN_A;
reg bufo_39_EN_A;
reg[3:0] bufo_39_WEN_A;
reg bufo_40_EN_A;
reg[3:0] bufo_40_WEN_A;
reg bufo_41_EN_A;
reg[3:0] bufo_41_WEN_A;
reg bufo_42_EN_A;
reg[3:0] bufo_42_WEN_A;
reg bufo_43_EN_A;
reg[3:0] bufo_43_WEN_A;
reg bufo_44_EN_A;
reg[3:0] bufo_44_WEN_A;
reg bufo_45_EN_A;
reg[3:0] bufo_45_WEN_A;
reg bufo_46_EN_A;
reg[3:0] bufo_46_WEN_A;
reg bufo_47_EN_A;
reg[3:0] bufo_47_WEN_A;
reg bufo_48_EN_A;
reg[3:0] bufo_48_WEN_A;
reg bufo_49_EN_A;
reg[3:0] bufo_49_WEN_A;
reg bufo_50_EN_A;
reg[3:0] bufo_50_WEN_A;
reg bufo_51_EN_A;
reg[3:0] bufo_51_WEN_A;
reg bufo_52_EN_A;
reg[3:0] bufo_52_WEN_A;
reg bufo_53_EN_A;
reg[3:0] bufo_53_WEN_A;
reg bufo_54_EN_A;
reg[3:0] bufo_54_WEN_A;
reg bufo_55_EN_A;
reg[3:0] bufo_55_WEN_A;
reg bufo_56_EN_A;
reg[3:0] bufo_56_WEN_A;
reg bufo_57_EN_A;
reg[3:0] bufo_57_WEN_A;
reg bufo_58_EN_A;
reg[3:0] bufo_58_WEN_A;
reg bufo_59_EN_A;
reg[3:0] bufo_59_WEN_A;
reg bufo_60_EN_A;
reg[3:0] bufo_60_WEN_A;
reg bufo_61_EN_A;
reg[3:0] bufo_61_WEN_A;
reg bufo_62_EN_A;
reg[3:0] bufo_62_WEN_A;
reg bufo_63_EN_A;
reg[3:0] bufo_63_WEN_A;
reg bufo_64_EN_A;
reg[3:0] bufo_64_WEN_A;
reg bufo_65_EN_A;
reg[3:0] bufo_65_WEN_A;
reg bufo_66_EN_A;
reg[3:0] bufo_66_WEN_A;
reg bufo_67_EN_A;
reg[3:0] bufo_67_WEN_A;
reg bufo_68_EN_A;
reg[3:0] bufo_68_WEN_A;
reg bufo_69_EN_A;
reg[3:0] bufo_69_WEN_A;
reg bufo_70_EN_A;
reg[3:0] bufo_70_WEN_A;
reg bufo_71_EN_A;
reg[3:0] bufo_71_WEN_A;
reg bufo_72_EN_A;
reg[3:0] bufo_72_WEN_A;
reg bufo_73_EN_A;
reg[3:0] bufo_73_WEN_A;
reg bufo_74_EN_A;
reg[3:0] bufo_74_WEN_A;
reg bufo_75_EN_A;
reg[3:0] bufo_75_WEN_A;
reg bufo_76_EN_A;
reg[3:0] bufo_76_WEN_A;
reg bufo_77_EN_A;
reg[3:0] bufo_77_WEN_A;
reg bufo_78_EN_A;
reg[3:0] bufo_78_WEN_A;
reg bufo_79_EN_A;
reg[3:0] bufo_79_WEN_A;
reg bufo_80_EN_A;
reg[3:0] bufo_80_WEN_A;
reg bufo_81_EN_A;
reg[3:0] bufo_81_WEN_A;
reg bufo_82_EN_A;
reg[3:0] bufo_82_WEN_A;
reg bufo_83_EN_A;
reg[3:0] bufo_83_WEN_A;
reg bufo_84_EN_A;
reg[3:0] bufo_84_WEN_A;
reg bufo_85_EN_A;
reg[3:0] bufo_85_WEN_A;
reg bufo_86_EN_A;
reg[3:0] bufo_86_WEN_A;
reg bufo_87_EN_A;
reg[3:0] bufo_87_WEN_A;
reg bufo_88_EN_A;
reg[3:0] bufo_88_WEN_A;
reg bufo_89_EN_A;
reg[3:0] bufo_89_WEN_A;
reg bufo_90_EN_A;
reg[3:0] bufo_90_WEN_A;
reg bufo_91_EN_A;
reg[3:0] bufo_91_WEN_A;
reg bufo_92_EN_A;
reg[3:0] bufo_92_WEN_A;
reg bufo_93_EN_A;
reg[3:0] bufo_93_WEN_A;
reg bufo_94_EN_A;
reg[3:0] bufo_94_WEN_A;
reg bufo_95_EN_A;
reg[3:0] bufo_95_WEN_A;
reg bufo_96_EN_A;
reg[3:0] bufo_96_WEN_A;
reg bufo_97_EN_A;
reg[3:0] bufo_97_WEN_A;
reg bufo_98_EN_A;
reg[3:0] bufo_98_WEN_A;
reg bufo_99_EN_A;
reg[3:0] bufo_99_WEN_A;
reg bufo_100_EN_A;
reg[3:0] bufo_100_WEN_A;
reg bufo_101_EN_A;
reg[3:0] bufo_101_WEN_A;
reg bufo_102_EN_A;
reg[3:0] bufo_102_WEN_A;
reg bufo_103_EN_A;
reg[3:0] bufo_103_WEN_A;
reg bufo_104_EN_A;
reg[3:0] bufo_104_WEN_A;
reg bufo_105_EN_A;
reg[3:0] bufo_105_WEN_A;
reg bufo_106_EN_A;
reg[3:0] bufo_106_WEN_A;
reg bufo_107_EN_A;
reg[3:0] bufo_107_WEN_A;
reg bufo_108_EN_A;
reg[3:0] bufo_108_WEN_A;
reg bufo_109_EN_A;
reg[3:0] bufo_109_WEN_A;
reg bufo_110_EN_A;
reg[3:0] bufo_110_WEN_A;
reg bufo_111_EN_A;
reg[3:0] bufo_111_WEN_A;
reg bufo_112_EN_A;
reg[3:0] bufo_112_WEN_A;
reg bufo_113_EN_A;
reg[3:0] bufo_113_WEN_A;
reg bufo_114_EN_A;
reg[3:0] bufo_114_WEN_A;
reg bufo_115_EN_A;
reg[3:0] bufo_115_WEN_A;
reg bufo_116_EN_A;
reg[3:0] bufo_116_WEN_A;
reg bufo_117_EN_A;
reg[3:0] bufo_117_WEN_A;
reg bufo_118_EN_A;
reg[3:0] bufo_118_WEN_A;
reg bufo_119_EN_A;
reg[3:0] bufo_119_WEN_A;
reg bufo_120_EN_A;
reg[3:0] bufo_120_WEN_A;
reg bufo_121_EN_A;
reg[3:0] bufo_121_WEN_A;
reg bufo_122_EN_A;
reg[3:0] bufo_122_WEN_A;
reg bufo_123_EN_A;
reg[3:0] bufo_123_WEN_A;
reg bufo_124_EN_A;
reg[3:0] bufo_124_WEN_A;
reg bufo_125_EN_A;
reg[3:0] bufo_125_WEN_A;
reg bufo_126_EN_A;
reg[3:0] bufo_126_WEN_A;
reg bufo_127_EN_A;
reg[3:0] bufo_127_WEN_A;
(* fsm_encoding = "none" *) reg [55:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [31:0] grp_fu_2558_p2;
reg [31:0] reg_2580;
wire ap_CS_fsm_state17;
wire ap_CS_fsm_state26;
wire ap_CS_fsm_state35;
wire ap_CS_fsm_state44;
wire ap_CS_fsm_state55;
wire [63:0] next_mul_fu_2714_p2;
reg [63:0] next_mul_reg_3471;
wire ap_CS_fsm_state2;
wire [31:0] tmp_fu_2720_p1;
reg [31:0] tmp_reg_3481;
wire ap_CS_fsm_state3;
wire [31:0] tmp_1_fu_2724_p1;
reg [31:0] tmp_1_reg_3486;
reg [31:0] tmp_6_reg_3491;
reg [31:0] tmp_8_reg_3496;
reg [31:0] tmp_4_reg_3501;
reg [31:0] tmp_11_reg_3506;
reg [31:0] tmp_13_reg_3511;
reg [31:0] tmp_15_reg_3516;
wire ap_CS_fsm_state4;
wire [31:0] grp_fu_2564_p2;
reg [31:0] tmp_s_reg_3561;
wire ap_CS_fsm_state8;
wire [31:0] grp_fu_2568_p2;
reg [31:0] tmp_5_1_reg_3566;
wire [31:0] grp_fu_2572_p2;
reg [31:0] tmp_5_2_reg_3571;
wire [31:0] grp_fu_2576_p2;
reg [31:0] tmp_5_3_reg_3576;
wire [6:0] to_b_V_fu_2820_p2;
reg [6:0] to_b_V_reg_3581;
reg [31:0] bufo_126_load_reg_3586;
wire ap_CS_fsm_state45;
reg [6:0] p_s_reg_2284;
reg [31:0] bufo_125_load_reg_3591;
reg [31:0] bufo_124_load_reg_3596;
reg [31:0] bufo_123_load_reg_3601;
reg [31:0] bufo_122_load_reg_3606;
reg [31:0] bufo_121_load_reg_3611;
reg [31:0] bufo_120_load_reg_3616;
reg [31:0] bufo_119_load_reg_3621;
reg [31:0] bufo_118_load_reg_3626;
reg [31:0] bufo_117_load_reg_3631;
reg [31:0] bufo_116_load_reg_3636;
reg [31:0] bufo_115_load_reg_3641;
reg [31:0] bufo_114_load_reg_3646;
reg [31:0] bufo_113_load_reg_3651;
reg [31:0] bufo_112_load_reg_3656;
reg [31:0] bufo_111_load_reg_3661;
reg [31:0] bufo_110_load_reg_3666;
reg [31:0] bufo_109_load_reg_3671;
reg [31:0] bufo_108_load_reg_3676;
reg [31:0] bufo_107_load_reg_3681;
reg [31:0] bufo_106_load_reg_3686;
reg [31:0] bufo_105_load_reg_3691;
reg [31:0] bufo_104_load_reg_3696;
reg [31:0] bufo_103_load_reg_3701;
reg [31:0] bufo_102_load_reg_3706;
reg [31:0] bufo_101_load_reg_3711;
reg [31:0] bufo_100_load_reg_3716;
reg [31:0] bufo_99_load_reg_3721;
reg [31:0] bufo_98_load_reg_3726;
reg [31:0] bufo_97_load_reg_3731;
reg [31:0] bufo_96_load_reg_3736;
reg [31:0] bufo_95_load_reg_3741;
reg [31:0] bufo_94_load_reg_3746;
reg [31:0] bufo_93_load_reg_3751;
reg [31:0] bufo_92_load_reg_3756;
reg [31:0] bufo_91_load_reg_3761;
reg [31:0] bufo_90_load_reg_3766;
reg [31:0] bufo_89_load_reg_3771;
reg [31:0] bufo_88_load_reg_3776;
reg [31:0] bufo_87_load_reg_3781;
reg [31:0] bufo_86_load_reg_3786;
reg [31:0] bufo_85_load_reg_3791;
reg [31:0] bufo_84_load_reg_3796;
reg [31:0] bufo_83_load_reg_3801;
reg [31:0] bufo_82_load_reg_3806;
reg [31:0] bufo_81_load_reg_3811;
reg [31:0] bufo_80_load_reg_3816;
reg [31:0] bufo_79_load_reg_3821;
reg [31:0] bufo_78_load_reg_3826;
reg [31:0] bufo_77_load_reg_3831;
reg [31:0] bufo_76_load_reg_3836;
reg [31:0] bufo_75_load_reg_3841;
reg [31:0] bufo_74_load_reg_3846;
reg [31:0] bufo_73_load_reg_3851;
reg [31:0] bufo_72_load_reg_3856;
reg [31:0] bufo_71_load_reg_3861;
reg [31:0] bufo_70_load_reg_3866;
reg [31:0] bufo_69_load_reg_3871;
reg [31:0] bufo_68_load_reg_3876;
reg [31:0] bufo_67_load_reg_3881;
reg [31:0] bufo_66_load_reg_3886;
reg [31:0] bufo_65_load_reg_3891;
reg [31:0] bufo_64_load_reg_3896;
reg [31:0] bufo_63_load_reg_3901;
reg [31:0] bufo_62_load_reg_3906;
reg [31:0] bufo_61_load_reg_3911;
reg [31:0] bufo_60_load_reg_3916;
reg [31:0] bufo_59_load_reg_3921;
reg [31:0] bufo_58_load_reg_3926;
reg [31:0] bufo_57_load_reg_3931;
reg [31:0] bufo_56_load_reg_3936;
reg [31:0] bufo_55_load_reg_3941;
reg [31:0] bufo_54_load_reg_3946;
reg [31:0] bufo_53_load_reg_3951;
reg [31:0] bufo_52_load_reg_3956;
reg [31:0] bufo_51_load_reg_3961;
reg [31:0] bufo_50_load_reg_3966;
reg [31:0] bufo_49_load_reg_3971;
reg [31:0] bufo_48_load_reg_3976;
reg [31:0] bufo_47_load_reg_3981;
reg [31:0] bufo_46_load_reg_3986;
reg [31:0] bufo_45_load_reg_3991;
reg [31:0] bufo_44_load_reg_3996;
reg [31:0] bufo_43_load_reg_4001;
reg [31:0] bufo_42_load_reg_4006;
reg [31:0] bufo_41_load_reg_4011;
reg [31:0] bufo_40_load_reg_4016;
reg [31:0] bufo_39_load_reg_4021;
reg [31:0] bufo_38_load_reg_4026;
reg [31:0] bufo_37_load_reg_4031;
reg [31:0] bufo_36_load_reg_4036;
reg [31:0] bufo_35_load_reg_4041;
reg [31:0] bufo_34_load_reg_4046;
reg [31:0] bufo_33_load_reg_4051;
reg [31:0] bufo_32_load_reg_4056;
reg [31:0] bufo_31_load_reg_4061;
reg [31:0] bufo_30_load_reg_4066;
reg [31:0] bufo_29_load_reg_4071;
reg [31:0] bufo_28_load_reg_4076;
reg [31:0] bufo_27_load_reg_4081;
reg [31:0] bufo_26_load_reg_4086;
reg [31:0] bufo_25_load_reg_4091;
reg [31:0] bufo_24_load_reg_4096;
reg [31:0] bufo_23_load_reg_4101;
reg [31:0] bufo_22_load_reg_4106;
reg [31:0] bufo_21_load_reg_4111;
reg [31:0] bufo_20_load_reg_4116;
reg [31:0] bufo_19_load_reg_4121;
reg [31:0] bufo_18_load_reg_4126;
reg [31:0] bufo_17_load_reg_4131;
reg [31:0] bufo_16_load_reg_4136;
reg [31:0] bufo_15_load_reg_4141;
reg [31:0] bufo_14_load_reg_4146;
reg [31:0] bufo_13_load_reg_4151;
reg [31:0] bufo_12_load_reg_4156;
reg [31:0] bufo_11_load_reg_4161;
reg [31:0] bufo_10_load_reg_4166;
reg [31:0] bufo_9_load_reg_4171;
reg [31:0] bufo_8_load_reg_4176;
reg [31:0] bufo_7_load_reg_4181;
reg [31:0] bufo_6_load_reg_4186;
reg [31:0] bufo_5_load_reg_4191;
reg [31:0] bufo_4_load_reg_4196;
reg [31:0] bufo_3_load_reg_4201;
reg [31:0] bufo_2_load_reg_4206;
reg [31:0] bufo_1_load_reg_4211;
reg [31:0] bufo_0_load_reg_4216;
reg [31:0] bufo_127_load_reg_4221;
reg [63:0] phi_mul_reg_2272;
wire ap_CS_fsm_state56;
reg [31:0] bufo_load_phi_reg_2296;
wire ap_CS_fsm_state46;
wire [31:0] bufw_Addr_A_orig;
wire [31:0] bufi_Addr_A_orig;
wire [31:0] bufo_126_Addr_A_orig;
wire [31:0] bufo_125_Addr_A_orig;
wire [31:0] bufo_124_Addr_A_orig;
wire [31:0] bufo_123_Addr_A_orig;
wire [31:0] bufo_122_Addr_A_orig;
wire [31:0] bufo_121_Addr_A_orig;
wire [31:0] bufo_120_Addr_A_orig;
wire [31:0] bufo_119_Addr_A_orig;
wire [31:0] bufo_118_Addr_A_orig;
wire [31:0] bufo_117_Addr_A_orig;
wire [31:0] bufo_116_Addr_A_orig;
wire [31:0] bufo_115_Addr_A_orig;
wire [31:0] bufo_114_Addr_A_orig;
wire [31:0] bufo_113_Addr_A_orig;
wire [31:0] bufo_112_Addr_A_orig;
wire [31:0] bufo_111_Addr_A_orig;
wire [31:0] bufo_110_Addr_A_orig;
wire [31:0] bufo_109_Addr_A_orig;
wire [31:0] bufo_108_Addr_A_orig;
wire [31:0] bufo_107_Addr_A_orig;
wire [31:0] bufo_106_Addr_A_orig;
wire [31:0] bufo_105_Addr_A_orig;
wire [31:0] bufo_104_Addr_A_orig;
wire [31:0] bufo_103_Addr_A_orig;
wire [31:0] bufo_102_Addr_A_orig;
wire [31:0] bufo_101_Addr_A_orig;
wire [31:0] bufo_100_Addr_A_orig;
wire [31:0] bufo_99_Addr_A_orig;
wire [31:0] bufo_98_Addr_A_orig;
wire [31:0] bufo_97_Addr_A_orig;
wire [31:0] bufo_96_Addr_A_orig;
wire [31:0] bufo_95_Addr_A_orig;
wire [31:0] bufo_94_Addr_A_orig;
wire [31:0] bufo_93_Addr_A_orig;
wire [31:0] bufo_92_Addr_A_orig;
wire [31:0] bufo_91_Addr_A_orig;
wire [31:0] bufo_90_Addr_A_orig;
wire [31:0] bufo_89_Addr_A_orig;
wire [31:0] bufo_88_Addr_A_orig;
wire [31:0] bufo_87_Addr_A_orig;
wire [31:0] bufo_86_Addr_A_orig;
wire [31:0] bufo_85_Addr_A_orig;
wire [31:0] bufo_84_Addr_A_orig;
wire [31:0] bufo_83_Addr_A_orig;
wire [31:0] bufo_82_Addr_A_orig;
wire [31:0] bufo_81_Addr_A_orig;
wire [31:0] bufo_80_Addr_A_orig;
wire [31:0] bufo_79_Addr_A_orig;
wire [31:0] bufo_78_Addr_A_orig;
wire [31:0] bufo_77_Addr_A_orig;
wire [31:0] bufo_76_Addr_A_orig;
wire [31:0] bufo_75_Addr_A_orig;
wire [31:0] bufo_74_Addr_A_orig;
wire [31:0] bufo_73_Addr_A_orig;
wire [31:0] bufo_72_Addr_A_orig;
wire [31:0] bufo_71_Addr_A_orig;
wire [31:0] bufo_70_Addr_A_orig;
wire [31:0] bufo_69_Addr_A_orig;
wire [31:0] bufo_68_Addr_A_orig;
wire [31:0] bufo_67_Addr_A_orig;
wire [31:0] bufo_66_Addr_A_orig;
wire [31:0] bufo_65_Addr_A_orig;
wire [31:0] bufo_64_Addr_A_orig;
wire [31:0] bufo_63_Addr_A_orig;
wire [31:0] bufo_62_Addr_A_orig;
wire [31:0] bufo_61_Addr_A_orig;
wire [31:0] bufo_60_Addr_A_orig;
wire [31:0] bufo_59_Addr_A_orig;
wire [31:0] bufo_58_Addr_A_orig;
wire [31:0] bufo_57_Addr_A_orig;
wire [31:0] bufo_56_Addr_A_orig;
wire [31:0] bufo_55_Addr_A_orig;
wire [31:0] bufo_54_Addr_A_orig;
wire [31:0] bufo_53_Addr_A_orig;
wire [31:0] bufo_52_Addr_A_orig;
wire [31:0] bufo_51_Addr_A_orig;
wire [31:0] bufo_50_Addr_A_orig;
wire [31:0] bufo_49_Addr_A_orig;
wire [31:0] bufo_48_Addr_A_orig;
wire [31:0] bufo_47_Addr_A_orig;
wire [31:0] bufo_46_Addr_A_orig;
wire [31:0] bufo_45_Addr_A_orig;
wire [31:0] bufo_44_Addr_A_orig;
wire [31:0] bufo_43_Addr_A_orig;
wire [31:0] bufo_42_Addr_A_orig;
wire [31:0] bufo_41_Addr_A_orig;
wire [31:0] bufo_40_Addr_A_orig;
wire [31:0] bufo_39_Addr_A_orig;
wire [31:0] bufo_38_Addr_A_orig;
wire [31:0] bufo_37_Addr_A_orig;
wire [31:0] bufo_36_Addr_A_orig;
wire [31:0] bufo_35_Addr_A_orig;
wire [31:0] bufo_34_Addr_A_orig;
wire [31:0] bufo_33_Addr_A_orig;
wire [31:0] bufo_32_Addr_A_orig;
wire [31:0] bufo_31_Addr_A_orig;
wire [31:0] bufo_30_Addr_A_orig;
wire [31:0] bufo_29_Addr_A_orig;
wire [31:0] bufo_28_Addr_A_orig;
wire [31:0] bufo_27_Addr_A_orig;
wire [31:0] bufo_26_Addr_A_orig;
wire [31:0] bufo_25_Addr_A_orig;
wire [31:0] bufo_24_Addr_A_orig;
wire [31:0] bufo_23_Addr_A_orig;
wire [31:0] bufo_22_Addr_A_orig;
wire [31:0] bufo_21_Addr_A_orig;
wire [31:0] bufo_20_Addr_A_orig;
wire [31:0] bufo_19_Addr_A_orig;
wire [31:0] bufo_18_Addr_A_orig;
wire [31:0] bufo_17_Addr_A_orig;
wire [31:0] bufo_16_Addr_A_orig;
wire [31:0] bufo_15_Addr_A_orig;
wire [31:0] bufo_14_Addr_A_orig;
wire [31:0] bufo_13_Addr_A_orig;
wire [31:0] bufo_12_Addr_A_orig;
wire [31:0] bufo_11_Addr_A_orig;
wire [31:0] bufo_10_Addr_A_orig;
wire [31:0] bufo_9_Addr_A_orig;
wire [31:0] bufo_8_Addr_A_orig;
wire [31:0] bufo_7_Addr_A_orig;
wire [31:0] bufo_6_Addr_A_orig;
wire [31:0] bufo_5_Addr_A_orig;
wire [31:0] bufo_4_Addr_A_orig;
wire [31:0] bufo_3_Addr_A_orig;
wire [31:0] bufo_2_Addr_A_orig;
wire [31:0] bufo_1_Addr_A_orig;
wire [31:0] bufo_0_Addr_A_orig;
wire [31:0] bufo_127_Addr_A_orig;
reg [31:0] grp_fu_2558_p0;
reg [31:0] grp_fu_2558_p1;
wire ap_CS_fsm_state9;
wire ap_CS_fsm_state18;
wire ap_CS_fsm_state27;
wire ap_CS_fsm_state36;
wire ap_CS_fsm_state47;
wire [31:0] grp_fu_2564_p0;
wire [31:0] grp_fu_2564_p1;
wire [31:0] grp_fu_2568_p0;
wire [31:0] grp_fu_2568_p1;
wire [31:0] grp_fu_2572_p0;
wire [31:0] grp_fu_2572_p1;
wire [31:0] grp_fu_2576_p0;
wire [31:0] grp_fu_2576_p1;
reg [55:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 56'd1;
end
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U1(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2558_p0),
.din1(grp_fu_2558_p1),
.ce(1'b1),
.dout(grp_fu_2558_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U2(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2564_p0),
.din1(grp_fu_2564_p1),
.ce(1'b1),
.dout(grp_fu_2564_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U3(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2568_p0),
.din1(grp_fu_2568_p1),
.ce(1'b1),
.dout(grp_fu_2568_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U4(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2572_p0),
.din1(grp_fu_2572_p1),
.ce(1'b1),
.dout(grp_fu_2572_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U5(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2576_p0),
.din1(grp_fu_2576_p1),
.ce(1'b1),
.dout(grp_fu_2576_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state46)) begin
if ((p_s_reg_2284 == 7'd127)) begin
bufo_load_phi_reg_2296 <= bufo_127_load_reg_4221;
end else if ((p_s_reg_2284 == 7'd126)) begin
bufo_load_phi_reg_2296 <= bufo_126_load_reg_3586;
end else if ((p_s_reg_2284 == 7'd125)) begin
bufo_load_phi_reg_2296 <= bufo_125_load_reg_3591;
end else if ((p_s_reg_2284 == 7'd124)) begin
bufo_load_phi_reg_2296 <= bufo_124_load_reg_3596;
end else if ((p_s_reg_2284 == 7'd123)) begin
bufo_load_phi_reg_2296 <= bufo_123_load_reg_3601;
end else if ((p_s_reg_2284 == 7'd122)) begin
bufo_load_phi_reg_2296 <= bufo_122_load_reg_3606;
end else if ((p_s_reg_2284 == 7'd121)) begin
bufo_load_phi_reg_2296 <= bufo_121_load_reg_3611;
end else if ((p_s_reg_2284 == 7'd120)) begin
bufo_load_phi_reg_2296 <= bufo_120_load_reg_3616;
end else if ((p_s_reg_2284 == 7'd119)) begin
bufo_load_phi_reg_2296 <= bufo_119_load_reg_3621;
end else if ((p_s_reg_2284 == 7'd118)) begin
bufo_load_phi_reg_2296 <= bufo_118_load_reg_3626;
end else if ((p_s_reg_2284 == 7'd117)) begin
bufo_load_phi_reg_2296 <= bufo_117_load_reg_3631;
end else if ((p_s_reg_2284 == 7'd116)) begin
bufo_load_phi_reg_2296 <= bufo_116_load_reg_3636;
end else if ((p_s_reg_2284 == 7'd115)) begin
bufo_load_phi_reg_2296 <= bufo_115_load_reg_3641;
end else if ((p_s_reg_2284 == 7'd114)) begin
bufo_load_phi_reg_2296 <= bufo_114_load_reg_3646;
end else if ((p_s_reg_2284 == 7'd113)) begin
bufo_load_phi_reg_2296 <= bufo_113_load_reg_3651;
end else if ((p_s_reg_2284 == 7'd112)) begin
bufo_load_phi_reg_2296 <= bufo_112_load_reg_3656;
end else if ((p_s_reg_2284 == 7'd111)) begin
bufo_load_phi_reg_2296 <= bufo_111_load_reg_3661;
end else if ((p_s_reg_2284 == 7'd110)) begin
bufo_load_phi_reg_2296 <= bufo_110_load_reg_3666;
end else if ((p_s_reg_2284 == 7'd109)) begin
bufo_load_phi_reg_2296 <= bufo_109_load_reg_3671;
end else if ((p_s_reg_2284 == 7'd108)) begin
bufo_load_phi_reg_2296 <= bufo_108_load_reg_3676;
end else if ((p_s_reg_2284 == 7'd107)) begin
bufo_load_phi_reg_2296 <= bufo_107_load_reg_3681;
end else if ((p_s_reg_2284 == 7'd106)) begin
bufo_load_phi_reg_2296 <= bufo_106_load_reg_3686;
end else if ((p_s_reg_2284 == 7'd105)) begin
bufo_load_phi_reg_2296 <= bufo_105_load_reg_3691;
end else if ((p_s_reg_2284 == 7'd104)) begin
bufo_load_phi_reg_2296 <= bufo_104_load_reg_3696;
end else if ((p_s_reg_2284 == 7'd103)) begin
bufo_load_phi_reg_2296 <= bufo_103_load_reg_3701;
end else if ((p_s_reg_2284 == 7'd102)) begin
bufo_load_phi_reg_2296 <= bufo_102_load_reg_3706;
end else if ((p_s_reg_2284 == 7'd101)) begin
bufo_load_phi_reg_2296 <= bufo_101_load_reg_3711;
end else if ((p_s_reg_2284 == 7'd100)) begin
bufo_load_phi_reg_2296 <= bufo_100_load_reg_3716;
end else if ((p_s_reg_2284 == 7'd99)) begin
bufo_load_phi_reg_2296 <= bufo_99_load_reg_3721;
end else if ((p_s_reg_2284 == 7'd98)) begin
bufo_load_phi_reg_2296 <= bufo_98_load_reg_3726;
end else if ((p_s_reg_2284 == 7'd97)) begin
bufo_load_phi_reg_2296 <= bufo_97_load_reg_3731;
end else if ((p_s_reg_2284 == 7'd96)) begin
bufo_load_phi_reg_2296 <= bufo_96_load_reg_3736;
end else if ((p_s_reg_2284 == 7'd95)) begin
bufo_load_phi_reg_2296 <= bufo_95_load_reg_3741;
end else if ((p_s_reg_2284 == 7'd94)) begin
bufo_load_phi_reg_2296 <= bufo_94_load_reg_3746;
end else if ((p_s_reg_2284 == 7'd93)) begin
bufo_load_phi_reg_2296 <= bufo_93_load_reg_3751;
end else if ((p_s_reg_2284 == 7'd92)) begin
bufo_load_phi_reg_2296 <= bufo_92_load_reg_3756;
end else if ((p_s_reg_2284 == 7'd91)) begin
bufo_load_phi_reg_2296 <= bufo_91_load_reg_3761;
end else if ((p_s_reg_2284 == 7'd90)) begin
bufo_load_phi_reg_2296 <= bufo_90_load_reg_3766;
end else if ((p_s_reg_2284 == 7'd89)) begin
bufo_load_phi_reg_2296 <= bufo_89_load_reg_3771;
end else if ((p_s_reg_2284 == 7'd88)) begin
bufo_load_phi_reg_2296 <= bufo_88_load_reg_3776;
end else if ((p_s_reg_2284 == 7'd87)) begin
bufo_load_phi_reg_2296 <= bufo_87_load_reg_3781;
end else if ((p_s_reg_2284 == 7'd86)) begin
bufo_load_phi_reg_2296 <= bufo_86_load_reg_3786;
end else if ((p_s_reg_2284 == 7'd85)) begin
bufo_load_phi_reg_2296 <= bufo_85_load_reg_3791;
end else if ((p_s_reg_2284 == 7'd84)) begin
bufo_load_phi_reg_2296 <= bufo_84_load_reg_3796;
end else if ((p_s_reg_2284 == 7'd83)) begin
bufo_load_phi_reg_2296 <= bufo_83_load_reg_3801;
end else if ((p_s_reg_2284 == 7'd82)) begin
bufo_load_phi_reg_2296 <= bufo_82_load_reg_3806;
end else if ((p_s_reg_2284 == 7'd81)) begin
bufo_load_phi_reg_2296 <= bufo_81_load_reg_3811;
end else if ((p_s_reg_2284 == 7'd80)) begin
bufo_load_phi_reg_2296 <= bufo_80_load_reg_3816;
end else if ((p_s_reg_2284 == 7'd79)) begin
bufo_load_phi_reg_2296 <= bufo_79_load_reg_3821;
end else if ((p_s_reg_2284 == 7'd78)) begin
bufo_load_phi_reg_2296 <= bufo_78_load_reg_3826;
end else if ((p_s_reg_2284 == 7'd77)) begin
bufo_load_phi_reg_2296 <= bufo_77_load_reg_3831;
end else if ((p_s_reg_2284 == 7'd76)) begin
bufo_load_phi_reg_2296 <= bufo_76_load_reg_3836;
end else if ((p_s_reg_2284 == 7'd75)) begin
bufo_load_phi_reg_2296 <= bufo_75_load_reg_3841;
end else if ((p_s_reg_2284 == 7'd74)) begin
bufo_load_phi_reg_2296 <= bufo_74_load_reg_3846;
end else if ((p_s_reg_2284 == 7'd73)) begin
bufo_load_phi_reg_2296 <= bufo_73_load_reg_3851;
end else if ((p_s_reg_2284 == 7'd72)) begin
bufo_load_phi_reg_2296 <= bufo_72_load_reg_3856;
end else if ((p_s_reg_2284 == 7'd71)) begin
bufo_load_phi_reg_2296 <= bufo_71_load_reg_3861;
end else if ((p_s_reg_2284 == 7'd70)) begin
bufo_load_phi_reg_2296 <= bufo_70_load_reg_3866;
end else if ((p_s_reg_2284 == 7'd69)) begin
bufo_load_phi_reg_2296 <= bufo_69_load_reg_3871;
end else if ((p_s_reg_2284 == 7'd68)) begin
bufo_load_phi_reg_2296 <= bufo_68_load_reg_3876;
end else if ((p_s_reg_2284 == 7'd67)) begin
bufo_load_phi_reg_2296 <= bufo_67_load_reg_3881;
end else if ((p_s_reg_2284 == 7'd66)) begin
bufo_load_phi_reg_2296 <= bufo_66_load_reg_3886;
end else if ((p_s_reg_2284 == 7'd65)) begin
bufo_load_phi_reg_2296 <= bufo_65_load_reg_3891;
end else if ((p_s_reg_2284 == 7'd64)) begin
bufo_load_phi_reg_2296 <= bufo_64_load_reg_3896;
end else if ((p_s_reg_2284 == 7'd63)) begin
bufo_load_phi_reg_2296 <= bufo_63_load_reg_3901;
end else if ((p_s_reg_2284 == 7'd62)) begin
bufo_load_phi_reg_2296 <= bufo_62_load_reg_3906;
end else if ((p_s_reg_2284 == 7'd61)) begin
bufo_load_phi_reg_2296 <= bufo_61_load_reg_3911;
end else if ((p_s_reg_2284 == 7'd60)) begin
bufo_load_phi_reg_2296 <= bufo_60_load_reg_3916;
end else if ((p_s_reg_2284 == 7'd59)) begin
bufo_load_phi_reg_2296 <= bufo_59_load_reg_3921;
end else if ((p_s_reg_2284 == 7'd58)) begin
bufo_load_phi_reg_2296 <= bufo_58_load_reg_3926;
end else if ((p_s_reg_2284 == 7'd57)) begin
bufo_load_phi_reg_2296 <= bufo_57_load_reg_3931;
end else if ((p_s_reg_2284 == 7'd56)) begin
bufo_load_phi_reg_2296 <= bufo_56_load_reg_3936;
end else if ((p_s_reg_2284 == 7'd55)) begin
bufo_load_phi_reg_2296 <= bufo_55_load_reg_3941;
end else if ((p_s_reg_2284 == 7'd54)) begin
bufo_load_phi_reg_2296 <= bufo_54_load_reg_3946;
end else if ((p_s_reg_2284 == 7'd53)) begin
bufo_load_phi_reg_2296 <= bufo_53_load_reg_3951;
end else if ((p_s_reg_2284 == 7'd52)) begin
bufo_load_phi_reg_2296 <= bufo_52_load_reg_3956;
end else if ((p_s_reg_2284 == 7'd51)) begin
bufo_load_phi_reg_2296 <= bufo_51_load_reg_3961;
end else if ((p_s_reg_2284 == 7'd50)) begin
bufo_load_phi_reg_2296 <= bufo_50_load_reg_3966;
end else if ((p_s_reg_2284 == 7'd49)) begin
bufo_load_phi_reg_2296 <= bufo_49_load_reg_3971;
end else if ((p_s_reg_2284 == 7'd48)) begin
bufo_load_phi_reg_2296 <= bufo_48_load_reg_3976;
end else if ((p_s_reg_2284 == 7'd47)) begin
bufo_load_phi_reg_2296 <= bufo_47_load_reg_3981;
end else if ((p_s_reg_2284 == 7'd46)) begin
bufo_load_phi_reg_2296 <= bufo_46_load_reg_3986;
end else if ((p_s_reg_2284 == 7'd45)) begin
bufo_load_phi_reg_2296 <= bufo_45_load_reg_3991;
end else if ((p_s_reg_2284 == 7'd44)) begin
bufo_load_phi_reg_2296 <= bufo_44_load_reg_3996;
end else if ((p_s_reg_2284 == 7'd43)) begin
bufo_load_phi_reg_2296 <= bufo_43_load_reg_4001;
end else if ((p_s_reg_2284 == 7'd42)) begin
bufo_load_phi_reg_2296 <= bufo_42_load_reg_4006;
end else if ((p_s_reg_2284 == 7'd41)) begin
bufo_load_phi_reg_2296 <= bufo_41_load_reg_4011;
end else if ((p_s_reg_2284 == 7'd40)) begin
bufo_load_phi_reg_2296 <= bufo_40_load_reg_4016;
end else if ((p_s_reg_2284 == 7'd39)) begin
bufo_load_phi_reg_2296 <= bufo_39_load_reg_4021;
end else if ((p_s_reg_2284 == 7'd38)) begin
bufo_load_phi_reg_2296 <= bufo_38_load_reg_4026;
end else if ((p_s_reg_2284 == 7'd37)) begin
bufo_load_phi_reg_2296 <= bufo_37_load_reg_4031;
end else if ((p_s_reg_2284 == 7'd36)) begin
bufo_load_phi_reg_2296 <= bufo_36_load_reg_4036;
end else if ((p_s_reg_2284 == 7'd35)) begin
bufo_load_phi_reg_2296 <= bufo_35_load_reg_4041;
end else if ((p_s_reg_2284 == 7'd34)) begin
bufo_load_phi_reg_2296 <= bufo_34_load_reg_4046;
end else if ((p_s_reg_2284 == 7'd33)) begin
bufo_load_phi_reg_2296 <= bufo_33_load_reg_4051;
end else if ((p_s_reg_2284 == 7'd32)) begin
bufo_load_phi_reg_2296 <= bufo_32_load_reg_4056;
end else if ((p_s_reg_2284 == 7'd31)) begin
bufo_load_phi_reg_2296 <= bufo_31_load_reg_4061;
end else if ((p_s_reg_2284 == 7'd30)) begin
bufo_load_phi_reg_2296 <= bufo_30_load_reg_4066;
end else if ((p_s_reg_2284 == 7'd29)) begin
bufo_load_phi_reg_2296 <= bufo_29_load_reg_4071;
end else if ((p_s_reg_2284 == 7'd28)) begin
bufo_load_phi_reg_2296 <= bufo_28_load_reg_4076;
end else if ((p_s_reg_2284 == 7'd27)) begin
bufo_load_phi_reg_2296 <= bufo_27_load_reg_4081;
end else if ((p_s_reg_2284 == 7'd26)) begin
bufo_load_phi_reg_2296 <= bufo_26_load_reg_4086;
end else if ((p_s_reg_2284 == 7'd25)) begin
bufo_load_phi_reg_2296 <= bufo_25_load_reg_4091;
end else if ((p_s_reg_2284 == 7'd24)) begin
bufo_load_phi_reg_2296 <= bufo_24_load_reg_4096;
end else if ((p_s_reg_2284 == 7'd23)) begin
bufo_load_phi_reg_2296 <= bufo_23_load_reg_4101;
end else if ((p_s_reg_2284 == 7'd22)) begin
bufo_load_phi_reg_2296 <= bufo_22_load_reg_4106;
end else if ((p_s_reg_2284 == 7'd21)) begin
bufo_load_phi_reg_2296 <= bufo_21_load_reg_4111;
end else if ((p_s_reg_2284 == 7'd20)) begin
bufo_load_phi_reg_2296 <= bufo_20_load_reg_4116;
end else if ((p_s_reg_2284 == 7'd19)) begin
bufo_load_phi_reg_2296 <= bufo_19_load_reg_4121;
end else if ((p_s_reg_2284 == 7'd18)) begin
bufo_load_phi_reg_2296 <= bufo_18_load_reg_4126;
end else if ((p_s_reg_2284 == 7'd17)) begin
bufo_load_phi_reg_2296 <= bufo_17_load_reg_4131;
end else if ((p_s_reg_2284 == 7'd16)) begin
bufo_load_phi_reg_2296 <= bufo_16_load_reg_4136;
end else if ((p_s_reg_2284 == 7'd15)) begin
bufo_load_phi_reg_2296 <= bufo_15_load_reg_4141;
end else if ((p_s_reg_2284 == 7'd14)) begin
bufo_load_phi_reg_2296 <= bufo_14_load_reg_4146;
end else if ((p_s_reg_2284 == 7'd13)) begin
bufo_load_phi_reg_2296 <= bufo_13_load_reg_4151;
end else if ((p_s_reg_2284 == 7'd12)) begin
bufo_load_phi_reg_2296 <= bufo_12_load_reg_4156;
end else if ((p_s_reg_2284 == 7'd11)) begin
bufo_load_phi_reg_2296 <= bufo_11_load_reg_4161;
end else if ((p_s_reg_2284 == 7'd10)) begin
bufo_load_phi_reg_2296 <= bufo_10_load_reg_4166;
end else if ((p_s_reg_2284 == 7'd9)) begin
bufo_load_phi_reg_2296 <= bufo_9_load_reg_4171;
end else if ((p_s_reg_2284 == 7'd8)) begin
bufo_load_phi_reg_2296 <= bufo_8_load_reg_4176;
end else if ((p_s_reg_2284 == 7'd7)) begin
bufo_load_phi_reg_2296 <= bufo_7_load_reg_4181;
end else if ((p_s_reg_2284 == 7'd6)) begin
bufo_load_phi_reg_2296 <= bufo_6_load_reg_4186;
end else if ((p_s_reg_2284 == 7'd5)) begin
bufo_load_phi_reg_2296 <= bufo_5_load_reg_4191;
end else if ((p_s_reg_2284 == 7'd4)) begin
bufo_load_phi_reg_2296 <= bufo_4_load_reg_4196;
end else if ((p_s_reg_2284 == 7'd3)) begin
bufo_load_phi_reg_2296 <= bufo_3_load_reg_4201;
end else if ((p_s_reg_2284 == 7'd2)) begin
bufo_load_phi_reg_2296 <= bufo_2_load_reg_4206;
end else if ((p_s_reg_2284 == 7'd1)) begin
bufo_load_phi_reg_2296 <= bufo_1_load_reg_4211;
end else if ((p_s_reg_2284 == 7'd0)) begin
bufo_load_phi_reg_2296 <= bufo_0_load_reg_4216;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state56)) begin
p_s_reg_2284 <= to_b_V_reg_3581;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
p_s_reg_2284 <= 7'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state56)) begin
phi_mul_reg_2272 <= next_mul_reg_3471;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
phi_mul_reg_2272 <= 64'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd0))) begin
bufo_0_load_reg_4216 <= bufo_0_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd100))) begin
bufo_100_load_reg_3716 <= bufo_100_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd101))) begin
bufo_101_load_reg_3711 <= bufo_101_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd102))) begin
bufo_102_load_reg_3706 <= bufo_102_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd103))) begin
bufo_103_load_reg_3701 <= bufo_103_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd104))) begin
bufo_104_load_reg_3696 <= bufo_104_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd105))) begin
bufo_105_load_reg_3691 <= bufo_105_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd106))) begin
bufo_106_load_reg_3686 <= bufo_106_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd107))) begin
bufo_107_load_reg_3681 <= bufo_107_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd108))) begin
bufo_108_load_reg_3676 <= bufo_108_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd109))) begin
bufo_109_load_reg_3671 <= bufo_109_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd10))) begin
bufo_10_load_reg_4166 <= bufo_10_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd110))) begin
bufo_110_load_reg_3666 <= bufo_110_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd111))) begin
bufo_111_load_reg_3661 <= bufo_111_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd112))) begin
bufo_112_load_reg_3656 <= bufo_112_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd113))) begin
bufo_113_load_reg_3651 <= bufo_113_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd114))) begin
bufo_114_load_reg_3646 <= bufo_114_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd115))) begin
bufo_115_load_reg_3641 <= bufo_115_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd116))) begin
bufo_116_load_reg_3636 <= bufo_116_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd117))) begin
bufo_117_load_reg_3631 <= bufo_117_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd118))) begin
bufo_118_load_reg_3626 <= bufo_118_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd119))) begin
bufo_119_load_reg_3621 <= bufo_119_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd11))) begin
bufo_11_load_reg_4161 <= bufo_11_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd120))) begin
bufo_120_load_reg_3616 <= bufo_120_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd121))) begin
bufo_121_load_reg_3611 <= bufo_121_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd122))) begin
bufo_122_load_reg_3606 <= bufo_122_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd123))) begin
bufo_123_load_reg_3601 <= bufo_123_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd124))) begin
bufo_124_load_reg_3596 <= bufo_124_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd125))) begin
bufo_125_load_reg_3591 <= bufo_125_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd126))) begin
bufo_126_load_reg_3586 <= bufo_126_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd127))) begin
bufo_127_load_reg_4221 <= bufo_127_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd12))) begin
bufo_12_load_reg_4156 <= bufo_12_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd13))) begin
bufo_13_load_reg_4151 <= bufo_13_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd14))) begin
bufo_14_load_reg_4146 <= bufo_14_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd15))) begin
bufo_15_load_reg_4141 <= bufo_15_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd16))) begin
bufo_16_load_reg_4136 <= bufo_16_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd17))) begin
bufo_17_load_reg_4131 <= bufo_17_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd18))) begin
bufo_18_load_reg_4126 <= bufo_18_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd19))) begin
bufo_19_load_reg_4121 <= bufo_19_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd1))) begin
bufo_1_load_reg_4211 <= bufo_1_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd20))) begin
bufo_20_load_reg_4116 <= bufo_20_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd21))) begin
bufo_21_load_reg_4111 <= bufo_21_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd22))) begin
bufo_22_load_reg_4106 <= bufo_22_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd23))) begin
bufo_23_load_reg_4101 <= bufo_23_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd24))) begin
bufo_24_load_reg_4096 <= bufo_24_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd25))) begin
bufo_25_load_reg_4091 <= bufo_25_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd26))) begin
bufo_26_load_reg_4086 <= bufo_26_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd27))) begin
bufo_27_load_reg_4081 <= bufo_27_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd28))) begin
bufo_28_load_reg_4076 <= bufo_28_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd29))) begin
bufo_29_load_reg_4071 <= bufo_29_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd2))) begin
bufo_2_load_reg_4206 <= bufo_2_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd30))) begin
bufo_30_load_reg_4066 <= bufo_30_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd31))) begin
bufo_31_load_reg_4061 <= bufo_31_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd32))) begin
bufo_32_load_reg_4056 <= bufo_32_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd33))) begin
bufo_33_load_reg_4051 <= bufo_33_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd34))) begin
bufo_34_load_reg_4046 <= bufo_34_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd35))) begin
bufo_35_load_reg_4041 <= bufo_35_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd36))) begin
bufo_36_load_reg_4036 <= bufo_36_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd37))) begin
bufo_37_load_reg_4031 <= bufo_37_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd38))) begin
bufo_38_load_reg_4026 <= bufo_38_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd39))) begin
bufo_39_load_reg_4021 <= bufo_39_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd3))) begin
bufo_3_load_reg_4201 <= bufo_3_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd40))) begin
bufo_40_load_reg_4016 <= bufo_40_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd41))) begin
bufo_41_load_reg_4011 <= bufo_41_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd42))) begin
bufo_42_load_reg_4006 <= bufo_42_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd43))) begin
bufo_43_load_reg_4001 <= bufo_43_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd44))) begin
bufo_44_load_reg_3996 <= bufo_44_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd45))) begin
bufo_45_load_reg_3991 <= bufo_45_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd46))) begin
bufo_46_load_reg_3986 <= bufo_46_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd47))) begin
bufo_47_load_reg_3981 <= bufo_47_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd48))) begin
bufo_48_load_reg_3976 <= bufo_48_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd49))) begin
bufo_49_load_reg_3971 <= bufo_49_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd4))) begin
bufo_4_load_reg_4196 <= bufo_4_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd50))) begin
bufo_50_load_reg_3966 <= bufo_50_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd51))) begin
bufo_51_load_reg_3961 <= bufo_51_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd52))) begin
bufo_52_load_reg_3956 <= bufo_52_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd53))) begin
bufo_53_load_reg_3951 <= bufo_53_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd54))) begin
bufo_54_load_reg_3946 <= bufo_54_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd55))) begin
bufo_55_load_reg_3941 <= bufo_55_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd56))) begin
bufo_56_load_reg_3936 <= bufo_56_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd57))) begin
bufo_57_load_reg_3931 <= bufo_57_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd58))) begin
bufo_58_load_reg_3926 <= bufo_58_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd59))) begin
bufo_59_load_reg_3921 <= bufo_59_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd5))) begin
bufo_5_load_reg_4191 <= bufo_5_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd60))) begin
bufo_60_load_reg_3916 <= bufo_60_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd61))) begin
bufo_61_load_reg_3911 <= bufo_61_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd62))) begin
bufo_62_load_reg_3906 <= bufo_62_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd63))) begin
bufo_63_load_reg_3901 <= bufo_63_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd64))) begin
bufo_64_load_reg_3896 <= bufo_64_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd65))) begin
bufo_65_load_reg_3891 <= bufo_65_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd66))) begin
bufo_66_load_reg_3886 <= bufo_66_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd67))) begin
bufo_67_load_reg_3881 <= bufo_67_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd68))) begin
bufo_68_load_reg_3876 <= bufo_68_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd69))) begin
bufo_69_load_reg_3871 <= bufo_69_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd6))) begin
bufo_6_load_reg_4186 <= bufo_6_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd70))) begin
bufo_70_load_reg_3866 <= bufo_70_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd71))) begin
bufo_71_load_reg_3861 <= bufo_71_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd72))) begin
bufo_72_load_reg_3856 <= bufo_72_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd73))) begin
bufo_73_load_reg_3851 <= bufo_73_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd74))) begin
bufo_74_load_reg_3846 <= bufo_74_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd75))) begin
bufo_75_load_reg_3841 <= bufo_75_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd76))) begin
bufo_76_load_reg_3836 <= bufo_76_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd77))) begin
bufo_77_load_reg_3831 <= bufo_77_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd78))) begin
bufo_78_load_reg_3826 <= bufo_78_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd79))) begin
bufo_79_load_reg_3821 <= bufo_79_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd7))) begin
bufo_7_load_reg_4181 <= bufo_7_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd80))) begin
bufo_80_load_reg_3816 <= bufo_80_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd81))) begin
bufo_81_load_reg_3811 <= bufo_81_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd82))) begin
bufo_82_load_reg_3806 <= bufo_82_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd83))) begin
bufo_83_load_reg_3801 <= bufo_83_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd84))) begin
bufo_84_load_reg_3796 <= bufo_84_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd85))) begin
bufo_85_load_reg_3791 <= bufo_85_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd86))) begin
bufo_86_load_reg_3786 <= bufo_86_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd87))) begin
bufo_87_load_reg_3781 <= bufo_87_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd88))) begin
bufo_88_load_reg_3776 <= bufo_88_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd89))) begin
bufo_89_load_reg_3771 <= bufo_89_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd8))) begin
bufo_8_load_reg_4176 <= bufo_8_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd90))) begin
bufo_90_load_reg_3766 <= bufo_90_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd91))) begin
bufo_91_load_reg_3761 <= bufo_91_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd92))) begin
bufo_92_load_reg_3756 <= bufo_92_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd93))) begin
bufo_93_load_reg_3751 <= bufo_93_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd94))) begin
bufo_94_load_reg_3746 <= bufo_94_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd95))) begin
bufo_95_load_reg_3741 <= bufo_95_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd96))) begin
bufo_96_load_reg_3736 <= bufo_96_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd97))) begin
bufo_97_load_reg_3731 <= bufo_97_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd98))) begin
bufo_98_load_reg_3726 <= bufo_98_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd99))) begin
bufo_99_load_reg_3721 <= bufo_99_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd9))) begin
bufo_9_load_reg_4171 <= bufo_9_Dout_A;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
next_mul_reg_3471 <= next_mul_fu_2714_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state35) | (1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state55))) begin
reg_2580 <= grp_fu_2558_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
tmp_11_reg_3506 <= {{bufi_Dout_A[95:64]}};
tmp_13_reg_3511 <= {{bufw_Dout_A[127:96]}};
tmp_15_reg_3516 <= {{bufi_Dout_A[127:96]}};
tmp_1_reg_3486 <= tmp_1_fu_2724_p1;
tmp_4_reg_3501 <= {{bufw_Dout_A[95:64]}};
tmp_6_reg_3491 <= {{bufw_Dout_A[63:32]}};
tmp_8_reg_3496 <= {{bufi_Dout_A[63:32]}};
tmp_reg_3481 <= tmp_fu_2720_p1;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state8)) begin
tmp_5_1_reg_3566 <= grp_fu_2568_p2;
tmp_5_2_reg_3571 <= grp_fu_2572_p2;
tmp_5_3_reg_3576 <= grp_fu_2576_p2;
tmp_s_reg_3561 <= grp_fu_2564_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state44)) begin
to_b_V_reg_3581 <= to_b_V_fu_2820_p2;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
bufi_EN_A = 1'b1;
end else begin
bufi_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_0_EN_A = 1'b1;
end else begin
bufo_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd0) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_0_WEN_A = 4'd15;
end else begin
bufo_0_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_100_EN_A = 1'b1;
end else begin
bufo_100_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd100) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_100_WEN_A = 4'd15;
end else begin
bufo_100_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_101_EN_A = 1'b1;
end else begin
bufo_101_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd101) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_101_WEN_A = 4'd15;
end else begin
bufo_101_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_102_EN_A = 1'b1;
end else begin
bufo_102_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd102) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_102_WEN_A = 4'd15;
end else begin
bufo_102_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_103_EN_A = 1'b1;
end else begin
bufo_103_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd103) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_103_WEN_A = 4'd15;
end else begin
bufo_103_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_104_EN_A = 1'b1;
end else begin
bufo_104_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd104) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_104_WEN_A = 4'd15;
end else begin
bufo_104_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_105_EN_A = 1'b1;
end else begin
bufo_105_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd105) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_105_WEN_A = 4'd15;
end else begin
bufo_105_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_106_EN_A = 1'b1;
end else begin
bufo_106_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd106) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_106_WEN_A = 4'd15;
end else begin
bufo_106_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_107_EN_A = 1'b1;
end else begin
bufo_107_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd107) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_107_WEN_A = 4'd15;
end else begin
bufo_107_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_108_EN_A = 1'b1;
end else begin
bufo_108_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd108) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_108_WEN_A = 4'd15;
end else begin
bufo_108_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_109_EN_A = 1'b1;
end else begin
bufo_109_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd109) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_109_WEN_A = 4'd15;
end else begin
bufo_109_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_10_EN_A = 1'b1;
end else begin
bufo_10_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd10) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_10_WEN_A = 4'd15;
end else begin
bufo_10_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_110_EN_A = 1'b1;
end else begin
bufo_110_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd110) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_110_WEN_A = 4'd15;
end else begin
bufo_110_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_111_EN_A = 1'b1;
end else begin
bufo_111_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd111) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_111_WEN_A = 4'd15;
end else begin
bufo_111_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_112_EN_A = 1'b1;
end else begin
bufo_112_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd112) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_112_WEN_A = 4'd15;
end else begin
bufo_112_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_113_EN_A = 1'b1;
end else begin
bufo_113_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd113) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_113_WEN_A = 4'd15;
end else begin
bufo_113_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_114_EN_A = 1'b1;
end else begin
bufo_114_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd114) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_114_WEN_A = 4'd15;
end else begin
bufo_114_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_115_EN_A = 1'b1;
end else begin
bufo_115_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd115) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_115_WEN_A = 4'd15;
end else begin
bufo_115_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_116_EN_A = 1'b1;
end else begin
bufo_116_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd116) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_116_WEN_A = 4'd15;
end else begin
bufo_116_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_117_EN_A = 1'b1;
end else begin
bufo_117_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd117) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_117_WEN_A = 4'd15;
end else begin
bufo_117_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_118_EN_A = 1'b1;
end else begin
bufo_118_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd118) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_118_WEN_A = 4'd15;
end else begin
bufo_118_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_119_EN_A = 1'b1;
end else begin
bufo_119_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd119) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_119_WEN_A = 4'd15;
end else begin
bufo_119_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_11_EN_A = 1'b1;
end else begin
bufo_11_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd11) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_11_WEN_A = 4'd15;
end else begin
bufo_11_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_120_EN_A = 1'b1;
end else begin
bufo_120_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd120) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_120_WEN_A = 4'd15;
end else begin
bufo_120_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_121_EN_A = 1'b1;
end else begin
bufo_121_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd121) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_121_WEN_A = 4'd15;
end else begin
bufo_121_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_122_EN_A = 1'b1;
end else begin
bufo_122_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd122) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_122_WEN_A = 4'd15;
end else begin
bufo_122_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_123_EN_A = 1'b1;
end else begin
bufo_123_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd123) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_123_WEN_A = 4'd15;
end else begin
bufo_123_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_124_EN_A = 1'b1;
end else begin
bufo_124_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd124) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_124_WEN_A = 4'd15;
end else begin
bufo_124_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_125_EN_A = 1'b1;
end else begin
bufo_125_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd125) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_125_WEN_A = 4'd15;
end else begin
bufo_125_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_126_EN_A = 1'b1;
end else begin
bufo_126_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd126) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_126_WEN_A = 4'd15;
end else begin
bufo_126_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_127_EN_A = 1'b1;
end else begin
bufo_127_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd127) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_127_WEN_A = 4'd15;
end else begin
bufo_127_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_12_EN_A = 1'b1;
end else begin
bufo_12_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd12) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_12_WEN_A = 4'd15;
end else begin
bufo_12_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_13_EN_A = 1'b1;
end else begin
bufo_13_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd13) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_13_WEN_A = 4'd15;
end else begin
bufo_13_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_14_EN_A = 1'b1;
end else begin
bufo_14_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd14) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_14_WEN_A = 4'd15;
end else begin
bufo_14_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_15_EN_A = 1'b1;
end else begin
bufo_15_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd15) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_15_WEN_A = 4'd15;
end else begin
bufo_15_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_16_EN_A = 1'b1;
end else begin
bufo_16_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd16) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_16_WEN_A = 4'd15;
end else begin
bufo_16_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_17_EN_A = 1'b1;
end else begin
bufo_17_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd17) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_17_WEN_A = 4'd15;
end else begin
bufo_17_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_18_EN_A = 1'b1;
end else begin
bufo_18_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd18) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_18_WEN_A = 4'd15;
end else begin
bufo_18_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_19_EN_A = 1'b1;
end else begin
bufo_19_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd19) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_19_WEN_A = 4'd15;
end else begin
bufo_19_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_1_EN_A = 1'b1;
end else begin
bufo_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd1) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_1_WEN_A = 4'd15;
end else begin
bufo_1_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_20_EN_A = 1'b1;
end else begin
bufo_20_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd20) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_20_WEN_A = 4'd15;
end else begin
bufo_20_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_21_EN_A = 1'b1;
end else begin
bufo_21_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd21) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_21_WEN_A = 4'd15;
end else begin
bufo_21_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_22_EN_A = 1'b1;
end else begin
bufo_22_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd22) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_22_WEN_A = 4'd15;
end else begin
bufo_22_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_23_EN_A = 1'b1;
end else begin
bufo_23_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd23) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_23_WEN_A = 4'd15;
end else begin
bufo_23_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_24_EN_A = 1'b1;
end else begin
bufo_24_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd24) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_24_WEN_A = 4'd15;
end else begin
bufo_24_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_25_EN_A = 1'b1;
end else begin
bufo_25_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd25) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_25_WEN_A = 4'd15;
end else begin
bufo_25_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_26_EN_A = 1'b1;
end else begin
bufo_26_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd26) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_26_WEN_A = 4'd15;
end else begin
bufo_26_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_27_EN_A = 1'b1;
end else begin
bufo_27_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd27) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_27_WEN_A = 4'd15;
end else begin
bufo_27_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_28_EN_A = 1'b1;
end else begin
bufo_28_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd28) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_28_WEN_A = 4'd15;
end else begin
bufo_28_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_29_EN_A = 1'b1;
end else begin
bufo_29_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd29) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_29_WEN_A = 4'd15;
end else begin
bufo_29_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_2_EN_A = 1'b1;
end else begin
bufo_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd2) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_2_WEN_A = 4'd15;
end else begin
bufo_2_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_30_EN_A = 1'b1;
end else begin
bufo_30_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd30) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_30_WEN_A = 4'd15;
end else begin
bufo_30_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_31_EN_A = 1'b1;
end else begin
bufo_31_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd31) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_31_WEN_A = 4'd15;
end else begin
bufo_31_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_32_EN_A = 1'b1;
end else begin
bufo_32_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd32) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_32_WEN_A = 4'd15;
end else begin
bufo_32_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_33_EN_A = 1'b1;
end else begin
bufo_33_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd33) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_33_WEN_A = 4'd15;
end else begin
bufo_33_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_34_EN_A = 1'b1;
end else begin
bufo_34_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd34) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_34_WEN_A = 4'd15;
end else begin
bufo_34_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_35_EN_A = 1'b1;
end else begin
bufo_35_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd35) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_35_WEN_A = 4'd15;
end else begin
bufo_35_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_36_EN_A = 1'b1;
end else begin
bufo_36_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd36) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_36_WEN_A = 4'd15;
end else begin
bufo_36_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_37_EN_A = 1'b1;
end else begin
bufo_37_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd37) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_37_WEN_A = 4'd15;
end else begin
bufo_37_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_38_EN_A = 1'b1;
end else begin
bufo_38_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd38) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_38_WEN_A = 4'd15;
end else begin
bufo_38_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_39_EN_A = 1'b1;
end else begin
bufo_39_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd39) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_39_WEN_A = 4'd15;
end else begin
bufo_39_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_3_EN_A = 1'b1;
end else begin
bufo_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd3) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_3_WEN_A = 4'd15;
end else begin
bufo_3_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_40_EN_A = 1'b1;
end else begin
bufo_40_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd40) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_40_WEN_A = 4'd15;
end else begin
bufo_40_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_41_EN_A = 1'b1;
end else begin
bufo_41_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd41) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_41_WEN_A = 4'd15;
end else begin
bufo_41_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_42_EN_A = 1'b1;
end else begin
bufo_42_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd42) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_42_WEN_A = 4'd15;
end else begin
bufo_42_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_43_EN_A = 1'b1;
end else begin
bufo_43_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd43) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_43_WEN_A = 4'd15;
end else begin
bufo_43_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_44_EN_A = 1'b1;
end else begin
bufo_44_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd44) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_44_WEN_A = 4'd15;
end else begin
bufo_44_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_45_EN_A = 1'b1;
end else begin
bufo_45_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd45) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_45_WEN_A = 4'd15;
end else begin
bufo_45_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_46_EN_A = 1'b1;
end else begin
bufo_46_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd46) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_46_WEN_A = 4'd15;
end else begin
bufo_46_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_47_EN_A = 1'b1;
end else begin
bufo_47_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd47) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_47_WEN_A = 4'd15;
end else begin
bufo_47_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_48_EN_A = 1'b1;
end else begin
bufo_48_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd48) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_48_WEN_A = 4'd15;
end else begin
bufo_48_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_49_EN_A = 1'b1;
end else begin
bufo_49_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd49) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_49_WEN_A = 4'd15;
end else begin
bufo_49_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_4_EN_A = 1'b1;
end else begin
bufo_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd4) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_4_WEN_A = 4'd15;
end else begin
bufo_4_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_50_EN_A = 1'b1;
end else begin
bufo_50_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd50) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_50_WEN_A = 4'd15;
end else begin
bufo_50_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_51_EN_A = 1'b1;
end else begin
bufo_51_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd51) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_51_WEN_A = 4'd15;
end else begin
bufo_51_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_52_EN_A = 1'b1;
end else begin
bufo_52_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd52) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_52_WEN_A = 4'd15;
end else begin
bufo_52_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_53_EN_A = 1'b1;
end else begin
bufo_53_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd53) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_53_WEN_A = 4'd15;
end else begin
bufo_53_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_54_EN_A = 1'b1;
end else begin
bufo_54_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd54) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_54_WEN_A = 4'd15;
end else begin
bufo_54_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_55_EN_A = 1'b1;
end else begin
bufo_55_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd55) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_55_WEN_A = 4'd15;
end else begin
bufo_55_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_56_EN_A = 1'b1;
end else begin
bufo_56_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd56) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_56_WEN_A = 4'd15;
end else begin
bufo_56_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_57_EN_A = 1'b1;
end else begin
bufo_57_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd57) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_57_WEN_A = 4'd15;
end else begin
bufo_57_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_58_EN_A = 1'b1;
end else begin
bufo_58_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd58) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_58_WEN_A = 4'd15;
end else begin
bufo_58_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_59_EN_A = 1'b1;
end else begin
bufo_59_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd59) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_59_WEN_A = 4'd15;
end else begin
bufo_59_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_5_EN_A = 1'b1;
end else begin
bufo_5_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd5) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_5_WEN_A = 4'd15;
end else begin
bufo_5_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_60_EN_A = 1'b1;
end else begin
bufo_60_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd60) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_60_WEN_A = 4'd15;
end else begin
bufo_60_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_61_EN_A = 1'b1;
end else begin
bufo_61_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd61) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_61_WEN_A = 4'd15;
end else begin
bufo_61_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_62_EN_A = 1'b1;
end else begin
bufo_62_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd62) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_62_WEN_A = 4'd15;
end else begin
bufo_62_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_63_EN_A = 1'b1;
end else begin
bufo_63_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd63) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_63_WEN_A = 4'd15;
end else begin
bufo_63_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_64_EN_A = 1'b1;
end else begin
bufo_64_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd64) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_64_WEN_A = 4'd15;
end else begin
bufo_64_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_65_EN_A = 1'b1;
end else begin
bufo_65_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd65) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_65_WEN_A = 4'd15;
end else begin
bufo_65_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_66_EN_A = 1'b1;
end else begin
bufo_66_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd66) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_66_WEN_A = 4'd15;
end else begin
bufo_66_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_67_EN_A = 1'b1;
end else begin
bufo_67_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd67) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_67_WEN_A = 4'd15;
end else begin
bufo_67_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_68_EN_A = 1'b1;
end else begin
bufo_68_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd68) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_68_WEN_A = 4'd15;
end else begin
bufo_68_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_69_EN_A = 1'b1;
end else begin
bufo_69_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd69) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_69_WEN_A = 4'd15;
end else begin
bufo_69_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_6_EN_A = 1'b1;
end else begin
bufo_6_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd6) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_6_WEN_A = 4'd15;
end else begin
bufo_6_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_70_EN_A = 1'b1;
end else begin
bufo_70_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd70) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_70_WEN_A = 4'd15;
end else begin
bufo_70_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_71_EN_A = 1'b1;
end else begin
bufo_71_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd71) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_71_WEN_A = 4'd15;
end else begin
bufo_71_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_72_EN_A = 1'b1;
end else begin
bufo_72_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd72) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_72_WEN_A = 4'd15;
end else begin
bufo_72_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_73_EN_A = 1'b1;
end else begin
bufo_73_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd73) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_73_WEN_A = 4'd15;
end else begin
bufo_73_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_74_EN_A = 1'b1;
end else begin
bufo_74_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd74) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_74_WEN_A = 4'd15;
end else begin
bufo_74_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_75_EN_A = 1'b1;
end else begin
bufo_75_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd75) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_75_WEN_A = 4'd15;
end else begin
bufo_75_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_76_EN_A = 1'b1;
end else begin
bufo_76_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd76) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_76_WEN_A = 4'd15;
end else begin
bufo_76_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_77_EN_A = 1'b1;
end else begin
bufo_77_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd77) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_77_WEN_A = 4'd15;
end else begin
bufo_77_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_78_EN_A = 1'b1;
end else begin
bufo_78_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd78) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_78_WEN_A = 4'd15;
end else begin
bufo_78_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_79_EN_A = 1'b1;
end else begin
bufo_79_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd79) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_79_WEN_A = 4'd15;
end else begin
bufo_79_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_7_EN_A = 1'b1;
end else begin
bufo_7_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd7) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_7_WEN_A = 4'd15;
end else begin
bufo_7_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_80_EN_A = 1'b1;
end else begin
bufo_80_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd80) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_80_WEN_A = 4'd15;
end else begin
bufo_80_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_81_EN_A = 1'b1;
end else begin
bufo_81_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd81) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_81_WEN_A = 4'd15;
end else begin
bufo_81_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_82_EN_A = 1'b1;
end else begin
bufo_82_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd82) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_82_WEN_A = 4'd15;
end else begin
bufo_82_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_83_EN_A = 1'b1;
end else begin
bufo_83_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd83) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_83_WEN_A = 4'd15;
end else begin
bufo_83_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_84_EN_A = 1'b1;
end else begin
bufo_84_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd84) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_84_WEN_A = 4'd15;
end else begin
bufo_84_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_85_EN_A = 1'b1;
end else begin
bufo_85_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd85) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_85_WEN_A = 4'd15;
end else begin
bufo_85_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_86_EN_A = 1'b1;
end else begin
bufo_86_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd86) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_86_WEN_A = 4'd15;
end else begin
bufo_86_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_87_EN_A = 1'b1;
end else begin
bufo_87_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd87) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_87_WEN_A = 4'd15;
end else begin
bufo_87_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_88_EN_A = 1'b1;
end else begin
bufo_88_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd88) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_88_WEN_A = 4'd15;
end else begin
bufo_88_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_89_EN_A = 1'b1;
end else begin
bufo_89_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd89) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_89_WEN_A = 4'd15;
end else begin
bufo_89_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_8_EN_A = 1'b1;
end else begin
bufo_8_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd8) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_8_WEN_A = 4'd15;
end else begin
bufo_8_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_90_EN_A = 1'b1;
end else begin
bufo_90_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd90) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_90_WEN_A = 4'd15;
end else begin
bufo_90_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_91_EN_A = 1'b1;
end else begin
bufo_91_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd91) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_91_WEN_A = 4'd15;
end else begin
bufo_91_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_92_EN_A = 1'b1;
end else begin
bufo_92_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd92) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_92_WEN_A = 4'd15;
end else begin
bufo_92_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_93_EN_A = 1'b1;
end else begin
bufo_93_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd93) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_93_WEN_A = 4'd15;
end else begin
bufo_93_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_94_EN_A = 1'b1;
end else begin
bufo_94_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd94) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_94_WEN_A = 4'd15;
end else begin
bufo_94_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_95_EN_A = 1'b1;
end else begin
bufo_95_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd95) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_95_WEN_A = 4'd15;
end else begin
bufo_95_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_96_EN_A = 1'b1;
end else begin
bufo_96_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd96) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_96_WEN_A = 4'd15;
end else begin
bufo_96_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_97_EN_A = 1'b1;
end else begin
bufo_97_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd97) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_97_WEN_A = 4'd15;
end else begin
bufo_97_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_98_EN_A = 1'b1;
end else begin
bufo_98_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd98) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_98_WEN_A = 4'd15;
end else begin
bufo_98_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_99_EN_A = 1'b1;
end else begin
bufo_99_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd99) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_99_WEN_A = 4'd15;
end else begin
bufo_99_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_9_EN_A = 1'b1;
end else begin
bufo_9_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd9) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_9_WEN_A = 4'd15;
end else begin
bufo_9_WEN_A = 4'd0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
bufw_EN_A = 1'b1;
end else begin
bufw_EN_A = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state47)) begin
grp_fu_2558_p0 = bufo_load_phi_reg_2296;
end else if (((1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state36))) begin
grp_fu_2558_p0 = reg_2580;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
grp_fu_2558_p0 = tmp_s_reg_3561;
end else begin
grp_fu_2558_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state47)) begin
grp_fu_2558_p1 = reg_2580;
end else if ((1'b1 == ap_CS_fsm_state36)) begin
grp_fu_2558_p1 = tmp_5_3_reg_3576;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
grp_fu_2558_p1 = tmp_5_2_reg_3571;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
grp_fu_2558_p1 = tmp_5_1_reg_3566;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
grp_fu_2558_p1 = 32'd0;
end else begin
grp_fu_2558_p1 = 'bx;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state6;
end
ap_ST_fsm_state6 : begin
ap_NS_fsm = ap_ST_fsm_state7;
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_state8;
end
ap_ST_fsm_state8 : begin
ap_NS_fsm = ap_ST_fsm_state9;
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state10;
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state11;
end
ap_ST_fsm_state11 : begin
ap_NS_fsm = ap_ST_fsm_state12;
end
ap_ST_fsm_state12 : begin
ap_NS_fsm = ap_ST_fsm_state13;
end
ap_ST_fsm_state13 : begin
ap_NS_fsm = ap_ST_fsm_state14;
end
ap_ST_fsm_state14 : begin
ap_NS_fsm = ap_ST_fsm_state15;
end
ap_ST_fsm_state15 : begin
ap_NS_fsm = ap_ST_fsm_state16;
end
ap_ST_fsm_state16 : begin
ap_NS_fsm = ap_ST_fsm_state17;
end
ap_ST_fsm_state17 : begin
ap_NS_fsm = ap_ST_fsm_state18;
end
ap_ST_fsm_state18 : begin
ap_NS_fsm = ap_ST_fsm_state19;
end
ap_ST_fsm_state19 : begin
ap_NS_fsm = ap_ST_fsm_state20;
end
ap_ST_fsm_state20 : begin
ap_NS_fsm = ap_ST_fsm_state21;
end
ap_ST_fsm_state21 : begin
ap_NS_fsm = ap_ST_fsm_state22;
end
ap_ST_fsm_state22 : begin
ap_NS_fsm = ap_ST_fsm_state23;
end
ap_ST_fsm_state23 : begin
ap_NS_fsm = ap_ST_fsm_state24;
end
ap_ST_fsm_state24 : begin
ap_NS_fsm = ap_ST_fsm_state25;
end
ap_ST_fsm_state25 : begin
ap_NS_fsm = ap_ST_fsm_state26;
end
ap_ST_fsm_state26 : begin
ap_NS_fsm = ap_ST_fsm_state27;
end
ap_ST_fsm_state27 : begin
ap_NS_fsm = ap_ST_fsm_state28;
end
ap_ST_fsm_state28 : begin
ap_NS_fsm = ap_ST_fsm_state29;
end
ap_ST_fsm_state29 : begin
ap_NS_fsm = ap_ST_fsm_state30;
end
ap_ST_fsm_state30 : begin
ap_NS_fsm = ap_ST_fsm_state31;
end
ap_ST_fsm_state31 : begin
ap_NS_fsm = ap_ST_fsm_state32;
end
ap_ST_fsm_state32 : begin
ap_NS_fsm = ap_ST_fsm_state33;
end
ap_ST_fsm_state33 : begin
ap_NS_fsm = ap_ST_fsm_state34;
end
ap_ST_fsm_state34 : begin
ap_NS_fsm = ap_ST_fsm_state35;
end
ap_ST_fsm_state35 : begin
ap_NS_fsm = ap_ST_fsm_state36;
end
ap_ST_fsm_state36 : begin
ap_NS_fsm = ap_ST_fsm_state37;
end
ap_ST_fsm_state37 : begin
ap_NS_fsm = ap_ST_fsm_state38;
end
ap_ST_fsm_state38 : begin
ap_NS_fsm = ap_ST_fsm_state39;
end
ap_ST_fsm_state39 : begin
ap_NS_fsm = ap_ST_fsm_state40;
end
ap_ST_fsm_state40 : begin
ap_NS_fsm = ap_ST_fsm_state41;
end
ap_ST_fsm_state41 : begin
ap_NS_fsm = ap_ST_fsm_state42;
end
ap_ST_fsm_state42 : begin
ap_NS_fsm = ap_ST_fsm_state43;
end
ap_ST_fsm_state43 : begin
ap_NS_fsm = ap_ST_fsm_state44;
end
ap_ST_fsm_state44 : begin
ap_NS_fsm = ap_ST_fsm_state45;
end
ap_ST_fsm_state45 : begin
ap_NS_fsm = ap_ST_fsm_state46;
end
ap_ST_fsm_state46 : begin
ap_NS_fsm = ap_ST_fsm_state47;
end
ap_ST_fsm_state47 : begin
ap_NS_fsm = ap_ST_fsm_state48;
end
ap_ST_fsm_state48 : begin
ap_NS_fsm = ap_ST_fsm_state49;
end
ap_ST_fsm_state49 : begin
ap_NS_fsm = ap_ST_fsm_state50;
end
ap_ST_fsm_state50 : begin
ap_NS_fsm = ap_ST_fsm_state51;
end
ap_ST_fsm_state51 : begin
ap_NS_fsm = ap_ST_fsm_state52;
end
ap_ST_fsm_state52 : begin
ap_NS_fsm = ap_ST_fsm_state53;
end
ap_ST_fsm_state53 : begin
ap_NS_fsm = ap_ST_fsm_state54;
end
ap_ST_fsm_state54 : begin
ap_NS_fsm = ap_ST_fsm_state55;
end
ap_ST_fsm_state55 : begin
ap_NS_fsm = ap_ST_fsm_state56;
end
ap_ST_fsm_state56 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16];
assign ap_CS_fsm_state18 = ap_CS_fsm[32'd17];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state26 = ap_CS_fsm[32'd25];
assign ap_CS_fsm_state27 = ap_CS_fsm[32'd26];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state35 = ap_CS_fsm[32'd34];
assign ap_CS_fsm_state36 = ap_CS_fsm[32'd35];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state44 = ap_CS_fsm[32'd43];
assign ap_CS_fsm_state45 = ap_CS_fsm[32'd44];
assign ap_CS_fsm_state46 = ap_CS_fsm[32'd45];
assign ap_CS_fsm_state47 = ap_CS_fsm[32'd46];
assign ap_CS_fsm_state55 = ap_CS_fsm[32'd54];
assign ap_CS_fsm_state56 = ap_CS_fsm[32'd55];
assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8];
assign ap_done = 1'b0;
assign ap_ready = 1'b0;
assign bufi_Addr_A = bufi_Addr_A_orig << 32'd4;
assign bufi_Addr_A_orig = 64'd0;
assign bufi_Clk_A = ap_clk;
assign bufi_Din_A = 128'd0;
assign bufi_Rst_A = ap_rst;
assign bufi_WEN_A = 16'd0;
assign bufo_0_Addr_A = bufo_0_Addr_A_orig << 32'd2;
assign bufo_0_Addr_A_orig = 64'd0;
assign bufo_0_Clk_A = ap_clk;
assign bufo_0_Din_A = reg_2580;
assign bufo_0_Rst_A = ap_rst;
assign bufo_100_Addr_A = bufo_100_Addr_A_orig << 32'd2;
assign bufo_100_Addr_A_orig = 64'd0;
assign bufo_100_Clk_A = ap_clk;
assign bufo_100_Din_A = reg_2580;
assign bufo_100_Rst_A = ap_rst;
assign bufo_101_Addr_A = bufo_101_Addr_A_orig << 32'd2;
assign bufo_101_Addr_A_orig = 64'd0;
assign bufo_101_Clk_A = ap_clk;
assign bufo_101_Din_A = reg_2580;
assign bufo_101_Rst_A = ap_rst;
assign bufo_102_Addr_A = bufo_102_Addr_A_orig << 32'd2;
assign bufo_102_Addr_A_orig = 64'd0;
assign bufo_102_Clk_A = ap_clk;
assign bufo_102_Din_A = reg_2580;
assign bufo_102_Rst_A = ap_rst;
assign bufo_103_Addr_A = bufo_103_Addr_A_orig << 32'd2;
assign bufo_103_Addr_A_orig = 64'd0;
assign bufo_103_Clk_A = ap_clk;
assign bufo_103_Din_A = reg_2580;
assign bufo_103_Rst_A = ap_rst;
assign bufo_104_Addr_A = bufo_104_Addr_A_orig << 32'd2;
assign bufo_104_Addr_A_orig = 64'd0;
assign bufo_104_Clk_A = ap_clk;
assign bufo_104_Din_A = reg_2580;
assign bufo_104_Rst_A = ap_rst;
assign bufo_105_Addr_A = bufo_105_Addr_A_orig << 32'd2;
assign bufo_105_Addr_A_orig = 64'd0;
assign bufo_105_Clk_A = ap_clk;
assign bufo_105_Din_A = reg_2580;
assign bufo_105_Rst_A = ap_rst;
assign bufo_106_Addr_A = bufo_106_Addr_A_orig << 32'd2;
assign bufo_106_Addr_A_orig = 64'd0;
assign bufo_106_Clk_A = ap_clk;
assign bufo_106_Din_A = reg_2580;
assign bufo_106_Rst_A = ap_rst;
assign bufo_107_Addr_A = bufo_107_Addr_A_orig << 32'd2;
assign bufo_107_Addr_A_orig = 64'd0;
assign bufo_107_Clk_A = ap_clk;
assign bufo_107_Din_A = reg_2580;
assign bufo_107_Rst_A = ap_rst;
assign bufo_108_Addr_A = bufo_108_Addr_A_orig << 32'd2;
assign bufo_108_Addr_A_orig = 64'd0;
assign bufo_108_Clk_A = ap_clk;
assign bufo_108_Din_A = reg_2580;
assign bufo_108_Rst_A = ap_rst;
assign bufo_109_Addr_A = bufo_109_Addr_A_orig << 32'd2;
assign bufo_109_Addr_A_orig = 64'd0;
assign bufo_109_Clk_A = ap_clk;
assign bufo_109_Din_A = reg_2580;
assign bufo_109_Rst_A = ap_rst;
assign bufo_10_Addr_A = bufo_10_Addr_A_orig << 32'd2;
assign bufo_10_Addr_A_orig = 64'd0;
assign bufo_10_Clk_A = ap_clk;
assign bufo_10_Din_A = reg_2580;
assign bufo_10_Rst_A = ap_rst;
assign bufo_110_Addr_A = bufo_110_Addr_A_orig << 32'd2;
assign bufo_110_Addr_A_orig = 64'd0;
assign bufo_110_Clk_A = ap_clk;
assign bufo_110_Din_A = reg_2580;
assign bufo_110_Rst_A = ap_rst;
assign bufo_111_Addr_A = bufo_111_Addr_A_orig << 32'd2;
assign bufo_111_Addr_A_orig = 64'd0;
assign bufo_111_Clk_A = ap_clk;
assign bufo_111_Din_A = reg_2580;
assign bufo_111_Rst_A = ap_rst;
assign bufo_112_Addr_A = bufo_112_Addr_A_orig << 32'd2;
assign bufo_112_Addr_A_orig = 64'd0;
assign bufo_112_Clk_A = ap_clk;
assign bufo_112_Din_A = reg_2580;
assign bufo_112_Rst_A = ap_rst;
assign bufo_113_Addr_A = bufo_113_Addr_A_orig << 32'd2;
assign bufo_113_Addr_A_orig = 64'd0;
assign bufo_113_Clk_A = ap_clk;
assign bufo_113_Din_A = reg_2580;
assign bufo_113_Rst_A = ap_rst;
assign bufo_114_Addr_A = bufo_114_Addr_A_orig << 32'd2;
assign bufo_114_Addr_A_orig = 64'd0;
assign bufo_114_Clk_A = ap_clk;
assign bufo_114_Din_A = reg_2580;
assign bufo_114_Rst_A = ap_rst;
assign bufo_115_Addr_A = bufo_115_Addr_A_orig << 32'd2;
assign bufo_115_Addr_A_orig = 64'd0;
assign bufo_115_Clk_A = ap_clk;
assign bufo_115_Din_A = reg_2580;
assign bufo_115_Rst_A = ap_rst;
assign bufo_116_Addr_A = bufo_116_Addr_A_orig << 32'd2;
assign bufo_116_Addr_A_orig = 64'd0;
assign bufo_116_Clk_A = ap_clk;
assign bufo_116_Din_A = reg_2580;
assign bufo_116_Rst_A = ap_rst;
assign bufo_117_Addr_A = bufo_117_Addr_A_orig << 32'd2;
assign bufo_117_Addr_A_orig = 64'd0;
assign bufo_117_Clk_A = ap_clk;
assign bufo_117_Din_A = reg_2580;
assign bufo_117_Rst_A = ap_rst;
assign bufo_118_Addr_A = bufo_118_Addr_A_orig << 32'd2;
assign bufo_118_Addr_A_orig = 64'd0;
assign bufo_118_Clk_A = ap_clk;
assign bufo_118_Din_A = reg_2580;
assign bufo_118_Rst_A = ap_rst;
assign bufo_119_Addr_A = bufo_119_Addr_A_orig << 32'd2;
assign bufo_119_Addr_A_orig = 64'd0;
assign bufo_119_Clk_A = ap_clk;
assign bufo_119_Din_A = reg_2580;
assign bufo_119_Rst_A = ap_rst;
assign bufo_11_Addr_A = bufo_11_Addr_A_orig << 32'd2;
assign bufo_11_Addr_A_orig = 64'd0;
assign bufo_11_Clk_A = ap_clk;
assign bufo_11_Din_A = reg_2580;
assign bufo_11_Rst_A = ap_rst;
assign bufo_120_Addr_A = bufo_120_Addr_A_orig << 32'd2;
assign bufo_120_Addr_A_orig = 64'd0;
assign bufo_120_Clk_A = ap_clk;
assign bufo_120_Din_A = reg_2580;
assign bufo_120_Rst_A = ap_rst;
assign bufo_121_Addr_A = bufo_121_Addr_A_orig << 32'd2;
assign bufo_121_Addr_A_orig = 64'd0;
assign bufo_121_Clk_A = ap_clk;
assign bufo_121_Din_A = reg_2580;
assign bufo_121_Rst_A = ap_rst;
assign bufo_122_Addr_A = bufo_122_Addr_A_orig << 32'd2;
assign bufo_122_Addr_A_orig = 64'd0;
assign bufo_122_Clk_A = ap_clk;
assign bufo_122_Din_A = reg_2580;
assign bufo_122_Rst_A = ap_rst;
assign bufo_123_Addr_A = bufo_123_Addr_A_orig << 32'd2;
assign bufo_123_Addr_A_orig = 64'd0;
assign bufo_123_Clk_A = ap_clk;
assign bufo_123_Din_A = reg_2580;
assign bufo_123_Rst_A = ap_rst;
assign bufo_124_Addr_A = bufo_124_Addr_A_orig << 32'd2;
assign bufo_124_Addr_A_orig = 64'd0;
assign bufo_124_Clk_A = ap_clk;
assign bufo_124_Din_A = reg_2580;
assign bufo_124_Rst_A = ap_rst;
assign bufo_125_Addr_A = bufo_125_Addr_A_orig << 32'd2;
assign bufo_125_Addr_A_orig = 64'd0;
assign bufo_125_Clk_A = ap_clk;
assign bufo_125_Din_A = reg_2580;
assign bufo_125_Rst_A = ap_rst;
assign bufo_126_Addr_A = bufo_126_Addr_A_orig << 32'd2;
assign bufo_126_Addr_A_orig = 64'd0;
assign bufo_126_Clk_A = ap_clk;
assign bufo_126_Din_A = reg_2580;
assign bufo_126_Rst_A = ap_rst;
assign bufo_127_Addr_A = bufo_127_Addr_A_orig << 32'd2;
assign bufo_127_Addr_A_orig = 64'd0;
assign bufo_127_Clk_A = ap_clk;
assign bufo_127_Din_A = reg_2580;
assign bufo_127_Rst_A = ap_rst;
assign bufo_128_Addr_A = 32'd0;
assign bufo_128_Addr_B = 32'd0;
assign bufo_128_Clk_A = ap_clk;
assign bufo_128_Clk_B = ap_clk;
assign bufo_128_Din_A = 32'd0;
assign bufo_128_Din_B = 32'd0;
assign bufo_128_EN_A = 1'b0;
assign bufo_128_EN_B = 1'b0;
assign bufo_128_Rst_A = ap_rst;
assign bufo_128_Rst_B = ap_rst;
assign bufo_128_WEN_A = 4'd0;
assign bufo_128_WEN_B = 4'd0;
assign bufo_129_Addr_A = 32'd0;
assign bufo_129_Addr_B = 32'd0;
assign bufo_129_Clk_A = ap_clk;
assign bufo_129_Clk_B = ap_clk;
assign bufo_129_Din_A = 32'd0;
assign bufo_129_Din_B = 32'd0;
assign bufo_129_EN_A = 1'b0;
assign bufo_129_EN_B = 1'b0;
assign bufo_129_Rst_A = ap_rst;
assign bufo_129_Rst_B = ap_rst;
assign bufo_129_WEN_A = 4'd0;
assign bufo_129_WEN_B = 4'd0;
assign bufo_12_Addr_A = bufo_12_Addr_A_orig << 32'd2;
assign bufo_12_Addr_A_orig = 64'd0;
assign bufo_12_Clk_A = ap_clk;
assign bufo_12_Din_A = reg_2580;
assign bufo_12_Rst_A = ap_rst;
assign bufo_130_Addr_A = 32'd0;
assign bufo_130_Addr_B = 32'd0;
assign bufo_130_Clk_A = ap_clk;
assign bufo_130_Clk_B = ap_clk;
assign bufo_130_Din_A = 32'd0;
assign bufo_130_Din_B = 32'd0;
assign bufo_130_EN_A = 1'b0;
assign bufo_130_EN_B = 1'b0;
assign bufo_130_Rst_A = ap_rst;
assign bufo_130_Rst_B = ap_rst;
assign bufo_130_WEN_A = 4'd0;
assign bufo_130_WEN_B = 4'd0;
assign bufo_131_Addr_A = 32'd0;
assign bufo_131_Addr_B = 32'd0;
assign bufo_131_Clk_A = ap_clk;
assign bufo_131_Clk_B = ap_clk;
assign bufo_131_Din_A = 32'd0;
assign bufo_131_Din_B = 32'd0;
assign bufo_131_EN_A = 1'b0;
assign bufo_131_EN_B = 1'b0;
assign bufo_131_Rst_A = ap_rst;
assign bufo_131_Rst_B = ap_rst;
assign bufo_131_WEN_A = 4'd0;
assign bufo_131_WEN_B = 4'd0;
assign bufo_132_Addr_A = 32'd0;
assign bufo_132_Addr_B = 32'd0;
assign bufo_132_Clk_A = ap_clk;
assign bufo_132_Clk_B = ap_clk;
assign bufo_132_Din_A = 32'd0;
assign bufo_132_Din_B = 32'd0;
assign bufo_132_EN_A = 1'b0;
assign bufo_132_EN_B = 1'b0;
assign bufo_132_Rst_A = ap_rst;
assign bufo_132_Rst_B = ap_rst;
assign bufo_132_WEN_A = 4'd0;
assign bufo_132_WEN_B = 4'd0;
assign bufo_133_Addr_A = 32'd0;
assign bufo_133_Addr_B = 32'd0;
assign bufo_133_Clk_A = ap_clk;
assign bufo_133_Clk_B = ap_clk;
assign bufo_133_Din_A = 32'd0;
assign bufo_133_Din_B = 32'd0;
assign bufo_133_EN_A = 1'b0;
assign bufo_133_EN_B = 1'b0;
assign bufo_133_Rst_A = ap_rst;
assign bufo_133_Rst_B = ap_rst;
assign bufo_133_WEN_A = 4'd0;
assign bufo_133_WEN_B = 4'd0;
assign bufo_134_Addr_A = 32'd0;
assign bufo_134_Addr_B = 32'd0;
assign bufo_134_Clk_A = ap_clk;
assign bufo_134_Clk_B = ap_clk;
assign bufo_134_Din_A = 32'd0;
assign bufo_134_Din_B = 32'd0;
assign bufo_134_EN_A = 1'b0;
assign bufo_134_EN_B = 1'b0;
assign bufo_134_Rst_A = ap_rst;
assign bufo_134_Rst_B = ap_rst;
assign bufo_134_WEN_A = 4'd0;
assign bufo_134_WEN_B = 4'd0;
assign bufo_135_Addr_A = 32'd0;
assign bufo_135_Addr_B = 32'd0;
assign bufo_135_Clk_A = ap_clk;
assign bufo_135_Clk_B = ap_clk;
assign bufo_135_Din_A = 32'd0;
assign bufo_135_Din_B = 32'd0;
assign bufo_135_EN_A = 1'b0;
assign bufo_135_EN_B = 1'b0;
assign bufo_135_Rst_A = ap_rst;
assign bufo_135_Rst_B = ap_rst;
assign bufo_135_WEN_A = 4'd0;
assign bufo_135_WEN_B = 4'd0;
assign bufo_136_Addr_A = 32'd0;
assign bufo_136_Addr_B = 32'd0;
assign bufo_136_Clk_A = ap_clk;
assign bufo_136_Clk_B = ap_clk;
assign bufo_136_Din_A = 32'd0;
assign bufo_136_Din_B = 32'd0;
assign bufo_136_EN_A = 1'b0;
assign bufo_136_EN_B = 1'b0;
assign bufo_136_Rst_A = ap_rst;
assign bufo_136_Rst_B = ap_rst;
assign bufo_136_WEN_A = 4'd0;
assign bufo_136_WEN_B = 4'd0;
assign bufo_137_Addr_A = 32'd0;
assign bufo_137_Addr_B = 32'd0;
assign bufo_137_Clk_A = ap_clk;
assign bufo_137_Clk_B = ap_clk;
assign bufo_137_Din_A = 32'd0;
assign bufo_137_Din_B = 32'd0;
assign bufo_137_EN_A = 1'b0;
assign bufo_137_EN_B = 1'b0;
assign bufo_137_Rst_A = ap_rst;
assign bufo_137_Rst_B = ap_rst;
assign bufo_137_WEN_A = 4'd0;
assign bufo_137_WEN_B = 4'd0;
assign bufo_138_Addr_A = 32'd0;
assign bufo_138_Addr_B = 32'd0;
assign bufo_138_Clk_A = ap_clk;
assign bufo_138_Clk_B = ap_clk;
assign bufo_138_Din_A = 32'd0;
assign bufo_138_Din_B = 32'd0;
assign bufo_138_EN_A = 1'b0;
assign bufo_138_EN_B = 1'b0;
assign bufo_138_Rst_A = ap_rst;
assign bufo_138_Rst_B = ap_rst;
assign bufo_138_WEN_A = 4'd0;
assign bufo_138_WEN_B = 4'd0;
assign bufo_139_Addr_A = 32'd0;
assign bufo_139_Addr_B = 32'd0;
assign bufo_139_Clk_A = ap_clk;
assign bufo_139_Clk_B = ap_clk;
assign bufo_139_Din_A = 32'd0;
assign bufo_139_Din_B = 32'd0;
assign bufo_139_EN_A = 1'b0;
assign bufo_139_EN_B = 1'b0;
assign bufo_139_Rst_A = ap_rst;
assign bufo_139_Rst_B = ap_rst;
assign bufo_139_WEN_A = 4'd0;
assign bufo_139_WEN_B = 4'd0;
assign bufo_13_Addr_A = bufo_13_Addr_A_orig << 32'd2;
assign bufo_13_Addr_A_orig = 64'd0;
assign bufo_13_Clk_A = ap_clk;
assign bufo_13_Din_A = reg_2580;
assign bufo_13_Rst_A = ap_rst;
assign bufo_140_Addr_A = 32'd0;
assign bufo_140_Addr_B = 32'd0;
assign bufo_140_Clk_A = ap_clk;
assign bufo_140_Clk_B = ap_clk;
assign bufo_140_Din_A = 32'd0;
assign bufo_140_Din_B = 32'd0;
assign bufo_140_EN_A = 1'b0;
assign bufo_140_EN_B = 1'b0;
assign bufo_140_Rst_A = ap_rst;
assign bufo_140_Rst_B = ap_rst;
assign bufo_140_WEN_A = 4'd0;
assign bufo_140_WEN_B = 4'd0;
assign bufo_141_Addr_A = 32'd0;
assign bufo_141_Addr_B = 32'd0;
assign bufo_141_Clk_A = ap_clk;
assign bufo_141_Clk_B = ap_clk;
assign bufo_141_Din_A = 32'd0;
assign bufo_141_Din_B = 32'd0;
assign bufo_141_EN_A = 1'b0;
assign bufo_141_EN_B = 1'b0;
assign bufo_141_Rst_A = ap_rst;
assign bufo_141_Rst_B = ap_rst;
assign bufo_141_WEN_A = 4'd0;
assign bufo_141_WEN_B = 4'd0;
assign bufo_142_Addr_A = 32'd0;
assign bufo_142_Addr_B = 32'd0;
assign bufo_142_Clk_A = ap_clk;
assign bufo_142_Clk_B = ap_clk;
assign bufo_142_Din_A = 32'd0;
assign bufo_142_Din_B = 32'd0;
assign bufo_142_EN_A = 1'b0;
assign bufo_142_EN_B = 1'b0;
assign bufo_142_Rst_A = ap_rst;
assign bufo_142_Rst_B = ap_rst;
assign bufo_142_WEN_A = 4'd0;
assign bufo_142_WEN_B = 4'd0;
assign bufo_143_Addr_A = 32'd0;
assign bufo_143_Addr_B = 32'd0;
assign bufo_143_Clk_A = ap_clk;
assign bufo_143_Clk_B = ap_clk;
assign bufo_143_Din_A = 32'd0;
assign bufo_143_Din_B = 32'd0;
assign bufo_143_EN_A = 1'b0;
assign bufo_143_EN_B = 1'b0;
assign bufo_143_Rst_A = ap_rst;
assign bufo_143_Rst_B = ap_rst;
assign bufo_143_WEN_A = 4'd0;
assign bufo_143_WEN_B = 4'd0;
assign bufo_144_Addr_A = 32'd0;
assign bufo_144_Addr_B = 32'd0;
assign bufo_144_Clk_A = ap_clk;
assign bufo_144_Clk_B = ap_clk;
assign bufo_144_Din_A = 32'd0;
assign bufo_144_Din_B = 32'd0;
assign bufo_144_EN_A = 1'b0;
assign bufo_144_EN_B = 1'b0;
assign bufo_144_Rst_A = ap_rst;
assign bufo_144_Rst_B = ap_rst;
assign bufo_144_WEN_A = 4'd0;
assign bufo_144_WEN_B = 4'd0;
assign bufo_145_Addr_A = 32'd0;
assign bufo_145_Addr_B = 32'd0;
assign bufo_145_Clk_A = ap_clk;
assign bufo_145_Clk_B = ap_clk;
assign bufo_145_Din_A = 32'd0;
assign bufo_145_Din_B = 32'd0;
assign bufo_145_EN_A = 1'b0;
assign bufo_145_EN_B = 1'b0;
assign bufo_145_Rst_A = ap_rst;
assign bufo_145_Rst_B = ap_rst;
assign bufo_145_WEN_A = 4'd0;
assign bufo_145_WEN_B = 4'd0;
assign bufo_146_Addr_A = 32'd0;
assign bufo_146_Addr_B = 32'd0;
assign bufo_146_Clk_A = ap_clk;
assign bufo_146_Clk_B = ap_clk;
assign bufo_146_Din_A = 32'd0;
assign bufo_146_Din_B = 32'd0;
assign bufo_146_EN_A = 1'b0;
assign bufo_146_EN_B = 1'b0;
assign bufo_146_Rst_A = ap_rst;
assign bufo_146_Rst_B = ap_rst;
assign bufo_146_WEN_A = 4'd0;
assign bufo_146_WEN_B = 4'd0;
assign bufo_147_Addr_A = 32'd0;
assign bufo_147_Addr_B = 32'd0;
assign bufo_147_Clk_A = ap_clk;
assign bufo_147_Clk_B = ap_clk;
assign bufo_147_Din_A = 32'd0;
assign bufo_147_Din_B = 32'd0;
assign bufo_147_EN_A = 1'b0;
assign bufo_147_EN_B = 1'b0;
assign bufo_147_Rst_A = ap_rst;
assign bufo_147_Rst_B = ap_rst;
assign bufo_147_WEN_A = 4'd0;
assign bufo_147_WEN_B = 4'd0;
assign bufo_148_Addr_A = 32'd0;
assign bufo_148_Addr_B = 32'd0;
assign bufo_148_Clk_A = ap_clk;
assign bufo_148_Clk_B = ap_clk;
assign bufo_148_Din_A = 32'd0;
assign bufo_148_Din_B = 32'd0;
assign bufo_148_EN_A = 1'b0;
assign bufo_148_EN_B = 1'b0;
assign bufo_148_Rst_A = ap_rst;
assign bufo_148_Rst_B = ap_rst;
assign bufo_148_WEN_A = 4'd0;
assign bufo_148_WEN_B = 4'd0;
assign bufo_149_Addr_A = 32'd0;
assign bufo_149_Addr_B = 32'd0;
assign bufo_149_Clk_A = ap_clk;
assign bufo_149_Clk_B = ap_clk;
assign bufo_149_Din_A = 32'd0;
assign bufo_149_Din_B = 32'd0;
assign bufo_149_EN_A = 1'b0;
assign bufo_149_EN_B = 1'b0;
assign bufo_149_Rst_A = ap_rst;
assign bufo_149_Rst_B = ap_rst;
assign bufo_149_WEN_A = 4'd0;
assign bufo_149_WEN_B = 4'd0;
assign bufo_14_Addr_A = bufo_14_Addr_A_orig << 32'd2;
assign bufo_14_Addr_A_orig = 64'd0;
assign bufo_14_Clk_A = ap_clk;
assign bufo_14_Din_A = reg_2580;
assign bufo_14_Rst_A = ap_rst;
assign bufo_150_Addr_A = 32'd0;
assign bufo_150_Addr_B = 32'd0;
assign bufo_150_Clk_A = ap_clk;
assign bufo_150_Clk_B = ap_clk;
assign bufo_150_Din_A = 32'd0;
assign bufo_150_Din_B = 32'd0;
assign bufo_150_EN_A = 1'b0;
assign bufo_150_EN_B = 1'b0;
assign bufo_150_Rst_A = ap_rst;
assign bufo_150_Rst_B = ap_rst;
assign bufo_150_WEN_A = 4'd0;
assign bufo_150_WEN_B = 4'd0;
assign bufo_151_Addr_A = 32'd0;
assign bufo_151_Addr_B = 32'd0;
assign bufo_151_Clk_A = ap_clk;
assign bufo_151_Clk_B = ap_clk;
assign bufo_151_Din_A = 32'd0;
assign bufo_151_Din_B = 32'd0;
assign bufo_151_EN_A = 1'b0;
assign bufo_151_EN_B = 1'b0;
assign bufo_151_Rst_A = ap_rst;
assign bufo_151_Rst_B = ap_rst;
assign bufo_151_WEN_A = 4'd0;
assign bufo_151_WEN_B = 4'd0;
assign bufo_152_Addr_A = 32'd0;
assign bufo_152_Addr_B = 32'd0;
assign bufo_152_Clk_A = ap_clk;
assign bufo_152_Clk_B = ap_clk;
assign bufo_152_Din_A = 32'd0;
assign bufo_152_Din_B = 32'd0;
assign bufo_152_EN_A = 1'b0;
assign bufo_152_EN_B = 1'b0;
assign bufo_152_Rst_A = ap_rst;
assign bufo_152_Rst_B = ap_rst;
assign bufo_152_WEN_A = 4'd0;
assign bufo_152_WEN_B = 4'd0;
assign bufo_153_Addr_A = 32'd0;
assign bufo_153_Addr_B = 32'd0;
assign bufo_153_Clk_A = ap_clk;
assign bufo_153_Clk_B = ap_clk;
assign bufo_153_Din_A = 32'd0;
assign bufo_153_Din_B = 32'd0;
assign bufo_153_EN_A = 1'b0;
assign bufo_153_EN_B = 1'b0;
assign bufo_153_Rst_A = ap_rst;
assign bufo_153_Rst_B = ap_rst;
assign bufo_153_WEN_A = 4'd0;
assign bufo_153_WEN_B = 4'd0;
assign bufo_154_Addr_A = 32'd0;
assign bufo_154_Addr_B = 32'd0;
assign bufo_154_Clk_A = ap_clk;
assign bufo_154_Clk_B = ap_clk;
assign bufo_154_Din_A = 32'd0;
assign bufo_154_Din_B = 32'd0;
assign bufo_154_EN_A = 1'b0;
assign bufo_154_EN_B = 1'b0;
assign bufo_154_Rst_A = ap_rst;
assign bufo_154_Rst_B = ap_rst;
assign bufo_154_WEN_A = 4'd0;
assign bufo_154_WEN_B = 4'd0;
assign bufo_155_Addr_A = 32'd0;
assign bufo_155_Addr_B = 32'd0;
assign bufo_155_Clk_A = ap_clk;
assign bufo_155_Clk_B = ap_clk;
assign bufo_155_Din_A = 32'd0;
assign bufo_155_Din_B = 32'd0;
assign bufo_155_EN_A = 1'b0;
assign bufo_155_EN_B = 1'b0;
assign bufo_155_Rst_A = ap_rst;
assign bufo_155_Rst_B = ap_rst;
assign bufo_155_WEN_A = 4'd0;
assign bufo_155_WEN_B = 4'd0;
assign bufo_156_Addr_A = 32'd0;
assign bufo_156_Addr_B = 32'd0;
assign bufo_156_Clk_A = ap_clk;
assign bufo_156_Clk_B = ap_clk;
assign bufo_156_Din_A = 32'd0;
assign bufo_156_Din_B = 32'd0;
assign bufo_156_EN_A = 1'b0;
assign bufo_156_EN_B = 1'b0;
assign bufo_156_Rst_A = ap_rst;
assign bufo_156_Rst_B = ap_rst;
assign bufo_156_WEN_A = 4'd0;
assign bufo_156_WEN_B = 4'd0;
assign bufo_157_Addr_A = 32'd0;
assign bufo_157_Addr_B = 32'd0;
assign bufo_157_Clk_A = ap_clk;
assign bufo_157_Clk_B = ap_clk;
assign bufo_157_Din_A = 32'd0;
assign bufo_157_Din_B = 32'd0;
assign bufo_157_EN_A = 1'b0;
assign bufo_157_EN_B = 1'b0;
assign bufo_157_Rst_A = ap_rst;
assign bufo_157_Rst_B = ap_rst;
assign bufo_157_WEN_A = 4'd0;
assign bufo_157_WEN_B = 4'd0;
assign bufo_158_Addr_A = 32'd0;
assign bufo_158_Addr_B = 32'd0;
assign bufo_158_Clk_A = ap_clk;
assign bufo_158_Clk_B = ap_clk;
assign bufo_158_Din_A = 32'd0;
assign bufo_158_Din_B = 32'd0;
assign bufo_158_EN_A = 1'b0;
assign bufo_158_EN_B = 1'b0;
assign bufo_158_Rst_A = ap_rst;
assign bufo_158_Rst_B = ap_rst;
assign bufo_158_WEN_A = 4'd0;
assign bufo_158_WEN_B = 4'd0;
assign bufo_159_Addr_A = 32'd0;
assign bufo_159_Addr_B = 32'd0;
assign bufo_159_Clk_A = ap_clk;
assign bufo_159_Clk_B = ap_clk;
assign bufo_159_Din_A = 32'd0;
assign bufo_159_Din_B = 32'd0;
assign bufo_159_EN_A = 1'b0;
assign bufo_159_EN_B = 1'b0;
assign bufo_159_Rst_A = ap_rst;
assign bufo_159_Rst_B = ap_rst;
assign bufo_159_WEN_A = 4'd0;
assign bufo_159_WEN_B = 4'd0;
assign bufo_15_Addr_A = bufo_15_Addr_A_orig << 32'd2;
assign bufo_15_Addr_A_orig = 64'd0;
assign bufo_15_Clk_A = ap_clk;
assign bufo_15_Din_A = reg_2580;
assign bufo_15_Rst_A = ap_rst;
assign bufo_160_Addr_A = 32'd0;
assign bufo_160_Addr_B = 32'd0;
assign bufo_160_Clk_A = ap_clk;
assign bufo_160_Clk_B = ap_clk;
assign bufo_160_Din_A = 32'd0;
assign bufo_160_Din_B = 32'd0;
assign bufo_160_EN_A = 1'b0;
assign bufo_160_EN_B = 1'b0;
assign bufo_160_Rst_A = ap_rst;
assign bufo_160_Rst_B = ap_rst;
assign bufo_160_WEN_A = 4'd0;
assign bufo_160_WEN_B = 4'd0;
assign bufo_161_Addr_A = 32'd0;
assign bufo_161_Addr_B = 32'd0;
assign bufo_161_Clk_A = ap_clk;
assign bufo_161_Clk_B = ap_clk;
assign bufo_161_Din_A = 32'd0;
assign bufo_161_Din_B = 32'd0;
assign bufo_161_EN_A = 1'b0;
assign bufo_161_EN_B = 1'b0;
assign bufo_161_Rst_A = ap_rst;
assign bufo_161_Rst_B = ap_rst;
assign bufo_161_WEN_A = 4'd0;
assign bufo_161_WEN_B = 4'd0;
assign bufo_162_Addr_A = 32'd0;
assign bufo_162_Addr_B = 32'd0;
assign bufo_162_Clk_A = ap_clk;
assign bufo_162_Clk_B = ap_clk;
assign bufo_162_Din_A = 32'd0;
assign bufo_162_Din_B = 32'd0;
assign bufo_162_EN_A = 1'b0;
assign bufo_162_EN_B = 1'b0;
assign bufo_162_Rst_A = ap_rst;
assign bufo_162_Rst_B = ap_rst;
assign bufo_162_WEN_A = 4'd0;
assign bufo_162_WEN_B = 4'd0;
assign bufo_163_Addr_A = 32'd0;
assign bufo_163_Addr_B = 32'd0;
assign bufo_163_Clk_A = ap_clk;
assign bufo_163_Clk_B = ap_clk;
assign bufo_163_Din_A = 32'd0;
assign bufo_163_Din_B = 32'd0;
assign bufo_163_EN_A = 1'b0;
assign bufo_163_EN_B = 1'b0;
assign bufo_163_Rst_A = ap_rst;
assign bufo_163_Rst_B = ap_rst;
assign bufo_163_WEN_A = 4'd0;
assign bufo_163_WEN_B = 4'd0;
assign bufo_164_Addr_A = 32'd0;
assign bufo_164_Addr_B = 32'd0;
assign bufo_164_Clk_A = ap_clk;
assign bufo_164_Clk_B = ap_clk;
assign bufo_164_Din_A = 32'd0;
assign bufo_164_Din_B = 32'd0;
assign bufo_164_EN_A = 1'b0;
assign bufo_164_EN_B = 1'b0;
assign bufo_164_Rst_A = ap_rst;
assign bufo_164_Rst_B = ap_rst;
assign bufo_164_WEN_A = 4'd0;
assign bufo_164_WEN_B = 4'd0;
assign bufo_165_Addr_A = 32'd0;
assign bufo_165_Addr_B = 32'd0;
assign bufo_165_Clk_A = ap_clk;
assign bufo_165_Clk_B = ap_clk;
assign bufo_165_Din_A = 32'd0;
assign bufo_165_Din_B = 32'd0;
assign bufo_165_EN_A = 1'b0;
assign bufo_165_EN_B = 1'b0;
assign bufo_165_Rst_A = ap_rst;
assign bufo_165_Rst_B = ap_rst;
assign bufo_165_WEN_A = 4'd0;
assign bufo_165_WEN_B = 4'd0;
assign bufo_166_Addr_A = 32'd0;
assign bufo_166_Addr_B = 32'd0;
assign bufo_166_Clk_A = ap_clk;
assign bufo_166_Clk_B = ap_clk;
assign bufo_166_Din_A = 32'd0;
assign bufo_166_Din_B = 32'd0;
assign bufo_166_EN_A = 1'b0;
assign bufo_166_EN_B = 1'b0;
assign bufo_166_Rst_A = ap_rst;
assign bufo_166_Rst_B = ap_rst;
assign bufo_166_WEN_A = 4'd0;
assign bufo_166_WEN_B = 4'd0;
assign bufo_167_Addr_A = 32'd0;
assign bufo_167_Addr_B = 32'd0;
assign bufo_167_Clk_A = ap_clk;
assign bufo_167_Clk_B = ap_clk;
assign bufo_167_Din_A = 32'd0;
assign bufo_167_Din_B = 32'd0;
assign bufo_167_EN_A = 1'b0;
assign bufo_167_EN_B = 1'b0;
assign bufo_167_Rst_A = ap_rst;
assign bufo_167_Rst_B = ap_rst;
assign bufo_167_WEN_A = 4'd0;
assign bufo_167_WEN_B = 4'd0;
assign bufo_168_Addr_A = 32'd0;
assign bufo_168_Addr_B = 32'd0;
assign bufo_168_Clk_A = ap_clk;
assign bufo_168_Clk_B = ap_clk;
assign bufo_168_Din_A = 32'd0;
assign bufo_168_Din_B = 32'd0;
assign bufo_168_EN_A = 1'b0;
assign bufo_168_EN_B = 1'b0;
assign bufo_168_Rst_A = ap_rst;
assign bufo_168_Rst_B = ap_rst;
assign bufo_168_WEN_A = 4'd0;
assign bufo_168_WEN_B = 4'd0;
assign bufo_169_Addr_A = 32'd0;
assign bufo_169_Addr_B = 32'd0;
assign bufo_169_Clk_A = ap_clk;
assign bufo_169_Clk_B = ap_clk;
assign bufo_169_Din_A = 32'd0;
assign bufo_169_Din_B = 32'd0;
assign bufo_169_EN_A = 1'b0;
assign bufo_169_EN_B = 1'b0;
assign bufo_169_Rst_A = ap_rst;
assign bufo_169_Rst_B = ap_rst;
assign bufo_169_WEN_A = 4'd0;
assign bufo_169_WEN_B = 4'd0;
assign bufo_16_Addr_A = bufo_16_Addr_A_orig << 32'd2;
assign bufo_16_Addr_A_orig = 64'd0;
assign bufo_16_Clk_A = ap_clk;
assign bufo_16_Din_A = reg_2580;
assign bufo_16_Rst_A = ap_rst;
assign bufo_170_Addr_A = 32'd0;
assign bufo_170_Addr_B = 32'd0;
assign bufo_170_Clk_A = ap_clk;
assign bufo_170_Clk_B = ap_clk;
assign bufo_170_Din_A = 32'd0;
assign bufo_170_Din_B = 32'd0;
assign bufo_170_EN_A = 1'b0;
assign bufo_170_EN_B = 1'b0;
assign bufo_170_Rst_A = ap_rst;
assign bufo_170_Rst_B = ap_rst;
assign bufo_170_WEN_A = 4'd0;
assign bufo_170_WEN_B = 4'd0;
assign bufo_171_Addr_A = 32'd0;
assign bufo_171_Addr_B = 32'd0;
assign bufo_171_Clk_A = ap_clk;
assign bufo_171_Clk_B = ap_clk;
assign bufo_171_Din_A = 32'd0;
assign bufo_171_Din_B = 32'd0;
assign bufo_171_EN_A = 1'b0;
assign bufo_171_EN_B = 1'b0;
assign bufo_171_Rst_A = ap_rst;
assign bufo_171_Rst_B = ap_rst;
assign bufo_171_WEN_A = 4'd0;
assign bufo_171_WEN_B = 4'd0;
assign bufo_172_Addr_A = 32'd0;
assign bufo_172_Addr_B = 32'd0;
assign bufo_172_Clk_A = ap_clk;
assign bufo_172_Clk_B = ap_clk;
assign bufo_172_Din_A = 32'd0;
assign bufo_172_Din_B = 32'd0;
assign bufo_172_EN_A = 1'b0;
assign bufo_172_EN_B = 1'b0;
assign bufo_172_Rst_A = ap_rst;
assign bufo_172_Rst_B = ap_rst;
assign bufo_172_WEN_A = 4'd0;
assign bufo_172_WEN_B = 4'd0;
assign bufo_173_Addr_A = 32'd0;
assign bufo_173_Addr_B = 32'd0;
assign bufo_173_Clk_A = ap_clk;
assign bufo_173_Clk_B = ap_clk;
assign bufo_173_Din_A = 32'd0;
assign bufo_173_Din_B = 32'd0;
assign bufo_173_EN_A = 1'b0;
assign bufo_173_EN_B = 1'b0;
assign bufo_173_Rst_A = ap_rst;
assign bufo_173_Rst_B = ap_rst;
assign bufo_173_WEN_A = 4'd0;
assign bufo_173_WEN_B = 4'd0;
assign bufo_174_Addr_A = 32'd0;
assign bufo_174_Addr_B = 32'd0;
assign bufo_174_Clk_A = ap_clk;
assign bufo_174_Clk_B = ap_clk;
assign bufo_174_Din_A = 32'd0;
assign bufo_174_Din_B = 32'd0;
assign bufo_174_EN_A = 1'b0;
assign bufo_174_EN_B = 1'b0;
assign bufo_174_Rst_A = ap_rst;
assign bufo_174_Rst_B = ap_rst;
assign bufo_174_WEN_A = 4'd0;
assign bufo_174_WEN_B = 4'd0;
assign bufo_175_Addr_A = 32'd0;
assign bufo_175_Addr_B = 32'd0;
assign bufo_175_Clk_A = ap_clk;
assign bufo_175_Clk_B = ap_clk;
assign bufo_175_Din_A = 32'd0;
assign bufo_175_Din_B = 32'd0;
assign bufo_175_EN_A = 1'b0;
assign bufo_175_EN_B = 1'b0;
assign bufo_175_Rst_A = ap_rst;
assign bufo_175_Rst_B = ap_rst;
assign bufo_175_WEN_A = 4'd0;
assign bufo_175_WEN_B = 4'd0;
assign bufo_176_Addr_A = 32'd0;
assign bufo_176_Addr_B = 32'd0;
assign bufo_176_Clk_A = ap_clk;
assign bufo_176_Clk_B = ap_clk;
assign bufo_176_Din_A = 32'd0;
assign bufo_176_Din_B = 32'd0;
assign bufo_176_EN_A = 1'b0;
assign bufo_176_EN_B = 1'b0;
assign bufo_176_Rst_A = ap_rst;
assign bufo_176_Rst_B = ap_rst;
assign bufo_176_WEN_A = 4'd0;
assign bufo_176_WEN_B = 4'd0;
assign bufo_177_Addr_A = 32'd0;
assign bufo_177_Addr_B = 32'd0;
assign bufo_177_Clk_A = ap_clk;
assign bufo_177_Clk_B = ap_clk;
assign bufo_177_Din_A = 32'd0;
assign bufo_177_Din_B = 32'd0;
assign bufo_177_EN_A = 1'b0;
assign bufo_177_EN_B = 1'b0;
assign bufo_177_Rst_A = ap_rst;
assign bufo_177_Rst_B = ap_rst;
assign bufo_177_WEN_A = 4'd0;
assign bufo_177_WEN_B = 4'd0;
assign bufo_178_Addr_A = 32'd0;
assign bufo_178_Addr_B = 32'd0;
assign bufo_178_Clk_A = ap_clk;
assign bufo_178_Clk_B = ap_clk;
assign bufo_178_Din_A = 32'd0;
assign bufo_178_Din_B = 32'd0;
assign bufo_178_EN_A = 1'b0;
assign bufo_178_EN_B = 1'b0;
assign bufo_178_Rst_A = ap_rst;
assign bufo_178_Rst_B = ap_rst;
assign bufo_178_WEN_A = 4'd0;
assign bufo_178_WEN_B = 4'd0;
assign bufo_179_Addr_A = 32'd0;
assign bufo_179_Addr_B = 32'd0;
assign bufo_179_Clk_A = ap_clk;
assign bufo_179_Clk_B = ap_clk;
assign bufo_179_Din_A = 32'd0;
assign bufo_179_Din_B = 32'd0;
assign bufo_179_EN_A = 1'b0;
assign bufo_179_EN_B = 1'b0;
assign bufo_179_Rst_A = ap_rst;
assign bufo_179_Rst_B = ap_rst;
assign bufo_179_WEN_A = 4'd0;
assign bufo_179_WEN_B = 4'd0;
assign bufo_17_Addr_A = bufo_17_Addr_A_orig << 32'd2;
assign bufo_17_Addr_A_orig = 64'd0;
assign bufo_17_Clk_A = ap_clk;
assign bufo_17_Din_A = reg_2580;
assign bufo_17_Rst_A = ap_rst;
assign bufo_180_Addr_A = 32'd0;
assign bufo_180_Addr_B = 32'd0;
assign bufo_180_Clk_A = ap_clk;
assign bufo_180_Clk_B = ap_clk;
assign bufo_180_Din_A = 32'd0;
assign bufo_180_Din_B = 32'd0;
assign bufo_180_EN_A = 1'b0;
assign bufo_180_EN_B = 1'b0;
assign bufo_180_Rst_A = ap_rst;
assign bufo_180_Rst_B = ap_rst;
assign bufo_180_WEN_A = 4'd0;
assign bufo_180_WEN_B = 4'd0;
assign bufo_181_Addr_A = 32'd0;
assign bufo_181_Addr_B = 32'd0;
assign bufo_181_Clk_A = ap_clk;
assign bufo_181_Clk_B = ap_clk;
assign bufo_181_Din_A = 32'd0;
assign bufo_181_Din_B = 32'd0;
assign bufo_181_EN_A = 1'b0;
assign bufo_181_EN_B = 1'b0;
assign bufo_181_Rst_A = ap_rst;
assign bufo_181_Rst_B = ap_rst;
assign bufo_181_WEN_A = 4'd0;
assign bufo_181_WEN_B = 4'd0;
assign bufo_182_Addr_A = 32'd0;
assign bufo_182_Addr_B = 32'd0;
assign bufo_182_Clk_A = ap_clk;
assign bufo_182_Clk_B = ap_clk;
assign bufo_182_Din_A = 32'd0;
assign bufo_182_Din_B = 32'd0;
assign bufo_182_EN_A = 1'b0;
assign bufo_182_EN_B = 1'b0;
assign bufo_182_Rst_A = ap_rst;
assign bufo_182_Rst_B = ap_rst;
assign bufo_182_WEN_A = 4'd0;
assign bufo_182_WEN_B = 4'd0;
assign bufo_183_Addr_A = 32'd0;
assign bufo_183_Addr_B = 32'd0;
assign bufo_183_Clk_A = ap_clk;
assign bufo_183_Clk_B = ap_clk;
assign bufo_183_Din_A = 32'd0;
assign bufo_183_Din_B = 32'd0;
assign bufo_183_EN_A = 1'b0;
assign bufo_183_EN_B = 1'b0;
assign bufo_183_Rst_A = ap_rst;
assign bufo_183_Rst_B = ap_rst;
assign bufo_183_WEN_A = 4'd0;
assign bufo_183_WEN_B = 4'd0;
assign bufo_184_Addr_A = 32'd0;
assign bufo_184_Addr_B = 32'd0;
assign bufo_184_Clk_A = ap_clk;
assign bufo_184_Clk_B = ap_clk;
assign bufo_184_Din_A = 32'd0;
assign bufo_184_Din_B = 32'd0;
assign bufo_184_EN_A = 1'b0;
assign bufo_184_EN_B = 1'b0;
assign bufo_184_Rst_A = ap_rst;
assign bufo_184_Rst_B = ap_rst;
assign bufo_184_WEN_A = 4'd0;
assign bufo_184_WEN_B = 4'd0;
assign bufo_185_Addr_A = 32'd0;
assign bufo_185_Addr_B = 32'd0;
assign bufo_185_Clk_A = ap_clk;
assign bufo_185_Clk_B = ap_clk;
assign bufo_185_Din_A = 32'd0;
assign bufo_185_Din_B = 32'd0;
assign bufo_185_EN_A = 1'b0;
assign bufo_185_EN_B = 1'b0;
assign bufo_185_Rst_A = ap_rst;
assign bufo_185_Rst_B = ap_rst;
assign bufo_185_WEN_A = 4'd0;
assign bufo_185_WEN_B = 4'd0;
assign bufo_186_Addr_A = 32'd0;
assign bufo_186_Addr_B = 32'd0;
assign bufo_186_Clk_A = ap_clk;
assign bufo_186_Clk_B = ap_clk;
assign bufo_186_Din_A = 32'd0;
assign bufo_186_Din_B = 32'd0;
assign bufo_186_EN_A = 1'b0;
assign bufo_186_EN_B = 1'b0;
assign bufo_186_Rst_A = ap_rst;
assign bufo_186_Rst_B = ap_rst;
assign bufo_186_WEN_A = 4'd0;
assign bufo_186_WEN_B = 4'd0;
assign bufo_187_Addr_A = 32'd0;
assign bufo_187_Addr_B = 32'd0;
assign bufo_187_Clk_A = ap_clk;
assign bufo_187_Clk_B = ap_clk;
assign bufo_187_Din_A = 32'd0;
assign bufo_187_Din_B = 32'd0;
assign bufo_187_EN_A = 1'b0;
assign bufo_187_EN_B = 1'b0;
assign bufo_187_Rst_A = ap_rst;
assign bufo_187_Rst_B = ap_rst;
assign bufo_187_WEN_A = 4'd0;
assign bufo_187_WEN_B = 4'd0;
assign bufo_188_Addr_A = 32'd0;
assign bufo_188_Addr_B = 32'd0;
assign bufo_188_Clk_A = ap_clk;
assign bufo_188_Clk_B = ap_clk;
assign bufo_188_Din_A = 32'd0;
assign bufo_188_Din_B = 32'd0;
assign bufo_188_EN_A = 1'b0;
assign bufo_188_EN_B = 1'b0;
assign bufo_188_Rst_A = ap_rst;
assign bufo_188_Rst_B = ap_rst;
assign bufo_188_WEN_A = 4'd0;
assign bufo_188_WEN_B = 4'd0;
assign bufo_189_Addr_A = 32'd0;
assign bufo_189_Addr_B = 32'd0;
assign bufo_189_Clk_A = ap_clk;
assign bufo_189_Clk_B = ap_clk;
assign bufo_189_Din_A = 32'd0;
assign bufo_189_Din_B = 32'd0;
assign bufo_189_EN_A = 1'b0;
assign bufo_189_EN_B = 1'b0;
assign bufo_189_Rst_A = ap_rst;
assign bufo_189_Rst_B = ap_rst;
assign bufo_189_WEN_A = 4'd0;
assign bufo_189_WEN_B = 4'd0;
assign bufo_18_Addr_A = bufo_18_Addr_A_orig << 32'd2;
assign bufo_18_Addr_A_orig = 64'd0;
assign bufo_18_Clk_A = ap_clk;
assign bufo_18_Din_A = reg_2580;
assign bufo_18_Rst_A = ap_rst;
assign bufo_190_Addr_A = 32'd0;
assign bufo_190_Addr_B = 32'd0;
assign bufo_190_Clk_A = ap_clk;
assign bufo_190_Clk_B = ap_clk;
assign bufo_190_Din_A = 32'd0;
assign bufo_190_Din_B = 32'd0;
assign bufo_190_EN_A = 1'b0;
assign bufo_190_EN_B = 1'b0;
assign bufo_190_Rst_A = ap_rst;
assign bufo_190_Rst_B = ap_rst;
assign bufo_190_WEN_A = 4'd0;
assign bufo_190_WEN_B = 4'd0;
assign bufo_191_Addr_A = 32'd0;
assign bufo_191_Addr_B = 32'd0;
assign bufo_191_Clk_A = ap_clk;
assign bufo_191_Clk_B = ap_clk;
assign bufo_191_Din_A = 32'd0;
assign bufo_191_Din_B = 32'd0;
assign bufo_191_EN_A = 1'b0;
assign bufo_191_EN_B = 1'b0;
assign bufo_191_Rst_A = ap_rst;
assign bufo_191_Rst_B = ap_rst;
assign bufo_191_WEN_A = 4'd0;
assign bufo_191_WEN_B = 4'd0;
assign bufo_192_Addr_A = 32'd0;
assign bufo_192_Addr_B = 32'd0;
assign bufo_192_Clk_A = ap_clk;
assign bufo_192_Clk_B = ap_clk;
assign bufo_192_Din_A = 32'd0;
assign bufo_192_Din_B = 32'd0;
assign bufo_192_EN_A = 1'b0;
assign bufo_192_EN_B = 1'b0;
assign bufo_192_Rst_A = ap_rst;
assign bufo_192_Rst_B = ap_rst;
assign bufo_192_WEN_A = 4'd0;
assign bufo_192_WEN_B = 4'd0;
assign bufo_193_Addr_A = 32'd0;
assign bufo_193_Addr_B = 32'd0;
assign bufo_193_Clk_A = ap_clk;
assign bufo_193_Clk_B = ap_clk;
assign bufo_193_Din_A = 32'd0;
assign bufo_193_Din_B = 32'd0;
assign bufo_193_EN_A = 1'b0;
assign bufo_193_EN_B = 1'b0;
assign bufo_193_Rst_A = ap_rst;
assign bufo_193_Rst_B = ap_rst;
assign bufo_193_WEN_A = 4'd0;
assign bufo_193_WEN_B = 4'd0;
assign bufo_194_Addr_A = 32'd0;
assign bufo_194_Addr_B = 32'd0;
assign bufo_194_Clk_A = ap_clk;
assign bufo_194_Clk_B = ap_clk;
assign bufo_194_Din_A = 32'd0;
assign bufo_194_Din_B = 32'd0;
assign bufo_194_EN_A = 1'b0;
assign bufo_194_EN_B = 1'b0;
assign bufo_194_Rst_A = ap_rst;
assign bufo_194_Rst_B = ap_rst;
assign bufo_194_WEN_A = 4'd0;
assign bufo_194_WEN_B = 4'd0;
assign bufo_195_Addr_A = 32'd0;
assign bufo_195_Addr_B = 32'd0;
assign bufo_195_Clk_A = ap_clk;
assign bufo_195_Clk_B = ap_clk;
assign bufo_195_Din_A = 32'd0;
assign bufo_195_Din_B = 32'd0;
assign bufo_195_EN_A = 1'b0;
assign bufo_195_EN_B = 1'b0;
assign bufo_195_Rst_A = ap_rst;
assign bufo_195_Rst_B = ap_rst;
assign bufo_195_WEN_A = 4'd0;
assign bufo_195_WEN_B = 4'd0;
assign bufo_196_Addr_A = 32'd0;
assign bufo_196_Addr_B = 32'd0;
assign bufo_196_Clk_A = ap_clk;
assign bufo_196_Clk_B = ap_clk;
assign bufo_196_Din_A = 32'd0;
assign bufo_196_Din_B = 32'd0;
assign bufo_196_EN_A = 1'b0;
assign bufo_196_EN_B = 1'b0;
assign bufo_196_Rst_A = ap_rst;
assign bufo_196_Rst_B = ap_rst;
assign bufo_196_WEN_A = 4'd0;
assign bufo_196_WEN_B = 4'd0;
assign bufo_197_Addr_A = 32'd0;
assign bufo_197_Addr_B = 32'd0;
assign bufo_197_Clk_A = ap_clk;
assign bufo_197_Clk_B = ap_clk;
assign bufo_197_Din_A = 32'd0;
assign bufo_197_Din_B = 32'd0;
assign bufo_197_EN_A = 1'b0;
assign bufo_197_EN_B = 1'b0;
assign bufo_197_Rst_A = ap_rst;
assign bufo_197_Rst_B = ap_rst;
assign bufo_197_WEN_A = 4'd0;
assign bufo_197_WEN_B = 4'd0;
assign bufo_198_Addr_A = 32'd0;
assign bufo_198_Addr_B = 32'd0;
assign bufo_198_Clk_A = ap_clk;
assign bufo_198_Clk_B = ap_clk;
assign bufo_198_Din_A = 32'd0;
assign bufo_198_Din_B = 32'd0;
assign bufo_198_EN_A = 1'b0;
assign bufo_198_EN_B = 1'b0;
assign bufo_198_Rst_A = ap_rst;
assign bufo_198_Rst_B = ap_rst;
assign bufo_198_WEN_A = 4'd0;
assign bufo_198_WEN_B = 4'd0;
assign bufo_199_Addr_A = 32'd0;
assign bufo_199_Addr_B = 32'd0;
assign bufo_199_Clk_A = ap_clk;
assign bufo_199_Clk_B = ap_clk;
assign bufo_199_Din_A = 32'd0;
assign bufo_199_Din_B = 32'd0;
assign bufo_199_EN_A = 1'b0;
assign bufo_199_EN_B = 1'b0;
assign bufo_199_Rst_A = ap_rst;
assign bufo_199_Rst_B = ap_rst;
assign bufo_199_WEN_A = 4'd0;
assign bufo_199_WEN_B = 4'd0;
assign bufo_19_Addr_A = bufo_19_Addr_A_orig << 32'd2;
assign bufo_19_Addr_A_orig = 64'd0;
assign bufo_19_Clk_A = ap_clk;
assign bufo_19_Din_A = reg_2580;
assign bufo_19_Rst_A = ap_rst;
assign bufo_1_Addr_A = bufo_1_Addr_A_orig << 32'd2;
assign bufo_1_Addr_A_orig = 64'd0;
assign bufo_1_Clk_A = ap_clk;
assign bufo_1_Din_A = reg_2580;
assign bufo_1_Rst_A = ap_rst;
assign bufo_20_Addr_A = bufo_20_Addr_A_orig << 32'd2;
assign bufo_20_Addr_A_orig = 64'd0;
assign bufo_20_Clk_A = ap_clk;
assign bufo_20_Din_A = reg_2580;
assign bufo_20_Rst_A = ap_rst;
assign bufo_21_Addr_A = bufo_21_Addr_A_orig << 32'd2;
assign bufo_21_Addr_A_orig = 64'd0;
assign bufo_21_Clk_A = ap_clk;
assign bufo_21_Din_A = reg_2580;
assign bufo_21_Rst_A = ap_rst;
assign bufo_22_Addr_A = bufo_22_Addr_A_orig << 32'd2;
assign bufo_22_Addr_A_orig = 64'd0;
assign bufo_22_Clk_A = ap_clk;
assign bufo_22_Din_A = reg_2580;
assign bufo_22_Rst_A = ap_rst;
assign bufo_23_Addr_A = bufo_23_Addr_A_orig << 32'd2;
assign bufo_23_Addr_A_orig = 64'd0;
assign bufo_23_Clk_A = ap_clk;
assign bufo_23_Din_A = reg_2580;
assign bufo_23_Rst_A = ap_rst;
assign bufo_24_Addr_A = bufo_24_Addr_A_orig << 32'd2;
assign bufo_24_Addr_A_orig = 64'd0;
assign bufo_24_Clk_A = ap_clk;
assign bufo_24_Din_A = reg_2580;
assign bufo_24_Rst_A = ap_rst;
assign bufo_25_Addr_A = bufo_25_Addr_A_orig << 32'd2;
assign bufo_25_Addr_A_orig = 64'd0;
assign bufo_25_Clk_A = ap_clk;
assign bufo_25_Din_A = reg_2580;
assign bufo_25_Rst_A = ap_rst;
assign bufo_26_Addr_A = bufo_26_Addr_A_orig << 32'd2;
assign bufo_26_Addr_A_orig = 64'd0;
assign bufo_26_Clk_A = ap_clk;
assign bufo_26_Din_A = reg_2580;
assign bufo_26_Rst_A = ap_rst;
assign bufo_27_Addr_A = bufo_27_Addr_A_orig << 32'd2;
assign bufo_27_Addr_A_orig = 64'd0;
assign bufo_27_Clk_A = ap_clk;
assign bufo_27_Din_A = reg_2580;
assign bufo_27_Rst_A = ap_rst;
assign bufo_28_Addr_A = bufo_28_Addr_A_orig << 32'd2;
assign bufo_28_Addr_A_orig = 64'd0;
assign bufo_28_Clk_A = ap_clk;
assign bufo_28_Din_A = reg_2580;
assign bufo_28_Rst_A = ap_rst;
assign bufo_29_Addr_A = bufo_29_Addr_A_orig << 32'd2;
assign bufo_29_Addr_A_orig = 64'd0;
assign bufo_29_Clk_A = ap_clk;
assign bufo_29_Din_A = reg_2580;
assign bufo_29_Rst_A = ap_rst;
assign bufo_2_Addr_A = bufo_2_Addr_A_orig << 32'd2;
assign bufo_2_Addr_A_orig = 64'd0;
assign bufo_2_Clk_A = ap_clk;
assign bufo_2_Din_A = reg_2580;
assign bufo_2_Rst_A = ap_rst;
assign bufo_30_Addr_A = bufo_30_Addr_A_orig << 32'd2;
assign bufo_30_Addr_A_orig = 64'd0;
assign bufo_30_Clk_A = ap_clk;
assign bufo_30_Din_A = reg_2580;
assign bufo_30_Rst_A = ap_rst;
assign bufo_31_Addr_A = bufo_31_Addr_A_orig << 32'd2;
assign bufo_31_Addr_A_orig = 64'd0;
assign bufo_31_Clk_A = ap_clk;
assign bufo_31_Din_A = reg_2580;
assign bufo_31_Rst_A = ap_rst;
assign bufo_32_Addr_A = bufo_32_Addr_A_orig << 32'd2;
assign bufo_32_Addr_A_orig = 64'd0;
assign bufo_32_Clk_A = ap_clk;
assign bufo_32_Din_A = reg_2580;
assign bufo_32_Rst_A = ap_rst;
assign bufo_33_Addr_A = bufo_33_Addr_A_orig << 32'd2;
assign bufo_33_Addr_A_orig = 64'd0;
assign bufo_33_Clk_A = ap_clk;
assign bufo_33_Din_A = reg_2580;
assign bufo_33_Rst_A = ap_rst;
assign bufo_34_Addr_A = bufo_34_Addr_A_orig << 32'd2;
assign bufo_34_Addr_A_orig = 64'd0;
assign bufo_34_Clk_A = ap_clk;
assign bufo_34_Din_A = reg_2580;
assign bufo_34_Rst_A = ap_rst;
assign bufo_35_Addr_A = bufo_35_Addr_A_orig << 32'd2;
assign bufo_35_Addr_A_orig = 64'd0;
assign bufo_35_Clk_A = ap_clk;
assign bufo_35_Din_A = reg_2580;
assign bufo_35_Rst_A = ap_rst;
assign bufo_36_Addr_A = bufo_36_Addr_A_orig << 32'd2;
assign bufo_36_Addr_A_orig = 64'd0;
assign bufo_36_Clk_A = ap_clk;
assign bufo_36_Din_A = reg_2580;
assign bufo_36_Rst_A = ap_rst;
assign bufo_37_Addr_A = bufo_37_Addr_A_orig << 32'd2;
assign bufo_37_Addr_A_orig = 64'd0;
assign bufo_37_Clk_A = ap_clk;
assign bufo_37_Din_A = reg_2580;
assign bufo_37_Rst_A = ap_rst;
assign bufo_38_Addr_A = bufo_38_Addr_A_orig << 32'd2;
assign bufo_38_Addr_A_orig = 64'd0;
assign bufo_38_Clk_A = ap_clk;
assign bufo_38_Din_A = reg_2580;
assign bufo_38_Rst_A = ap_rst;
assign bufo_39_Addr_A = bufo_39_Addr_A_orig << 32'd2;
assign bufo_39_Addr_A_orig = 64'd0;
assign bufo_39_Clk_A = ap_clk;
assign bufo_39_Din_A = reg_2580;
assign bufo_39_Rst_A = ap_rst;
assign bufo_3_Addr_A = bufo_3_Addr_A_orig << 32'd2;
assign bufo_3_Addr_A_orig = 64'd0;
assign bufo_3_Clk_A = ap_clk;
assign bufo_3_Din_A = reg_2580;
assign bufo_3_Rst_A = ap_rst;
assign bufo_40_Addr_A = bufo_40_Addr_A_orig << 32'd2;
assign bufo_40_Addr_A_orig = 64'd0;
assign bufo_40_Clk_A = ap_clk;
assign bufo_40_Din_A = reg_2580;
assign bufo_40_Rst_A = ap_rst;
assign bufo_41_Addr_A = bufo_41_Addr_A_orig << 32'd2;
assign bufo_41_Addr_A_orig = 64'd0;
assign bufo_41_Clk_A = ap_clk;
assign bufo_41_Din_A = reg_2580;
assign bufo_41_Rst_A = ap_rst;
assign bufo_42_Addr_A = bufo_42_Addr_A_orig << 32'd2;
assign bufo_42_Addr_A_orig = 64'd0;
assign bufo_42_Clk_A = ap_clk;
assign bufo_42_Din_A = reg_2580;
assign bufo_42_Rst_A = ap_rst;
assign bufo_43_Addr_A = bufo_43_Addr_A_orig << 32'd2;
assign bufo_43_Addr_A_orig = 64'd0;
assign bufo_43_Clk_A = ap_clk;
assign bufo_43_Din_A = reg_2580;
assign bufo_43_Rst_A = ap_rst;
assign bufo_44_Addr_A = bufo_44_Addr_A_orig << 32'd2;
assign bufo_44_Addr_A_orig = 64'd0;
assign bufo_44_Clk_A = ap_clk;
assign bufo_44_Din_A = reg_2580;
assign bufo_44_Rst_A = ap_rst;
assign bufo_45_Addr_A = bufo_45_Addr_A_orig << 32'd2;
assign bufo_45_Addr_A_orig = 64'd0;
assign bufo_45_Clk_A = ap_clk;
assign bufo_45_Din_A = reg_2580;
assign bufo_45_Rst_A = ap_rst;
assign bufo_46_Addr_A = bufo_46_Addr_A_orig << 32'd2;
assign bufo_46_Addr_A_orig = 64'd0;
assign bufo_46_Clk_A = ap_clk;
assign bufo_46_Din_A = reg_2580;
assign bufo_46_Rst_A = ap_rst;
assign bufo_47_Addr_A = bufo_47_Addr_A_orig << 32'd2;
assign bufo_47_Addr_A_orig = 64'd0;
assign bufo_47_Clk_A = ap_clk;
assign bufo_47_Din_A = reg_2580;
assign bufo_47_Rst_A = ap_rst;
assign bufo_48_Addr_A = bufo_48_Addr_A_orig << 32'd2;
assign bufo_48_Addr_A_orig = 64'd0;
assign bufo_48_Clk_A = ap_clk;
assign bufo_48_Din_A = reg_2580;
assign bufo_48_Rst_A = ap_rst;
assign bufo_49_Addr_A = bufo_49_Addr_A_orig << 32'd2;
assign bufo_49_Addr_A_orig = 64'd0;
assign bufo_49_Clk_A = ap_clk;
assign bufo_49_Din_A = reg_2580;
assign bufo_49_Rst_A = ap_rst;
assign bufo_4_Addr_A = bufo_4_Addr_A_orig << 32'd2;
assign bufo_4_Addr_A_orig = 64'd0;
assign bufo_4_Clk_A = ap_clk;
assign bufo_4_Din_A = reg_2580;
assign bufo_4_Rst_A = ap_rst;
assign bufo_50_Addr_A = bufo_50_Addr_A_orig << 32'd2;
assign bufo_50_Addr_A_orig = 64'd0;
assign bufo_50_Clk_A = ap_clk;
assign bufo_50_Din_A = reg_2580;
assign bufo_50_Rst_A = ap_rst;
assign bufo_51_Addr_A = bufo_51_Addr_A_orig << 32'd2;
assign bufo_51_Addr_A_orig = 64'd0;
assign bufo_51_Clk_A = ap_clk;
assign bufo_51_Din_A = reg_2580;
assign bufo_51_Rst_A = ap_rst;
assign bufo_52_Addr_A = bufo_52_Addr_A_orig << 32'd2;
assign bufo_52_Addr_A_orig = 64'd0;
assign bufo_52_Clk_A = ap_clk;
assign bufo_52_Din_A = reg_2580;
assign bufo_52_Rst_A = ap_rst;
assign bufo_53_Addr_A = bufo_53_Addr_A_orig << 32'd2;
assign bufo_53_Addr_A_orig = 64'd0;
assign bufo_53_Clk_A = ap_clk;
assign bufo_53_Din_A = reg_2580;
assign bufo_53_Rst_A = ap_rst;
assign bufo_54_Addr_A = bufo_54_Addr_A_orig << 32'd2;
assign bufo_54_Addr_A_orig = 64'd0;
assign bufo_54_Clk_A = ap_clk;
assign bufo_54_Din_A = reg_2580;
assign bufo_54_Rst_A = ap_rst;
assign bufo_55_Addr_A = bufo_55_Addr_A_orig << 32'd2;
assign bufo_55_Addr_A_orig = 64'd0;
assign bufo_55_Clk_A = ap_clk;
assign bufo_55_Din_A = reg_2580;
assign bufo_55_Rst_A = ap_rst;
assign bufo_56_Addr_A = bufo_56_Addr_A_orig << 32'd2;
assign bufo_56_Addr_A_orig = 64'd0;
assign bufo_56_Clk_A = ap_clk;
assign bufo_56_Din_A = reg_2580;
assign bufo_56_Rst_A = ap_rst;
assign bufo_57_Addr_A = bufo_57_Addr_A_orig << 32'd2;
assign bufo_57_Addr_A_orig = 64'd0;
assign bufo_57_Clk_A = ap_clk;
assign bufo_57_Din_A = reg_2580;
assign bufo_57_Rst_A = ap_rst;
assign bufo_58_Addr_A = bufo_58_Addr_A_orig << 32'd2;
assign bufo_58_Addr_A_orig = 64'd0;
assign bufo_58_Clk_A = ap_clk;
assign bufo_58_Din_A = reg_2580;
assign bufo_58_Rst_A = ap_rst;
assign bufo_59_Addr_A = bufo_59_Addr_A_orig << 32'd2;
assign bufo_59_Addr_A_orig = 64'd0;
assign bufo_59_Clk_A = ap_clk;
assign bufo_59_Din_A = reg_2580;
assign bufo_59_Rst_A = ap_rst;
assign bufo_5_Addr_A = bufo_5_Addr_A_orig << 32'd2;
assign bufo_5_Addr_A_orig = 64'd0;
assign bufo_5_Clk_A = ap_clk;
assign bufo_5_Din_A = reg_2580;
assign bufo_5_Rst_A = ap_rst;
assign bufo_60_Addr_A = bufo_60_Addr_A_orig << 32'd2;
assign bufo_60_Addr_A_orig = 64'd0;
assign bufo_60_Clk_A = ap_clk;
assign bufo_60_Din_A = reg_2580;
assign bufo_60_Rst_A = ap_rst;
assign bufo_61_Addr_A = bufo_61_Addr_A_orig << 32'd2;
assign bufo_61_Addr_A_orig = 64'd0;
assign bufo_61_Clk_A = ap_clk;
assign bufo_61_Din_A = reg_2580;
assign bufo_61_Rst_A = ap_rst;
assign bufo_62_Addr_A = bufo_62_Addr_A_orig << 32'd2;
assign bufo_62_Addr_A_orig = 64'd0;
assign bufo_62_Clk_A = ap_clk;
assign bufo_62_Din_A = reg_2580;
assign bufo_62_Rst_A = ap_rst;
assign bufo_63_Addr_A = bufo_63_Addr_A_orig << 32'd2;
assign bufo_63_Addr_A_orig = 64'd0;
assign bufo_63_Clk_A = ap_clk;
assign bufo_63_Din_A = reg_2580;
assign bufo_63_Rst_A = ap_rst;
assign bufo_64_Addr_A = bufo_64_Addr_A_orig << 32'd2;
assign bufo_64_Addr_A_orig = 64'd0;
assign bufo_64_Clk_A = ap_clk;
assign bufo_64_Din_A = reg_2580;
assign bufo_64_Rst_A = ap_rst;
assign bufo_65_Addr_A = bufo_65_Addr_A_orig << 32'd2;
assign bufo_65_Addr_A_orig = 64'd0;
assign bufo_65_Clk_A = ap_clk;
assign bufo_65_Din_A = reg_2580;
assign bufo_65_Rst_A = ap_rst;
assign bufo_66_Addr_A = bufo_66_Addr_A_orig << 32'd2;
assign bufo_66_Addr_A_orig = 64'd0;
assign bufo_66_Clk_A = ap_clk;
assign bufo_66_Din_A = reg_2580;
assign bufo_66_Rst_A = ap_rst;
assign bufo_67_Addr_A = bufo_67_Addr_A_orig << 32'd2;
assign bufo_67_Addr_A_orig = 64'd0;
assign bufo_67_Clk_A = ap_clk;
assign bufo_67_Din_A = reg_2580;
assign bufo_67_Rst_A = ap_rst;
assign bufo_68_Addr_A = bufo_68_Addr_A_orig << 32'd2;
assign bufo_68_Addr_A_orig = 64'd0;
assign bufo_68_Clk_A = ap_clk;
assign bufo_68_Din_A = reg_2580;
assign bufo_68_Rst_A = ap_rst;
assign bufo_69_Addr_A = bufo_69_Addr_A_orig << 32'd2;
assign bufo_69_Addr_A_orig = 64'd0;
assign bufo_69_Clk_A = ap_clk;
assign bufo_69_Din_A = reg_2580;
assign bufo_69_Rst_A = ap_rst;
assign bufo_6_Addr_A = bufo_6_Addr_A_orig << 32'd2;
assign bufo_6_Addr_A_orig = 64'd0;
assign bufo_6_Clk_A = ap_clk;
assign bufo_6_Din_A = reg_2580;
assign bufo_6_Rst_A = ap_rst;
assign bufo_70_Addr_A = bufo_70_Addr_A_orig << 32'd2;
assign bufo_70_Addr_A_orig = 64'd0;
assign bufo_70_Clk_A = ap_clk;
assign bufo_70_Din_A = reg_2580;
assign bufo_70_Rst_A = ap_rst;
assign bufo_71_Addr_A = bufo_71_Addr_A_orig << 32'd2;
assign bufo_71_Addr_A_orig = 64'd0;
assign bufo_71_Clk_A = ap_clk;
assign bufo_71_Din_A = reg_2580;
assign bufo_71_Rst_A = ap_rst;
assign bufo_72_Addr_A = bufo_72_Addr_A_orig << 32'd2;
assign bufo_72_Addr_A_orig = 64'd0;
assign bufo_72_Clk_A = ap_clk;
assign bufo_72_Din_A = reg_2580;
assign bufo_72_Rst_A = ap_rst;
assign bufo_73_Addr_A = bufo_73_Addr_A_orig << 32'd2;
assign bufo_73_Addr_A_orig = 64'd0;
assign bufo_73_Clk_A = ap_clk;
assign bufo_73_Din_A = reg_2580;
assign bufo_73_Rst_A = ap_rst;
assign bufo_74_Addr_A = bufo_74_Addr_A_orig << 32'd2;
assign bufo_74_Addr_A_orig = 64'd0;
assign bufo_74_Clk_A = ap_clk;
assign bufo_74_Din_A = reg_2580;
assign bufo_74_Rst_A = ap_rst;
assign bufo_75_Addr_A = bufo_75_Addr_A_orig << 32'd2;
assign bufo_75_Addr_A_orig = 64'd0;
assign bufo_75_Clk_A = ap_clk;
assign bufo_75_Din_A = reg_2580;
assign bufo_75_Rst_A = ap_rst;
assign bufo_76_Addr_A = bufo_76_Addr_A_orig << 32'd2;
assign bufo_76_Addr_A_orig = 64'd0;
assign bufo_76_Clk_A = ap_clk;
assign bufo_76_Din_A = reg_2580;
assign bufo_76_Rst_A = ap_rst;
assign bufo_77_Addr_A = bufo_77_Addr_A_orig << 32'd2;
assign bufo_77_Addr_A_orig = 64'd0;
assign bufo_77_Clk_A = ap_clk;
assign bufo_77_Din_A = reg_2580;
assign bufo_77_Rst_A = ap_rst;
assign bufo_78_Addr_A = bufo_78_Addr_A_orig << 32'd2;
assign bufo_78_Addr_A_orig = 64'd0;
assign bufo_78_Clk_A = ap_clk;
assign bufo_78_Din_A = reg_2580;
assign bufo_78_Rst_A = ap_rst;
assign bufo_79_Addr_A = bufo_79_Addr_A_orig << 32'd2;
assign bufo_79_Addr_A_orig = 64'd0;
assign bufo_79_Clk_A = ap_clk;
assign bufo_79_Din_A = reg_2580;
assign bufo_79_Rst_A = ap_rst;
assign bufo_7_Addr_A = bufo_7_Addr_A_orig << 32'd2;
assign bufo_7_Addr_A_orig = 64'd0;
assign bufo_7_Clk_A = ap_clk;
assign bufo_7_Din_A = reg_2580;
assign bufo_7_Rst_A = ap_rst;
assign bufo_80_Addr_A = bufo_80_Addr_A_orig << 32'd2;
assign bufo_80_Addr_A_orig = 64'd0;
assign bufo_80_Clk_A = ap_clk;
assign bufo_80_Din_A = reg_2580;
assign bufo_80_Rst_A = ap_rst;
assign bufo_81_Addr_A = bufo_81_Addr_A_orig << 32'd2;
assign bufo_81_Addr_A_orig = 64'd0;
assign bufo_81_Clk_A = ap_clk;
assign bufo_81_Din_A = reg_2580;
assign bufo_81_Rst_A = ap_rst;
assign bufo_82_Addr_A = bufo_82_Addr_A_orig << 32'd2;
assign bufo_82_Addr_A_orig = 64'd0;
assign bufo_82_Clk_A = ap_clk;
assign bufo_82_Din_A = reg_2580;
assign bufo_82_Rst_A = ap_rst;
assign bufo_83_Addr_A = bufo_83_Addr_A_orig << 32'd2;
assign bufo_83_Addr_A_orig = 64'd0;
assign bufo_83_Clk_A = ap_clk;
assign bufo_83_Din_A = reg_2580;
assign bufo_83_Rst_A = ap_rst;
assign bufo_84_Addr_A = bufo_84_Addr_A_orig << 32'd2;
assign bufo_84_Addr_A_orig = 64'd0;
assign bufo_84_Clk_A = ap_clk;
assign bufo_84_Din_A = reg_2580;
assign bufo_84_Rst_A = ap_rst;
assign bufo_85_Addr_A = bufo_85_Addr_A_orig << 32'd2;
assign bufo_85_Addr_A_orig = 64'd0;
assign bufo_85_Clk_A = ap_clk;
assign bufo_85_Din_A = reg_2580;
assign bufo_85_Rst_A = ap_rst;
assign bufo_86_Addr_A = bufo_86_Addr_A_orig << 32'd2;
assign bufo_86_Addr_A_orig = 64'd0;
assign bufo_86_Clk_A = ap_clk;
assign bufo_86_Din_A = reg_2580;
assign bufo_86_Rst_A = ap_rst;
assign bufo_87_Addr_A = bufo_87_Addr_A_orig << 32'd2;
assign bufo_87_Addr_A_orig = 64'd0;
assign bufo_87_Clk_A = ap_clk;
assign bufo_87_Din_A = reg_2580;
assign bufo_87_Rst_A = ap_rst;
assign bufo_88_Addr_A = bufo_88_Addr_A_orig << 32'd2;
assign bufo_88_Addr_A_orig = 64'd0;
assign bufo_88_Clk_A = ap_clk;
assign bufo_88_Din_A = reg_2580;
assign bufo_88_Rst_A = ap_rst;
assign bufo_89_Addr_A = bufo_89_Addr_A_orig << 32'd2;
assign bufo_89_Addr_A_orig = 64'd0;
assign bufo_89_Clk_A = ap_clk;
assign bufo_89_Din_A = reg_2580;
assign bufo_89_Rst_A = ap_rst;
assign bufo_8_Addr_A = bufo_8_Addr_A_orig << 32'd2;
assign bufo_8_Addr_A_orig = 64'd0;
assign bufo_8_Clk_A = ap_clk;
assign bufo_8_Din_A = reg_2580;
assign bufo_8_Rst_A = ap_rst;
assign bufo_90_Addr_A = bufo_90_Addr_A_orig << 32'd2;
assign bufo_90_Addr_A_orig = 64'd0;
assign bufo_90_Clk_A = ap_clk;
assign bufo_90_Din_A = reg_2580;
assign bufo_90_Rst_A = ap_rst;
assign bufo_91_Addr_A = bufo_91_Addr_A_orig << 32'd2;
assign bufo_91_Addr_A_orig = 64'd0;
assign bufo_91_Clk_A = ap_clk;
assign bufo_91_Din_A = reg_2580;
assign bufo_91_Rst_A = ap_rst;
assign bufo_92_Addr_A = bufo_92_Addr_A_orig << 32'd2;
assign bufo_92_Addr_A_orig = 64'd0;
assign bufo_92_Clk_A = ap_clk;
assign bufo_92_Din_A = reg_2580;
assign bufo_92_Rst_A = ap_rst;
assign bufo_93_Addr_A = bufo_93_Addr_A_orig << 32'd2;
assign bufo_93_Addr_A_orig = 64'd0;
assign bufo_93_Clk_A = ap_clk;
assign bufo_93_Din_A = reg_2580;
assign bufo_93_Rst_A = ap_rst;
assign bufo_94_Addr_A = bufo_94_Addr_A_orig << 32'd2;
assign bufo_94_Addr_A_orig = 64'd0;
assign bufo_94_Clk_A = ap_clk;
assign bufo_94_Din_A = reg_2580;
assign bufo_94_Rst_A = ap_rst;
assign bufo_95_Addr_A = bufo_95_Addr_A_orig << 32'd2;
assign bufo_95_Addr_A_orig = 64'd0;
assign bufo_95_Clk_A = ap_clk;
assign bufo_95_Din_A = reg_2580;
assign bufo_95_Rst_A = ap_rst;
assign bufo_96_Addr_A = bufo_96_Addr_A_orig << 32'd2;
assign bufo_96_Addr_A_orig = 64'd0;
assign bufo_96_Clk_A = ap_clk;
assign bufo_96_Din_A = reg_2580;
assign bufo_96_Rst_A = ap_rst;
assign bufo_97_Addr_A = bufo_97_Addr_A_orig << 32'd2;
assign bufo_97_Addr_A_orig = 64'd0;
assign bufo_97_Clk_A = ap_clk;
assign bufo_97_Din_A = reg_2580;
assign bufo_97_Rst_A = ap_rst;
assign bufo_98_Addr_A = bufo_98_Addr_A_orig << 32'd2;
assign bufo_98_Addr_A_orig = 64'd0;
assign bufo_98_Clk_A = ap_clk;
assign bufo_98_Din_A = reg_2580;
assign bufo_98_Rst_A = ap_rst;
assign bufo_99_Addr_A = bufo_99_Addr_A_orig << 32'd2;
assign bufo_99_Addr_A_orig = 64'd0;
assign bufo_99_Clk_A = ap_clk;
assign bufo_99_Din_A = reg_2580;
assign bufo_99_Rst_A = ap_rst;
assign bufo_9_Addr_A = bufo_9_Addr_A_orig << 32'd2;
assign bufo_9_Addr_A_orig = 64'd0;
assign bufo_9_Clk_A = ap_clk;
assign bufo_9_Din_A = reg_2580;
assign bufo_9_Rst_A = ap_rst;
assign bufw_Addr_A = bufw_Addr_A_orig << 32'd4;
assign bufw_Addr_A_orig = phi_mul_reg_2272;
assign bufw_Clk_A = ap_clk;
assign bufw_Din_A = 128'd0;
assign bufw_Rst_A = ap_rst;
assign bufw_WEN_A = 16'd0;
assign grp_fu_2564_p0 = tmp_reg_3481;
assign grp_fu_2564_p1 = tmp_1_reg_3486;
assign grp_fu_2568_p0 = tmp_6_reg_3491;
assign grp_fu_2568_p1 = tmp_8_reg_3496;
assign grp_fu_2572_p0 = tmp_4_reg_3501;
assign grp_fu_2572_p1 = tmp_11_reg_3506;
assign grp_fu_2576_p0 = tmp_13_reg_3511;
assign grp_fu_2576_p1 = tmp_15_reg_3516;
assign next_mul_fu_2714_p2 = (64'd25 + phi_mul_reg_2272);
assign tmp_1_fu_2724_p1 = bufi_Dout_A[31:0];
assign tmp_fu_2720_p1 = bufw_Dout_A[31:0];
assign to_b_V_fu_2820_p2 = (7'd1 + p_s_reg_2284);
endmodule //convolve_kernel
|
`ifndef SDIO_DEVICE_CIA_DEFINES
`define SDIO_DEVICE_CIA_DEFINES
`include "sdio_defines.v"
//Addresses
`define CCCR_SDIO_REV_ADDR 18'h000
`define SD_SPEC_ADDR 18'h001
`define IO_FUNC_ENABLE_ADDR 18'h002
`define IO_FUNC_READY_ADDR 18'h003
`define INT_ENABLE_ADDR 18'h004
`define INT_PENDING_ADDR 18'h005
`define IO_ABORT_ADDR 18'h006
`define BUS_IF_CONTROL_ADDR 18'h007
`define CARD_COMPAT_ADDR 18'h008
`define CARD_CIS_LOW_ADDR 18'h00A
`define CARD_CIS_MID_ADDR 18'h00A
`define CARD_CIS_HIGH_ADDR 18'h00B
`define BUS_SUSPEND_ADDR 18'h00C
`define FUNC_SELECT_ADDR 18'h00D
`define EXEC_SELECT_ADDR 18'h00E
`define READY_SELECT_ADDR 18'h00F
`define FN0_BLOCK_SIZE_0_ADDR 18'h010
`define FN0_BLOCK_SIZE_1_ADDR 18'h011
`define POWER_CONTROL_ADDR 18'h012
`define BUS_SPD_SELECT_ADDR 18'h013
`define UHS_I_SUPPORT_ADDR 18'h014
`define DRIVE_STRENGTH_ADDR 18'h015
`define INTERRUPT_EXT_ADDR 18'h016
//Values
`define CCCR_FORMAT 4'h3 /* CCCR/FBR Version 3.0 (is this right?) */
`define SDIO_VERSION 4'h4 /* SDIO Version 3.0 (is this right?) */
`define SD_PHY_VERSION 4'h3 /* SD PHY Version 3.01 (is this right?) */
`define ECSI 1'b0 /* Enable Continuous SPI Interrupt */
`define SCSI 1'b0 /* Support Continuous SPI Interrupt */
`define SDC 1'b1 /* Support Command 52 While Data Transfer In progress */
`define SMB 1'b1 /* Support Multiple Block Transfer CMD 53 */
`define SRW 1'b1 /* Support Read Wait */
`define SBS 1'b1 /* Support Suspend/Resume */
`define S4MI 1'b1 /* Support Interrupts ine 4-bit data transfer mode */
`define LSC 1'b0 /* Card is a low speed card only */
`define S4BLS 1'b0 /* Support 4-bit mode in low speed mode */
`define SMPC 1'b0 /* Master Power Control Support (don't let the process control power)*/
`define EMPC 1'b0 /* Enable Power Control, This always returns 0, host has no control */
`define TPC 3'b000 /* No Total Power Control */
`define SHS 1'b1 /* Support High Speed */
`define SSDR50 1'b0 /* Support SDR50 */
`define SSDR104 1'b0 /* Support SDR104 */
`define SDDR50 1'b1 /* Support DDR50 */
`define SDTA 1'b0 /* Support Driver Type A */
`define SDTC 1'b0 /* Support Driver Type C */
`define SDTD 1'b0 /* Support Driver Type D */
`define SAI 1'b1 /* Support Asynchronous Interrupts */
`define D1_BIT_MODE 2'b00
`define D4_BIT_MODE 2'b10
`define D8_BIT_MODE 2'b11
`define DRIVER_TYPE_B 2'b00
`define DRIVER_TYPE_A 2'b01
`define DRIVER_TYPE_C 2'b10
`define DRIVER_TYPE_D 2'b11
`define SDR12 3'b000 /* Single Data Rate 12 MHz */
`define SDR25 3'b001 /* Single Data Rate 25 MHz */
`define SDR50 3'b010 /* Single Data Rate 50 MHz */
`define SDR104 3'b011 /* Single Data Rate 104 MHz */
`define DDR50 3'b100 /* Double Data Rate 50MHz */
//Address of Functions
`define CCCR_FUNCTION_START_ADDR (18'h00000)
`define CCCR_FUNCTION_END_ADDR (18'h000FF)
`define CCCR_INDEX 0
`define FUNCTION_1_START_ADDR (18'h00100)
`define FUNCTION_1_END_ADDR (18'h001FF)
`define F1_INDEX 1
`define FUNCTION_2_START_ADDR (18'h00200)
`define FUNCTION_2_END_ADDR (18'h002FF)
`define F2_INDEX 2
`define FUNCTION_3_START_ADDR (18'h00300)
`define FUNCTION_3_END_ADDR (18'h003FF)
`define F3_INDEX 3
`define FUNCTION_4_START_ADDR (18'h00400)
`define FUNCTION_4_END_ADDR (18'h004FF)
`define F4_INDEX 4
`define FUNCTION_5_START_ADDR (18'h00500)
`define FUNCTION_5_END_ADDR (18'h005FF)
`define F5_INDEX 5
`define FUNCTION_6_START_ADDR (18'h00600)
`define FUNCTION_6_END_ADDR (18'h006FF)
`define F6_INDEX 6
`define FUNCTION_7_START_ADDR (18'h00700)
`define FUNCTION_7_END_ADDR (18'h007FF)
`define F7_INDEX 7
`define MAIN_CIS_START_ADDR (18'h01000)
`define MAIN_CIS_END_ADDR (18'h17FFF)
`define MAIN_CIS_INDEX 8
`define NO_SELECT_INDEX 9
`endif /* SDIO_DEVICE_CIA_DEFINES */
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: add_float_float_float.v
// /___/ /\ Timestamp: Wed Jan 27 15:36:55 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/add_float_float_float.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/add_float_float_float.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/add_float_float_float.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/add_float_float_float.v
// # of Modules : 1
// Design Name : add_float_float_float
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module add_float32_float32_float32 (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [63 : 0] inp;
output [31 : 0] out;
wire clk;
assign clk=CLK;
wire [31:0] a;
wire [31:0] b;
wire [31:0] result;
assign a = inp[31:0];
assign b = inp[63:32];
assign out = result;
wire \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire sig00000207;
wire sig00000208;
wire sig00000209;
wire sig0000020a;
wire sig0000020b;
wire sig0000020c;
wire sig0000020d;
wire sig0000020e;
wire sig0000020f;
wire sig00000210;
wire sig00000211;
wire sig00000212;
wire sig00000213;
wire sig00000214;
wire sig00000215;
wire sig00000216;
wire sig00000217;
wire sig00000218;
wire sig00000219;
wire sig0000021a;
wire sig0000021b;
wire sig0000021c;
wire sig0000021d;
wire sig0000021e;
wire sig0000021f;
wire sig00000220;
wire sig00000221;
wire sig00000222;
wire sig00000223;
wire sig00000224;
wire sig00000225;
wire sig00000226;
wire sig00000227;
wire sig00000228;
wire sig00000229;
wire sig0000022a;
wire sig0000022b;
wire sig0000022c;
wire sig0000022d;
wire sig0000022e;
wire sig0000022f;
wire sig00000230;
wire sig00000231;
wire sig00000232;
wire sig00000233;
wire sig00000234;
wire sig00000235;
wire sig00000236;
wire sig00000237;
wire sig00000238;
wire sig00000239;
wire sig0000023a;
wire sig0000023b;
wire sig0000023c;
wire sig0000023d;
wire sig0000023e;
wire sig0000023f;
wire sig00000240;
wire sig00000241;
wire sig00000242;
wire sig00000243;
wire sig00000244;
wire sig00000245;
wire sig00000246;
wire sig00000247;
wire sig00000248;
wire sig00000249;
wire sig0000024a;
wire sig0000024b;
wire sig0000024c;
wire sig0000024d;
wire sig0000024e;
wire sig0000024f;
wire sig00000250;
wire sig00000251;
wire sig00000252;
wire sig00000253;
wire sig00000254;
wire sig00000255;
wire sig00000256;
wire sig00000257;
wire sig00000258;
wire sig00000259;
wire sig0000025a;
wire sig0000025b;
wire sig0000025c;
wire sig0000025d;
wire sig0000025e;
wire sig0000025f;
wire sig00000260;
wire sig00000261;
wire sig00000262;
wire sig00000263;
wire sig00000264;
wire sig00000265;
wire sig00000266;
wire sig00000267;
wire sig00000268;
wire sig00000269;
wire sig0000026a;
wire sig0000026b;
wire sig0000026c;
wire sig0000026d;
wire sig0000026e;
wire sig0000026f;
wire sig00000270;
wire sig00000271;
wire sig00000272;
wire sig00000273;
wire sig00000274;
wire sig00000275;
wire sig00000276;
wire sig00000277;
wire sig00000278;
wire sig00000279;
wire sig0000027a;
wire sig0000027b;
wire sig0000027c;
wire sig0000027d;
wire sig0000027e;
wire sig0000027f;
wire sig00000280;
wire sig00000281;
wire sig00000282;
wire sig00000283;
wire sig00000284;
wire sig00000285;
wire sig00000286;
wire sig00000287;
wire sig00000288;
wire sig00000289;
wire sig0000028a;
wire sig0000028b;
wire sig0000028c;
wire sig0000028d;
wire sig0000028e;
wire sig0000028f;
wire sig00000290;
wire sig00000291;
wire sig00000292;
wire sig00000293;
wire sig00000294;
wire sig00000295;
wire sig00000296;
wire sig00000297;
wire sig00000298;
wire sig00000299;
wire sig0000029a;
wire sig0000029b;
wire sig0000029c;
wire sig0000029d;
wire sig0000029e;
wire sig0000029f;
wire sig000002a0;
wire sig000002a1;
wire sig000002a2;
wire sig000002a3;
wire sig000002a4;
wire sig000002a5;
wire sig000002a6;
wire sig000002a7;
wire sig000002a8;
wire sig000002a9;
wire sig000002aa;
wire sig000002ab;
wire sig000002ac;
wire sig000002ad;
wire sig000002ae;
wire sig000002af;
wire sig000002b0;
wire sig000002b1;
wire sig000002b2;
wire sig000002b3;
wire sig000002b4;
wire sig000002b5;
wire sig000002b6;
wire sig000002b7;
wire sig000002b8;
wire sig000002b9;
wire sig000002ba;
wire sig000002bb;
wire sig000002bc;
wire sig000002bd;
wire sig000002be;
wire sig000002bf;
wire sig000002c0;
wire sig000002c1;
wire sig000002c2;
wire sig000002c3;
wire sig000002c4;
wire sig000002c5;
wire sig000002c6;
wire sig000002c7;
wire sig000002c8;
wire sig000002c9;
wire sig000002ca;
wire sig000002cb;
wire sig000002cc;
wire sig000002cd;
wire sig000002ce;
wire sig000002cf;
wire sig000002d0;
wire sig000002d1;
wire sig000002d2;
wire sig000002d3;
wire sig000002d4;
wire sig000002d5;
wire sig000002d6;
wire sig000002d7;
wire sig000002d8;
wire sig000002d9;
wire sig000002da;
wire sig000002db;
wire sig000002dc;
wire sig000002dd;
wire sig000002de;
wire sig000002df;
wire sig000002e0;
wire sig000002e1;
wire sig000002e2;
wire sig000002e3;
wire sig000002e4;
wire NLW_blk00000082_O_UNCONNECTED;
wire NLW_blk000000cb_O_UNCONNECTED;
wire NLW_blk000002a3_Q15_UNCONNECTED;
wire NLW_blk000002a5_Q15_UNCONNECTED;
wire NLW_blk000002a7_Q15_UNCONNECTED;
wire NLW_blk000002a9_Q15_UNCONNECTED;
wire NLW_blk000002ab_Q15_UNCONNECTED;
wire NLW_blk000002ad_Q15_UNCONNECTED;
wire NLW_blk000002af_Q15_UNCONNECTED;
wire NLW_blk000002b1_Q15_UNCONNECTED;
wire NLW_blk000002b3_Q15_UNCONNECTED;
wire NLW_blk000002b5_Q15_UNCONNECTED;
wire NLW_blk000002b7_Q15_UNCONNECTED;
wire NLW_blk000002b9_Q15_UNCONNECTED;
wire NLW_blk000002bb_Q15_UNCONNECTED;
wire NLW_blk000002bd_Q15_UNCONNECTED;
wire NLW_blk000002bf_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk000002bf_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk000002bf_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk000002bf_UNDERFLOW_UNCONNECTED;
wire NLW_blk000002bf_OVERFLOW_UNCONNECTED;
wire \NLW_blk000002bf_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk000002bf_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk000002bf_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk000002bf_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk000002bf_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk000002bf_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002bf_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002bf_P<47>_UNCONNECTED ;
wire \NLW_blk000002bf_P<46>_UNCONNECTED ;
wire \NLW_blk000002bf_P<45>_UNCONNECTED ;
wire \NLW_blk000002bf_P<44>_UNCONNECTED ;
wire \NLW_blk000002bf_P<43>_UNCONNECTED ;
wire \NLW_blk000002bf_P<42>_UNCONNECTED ;
wire \NLW_blk000002bf_P<41>_UNCONNECTED ;
wire \NLW_blk000002bf_P<40>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002bf_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_P<26>_UNCONNECTED ;
wire NLW_blk000002c0_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk000002c0_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk000002c0_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk000002c0_UNDERFLOW_UNCONNECTED;
wire NLW_blk000002c0_PATTERNDETECT_UNCONNECTED;
wire NLW_blk000002c0_OVERFLOW_UNCONNECTED;
wire \NLW_blk000002c0_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_P<47>_UNCONNECTED ;
wire \NLW_blk000002c0_P<46>_UNCONNECTED ;
wire \NLW_blk000002c0_P<45>_UNCONNECTED ;
wire \NLW_blk000002c0_P<44>_UNCONNECTED ;
wire \NLW_blk000002c0_P<43>_UNCONNECTED ;
wire \NLW_blk000002c0_P<42>_UNCONNECTED ;
wire \NLW_blk000002c0_P<41>_UNCONNECTED ;
wire \NLW_blk000002c0_P<40>_UNCONNECTED ;
wire \NLW_blk000002c0_P<39>_UNCONNECTED ;
wire \NLW_blk000002c0_P<38>_UNCONNECTED ;
wire \NLW_blk000002c0_P<37>_UNCONNECTED ;
wire \NLW_blk000002c0_P<36>_UNCONNECTED ;
wire \NLW_blk000002c0_P<35>_UNCONNECTED ;
wire \NLW_blk000002c0_P<25>_UNCONNECTED ;
wire \NLW_blk000002c0_P<1>_UNCONNECTED ;
wire \NLW_blk000002c0_P<0>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<0>_UNCONNECTED ;
wire [7 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op ;
wire [22 : 0] \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op ;
assign
result[31] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op ,
result[30] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [7],
result[29] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [6],
result[28] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [5],
result[27] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [4],
result[26] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [3],
result[25] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [2],
result[24] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [1],
result[23] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [0],
result[22] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22],
result[21] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21],
result[20] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20],
result[19] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19],
result[18] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18],
result[17] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17],
result[16] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16],
result[15] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15],
result[14] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14],
result[13] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13],
result[12] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12],
result[11] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11],
result[10] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10],
result[9] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9],
result[8] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8],
result[7] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7],
result[6] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6],
result[5] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5],
result[4] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4],
result[3] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3],
result[2] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2],
result[1] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1],
result[0] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig000000af),
.Q(sig0000000f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.CE(ce),
.D(sig000000ae),
.Q(sig0000000e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.CE(ce),
.D(sig000000ad),
.Q(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.CE(ce),
.D(sig000000dd),
.Q(sig00000010)
);
FDE #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.CE(ce),
.D(sig000000de),
.Q(sig0000000d)
);
XORCY blk00000008 (
.CI(sig0000008c),
.LI(sig00000001),
.O(sig000000dc)
);
MUXCY blk00000009 (
.CI(sig0000008d),
.DI(sig00000002),
.S(sig00000001),
.O(sig0000008c)
);
XORCY blk0000000a (
.CI(sig0000008f),
.LI(sig0000008e),
.O(sig000000db)
);
MUXCY blk0000000b (
.CI(sig0000008f),
.DI(sig000000ea),
.S(sig0000008e),
.O(sig0000008d)
);
XORCY blk0000000c (
.CI(sig00000091),
.LI(sig00000090),
.O(sig000000da)
);
MUXCY blk0000000d (
.CI(sig00000091),
.DI(sig000000e9),
.S(sig00000090),
.O(sig0000008f)
);
XORCY blk0000000e (
.CI(sig00000093),
.LI(sig00000092),
.O(sig000000d9)
);
MUXCY blk0000000f (
.CI(sig00000093),
.DI(sig000000e8),
.S(sig00000092),
.O(sig00000091)
);
XORCY blk00000010 (
.CI(sig00000095),
.LI(sig00000094),
.O(sig000000d8)
);
MUXCY blk00000011 (
.CI(sig00000095),
.DI(sig000000e7),
.S(sig00000094),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000012 (
.I0(sig000000e7),
.I1(sig00000067),
.O(sig00000094)
);
XORCY blk00000013 (
.CI(sig00000097),
.LI(sig00000096),
.O(sig000000d7)
);
MUXCY blk00000014 (
.CI(sig00000097),
.DI(sig000000e6),
.S(sig00000096),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000015 (
.I0(sig000000e6),
.I1(sig00000068),
.O(sig00000096)
);
XORCY blk00000016 (
.CI(sig00000099),
.LI(sig00000098),
.O(sig000000d6)
);
MUXCY blk00000017 (
.CI(sig00000099),
.DI(sig000000e5),
.S(sig00000098),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000018 (
.I0(sig000000e5),
.I1(sig00000069),
.O(sig00000098)
);
XORCY blk00000019 (
.CI(sig0000009b),
.LI(sig0000009a),
.O(sig000000d5)
);
MUXCY blk0000001a (
.CI(sig0000009b),
.DI(sig000000e4),
.S(sig0000009a),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001b (
.I0(sig000000e4),
.I1(sig0000006a),
.O(sig0000009a)
);
XORCY blk0000001c (
.CI(sig00000001),
.LI(sig0000009c),
.O(sig000000d4)
);
MUXCY blk0000001d (
.CI(sig00000001),
.DI(sig000000e3),
.S(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001e (
.I0(sig000000e3),
.I1(sig0000006b),
.O(sig0000009c)
);
XORCY blk0000001f (
.CI(sig0000009d),
.LI(sig00000001),
.O(sig000000cc)
);
XORCY blk00000020 (
.CI(sig0000009f),
.LI(sig0000009e),
.O(sig000000cb)
);
MUXCY blk00000021 (
.CI(sig0000009f),
.DI(b[30]),
.S(sig0000009e),
.O(sig0000009d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000022 (
.I0(b[30]),
.I1(a[30]),
.O(sig0000009e)
);
XORCY blk00000023 (
.CI(sig000000a1),
.LI(sig000000a0),
.O(sig000000ca)
);
MUXCY blk00000024 (
.CI(sig000000a1),
.DI(b[29]),
.S(sig000000a0),
.O(sig0000009f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000025 (
.I0(b[29]),
.I1(a[29]),
.O(sig000000a0)
);
XORCY blk00000026 (
.CI(sig000000a3),
.LI(sig000000a2),
.O(sig000000c9)
);
MUXCY blk00000027 (
.CI(sig000000a3),
.DI(b[28]),
.S(sig000000a2),
.O(sig000000a1)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000028 (
.I0(b[28]),
.I1(a[28]),
.O(sig000000a2)
);
XORCY blk00000029 (
.CI(sig000000a5),
.LI(sig000000a4),
.O(sig000000c8)
);
MUXCY blk0000002a (
.CI(sig000000a5),
.DI(b[27]),
.S(sig000000a4),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002b (
.I0(b[27]),
.I1(a[27]),
.O(sig000000a4)
);
XORCY blk0000002c (
.CI(sig000000a7),
.LI(sig000000a6),
.O(sig000000c7)
);
MUXCY blk0000002d (
.CI(sig000000a7),
.DI(b[26]),
.S(sig000000a6),
.O(sig000000a5)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002e (
.I0(b[26]),
.I1(a[26]),
.O(sig000000a6)
);
XORCY blk0000002f (
.CI(sig000000a9),
.LI(sig000000a8),
.O(sig000000c6)
);
MUXCY blk00000030 (
.CI(sig000000a9),
.DI(b[25]),
.S(sig000000a8),
.O(sig000000a7)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000031 (
.I0(b[25]),
.I1(a[25]),
.O(sig000000a8)
);
XORCY blk00000032 (
.CI(sig000000ab),
.LI(sig000000aa),
.O(sig000000c5)
);
MUXCY blk00000033 (
.CI(sig000000ab),
.DI(b[24]),
.S(sig000000aa),
.O(sig000000a9)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000034 (
.I0(b[24]),
.I1(a[24]),
.O(sig000000aa)
);
XORCY blk00000035 (
.CI(sig00000001),
.LI(sig000000ac),
.O(sig000000c4)
);
MUXCY blk00000036 (
.CI(sig00000001),
.DI(b[23]),
.S(sig000000ac),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000037 (
.I0(b[23]),
.I1(a[23]),
.O(sig000000ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000038 (
.C(clk),
.CE(ce),
.D(sig000000bf),
.Q(sig000000df)
);
FDE #(
.INIT ( 1'b0 ))
blk00000039 (
.C(clk),
.CE(ce),
.D(sig000000e2),
.Q(sig000000e1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003a (
.C(clk),
.CE(ce),
.D(sig000000be),
.Q(sig000000e0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003b (
.C(clk),
.CE(ce),
.D(sig000000ce),
.Q(sig000000b0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003c (
.C(clk),
.CE(ce),
.D(a[31]),
.Q(sig000000fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003d (
.C(clk),
.CE(ce),
.D(b[31]),
.Q(sig000000fd)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003e (
.C(clk),
.CE(ce),
.D(sig0000008b),
.Q(sig000000b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003f (
.C(clk),
.CE(ce),
.D(sig0000001a),
.Q(sig000000fc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000040 (
.C(clk),
.CE(ce),
.D(sig000000c1),
.Q(sig000000fb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000041 (
.C(clk),
.CE(ce),
.D(sig000000c3),
.Q(sig000000fa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000042 (
.C(clk),
.CE(ce),
.D(sig000000c2),
.Q(sig000000f8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000043 (
.C(clk),
.CE(ce),
.D(sig000000c0),
.Q(sig000001a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000044 (
.C(clk),
.CE(ce),
.D(sig000000d1),
.Q(sig000000f7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000045 (
.C(clk),
.CE(ce),
.D(sig000000d2),
.Q(sig000000f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000046 (
.C(clk),
.CE(ce),
.D(sig000000d3),
.Q(sig000000f6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.CE(ce),
.D(sig000000cd),
.Q(sig0000001b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.CE(ce),
.D(sig000000b5),
.Q(sig00000110)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.CE(ce),
.D(sig000000b4),
.Q(sig00000111)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.CE(ce),
.D(sig000000b3),
.Q(sig00000113)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.CE(ce),
.D(sig000000b2),
.Q(sig00000114)
);
MUXCY blk0000004c (
.CI(sig00000001),
.DI(sig00000002),
.S(sig0000011c),
.O(sig00000116)
);
MUXCY blk0000004d (
.CI(sig00000116),
.DI(sig00000002),
.S(sig0000011b),
.O(sig00000117)
);
MUXCY blk0000004e (
.CI(sig00000117),
.DI(sig00000002),
.S(sig0000011a),
.O(sig00000118)
);
MUXCY blk0000004f (
.CI(sig00000118),
.DI(sig00000002),
.S(sig0000011d),
.O(sig00000119)
);
FDE #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.CE(ce),
.D(sig00000119),
.Q(sig00000115)
);
MUXCY blk00000051 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000124),
.O(sig0000011e)
);
MUXCY blk00000052 (
.CI(sig0000011e),
.DI(sig00000002),
.S(sig00000123),
.O(sig0000011f)
);
MUXCY blk00000053 (
.CI(sig0000011f),
.DI(sig00000002),
.S(sig00000122),
.O(sig00000120)
);
MUXCY blk00000054 (
.CI(sig00000120),
.DI(sig00000002),
.S(sig00000125),
.O(sig00000121)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(ce),
.D(sig00000121),
.Q(sig00000112)
);
MUXCY blk00000056 (
.CI(sig00000147),
.DI(sig00000126),
.S(sig00000127),
.O(sig00000146)
);
MUXCY blk00000057 (
.CI(sig00000148),
.DI(sig00000128),
.S(sig00000129),
.O(sig00000147)
);
MUXCY blk00000058 (
.CI(sig00000149),
.DI(sig0000012a),
.S(sig0000012b),
.O(sig00000148)
);
MUXCY blk00000059 (
.CI(sig0000014a),
.DI(sig0000012c),
.S(sig0000012d),
.O(sig00000149)
);
MUXCY blk0000005a (
.CI(sig0000014b),
.DI(sig0000012e),
.S(sig0000012f),
.O(sig0000014a)
);
MUXCY blk0000005b (
.CI(sig0000014c),
.DI(sig00000130),
.S(sig00000131),
.O(sig0000014b)
);
MUXCY blk0000005c (
.CI(sig0000014d),
.DI(sig00000132),
.S(sig00000133),
.O(sig0000014c)
);
MUXCY blk0000005d (
.CI(sig0000014e),
.DI(sig00000134),
.S(sig00000135),
.O(sig0000014d)
);
MUXCY blk0000005e (
.CI(sig0000014f),
.DI(sig00000136),
.S(sig00000137),
.O(sig0000014e)
);
MUXCY blk0000005f (
.CI(sig00000150),
.DI(sig00000138),
.S(sig00000139),
.O(sig0000014f)
);
MUXCY blk00000060 (
.CI(sig00000151),
.DI(sig0000013a),
.S(sig0000013b),
.O(sig00000150)
);
MUXCY blk00000061 (
.CI(sig00000152),
.DI(sig0000013c),
.S(sig0000013d),
.O(sig00000151)
);
MUXCY blk00000062 (
.CI(sig00000153),
.DI(sig0000013e),
.S(sig0000013f),
.O(sig00000152)
);
MUXCY blk00000063 (
.CI(sig00000154),
.DI(sig00000140),
.S(sig00000141),
.O(sig00000153)
);
MUXCY blk00000064 (
.CI(sig00000155),
.DI(sig00000142),
.S(sig00000143),
.O(sig00000154)
);
MUXCY blk00000065 (
.CI(sig00000002),
.DI(sig00000144),
.S(sig00000145),
.O(sig00000155)
);
FDE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(clk),
.CE(ce),
.D(sig00000146),
.Q(sig00000019)
);
FDE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(clk),
.CE(ce),
.D(b[30]),
.Q(sig00000106)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(ce),
.D(b[29]),
.Q(sig00000105)
);
FDE #(
.INIT ( 1'b0 ))
blk00000069 (
.C(clk),
.CE(ce),
.D(b[28]),
.Q(sig00000104)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006a (
.C(clk),
.CE(ce),
.D(b[27]),
.Q(sig00000103)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006b (
.C(clk),
.CE(ce),
.D(b[26]),
.Q(sig00000102)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006c (
.C(clk),
.CE(ce),
.D(b[25]),
.Q(sig00000101)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006d (
.C(clk),
.CE(ce),
.D(b[24]),
.Q(sig00000100)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006e (
.C(clk),
.CE(ce),
.D(b[23]),
.Q(sig000000ff)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006f (
.C(clk),
.CE(ce),
.D(a[30]),
.Q(sig0000010e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000070 (
.C(clk),
.CE(ce),
.D(a[29]),
.Q(sig0000010d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000071 (
.C(clk),
.CE(ce),
.D(a[28]),
.Q(sig0000010c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(ce),
.D(a[27]),
.Q(sig0000010b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000073 (
.C(clk),
.CE(ce),
.D(a[26]),
.Q(sig0000010a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000074 (
.C(clk),
.CE(ce),
.D(a[25]),
.Q(sig00000109)
);
FDE #(
.INIT ( 1'b0 ))
blk00000075 (
.C(clk),
.CE(ce),
.D(a[24]),
.Q(sig00000108)
);
FDE #(
.INIT ( 1'b0 ))
blk00000076 (
.C(clk),
.CE(ce),
.D(a[23]),
.Q(sig00000107)
);
FDE #(
.INIT ( 1'b0 ))
blk00000077 (
.C(clk),
.CE(ce),
.D(sig000000cc),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000078 (
.C(clk),
.CE(ce),
.D(sig000000cb),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000079 (
.C(clk),
.CE(ce),
.D(sig000000ca),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007a (
.C(clk),
.CE(ce),
.D(sig000000c9),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007b (
.C(clk),
.CE(ce),
.D(sig000000c8),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(clk),
.CE(ce),
.D(sig000000c7),
.Q(sig00000008)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(clk),
.CE(ce),
.D(sig000000c6),
.Q(sig00000009)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(clk),
.CE(ce),
.D(sig000000c5),
.Q(sig0000000a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(clk),
.CE(ce),
.D(sig000000c4),
.Q(sig0000000b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(clk),
.CE(ce),
.D(sig000000d0),
.Q(sig00000157)
);
FDE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(clk),
.CE(ce),
.D(sig000000cf),
.Q(sig00000156)
);
XORCY blk00000082 (
.CI(sig00000158),
.LI(sig00000002),
.O(NLW_blk00000082_O_UNCONNECTED)
);
XORCY blk00000083 (
.CI(sig00000159),
.LI(sig000000bd),
.O(sig000000f2)
);
MUXCY blk00000084 (
.CI(sig00000159),
.DI(sig00000002),
.S(sig000000bd),
.O(sig00000158)
);
XORCY blk00000085 (
.CI(sig0000015a),
.LI(sig000000bc),
.O(sig000000f1)
);
MUXCY blk00000086 (
.CI(sig0000015a),
.DI(sig00000002),
.S(sig000000bc),
.O(sig00000159)
);
XORCY blk00000087 (
.CI(sig0000015b),
.LI(sig000000bb),
.O(sig000000f0)
);
MUXCY blk00000088 (
.CI(sig0000015b),
.DI(sig00000002),
.S(sig000000bb),
.O(sig0000015a)
);
XORCY blk00000089 (
.CI(sig0000015c),
.LI(sig000000ba),
.O(sig000000ef)
);
MUXCY blk0000008a (
.CI(sig0000015c),
.DI(sig00000002),
.S(sig000000ba),
.O(sig0000015b)
);
XORCY blk0000008b (
.CI(sig0000015d),
.LI(sig000000b9),
.O(sig000000ee)
);
MUXCY blk0000008c (
.CI(sig0000015d),
.DI(sig00000002),
.S(sig000000b9),
.O(sig0000015c)
);
XORCY blk0000008d (
.CI(sig0000015e),
.LI(sig000000b8),
.O(sig000000ed)
);
MUXCY blk0000008e (
.CI(sig0000015e),
.DI(sig00000002),
.S(sig000000b8),
.O(sig0000015d)
);
XORCY blk0000008f (
.CI(sig0000015f),
.LI(sig000000b7),
.O(sig000000ec)
);
MUXCY blk00000090 (
.CI(sig0000015f),
.DI(sig00000002),
.S(sig000000b7),
.O(sig0000015e)
);
XORCY blk00000091 (
.CI(sig00000002),
.LI(sig000000b6),
.O(sig000000eb)
);
MUXCY blk00000092 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig000000b6),
.O(sig0000015f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000093 (
.C(clk),
.CE(ce),
.D(sig000000dc),
.Q(sig000000e2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(ce),
.D(sig000000db),
.Q(sig00000011)
);
FDE #(
.INIT ( 1'b0 ))
blk00000095 (
.C(clk),
.CE(ce),
.D(sig000000da),
.Q(sig00000012)
);
FDE #(
.INIT ( 1'b0 ))
blk00000096 (
.C(clk),
.CE(ce),
.D(sig000000d9),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk00000097 (
.C(clk),
.CE(ce),
.D(sig000000d8),
.Q(sig00000014)
);
FDE #(
.INIT ( 1'b0 ))
blk00000098 (
.C(clk),
.CE(ce),
.D(sig000000d7),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk00000099 (
.C(clk),
.CE(ce),
.D(sig000000d6),
.Q(sig00000016)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009a (
.C(clk),
.CE(ce),
.D(sig000000d5),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009b (
.C(clk),
.CE(ce),
.D(sig000000d4),
.Q(sig00000018)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009c (
.C(clk),
.CE(ce),
.D(a[22]),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009d (
.C(clk),
.CE(ce),
.D(a[21]),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009e (
.C(clk),
.CE(ce),
.D(a[20]),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009f (
.C(clk),
.CE(ce),
.D(a[19]),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(ce),
.D(a[18]),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(clk),
.CE(ce),
.D(a[17]),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(clk),
.CE(ce),
.D(a[16]),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(clk),
.CE(ce),
.D(a[15]),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(clk),
.CE(ce),
.D(a[14]),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(clk),
.CE(ce),
.D(a[13]),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(clk),
.CE(ce),
.D(a[12]),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(clk),
.CE(ce),
.D(a[11]),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(clk),
.CE(ce),
.D(a[10]),
.Q(sig00000028)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(clk),
.CE(ce),
.D(a[9]),
.Q(sig00000029)
);
FDE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(clk),
.CE(ce),
.D(a[8]),
.Q(sig0000002a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(clk),
.CE(ce),
.D(a[7]),
.Q(sig0000002b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ac (
.C(clk),
.CE(ce),
.D(a[6]),
.Q(sig0000002c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ad (
.C(clk),
.CE(ce),
.D(a[5]),
.Q(sig0000002d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ae (
.C(clk),
.CE(ce),
.D(a[4]),
.Q(sig0000002e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000af (
.C(clk),
.CE(ce),
.D(a[3]),
.Q(sig0000002f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b0 (
.C(clk),
.CE(ce),
.D(a[2]),
.Q(sig00000030)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b1 (
.C(clk),
.CE(ce),
.D(a[1]),
.Q(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b2 (
.C(clk),
.CE(ce),
.D(a[0]),
.Q(sig00000032)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b3 (
.C(clk),
.CE(ce),
.D(b[22]),
.Q(sig00000033)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b4 (
.C(clk),
.CE(ce),
.D(b[21]),
.Q(sig00000034)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b5 (
.C(clk),
.CE(ce),
.D(b[20]),
.Q(sig00000035)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b6 (
.C(clk),
.CE(ce),
.D(b[19]),
.Q(sig00000036)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(clk),
.CE(ce),
.D(b[18]),
.Q(sig00000037)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(clk),
.CE(ce),
.D(b[17]),
.Q(sig00000038)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(clk),
.CE(ce),
.D(b[16]),
.Q(sig00000039)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ba (
.C(clk),
.CE(ce),
.D(b[15]),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bb (
.C(clk),
.CE(ce),
.D(b[14]),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(clk),
.CE(ce),
.D(b[13]),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.CE(ce),
.D(b[12]),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.CE(ce),
.D(b[11]),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.CE(ce),
.D(b[10]),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.CE(ce),
.D(b[9]),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.CE(ce),
.D(b[8]),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.CE(ce),
.D(b[7]),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.CE(ce),
.D(b[6]),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.CE(ce),
.D(b[5]),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.CE(ce),
.D(b[4]),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.CE(ce),
.D(b[3]),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.CE(ce),
.D(b[2]),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.CE(ce),
.D(b[1]),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.CE(ce),
.D(b[0]),
.Q(sig00000049)
);
MUXCY blk000000ca (
.CI(sig000001fa),
.DI(sig00000001),
.S(sig000002d6),
.O(sig000001a2)
);
XORCY blk000000cb (
.CI(sig000001fa),
.LI(sig000002d6),
.O(NLW_blk000000cb_O_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.CE(ce),
.D(sig000001a2),
.Q(sig000001f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.CE(ce),
.D(sig000001a3),
.Q(sig000001fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.CE(ce),
.D(sig000001c0),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.CE(ce),
.D(sig000001a4),
.Q(sig000001a1)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.CE(ce),
.D(sig000001fc),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.CE(ce),
.D(sig000001a5),
.Q(sig000001a0)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.CE(ce),
.D(sig000001bf),
.Q(sig000001f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.CE(ce),
.D(sig000001be),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.CE(ce),
.D(sig00000214),
.Q(sig00000188)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.CE(ce),
.D(sig00000213),
.Q(sig00000189)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.CE(ce),
.D(sig00000212),
.Q(sig0000018a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.CE(ce),
.D(sig00000211),
.Q(sig0000018b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.CE(ce),
.D(sig00000210),
.Q(sig0000018c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.CE(ce),
.D(sig0000020f),
.Q(sig0000018d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.CE(ce),
.D(sig0000020e),
.Q(sig0000018e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.CE(ce),
.D(sig0000020d),
.Q(sig0000018f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.CE(ce),
.D(sig0000020c),
.Q(sig00000190)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.CE(ce),
.D(sig0000020b),
.Q(sig00000191)
);
FDE #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.CE(ce),
.D(sig0000020a),
.Q(sig00000192)
);
FDE #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.CE(ce),
.D(sig00000209),
.Q(sig00000193)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.CE(ce),
.D(sig00000208),
.Q(sig00000194)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.CE(ce),
.D(sig00000207),
.Q(sig00000195)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.CE(ce),
.D(sig00000206),
.Q(sig00000196)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.CE(ce),
.D(sig00000205),
.Q(sig00000197)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.CE(ce),
.D(sig00000204),
.Q(sig00000198)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.CE(ce),
.D(sig00000203),
.Q(sig00000199)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.CE(ce),
.D(sig00000202),
.Q(sig0000019a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.CE(ce),
.D(sig00000201),
.Q(sig0000019b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.CE(ce),
.D(sig00000200),
.Q(sig0000019c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.CE(ce),
.D(sig000001ff),
.Q(sig0000019d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.CE(ce),
.D(sig000001fe),
.Q(sig0000019e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.CE(ce),
.D(sig000001fd),
.Q(sig0000019f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.CE(ce),
.D(sig00000001),
.Q(sig00000214)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.CE(ce),
.D(sig000001e9),
.Q(sig00000213)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.CE(ce),
.D(sig000001e8),
.Q(sig00000212)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.CE(ce),
.D(sig000001e7),
.Q(sig00000211)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.CE(ce),
.D(sig000001e6),
.Q(sig00000210)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.CE(ce),
.D(sig000001e5),
.Q(sig0000020f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.CE(ce),
.D(sig000001e4),
.Q(sig0000020e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.CE(ce),
.D(sig000001e3),
.Q(sig0000020d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.CE(ce),
.D(sig000001e2),
.Q(sig0000020c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.CE(ce),
.D(sig000001e1),
.Q(sig0000020b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.CE(ce),
.D(sig000001e0),
.Q(sig0000020a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.CE(ce),
.D(sig000001df),
.Q(sig00000209)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.CE(ce),
.D(sig000001de),
.Q(sig00000208)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.CE(ce),
.D(sig000001dd),
.Q(sig00000207)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.CE(ce),
.D(sig000001dc),
.Q(sig00000206)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.CE(ce),
.D(sig000001db),
.Q(sig00000205)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.CE(ce),
.D(sig000001da),
.Q(sig00000204)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.CE(ce),
.D(sig000001d9),
.Q(sig00000203)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.CE(ce),
.D(sig000001d8),
.Q(sig00000202)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.CE(ce),
.D(sig000001d7),
.Q(sig00000201)
);
FDE #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.CE(ce),
.D(sig000001d6),
.Q(sig00000200)
);
FDE #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.CE(ce),
.D(sig000001d5),
.Q(sig000001ff)
);
FDE #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.CE(ce),
.D(sig000001d4),
.Q(sig000001fe)
);
FDE #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.CE(ce),
.D(sig000001d3),
.Q(sig000001fd)
);
MUXCY blk00000104 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000221),
.O(sig00000215)
);
MUXCY blk00000105 (
.CI(sig00000215),
.DI(sig00000002),
.S(sig00000220),
.O(sig00000216)
);
MUXCY blk00000106 (
.CI(sig00000216),
.DI(sig00000002),
.S(sig0000021f),
.O(sig00000217)
);
MUXCY blk00000107 (
.CI(sig00000217),
.DI(sig00000002),
.S(sig0000021e),
.O(sig00000218)
);
MUXCY blk00000108 (
.CI(sig00000218),
.DI(sig00000002),
.S(sig0000021d),
.O(sig00000219)
);
MUXCY blk00000109 (
.CI(sig00000219),
.DI(sig00000002),
.S(sig0000021c),
.O(sig0000021a)
);
MUXCY blk0000010a (
.CI(sig0000021a),
.DI(sig00000002),
.S(sig0000021b),
.O(sig000001fa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.CE(ce),
.D(sig000001d0),
.Q(sig00000178)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.CE(ce),
.D(sig000001cf),
.Q(sig00000179)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.CE(ce),
.D(sig000001ce),
.Q(sig0000017a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010e (
.C(clk),
.CE(ce),
.D(sig000001cd),
.Q(sig0000017b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010f (
.C(clk),
.CE(ce),
.D(sig000001cc),
.Q(sig0000017c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000110 (
.C(clk),
.CE(ce),
.D(sig000001cb),
.Q(sig0000017d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000111 (
.C(clk),
.CE(ce),
.D(sig000001ca),
.Q(sig0000017e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000112 (
.C(clk),
.CE(ce),
.D(sig000001c9),
.Q(sig0000017f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000113 (
.C(clk),
.CE(ce),
.D(sig000001c8),
.Q(sig00000180)
);
FDE #(
.INIT ( 1'b0 ))
blk00000114 (
.C(clk),
.CE(ce),
.D(sig000001c7),
.Q(sig00000181)
);
FDE #(
.INIT ( 1'b0 ))
blk00000115 (
.C(clk),
.CE(ce),
.D(sig000001c6),
.Q(sig00000182)
);
FDE #(
.INIT ( 1'b0 ))
blk00000116 (
.C(clk),
.CE(ce),
.D(sig000001c5),
.Q(sig00000183)
);
FDE #(
.INIT ( 1'b0 ))
blk00000117 (
.C(clk),
.CE(ce),
.D(sig000001c4),
.Q(sig00000184)
);
FDE #(
.INIT ( 1'b0 ))
blk00000118 (
.C(clk),
.CE(ce),
.D(sig000001c3),
.Q(sig00000185)
);
FDE #(
.INIT ( 1'b0 ))
blk00000119 (
.C(clk),
.CE(ce),
.D(sig000001c2),
.Q(sig00000186)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011a (
.C(clk),
.CE(ce),
.D(sig000001c1),
.Q(sig00000187)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011b (
.C(clk),
.CE(ce),
.D(sig000001bd),
.Q(sig00000160)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011c (
.C(clk),
.CE(ce),
.D(sig000001bc),
.Q(sig00000161)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011d (
.C(clk),
.CE(ce),
.D(sig000001bb),
.Q(sig00000162)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011e (
.C(clk),
.CE(ce),
.D(sig000001ba),
.Q(sig00000163)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011f (
.C(clk),
.CE(ce),
.D(sig000001b9),
.Q(sig00000164)
);
FDE #(
.INIT ( 1'b0 ))
blk00000120 (
.C(clk),
.CE(ce),
.D(sig000001b8),
.Q(sig00000165)
);
FDE #(
.INIT ( 1'b0 ))
blk00000121 (
.C(clk),
.CE(ce),
.D(sig000001b7),
.Q(sig00000166)
);
FDE #(
.INIT ( 1'b0 ))
blk00000122 (
.C(clk),
.CE(ce),
.D(sig000001b6),
.Q(sig00000167)
);
FDE #(
.INIT ( 1'b0 ))
blk00000123 (
.C(clk),
.CE(ce),
.D(sig000001b5),
.Q(sig00000168)
);
FDE #(
.INIT ( 1'b0 ))
blk00000124 (
.C(clk),
.CE(ce),
.D(sig000001b4),
.Q(sig00000169)
);
FDE #(
.INIT ( 1'b0 ))
blk00000125 (
.C(clk),
.CE(ce),
.D(sig000001b3),
.Q(sig0000016a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000126 (
.C(clk),
.CE(ce),
.D(sig000001b2),
.Q(sig0000016b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000127 (
.C(clk),
.CE(ce),
.D(sig000001b1),
.Q(sig0000016c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000128 (
.C(clk),
.CE(ce),
.D(sig000001b0),
.Q(sig0000016d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000129 (
.C(clk),
.CE(ce),
.D(sig000001af),
.Q(sig0000016e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012a (
.C(clk),
.CE(ce),
.D(sig000001ae),
.Q(sig0000016f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012b (
.C(clk),
.CE(ce),
.D(sig000001ad),
.Q(sig00000170)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012c (
.C(clk),
.CE(ce),
.D(sig000001ac),
.Q(sig00000171)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012d (
.C(clk),
.CE(ce),
.D(sig000001ab),
.Q(sig00000172)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012e (
.C(clk),
.CE(ce),
.D(sig000001aa),
.Q(sig00000173)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012f (
.C(clk),
.CE(ce),
.D(sig000001a9),
.Q(sig00000174)
);
FDE #(
.INIT ( 1'b0 ))
blk00000130 (
.C(clk),
.CE(ce),
.D(sig000001a8),
.Q(sig00000175)
);
FDE #(
.INIT ( 1'b0 ))
blk00000131 (
.C(clk),
.CE(ce),
.D(sig000001a7),
.Q(sig00000176)
);
FDE #(
.INIT ( 1'b0 ))
blk00000132 (
.C(clk),
.CE(ce),
.D(sig000001a6),
.Q(sig00000177)
);
FDE #(
.INIT ( 1'b0 ))
blk00000133 (
.C(clk),
.CE(ce),
.D(sig00000229),
.Q(sig00000222)
);
FDE #(
.INIT ( 1'b0 ))
blk00000134 (
.C(clk),
.CE(ce),
.D(sig00000222),
.Q(sig0000022a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000135 (
.C(clk),
.CE(ce),
.D(sig00000228),
.Q(sig00000223)
);
FDE #(
.INIT ( 1'b0 ))
blk00000136 (
.C(clk),
.CE(ce),
.D(sig00000223),
.Q(sig0000022e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000137 (
.C(clk),
.CE(ce),
.D(sig00000227),
.Q(sig00000224)
);
FDE #(
.INIT ( 1'b0 ))
blk00000138 (
.C(clk),
.CE(ce),
.D(sig00000224),
.Q(sig0000022d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000139 (
.C(clk),
.CE(ce),
.D(sig00000226),
.Q(sig00000230)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013a (
.C(clk),
.CE(ce),
.D(sig00000231),
.Q(sig0000022f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013b (
.C(clk),
.CE(ce),
.D(sig00000225),
.Q(sig0000022c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013c (
.C(clk),
.CE(ce),
.D(sig00000285),
.Q(sig0000024c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013d (
.C(clk),
.CE(ce),
.D(sig00000282),
.Q(sig0000024d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013e (
.C(clk),
.CE(ce),
.D(sig00000281),
.Q(sig0000024e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013f (
.C(clk),
.CE(ce),
.D(sig00000280),
.Q(sig0000024f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000140 (
.C(clk),
.CE(ce),
.D(sig0000027f),
.Q(sig00000250)
);
FDE #(
.INIT ( 1'b0 ))
blk00000141 (
.C(clk),
.CE(ce),
.D(sig0000027c),
.Q(sig00000251)
);
FDE #(
.INIT ( 1'b0 ))
blk00000142 (
.C(clk),
.CE(ce),
.D(sig0000027b),
.Q(sig00000252)
);
FDE #(
.INIT ( 1'b0 ))
blk00000143 (
.C(clk),
.CE(ce),
.D(sig0000027a),
.Q(sig00000253)
);
FDE #(
.INIT ( 1'b0 ))
blk00000144 (
.C(clk),
.CE(ce),
.D(sig00000279),
.Q(sig00000254)
);
FDE #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.CE(ce),
.D(sig00000276),
.Q(sig00000255)
);
FDE #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.CE(ce),
.D(sig00000275),
.Q(sig00000256)
);
FDE #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.CE(ce),
.D(sig00000274),
.Q(sig00000257)
);
FDE #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.CE(ce),
.D(sig00000273),
.Q(sig00000258)
);
FDE #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.CE(ce),
.D(sig00000270),
.Q(sig00000259)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.CE(ce),
.D(sig0000026f),
.Q(sig0000025a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.CE(ce),
.D(sig0000026e),
.Q(sig0000025b)
);
MUXCY blk0000014c (
.CI(sig0000025d),
.DI(sig00000002),
.S(sig00000264),
.O(sig0000025c)
);
MUXCY blk0000014d (
.CI(sig0000025e),
.DI(sig00000002),
.S(sig00000265),
.O(sig0000025d)
);
MUXCY blk0000014e (
.CI(sig0000025f),
.DI(sig00000002),
.S(sig00000266),
.O(sig0000025e)
);
MUXCY blk0000014f (
.CI(sig00000260),
.DI(sig00000002),
.S(sig00000267),
.O(sig0000025f)
);
MUXCY blk00000150 (
.CI(sig00000261),
.DI(sig00000002),
.S(sig00000268),
.O(sig00000260)
);
MUXCY blk00000151 (
.CI(sig00000262),
.DI(sig00000002),
.S(sig00000269),
.O(sig00000261)
);
MUXCY blk00000152 (
.CI(sig00000263),
.DI(sig00000002),
.S(sig0000026a),
.O(sig00000262)
);
MUXCY blk00000153 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig0000026b),
.O(sig00000263)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000154 (
.I0(sig00000002),
.I1(sig0000023c),
.I2(sig0000023d),
.I3(sig0000023e),
.I4(sig0000023f),
.O(sig00000271)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000155 (
.I0(sig00000002),
.I1(sig0000023c),
.I2(sig0000023d),
.I3(sig0000023e),
.I4(sig0000023f),
.O(sig00000272)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000156 (
.I0(sig00000002),
.I1(sig00000240),
.I2(sig00000241),
.I3(sig00000242),
.I4(sig00000243),
.O(sig00000277)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000157 (
.I0(sig00000002),
.I1(sig00000240),
.I2(sig00000241),
.I3(sig00000242),
.I4(sig00000243),
.O(sig00000278)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000158 (
.I0(sig00000002),
.I1(sig00000244),
.I2(sig00000245),
.I3(sig00000246),
.I4(sig00000247),
.O(sig0000027d)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000159 (
.I0(sig00000002),
.I1(sig00000244),
.I2(sig00000245),
.I3(sig00000246),
.I4(sig00000247),
.O(sig0000027e)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk0000015a (
.I0(sig00000002),
.I1(sig00000248),
.I2(sig00000249),
.I3(sig0000024b),
.I4(sig0000024a),
.O(sig00000283)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk0000015b (
.I0(sig00000002),
.I1(sig00000248),
.I2(sig00000249),
.I3(sig0000024b),
.I4(sig0000024a),
.O(sig00000284)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(ce),
.D(sig0000026d),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.CE(ce),
.D(sig0000026c),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(ce),
.D(sig00000286),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.CE(ce),
.D(sig0000028b),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(ce),
.D(sig0000028f),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk00000161 (
.C(clk),
.CE(ce),
.D(sig00000066),
.Q(sig0000028f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(ce),
.D(sig0000025c),
.Q(sig00000287)
);
FDE #(
.INIT ( 1'b0 ))
blk00000163 (
.C(clk),
.CE(ce),
.D(sig0000025d),
.Q(sig00000288)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(ce),
.D(sig0000025e),
.Q(sig00000289)
);
FDE #(
.INIT ( 1'b0 ))
blk00000165 (
.C(clk),
.CE(ce),
.D(sig0000025f),
.Q(sig0000028a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(ce),
.D(sig00000260),
.Q(sig0000028b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000167 (
.C(clk),
.CE(ce),
.D(sig00000261),
.Q(sig0000028c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(ce),
.D(sig00000262),
.Q(sig0000028d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000169 (
.C(clk),
.CE(ce),
.D(sig00000263),
.Q(sig0000028e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(ce),
.D(sig000002a9),
.Q(sig0000024a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016b (
.C(clk),
.CE(ce),
.D(sig000002a8),
.Q(sig0000024b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(ce),
.D(sig000002a7),
.Q(sig00000249)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016d (
.C(clk),
.CE(ce),
.D(sig000002a6),
.Q(sig00000248)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(ce),
.D(sig000002a5),
.Q(sig00000247)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016f (
.C(clk),
.CE(ce),
.D(sig000002a4),
.Q(sig00000246)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(ce),
.D(sig000002a3),
.Q(sig00000245)
);
FDE #(
.INIT ( 1'b0 ))
blk00000171 (
.C(clk),
.CE(ce),
.D(sig000002a2),
.Q(sig00000244)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(ce),
.D(sig000002a1),
.Q(sig00000243)
);
FDE #(
.INIT ( 1'b0 ))
blk00000173 (
.C(clk),
.CE(ce),
.D(sig000002a0),
.Q(sig00000242)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(ce),
.D(sig0000029f),
.Q(sig00000241)
);
FDE #(
.INIT ( 1'b0 ))
blk00000175 (
.C(clk),
.CE(ce),
.D(sig0000029e),
.Q(sig00000240)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(ce),
.D(sig0000029d),
.Q(sig0000023f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000177 (
.C(clk),
.CE(ce),
.D(sig0000029c),
.Q(sig0000023e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(ce),
.D(sig0000029b),
.Q(sig0000023d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000179 (
.C(clk),
.CE(ce),
.D(sig0000029a),
.Q(sig0000023c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(ce),
.D(sig00000299),
.Q(sig0000023b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017b (
.C(clk),
.CE(ce),
.D(sig00000298),
.Q(sig0000023a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(ce),
.D(sig00000297),
.Q(sig00000239)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017d (
.C(clk),
.CE(ce),
.D(sig00000296),
.Q(sig00000238)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(ce),
.D(sig00000295),
.Q(sig00000237)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017f (
.C(clk),
.CE(ce),
.D(sig00000294),
.Q(sig00000236)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(ce),
.D(sig00000293),
.Q(sig00000235)
);
FDE #(
.INIT ( 1'b0 ))
blk00000181 (
.C(clk),
.CE(ce),
.D(sig00000292),
.Q(sig00000234)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(ce),
.D(sig00000291),
.Q(sig00000233)
);
FDE #(
.INIT ( 1'b0 ))
blk00000183 (
.C(clk),
.CE(ce),
.D(sig00000290),
.Q(sig00000232)
);
FD blk00000184 (
.C(clk),
.D(sig000002c0),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22])
);
FD blk00000185 (
.C(clk),
.D(sig000002bf),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21])
);
FD blk00000186 (
.C(clk),
.D(sig000002be),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20])
);
FD blk00000187 (
.C(clk),
.D(sig000002bd),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19])
);
FD blk00000188 (
.C(clk),
.D(sig000002bc),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18])
);
FD blk00000189 (
.C(clk),
.D(sig000002bb),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17])
);
FD blk0000018a (
.C(clk),
.D(sig000002ba),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16])
);
FD blk0000018b (
.C(clk),
.D(sig000002b9),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15])
);
FD blk0000018c (
.C(clk),
.D(sig000002b8),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14])
);
FD blk0000018d (
.C(clk),
.D(sig000002b7),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13])
);
FD blk0000018e (
.C(clk),
.D(sig000002b6),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12])
);
FD blk0000018f (
.C(clk),
.D(sig000002b5),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11])
);
FD blk00000190 (
.C(clk),
.D(sig000002b4),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10])
);
FD blk00000191 (
.C(clk),
.D(sig000002b3),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9])
);
FD blk00000192 (
.C(clk),
.D(sig000002b2),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8])
);
FD blk00000193 (
.C(clk),
.D(sig000002b1),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7])
);
FD blk00000194 (
.C(clk),
.D(sig000002b0),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6])
);
FD blk00000195 (
.C(clk),
.D(sig000002af),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5])
);
FD blk00000196 (
.C(clk),
.D(sig000002ae),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4])
);
FD blk00000197 (
.C(clk),
.D(sig000002ad),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3])
);
FD blk00000198 (
.C(clk),
.D(sig000002ac),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2])
);
FD blk00000199 (
.C(clk),
.D(sig000002ab),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1])
);
FD blk0000019a (
.C(clk),
.D(sig000002aa),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0])
);
LUT4 #(
.INIT ( 16'hAA8A ))
blk0000019b (
.I0(sig000000f3),
.I1(sig000000f5),
.I2(sig0000010f),
.I3(sig000000f4),
.O(sig000000cd)
);
LUT4 #(
.INIT ( 16'hEA2A ))
blk0000019c (
.I0(sig000000fd),
.I1(sig00000114),
.I2(sig00000115),
.I3(sig000000fe),
.O(sig000000d1)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk0000019d (
.I0(sig00000111),
.I1(sig00000112),
.I2(sig00000114),
.I3(sig00000115),
.O(sig000000c2)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000019e (
.I0(sig00000111),
.I1(sig00000112),
.I2(sig00000114),
.I3(sig00000115),
.O(sig000000c3)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk0000019f (
.I0(sig0000010f),
.I1(sig000000df),
.I2(sig000000e1),
.I3(sig000000e0),
.I4(sig000000f4),
.I5(sig000000f5),
.O(sig000000ad)
);
LUT5 #(
.INIT ( 32'h55555554 ))
blk000001a0 (
.I0(sig000000f4),
.I1(sig0000010f),
.I2(sig000000f5),
.I3(sig000000e1),
.I4(sig000000e0),
.O(sig000000af)
);
LUT5 #(
.INIT ( 32'hFFFF1504 ))
blk000001a1 (
.I0(sig000000fb),
.I1(sig000000fa),
.I2(sig000001a3),
.I3(sig000000f8),
.I4(sig000000fc),
.O(sig000000d0)
);
LUT4 #(
.INIT ( 16'h5554 ))
blk000001a2 (
.I0(sig000000fc),
.I1(sig000000fa),
.I2(sig000000f8),
.I3(sig000000fb),
.O(sig000000cf)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF55555554 ))
blk000001a3 (
.I0(sig000000f4),
.I1(sig0000010f),
.I2(sig000000df),
.I3(sig000000e1),
.I4(sig000000e0),
.I5(sig000000f5),
.O(sig000000de)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001a4 (
.I0(sig000000f5),
.I1(sig000000f4),
.O(sig000000ae)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAABAA ))
blk000001a5 (
.I0(sig000000f4),
.I1(sig0000010f),
.I2(sig000000f5),
.I3(sig000000df),
.I4(sig000000e1),
.I5(sig000000e0),
.O(sig000000dd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a6 (
.I0(sig00000003),
.I1(sig00000108),
.I2(sig00000100),
.O(sig000000b7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a7 (
.I0(sig00000003),
.I1(sig00000109),
.I2(sig00000101),
.O(sig000000b8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a8 (
.I0(sig00000003),
.I1(sig0000010a),
.I2(sig00000102),
.O(sig000000b9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a9 (
.I0(sig00000003),
.I1(sig0000010b),
.I2(sig00000103),
.O(sig000000ba)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001aa (
.I0(sig00000003),
.I1(sig0000010c),
.I2(sig00000104),
.O(sig000000bb)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ab (
.I0(sig00000003),
.I1(sig0000010d),
.I2(sig00000105),
.O(sig000000bc)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ac (
.I0(sig00000003),
.I1(sig0000010e),
.I2(sig00000106),
.O(sig000000bd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ad (
.I0(sig00000019),
.I1(sig000000fd),
.I2(sig000000fe),
.O(sig000000d3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001ae (
.I0(sig000000fe),
.I1(sig000000fd),
.O(sig000000c0)
);
LUT3 #(
.INIT ( 8'h1B ))
blk000001af (
.I0(sig00000003),
.I1(sig000000ff),
.I2(sig00000107),
.O(sig000000b6)
);
LUT4 #(
.INIT ( 16'h22F2 ))
blk000001b0 (
.I0(sig00000114),
.I1(sig00000115),
.I2(sig00000111),
.I3(sig00000112),
.O(sig000000c1)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001b1 (
.I0(sig000000fe),
.I1(sig000000fd),
.O(sig000000d2)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001b2 (
.I0(sig00000110),
.I1(sig00000113),
.O(sig0000001a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b3 (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000011a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b4 (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000011b)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b5 (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000011c)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk000001b6 (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.O(sig0000011d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b7 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000122)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b8 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000123)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b9 (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000124)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk000001ba (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.O(sig00000125)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bb (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000133)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bc (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000135)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bd (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000137)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001be (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig00000139)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bf (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000013b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c0 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000013d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c1 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig0000013f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c2 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000141)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c3 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000143)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c4 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig00000129)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c5 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000012b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c6 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000012d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c7 (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig0000012f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c8 (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000131)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c9 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000145)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001ca (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig00000128)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cb (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000012a)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cc (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000012c)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cd (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig0000012e)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001ce (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000130)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cf (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000132)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d0 (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000134)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d1 (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000136)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d2 (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig00000138)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d3 (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000013a)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d4 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000013c)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d5 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig0000013e)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d6 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000140)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d7 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000142)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d8 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000144)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001d9 (
.I0(a[30]),
.I1(b[30]),
.O(sig00000126)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000001da (
.I0(a[30]),
.I1(b[30]),
.O(sig00000127)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001db (
.I0(sig0000001c),
.I1(sig00000033),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001bc)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001dc (
.I0(sig0000001d),
.I1(sig00000034),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001bb)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001dd (
.I0(sig0000001e),
.I1(sig00000035),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001ba)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001de (
.I0(sig0000001f),
.I1(sig00000036),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b9)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001df (
.I0(sig00000020),
.I1(sig00000037),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b8)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e0 (
.I0(sig00000021),
.I1(sig00000038),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b7)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e1 (
.I0(sig00000022),
.I1(sig00000039),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b6)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e2 (
.I0(sig00000023),
.I1(sig0000003a),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b5)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e3 (
.I0(sig00000024),
.I1(sig0000003b),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e4 (
.I0(sig00000019),
.I1(sig00000049),
.I2(sig00000032),
.O(sig000001d3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e5 (
.I0(sig00000019),
.I1(sig0000003f),
.I2(sig00000028),
.O(sig000001dd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e6 (
.I0(sig00000019),
.I1(sig0000003e),
.I2(sig00000027),
.O(sig000001de)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e7 (
.I0(sig00000019),
.I1(sig0000003d),
.I2(sig00000026),
.O(sig000001df)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e8 (
.I0(sig00000019),
.I1(sig0000003c),
.I2(sig00000025),
.O(sig000001e0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e9 (
.I0(sig00000019),
.I1(sig0000003b),
.I2(sig00000024),
.O(sig000001e1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ea (
.I0(sig00000019),
.I1(sig0000003a),
.I2(sig00000023),
.O(sig000001e2)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001eb (
.I0(sig00000019),
.I1(sig00000039),
.I2(sig00000022),
.O(sig000001e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ec (
.I0(sig00000019),
.I1(sig00000038),
.I2(sig00000021),
.O(sig000001e4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ed (
.I0(sig00000019),
.I1(sig00000037),
.I2(sig00000020),
.O(sig000001e5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ee (
.I0(sig00000019),
.I1(sig00000036),
.I2(sig0000001f),
.O(sig000001e6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ef (
.I0(sig00000019),
.I1(sig00000048),
.I2(sig00000031),
.O(sig000001d4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f0 (
.I0(sig00000019),
.I1(sig00000035),
.I2(sig0000001e),
.O(sig000001e7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f1 (
.I0(sig00000019),
.I1(sig00000034),
.I2(sig0000001d),
.O(sig000001e8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f2 (
.I0(sig00000019),
.I1(sig00000033),
.I2(sig0000001c),
.O(sig000001e9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f3 (
.I0(sig00000019),
.I1(sig00000047),
.I2(sig00000030),
.O(sig000001d5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f4 (
.I0(sig00000019),
.I1(sig00000046),
.I2(sig0000002f),
.O(sig000001d6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f5 (
.I0(sig00000019),
.I1(sig00000045),
.I2(sig0000002e),
.O(sig000001d7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f6 (
.I0(sig00000019),
.I1(sig00000044),
.I2(sig0000002d),
.O(sig000001d8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f7 (
.I0(sig00000019),
.I1(sig00000043),
.I2(sig0000002c),
.O(sig000001d9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f8 (
.I0(sig00000019),
.I1(sig00000042),
.I2(sig0000002b),
.O(sig000001da)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f9 (
.I0(sig00000019),
.I1(sig00000041),
.I2(sig0000002a),
.O(sig000001db)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001fa (
.I0(sig00000019),
.I1(sig00000040),
.I2(sig00000029),
.O(sig000001dc)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001fb (
.I0(sig000001f9),
.I1(sig000001a3),
.O(sig000001bf)
);
LUT4 #(
.INIT ( 16'h1537 ))
blk000001fc (
.I0(sig0000004a),
.I1(sig00000064),
.I2(sig0000004b),
.I3(sig00000063),
.O(sig00000226)
);
LUT3 #(
.INIT ( 8'hA2 ))
blk000001fd (
.I0(sig0000022e),
.I1(sig0000022f),
.I2(sig0000022d),
.O(sig00000225)
);
LUT6 #(
.INIT ( 64'hFBEAEAEA51404040 ))
blk000001fe (
.I0(sig0000004a),
.I1(sig0000004b),
.I2(sig00000062),
.I3(sig00000063),
.I4(sig0000004c),
.I5(sig00000061),
.O(sig00000227)
);
LUT6 #(
.INIT ( 64'hFBEAEAEA51404040 ))
blk000001ff (
.I0(sig0000004a),
.I1(sig0000004b),
.I2(sig00000063),
.I3(sig00000064),
.I4(sig0000004c),
.I5(sig00000062),
.O(sig00000228)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000200 (
.I0(sig0000024b),
.I1(sig0000024a),
.O(sig00000229)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000201 (
.I0(sig00000230),
.I1(sig00000065),
.O(sig00000231)
);
LUT3 #(
.INIT ( 8'hF1 ))
blk00000202 (
.I0(sig00000059),
.I1(sig00000058),
.I2(sig00000066),
.O(sig00000264)
);
LUT3 #(
.INIT ( 8'hF1 ))
blk00000203 (
.I0(sig00000057),
.I1(sig00000056),
.I2(sig00000066),
.O(sig00000265)
);
LUT4 #(
.INIT ( 16'h0F11 ))
blk00000204 (
.I0(sig00000055),
.I1(sig00000054),
.I2(sig00000064),
.I3(sig00000066),
.O(sig00000266)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000205 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000062),
.I3(sig00000063),
.I4(sig00000066),
.O(sig00000267)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000206 (
.I0(sig0000004f),
.I1(sig0000004e),
.I2(sig0000005f),
.I3(sig0000005e),
.I4(sig00000066),
.O(sig00000269)
);
LUT5 #(
.INIT ( 32'h03030055 ))
blk00000207 (
.I0(sig0000004d),
.I1(sig0000005d),
.I2(sig0000005c),
.I3(sig0000004c),
.I4(sig00000066),
.O(sig0000026a)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000208 (
.I0(sig00000051),
.I1(sig00000050),
.I2(sig00000060),
.I3(sig00000061),
.I4(sig00000066),
.O(sig00000268)
);
LUT5 #(
.INIT ( 32'h1111000F ))
blk00000209 (
.I0(sig0000005b),
.I1(sig0000005a),
.I2(sig0000004b),
.I3(sig0000004a),
.I4(sig00000066),
.O(sig0000026b)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000020a (
.I0(sig0000028b),
.I1(sig00000289),
.I2(sig0000028d),
.O(sig00000286)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020b (
.I0(sig00000066),
.I1(sig0000005a),
.O(sig00000299)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020c (
.I0(sig00000066),
.I1(sig00000059),
.O(sig0000029a)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020d (
.I0(sig00000066),
.I1(sig00000058),
.O(sig0000029b)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020e (
.I0(sig00000066),
.I1(sig00000057),
.O(sig0000029c)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020f (
.I0(sig00000066),
.I1(sig00000056),
.O(sig0000029d)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000210 (
.I0(sig00000066),
.I1(sig00000055),
.O(sig0000029e)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000211 (
.I0(sig00000066),
.I1(sig00000064),
.I2(sig00000054),
.O(sig0000029f)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000212 (
.I0(sig00000066),
.I1(sig00000063),
.I2(sig00000053),
.O(sig000002a0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000213 (
.I0(sig00000066),
.I1(sig00000062),
.I2(sig00000052),
.O(sig000002a1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000214 (
.I0(sig00000066),
.I1(sig00000061),
.I2(sig00000051),
.O(sig000002a2)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000215 (
.I0(sig00000066),
.I1(sig00000063),
.O(sig00000290)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000216 (
.I0(sig00000066),
.I1(sig00000060),
.I2(sig00000050),
.O(sig000002a3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000217 (
.I0(sig00000066),
.I1(sig0000005f),
.I2(sig0000004f),
.O(sig000002a4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000218 (
.I0(sig00000066),
.I1(sig0000005e),
.I2(sig0000004e),
.O(sig000002a5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000219 (
.I0(sig00000066),
.I1(sig0000005d),
.I2(sig0000004d),
.O(sig000002a6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021a (
.I0(sig00000066),
.I1(sig0000005c),
.I2(sig0000004c),
.O(sig000002a7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021b (
.I0(sig00000066),
.I1(sig0000005b),
.I2(sig0000004b),
.O(sig000002a8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021c (
.I0(sig00000066),
.I1(sig0000005a),
.I2(sig0000004a),
.O(sig000002a9)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021d (
.I0(sig00000066),
.I1(sig00000062),
.O(sig00000291)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021e (
.I0(sig00000066),
.I1(sig00000061),
.O(sig00000292)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021f (
.I0(sig00000066),
.I1(sig00000060),
.O(sig00000293)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000220 (
.I0(sig00000066),
.I1(sig0000005f),
.O(sig00000294)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000221 (
.I0(sig00000066),
.I1(sig0000005e),
.O(sig00000295)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000222 (
.I0(sig00000066),
.I1(sig0000005d),
.O(sig00000296)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000223 (
.I0(sig00000066),
.I1(sig0000005c),
.O(sig00000297)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000224 (
.I0(sig00000066),
.I1(sig0000005b),
.O(sig00000298)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000225 (
.I0(sig0000023c),
.I1(sig0000023d),
.I2(sig00000288),
.I3(sig00000287),
.O(sig0000026e)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000226 (
.I0(sig0000023d),
.I1(sig00000288),
.I2(sig00000287),
.O(sig0000026f)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000227 (
.I0(sig0000023e),
.I1(sig0000023f),
.I2(sig00000289),
.I3(sig00000288),
.O(sig00000270)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000228 (
.I0(sig0000023f),
.I1(sig00000289),
.I2(sig00000288),
.O(sig00000273)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000229 (
.I0(sig00000240),
.I1(sig00000241),
.I2(sig0000028a),
.I3(sig00000289),
.O(sig00000274)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022a (
.I0(sig00000241),
.I1(sig0000028a),
.I2(sig00000289),
.O(sig00000275)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022b (
.I0(sig00000242),
.I1(sig00000243),
.I2(sig0000028b),
.I3(sig0000028a),
.O(sig00000276)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022c (
.I0(sig00000243),
.I1(sig0000028b),
.I2(sig0000028a),
.O(sig00000279)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022d (
.I0(sig00000244),
.I1(sig00000245),
.I2(sig0000028c),
.I3(sig0000028b),
.O(sig0000027a)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022e (
.I0(sig00000245),
.I1(sig0000028c),
.I2(sig0000028b),
.O(sig0000027b)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022f (
.I0(sig00000246),
.I1(sig00000247),
.I2(sig0000028d),
.I3(sig0000028c),
.O(sig0000027c)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000230 (
.I0(sig00000247),
.I1(sig0000028d),
.I2(sig0000028c),
.O(sig0000027f)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000231 (
.I0(sig00000248),
.I1(sig00000249),
.I2(sig0000028e),
.I3(sig0000028d),
.O(sig00000280)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000232 (
.I0(sig00000249),
.I1(sig0000028e),
.I2(sig0000028d),
.O(sig00000281)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000233 (
.I0(sig0000024b),
.I1(sig0000024a),
.I2(sig0000028e),
.O(sig00000282)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000234 (
.I0(sig0000028e),
.I1(sig0000024a),
.O(sig00000285)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000235 (
.I0(sig0000028f),
.I1(sig00000287),
.O(sig0000008b)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000236 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000082),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0]),
.O(sig000002aa)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000237 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000081),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1]),
.O(sig000002ab)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000238 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3]),
.O(sig000002ad)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000239 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4]),
.O(sig000002ae)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023a (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000080),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2]),
.O(sig000002ac)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023b (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5]),
.O(sig000002af)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023c (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6]),
.O(sig000002b0)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023d (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7]),
.O(sig000002b1)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023e (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007a),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8]),
.O(sig000002b2)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023f (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000079),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9]),
.O(sig000002b3)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000240 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000078),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10]),
.O(sig000002b4)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000241 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000076),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12]),
.O(sig000002b6)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000242 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000075),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13]),
.O(sig000002b7)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000243 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000077),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11]),
.O(sig000002b5)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000244 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000074),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14]),
.O(sig000002b8)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000245 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000073),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15]),
.O(sig000002b9)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000246 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000072),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16]),
.O(sig000002ba)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000247 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000071),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17]),
.O(sig000002bb)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000248 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000070),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18]),
.O(sig000002bc)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000249 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19]),
.O(sig000002bd)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024a (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21]),
.O(sig000002bf)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024b (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20]),
.O(sig000002be)
);
LUT5 #(
.INIT ( 32'h77752220 ))
blk0000024c (
.I0(ce),
.I1(sig0000000d),
.I2(sig0000000e),
.I3(sig0000006c),
.I4(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22]),
.O(sig000002c0)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000024d (
.I0(sig0000000f),
.I1(ce),
.O(sig000002c1)
);
LUT4 #(
.INIT ( 16'hF7FF ))
blk0000024e (
.I0(sig00000013),
.I1(sig00000015),
.I2(sig000000e2),
.I3(sig00000014),
.O(sig000002c2)
);
LUT6 #(
.INIT ( 64'h0000000080000000 ))
blk0000024f (
.I0(sig00000017),
.I1(sig00000018),
.I2(sig00000016),
.I3(sig00000011),
.I4(sig00000012),
.I5(sig000002c2),
.O(sig000000bf)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000250 (
.I0(sig000000f8),
.I1(sig000000f7),
.I2(sig000000f6),
.O(sig000002c3)
);
LUT5 #(
.INIT ( 32'hAA0BAA08 ))
blk00000251 (
.I0(sig000000f9),
.I1(sig000000fa),
.I2(sig000000fb),
.I3(sig000000fc),
.I4(sig000002c3),
.O(sig000000ce)
);
LUT3 #(
.INIT ( 8'h80 ))
blk00000252 (
.I0(a[25]),
.I1(a[24]),
.I2(a[23]),
.O(sig000002c4)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000253 (
.I0(a[30]),
.I1(a[29]),
.I2(a[28]),
.I3(a[27]),
.I4(a[26]),
.I5(sig000002c4),
.O(sig000000b2)
);
LUT3 #(
.INIT ( 8'hFE ))
blk00000254 (
.I0(a[25]),
.I1(a[24]),
.I2(a[23]),
.O(sig000002c5)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000255 (
.I0(a[30]),
.I1(a[29]),
.I2(a[28]),
.I3(a[27]),
.I4(a[26]),
.I5(sig000002c5),
.O(sig000000b3)
);
LUT3 #(
.INIT ( 8'h80 ))
blk00000256 (
.I0(b[25]),
.I1(b[24]),
.I2(b[23]),
.O(sig000002c6)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000257 (
.I0(b[30]),
.I1(b[29]),
.I2(b[28]),
.I3(b[27]),
.I4(b[26]),
.I5(sig000002c6),
.O(sig000000b4)
);
LUT3 #(
.INIT ( 8'hFE ))
blk00000258 (
.I0(b[25]),
.I1(b[24]),
.I2(b[23]),
.O(sig000002c7)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000259 (
.I0(b[30]),
.I1(b[29]),
.I2(b[28]),
.I3(b[27]),
.I4(b[26]),
.I5(sig000002c7),
.O(sig000000b5)
);
LUT4 #(
.INIT ( 16'hFFFE ))
blk0000025a (
.I0(sig00000013),
.I1(sig00000015),
.I2(sig00000014),
.I3(sig000000e2),
.O(sig000002c8)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000025b (
.I0(sig00000017),
.I1(sig00000018),
.I2(sig00000016),
.I3(sig00000011),
.I4(sig00000012),
.I5(sig000002c8),
.O(sig000000be)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000025c (
.I0(sig00000110),
.I1(sig00000113),
.O(sig000002c9)
);
LUT6 #(
.INIT ( 64'h0000000000008001 ))
blk0000025d (
.I0(sig00000005),
.I1(sig00000004),
.I2(sig00000003),
.I3(sig00000006),
.I4(sig000002c9),
.I5(sig000001d1),
.O(sig000001c0)
);
LUT6 #(
.INIT ( 64'h0000000000010000 ))
blk0000025e (
.I0(sig000001ed),
.I1(sig000001ee),
.I2(sig000001ef),
.I3(sig000001f0),
.I4(sig000001f7),
.I5(sig000001f1),
.O(sig000002ca)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000025f (
.I0(sig000001f3),
.I1(sig000001f2),
.I2(sig000001f4),
.I3(sig000001f5),
.I4(sig000001ea),
.I5(sig000001eb),
.O(sig000002cb)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000260 (
.I0(sig000002cb),
.I1(sig000001f6),
.I2(sig000002ca),
.I3(sig000001ec),
.O(sig000001be)
);
LUT3 #(
.INIT ( 8'h1B ))
blk00000261 (
.I0(sig0000028d),
.I1(sig00000283),
.I2(sig0000027d),
.O(sig000002cc)
);
LUT5 #(
.INIT ( 32'h8A80DFD5 ))
blk00000262 (
.I0(sig0000028b),
.I1(sig00000271),
.I2(sig00000289),
.I3(sig00000277),
.I4(sig000002cc),
.O(sig0000026c)
);
LUT3 #(
.INIT ( 8'h1B ))
blk00000263 (
.I0(sig0000028d),
.I1(sig00000284),
.I2(sig0000027e),
.O(sig000002cd)
);
LUT5 #(
.INIT ( 32'h8A80DFD5 ))
blk00000264 (
.I0(sig0000028b),
.I1(sig00000272),
.I2(sig00000289),
.I3(sig00000278),
.I4(sig000002cd),
.O(sig0000026d)
);
FDRE blk00000265 (
.C(clk),
.CE(ce),
.D(sig000002ce),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [7])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000266 (
.I0(sig00000083),
.I1(sig00000010),
.O(sig000002ce)
);
FDRE blk00000267 (
.C(clk),
.CE(ce),
.D(sig000002cf),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [6])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000268 (
.I0(sig00000084),
.I1(sig00000010),
.O(sig000002cf)
);
FDRE blk00000269 (
.C(clk),
.CE(ce),
.D(sig000002d0),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [5])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026a (
.I0(sig00000085),
.I1(sig00000010),
.O(sig000002d0)
);
FDRE blk0000026b (
.C(clk),
.CE(ce),
.D(sig000002d1),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [4])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026c (
.I0(sig00000086),
.I1(sig00000010),
.O(sig000002d1)
);
FDRE blk0000026d (
.C(clk),
.CE(ce),
.D(sig000002d2),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [3])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026e (
.I0(sig00000087),
.I1(sig00000010),
.O(sig000002d2)
);
FDRE blk0000026f (
.C(clk),
.CE(ce),
.D(sig000002d3),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [2])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000270 (
.I0(sig00000088),
.I1(sig00000010),
.O(sig000002d3)
);
FDRE blk00000271 (
.C(clk),
.CE(ce),
.D(sig000002d4),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [1])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000272 (
.I0(sig00000089),
.I1(sig00000010),
.O(sig000002d4)
);
FDRE blk00000273 (
.C(clk),
.CE(ce),
.D(sig000002d5),
.R(sig000002c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [0])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000274 (
.I0(sig0000008a),
.I1(sig00000010),
.O(sig000002d5)
);
FDE blk00000275 (
.C(clk),
.CE(ce),
.D(sig0000001b),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op )
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000276 (
.I0(sig000001d2),
.O(sig000002d6)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000277 (
.I0(sig00000019),
.I1(sig00000031),
.I2(sig00000032),
.I3(sig00000048),
.I4(sig00000049),
.O(sig00000221)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000278 (
.I0(sig00000019),
.I1(sig0000002f),
.I2(sig00000030),
.I3(sig00000046),
.I4(sig00000047),
.O(sig00000220)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000279 (
.I0(sig00000046),
.I1(sig0000002f),
.I2(sig00000021),
.I3(sig00000038),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001a9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027a (
.I0(sig00000047),
.I1(sig00000030),
.I2(sig00000022),
.I3(sig00000039),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001a8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027b (
.I0(sig00000048),
.I1(sig00000031),
.I2(sig00000023),
.I3(sig0000003a),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001a7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027c (
.I0(sig00000049),
.I1(sig00000032),
.I2(sig00000024),
.I3(sig0000003b),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001a6)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027d (
.I0(sig00000019),
.I1(sig0000002e),
.I2(sig0000002d),
.I3(sig00000045),
.I4(sig00000044),
.O(sig0000021f)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027e (
.I0(sig00000019),
.I1(sig0000002c),
.I2(sig0000002b),
.I3(sig00000043),
.I4(sig00000042),
.O(sig0000021e)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027f (
.I0(sig00000019),
.I1(sig0000002a),
.I2(sig00000029),
.I3(sig00000041),
.I4(sig00000040),
.O(sig0000021d)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000280 (
.I0(sig00000019),
.I1(sig00000028),
.I2(sig00000027),
.I3(sig0000003f),
.I4(sig0000003e),
.O(sig0000021c)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000281 (
.I0(sig00000019),
.I1(sig00000026),
.I2(sig00000025),
.I3(sig0000003d),
.I4(sig0000003c),
.O(sig0000021b)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000282 (
.I0(sig00000110),
.I1(sig00000113),
.O(sig000001fc)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000283 (
.I0(sig00000041),
.I1(sig0000002a),
.I2(sig0000001c),
.I3(sig00000033),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001ae)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000284 (
.I0(sig00000042),
.I1(sig0000002b),
.I2(sig0000001d),
.I3(sig00000034),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001ad)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000285 (
.I0(sig00000043),
.I1(sig0000002c),
.I2(sig0000001e),
.I3(sig00000035),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001ac)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000286 (
.I0(sig00000044),
.I1(sig0000002d),
.I2(sig0000001f),
.I3(sig00000036),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001ab)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000287 (
.I0(sig00000045),
.I1(sig0000002e),
.I2(sig00000020),
.I3(sig00000037),
.I4(sig00000019),
.I5(sig000001d2),
.O(sig000001aa)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk00000288 (
.I0(sig00000028),
.I1(sig0000003f),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b0)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk00000289 (
.I0(sig00000027),
.I1(sig0000003e),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b1)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk0000028a (
.I0(sig00000026),
.I1(sig0000003d),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b2)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk0000028b (
.I0(sig00000025),
.I1(sig0000003c),
.I2(sig00000019),
.I3(sig000001d2),
.O(sig000001b3)
);
LUT4 #(
.INIT ( 16'hFFD8 ))
blk0000028c (
.I0(sig00000019),
.I1(sig00000029),
.I2(sig00000040),
.I3(sig000001d2),
.O(sig000001af)
);
INV blk0000028d (
.I(sig000001d2),
.O(sig000001bd)
);
INV blk0000028e (
.I(sig000000e8),
.O(sig00000092)
);
INV blk0000028f (
.I(sig000000e9),
.O(sig00000090)
);
INV blk00000290 (
.I(sig000000ea),
.O(sig0000008e)
);
LUT6 #(
.INIT ( 64'h0818181018181810 ))
blk00000291 (
.I0(sig00000008),
.I1(sig00000007),
.I2(sig00000006),
.I3(sig0000000a),
.I4(sig00000009),
.I5(sig0000000b),
.O(sig000001d1)
);
LUT6 #(
.INIT ( 64'h666666666666666A ))
blk00000292 (
.I0(sig00000007),
.I1(sig00000006),
.I2(sig00000008),
.I3(sig00000009),
.I4(sig0000000a),
.I5(sig0000000b),
.O(sig000001d2)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk00000293 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.O(sig000001d0)
);
LUT6 #(
.INIT ( 64'h8000000000000002 ))
blk00000294 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001cf)
);
LUT6 #(
.INIT ( 64'h4001000000010004 ))
blk00000295 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001ce)
);
LUT6 #(
.INIT ( 64'h2800000000000028 ))
blk00000296 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000007),
.I3(sig00000009),
.I4(sig00000008),
.I5(sig00000006),
.O(sig000001cd)
);
LUT6 #(
.INIT ( 64'h0400400000100004 ))
blk00000297 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001cc)
);
LUT6 #(
.INIT ( 64'h0820000000000820 ))
blk00000298 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000007),
.I4(sig00000008),
.I5(sig00000006),
.O(sig000001cb)
);
LUT6 #(
.INIT ( 64'h1000040000040040 ))
blk00000299 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001ca)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk0000029a (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000008),
.I5(sig00000009),
.O(sig000001c9)
);
LUT6 #(
.INIT ( 64'h0010100004000010 ))
blk0000029b (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig00000008),
.I3(sig0000000a),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c8)
);
LUT5 #(
.INIT ( 32'h00800200 ))
blk0000029c (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.O(sig000001c7)
);
LUT6 #(
.INIT ( 64'h0400001000101000 ))
blk0000029d (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig00000008),
.I3(sig0000000a),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c6)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk0000029e (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000009),
.I5(sig00000008),
.O(sig000001c5)
);
LUT6 #(
.INIT ( 64'h0010000404004000 ))
blk0000029f (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000007),
.I5(sig00000008),
.O(sig000001c4)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk000002a0 (
.I0(sig0000000b),
.I1(sig00000006),
.I2(sig00000008),
.I3(sig00000007),
.I4(sig0000000a),
.I5(sig00000009),
.O(sig000001c3)
);
LUT6 #(
.INIT ( 64'h0010000404004000 ))
blk000002a1 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c2)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk000002a2 (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000009),
.I5(sig00000006),
.O(sig000001c1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a3 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000b0),
.Q(sig000002d7),
.Q15(NLW_blk000002a3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a4 (
.C(clk),
.CE(ce),
.D(sig000002d7),
.Q(sig000000f3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a5 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000b1),
.Q(sig000002d8),
.Q15(NLW_blk000002a5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a6 (
.C(clk),
.CE(ce),
.D(sig000002d8),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a7 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig00000157),
.Q(sig000002d9),
.Q15(NLW_blk000002a7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a8 (
.C(clk),
.CE(ce),
.D(sig000002d9),
.Q(sig000000f5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a9 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig00000156),
.Q(sig000002da),
.Q15(NLW_blk000002a9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002aa (
.C(clk),
.CE(ce),
.D(sig000002da),
.Q(sig000000f4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ab (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f0),
.Q(sig000002db),
.Q15(NLW_blk000002ab_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ac (
.C(clk),
.CE(ce),
.D(sig000002db),
.Q(sig000000e8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ad (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f2),
.Q(sig000002dc),
.Q15(NLW_blk000002ad_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ae (
.C(clk),
.CE(ce),
.D(sig000002dc),
.Q(sig000000ea)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002af (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f1),
.Q(sig000002dd),
.Q15(NLW_blk000002af_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b0 (
.C(clk),
.CE(ce),
.D(sig000002dd),
.Q(sig000000e9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b1 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ef),
.Q(sig000002de),
.Q15(NLW_blk000002b1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b2 (
.C(clk),
.CE(ce),
.D(sig000002de),
.Q(sig000000e7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b3 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ee),
.Q(sig000002df),
.Q15(NLW_blk000002b3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b4 (
.C(clk),
.CE(ce),
.D(sig000002df),
.Q(sig000000e6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b5 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ed),
.Q(sig000002e0),
.Q15(NLW_blk000002b5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b6 (
.C(clk),
.CE(ce),
.D(sig000002e0),
.Q(sig000000e5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b7 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ec),
.Q(sig000002e1),
.Q15(NLW_blk000002b7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b8 (
.C(clk),
.CE(ce),
.D(sig000002e1),
.Q(sig000000e4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b9 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig0000024b),
.Q(sig000002e2),
.Q15(NLW_blk000002b9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ba (
.C(clk),
.CE(ce),
.D(sig000002e2),
.Q(sig0000022b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bb (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000eb),
.Q(sig000002e3),
.Q15(NLW_blk000002bb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bc (
.C(clk),
.CE(ce),
.D(sig000002e3),
.Q(sig000000e3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bd (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000001f9),
.Q(sig000002e4),
.Q15(NLW_blk000002bd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002be (
.C(clk),
.CE(ce),
.D(sig000002e4),
.Q(sig000001f7)
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 1 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( 0 ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'hFF0000FFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "PATDET" ),
.USE_SIMD ( "ONE48" ))
blk000002bf (
.CEM(ce),
.PATTERNDETECT(sig00000066),
.CLK(clk),
.CARRYIN(sig000001f8),
.PATTERNBDETECT(NLW_blk000002bf_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000002),
.CEB1(sig00000002),
.MULTSIGNOUT(NLW_blk000002bf_MULTSIGNOUT_UNCONNECTED),
.CEC(ce),
.RSTM(sig00000002),
.MULTSIGNIN(sig00000002),
.CEB2(ce),
.RSTCTRL(sig00000002),
.CEP(ce),
.CARRYCASCOUT(NLW_blk000002bf_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000002),
.CECARRYIN(ce),
.UNDERFLOW(NLW_blk000002bf_UNDERFLOW_UNCONNECTED),
.RSTALUMODE(sig00000002),
.RSTALLCARRYIN(sig00000002),
.CEALUMODE(ce),
.CEA2(ce),
.CEA1(sig00000002),
.RSTB(sig00000002),
.CEMULTCARRYIN(sig00000002),
.OVERFLOW(NLW_blk000002bf_OVERFLOW_UNCONNECTED),
.CECTRL(ce),
.CARRYCASCIN(sig00000002),
.RSTP(sig00000002),
.CARRYINSEL({sig00000002, sig00000002, sig00000002}),
.OPMODE({sig00000002, sig000001a0, sig000001a0, sig00000002, sig000001a1, sig00000002, sig000001a1}),
.ALUMODE({sig00000002, sig00000002, sig000001fb, sig000001fb}),
.C({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000188, sig00000189
, sig0000018a, sig0000018b, sig0000018c, sig0000018d, sig0000018e, sig0000018f, sig00000190, sig00000191, sig00000192, sig00000193, sig00000194,
sig00000195, sig00000196, sig00000197, sig00000198, sig00000199, sig0000019a, sig0000019b, sig0000019c, sig0000019d, sig0000019e, sig0000019f,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002}),
.B({sig00000002, sig00000002, sig00000178, sig00000179, sig0000017a, sig0000017b, sig0000017c, sig0000017d, sig0000017e, sig0000017f, sig00000180
, sig00000181, sig00000182, sig00000183, sig00000184, sig00000185, sig00000186, sig00000187}),
.P({\NLW_blk000002bf_P<47>_UNCONNECTED , \NLW_blk000002bf_P<46>_UNCONNECTED , \NLW_blk000002bf_P<45>_UNCONNECTED ,
\NLW_blk000002bf_P<44>_UNCONNECTED , \NLW_blk000002bf_P<43>_UNCONNECTED , \NLW_blk000002bf_P<42>_UNCONNECTED , \NLW_blk000002bf_P<41>_UNCONNECTED ,
\NLW_blk000002bf_P<40>_UNCONNECTED , sig0000004a, sig0000004b, sig0000004c, sig0000004d, sig0000004e, sig0000004f, sig00000050, sig00000051,
sig00000052, sig00000053, sig00000054, sig00000055, sig00000056, sig00000057, sig00000058, sig00000059, sig0000005a, sig0000005b, sig0000005c,
sig0000005d, sig0000005e, sig0000005f, sig00000060, sig00000061, sig00000062, sig00000063, sig00000064, sig000001ea, sig000001eb, sig000001ec,
sig000001ed, sig000001ee, sig000001ef, sig000001f0, sig000001f1, sig000001f2, sig000001f3, sig000001f4, sig000001f5, sig000001f6}),
.A({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000160, sig00000161, sig00000162, sig00000163, sig00000164
, sig00000165, sig00000166, sig00000167, sig00000168, sig00000169, sig0000016a, sig0000016b, sig0000016c, sig0000016d, sig0000016e, sig0000016f,
sig00000170, sig00000171, sig00000172, sig00000173, sig00000174, sig00000175, sig00000176, sig00000177}),
.ACOUT({\NLW_blk000002bf_ACOUT<29>_UNCONNECTED , \NLW_blk000002bf_ACOUT<28>_UNCONNECTED , \NLW_blk000002bf_ACOUT<27>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<26>_UNCONNECTED , \NLW_blk000002bf_ACOUT<25>_UNCONNECTED , \NLW_blk000002bf_ACOUT<24>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<23>_UNCONNECTED , \NLW_blk000002bf_ACOUT<22>_UNCONNECTED , \NLW_blk000002bf_ACOUT<21>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<20>_UNCONNECTED , \NLW_blk000002bf_ACOUT<19>_UNCONNECTED , \NLW_blk000002bf_ACOUT<18>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<17>_UNCONNECTED , \NLW_blk000002bf_ACOUT<16>_UNCONNECTED , \NLW_blk000002bf_ACOUT<15>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<14>_UNCONNECTED , \NLW_blk000002bf_ACOUT<13>_UNCONNECTED , \NLW_blk000002bf_ACOUT<12>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<11>_UNCONNECTED , \NLW_blk000002bf_ACOUT<10>_UNCONNECTED , \NLW_blk000002bf_ACOUT<9>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<8>_UNCONNECTED , \NLW_blk000002bf_ACOUT<7>_UNCONNECTED , \NLW_blk000002bf_ACOUT<6>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<5>_UNCONNECTED , \NLW_blk000002bf_ACOUT<4>_UNCONNECTED , \NLW_blk000002bf_ACOUT<3>_UNCONNECTED ,
\NLW_blk000002bf_ACOUT<2>_UNCONNECTED , \NLW_blk000002bf_ACOUT<1>_UNCONNECTED , \NLW_blk000002bf_ACOUT<0>_UNCONNECTED }),
.PCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.CARRYOUT({\NLW_blk000002bf_CARRYOUT<3>_UNCONNECTED , \NLW_blk000002bf_CARRYOUT<2>_UNCONNECTED , \NLW_blk000002bf_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk000002bf_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.BCOUT({\NLW_blk000002bf_BCOUT<17>_UNCONNECTED , \NLW_blk000002bf_BCOUT<16>_UNCONNECTED , \NLW_blk000002bf_BCOUT<15>_UNCONNECTED ,
\NLW_blk000002bf_BCOUT<14>_UNCONNECTED , \NLW_blk000002bf_BCOUT<13>_UNCONNECTED , \NLW_blk000002bf_BCOUT<12>_UNCONNECTED ,
\NLW_blk000002bf_BCOUT<11>_UNCONNECTED , \NLW_blk000002bf_BCOUT<10>_UNCONNECTED , \NLW_blk000002bf_BCOUT<9>_UNCONNECTED ,
\NLW_blk000002bf_BCOUT<8>_UNCONNECTED , \NLW_blk000002bf_BCOUT<7>_UNCONNECTED , \NLW_blk000002bf_BCOUT<6>_UNCONNECTED ,
\NLW_blk000002bf_BCOUT<5>_UNCONNECTED , \NLW_blk000002bf_BCOUT<4>_UNCONNECTED , \NLW_blk000002bf_BCOUT<3>_UNCONNECTED ,
\NLW_blk000002bf_BCOUT<2>_UNCONNECTED , \NLW_blk000002bf_BCOUT<1>_UNCONNECTED , \NLW_blk000002bf_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk000002bf_PCOUT<47>_UNCONNECTED , \NLW_blk000002bf_PCOUT<46>_UNCONNECTED , \NLW_blk000002bf_PCOUT<45>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<44>_UNCONNECTED , \NLW_blk000002bf_PCOUT<43>_UNCONNECTED , \NLW_blk000002bf_PCOUT<42>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<41>_UNCONNECTED , \NLW_blk000002bf_PCOUT<40>_UNCONNECTED , \NLW_blk000002bf_PCOUT<39>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<38>_UNCONNECTED , \NLW_blk000002bf_PCOUT<37>_UNCONNECTED , \NLW_blk000002bf_PCOUT<36>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<35>_UNCONNECTED , \NLW_blk000002bf_PCOUT<34>_UNCONNECTED , \NLW_blk000002bf_PCOUT<33>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<32>_UNCONNECTED , \NLW_blk000002bf_PCOUT<31>_UNCONNECTED , \NLW_blk000002bf_PCOUT<30>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<29>_UNCONNECTED , \NLW_blk000002bf_PCOUT<28>_UNCONNECTED , \NLW_blk000002bf_PCOUT<27>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<26>_UNCONNECTED , \NLW_blk000002bf_PCOUT<25>_UNCONNECTED , \NLW_blk000002bf_PCOUT<24>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<23>_UNCONNECTED , \NLW_blk000002bf_PCOUT<22>_UNCONNECTED , \NLW_blk000002bf_PCOUT<21>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<20>_UNCONNECTED , \NLW_blk000002bf_PCOUT<19>_UNCONNECTED , \NLW_blk000002bf_PCOUT<18>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<17>_UNCONNECTED , \NLW_blk000002bf_PCOUT<16>_UNCONNECTED , \NLW_blk000002bf_PCOUT<15>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<14>_UNCONNECTED , \NLW_blk000002bf_PCOUT<13>_UNCONNECTED , \NLW_blk000002bf_PCOUT<12>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<11>_UNCONNECTED , \NLW_blk000002bf_PCOUT<10>_UNCONNECTED , \NLW_blk000002bf_PCOUT<9>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<8>_UNCONNECTED , \NLW_blk000002bf_PCOUT<7>_UNCONNECTED , \NLW_blk000002bf_PCOUT<6>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<5>_UNCONNECTED , \NLW_blk000002bf_PCOUT<4>_UNCONNECTED , \NLW_blk000002bf_PCOUT<3>_UNCONNECTED ,
\NLW_blk000002bf_PCOUT<2>_UNCONNECTED , \NLW_blk000002bf_PCOUT<1>_UNCONNECTED , \NLW_blk000002bf_PCOUT<0>_UNCONNECTED }),
.ACIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 1 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( 0 ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk000002c0 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk000002c0_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000002),
.CEB1(sig00000002),
.MULTSIGNOUT(NLW_blk000002c0_MULTSIGNOUT_UNCONNECTED),
.CEC(ce),
.RSTM(sig00000002),
.MULTSIGNIN(sig00000002),
.CEB2(ce),
.RSTCTRL(sig00000002),
.CEP(ce),
.CARRYCASCOUT(NLW_blk000002c0_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000002),
.CECARRYIN(ce),
.UNDERFLOW(NLW_blk000002c0_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk000002c0_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000002),
.RSTALLCARRYIN(sig00000002),
.CEALUMODE(ce),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000002),
.CEMULTCARRYIN(sig00000002),
.OVERFLOW(NLW_blk000002c0_OVERFLOW_UNCONNECTED),
.CECTRL(ce),
.CARRYIN(sig00000002),
.CARRYCASCIN(sig00000002),
.RSTP(sig00000002),
.CARRYINSEL({sig00000002, sig00000002, sig00000002}),
.C({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002
, sig00000002, sig00000002, sig00000011, sig00000012, sig00000013, sig00000014, sig00000015, sig00000016, sig00000017, sig00000018, sig00000001,
sig0000022b, sig0000022a, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig0000022c, sig00000002, sig00000002}),
.B({sig00000002, sig00000002, sig0000025b, sig0000025a, sig00000259, sig00000258, sig00000257, sig00000256, sig00000255, sig00000254, sig00000253
, sig00000252, sig00000251, sig00000250, sig0000024f, sig0000024e, sig0000024d, sig0000024c}),
.P({\NLW_blk000002c0_P<47>_UNCONNECTED , \NLW_blk000002c0_P<46>_UNCONNECTED , \NLW_blk000002c0_P<45>_UNCONNECTED ,
\NLW_blk000002c0_P<44>_UNCONNECTED , \NLW_blk000002c0_P<43>_UNCONNECTED , \NLW_blk000002c0_P<42>_UNCONNECTED , \NLW_blk000002c0_P<41>_UNCONNECTED ,
\NLW_blk000002c0_P<40>_UNCONNECTED , \NLW_blk000002c0_P<39>_UNCONNECTED , \NLW_blk000002c0_P<38>_UNCONNECTED , \NLW_blk000002c0_P<37>_UNCONNECTED ,
\NLW_blk000002c0_P<36>_UNCONNECTED , \NLW_blk000002c0_P<35>_UNCONNECTED , sig00000083, sig00000084, sig00000085, sig00000086, sig00000087, sig00000088
, sig00000089, sig0000008a, \NLW_blk000002c0_P<26>_UNCONNECTED , \NLW_blk000002c0_P<25>_UNCONNECTED , sig0000006c, sig0000006d, sig0000006e,
sig0000006f, sig00000070, sig00000071, sig00000072, sig00000073, sig00000074, sig00000075, sig00000076, sig00000077, sig00000078, sig00000079,
sig0000007a, sig0000007b, sig0000007c, sig0000007d, sig0000007e, sig0000007f, sig00000080, sig00000081, sig00000082,
\NLW_blk000002c0_P<1>_UNCONNECTED , \NLW_blk000002c0_P<0>_UNCONNECTED }),
.A({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000249, sig00000248, sig00000247, sig00000246, sig00000245
, sig00000244, sig00000243, sig00000242, sig00000241, sig00000240, sig0000023f, sig0000023e, sig0000023d, sig0000023c, sig0000023b, sig0000023a,
sig00000239, sig00000238, sig00000237, sig00000236, sig00000235, sig00000234, sig00000233, sig00000232}),
.ACOUT({\NLW_blk000002c0_ACOUT<29>_UNCONNECTED , \NLW_blk000002c0_ACOUT<28>_UNCONNECTED , \NLW_blk000002c0_ACOUT<27>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<26>_UNCONNECTED , \NLW_blk000002c0_ACOUT<25>_UNCONNECTED , \NLW_blk000002c0_ACOUT<24>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<23>_UNCONNECTED , \NLW_blk000002c0_ACOUT<22>_UNCONNECTED , \NLW_blk000002c0_ACOUT<21>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<20>_UNCONNECTED , \NLW_blk000002c0_ACOUT<19>_UNCONNECTED , \NLW_blk000002c0_ACOUT<18>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<17>_UNCONNECTED , \NLW_blk000002c0_ACOUT<16>_UNCONNECTED , \NLW_blk000002c0_ACOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<14>_UNCONNECTED , \NLW_blk000002c0_ACOUT<13>_UNCONNECTED , \NLW_blk000002c0_ACOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<11>_UNCONNECTED , \NLW_blk000002c0_ACOUT<10>_UNCONNECTED , \NLW_blk000002c0_ACOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<8>_UNCONNECTED , \NLW_blk000002c0_ACOUT<7>_UNCONNECTED , \NLW_blk000002c0_ACOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<5>_UNCONNECTED , \NLW_blk000002c0_ACOUT<4>_UNCONNECTED , \NLW_blk000002c0_ACOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<2>_UNCONNECTED , \NLW_blk000002c0_ACOUT<1>_UNCONNECTED , \NLW_blk000002c0_ACOUT<0>_UNCONNECTED }),
.OPMODE({sig00000002, sig00000001, sig00000001, sig00000002, sig00000001, sig00000002, sig00000001}),
.PCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.ALUMODE({sig00000002, sig00000002, sig00000002, sig00000002}),
.CARRYOUT({\NLW_blk000002c0_CARRYOUT<3>_UNCONNECTED , \NLW_blk000002c0_CARRYOUT<2>_UNCONNECTED , \NLW_blk000002c0_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk000002c0_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.BCOUT({\NLW_blk000002c0_BCOUT<17>_UNCONNECTED , \NLW_blk000002c0_BCOUT<16>_UNCONNECTED , \NLW_blk000002c0_BCOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<14>_UNCONNECTED , \NLW_blk000002c0_BCOUT<13>_UNCONNECTED , \NLW_blk000002c0_BCOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<11>_UNCONNECTED , \NLW_blk000002c0_BCOUT<10>_UNCONNECTED , \NLW_blk000002c0_BCOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<8>_UNCONNECTED , \NLW_blk000002c0_BCOUT<7>_UNCONNECTED , \NLW_blk000002c0_BCOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<5>_UNCONNECTED , \NLW_blk000002c0_BCOUT<4>_UNCONNECTED , \NLW_blk000002c0_BCOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<2>_UNCONNECTED , \NLW_blk000002c0_BCOUT<1>_UNCONNECTED , \NLW_blk000002c0_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk000002c0_PCOUT<47>_UNCONNECTED , \NLW_blk000002c0_PCOUT<46>_UNCONNECTED , \NLW_blk000002c0_PCOUT<45>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<44>_UNCONNECTED , \NLW_blk000002c0_PCOUT<43>_UNCONNECTED , \NLW_blk000002c0_PCOUT<42>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<41>_UNCONNECTED , \NLW_blk000002c0_PCOUT<40>_UNCONNECTED , \NLW_blk000002c0_PCOUT<39>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<38>_UNCONNECTED , \NLW_blk000002c0_PCOUT<37>_UNCONNECTED , \NLW_blk000002c0_PCOUT<36>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<35>_UNCONNECTED , \NLW_blk000002c0_PCOUT<34>_UNCONNECTED , \NLW_blk000002c0_PCOUT<33>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<32>_UNCONNECTED , \NLW_blk000002c0_PCOUT<31>_UNCONNECTED , \NLW_blk000002c0_PCOUT<30>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<29>_UNCONNECTED , \NLW_blk000002c0_PCOUT<28>_UNCONNECTED , \NLW_blk000002c0_PCOUT<27>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<26>_UNCONNECTED , \NLW_blk000002c0_PCOUT<25>_UNCONNECTED , \NLW_blk000002c0_PCOUT<24>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<23>_UNCONNECTED , \NLW_blk000002c0_PCOUT<22>_UNCONNECTED , \NLW_blk000002c0_PCOUT<21>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<20>_UNCONNECTED , \NLW_blk000002c0_PCOUT<19>_UNCONNECTED , \NLW_blk000002c0_PCOUT<18>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<17>_UNCONNECTED , \NLW_blk000002c0_PCOUT<16>_UNCONNECTED , \NLW_blk000002c0_PCOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<14>_UNCONNECTED , \NLW_blk000002c0_PCOUT<13>_UNCONNECTED , \NLW_blk000002c0_PCOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<11>_UNCONNECTED , \NLW_blk000002c0_PCOUT<10>_UNCONNECTED , \NLW_blk000002c0_PCOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<8>_UNCONNECTED , \NLW_blk000002c0_PCOUT<7>_UNCONNECTED , \NLW_blk000002c0_PCOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<5>_UNCONNECTED , \NLW_blk000002c0_PCOUT<4>_UNCONNECTED , \NLW_blk000002c0_PCOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<2>_UNCONNECTED , \NLW_blk000002c0_PCOUT<1>_UNCONNECTED , \NLW_blk000002c0_PCOUT<0>_UNCONNECTED }),
.ACIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_BLACKBOX_V
`define SKY130_FD_SC_HS__AND4BB_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_1_V
`define SKY130_FD_SC_HS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
|
/**********************************************************************
date:2016/3/26
designer:ZhaiShaoMin
project:ring network multicore
module name:tb_arbiter_OUT_rep
module function: figure out what's wrong with it
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_OUT_req();
//input
reg clk;
reg rst;
reg OUT_req_rdy;
reg v_ic_req;
reg v_dc_req;
reg v_mem_req;
reg [1:0] ic_req_ctrl;
reg [1:0] dc_req_ctrl;
reg [1:0] mem_req_ctrl;
//output
wire ack_OUT_req;
wire ack_ic_req;
wire ack_dc_req;
wire ack_mem_req;
wire [2:0] select; // select 1/3
arbiter_for_OUT_req uut(//input
.clk(clk),
.rst(rst),
.OUT_req_rdy(OUT_req_rdy),
.v_ic_req(v_ic_req),
.v_dc_req(v_dc_req),
.v_mem_req(v_mem_req),
.ic_req_ctrl(ic_req_ctrl),
.dc_req_ctrl(dc_req_ctrl),
.mem_req_ctrl(mem_req_ctrl),
//output
.ack_OUT_req(ack_OUT_req),
.ack_ic_req(ack_ic_req),
.ack_dc_req(ack_dc_req),
.ack_mem_req(ack_mem_req),
.select(select)
);
integer log_file;
//define task for compare expected outputs with actural outputs
task cmp_outputs;
input exp_ack_OUT_req;
input exp_ack_ic_req;
input exp_ack_dc_req;
input exp_ack_mem_req;
input [2:0] exp_select;
begin
$display("Time:%t\n",$time);
$fdisplay (log_file, "Time: %t\n", $time);
if (ack_OUT_req != exp_ack_OUT_req)
begin
$display("ERROR: Invalid ack_OUT_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
$fdisplay(log_file,"ERROR: Invalid ack_OUT_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
end
if (ack_ic_req != exp_ack_ic_req)
begin
$display("ERROR: Invalid ack_ic_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
$fdisplay(log_file,"ERROR: Invalid ack_ic_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
end
if (ack_dc_req != exp_ack_dc_req)
begin
$display("ERROR: Invalid ack_dc_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
$fdisplay(log_file,"ERROR: Invalid ack_dc_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
end
if (ack_mem_req != exp_ack_mem_req)
begin
$display("ERROR: Invalid ack_mem_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
$fdisplay(log_file,"ERROR: Invalid ack_mem_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
end
if (select != exp_select)
begin
$display("ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
$fdisplay(log_file,"ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
end
if((ack_OUT_req != exp_ack_OUT_req)&&
(ack_ic_req != exp_ack_ic_req)&&
(ack_dc_req != exp_ack_dc_req)&&
(ack_mem_req != exp_ack_mem_req)&&
(select != exp_select))
begin
$display("passed test!");
$fdisplay(log_file,"passed test!");
end
end
endtask
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b00;
mem_req_ctrl=2'b00;
log_file=$fopen("log_arbiter_for_OUT_req.txt");
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////
///////////initial actural test : arbiter_for_OUT_req ////
initial begin
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1'b0;
`clk_step
///////////////////////////////////////////////////////////////
//First case: v_ic_req ,v_dc_req and v_mem_req are all valid///
$display("First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$fdisplay(log_file,"First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b0;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("2nd try : ic should win! ");
$fdisplay(log_file,"2nd try : ic should win!");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("3rd try : ic should win! ");
$fdisplay(log_file,"3rd try : ic should win!");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("last try : ic should finish ! ");
$fdisplay(log_file,"last try : ic should finish !");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b11;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
/* `clk_step
$display("last try :just test if ic has finish and mem win ! ");
$fdisplay(log_file,"last try : if ic has finish and mem win !");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
*/
/////////////////////////////////////////////////////////////////
///////2nd case :both mem and dc are valid! and mem will win!////
/////////////////////////////////////////////////////////////////
rst=1'b1;
#7;
rst=1'b0;
#7;
//clk_step
$display("2nd case: v_dc_req and v_mem_req are valid");
$fdisplay(log_file,"2nd case: v_dc_req and v_mem_req are valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b11;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/////////////////////////////////////////////////////////////////////////////
////3rd case: both mem and dc are valid but it's dc's turn to transfer msg///
`clk_step
$display("3rd case: both mem and dc are valid but it's dc's turn to transfer msg\n also test for last try error");
$fdisplay(log_file,"3rd case: both mem and dc are valid but it's dc's turn to transfer msg\n also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
// req fifo is not ready
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
///////////////////////////////////////////////////////////////
////4th case : only dc is valid! /////
`clk_step
$display("4th case : only dc is valid!\n also test for last try error");
$fdisplay(log_file,"4th case : only dc is valid!\n also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b00;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
//req fifo is not ready
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
////////////////////////////////////////////////////////////
////5th case: only mem is valid !///////////////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b11;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/////////////////////////////////////////////////
////both mem and ic are valid ///////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b11;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
/**
* testbench.v
*/
module testbench();
import bsg_cache_non_blocking_pkg::*;
// parameters
//
parameter id_width_p = 30;
parameter addr_width_p = 32;
parameter data_width_p = 32;
parameter block_size_in_words_p = 8;
parameter sets_p = 128;
parameter ways_p = 8;
parameter miss_fifo_els_p = `MISS_FIFO_ELS_P;
parameter data_mask_width_lp=(data_width_p>>3);
parameter mem_size_p = 2**15;
parameter dma_read_delay_p = `DMA_READ_DELAY_P;
parameter dma_write_delay_p = `DMA_WRITE_DELAY_P;
parameter dma_data_delay_p = `DMA_DATA_DELAY_P;
parameter dma_req_delay_p = `DMA_REQ_DELAY_P;
parameter yumi_max_delay_p = `YUMI_MAX_DELAY_P;
parameter yumi_min_delay_p = `YUMI_MIN_DELAY_P;
localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p);
localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p);
localparam lg_block_size_in_words_lp = `BSG_SAFE_CLOG2(block_size_in_words_p);
localparam byte_sel_width_lp = `BSG_SAFE_CLOG2(data_width_p>>3);
localparam tag_width_lp = (addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp);
localparam block_offset_width_lp = lg_block_size_in_words_lp+byte_sel_width_lp;
// synopsys translate_off
integer status;
integer wave;
string checker;
initial begin
status = $value$plusargs("wave=%d",wave);
status = $value$plusargs("checker=%s",checker);
if (wave) $vcdpluson;
end
// clock and reset
//
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(100)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(8)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
// synopsys translate_on
// non-blocking cache
//
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
logic cache_v_li;
logic cache_ready_lo;
logic [id_width_p-1:0] cache_id_lo;
logic [data_width_p-1:0] cache_data_lo;
logic cache_v_lo;
logic cache_yumi_li;
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
logic [data_width_p-1:0] dma_data_li;
logic dma_data_v_li;
logic dma_data_ready_lo;
logic [data_width_p-1:0] dma_data_lo;
logic dma_data_v_lo;
logic dma_data_yumi_li;
bsg_cache_non_blocking #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.miss_fifo_els_p(miss_fifo_els_p)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.cache_pkt_i(cache_pkt)
,.v_i(cache_v_li)
,.ready_o(cache_ready_lo)
,.data_o(cache_data_lo)
,.id_o(cache_id_lo)
,.v_o(cache_v_lo)
,.yumi_i(cache_yumi_li)
,.dma_pkt_o(dma_pkt)
,.dma_pkt_v_o(dma_pkt_v_lo)
,.dma_pkt_yumi_i(dma_pkt_yumi_li)
,.dma_data_i(dma_data_li)
,.dma_data_v_i(dma_data_v_li)
,.dma_data_ready_o(dma_data_ready_lo)
,.dma_data_o(dma_data_lo)
,.dma_data_v_o(dma_data_v_lo)
,.dma_data_yumi_i(dma_data_yumi_li)
);
// synopsys translate_off
// random yumi generator
//
bsg_nonsynth_random_yumi_gen #(
.yumi_min_delay_p(yumi_min_delay_p)
,.yumi_max_delay_p(yumi_max_delay_p)
) yumi_gen (
.clk_i(clk)
,.reset_i(reset)
,.v_i(cache_v_lo)
,.yumi_o(cache_yumi_li)
);
// dma model
//
bsg_nonsynth_non_blocking_dma_model #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.els_p(4*ways_p*sets_p*block_size_in_words_p)
,.read_delay_p(dma_read_delay_p)
,.write_delay_p(dma_write_delay_p)
,.dma_data_delay_p(dma_data_delay_p)
,.dma_req_delay_p(dma_req_delay_p)
) dma_model (
.clk_i(clk)
,.reset_i(reset)
,.dma_pkt_i(dma_pkt)
,.dma_pkt_v_i(dma_pkt_v_lo)
,.dma_pkt_yumi_o(dma_pkt_yumi_li)
,.dma_data_o(dma_data_li)
,.dma_data_v_o(dma_data_v_li)
,.dma_data_ready_i(dma_data_ready_lo)
,.dma_data_i(dma_data_lo)
,.dma_data_v_i(dma_data_v_lo)
,.dma_data_yumi_o(dma_data_yumi_li)
);
// trace replay
//
localparam rom_addr_width_lp = 26;
localparam ring_width_lp =
`bsg_cache_non_blocking_pkt_width(id_width_p,addr_width_p,data_width_p);
logic [rom_addr_width_lp-1:0] trace_rom_addr;
logic [ring_width_lp+4-1:0] trace_rom_data;
logic tr_v_lo;
logic [ring_width_lp-1:0] tr_data_lo;
logic tr_yumi_li;
logic done;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) trace_replay (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(trace_rom_addr)
,.rom_data_i(trace_rom_data)
,.done_o(done)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(ring_width_lp+4)
,.addr_width_p(rom_addr_width_lp)
) test_rom (
.addr_i(trace_rom_addr)
,.data_o(trace_rom_data)
);
assign cache_pkt = tr_data_lo;
assign cache_v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & cache_ready_lo;
bind bsg_cache_non_blocking basic_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
,.mem_size_p($root.testbench.mem_size_p)
) bc (
.*
,.en_i($root.testbench.checker == "basic")
);
bind bsg_cache_non_blocking tag_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.tag_width_lp(tag_width_lp)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
) tc (
.*
,.en_i($root.testbench.checker == "tag")
);
bind bsg_cache_non_blocking ainv_checker #(
.data_width_p(data_width_p)
) ac (
.*
,.en_i($root.testbench.checker == "ainv")
);
bind bsg_cache_non_blocking block_ld_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
,.mem_size_p($root.testbench.mem_size_p)
) blc (
.*
,.en_i($root.testbench.checker == "block_ld")
);
// //
// FUNCTIONAL COVERAGE //
// //
bind bsg_cache_non_blocking cov_top _cov_top (.*);
bind bsg_cache_non_blocking_tl_stage cov_tl_stage _cov_tl_stage (.*);
bind bsg_cache_non_blocking_mhu cov_mhu _cov_mhu (.*);
bind bsg_cache_non_blocking_miss_fifo cov_miss_fifo _cov_miss_fifo (.*);
// waiting for all responses to be received.
//
integer sent_r, recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= '0;
recv_r <= '0;
end
else begin
if (cache_v_li & cache_ready_lo)
if (cache_pkt.opcode == BLOCK_LD)
sent_r <= sent_r + block_size_in_words_p;
else
sent_r <= sent_r + 1;
if (cache_v_lo & cache_yumi_li)
recv_r <= recv_r + 1;
end
end
initial begin
wait(done & (sent_r == recv_r));
$display("[BSG_FINISH] Test Successful.");
//for (integer i = 0; i < 1000000; i++)
// @(posedge clk);
#500;
$finish;
end
// synopsys translate_on
endmodule
|
`default_nettype none
module gci_std_display_vram_interface #(
parameter P_MEM_ADDR_N = 19
)(
input wire iGCI_CLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//IF0 (Priority IF0>IF1)
input wire iIF0_REQ,
output wire oIF0_ACK,
input wire iIF0_FINISH,
input wire iIF0_ENA,
output wire oIF0_BUSY,
input wire iIF0_RW,
input wire [P_MEM_ADDR_N-1:0] iIF0_ADDR,
input wire [31:0] iIF0_DATA,
output wire oIF0_VALID,
input wire iIF0_BUSY,
output wire [31:0] oIF0_DATA,
//IF1
input wire iIF1_REQ,
output wire oIF1_ACK,
input wire iIF1_FINISH,
output wire oIF1_BREAK,
input wire iIF1_ENA,
output wire oIF1_BUSY,
input wire iIF1_RW,
input wire [P_MEM_ADDR_N-1:0] iIF1_ADDR,
input wire [31:0] iIF1_DATA,
output wire oIF1_VALID,
input wire iIF1_BUSY,
output wire [31:0] oIF1_DATA,
//Vram Interface
output wire oVRAM_ARBIT_REQ,
input wire iVRAM_ARBIT_ACK,
output wire oVRAM_ARBIT_FINISH,
output wire oVRAM_ENA,
input wire iVRAM_BUSY,
output wire oVRAM_RW,
output wire [P_MEM_ADDR_N-1:0] oVRAM_ADDR,
output wire [31:0] oVRAM_DATA,
input wire iVRAM_VALID,
output wire oVRAM_BUSY,
input wire [31:0] iVRAM_DATA
);
//Main State
parameter P_L_MAIN_STT_IDLE = 2'h0;
parameter P_L_MAIN_STT_REQ = 2'h1;
parameter P_L_MAIN_STT_IF0 = 2'h2;
parameter P_L_MAIN_STT_IF1 = 2'h3;
//Main State
reg [1:0] b_main_state;
reg [1:0] b_main_if_select;
//IF 2 Memory
reg b_if2vram_req;
reg b_if2vram_finish;
reg b_if2vram_ena;
reg b_if2vram_rw;
reg [P_MEM_ADDR_N-1:0] b_if2vram_addr;
reg [31:0] b_if2vram_data;
reg b_if2vram_busy;
//Memory 2 IF0
reg b_vram2if0_ack;
reg b_vram2if0_busy;
reg b_vram2if0_valid;
reg [31:0] b_vram2if0_data;
//Memory 2 IF1
reg b_vram2if1_ack;
reg b_vram2if1_busy;
reg b_vram2if1_valid;
reg [31:0] b_vram2if1_data;
//IF0 Pryority
reg b_if0_break;
/***************************************************
State
***************************************************/
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_IDLE;
b_main_if_select <= P_L_PARAM_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_main_state <= P_L_PARAM_STT_IDLE;
b_main_if_select <= P_L_PARAM_STT_IDLE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_IDLE:
begin
if(iIF0_REQ)begin
b_main_state <= P_L_MAIN_STT_REQ;
b_main_if_select <= P_L_MAIN_STT_IF0;
end
else if(iIF1_REQ)begin
b_main_state <= P_L_MAIN_STT_REQ;
b_main_if_select <= P_L_MAIN_STT_IF1;
end
end
P_L_MAIN_STT_REQ:
begin
if(iVRAM_ARBIT_ACK)begin
b_main_state <= b_main_if_select;
end
end
P_L_MAIN_STT_IF0:
begin
if(iIF0_FINISH)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
end
P_L_MAIN_STT_IF1:
begin
if(iIF1_FINISH)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
end
default:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
endcase
end
end //main state
//IF 2 Memory
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if2vram_req <= 1'b0;
b_if2vram_finish <= 1'b0;
b_if2vram_ena <= 1'b0;
b_if2vram_rw <= 1'b0;
b_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2vram_data <= 32'h0;
b_if2vram_busy <= 1'b0;
end
else if(iRESET_SYNC)begin
b_if2vram_req <= 1'b0;
b_if2vram_finish <= 1'b0;
b_if2vram_ena <= 1'b0;
b_if2vram_rw <= 1'b0;
b_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2vram_data <= 32'h0;
b_if2vram_busy <= 1'b0;
end
else begin
if(b_main_state == P_L_MAIN_STT_IF0)begin
b_if2vram_req <= iIF0_REQ;
b_if2vram_finish <= iIF0_FINISH;
b_if2vram_ena <= iIF0_ENA;
b_if2vram_rw <= iIF0_RW;
b_if2vram_addr <= iIF0_ADDR;
b_if2vram_data <= iIF0_DATA;
b_if2vram_busy <= iIF0_BUSY;
end
else if(b_main_state == P_L_MAIN_STT_IF1)begin
b_if2vram_req <= iIF1_REQ;
b_if2vram_finish <= iIF1_FINISH;
b_if2vram_ena <= iIF1_ENA;
b_if2vram_rw <= iIF1_RW;
b_if2vram_addr <= iIF1_ADDR;
b_if2vram_data <= iIF1_DATA;
b_if2vram_busy <= iIF1_BUSY;
end
else begin
b_if2vram_req <= 1'b0;
b_if2vram_finish <= 1'b0;
b_if2vram_ena <= 1'b0;
b_if2vram_rw <= 1'b0;
b_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2vram_busy <= 1'b0;
b_if2vram_data <= 32'h0;
b_if2vram_busy <= 1'b0;
end
end
end //Output buffer alwyas
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_vram2if0_ack <= 1'b0;
b_vram2if0_busy <= 1'b0;
b_vram2if0_valid <= 1'b0;
b_vram2if0_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_vram2if0_ack <= 1'b0;
b_vram2if0_busy <= 1'b0;
b_vram2if0_valid <= 1'b0;
b_vram2if0_data <= 32'h0;
end
else begin
if(b_main_state == P_L_MAIN_STT_IF0)begin
b_vram2if0_ack <= iVRAM_ARBIT_ACK;
b_vram2if0_busy <= iVRAM_BUSY;
b_vram2if0_valid <= iVRAM_VALID;
b_vram2if0_data <= iVRAM_DATA;
end
else begin
b_vram2if0_ack <= 1'b0;
b_vram2if0_busy <= 1'b0;
b_vram2if0_valid <= 1'b0;
b_vram2if0_data <= 32'h0;
end
end
end
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_vram2if1_ack <= 1'b0;
b_vram2if1_busy <= 1'b0;
b_vram2if1_valid <= 1'b0;
b_vram2if1_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_vram2if1_ack <= 1'b0;
b_vram2if1_busy <= 1'b0;
b_vram2if1_valid <= 1'b0;
b_vram2if1_data <= 32'h0;
end
else begin
if(b_main_state == P_L_MAIN_STT_IF1)begin
b_vram2if1_ack <= iVRAM_ARBIT_ACK;
b_vram2if1_busy <= iVRAM_BUSY;
b_vram2if1_valid <= iVRAM_VALID;
b_vram2if1_data <= iVRAM_DATA;
end
else begin
b_vram2if1_ack <= 1'b0;
b_vram2if1_busy <= 1'b0;
b_vram2if1_valid <= 1'b0;
b_vram2if1_data <= 32'h0;
end
end
end
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if0_break <= 1'b0;
end
else if(iRESET_SYNC)begin
b_if0_break <= 1'b0;
end
else begin
b_if0_break <= (b_main_state == P_L_MAIN_STT_IF1) && iIF0_REQ;
end
end //Priority
assign oVRAM_ARBIT_REQ = b_if2vram_req;
assign oVRAM_ARBIT_FINISH = b_if2vram_finish;
assign oVRAM_ENA = b_if2vram_ena;
assign oVRAM_RW = b_if2vram_rw;
assign oVRAM_ADDR = b_if2vram_addr;
assign oVRAM_DATA = b_if2vram_data;
assign oVRAM_BUSY = b_if2vram_busy;
assign oIF0_ACK = b_vram2if0_ack;
assign oIF0_BUSY = b_vram2if0_busy;
assign oIF0_VALID = b_vram2if0_valid;
assign oIF0_DATA = b_vram2if0_data;
assign oIF1_ACK = b_vram2if1_ack;
assign oIF1_BREAK = b_if0_break;
assign oIF1_BUSY = b_vram2if1_busy;
assign oIF1_VALID = b_vram2if1_valid;
assign oIF1_DATA = b_vram2if1_data;
endmodule
`default_nettype wire
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_e_e
//
// Generated
// by: wig
// on: Tue Mar 30 18:39:52 2004
// cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_e_e.v,v 1.2 2006/01/19 08:50:42 wig Exp $
// $Date: 2006/01/19 08:50:42 $
// $Log: inst_e_e.v,v $
// Revision 1.2 2006/01/19 08:50:42 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
// Revision 1.1 2004/04/06 11:19:55 wig
// Adding result/autoopen
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
//
// Generator: mix_0.pl Revision: 1.28 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_e_e
//
// No `defines in this module
module inst_e_e
//
// Generated module inst_e
//
(
p_mix_s_eo3_go,
s_eo1,
s_eo2,
s_eo4,
s_eo5,
s_outname
);
// Generated Module Inputs:
input s_outname;
// Generated Module Outputs:
output p_mix_s_eo3_go;
output s_eo1;
output s_eo2;
output s_eo4;
output s_eo5;
// Generated Wires:
wire p_mix_s_eo3_go;
wire s_eo1;
wire s_eo2;
wire s_eo4;
wire s_eo5;
wire s_outname;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire s_eo3; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_s_eo3_go = s_eo3; // __I_O_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ea
inst_ea_e inst_ea(
.p_mix_s_eo1_go(s_eo1),
.p_mix_s_eo2_go(s_eo2),
.p_mix_s_eo3_go(s_eo3),
.p_mix_s_eo4_gi(s_eo4),
.p_mix_s_eo5_go(s_eo5)
);
// End of Generated Instance Port Map for inst_ea
// Generated Instance Port Map for inst_eb
inst_eb_e inst_eb(
.p_mix_s_eo2_gi(s_eo2)
);
// End of Generated Instance Port Map for inst_eb
endmodule
//
// End of Generated Module rtl of inst_e_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1 ns / 1 ps
module apsk_modulator_control #
(
// user register parameters
parameter integer BITS_PER_SYMBOL_WIDTH = 4,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// user register ports
output wire [BITS_PER_SYMBOL_WIDTH-1:0] bits_per_symbol,
output wire offset_symbol_enable,
// Global Clock Signal
input wire s_axi_aclk,
// Global Reset Signal. This Signal is Active LOW
input wire s_axi_aresetn,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2:0] s_axi_awprot,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire s_axi_awvalid,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire s_axi_awready,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire s_axi_wvalid,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire s_axi_wready,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1:0] s_axi_bresp,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire s_axi_bvalid,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire s_axi_bready,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2:0] s_axi_arprot,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire s_axi_arvalid,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire s_axi_arready,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1:0] s_axi_rresp,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire s_axi_rvalid,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire s_axi_rready
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1:0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign s_axi_awready = axi_awready;
assign s_axi_wready = axi_wready;
assign s_axi_bresp = axi_bresp;
assign s_axi_bvalid = axi_bvalid;
assign s_axi_arready = axi_arready;
assign s_axi_rdata = axi_rdata;
assign s_axi_rresp = axi_rresp;
assign s_axi_rvalid = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else begin
if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (s_axi_bready && axi_bvalid) begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_awaddr <= 0;
end
else begin
if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) begin
// Write Address latching
axi_awaddr <= s_axi_awaddr;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_wready <= 1'b0;
end
else begin
if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid;
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren) begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( s_axi_wstrb[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( s_axi_wstrb[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( s_axi_wstrb[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( s_axi_wstrb[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else begin
if (s_axi_bready && axi_bvalid) begin
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else begin
if (~axi_arready && s_axi_arvalid) begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= s_axi_araddr;
end
else begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge s_axi_aclk ) begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arready && s_axi_arvalid && ~axi_rvalid) begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && s_axi_rready) begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 :reg_data_out <= slv_reg0;
2'h1 :reg_data_out <= slv_reg1;
2'h2 :reg_data_out <= slv_reg2;
2'h3 :reg_data_out <= slv_reg3;
default:reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge s_axi_aclk )
begin
if ( s_axi_aresetn == 1'b0 ) begin
axi_rdata <= 0;
end
else begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden) begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
assign bits_per_symbol = reg_data_out[BITS_PER_SYMBOL_WIDTH-1:0];
assign offset_symbol_enable = reg_data_out[BITS_PER_SYMBOL_WIDTH];
endmodule |
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ForwardUnit(EX_RS, EX_RT, MEM_RD, WB_RD, MEM_WB, WB_WB, Forward_A, Forward_B);
input MEM_WB, WB_WB;
input [4:0] EX_RS, EX_RT, MEM_RD, WB_RD;
output [1:0] Forward_A, Forward_B;
reg [1:0] Forward_A, Forward_B;
always @(EX_RS or EX_RT)
begin
//Forward A Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RS)
begin
assign Forward_A = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RS)
begin
assign Forward_A = 2'b10;
end
else
begin
assign Forward_A = 2'b00;
end
//Forward B Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RT)
begin
assign Forward_B = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RT)
begin
assign Forward_B = 2'b10;
end
else
begin
assign Forward_B = 2'b00;
end
end
//initial begin
// assign Forward_A = 2'b00;
//assign Forward_B = 2'b00;
//end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_8_V
`define SKY130_FD_SC_HS__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_8 (
A ,
TE ,
Z ,
VPWR,
VGND
);
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_8 (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_8_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_shiftreg.v,v $
// Revision 1.6 2005/03/08 14:45:09 igorm
// Case statement improved for synthesys.
//
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "DemoInterconnect_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "DemoInterconnect_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DemoInterconnect_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 72000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_14_axi_protocol_converter #(
.C_FAMILY("artix7"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.