text
stringlengths 938
1.05M
|
|---|
//---------------------------------------------------------------------\
// scrambler module for data[31:0], lfsr[15:0]=1+x^4+x^13+x^15+x^16; |
//---------------------------------------------------------------------/
module scrambler(
input [31:0] data_in ,
input scram_en ,
input scram_rst,
output reg [31:0] data_out ,
input rst ,
output reg [31:0] data_c ,
input clk );
reg [15:0] lfsr_q,lfsr_c;
// reg [31:0] data_c;
//assign data_out = data_c ;
always @(*)
begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[10] ^
lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^ lfsr_q[15] ;
lfsr_c[1] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^
lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15] ;
lfsr_c[2] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^
lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ;
lfsr_c[3] = lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^
lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ;
lfsr_c[4] = lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^
lfsr_q[9] ^ lfsr_q[12] ;
lfsr_c[5] = lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^
lfsr_q[10] ^ lfsr_q[13] ;
lfsr_c[6] = lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^
lfsr_q[11] ^ lfsr_q[14] ;
lfsr_c[7] = lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^
lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[15] ;
lfsr_c[8] = lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^
lfsr_q[11] ^ lfsr_q[13] ;
lfsr_c[9] = lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^
lfsr_q[12] ^ lfsr_q[14] ;
lfsr_c[10] = lfsr_q[3] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^
lfsr_q[13] ^ lfsr_q[15] ;
lfsr_c[11] = lfsr_q[0] ^ lfsr_q[4] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^
lfsr_q[13] ^ lfsr_q[14] ;
lfsr_c[12] = lfsr_q[1] ^ lfsr_q[5] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^
lfsr_q[14] ^ lfsr_q[15] ;
lfsr_c[13] = lfsr_q[2] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[10] ^ lfsr_q[11] ^
lfsr_q[13] ;
lfsr_c[14] = lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[12] ^
lfsr_q[14] ;
lfsr_c[15] = lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[9] ^ lfsr_q[10] ^
lfsr_q[11] ^ lfsr_q[13] ^ lfsr_q[14] ;
data_c[0] = data_in[0] ^ lfsr_q[15] ;
data_c[1] = data_in[1] ^ lfsr_q[14] ^ lfsr_q[15] ;
data_c[2] = data_in[2] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ;
data_c[3] = data_in[3] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ;
data_c[4] = data_in[4] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15] ;
data_c[5] = data_in[5] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ;
data_c[6] = data_in[6] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13] ;
data_c[7] = data_in[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^
lfsr_q[15] ;
data_c[8] = data_in[8] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^
lfsr_q[14] ^ lfsr_q[15];
data_c[9] = data_in[9] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^
lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ;
data_c[10] = data_in[10] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[9] ^
lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ;
data_c[11] = data_in[11] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[8] ^
lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15] ;
data_c[12] = data_in[12] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[7] ^
lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^
lfsr_q[15] ;
data_c[13] = data_in[13] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[6] ^
lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13] ^
lfsr_q[14] ;
data_c[14] = data_in[14] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[5] ^
lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^
lfsr_q[13] ;
data_c[15] = data_in[15] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[4] ^
lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^
lfsr_q[12] ^ lfsr_q[15] ;
data_c[16] = data_in[16] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[6] ^
lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[11] ^
lfsr_q[14] ^ lfsr_q[15] ;
data_c[17] = data_in[17] ^ lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[5] ^ lfsr_q[6] ^
lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[13] ^
lfsr_q[14] ;
data_c[18] = data_in[18] ^ lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^
lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ;
data_c[19] = data_in[19] ^ lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^
lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[12] ;
data_c[20] = data_in[20] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[6] ^
lfsr_q[7] ^ lfsr_q[10] ^ lfsr_q[11] ;
data_c[21] = data_in[21] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[5] ^
lfsr_q[6] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[15] ;
data_c[22] = data_in[22] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[4] ^
lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[14] ^
lfsr_q[15] ;
data_c[23] = data_in[23] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[4] ^
lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[13] ^ lfsr_q[14] ^
lfsr_q[15] ;
data_c[24] = data_in[24] ^ lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[6] ^
lfsr_q[7] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ;
data_c[25] = data_in[25] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[5] ^ lfsr_q[6] ^
lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ;
data_c[26] = data_in[26] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[5] ^
lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[15] ;
data_c[27] = data_in[27] ^ lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[9] ^
lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[14] ^ lfsr_q[15] ;
data_c[28] = data_in[28] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[8] ^ lfsr_q[9] ^
lfsr_q[10] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ;
data_c[29] = data_in[29] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[7] ^ lfsr_q[8] ^
lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ;
data_c[30] = data_in[30] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[6] ^ lfsr_q[7] ^
lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^
lfsr_q[15] ;
data_c[31] = data_in[31] ^ lfsr_q[0] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^
lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^
lfsr_q[15] ;
end // always
always @(posedge clk) //, posedge rst)
begin
if(rst)
begin
lfsr_q <= {16{1'b1}};
// data_out <= {32{1'b0}};
end
else
begin
lfsr_q <= scram_rst ? {16{1'b1}} : scram_en ? lfsr_c : lfsr_q;
data_out <= scram_en ? data_c : data_out;
end
end // always
endmodule // scrambler
/*
integer fp;
initial
begin
#1;
fp = $fopen("test.txt","w");
end
always @(negedge clk)
begin
if(rst==0)
begin
// if(lfsr_c == 32'h 52325032)
// begin
$fwrite(fp,"%h\t\t%h\n",data_in,data_out);
// $stop();
// end
end
end
endmodule */ |
module tester;
reg rrst ;
reg [63:0] rdata ;
reg [31:0] rparameter_Block ;
reg [63:0] rparameter_Block2 ;
reg [7:0] rbmRequestType ;
reg [7:0] rbRequest ;
reg [15:0] rwValue ;
reg [15:0] rwIndex ;
reg [15:0] rwLength ;
reg renable ;
wire wbusy ;
wire [31:0] wdata_out;
wire [63:0] wdata_out2;
wire [15:0] wdata_out3;
reg rclk = 0;
always #1 rclk = !rclk;
always @(rclk)
begin
rdata [63:56] = rbmRequestType [7:0];
rdata [55:47]= rbRequest [7:0];
rdata [46:33] = rwValue [15:0];
rdata [32:16] = rwIndex [15:0];
rdata [15:0] = rwLength ;
end
initial begin
$dumpfile("tester.vcd");
$dumpvars(0,tester);
rrst = 1;
#5
rrst =0 ;
rdata = 0;
//rparameter_Block = 1;
// rparameter_Block2 = 12;
rbmRequestType [7:0] = 8'b00100001;
rbRequest = 8'h06 ;
rwValue = 0;
rwIndex = 5;
rwLength = 2;
renable = 1 ;
#5
rwIndex = 235;
# 513 $finish;
end
control control_intance (
.busy (wbusy),
.clk (rclk),
.rst (rrst),
.data (rdata),
.data_out32 (wdata_out),
.data_out64 (wdata_out2),
.data_out16 (wdata_out3),
.parameter_Block32 (rparameter_Block),
.parameter_Block64 (rparameter_Block2),
.enable (renable)
);
endmodule |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_blend #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-1-1:0] dadr,
input [15:0] colora,
input [15:0] colorb,
input [15:0] colorc,
input [15:0] colord,
input [5:0] x_frac,
input [5:0] y_frac,
output pipe_stb_o,
input pipe_ack_i,
output [fml_depth-1-1:0] dadr_f,
output [15:0] color
);
/* Arithmetic pipeline. Enable signal is shared to ease usage of hard macros. */
wire pipe_en;
reg valid_1;
reg [15:0] colora_1;
reg [15:0] colorb_1;
reg [15:0] colorc_1;
reg [15:0] colord_1;
reg [fml_depth-1-1:0] dadr_1;
reg valid_2;
wire [12:0] pa_2;
wire [12:0] pb_2;
wire [12:0] pc_2;
wire [12:0] pd_2;
reg [15:0] colora_2;
reg [15:0] colorb_2;
reg [15:0] colorc_2;
reg [15:0] colord_2;
reg [fml_depth-1-1:0] dadr_2;
wire [4:0] ra_2 = colora_2[15:11];
wire [5:0] ga_2 = colora_2[10:5];
wire [4:0] ba_2 = colora_2[4:0];
wire [4:0] rb_2 = colorb_2[15:11];
wire [5:0] gb_2 = colorb_2[10:5];
wire [4:0] bb_2 = colorb_2[4:0];
wire [4:0] rc_2 = colorc_2[15:11];
wire [5:0] gc_2 = colorc_2[10:5];
wire [4:0] bc_2 = colorc_2[4:0];
wire [4:0] rd_2 = colord_2[15:11];
wire [5:0] gd_2 = colord_2[10:5];
wire [4:0] bd_2 = colord_2[4:0];
reg valid_3;
reg [fml_depth-1-1:0] dadr_3;
reg valid_4;
wire [16:0] ra_4;
wire [17:0] ga_4;
wire [16:0] ba_4;
wire [16:0] rb_4;
wire [17:0] gb_4;
wire [16:0] bb_4;
wire [16:0] rc_4;
wire [17:0] gc_4;
wire [16:0] bc_4;
wire [16:0] rd_4;
wire [17:0] gd_4;
wire [16:0] bd_4;
reg [fml_depth-1-1:0] dadr_4;
reg valid_5;
reg [16:0] r_5;
reg [17:0] g_5;
reg [16:0] b_5;
reg [fml_depth-1-1:0] dadr_5;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
valid_4 <= 1'b0;
valid_5 <= 1'b0;
end else if(pipe_en) begin
valid_1 <= pipe_stb_i;
dadr_1 <= dadr;
colora_1 <= colora;
colorb_1 <= colorb;
colorc_1 <= colorc;
colord_1 <= colord;
valid_2 <= valid_1;
dadr_2 <= dadr_1;
colora_2 <= colora_1;
colorb_2 <= colorb_1;
colorc_2 <= colorc_1;
colord_2 <= colord_1;
valid_3 <= valid_2;
dadr_3 <= dadr_2;
valid_4 <= valid_3;
dadr_4 <= dadr_3;
valid_5 <= valid_4;
r_5 <= ra_4 + rb_4 + rc_4 + rd_4;
g_5 <= ga_4 + gb_4 + gc_4 + gd_4;
b_5 <= ba_4 + bb_4 + bc_4 + bd_4;
dadr_5 <= dadr_4;
end
end
tmu2_mult2 m_pa(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(7'd64 - x_frac),
.b(7'd64 - y_frac),
.p(pa_2)
);
tmu2_mult2 m_pb(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(x_frac),
.b(7'd64 - y_frac),
.p(pb_2)
);
tmu2_mult2 m_pc(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(7'd64 - x_frac),
.b(y_frac),
.p(pc_2)
);
tmu2_mult2 m_pd(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(x_frac),
.b(y_frac),
.p(pd_2)
);
tmu2_mult2 m_ra(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pa_2),
.b(ra_2),
.p(ra_4)
);
tmu2_mult2 m_ga(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pa_2),
.b(ga_2),
.p(ga_4)
);
tmu2_mult2 m_ba(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pa_2),
.b(ba_2),
.p(ba_4)
);
tmu2_mult2 m_rb(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pb_2),
.b(rb_2),
.p(rb_4)
);
tmu2_mult2 m_gb(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pb_2),
.b(gb_2),
.p(gb_4)
);
tmu2_mult2 m_bb(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pb_2),
.b(bb_2),
.p(bb_4)
);
tmu2_mult2 m_rc(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pc_2),
.b(rc_2),
.p(rc_4)
);
tmu2_mult2 m_gc(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pc_2),
.b(gc_2),
.p(gc_4)
);
tmu2_mult2 m_bc(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pc_2),
.b(bc_2),
.p(bc_4)
);
tmu2_mult2 m_rd(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pd_2),
.b(rd_2),
.p(rd_4)
);
tmu2_mult2 m_gd(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pd_2),
.b(gd_2),
.p(gd_4)
);
tmu2_mult2 m_bd(
.sys_clk(sys_clk),
.ce(pipe_en),
.a(pd_2),
.b(bd_2),
.p(bd_4)
);
/* Glue logic */
assign pipe_stb_o = valid_5;
assign dadr_f = dadr_5;
assign color = {r_5[16:12], g_5[17:12], b_5[16:12]};
assign pipe_en = ~valid_5 | pipe_ack_i;
assign pipe_ack_o = ~valid_5 | pipe_ack_i;
assign busy = valid_1 | valid_2 | valid_3 | valid_4 | valid_5;
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_buttons, input_switches, input_eth_rx, input_ps2, input_timer_stb, input_rs232_rx_stb, input_buttons_stb, input_switches_stb, input_eth_rx_stb, input_ps2_stb, input_timer_ack, input_rs232_rx_ack, input_buttons_ack, input_switches_ack, input_eth_rx_ack, input_ps2_ack, output_eth_tx, output_rs232_tx, output_leds, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
wire exception_140292293449776;
wire exception_140292292520776;
wire exception_140292291707392;
wire exception_140292291794560;
wire exception_140292291718680;
wire exception_140292290886400;
wire exception_140292291068416;
main_0 main_0_140292293449776(
.clk(clk),
.rst(rst),
.exception(exception_140292293449776),
.input_eth_in(input_eth_rx),
.input_eth_in_stb(input_eth_rx_stb),
.input_eth_in_ack(input_eth_rx_ack),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_eth_out(output_eth_tx),
.output_eth_out_stb(output_eth_tx_stb),
.output_eth_out_ack(output_eth_tx_ack));
main_1 main_1_140292292520776(
.clk(clk),
.rst(rst),
.exception(exception_140292292520776),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_140292291707392(
.clk(clk),
.rst(rst),
.exception(exception_140292291707392),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_140292291794560(
.clk(clk),
.rst(rst),
.exception(exception_140292291794560),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_4 main_4_140292291718680(
.clk(clk),
.rst(rst),
.exception(exception_140292291718680),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_140292290886400(
.clk(clk),
.rst(rst),
.exception(exception_140292290886400),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_6 main_6_140292291068416(
.clk(clk),
.rst(rst),
.exception(exception_140292291068416),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
assign exception = exception_140292293449776 || exception_140292292520776 || exception_140292291707392 || exception_140292291794560 || exception_140292291718680 || exception_140292290886400 || exception_140292291068416;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_arithm_pro (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
src_data_stream_0_V_dout,
src_data_stream_0_V_empty_n,
src_data_stream_0_V_read,
src_data_stream_1_V_dout,
src_data_stream_1_V_empty_n,
src_data_stream_1_V_read,
src_data_stream_2_V_dout,
src_data_stream_2_V_empty_n,
src_data_stream_2_V_read,
dst_rows_V_read,
dst_cols_V_read,
dst_data_stream_0_V_din,
dst_data_stream_0_V_full_n,
dst_data_stream_0_V_write,
dst_data_stream_1_V_din,
dst_data_stream_1_V_full_n,
dst_data_stream_1_V_write,
dst_data_stream_2_V_din,
dst_data_stream_2_V_full_n,
dst_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st5_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv8_1 = 8'b1;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [7:0] src_data_stream_0_V_dout;
input src_data_stream_0_V_empty_n;
output src_data_stream_0_V_read;
input [7:0] src_data_stream_1_V_dout;
input src_data_stream_1_V_empty_n;
output src_data_stream_1_V_read;
input [7:0] src_data_stream_2_V_dout;
input src_data_stream_2_V_empty_n;
output src_data_stream_2_V_read;
input [11:0] dst_rows_V_read;
input [11:0] dst_cols_V_read;
output [7:0] dst_data_stream_0_V_din;
input dst_data_stream_0_V_full_n;
output dst_data_stream_0_V_write;
output [7:0] dst_data_stream_1_V_din;
input dst_data_stream_1_V_full_n;
output dst_data_stream_1_V_write;
output [7:0] dst_data_stream_2_V_din;
input dst_data_stream_2_V_full_n;
output dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg src_data_stream_0_V_read;
reg src_data_stream_1_V_read;
reg src_data_stream_2_V_read;
reg dst_data_stream_0_V_write;
reg dst_data_stream_1_V_write;
reg dst_data_stream_2_V_write;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_22;
reg [10:0] p_5_reg_154;
wire [0:0] exitcond5_fu_170_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_69;
wire [10:0] i_V_fu_175_p2;
reg [10:0] i_V_reg_279;
wire [0:0] exitcond6_fu_185_p2;
reg [0:0] exitcond6_reg_284;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_80;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_sig_bdd_103;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [10:0] j_V_fu_190_p2;
reg [10:0] p_s_reg_143;
reg ap_sig_cseq_ST_st5_fsm_3;
reg ap_sig_bdd_127;
wire [11:0] p_cast_fu_166_p1;
wire [11:0] p_5_cast_fu_181_p1;
wire [0:0] overflow_fu_202_p3;
wire [7:0] p_Val2_s_fu_196_p2;
wire [0:0] overflow_1_fu_225_p3;
wire [7:0] p_Val2_2_fu_219_p2;
wire [0:0] overflow_2_fu_248_p3;
wire [7:0] p_Val2_4_fu_242_p2;
reg [3:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond6_fu_185_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond5_fu_170_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond6_fu_185_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond5_fu_170_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond6_fu_185_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond6_fu_185_p2 == ap_const_lv1_0))) begin
p_5_reg_154 <= j_V_fu_190_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond5_fu_170_p2 == ap_const_lv1_0))) begin
p_5_reg_154 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
p_s_reg_143 <= ap_const_lv11_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_3)) begin
p_s_reg_143 <= i_V_reg_279;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond6_reg_284 <= exitcond6_fu_185_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_279 <= i_V_fu_175_p2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0 or exitcond5_fu_170_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond5_fu_170_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond5_fu_170_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond5_fu_170_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_80)
begin
if (ap_sig_bdd_80) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_22)
begin
if (ap_sig_bdd_22) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_69)
begin
if (ap_sig_bdd_69) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_3 assign process. ///
always @ (ap_sig_bdd_127)
begin
if (ap_sig_bdd_127) begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_0;
end
end
/// dst_data_stream_0_V_write assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
dst_data_stream_0_V_write = ap_const_logic_1;
end else begin
dst_data_stream_0_V_write = ap_const_logic_0;
end
end
/// dst_data_stream_1_V_write assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
dst_data_stream_1_V_write = ap_const_logic_1;
end else begin
dst_data_stream_1_V_write = ap_const_logic_0;
end
end
/// dst_data_stream_2_V_write assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
dst_data_stream_2_V_write = ap_const_logic_1;
end else begin
dst_data_stream_2_V_write = ap_const_logic_0;
end
end
/// src_data_stream_0_V_read assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
src_data_stream_0_V_read = ap_const_logic_1;
end else begin
src_data_stream_0_V_read = ap_const_logic_0;
end
end
/// src_data_stream_1_V_read assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
src_data_stream_1_V_read = ap_const_logic_1;
end else begin
src_data_stream_1_V_read = ap_const_logic_0;
end
end
/// src_data_stream_2_V_read assign process. ///
always @ (exitcond6_reg_284 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond6_reg_284 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
src_data_stream_2_V_read = ap_const_logic_1;
end else begin
src_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or exitcond5_fu_170_p2 or exitcond6_fu_185_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_103 or ap_reg_ppiten_pp0_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond5_fu_170_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond6_fu_185_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_103 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond6_fu_185_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st5_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_sig_bdd_103 assign process. ///
always @ (src_data_stream_0_V_empty_n or src_data_stream_1_V_empty_n or src_data_stream_2_V_empty_n or dst_data_stream_0_V_full_n or dst_data_stream_1_V_full_n or dst_data_stream_2_V_full_n or exitcond6_reg_284)
begin
ap_sig_bdd_103 = (((src_data_stream_0_V_empty_n == ap_const_logic_0) & (exitcond6_reg_284 == ap_const_lv1_0)) | ((exitcond6_reg_284 == ap_const_lv1_0) & (src_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond6_reg_284 == ap_const_lv1_0) & (src_data_stream_2_V_empty_n == ap_const_logic_0)) | ((exitcond6_reg_284 == ap_const_lv1_0) & (dst_data_stream_0_V_full_n == ap_const_logic_0)) | ((exitcond6_reg_284 == ap_const_lv1_0) & (dst_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond6_reg_284 == ap_const_lv1_0) & (dst_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_127 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_127 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_22 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_22 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_69 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_69 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_80 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_80 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign dst_data_stream_0_V_din = ((overflow_fu_202_p3)? ap_const_lv8_FF: p_Val2_s_fu_196_p2);
assign dst_data_stream_1_V_din = ((overflow_1_fu_225_p3)? ap_const_lv8_FF: p_Val2_2_fu_219_p2);
assign dst_data_stream_2_V_din = ((overflow_2_fu_248_p3)? ap_const_lv8_FF: p_Val2_4_fu_242_p2);
assign exitcond5_fu_170_p2 = (p_cast_fu_166_p1 == dst_rows_V_read? 1'b1: 1'b0);
assign exitcond6_fu_185_p2 = (p_5_cast_fu_181_p1 == dst_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_175_p2 = (p_s_reg_143 + ap_const_lv11_1);
assign j_V_fu_190_p2 = (p_5_reg_154 + ap_const_lv11_1);
assign overflow_1_fu_225_p3 = src_data_stream_1_V_dout[ap_const_lv32_7];
assign overflow_2_fu_248_p3 = src_data_stream_2_V_dout[ap_const_lv32_7];
assign overflow_fu_202_p3 = src_data_stream_0_V_dout[ap_const_lv32_7];
assign p_5_cast_fu_181_p1 = p_5_reg_154;
assign p_Val2_2_fu_219_p2 = src_data_stream_1_V_dout << ap_const_lv8_1;
assign p_Val2_4_fu_242_p2 = src_data_stream_2_V_dout << ap_const_lv8_1;
assign p_Val2_s_fu_196_p2 = src_data_stream_0_V_dout << ap_const_lv8_1;
assign p_cast_fu_166_p1 = p_s_reg_143;
endmodule //image_filter_arithm_pro
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_4/sky130_fd_sc_hs__u_mux_4.v"
`celldefine
module sky130_fd_sc_hs__mux4 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
// Local signals
wire u_mux_40_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_4_2 u_mux_40 (u_mux_40_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_40_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_1_V
`define SKY130_FD_SC_HDLL__A222OI_1_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a222oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a222oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a222oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_1_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll54.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll54 (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
//altpll_component.clk0_phase_shift = "0", // 0°
//altpll_component.clk0_phase_shift = "2315", // 45°
altpll_component.clk0_phase_shift = "4629", // 90°
//altpll_component.clk0_phase_shift = "6944", // 135°
//altpll_component.clk0_phase_shift = "9259", // 180°
//altpll_component.clk0_phase_shift = "11574", // 225°
//altpll_component.clk0_phase_shift = "13889", // 270°
//altpll_component.clk0_phase_shift = "16204", // 315°
//altpll_component.clk0_phase_shift = "16975", // 330°
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 18518,
altpll_component.intended_device_family = "Cyclone 10 LP",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll54",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "54.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "54.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "180.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll54.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "18518"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll54_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "tutorial_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "tutorial_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=4,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000043c1000000000000430000000000000043c000000000000041600000,C_M_AXI_ADDR_WIDTH=0x00000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x00000001000000010000000100000001,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(4),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(256'H0000000043c1000000000000430000000000000043c000000000000041600000),
.C_M_AXI_ADDR_WIDTH(128'H00000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(128'H00000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(4'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(4'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(4'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(4'HF),
.m_axi_ruser(4'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// tb201.v - A WCI::AXI test bench with BFM, DUT, and Monitor/Observer
// Copyright (c) 2010 Atomic Rules LLC - ALL RIGHTS RESERVED
//
// This testbench instances three components, and provides them with a common clock and reset
// These three components are connected together with the WCI0_ signal group
// 1. A BFM "Initiator" which initiates WCI cycles
// 2. A DUT "Taget" which completes WCI cycles
// 3. A Monitor/Observer which watches ober the WCI cycles
`timescale 1ns/1ps
module tb201 ();
reg CLK; // System Clock
reg RST_N; // System Reset (active-low)
always begin // Clock generation...
#5; CLK = 1'b0;
#5; CLK = 1'b1;
end
initial begin: initblock
integer i;
localparam resetCycles = 16;
#0 RST_N = 1'b0; $display("reset asserted, RST_N=0");
for (i=0;i<resetCycles;i=i+1) @(posedge CLK);
#0 RST_N = 1'b1; $display("reset released, RST_N=1");
end
// WCI0_ WCI::AXI Wires to interconnect the BFM, DUT and Monitor...
wire WCI0_ACLK = CLK; // Connect system clock to WCI0 Link
wire WCI0_ARESETn;
wire WCI0_AWVALID;
wire WCI0_AWREADY;
wire [31:0] WCI0_AWADDR;
wire [2:0] WCI0_AWPROT;
wire WCI0_WVALID;
wire WCI0_WREADY;
wire [31:0] WCI0_WDATA;
wire [3:0] WCI0_WSTRB;
wire WCI0_BVALID;
wire WCI0_BREADY;
wire [1:0] WCI0_BRESP;
wire WCI0_ARVALID;
wire WCI0_ARREADY;
wire [31:0] WCI0_ARADDR;
wire [2:0] WCI0_ARPROT;
wire WCI0_RVALID;
wire WCI0_RREADY;
wire [31:0] WCI0_RDATA;
wire [1:0] WCI0_RRESP;
mkWciAxiInitiator bfm ( // Instance the BFM Initiator...
.CLK (CLK),
.RST_N (RST_N),
.wciM0_ACLK (WCI0_ACLK),
.RST_N_wciM0_ARESETn (WCI0_ARESETn), // WCI0_MReset_n is the reset source for this WCI0 link
.wciM0_AWVALID (WCI0_AWVALID),
.wciM0_AWREADY (WCI0_AWREADY),
.wciM0_AWADDR (WCI0_AWADDR),
.wciM0_AWPROT (WCI0_AWPROT),
.wciM0_WVALID (WCI0_WVALID),
.wciM0_WREADY (WCI0_WREADY),
.wciM0_WDATA (WCI0_WDATA),
.wciM0_WSTRB (WCI0_WSTRB),
.wciM0_BVALID (WCI0_BVALID),
.wciM0_BREADY (WCI0_BREADY),
.wciM0_BRESP (WCI0_BRESP),
.wciM0_ARVALID (WCI0_ARVALID),
.wciM0_ARREADY (WCI0_ARVALID),
.wciM0_ARADDR (WCI0_ARADDR),
.wciM0_ARPROT (WCI0_ARPROT),
.wciM0_RVALID (WCI0_RVALID),
.wciM0_RREADY (WCI0_RREADY),
.wciM0_RDATA (WCI0_RDATA),
.wciM0_RRESP (WCI0_RRESP)
);
mkWciAxiTarget dut ( // Instance the DUT Target...
.wciS0_ACLK (WCI0_ACLK),
.wciS0_ARESETn (WCI0_ARESETn),
.wciS0_AWVALID (WCI0_AWVALID),
.wciS0_AWREADY (WCI0_AWREADY),
.wciS0_AWADDR (WCI0_AWADDR),
.wciS0_AWPROT (WCI0_AWPROT),
.wciS0_WVALID (WCI0_WVALID),
.wciS0_WREADY (WCI0_WREADY),
.wciS0_WDATA (WCI0_WDATA),
.wciS0_WSTRB (WCI0_WSTRB),
.wciS0_BVALID (WCI0_BVALID),
.wciS0_BREADY (WCI0_BREADY),
.wciS0_BRESP (WCI0_BRESP),
.wciS0_ARVALID (WCI0_ARVALID),
.wciS0_ARREADY (WCI0_ARVALID),
.wciS0_ARADDR (WCI0_ARADDR),
.wciS0_ARPROT (WCI0_ARPROT),
.wciS0_RVALID (WCI0_RVALID),
.wciS0_RREADY (WCI0_RREADY),
.wciS0_RDATA (WCI0_RDATA),
.wciS0_RRESP (WCI0_RRESP)
);
mkWciAxiMonitor mon( // Instance the Monitor/Observer...
.wciO0_ACLK (WCI0_ACLK),
.wciO0_ARESETn (WCI0_ARESETn),
.wciO0_AWVALID (WCI0_AWVALID),
.wciO0_AWREADY (WCI0_AWREADY),
.wciO0_AWADDR (WCI0_AWADDR),
.wciO0_AWPROT (WCI0_AWPROT),
.wciO0_WVALID (WCI0_WVALID),
.wciO0_WREADY (WCI0_WREADY),
.wciO0_WDATA (WCI0_WDATA),
.wciO0_WSTRB (WCI0_WSTRB),
.wciO0_BVALID (WCI0_BVALID),
.wciO0_BREADY (WCI0_BREADY),
.wciO0_BRESP (WCI0_BRESP),
.wciO0_ARVALID (WCI0_ARVALID),
.wciO0_ARREADY (WCI0_ARVALID),
.wciO0_ARADDR (WCI0_ARADDR),
.wciO0_ARPROT (WCI0_ARPROT),
.wciO0_RVALID (WCI0_RVALID),
.wciO0_RREADY (WCI0_RREADY),
.wciO0_RDATA (WCI0_RDATA),
.wciO0_RRESP (WCI0_RRESP)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_HS__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_SYMBOL_V
|
`define ROMMatrix_NOP 4'h0
`define ROMMatrix_LDR 4'h1
`define ROMMatrix_LDC 4'h2
`define ROMMatrix_State_Reset 2'h0
`define ROMMatrix_State_Ready 2'h1
`define ROMMatrix_State_Error 2'h2
module ROMMatrix(clock,reset,inst,inst_en,out,rom_addr,rom_data_o);
parameter ROMRows = 8;
parameter ROMCols = 8;
parameter ROMDataSize = 8;
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [ROMDataSize-1:0] out;
output wire [15:0] rom_addr;
input wire [ROMDataSize-1:0] rom_data_o;
reg [1:0] s_State;
reg [7:0] s_ROMRow;
reg [7:0] s_ROMCol;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign rom_addr = s_ROMRow * ROMCols + s_ROMCol;
assign out = rom_data_o;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
always @ (posedge clock) begin
if (reset) begin
s_State <= `ROMMatrix_State_Reset;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
else begin
case (s_State)
`ROMMatrix_State_Reset: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
`ROMMatrix_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`ROMMatrix_NOP: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= s_ROMCol;
end
`ROMMatrix_LDR: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= w_InstImm;
s_ROMCol <= s_ROMCol;
end
`ROMMatrix_LDC: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= w_InstImm;
end
default: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= s_ROMCol;
end // else: !if(inst_en)
end // case: `ROMMatrix_State_Ready
`ROMMatrix_State_Error: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
default: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`ROMMatrix_NOP: begin
$sformat(d_Input,"EN NOP");
end
`ROMMatrix_LDR: begin
$sformat(d_Input,"EN (LDR %D)",w_InstImm);
end
`ROMMatrix_LDC: begin
$sformat(d_Input,"EN (LDC %D)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`ROMMatrix_State_Reset: begin
$sformat(d_State,"X");
end
`ROMMatrix_State_Ready: begin
$sformat(d_State,"R %D %D %D",s_ROMRow,s_ROMCol,rom_addr);
end
`ROMMatrix_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // ROMMatrix
|
`include "bsg_defines.v"
module bsg_fsb_to_nasti_slave_connector
import bsg_fsb_pkg::RingPacketType;
import bsg_nasti_pkg::bsg_nasti_addr_channel_s;
import bsg_nasti_pkg::bsg_nasti_write_data_channel_s;
import bsg_nasti_pkg::bsg_nasti_read_data_channel_s;
import bsg_nasti_pkg::bsg_nasti_write_response_channel_s;
#(parameter ring_width_p=$bits(bsg_fsb_pkg::RingPacketType)
, destid_p="inv")
(
input clk_i
, input reset_i
, output bsg_nasti_addr_channel_s nasti_read_addr_ch_o
, input logic nasti_read_addr_ch_ready_i
, output bsg_nasti_addr_channel_s nasti_write_addr_ch_o
, input logic nasti_write_addr_ch_ready_i
, output bsg_nasti_write_data_channel_s nasti_write_data_ch_o
, input logic nasti_write_data_ch_ready_i
, input bsg_nasti_read_data_channel_s nasti_read_data_ch_i
, output logic nasti_read_data_ch_ready_o
, input bsg_nasti_write_response_channel_s nasti_write_resp_ch_i
, output logic nasti_write_resp_ch_ready_o
// from fsb
, input fsb_v_i
, input [ring_width_p-1:0] fsb_data_i
, output logic fsb_ready_o
// to fsb
, output logic fsb_v_o
, output logic [ring_width_p-1:0] fsb_data_o
, input fsb_yumi_i
);
// first buffer all of the signals with a fifo
// because we cannot reliable assert ready without
// inspecting the input packets
logic [ring_width_p-1:0] in_fifo_data;
logic in_fifo_yumi;
logic in_fifo_v;
bsg_two_fifo #( .width_p(ring_width_p)) fifo_in
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(fsb_ready_o)
,.v_i (fsb_v_i )
,.data_i (fsb_data_i )
,.v_o (in_fifo_v)
,.data_o(in_fifo_data)
,.yumi_i(in_fifo_yumi)
);
RingPacketType ring_data_in, ring_data_out;
// demultiplex incoming data
assign ring_data_in = in_fifo_data;
// handle channels going to nasti
// we demultiplex packets going from fsb to nasti
always @(*)
begin
nasti_read_addr_ch_o.v = 1'b0;
nasti_read_addr_ch_o.addr = ring_data_in.data[31:0];
nasti_read_addr_ch_o.id = ring_data_in.data[32+:5];
nasti_read_addr_ch_o.size = 3'b11; // fixme; hardcode this to correct val
nasti_read_addr_ch_o.len = 8'b111; // fixme; hardcode this to correct val
nasti_write_addr_ch_o.v = 1'b0;
nasti_write_addr_ch_o.addr = ring_data_in.data[31:0];
nasti_write_addr_ch_o.id = ring_data_in.data[32+:5];
nasti_write_addr_ch_o.size = 3'b11; // fixme; hardcode this to correct val
nasti_write_addr_ch_o.len = 8'b111; // fixme; hardcode this to correct val
nasti_write_data_ch_o.v = 1'b0;
nasti_write_data_ch_o.data = ring_data_in.data[63:0];
nasti_write_data_ch_o.strb = 8'b1111_1111; // fixme; hardcode this to correct val
nasti_write_data_ch_o.last = 1'b0;
in_fifo_yumi = 1'b0;
if (in_fifo_v & ~ring_data_in.cmd)
begin
// note, these are only requests from master to slave
unique casez (ring_data_in.opcode)
// read request addr
7'b000_0100:
begin
nasti_read_addr_ch_o.v = 1'b1;
in_fifo_yumi = nasti_read_addr_ch_ready_i;
end
// write request addr
7'b000_0101:
begin
nasti_write_addr_ch_o.v = 1'b1;
in_fifo_yumi = nasti_write_addr_ch_ready_i;
end
// write request data not last
7'b000_0110:
begin
nasti_write_data_ch_o.v = 1'b1;
in_fifo_yumi = nasti_write_data_ch_ready_i;
end
// write request data last
7'b000_0111:
begin
nasti_write_data_ch_o.v = 1'b1;
nasti_write_data_ch_o.last = 1'b1;
in_fifo_yumi = nasti_write_data_ch_ready_i;
end
default:
begin
$display("*** %m unmatched opcode for fsb_to_nasti_slave",ring_data_in.opcode);
end
endcase // unique casez {
end // if (in_fifo_v && ring_data_in.cmd)
end // always @ (*)
logic out_fifo_ready;
RingPacketType out_fifo_data;
logic out_fifo_v;
bsg_two_fifo #( .width_p(ring_width_p)) fifo_out
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(out_fifo_ready)
,.v_i (out_fifo_v )
,.data_i (out_fifo_data )
,.v_o (fsb_v_o )
,.data_o(fsb_data_o)
,.yumi_i(fsb_yumi_i)
);
// these are channels coming in from nasti slave
// we need to multiplex them onto the FSB
// interconnect. what's more important, read
// responses or write responses?
assign out_fifo_data = ring_data_out;
always @(*)
begin
out_fifo_v = nasti_read_data_ch_i.v
| nasti_write_resp_ch_i.v;
ring_data_out.data = nasti_read_data_ch_i.data;
ring_data_out.cmd = 1'b0;
// per AXI4 spec, valid must be continuously asserted
// once first asserted
// but not so for ready signal
nasti_read_data_ch_ready_o = 1'b0;
nasti_write_resp_ch_ready_o = 1'b0;
if (nasti_read_data_ch_i.v)
begin : rd
ring_data_out.opcode[6] = 1'b1;
ring_data_out.opcode[5] = nasti_read_data_ch_i.last;
ring_data_out.opcode[4:0] = nasti_read_data_ch_i.id;
nasti_read_data_ch_ready_o = out_fifo_ready;
end
else
begin : wr
ring_data_out.opcode=7'b0001000;
nasti_write_resp_ch_ready_o = out_fifo_ready;
ring_data_out.data[4:0] = nasti_write_resp_ch_i.id;
ring_data_out.data[6:5] = nasti_write_resp_ch_i.resp;
// fixme: where does the ID go?
end
ring_data_out.srcid = 4'b0; // fixme
// we have a hardcoded destid_p, which is okay
// because this thing will be in FPGA
ring_data_out.destid = destid_p ;
end // always @ (*)
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:58:29 05/12/2015
// Design Name:
// Module Name: sbox5
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox5(
Bin,
BSout
);
input [6:1] Bin;
output reg [4:1] BSout;
wire [6:1] offset;
assign offset = {Bin[6], Bin[1], Bin[5 : 2]};
always @(offset)
begin
case (offset)
6'b000000: BSout <= 4'd2;
6'b000001: BSout <= 4'd12;
6'b000010: BSout <= 4'd4;
6'b000011: BSout <= 4'd1;
6'b000100: BSout <= 4'd7;
6'b000101: BSout <= 4'd10;
6'b000110: BSout <= 4'd11;
6'b000111: BSout <= 4'd6;
6'b001000: BSout <= 4'd8;
6'b001001: BSout <= 4'd5;
6'b001010: BSout <= 4'd3;
6'b001011: BSout <= 4'd15;
6'b001100: BSout <= 4'd13;
6'b001101: BSout <= 4'd0;
6'b001110: BSout <= 4'd14;
6'b001111: BSout <= 4'd9;
6'b010000: BSout <= 4'd14;
6'b010001: BSout <= 4'd11;
6'b010010: BSout <= 4'd2;
6'b010011: BSout <= 4'd12;
6'b010100: BSout <= 4'd4;
6'b010101: BSout <= 4'd7;
6'b010110: BSout <= 4'd13;
6'b010111: BSout <= 4'd1;
6'b011000: BSout <= 4'd5;
6'b011001: BSout <= 4'd0;
6'b011010: BSout <= 4'd15;
6'b011011: BSout <= 4'd10;
6'b011100: BSout <= 4'd3;
6'b011101: BSout <= 4'd9;
6'b011110: BSout <= 4'd8;
6'b011111: BSout <= 4'd6;
6'b100000: BSout <= 4'd4;
6'b100001: BSout <= 4'd2;
6'b100010: BSout <= 4'd1;
6'b100011: BSout <= 4'd11;
6'b100100: BSout <= 4'd10;
6'b100101: BSout <= 4'd13;
6'b100110: BSout <= 4'd7;
6'b100111: BSout <= 4'd8;
6'b101000: BSout <= 4'd15;
6'b101001: BSout <= 4'd9;
6'b101010: BSout <= 4'd12;
6'b101011: BSout <= 4'd5;
6'b101100: BSout <= 4'd6;
6'b101101: BSout <= 4'd3;
6'b101110: BSout <= 4'd0;
6'b101111: BSout <= 4'd14;
6'b110000: BSout <= 4'd11;
6'b110001: BSout <= 4'd8;
6'b110010: BSout <= 4'd12;
6'b110011: BSout <= 4'd7;
6'b110100: BSout <= 4'd1;
6'b110101: BSout <= 4'd14;
6'b110110: BSout <= 4'd2;
6'b110111: BSout <= 4'd13;
6'b111000: BSout <= 4'd6;
6'b111001: BSout <= 4'd15;
6'b111010: BSout <= 4'd0;
6'b111011: BSout <= 4'd9;
6'b111100: BSout <= 4'd10;
6'b111101: BSout <= 4'd4;
6'b111110: BSout <= 4'd5;
6'b111111: BSout <= 4'd3;
default: BSout <= 4'd0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_4_V
`define SKY130_FD_SC_LS__BUF_4_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_4_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DEFENDER_BROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("DEFENDER_BROM.mif"),
.C_INIT_FILE("DEFENDER_BROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// soc_system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 188 at 2015.01.20.10:18:05
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_1 (
output wire [7:0] hps_0_f2h_axi_slave_awid, // hps_0_f2h_axi_slave.awid
output wire [31:0] hps_0_f2h_axi_slave_awaddr, // .awaddr
output wire [3:0] hps_0_f2h_axi_slave_awlen, // .awlen
output wire [2:0] hps_0_f2h_axi_slave_awsize, // .awsize
output wire [1:0] hps_0_f2h_axi_slave_awburst, // .awburst
output wire [1:0] hps_0_f2h_axi_slave_awlock, // .awlock
output wire [3:0] hps_0_f2h_axi_slave_awcache, // .awcache
output wire [2:0] hps_0_f2h_axi_slave_awprot, // .awprot
output wire [4:0] hps_0_f2h_axi_slave_awuser, // .awuser
output wire hps_0_f2h_axi_slave_awvalid, // .awvalid
input wire hps_0_f2h_axi_slave_awready, // .awready
output wire [7:0] hps_0_f2h_axi_slave_wid, // .wid
output wire [127:0] hps_0_f2h_axi_slave_wdata, // .wdata
output wire [15:0] hps_0_f2h_axi_slave_wstrb, // .wstrb
output wire hps_0_f2h_axi_slave_wlast, // .wlast
output wire hps_0_f2h_axi_slave_wvalid, // .wvalid
input wire hps_0_f2h_axi_slave_wready, // .wready
input wire [7:0] hps_0_f2h_axi_slave_bid, // .bid
input wire [1:0] hps_0_f2h_axi_slave_bresp, // .bresp
input wire hps_0_f2h_axi_slave_bvalid, // .bvalid
output wire hps_0_f2h_axi_slave_bready, // .bready
output wire [7:0] hps_0_f2h_axi_slave_arid, // .arid
output wire [31:0] hps_0_f2h_axi_slave_araddr, // .araddr
output wire [3:0] hps_0_f2h_axi_slave_arlen, // .arlen
output wire [2:0] hps_0_f2h_axi_slave_arsize, // .arsize
output wire [1:0] hps_0_f2h_axi_slave_arburst, // .arburst
output wire [1:0] hps_0_f2h_axi_slave_arlock, // .arlock
output wire [3:0] hps_0_f2h_axi_slave_arcache, // .arcache
output wire [2:0] hps_0_f2h_axi_slave_arprot, // .arprot
output wire [4:0] hps_0_f2h_axi_slave_aruser, // .aruser
output wire hps_0_f2h_axi_slave_arvalid, // .arvalid
input wire hps_0_f2h_axi_slave_arready, // .arready
input wire [7:0] hps_0_f2h_axi_slave_rid, // .rid
input wire [127:0] hps_0_f2h_axi_slave_rdata, // .rdata
input wire [1:0] hps_0_f2h_axi_slave_rresp, // .rresp
input wire hps_0_f2h_axi_slave_rlast, // .rlast
input wire hps_0_f2h_axi_slave_rvalid, // .rvalid
output wire hps_0_f2h_axi_slave_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
input wire hps_only_master_clk_reset_reset_bridge_in_reset_reset, // hps_only_master_clk_reset_reset_bridge_in_reset.reset
input wire hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] hps_only_master_master_address, // hps_only_master_master.address
output wire hps_only_master_master_waitrequest, // .waitrequest
input wire [3:0] hps_only_master_master_byteenable, // .byteenable
input wire hps_only_master_master_read, // .read
output wire [31:0] hps_only_master_master_readdata, // .readdata
output wire hps_only_master_master_readdatavalid, // .readdatavalid
input wire hps_only_master_master_write, // .write
input wire [31:0] hps_only_master_master_writedata // .writedata
);
wire hps_only_master_master_translator_avalon_universal_master_0_waitrequest; // hps_only_master_master_agent:av_waitrequest -> hps_only_master_master_translator:uav_waitrequest
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_readdata; // hps_only_master_master_agent:av_readdata -> hps_only_master_master_translator:uav_readdata
wire hps_only_master_master_translator_avalon_universal_master_0_debugaccess; // hps_only_master_master_translator:uav_debugaccess -> hps_only_master_master_agent:av_debugaccess
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_address; // hps_only_master_master_translator:uav_address -> hps_only_master_master_agent:av_address
wire hps_only_master_master_translator_avalon_universal_master_0_read; // hps_only_master_master_translator:uav_read -> hps_only_master_master_agent:av_read
wire [3:0] hps_only_master_master_translator_avalon_universal_master_0_byteenable; // hps_only_master_master_translator:uav_byteenable -> hps_only_master_master_agent:av_byteenable
wire hps_only_master_master_translator_avalon_universal_master_0_readdatavalid; // hps_only_master_master_agent:av_readdatavalid -> hps_only_master_master_translator:uav_readdatavalid
wire hps_only_master_master_translator_avalon_universal_master_0_lock; // hps_only_master_master_translator:uav_lock -> hps_only_master_master_agent:av_lock
wire hps_only_master_master_translator_avalon_universal_master_0_write; // hps_only_master_master_translator:uav_write -> hps_only_master_master_agent:av_write
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_writedata; // hps_only_master_master_translator:uav_writedata -> hps_only_master_master_agent:av_writedata
wire [2:0] hps_only_master_master_translator_avalon_universal_master_0_burstcount; // hps_only_master_master_translator:uav_burstcount -> hps_only_master_master_agent:av_burstcount
wire hps_only_master_master_agent_cp_valid; // hps_only_master_master_agent:cp_valid -> router:sink_valid
wire [119:0] hps_only_master_master_agent_cp_data; // hps_only_master_master_agent:cp_data -> router:sink_data
wire hps_only_master_master_agent_cp_ready; // router:sink_ready -> hps_only_master_master_agent:cp_ready
wire hps_only_master_master_agent_cp_startofpacket; // hps_only_master_master_agent:cp_startofpacket -> router:sink_startofpacket
wire hps_only_master_master_agent_cp_endofpacket; // hps_only_master_master_agent:cp_endofpacket -> router:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_valid; // hps_0_f2h_axi_slave_agent:write_rp_valid -> router_001:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_write_rp_data; // hps_0_f2h_axi_slave_agent:write_rp_data -> router_001:sink_data
wire hps_0_f2h_axi_slave_agent_write_rp_ready; // router_001:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
wire hps_0_f2h_axi_slave_agent_write_rp_startofpacket; // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> router_001:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_endofpacket; // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> router_001:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_valid; // hps_0_f2h_axi_slave_agent:read_rp_valid -> router_002:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_read_rp_data; // hps_0_f2h_axi_slave_agent:read_rp_data -> router_002:sink_data
wire hps_0_f2h_axi_slave_agent_read_rp_ready; // router_002:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
wire hps_0_f2h_axi_slave_agent_read_rp_startofpacket; // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> router_002:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_endofpacket; // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> router_002:sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_only_master_master_limiter:cmd_sink_valid
wire [119:0] router_src_data; // router:src_data -> hps_only_master_master_limiter:cmd_sink_data
wire router_src_ready; // hps_only_master_master_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> hps_only_master_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> hps_only_master_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> hps_only_master_master_limiter:cmd_sink_endofpacket
wire [119:0] hps_only_master_master_limiter_cmd_src_data; // hps_only_master_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire hps_only_master_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_only_master_master_limiter:cmd_src_ready
wire [1:0] hps_only_master_master_limiter_cmd_src_channel; // hps_only_master_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_only_master_master_limiter_cmd_src_startofpacket; // hps_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire hps_only_master_master_limiter_cmd_src_endofpacket; // hps_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_only_master_master_limiter:rsp_sink_valid
wire [119:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_only_master_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // hps_only_master_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_only_master_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_only_master_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_only_master_master_limiter:rsp_sink_endofpacket
wire hps_only_master_master_limiter_rsp_src_valid; // hps_only_master_master_limiter:rsp_src_valid -> hps_only_master_master_agent:rp_valid
wire [119:0] hps_only_master_master_limiter_rsp_src_data; // hps_only_master_master_limiter:rsp_src_data -> hps_only_master_master_agent:rp_data
wire hps_only_master_master_limiter_rsp_src_ready; // hps_only_master_master_agent:rp_ready -> hps_only_master_master_limiter:rsp_src_ready
wire [1:0] hps_only_master_master_limiter_rsp_src_channel; // hps_only_master_master_limiter:rsp_src_channel -> hps_only_master_master_agent:rp_channel
wire hps_only_master_master_limiter_rsp_src_startofpacket; // hps_only_master_master_limiter:rsp_src_startofpacket -> hps_only_master_master_agent:rp_startofpacket
wire hps_only_master_master_limiter_rsp_src_endofpacket; // hps_only_master_master_limiter:rsp_src_endofpacket -> hps_only_master_master_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [119:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [119:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [119:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [119:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
wire [227:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:write_cp_ready -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_data
wire cmd_mux_001_src_ready; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
wire [227:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:read_cp_ready -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_valid
wire [227:0] router_001_src_data; // router_001:src_data -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_data
wire router_001_src_ready; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [119:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_valid
wire [227:0] router_002_src_data; // router_002:src_data -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_data
wire router_002_src_ready; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire [119:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire [1:0] hps_only_master_master_limiter_cmd_valid_data; // hps_only_master_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) hps_only_master_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_only_master_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.uav_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (hps_only_master_master_address), // avalon_anti_master_0.address
.av_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.av_byteenable (hps_only_master_master_byteenable), // .byteenable
.av_read (hps_only_master_master_read), // .read
.av_readdata (hps_only_master_master_readdata), // .readdata
.av_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.av_write (hps_only_master_master_write), // .write
.av_writedata (hps_only_master_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (104),
.PKT_QOS_L (104),
.PKT_DATA_SIDEBAND_H (102),
.PKT_DATA_SIDEBAND_L (102),
.PKT_ADDR_SIDEBAND_H (101),
.PKT_ADDR_SIDEBAND_L (97),
.PKT_BURST_TYPE_H (96),
.PKT_BURST_TYPE_L (95),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (94),
.PKT_BURST_SIZE_L (92),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (103),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (91),
.PKT_BURSTWRAP_L (83),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (511),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hps_only_master_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (hps_only_master_master_translator_avalon_universal_master_0_address), // av.address
.av_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.av_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (hps_only_master_master_agent_cp_valid), // cp.valid
.cp_data (hps_only_master_master_agent_cp_data), // .data
.cp_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (hps_only_master_master_agent_cp_ready), // .ready
.rp_valid (hps_only_master_master_limiter_rsp_src_valid), // rp.valid
.rp_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rp_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (hps_only_master_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_slave_ni #(
.PKT_QOS_H (212),
.PKT_QOS_L (212),
.PKT_THREAD_ID_H (215),
.PKT_THREAD_ID_L (215),
.PKT_RESPONSE_STATUS_H (224),
.PKT_RESPONSE_STATUS_L (223),
.PKT_BEGIN_BURST (211),
.PKT_CACHE_H (222),
.PKT_CACHE_L (219),
.PKT_DATA_SIDEBAND_H (210),
.PKT_DATA_SIDEBAND_L (210),
.PKT_ADDR_SIDEBAND_H (209),
.PKT_ADDR_SIDEBAND_L (205),
.PKT_BURST_TYPE_H (204),
.PKT_BURST_TYPE_L (203),
.PKT_PROTECTION_H (218),
.PKT_PROTECTION_L (216),
.PKT_BURST_SIZE_H (202),
.PKT_BURST_SIZE_L (200),
.PKT_BURSTWRAP_H (199),
.PKT_BURSTWRAP_L (191),
.PKT_BYTE_CNT_H (190),
.PKT_BYTE_CNT_L (182),
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_TRANS_EXCLUSIVE (181),
.PKT_TRANS_LOCK (180),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.PKT_DATA_H (127),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_SRC_ID_H (213),
.PKT_SRC_ID_L (213),
.PKT_DEST_ID_H (214),
.PKT_DEST_ID_L (214),
.PKT_ORI_BURST_SIZE_L (225),
.PKT_ORI_BURST_SIZE_H (227),
.ADDR_USER_WIDTH (5),
.DATA_USER_WIDTH (1),
.ST_DATA_W (228),
.ADDR_WIDTH (32),
.RDATA_WIDTH (128),
.WDATA_WIDTH (128),
.ST_CHANNEL_W (2),
.AXI_SLAVE_ID_W (8),
.PASS_ID_TO_SLAVE (0),
.AXI_VERSION ("AXI3"),
.WRITE_ACCEPTANCE_CAPABILITY (8),
.READ_ACCEPTANCE_CAPABILITY (8)
) hps_0_f2h_axi_slave_agent (
.aclk (clk_0_clk_clk), // clock_sink.clk
.aresetn (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // reset_sink.reset_n
.read_cp_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // read_cp.valid
.read_cp_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.read_cp_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.read_cp_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.read_cp_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // .endofpacket
.write_cp_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // write_cp.ready
.write_cp_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.write_cp_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.write_cp_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.write_cp_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // read_rp.ready
.read_rp_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.read_rp_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.read_rp_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.write_rp_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // write_rp.ready
.write_rp_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.write_rp_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.awid (hps_0_f2h_axi_slave_awid), // altera_axi_master.awid
.awaddr (hps_0_f2h_axi_slave_awaddr), // .awaddr
.awlen (hps_0_f2h_axi_slave_awlen), // .awlen
.awsize (hps_0_f2h_axi_slave_awsize), // .awsize
.awburst (hps_0_f2h_axi_slave_awburst), // .awburst
.awlock (hps_0_f2h_axi_slave_awlock), // .awlock
.awcache (hps_0_f2h_axi_slave_awcache), // .awcache
.awprot (hps_0_f2h_axi_slave_awprot), // .awprot
.awuser (hps_0_f2h_axi_slave_awuser), // .awuser
.awvalid (hps_0_f2h_axi_slave_awvalid), // .awvalid
.awready (hps_0_f2h_axi_slave_awready), // .awready
.wid (hps_0_f2h_axi_slave_wid), // .wid
.wdata (hps_0_f2h_axi_slave_wdata), // .wdata
.wstrb (hps_0_f2h_axi_slave_wstrb), // .wstrb
.wlast (hps_0_f2h_axi_slave_wlast), // .wlast
.wvalid (hps_0_f2h_axi_slave_wvalid), // .wvalid
.wready (hps_0_f2h_axi_slave_wready), // .wready
.bid (hps_0_f2h_axi_slave_bid), // .bid
.bresp (hps_0_f2h_axi_slave_bresp), // .bresp
.bvalid (hps_0_f2h_axi_slave_bvalid), // .bvalid
.bready (hps_0_f2h_axi_slave_bready), // .bready
.arid (hps_0_f2h_axi_slave_arid), // .arid
.araddr (hps_0_f2h_axi_slave_araddr), // .araddr
.arlen (hps_0_f2h_axi_slave_arlen), // .arlen
.arsize (hps_0_f2h_axi_slave_arsize), // .arsize
.arburst (hps_0_f2h_axi_slave_arburst), // .arburst
.arlock (hps_0_f2h_axi_slave_arlock), // .arlock
.arcache (hps_0_f2h_axi_slave_arcache), // .arcache
.arprot (hps_0_f2h_axi_slave_arprot), // .arprot
.aruser (hps_0_f2h_axi_slave_aruser), // .aruser
.arvalid (hps_0_f2h_axi_slave_arvalid), // .arvalid
.arready (hps_0_f2h_axi_slave_arready), // .arready
.rid (hps_0_f2h_axi_slave_rid), // .rid
.rdata (hps_0_f2h_axi_slave_rdata), // .rdata
.rresp (hps_0_f2h_axi_slave_rresp), // .rresp
.rlast (hps_0_f2h_axi_slave_rlast), // .rlast
.rvalid (hps_0_f2h_axi_slave_rvalid), // .rvalid
.rready (hps_0_f2h_axi_slave_rready) // .rready
);
soc_system_mm_interconnect_1_router router (
.sink_ready (hps_only_master_master_agent_cp_ready), // sink.ready
.sink_valid (hps_only_master_master_agent_cp_valid), // .valid
.sink_data (hps_only_master_master_agent_cp_data), // .data
.sink_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_001 (
.sink_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_002 (
.sink_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (16),
.PIPELINED (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.REORDER (0)
) hps_only_master_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_only_master_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_only_master_master_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_only_master_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_only_master_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_only_master_master_limiter_cmd_valid_data) // cmd_valid.data
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_only_master_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.sink_data (hps_only_master_master_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_only_master_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: helloworld.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To create a *very* simple UART test program, which can be used
// as the top level design file of any FPGA program.
//
// With some modifications (discussed below), this RTL should be able to
// run as a top-level testing file, requiring only the UART and clock pin
// to work.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
// }}}
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// {{{
//
// Two versions of the UART can be found in the rtl directory: a full featured
// UART, and a LITE UART that only handles 8N1 -- no break sending, break
// detection, parity error detection, etc. If we set USE_LITE_UART here, those
// simplified UART modules will be used.
// }}}
// `define USE_LITE_UART
//
`default_nettype none
//
module helloworld #(
// {{{
// Here we set i_setup to something appropriate to create a
// 115200 Baud UART system from a 100MHz clock. This also sets
// us to an 8-bit data word, 1-stop bit, and no parity. This
// will be overwritten by i_setup, but at least it gives us
// something to start with/from.
// Verilator lint_off UNUSED
parameter INITIAL_UART_SETUP = 31'd868
// Verilator lint_on UNUSED
// }}}
) (
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg [7:0] message [0:15];
reg pwr_reset;
reg [27:0] counter;
wire tx_break, tx_busy;
reg tx_stb;
reg [3:0] tx_index;
reg [7:0] tx_data;
wire cts_n;
// }}}
// i_setup
// {{{
`ifdef OPT_STANDALONE
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
assign i_setup = INITIAL_UART_SETUP;
`endif
// }}}
// pwr_reset
// {{{
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// Initialize the message
// {{{
initial begin
message[ 0] = "H";
message[ 1] = "e";
message[ 2] = "l";
message[ 3] = "l";
message[ 4] = "o";
message[ 5] = ",";
message[ 6] = " ";
message[ 7] = "W";
message[ 8] = "o";
message[ 9] = "r";
message[10] = "l";
message[11] = "d";
message[12] = "!";
message[13] = " ";
message[14] = "\r";
message[15] = "\n";
end
// }}}
// Send a Hello World message to the transmitter
// {{{
initial counter = 28'hffffff0;
always @(posedge i_clk)
counter <= counter + 1'b1;
assign tx_break = 1'b0;
initial tx_index = 4'h0;
always @(posedge i_clk)
if ((tx_stb)&&(!tx_busy))
tx_index <= tx_index + 1'b1;
always @(posedge i_clk)
tx_data <= message[tx_index];
initial tx_stb = 1'b0;
always @(posedge i_clk)
if (&counter)
tx_stb <= 1'b1;
else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
tx_stb <= 1'b0;
// }}}
// The UART transmitter
// {{{
// Bypass any hardware flow control
assign cts_n = 1'b0;
`ifdef USE_LITE_UART
txuartlite
#(24'd868)
transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
`else
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
`endif
// }}}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_2_V
`define SKY130_FD_SC_LS__DLRBP_2_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_2_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_0_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This file contains only Doxygen documentation.
*/
/*! \file documentation.v
* \brief ao68000 Doxygen documentation.
*/
/*! \mainpage
* <table border=0 width=100%><tr><td>
* OpenCores ao68000 IP Core.
* \author Aleksander Osman, <[email protected]>
* \date 11.12.2010
* \version 1.1
* </td><td>
* \image html ./doc/img/opencores.jpg
* </td></tr></table>
*
* <table border=0 width=100%><tr><td>
* <b>Contents:</b>
* - <a href="./../../specification.pdf">Specification</a>, automatically generated from:
* - \subpage page_spec_revisions,
* - \subpage page_spec_introduction,
* - \subpage page_spec_architecture,
* - \subpage page_spec_operation,
* - \subpage page_spec_registers,
* - \subpage page_spec_clocks,
* - \subpage page_spec_ports,
* - \subpage page_spec_references.
* - \subpage page_directory,
* - \subpage page_tool,
* - \subpage page_verification,
* - \subpage page_mc68000,
* - \subpage page_old_notes,
* - \subpage page_microcode_compilation,
* - \subpage page_microcode_operations,
* - \subpage page_microcode,
* - \subpage page_soc_linux.
* </td><td>
* \image html ./doc/img/wishbone_compatible.png
* </td></tr></table>
*
* <b>Structure Diagram:</b>
* \image html structure.png
*
* <b>About the documentation:</b>
* The ao68000 core documentation is generated by the Doxygen tool
* (www.doxygen.org) with the doxverilog patch
* (http://developer.berlios.de/projects/doxverilog/).
*/
/*! \page page_spec_revisions Revision History
* <table width=100%>
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td>Rev. </td><td>Date </td><td>Author </td><td>Description </td></tr>
* <tr><td>1.0 </td><td>28.03.2010 </td><td>Aleksander Osman </td><td>First Draft </td></tr>
* <tr><td>1.1 </td><td>11.12.2010 </td><td>Aleksander Osman </td><td>DBcc opcode microcode fix. Wishbone SEL signal fix. Project directory structure simplification.</td></tr>
* <tr><td>1.2 </td><td>15.01.2011 </td><td>Aleksander Osman, Frederic Requin</td><td>Core area optimization: biggest gain in ALU multiplication and division reimplementation.</td></tr>
* </table>
*/
/*! \page page_spec_introduction Introduction
*
* The OpenCores ao68000 IP Core is a Motorola MC68000 compatible processor.
*
* <h3>Features</h3>
* - CISC processor with microcode,
* - WISHBONE revision B.3 compatible MASTER interface,
* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
* - Uses about 4810 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
* (\ref page_verification). The result of execution was compared,
* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
* is automatically extracted from the Doxygen HTML output.
*
* <h3>WISHBONE compatibility</h3>
* - Version: WISHBONE specification Revision B.3,
* - General description: 32-bit WISHBONE Master interface,
* - WISHBONE signals described in \ref page_spec_ports,
* - Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction,
* Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,
* - Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt,
* - Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector,
* - WISHBONE data port size: 32-bit,
* - Data port granularity: 8-bits,
* - Data port maximum operand size: 32-bits,
* - Data transfer ordering: BIG ENDIAN,
* - Data transfer sequencing: UNDEFINED,
* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 90 MHz.
*
* <h3>Use</h3>
* - The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(http://opencores.org/project,aoocs).
* - It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <tt>init</tt> program lookup (\ref page_soc_linux).
*
* <h3>Similar projects</h3>
* Other free soft-core implementations of M68000 microprocessor include:
* - OpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core,
* - Suska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software,
* - OpenCores K68 (http://www.opencores.org/project,k68) - no user and supervisor modes distinction, executes most instructions, but not all.
* - OpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010.
*
* <h3>Limitations</h3>
* - Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
* - TRACE not tested,
* - The core is still large compared to other implementations.
*
* <h3>TODO</h3>
* - Optimize the desgin and microcode,
* - Count the exact cycle count for every instruction,
* - Test TRACE,
* - Write more documentation.
*
* <h3>Status</h3>
* - April 2010: Tested with WinUAE software MC68000 emulator,
* - April 2010: Booted Linux kernel up to <tt>init</tt> process lookup,
* - December 2010: Runs as a processor in OpenCores aoOCS project,
* - January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
*
* <h3>Requirements</h3>
* - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
* - Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
* - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
* - Java runtime (http://java.sun.com) is required to run the <tt>ao68000_tool</tt> (\ref page_tool),
* - Java SDK (http://java.sun.com) is required to compile the <tt>ao68000_tool</tt> (\ref page_tool),
* - Altera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the <tt>soc_for_linux</tt> System-on-Chip
* (\ref page_soc_linux).
*
* <h3>Glossary</h3>
* - <b>ao68000</b> - the ao68000 IP Core processor,
* - <b>MC68000</b> - the original Motorola MC68000 processor.
*/
/*! \page page_spec_architecture Architecture
* <table border=0 align=center>
* <caption>
* <b>Figure 1:</b> Simplified block diagram of ao68000 top module.
* </caption> <tr><td>
* \image html ./doc/img/architecture.png
* </td></tr></table>
* <h3>ao68000</h3>
* \copydoc ao68000
*
* <h3>bus_control</h3>
* \copydoc bus_control
*
* <h3>registers</h3>
* \copydoc registers
*
* <h3>memory_registers</h3>
* \copydoc memory_registers
*
* <h3>decoder</h3>
* \copydoc decoder
*
* <h3>condition</h3>
* \copydoc condition
*
* <h3>alu</h3>
* \copydoc alu
*
* <h3>microcode_branch</h3>
* \copydoc microcode_branch
*/
/*! \page page_directory Directory structure
* The ao68000 project consists of the following directories:
*
* \verbinclude ./doc/src/directory.txt
*/
/*! \page page_tool ao68000_tool documentation
*
* The ao68000_tool is used to:
* - generate a microcode operations Java file, which contains all available microcode operations (\ref page_microcode_operations):
* <tt>./sw/ao68000_tool/src/ao68000_tool/Parser.java</tt>. It is generated from <tt>./rtl/ao68000.v</tt>,
* - generate microcode for ao680000 (\ref page_microcode_compilation) with microcode locations. The microcode
* is generated and stored into an Altera MIF format file located at:
* <tt>./rtl/ao68000_microcode.mif</tt>. The microcode locations are
* inserted into:<tt>./rtl/ao68000.v</tt>
* - run and compare the results of ao68000 RTL simulation of
* <tt>./tests/compare_with_winuae/verilog/tb_ao68000</tt> with the software MC68000
* emulation of <tt>./tests/compare_with_winuae/winuae/ao</tt> (\ref page_verification),
* - extract the specification contents from Doxygen HTML output, to generate the specification ODT file.
*
* The tool is located at: <tt>./sw/ao68000_tool.jar</tt>.
*/
/*! \page page_verification Processor verification
* The ao68000 IP Core is verified with the WinUAE MC68000 software emulator.
* The verification is based on the idea that given the same contents of:
* - every register in the processor,
* - all memory locations that are read during execution,
*
* the result of execution, that is the contents of:
* - every register in the processor,
* - all memory locations written during execution,
*
* should be the same for the IP Core and the software emulator.
*
* <h3>Verification procedure</h3>
* The verification is performed in the following way:
* - the WinUAE MC68000 software emulator is compiled. The sources of the emulator are located at: <tt>./tests/compare_with_winuae/winuae/</tt>.
* The compiled binary is located at: <tt>./tmp/compare_with_winuae/winuae/ao</tt>.
* - the ao68000 testbench is compiled. The sources of the testbench are located at: <tt>./tests/compare_with_winuae/verilog/</tt>.
* The compiled Icarus Verilog script is located at: <tt>./tmp/compare_with_winuae/verilog/tb_ao68000</tt>.
* - Both of the above executable programs accept arguments that specify the values of:
* - memory locations that are read during execution,
* - the contents of every register in the processor.
* - The result of executing both of the programs is the contents of:
* - memory locations written during execution,
* - the contents of every register in the processor after execution.
* - The tool <tt>./sw/ao68000_tool/</tt> (\ref page_tool) is used to run both of the executable programs and
* compare the result of execution. The tool is capable of executing multiple concurrent simulations in order to utilize current
* multicore processors.
*
* The makefile with instructions to perform the above operations is located at: <tt>./Makefile</tt>.
*
* <h3>Requirements</h3>
* - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
* - Access to Altera Quartus II instalation (directory eda/sim_lib/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
* - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
* - Java SDK (http://java.sun.com) is required to compile the <tt>ao68000_tool</tt> (\ref page_tool),
* - Java runtime (http://java.sun.com) is required to run the <tt>ao68000_tool</tt> (\ref page_tool).
*/
/*! \page page_mc68000 MC68000 notes
* \verbinclude ./doc/src/mc68000.txt
*/
/*! \page page_old_notes Old ao68000 notes
* \verbinclude ./doc/src/old_notes.txt
*/
/*! \page page_microcode_compilation Microcode compilation
* The ao68000 microcode is represented as an Java program. Execution of this program results in generating the binary
* microcode.
*
* <h3>Microcode operations</h3>
* All possible microcode operations are described at the beginning of <tt>./rtl/ao68000.v</tt>.
* The locations of:
* - each operation in the microcode word,
* - every procedure in the microcode
*
* are auto-generated and inserted to the same file. All the available operation are also represented as Java functions and
* saved in an auto-generated file, located at <tt>./sw/ao68000_tool/Parser.java</tt> (\ref page_microcode_operations).
* This auto-generated data is generated by the tool <tt>./sw/ao68000_tool/</tt> (\ref page_tool).
*
* <h3>Microcode compilation</h3>
* The source for the microcode is located at <tt>./sw/ao68000_tool/Microcode.java</tt> (\ref page_microcode).
*
* The compiled microcode, in Altera MIF format, is located at <tt>./rtl/ao68000_microcode.mif</tt>.
*
* The tool <tt>./sw/ao68000_tool/</tt> (\ref page_tool) is used to compile the microcode source and transform it into a MIF file.
* The makefile containing instructions for performing the compilation is located at <tt>./Makefile</tt>.
*/
/*! \page page_microcode_operations Microcode operations
* The listing below represents operations available in the \ref page_microcode. It is taken from:
* <tt>./sw/ao68000_tool/Parser.java</tt>. More information about the microcode structure and compilation is available at
* \ref page_microcode_compilation.
*
* \include ./sw/ao68000_tool/Parser.java
*/
/*! \page page_microcode Microcode
* The listing below represents the microcode.
* It is taken from <tt>./sw/ao68000_tool/Microcode.java</tt>. More information about the microcode structure and
* compilation is available at \ref page_microcode_compilation.
*
* \include ./sw/ao68000_tool/Microcode.java
*/
/*! \page page_spec_operation Operation
* The ao68000 IP Core is designed to operate in a similar way as the original MC68000. The most import differences are:
* - the core IO ports are compatible with the WISHBONE specification,
* - the execution of instructions in the ao68000 core is not cycle-exact with the original MC68000 and usually takes a few cycles longer.
*
* <h3>Setting up the core</h3>
* The ao68000 IP Core has an WISHBONE MASTER interface. All standard memory access bus cycles conform to the WISHBONE specification.
* These cycles include:
* - instruction fetch,
* - data read,
* - data write.
*
* The cycles are either Single, Block or Read-Modify-Write (for the TAS instruction). When waiting to finish a bus cycle
* the ao68000 reacts on the following input signals:
* - ACK_I: the cycle is completed successfully,
* - RTY_I: the cycle is immediately repeated, the processor does not continue its operation before the current bus cycle is finished.
* In case of the Read-Modify-Write cycle - only the current bus cycle is repeated: either the read or write.
* - ERR_I: the cycle is terminated and a bus error is processed. In case of double bus error the processor enters the blocked state.
*
* There is also a special bus cycle: the interrupt acknowledge cycle. This cycle is a reaction on receiving a external interrupt from
* the ipl_i inputs. The processor only samples the ipl_i lines after processing an instruction, so the interrupt lines have to be asserted
* for some time before the core reacts. The interrupt acknowledge cycle is performed in the following way:
* - ADR_O is set to { 27'b111_1111_1111_1111_1111_1111_1111, 3 bits indicating the interrupt priority level for this cycle },
* - SEL_O is set to 4'b1111,
* - fc_o is set to 3'b111 to indicate a CPU Cycle as in the original MC68000.
*
* The ao68000 reacts on the following signals when waiting to finish a interrupt acknowledge bus cycle:
* - ACK_I: the cycle is completed successfully and the interrupt vector is read from DAT_I[7:0],
* - RTY_I: the cycle is completed successfully and the processor generates a auto-vector internally,
* - ERR_I: the cycle is terminated and the processor starts processing a spurious interrupt exception.
*
* Every bus cycle is supplemented with output tags:
* - WISHBONE standard tags: SGL_O, BLK_O, RMW_O, CTI_O, BTE_O,
* - ao68000 custom tag: fc_o that operates like the Function Code of the original MC68000.
*
* The ao68000 core has two additional outputs that are used to indicate the state of the processor:
* - reset_o is a external device reset signal. It is asserted when processing the RESET instruction. It is asserted for 124 bus cycles.
* After that the processor returns to normal instruction processing.
* - blocked_o is an output that indicates that the processor is blocked after a double bus error. When this output line is asserted
* the processor is blocked and does not process any instructions. The only way to continue processing instructions is to reset
* the core.
*
* <h3>Resetting the core</h3>
* The ao68000 core is reset with a asynchronous reset_n input. After deasserting the signal, the core starts its standard startup sequence,
* which is similar to the one performed by the original MC68000:
* - the value of the SSP register is read from address 0,
* - the value of the PC is read from address 1.
*
* An identical sequence is performed when powering up the core for the first time.
*
* <h3>Processor modes</h3>
* The ao68000 core has two modes of operation - exactly like the original MC68000:
* - Supervisor mode
* - User mode.
*
* Performing a privileged instruction when running in user mode results in a privilege exception, just like in MC68000.
*
* <h3>Processor states</h3>
* The ao68000 core can be in one of the following states:
* - instruction processing, which includes group 2 exception processing,
* - group 0 and group 1 exception processing,
* - external device reset state when processing the RESET instruction,
* - blocked state after a double bus error.
*/
/*! \page page_spec_registers Registers
* The ao68000 IP Core is a WISHBONE Master and does not contain any registers available for reading or writing from outside of the core.
*/
/*! \page page_spec_clocks Clocks
* <table width=100%>
* <caption><b>Table 1:</b> List of clocks.</caption>
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td rowspan=2>Name</td><td rowspan=2>Source</td><td colspan=3>Rates (MHz)</td><td rowspan=2>Remarks</td><td rowspan=2>Description</td></tr>
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td>Max</td><td>Min</td><td>Resolution</td></tr>
*
* <tr><td>CLK_I</td><td>Input Port</td><td>90</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
* </table>
*/
/*! \page page_spec_ports IO Ports
* <h3>WISHBONE IO Ports</h3>
* <table width=100%>
* <caption><b>Table 1:</b> List of WISHBONE IO ports.</caption>
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td>Port </td><td>Width </td><td>Direction </td><td>Description </td></tr>
* <tr><td>CLK_I </td><td>1 </td><td>Input </td><td>\copydoc CLK_I </td></tr>
* <tr><td>reset_n </td><td>1 </td><td>Input </td><td>\copydoc reset_n </td></tr>
* <tr><td>CYC_O </td><td>1 </td><td>Output </td><td>\copydoc CYC_O </td></tr>
* <tr><td>ADR_O </td><td>30 </td><td>Output </td><td>\copydoc ADR_O </td></tr>
* <tr><td>DAT_O </td><td>32 </td><td>Output </td><td>\copydoc DAT_O </td></tr>
* <tr><td>DAT_I </td><td>32 </td><td>Input </td><td>\copydoc DAT_I </td></tr>
* <tr><td>SEL_O </td><td>4 </td><td>Output </td><td>\copydoc SEL_O </td></tr>
* <tr><td>STB_O </td><td>1 </td><td>Output </td><td>\copydoc STB_O </td></tr>
* <tr><td>WE_O </td><td>1 </td><td>Output </td><td>\copydoc WE_O </td></tr>
* <tr><td>ACK_I </td><td>1 </td><td>Input </td><td>\copydoc ACK_I </td></tr>
* <tr><td>ERR_I </td><td>1 </td><td>Input </td><td>\copydoc ERR_I </td></tr>
* <tr><td>RTY_I </td><td>1 </td><td>Input </td><td>\copydoc RTY_I </td></tr>
* <tr><td>SGL_O </td><td>1 </td><td>Output </td><td>\copydoc SGL_O </td></tr>
* <tr><td>BLK_O </td><td>1 </td><td>Output </td><td>\copydoc BLK_O </td></tr>
* <tr><td>RMW_O </td><td>1 </td><td>Output </td><td>\copydoc RMW_O </td></tr>
* <tr><td>CTI_O </td><td>3 </td><td>Output </td><td>\copydoc CTI_O </td></tr>
* <tr><td>BTE_O </td><td>2 </td><td>Output </td><td>\copydoc BTE_O </td></tr>
* <tr><td>fc_o </td><td>3 </td><td>Output </td><td>\copydoc fc_o </td></tr>
* </table>
*
* <h3>Other IO Ports</h3>
* <table width=100%>
* <caption><b>Table 2:</b> List of Other IO ports.</caption>
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td>Port </td><td>Width </td><td>Direction </td><td>Description </td></tr>
* <tr><td>ipl_i </td><td>3 </td><td>Input </td><td>\copydoc ipl_i </td></tr>
* <tr><td>reset_o </td><td>1 </td><td>Output </td><td>\copydoc reset_o </td></tr>
* <tr><td>blocked_o</td><td>1 </td><td>Output </td><td>\copydoc blocked_o </td></tr>
* </table>
*/
/*! \addtogroup CLK_I CLK_I Port
* WISHBONE Clock Input
*/
/*! \addtogroup reset_n reset_n Port
* Asynchronous Reset Input
*/
/*! \addtogroup CYC_O CYC_O Port
* WISHBONE Master Cycle Output
*/
/*! \addtogroup ADR_O ADR_O Port
* WISHBONE Master Address Output
*/
/*! \addtogroup DAT_O DAT_O Port
* WISHBONE Master Data Output
*/
/*! \addtogroup DAT_I DAT_I Port
* WISHBONE Master Data Input
*/
/*! \addtogroup SEL_O SEL_O Port
* WISHBONE Master Byte Select
*/
/*! \addtogroup STB_O STB_O Port
* WISHBONE Master Strobe Output
*/
/*! \addtogroup WE_O WE_O Port
* WISHBONE Master Write Enable Output
*/
/*! \addtogroup ACK_I ACK_I Port
* WISHBONE Master Acknowledge Input:
* - on normal cycle: acknowledge,
* - on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].
*/
/*! \addtogroup ERR_I ERR_I Port
* WISHBONE Master Error Input
* - on normal cycle: bus error,
* - on interrupt acknowledge cycle: spurious interrupt.
*/
/*! \addtogroup RTY_I RTY_I Port
* WISHBONE Master Retry Input
* - on normal cycle: retry bus cycle,
* - on interrupt acknowledge: use auto-vector.
*/
/*! \addtogroup SGL_O SGL_O Port
* WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.
*/
/*! \addtogroup BLK_O BLK_O Port
* WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.
*/
/*! \addtogroup RMW_O RMW_O Port
* WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.
*/
/*! \addtogroup CTI_O CTI_O Port
* WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier,
* Incrementing Bus Cycle or End-of-Burst Cycle.
*/
/*! \addtogroup BTE_O BTE_O Port
* WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension,
* always Linear Burst.
*/
/*! \addtogroup fc_o fc_o Port
* Custom TAG_TYPE: TGC_O, Cycle Tag,
* Processor Function Code:
* - 1 - user data,
* - 2 - user program,
* - 5 - supervisor data : all exception vector entries except reset,
* - 6 - supervisor program : exception vector for reset,
* - 7 - cpu space: interrupt acknowledge.
*/
/*! \addtogroup ipl_i ipl_i Port
* Interrupt Priority Level
* Interrupt acknowledge cycle:
* - ACK_I: interrupt vector on DAT_I[7:0],
* - ERR_I: spurious interrupt,
* - RTY_I: auto-vector.
*/
/*! \addtogroup reset_o reset_o Port
* External device reset. Output high when processing the RESET instruction.
*/
/*! \addtogroup blocked_o blocked_o Port
* Processor blocked indicator. The processor is blocked after a double bus error.
*/
/*! \page page_spec_references References
* <ol><li>
* <em>Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores.</em><br/>
* Revision: B.3.<br/>
* Released: September 7, 2002.<br/>
* Available from: http://www.opencores.org. <br/>
* </li><li>
* <em>M68000 8-/16-/32-Bit Microprocessors User’s Manual.</em><br/>
* Ninth Edition.<br/>
* Freescale Semiconductor, Inc.<br/>
* Available from: http://www.freescale.com. <br/>
* </li><li>
* <em>MOTOROLA M68000 FAMILY Programmer’s Reference Manual (Includes CPU32 Instructions).</em><br/>
* MOTOROLA INC., 1992. M68000PM/AD REV.1.<br/>
* Available form: http://www.freescale.com. <br/>
* </li><li>
* <em>ao68000 Doxygen(Design) Documentation.</em><br/>
* </li></ol>
*/
/*! \page page_soc_linux System-on-Chip example with ao68000 running Linux
* The ao68000 IP Core is capable of booting the Linux kernel (http://www.kernel.org) up to the <tt>init</tt> program search.
*
* <h3>Requirements</h3>
* - Linux kernel sources (http://www.kernel.org), tested with version 2.6.33.1,
* - a MC68000 toolchain (http://www.gnu.org), tested with binutils-2.20 and gcc-core-4.4.3,
* - a development board to run the system, tested with Terasic DE2-70 board (http://www.terasic.com.tw),
* - a SDHC card,
* - a serial cable to view the output of kernel execution on a serial terminal program.
*
* <h3>System-on-Chip</h3>
* In order to test the ao68000 processor by booting the Linux kernel, a System-on-Chip is prepared and located at:
* <tt>./tests/soc_for_linux_on_terasic_de2_70/verilog/</tt>. The system consists of:
* - an early boot state machine: early_boot.v,
* - a SDHC card controller: sd.v,
* - a serial line transmitter: serial_txd.v,
* - a SSRAM controller: ssram.v,
* - a simple timer: timer.v,
* - a top level module, that instantiates the above modules and the ao68000 processor: soc_for_linux.v.
*
* <h3>Step-by-step instruction to prepare the system</h3>
* - download the Linux kernel (linux-2.6.33.1.tar.bz2),
* - download the toolchain (binutils-2.20.tar.bz2, gcc-core-4.4.3.tar.bz2),
* - configure and make Binutils: <br/>
* <code>./configure --prefix=(build prefix) --target=m68knommu-none-linux</code> <br/>
* <code>make</code> <br/>
* <code>make install</code> <br/>
* - configure and make GCC:
* <code>./../gcc-4.4.3/configure --prefix=(build prefix) --target=m68knommu-none-linux
* --disable-threads --disable-shared --disable-libmudflap --disable-libssp --disable-libiberty --disable-zlib --disable-libgomp</code>
* <br/>
* <code>make</code> <br/>
* <code>make install</code> <br/>
* - patch the Linux kernel sources by copying the contents of the directory <tt>./tests/soc_for_linux_on_terasic_de2_70/software/linux-2.6.33.1-ao68000/</tt> into the Linux kernel
* sources directory,
* - configure and make the Linux kernel: <br/>
* <code>make menuconfig ARCH=m68knommu CROSS_COMPILE=(build prefix)/bin/m68knommu-none-linux-</code> <br/>
* <code>make ARCH=m68knommu CROSS_COMPILE=(build prefix)/bin/m68knommu-none-linux-</code> <br/>
* - convert the Linux kernel binary in ELF format into a flat binary format:
* <code>(build prefix)//bin/m68knommu-none-linux-objcopy -O binary vmlinux vmlinux.bin</code> <br/>
* - synthesise the <tt>soc_for_linux</tt> with the Altera Quartus II tool. The instructions to perform the synthesis are located in the makefile
* located at: <tt>./Makefile</tt>,
* - prepare a SDHC card with the software:
* - copy the first 8 bytes of memory form the file <tt>./tests/soc_for_linux_on_terasic_de2_70/sd_card/sector0.dat</tt>: <br/>
* <code>dd if=sector0.dat of=/dev/(SD card device)</code>
* This file contains the SSP and PC values read by the ao68000 processor after booting.
* - copy the Linux kernel flat binary, at offset 1024: <br/>
* <code>dd if=vmlinux.bin of=/dev/(SD card device) bs=1024 seek=1</code> <br/>
* - insert the SDHC card into the reader in the Terasic DE2-70 board,
* - load the synthesised SOF file into the FPGA
* - look at the output of the kernel console by opening a serial terminal application and reading the output of the board.
*
* <h3>Notes</h3>
* - the SLOB allocator and not the default SLAB allocator had to be selected because of a problem in the kernel sources
* (in_interrupt() check before enabling the interrupts (at in ./kernel/slab.c:2109)),
* - the source file in the Linux kernel: <tt>./init/initramfs.c</tt> compiled with the GCC option <tt>-m68000</tt> contains illegal code
* to execute on a MC68000 (copy a long word from an unaligned address). Even after correcting this problem, the kernel did not want to boot
* reliably (sometimes it booted and found the init program, sometimes not).
*
* <h3>Linux console output</h3>
* The output of the running kernel is presented below:
* \verbinclude ./doc/src/linux_booting.txt
*/
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This unit handles 32x32=32/64 multiplication using an FSM using --
// -- a 17x17 signed array multiplier. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_shifter_multiply
#(
parameter PHY_REGS = 46,
parameter ALU_OPS = 32
)
(
input wire i_clk,
input wire i_reset,
// Clear and stall signals.
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
// ALU operation to perform. Activate if this is multiplication.
input wire [$clog2(ALU_OPS)-1:0] i_alu_operation_ff,
// This is not used.
input wire i_cc_satisfied,
// rm.rs + {rh,rn}. For non accumulate versions, rn = 0x0 and rh = 0x0.
input wire [31:0] i_rm,
input wire [31:0] i_rn,
input wire [31:0] i_rh,
input wire [31:0] i_rs,
//
// Outputs.
//
output reg [31:0] o_rd, // Result.
output reg o_sat,
output reg o_busy, // Unit busy.
output reg o_nozero // Don't set zero flag.
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
///////////////////////////////////////////////////////////////////////////////
// States
localparam IDLE = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam NUMBER_OF_STATES = 4;
///////////////////////////////////////////////////////////////////////////////
reg old_nozero_nxt, old_nozero_ff;
wire higher = i_alu_operation_ff[0] ||
i_alu_operation_ff == SMLAL00H ||
i_alu_operation_ff == SMLAL01H ||
i_alu_operation_ff == SMLAL10H ||
i_alu_operation_ff == SMLAL11H;
// 17-bit partial products.
reg signed [16:0] a;
reg signed [16:0] b;
reg signed [16:0] c;
reg signed [16:0] d;
// Signed products.
reg signed [63:0] x_ff, x_nxt, y_ff, y_nxt;
reg signed [63:0] prod_ab, prod_bc, prod_ad, prod_cd;
// Indicates to take upper product.
reg take_upper;
// State
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
///////////////////////////////////////////////////////////////////////////////
// Precompute products using DSP 17x17 signed multipliers.
always @ (posedge i_clk)
begin
prod_ab <= $signed(a) * $signed(b);
prod_bc <= $signed(b) * $signed(c);
prod_ad <= $signed(a) * $signed(d);
prod_cd <= $signed(c) * $signed(d);
end
///////////////////////////////////////////////////////////////////////////////
always @* // {ac} * {bd} = RM x RS
begin
take_upper = 0;
if ( i_alu_operation_ff == SMLALL || i_alu_operation_ff == SMLALH )
begin
// Signed RM x Signed RS
a = $signed({i_rm[31], i_rm[31:16]});
c = $signed({1'd0, i_rm[15:0]});
b = $signed({i_rs[31], i_rs[31:16]});
d = $signed({1'd0, i_rs[15:0]});
end
else if ( i_alu_operation_ff == OP_SMULW0 )
begin
// Signed RM x Lower RS
a = $signed({i_rm[31], i_rm[31:16]});
c = $signed({1'd0, i_rm[15:0]});
b = $signed({17{i_rs[15]}});
d = $signed({1'd0, i_rs[15:0]});
take_upper = 1;
end
else if ( i_alu_operation_ff == OP_SMULW1 )
begin
// Signed RM x Upper RS
a = $signed({i_rm[31], i_rm[31:16]});
c = $signed({1'd0, i_rm[15:0]});
b = $signed({17{i_rs[31]}});
d = $signed({1'd0, i_rs[31:16]});
take_upper = 1;
end
else if ( i_alu_operation_ff == OP_SMUL00 || i_alu_operation_ff == OP_SMLA00 ||
i_alu_operation_ff == OP_SMLAL00L || i_alu_operation_ff == OP_SMLAL00H )
begin
// lower RM x lower RS
a = $signed({17{i_rm[15]}});
c = $signed({1'd0, i_rm[15:0]});
b = $signed({17{i_rs[15]}});
d = $signed({1'd0, i_rs[15:0]});
if ( i_alu_operation_ff == OP_SMUL00 || i_alu_operation_ff == OP_SMLA00 ) take_upper = 1;
end
else if ( i_alu_operation_ff == OP_SMUL01 || i_alu_operation_ff == OP_SMLA01 ||
i_alu_operation_ff == OP_SMLAL01L || i_alu_operation_ff == OP_SMLAL01H )
begin
// lower RM x upper RS
a = $signed({17{i_rm[15]}}); // x = 0 for Rm
c = $signed({1'd0, i_rm[15:0]});
b = $signed({17{i_rs[16]}}); // y = 1 for Rs
d = $signed({1'd0, i_rs[31:16]});
if ( i_alu_operation_ff == OP_SMUL01 || i_alu_operation_ff == OP_SMLA01 ) take_upper = 1;
end
else if ( i_alu_operation_ff == OP_SMUL10 || i_alu_operation_ff == OP_SMLA10 ||
i_alu_operation_ff == OP_SMLAL10L || i_alu_operation_ff == OP_SMLAL10H )
begin
// upper RM x lower RS
a = $signed({17{i_rm[31]}}); // x = 1 for Rm
c = $signed({1'd0, i_rm[31:16]});
b = $signed({17{i_rs}}); // y = 0 for Rs
d = $signed({1'd0, i_rs[15:0]});
if ( i_alu_operation_ff == OP_SMUL10 || i_alu_operation_ff == OP_SMLA10 ) take_upper = 1;
end
else if ( i_alu_operation_ff == OP_SMUL11 || i_alu_operation_ff == OP_SMLA11 ||
i_alu_operation_ff == OP_SMLAL11L || i_alu_operation_ff == OP_SMLAL11H)
begin
// upper RM x upper RS
a = $signed({17{i_rm[31]}});
c = $signed({1'd0, i_rm[31:16]});
b = $signed({17{i_rs[31]}});
d = $signed({1'd0, i_rs[31:16]});
end
else
begin
// unsigned RM x RS
a = $signed({1'd0, i_rm[31:16]});
c = $signed({1'd0, i_rm[15:0]});
b = $signed({1'd0, i_rs[31:16]});
d = $signed({1'd0, i_rs[15:0]});
end
end
///////////////////////////////////////////////////////////////////////////////
always @*
begin
old_nozero_nxt = old_nozero_ff;
o_nozero = 1'd0;
o_busy = 1'd1;
o_rd = 32'd0;
state_nxt = state_ff;
x_nxt = x_ff;
o_sat = 1'd0;
y_nxt = y_ff;
case ( state_ff )
IDLE:
begin
o_busy = 1'd0;
// If we have the go signal.
if ( i_cc_satisfied && (i_alu_operation_ff == UMLALL ||
i_alu_operation_ff == UMLALH ||
i_alu_operation_ff == SMLALL ||
i_alu_operation_ff == SMLALH ||
i_alu_operation_ff == OP_SMULW0 ||
i_alu_operation_ff == OP_SMULW1 ||
i_alu_operation_ff == OP_SMUL00 ||
i_alu_operation_ff == OP_SMUL01 ||
i_alu_operation_ff == OP_SMUL10 ||
i_alu_operation_ff == OP_SMUL11 ||
i_alu_operation_ff == OP_SMLA00 ||
i_alu_operation_ff == OP_SMLA01 ||
i_alu_operation_ff == OP_SMLA10 ||
i_alu_operation_ff == OP_SMLA11 ||
i_alu_operation_ff == OP_SMLAW0 ||
i_alu_operation_ff == OP_SMLAW1 ||
i_alu_operation_ff == OP_SMLAL00L ||
i_alu_operation_ff == OP_SMLAL01L ||
i_alu_operation_ff == OP_SMLAL10L ||
i_alu_operation_ff == OP_SMLAL11L ||
i_alu_operation_ff == OP_SMLAL00H ||
i_alu_operation_ff == OP_SMLAL01H ||
i_alu_operation_ff == OP_SMLAL10H ||
i_alu_operation_ff == OP_SMLAL11H )
)
begin
o_busy = 1'd1;
if ( !higher )
begin
state_nxt = S1;
end
else
begin
state_nxt = S3;
end
end
end
S1:
begin
// 3 input adder.
x_nxt = (prod_cd << 0) + (prod_bc << 16) + (prod_ad << 16);
state_nxt = S2;
end
S2:
begin
// 3 input adder.
state_nxt = S3;
x_nxt = (x_ff[63:0] >> 0) + (prod_ab << 32) + {i_rh, i_rn};
y_nxt = (x_ff[47:0] >> 16) + (prod_ab << 32) + {i_rh, i_rn};
end
S3:
begin
state_nxt = IDLE;
if ( take_upper )
x_nxt = y_ff;
// Is this the first or second portion of the long multiply.
o_rd = higher ? x_nxt[63:32] : x_nxt[31:0];
// Record if older was not zero.
if ( !higher )
old_nozero_nxt = |x_nxt[31:0]; // 0x1 - Older was not zero. 0x0 - Older was zero.
o_busy = 1'd0;
// During higher operation, override setting of zero flag IF lower value was non-zero.
if ( higher && old_nozero_ff )
begin
o_nozero = 1'd1;
end
// Addition Saturated. For short DSP MAC.
if ( x_nxt[31] != x_ff[31] && x_ff[31] == i_rn[31] )
o_sat = 1'd1;
else
o_sat = 1'd0;
// 64-bit MAC with saturation. For long DSP MAC.
if ( i_alu_operation_ff == OP_SMLAL00L ||
i_alu_operation_ff == OP_SMLAL01L ||
i_alu_operation_ff == OP_SMLAL10L ||
i_alu_operation_ff == OP_SMLAL11L ||
i_alu_operation_ff == OP_SMLAL00H ||
i_alu_operation_ff == OP_SMLAL01H ||
i_alu_operation_ff == OP_SMLAL10H ||
i_alu_operation_ff == OP_SMLAL11H )
begin
if ( x_nxt[63] != x_ff[63] && x_ff[63] != i_rh[31] )
o_sat = 1'd1;
else
o_sat = 1'd0;
end
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
always @ (posedge i_clk)
begin
if ( i_reset )
begin
x_ff <= 64'd0;
y_ff <= 64'd0;
state_ff <= IDLE;
old_nozero_ff <= 32'd0;
end
else if ( i_clear_from_writeback )
begin
state_ff <= IDLE;
old_nozero_ff <= 32'd0;
end
else if ( i_data_stall )
begin
// Hold values
end
else if ( i_clear_from_alu )
begin
state_ff <= IDLE;
old_nozero_ff <= 32'd0;
end
else
begin
x_ff <= x_nxt;
y_ff <= y_nxt;
state_ff <= state_nxt;
old_nozero_ff <= old_nozero_nxt;
end
end
///////////////////////////////////////////////////////////////////////////////
endmodule // zap_multiply.v
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V |
// soc_system_hps_only_master.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.12.19.15:54:19
`timescale 1 ps / 1 ps
module soc_system_hps_only_master #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset) // resetrequest.reset
);
soc_system_hps_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // in.valid
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // .data
.out_valid (timing_adt_out_valid), // out.valid
.out_data (timing_adt_out_data), // .data
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_hps_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (b2p_out_packets_stream_ready), // in.ready
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_data (b2p_out_packets_stream_data), // .data
.in_channel (b2p_out_packets_stream_channel), // .channel
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.out_ready (b2p_adapter_out_ready), // out.ready
.out_valid (b2p_adapter_out_valid), // .valid
.out_data (b2p_adapter_out_data), // .data
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_hps_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (transacto_out_stream_ready), // in.ready
.in_valid (transacto_out_stream_valid), // .valid
.in_data (transacto_out_stream_data), // .data
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_ready (p2b_adapter_out_ready), // out.ready
.out_valid (p2b_adapter_out_valid), // .valid
.out_data (p2b_adapter_out_data), // .data
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
DDR3 DRAM controller
(C) Copyright 2012 Silicon On Inspiration
www.sioi.com.au
86 Longueville Road
Lane Cove 2066
New South Wales
AUSTRALIA
Slightly modified by Chris Pavlina to fit pinout changes
in C4-0.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module drac_ddr3
(
input ckin,
output ckout,
output ckouthalf,
output reset,
inout [63:0] ddq,
inout [7:0] dqsp,
inout [7:0] dqsn,
output [7:0] ddm,
output [15:0] da,
output [2:0] dba,
output [2:0] dcmd,
output [1:0] dce,
output [1:0] dcs,
output [1:0] dckp,
output [1:0] dckn,
output [1:0] dodt,
input srd,
input swr,
input [33:5] sa,
input [255:0] swdat,
input [31:0] smsk,
output [255:0] srdat,
output srdy,
input [2:0] dbg_out,
output [7:0] dbg_in
);
reg READ;
reg READ2;
reg ack;
reg [15:0] rDDR_Addr;
reg [2:0] rDDR_BankAddr;
reg [1:0] rDDR_CS_n;
reg [2:0] rDDR_Cmd;
reg [1:0] rDDR_CKE;
reg [1:0] rDDR_ODT;
reg [2:0] STATE;
reg [2:0] RTN;
reg [5:0] DLY;
reg [10:0] RFCNTR;
reg REFRESH;
reg RPULSE0;
reg RPULSE1;
reg RPULSE2;
reg RPULSE3;
reg RPULSE4;
reg RPULSE5;
reg RPULSE6;
reg RPULSE7;
reg WPULSE0;
reg [255:0] Q;
wire [7:0] DM;
wire [7:0] DM_t;
wire [7:0] wDDR_DM;
wire [7:0] wDDR_DQS;
wire [63:0] DQ_i;
wire [63:0] DQ_i_dly;
wire [255:0] wQ;
wire [63:0] DQ_o;
wire [63:0] DQ_t;
wire [63:0] wDDR_DQ;
reg [255:0] rWdat;
reg [31:0] rSmsk;
reg [13:0] rLock = 0;
reg rClrPll = 1;
reg [13:0] rStart = 0;
reg rStarted = 0;
reg [63:0] rChgDelay;
reg [63:0] rIncDelay;
reg [63:0] rCalDelay;
reg [63:0] rCalDelay2;
reg [63:0] rRstDelay;
// Set up clocks for DDR3. Use circuitry based on UG382 Ch 1 pp33,34
// Generate the following clocks:
//
// ck600 600MHz clock for DQ IOSERDES2 high speed clock
// ck600_180 600MHz clock for DQS OSERDES2 high speed clock
// DQS clocking lags DQ clocking by half of one bit time
// ck150 1/4 speed clock for IOSERDES2 parallel side and control logic
// ck75 Clock for MicroBlaze CPU
//
// Create two copies of the 600MHz clocks, providing separate copies for
// bank 1 and bank 3. This is necessary as each BUFPLL reaches only a
// single bank. The other clocks are global (BUFG).
wire ck600raw;
wire ck600_180raw;
wire ck150;
wire ck150raw;
wire ck75;
wire ck75raw;
wire [1:0] ck600;
wire [1:0] ck600_180;
wire [1:0] strobe;
wire [1:0] strobe180;
// DDR3 DIMM byte lane levelling is achieved with these IODELAY2 settings:
parameter LVL_WSLOPE = 3;
parameter LVL_WPHASE = 6;
BUFG bufg_main
(
.O (ckinb),
.I (ckin)
);
PLL_BASE
#(
.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (3),
.CLKFBOUT_MULT (29),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (1),
.CLKOUT1_PHASE (180.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (4),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (8),
.CLKOUT3_PHASE (0.0),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DIVIDE (8),
.CLKOUT4_PHASE (0.0),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DIVIDE (8),
.CLKOUT5_PHASE (0.000),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (16.000)
)
pll_base_main
(
.CLKFBOUT (pllfb0),
.CLKOUT0 (ck600raw),
.CLKOUT1 (ck600_180raw),
.CLKOUT2 (ck150raw),
.CLKOUT3 (ck75raw),
.CLKOUT4 (),
.CLKOUT5 (),
.LOCKED (locked),
.RST (rClrPll),
.CLKFBIN (pllfb0),
.CLKIN (ckinb)
);
BUFG bufg_150
(
.O (ck150),
.I (ck150raw)
);
BUFG bufg_75
(
.O (ck75),
.I (ck75raw)
);
genvar i;
generate
for (i = 0; i <= 1; i = i + 1) begin: BUFPLLS
BUFPLL
#(
.DIVIDE (4),
.ENABLE_SYNC ("TRUE")
)
bufpll_600
(
.IOCLK (ck600[i]),
.LOCK (dbg_in[i]),
.SERDESSTROBE (strobe[i]),
.GCLK (ck150),
.LOCKED (locked),
.PLLIN (ck600raw)
);
BUFPLL
#(
.DIVIDE (4),
.ENABLE_SYNC ("TRUE")
)
bufpll_600_18
(
.IOCLK (ck600_180[i]),
.LOCK (dbg_in[2 + i]),
.SERDESSTROBE (strobe180[i]),
.GCLK (ck150),
.LOCKED (locked),
.PLLIN (ck600_180raw)
);
end
// CLOCKS, two
wire [1:0] ckp;
wire [1:0] ckn;
for (i = 0; i <= 1; i = i + 1) begin: DDRO_CLKS
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dckp
(
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[1]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (ckp[i]),
.TQ (),
.IOCE (strobe180[1]),
.TCE (1'b1),
.RST (reset)
);
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dckn
(
.D1 (1'b1),
.D2 (1'b0),
.D3 (1'b1),
.D4 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[1]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (ckn[i]),
.TQ (),
.IOCE (strobe180[1]),
.TCE (1'b1),
.RST (reset)
);
OBUF obuft_ckp
(
.O(dckp[i]),
.I(ckp[i])
);
OBUF obuf_ckn
(
.O(dckn[i]),
.I(ckn[i])
);
end
// Address, Bank address
// NB ISIM can't grok parameter arrays, hence the following sim/synth bifurcation
`ifdef XILINX_ISIM
`else
// Bank ID here are backwards from the SIOI original, as I mirrored the PCB
// layout. Bank 1 (BUFPLL_X2Y3) is '1'; bank 3 (BUFPLL_X0Y3) is '0'.
parameter integer bank_a[15:0] = {0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1};
// f e d c b a 9 8 7 6 5 4 3 2 1 0
parameter integer bank_ba[2:0] = {0, 1, 1};
// 2 1 0
`endif
wire [15:0] wa;
for (i = 0; i <= 15; i = i + 1) begin: DDRO_A
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_a
(
.D1 (rDDR_Addr[i]),
.D2 (rDDR_Addr[i]),
.D3 (rDDR_Addr[i]),
.D4 (rDDR_Addr[i]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
`ifdef XILINX_ISIM
.CLK0 (ck600_180[0]),
`else
.CLK0 (ck600_180[bank_a[i]]),
`endif
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wa[i]),
.TQ (),
`ifdef XILINX_ISIM
.IOCE (strobe180[0]),
`else
.IOCE (strobe180[bank_a[i]]),
`endif
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_a
(
.O(da[i]),
.I(wa[i])
);
end
wire [2:0] wba;
for (i = 0; i <= 2; i = i + 1) begin: DDRO_BA
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_ba
(
.D1 (rDDR_BankAddr[i]),
.D2 (rDDR_BankAddr[i]),
.D3 (rDDR_BankAddr[i]),
.D4 (rDDR_BankAddr[i]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
`ifdef XILINX_ISIM
.CLK0 (ck600_180[0]),
`else
.CLK0 (ck600_180[bank_ba[i]]),
`endif
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wba[i]),
.TQ (),
`ifdef XILINX_ISIM
.IOCE (strobe180[0]),
`else
.IOCE (strobe180[bank_ba[i]]),
`endif
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_ba
(
.O(dba[i]),
.I(wba[i])
);
end
// command, ChipSelect
wire [2:0] wkmd;
for (i = 0; i <= 2; i = i + 1) begin: DDRO_KMD
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_kmd
(
.D1 (rDDR_Cmd[i]), // Command for 1 cycle
.D2 (rDDR_Cmd[i]),
.D3 (1'b1), // NOP thereafter
.D4 (1'b1),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[1]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wkmd[i]),
.TQ (),
.IOCE (strobe180[1]),
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_kmd
(
.O(dcmd[i]),
.I(wkmd[i])
);
end
wire [1:0] wcs;
for (i = 0; i <= 1; i = i + 1) begin: DDRO_CS
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_cs
(
.D1 (rDDR_CS_n[i]),
.D2 (rDDR_CS_n[i]),
.D3 (rDDR_CS_n[i]),
.D4 (rDDR_CS_n[i]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[1]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wcs[i]),
.TQ (),
.IOCE (strobe180[1]),
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_cs
(
.O(dcs[i]),
.I(wcs[i])
);
end
// CKE, ODT
wire [1:0] wcke;
for (i = 0; i <= 1; i = i + 1) begin: DDRO_CKE
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_cke
(
.D1 (rDDR_CKE[i]),
.D2 (rDDR_CKE[i]),
.D3 (rDDR_CKE[i]),
.D4 (rDDR_CKE[i]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[0]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wcke[i]),
.TQ (),
.IOCE (strobe180[0]),
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_cke
(
.O(dce[i]),
.I(wcke[i])
);
end
wire [1:0] wodt;
for (i = 0; i <= 1; i = i + 1) begin: DDRO_ODT
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_odt
(
.D1 (rDDR_ODT[i]),
.D2 (rDDR_ODT[i]),
.D3 (rDDR_ODT[i]),
.D4 (rDDR_ODT[i]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[1]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (wodt[i]),
.TQ (),
.IOCE (strobe180[1]),
.TCE (1'b1),
.RST (reset)
);
OBUF obuf_odt
(
.O(dodt[i]),
.I(wodt[i])
);
end
// DQ STROBES, 8 differential pairs
wire [7:0] dqso;
wire [7:0] dqso_d;
wire [7:0] dqst;
wire [7:0] dqst_d;
wire [7:0] dqson;
wire [7:0] dqson_d;
wire [7:0] dqstn;
wire [7:0] dqstn_d;
wire [7:0] dummy;
wire [7:0] dummyp;
wire [7:0] dummyn;
for (i = 0; i <= 7; i = i + 1) begin: DDRIO_DQS
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dqsp
(
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.T1 (READ),
.T2 (READ),
.T3 (READ),
.T4 (READ),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[i >> 2]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (dqso[i]),
.TQ (dqst[i]),
.IOCE (strobe180[i >> 2]),
.TCE (1'b1),
.RST (reset)
);
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dqsn
(
.D1 (1'b1),
.D2 (1'b0),
.D3 (1'b1),
.D4 (1'b0),
.T1 (READ),
.T2 (READ),
.T3 (READ),
.T4 (READ),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600_180[i >> 2]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (dqson[i]),
.TQ (dqstn[i]),
.IOCE (strobe180[i >> 2]),
.TCE (1'b1),
.RST (reset)
);
IODELAY2
#(
.DATA_RATE ("SDR"),
.ODELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IO")
)
iodelay2_dqsp
(
.ODATAIN (dqso[i]),
.DOUT (dqso_d[i]),
.T (dqst[i]),
.TOUT (dqst_d[i]),
.IDATAIN (dummyp[i])
);
IODELAY2
#(
.DATA_RATE ("SDR"),
.ODELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IO")
)
iodelay2_dqsn
(
.ODATAIN (dqson[i]),
.DOUT (dqson_d[i]),
.T (dqstn[i]),
.TOUT (dqstn_d[i]),
.IDATAIN (dummyn[i])
);
IOBUF iobuf_dqsp
(
.O(dummyp[i]),
.IO(dqsp[i]),
.I(dqso_d[i]),
.T(dqst_d[i])
);
IOBUF iobuf_dqsn
(
.O(dummyn[i]),
.IO(dqsn[i]),
.I(dqson_d[i]),
.T(dqstn_d[i])
);
end
// DATA MASKS, 8
wire [7:0] dmo;
wire [7:0] dmo_d;
wire [7:0] dmt;
wire [7:0] dmt_d;
for (i = 0; i <= 7; i = i + 1) begin: DDRO_DM
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dm
(
.D1 (rSmsk[i]),
.D2 (rSmsk[i + 8]),
.D3 (rSmsk[i + 16]),
.D4 (rSmsk[i + 24]),
.T1 (READ),
.T2 (READ),
.T3 (READ),
.T4 (READ),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600[i >> 2]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (dmo[i]),
.TQ (dmt[i]),
.IOCE (strobe[i >> 2]),
.TCE (1'b1),
.RST (reset)
);
IODELAY2
#(
.DATA_RATE ("SDR"),
.ODELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_VALUE (LVL_WPHASE + i * LVL_WSLOPE),
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IO")
)
iodelay2_dm
(
.ODATAIN (dmo[i]),
.DOUT (dmo_d[i]),
.T (dmt[i]),
.TOUT (dmt_d[i]),
.IDATAIN (dummy[i])
);
IOBUF iobuf_dm
(
.O(dummy[i]),
.IO(ddm[i]),
.I(dmo_d[i]),
.T(dmt_d[i])
);
end
// DQ LINES, 64
wire [63:0] dqo;
wire [63:0] dqo_d;
wire [63:0] dqt;
wire [63:0] dqt_d;
wire [63:0] dqi;
wire [63:0] dqi_d;
for (i = 0; i <= 63; i = i + 1) begin: DDRIO_DQ
OSERDES2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_OT ("SDR"),
.TRAIN_PATTERN (0),
.DATA_WIDTH (4),
.SERDES_MODE ("NONE"),
.OUTPUT_MODE ("SINGLE_ENDED")
)
oserdes2_dq
(
.D1 (rWdat[i]),
.D2 (rWdat[i + 64]),
.D3 (rWdat[i + 128]),
.D4 (rWdat[i + 192]),
.T1 (READ),
.T2 (READ),
.T3 (READ),
.T4 (READ),
.SHIFTIN1 (1'b1),
.SHIFTIN2 (1'b1),
.SHIFTIN3 (1'b1),
.SHIFTIN4 (1'b1),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.SHIFTOUT3 (),
.SHIFTOUT4 (),
.TRAIN (1'b0),
.OCE (1'b1),
.CLK0 (ck600[i >> 5]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.OQ (dqo[i]),
.TQ (dqt[i]),
.IOCE (strobe[i >> 5]),
.TCE (1'b1),
.RST (reset)
);
IODELAY2
#(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.ODELAY_VALUE (LVL_WPHASE + ((i * LVL_WSLOPE) >> 3)),
.IDELAY_TYPE ("VARIABLE_FROM_ZERO"),
.DELAY_SRC ("IO")
)
iodelay2_dq
(
.ODATAIN (dqo[i]),
.DOUT (dqo_d[i]),
.T (dqt[i]),
.TOUT (dqt_d[i]),
.IDATAIN (dqi[i]),
.DATAOUT (dqi_d[i]),
.CE (rChgDelay[i]),
.INC (rIncDelay[i]),
.CLK (ck150),
.CAL (rCalDelay2[i]),
.RST (rRstDelay[i]),
.IOCLK0 (ck600[i >> 5])
);
IOBUF iobuf_dq
(
.O(dqi[i]),
.IO(ddq[i]),
.I(dqo_d[i]),
.T(dqt_d[i])
);
ISERDES2
#(
.BITSLIP_ENABLE ("FALSE"),
.DATA_RATE ("SDR"),
.DATA_WIDTH (4),
.INTERFACE_TYPE ("RETIMED"),
.SERDES_MODE ("NONE")
)
iserdes2_dq
(
.Q1 (wQ[i]),
.Q2 (wQ[i + 64]),
.Q3 (wQ[i + 128]),
.Q4 (wQ[i + 192]),
.SHIFTOUT (),
.INCDEC (),
.VALID (),
.BITSLIP (),
.CE0 (READ),
.CLK0 (ck600[i >> 5]),
.CLK1 (1'b0),
.CLKDIV (ck150),
.D (dqi_d[i]),
.IOCE (strobe[i >> 5]),
.RST (reset),
.SHIFTIN (),
.FABRICOUT (),
.CFB0 (),
.CFB1 (),
.DFB ()
);
end
endgenerate
// DDR commands
parameter K_LMR = 3'h0; // Load Mode Register (Mode Register Set)
parameter K_RFSH = 3'h1; // Refresh (auto or self)
parameter K_CLOSE = 3'h2; // aka PRECHARGE
parameter K_OPEN = 3'h3; // aka ACTIVATE
parameter K_WRITE = 3'h4;
parameter K_READ = 3'h5;
parameter K_ZQCAL = 3'h6; // ZQ calibration
parameter K_NOP = 3'h7;
// States
parameter S_INIT = 3'h3;
parameter S_INIT2 = 3'h5;
parameter S_IDLE = 3'h0;
parameter S_READ = 3'h1;
parameter S_WRITE = 3'h2;
parameter S_PAUSE = 3'h4;
// Main DDR3 timings spec @150MHz
// tRAS RAS time 37.5 ns 6 clks open to close
// tRC RAS cycle 50.6 ns 8 clks open to next open
// tRP RAS precharge 13.1 ns 2 clks close to open
// tRRD RAS to RAS delay 4 clks 4 clks
// tRCD RAS to CAS delay 13.2 ns 2 clks
// CL CAS Latency 5 clks 5 clks
// tWR Write time 15 ns 3 clks Write finished to close issued
// tWTR Write to Read 4 clks 4 clks Write finished to read issued
// tRFC Refresh command 1Gb 110ns 17 clks Refresh command time for 1Gb parts
// tRFC Refresh command 2Gb 160ns 24 clks Refresh command time for 2Gb parts
// tRFC Refresh command 4Gb 260ns 39 clks Refresh command time for 4Gb parts
// tREFI Refresh interval 7.8 us 1170 clks
// tDQSS DQS start +-0.25 clks Time from DDR_Clk to DQS
parameter tRFC = 39;
parameter tRCD = 3;
parameter tRP = 3;
// Provide the PLL with a good long start up reset
always @ (posedge ckinb) begin
if (rLock[13] == 1'b1) begin
rClrPll <= 1'b0;
end else begin
rClrPll <= 1'b1;
rLock <= rLock + 14'b1;
end
end
// Hold the rest of the system in reset until the PLL has been locked for
// a good long while
always @ (posedge ckinb) begin
if (rStart[13] == 1'b1) begin
rStarted <= 1'b1;
end else begin
rStarted <= 1'b0;
if (locked) begin
rStart <= rStart + 14'b1;
end else begin
rStart <= 0;
end
end
end
// Add pipeline delays as required to make it easy for PAR to meet timing
always @ (posedge ck150) begin
Q <= wQ;
rWdat <= swdat;
rSmsk <= smsk;
rCalDelay2 <= rCalDelay;
end
always @ (posedge reset or posedge ck150)
if (reset) begin
rDDR_CKE <= 2'b00;
rDDR_CS_n <= 2'b11;
rDDR_ODT <= 2'b00;
rDDR_Cmd <= K_NOP;
STATE <= S_INIT;
DLY <= 0;
RTN <= 0;
RFCNTR <= 0;
REFRESH <= 0;
ack <= 0;
RPULSE0 <= 0;
WPULSE0 <= 0;
rChgDelay <= 64'd0;
rIncDelay <= 64'd0;
rCalDelay <= 64'd0;
rRstDelay <= 64'd0;
end else begin
if (RFCNTR[10:7] == 4'b1001) begin // 1153/150Mhz ~7.7us
RFCNTR <= 0;
REFRESH <= 1;
end else
RFCNTR <= RFCNTR + 11'b1;
RPULSE1 <= RPULSE0;
RPULSE2 <= RPULSE1;
RPULSE3 <= RPULSE2;
RPULSE4 <= RPULSE3;
RPULSE5 <= RPULSE4;
RPULSE6 <= RPULSE5;
RPULSE7 <= RPULSE6;
case (dbg_out[2:0])
3'd0: begin
ack <= WPULSE0 | RPULSE4;
end
3'd1: begin
ack <= WPULSE0 | RPULSE5;
end
3'd2: begin
ack <= WPULSE0 | RPULSE6;
end
3'd3: begin
ack <= WPULSE0 | RPULSE7;
end
3'd4: begin
ack <= WPULSE0 | RPULSE4;
end
3'd5: begin
ack <= WPULSE0 | RPULSE5;
end
3'd6: begin
ack <= WPULSE0 | RPULSE6;
end
3'd7: begin
ack <= WPULSE0 | RPULSE7;
end
endcase
case (STATE)
S_INIT: begin
rDDR_CKE <= 2'b11;
READ <= 0;
rDDR_BankAddr <= sa[15:13];
rDDR_Addr <= sa[31:16];
if (swr) begin
rDDR_CS_n <= sa[32] ? 2'b01 : 2'b10;
STATE <= S_INIT2;
rDDR_Cmd <= sa[10:8];
WPULSE0 <= 1;
end
end
S_INIT2: begin
RTN <= sa[33] ? S_INIT : S_IDLE;
rDDR_Cmd <= K_NOP;
STATE <= S_PAUSE;
DLY <= 20;
WPULSE0 <= 0;
end
S_IDLE: begin
READ <= 0;
rDDR_ODT <= 2'b00;
if (swr) begin
rDDR_Cmd <= K_OPEN;
STATE <= S_PAUSE;
RTN <= S_WRITE;
DLY <= tRCD - 1;
rDDR_Addr <= sa[31:16];
rDDR_BankAddr <= sa[15:13];
rDDR_CS_n <= sa[32] ? 2'b01 : 2'b10;
end else if (srd) begin
rDDR_Cmd <= K_OPEN;
STATE <= S_PAUSE;
RTN <= S_READ;
DLY <= tRCD - 1;
rDDR_Addr <= sa[31:16];
rDDR_BankAddr <= sa[15:13];
rDDR_CS_n <= sa[32] ? 2'b01 : 2'b10;
end else if (REFRESH) begin
rDDR_Cmd <= K_RFSH;
STATE <= S_PAUSE;
RTN <= S_IDLE;
DLY <= tRFC - 1;
REFRESH <= 0;
rDDR_CS_n <= 2'b00;
end else begin
rDDR_Cmd <= K_NOP;
rDDR_CS_n <= 2'b00;
end
end
// Address bits
// ============
// MB pg Lwd sa Row Col Bnk CS
// [X] - - - - - - -
// [X] - - - - - - -
// 2 - 0 - - - - -
// 3 - 1 [L] - 0 - -
// 4 - 2 [L] - 1 - -
// 5 - - 5 - 2 - -
// 6 - - 6 - 3 - -
// 7 - - 7 - 4 - -
// 8 - - 8 - 5 - -
// 9 - - 9 - 6 - -
// 10 - - 10 - 7 - -
// 11 - - 11 - 8 - -
// 12 - - 12 - 9 - -
// 13 - - 13 - [P] 0 -
// 14 - - 14 - - 1 -
// 15 - - 15 - - 2 -
// 16 - - 16 0 - - -
// 17 - - 17 1 - - -
// 18 - - 18 2 - - -
// 19 - - 19 3 - - -
// 20 - - 20 4 - - -
// 21 - - 21 5 - - -
// 22 - - 22 6 - - -
// 23 - - 23 7 - - -
// 24 - - 24 8 - - -
// 25 - - 25 9 - - -
// 26 - - 26 10 - - -
// 27 - - 27 11 - - -
// 28 - - 28 12 - - -
// 29 - - 29 13 - - -
// [H] 0 - 30 14 - - -
// [H] 1 - 31 15 - - -
// - 2 - 32 - - - 0
// - 3 - 33 - - - Extra address bit for DRAM init register space
S_WRITE: begin
rDDR_Cmd <= K_WRITE;
STATE <= S_PAUSE;
RTN <= S_IDLE;
DLY <= 14; // CWL + 2xfer + tWR + tRP
rDDR_Addr[10:0] <= {1'b1, sa[12:5], 2'b00}; // NB two LSBs ignored by DDR3 during WRITE
rDDR_Addr[12] <= dbg_out[2];
rDDR_BankAddr <= sa[15:13];
rDDR_ODT <= sa[16] ? 2'b10 : 2'b01; // Use ODT only in one rank, otherwise 40R || 40R -> 20R
WPULSE0 <= 1;
if (sa[33]) begin
rChgDelay <= rWdat[63:0];
rIncDelay <= rWdat[127:64];
rCalDelay <= rWdat[191:128];
rRstDelay <= rWdat[255:192];
end else begin
rChgDelay <= 64'd0;
rIncDelay <= 64'd0;
rCalDelay <= 64'd0;
rRstDelay <= 64'd0;
end
end
S_READ: begin
rDDR_Cmd <= K_READ;
STATE <= S_PAUSE;
RTN <= S_IDLE;
DLY <= 10; // CL + 2xfer + 1 + tRP
rDDR_Addr[10:0] <= {1'b1, sa[12:5], 2'b00};
rDDR_Addr[12] <= dbg_out[2];
rDDR_BankAddr <= sa[15:13];
READ <= 1;
RPULSE0 <= 1;
end
S_PAUSE: begin
rDDR_Cmd <= K_NOP;
DLY <= DLY - 6'b000001;
if (DLY == 6'b000001)
STATE <= RTN;
else
STATE <= S_PAUSE;
RPULSE0 <= 0;
WPULSE0 <= 0;
rChgDelay <= 64'd0;
rIncDelay <= 64'd0;
rCalDelay <= 64'd0;
rRstDelay <= 64'd0;
end
endcase
end
assign srdat = Q;
assign srdy = ack;
assign ckouthalf = ck75;
assign ckout = ck150;
assign reset = ~rStarted;
assign dbg_in[4] = locked;
assign dbg_in[7:5] = rDDR_Cmd;
endmodule
|
// Name: WcaWriteByteReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaWriteByteReg
(
input wire reset,
output wire [7:0] out, //Output data.
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire write = addrValid & rbusCtrl[2];
WcaRegCore8 sr( .Data( rbusData), .Enable( write ), .Aclr(reset), .Clock(~rbusCtrl[0]), .Q(out));
endmodule // WcaWriteByteReg
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_if_lt24_reg.v
//
// *Module Description:
// Registers for LT24 interface.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_if_lt24_reg (
// OUTPUTs
irq_adc_o, // LT24 ADC interface interrupt
irq_lcd_o, // LT24 LCD interface interrupt
lcd_reset_n_o, // LT24 LCD Reset (Active Low)
lcd_on_o, // LT24 LCD on/off
lcd_cfg_clk_o, // LT24 LCD Interface clock configuration
lcd_cfg_refr_o, // LT24 LCD Interface refresh configuration
lcd_cfg_refr_sync_en_o, // LT24 LCD Interface refresh sync enable configuration
lcd_cfg_refr_sync_val_o, // LT24 LCD Interface refresh sync value configuration
lcd_cmd_refr_o, // LT24 LCD Interface refresh command
lcd_cmd_val_o, // LT24 LCD Generic command value
lcd_cmd_has_param_o, // LT24 LCD Generic command has parameters
lcd_cmd_param_o, // LT24 LCD Generic command parameter value
lcd_cmd_param_rdy_o, // LT24 LCD Generic command trigger
lcd_cmd_dfill_o, // LT24 LCD Data fill value
lcd_cmd_dfill_wr_o, // LT24 LCD Data fill trigger
adc_enabled_o, // LT24 ADC Enabled
adc_cfg_clk_o, // LT24 ADC Clock configuration
adc_coord_y_swap_o, // LT24 Coordinates: swap Y axis (horizontal symmetry)
adc_coord_x_swap_o, // LT24 Coordinates: swap X axis (vertical symmetry)
adc_coord_cl_swap_o, // LT24 Coordinates: swap column/lines
per_dout_o, // Peripheral data output
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
lcd_status_i, // LT24 LCD FSM Status
lcd_start_evt_i, // LT24 LCD FSM is starting
lcd_done_evt_i, // LT24 LCD FSM is done
lcd_uflow_evt_i, // LT24 LCD refresh underfow
adc_done_evt_i, // LT24 ADC FSM is done
adc_x_data_i, // LT24 ADC X sampled data
adc_y_data_i, // LT24 ADC Y sampled data
adc_x_coord_i, // LT24 ADC X coordinate
adc_y_coord_i, // LT24 ADC Y coordinate
per_addr_i, // Peripheral address
per_din_i, // Peripheral data input
per_en_i, // Peripheral enable (high active)
per_we_i // Peripheral write enable (high active)
);
// PARAMETERs
//============
parameter [14:0] BASE_ADDR = 15'h0280; // Register base address
// - 5 LSBs must stay cleared: 0x0020, 0x0040,
// 0x0060, 0x0080,
// 0x00A0, ...
// OUTPUTs
//============
output irq_adc_o; // LT24 ADC interface interrupt
output irq_lcd_o; // LT24 LCD interface interrupt
output lcd_reset_n_o; // LT24 LCD Reset (Active Low)
output lcd_on_o; // LT24 LCD on/off
output [2:0] lcd_cfg_clk_o; // LT24 LCD Interface clock configuration
output [14:0] lcd_cfg_refr_o; // LT24 LCD Interface refresh configuration
output lcd_cfg_refr_sync_en_o; // LT24 LCD Interface refresh sync configuration
output [9:0] lcd_cfg_refr_sync_val_o; // LT24 LCD Interface refresh sync value configuration
output lcd_cmd_refr_o; // LT24 LCD Interface refresh command
output [7:0] lcd_cmd_val_o; // LT24 LCD Generic command value
output lcd_cmd_has_param_o; // LT24 LCD Generic command has parameters
output [15:0] lcd_cmd_param_o; // LT24 LCD Generic command parameter value
output lcd_cmd_param_rdy_o; // LT24 LCD Generic command trigger
output [15:0] lcd_cmd_dfill_o; // LT24 LCD Data fill value
output lcd_cmd_dfill_wr_o; // LT24 LCD Data fill trigger
output adc_enabled_o; // LT24 ADC Enabled
output [7:0] adc_cfg_clk_o; // LT24 ADC Clock configuration
output adc_coord_y_swap_o; // LT24 Coordinates: swap Y axis (horizontal symmetry)
output adc_coord_x_swap_o; // LT24 Coordinates: swap X axis (vertical symmetry)
output adc_coord_cl_swap_o; // LT24 Coordinates: swap column/lines
output [15:0] per_dout_o; // Peripheral data output
// INPUTs
//============
input mclk; // Main system clock
input puc_rst; // Main system reset
input [4:0] lcd_status_i; // LT24 LCD FSM Status
input lcd_start_evt_i; // LT24 LCD FSM is starting
input lcd_done_evt_i; // LT24 LCD FSM is done
input lcd_uflow_evt_i; // LT24 LCD refresh underfow
input adc_done_evt_i; // LT24 ADC FSM is done
input [11:0] adc_x_data_i; // LT24 ADC X sampled data
input [11:0] adc_y_data_i; // LT24 ADC Y sampled data
input [8:0] adc_x_coord_i; // LT24 ADC X coordinate
input [8:0] adc_y_coord_i; // LT24 ADC Y coordinate
input [13:0] per_addr_i; // Peripheral address
input [15:0] per_din_i; // Peripheral data input
input per_en_i; // Peripheral enable (high active)
input [1:0] per_we_i; // Peripheral write enable (high active)
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 5;
// Register addresses offset
parameter [DEC_WD-1:0] LT24_LCD_CFG = 'h00, // LT24 configuration and Generic command sending
LT24_LCD_REFRESH = 'h02,
LT24_LCD_REFRESH_SYNC = 'h04,
LT24_LCD_CMD = 'h06,
LT24_LCD_CMD_PARAM = 'h08,
LT24_LCD_CMD_DFILL = 'h0A,
LT24_LCD_STATUS = 'h0C,
LT24_LCD_IRQ = 'h0E,
LT24_ADC_CFG = 'h10,
LT24_ADC_IRQ = 'h12,
LT24_ADC_DATA_X = 'h14,
LT24_ADC_DATA_Y = 'h16,
LT24_ADC_COORD_X = 'h18,
LT24_ADC_COORD_Y = 'h1A;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] LT24_LCD_CFG_D = (BASE_REG << LT24_LCD_CFG ),
LT24_LCD_REFRESH_D = (BASE_REG << LT24_LCD_REFRESH ),
LT24_LCD_REFRESH_SYNC_D = (BASE_REG << LT24_LCD_REFRESH_SYNC ),
LT24_LCD_CMD_D = (BASE_REG << LT24_LCD_CMD ),
LT24_LCD_CMD_PARAM_D = (BASE_REG << LT24_LCD_CMD_PARAM ),
LT24_LCD_CMD_DFILL_D = (BASE_REG << LT24_LCD_CMD_DFILL ),
LT24_LCD_STATUS_D = (BASE_REG << LT24_LCD_STATUS ),
LT24_LCD_IRQ_D = (BASE_REG << LT24_LCD_IRQ ),
LT24_ADC_CFG_D = (BASE_REG << LT24_ADC_CFG ),
LT24_ADC_IRQ_D = (BASE_REG << LT24_ADC_IRQ ),
LT24_ADC_DATA_X_D = (BASE_REG << LT24_ADC_DATA_X ),
LT24_ADC_DATA_Y_D = (BASE_REG << LT24_ADC_DATA_Y ),
LT24_ADC_COORD_X_D = (BASE_REG << LT24_ADC_COORD_X ),
LT24_ADC_COORD_Y_D = (BASE_REG << LT24_ADC_COORD_Y );
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en_i & (per_addr_i[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr_i[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (LT24_LCD_CFG_D & {DEC_SZ{(reg_addr == LT24_LCD_CFG )}}) |
(LT24_LCD_REFRESH_D & {DEC_SZ{(reg_addr == LT24_LCD_REFRESH )}}) |
(LT24_LCD_REFRESH_SYNC_D & {DEC_SZ{(reg_addr == LT24_LCD_REFRESH_SYNC )}}) |
(LT24_LCD_CMD_D & {DEC_SZ{(reg_addr == LT24_LCD_CMD )}}) |
(LT24_LCD_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_LCD_CMD_PARAM )}}) |
(LT24_LCD_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_LCD_CMD_DFILL )}}) |
(LT24_LCD_STATUS_D & {DEC_SZ{(reg_addr == LT24_LCD_STATUS )}}) |
(LT24_LCD_IRQ_D & {DEC_SZ{(reg_addr == LT24_LCD_IRQ )}}) |
(LT24_ADC_CFG_D & {DEC_SZ{(reg_addr == LT24_ADC_CFG )}}) |
(LT24_ADC_IRQ_D & {DEC_SZ{(reg_addr == LT24_ADC_IRQ )}}) |
(LT24_ADC_DATA_X_D & {DEC_SZ{(reg_addr == LT24_ADC_DATA_X )}}) |
(LT24_ADC_DATA_Y_D & {DEC_SZ{(reg_addr == LT24_ADC_DATA_Y )}}) |
(LT24_ADC_COORD_X_D & {DEC_SZ{(reg_addr == LT24_ADC_COORD_X )}}) |
(LT24_ADC_COORD_Y_D & {DEC_SZ{(reg_addr == LT24_ADC_COORD_Y )}}) ;
// Read/Write probes
wire reg_write = |per_we_i & reg_sel;
wire reg_read = ~|per_we_i & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
//------------------------------------------------
// LT24_LCD_CFG Register
//------------------------------------------------
reg [15:0] lt24_lcd_cfg;
wire lt24_lcd_cfg_wr = reg_wr[LT24_LCD_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_lcd_cfg <= 16'h0000;
else if (lt24_lcd_cfg_wr) lt24_lcd_cfg <= per_din_i & 16'hE07F;
// Bitfield assignments
wire lcd_irq_refr_done_en = lt24_lcd_cfg[15];
wire lcd_irq_refr_start_en = lt24_lcd_cfg[14];
wire lcd_irq_refr_uflow_en = lt24_lcd_cfg[13];
assign lcd_cfg_clk_o = lt24_lcd_cfg[6:4];
assign lcd_reset_n_o = ~lt24_lcd_cfg[1];
assign lcd_on_o = lt24_lcd_cfg[0];
//------------------------------------------------
// LT24_LCD_REFRESH Register
//------------------------------------------------
reg lcd_cmd_refr_o;
reg [14:0] lcd_cfg_refr_o;
wire lt24_lcd_refresh_wr = reg_wr[LT24_LCD_REFRESH];
wire lcd_cmd_refr_clr = lcd_done_evt_i & lcd_status_i[2] & (lcd_cfg_refr_o==15'h0000); // Auto-clear in manual refresh mode when done
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cmd_refr_o <= 1'h0;
else if (lt24_lcd_refresh_wr) lcd_cmd_refr_o <= per_din_i[0];
else if (lcd_cmd_refr_clr) lcd_cmd_refr_o <= 1'h0;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cfg_refr_o <= 15'h0000;
else if (lt24_lcd_refresh_wr) lcd_cfg_refr_o <= per_din_i[15:1];
wire [15:0] lt24_lcd_refresh = {lcd_cfg_refr_o, lcd_cmd_refr_o};
//------------------------------------------------
// LT24_LCD_REFRESH_SYNC Register
//------------------------------------------------
reg lcd_cfg_refr_sync_en_o;
reg [9:0] lcd_cfg_refr_sync_val_o;
wire lt24_lcd_refresh_sync_wr = reg_wr[LT24_LCD_REFRESH_SYNC];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cfg_refr_sync_en_o <= 1'h0;
else if (lt24_lcd_refresh_sync_wr) lcd_cfg_refr_sync_en_o <= per_din_i[15];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cfg_refr_sync_val_o <= 10'h000;
else if (lt24_lcd_refresh_sync_wr) lcd_cfg_refr_sync_val_o <= per_din_i[9:0];
wire [15:0] lt24_lcd_refresh_sync = {lcd_cfg_refr_sync_en_o, 5'h00, lcd_cfg_refr_sync_val_o};
//------------------------------------------------
// LT24_LCD_CMD Register
//------------------------------------------------
reg [15:0] lt24_lcd_cmd;
wire lt24_lcd_cmd_wr = reg_wr[LT24_LCD_CMD];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_lcd_cmd <= 16'h0000;
else if (lt24_lcd_cmd_wr) lt24_lcd_cmd <= per_din_i & 16'h01FF;
assign lcd_cmd_val_o = lt24_lcd_cmd[7:0];
assign lcd_cmd_has_param_o = lt24_lcd_cmd[8];
//------------------------------------------------
// LT24_LCD_CMD_PARAM Register
//------------------------------------------------
reg [15:0] lcd_cmd_param_o;
wire lt24_lcd_cmd_param_wr = reg_wr[LT24_LCD_CMD_PARAM];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cmd_param_o <= 16'h0000;
else if (lt24_lcd_cmd_param_wr) lcd_cmd_param_o <= per_din_i;
reg lcd_cmd_param_rdy_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cmd_param_rdy_o <= 1'b0;
else lcd_cmd_param_rdy_o <= lt24_lcd_cmd_param_wr;
//------------------------------------------------
// LT24_LCD_CMD_DFILL Register
//------------------------------------------------
reg [15:0] lcd_cmd_dfill_o;
assign lcd_cmd_dfill_wr_o = reg_wr[LT24_LCD_CMD_DFILL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lcd_cmd_dfill_o <= 16'h0000;
else if (lcd_cmd_dfill_wr_o) lcd_cmd_dfill_o <= per_din_i;
//------------------------------------------------
// LT24_LCD_STATUS Register
//------------------------------------------------
wire [15:0] lt24_lcd_status;
assign lt24_lcd_status[0] = lcd_status_i[0]; // FSM_BUSY
assign lt24_lcd_status[1] = lcd_status_i[1]; // WAIT_PARAM
assign lt24_lcd_status[2] = lcd_status_i[2]; // REFRESH_BUSY
assign lt24_lcd_status[3] = lcd_status_i[3]; // WAIT_FOR_SCANLINE
assign lt24_lcd_status[4] = lcd_status_i[4]; // DATA_FILL_BUSY
assign lt24_lcd_status[15:5] = 11'h000;
//------------------------------------------------
// LT24_LCD_IRQ Register
//------------------------------------------------
wire [15:0] lt24_lcd_irq;
// Clear IRQ when 1 is written. Set IRQ when FSM is done
wire lcd_irq_refr_done_clr = per_din_i[15] & reg_wr[LT24_LCD_IRQ];
wire lcd_irq_refr_done_set = lcd_done_evt_i;
wire lcd_irq_refr_start_clr = per_din_i[14] & reg_wr[LT24_LCD_IRQ];
wire lcd_irq_refr_start_set = lcd_start_evt_i;
wire lcd_irq_refr_uflow_clr = per_din_i[13] & reg_wr[LT24_LCD_IRQ];
wire lcd_irq_refr_uflow_set = lcd_uflow_evt_i;
reg lcd_irq_refr_done;
reg lcd_irq_refr_start;
reg lcd_irq_refr_uflow;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
lcd_irq_refr_done <= 1'b0;
lcd_irq_refr_start <= 1'b0;
lcd_irq_refr_uflow <= 1'b0;
end
else
begin
lcd_irq_refr_done <= ( lcd_irq_refr_done_set | (~lcd_irq_refr_done_clr & lcd_irq_refr_done ) ); // IRQ set has priority over clear
lcd_irq_refr_start <= ( lcd_irq_refr_start_set | (~lcd_irq_refr_start_clr & lcd_irq_refr_start) ); // IRQ set has priority over clear
lcd_irq_refr_uflow <= ( lcd_irq_refr_uflow_set | (~lcd_irq_refr_uflow_clr & lcd_irq_refr_uflow) ); // IRQ set has priority over clear
end
assign lt24_lcd_irq = {lcd_irq_refr_done, lcd_irq_refr_start, lcd_irq_refr_uflow, 13'h0000};
assign irq_lcd_o = (lcd_irq_refr_done & lcd_irq_refr_done_en) |
(lcd_irq_refr_start & lcd_irq_refr_start_en) |
(lcd_irq_refr_uflow & lcd_irq_refr_uflow_en) ; // LT24 LCD interrupt
//------------------------------------------------
// LT24_ADC_CFG Register
//------------------------------------------------
reg [15:0] lt24_adc_cfg;
wire lt24_adc_cfg_wr = reg_wr[LT24_ADC_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_cfg <= 16'h0000;
else if (lt24_adc_cfg_wr) lt24_adc_cfg <= per_din_i & 16'h9EFF;
// Bitfield assignments
wire adc_irq_done_en = lt24_adc_cfg[15];
assign adc_enabled_o = lt24_adc_cfg[12];
assign adc_coord_x_swap_o = lt24_adc_cfg[11];
assign adc_coord_y_swap_o = lt24_adc_cfg[10];
assign adc_coord_cl_swap_o = lt24_adc_cfg[ 9];
assign adc_cfg_clk_o = lt24_adc_cfg[7:0];
//------------------------------------------------
// LT24_ADC_IRQ Register
//------------------------------------------------
wire [15:0] lt24_adc_irq;
// Clear IRQ when 1 is written. Set IRQ when FSM is done
wire adc_irq_done_clr = per_din_i[15] & reg_wr[LT24_ADC_IRQ];
wire adc_irq_done_set = adc_done_evt_i;
reg adc_irq_done;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
adc_irq_done <= 1'b0;
end
else
begin
adc_irq_done <= ( adc_irq_done_set | (~adc_irq_done_clr & adc_irq_done ) ); // IRQ set has priority over clear
end
assign lt24_adc_irq = {adc_irq_done, 15'h0000};
assign irq_adc_o = (adc_irq_done & adc_irq_done_en); // LT24 ADC interrupt
//------------------------------------------------
// LT24_ADC_DATA_X/Y Register
//------------------------------------------------
// Mark that new data has been received
reg lt24_adc_new_data_rdy;
wire copy_adc_data;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_new_data_rdy <= 1'b0;
else if (adc_done_evt_i) lt24_adc_new_data_rdy <= 1'b1;
else if (copy_adc_data) lt24_adc_new_data_rdy <= 1'b0;
// Latch new data
reg [23:0] lt24_adc_new_data;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_new_data <= 24'h000000;
else if (adc_done_evt_i) lt24_adc_new_data <= {adc_y_data_i, adc_x_data_i};
// Detect when both X and Y data have be read so that we can push the new data in
reg [1:0] lt24_adc_data_empty;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_data_empty <= 2'h3;
else if (copy_adc_data) lt24_adc_data_empty <= 2'h0;
else if (reg_rd[LT24_ADC_DATA_X]) lt24_adc_data_empty <= lt24_adc_data_empty | 2'h1;
else if (reg_rd[LT24_ADC_DATA_Y]) lt24_adc_data_empty <= lt24_adc_data_empty | 2'h2;
assign copy_adc_data = (lt24_adc_data_empty==2'h3) & lt24_adc_new_data_rdy;
// Push new data into read buffers when these have been read
reg [15:0] lt24_adc_data_x;
reg [15:0] lt24_adc_data_y;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_data_x <= 16'h0000;
else if (copy_adc_data) lt24_adc_data_x <= {4'h0, lt24_adc_new_data[11:0]};
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_data_y <= 16'h0000;
else if (copy_adc_data) lt24_adc_data_y <= {4'h0, lt24_adc_new_data[23:12]};
//------------------------------------------------
// LT24_ADC_COORD_X/Y Register
//------------------------------------------------
// Mark that new coordinates has been received
reg lt24_adc_new_coord_rdy;
wire copy_adc_coord;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_new_coord_rdy <= 1'b0;
else if (adc_done_evt_i) lt24_adc_new_coord_rdy <= 1'b1;
else if (copy_adc_coord) lt24_adc_new_coord_rdy <= 1'b0;
// Latch new data
reg [17:0] lt24_adc_new_coord;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_new_coord <= 18'h00000;
else if (adc_done_evt_i) lt24_adc_new_coord <= {adc_y_coord_i, adc_x_coord_i};
// Detect when both X and Y data have be read so that we can push the new data in
reg [1:0] lt24_adc_coord_empty;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_coord_empty <= 2'h3;
else if (copy_adc_coord) lt24_adc_coord_empty <= 2'h0;
else if (reg_rd[LT24_ADC_COORD_X]) lt24_adc_coord_empty <= lt24_adc_coord_empty | 2'h1;
else if (reg_rd[LT24_ADC_COORD_Y]) lt24_adc_coord_empty <= lt24_adc_coord_empty | 2'h2;
assign copy_adc_coord = (lt24_adc_coord_empty==2'h3) & lt24_adc_new_coord_rdy;
// Push new data into read buffers when these have been read
reg [15:0] lt24_adc_coord_x;
reg [15:0] lt24_adc_coord_y;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_coord_x <= 16'h0000;
else if (copy_adc_coord) lt24_adc_coord_x <= {7'h00, lt24_adc_new_coord[8:0]};
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_adc_coord_y <= 16'h0000;
else if (copy_adc_coord) lt24_adc_coord_y <= {7'h00, lt24_adc_new_coord[17:9]};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] lt24_lcd_cfg_read = lt24_lcd_cfg & {16{reg_rd[LT24_LCD_CFG ]}};
wire [15:0] lt24_lcd_refresh_read = lt24_lcd_refresh & {16{reg_rd[LT24_LCD_REFRESH ]}};
wire [15:0] lt24_lcd_refresh_sync_read = lt24_lcd_refresh_sync & {16{reg_rd[LT24_LCD_REFRESH_SYNC]}};
wire [15:0] lt24_lcd_cmd_read = lt24_lcd_cmd & {16{reg_rd[LT24_LCD_CMD ]}};
wire [15:0] lt24_lcd_cmd_param_read = lcd_cmd_param_o & {16{reg_rd[LT24_LCD_CMD_PARAM ]}};
wire [15:0] lt24_lcd_cmd_dfill_read = lcd_cmd_dfill_o & {16{reg_rd[LT24_LCD_CMD_DFILL ]}};
wire [15:0] lt24_lcd_status_read = lt24_lcd_status & {16{reg_rd[LT24_LCD_STATUS ]}};
wire [15:0] lt24_lcd_irq_read = lt24_lcd_irq & {16{reg_rd[LT24_LCD_IRQ ]}};
wire [15:0] lt24_adc_cfg_read = lt24_adc_cfg & {16{reg_rd[LT24_ADC_CFG ]}};
wire [15:0] lt24_adc_irq_read = lt24_adc_irq & {16{reg_rd[LT24_ADC_IRQ ]}};
wire [15:0] lt24_adc_data_x_read = lt24_adc_data_x & {16{reg_rd[LT24_ADC_DATA_X ]}};
wire [15:0] lt24_adc_data_y_read = lt24_adc_data_y & {16{reg_rd[LT24_ADC_DATA_Y ]}};
wire [15:0] lt24_adc_coord_x_read = lt24_adc_coord_x & {16{reg_rd[LT24_ADC_COORD_X ]}};
wire [15:0] lt24_adc_coord_y_read = lt24_adc_coord_y & {16{reg_rd[LT24_ADC_COORD_Y ]}};
wire [15:0] per_dout_o = lt24_lcd_cfg_read |
lt24_lcd_refresh_read |
lt24_lcd_refresh_sync_read |
lt24_lcd_cmd_read |
lt24_lcd_cmd_param_read |
lt24_lcd_cmd_dfill_read |
lt24_lcd_status_read |
lt24_lcd_irq_read |
lt24_adc_cfg_read |
lt24_adc_irq_read |
lt24_adc_data_x_read |
lt24_adc_data_y_read |
lt24_adc_coord_x_read |
lt24_adc_coord_y_read ;
endmodule // ogfx_if_lt24_reg
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:35:00 08/24/2014
// Design Name: Top_N3_Computer_IOBUS_VGA_PS2
// Module Name: E:/Summer Course/Top_Computer_IOBUS_VGA_PS2_N3/test.v
// Project Name: Top_Computer_IOBUS_VGA_PS2_N3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top_N3_Computer_IOBUS_VGA_PS2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clk_100mhz;
reg [4:0] BTN;
reg [7:0] SW;
reg PS2_clk;
reg PS2_Data;
// Outputs
wire [7:0] LED;
wire [7:0] SEGMENT;
wire [3:0] AN_SEL;
wire [2:0] Red;
wire [2:0] Green;
wire [1:0] Blue;
wire HSYNC;
wire VSYNC;
// Instantiate the Unit Under Test (UUT)
Top_N3_Computer_IOBUS_VGA_PS2 uut (
.clk_100mhz(clk_100mhz),
.BTN(BTN),
.SW(SW),
.LED(LED),
.SEGMENT(SEGMENT),
.AN_SEL(AN_SEL),
.PS2_clk(PS2_clk),
.PS2_Data(PS2_Data),
.Red(Red),
.Green(Green),
.Blue(Blue),
.HSYNC(HSYNC),
.VSYNC(VSYNC)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
clk_100mhz = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk_100mhz = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial forever begin
PS2_clk = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) PS2_clk = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
clk_100mhz = 0;
BTN = 0;
SW = 0;
PS2_clk = 0;
PS2_Data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
//0d
#100 BTN[3] = 1;
#100 BTN[3] = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
//5a
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
//5a
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
//5a
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
//5a
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
#200 PS2_Data = 0;
#200 PS2_Data = 0;
#200 PS2_Data = 1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V |
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (c.phase==0 && c.initdone) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (c.phase==1 && c.initdone) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (c.phase==2 && c.initdone) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (c.phase==3 && c.initdone) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (c.phase==4 && c.initdone) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (c.phase==5 && c.initdone) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (c.phase==6 && c.initdone) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (c.phase==7 && c.initdone) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (c.phase==8 && c.initdone) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (c.phase==9 && c.initdone) ? cnt9 + 1 : cnt9;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], c.elem, c.phase[2:0], c.iter_done, c.pchange, c.irst, c.ecnt);
$write("%d %d (%d) : ", d_dout[63:32], d_dout[31:0], d_douten);
$write("[%d](%d)", c.req, c.state);
$write("|");
if (c.stree.F08_emp) $write("---------- "); else $write("%d ", c.stree.F08_dot);
if (c.stree.F09_emp) $write("---------- "); else $write("%d ", c.stree.F09_dot);
if (c.stree.F10_emp) $write("---------- "); else $write("%d ", c.stree.F10_dot);
if (c.stree.F11_emp) $write("---------- "); else $write("%d ", c.stree.F11_dot);
if (c.stree.F12_emp) $write("---------- "); else $write("%d ", c.stree.F12_dot);
if (c.stree.F13_emp) $write("---------- "); else $write("%d ", c.stree.F13_dot);
if (c.stree.F14_emp) $write("---------- "); else $write("%d ", c.stree.F14_dot);
if (c.stree.F15_emp) $write("---------- "); else $write("%d ", c.stree.F15_dot);
$write("|");
$write("| %d %d %d %d %d %d %d %d|",
c.im00.imf.cnt, c.im01.imf.cnt, c.im02.imf.cnt, c.im03.imf.cnt,
c.im04.imf.cnt, c.im05.imf.cnt, c.im06.imf.cnt, c.im07.imf.cnt);
$write("| %d %d %d %d %d %d %d %d|",
c.im00.im_deq, c.im01.im_deq, c.im02.im_deq, c.im03.im_deq,
c.im04.im_deq, c.im05.im_deq, c.im06.im_deq, c.im07.im_deq);
if (c.F01_deq) $write("%d", c.F01_dot); else $write(" ");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if(c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.phase==`LAST_PHASE && c.F01_deq) begin
$write("%08x ", c.F01_dot);
$fwrite(fp, "%08x ", c.F01_dot);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sync_pulse_synchronizer.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// Synchronizer without reset for use in cluster_header_sync.
// For simulation only.
module sync_pulse_synchronizer (/*AUTOARG*/
// Outputs
sync_out, so,
// Inputs
async_in, gclk, rclk, si, se
);
output sync_out;
output so;
input async_in;
input gclk;
input rclk;
input si;
input se;
wire pre_sync_out;
wire so_rptr;
wire so_lockup;
// Flop drive strengths to be adjusted as necessary
bw_u1_soff_8x repeater (
.q (pre_sync_out),
.so (so_rptr),
.ck (gclk),
.d (async_in),
.se (se),
.sd (si)
);
bw_u1_scanl_2x lockup (
.so (so_lockup),
.sd (so_rptr),
.ck (gclk)
);
bw_u1_soff_8x syncff (
.q (sync_out),
.so (so),
.ck (rclk),
.d (pre_sync_out),
.se (se),
.sd (so_lockup)
);
endmodule // sync_pulse_synchronizer
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_TB_V
`define SKY130_FD_SC_LS__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFSTP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_BLACKBOX_V
|
// Filename: channel_tb1.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module connecting transmit to receive. This uses a clock of
// sufficent period to ensure that the parity gen can keep up.
`timescale 1ns/100ps
module channel_tb1();
reg enable; // Enable for counter
reg clear; // Clear for counter
reg clk_en; // Clock enable
wire clk; // Wire connecting clock to counter and both regs
wire[9:0] data; // Bus connecting transmit and receive modules
wire[8:0] data_out; // Data output of receive
wire data_valid; // Output of comparator from receive module
// Transmit module containing counter and parity gen.
transmit DUT1(enable, clear, clk, data);
// Receive module containing reg, parity gen, and comparator
receive DUT2(clk, data, data_out, data_valid);
// Clock feeding counter and both regs, period set to 100
clk #(100) DUT3(clk_en, clk);
// Using similar inputs as ctr_tb.v
initial begin
enable = 0;
clear = 0;
clk_en = 1;
#10 clear = 1;
#40 clear = 0;
#50 enable = 1;
#400 enable = 0;
#100 enable = 1;
#500 clear = 1;
#60 clear = 0;
end
endmodule |
////////////////////////////////////////////////////////////////////////////////////////////////////////////
/// network_interface include: pass fifo, which is used to pass non_local messages to next node ///////////
/// IN_local req fifo and rep fifo,which is used to buffers msgs to local node//
/// OUT_local req fifo and rep fifo ,which is used to buffers msgs leave local//
/// and some other FSMs to help manage these fifos! ////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
module network_interface(
//input
clk, //global clock
rst, //global reset
ctrl_in, //[2:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
//ctrl[2] 1:next_node; 0:not_next_node;
flit_in,
dest_fifo_in,
en_IN_req_deq, // from arbiter_for_IN_node in commu_assist
en_IN_rep_deq,
enq_req_data, // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
enq_rep_data, // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
en_OUT_req_enq, // from arbiter_for_OUT_req fifo in commu_assist
en_OUT_rep_enq, // from arbiter_for_OUT_rep fifo in commu_assist
en_local_req_in,
en_local_rep_in,
en_pass_req_in,
en_pass_rep_in,
used_slots_pass_req_in,
used_slots_pass_rep_in, //the pass req fifo of next node says it can receive a flit
//output
deq_req_data, //[17:0]cache or memory dequeue a flit from IN_local req fifo
deq_rep_data, //[17:0]cache or memory dequeue a flit from IN_local rep fifo
req_rdy,
rep_rdy,
en_local_req, // to previous node refer to below notes
en_local_rep,
en_pass_req, // from next node //local_in_req fifo in next node says that it can receive
en_pass_rep, // refer to notes below
used_slots_pass_req,
used_slots_pass_rep,
flit_out,
ctrl_out,
dest_fifo_out,
OUT_req_rdy,
OUT_rep_rdy
);
/////// parameter for reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
parameter local_id=2'b00;
parameter next_id=local_id+1;
//input
input clk;
input rst;
input [2:0] ctrl_in;
input [15:0] flit_in;
input [1:0] dest_fifo_in;
input en_IN_req_deq; // from arbiter_for_IN_node in commu_assist
input en_IN_rep_deq;
input [17:0] enq_req_data; // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
input [17:0] enq_rep_data; // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
input en_OUT_req_enq; // from arbiter_for_OUT_req fifo in commu_assist
input en_OUT_rep_enq; // from arbiter_for_OUT_rep fifo in commu_assist
input en_local_req_in; // from next node //local_in_req fifo in next node says that it can receive
input en_local_rep_in; //local_in_req fifo in next node says that it can receive
input en_pass_req_in; //pass_req fifo in next node says that it can receive
input en_pass_rep_in; //pass_req fifo in next node says that it can receive
input [3:0] used_slots_pass_req_in; //pass_req fifo in next node says how many used slots
input [3:0] used_slots_pass_rep_in; //pass_req fifo in next node says how many used slots
//output
output [2:0] ctrl_out;
output [15:0] flit_out;
output [1:0] dest_fifo_out; // used for arbiter_enq to select which fifo to write in
output OUT_req_rdy; // it's ready for ic_req_upload,dc_req_upload or mem_req_upload to enq their req flit
output OUT_rep_rdy; // it's ready for dc_rep_upload or mem_rep_upload to enq their rep flit
output [17:0] deq_req_data; // from IN_req fifo (include ctrl)
output [17:0] deq_rep_data; // from IN_rep fifo (include ctrl)
output req_rdy; // it's ready for arbiter_IN_node to dequeue flit from In req fifo
output rep_rdy; // it's ready for arbiter_IN_node to dequeue flit from In rep fifo
output en_local_req; // to previous node refer to above notes
output en_local_rep;
output en_pass_req;
output en_pass_rep;
output [3:0] used_slots_pass_req;
output [3:0] used_slots_pass_rep;
// output from pass fifos and OUT_local fifos
wire [17:0] pass_rep_dout;
wire [17:0] out_local_rep_dout;
wire [17:0] pass_req_dout;
wire [17:0] out_local_req_dout;
//full state of fifos
wire pass_req_full;
wire pass_rep_full;
wire in_req_full;
wire in_rep_full;
wire out_req_full;
wire out_rep_full;
//empty state of fifos
wire pass_req_empty;
wire pass_rep_empty;
wire IN_local_req_empty;
wire IN_local_rep_empty;
wire OUT_local_req_empty;
wire OUT_local_rep_empty;
//// mux 4 kinds of flits to output to next node
reg [17:0] temp_flit_out;
// arbietr for deq
wire [3:0] select;
wire next_pass_req;
wire next_pass_rep;
wire next_local_req;
wire next_local_rep;
//arbiter for enq
wire [15:0] flit2pass_req; // seled flit output to pass req
wire [1:0] ctrl2pass_req; // seled ctrl output to pass req
wire [15:0] flit2pass_rep; // seled flit output to pass req
wire [1:0] ctrl2pass_rep; // seled ctrl output to pass req
wire [15:0] flit2local_in_req; // seled flit output to pass req
wire [1:0] ctrl2local_in_req; // seled ctrl output to pass req
wire [15:0] flit2local_in_rep; // seled flit output to pass req
wire [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
wire en_pass_req; // enable for pass req fifo to write data to tail
wire en_pass_rep; // enable for pass rep fifo to write data to tail
wire en_local_in_req; // enable for local in req fifo to write data to tail
wire en_local_in_rep; // enable for local in rep fifo to write data to tail
// output to uploads saying it's ready for them to receive flits from uploads
assign OUT_req_rdy=!out_req_full;
assign OUT_rep_rdy=!out_rep_full;
// to previous node refer to below notes
assign en_local_req=!in_req_full;
assign en_local_rep=!in_rep_full;
//assign en_pass_req=!pass_req_full; // from next node //local_in_req fifo in next node says that it can receive
//assign en_pass_rep=!pass_rep_full; // refer to notes below
// output to arbiter_IN_node to tell it it's ready for them to deq flit from IN_local fifos
assign req_rdy=!IN_local_req_empty;
assign rep_rdy=!IN_local_rep_empty;
//wires just for convenience
assign flit_out=temp_flit_out[15:0];
assign ctrl_out=temp_flit_out[17:16];
wire next_or_not;
assign next_or_not=(flit_out[15:14]==next_id)?1'b1:1'b0;
assign dest_fifo_out={next_or_not,flit_out[9]};
// figure out which fifo output its flit to next node
always@(*)
begin
case(select)
4'b0001:temp_flit_out=pass_rep_dout;
4'b0010:temp_flit_out=out_local_rep_dout;
4'b0100:temp_flit_out=pass_req_dout;
4'b1000:temp_flit_out=out_local_req_dout;
default:temp_flit_out=pass_rep_dout;
endcase
end
reg [1:0] OUT_rep_length_code;
// use hesd flit of every msg at the head of OUT_local_rep fifo
// to produce OUT_rep_length_code ,which is usefull to avoid deadlock
always@(*)
begin
if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==ATflurep_cmd||out_local_rep_dout[9:5]==wbrep_cmd))
OUT_rep_length_code=2'b11;//msg has 11 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==exrep_cmd||out_local_rep_dout[9:5]==shrep_cmd||out_local_rep_dout[9:5]==instrep_cmd||out_local_rep_dout[9:5]==SH_exrep_cmd))
OUT_rep_length_code=2'b10; //msg has 9 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==nackrep_cmd||out_local_rep_dout[9:5]==flushrep_cmd||out_local_rep_dout[9:5]==C2Hinvrep_cmd||out_local_rep_dout[9:5]==flushfail_rep_cmd||out_local_rep_dout[9:5]==wbfail_rep_cmd))
OUT_rep_length_code=2'b01; //msg has 3 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==C2Cinvrep_cmd||out_local_rep_dout[9:5]==nackrep_cmd))
OUT_rep_length_code=2'b00; // msg has only 1 flit
else //default valus
OUT_rep_length_code=2'b00; // msg has only 1 flit
end
my_scfifo pass_req_fifo(
.aclr(rst),
.clock(clk),
.data({ctrl2pass_req,flit2pass_req}),
.rdreq(select[2]),
.wrreq(en_pass_req),
.empty(pass_req_empty),
.full(pass_req_full),
.q(pass_req_dout),
.usedw(used_slots_pass_req)
);
my_scfifo pass_rep_fifo(
.aclr(rst),
.clock(clk),
.data({ctrl2pass_rep,flit2pass_rep}),
.rdreq(select[0]),
.wrreq(en_pass_rep),
.empty(pass_rep_empty),
.full(pass_rep_full),
.q(pass_rep_dout),
.usedw(used_slots_pass_rep)
);
my_scfifo IN_req_fifo(
.aclr(rst),
.clock(clk),
.data({ctrl2local_in_req,flit2local_in_req}),
.rdreq(en_IN_req_deq),
.wrreq(en_local_in_req),
.empty(IN_local_req_empty),
.full(in_req_full),
.q({deq_req_data}),
.usedw()
);
my_scfifo IN_rep_fifo(
.aclr(rst),
.clock(clk),
.data({ctrl2local_in_rep,flit2local_in_rep}),
.rdreq(en_IN_rep_deq),
.wrreq(en_local_in_rep),
.empty(IN_local_rep_empty),
.full(in_rep_full),
.q({deq_rep_data}),
.usedw()
);
my_scfifo OUT_req_fifo(
.aclr(rst),
.clock(clk),
.data({enq_req_data}),
.rdreq(select[3]),
.wrreq(en_OUT_req_enq),
.empty(OUT_local_req_empty),
.full(out_req_full),
.q(out_local_req_dout),
.usedw()
);
my_scfifo OUT_rep_fifo(
.aclr(rst),
.clock(clk),
.data({enq_rep_data}),
.rdreq(select[1]),
.wrreq(en_OUT_rep_enq),
.empty(OUT_local_rep_empty),
.full(out_rep_full),
.q(out_local_rep_dout),
.usedw()
);
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////Here need a arbiter to decide which flit to select to send out/////////
////////////////////from pass rep/req fifo, OUT_local rep/req fifo ////////////////
///////////////////////////////////////////////////////////////////////////////////////////
arbiter_4_deq my_arbiter_4_deq(
//input
.clk(clk),
.rst(rst),
.pass_req_empty(pass_req_empty),
.pass_rep_empty(pass_rep_empty),
.OUT_local_req_empty(OUT_local_req_empty),
.OUT_local_rep_empty(OUT_local_rep_empty),
.OUT_rep_length_code(OUT_rep_length_code),
.en_local_req(en_local_req_in),
.en_local_rep(en_local_rep_in),
.en_pass_req(en_pass_req_in),
.en_pass_rep(en_pass_rep_in),
.used_slots_pass_req(used_slots_pass_req_in),
.used_slots_pass_rep(used_slots_pass_rep_in),
.next_pass_req(next_pass_req),
.next_pass_rep(next_pass_rep),
.next_local_req(next_local_req),
.next_local_rep(next_local_rep),
//output
.select(select)
);
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////Here need a arbiter to decide which fifo to select to write flit in////
////////////////////write to pass rep/req fifo ,IN_local rep/req fifo ///////////////
///////////////////////////////////////////////////////////////////////////////////////////
arbiter_4_enq my_arbiter_4_enq( // input
.flit(flit_in),
.ctrl(ctrl_in),
.en_dest_fifo(|ctrl_in),
.dest_fifo(dest_fifo_in),
// output
.flit2pass_req(flit2pass_req), // seled flit output to pass req
.ctrl2pass_req(ctrl2pass_req), // seled ctrl output to pass req
.flit2pass_rep(flit2pass_rep), // seled flit output to pass rep
.ctrl2pass_rep(ctrl2pass_rep), // seled ctrl output to pass rep
.flit2local_in_req(flit2local_in_req), // seled flit output to local in req
.ctrl2local_in_req(ctrl2local_in_req), // seled ctrl output to local in req
.flit2local_in_rep(flit2local_in_rep), // seled flit output to local in rep
.ctrl2local_in_rep(ctrl2local_in_rep), // seled ctrl output to local in rep
.en_pass_req(en_pass_req),
.en_pass_rep(en_pass_rep),
.en_local_in_req(en_local_in_req),
.en_local_in_rep(en_local_in_rep)
);
endmodule
///////////////////////////////////////////////////////////////////////////////////////////
////////////here we process cache request or memory request for dequeuing IN_local fifo////
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////here we process cache reply or memory reply for dequeuing OUT_local fifo///////
////////////////////////////////////////////////////////////////////////////////////////////
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:47:43 03/06/2017
// Design Name: MUX32
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testMUX32.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MUX32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testMUX32;
// Inputs
reg [31:0] in;
reg [4:0] sel;
// Outputs
wire out;
// Instantiate the DESIGN Under Test (DUT)
MUX32 dut (
.in(in),
.sel(sel),
.out(out)
);
/*
//integer i;
initial begin
// Initialize Inputs
in = 0;
sel = 0;
for(sel=0;sel<=4'b1111 ;sel=sel+1) begin
// Wait 100 ns for global reset to finish
for(in=0;in<=32'hEEEEEEEE ;in=in+1) begin
#30;
end
end
// Add stimulus here
end
*/
initial begin
// Initialize Inputs
in = 0;
sel = 0;
#30;
in=32'hEEEEEEEE ;
sel=4'b1111 ;
#30;
in=32'hEE0E5EA0 ;
sel=4'b0010 ;
#30;
in=32'hEEEE5EEE ;
sel=4'b1011 ;
#30;
in=32'h000050A0 ;
sel=4'b1000 ;
#30;
in=32'hEE3EEEEE ;
sel=4'b1011 ;
#30;
in=32'h0AB000A0 ;
sel=4'b1011 ;
#30;
in=32'hEE0E5EEE ;
sel=4'b1001 ;
#30;
in=32'h0AB000B0 ;
sel=4'b0011 ;
#30;
in=32'hEE0E5EAE ;
sel=4'b0011 ;
#30;
in=32'hEA003070 ;
sel=4'b1111 ;
#30;
in=32'h100200E5 ;
sel=4'b0110 ;
#30;
in=32'hD0D020E0 ;
sel=4'b1001 ;
#30;
in=32'h0607A061 ;
sel=4'b0001 ;
#30;
in=32'h09005E00 ;
sel=4'b1000 ;
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
// altera message_level level1
`timescale 1ns / 100ps
module soc_system_hps_only_master_timing_adt (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [ 7: 0] in_data,
// Interface: out
output reg out_valid,
output reg [ 7: 0] out_data,
input out_ready
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 7: 0] in_payload;
reg [ 7: 0] out_payload;
reg [ 0: 0] ready;
reg in_ready;
// synthesis translate_off
always @(negedge in_ready) begin
$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
end
// synthesis translate_on
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data};
{out_data} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[0] = out_ready;
out_valid = in_valid;
out_payload = in_payload;
in_ready = ready[0];
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [0:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign flash_addr_wire =
(valid_csr_erase && valid_csr_sector_erase_addr) ? { flash_sector_addr, 1'b0, {(19){1'b1}} } : flash_page_addr;
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
assign flash_addr_wire = flash_page_addr;
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1) || (avmm_read == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = avmm_addr; // (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && read_state == READ_STATE_READY);
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
assign avmm_readdata = (csr_status_r_pass) ? flash_drdout : 32'hffffffff;
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
read_wait <= 1;
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_SETUP;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_READ;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 4) begin
read_wait <= 0;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
end
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:36 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_bram_0_stub.v
// Design : zynq_design_1_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
`timescale 1 ns / 1 ps
`include "myip_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
// Burst Size Defines
`define BURST_SIZE_4_BYTES 3'b010
// Lock Type Defines
`define LOCK_TYPE_NORMAL 1'b0
// AMBA S01_AXI AXI4 Range Constants
`define S01_AXI_MAX_BURST_LENGTH 8'b1111_1111
`define S01_AXI_MAX_DATA_SIZE (`S01_AXI_DATA_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1))/8
`define S01_AXI_DATA_BUS_WIDTH 32
`define S01_AXI_ADDRESS_BUS_WIDTH 32
`define S01_AXI_RUSER_BUS_WIDTH 1
`define S01_AXI_WUSER_BUS_WIDTH 1
module myip_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// AMBA S01_AXI AXI4 Local Reg
reg [(`S01_AXI_DATA_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S01_AXI_rd_data;
reg [(`S01_AXI_DATA_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S01_AXI_test_data [2:0];
reg [(`RESP_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1))-1:0] S01_AXI_vresponse;
reg [`S01_AXI_ADDRESS_BUS_WIDTH-1:0] S01_AXI_mtestAddress;
reg [(`S01_AXI_RUSER_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1))-1:0] S01_AXI_v_ruser;
reg [(`S01_AXI_WUSER_BUS_WIDTH*(`S01_AXI_MAX_BURST_LENGTH+1))-1:0] S01_AXI_v_wuser;
reg [`RESP_BUS_WIDTH-1:0] S01_AXI_response;
integer S01_AXI_mtestID; // Master side testID
integer S01_AXI_mtestBurstLength;
integer S01_AXI_mtestvector; // Master side testvector
integer S01_AXI_mtestdatasize;
integer S01_AXI_mtestCacheType = 0;
integer S01_AXI_mtestProtectionType = 0;
integer S01_AXI_mtestRegion = 0;
integer S01_AXI_mtestQOS = 0;
integer S01_AXI_mtestAWUSER = 0;
integer S01_AXI_mtestARUSER = 0;
integer S01_AXI_mtestBUSER = 0;
integer result_slave_full;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_full = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
result_slave_full = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
task automatic S01_AXI_TEST;
begin
//---------------------------------------------------------------------
// EXAMPLE TEST 1:
// Simple sequential write and read burst transfers example
// DESCRIPTION:
// The following master code does a simple write and read burst for
// each burst transfer type.
//---------------------------------------------------------------------
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S01_AXI:");
$display("Simple sequential write and read burst transfers example");
$display("---------------------------------------------------------");
S01_AXI_mtestID = 1;
S01_AXI_mtestvector = 0;
S01_AXI_mtestBurstLength = 15;
S01_AXI_mtestAddress = `S01_AXI_SLAVE_ADDRESS;
S01_AXI_mtestCacheType = 0;
S01_AXI_mtestProtectionType = 0;
S01_AXI_mtestdatasize = `S01_AXI_MAX_DATA_SIZE;
S01_AXI_mtestRegion = 0;
S01_AXI_mtestQOS = 0;
S01_AXI_mtestAWUSER = 0;
S01_AXI_mtestARUSER = 0;
result_slave_full = 1;
dut.`BD_INST_NAME.master_1.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S01_AXI_mtestID,
S01_AXI_mtestAddress,
S01_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_INCR,
`LOCK_TYPE_NORMAL,
S01_AXI_mtestCacheType,
S01_AXI_mtestProtectionType,
S01_AXI_test_data[S01_AXI_mtestvector],
S01_AXI_mtestdatasize,
S01_AXI_mtestRegion,
S01_AXI_mtestQOS,
S01_AXI_mtestAWUSER,
S01_AXI_v_wuser,
S01_AXI_response,
S01_AXI_mtestBUSER);
$display("EXAMPLE TEST 1 : DATA = 0x%h, response = 0x%h",S01_AXI_test_data[S01_AXI_mtestvector],S01_AXI_response);
CHECK_RESPONSE_OKAY(S01_AXI_response);
S01_AXI_mtestID = S01_AXI_mtestID+1;
dut.`BD_INST_NAME.master_1.cdn_axi4_master_bfm_inst.READ_BURST(S01_AXI_mtestID,
S01_AXI_mtestAddress,
S01_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_WRAP,
`LOCK_TYPE_NORMAL,
S01_AXI_mtestCacheType,
S01_AXI_mtestProtectionType,
S01_AXI_mtestRegion,
S01_AXI_mtestQOS,
S01_AXI_mtestARUSER,
S01_AXI_rd_data,
S01_AXI_vresponse,
S01_AXI_v_ruser);
$display("EXAMPLE TEST 1 : DATA = 0x%h, vresponse = 0x%h",S01_AXI_rd_data,S01_AXI_vresponse);
CHECK_RESPONSE_OKAY(S01_AXI_vresponse);
// Check that the data received by the master is the same as the test
// vector supplied by the slave.
COMPARE_DATA(S01_AXI_test_data[S01_AXI_mtestvector],S01_AXI_rd_data);
$display("EXAMPLE TEST 1 : Sequential write and read FIXED burst transfers complete from the master side.");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S01_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_full ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
dut.`BD_INST_NAME.master_1.cdn_axi4_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S01_AXI_test_data[1] = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
S01_AXI_test_data[0] = 512'h00abcdef111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF;
S01_AXI_test_data[2] = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
S01_AXI_v_ruser = 0;
S01_AXI_v_wuser = 0;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S01_AXI_TEST();
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_1_V
`define SKY130_FD_SC_HVL__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 21 11:24:56 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[31:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[31:0],probe16[0:0],probe17[0:0],probe18[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [31:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [31:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module nios_system_VGA_Controller (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:45:31 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J55_123_4652_n8, DP_OP_15J55_123_4652_n7,
DP_OP_15J55_123_4652_n6, DP_OP_15J55_123_4652_n5,
DP_OP_15J55_123_4652_n4, intadd_61_B_12_, intadd_61_B_11_,
intadd_61_B_10_, intadd_61_B_9_, intadd_61_B_8_, intadd_61_B_7_,
intadd_61_B_6_, intadd_61_B_5_, intadd_61_B_4_, intadd_61_B_3_,
intadd_61_B_2_, intadd_61_B_1_, intadd_61_B_0_, intadd_61_CI,
intadd_61_SUM_12_, intadd_61_SUM_11_, intadd_61_SUM_10_,
intadd_61_SUM_9_, intadd_61_SUM_8_, intadd_61_SUM_7_,
intadd_61_SUM_6_, intadd_61_SUM_5_, intadd_61_SUM_4_,
intadd_61_SUM_3_, intadd_61_SUM_2_, intadd_61_SUM_1_,
intadd_61_SUM_0_, intadd_61_n13, intadd_61_n12, intadd_61_n11,
intadd_61_n10, intadd_61_n9, intadd_61_n8, intadd_61_n7, intadd_61_n6,
intadd_61_n5, intadd_61_n4, intadd_61_n3, intadd_61_n2, intadd_61_n1,
intadd_62_A_6_, intadd_62_A_4_, intadd_62_A_1_, intadd_62_B_6_,
intadd_62_B_5_, intadd_62_B_4_, intadd_62_B_3_, intadd_62_B_0_,
intadd_62_CI, intadd_62_SUM_6_, intadd_62_SUM_5_, intadd_62_SUM_4_,
intadd_62_SUM_3_, intadd_62_SUM_2_, intadd_62_SUM_1_,
intadd_62_SUM_0_, intadd_62_n7, intadd_62_n6, intadd_62_n5,
intadd_62_n4, intadd_62_n3, intadd_62_n2, intadd_62_n1, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917,
n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1232, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1338,
n1339, n1340, n1341, n1343, n1344, n1345, n1346, n1347, n1348, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1611, n1612, n1613;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1578), .QN(
n883) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1578),
.QN(n880) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1587), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1583), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1580),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1582),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1585),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1581),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1586),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1604), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1606), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1588), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1592), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1589), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1593), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1596), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1596), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1580), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1580), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1580), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1605), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1593), .QN(n885)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1606), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1605), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1596), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1596), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1593), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1592), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1605), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1606), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1605), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1590), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1591), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1607), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1607), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1594), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1607), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1607), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1607), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1591), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n892), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1607), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1593), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1606), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1592), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1593), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1605), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1592), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1606), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1605), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1596), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1593), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n892), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1607), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1604), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1591), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n892), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1594), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1607), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1601), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1591), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1607), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1590), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n892), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1608), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1598), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1599), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1589), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1607), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1598), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1602), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1580), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1588), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1605), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1606), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1605), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1593), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1589), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1588), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n934), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1608), .QN(
n889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1600), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1597), .QN(
n886) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1604), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1600), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1597), .QN(
n890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1604),
.QN(n887) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n934), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1604), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1600), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1598),
.QN(n888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1593), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1602), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1588), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1595), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1598), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n934), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1608), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1600), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1597), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1604), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1603), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1608), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n934), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1600), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1597), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1604), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1606), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1601), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1606), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1602), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1595), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1578), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1594), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1598), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1599), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1602), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1595), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1587), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n934), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1608), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1600), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1597), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1604), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1603), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n934), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1608), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1600), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1597), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1604), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1603), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n934), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1604), .Q(
DmP_mant_SFG_SWR[2]), .QN(n923) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1603), .Q(
DmP_mant_SFG_SWR[3]), .QN(n924) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[6]), .QN(n927) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1604), .Q(
DmP_mant_SFG_SWR[8]), .QN(n932) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[25]), .QN(n920) );
CMPR32X2TS intadd_61_U14 ( .A(n1515), .B(intadd_61_B_0_), .C(intadd_61_CI),
.CO(intadd_61_n13), .S(intadd_61_SUM_0_) );
CMPR32X2TS intadd_61_U13 ( .A(n1521), .B(intadd_61_B_1_), .C(intadd_61_n13),
.CO(intadd_61_n12), .S(intadd_61_SUM_1_) );
CMPR32X2TS intadd_61_U12 ( .A(n1520), .B(intadd_61_B_2_), .C(intadd_61_n12),
.CO(intadd_61_n11), .S(intadd_61_SUM_2_) );
CMPR32X2TS intadd_61_U11 ( .A(n1526), .B(intadd_61_B_3_), .C(intadd_61_n11),
.CO(intadd_61_n10), .S(intadd_61_SUM_3_) );
CMPR32X2TS intadd_61_U10 ( .A(n1525), .B(intadd_61_B_4_), .C(intadd_61_n10),
.CO(intadd_61_n9), .S(intadd_61_SUM_4_) );
CMPR32X2TS intadd_61_U9 ( .A(n1533), .B(intadd_61_B_5_), .C(intadd_61_n9),
.CO(intadd_61_n8), .S(intadd_61_SUM_5_) );
CMPR32X2TS intadd_61_U8 ( .A(n1556), .B(intadd_61_B_6_), .C(intadd_61_n8),
.CO(intadd_61_n7), .S(intadd_61_SUM_6_) );
CMPR32X2TS intadd_61_U7 ( .A(n1555), .B(intadd_61_B_7_), .C(intadd_61_n7),
.CO(intadd_61_n6), .S(intadd_61_SUM_7_) );
CMPR32X2TS intadd_61_U6 ( .A(n1562), .B(intadd_61_B_8_), .C(intadd_61_n6),
.CO(intadd_61_n5), .S(intadd_61_SUM_8_) );
CMPR32X2TS intadd_61_U5 ( .A(n1561), .B(intadd_61_B_9_), .C(intadd_61_n5),
.CO(intadd_61_n4), .S(intadd_61_SUM_9_) );
CMPR32X2TS intadd_61_U4 ( .A(n1570), .B(intadd_61_B_10_), .C(intadd_61_n4),
.CO(intadd_61_n3), .S(intadd_61_SUM_10_) );
CMPR32X2TS intadd_61_U3 ( .A(n1569), .B(intadd_61_B_11_), .C(intadd_61_n3),
.CO(intadd_61_n2), .S(intadd_61_SUM_11_) );
CMPR32X2TS intadd_61_U2 ( .A(n1574), .B(intadd_61_B_12_), .C(intadd_61_n2),
.CO(intadd_61_n1), .S(intadd_61_SUM_12_) );
CMPR32X2TS intadd_62_U8 ( .A(n1531), .B(intadd_62_B_0_), .C(intadd_62_CI),
.CO(intadd_62_n7), .S(intadd_62_SUM_0_) );
CMPR32X2TS intadd_62_U7 ( .A(intadd_62_A_1_), .B(n895), .C(intadd_62_n7),
.CO(intadd_62_n6), .S(intadd_62_SUM_1_) );
CMPR32X2TS intadd_62_U6 ( .A(n879), .B(n896), .C(intadd_62_n6), .CO(
intadd_62_n5), .S(intadd_62_SUM_2_) );
CMPR32X2TS intadd_62_U5 ( .A(n1553), .B(intadd_62_B_3_), .C(intadd_62_n5),
.CO(intadd_62_n4), .S(intadd_62_SUM_3_) );
CMPR32X2TS intadd_62_U4 ( .A(intadd_62_A_4_), .B(intadd_62_B_4_), .C(
intadd_62_n4), .CO(intadd_62_n3), .S(intadd_62_SUM_4_) );
CMPR32X2TS intadd_62_U3 ( .A(n1559), .B(intadd_62_B_5_), .C(intadd_62_n3),
.CO(intadd_62_n2), .S(intadd_62_SUM_5_) );
CMPR32X2TS intadd_62_U2 ( .A(intadd_62_A_6_), .B(intadd_62_B_6_), .C(
intadd_62_n2), .CO(intadd_62_n1), .S(intadd_62_SUM_6_) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[25]), .QN(n1613) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[15]), .QN(n1612) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1585),
.Q(intDY_EWSW[11]), .QN(n1611) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n934), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1560) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1603), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1554) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1590), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1532) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1604), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1514) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1563) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1604), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1485) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n892), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1510) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1607), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1517) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1489) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n892), .Q(
DMP_SFG[7]), .QN(n1559) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1607), .Q(
DMP_SFG[5]), .QN(n1553) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1484) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1486) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n892), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1488) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n892), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1483) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1579), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1530) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1606), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1504) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1493) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1599), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1492) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[19]), .QN(n1501) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1578),
.Q(intDY_EWSW[27]), .QN(n1551) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[24]), .QN(n1487) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[16]), .QN(n1545) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1585), .Q(
intDY_EWSW[9]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1584), .Q(
intDY_EWSW[6]), .QN(n1528) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1592),
.Q(intDY_EWSW[28]), .QN(n1548) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1481) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1593), .Q(
intDY_EWSW[0]), .QN(n1498) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1583), .Q(
intDY_EWSW[2]), .QN(n1541) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1593), .Q(
intDY_EWSW[4]), .QN(n1542) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1582), .Q(
intDY_EWSW[7]), .QN(n1529) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1581), .Q(
intDY_EWSW[5]), .QN(n1497) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1580),
.Q(intDX_EWSW[26]), .QN(n1571) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[28]), .QN(n1524) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[26]), .QN(n1505) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[24]), .QN(n1502) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[25]), .QN(n1568) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1606), .Q(
DMP_EXP_EWSW[25]), .QN(n1557) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[26]), .QN(n1507) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1592), .Q(
DMP_EXP_EWSW[24]), .QN(n1503) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1509) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1583), .Q(
shift_value_SHT2_EWR[3]), .QN(n1511) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1607), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1512) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1508) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1479) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1480) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1491) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[10]), .QN(n1572) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1583), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1496) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1558) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1604), .Q(
OP_FLAG_SFG) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n934), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1482) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1585),
.Q(intDY_EWSW[23]), .QN(n1549) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[22]), .QN(n1499) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[21]), .QN(n1538) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[20]), .QN(n1546) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[14]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1584),
.Q(intDY_EWSW[13]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[12]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1580),
.Q(intDY_EWSW[30]), .QN(n1550) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[29]), .QN(n1500) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1584),
.Q(intDY_EWSW[26]), .QN(n1547) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[18]), .QN(n1552) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1586), .Q(
intDY_EWSW[8]), .QN(n1540) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1585), .Q(
intDY_EWSW[3]), .QN(n1535) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1587), .Q(
intDY_EWSW[1]), .QN(n1539) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1580),
.Q(intDX_EWSW[25]), .QN(n1506) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[24]), .QN(n1567) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[16]), .QN(n1518) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1587), .Q(
intDX_EWSW[7]), .QN(n1495) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[6]), .QN(n1519) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1580), .Q(
intDX_EWSW[5]), .QN(n1513) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[4]), .QN(n1494) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1583), .Q(
shift_value_SHT2_EWR[4]), .QN(n1516) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[23]), .QN(n1564) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1584), .Q(
Data_array_SWR[14]), .QN(n1566) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1581), .Q(
Data_array_SWR[12]), .QN(n1565) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1592), .Q(
DMP_SFG[18]), .QN(n1562) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1591), .Q(
LZD_output_NRM2_EW[4]), .QN(n1534) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1580), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1580),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1578), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1606), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1583), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1606), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1587), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1580), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1584), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1599), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1592), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1580), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1581), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1584), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1580), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1594), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1588), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[31]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[10]), .QN(n881) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1608), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n934), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1602), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1602), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n934), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1608), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1597), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1590), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1597), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1592), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1589), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1605), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1606), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1603), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1605), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1584),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[17]), .QN(n1577) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1591), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n892), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1590), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1580),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1580),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1592), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1606), .Q(
DmP_mant_SFG_SWR[22]), .QN(n917) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[23]), .QN(n912) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1581), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1584), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1607), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n892), .Q(
DMP_SFG[4]), .QN(n879) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1608), .Q(
DmP_mant_SFG_SWR[0]), .QN(n921) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1597), .Q(
DmP_mant_SFG_SWR[1]), .QN(n922) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n934), .Q(
DmP_mant_SFG_SWR[4]), .QN(n925) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1597), .Q(
DmP_mant_SFG_SWR[7]), .QN(n931) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1603), .Q(
DmP_mant_SFG_SWR[9]), .QN(n930) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1605), .Q(
DmP_mant_SFG_SWR[16]), .QN(n929) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[17]), .QN(n928) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[18]), .QN(n913) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[19]), .QN(n914) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[20]), .QN(n915) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[21]), .QN(n916) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[23]), .QN(n918) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[24]), .QN(n919) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1594), .Q(
DMP_SFG[22]), .QN(n1574) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1607), .Q(
DMP_SFG[21]), .QN(n1569) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n934), .Q(
DMP_SFG[20]), .QN(n1570) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1590), .Q(
DMP_SFG[19]), .QN(n1561) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1589), .Q(
DMP_SFG[17]), .QN(n1555) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1593), .Q(
DMP_SFG[16]), .QN(n1556) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1596), .Q(
DMP_SFG[15]), .QN(n1533) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1596), .Q(
DMP_SFG[14]), .QN(n1525) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1592), .Q(
DMP_SFG[13]), .QN(n1526) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1596), .Q(
DMP_SFG[12]), .QN(n1520) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1589), .Q(
DMP_SFG[11]), .QN(n1521) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1594), .Q(
DMP_SFG[10]), .QN(n1515) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1606), .Q(
DMP_SFG[2]), .QN(n1531) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1607), .Q(
LZD_output_NRM2_EW[2]), .QN(n1523) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1601), .Q(
LZD_output_NRM2_EW[3]), .QN(n1527) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1591), .Q(
LZD_output_NRM2_EW[1]), .QN(n1522) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1608), .Q(
DmP_mant_SFG_SWR[5]), .QN(n926) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1578), .Q(
n1490), .QN(n1573) );
ADDFX1TS DP_OP_15J55_123_4652_U8 ( .A(n1522), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J55_123_4652_n8), .CO(DP_OP_15J55_123_4652_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J55_123_4652_U7 ( .A(n1523), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J55_123_4652_n7), .CO(DP_OP_15J55_123_4652_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J55_123_4652_U6 ( .A(n1527), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J55_123_4652_n6), .CO(DP_OP_15J55_123_4652_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J55_123_4652_U5 ( .A(n1534), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J55_123_4652_n5), .CO(DP_OP_15J55_123_4652_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1579), .Q(
Shift_reg_FLAGS_7[1]), .QN(n874) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1579), .Q(
n873), .QN(n1575) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1587), .Q(
Shift_reg_FLAGS_7_6), .QN(n877) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1587), .Q(
Shift_reg_FLAGS_7[0]), .QN(n872) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1587), .Q(
n933), .QN(n1609) );
NAND2X4TS U897 ( .A(n1170), .B(n1295), .Y(n1156) );
AOI222X4TS U898 ( .A0(Data_array_SWR[21]), .A1(n1411), .B0(
Data_array_SWR[17]), .B1(n1410), .C0(Data_array_SWR[25]), .C1(n1396),
.Y(n1433) );
NOR2X4TS U899 ( .A(n1170), .B(n1212), .Y(n1171) );
NAND2X4TS U900 ( .A(n1152), .B(n1311), .Y(n1151) );
AOI211X2TS U901 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1139), .B0(n1267), .C0(
n1138), .Y(n1153) );
AOI222X2TS U902 ( .A0(DMP_SFG[7]), .A1(n1246), .B0(DMP_SFG[7]), .B1(n1245),
.C0(n1246), .C1(n1245), .Y(n1247) );
CLKINVX6TS U903 ( .A(n1305), .Y(n1168) );
INVX3TS U904 ( .A(n1297), .Y(n905) );
NAND3X1TS U905 ( .A(n1124), .B(n1261), .C(Raw_mant_NRM_SWR[1]), .Y(n1255) );
NAND3X1TS U906 ( .A(n1145), .B(n1131), .C(n1256), .Y(n1267) );
OAI211X1TS U907 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1130), .B0(n1260), .C0(
n1517), .Y(n1131) );
BUFX4TS U908 ( .A(n1038), .Y(n894) );
OAI21X1TS U909 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1122), .Y(n1123) );
NOR2X4TS U910 ( .A(n1018), .B(n1068), .Y(n1026) );
INVX4TS U911 ( .A(n1284), .Y(n875) );
NOR2X6TS U912 ( .A(n1475), .B(n1421), .Y(n1374) );
AND2X4TS U913 ( .A(beg_OP), .B(n1278), .Y(n1282) );
NOR2X6TS U914 ( .A(shift_value_SHT2_EWR[4]), .B(n1390), .Y(n1373) );
NAND2X2TS U915 ( .A(n897), .B(n1430), .Y(n1335) );
CLKBUFX2TS U916 ( .A(n932), .Y(n891) );
NAND3X1TS U917 ( .A(n1509), .B(n1492), .C(n1481), .Y(n1253) );
CLKINVX6TS U918 ( .A(rst), .Y(n934) );
NAND2BXLTS U919 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n968) );
NAND2BXLTS U920 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1002) );
NAND2BXLTS U921 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n956) );
NAND2BXLTS U922 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n981) );
NAND2BXLTS U923 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n977) );
NAND2BXLTS U924 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n996) );
NAND3XLTS U925 ( .A(n1547), .B(n956), .C(intDX_EWSW[26]), .Y(n958) );
NAND3BXLTS U926 ( .AN(n1000), .B(n998), .C(n997), .Y(n1016) );
AO22XLTS U927 ( .A0(n1366), .A1(n927), .B0(DmP_mant_SFG_SWR[6]), .B1(n1365),
.Y(n876) );
AO22XLTS U928 ( .A0(n1366), .A1(n926), .B0(DmP_mant_SFG_SWR[5]), .B1(n1365),
.Y(n878) );
AOI222X4TS U929 ( .A0(Data_array_SWR[14]), .A1(n1373), .B0(
Data_array_SWR[22]), .B1(n1437), .C0(Data_array_SWR[18]), .C1(n1436),
.Y(n1386) );
AOI222X4TS U930 ( .A0(Data_array_SWR[23]), .A1(n1437), .B0(
Data_array_SWR[19]), .B1(n1436), .C0(Data_array_SWR[15]), .C1(n1373),
.Y(n1382) );
AOI222X4TS U931 ( .A0(Data_array_SWR[24]), .A1(n1437), .B0(
Data_array_SWR[20]), .B1(n1436), .C0(Data_array_SWR[16]), .C1(n1373),
.Y(n1378) );
AOI222X4TS U932 ( .A0(Data_array_SWR[21]), .A1(n1436), .B0(
Data_array_SWR[17]), .B1(n1373), .C0(Data_array_SWR[25]), .C1(n1437),
.Y(n1379) );
NAND2BXLTS U933 ( .AN(n1269), .B(n949), .Y(n951) );
OAI21XLTS U934 ( .A0(n1517), .A1(n1297), .B0(n1194), .Y(n1195) );
AOI222X1TS U935 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n905), .B0(n909), .B1(n900),
.C0(n1294), .C1(DmP_mant_SHT1_SW[10]), .Y(n1223) );
AOI222X1TS U936 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1294), .C1(n898), .Y(n1180) );
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1294), .C1(DmP_mant_SHT1_SW[3]), .Y(n1185)
);
AOI222X1TS U938 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1294), .C1(DmP_mant_SHT1_SW[8]), .Y(n1188)
);
AOI222X1TS U939 ( .A0(n1239), .A1(DMP_SFG[1]), .B0(n1239), .B1(n893), .C0(
DMP_SFG[1]), .C1(n893), .Y(intadd_62_CI) );
AOI222X1TS U940 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1294), .C1(DmP_mant_SHT1_SW[7]), .Y(n1209)
);
AOI222X1TS U941 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1294), .C1(DmP_mant_SHT1_SW[16]), .Y(n1230) );
AOI211X1TS U942 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n874), .B0(n1214), .C0(
n1213), .Y(n1288) );
OAI21XLTS U943 ( .A0(n1488), .A1(n1297), .B0(n1198), .Y(n1199) );
OAI21XLTS U944 ( .A0(n1485), .A1(n1125), .B0(n1255), .Y(n1126) );
AO22XLTS U945 ( .A0(n1366), .A1(DmP_mant_SFG_SWR[3]), .B0(n1365), .B1(n924),
.Y(n882) );
OAI21XLTS U946 ( .A0(n1504), .A1(n1297), .B0(n1296), .Y(n1298) );
NAND4XLTS U947 ( .A(n1257), .B(n1256), .C(n1255), .D(n1262), .Y(n1258) );
OAI211XLTS U948 ( .A0(n1265), .A1(n1264), .B0(n1263), .C0(n1262), .Y(n1266)
);
AOI222X1TS U949 ( .A0(n1398), .A1(n1475), .B0(Data_array_SWR[8]), .B1(n1445),
.C0(n1397), .C1(n1418), .Y(n1464) );
AOI222X1TS U950 ( .A0(n1398), .A1(n1444), .B0(Data_array_SWR[8]), .B1(n1374),
.C0(n1397), .C1(n1417), .Y(n1453) );
AOI222X1TS U951 ( .A0(n1393), .A1(n1475), .B0(Data_array_SWR[9]), .B1(n1445),
.C0(n1392), .C1(n1418), .Y(n1463) );
AOI222X1TS U952 ( .A0(n1393), .A1(n1444), .B0(Data_array_SWR[9]), .B1(n1374),
.C0(n1392), .C1(n1417), .Y(n1454) );
AO22XLTS U953 ( .A0(n1346), .A1(DmP_EXP_EWSW[22]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
OAI21XLTS U954 ( .A0(n1206), .A1(n1151), .B0(n1205), .Y(n791) );
OAI211XLTS U955 ( .A0(n1230), .A1(n1151), .B0(n1229), .C0(n1228), .Y(n788)
);
OAI21XLTS U956 ( .A0(n1206), .A1(n1168), .B0(n1197), .Y(n789) );
OAI211XLTS U957 ( .A0(n1188), .A1(n1151), .B0(n1187), .C0(n1186), .Y(n780)
);
AOI2BB2XLTS U958 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1303), .A0N(n1223), .A1N(
n1168), .Y(n1186) );
AO22XLTS U959 ( .A0(n1281), .A1(Data_X[19]), .B0(n1286), .B1(intDX_EWSW[19]),
.Y(n843) );
AO22XLTS U960 ( .A0(n1282), .A1(Data_X[30]), .B0(n1279), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U961 ( .A0(n1287), .A1(Data_X[10]), .B0(n1286), .B1(intDX_EWSW[10]),
.Y(n852) );
AO22XLTS U962 ( .A0(n1287), .A1(Data_Y[31]), .B0(n875), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U963 ( .A0(n1469), .A1(DMP_SHT2_EWSW[0]), .B0(n1465), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U964 ( .A0(n1490), .A1(DmP_EXP_EWSW[0]), .B0(n1347), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U965 ( .A0(n1490), .A1(DmP_EXP_EWSW[1]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U966 ( .A0(n1490), .A1(DmP_EXP_EWSW[2]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U967 ( .A0(n1490), .A1(DmP_EXP_EWSW[6]), .B0(n1338), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U968 ( .A0(n1346), .A1(DmP_EXP_EWSW[15]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U969 ( .A0(n1346), .A1(DmP_EXP_EWSW[12]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U970 ( .A0(n1346), .A1(DmP_EXP_EWSW[18]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U971 ( .A0(n1346), .A1(DmP_EXP_EWSW[14]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U972 ( .A0(n1346), .A1(DmP_EXP_EWSW[13]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U973 ( .A0(n1490), .A1(DmP_EXP_EWSW[8]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U974 ( .A0(n1346), .A1(DmP_EXP_EWSW[21]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U975 ( .A0(n1346), .A1(DmP_EXP_EWSW[16]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U976 ( .A0(n1346), .A1(DmP_EXP_EWSW[17]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U977 ( .A0(n1346), .A1(DmP_EXP_EWSW[20]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U978 ( .A0(n1287), .A1(Data_X[31]), .B0(n1285), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U979 ( .A0(n1459), .A1(DMP_SHT2_EWSW[1]), .B0(n1335), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U980 ( .A0(n1478), .A1(DMP_SHT2_EWSW[9]), .B0(n1462), .B1(
DMP_SFG[9]), .Y(n690) );
OAI211XLTS U981 ( .A0(n1185), .A1(n1151), .B0(n1167), .C0(n1166), .Y(n775)
);
OAI211XLTS U982 ( .A0(n1188), .A1(n1168), .B0(n1173), .C0(n1172), .Y(n778)
);
OAI211XLTS U983 ( .A0(n1209), .A1(n1168), .B0(n1176), .C0(n1175), .Y(n777)
);
OAI211XLTS U984 ( .A0(n1236), .A1(n1151), .B0(n1235), .C0(n1234), .Y(n790)
);
OAI21XLTS U985 ( .A0(n1301), .A1(n1168), .B0(n1211), .Y(n779) );
AO22XLTS U986 ( .A0(n1287), .A1(Data_X[27]), .B0(n875), .B1(intDX_EWSW[27]),
.Y(n835) );
AO22XLTS U987 ( .A0(n1281), .A1(Data_X[29]), .B0(n875), .B1(intDX_EWSW[29]),
.Y(n833) );
AO22XLTS U988 ( .A0(n1284), .A1(Data_X[18]), .B0(n875), .B1(intDX_EWSW[18]),
.Y(n844) );
OAI211XLTS U989 ( .A0(n1224), .A1(n1151), .B0(n1219), .C0(n1218), .Y(n786)
);
AOI32X1TS U990 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1311), .A2(n874), .B0(
shift_value_SHT2_EWR[2]), .B1(n1308), .Y(n1310) );
AO22XLTS U991 ( .A0(n1283), .A1(Data_X[1]), .B0(n875), .B1(intDX_EWSW[1]),
.Y(n861) );
AOI2BB2XLTS U992 ( .B0(n1364), .B1(intadd_61_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1362), .Y(n522) );
OAI21XLTS U993 ( .A0(n1510), .A1(n1156), .B0(n1217), .Y(n793) );
OAI211XLTS U994 ( .A0(n1311), .A1(n1516), .B0(n1251), .C0(n1128), .Y(n767)
);
AO22XLTS U995 ( .A0(n1276), .A1(n1362), .B0(n1277), .B1(n897), .Y(n865) );
AO22XLTS U996 ( .A0(n1346), .A1(DmP_EXP_EWSW[19]), .B0(n1340), .B1(n899),
.Y(n571) );
AO22XLTS U997 ( .A0(n1346), .A1(DmP_EXP_EWSW[9]), .B0(n1338), .B1(n900), .Y(
n591) );
AO22XLTS U998 ( .A0(n1490), .A1(DmP_EXP_EWSW[5]), .B0(n1340), .B1(n902), .Y(
n599) );
AO22XLTS U999 ( .A0(n1490), .A1(DmP_EXP_EWSW[4]), .B0(n1340), .B1(n898), .Y(
n601) );
OAI21XLTS U1000 ( .A0(n1118), .A1(n1068), .B0(n1115), .Y(n1116) );
AO22XLTS U1001 ( .A0(n1283), .A1(Data_X[0]), .B0(n1286), .B1(n910), .Y(n862)
);
AO22XLTS U1002 ( .A0(n1277), .A1(busy), .B0(n1276), .B1(n897), .Y(n866) );
OR2X1TS U1003 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n884) );
OAI211XLTS U1004 ( .A0(n1159), .A1(n1151), .B0(n1158), .C0(n1157), .Y(n772)
);
OAI211XLTS U1005 ( .A0(n1185), .A1(n1168), .B0(n1184), .C0(n1183), .Y(n773)
);
OAI211XLTS U1006 ( .A0(n1180), .A1(n1168), .B0(n1179), .C0(n1178), .Y(n774)
);
AOI222X4TS U1007 ( .A0(n1244), .A1(intadd_62_A_4_), .B0(n1244), .B1(
intadd_62_B_4_), .C0(intadd_62_A_4_), .C1(intadd_62_B_4_), .Y(n1245)
);
BUFX4TS U1008 ( .A(n934), .Y(n1604) );
NOR2BX2TS U1009 ( .AN(n1265), .B(n1264), .Y(n1135) );
NOR2X2TS U1010 ( .A(Raw_mant_NRM_SWR[6]), .B(n1129), .Y(n1260) );
BUFX4TS U1011 ( .A(n1598), .Y(n1606) );
BUFX3TS U1012 ( .A(n1573), .Y(n1339) );
OAI211XLTS U1013 ( .A0(n959), .A1(n1081), .B0(n958), .C0(n957), .Y(n964) );
OAI21X2TS U1014 ( .A0(intDX_EWSW[26]), .A1(n1547), .B0(n956), .Y(n1081) );
BUFX4TS U1015 ( .A(n1599), .Y(n1589) );
BUFX4TS U1016 ( .A(n1602), .Y(n1592) );
BUFX4TS U1017 ( .A(n1595), .Y(n1593) );
BUFX4TS U1018 ( .A(n1579), .Y(n1596) );
BUFX3TS U1019 ( .A(n1600), .Y(n892) );
BUFX4TS U1020 ( .A(n934), .Y(n1594) );
BUFX4TS U1021 ( .A(n1597), .Y(n1590) );
BUFX4TS U1022 ( .A(n1604), .Y(n1607) );
BUFX3TS U1023 ( .A(n934), .Y(n1608) );
BUFX4TS U1024 ( .A(n1581), .Y(n1587) );
INVX2TS U1025 ( .A(n882), .Y(n893) );
NOR2X2TS U1026 ( .A(Raw_mant_NRM_SWR[13]), .B(n1254), .Y(n1144) );
BUFX4TS U1027 ( .A(n1586), .Y(n1580) );
BUFX4TS U1028 ( .A(n1585), .Y(n1583) );
BUFX4TS U1029 ( .A(n1582), .Y(n1578) );
XNOR2X2TS U1030 ( .A(DMP_exp_NRM2_EW[7]), .B(n940), .Y(n950) );
INVX2TS U1031 ( .A(n878), .Y(n895) );
XNOR2X2TS U1032 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J55_123_4652_n4), .Y(
n953) );
INVX2TS U1033 ( .A(n876), .Y(n896) );
NOR2X4TS U1034 ( .A(shift_value_SHT2_EWR[4]), .B(n1475), .Y(n1418) );
BUFX6TS U1035 ( .A(left_right_SHT2), .Y(n1475) );
BUFX4TS U1036 ( .A(n1021), .Y(n1332) );
INVX2TS U1037 ( .A(n883), .Y(n897) );
INVX2TS U1038 ( .A(n889), .Y(n898) );
INVX2TS U1039 ( .A(n888), .Y(n899) );
INVX2TS U1040 ( .A(n890), .Y(n900) );
INVX2TS U1041 ( .A(n887), .Y(n901) );
CLKINVX6TS U1042 ( .A(n1462), .Y(n1459) );
INVX2TS U1043 ( .A(n886), .Y(n902) );
CLKINVX6TS U1044 ( .A(n1335), .Y(n1469) );
INVX2TS U1045 ( .A(n885), .Y(n903) );
NOR4BX2TS U1046 ( .AN(n1150), .B(n1149), .C(n1148), .D(n1147), .Y(n1170) );
INVX2TS U1047 ( .A(n1297), .Y(n904) );
BUFX4TS U1048 ( .A(n1375), .Y(n1445) );
BUFX4TS U1049 ( .A(n1372), .Y(n1436) );
BUFX4TS U1050 ( .A(n1068), .Y(n1275) );
INVX2TS U1051 ( .A(n1151), .Y(n906) );
INVX2TS U1052 ( .A(n906), .Y(n907) );
BUFX4TS U1053 ( .A(n1462), .Y(n1476) );
BUFX4TS U1054 ( .A(n1462), .Y(n1465) );
CLKINVX6TS U1055 ( .A(n1335), .Y(n1478) );
CLKINVX3TS U1056 ( .A(n884), .Y(n908) );
INVX3TS U1057 ( .A(n884), .Y(n909) );
AOI222X4TS U1058 ( .A0(Data_array_SWR[24]), .A1(n1396), .B0(
Data_array_SWR[20]), .B1(n1411), .C0(Data_array_SWR[16]), .C1(n1410),
.Y(n1441) );
OAI211XLTS U1059 ( .A0(n1223), .A1(n907), .B0(n1222), .C0(n1221), .Y(n782)
);
AOI32X1TS U1060 ( .A0(n1552), .A1(n1002), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1501), .Y(n1003) );
AOI221X1TS U1061 ( .A0(n1552), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1501), .C0(n1088), .Y(n1093) );
AOI221X1TS U1062 ( .A0(n1550), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1577), .C0(n1087), .Y(n1094) );
AOI221X4TS U1063 ( .A0(intDX_EWSW[30]), .A1(n1550), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n961), .Y(n963) );
INVX2TS U1064 ( .A(n880), .Y(n910) );
AOI221X1TS U1065 ( .A0(n881), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1611), .C0(n1096), .Y(n1101) );
INVX4TS U1066 ( .A(n1366), .Y(n911) );
AOI221X1TS U1067 ( .A0(n1541), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1535), .C0(n1104), .Y(n1109) );
AOI221X1TS U1068 ( .A0(n1499), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1549), .C0(n1090), .Y(n1091) );
AOI221X1TS U1069 ( .A0(n1544), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1612), .C0(n1098), .Y(n1099) );
OAI211X2TS U1070 ( .A0(intDX_EWSW[20]), .A1(n1546), .B0(n1010), .C0(n996),
.Y(n1005) );
AOI221X1TS U1071 ( .A0(n1546), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1538), .C0(n1089), .Y(n1092) );
OAI211X2TS U1072 ( .A0(intDX_EWSW[12]), .A1(n1543), .B0(n991), .C0(n977),
.Y(n993) );
AOI221X1TS U1073 ( .A0(n1543), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1537), .C0(n1097), .Y(n1100) );
INVX1TS U1074 ( .A(DMP_SFG[3]), .Y(intadd_62_A_1_) );
INVX1TS U1075 ( .A(DMP_SFG[6]), .Y(intadd_62_A_4_) );
INVX1TS U1076 ( .A(DMP_SFG[8]), .Y(intadd_62_A_6_) );
AOI222X1TS U1077 ( .A0(DMP_SFG[5]), .A1(n1243), .B0(DMP_SFG[5]), .B1(n1242),
.C0(n1243), .C1(n1242), .Y(n1244) );
AOI222X4TS U1078 ( .A0(n1241), .A1(n879), .B0(n1241), .B1(n896), .C0(n879),
.C1(n896), .Y(n1242) );
OAI31XLTS U1079 ( .A0(n1334), .A1(n1118), .A2(n1343), .B0(n1117), .Y(n720)
);
NOR2X2TS U1080 ( .A(n912), .B(DMP_EXP_EWSW[23]), .Y(n1318) );
BUFX4TS U1081 ( .A(n1601), .Y(n1582) );
XNOR2X2TS U1082 ( .A(DMP_exp_NRM2_EW[0]), .B(n1249), .Y(n952) );
INVX1TS U1083 ( .A(LZD_output_NRM2_EW[0]), .Y(n1249) );
XNOR2X2TS U1084 ( .A(DMP_exp_NRM2_EW[6]), .B(n937), .Y(n1269) );
AOI22X2TS U1085 ( .A0(n1366), .A1(n891), .B0(DmP_mant_SFG_SWR[8]), .B1(n1365), .Y(intadd_62_B_4_) );
BUFX6TS U1086 ( .A(OP_FLAG_SFG), .Y(n1366) );
CLKINVX6TS U1087 ( .A(n1072), .Y(n1051) );
NOR2X4TS U1088 ( .A(shift_value_SHT2_EWR[4]), .B(n1444), .Y(n1417) );
CLKINVX6TS U1089 ( .A(n1475), .Y(n1444) );
AOI2BB2X2TS U1090 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n911), .A0N(n911), .A1N(
DmP_mant_SFG_SWR[10]), .Y(intadd_62_B_6_) );
AOI2BB2X2TS U1091 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1366), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1359) );
AOI222X1TS U1092 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n904), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1294), .C0(n908), .C1(DmP_mant_SHT1_SW[13]), .Y(n1224) );
AOI222X4TS U1093 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n904), .B0(n908), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1294), .C1(DmP_mant_SHT1_SW[17]), .Y(n1200) );
AOI222X1TS U1094 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1294), .C1(DmP_mant_SHT1_SW[18]), .Y(n1236) );
AOI222X4TS U1095 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n904), .B0(n909), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1294), .C1(DmP_mant_SHT1_SW[21]), .Y(n1215) );
NOR2XLTS U1096 ( .A(n979), .B(intDY_EWSW[10]), .Y(n980) );
NOR2X4TS U1097 ( .A(n1371), .B(n1370), .Y(n1391) );
OAI2BB1X2TS U1098 ( .A0N(n943), .A1N(n942), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1370) );
INVX4TS U1099 ( .A(n1282), .Y(n1285) );
CLKINVX6TS U1100 ( .A(n1575), .Y(busy) );
NAND2X2TS U1101 ( .A(n874), .B(n1575), .Y(n1311) );
AOI222X4TS U1102 ( .A0(DMP_SFG[9]), .A1(n1359), .B0(DMP_SFG[9]), .B1(n1248),
.C0(n1359), .C1(n1248), .Y(intadd_61_B_0_) );
AOI222X1TS U1103 ( .A0(n1412), .A1(n1444), .B0(n1374), .B1(Data_array_SWR[5]), .C0(n1413), .C1(n1417), .Y(n1450) );
AOI222X1TS U1104 ( .A0(n1412), .A1(n1475), .B0(Data_array_SWR[5]), .B1(n1445), .C0(n1413), .C1(n1418), .Y(n1468) );
AOI222X1TS U1105 ( .A0(n1420), .A1(n1444), .B0(n1374), .B1(Data_array_SWR[4]), .C0(n1419), .C1(n1417), .Y(n1449) );
AOI222X1TS U1106 ( .A0(n1420), .A1(n1475), .B0(Data_array_SWR[4]), .B1(n1445), .C0(n1419), .C1(n1418), .Y(n1470) );
AOI222X1TS U1107 ( .A0(n1402), .A1(n1444), .B0(Data_array_SWR[7]), .B1(n1374), .C0(n1401), .C1(n1417), .Y(n1452) );
AOI222X1TS U1108 ( .A0(n1402), .A1(n1475), .B0(Data_array_SWR[7]), .B1(n1445), .C0(n1401), .C1(n1418), .Y(n1466) );
AOI222X1TS U1109 ( .A0(n1407), .A1(n1444), .B0(Data_array_SWR[6]), .B1(n1374), .C0(n1406), .C1(n1417), .Y(n1451) );
AOI222X1TS U1110 ( .A0(n1407), .A1(n1475), .B0(Data_array_SWR[6]), .B1(n1445), .C0(n1406), .C1(n1418), .Y(n1467) );
INVX4TS U1111 ( .A(n1609), .Y(n1364) );
INVX3TS U1112 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1430) );
AOI222X1TS U1113 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n904), .B0(n908), .B1(n899),
.C0(n1294), .C1(DmP_mant_SHT1_SW[20]), .Y(n1232) );
OAI21XLTS U1114 ( .A0(n1293), .A1(n1151), .B0(n1202), .Y(n787) );
NOR2X2TS U1115 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1530), .Y(n1274) );
AOI221X1TS U1116 ( .A0(n1547), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1551), .C0(n1081), .Y(n1085) );
OAI21X2TS U1117 ( .A0(intDX_EWSW[18]), .A1(n1552), .B0(n1002), .Y(n1088) );
NOR3X1TS U1118 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1265) );
NOR2X2TS U1119 ( .A(Raw_mant_NRM_SWR[12]), .B(n1137), .Y(n1259) );
AOI222X1TS U1120 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n904), .B0(n908), .B1(n901), .C0(n1294), .C1(DmP_mant_SHT1_SW[12]), .Y(n1227) );
OAI211XLTS U1121 ( .A0(n1227), .A1(n907), .B0(n1226), .C0(n1225), .Y(n784)
);
NOR3X1TS U1122 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1511), .Y(n1372) );
NOR2X4TS U1123 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1410) );
NOR2XLTS U1124 ( .A(n1611), .B(intDX_EWSW[11]), .Y(n979) );
NOR2XLTS U1125 ( .A(n1000), .B(intDY_EWSW[16]), .Y(n1001) );
OAI21XLTS U1126 ( .A0(intDX_EWSW[21]), .A1(n1538), .B0(intDX_EWSW[20]), .Y(
n999) );
NOR2XLTS U1127 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1140) );
NOR2XLTS U1128 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1143) );
AOI31XLTS U1129 ( .A0(n1135), .A1(Raw_mant_NRM_SWR[16]), .A2(n1509), .B0(
n1134), .Y(n1136) );
OAI21XLTS U1130 ( .A0(n1482), .A1(n1297), .B0(n1291), .Y(n1292) );
OR2X1TS U1131 ( .A(n951), .B(n950), .Y(n1237) );
OAI21XLTS U1132 ( .A0(n1493), .A1(n1212), .B0(n1207), .Y(n1208) );
OAI21XLTS U1133 ( .A0(n1563), .A1(n1212), .B0(n1190), .Y(n1191) );
NOR2XLTS U1134 ( .A(n1371), .B(SIGN_FLAG_SHT1SHT2), .Y(n1238) );
OAI21XLTS U1135 ( .A0(n1540), .A1(n1051), .B0(n1047), .Y(n745) );
OAI211XLTS U1136 ( .A0(n1180), .A1(n907), .B0(n1163), .C0(n1162), .Y(n776)
);
OAI21XLTS U1137 ( .A0(n1290), .A1(n1168), .B0(n1193), .Y(n792) );
BUFX3TS U1138 ( .A(n1591), .Y(n1595) );
BUFX3TS U1139 ( .A(n934), .Y(n1597) );
BUFX3TS U1140 ( .A(n1601), .Y(n1598) );
BUFX3TS U1141 ( .A(n1591), .Y(n1586) );
BUFX3TS U1142 ( .A(n1600), .Y(n1591) );
BUFX3TS U1143 ( .A(n1591), .Y(n1584) );
BUFX3TS U1144 ( .A(n1601), .Y(n1581) );
BUFX3TS U1145 ( .A(n934), .Y(n1603) );
BUFX3TS U1146 ( .A(n1582), .Y(n1579) );
BUFX3TS U1147 ( .A(n1588), .Y(n1585) );
BUFX3TS U1148 ( .A(n934), .Y(n1600) );
BUFX3TS U1149 ( .A(n1592), .Y(n1605) );
BUFX3TS U1150 ( .A(n1593), .Y(n1588) );
BUFX3TS U1151 ( .A(n1604), .Y(n1601) );
BUFX3TS U1152 ( .A(n892), .Y(n1602) );
BUFX3TS U1153 ( .A(n1590), .Y(n1599) );
INVX2TS U1154 ( .A(DP_OP_15J55_123_4652_n4), .Y(n935) );
NAND2X1TS U1155 ( .A(n1532), .B(n935), .Y(n937) );
INVX2TS U1156 ( .A(n937), .Y(n936) );
NAND2X1TS U1157 ( .A(n1554), .B(n936), .Y(n940) );
AND4X1TS U1158 ( .A(exp_rslt_NRM2_EW1[3]), .B(n952), .C(exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n938) );
AND4X1TS U1159 ( .A(n1269), .B(n953), .C(exp_rslt_NRM2_EW1[4]), .D(n938),
.Y(n939) );
CLKAND2X2TS U1160 ( .A(n950), .B(n939), .Y(n943) );
INVX2TS U1161 ( .A(n940), .Y(n941) );
CLKAND2X2TS U1162 ( .A(n1560), .B(n941), .Y(n942) );
INVX2TS U1163 ( .A(n1370), .Y(n944) );
AO22XLTS U1164 ( .A0(n944), .A1(n950), .B0(n1430), .B1(final_result_ieee[30]), .Y(n754) );
NOR2XLTS U1165 ( .A(n952), .B(exp_rslt_NRM2_EW1[1]), .Y(n947) );
INVX2TS U1166 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n946) );
INVX2TS U1167 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n945) );
NAND4BXLTS U1168 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n947), .C(n946), .D(n945),
.Y(n948) );
NOR2XLTS U1169 ( .A(n948), .B(n953), .Y(n949) );
NAND2X2TS U1170 ( .A(n1237), .B(Shift_reg_FLAGS_7[0]), .Y(n1270) );
OA22X1TS U1171 ( .A0(n1270), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1172 ( .A0(n1270), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OA22X1TS U1173 ( .A0(n1270), .A1(n952), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1174 ( .A0(n1270), .A1(n953), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1175 ( .A0(n1270), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1176 ( .A0(n1270), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OAI21XLTS U1177 ( .A0(n873), .A1(n1444), .B0(n874), .Y(n829) );
AOI2BB2XLTS U1178 ( .B0(beg_OP), .B1(n1496), .A0N(n1496), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n954) );
NAND3XLTS U1179 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1496), .C(
n1530), .Y(n1271) );
OAI21XLTS U1180 ( .A0(n1274), .A1(n954), .B0(n1271), .Y(n870) );
NOR2X1TS U1181 ( .A(n1613), .B(intDX_EWSW[25]), .Y(n1013) );
NOR2XLTS U1182 ( .A(n1013), .B(intDY_EWSW[24]), .Y(n955) );
AOI22X1TS U1183 ( .A0(intDX_EWSW[25]), .A1(n1613), .B0(intDX_EWSW[24]), .B1(
n955), .Y(n959) );
NAND2BXLTS U1184 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n957) );
NOR2X1TS U1185 ( .A(n1550), .B(intDX_EWSW[30]), .Y(n962) );
NOR2X1TS U1186 ( .A(n1500), .B(intDX_EWSW[29]), .Y(n960) );
AOI211X1TS U1187 ( .A0(intDY_EWSW[28]), .A1(n1524), .B0(n962), .C0(n960),
.Y(n1012) );
NOR3XLTS U1188 ( .A(n1524), .B(n960), .C(intDY_EWSW[28]), .Y(n961) );
AOI2BB2X1TS U1189 ( .B0(n964), .B1(n1012), .A0N(n963), .A1N(n962), .Y(n1017)
);
NOR2X1TS U1190 ( .A(n1577), .B(intDX_EWSW[17]), .Y(n1000) );
OAI22X1TS U1191 ( .A0(n881), .A1(intDX_EWSW[10]), .B0(n1611), .B1(
intDX_EWSW[11]), .Y(n1096) );
INVX2TS U1192 ( .A(n1096), .Y(n984) );
OAI211XLTS U1193 ( .A0(intDX_EWSW[8]), .A1(n1540), .B0(n981), .C0(n984), .Y(
n995) );
OAI2BB1X1TS U1194 ( .A0N(n1513), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n965) );
OAI22X1TS U1195 ( .A0(intDY_EWSW[4]), .A1(n965), .B0(n1513), .B1(
intDY_EWSW[5]), .Y(n976) );
OAI2BB1X1TS U1196 ( .A0N(n1495), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n966) );
OAI22X1TS U1197 ( .A0(intDY_EWSW[6]), .A1(n966), .B0(n1495), .B1(
intDY_EWSW[7]), .Y(n975) );
OAI21XLTS U1198 ( .A0(intDX_EWSW[1]), .A1(n1539), .B0(n910), .Y(n967) );
OAI2BB2XLTS U1199 ( .B0(intDY_EWSW[0]), .B1(n967), .A0N(intDX_EWSW[1]),
.A1N(n1539), .Y(n969) );
OAI211XLTS U1200 ( .A0(n1535), .A1(intDX_EWSW[3]), .B0(n969), .C0(n968), .Y(
n972) );
OAI21XLTS U1201 ( .A0(intDX_EWSW[3]), .A1(n1535), .B0(intDX_EWSW[2]), .Y(
n970) );
AOI2BB2XLTS U1202 ( .B0(intDX_EWSW[3]), .B1(n1535), .A0N(intDY_EWSW[2]),
.A1N(n970), .Y(n971) );
AOI222X1TS U1203 ( .A0(intDY_EWSW[4]), .A1(n1494), .B0(n972), .B1(n971),
.C0(intDY_EWSW[5]), .C1(n1513), .Y(n974) );
AOI22X1TS U1204 ( .A0(intDY_EWSW[7]), .A1(n1495), .B0(intDY_EWSW[6]), .B1(
n1519), .Y(n973) );
OAI32X1TS U1205 ( .A0(n976), .A1(n975), .A2(n974), .B0(n973), .B1(n975), .Y(
n994) );
OA22X1TS U1206 ( .A0(n1544), .A1(intDX_EWSW[14]), .B0(n1612), .B1(
intDX_EWSW[15]), .Y(n991) );
OAI21XLTS U1207 ( .A0(intDX_EWSW[13]), .A1(n1537), .B0(intDX_EWSW[12]), .Y(
n978) );
OAI2BB2XLTS U1208 ( .B0(intDY_EWSW[12]), .B1(n978), .A0N(intDX_EWSW[13]),
.A1N(n1537), .Y(n990) );
AOI22X1TS U1209 ( .A0(intDX_EWSW[11]), .A1(n1611), .B0(intDX_EWSW[10]), .B1(
n980), .Y(n986) );
NAND2BXLTS U1210 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n983) );
NAND3XLTS U1211 ( .A(n1540), .B(n981), .C(intDX_EWSW[8]), .Y(n982) );
AOI21X1TS U1212 ( .A0(n983), .A1(n982), .B0(n993), .Y(n985) );
OAI2BB2XLTS U1213 ( .B0(n986), .B1(n993), .A0N(n985), .A1N(n984), .Y(n989)
);
OAI21XLTS U1214 ( .A0(intDX_EWSW[15]), .A1(n1612), .B0(intDX_EWSW[14]), .Y(
n987) );
OAI2BB2XLTS U1215 ( .B0(intDY_EWSW[14]), .B1(n987), .A0N(intDX_EWSW[15]),
.A1N(n1612), .Y(n988) );
AOI211X1TS U1216 ( .A0(n991), .A1(n990), .B0(n989), .C0(n988), .Y(n992) );
OAI31X1TS U1217 ( .A0(n995), .A1(n994), .A2(n993), .B0(n992), .Y(n998) );
OA22X1TS U1218 ( .A0(n1499), .A1(intDX_EWSW[22]), .B0(n1549), .B1(
intDX_EWSW[23]), .Y(n1010) );
AOI211XLTS U1219 ( .A0(intDY_EWSW[16]), .A1(n1518), .B0(n1005), .C0(n1088),
.Y(n997) );
OAI2BB2XLTS U1220 ( .B0(intDY_EWSW[20]), .B1(n999), .A0N(intDX_EWSW[21]),
.A1N(n1538), .Y(n1009) );
AOI22X1TS U1221 ( .A0(intDX_EWSW[17]), .A1(n1577), .B0(intDX_EWSW[16]), .B1(
n1001), .Y(n1004) );
OAI32X1TS U1222 ( .A0(n1088), .A1(n1005), .A2(n1004), .B0(n1003), .B1(n1005),
.Y(n1008) );
OAI21XLTS U1223 ( .A0(intDX_EWSW[23]), .A1(n1549), .B0(intDX_EWSW[22]), .Y(
n1006) );
OAI2BB2XLTS U1224 ( .B0(intDY_EWSW[22]), .B1(n1006), .A0N(intDX_EWSW[23]),
.A1N(n1549), .Y(n1007) );
AOI211X1TS U1225 ( .A0(n1010), .A1(n1009), .B0(n1008), .C0(n1007), .Y(n1015)
);
NAND2BXLTS U1226 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1011) );
NAND4BBX1TS U1227 ( .AN(n1081), .BN(n1013), .C(n1012), .D(n1011), .Y(n1014)
);
AOI32X1TS U1228 ( .A0(n1017), .A1(n1016), .A2(n1015), .B0(n1014), .B1(n1017),
.Y(n1018) );
INVX2TS U1229 ( .A(Shift_reg_FLAGS_7_6), .Y(n1021) );
INVX4TS U1230 ( .A(n1026), .Y(n1343) );
AND2X2TS U1231 ( .A(Shift_reg_FLAGS_7_6), .B(n1018), .Y(n1041) );
AOI22X1TS U1232 ( .A0(n903), .A1(n1275), .B0(intDX_EWSW[27]), .B1(n1041),
.Y(n1019) );
OAI21XLTS U1233 ( .A0(n1551), .A1(n1343), .B0(n1019), .Y(n726) );
AOI22X1TS U1234 ( .A0(intDX_EWSW[1]), .A1(n1041), .B0(DMP_EXP_EWSW[1]), .B1(
n1332), .Y(n1020) );
OAI21XLTS U1235 ( .A0(n1539), .A1(n1343), .B0(n1020), .Y(n752) );
BUFX3TS U1236 ( .A(n1041), .Y(n1038) );
BUFX4TS U1237 ( .A(n1021), .Y(n1068) );
AOI22X1TS U1238 ( .A0(intDX_EWSW[28]), .A1(n1038), .B0(DMP_EXP_EWSW[28]),
.B1(n1068), .Y(n1022) );
OAI21XLTS U1239 ( .A0(n1548), .A1(n1343), .B0(n1022), .Y(n725) );
AOI22X1TS U1240 ( .A0(intDX_EWSW[29]), .A1(n1038), .B0(DMP_EXP_EWSW[29]),
.B1(n1068), .Y(n1023) );
OAI21XLTS U1241 ( .A0(n1500), .A1(n1343), .B0(n1023), .Y(n724) );
AOI22X1TS U1242 ( .A0(intDX_EWSW[30]), .A1(n1038), .B0(DMP_EXP_EWSW[30]),
.B1(n1332), .Y(n1024) );
OAI21XLTS U1243 ( .A0(n1550), .A1(n1343), .B0(n1024), .Y(n723) );
AOI22X1TS U1244 ( .A0(DMP_EXP_EWSW[23]), .A1(n1275), .B0(intDX_EWSW[23]),
.B1(n1038), .Y(n1025) );
OAI21XLTS U1245 ( .A0(n1549), .A1(n1343), .B0(n1025), .Y(n730) );
BUFX3TS U1246 ( .A(n1026), .Y(n1072) );
AOI22X1TS U1247 ( .A0(intDX_EWSW[17]), .A1(n1038), .B0(DMP_EXP_EWSW[17]),
.B1(n1068), .Y(n1027) );
OAI21XLTS U1248 ( .A0(n1577), .A1(n1051), .B0(n1027), .Y(n736) );
AOI22X1TS U1249 ( .A0(intDX_EWSW[20]), .A1(n1038), .B0(DMP_EXP_EWSW[20]),
.B1(n1332), .Y(n1028) );
OAI21XLTS U1250 ( .A0(n1546), .A1(n1051), .B0(n1028), .Y(n733) );
AOI22X1TS U1251 ( .A0(intDX_EWSW[22]), .A1(n1038), .B0(DMP_EXP_EWSW[22]),
.B1(n1332), .Y(n1029) );
OAI21XLTS U1252 ( .A0(n1499), .A1(n1051), .B0(n1029), .Y(n731) );
AOI22X1TS U1253 ( .A0(intDX_EWSW[21]), .A1(n1038), .B0(DMP_EXP_EWSW[21]),
.B1(n1068), .Y(n1030) );
OAI21XLTS U1254 ( .A0(n1538), .A1(n1051), .B0(n1030), .Y(n732) );
AOI22X1TS U1255 ( .A0(intDX_EWSW[18]), .A1(n1038), .B0(DMP_EXP_EWSW[18]),
.B1(n1332), .Y(n1031) );
OAI21XLTS U1256 ( .A0(n1552), .A1(n1051), .B0(n1031), .Y(n735) );
AOI22X1TS U1257 ( .A0(intDX_EWSW[7]), .A1(n1041), .B0(DMP_EXP_EWSW[7]), .B1(
n1332), .Y(n1032) );
OAI21XLTS U1258 ( .A0(n1529), .A1(n1051), .B0(n1032), .Y(n746) );
AOI22X1TS U1259 ( .A0(intDX_EWSW[2]), .A1(n1041), .B0(DMP_EXP_EWSW[2]), .B1(
n1068), .Y(n1033) );
OAI21XLTS U1260 ( .A0(n1541), .A1(n1051), .B0(n1033), .Y(n751) );
AOI22X1TS U1261 ( .A0(n910), .A1(n1038), .B0(DMP_EXP_EWSW[0]), .B1(n1332),
.Y(n1034) );
OAI21XLTS U1262 ( .A0(n1498), .A1(n1051), .B0(n1034), .Y(n753) );
AOI22X1TS U1263 ( .A0(intDX_EWSW[19]), .A1(n1038), .B0(DMP_EXP_EWSW[19]),
.B1(n1068), .Y(n1035) );
OAI21XLTS U1264 ( .A0(n1501), .A1(n1051), .B0(n1035), .Y(n734) );
AOI22X1TS U1265 ( .A0(intDX_EWSW[4]), .A1(n1041), .B0(DMP_EXP_EWSW[4]), .B1(
n1068), .Y(n1036) );
OAI21XLTS U1266 ( .A0(n1542), .A1(n1051), .B0(n1036), .Y(n749) );
AOI22X1TS U1267 ( .A0(intDX_EWSW[6]), .A1(n1041), .B0(DMP_EXP_EWSW[6]), .B1(
n1068), .Y(n1037) );
OAI21XLTS U1268 ( .A0(n1528), .A1(n1051), .B0(n1037), .Y(n747) );
AOI22X1TS U1269 ( .A0(intDX_EWSW[5]), .A1(n894), .B0(DMP_EXP_EWSW[5]), .B1(
n1068), .Y(n1039) );
OAI21XLTS U1270 ( .A0(n1497), .A1(n1343), .B0(n1039), .Y(n748) );
AOI22X1TS U1271 ( .A0(intDX_EWSW[16]), .A1(n894), .B0(DMP_EXP_EWSW[16]),
.B1(n1068), .Y(n1040) );
OAI21XLTS U1272 ( .A0(n1545), .A1(n1051), .B0(n1040), .Y(n737) );
AOI222X1TS U1273 ( .A0(n1072), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1332), .C0(intDY_EWSW[23]), .C1(n1041), .Y(n1042) );
INVX2TS U1274 ( .A(n1042), .Y(n564) );
AOI22X1TS U1275 ( .A0(intDX_EWSW[10]), .A1(n894), .B0(DMP_EXP_EWSW[10]),
.B1(n1332), .Y(n1043) );
OAI21XLTS U1276 ( .A0(n881), .A1(n1051), .B0(n1043), .Y(n743) );
AOI22X1TS U1277 ( .A0(intDX_EWSW[9]), .A1(n894), .B0(DMP_EXP_EWSW[9]), .B1(
n1068), .Y(n1044) );
OAI21XLTS U1278 ( .A0(n1536), .A1(n1343), .B0(n1044), .Y(n744) );
AOI22X1TS U1279 ( .A0(intDX_EWSW[14]), .A1(n894), .B0(DMP_EXP_EWSW[14]),
.B1(n1275), .Y(n1045) );
OAI21XLTS U1280 ( .A0(n1544), .A1(n1051), .B0(n1045), .Y(n739) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[12]), .A1(n894), .B0(DMP_EXP_EWSW[12]),
.B1(n1275), .Y(n1046) );
OAI21XLTS U1282 ( .A0(n1543), .A1(n1051), .B0(n1046), .Y(n741) );
AOI22X1TS U1283 ( .A0(intDX_EWSW[8]), .A1(n894), .B0(DMP_EXP_EWSW[8]), .B1(
n1275), .Y(n1047) );
AOI22X1TS U1284 ( .A0(intDX_EWSW[11]), .A1(n894), .B0(DMP_EXP_EWSW[11]),
.B1(n1068), .Y(n1048) );
OAI21XLTS U1285 ( .A0(n1611), .A1(n1051), .B0(n1048), .Y(n742) );
AOI22X1TS U1286 ( .A0(intDX_EWSW[13]), .A1(n894), .B0(DMP_EXP_EWSW[13]),
.B1(n1332), .Y(n1049) );
OAI21XLTS U1287 ( .A0(n1537), .A1(n1051), .B0(n1049), .Y(n740) );
AOI22X1TS U1288 ( .A0(intDX_EWSW[15]), .A1(n894), .B0(DMP_EXP_EWSW[15]),
.B1(n1332), .Y(n1050) );
OAI21XLTS U1289 ( .A0(n1612), .A1(n1051), .B0(n1050), .Y(n738) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[3]), .A1(n894), .B0(DMP_EXP_EWSW[3]), .B1(
n1332), .Y(n1052) );
OAI21XLTS U1291 ( .A0(n1535), .A1(n1343), .B0(n1052), .Y(n750) );
INVX3TS U1292 ( .A(n894), .Y(n1115) );
AOI22X1TS U1293 ( .A0(DmP_EXP_EWSW[27]), .A1(n1275), .B0(intDX_EWSW[27]),
.B1(n1072), .Y(n1053) );
OAI21XLTS U1294 ( .A0(n1551), .A1(n1115), .B0(n1053), .Y(n560) );
AOI22X1TS U1295 ( .A0(intDX_EWSW[12]), .A1(n1072), .B0(DmP_EXP_EWSW[12]),
.B1(n1021), .Y(n1054) );
OAI21XLTS U1296 ( .A0(n1543), .A1(n1115), .B0(n1054), .Y(n586) );
CLKBUFX3TS U1297 ( .A(n1072), .Y(n1078) );
AOI22X1TS U1298 ( .A0(intDX_EWSW[13]), .A1(n1078), .B0(DmP_EXP_EWSW[13]),
.B1(n1275), .Y(n1055) );
OAI21XLTS U1299 ( .A0(n1537), .A1(n1115), .B0(n1055), .Y(n584) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[8]), .A1(n1072), .B0(DmP_EXP_EWSW[8]), .B1(
n1332), .Y(n1056) );
OAI21XLTS U1301 ( .A0(n1540), .A1(n1115), .B0(n1056), .Y(n594) );
AOI22X1TS U1302 ( .A0(intDX_EWSW[15]), .A1(n1078), .B0(DmP_EXP_EWSW[15]),
.B1(n1275), .Y(n1057) );
OAI21XLTS U1303 ( .A0(n1612), .A1(n1115), .B0(n1057), .Y(n580) );
AOI22X1TS U1304 ( .A0(intDX_EWSW[14]), .A1(n1078), .B0(DmP_EXP_EWSW[14]),
.B1(n1021), .Y(n1058) );
OAI21XLTS U1305 ( .A0(n1544), .A1(n1115), .B0(n1058), .Y(n582) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[4]), .A1(n1026), .B0(DmP_EXP_EWSW[4]), .B1(
n1332), .Y(n1059) );
OAI21XLTS U1307 ( .A0(n1542), .A1(n1115), .B0(n1059), .Y(n602) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[9]), .A1(n1026), .B0(DmP_EXP_EWSW[9]), .B1(
n1332), .Y(n1060) );
OAI21XLTS U1309 ( .A0(n1536), .A1(n1115), .B0(n1060), .Y(n592) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[6]), .A1(n1072), .B0(DmP_EXP_EWSW[6]), .B1(
n1332), .Y(n1061) );
OAI21XLTS U1311 ( .A0(n1528), .A1(n1115), .B0(n1061), .Y(n598) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[5]), .A1(n1072), .B0(DmP_EXP_EWSW[5]), .B1(
n1275), .Y(n1062) );
OAI21XLTS U1313 ( .A0(n1497), .A1(n1115), .B0(n1062), .Y(n600) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[7]), .A1(n1026), .B0(DmP_EXP_EWSW[7]), .B1(
n1021), .Y(n1063) );
OAI21XLTS U1315 ( .A0(n1529), .A1(n1115), .B0(n1063), .Y(n596) );
AOI22X1TS U1316 ( .A0(intDX_EWSW[10]), .A1(n1026), .B0(DmP_EXP_EWSW[10]),
.B1(n1068), .Y(n1064) );
OAI21XLTS U1317 ( .A0(n881), .A1(n1115), .B0(n1064), .Y(n590) );
AOI22X1TS U1318 ( .A0(intDX_EWSW[11]), .A1(n1072), .B0(DmP_EXP_EWSW[11]),
.B1(n1021), .Y(n1065) );
OAI21XLTS U1319 ( .A0(n1611), .A1(n1115), .B0(n1065), .Y(n588) );
INVX4TS U1320 ( .A(n894), .Y(n1341) );
AOI22X1TS U1321 ( .A0(intDX_EWSW[16]), .A1(n1078), .B0(DmP_EXP_EWSW[16]),
.B1(n1275), .Y(n1066) );
OAI21XLTS U1322 ( .A0(n1545), .A1(n1341), .B0(n1066), .Y(n578) );
AOI22X1TS U1323 ( .A0(intDX_EWSW[21]), .A1(n1078), .B0(DmP_EXP_EWSW[21]),
.B1(n1275), .Y(n1067) );
OAI21XLTS U1324 ( .A0(n1538), .A1(n1341), .B0(n1067), .Y(n568) );
AOI22X1TS U1325 ( .A0(n910), .A1(n1078), .B0(DmP_EXP_EWSW[0]), .B1(n1068),
.Y(n1069) );
OAI21XLTS U1326 ( .A0(n1498), .A1(n1341), .B0(n1069), .Y(n610) );
AOI22X1TS U1327 ( .A0(intDX_EWSW[1]), .A1(n1072), .B0(DmP_EXP_EWSW[1]), .B1(
n1275), .Y(n1070) );
OAI21XLTS U1328 ( .A0(n1539), .A1(n1341), .B0(n1070), .Y(n608) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[2]), .A1(n1072), .B0(DmP_EXP_EWSW[2]), .B1(
n1068), .Y(n1071) );
OAI21XLTS U1330 ( .A0(n1541), .A1(n1341), .B0(n1071), .Y(n606) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[3]), .A1(n1072), .B0(DmP_EXP_EWSW[3]), .B1(
n1021), .Y(n1073) );
OAI21XLTS U1332 ( .A0(n1535), .A1(n1341), .B0(n1073), .Y(n604) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[18]), .A1(n1026), .B0(DmP_EXP_EWSW[18]),
.B1(n1275), .Y(n1074) );
OAI21XLTS U1334 ( .A0(n1552), .A1(n1341), .B0(n1074), .Y(n574) );
AOI22X1TS U1335 ( .A0(intDX_EWSW[17]), .A1(n1078), .B0(DmP_EXP_EWSW[17]),
.B1(n1275), .Y(n1075) );
OAI21XLTS U1336 ( .A0(n1577), .A1(n1341), .B0(n1075), .Y(n576) );
AOI22X1TS U1337 ( .A0(intDX_EWSW[20]), .A1(n1078), .B0(DmP_EXP_EWSW[20]),
.B1(n1275), .Y(n1076) );
OAI21XLTS U1338 ( .A0(n1546), .A1(n1341), .B0(n1076), .Y(n570) );
AOI22X1TS U1339 ( .A0(intDX_EWSW[19]), .A1(n1078), .B0(DmP_EXP_EWSW[19]),
.B1(n1275), .Y(n1077) );
OAI21XLTS U1340 ( .A0(n1501), .A1(n1341), .B0(n1077), .Y(n572) );
AOI22X1TS U1341 ( .A0(intDX_EWSW[22]), .A1(n1078), .B0(DmP_EXP_EWSW[22]),
.B1(n1275), .Y(n1079) );
OAI21XLTS U1342 ( .A0(n1499), .A1(n1341), .B0(n1079), .Y(n566) );
OAI22X1TS U1343 ( .A0(n1539), .A1(intDX_EWSW[1]), .B0(n1613), .B1(
intDX_EWSW[25]), .Y(n1080) );
AOI221X1TS U1344 ( .A0(n1539), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1613), .C0(n1080), .Y(n1086) );
OAI22X1TS U1345 ( .A0(n1548), .A1(intDX_EWSW[28]), .B0(n1500), .B1(
intDX_EWSW[29]), .Y(n1082) );
AOI221X1TS U1346 ( .A0(n1548), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n1082), .Y(n1084) );
AOI2BB2XLTS U1347 ( .B0(intDX_EWSW[7]), .B1(n1529), .A0N(n1529), .A1N(
intDX_EWSW[7]), .Y(n1083) );
NAND4XLTS U1348 ( .A(n1086), .B(n1085), .C(n1084), .D(n1083), .Y(n1114) );
OAI22X1TS U1349 ( .A0(n1550), .A1(intDX_EWSW[30]), .B0(n1577), .B1(
intDX_EWSW[17]), .Y(n1087) );
OAI22X1TS U1350 ( .A0(n1546), .A1(intDX_EWSW[20]), .B0(n1538), .B1(
intDX_EWSW[21]), .Y(n1089) );
OAI22X1TS U1351 ( .A0(n1499), .A1(intDX_EWSW[22]), .B0(n1549), .B1(
intDX_EWSW[23]), .Y(n1090) );
NAND4XLTS U1352 ( .A(n1094), .B(n1093), .C(n1092), .D(n1091), .Y(n1113) );
OAI22X1TS U1353 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(n1536), .B1(
intDX_EWSW[9]), .Y(n1095) );
AOI221X1TS U1354 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1536), .C0(n1095), .Y(n1102) );
OAI22X1TS U1355 ( .A0(n1543), .A1(intDX_EWSW[12]), .B0(n1537), .B1(
intDX_EWSW[13]), .Y(n1097) );
OAI22X1TS U1356 ( .A0(n1544), .A1(intDX_EWSW[14]), .B0(n1612), .B1(
intDX_EWSW[15]), .Y(n1098) );
NAND4XLTS U1357 ( .A(n1102), .B(n1101), .C(n1100), .D(n1099), .Y(n1112) );
OAI22X1TS U1358 ( .A0(n1545), .A1(intDX_EWSW[16]), .B0(n1498), .B1(n910),
.Y(n1103) );
AOI221X1TS U1359 ( .A0(n1545), .A1(intDX_EWSW[16]), .B0(n910), .B1(n1498),
.C0(n1103), .Y(n1110) );
OAI22X1TS U1360 ( .A0(n1541), .A1(intDX_EWSW[2]), .B0(n1535), .B1(
intDX_EWSW[3]), .Y(n1104) );
OAI22X1TS U1361 ( .A0(n1542), .A1(intDX_EWSW[4]), .B0(n1497), .B1(
intDX_EWSW[5]), .Y(n1105) );
AOI221X1TS U1362 ( .A0(n1542), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1497), .C0(n1105), .Y(n1108) );
OAI22X1TS U1363 ( .A0(n1540), .A1(intDX_EWSW[8]), .B0(n1528), .B1(
intDX_EWSW[6]), .Y(n1106) );
AOI221X1TS U1364 ( .A0(n1540), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1528), .C0(n1106), .Y(n1107) );
NAND4XLTS U1365 ( .A(n1110), .B(n1109), .C(n1108), .D(n1107), .Y(n1111) );
NOR4X1TS U1366 ( .A(n1114), .B(n1113), .C(n1112), .D(n1111), .Y(n1334) );
CLKXOR2X2TS U1367 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1331) );
INVX2TS U1368 ( .A(n1331), .Y(n1118) );
AOI22X1TS U1369 ( .A0(intDX_EWSW[31]), .A1(n1116), .B0(SIGN_FLAG_EXP), .B1(
n877), .Y(n1117) );
NOR2XLTS U1370 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1120)
);
NAND4X1TS U1371 ( .A(n1491), .B(n1480), .C(n1479), .D(n1508), .Y(n1264) );
NOR2BX1TS U1372 ( .AN(n1135), .B(Raw_mant_NRM_SWR[18]), .Y(n1252) );
NOR2BX1TS U1373 ( .AN(n1252), .B(n1253), .Y(n1132) );
NAND2X1TS U1374 ( .A(n1132), .B(n1493), .Y(n1254) );
NAND2X1TS U1375 ( .A(n1144), .B(n1482), .Y(n1137) );
NAND2X1TS U1376 ( .A(n1259), .B(n1483), .Y(n1119) );
NOR2X1TS U1377 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1121)
);
NOR3X1TS U1378 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1119),
.Y(n1122) );
NAND2X1TS U1379 ( .A(n1122), .B(n1484), .Y(n1129) );
OAI22X1TS U1380 ( .A0(n1120), .A1(n1119), .B0(n1121), .B1(n1129), .Y(n1127)
);
NOR2X1TS U1381 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1124)
);
NAND2X1TS U1382 ( .A(n1260), .B(n1121), .Y(n1125) );
OAI21X1TS U1383 ( .A0(n1124), .A1(n1125), .B0(n1123), .Y(n1148) );
INVX2TS U1384 ( .A(n1125), .Y(n1261) );
OAI31X1TS U1385 ( .A0(n1127), .A1(n1148), .A2(n1126), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1251) );
NAND3XLTS U1386 ( .A(n873), .B(Shift_amount_SHT1_EWR[4]), .C(n874), .Y(n1128) );
INVX2TS U1387 ( .A(n1129), .Y(n1139) );
AOI22X1TS U1388 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1135), .B0(n1259), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1145) );
OAI32X1TS U1389 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1485), .B0(n1510), .B1(Raw_mant_NRM_SWR[3]), .Y(n1130) );
NAND2X1TS U1390 ( .A(Raw_mant_NRM_SWR[12]), .B(n1144), .Y(n1256) );
NAND2X1TS U1391 ( .A(Raw_mant_NRM_SWR[14]), .B(n1132), .Y(n1150) );
AOI32X1TS U1392 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1479), .A2(n1512), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1479), .Y(n1133) );
AOI32X1TS U1393 ( .A0(n1480), .A1(n1150), .A2(n1133), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1150), .Y(n1134) );
OAI31X1TS U1394 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1137), .A2(n1486), .B0(
n1136), .Y(n1138) );
NAND2X2TS U1395 ( .A(Shift_reg_FLAGS_7[1]), .B(n1153), .Y(n1297) );
NOR2BX1TS U1396 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1189) );
CLKBUFX2TS U1397 ( .A(n1189), .Y(n1214) );
BUFX4TS U1398 ( .A(n1214), .Y(n1294) );
AOI22X1TS U1399 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n905), .B0(n1294), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1159) );
NOR2X1TS U1400 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1141) );
AOI32X1TS U1401 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1141), .A2(n1140), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1141), .Y(n1142) );
AOI211X1TS U1402 ( .A0(n1143), .A1(n1142), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1149) );
INVX2TS U1403 ( .A(n1144), .Y(n1146) );
OAI31X1TS U1404 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1482), .A2(n1146), .B0(
n1145), .Y(n1147) );
NOR2X1TS U1405 ( .A(n1170), .B(n874), .Y(n1268) );
AOI21X1TS U1406 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n874), .B0(n1268), .Y(
n1152) );
INVX2TS U1407 ( .A(n1311), .Y(n1220) );
BUFX4TS U1408 ( .A(n1220), .Y(n1308) );
NOR2X2TS U1409 ( .A(n1308), .B(n1152), .Y(n1305) );
NOR2X4TS U1410 ( .A(n1153), .B(n874), .Y(n1295) );
AOI22X1TS U1411 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1295), .B0(n1214), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1155) );
AOI22X1TS U1412 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n904), .B0(n908), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1154) );
NAND2X1TS U1413 ( .A(n1155), .B(n1154), .Y(n1177) );
AOI22X1TS U1414 ( .A0(n1220), .A1(Data_array_SWR[1]), .B0(n1305), .B1(n1177),
.Y(n1158) );
INVX2TS U1415 ( .A(n1156), .Y(n1303) );
NAND2X1TS U1416 ( .A(Raw_mant_NRM_SWR[23]), .B(n1303), .Y(n1157) );
AOI22X1TS U1417 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1295), .B0(n1214), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1161) );
AOI22X1TS U1418 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n904), .B0(n908), .B1(n902),
.Y(n1160) );
NAND2X1TS U1419 ( .A(n1161), .B(n1160), .Y(n1169) );
AOI22X1TS U1420 ( .A0(n1308), .A1(Data_array_SWR[5]), .B0(n1305), .B1(n1169),
.Y(n1163) );
NAND2X1TS U1421 ( .A(Raw_mant_NRM_SWR[19]), .B(n1303), .Y(n1162) );
AOI22X1TS U1422 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1295), .B0(n1214), .B1(
n902), .Y(n1165) );
AOI22X1TS U1423 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n904), .B0(n908), .B1(n898),
.Y(n1164) );
NAND2X1TS U1424 ( .A(n1165), .B(n1164), .Y(n1174) );
AOI22X1TS U1425 ( .A0(n1220), .A1(Data_array_SWR[4]), .B0(n1305), .B1(n1174),
.Y(n1167) );
NAND2X1TS U1426 ( .A(Raw_mant_NRM_SWR[20]), .B(n1303), .Y(n1166) );
AOI22X1TS U1427 ( .A0(n1220), .A1(Data_array_SWR[7]), .B0(n906), .B1(n1169),
.Y(n1173) );
INVX2TS U1428 ( .A(n1295), .Y(n1212) );
NAND2X1TS U1429 ( .A(Raw_mant_NRM_SWR[15]), .B(n1171), .Y(n1172) );
AOI22X1TS U1430 ( .A0(n1220), .A1(Data_array_SWR[6]), .B0(n906), .B1(n1174),
.Y(n1176) );
NAND2X1TS U1431 ( .A(Raw_mant_NRM_SWR[16]), .B(n1171), .Y(n1175) );
AOI22X1TS U1432 ( .A0(n1220), .A1(Data_array_SWR[3]), .B0(n906), .B1(n1177),
.Y(n1179) );
NAND2X1TS U1433 ( .A(Raw_mant_NRM_SWR[19]), .B(n1171), .Y(n1178) );
AOI22X1TS U1434 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1295), .B0(n1294), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1182) );
AOI22X1TS U1435 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n904), .B0(n908), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1181) );
NAND2X1TS U1436 ( .A(n1182), .B(n1181), .Y(n1304) );
AOI22X1TS U1437 ( .A0(n1308), .A1(Data_array_SWR[2]), .B0(n906), .B1(n1304),
.Y(n1184) );
NAND2X1TS U1438 ( .A(Raw_mant_NRM_SWR[20]), .B(n1171), .Y(n1183) );
AOI22X1TS U1439 ( .A0(n1220), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1171), .Y(n1187) );
AOI22X1TS U1440 ( .A0(n908), .A1(DmP_mant_SHT1_SW[21]), .B0(n1189), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1190) );
AOI21X1TS U1441 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n905), .B0(n1191), .Y(n1290)
);
OAI22X1TS U1442 ( .A0(n1232), .A1(n907), .B0(n1558), .B1(n1156), .Y(n1192)
);
AOI21X1TS U1443 ( .A0(n1308), .A1(Data_array_SWR[21]), .B0(n1192), .Y(n1193)
);
AOI22X1TS U1444 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1295), .B0(n1294), .B1(n899), .Y(n1194) );
AOI21X1TS U1445 ( .A0(n909), .A1(DmP_mant_SHT1_SW[18]), .B0(n1195), .Y(n1206) );
OAI22X1TS U1446 ( .A0(n1200), .A1(n907), .B0(n1489), .B1(n1156), .Y(n1196)
);
AOI21X1TS U1447 ( .A0(n1308), .A1(Data_array_SWR[18]), .B0(n1196), .Y(n1197)
);
AOI22X1TS U1448 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1295), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1214), .Y(n1198) );
AOI21X1TS U1449 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n909), .B0(n1199), .Y(n1293) );
INVX2TS U1450 ( .A(n1171), .Y(n1203) );
OAI22X1TS U1451 ( .A0(n1200), .A1(n1168), .B0(n1489), .B1(n1203), .Y(n1201)
);
AOI21X1TS U1452 ( .A0(n1308), .A1(Data_array_SWR[16]), .B0(n1201), .Y(n1202)
);
OAI22X1TS U1453 ( .A0(n1215), .A1(n1168), .B0(n1510), .B1(n1203), .Y(n1204)
);
AOI21X1TS U1454 ( .A0(n1308), .A1(Data_array_SWR[20]), .B0(n1204), .Y(n1205)
);
AOI22X1TS U1455 ( .A0(n908), .A1(DmP_mant_SHT1_SW[8]), .B0(n1294), .B1(n900),
.Y(n1207) );
AOI21X1TS U1456 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n905), .B0(n1208), .Y(n1301) );
OAI22X1TS U1457 ( .A0(n1209), .A1(n907), .B0(n1481), .B1(n1156), .Y(n1210)
);
AOI21X1TS U1458 ( .A0(n1308), .A1(Data_array_SWR[8]), .B0(n1210), .Y(n1211)
);
OAI22X1TS U1459 ( .A0(n1563), .A1(n1297), .B0(n1485), .B1(n1212), .Y(n1213)
);
OAI22X1TS U1460 ( .A0(n1288), .A1(n1168), .B0(n1215), .B1(n907), .Y(n1216)
);
AOI21X1TS U1461 ( .A0(n1308), .A1(Data_array_SWR[22]), .B0(n1216), .Y(n1217)
);
AOI22X1TS U1462 ( .A0(n1308), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1171), .Y(n1219) );
OA22X1TS U1463 ( .A0(n1488), .A1(n1156), .B0(n1230), .B1(n1168), .Y(n1218)
);
AOI22X1TS U1464 ( .A0(n1220), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1171), .Y(n1222) );
OA22X1TS U1465 ( .A0(n1504), .A1(n1156), .B0(n1227), .B1(n1168), .Y(n1221)
);
AOI22X1TS U1466 ( .A0(n1308), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1171), .Y(n1226) );
OA22X1TS U1467 ( .A0(n1482), .A1(n1156), .B0(n1224), .B1(n1168), .Y(n1225)
);
AOI22X1TS U1468 ( .A0(n1308), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1171), .Y(n1229) );
OA22X1TS U1469 ( .A0(n1484), .A1(n1156), .B0(n1236), .B1(n1168), .Y(n1228)
);
AOI22X1TS U1470 ( .A0(n1308), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1171), .Y(n1235) );
OA22X1TS U1471 ( .A0(n1517), .A1(n1156), .B0(n1232), .B1(n1168), .Y(n1234)
);
INVX4TS U1472 ( .A(OP_FLAG_SFG), .Y(n1365) );
AOI22X1TS U1473 ( .A0(n1366), .A1(n931), .B0(DmP_mant_SFG_SWR[7]), .B1(n1365), .Y(intadd_62_B_3_) );
AOI22X1TS U1474 ( .A0(n1366), .A1(n930), .B0(DmP_mant_SFG_SWR[9]), .B1(n1365), .Y(intadd_62_B_5_) );
INVX2TS U1475 ( .A(n1237), .Y(n1371) );
OAI2BB2XLTS U1476 ( .B0(n1238), .B1(n1370), .A0N(n1430), .A1N(
final_result_ieee[31]), .Y(n543) );
AOI22X1TS U1477 ( .A0(n1366), .A1(DmP_mant_SFG_SWR[2]), .B0(n1365), .B1(n923), .Y(n1354) );
NAND2X1TS U1478 ( .A(n1354), .B(DMP_SFG[0]), .Y(n1356) );
INVX2TS U1479 ( .A(n1356), .Y(n1239) );
AOI22X1TS U1480 ( .A0(n1366), .A1(n925), .B0(DmP_mant_SFG_SWR[4]), .B1(n1365), .Y(intadd_62_B_0_) );
INVX2TS U1481 ( .A(intadd_62_B_5_), .Y(n1246) );
INVX2TS U1482 ( .A(intadd_62_B_3_), .Y(n1243) );
AOI21X1TS U1483 ( .A0(intadd_62_A_1_), .A1(n895), .B0(intadd_62_B_0_), .Y(
n1240) );
AOI2BB2X1TS U1484 ( .B0(DMP_SFG[2]), .B1(n1240), .A0N(intadd_62_A_1_), .A1N(
n895), .Y(n1241) );
AOI222X1TS U1485 ( .A0(n1247), .A1(intadd_62_A_6_), .B0(n1247), .B1(
intadd_62_B_6_), .C0(intadd_62_A_6_), .C1(intadd_62_B_6_), .Y(n1248)
);
INVX2TS U1486 ( .A(n1249), .Y(n1250) );
NAND2X1TS U1487 ( .A(n1514), .B(n1250), .Y(DP_OP_15J55_123_4652_n8) );
MX2X1TS U1488 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1489 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1490 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1491 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1492 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1493 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1494 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1495 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
OAI2BB1X1TS U1496 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n874), .B0(n1251), .Y(
n512) );
OAI32X1TS U1497 ( .A0(n874), .A1(Raw_mant_NRM_SWR[14]), .A2(n1253), .B0(
n1252), .B1(n874), .Y(n1257) );
AO21XLTS U1498 ( .A0(n1482), .A1(n1504), .B0(n1254), .Y(n1262) );
AOI21X1TS U1499 ( .A0(n1259), .A1(Raw_mant_NRM_SWR[10]), .B0(n1258), .Y(
n1313) );
AOI2BB1XLTS U1500 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1313), .Y(n516) );
AOI22X1TS U1501 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1261), .B0(n1260), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1263) );
OAI21X1TS U1502 ( .A0(n1267), .A1(n1266), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1309) );
OAI2BB1X1TS U1503 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n874), .B0(n1309), .Y(
n514) );
AO21XLTS U1504 ( .A0(LZD_output_NRM2_EW[1]), .A1(n874), .B0(n1268), .Y(n513)
);
AO21XLTS U1505 ( .A0(LZD_output_NRM2_EW[0]), .A1(n874), .B0(n1295), .Y(n515)
);
OA22X1TS U1506 ( .A0(n1270), .A1(n1269), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1507 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1370),
.Y(n558) );
INVX2TS U1508 ( .A(n1274), .Y(n1272) );
AOI22X1TS U1509 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1272), .B1(n1496), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1510 ( .A(n1272), .B(n1271), .Y(n871) );
NOR2XLTS U1511 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1273) );
AOI32X4TS U1512 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1273), .B1(n1530), .Y(n1277)
);
INVX2TS U1513 ( .A(n1277), .Y(n1276) );
AOI22X1TS U1514 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1274), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1496), .Y(n1278) );
AO22XLTS U1515 ( .A0(n1276), .A1(Shift_reg_FLAGS_7_6), .B0(n1277), .B1(n1278), .Y(n869) );
AOI22X1TS U1516 ( .A0(n1277), .A1(n1275), .B0(n1339), .B1(n1276), .Y(n868)
);
AOI22X1TS U1517 ( .A0(n1277), .A1(n1339), .B0(n1575), .B1(n1276), .Y(n867)
);
INVX4TS U1518 ( .A(n1609), .Y(n1362) );
AOI22X1TS U1519 ( .A0(n1277), .A1(n1609), .B0(n874), .B1(n1276), .Y(n864) );
AOI22X1TS U1520 ( .A0(n1277), .A1(n874), .B0(n1430), .B1(n1276), .Y(n863) );
BUFX4TS U1521 ( .A(n1282), .Y(n1283) );
BUFX3TS U1522 ( .A(n1282), .Y(n1284) );
BUFX3TS U1523 ( .A(n1282), .Y(n1281) );
AO22XLTS U1524 ( .A0(n1281), .A1(Data_X[2]), .B0(n875), .B1(intDX_EWSW[2]),
.Y(n860) );
BUFX3TS U1525 ( .A(n1282), .Y(n1287) );
AO22XLTS U1526 ( .A0(n1287), .A1(Data_X[3]), .B0(n875), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1527 ( .A0(n1284), .A1(Data_X[4]), .B0(n1286), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1528 ( .A0(n1283), .A1(Data_X[5]), .B0(n875), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1529 ( .A0(n1283), .A1(Data_X[6]), .B0(n875), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1530 ( .A0(n1282), .A1(Data_X[7]), .B0(n1286), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1531 ( .A0(n1287), .A1(Data_X[8]), .B0(n875), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1532 ( .A0(n1287), .A1(Data_X[9]), .B0(n875), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1533 ( .A0(n1287), .A1(Data_X[11]), .B0(n1286), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1534 ( .A0(n1283), .A1(Data_X[12]), .B0(n875), .B1(intDX_EWSW[12]),
.Y(n850) );
AO22XLTS U1535 ( .A0(n1284), .A1(Data_X[13]), .B0(n875), .B1(intDX_EWSW[13]),
.Y(n849) );
AO22XLTS U1536 ( .A0(n1282), .A1(Data_X[14]), .B0(n1286), .B1(intDX_EWSW[14]), .Y(n848) );
INVX2TS U1537 ( .A(n1284), .Y(n1286) );
AO22XLTS U1538 ( .A0(n1283), .A1(Data_X[15]), .B0(n1286), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1539 ( .A0(n1281), .A1(Data_X[16]), .B0(n875), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1540 ( .A0(n1283), .A1(Data_X[17]), .B0(n875), .B1(intDX_EWSW[17]),
.Y(n845) );
AO22XLTS U1541 ( .A0(n1282), .A1(Data_X[20]), .B0(n1286), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1542 ( .A0(n1284), .A1(Data_X[21]), .B0(n875), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1543 ( .A0(n1284), .A1(Data_X[22]), .B0(n875), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1544 ( .A0(n1281), .A1(Data_X[23]), .B0(n1286), .B1(intDX_EWSW[23]), .Y(n839) );
INVX2TS U1545 ( .A(n1282), .Y(n1279) );
AO22XLTS U1546 ( .A0(n1279), .A1(intDX_EWSW[24]), .B0(n1282), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1547 ( .A0(n1279), .A1(intDX_EWSW[25]), .B0(n1287), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1548 ( .A0(n1279), .A1(intDX_EWSW[26]), .B0(n1282), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1549 ( .A0(n1287), .A1(Data_X[28]), .B0(n875), .B1(intDX_EWSW[28]),
.Y(n834) );
AO22XLTS U1550 ( .A0(n1283), .A1(add_subt), .B0(n1279), .B1(intAS), .Y(n830)
);
AO22XLTS U1551 ( .A0(n1279), .A1(intDY_EWSW[0]), .B0(n1287), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1552 ( .A0(n1279), .A1(intDY_EWSW[1]), .B0(n1281), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1553 ( .A0(n1279), .A1(intDY_EWSW[2]), .B0(n1281), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1554 ( .A0(n1279), .A1(intDY_EWSW[3]), .B0(n1281), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1555 ( .A0(n1280), .A1(intDY_EWSW[4]), .B0(n1281), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1556 ( .A0(n1285), .A1(intDY_EWSW[5]), .B0(n1281), .B1(Data_Y[5]),
.Y(n823) );
INVX2TS U1557 ( .A(n1282), .Y(n1280) );
AO22XLTS U1558 ( .A0(n1285), .A1(intDY_EWSW[6]), .B0(n1281), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1559 ( .A0(n1280), .A1(intDY_EWSW[7]), .B0(n1281), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1560 ( .A0(n1285), .A1(intDY_EWSW[8]), .B0(n1281), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1561 ( .A0(n1280), .A1(intDY_EWSW[9]), .B0(n1282), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1562 ( .A0(n1285), .A1(intDY_EWSW[10]), .B0(n1283), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1563 ( .A0(n1280), .A1(intDY_EWSW[11]), .B0(n1284), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1564 ( .A0(n1285), .A1(intDY_EWSW[12]), .B0(n1283), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1565 ( .A0(n1285), .A1(intDY_EWSW[13]), .B0(n1283), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1566 ( .A0(n1280), .A1(intDY_EWSW[14]), .B0(n1283), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1567 ( .A0(n1285), .A1(intDY_EWSW[15]), .B0(n1283), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1568 ( .A0(n1285), .A1(intDY_EWSW[16]), .B0(n1283), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1569 ( .A0(n1280), .A1(intDY_EWSW[17]), .B0(n1283), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1570 ( .A0(n1285), .A1(intDY_EWSW[18]), .B0(n1283), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1571 ( .A0(n1285), .A1(intDY_EWSW[19]), .B0(n1283), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1572 ( .A0(n1280), .A1(intDY_EWSW[20]), .B0(n1283), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1573 ( .A0(n1285), .A1(intDY_EWSW[21]), .B0(n1283), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1574 ( .A0(n1285), .A1(intDY_EWSW[22]), .B0(n1287), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1575 ( .A0(n1280), .A1(intDY_EWSW[23]), .B0(n1287), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1576 ( .A0(n1280), .A1(intDY_EWSW[24]), .B0(n1287), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1577 ( .A0(n1285), .A1(intDY_EWSW[25]), .B0(n1282), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1578 ( .A0(n1285), .A1(intDY_EWSW[26]), .B0(n1281), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1579 ( .A0(n1285), .A1(intDY_EWSW[27]), .B0(n1282), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1580 ( .A0(n1285), .A1(intDY_EWSW[28]), .B0(n1282), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1581 ( .A0(n1280), .A1(intDY_EWSW[29]), .B0(n1283), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1582 ( .A0(n1285), .A1(intDY_EWSW[30]), .B0(n1284), .B1(Data_Y[30]), .Y(n798) );
AOI21X1TS U1583 ( .A0(n905), .A1(Raw_mant_NRM_SWR[0]), .B0(n909), .Y(n1289)
);
OAI2BB2XLTS U1584 ( .B0(n1289), .B1(n1151), .A0N(n1308), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1585 ( .B0(n1288), .B1(n1151), .A0N(n1308), .A1N(
Data_array_SWR[24]), .Y(n795) );
OAI222X1TS U1586 ( .A0(n1564), .A1(n1311), .B0(n1151), .B1(n1290), .C0(n1168), .C1(n1289), .Y(n794) );
AOI22X1TS U1587 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1295), .B0(n1294), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1291) );
AOI21X1TS U1588 ( .A0(n909), .A1(DmP_mant_SHT1_SW[12]), .B0(n1292), .Y(n1299) );
OAI222X1TS U1589 ( .A0(n1311), .A1(n1566), .B0(n1151), .B1(n1299), .C0(n1168), .C1(n1293), .Y(n785) );
AOI22X1TS U1590 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1295), .B0(n1294), .B1(
n901), .Y(n1296) );
AOI21X1TS U1591 ( .A0(n909), .A1(DmP_mant_SHT1_SW[10]), .B0(n1298), .Y(n1300) );
OAI222X1TS U1592 ( .A0(n1565), .A1(n1311), .B0(n1151), .B1(n1300), .C0(n1168), .C1(n1299), .Y(n783) );
OAI222X1TS U1593 ( .A0(n1572), .A1(n1311), .B0(n1151), .B1(n1301), .C0(n1168), .C1(n1300), .Y(n781) );
AOI22X1TS U1594 ( .A0(n1308), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1303), .Y(n1307) );
AOI22X1TS U1595 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n905), .B0(n1305), .B1(
n1304), .Y(n1306) );
NAND2X1TS U1596 ( .A(n1307), .B(n1306), .Y(n771) );
NAND2X1TS U1597 ( .A(n1310), .B(n1309), .Y(n770) );
AOI21X1TS U1598 ( .A0(n873), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1312) );
OAI22X1TS U1599 ( .A0(n1313), .A1(n1312), .B0(n1311), .B1(n1511), .Y(n769)
);
INVX4TS U1600 ( .A(n1339), .Y(n1346) );
AOI21X1TS U1601 ( .A0(DMP_EXP_EWSW[23]), .A1(n912), .B0(n1318), .Y(n1314) );
INVX4TS U1602 ( .A(n1339), .Y(n1348) );
AOI2BB2XLTS U1603 ( .B0(n1346), .B1(n1314), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1348), .Y(n766) );
NOR2X1TS U1604 ( .A(n1502), .B(DMP_EXP_EWSW[24]), .Y(n1317) );
AOI21X1TS U1605 ( .A0(DMP_EXP_EWSW[24]), .A1(n1502), .B0(n1317), .Y(n1315)
);
XNOR2X1TS U1606 ( .A(n1318), .B(n1315), .Y(n1316) );
AO22XLTS U1607 ( .A0(n1348), .A1(n1316), .B0(n1339), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
INVX4TS U1608 ( .A(n1339), .Y(n1336) );
OAI22X1TS U1609 ( .A0(n1318), .A1(n1317), .B0(DmP_EXP_EWSW[24]), .B1(n1503),
.Y(n1321) );
NAND2X1TS U1610 ( .A(DmP_EXP_EWSW[25]), .B(n1557), .Y(n1322) );
OAI21XLTS U1611 ( .A0(DmP_EXP_EWSW[25]), .A1(n1557), .B0(n1322), .Y(n1319)
);
XNOR2X1TS U1612 ( .A(n1321), .B(n1319), .Y(n1320) );
AO22XLTS U1613 ( .A0(n1336), .A1(n1320), .B0(n1573), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1614 ( .A0(DMP_EXP_EWSW[25]), .A1(n1568), .B0(n1322), .B1(n1321),
.Y(n1325) );
NOR2X1TS U1615 ( .A(n1505), .B(DMP_EXP_EWSW[26]), .Y(n1326) );
AOI21X1TS U1616 ( .A0(DMP_EXP_EWSW[26]), .A1(n1505), .B0(n1326), .Y(n1323)
);
XNOR2X1TS U1617 ( .A(n1325), .B(n1323), .Y(n1324) );
AO22XLTS U1618 ( .A0(n1348), .A1(n1324), .B0(n1573), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1619 ( .A0(n1326), .A1(n1325), .B0(DmP_EXP_EWSW[26]), .B1(n1507),
.Y(n1328) );
XNOR2X1TS U1620 ( .A(DmP_EXP_EWSW[27]), .B(n903), .Y(n1327) );
XOR2XLTS U1621 ( .A(n1328), .B(n1327), .Y(n1329) );
BUFX3TS U1622 ( .A(n1573), .Y(n1338) );
AO22XLTS U1623 ( .A0(n1336), .A1(n1329), .B0(n1338), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1624 ( .A0(n1341), .A1(n1567), .B0(n1503), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1343), .Y(n729) );
OAI222X1TS U1625 ( .A0(n1341), .A1(n1506), .B0(n1557), .B1(
Shift_reg_FLAGS_7_6), .C0(n1613), .C1(n1343), .Y(n728) );
OAI222X1TS U1626 ( .A0(n1341), .A1(n1571), .B0(n1507), .B1(
Shift_reg_FLAGS_7_6), .C0(n1547), .C1(n1343), .Y(n727) );
OAI21XLTS U1627 ( .A0(n1331), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1330) );
AOI21X1TS U1628 ( .A0(n1331), .A1(intDX_EWSW[31]), .B0(n1330), .Y(n1333) );
AO21XLTS U1629 ( .A0(OP_FLAG_EXP), .A1(n1332), .B0(n1333), .Y(n722) );
AO22XLTS U1630 ( .A0(n1334), .A1(n1333), .B0(ZERO_FLAG_EXP), .B1(n1332), .Y(
n721) );
AO22XLTS U1631 ( .A0(n1336), .A1(DMP_EXP_EWSW[0]), .B0(n1338), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1632 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1575), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
BUFX4TS U1633 ( .A(n1335), .Y(n1462) );
AO22XLTS U1634 ( .A0(n1348), .A1(DMP_EXP_EWSW[1]), .B0(n1338), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1635 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1575), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1636 ( .A0(n1336), .A1(DMP_EXP_EWSW[2]), .B0(n1338), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1637 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1575), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1638 ( .A0(n1476), .A1(DMP_SFG[2]), .B0(n1459), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1639 ( .A0(n1336), .A1(DMP_EXP_EWSW[3]), .B0(n1338), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1640 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1575), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1641 ( .A0(n1465), .A1(DMP_SFG[3]), .B0(n1459), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1642 ( .A0(n1336), .A1(DMP_EXP_EWSW[4]), .B0(n1338), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1643 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1575), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1644 ( .A0(n1476), .A1(DMP_SFG[4]), .B0(n1459), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1645 ( .A0(n1336), .A1(DMP_EXP_EWSW[5]), .B0(n1338), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1646 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1575), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1647 ( .A0(n1476), .A1(DMP_SFG[5]), .B0(n1459), .B1(
DMP_SHT2_EWSW[5]), .Y(n702) );
AO22XLTS U1648 ( .A0(n1336), .A1(DMP_EXP_EWSW[6]), .B0(n1338), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1649 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1575), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1650 ( .A0(n1465), .A1(DMP_SFG[6]), .B0(n1459), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1651 ( .A0(n1336), .A1(DMP_EXP_EWSW[7]), .B0(n1338), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1652 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1575), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1653 ( .A0(n1465), .A1(DMP_SFG[7]), .B0(n1469), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1654 ( .A0(n1336), .A1(DMP_EXP_EWSW[8]), .B0(n1338), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1655 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1575), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1656 ( .A0(n1465), .A1(DMP_SFG[8]), .B0(n1469), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1657 ( .A0(n1336), .A1(DMP_EXP_EWSW[9]), .B0(n1338), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1658 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1575), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1659 ( .A0(n1336), .A1(DMP_EXP_EWSW[10]), .B0(n1338), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
BUFX4TS U1660 ( .A(n1575), .Y(n1345) );
AO22XLTS U1661 ( .A0(n873), .A1(DMP_SHT1_EWSW[10]), .B0(n1345), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1662 ( .A0(n1476), .A1(DMP_SFG[10]), .B0(n1459), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX4TS U1663 ( .A(n1573), .Y(n1340) );
AO22XLTS U1664 ( .A0(n1336), .A1(DMP_EXP_EWSW[11]), .B0(n1340), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1665 ( .A0(n873), .A1(DMP_SHT1_EWSW[11]), .B0(n1345), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1666 ( .A0(n1476), .A1(DMP_SFG[11]), .B0(n1459), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1667 ( .A0(n1336), .A1(DMP_EXP_EWSW[12]), .B0(n1573), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1668 ( .A0(n873), .A1(DMP_SHT1_EWSW[12]), .B0(n1345), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1669 ( .A0(n1476), .A1(DMP_SFG[12]), .B0(n1459), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
BUFX3TS U1670 ( .A(n1573), .Y(n1347) );
AO22XLTS U1671 ( .A0(n1336), .A1(DMP_EXP_EWSW[13]), .B0(n1347), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1672 ( .A0(n873), .A1(DMP_SHT1_EWSW[13]), .B0(n1345), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1673 ( .A0(n1476), .A1(DMP_SFG[13]), .B0(n1459), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1674 ( .A0(n1336), .A1(DMP_EXP_EWSW[14]), .B0(n1340), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1675 ( .A0(n873), .A1(DMP_SHT1_EWSW[14]), .B0(n1345), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1676 ( .A0(n1476), .A1(DMP_SFG[14]), .B0(n1459), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1677 ( .A0(n1336), .A1(DMP_EXP_EWSW[15]), .B0(n1573), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1678 ( .A0(n873), .A1(DMP_SHT1_EWSW[15]), .B0(n1345), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1679 ( .A0(n1476), .A1(DMP_SFG[15]), .B0(n1459), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1680 ( .A0(n1336), .A1(DMP_EXP_EWSW[16]), .B0(n1347), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1681 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1345), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1682 ( .A0(n1476), .A1(DMP_SFG[16]), .B0(n1469), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
AO22XLTS U1683 ( .A0(n1348), .A1(DMP_EXP_EWSW[17]), .B0(n1340), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1684 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1345), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1685 ( .A0(n1476), .A1(DMP_SFG[17]), .B0(n1459), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1686 ( .A0(n1348), .A1(DMP_EXP_EWSW[18]), .B0(n1339), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1687 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1345), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1688 ( .A0(n1465), .A1(DMP_SFG[18]), .B0(n1469), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1689 ( .A0(n1348), .A1(DMP_EXP_EWSW[19]), .B0(n1347), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1690 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1345), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1691 ( .A0(n1476), .A1(DMP_SFG[19]), .B0(n1469), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1692 ( .A0(n1348), .A1(DMP_EXP_EWSW[20]), .B0(n1340), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1693 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1345), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1694 ( .A0(n1476), .A1(DMP_SFG[20]), .B0(n1469), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1695 ( .A0(n1348), .A1(DMP_EXP_EWSW[21]), .B0(n1339), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1696 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1345), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1697 ( .A0(n1476), .A1(DMP_SFG[21]), .B0(n1469), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1698 ( .A0(n1348), .A1(DMP_EXP_EWSW[22]), .B0(n1347), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1699 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1575), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1700 ( .A0(n1476), .A1(DMP_SFG[22]), .B0(n1469), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1701 ( .A0(n1348), .A1(DMP_EXP_EWSW[23]), .B0(n1347), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1702 ( .A0(n873), .A1(DMP_SHT1_EWSW[23]), .B0(n1575), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1703 ( .A0(n1459), .A1(DMP_SHT2_EWSW[23]), .B0(n1476), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1704 ( .A0(n1362), .A1(DMP_SFG[23]), .B0(n1368), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1705 ( .A0(n1348), .A1(DMP_EXP_EWSW[24]), .B0(n1347), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1706 ( .A0(n873), .A1(DMP_SHT1_EWSW[24]), .B0(n1345), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1707 ( .A0(n1469), .A1(DMP_SHT2_EWSW[24]), .B0(n1465), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1708 ( .A0(n1362), .A1(DMP_SFG[24]), .B0(n1609), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1709 ( .A0(n1348), .A1(DMP_EXP_EWSW[25]), .B0(n1347), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1710 ( .A0(n873), .A1(DMP_SHT1_EWSW[25]), .B0(n1345), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1711 ( .A0(n1478), .A1(DMP_SHT2_EWSW[25]), .B0(n1462), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1712 ( .A0(n1362), .A1(DMP_SFG[25]), .B0(n1609), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1713 ( .A0(n1348), .A1(DMP_EXP_EWSW[26]), .B0(n1347), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1714 ( .A0(n873), .A1(DMP_SHT1_EWSW[26]), .B0(n1345), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1715 ( .A0(n1459), .A1(DMP_SHT2_EWSW[26]), .B0(n1476), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1716 ( .A0(n1362), .A1(DMP_SFG[26]), .B0(n1609), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1717 ( .A0(n1348), .A1(n903), .B0(n1347), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1718 ( .A0(n873), .A1(DMP_SHT1_EWSW[27]), .B0(n1345), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1719 ( .A0(n1469), .A1(DMP_SHT2_EWSW[27]), .B0(n1465), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1720 ( .A0(n1362), .A1(DMP_SFG[27]), .B0(n1609), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1721 ( .A0(n1348), .A1(DMP_EXP_EWSW[28]), .B0(n1347), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1722 ( .A0(n873), .A1(DMP_SHT1_EWSW[28]), .B0(n1345), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1723 ( .A0(n1469), .A1(DMP_SHT2_EWSW[28]), .B0(n1476), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1724 ( .A0(n1362), .A1(DMP_SFG[28]), .B0(n1609), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1725 ( .A0(n1348), .A1(DMP_EXP_EWSW[29]), .B0(n1347), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1726 ( .A0(n873), .A1(DMP_SHT1_EWSW[29]), .B0(n1345), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1727 ( .A0(n1469), .A1(DMP_SHT2_EWSW[29]), .B0(n1462), .B1(
DMP_SFG[29]), .Y(n618) );
BUFX4TS U1728 ( .A(n1609), .Y(n1368) );
AO22XLTS U1729 ( .A0(n1362), .A1(DMP_SFG[29]), .B0(n1368), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1730 ( .A0(n1490), .A1(DMP_EXP_EWSW[30]), .B0(n1347), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1731 ( .A0(n873), .A1(DMP_SHT1_EWSW[30]), .B0(n1345), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1732 ( .A0(n1469), .A1(DMP_SHT2_EWSW[30]), .B0(n1465), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1733 ( .A0(n1362), .A1(DMP_SFG[30]), .B0(n1368), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1734 ( .A0(n1490), .A1(DmP_EXP_EWSW[3]), .B0(n1573), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U1735 ( .A0(n1490), .A1(DmP_EXP_EWSW[7]), .B0(n1339), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1736 ( .A0(n1346), .A1(DmP_EXP_EWSW[10]), .B0(n1339), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1737 ( .A0(n1346), .A1(DmP_EXP_EWSW[11]), .B0(n1339), .B1(n901),
.Y(n587) );
OAI222X1TS U1738 ( .A0(n1343), .A1(n1567), .B0(n1502), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1341), .Y(n563) );
OAI222X1TS U1739 ( .A0(n1343), .A1(n1506), .B0(n1568), .B1(
Shift_reg_FLAGS_7_6), .C0(n1613), .C1(n1341), .Y(n562) );
OAI222X1TS U1740 ( .A0(n1343), .A1(n1571), .B0(n1505), .B1(
Shift_reg_FLAGS_7_6), .C0(n1547), .C1(n1341), .Y(n561) );
NAND2X1TS U1741 ( .A(n1371), .B(Shift_reg_FLAGS_7[0]), .Y(n1344) );
OAI2BB1X1TS U1742 ( .A0N(underflow_flag), .A1N(n872), .B0(n1344), .Y(n559)
);
AO22XLTS U1743 ( .A0(n1346), .A1(ZERO_FLAG_EXP), .B0(n1339), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1744 ( .A0(n873), .A1(ZERO_FLAG_SHT1), .B0(n1345), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1745 ( .A0(n1469), .A1(ZERO_FLAG_SHT2), .B0(n1462), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1746 ( .A0(n1362), .A1(ZERO_FLAG_SFG), .B0(n1368), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1747 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n874),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1748 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n872), .B1(zero_flag), .Y(n552) );
AO22XLTS U1749 ( .A0(n1346), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1573),
.Y(n551) );
AO22XLTS U1750 ( .A0(n873), .A1(OP_FLAG_SHT1), .B0(n1575), .B1(OP_FLAG_SHT2),
.Y(n550) );
AO22XLTS U1751 ( .A0(n1476), .A1(OP_FLAG_SFG), .B0(n1469), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1752 ( .A0(n1348), .A1(SIGN_FLAG_EXP), .B0(n1347), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1753 ( .A0(n873), .A1(SIGN_FLAG_SHT1), .B0(n1575), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1754 ( .A0(n1469), .A1(SIGN_FLAG_SHT2), .B0(n1465), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1755 ( .A0(n1362), .A1(SIGN_FLAG_SFG), .B0(n1609), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1756 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n874),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1757 ( .A0(n1366), .A1(n921), .B0(DmP_mant_SFG_SWR[0]), .B1(n1365), .Y(n1352) );
AOI22X1TS U1758 ( .A0(n1364), .A1(n1352), .B0(n1485), .B1(n1368), .Y(n542)
);
AOI22X1TS U1759 ( .A0(n1366), .A1(n922), .B0(DmP_mant_SFG_SWR[1]), .B1(n1365), .Y(n1353) );
AOI22X1TS U1760 ( .A0(n1364), .A1(n1353), .B0(n1563), .B1(n1368), .Y(n541)
);
OAI21XLTS U1761 ( .A0(n1354), .A1(DMP_SFG[0]), .B0(n1356), .Y(n1355) );
AOI22X1TS U1762 ( .A0(n1364), .A1(n1355), .B0(n1510), .B1(n1368), .Y(n540)
);
XNOR2X1TS U1763 ( .A(DMP_SFG[1]), .B(n1356), .Y(n1357) );
XNOR2X1TS U1764 ( .A(n1357), .B(n893), .Y(n1358) );
AOI22X1TS U1765 ( .A0(n1364), .A1(n1358), .B0(n1558), .B1(n1368), .Y(n539)
);
AOI2BB2XLTS U1766 ( .B0(n933), .B1(intadd_62_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1362), .Y(n538) );
AOI22X1TS U1767 ( .A0(n1364), .A1(intadd_62_SUM_1_), .B0(n1517), .B1(n1368),
.Y(n537) );
AOI22X1TS U1768 ( .A0(n933), .A1(intadd_62_SUM_2_), .B0(n1489), .B1(n1368),
.Y(n536) );
AOI22X1TS U1769 ( .A0(n933), .A1(intadd_62_SUM_3_), .B0(n1484), .B1(n1368),
.Y(n535) );
AOI22X1TS U1770 ( .A0(n933), .A1(intadd_62_SUM_4_), .B0(n1486), .B1(n1368),
.Y(n534) );
AOI22X1TS U1771 ( .A0(n933), .A1(intadd_62_SUM_5_), .B0(n1488), .B1(n1368),
.Y(n533) );
AOI22X1TS U1772 ( .A0(n933), .A1(intadd_62_SUM_6_), .B0(n1483), .B1(n1368),
.Y(n532) );
XNOR2X1TS U1773 ( .A(DMP_SFG[9]), .B(n1359), .Y(n1360) );
XNOR2X1TS U1774 ( .A(intadd_62_n1), .B(n1360), .Y(n1361) );
AOI22X1TS U1775 ( .A0(n933), .A1(n1361), .B0(n1482), .B1(n1368), .Y(n531) );
AOI2BB2XLTS U1776 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n911), .A0N(n911), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_61_CI) );
AOI2BB2XLTS U1777 ( .B0(n1362), .B1(intadd_61_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1362), .Y(n530) );
AOI2BB2XLTS U1778 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n911), .A0N(n911), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_61_B_1_) );
AOI22X1TS U1779 ( .A0(n1364), .A1(intadd_61_SUM_1_), .B0(n1504), .B1(n1368),
.Y(n529) );
AOI2BB2XLTS U1780 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n911), .A0N(n1365), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_61_B_2_) );
AOI22X1TS U1781 ( .A0(n1364), .A1(intadd_61_SUM_2_), .B0(n1493), .B1(n1368),
.Y(n528) );
AOI2BB2XLTS U1782 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n911), .A0N(n911), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_61_B_3_) );
AOI22X1TS U1783 ( .A0(n1364), .A1(intadd_61_SUM_3_), .B0(n1492), .B1(n1368),
.Y(n527) );
AOI22X1TS U1784 ( .A0(n1366), .A1(n929), .B0(DmP_mant_SFG_SWR[16]), .B1(n911), .Y(intadd_61_B_4_) );
AOI22X1TS U1785 ( .A0(n1364), .A1(intadd_61_SUM_4_), .B0(n1481), .B1(n1609),
.Y(n526) );
AOI22X1TS U1786 ( .A0(n1366), .A1(n928), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1365), .Y(intadd_61_B_5_) );
AOI22X1TS U1787 ( .A0(n1364), .A1(intadd_61_SUM_5_), .B0(n1509), .B1(n1609),
.Y(n525) );
AOI22X1TS U1788 ( .A0(n1366), .A1(n913), .B0(DmP_mant_SFG_SWR[18]), .B1(n911), .Y(intadd_61_B_6_) );
AOI2BB2XLTS U1789 ( .B0(n933), .B1(intadd_61_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1362), .Y(n524) );
AOI22X1TS U1790 ( .A0(n1366), .A1(n914), .B0(DmP_mant_SFG_SWR[19]), .B1(n911), .Y(intadd_61_B_7_) );
AOI2BB2XLTS U1791 ( .B0(n1362), .B1(intadd_61_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1362), .Y(n523) );
AOI22X1TS U1792 ( .A0(n1366), .A1(n915), .B0(DmP_mant_SFG_SWR[20]), .B1(n911), .Y(intadd_61_B_8_) );
AOI22X1TS U1793 ( .A0(n1366), .A1(n916), .B0(DmP_mant_SFG_SWR[21]), .B1(n911), .Y(intadd_61_B_9_) );
AOI22X1TS U1794 ( .A0(n1364), .A1(intadd_61_SUM_9_), .B0(n1512), .B1(n1609),
.Y(n521) );
AOI22X1TS U1795 ( .A0(OP_FLAG_SFG), .A1(n917), .B0(DmP_mant_SFG_SWR[22]),
.B1(n911), .Y(intadd_61_B_10_) );
AOI22X1TS U1796 ( .A0(n1364), .A1(intadd_61_SUM_10_), .B0(n1508), .B1(n1609),
.Y(n520) );
AOI22X1TS U1797 ( .A0(OP_FLAG_SFG), .A1(n918), .B0(DmP_mant_SFG_SWR[23]),
.B1(n1365), .Y(intadd_61_B_11_) );
AOI22X1TS U1798 ( .A0(n1364), .A1(intadd_61_SUM_11_), .B0(n1479), .B1(n1609),
.Y(n519) );
AOI22X1TS U1799 ( .A0(OP_FLAG_SFG), .A1(n919), .B0(DmP_mant_SFG_SWR[24]),
.B1(n1365), .Y(intadd_61_B_12_) );
AOI22X1TS U1800 ( .A0(n1364), .A1(intadd_61_SUM_12_), .B0(n1480), .B1(n1609),
.Y(n518) );
AOI22X1TS U1801 ( .A0(n1366), .A1(DmP_mant_SFG_SWR[25]), .B0(n1365), .B1(
n920), .Y(n1367) );
XNOR2X1TS U1802 ( .A(intadd_61_n1), .B(n1367), .Y(n1369) );
AOI22X1TS U1803 ( .A0(n933), .A1(n1369), .B0(n1491), .B1(n1368), .Y(n517) );
AND3X4TS U1804 ( .A(shift_value_SHT2_EWR[2]), .B(n1516), .C(
shift_value_SHT2_EWR[3]), .Y(n1437) );
NAND2X1TS U1805 ( .A(shift_value_SHT2_EWR[2]), .B(n1511), .Y(n1390) );
NAND2X1TS U1806 ( .A(n1410), .B(n1516), .Y(n1421) );
NOR2XLTS U1807 ( .A(n1444), .B(n1421), .Y(n1375) );
AOI22X1TS U1808 ( .A0(Data_array_SWR[12]), .A1(n1374), .B0(
Data_array_SWR[13]), .B1(n1445), .Y(n1376) );
OAI221X1TS U1809 ( .A0(n1475), .A1(n1378), .B0(n1444), .B1(n1379), .C0(n1376), .Y(n1457) );
AO22XLTS U1810 ( .A0(final_result_ieee[10]), .A1(n872), .B0(n1391), .B1(
n1457), .Y(n511) );
AOI22X1TS U1811 ( .A0(Data_array_SWR[12]), .A1(n1445), .B0(
Data_array_SWR[13]), .B1(n1374), .Y(n1377) );
OAI221X1TS U1812 ( .A0(n1475), .A1(n1379), .B0(n1444), .B1(n1378), .C0(n1377), .Y(n1458) );
AO22XLTS U1813 ( .A0(n1391), .A1(n1458), .B0(final_result_ieee[11]), .B1(
n872), .Y(n510) );
AOI22X1TS U1814 ( .A0(Data_array_SWR[22]), .A1(n1436), .B0(
Data_array_SWR[18]), .B1(n1373), .Y(n1383) );
AOI22X1TS U1815 ( .A0(Data_array_SWR[14]), .A1(n1445), .B0(
Data_array_SWR[11]), .B1(n1374), .Y(n1380) );
OAI221X1TS U1816 ( .A0(n1475), .A1(n1382), .B0(n1444), .B1(n1383), .C0(n1380), .Y(n1456) );
AO22XLTS U1817 ( .A0(n1391), .A1(n1456), .B0(final_result_ieee[9]), .B1(n872), .Y(n509) );
AOI22X1TS U1818 ( .A0(Data_array_SWR[14]), .A1(n1374), .B0(
Data_array_SWR[11]), .B1(n1445), .Y(n1381) );
OAI221X1TS U1819 ( .A0(n1475), .A1(n1383), .B0(n1444), .B1(n1382), .C0(n1381), .Y(n1460) );
AO22XLTS U1820 ( .A0(n1391), .A1(n1460), .B0(final_result_ieee[12]), .B1(
n872), .Y(n508) );
AOI22X1TS U1821 ( .A0(Data_array_SWR[23]), .A1(n1436), .B0(
Data_array_SWR[19]), .B1(n1373), .Y(n1387) );
AOI22X1TS U1822 ( .A0(Data_array_SWR[10]), .A1(n1374), .B0(
Data_array_SWR[15]), .B1(n1445), .Y(n1384) );
OAI221X1TS U1823 ( .A0(n1475), .A1(n1386), .B0(n1444), .B1(n1387), .C0(n1384), .Y(n1455) );
AO22XLTS U1824 ( .A0(n1391), .A1(n1455), .B0(final_result_ieee[8]), .B1(n872), .Y(n507) );
AOI22X1TS U1825 ( .A0(Data_array_SWR[10]), .A1(n1445), .B0(
Data_array_SWR[15]), .B1(n1374), .Y(n1385) );
OAI221X1TS U1826 ( .A0(n1475), .A1(n1387), .B0(n1444), .B1(n1386), .C0(n1385), .Y(n1461) );
AO22XLTS U1827 ( .A0(n1391), .A1(n1461), .B0(final_result_ieee[13]), .B1(
n872), .Y(n506) );
AOI22X1TS U1828 ( .A0(Data_array_SWR[17]), .A1(n1436), .B0(
Data_array_SWR[13]), .B1(n1373), .Y(n1389) );
CLKAND2X2TS U1829 ( .A(n1410), .B(shift_value_SHT2_EWR[4]), .Y(n1403) );
AOI22X1TS U1830 ( .A0(Data_array_SWR[21]), .A1(n1437), .B0(
Data_array_SWR[25]), .B1(n1403), .Y(n1388) );
NAND2X1TS U1831 ( .A(n1389), .B(n1388), .Y(n1393) );
NOR2X1TS U1832 ( .A(shift_value_SHT2_EWR[2]), .B(n1511), .Y(n1396) );
INVX2TS U1833 ( .A(n1390), .Y(n1411) );
INVX2TS U1834 ( .A(n1441), .Y(n1392) );
INVX4TS U1835 ( .A(n1391), .Y(n1435) );
OAI2BB2XLTS U1836 ( .B0(n1454), .B1(n1435), .A0N(final_result_ieee[7]),
.A1N(n872), .Y(n505) );
OAI2BB2XLTS U1837 ( .B0(n1463), .B1(n1435), .A0N(final_result_ieee[14]),
.A1N(n872), .Y(n504) );
AOI22X1TS U1838 ( .A0(Data_array_SWR[12]), .A1(n1373), .B0(
Data_array_SWR[16]), .B1(n1436), .Y(n1395) );
AOI22X1TS U1839 ( .A0(Data_array_SWR[24]), .A1(n1403), .B0(
Data_array_SWR[20]), .B1(n1437), .Y(n1394) );
NAND2X1TS U1840 ( .A(n1395), .B(n1394), .Y(n1398) );
INVX2TS U1841 ( .A(n1433), .Y(n1397) );
OAI2BB2XLTS U1842 ( .B0(n1453), .B1(n1435), .A0N(final_result_ieee[6]),
.A1N(n872), .Y(n503) );
OAI2BB2XLTS U1843 ( .B0(n1464), .B1(n1435), .A0N(final_result_ieee[15]),
.A1N(n872), .Y(n502) );
AOI22X1TS U1844 ( .A0(Data_array_SWR[15]), .A1(n1436), .B0(
Data_array_SWR[11]), .B1(n1373), .Y(n1400) );
AOI22X1TS U1845 ( .A0(Data_array_SWR[23]), .A1(n1403), .B0(
Data_array_SWR[19]), .B1(n1437), .Y(n1399) );
NAND2X1TS U1846 ( .A(n1400), .B(n1399), .Y(n1402) );
AOI22X1TS U1847 ( .A0(Data_array_SWR[22]), .A1(n1411), .B0(
Data_array_SWR[18]), .B1(n1410), .Y(n1427) );
INVX2TS U1848 ( .A(n1427), .Y(n1401) );
OAI2BB2XLTS U1849 ( .B0(n1452), .B1(n1435), .A0N(final_result_ieee[5]),
.A1N(n872), .Y(n501) );
OAI2BB2XLTS U1850 ( .B0(n1466), .B1(n1435), .A0N(final_result_ieee[16]),
.A1N(n872), .Y(n500) );
AOI22X1TS U1851 ( .A0(Data_array_SWR[14]), .A1(n1436), .B0(
Data_array_SWR[10]), .B1(n1373), .Y(n1405) );
AOI22X1TS U1852 ( .A0(Data_array_SWR[22]), .A1(n1403), .B0(
Data_array_SWR[18]), .B1(n1437), .Y(n1404) );
NAND2X1TS U1853 ( .A(n1405), .B(n1404), .Y(n1407) );
AOI22X1TS U1854 ( .A0(Data_array_SWR[23]), .A1(n1411), .B0(
Data_array_SWR[19]), .B1(n1410), .Y(n1424) );
INVX2TS U1855 ( .A(n1424), .Y(n1406) );
OAI2BB2XLTS U1856 ( .B0(n1451), .B1(n1435), .A0N(final_result_ieee[4]),
.A1N(n1430), .Y(n499) );
OAI2BB2XLTS U1857 ( .B0(n1467), .B1(n1435), .A0N(final_result_ieee[17]),
.A1N(n1430), .Y(n498) );
AOI22X1TS U1858 ( .A0(Data_array_SWR[21]), .A1(n1410), .B0(
Data_array_SWR[25]), .B1(n1411), .Y(n1416) );
AOI22X1TS U1859 ( .A0(Data_array_SWR[13]), .A1(n1436), .B0(Data_array_SWR[9]), .B1(n1373), .Y(n1409) );
NAND2X1TS U1860 ( .A(Data_array_SWR[17]), .B(n1437), .Y(n1408) );
OAI211X1TS U1861 ( .A0(n1416), .A1(n1516), .B0(n1409), .C0(n1408), .Y(n1412)
);
AO22X1TS U1862 ( .A0(Data_array_SWR[24]), .A1(n1411), .B0(Data_array_SWR[20]), .B1(n1410), .Y(n1413) );
OAI2BB2XLTS U1863 ( .B0(n1450), .B1(n1435), .A0N(final_result_ieee[3]),
.A1N(n1430), .Y(n497) );
OAI2BB2XLTS U1864 ( .B0(n1468), .B1(n1435), .A0N(final_result_ieee[18]),
.A1N(n1430), .Y(n496) );
AOI22X1TS U1865 ( .A0(Data_array_SWR[12]), .A1(n1436), .B0(Data_array_SWR[8]), .B1(n1373), .Y(n1415) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[16]), .A1(n1437), .B0(
shift_value_SHT2_EWR[4]), .B1(n1413), .Y(n1414) );
NAND2X1TS U1867 ( .A(n1415), .B(n1414), .Y(n1420) );
INVX2TS U1868 ( .A(n1416), .Y(n1419) );
OAI2BB2XLTS U1869 ( .B0(n1449), .B1(n1435), .A0N(final_result_ieee[2]),
.A1N(n1430), .Y(n495) );
OAI2BB2XLTS U1870 ( .B0(n1470), .B1(n1435), .A0N(final_result_ieee[19]),
.A1N(n1430), .Y(n494) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[15]), .A1(n1437), .B0(
Data_array_SWR[11]), .B1(n1436), .Y(n1423) );
INVX2TS U1872 ( .A(n1421), .Y(n1438) );
AOI22X1TS U1873 ( .A0(Data_array_SWR[7]), .A1(n1373), .B0(Data_array_SWR[3]),
.B1(n1438), .Y(n1422) );
OAI211X1TS U1874 ( .A0(n1424), .A1(n1516), .B0(n1423), .C0(n1422), .Y(n1428)
);
AOI22X1TS U1875 ( .A0(Data_array_SWR[22]), .A1(n1445), .B0(n1444), .B1(n1428), .Y(n1448) );
OAI2BB2XLTS U1876 ( .B0(n1448), .B1(n1435), .A0N(final_result_ieee[1]),
.A1N(n1430), .Y(n493) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[14]), .A1(n1437), .B0(
Data_array_SWR[10]), .B1(n1436), .Y(n1426) );
AOI22X1TS U1878 ( .A0(Data_array_SWR[6]), .A1(n1373), .B0(Data_array_SWR[2]),
.B1(n1438), .Y(n1425) );
OAI211X1TS U1879 ( .A0(n1427), .A1(n1516), .B0(n1426), .C0(n1425), .Y(n1429)
);
AOI22X1TS U1880 ( .A0(Data_array_SWR[23]), .A1(n1445), .B0(n1444), .B1(n1429), .Y(n1447) );
OAI2BB2XLTS U1881 ( .B0(n1447), .B1(n1435), .A0N(final_result_ieee[0]),
.A1N(n1430), .Y(n492) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[22]), .A1(n1374), .B0(n1475), .B1(n1428), .Y(n1471) );
OAI2BB2XLTS U1883 ( .B0(n1471), .B1(n1435), .A0N(final_result_ieee[20]),
.A1N(n1430), .Y(n491) );
AOI22X1TS U1884 ( .A0(Data_array_SWR[23]), .A1(n1374), .B0(n1475), .B1(n1429), .Y(n1472) );
OAI2BB2XLTS U1885 ( .B0(n1472), .B1(n1435), .A0N(final_result_ieee[21]),
.A1N(n1430), .Y(n490) );
AOI22X1TS U1886 ( .A0(Data_array_SWR[13]), .A1(n1437), .B0(Data_array_SWR[9]), .B1(n1436), .Y(n1432) );
AOI22X1TS U1887 ( .A0(Data_array_SWR[5]), .A1(n1373), .B0(Data_array_SWR[1]),
.B1(n1438), .Y(n1431) );
OAI211X1TS U1888 ( .A0(n1433), .A1(n1516), .B0(n1432), .C0(n1431), .Y(n1443)
);
AOI22X1TS U1889 ( .A0(Data_array_SWR[24]), .A1(n1374), .B0(n1475), .B1(n1443), .Y(n1473) );
OAI2BB2XLTS U1890 ( .B0(n1473), .B1(n1435), .A0N(final_result_ieee[22]),
.A1N(n872), .Y(n489) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[12]), .A1(n1437), .B0(Data_array_SWR[8]), .B1(n1436), .Y(n1440) );
AOI22X1TS U1892 ( .A0(Data_array_SWR[4]), .A1(n1373), .B0(Data_array_SWR[0]),
.B1(n1438), .Y(n1439) );
OAI211X1TS U1893 ( .A0(n1441), .A1(n1516), .B0(n1440), .C0(n1439), .Y(n1474)
);
AOI22X1TS U1894 ( .A0(Data_array_SWR[25]), .A1(n1445), .B0(n1444), .B1(n1474), .Y(n1442) );
AOI22X1TS U1895 ( .A0(n1459), .A1(n1442), .B0(n921), .B1(n1462), .Y(n488) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[24]), .A1(n1445), .B0(n1444), .B1(n1443), .Y(n1446) );
AOI22X1TS U1897 ( .A0(n1478), .A1(n1446), .B0(n922), .B1(n1462), .Y(n487) );
AOI22X1TS U1898 ( .A0(n1478), .A1(n1447), .B0(n1462), .B1(n923), .Y(n486) );
AOI22X1TS U1899 ( .A0(n1478), .A1(n1448), .B0(n1465), .B1(n924), .Y(n485) );
AOI22X1TS U1900 ( .A0(n1478), .A1(n1449), .B0(n925), .B1(n1462), .Y(n484) );
AOI22X1TS U1901 ( .A0(n1478), .A1(n1450), .B0(n926), .B1(n1465), .Y(n483) );
AOI22X1TS U1902 ( .A0(n1478), .A1(n1451), .B0(n927), .B1(n1462), .Y(n482) );
AOI22X1TS U1903 ( .A0(n1478), .A1(n1452), .B0(n931), .B1(n1462), .Y(n481) );
AOI22X1TS U1904 ( .A0(n1478), .A1(n1453), .B0(n891), .B1(n1462), .Y(n480) );
AOI22X1TS U1905 ( .A0(n1478), .A1(n1454), .B0(n930), .B1(n1465), .Y(n479) );
AO22XLTS U1906 ( .A0(n1462), .A1(DmP_mant_SFG_SWR[10]), .B0(n1459), .B1(
n1455), .Y(n478) );
AO22XLTS U1907 ( .A0(n1465), .A1(DmP_mant_SFG_SWR[11]), .B0(n1459), .B1(
n1456), .Y(n477) );
AO22XLTS U1908 ( .A0(n1462), .A1(DmP_mant_SFG_SWR[12]), .B0(n1459), .B1(
n1457), .Y(n476) );
AO22XLTS U1909 ( .A0(n1462), .A1(DmP_mant_SFG_SWR[13]), .B0(n1459), .B1(
n1458), .Y(n475) );
AO22XLTS U1910 ( .A0(n1462), .A1(DmP_mant_SFG_SWR[14]), .B0(n1469), .B1(
n1460), .Y(n474) );
AO22XLTS U1911 ( .A0(n1462), .A1(DmP_mant_SFG_SWR[15]), .B0(n1469), .B1(
n1461), .Y(n473) );
AOI22X1TS U1912 ( .A0(n1478), .A1(n1463), .B0(n929), .B1(n1465), .Y(n472) );
AOI22X1TS U1913 ( .A0(n1478), .A1(n1464), .B0(n928), .B1(n1465), .Y(n471) );
AOI22X1TS U1914 ( .A0(n1478), .A1(n1466), .B0(n913), .B1(n1465), .Y(n470) );
AOI22X1TS U1915 ( .A0(n1478), .A1(n1467), .B0(n914), .B1(n1476), .Y(n469) );
AOI22X1TS U1916 ( .A0(n1469), .A1(n1468), .B0(n915), .B1(n1465), .Y(n468) );
AOI22X1TS U1917 ( .A0(n1478), .A1(n1470), .B0(n916), .B1(n1335), .Y(n467) );
AOI22X1TS U1918 ( .A0(n1478), .A1(n1471), .B0(n917), .B1(n1335), .Y(n466) );
AOI22X1TS U1919 ( .A0(n1478), .A1(n1472), .B0(n918), .B1(n1335), .Y(n465) );
AOI22X1TS U1920 ( .A0(n1478), .A1(n1473), .B0(n919), .B1(n1335), .Y(n464) );
AOI22X1TS U1921 ( .A0(Data_array_SWR[25]), .A1(n1374), .B0(n1475), .B1(n1474), .Y(n1477) );
AOI22X1TS U1922 ( .A0(n1478), .A1(n1477), .B0(n1465), .B1(n920), .Y(n463) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_GeArN16R4P8_syn.sdf");
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____6.144______0.000______50.0______571.196____386.048
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dimm_if_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dimm_if_mon(/*AUTOARG*/
// Inputs
clk,
DRAM_CK, DRAM_CKE, DRAM_RST_L,
DRAM_CS_L, DRAM_BA, DRAM_ADDR,
DRAM_RAS_L, DRAM_CAS_L, DRAM_WE_L,
DRAM_DQ, DRAM_CB, DRAM_DQS,
DRAM_ENB_ERROR, DRAM_FAIL_OVER,
DRAM_FAIL_PART
);
parameter AUTOREF_PERIOD = 1500;
parameter ST_RAS = 2'b00;
parameter ST_CAS = 2'b01;
parameter ST_DATA = 2'b10;
parameter ST_REL = 2'b11;
//parameter ENB_MECC_ERROR = 1'b0;
input clk;
input [7:0] DRAM_CK;
input DRAM_CKE;
input DRAM_RST_L;
input [1:0] DRAM_CS_L;
input [2:0] DRAM_BA;
input [14:0] DRAM_ADDR;
input DRAM_RAS_L;
input DRAM_CAS_L;
input DRAM_WE_L;
inout [127:0] DRAM_DQ;
input [15:0] DRAM_CB;
input [35:0] DRAM_DQS;
input DRAM_ENB_ERROR;
input DRAM_FAIL_OVER;
input [5:0] DRAM_FAIL_PART;
integer ref_timer;
integer dq_dly;
//reg enable_errors;
reg [1:0] error_st;
reg inject_err_s1;
reg inject_err_s1_1;
reg inject_err_s1_2;
reg inject_err_s1_3;
reg inject_err_s1_4;
reg inject_err_s1_5;
wire inject_err_s2;
wire inject_err_s2_d1;
wire inject_err_s2_d2;
wire inject_err_s2_d3;
reg inject_err_s3;
reg inject_err_s3_d1;
reg inject_err_s3_d2;
reg inject_err_s3_d3;
reg [127:0] data;
reg [15:0] ecc;
reg [3:0] err_bits,err_bits1;
wire [3:0] synd_err_bits;
reg [3:0] inject_enable;
reg ecc_err_inject;
wire synd_ecc_err_inject;
reg [31:0] err_pos;
reg [31:0] err_pos1;
reg [31:0] synd_err_pos;
wire [31:0] synd_err_pos1;
integer flip_for_mecc;
reg ADDR_PARITY_ERR;
reg ENB_MECC_ERROR;
reg disable_mecc, disable_secc;
reg [2:0] cas_latency;
integer stop_dq_dly;
initial begin
@(posedge DRAM_RST_L) ref_timer = 0;
flip_for_mecc = 1;
if ($test$plusargs("ADDR_PARITY_ERR")) begin
ADDR_PARITY_ERR = 1;
end else begin
ADDR_PARITY_ERR = 0;
end
if ($test$plusargs("ENB_MECC_ERROR")) begin
ENB_MECC_ERROR = 1;
end else begin
ENB_MECC_ERROR = 0;
end
end
initial begin
err_pos = 0;
err_pos1 = 0;
ecc_err_inject = 1;
end
/*
always @ (posedge DRAM_CK) begin
if ( !DRAM_CS_L && !DRAM_RAS_L && !DRAM_CAS_L) ref_timer = 0;
else if (DRAM_RST_L) ref_timer = ref_timer + 1;
if (ref_timer > AUTOREF_PERIOD) begin
$display("%0d Error: %m : Autorefresh time has expired", $time);
cmp_top.monitor.fail("Autorefresh time has expired");
end
end
*/
initial
begin
if (! $value$plusargs("force_cas_latency=%d", cas_latency)) begin
cas_latency = 3 ;
end
end
initial begin
//enable_errors = 1'b0;
error_st = ST_RAS;
dq_dly = 0;
inject_err_s1 = 1'b0;
inject_err_s3 = 1'b0;
data = 128'h0;
ecc = 16'h0;
disable_mecc = 1'b0;
disable_secc = 1'b0;
end
always @(clk) begin
//if (DRAM_RST_L && enable_errors) begin
if ( (DRAM_RST_L && DRAM_ENB_ERROR) || (DRAM_RST_L && DRAM_FAIL_OVER) ) begin
case (error_st)
ST_RAS: begin
//$display ("%0d %m: Err injector state ST_RAS\n", $time);
if ( !DRAM_RAS_L && DRAM_CAS_L && DRAM_WE_L &&
// why restrict errors to Bank 0 only, inject in all banks.
//!DRAM_CS_L[0] && (DRAM_BA[2:0] === 3'b000) )
!DRAM_CS_L[0] )
error_st <= ST_CAS;
end
ST_CAS: begin
//$display ("%0d %m: Err injector state ST_CAS\n", $time);
if ( DRAM_RAS_L && !DRAM_CAS_L && !DRAM_WE_L &&
// why restrict errors to Bank 0 only, inject in all banks.
//!DRAM_CS_L[0] && (DRAM_BA[2:0] === 3'b000) )
!DRAM_CS_L[0] )
error_st <= ST_DATA;
end
ST_DATA: begin
$display ("%0d %m: Err injector state ST_DATA\n", $time);
case(cas_latency)
4: begin
stop_dq_dly = 4;
end
5: begin
stop_dq_dly = 6;
end
6: begin
stop_dq_dly = 8;
end
7: begin
stop_dq_dly = 10;
end
default: begin
stop_dq_dly = cas_latency-1;
end
endcase
if (dq_dly == stop_dq_dly) begin
//if (dq_dly == 2) begin
inject_err_s1 <= 1'b1;
dq_dly <= 0;
error_st <= ST_REL;
end
else dq_dly <= dq_dly + 1;
end
ST_REL: begin
//$display ("%0d %m: Err injector state ST_REL\n", $time);
inject_err_s1 <= 1'b0;
//release DRAM_DQ;
error_st <= ST_RAS;
end
default: begin
$display ("%0d %m: Err injector entered unknown state\n", $time);
error_st <= ST_RAS;
end
endcase
end
end
//assign #1506 inject_err_s2 = inject_err_s1;
always @(clk) begin
inject_err_s1_1 <= inject_err_s1;
inject_err_s1_2 <= inject_err_s1_1;
inject_err_s1_3 <= inject_err_s1_2;
inject_err_s1_4 <= inject_err_s1_3;
inject_err_s1_5 <= inject_err_s1_4;
end
// for the default run the clks are updated and needed to add 155 ps to
// capture the data and inject error.
// This need to be verified for the regression
assign #1661 inject_err_s2 = inject_err_s1_2;
assign #1662 inject_err_s2_d1 = inject_err_s1_3;
assign #1663 inject_err_s2_d2 = inject_err_s1_4;
assign #1664 inject_err_s2_d3 = inject_err_s1_5;
// before adding CTU/ clock change
//assign #1506 inject_err_s2 = inject_err_s1_2;
//assign #1507 inject_err_s2_d1 = inject_err_s1_3;
//assign #1508 inject_err_s2_d2 = inject_err_s1_4;
//assign #1509 inject_err_s2_d3 = inject_err_s1_5;
// always @ (posedge inject_err_s2 ) begin
// data <= DRAM_DQ;
// inject_err_s3 <= 1'b1;
// end
// always @ (negedge inject_err_s2) begin
// inject_err_s3 = 1'b0;
// end
always @ (posedge inject_err_s2 or posedge inject_err_s2_d1 or posedge inject_err_s2_d2 or posedge inject_err_s2_d3 ) begin
data <= DRAM_DQ;
ecc <= DRAM_CB;
inject_enable = $random & 4'hf;
//inject_enable = 4'hf;
if ($test$plusargs("ONE_ERROR")) begin
inject_err_s3 <= (1'b1 && inject_err_s2);
inject_err_s3_d1 <= (1'b0 && inject_err_s2_d1);
inject_err_s3_d2 <= (1'b0 && inject_err_s2_d2);
inject_err_s3_d3 <= (1'b0 && inject_err_s2_d3);
end else begin
if ($test$plusargs("TWO_ERROR")) begin
inject_err_s3 <= (1'b1 && inject_err_s2);
inject_err_s3_d1 <= (1'b0 && inject_err_s2_d1);
inject_err_s3_d2 <= (1'b1 && inject_err_s2_d2);
inject_err_s3_d3 <= (1'b0 && inject_err_s2_d3);
end else begin
inject_err_s3 <= (inject_enable[0] && inject_err_s2);
inject_err_s3_d1 <= (inject_enable[0] && inject_err_s2_d1);
inject_err_s3_d2 <= (inject_enable[0] && inject_err_s2_d2);
inject_err_s3_d3 <= (inject_enable[0] && inject_err_s2_d3);
end
end
end
always @ (negedge inject_err_s2) begin
inject_err_s3 = 1'b0;
end
always @ (negedge inject_err_s2_d1) begin
inject_err_s3_d1 = 1'b0;
end
always @ (negedge inject_err_s2_d2) begin
inject_err_s3_d2 = 1'b0;
end
always @ (negedge inject_err_s2_d3) begin
inject_err_s3_d3 = 1'b0;
end
always @ (posedge inject_err_s2_d3)
flip_for_mecc = !flip_for_mecc;
always @ (posedge inject_err_s3 or posedge inject_err_s3_d1 or posedge inject_err_s3_d2 or posedge inject_err_s3_d3) begin
err_bits = $random & 4'hf;
err_bits1 = $random & 4'hf;
// If injecting error in each nibble
if ($test$plusargs("EACH_NIBBLE_ERROR")) begin
ecc_err_inject = (err_pos == 0) ? !ecc_err_inject : ecc_err_inject;
err_pos = (err_pos == 124) ? 0 : (((err_pos >> 2) + 1)*4);
err_pos1 = (err_pos1 == 124) ? 0 : (err_pos == 124) ? (((err_pos1 >> 2) + 1)*4) : err_pos1;
end else begin
ecc_err_inject = $random & 1'b1;
err_pos = ($random & 5'h1f) * 4;
err_pos1 = ($random & 5'h1f) * 4;
end
//force DRAM_DQ = data ^ (1'b1 << err_pos);
if (DRAM_ENB_ERROR && DRAM_FAIL_OVER) begin
force DRAM_DQ = data ^ ((err_bits << err_pos) | (4'hf << (DRAM_FAIL_PART * 4)));
$display ("%0d: Injecting Err on data %x at bit %d\n", $time, data, err_pos);
end else if (DRAM_ENB_ERROR) begin
// This part of code to send only one error
// So for mecc secc : ONLY_ONE_MECC_SECC, ADDR_PARITY_ERR
// So for secc mecc : ONLY_ONE_SECC_MECC, ADDR_PARITY_ERR
if ($test$plusargs("ONLY_ONE_MECC_SECC")) begin
if (ADDR_PARITY_ERR && !disable_mecc) begin
force DRAM_CB = ~ecc;
$display ("%0d: Address parity inversion : Injecting Err by inverting ecc %x \n", $time, ecc);
disable_mecc = 1;
end else begin
if(!disable_secc) begin
disable_secc = 1;
force DRAM_DQ = data ^ (err_bits << err_pos);
$display ("%0d: Injecting Err on data %x at bit %d\n", $time, data, err_pos);
end
end
end else if ($test$plusargs("ONLY_ONE_SECC_MECC")) begin
if(!disable_secc) begin
disable_secc = 1;
force DRAM_DQ = data ^ (err_bits << err_pos);
$display ("%0d: Injecting Err on data %x at bit %d\n", $time, data, err_pos);
end else begin
if (ADDR_PARITY_ERR && !disable_mecc) begin
force DRAM_CB = ~ecc;
$display ("%0d: Address parity inversion : Injecting Err by inverting ecc %x \n", $time, ecc);
disable_mecc = 1;
end
end
end else if ($test$plusargs("SYNDROME_TEST")) begin
synd_err_pos = (synd_err_pos1 & 5'h1f) * 4;
if(!synd_ecc_err_inject) begin // this is a random number so inject data or ecc errors randomly
force DRAM_DQ = data ^ (synd_err_bits << synd_err_pos);
$display ("%0d: Injecting Err on data %x at bit %d\n", $time, data, synd_err_pos);
$display ("%0d: Erred data %x at synd_err_pos %x with synd_err_bits %x\n", $time, DRAM_DQ, synd_err_pos,synd_err_bits);
end else begin
force DRAM_CB = ecc ^ (synd_err_bits << synd_err_pos[3:0]);
$display ("%0d: Injecting Err on ecc %x at bit %d\n", $time, ecc, synd_err_pos[3:0]);
$display ("%0d: Erred ecc %x at synd_err_pos %x with synd_err_bits %x\n", $time, DRAM_CB, synd_err_pos[3:0],synd_err_bits);
end
end else begin
// This is normal error injection
if (ADDR_PARITY_ERR) begin
force DRAM_CB = ~ecc;
$display ("%0d: Address parity inversion : Injecting Err by inverting ecc %x \n", $time, ecc);
end else begin
if (ENB_MECC_ERROR ) begin
//if (ENB_MECC_ERROR & flip_for_mecc) begin
//force DRAM_DQ = ~(data ^ (err_bits << err_pos));
// MECC is multiple errors in different chunks for data
force DRAM_DQ = (data ^ (err_bits << err_pos) ^ (err_bits1 << err_pos1) );
$display ("%0d: Injecting Err on data %x at bit %d %d\n", $time, data, err_pos,err_pos1);
end else
if(!ecc_err_inject) begin // this is a random number so inject data or ecc errors randomly
force DRAM_DQ = data ^ (err_bits << err_pos);
$display ("%0d: Injecting Err on data %x at bit %d\n", $time, data, err_pos);
$display ("%0d: Erred data %x at err_pos %x with err_bits %x\n", $time, DRAM_DQ, err_pos,err_bits);
end else begin
force DRAM_CB = ecc ^ (err_bits << err_pos[3:0]);
$display ("%0d: Injecting Err on ecc %x at bit %d\n", $time, ecc, err_pos[3:0]);
$display ("%0d: Erred ecc %x at err_pos %x with err_bits %x\n", $time, DRAM_CB, err_pos[3:0],err_bits);
end
end
end
end
else if (DRAM_FAIL_OVER)
force DRAM_DQ = data ^ (4'hf << (DRAM_FAIL_PART * 4));
else
force DRAM_DQ = data;
//force DRAM_DQ[3:0] = ~data[3:0];
end
always @ (negedge inject_err_s3 or negedge inject_err_s3_d1 or negedge inject_err_s3_d2 or negedge inject_err_s3_d3 ) begin
release DRAM_DQ[127:0];
release DRAM_CB[15:0];
end
//assign DRAM_DQ[127:0] = (inject_err_s3) ? data[127:0] : 128'hZ;
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931282546056;
wire exception_139931280760344;
wire exception_139931282537000;
wire exception_139931282531896;
wire exception_139931277447608;
wire exception_139931281903056;
wire exception_139931281254664;
wire exception_139931278294480;
wire exception_139931277019760;
wire exception_139931279973840;
wire exception_139931281230160;
wire exception_139931278403200;
wire exception_139931285498840;
wire exception_139931281048568;
wire exception_139931285499128;
wire exception_139931280716000;
main_0 main_0_139931282546056(
.clk(clk),
.rst(rst),
.exception(exception_139931282546056),
.input_eth_in(input_eth_rx),
.input_eth_in_stb(input_eth_rx_stb),
.input_eth_in_ack(input_eth_rx_ack),
.output_audio_out(output_audio),
.output_audio_out_stb(output_audio_stb),
.output_audio_out_ack(output_audio_ack),
.output_eth_out(output_eth_tx),
.output_eth_out_stb(output_eth_tx_stb),
.output_eth_out_ack(output_eth_tx_ack));
main_1 main_1_139931280760344(
.clk(clk),
.rst(rst),
.exception(exception_139931280760344),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931282537000(
.clk(clk),
.rst(rst),
.exception(exception_139931282537000),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931282531896(
.clk(clk),
.rst(rst),
.exception(exception_139931282531896),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931277447608(
.clk(clk),
.rst(rst),
.exception(exception_139931277447608),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931281903056(
.clk(clk),
.rst(rst),
.exception(exception_139931281903056),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931281254664(
.clk(clk),
.rst(rst),
.exception(exception_139931281254664),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931278294480(
.clk(clk),
.rst(rst),
.exception(exception_139931278294480),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931277019760(
.clk(clk),
.rst(rst),
.exception(exception_139931277019760),
.output_out(output_rs232_tx),
.output_out_stb(output_rs232_tx_stb),
.output_out_ack(output_rs232_tx_ack));
main_9 main_9_139931279973840(
.clk(clk),
.rst(rst),
.exception(exception_139931279973840),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_10 main_10_139931281230160(
.clk(clk),
.rst(rst),
.exception(exception_139931281230160),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_11 main_11_139931278403200(
.clk(clk),
.rst(rst),
.exception(exception_139931278403200),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_12 main_12_139931285498840(
.clk(clk),
.rst(rst),
.exception(exception_139931285498840),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_13 main_13_139931281048568(
.clk(clk),
.rst(rst),
.exception(exception_139931281048568),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_14 main_14_139931285499128(
.clk(clk),
.rst(rst),
.exception(exception_139931285499128),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_15 main_15_139931280716000(
.clk(clk),
.rst(rst),
.exception(exception_139931280716000),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931282546056 || exception_139931280760344 || exception_139931282537000 || exception_139931282531896 || exception_139931277447608 || exception_139931281903056 || exception_139931281254664 || exception_139931278294480 || exception_139931277019760 || exception_139931279973840 || exception_139931281230160 || exception_139931278403200 || exception_139931285498840 || exception_139931281048568 || exception_139931285499128 || exception_139931280716000;
endmodule
|
`include "timescale.v"
module fb_txmac (MTxClk, Reset, TxStartFrm, TxUnderRun, DataSoC, NumbSoC, DistSoC, DelaySoC, DelayDistSoC, TxData,
LastSlaveIDPlus1, AveSlaveDelay,
MTxD, MTxEn, MTxErr, TxDone, TxUsedData, WillTransmit,
StartTxDone, StateIdle, StatePreamble, StateSoC, StateNumb, StateDist, StateDelay, StateDelayDist, StateData, StateCrc, StateFrmCrc,
TxRamAddr
);
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxUnderRun; // Transmit packet under-run
input DataSoC;
input NumbSoC;
input DistSoC;
input DelaySoC;
input DelayDistSoC;
input [7:0] LastSlaveIDPlus1;
input [7:0] AveSlaveDelay;
input [7:0] TxData; // Transmit packet data byte
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output StartTxDone;
output StateIdle;
output StatePreamble;
output StateSoC;
output StateNumb;
output [1:0] StateDist;
output StateDelay;
output [1:0] StateDelayDist;
output [1:0] StateData;
output StateCrc;
output StateFrmCrc;
output [7:0]TxRamAddr;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxUsedData;
reg WillTransmit;
reg [3:0] MTxD_d;
reg PacketFinished_q;
reg PacketFinished;
reg RegDataSoC;
reg RegNumbSoC;
reg RegDistSoC;
reg RegDelaySoC;
reg RegDelayDistSoC;
reg [15:0] RegTotalFrmNibbleCnt;
wire MTxClk_n;
wire SlaveEndFrm;
wire TxEndFrm;
wire NumbStateEnd;
wire DistStateEnd;
wire DelayStateEnd;
wire DelayDistStateEnd;
wire [1: 0] StartData;
wire UnderRun;
wire [7:0] Crc;
wire [7:0] FrmCrc;
wire CrcError;
wire FrmCrcError;
wire [15:0] TotalNibCnt;
wire [15:0] NibCnt;
wire PacketFinished_d;
wire CrcStateEnd;
wire PreambleStateEnd;
wire FrmCrcStateEnd;
wire [7:0]TxRamAddr;
wire [3:0]CrcNibCnt;
wire [7:0] SlaveDataNibbleCnt;
assign SlaveDataNibbleCnt = 8'd4; // assume each slave has 4 nibbles(2bytes) data
assign StartTxDone = (StateFrmCrc & FrmCrcStateEnd);
assign UnderRun = StateData[0] & TxUnderRun ;
assign SlaveEndFrm = (NibCnt == (SlaveDataNibbleCnt - 1'b1 ) & ( NibCnt != 32'b0 ));
assign TxEndFrm = (TotalNibCnt == (RegTotalFrmNibbleCnt - 1'b1)) ;
assign NumbStateEnd = (TotalNibCnt == 16'd6 - 16'd1 );
assign DistStateEnd = (TotalNibCnt == 16'd6 - 16'd1 );
assign DelayStateEnd = (TotalNibCnt == 16'd6 - 16'd1 );
assign DelayDistStateEnd = (TotalNibCnt == 16'd6 - 16'd1 );
always @ (LastSlaveIDPlus1 or SlaveDataNibbleCnt or Reset)
begin
if(Reset)
RegTotalFrmNibbleCnt = 0 ;
else
RegTotalFrmNibbleCnt = ((SlaveDataNibbleCnt + 8'd2 ) * LastSlaveIDPlus1) + 8'd4;
end
// register SoC when receiving the start command
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
else
if (TxStartFrm)
begin
if (DataSoC)
RegDataSoC <= 1'b1;
else
if (NumbSoC)
RegNumbSoC <= 1'b1;
else
if (DistSoC)
RegDistSoC <= 1'b1;
else
if (DelaySoC)
RegDelaySoC <= 1'b1;
else
if (DelayDistSoC)
RegDelayDistSoC <= 1'b1;
end
else
if (StateIdle)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= 1'b0;
else
TxUsedData <= |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= 1'b0;
else
begin
if(TxStartFrm)
TxDone <= 1'b0;
else
if(StartTxDone)
TxDone <= 1'b1;
end
end
// Transmit nibble
always @ (*)
begin
if(StateNumb | StateDelay)
MTxD_d[3:0] = 4'b0000;
else
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibbles
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateCrc)
MTxD_d[3:0] = {~Crc[4], ~Crc[5], ~Crc[6], ~Crc[7]}; // Crc
else
if(StatePreamble)
MTxD_d[3:0] = 4'b0101; // Preamble 6
else
if (StateFrmCrc)
MTxD_d[3:0] = {~FrmCrc[4], ~FrmCrc[5], ~FrmCrc[6], ~FrmCrc[7]};
else
if(StateSoC)
begin
if(RegDataSoC)
MTxD_d[3:0] = 4'b0111; // DataSoC 7
else
if(RegNumbSoC)
MTxD_d[3:0] = 4'b0110; // NumbSoC 6
else
if(RegDistSoC)
MTxD_d[3:0] = 4'b0100; // DistSoC 4
else
if(RegDelaySoC)
MTxD_d[3:0] = 4'b0011; // DelaySoC 3
else
if(RegDelayDistSoC)
MTxD_d[3:0] = 4'b0010; // DelayDistSoC 2
else
MTxD_d[3:0] = 4'b0000;
end
else
if(StateDist[0])
MTxD_d[3:0] = LastSlaveIDPlus1[3:0];
else
if(StateDist[1])
MTxD_d[3:0] = LastSlaveIDPlus1[7:4];
else
if(StateDelayDist[0])
MTxD_d[3:0] = AveSlaveDelay[3:0];
else
if(StateDelayDist[1])
MTxD_d[3:0] = AveSlaveDelay[7:4];
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= 1'b0;
else
MTxEn <= StatePreamble | StateSoC | StateNumb | (|StateDist) | StateDelay | (|StateDelayDist) |(|StateData) | StateCrc | StateFrmCrc ;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= 4'h0;
else
MTxD[3:0] <= MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= 1'b0;
else
MTxErr <= UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= 1'b0;
else
WillTransmit <= StatePreamble | StateSoC | StateNumb | (|StateDist) | StateDelay | (|StateDelayDist) | (|StateData) | StateCrc | StateFrmCrc;
end
assign PacketFinished_d = StartTxDone ;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= 1'b0;
PacketFinished_q <= 1'b0;
end
else
begin
PacketFinished <= PacketFinished_d;
PacketFinished_q <= PacketFinished;
end
end
// Connecting module Counters
fb_txcounters txcounters1 (.MTxClk(MTxClk), .Reset(Reset),
.StateIdle(StateIdle),.StatePreamble(StatePreamble), .StateSoC(StateSoC),
.StateNumb(StateNumb), .StateDist(StateDist), .StateDelay(StateDelay),
.StateDelayDist(StateDelayDist),
.StateData(StateData), .StateCrc(StateCrc), .StateFrmCrc(StateFrmCrc),
.StartData(StartData),
.TotalNibCnt(TotalNibCnt), .NibCnt(NibCnt), .CrcNibCnt(CrcNibCnt),
.CrcStateEnd(CrcStateEnd), .PreambleStateEnd(PreambleStateEnd),
.FrmCrcStateEnd(FrmCrcStateEnd), .TxRamAddr(TxRamAddr)
);
// Connecting module StateM
fb_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .NumbStateEnd(NumbStateEnd),.DistStateEnd(DistStateEnd),.DelayStateEnd(DelayStateEnd),
.TxStartFrm(TxStartFrm), .SlaveEndFrm(SlaveEndFrm), .TxEndFrm(TxEndFrm),
.RegNumbSoC(RegNumbSoC), .RegDataSoC(RegDataSoC), .RegDistSoC(RegDistSoC),
.RegDelaySoC(RegDelaySoC), .RegDelayDistSoC(RegDelayDistSoC),
.CrcStateEnd(CrcStateEnd),.PreambleStateEnd(PreambleStateEnd),
.TxUnderRun(TxUnderRun), .UnderRun(UnderRun), .StartTxDone(StartTxDone),
.StateIdle(StateIdle), .StatePreamble(StatePreamble),.StateSoC(StateSoC),
.StateNumb(StateNumb), .StateDist(StateDist), .StateDelayDist(StateDelayDist),
.StateDelay(StateDelay), .StateData(StateData), .StateCrc(StateCrc),
.StateFrmCrc(StateFrmCrc),
.StartData(StartData)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateCrc;
assign Data_Crc = MTxD_d;
assign Initialize_Crc = StateIdle | StateSoC | CrcStateEnd;
// Connecting module Crc
fb_crc slavecrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
wire Enable_FrmCrc;
wire [3:0] Data_FrmCrc;
wire Initialize_FrmCrc;
assign Enable_FrmCrc = ~StateFrmCrc;
assign Data_FrmCrc = MTxD_d;
assign Initialize_FrmCrc = StateIdle;
// Connecting module Crc
fb_crc framecrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_FrmCrc), .Enable(Enable_FrmCrc), .Initialize(Initialize_FrmCrc),
.Crc(FrmCrc), .CrcError(FrmCrcError)
);
endmodule
|
module Arria10_tb;
reg clk; // in
reg reset; // in
reg [6:0] addr; // in
wire [31:0] readdata; // out
reg [31:0] writedata; // in
wire io_rdata;
reg chipselect; // in
reg write; // in
reg read; // in
Top top0 (
.clock (clk),
.reset (reset),
.io_raddr (clk),
.io_wen (write),
.io_waddr (clk),
.io_rdata (io_rdata),
.io_S_AVALON_readdata (readdata),
.io_S_AVALON_address (addr),
.io_S_AVALON_chipselect (chipselect),
.io_S_AVALON_write (write),
.io_S_AVALON_read (read),
.io_S_AVALON_writedata (writedata)
);
initial
begin
$dumpfile("arria10_argInOuts.vcd");
$dumpvars(0, top0);
clk = 0;
chipselect = 1;
reset = 0;
write = 0;
addr = 0;
writedata = 0;
chipselect = 0;
write = 0;
read = 0;
#10
reset = 1;
#10
reset = 0;
#10 // argIn
addr = 10'h2;
writedata = 32'h4;
write = 1;
#10
write = 0;
#20
addr = 10'h0;
writedata = 32'h1;
write = 1;
#10
write = 0;
#490
// check results and status
// argouts
#10
addr = 10'h3;
read = 1;
#30
addr = 10'h1;
$finish;
end
always
#5 clk = !clk;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_scbuf_rptr0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_scbuf_rptr0 (/*AUTOARG*/
// Outputs
sctag_scbuf_fbrd_en_c3_buf, sctag_scbuf_fbrd_wl_c3_buf,
sctag_scbuf_fbwr_wen_r2_buf, sctag_scbuf_fbwr_wl_r2_buf,
sctag_scbuf_fbd_stdatasel_c3_buf, sctag_scbuf_stdecc_c3_buf,
sctag_scbuf_ev_dword_r0_buf, sctag_scbuf_evict_en_r0_buf,
sctag_scbuf_wbwr_wen_c6_buf, sctag_scbuf_wbwr_wl_c6_buf,
sctag_scbuf_wbrd_en_r0_buf, sctag_scbuf_wbrd_wl_r0_buf,
sctag_scbuf_rdma_wren_s2_buf, sctag_scbuf_rdma_wrwl_s2_buf,
sctag_scbuf_rdma_rden_r0_buf, sctag_scbuf_rdma_rdwl_r0_buf,
sctag_scbuf_ctag_en_c7_buf, sctag_scbuf_ctag_c7_buf,
sctag_scbuf_req_en_c7_buf, sctag_scbuf_word_c7_buf,
sctag_scbuf_word_vld_c7_buf, scbuf_sctag_ev_uerr_r5_buf,
scbuf_sctag_ev_cerr_r5_buf, scbuf_sctag_rdma_uerr_c10_buf,
scbuf_sctag_rdma_cerr_c10_buf,
// Inputs
sctag_scbuf_fbrd_en_c3, sctag_scbuf_fbrd_wl_c3,
sctag_scbuf_fbwr_wen_r2, sctag_scbuf_fbwr_wl_r2,
sctag_scbuf_fbd_stdatasel_c3, sctag_scbuf_stdecc_c3,
sctag_scbuf_ev_dword_r0, sctag_scbuf_evict_en_r0,
sctag_scbuf_wbwr_wen_c6, sctag_scbuf_wbwr_wl_c6,
sctag_scbuf_wbrd_en_r0, sctag_scbuf_wbrd_wl_r0,
sctag_scbuf_rdma_wren_s2, sctag_scbuf_rdma_wrwl_s2,
sctag_scbuf_rdma_rden_r0, sctag_scbuf_rdma_rdwl_r0,
sctag_scbuf_ctag_en_c7, sctag_scbuf_ctag_c7,
sctag_scbuf_req_en_c7, sctag_scbuf_word_c7,
sctag_scbuf_word_vld_c7, scbuf_sctag_ev_uerr_r5,
scbuf_sctag_ev_cerr_r5, scbuf_sctag_rdma_uerr_c10,
scbuf_sctag_rdma_cerr_c10
);
//////////////////////////////////////////////////////////////////////////////
input sctag_scbuf_fbrd_en_c3;
input [2:0] sctag_scbuf_fbrd_wl_c3 ;
input [15:0] sctag_scbuf_fbwr_wen_r2 ;
input [2:0] sctag_scbuf_fbwr_wl_r2 ;
input sctag_scbuf_fbd_stdatasel_c3;
input [77:0] sctag_scbuf_stdecc_c3;
input [2:0] sctag_scbuf_ev_dword_r0;
input sctag_scbuf_evict_en_r0;
input [3:0] sctag_scbuf_wbwr_wen_c6;
input [2:0] sctag_scbuf_wbwr_wl_c6;
input sctag_scbuf_wbrd_en_r0;
input [2:0] sctag_scbuf_wbrd_wl_r0;
input [15:0] sctag_scbuf_rdma_wren_s2;
input [1:0] sctag_scbuf_rdma_wrwl_s2;
input sctag_scbuf_rdma_rden_r0;
input [1:0] sctag_scbuf_rdma_rdwl_r0;
input sctag_scbuf_ctag_en_c7;
input [14:0] sctag_scbuf_ctag_c7;
input sctag_scbuf_req_en_c7;
input [3:0] sctag_scbuf_word_c7;
input sctag_scbuf_word_vld_c7;
output sctag_scbuf_fbrd_en_c3_buf;
output [2:0] sctag_scbuf_fbrd_wl_c3_buf;
output [15:0] sctag_scbuf_fbwr_wen_r2_buf;
output [2:0] sctag_scbuf_fbwr_wl_r2_buf;
output sctag_scbuf_fbd_stdatasel_c3_buf;
output [77:0] sctag_scbuf_stdecc_c3_buf;
output [2:0] sctag_scbuf_ev_dword_r0_buf;
output sctag_scbuf_evict_en_r0_buf;
output [3:0] sctag_scbuf_wbwr_wen_c6_buf;
output [2:0] sctag_scbuf_wbwr_wl_c6_buf;
output sctag_scbuf_wbrd_en_r0_buf;
output [2:0] sctag_scbuf_wbrd_wl_r0_buf;
output [15:0] sctag_scbuf_rdma_wren_s2_buf;
output [1:0] sctag_scbuf_rdma_wrwl_s2_buf;
output sctag_scbuf_rdma_rden_r0_buf;
output [1:0] sctag_scbuf_rdma_rdwl_r0_buf;
output sctag_scbuf_ctag_en_c7_buf;
output [14:0] sctag_scbuf_ctag_c7_buf;
output sctag_scbuf_req_en_c7_buf;
output [3:0] sctag_scbuf_word_c7_buf;
output sctag_scbuf_word_vld_c7_buf;
input scbuf_sctag_ev_uerr_r5;
input scbuf_sctag_ev_cerr_r5;
input scbuf_sctag_rdma_uerr_c10;
input scbuf_sctag_rdma_cerr_c10;
output scbuf_sctag_ev_uerr_r5_buf;
output scbuf_sctag_ev_cerr_r5_buf;
output scbuf_sctag_rdma_uerr_c10_buf;
output scbuf_sctag_rdma_cerr_c10_buf;
//////////////////////////////////////////////////////////////////////////////
wire sctag_scbuf_fbrd_en_c3_buf;
wire [2:0] sctag_scbuf_fbrd_wl_c3_buf;
wire [15:0] sctag_scbuf_fbwr_wen_r2_buf;
wire [2:0] sctag_scbuf_fbwr_wl_r2_buf;
wire sctag_scbuf_fbd_stdatasel_c3_buf;
wire [77:0] sctag_scbuf_stdecc_c3_buf;
wire [2:0] sctag_scbuf_ev_dword_r0_buf;
wire sctag_scbuf_evict_en_r0_buf;
wire [3:0] sctag_scbuf_wbwr_wen_c6_buf;
wire [2:0] sctag_scbuf_wbwr_wl_c6_buf;
wire sctag_scbuf_wbrd_en_r0_buf;
wire [2:0] sctag_scbuf_wbrd_wl_r0_buf;
wire [15:0] sctag_scbuf_rdma_wren_s2_buf;
wire [1:0] sctag_scbuf_rdma_wrwl_s2_buf;
wire sctag_scbuf_rdma_rden_r0_buf;
wire [1:0] sctag_scbuf_rdma_rdwl_r0_buf;
wire sctag_scbuf_ctag_en_c7_buf;
wire [14:0] sctag_scbuf_ctag_c7_buf;
wire sctag_scbuf_req_en_c7_buf;
wire [3:0] sctag_scbuf_word_c7_buf;
wire sctag_scbuf_word_vld_c7_buf;
wire scbuf_sctag_ev_uerr_r5_buf;
wire scbuf_sctag_ev_cerr_r5_buf;
wire scbuf_sctag_rdma_uerr_c10_buf;
wire scbuf_sctag_rdma_cerr_c10_buf;
//////////////////////////////////////////////////////////////////////////////
assign sctag_scbuf_fbrd_en_c3_buf = sctag_scbuf_fbrd_en_c3;
assign sctag_scbuf_fbrd_wl_c3_buf = sctag_scbuf_fbrd_wl_c3;
assign sctag_scbuf_fbwr_wen_r2_buf = sctag_scbuf_fbwr_wen_r2;
assign sctag_scbuf_fbwr_wl_r2_buf = sctag_scbuf_fbwr_wl_r2;
assign sctag_scbuf_fbd_stdatasel_c3_buf = sctag_scbuf_fbd_stdatasel_c3;
assign sctag_scbuf_stdecc_c3_buf = sctag_scbuf_stdecc_c3;
assign sctag_scbuf_ev_dword_r0_buf = sctag_scbuf_ev_dword_r0;
assign sctag_scbuf_evict_en_r0_buf = sctag_scbuf_evict_en_r0;
assign sctag_scbuf_wbwr_wen_c6_buf = sctag_scbuf_wbwr_wen_c6;
assign sctag_scbuf_wbwr_wl_c6_buf = sctag_scbuf_wbwr_wl_c6;
assign sctag_scbuf_wbrd_en_r0_buf = sctag_scbuf_wbrd_en_r0;
assign sctag_scbuf_wbrd_wl_r0_buf = sctag_scbuf_wbrd_wl_r0;
assign sctag_scbuf_rdma_wren_s2_buf = sctag_scbuf_rdma_wren_s2;
assign sctag_scbuf_rdma_wrwl_s2_buf = sctag_scbuf_rdma_wrwl_s2;
assign sctag_scbuf_rdma_rden_r0_buf = sctag_scbuf_rdma_rden_r0;
assign sctag_scbuf_rdma_rdwl_r0_buf = sctag_scbuf_rdma_rdwl_r0;
assign sctag_scbuf_ctag_en_c7_buf = sctag_scbuf_ctag_en_c7;
assign sctag_scbuf_ctag_c7_buf = sctag_scbuf_ctag_c7;
assign sctag_scbuf_req_en_c7_buf = sctag_scbuf_req_en_c7;
assign sctag_scbuf_word_c7_buf = sctag_scbuf_word_c7;
assign sctag_scbuf_word_vld_c7_buf = sctag_scbuf_word_vld_c7;
assign scbuf_sctag_ev_uerr_r5_buf = scbuf_sctag_ev_uerr_r5;
assign scbuf_sctag_ev_cerr_r5_buf = scbuf_sctag_ev_cerr_r5;
assign scbuf_sctag_rdma_uerr_c10_buf = scbuf_sctag_rdma_uerr_c10;
assign scbuf_sctag_rdma_cerr_c10_buf = scbuf_sctag_rdma_cerr_c10;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A21BOI_BEHAVIORAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_BEHAVIORAL_V |
/*
* cpu.v
* The Brainfuck Processor
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read);
// Width of instruction addresses (affects size of ROM)
parameter IADDR_WIDTH = 8;
// Width of data addresses (affects size of RAM area)
parameter DADDR_WIDTH = 15;
// Width of stack addresses (affects size of loop stack)
parameter SADDR_WIDTH = 5;
// Width of data entries
parameter DATA_WIDTH = 8;
// True to initialize RAM for simulations
parameter INIT_RAM = 0;
// Inputs and outputs
output reg [DATA_WIDTH - 1:0] data_out; // Output data bus
output reg data_out_en; // If high, output was written on last cycle
output reg data_read; // If high, input was read on last cycle
input clk; // Clock
input [DATA_WIDTH - 1:0] data_in; // Input data bus
input data_available; // Data available on the input bus
// Internal Registers
reg [IADDR_WIDTH - 1:0] pc; // Program counter
reg [DADDR_WIDTH - 1:0] dp; // Data pointer
reg [SADDR_WIDTH - 1:0] lsc; // Loop skip counter
/*
* The loop skip counter is used for skipping entire loops
* when *DP == 0 when entering them. During normal operation
* the counter equals 0. When entering a loop which should be
* skipped, the counter is set to 1 and is used to detect nested
* loops and when the program should resume.
* When loop_skip_count != 0, normal instructions are not executed.
*/
// Internal Signals (wires driven by block memories)
wire [3:0] ci; // Current instruction
wire [DATA_WIDTH - 1:0] data_from_ram; // Data at dp from RAM
reg [DATA_WIDTH - 1:0] data_to_ram; // Data to write into RAM at dp
reg ram_write; // Write enable on RAM
wire [IADDR_WIDTH - 1:0] stack_top; // Address on top of the loop stack
reg [IADDR_WIDTH - 1:0] stack_data; // Data to push onto the stack
reg stack_push; // High to push onto the stack
reg stack_pop; // High to pop off the stack
reg [IADDR_WIDTH - 1:0] next_pc; // Next value of the program counter
reg [DADDR_WIDTH - 1:0] next_dp; // Next value of the data pointer
reg [SADDR_WIDTH - 1:0] next_lsc; // Next value of the loop skip counter
// Block memory instances
instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (
.address(pc),
.data_out(ci)
);
data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (
.data_out(data_from_ram),
.clk(clk),
.address(next_dp),
.data_in(data_to_ram),
.write(ram_write)
);
stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (
.top(stack_top),
.clk(clk),
.pushd(stack_data),
.push_en(stack_push),
.pop_en(stack_pop)
);
// Register initialization
initial
begin
pc = 0;
dp = 0;
lsc = 0;
end
// Combinational part
always @(*)
begin
// Default signal states
data_out = 32'bX;
data_out_en = 0;
data_read = 0;
data_to_ram = 32'bX;
ram_write = 0;
stack_data = 32'bX;
stack_push = 0;
stack_pop = 0;
next_dp = dp;
next_pc = pc + 1'b1;
next_lsc = lsc;
// Different handling depending on lsc
if (lsc == 0)
begin
// Handle each opcode
case (ci)
4'h0:
begin
// Halt - set pc to itself so we just loop on this instruction
next_pc = pc;
end
4'h8:
begin
// Increment DP
next_dp = dp + 1'b1;
end
4'h9:
begin
// Decrement DP
next_dp = dp - 1'b1;
end
4'hA:
begin
// Increment *DP
data_to_ram = data_from_ram + 1'b1;
ram_write = 1;
end
4'hB:
begin
// Decrement *DP
data_to_ram = data_from_ram - 1'b1;
ram_write = 1;
end
4'hC:
begin
// Start loop - either skip entire loop or push into it
if (data_from_ram == 0)
begin
// Skip entire loop
next_lsc = 1;
end
else
begin
// Start loop - push PC + 1 onto the stack
stack_data = next_pc;
stack_push = 1;
end
end
4'hD:
begin
// End of loop - either exit the loop or loop around
if (data_from_ram == 0)
stack_pop = 1;
else
next_pc = stack_top;
end
4'hE:
begin
// Output 1 byte
data_out = data_from_ram;
data_out_en = 1;
end
4'hF:
begin
// Input 1 byte
if (data_available)
begin
// Read this byte into memory and signal that it was read
data_to_ram = data_in;
ram_write = 1;
data_read = 1;
end
else
begin
// Busy wait here until we can read (this is like the halt instruction)
next_pc = pc;
end
end
// Default - no op
endcase
end
else
begin
// Special loop skip counter handling
case (ci)
4'hC:
begin
// Increment lsc
next_lsc = lsc + 1'b1;
end
4'hD:
begin
// Decrement lsc
next_lsc = lsc - 1'b1;
end
endcase
end
end
// Synchronous (register update) part
always @(posedge clk)
begin
// Update registers
pc <= next_pc;
dp <= next_dp;
lsc <= next_lsc;
end
endmodule
|
`define Alu_NOP 4'h0
`define Alu_LDI 4'h1
`define Alu_ADD 4'h2
`define Alu_SUB 4'h3
`define Alu_NOT 4'h4
`define Alu_AND 4'h5
`define Alu_IOR 4'h6
`define Alu_XOR 4'h7
`define Alu_SHL 4'h8
`define Alu_SHR 4'h9
`define Alu_EQL 4'hA
`define Alu_NEQ 4'hB
`define Alu_LTS 4'hC
`define Alu_LTE 4'hD
`define Alu_GTS 4'hE
`define Alu_GTE 4'hF
`define Alu_State_Reset 2'h0
`define Alu_State_Ready 2'h1
`define Alu_State_Error 2'h2
module Alu(clock,reset,inst,inst_en,result);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [7:0] result;
reg [1:0] s_State;
reg [7:0] s_Accum;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign result = s_Accum;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
always @ (posedge clock) begin
if (reset) begin
s_State <= `Alu_State_Reset;
s_Accum <= 0;
end
else begin
case (s_State)
`Alu_State_Reset: begin
s_State <= `Alu_State_Ready;
s_Accum <= 0;
end
`Alu_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Alu_NOP: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum;
end
`Alu_LDI: begin
s_State <= `Alu_State_Ready;
s_Accum <= w_InstImm;
end
`Alu_ADD: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum + w_InstImm;
end
`Alu_SUB: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum - w_InstImm;
end
`Alu_NOT: begin
s_State <= `Alu_State_Ready;
s_Accum <= ~s_Accum;
end
`Alu_AND: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum & w_InstImm;
end
`Alu_IOR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum | w_InstImm;
end
`Alu_XOR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum ^ w_InstImm;
end
`Alu_SHL: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum << 1;
end
`Alu_SHR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum >> 1;
end
`Alu_EQL: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum == w_InstImm;
end
`Alu_NEQ: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum != w_InstImm;
end
`Alu_LTS: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum < w_InstImm;
end
`Alu_LTE: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum <= w_InstImm;
end
`Alu_GTS: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum > w_InstImm;
end
`Alu_GTE: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum >= w_InstImm;
end
default: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum;
end // else: !if(inst_en)
end // case: `Alu_State_Ready
`Alu_State_Error: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
default: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Alu_NOP: begin
$sformat(d_Input,"EN NOP");
end
`Alu_LDI: begin
$sformat(d_Input,"EN (LDI %2X)",w_InstImm);
end
`Alu_ADD: begin
$sformat(d_Input,"EN (ADD %2X)",w_InstImm);
end
`Alu_SUB: begin
$sformat(d_Input,"EN (SUB %2X)",w_InstImm);
end
`Alu_NOT: begin
$sformat(d_Input,"EN NOT");
end
`Alu_AND: begin
$sformat(d_Input,"EN (AND %2X)",w_InstImm);
end
`Alu_IOR: begin
$sformat(d_Input,"EN (IOR %2X)",w_InstImm);
end
`Alu_XOR: begin
$sformat(d_Input,"EN (XOR %2X)",w_InstImm);
end
`Alu_SHL: begin
$sformat(d_Input,"EN SHL");
end
`Alu_SHR: begin
$sformat(d_Input,"EN SHR");
end
`Alu_EQL: begin
$sformat(d_Input,"EN (EQL %2X)",w_InstImm);
end
`Alu_NEQ: begin
$sformat(d_Input,"EN (NEQ %2X)",w_InstImm);
end
`Alu_LTS: begin
$sformat(d_Input,"EN (LTS %2X)",w_InstImm);
end
`Alu_LTE: begin
$sformat(d_Input,"EN (LTE %2X)",w_InstImm);
end
`Alu_GTS: begin
$sformat(d_Input,"EN (GTS %2X)",w_InstImm);
end
`Alu_GTE: begin
$sformat(d_Input,"EN (GTE %2X)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Alu_State_Reset: begin
$sformat(d_State,"X");
end
`Alu_State_Ready: begin
$sformat(d_State,"R %2X",s_Accum);
end
`Alu_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // Alu
|
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module out_arbiter
(// --- data path interface
output [63:0] out_data,
output [7:0] out_ctrl,
output reg out_wr,
input out_rdy,
input [63:0] in_data0,
input in_wr0,
input in_req0,
output in_ack0,
input in_bop0,
input in_eop0,
output in_outrdy0,
input [63:0] in_data1,
input in_wr1,
input in_req1,
output in_ack1,
input in_bop1,
input in_eop1,
output in_outrdy1,
input [63:0] in_data2,
input in_wr2,
input in_req2,
output in_ack2,
input in_bop2,
input in_eop2,
output in_outrdy2,
input [63:0] in_data3,
input in_wr3,
input in_req3,
output in_ack3,
input in_bop3,
input in_eop3,
output in_outrdy3,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
reg [3:0] in_ack;
assign in_ack0 = in_ack[0];
assign in_ack1 = in_ack[1];
assign in_ack2 = in_ack[2];
assign in_ack3 = in_ack[3];
wire [3:0] in_req;
assign in_req[0] = in_req0;
assign in_req[1] = in_req1;
assign in_req[2] = in_req2;
assign in_req[3] = in_req3;
wire [3:0] in_wr;
assign in_wr[0] = in_wr0;
assign in_wr[1] = in_wr1;
assign in_wr[2] = in_wr2;
assign in_wr[3] = in_wr3;
wire [63:0] in_data[3:0];
assign in_data[0] = in_data0;
assign in_data[1] = in_data1;
assign in_data[2] = in_data2;
assign in_data[3] = in_data3;
wire [3:0] in_bop;
assign in_bop[0] = in_bop0;
assign in_bop[1] = in_bop1;
assign in_bop[2] = in_bop2;
assign in_bop[3] = in_bop3;
wire [3:0] in_eop;
assign in_eop[0] = in_eop0;
assign in_eop[1] = in_eop1;
assign in_eop[2] = in_eop2;
assign in_eop[3] = in_eop3;
//reg [1:0] in_outrdy;
//assign in_outrdy0 = in_outrdy[0];
//assign in_outrdy1 = in_outrdy[1];
assign in_outrdy0 = out_rdy;
assign in_outrdy1 = out_rdy;
assign in_outrdy2 = out_rdy;
assign in_outrdy3 = out_rdy;
reg[1:0] curr_input;
reg[1:0] curr_input_next;
wire[1:0] curr_input_plus_1;
assign curr_input_plus_1 = (curr_input == 2'b11) ? 0 : curr_input + 1;
//assign curr_input_plus_1 = (curr_input == 2'b00) ? 0 : curr_input + 1;
parameter OA_STATE_IDLE = 1'b0,
OA_STATE_TX = 1'b1;
reg oa_state;
reg oa_state_next;
always @(*) begin
in_ack = 0;
curr_input_next = curr_input;
oa_state_next = oa_state;
case(oa_state)
OA_STATE_IDLE: begin
if(in_req[curr_input]) begin
oa_state_next = OA_STATE_TX;
end else begin
curr_input_next = curr_input_plus_1;
end
end
OA_STATE_TX: begin
if(in_req[curr_input]) begin
in_ack[curr_input] = 1;
end else begin
oa_state_next = OA_STATE_IDLE;
curr_input_next = curr_input_plus_1;
end
end
default: begin
oa_state_next = OA_STATE_IDLE;
end
endcase
end
wire [63:0] fifo_in_data;
wire [7:0] fifo_in_ctrl;
wire [7:0] fifo_in_ctrl0;
wire [7:0] fifo_in_ctrl1;
wire [7:0] fifo_in_ctrl2;
wire [7:0] fifo_in_ctrl3;
wire fifo_prog_full;
wire fifo_empty;
wire fifo_wr;
wire fifo_rd;
always @(posedge clk) begin
if(reset) begin
oa_state <= 0;
curr_input <= 2'b00;
end else begin
oa_state <= oa_state_next;
curr_input <= curr_input_next;
out_wr <= fifo_rd;
end
end
assign fifo_in_data = (curr_input == 2'b00) ? in_data0 : (curr_input == 2'b01) ? in_data1 : (curr_input == 2'b10) ? in_data2 : in_data3;
assign fifo_in_ctrl0 = (in_bop0) ? 8'b11111111 : (in_eop0) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl1 = (in_bop1) ? 8'b11111111 : (in_eop1) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl2 = (in_bop2) ? 8'b11111111 : (in_eop2) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl3 = (in_bop3) ? 8'b11111111 : (in_eop3) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl = (curr_input == 2'b00) ? fifo_in_ctrl0 : (curr_input == 2'b01) ? fifo_in_ctrl1 :(curr_input == 2'b10) ? fifo_in_ctrl2 : fifo_in_ctrl3;
assign fifo_wr = (curr_input == 2'b00) ? in_wr0 : (curr_input == 2'b01) ? in_wr1 :(curr_input == 2'b10) ? in_wr2: in_wr3;
assign fifo_rd = (fifo_empty == 1) ? 0 : out_rdy;
small_fifo_test_72 input_fifo(
.data ({fifo_in_ctrl, fifo_in_data}), // Data in
.wrreq (fifo_wr), // Write enable
.rdreq (fifo_rd), // Read the next word
.q ({out_ctrl, out_data}),
.full (),
.empty (fifo_empty),
.sclr (reset),
.clock (clk),
.usedw ()
);
//assign out_wr = (out_rdy == 0) ? 0 : (fifo_empty == 1) ? 0 : 1;
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_single cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = out_data;
assign TRIG0[71:64] = out_ctrl;
assign TRIG0[80] = out_wr;
assign TRIG0[81] = out_rdy;
assign TRIG0[163:100] = in_data0;
assign TRIG0[170] = in_wr0;
assign TRIG0[171] = in_req0;
assign TRIG0[172] = in_ack0;
assign TRIG0[173] = in_bop0;
assign TRIG0[174] = in_eop0;
assign TRIG0[175] = in_outrdy0;
assign TRIG0[180] = oa_state;
assign TRIG0[181] = curr_input;
assign TRIG0[182] = fifo_empty;
assign TRIG0[183] = fifo_wr;
assign TRIG0[184] = fifo_rd;
assign TRIG0[207:200] = fifo_in_ctrl;
*/
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:06:19 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_A, FSM_selector_C, FSM_selector_B_1_,
exp_oper_result_8_, Exp_module_Overflow_flag_A, n168, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n202, n203, n204, n205,
n206, n208, n222, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n238, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296,
n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
n308, n309, n310, n311, n312, n313, n314, n316, n317, n318, n319,
n321, n323, n324, n325, n327, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n348, n349, n350, n352,
n353, n354, n355, n356, n357, n358, n360, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376,
n377, n378, n380, n381, mult_x_19_n1805, mult_x_19_n1801,
mult_x_19_n1800, mult_x_19_n1797, mult_x_19_n1791, mult_x_19_n1777,
mult_x_19_n1775, mult_x_19_n1773, mult_x_19_n1753, mult_x_19_n1751,
mult_x_19_n1749, mult_x_19_n1697, mult_x_19_n1687, mult_x_19_n1678,
mult_x_19_n1677, mult_x_19_n1676, mult_x_19_n1674, mult_x_19_n1656,
mult_x_19_n1635, mult_x_19_n1617, mult_x_19_n1610, mult_x_19_n1603,
mult_x_19_n1587, mult_x_19_n1585, mult_x_19_n1556, mult_x_19_n1552,
mult_x_19_n1542, mult_x_19_n1010, mult_x_19_n995, mult_x_19_n994,
mult_x_19_n977, mult_x_19_n976, mult_x_19_n960, mult_x_19_n959,
mult_x_19_n958, mult_x_19_n943, mult_x_19_n941, mult_x_19_n940,
mult_x_19_n923, mult_x_19_n921, mult_x_19_n897, mult_x_19_n896,
mult_x_19_n875, mult_x_19_n874, mult_x_19_n853, mult_x_19_n852,
mult_x_19_n851, mult_x_19_n832, mult_x_19_n830, mult_x_19_n829,
mult_x_19_n810, mult_x_19_n808, mult_x_19_n807, mult_x_19_n788,
mult_x_19_n786, mult_x_19_n764, mult_x_19_n763, mult_x_19_n744,
mult_x_19_n743, mult_x_19_n726, mult_x_19_n725, mult_x_19_n723,
mult_x_19_n708, mult_x_19_n707, mult_x_19_n692, mult_x_19_n691,
mult_x_19_n689, mult_x_19_n676, mult_x_19_n675, mult_x_19_n662,
mult_x_19_n661, mult_x_19_n651, mult_x_19_n649, mult_x_19_n648,
mult_x_19_n647, mult_x_19_n639, mult_x_19_n638, mult_x_19_n637,
mult_x_19_n633, mult_x_19_n626, mult_x_19_n614, mult_x_19_n613,
mult_x_19_n611, mult_x_19_n604, mult_x_19_n593, mult_x_19_n579,
mult_x_19_n555, mult_x_19_n525, mult_x_19_n524, mult_x_19_n480,
mult_x_19_n474, mult_x_19_n471, mult_x_19_n466, mult_x_19_n465,
mult_x_19_n459, mult_x_19_n458, mult_x_19_n453, mult_x_19_n451,
mult_x_19_n439, mult_x_19_n430, mult_x_19_n424, mult_x_19_n423,
mult_x_19_n421, mult_x_19_n418, mult_x_19_n267, mult_x_19_n211,
mult_x_19_n198, mult_x_19_n197, mult_x_19_n181, mult_x_19_n179,
mult_x_19_n166, mult_x_19_n165, mult_x_19_n146, mult_x_19_n145,
mult_x_19_n135, mult_x_19_n115, mult_x_19_n114, mult_x_19_n113,
mult_x_19_n112, mult_x_19_n111, mult_x_19_n110, mult_x_19_n109,
mult_x_19_n108, mult_x_19_n82, mult_x_19_n58, mult_x_19_n52,
mult_x_19_n49, mult_x_19_n43, mult_x_19_n28, mult_x_19_n19,
mult_x_19_n7, mult_x_19_n4, n397, n398, n399, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n815, n816, n817,
n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828,
n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2878, n2879, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3360, n3361;
wire [6:0] P_Sgf;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [23:0] Add_result;
wire [20:0] Sgf_normalized_result;
wire [3:1] FS_Module_state_reg;
wire [9:7] Sgf_operation_Result;
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n3156), .Q(
FS_Module_state_reg[1]), .QN(n3139) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n3158), .Q(
FS_Module_state_reg[2]), .QN(n3119) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n3088), .Q(
FS_Module_state_reg[3]), .QN(n3120) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n3154), .Q(FSM_selector_A),
.QN(n3121) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n3155), .Q(Op_MX[25]), .QN(n3117) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n3285), .Q(Op_MX[24]), .QN(n997) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n3164),
.Q(Add_result[18]), .QN(n3125) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n3284),
.Q(Add_result[9]), .QN(n3133) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n788),
.Q(Add_result[8]), .QN(n3142) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n3165),
.Q(Add_result[7]), .QN(n3144) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n815),
.Q(Add_result[6]), .QN(n3143) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n3167),
.Q(Add_result[5]), .QN(n3145) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n3075),
.Q(Add_result[3]), .QN(n3146) );
DFFRX2TS R_510 ( .D(mult_x_19_n1775), .CK(clk), .RN(n3281), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n778), .Q(Op_MY[5]), .QN(n696) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n773), .Q(
FSM_selector_B_1_), .QN(n3118) );
DFFSX1TS R_2 ( .D(n3325), .CK(clk), .SN(n3161), .Q(n3272) );
DFFSX1TS R_5 ( .D(n3321), .CK(clk), .SN(n3161), .Q(n3271) );
DFFSX1TS R_8 ( .D(n3297), .CK(clk), .SN(n3158), .Q(n3270) );
DFFSX1TS R_11 ( .D(n3296), .CK(clk), .SN(n3161), .Q(n3269) );
DFFSX1TS R_12 ( .D(n3275), .CK(clk), .SN(n3159), .Q(n3268) );
DFFSX1TS R_15 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3266) );
DFFSX1TS R_17 ( .D(n3337), .CK(clk), .SN(n3159), .Q(n3265) );
DFFSX1TS R_20 ( .D(n3313), .CK(clk), .SN(n3080), .Q(n3264) );
DFFSX1TS R_23 ( .D(n3309), .CK(clk), .SN(n3162), .Q(n3263) );
DFFSX1TS R_26 ( .D(n3305), .CK(clk), .SN(n3161), .Q(n3262) );
DFFSX1TS R_29 ( .D(n3301), .CK(clk), .SN(n3158), .Q(n3261) );
DFFSX1TS R_30 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3260) );
DFFSX1TS R_33 ( .D(n3275), .CK(clk), .SN(n3086), .Q(n3258) );
DFFSX1TS R_35 ( .D(n3317), .CK(clk), .SN(n3162), .Q(n3257) );
DFFSX1TS R_36 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3256) );
DFFSX1TS R_38 ( .D(n3329), .CK(clk), .SN(n3160), .Q(n3255) );
DFFSX1TS R_44 ( .D(n3292), .CK(clk), .SN(n3161), .Q(n3252) );
DFFSX1TS R_47 ( .D(n3288), .CK(clk), .SN(n3360), .Q(n3251) );
DFFSX1TS R_50 ( .D(n3286), .CK(clk), .SN(n3360), .Q(n3250) );
DFFRXLTS R_52 ( .D(n258), .CK(clk), .RN(n3277), .Q(n3249) );
DFFSX1TS R_54 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3248) );
DFFRXLTS R_58 ( .D(n266), .CK(clk), .RN(n3159), .Q(n3246) );
DFFRXLTS R_95 ( .D(n265), .CK(clk), .RN(n3159), .Q(n3245) );
DFFRXLTS R_98 ( .D(n267), .CK(clk), .RN(n3159), .Q(n3244) );
DFFRXLTS R_101 ( .D(n264), .CK(clk), .RN(n3159), .Q(n3243) );
DFFRXLTS R_104 ( .D(n262), .CK(clk), .RN(n3162), .Q(n3242) );
DFFRXLTS R_107 ( .D(n261), .CK(clk), .RN(n3277), .Q(n3241) );
DFFRXLTS R_110 ( .D(n263), .CK(clk), .RN(n3159), .Q(n3240) );
DFFRXLTS R_113 ( .D(n260), .CK(clk), .RN(n3081), .Q(n3239) );
DFFRXLTS R_121 ( .D(n259), .CK(clk), .RN(n794), .Q(n3237) );
DFFRXLTS R_158 ( .D(n254), .CK(clk), .RN(n3157), .Q(n3236) );
DFFRXLTS R_237 ( .D(n256), .CK(clk), .RN(n3157), .Q(n3235) );
DFFRXLTS R_278 ( .D(n252), .CK(clk), .RN(n3157), .Q(n3234) );
DFFRXLTS R_299 ( .D(n255), .CK(clk), .RN(n3157), .Q(n3233) );
DFFRXLTS R_302 ( .D(n253), .CK(clk), .RN(n3157), .Q(n3232) );
DFFRXLTS R_118 ( .D(n257), .CK(clk), .RN(n3081), .Q(n3238) );
DFFSX4TS R_911 ( .D(n3353), .CK(clk), .SN(n3156), .Q(n3217) );
DFFSX4TS R_912 ( .D(n3354), .CK(clk), .SN(n3156), .Q(n3216) );
DFFSX4TS R_981 ( .D(n3348), .CK(clk), .SN(n815), .Q(n3188) );
DFFSX4TS R_1026 ( .D(n3355), .CK(clk), .SN(n3282), .Q(n3182) );
DFFSX4TS R_1039 ( .D(n3351), .CK(clk), .SN(n3154), .Q(n3180) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n3163),
.Q(Add_result[20]), .QN(n3123) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n773), .Q(final_result_ieee[31]), .QN(n3152) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n3282), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n788), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n778), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n778), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n817), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n815), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n3361), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n788), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n3361), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n788), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n788), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n788), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n3361), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n3361), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n788), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n3361), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n795), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n795), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n795), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n795), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n795), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n795), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n795), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n795), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n795), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n795), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n3278), .Q(final_result_ieee[30]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n3163),
.Q(Add_result[19]), .QN(n3124) );
DFFRXLTS R_437 ( .D(mult_x_19_n1773), .CK(clk), .RN(n3164), .Q(Op_MY[21]),
.QN(n3110) );
DFFRXLTS R_448 ( .D(mult_x_19_n579), .CK(clk), .RN(n3155), .Q(Op_MY[20]),
.QN(n3111) );
DFFRXLTS R_1037 ( .D(mult_x_19_n633), .CK(clk), .RN(n3281), .Q(Op_MY[14]),
.QN(n3109) );
DFFRXLTS R_913 ( .D(mult_x_19_n611), .CK(clk), .RN(n3281), .Q(Op_MY[16]),
.QN(n3150) );
DFFSX1TS R_866 ( .D(n3287), .CK(clk), .SN(n817), .Q(n3220) );
DFFRXLTS R_867 ( .D(n310), .CK(clk), .RN(n817), .Q(n3219) );
DFFSX2TS R_868 ( .D(n3273), .CK(clk), .SN(n817), .Q(n3218) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n3155), .Q(
Exp_module_Overflow_flag_A), .QN(n3151) );
DFFRXLTS R_545 ( .D(n364), .CK(clk), .RN(n771), .Q(Op_MX[20]), .QN(n409) );
DFFRX2TS R_483 ( .D(n357), .CK(clk), .RN(n815), .Q(Op_MX[13]) );
DFFRX2TS R_471 ( .D(n352), .CK(clk), .RN(n771), .Q(Op_MX[8]) );
DFFRX2TS R_321 ( .D(n354), .CK(clk), .RN(n773), .Q(Op_MX[10]) );
DFFRX2TS R_169 ( .D(mult_x_19_n19), .CK(clk), .RN(n3285), .Q(Op_MX[7]) );
DFFRX2TS R_377 ( .D(n350), .CK(clk), .RN(n772), .Q(Op_MX[6]) );
DFFRX2TS R_427 ( .D(n356), .CK(clk), .RN(n3166), .Q(Op_MX[12]) );
DFFRX2TS R_320 ( .D(n353), .CK(clk), .RN(n772), .Q(Op_MX[9]) );
DFFRX2TS R_199 ( .D(n365), .CK(clk), .RN(n3167), .Q(Op_MX[21]) );
DFFRX2TS R_200 ( .D(n366), .CK(clk), .RN(n816), .Q(Op_MX[22]) );
DFFRX2TS R_204 ( .D(n349), .CK(clk), .RN(n3285), .Q(Op_MX[5]) );
DFFSX1TS R_727 ( .D(Sgf_operation_Result[8]), .CK(clk), .SN(n3084), .Q(n3228) );
DFFSX1TS R_1067 ( .D(Sgf_operation_Result[7]), .CK(clk), .SN(n3161), .Q(
n3172) );
DFFRXLTS R_745 ( .D(n247), .CK(clk), .RN(n3160), .Q(n3224) );
DFFSX1TS R_852 ( .D(n3294), .CK(clk), .SN(n816), .Q(n3222) );
DFFSX1TS R_919 ( .D(n3307), .CK(clk), .SN(n3165), .Q(n3214) );
DFFSX1TS R_964 ( .D(n3331), .CK(clk), .SN(n3167), .Q(n3205) );
DFFSX1TS R_967 ( .D(n3315), .CK(clk), .SN(n3166), .Q(n3202) );
DFFSX1TS R_976 ( .D(n3335), .CK(clk), .SN(n3076), .Q(n3193) );
DFFSX1TS R_1071 ( .D(n3299), .CK(clk), .SN(n817), .Q(n3169) );
DFFSX2TS R_851 ( .D(n3295), .CK(clk), .SN(n816), .Q(n3223) );
DFFSX2TS R_918 ( .D(n3308), .CK(clk), .SN(n3283), .Q(n3215) );
DFFSX2TS R_963 ( .D(n3332), .CK(clk), .SN(n3167), .Q(n3206) );
DFFSX2TS R_966 ( .D(n3316), .CK(clk), .SN(n3167), .Q(n3203) );
DFFSX2TS R_975 ( .D(n3336), .CK(clk), .SN(n3163), .Q(n3194) );
DFFSX2TS R_1070 ( .D(n3300), .CK(clk), .SN(n816), .Q(n3170) );
DFFSX1TS R_853 ( .D(n3293), .CK(clk), .SN(n817), .Q(n3221) );
DFFSX1TS R_920 ( .D(n3306), .CK(clk), .SN(n3165), .Q(n3213) );
DFFSX1TS R_965 ( .D(n3330), .CK(clk), .SN(n3166), .Q(n3204) );
DFFSX1TS R_977 ( .D(n3334), .CK(clk), .SN(n3165), .Q(n3192) );
DFFSX1TS R_1072 ( .D(n3298), .CK(clk), .SN(n816), .Q(n3168) );
DFFSX1TS R_950 ( .D(n3327), .CK(clk), .SN(n3283), .Q(n3211) );
DFFSX1TS R_958 ( .D(n3303), .CK(clk), .SN(n3167), .Q(n3208) );
DFFSX1TS R_970 ( .D(n3323), .CK(clk), .SN(n3167), .Q(n3199) );
DFFSX1TS R_973 ( .D(n3319), .CK(clk), .SN(n3361), .Q(n3196) );
DFFSX1TS R_982 ( .D(n3347), .CK(clk), .SN(n778), .Q(n3187) );
DFFSX1TS R_992 ( .D(n3290), .CK(clk), .SN(n816), .Q(n3184) );
DFFSX1TS R_1061 ( .D(n3339), .CK(clk), .SN(n3165), .Q(n3174) );
DFFSX2TS R_949 ( .D(n3328), .CK(clk), .SN(n3075), .Q(n3212) );
DFFSX2TS R_957 ( .D(n3304), .CK(clk), .SN(n3166), .Q(n3209) );
DFFSX2TS R_969 ( .D(n3324), .CK(clk), .SN(n3166), .Q(n3200) );
DFFSX2TS R_972 ( .D(n3320), .CK(clk), .SN(n403), .Q(n3197) );
DFFSX2TS R_991 ( .D(n3291), .CK(clk), .SN(n817), .Q(n3185) );
DFFSX2TS R_1060 ( .D(n3340), .CK(clk), .SN(n3166), .Q(n3175) );
DFFSX1TS R_951 ( .D(n3326), .CK(clk), .SN(n3079), .Q(n3210) );
DFFSX1TS R_959 ( .D(n3302), .CK(clk), .SN(n3361), .Q(n3207) );
DFFSX1TS R_971 ( .D(n3322), .CK(clk), .SN(n3166), .Q(n3198) );
DFFSX1TS R_974 ( .D(n3318), .CK(clk), .SN(n3361), .Q(n3195) );
DFFSX1TS R_983 ( .D(n3346), .CK(clk), .SN(n817), .Q(n3186) );
DFFSX1TS R_993 ( .D(n3289), .CK(clk), .SN(n816), .Q(n3183) );
DFFSX1TS R_1062 ( .D(n3338), .CK(clk), .SN(n3165), .Q(n3173) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n3153), .Q(Sgf_normalized_result[3]), .QN(n3138) );
DFFSX1TS R_1048 ( .D(n3357), .CK(clk), .SN(n3164), .Q(n3177) );
DFFSX1TS mult_x_19_R_773 ( .D(mult_x_19_n976), .CK(clk), .SN(n3091), .Q(
n2975) );
DFFSX2TS mult_x_19_R_656 ( .D(mult_x_19_n692), .CK(clk), .SN(n3084), .Q(
n2964) );
DFFRX1TS mult_x_19_R_829 ( .D(mult_x_19_n763), .CK(clk), .RN(n794), .Q(n2988) );
DFFSX2TS mult_x_19_R_845 ( .D(mult_x_19_n763), .CK(clk), .SN(n3083), .Q(
n2995) );
DFFSX2TS mult_x_19_R_846 ( .D(mult_x_19_n744), .CK(clk), .SN(n3083), .Q(
n2996) );
DFFRX1TS mult_x_19_R_850 ( .D(mult_x_19_n725), .CK(clk), .RN(n794), .Q(n2997) );
DFFSX2TS mult_x_19_R_998 ( .D(mult_x_19_n661), .CK(clk), .SN(n3087), .Q(
n3034) );
DFFSX2TS mult_x_19_R_997 ( .D(mult_x_19_n648), .CK(clk), .SN(n3087), .Q(
n3033) );
DFFRX1TS mult_x_19_R_1077 ( .D(mult_x_19_n994), .CK(clk), .RN(n3091), .Q(
n3061) );
DFFSX1TS mult_x_19_R_1138 ( .D(mult_x_19_n480), .CK(clk), .SN(n3089), .Q(
n3072) );
DFFSX2TS mult_x_19_R_531 ( .D(n2925), .CK(clk), .SN(n2575), .Q(n2899) );
DFFRX1TS mult_x_19_R_960_RW_0 ( .D(mult_x_19_n267), .CK(clk), .RN(n3086),
.QN(n3100) );
DFFSX2TS mult_x_19_R_1136 ( .D(n3071), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1556) );
DFFSX2TS mult_x_19_R_478 ( .D(n2926), .CK(clk), .SN(n3078), .Q(n2888) );
DFFSX2TS mult_x_19_R_523 ( .D(n2942), .CK(clk), .SN(n3280), .Q(
mult_x_19_n1676) );
DFFSX2TS mult_x_19_R_1083 ( .D(n3063), .CK(clk), .SN(n815), .Q(
mult_x_19_n1656) );
DFFSX2TS mult_x_19_R_1058 ( .D(n3054), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1587) );
DFFSX2TS mult_x_19_R_1055 ( .D(n3053), .CK(clk), .SN(n3282), .Q(
mult_x_19_n1687) );
DFFRX4TS mult_x_19_R_1120 ( .D(n2913), .CK(clk), .RN(n3090), .QN(n3093) );
DFFSX1TS mult_x_19_R_1106 ( .D(n3067), .CK(clk), .SN(n3155), .Q(
mult_x_19_n1610) );
DFFRX4TS mult_x_19_R_1127 ( .D(n357), .CK(clk), .RN(n404), .Q(n2890), .QN(
n779) );
DFFSX1TS mult_x_19_R_1087 ( .D(n3064), .CK(clk), .SN(n3076), .Q(
mult_x_19_n1674) );
DFFRXLTS mult_x_19_R_870_RW_1 ( .D(mult_x_19_n958), .CK(clk), .RN(n2576),
.Q(n3004) );
DFFRX4TS mult_x_19_R_1118 ( .D(n3050), .CK(clk), .RN(n3079), .Q(n2905), .QN(
n3098) );
DFFRX4TS mult_x_19_R_1054 ( .D(mult_x_19_n19), .CK(clk), .RN(n402), .Q(n2898), .QN(n629) );
DFFSX1TS mult_x_19_R_1036 ( .D(n3049), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1751) );
DFFSX1TS mult_x_19_R_1033 ( .D(mult_x_19_n179), .CK(clk), .SN(n3085), .Q(
n3048) );
DFFSX1TS mult_x_19_R_1022 ( .D(n3045), .CK(clk), .SN(n3278), .Q(
mult_x_19_n1635) );
DFFSX1TS mult_x_19_R_1013 ( .D(mult_x_19_n198), .CK(clk), .SN(n3083), .Q(
n3044) );
DFFSX1TS mult_x_19_R_1012 ( .D(mult_x_19_n525), .CK(clk), .SN(n3083), .Q(
n3043) );
DFFSX1TS mult_x_19_R_722_RW_1 ( .D(mult_x_19_n421), .CK(clk), .SN(n3088),
.Q(n2970) );
DFFRX2TS mult_x_19_R_1000 ( .D(mult_x_19_n676), .CK(clk), .RN(n3086), .Q(
n3035) );
DFFSX4TS mult_x_19_R_988 ( .D(mult_x_19_n788), .CK(clk), .SN(n3086), .Q(
n3030) );
DFFRXLTS mult_x_19_R_986 ( .D(mult_x_19_n198), .CK(clk), .RN(n3086), .Q(
n3029) );
DFFRX4TS mult_x_19_R_961 ( .D(n312), .CK(clk), .RN(n3283), .Q(n2904), .QN(
n749) );
DFFSX1TS mult_x_19_R_948 ( .D(mult_x_19_n424), .CK(clk), .SN(n3091), .Q(
n3027) );
DFFSX2TS mult_x_19_R_947 ( .D(mult_x_19_n423), .CK(clk), .SN(n3087), .Q(
n3026) );
DFFRXLTS mult_x_19_R_943 ( .D(mult_x_19_n145), .CK(clk), .RN(n3082), .Q(
n3025) );
DFFRXLTS mult_x_19_R_842_RW_0 ( .D(mult_x_19_n897), .CK(clk), .RN(n3277),
.Q(n2994) );
DFFSX4TS mult_x_19_R_930 ( .D(mult_x_19_n940), .CK(clk), .SN(n3087), .Q(
n3021) );
DFFSX4TS mult_x_19_R_928 ( .D(n2934), .CK(clk), .SN(n3278), .Q(n2915), .QN(
n608) );
DFFRXLTS mult_x_19_R_927 ( .D(mult_x_19_n614), .CK(clk), .RN(n3082), .Q(
n3019) );
DFFSX4TS mult_x_19_R_925 ( .D(mult_x_19_n637), .CK(clk), .SN(n3082), .Q(
n3017) );
DFFRX4TS mult_x_19_R_926 ( .D(mult_x_19_n626), .CK(clk), .RN(n3082), .Q(
n3018) );
DFFSX1TS mult_x_19_R_909 ( .D(n3012), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1753) );
DFFRX4TS mult_x_19_R_910 ( .D(n345), .CK(clk), .RN(n3076), .Q(n2947), .QN(
n630) );
DFFSX4TS mult_x_19_R_897 ( .D(mult_x_19_n832), .CK(clk), .SN(n794), .Q(n3006) );
DFFSX1TS mult_x_19_R_703_RW_0 ( .D(mult_x_19_n146), .CK(clk), .SN(n3161),
.Q(n2968) );
DFFSX4TS mult_x_19_R_857 ( .D(mult_x_19_n651), .CK(clk), .SN(n3082), .Q(
n3000) );
DFFSX4TS mult_x_19_R_858 ( .D(mult_x_19_n649), .CK(clk), .SN(n3082), .Q(
n3001) );
DFFSX2TS mult_x_19_R_803 ( .D(n634), .CK(clk), .SN(n3089), .Q(n2981) );
DFFSX4TS mult_x_19_R_796 ( .D(n2927), .CK(clk), .SN(n3279), .Q(n2914), .QN(
n774) );
DFFSX1TS mult_x_19_R_788 ( .D(mult_x_19_n958), .CK(clk), .SN(n3091), .Q(
n2977) );
DFFSX1TS mult_x_19_R_776 ( .D(mult_x_19_n430), .CK(clk), .SN(n3089), .Q(
n2976) );
DFFSX1TS mult_x_19_R_770 ( .D(mult_x_19_n614), .CK(clk), .SN(n3081), .Q(
n2974) );
DFFSX1TS mult_x_19_R_767 ( .D(n462), .CK(clk), .SN(n3089), .Q(n2972) );
DFFSX2TS mult_x_19_R_758 ( .D(mult_x_19_n874), .CK(clk), .SN(n3085), .Q(
n2971) );
DFFSX1TS mult_x_19_R_702 ( .D(mult_x_19_n145), .CK(clk), .SN(n3091), .Q(
n2967) );
DFFSX4TS mult_x_19_R_666 ( .D(n2966), .CK(clk), .SN(n3284), .Q(mult_x_19_n52), .QN(n701) );
DFFSX2TS mult_x_19_R_662 ( .D(mult_x_19_n676), .CK(clk), .SN(n3081), .Q(
n2965) );
DFFRX4TS mult_x_19_R_1081 ( .D(n353), .CK(clk), .RN(n3075), .Q(n2895), .QN(
n3013) );
DFFSX4TS mult_x_19_R_637 ( .D(n2943), .CK(clk), .SN(n3278), .Q(n2894), .QN(
n705) );
DFFSX4TS mult_x_19_R_615 ( .D(n2961), .CK(clk), .SN(n3284), .Q(mult_x_19_n58), .QN(n561) );
DFFSX4TS mult_x_19_R_1130 ( .D(n2932), .CK(clk), .SN(n3078), .Q(n2885), .QN(
n797) );
DFFRX4TS mult_x_19_R_603 ( .D(n2960), .CK(clk), .RN(n3078), .Q(
mult_x_19_n1797) );
DFFRX4TS mult_x_19_R_1034 ( .D(n345), .CK(clk), .RN(n2575), .Q(n2948), .QN(
n702) );
DFFSX1TS mult_x_19_R_581 ( .D(mult_x_19_n108), .CK(clk), .SN(n3089), .Q(
n2956) );
DFFSX1TS mult_x_19_R_528 ( .D(n2944), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1585) );
DFFSX2TS mult_x_19_R_1078 ( .D(n2939), .CK(clk), .SN(n2575), .Q(n2889) );
DFFRX4TS mult_x_19_R_1105 ( .D(mult_x_19_n689), .CK(clk), .RN(n3282), .Q(
n2908), .QN(n2950) );
DFFSX4TS R_1163 ( .D(n2937), .CK(clk), .SN(n772), .Q(mult_x_19_n28) );
DFFSX1TS mult_x_19_R_455 ( .D(mult_x_19_n135), .CK(clk), .SN(n3091), .Q(
n2936) );
DFFRX4TS mult_x_19_R_537 ( .D(mult_x_19_n579), .CK(clk), .RN(n3281), .Q(
n2906), .QN(n3095) );
DFFSX2TS mult_x_19_R_607 ( .D(n2932), .CK(clk), .SN(n3078), .Q(n2884) );
DFFSX1TS mult_x_19_R_332 ( .D(n2928), .CK(clk), .SN(n3153), .Q(
mult_x_19_n1552) );
DFFSX4TS mult_x_19_R_1134 ( .D(n2929), .CK(clk), .SN(n3078), .Q(n2887) );
DFFSX2TS mult_x_19_R_335 ( .D(n2929), .CK(clk), .SN(n3153), .Q(n2886) );
DFFRX4TS R_1161 ( .D(mult_x_19_n593), .CK(clk), .RN(n3281), .Q(n2907), .QN(
n3066) );
DFFSX4TS mult_x_19_R_325 ( .D(n2923), .CK(clk), .SN(n3285), .Q(n2901), .QN(
n688) );
DFFSX4TS mult_x_19_R_1044 ( .D(n2922), .CK(clk), .SN(n3278), .Q(n2897) );
DFFSX2TS mult_x_19_R_207 ( .D(n2923), .CK(clk), .SN(n3074), .Q(n2900) );
DFFSX2TS mult_x_19_R_197 ( .D(n2922), .CK(clk), .SN(n2575), .Q(n2896) );
DFFSX1TS mult_x_19_R_151 ( .D(mult_x_19_n166), .CK(clk), .SN(n3083), .Q(
n2921) );
DFFSX1TS mult_x_19_R_75 ( .D(n2912), .CK(clk), .SN(n3091), .QN(n421) );
DFFSX1TS mult_x_19_R_69 ( .D(n2909), .CK(clk), .SN(n3085), .Q(n2917) );
DFFRXLTS mult_x_19_R_67 ( .D(mult_x_19_n82), .CK(clk), .RN(n3086), .Q(n2916)
);
DFFSX2TS R_980 ( .D(n3342), .CK(clk), .SN(n3167), .Q(n3189) );
DFFRX4TS mult_x_19_R_1064 ( .D(mult_x_19_n960), .CK(clk), .RN(n2576), .Q(
n3056) );
DFFSX2TS mult_x_19_R_838 ( .D(mult_x_19_n994), .CK(clk), .SN(n3091), .Q(
n2992) );
DFFRX2TS mult_x_19_R_830 ( .D(mult_x_19_n744), .CK(clk), .RN(n794), .Q(n2989) );
DFFSX2TS R_979 ( .D(n3343), .CK(clk), .SN(n3165), .Q(n3190) );
DFFSX4TS mult_x_19_R_859 ( .D(mult_x_19_n638), .CK(clk), .SN(n3082), .Q(
n3002) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n3283),
.QN(n3103) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n778),
.QN(n3104) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n3282),
.QN(n3113) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n3155),
.QN(n3114) );
DFFRX4TS mult_x_19_R_902 ( .D(mult_x_19_n829), .CK(clk), .RN(n2576), .Q(
n3010) );
DFFSX4TS mult_x_19_R_898 ( .D(mult_x_19_n853), .CK(clk), .SN(n794), .Q(n3007) );
DFFSX2TS mult_x_19_R_790 ( .D(mult_x_19_n725), .CK(clk), .SN(n3083), .Q(
n2978) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n3280), .Q(Op_MY[29]) );
DFFSX4TS mult_x_19_R_1074 ( .D(mult_x_19_n453), .CK(clk), .SN(n3087), .Q(
n3059) );
DFFRX2TS mult_x_19_R_863 ( .D(mult_x_19_n662), .CK(clk), .RN(n3086), .Q(
n3003) );
DFFRX2TS mult_x_19_R_990 ( .D(mult_x_19_n786), .CK(clk), .RN(n794), .Q(n3032) );
DFFSX4TS mult_x_19_R_924 ( .D(mult_x_19_n639), .CK(clk), .SN(n3082), .Q(
n3016) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n3285),
.Q(Add_result[2]), .QN(n3147) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n3154),
.Q(Add_result[0]) );
DFFRHQX1TS R_426 ( .D(n355), .CK(clk), .RN(n772), .Q(Op_MX[11]) );
DFFRHQX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n771), .Q(zero_flag) );
DFFRHQX1TS R_330 ( .D(mult_x_19_n49), .CK(clk), .RN(n772), .Q(Op_MX[17]) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n773),
.Q(Add_result[4]) );
DFFRHQX2TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n773),
.Q(n2878) );
DFFSX4TS mult_x_19_R_493 ( .D(n2931), .CK(clk), .SN(n771), .Q(n2903), .QN(
n2949) );
DFFRHQX4TS mult_x_19_R_520 ( .D(n2941), .CK(clk), .RN(n3285), .Q(
mult_x_19_n1801) );
DFFRHQX8TS mult_x_19_R_660_IP ( .D(n1001), .CK(clk), .RN(n773), .Q(n3102) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n3285), .Q(Add_result[10]) );
DFFRX4TS mult_x_19_R_635 ( .D(mult_x_19_n7), .CK(clk), .RN(n771), .Q(n2902),
.QN(n2951) );
DFFSX4TS mult_x_19_R_1046 ( .D(n2924), .CK(clk), .SN(n773), .QN(n2946) );
DFFSX1TS R_744 ( .D(Sgf_operation_Result[9]), .CK(clk), .SN(n3276), .Q(n3225) );
DFFRX2TS mult_x_19_R_873 ( .D(mult_x_19_n976), .CK(clk), .RN(n3276), .Q(
n3005) );
DFFRX4TS mult_x_19_R_935 ( .D(n3023), .CK(clk), .RN(n3076), .Q(
mult_x_19_n1800) );
DFFRX4TS mult_x_19_R_636 ( .D(n2963), .CK(clk), .RN(n2575), .Q(
mult_x_19_n1805) );
DFFSX4TS mult_x_19_R_929 ( .D(mult_x_19_n923), .CK(clk), .SN(n3162), .Q(
n3020) );
DFFSX4TS mult_x_19_R_1063 ( .D(mult_x_19_n943), .CK(clk), .SN(n3161), .Q(
n3055) );
DFFSX4TS mult_x_19_R_931 ( .D(mult_x_19_n921), .CK(clk), .SN(n3162), .Q(
n3022) );
DFFRX4TS mult_x_19_R_1065 ( .D(mult_x_19_n941), .CK(clk), .RN(n2576), .Q(
n3057) );
DFFSX4TS mult_x_19_R_1073 ( .D(n3101), .CK(clk), .SN(n3087), .Q(n3058) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n815), .Q(Sgf_normalized_result[20]), .QN(n3141) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n815), .Q(FSM_selector_C),
.QN(n998) );
DFFRX1TS mult_x_19_R_917 ( .D(mult_x_19_n466), .CK(clk), .RN(n3090), .Q(
n3015) );
DFFRX4TS R_338 ( .D(n345), .CK(clk), .RN(n3163), .Q(Op_MX[1]) );
DFFSX2TS R_32 ( .D(n3341), .CK(clk), .SN(n3160), .Q(n3259) );
DFFSX2TS mult_x_19_R_814 ( .D(n3094), .CK(clk), .SN(n3081), .Q(n2983) );
DFFRX1TS R_434 ( .D(n346), .CK(clk), .RN(n3163), .Q(Op_MX[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n3163),
.Q(Add_result[22]), .QN(n3122) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n3163),
.Q(Add_result[21]), .QN(n3134) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_1_ ( .D(n3140), .CK(clk), .RN(n3080),
.Q(P_Sgf[1]) );
DFFRX1TS R_209 ( .D(mult_x_19_n43), .CK(clk), .RN(n3166), .Q(Op_MX[15]) );
DFFRX1TS R_665 ( .D(n360), .CK(clk), .RN(n3165), .Q(Op_MX[16]) );
DFFRX1TS R_344 ( .D(n363), .CK(clk), .RN(n3075), .Q(Op_MX[19]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n816),
.Q(exp_oper_result_8_), .QN(n3106) );
DFFRX4TS R_195 ( .D(mult_x_19_n7), .CK(clk), .RN(n3164), .Q(Op_MX[3]) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(n3276),
.Q(P_Sgf[2]) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(n3276),
.Q(P_Sgf[3]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n778), .Q(final_result_ieee[0]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n3164), .Q(Op_MX[23]), .QN(n3136) );
DFFSX2TS mult_x_19_R_1025 ( .D(n3046), .CK(clk), .SN(n3280), .Q(n2891), .QN(
n775) );
DFFSX2TS mult_x_19_R_833 ( .D(mult_x_19_n743), .CK(clk), .SN(n3091), .Q(
n2990) );
DFFRHQX4TS mult_x_19_R_1023 ( .D(n355), .CK(clk), .RN(n405), .Q(n758) );
DFFRHQX8TS mult_x_19_R_1035 ( .D(mult_x_19_n1775), .CK(clk), .RN(n3281), .Q(
n755) );
DFFRHQX8TS mult_x_19_R_914 ( .D(mult_x_19_n611), .CK(clk), .RN(n3279), .Q(
n754) );
DFFRHQX8TS mult_x_19_R_1137 ( .D(mult_x_19_n49), .CK(clk), .RN(n3078), .Q(
n753) );
DFFSX1TS R_923 ( .D(n3310), .CK(clk), .SN(n3165), .QN(n752) );
DFFSX2TS R_922 ( .D(n3311), .CK(clk), .SN(n3165), .QN(n751) );
DFFSX1TS R_921 ( .D(n3312), .CK(clk), .SN(n3166), .QN(n750) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n815),
.QN(n3105) );
DFFSX4TS mult_x_19_R_1008 ( .D(mult_x_19_n995), .CK(clk), .SN(n3088), .Q(
n3040) );
DFFSX2TS mult_x_19_R_585 ( .D(mult_x_19_n439), .CK(clk), .SN(n3089), .QN(
n703) );
DFFSX2TS mult_x_19_R_1117 ( .D(n3068), .CK(clk), .SN(n3076), .Q(
mult_x_19_n1603), .QN(n607) );
DFFSHQX8TS mult_x_19_R_546 ( .D(n2953), .CK(clk), .SN(n3284), .Q(n744) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n3283), .Q(n736) );
DFFSHQX8TS mult_x_19_R_934 ( .D(n2935), .CK(clk), .SN(n3074), .Q(n734) );
DFFRHQX8TS mult_x_19_R_1086 ( .D(mult_x_19_n1773), .CK(clk), .RN(n3281), .Q(
n732) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n815),
.Q(n731), .QN(n3108) );
DFFRX2TS Sgf_operation_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(n3080),
.Q(P_Sgf[6]) );
DFFRX2TS R_954 ( .D(n312), .CK(clk), .RN(n3283), .Q(Op_MY[0]) );
DFFRX2TS R_489 ( .D(mult_x_19_n689), .CK(clk), .RN(n3285), .Q(Op_MY[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n3163), .Q(Op_MX[31]) );
DFFRX2TS R_632 ( .D(n344), .CK(clk), .RN(n3163), .Q(Op_MX[0]) );
DFFRX4TS R_906 ( .D(mult_x_19_n1777), .CK(clk), .RN(n402), .Q(Op_MY[17]) );
DFFRX2TS R_602 ( .D(n362), .CK(clk), .RN(n3283), .Q(Op_MX[18]) );
DFFSX2TS mult_x_19_R_579 ( .D(mult_x_19_n110), .CK(clk), .SN(n3089), .Q(
n2955) );
DFFSX4TS mult_x_19_R_1075 ( .D(n697), .CK(clk), .SN(n3087), .Q(n3060) );
DFFSHQX8TS mult_x_19_R_1119 ( .D(n2924), .CK(clk), .SN(n3078), .Q(n695) );
DFFRHQX8TS mult_x_19_R_1107 ( .D(n357), .CK(clk), .RN(n3076), .Q(n693) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n3154), .Q(n691) );
DFFRHQX8TS mult_x_19_R_1085 ( .D(mult_x_19_n19), .CK(clk), .RN(n403), .Q(
n690) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n3076), .Q(n686) );
DFFRX1TS mult_x_19_R_1007 ( .D(mult_x_19_n418), .CK(clk), .RN(n3090), .Q(
n3039) );
DFFSHQX8TS mult_x_19_R_485 ( .D(n2938), .CK(clk), .SN(n3153), .Q(n679) );
DFFRX4TS mult_x_19_R_901 ( .D(mult_x_19_n810), .CK(clk), .RN(n3087), .Q(
n3009) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n3283), .Q(n673) );
DFFRHQX8TS mult_x_19_R_1128 ( .D(mult_x_19_n723), .CK(clk), .RN(n404), .Q(
n671) );
DFFRHQX4TS mult_x_19_R_477 ( .D(n348), .CK(clk), .RN(n2575), .Q(n670) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n3280), .Q(n668) );
DFFRHQX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n3279), .Q(n664) );
DFFSX2TS mult_x_19_R_337 ( .D(mult_x_19_n109), .CK(clk), .SN(n3089), .Q(
n2930) );
DFFRHQX4TS mult_x_19_R_379 ( .D(n350), .CK(clk), .RN(n3076), .Q(n659) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n815),
.QN(n3107) );
DFFRHQX8TS mult_x_19_R_647 ( .D(n345), .CK(clk), .RN(n3075), .Q(n727) );
DFFRHQX8TS mult_x_19_R_1135 ( .D(mult_x_19_n633), .CK(clk), .RN(n405), .Q(
n654) );
DFFRHQX8TS mult_x_19_R_1116 ( .D(mult_x_19_n1777), .CK(clk), .RN(n3281), .Q(
n650) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n3361), .Q(n648) );
DFFSX2TS mult_x_19_R_800 ( .D(mult_x_19_n896), .CK(clk), .SN(n3084), .Q(
n2979) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n3281), .Q(n646) );
DFFSX2TS mult_x_19_R_518 ( .D(mult_x_19_n267), .CK(clk), .SN(n3083), .Q(
n2940) );
DFFRX1TS mult_x_19_R_835_RW_0 ( .D(mult_x_19_n647), .CK(clk), .RN(n3082),
.Q(n2991) );
DFFSX2TS mult_x_19_R_712 ( .D(mult_x_19_n647), .CK(clk), .SN(n3084), .Q(
n2969) );
DFFRHQX8TS mult_x_19_R_1133 ( .D(n363), .CK(clk), .RN(n3079), .Q(n645) );
DFFRHQX8TS mult_x_19_R_529 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n644) );
DFFRHQX8TS mult_x_19_R_1131 ( .D(mult_x_19_n1791), .CK(clk), .RN(n403), .Q(
n638) );
DFFRHQX2TS mult_x_19_R_547 ( .D(n364), .CK(clk), .RN(n3079), .Q(n635) );
DFFSHQX8TS mult_x_19_R_622 ( .D(n2925), .CK(clk), .SN(n3075), .Q(n627) );
DFFRXLTS R_311 ( .D(n250), .CK(clk), .RN(n3157), .Q(n3231) );
DFFRXLTS R_314 ( .D(n251), .CK(clk), .RN(n3157), .Q(n3230) );
DFFRXLTS R_576 ( .D(n249), .CK(clk), .RN(n3158), .Q(n3229) );
DFFRXLTS R_734 ( .D(n248), .CK(clk), .RN(n3161), .Q(n3226) );
DFFRX1TS R_728 ( .D(n246), .CK(clk), .RN(n3161), .Q(n3227) );
DFFRX1TS R_1068 ( .D(n245), .CK(clk), .RN(n3360), .Q(n3171) );
DFFRHQX2TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n772), .Q(n2875) );
DFFSX2TS mult_x_19_R_1003 ( .D(mult_x_19_n458), .CK(clk), .SN(n3088), .Q(
n3037) );
DFFRHQX4TS mult_x_19_R_487 ( .D(n358), .CK(clk), .RN(n3075), .Q(n740) );
DFFSX4TS R_1028 ( .D(n2723), .CK(clk), .SN(n3279), .Q(n3181) );
DFFRHQX8TS mult_x_19_R_962 ( .D(n312), .CK(clk), .RN(n3155), .Q(n626) );
DFFRHQX2TS mult_x_19_R_667 ( .D(n360), .CK(clk), .RN(n3079), .Q(n625) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n3283), .Q(n623) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n3281), .Q(n621) );
DFFRHQX8TS mult_x_19_R_614 ( .D(mult_x_19_n49), .CK(clk), .RN(n3079), .Q(
n618) );
DFFRHQX4TS mult_x_19_R_623 ( .D(n349), .CK(clk), .RN(n3076), .Q(n698) );
DFFSX4TS mult_x_19_R_824 ( .D(mult_x_19_n613), .CK(clk), .SN(n3080), .Q(
n2985) );
DFFSX4TS mult_x_19_R_825 ( .D(mult_x_19_n604), .CK(clk), .SN(n3080), .Q(
n2986) );
DFFRX1TS mult_x_19_R_828_RW_0 ( .D(mult_x_19_n896), .CK(clk), .RN(n3087),
.Q(n2987) );
DFFRHQX8TS mult_x_19_R_956 ( .D(n312), .CK(clk), .RN(n3282), .Q(n612) );
DFFRHQX8TS mult_x_19_R_1059 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n604) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n3285), .Q(n600) );
DFFRHQX4TS mult_x_19_R_634 ( .D(n344), .CK(clk), .RN(n2575), .Q(n599) );
DFFSX2TS mult_x_19_R_593 ( .D(n2957), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1749) );
DFFSX2TS R_1156 ( .D(n950), .CK(clk), .SN(n3083), .Q(n598) );
DFFRX2TS R_1157 ( .D(n2105), .CK(clk), .RN(n3276), .Q(n597) );
DFFSX2TS R_1162 ( .D(n596), .CK(clk), .SN(n404), .Q(n1324) );
DFFRX2TS R_1160 ( .D(n349), .CK(clk), .RN(n402), .Q(mult_x_19_n1697) );
DFFSX4TS mult_x_19_R_587 ( .D(n2943), .CK(clk), .SN(n3282), .Q(n2893), .QN(
n593) );
DFFSX4TS mult_x_19_R_1024 ( .D(n3046), .CK(clk), .SN(n3164), .Q(n2892), .QN(
n706) );
DFFSX2TS R_1183 ( .D(n3274), .CK(clk), .SN(n3277), .Q(n589), .QN(n420) );
DFFSX4TS R_1184 ( .D(n424), .CK(clk), .SN(n3088), .Q(n588) );
DFFSX2TS R_1185 ( .D(n425), .CK(clk), .SN(n3162), .Q(n587) );
DFFSX2TS R_1187 ( .D(n424), .CK(clk), .SN(n3160), .Q(n586), .QN(n418) );
DFFSX2TS R_1188 ( .D(n425), .CK(clk), .SN(n3156), .Q(n585) );
DFFSX2TS R_1189 ( .D(mult_x_19_n524), .CK(clk), .SN(n3080), .Q(n584) );
DFFSX2TS R_1190 ( .D(mult_x_19_n211), .CK(clk), .SN(n3085), .Q(n583) );
DFFSX2TS R_1191 ( .D(mult_x_19_n474), .CK(clk), .SN(n3088), .Q(n582) );
DFFSX2TS R_1192 ( .D(n3092), .CK(clk), .SN(n3081), .Q(n581) );
DFFSX2TS R_1194 ( .D(mult_x_19_n708), .CK(clk), .SN(n3085), .Q(n579) );
DFFSX2TS R_1195 ( .D(mult_x_19_n851), .CK(clk), .SN(n794), .Q(n578) );
DFFSX2TS R_1197 ( .D(mult_x_19_n726), .CK(clk), .SN(n3276), .Q(n576) );
DFFSX2TS R_1198 ( .D(mult_x_19_n197), .CK(clk), .SN(n3360), .Q(n575) );
DFFSX2TS R_1199 ( .D(mult_x_19_n959), .CK(clk), .SN(n3277), .Q(n574) );
DFFSX4TS R_1200 ( .D(mult_x_19_n977), .CK(clk), .SN(n3091), .Q(n573) );
DFFSX2TS R_1202 ( .D(mult_x_19_n181), .CK(clk), .SN(n3081), .Q(n571) );
DFFSX2TS R_1203 ( .D(n3096), .CK(clk), .SN(n3080), .Q(n570) );
DFFSX2TS R_1204 ( .D(mult_x_19_n875), .CK(clk), .SN(n2576), .Q(n569) );
DFFSX2TS R_1205 ( .D(mult_x_19_n691), .CK(clk), .SN(n3084), .Q(n568) );
DFFSX2TS R_1206 ( .D(mult_x_19_n418), .CK(clk), .SN(n3085), .Q(n567), .QN(
n566) );
DFFSX2TS R_1207 ( .D(mult_x_19_n165), .CK(clk), .SN(n3081), .Q(n565) );
DFFSX4TS R_1208 ( .D(n3356), .CK(clk), .SN(n778), .Q(n564) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n3282), .Q(n563) );
DFFSX2TS R_968 ( .D(n3314), .CK(clk), .SN(n3166), .Q(n3201) );
DFFRX1TS mult_x_19_R_805_RW_0 ( .D(mult_x_19_n874), .CK(clk), .RN(n2576),
.Q(n2982) );
DFFSX1TS R_1196 ( .D(mult_x_19_n852), .CK(clk), .SN(n794), .Q(n577) );
DFFSX4TS R_1158 ( .D(n2962), .CK(clk), .SN(n3074), .Q(mult_x_19_n4), .QN(
n3097) );
DFFSX4TS R_1164 ( .D(n595), .CK(clk), .SN(n3075), .Q(n1091) );
DFFSX2TS mult_x_19_R_1132 ( .D(n3070), .CK(clk), .SN(n3154), .Q(
mult_x_19_n1542) );
DFFRX4TS mult_x_19_R_899_RW_0 ( .D(mult_x_19_n830), .CK(clk), .RN(n3087),
.Q(n3008) );
DFFSX2TS mult_x_19_R_1103 ( .D(n3065), .CK(clk), .SN(n3075), .Q(
mult_x_19_n1617) );
DFFSX2TS mult_x_19_R_1053 ( .D(n3052), .CK(clk), .SN(n3167), .Q(
mult_x_19_n1678) );
DFFSX2TS R_978 ( .D(n3344), .CK(clk), .SN(n3279), .Q(n3191) );
DFFSX1TS R_1049 ( .D(n3358), .CK(clk), .SN(n816), .Q(n3176) );
DFFRX1TS R_484 ( .D(n358), .CK(clk), .RN(n3164), .Q(Op_MX[14]) );
DFFSX1TS mult_x_19_R_840 ( .D(mult_x_19_n114), .CK(clk), .SN(n3089), .Q(
n2993) );
DFFSX1TS mult_x_19_R_1004 ( .D(mult_x_19_n459), .CK(clk), .SN(n3088), .Q(
n3038) );
DFFRX1TS mult_x_19_R_1011 ( .D(mult_x_19_n743), .CK(clk), .RN(n3086), .Q(
n3042) );
DFFRHQX4TS mult_x_19_R_202 ( .D(n365), .CK(clk), .RN(n3079), .Q(n759) );
DFFSX4TS mult_x_19_R_1002 ( .D(n614), .CK(clk), .SN(n3088), .Q(n3036) );
DFFSX4TS R_1159 ( .D(n2962), .CK(clk), .SN(n3074), .Q(n862), .QN(n552) );
DFFRX4TS mult_x_19_R_953 ( .D(mult_x_19_n692), .CK(clk), .RN(n3086), .Q(
n3028) );
DFFRX4TS mult_x_19_R_903 ( .D(mult_x_19_n808), .CK(clk), .RN(n3158), .Q(
n3011) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n817), .Q(Sgf_normalized_result[0]) );
DFFSX2TS R_1041 ( .D(n3349), .CK(clk), .SN(n3153), .Q(n3178) );
DFFSX2TS mult_x_19_R_1009 ( .D(mult_x_19_n1010), .CK(clk), .SN(n3088), .Q(
n3041) );
DFFRHQX4TS mult_x_19_R_664 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n684) );
DFFSHQX4TS mult_x_19_R_1080 ( .D(n3062), .CK(clk), .SN(n3284), .Q(n689) );
DFFSX1TS mult_x_19_R_936 ( .D(mult_x_19_n662), .CK(clk), .SN(n3277), .Q(
n3024) );
DFFSX2TS R_1201 ( .D(mult_x_19_n675), .CK(clk), .SN(n3277), .Q(n572) );
DFFRX2TS mult_x_19_R_989 ( .D(mult_x_19_n807), .CK(clk), .RN(n794), .Q(n3031) );
DFFRHQX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n771), .Q(Op_MY[26]) );
DFFSRHQX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk),
.SN(1'b1), .RN(n772), .Q(Op_MY[23]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n3280), .Q(Op_MY[24]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n3280), .Q(Op_MY[25]) );
DFFSX1TS mult_x_19_R_816_RW_0 ( .D(mult_x_19_n897), .CK(clk), .SN(n3080),
.Q(n2984) );
DFFSX2TS R_1193 ( .D(mult_x_19_n707), .CK(clk), .SN(n3084), .Q(n580) );
DFFSHQX8TS mult_x_19_R_987 ( .D(n2933), .CK(clk), .SN(n3278), .Q(n633) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n3280), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n3280), .Q(Op_MY[28]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n3154), .Q(Op_MX[26]), .QN(n996) );
DFFRX1TS mult_x_19_R_856 ( .D(mult_x_19_n471), .CK(clk), .RN(n3090), .Q(
n2999) );
DFFRX2TS mult_x_19_R_855 ( .D(mult_x_19_n555), .CK(clk), .RN(n3090), .Q(
n2998) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n3155), .Q(Op_MX[28]), .QN(n3115) );
DFFSX2TS mult_x_19_R_1031 ( .D(n3047), .CK(clk), .SN(n3153), .Q(
mult_x_19_n1677) );
DFFSX2TS mult_x_19_R_538 ( .D(n2945), .CK(clk), .SN(n3285), .Q(n419), .QN(
n704) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n3154), .Q(Op_MX[27]), .QN(n3116) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n3155), .Q(Op_MX[29]), .QN(n3135) );
DFFSRHQX2TS mult_x_19_R_1020_IP ( .D(n3046), .CK(clk), .SN(n772), .RN(1'b1),
.Q(n2952) );
DFFRX1TS mult_x_19_R_1129 ( .D(n3069), .CK(clk), .RN(n3075), .Q(n602), .QN(
n700) );
DFFRX1TS mult_x_19_R_596 ( .D(mult_x_19_n113), .CK(clk), .RN(n3090), .Q(
n2958) );
DFFSX2TS mult_x_19_R_1139 ( .D(mult_x_19_n115), .CK(clk), .SN(n3088), .Q(
n3073) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n3280), .Q(Op_MY[30]), .QN(n3137) );
DFFRXLTS mult_x_19_R_768 ( .D(mult_x_19_n451), .CK(clk), .RN(n3090), .Q(
n2973) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(n3080),
.Q(P_Sgf[5]) );
DFFRX1TS mult_x_19_R_916 ( .D(mult_x_19_n465), .CK(clk), .RN(n3090), .Q(
n3014) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n3155), .Q(Op_MX[30]) );
DFFSX1TS mult_x_19_R_802 ( .D(n3099), .CK(clk), .SN(n3089), .Q(n2980) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(n3083),
.Q(P_Sgf[4]) );
DFFSX2TS R_1040 ( .D(n3350), .CK(clk), .SN(n816), .Q(n3179) );
DFFSRHQX2TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk),
.SN(1'b1), .RN(n773), .Q(Op_MY[31]) );
DFFRXLTS mult_x_19_R_598 ( .D(mult_x_19_n112), .CK(clk), .RN(n3090), .Q(
n2959) );
DFFRXLTS mult_x_19_R_565 ( .D(mult_x_19_n111), .CK(clk), .RN(n3090), .Q(
n2954) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n788), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n3284), .Q(Sgf_normalized_result[6]), .QN(n3148) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n3154), .Q(n640) );
DFFSRHQX2TS mult_x_19_R_1082_IP ( .D(n2879), .CK(clk), .SN(n3154), .RN(1'b1),
.Q(n3051) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(n3083),
.Q(P_Sgf[0]) );
DFFSRHQX2TS R_327 ( .D(mult_x_19_n593), .CK(clk), .SN(1'b1), .RN(n3154), .Q(
Op_MY[18]) );
DFFSX1TS mult_x_19_R_73 ( .D(n2911), .CK(clk), .SN(n3081), .Q(n2919) );
DFFRX1TS R_1042 ( .D(mult_x_19_n723), .CK(clk), .RN(n3283), .Q(Op_MY[8]) );
DFFRX1TS R_1102 ( .D(mult_x_19_n1791), .CK(clk), .RN(n778), .Q(n3112), .QN(
n3149) );
DFFRX1TS R_475 ( .D(n348), .CK(clk), .RN(n3164), .Q(Op_MX[4]) );
DFFSX1TS R_39 ( .D(n3275), .CK(clk), .SN(n3156), .Q(n3254) );
DFFSRHQX2TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .SN(1'b1),
.RN(n771), .Q(Add_result[1]) );
DFFSX1TS R_56 ( .D(n3345), .CK(clk), .SN(n3160), .Q(n3247) );
DFFSX2TS R_41 ( .D(n3352), .CK(clk), .SN(n3156), .Q(n3253) );
DFFSX1TS mult_x_19_R_71 ( .D(n2910), .CK(clk), .SN(n3081), .Q(n2918) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n771),
.Q(Add_result[23]) );
DFFSX2TS R_14 ( .D(n3333), .CK(clk), .SN(n3160), .Q(n3267) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n3279),
.Q(Add_result[16]), .QN(n3127) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n3284),
.Q(Add_result[11]), .QN(n3132) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n3284),
.Q(Add_result[17]), .QN(n3126) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n3284),
.Q(Add_result[14]), .QN(n3129) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n3164),
.Q(Add_result[15]), .QN(n3128) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n3279),
.Q(Add_result[13]), .QN(n3130) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n3164),
.Q(Add_result[12]), .QN(n3131) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n3282), .Q(final_result_ieee[7]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n3282), .Q(final_result_ieee[5]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n778), .Q(final_result_ieee[2]) );
INVX2TS U406 ( .A(mult_x_19_n197), .Y(mult_x_19_n525) );
INVX2TS U407 ( .A(n2532), .Y(mult_x_19_n524) );
CLKMX2X2TS U408 ( .A(Data_MY[5]), .B(n429), .S0(n2795), .Y(n317) );
OAI21X2TS U409 ( .A0(mult_x_19_n179), .A1(n2538), .B0(n2537), .Y(
mult_x_19_n166) );
CLKMX2X2TS U410 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n2795), .Y(n336) );
NAND2X2TS U411 ( .A(mult_x_19_n613), .B(mult_x_19_n604), .Y(mult_x_19_n211)
);
CLKINVX1TS U412 ( .A(n401), .Y(n404) );
CLKMX2X2TS U413 ( .A(n2803), .B(P_Sgf[0]), .S0(n424), .Y(n238) );
AND2X4TS U414 ( .A(n2257), .B(n2287), .Y(n3096) );
CLKINVX6TS U415 ( .A(n2282), .Y(mult_x_19_n471) );
BUFX3TS U416 ( .A(n3276), .Y(n3087) );
NAND2X4TS U417 ( .A(n936), .B(n933), .Y(mult_x_19_n474) );
CLKBUFX3TS U418 ( .A(n3163), .Y(n3074) );
CLKINVX1TS U419 ( .A(n401), .Y(n402) );
ADDFHX2TS U420 ( .A(n2464), .B(n2463), .CI(n2462), .CO(mult_x_19_n807), .S(
mult_x_19_n808) );
ADDFHX2TS U421 ( .A(n2167), .B(n2166), .CI(n2165), .CO(mult_x_19_n707), .S(
mult_x_19_n708) );
ADDFHX2TS U422 ( .A(n2513), .B(n2512), .CI(n2511), .CO(mult_x_19_n829), .S(
mult_x_19_n830) );
NOR2X6TS U423 ( .A(n2534), .B(n2533), .Y(mult_x_19_n197) );
INVX2TS U424 ( .A(n2835), .Y(n2852) );
NAND2X1TS U425 ( .A(n776), .B(P_Sgf[6]), .Y(n926) );
NOR2X4TS U426 ( .A(n2535), .B(n2536), .Y(n2532) );
XOR2X2TS U427 ( .A(n2299), .B(n2298), .Y(n829) );
INVX3TS U428 ( .A(n2835), .Y(n2849) );
BUFX3TS U429 ( .A(n3279), .Y(n3163) );
BUFX3TS U430 ( .A(n2835), .Y(n2834) );
INVX4TS U431 ( .A(n425), .Y(n424) );
NOR2X6TS U432 ( .A(n935), .B(n934), .Y(n933) );
ADDFHX2TS U433 ( .A(n2510), .B(n2509), .CI(n2508), .CO(n2511), .S(n1902) );
BUFX4TS U434 ( .A(n2723), .Y(n2757) );
ADDFHX2TS U435 ( .A(n2507), .B(n2506), .CI(n2505), .CO(n2464), .S(n2512) );
XOR2X2TS U436 ( .A(n2296), .B(n2295), .Y(n875) );
NAND2X2TS U437 ( .A(n514), .B(n513), .Y(n2557) );
ADDFHX2TS U438 ( .A(n2522), .B(n2521), .CI(n2520), .CO(n2523), .S(n2432) );
ADDFHX2TS U439 ( .A(n2429), .B(n2428), .CI(n2427), .CO(mult_x_19_n960), .S(
n2430) );
NAND2X2TS U440 ( .A(n1981), .B(n1966), .Y(n1967) );
XOR2X1TS U441 ( .A(n2354), .B(n2353), .Y(n858) );
CLKMX2X2TS U442 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n2791), .Y(
mult_x_19_n579) );
OAI22X1TS U443 ( .A0(n427), .A1(zero_flag), .B0(n1938), .B1(
FS_Module_state_reg[2]), .Y(n526) );
NOR2X4TS U444 ( .A(n2640), .B(n853), .Y(n527) );
INVX2TS U445 ( .A(n3077), .Y(n401) );
NAND2X1TS U446 ( .A(n1524), .B(n1525), .Y(n1526) );
AOI2BB2X2TS U447 ( .B0(n1483), .B1(n262), .A0N(n805), .A1N(n2787), .Y(n2613)
);
BUFX4TS U448 ( .A(n2873), .Y(n796) );
INVX3TS U449 ( .A(mult_x_19_n145), .Y(n2541) );
INVX16TS U450 ( .A(n461), .Y(n3101) );
AND2X6TS U451 ( .A(n1957), .B(n1956), .Y(n634) );
AND2X6TS U452 ( .A(n1971), .B(n1970), .Y(n697) );
INVX2TS U453 ( .A(n1523), .Y(n2283) );
NOR2X4TS U454 ( .A(n2266), .B(n1981), .Y(n935) );
CLKMX2X4TS U455 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n2568), .Y(n365) );
NOR2X4TS U456 ( .A(n2191), .B(n2190), .Y(n2281) );
NAND2X4TS U457 ( .A(n1172), .B(n1171), .Y(n2436) );
OAI21X2TS U458 ( .A0(n2378), .A1(n2379), .B0(n2377), .Y(n943) );
NAND2X1TS U459 ( .A(n2735), .B(n2725), .Y(n2726) );
NAND2X4TS U460 ( .A(n2213), .B(n1362), .Y(n2723) );
INVX4TS U461 ( .A(n2783), .Y(n806) );
NAND2X4TS U462 ( .A(n494), .B(n830), .Y(n2105) );
BUFX3TS U463 ( .A(n3360), .Y(n3276) );
CLKMX2X4TS U464 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n2263), .Y(n352) );
NAND2X1TS U465 ( .A(n2552), .B(n518), .Y(n513) );
INVX3TS U466 ( .A(n2783), .Y(n807) );
CLKINVX6TS U467 ( .A(n2267), .Y(n934) );
ADDFHX2TS U468 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2167), .S(n2136) );
INVX6TS U469 ( .A(n425), .Y(n2873) );
OAI2BB1X1TS U470 ( .A0N(n516), .A1N(n515), .B0(n2551), .Y(n514) );
CLKINVX6TS U471 ( .A(n1669), .Y(n2700) );
AO22X2TS U472 ( .A0(n1002), .A1(n711), .B0(n647), .B1(n710), .Y(n2555) );
NOR2BX1TS U473 ( .AN(n2259), .B(FS_Module_state_reg[1]), .Y(n964) );
CLKBUFX2TS U474 ( .A(n2575), .Y(n3077) );
CLKINVX6TS U475 ( .A(n1669), .Y(n2784) );
INVX2TS U476 ( .A(n1647), .Y(n2701) );
BUFX3TS U477 ( .A(n1899), .Y(n658) );
INVX2TS U478 ( .A(n2605), .Y(n2599) );
NAND2BXLTS U479 ( .AN(n647), .B(n713), .Y(n711) );
XOR2X2TS U480 ( .A(n2551), .B(n517), .Y(n2405) );
AND2X6TS U481 ( .A(n524), .B(n1524), .Y(n938) );
NAND2X6TS U482 ( .A(n1098), .B(n1097), .Y(n1981) );
NAND2XLTS U483 ( .A(n2659), .B(n2662), .Y(n1630) );
NAND2X2TS U484 ( .A(n2299), .B(n2298), .Y(n830) );
NAND2XLTS U485 ( .A(n2646), .B(n2645), .Y(n2647) );
ADDFHX2TS U486 ( .A(n1840), .B(n1839), .CI(n1838), .CO(n2133), .S(n2010) );
NAND2X2TS U487 ( .A(n1400), .B(n427), .Y(n1401) );
NAND2X2TS U488 ( .A(n1391), .B(n427), .Y(n1392) );
ADDFHX2TS U489 ( .A(n1560), .B(n1559), .CI(n1558), .CO(n2404), .S(n1578) );
NOR2X2TS U490 ( .A(n2741), .B(n3141), .Y(n2742) );
NAND2BX2TS U491 ( .AN(n2603), .B(n1444), .Y(n1445) );
ADDFHX2TS U492 ( .A(n2452), .B(n2451), .CI(n2450), .CO(n2506), .S(n2503) );
ADDFHX2TS U493 ( .A(n2130), .B(n2129), .CI(n2128), .CO(n2540), .S(n1615) );
OR2X6TS U494 ( .A(n2186), .B(n2187), .Y(n823) );
OAI21X2TS U495 ( .A0(n2112), .A1(n2108), .B0(n2109), .Y(n1012) );
OAI2BB1X2TS U496 ( .A0N(n870), .A1N(n1868), .B0(n903), .Y(n2451) );
NAND2BX1TS U497 ( .AN(n1892), .B(n914), .Y(n913) );
NAND2X1TS U498 ( .A(n1458), .B(n1457), .Y(n1470) );
NOR2X6TS U499 ( .A(n1486), .B(n793), .Y(n1483) );
NAND2X6TS U500 ( .A(n1523), .B(n1525), .Y(n524) );
OAI21X1TS U501 ( .A0(n947), .A1(n1865), .B0(n1864), .Y(n948) );
INVX2TS U502 ( .A(n2252), .Y(n1916) );
XNOR2X2TS U503 ( .A(n1469), .B(n1407), .Y(n1408) );
ADDFHX2TS U504 ( .A(n1601), .B(n1600), .CI(n1599), .CO(n2529), .S(n2527) );
NOR2X2TS U505 ( .A(n1449), .B(n1452), .Y(n1454) );
NAND2X4TS U506 ( .A(n1079), .B(n1080), .Y(n1524) );
CMPR32X2TS U507 ( .A(n2476), .B(n786), .C(n2475), .CO(n2489), .S(n2548) );
NAND2X2TS U508 ( .A(n2248), .B(n2251), .Y(n2254) );
OAI22X2TS U509 ( .A0(n407), .A1(n1540), .B0(n2469), .B1(n2468), .Y(n2543) );
ADDFHX2TS U510 ( .A(n1587), .B(n1586), .CI(n1585), .CO(n1580), .S(n2175) );
ADDFHX2TS U511 ( .A(n495), .B(n1551), .CI(n1550), .CO(n1559), .S(n1581) );
NAND2X2TS U512 ( .A(n2661), .B(n1531), .Y(n1533) );
OAI22X2TS U513 ( .A0(n676), .A1(mult_x_19_n1552), .B0(n1541), .B1(n2471),
.Y(n1566) );
OR2X6TS U514 ( .A(n1078), .B(n1077), .Y(n2284) );
AO21X2TS U515 ( .A0(n2041), .A1(n2479), .B0(n2884), .Y(n1613) );
INVX2TS U516 ( .A(n957), .Y(n955) );
AO21X2TS U517 ( .A0(n760), .A1(n1674), .B0(n2888), .Y(n1507) );
OAI22X1TS U518 ( .A0(n551), .A1(n863), .B0(n695), .B1(n787), .Y(n2132) );
INVX6TS U519 ( .A(n2788), .Y(n427) );
NAND3X2TS U520 ( .A(n3185), .B(n3184), .C(n3183), .Y(n2854) );
OAI22X1TS U521 ( .A0(n676), .A1(n1552), .B0(mult_x_19_n1552), .B1(n2322),
.Y(n1553) );
CLKBUFX2TS U522 ( .A(n2950), .Y(n495) );
BUFX4TS U523 ( .A(n1866), .Y(n947) );
INVX1TS U524 ( .A(n1389), .Y(n1383) );
CLKXOR2X2TS U525 ( .A(n988), .B(n525), .Y(n871) );
AO21XLTS U526 ( .A0(n678), .A1(n799), .B0(n2886), .Y(n1594) );
ADDFHX2TS U527 ( .A(n2181), .B(n2179), .CI(n2180), .CO(n1591), .S(n2270) );
CLKBUFX2TS U528 ( .A(FSM_selector_C), .Y(n793) );
INVX3TS U529 ( .A(n1052), .Y(n488) );
OAI22X2TS U530 ( .A0(n784), .A1(n2480), .B0(n1505), .B1(n2479), .Y(n2466) );
OAI21X2TS U531 ( .A0(n1249), .A1(n1451), .B0(n1248), .Y(n1250) );
NAND2BX1TS U532 ( .AN(n723), .B(n2146), .Y(n719) );
NOR2X4TS U533 ( .A(n1940), .B(n1529), .Y(n1531) );
INVX2TS U534 ( .A(n606), .Y(n1782) );
CLKXOR2X2TS U535 ( .A(n1439), .B(n1438), .Y(n1440) );
OAI22X2TS U536 ( .A0(n1504), .A1(n509), .B0(n970), .B1(n1502), .Y(n1512) );
CLKXOR2X2TS U537 ( .A(n1415), .B(n1414), .Y(n1419) );
NAND2BX2TS U538 ( .AN(n1597), .B(n974), .Y(n973) );
INVX2TS U539 ( .A(n723), .Y(n721) );
AO22X2TS U540 ( .A0(n2474), .A1(n622), .B0(n2946), .B1(n2238), .Y(n2478) );
OAI22X1TS U541 ( .A0(n677), .A1(n1884), .B0(n2471), .B1(n2886), .Y(n1515) );
BUFX3TS U542 ( .A(n887), .Y(n844) );
OAI22X1TS U543 ( .A0(n1796), .A1(n1322), .B0(n1302), .B1(n757), .Y(n1334) );
INVX2TS U544 ( .A(n775), .Y(n498) );
OA21X2TS U545 ( .A0(n558), .A1(n1939), .B0(n1942), .Y(n1528) );
OAI2BB1X2TS U546 ( .A0N(n1291), .A1N(n941), .B0(n940), .Y(n1879) );
XNOR2X2TS U547 ( .A(n791), .B(n879), .Y(n1504) );
INVX2TS U548 ( .A(n1634), .Y(n1660) );
NAND2X2TS U549 ( .A(n2258), .B(n1481), .Y(n1482) );
AOI21X2TS U550 ( .A0(n2121), .A1(n2003), .B0(n566), .Y(n1859) );
NOR2X2TS U551 ( .A(n1940), .B(n1494), .Y(n1496) );
NOR2X6TS U552 ( .A(n1274), .B(FS_Module_state_reg[1]), .Y(n2788) );
INVX2TS U553 ( .A(n1429), .Y(n1426) );
NAND2X4TS U554 ( .A(n559), .B(n1848), .Y(n1529) );
NOR2X4TS U555 ( .A(n1269), .B(n699), .Y(n1456) );
NAND2X1TS U556 ( .A(n1999), .B(n2116), .Y(n2000) );
INVX3TS U557 ( .A(n636), .Y(n1450) );
NAND2BX2TS U558 ( .AN(n2484), .B(n974), .Y(n925) );
MX2X4TS U559 ( .A(n2127), .B(n3237), .S0(n589), .Y(n259) );
OAI21X1TS U560 ( .A0(n1948), .A1(n1494), .B0(n2654), .Y(n1495) );
ADDFHX2TS U561 ( .A(n1160), .B(n1159), .CI(n1158), .CO(n1914), .S(n1168) );
INVX6TS U562 ( .A(n1619), .Y(n2661) );
NAND2X2TS U563 ( .A(n1394), .B(n1464), .Y(n1398) );
ADDFHX2TS U564 ( .A(n2102), .B(n2103), .CI(n2104), .CO(n2293), .S(n2294) );
NAND2X2TS U565 ( .A(n1382), .B(n1381), .Y(n1389) );
XNOR2X2TS U566 ( .A(n883), .B(n755), .Y(n1541) );
OAI22X2TS U567 ( .A0(n667), .A1(n1774), .B0(n1779), .B1(n744), .Y(n1776) );
NAND2BX2TS U568 ( .AN(n2483), .B(n972), .Y(n971) );
XNOR2X2TS U569 ( .A(n883), .B(n650), .Y(n1552) );
XNOR2X2TS U570 ( .A(n792), .B(n884), .Y(n1543) );
ADDFHX2TS U571 ( .A(n2302), .B(n2301), .CI(n2300), .CO(n2344), .S(n2349) );
ADDFX2TS U572 ( .A(n781), .B(n884), .CI(n1503), .CO(n1517), .S(n1511) );
NAND2X2TS U573 ( .A(n699), .B(n1269), .Y(n1457) );
NAND2X2TS U574 ( .A(Sgf_normalized_result[20]), .B(n2856), .Y(n2753) );
INVX2TS U575 ( .A(n2184), .Y(n958) );
INVX2TS U576 ( .A(n667), .Y(n974) );
NOR2BX2TS U577 ( .AN(n789), .B(n2307), .Y(n1129) );
INVX1TS U578 ( .A(n1855), .Y(n1857) );
INVX2TS U579 ( .A(n558), .Y(n1945) );
INVX2TS U580 ( .A(n683), .Y(n1338) );
NOR2X6TS U581 ( .A(n1051), .B(n1050), .Y(n2607) );
INVX2TS U582 ( .A(n622), .Y(n781) );
AND2X4TS U583 ( .A(n616), .B(n2655), .Y(n559) );
INVX4TS U584 ( .A(n2650), .Y(n1948) );
OAI22X1TS U585 ( .A0(n676), .A1(n1359), .B0(n1353), .B1(n2471), .Y(n2341) );
NAND2X4TS U586 ( .A(n1047), .B(n1046), .Y(n2863) );
NOR2X4TS U587 ( .A(n1049), .B(n1048), .Y(n2605) );
OAI21X2TS U588 ( .A0(n2198), .A1(n2972), .B0(n2973), .Y(n2195) );
XNOR2X2TS U589 ( .A(n2013), .B(n650), .Y(n2075) );
NOR2X4TS U590 ( .A(n916), .B(n915), .Y(n914) );
NAND3X4TS U591 ( .A(n3197), .B(n3196), .C(n3195), .Y(n2842) );
NAND3X4TS U592 ( .A(n3191), .B(n3190), .C(n3189), .Y(n2838) );
OAI21X2TS U593 ( .A0(n2221), .A1(n714), .B0(n716), .Y(n1787) );
XNOR2X2TS U594 ( .A(n604), .B(n638), .Y(n2228) );
XNOR2X2TS U595 ( .A(n969), .B(n863), .Y(n1597) );
NAND2X2TS U596 ( .A(n1266), .B(n1265), .Y(n1381) );
INVX2TS U597 ( .A(n1921), .Y(n1922) );
XNOR2X2TS U598 ( .A(n791), .B(n650), .Y(n2483) );
XOR2X2TS U599 ( .A(n828), .B(n737), .Y(n836) );
XNOR2X2TS U600 ( .A(n2241), .B(n686), .Y(n981) );
XNOR2X2TS U601 ( .A(n883), .B(n668), .Y(n1506) );
ADDFHX2TS U602 ( .A(n1065), .B(n1064), .CI(n1063), .CO(n1095), .S(n1073) );
NAND2X4TS U603 ( .A(n1364), .B(n2584), .Y(n1274) );
BUFX8TS U604 ( .A(n763), .Y(n407) );
OAI22X2TS U605 ( .A0(n803), .A1(n1784), .B0(n1821), .B1(n2314), .Y(n1837) );
XNOR2X2TS U606 ( .A(n792), .B(n881), .Y(n2484) );
INVX2TS U607 ( .A(n1209), .Y(n2654) );
NOR4X1TS U608 ( .A(P_Sgf[4]), .B(P_Sgf[3]), .C(P_Sgf[2]), .D(P_Sgf[1]), .Y(
n2209) );
OAI22X2TS U609 ( .A0(n523), .A1(n900), .B0(n553), .B1(n1102), .Y(n1143) );
INVX4TS U610 ( .A(n2006), .Y(n2198) );
NOR2X1TS U611 ( .A(n2327), .B(mult_x_19_n1677), .Y(n915) );
CLKBUFX2TS U612 ( .A(n2013), .Y(n445) );
INVX1TS U613 ( .A(n2659), .Y(n2663) );
NOR2X4TS U614 ( .A(n1266), .B(n1265), .Y(n1380) );
OR2X2TS U615 ( .A(n2223), .B(mult_x_19_n1656), .Y(n653) );
INVX2TS U616 ( .A(n1433), .Y(n1435) );
OR2X4TS U617 ( .A(n804), .B(mult_x_19_n1656), .Y(n609) );
BUFX3TS U618 ( .A(n2905), .Y(n435) );
OAI22X2TS U619 ( .A0(n2318), .A1(n2052), .B0(n756), .B1(n2900), .Y(n2085) );
OR2X4TS U620 ( .A(n1039), .B(n1038), .Y(n2779) );
XNOR2X2TS U621 ( .A(n2052), .B(n2319), .Y(n1105) );
INVX6TS U622 ( .A(n1481), .Y(n1364) );
NOR2BX2TS U623 ( .AN(n612), .B(mult_x_19_n52), .Y(n1755) );
XNOR2X2TS U624 ( .A(n1090), .B(n762), .Y(n1102) );
INVX2TS U625 ( .A(n1849), .Y(n1942) );
CLKAND2X2TS U626 ( .A(n789), .B(n592), .Y(n1089) );
INVX2TS U627 ( .A(n621), .Y(n622) );
OAI22X2TS U628 ( .A0(n1762), .A1(n1058), .B0(n1083), .B1(n756), .Y(n1086) );
INVX4TS U629 ( .A(n1848), .Y(n1939) );
NOR2X4TS U630 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n2264) );
XNOR2X2TS U631 ( .A(n881), .B(n644), .Y(n1812) );
NAND2BX2TS U632 ( .AN(n452), .B(n2387), .Y(n448) );
CMPR22X2TS U633 ( .A(n1294), .B(n1295), .CO(n1880), .S(n1285) );
CMPR22X2TS U634 ( .A(n1701), .B(n1700), .CO(n1752), .S(n1698) );
XNOR2X2TS U635 ( .A(n753), .B(n736), .Y(n2220) );
NAND2X6TS U636 ( .A(n703), .B(n2006), .Y(n963) );
INVX12TS U637 ( .A(n1938), .Y(n2584) );
OAI22X2TS U638 ( .A0(n406), .A1(n917), .B0(n556), .B1(n1686), .Y(n1720) );
OAI22X2TS U639 ( .A0(n1705), .A1(n548), .B0(n556), .B1(n1760), .Y(n1753) );
OAI21X2TS U640 ( .A0(n406), .A1(mult_x_19_n1751), .B0(n549), .Y(n2303) );
ADDFHX2TS U641 ( .A(n2091), .B(n2092), .CI(n2090), .CO(n2446), .S(n2453) );
ADDFHX2TS U642 ( .A(n2095), .B(n2094), .CI(n2093), .CO(n2445), .S(n2454) );
OAI22X2TS U643 ( .A0(n841), .A1(n1060), .B0(n1082), .B1(n2327), .Y(n1085) );
OAI22X2TS U644 ( .A0(n406), .A1(n942), .B0(n900), .B1(n556), .Y(n1087) );
NAND2X6TS U645 ( .A(n1049), .B(n1048), .Y(n2604) );
OR2X6TS U646 ( .A(n3119), .B(FS_Module_state_reg[3]), .Y(n1481) );
INVX2TS U647 ( .A(n1050), .Y(n485) );
BUFX4TS U648 ( .A(n684), .Y(n433) );
BUFX4TS U649 ( .A(n744), .Y(n2151) );
NAND2X2TS U650 ( .A(n1186), .B(n1185), .Y(n1924) );
XNOR2X2TS U651 ( .A(n617), .B(n2793), .Y(n1081) );
BUFX16TS U652 ( .A(n1300), .Y(n2310) );
NAND2X2TS U653 ( .A(n1260), .B(n1259), .Y(n1424) );
NAND2X1TS U654 ( .A(n406), .B(n555), .Y(n954) );
INVX8TS U655 ( .A(n592), .Y(n590) );
XNOR2X2TS U656 ( .A(n644), .B(n2794), .Y(n1743) );
OR2X4TS U657 ( .A(n899), .B(n1762), .Y(n446) );
NAND2X4TS U658 ( .A(n1258), .B(n1257), .Y(n1434) );
BUFX12TS U659 ( .A(n2330), .Y(n841) );
OAI22X2TS U660 ( .A0(n1887), .A1(n2312), .B0(n2054), .B1(n1026), .Y(n2090)
);
BUFX16TS U661 ( .A(n855), .Y(n800) );
NOR2X6TS U662 ( .A(n1237), .B(n1259), .Y(n1239) );
NAND2X4TS U663 ( .A(n1235), .B(n1226), .Y(n1268) );
CLKINVX12TS U664 ( .A(n1853), .Y(n2121) );
XOR2X2TS U665 ( .A(n1090), .B(n672), .Y(n900) );
BUFX12TS U666 ( .A(n847), .Y(n2307) );
NAND2X4TS U667 ( .A(n1817), .B(mult_x_19_n1800), .Y(n743) );
NOR2X6TS U668 ( .A(n1256), .B(n1255), .Y(n1411) );
NOR2X6TS U669 ( .A(n1257), .B(n1258), .Y(n1433) );
NAND2BX2TS U670 ( .AN(n419), .B(n3097), .Y(n549) );
INVX2TS U671 ( .A(n2875), .Y(n2697) );
XNOR2X2TS U672 ( .A(n623), .B(n645), .Y(n975) );
XNOR2X2TS U673 ( .A(n644), .B(n646), .Y(n2072) );
XNOR2X2TS U674 ( .A(n617), .B(n638), .Y(n1055) );
NAND2X2TS U675 ( .A(n1237), .B(n1259), .Y(n1238) );
NOR2X2TS U676 ( .A(n902), .B(n1032), .Y(n2773) );
NAND2X2TS U677 ( .A(n902), .B(n1032), .Y(n2774) );
XNOR2X2TS U678 ( .A(n464), .B(n668), .Y(n1583) );
XOR2X2TS U679 ( .A(n464), .B(n2238), .Y(n2049) );
XOR2X2TS U680 ( .A(n2241), .B(n669), .Y(n2053) );
OAI22X2TS U681 ( .A0(n764), .A1(n2888), .B0(n2468), .B1(n1683), .Y(n1700) );
NAND2X2TS U682 ( .A(n828), .B(n737), .Y(n831) );
MXI2X4TS U683 ( .A(n3116), .B(n2588), .S0(n434), .Y(n1264) );
CLKXOR2X2TS U684 ( .A(n2241), .B(n655), .Y(n976) );
INVX12TS U685 ( .A(n675), .Y(n676) );
NAND2X6TS U686 ( .A(n1235), .B(n1225), .Y(n1266) );
INVX2TS U687 ( .A(n2878), .Y(n2588) );
BUFX8TS U688 ( .A(n594), .Y(n803) );
INVX6TS U689 ( .A(n2801), .Y(n761) );
INVX8TS U690 ( .A(n901), .Y(n790) );
INVX2TS U691 ( .A(n648), .Y(n649) );
BUFX16TS U692 ( .A(n1300), .Y(n2051) );
INVX12TS U693 ( .A(n2470), .Y(n764) );
BUFX4TS U694 ( .A(n633), .Y(n2327) );
XNOR2X2TS U695 ( .A(n604), .B(n2793), .Y(n2326) );
NAND2X2TS U696 ( .A(n1184), .B(n1183), .Y(n1664) );
NOR2X2TS U697 ( .A(n1938), .B(n3120), .Y(n1174) );
XNOR2X2TS U698 ( .A(n693), .B(n2476), .Y(n2036) );
INVX3TS U699 ( .A(n604), .Y(n605) );
BUFX16TS U700 ( .A(n2237), .Y(n492) );
INVX2TS U701 ( .A(n736), .Y(n737) );
BUFX12TS U702 ( .A(n1674), .Y(n2227) );
INVX1TS U703 ( .A(n645), .Y(n542) );
XNOR2X2TS U704 ( .A(n644), .B(n601), .Y(n2073) );
INVX12TS U705 ( .A(n675), .Y(n678) );
INVX2TS U706 ( .A(n691), .Y(n692) );
NOR2BX2TS U707 ( .AN(n612), .B(n1674), .Y(n1689) );
INVX4TS U708 ( .A(n2115), .Y(n2118) );
BUFX6TS U709 ( .A(n2319), .Y(n839) );
BUFX12TS U710 ( .A(n505), .Y(n509) );
NAND2X4TS U711 ( .A(n1235), .B(n1224), .Y(n1263) );
BUFX8TS U712 ( .A(n1500), .Y(n715) );
NAND2X2TS U713 ( .A(n568), .B(n3035), .Y(n2664) );
BUFX12TS U714 ( .A(n763), .Y(n760) );
INVX6TS U715 ( .A(n480), .Y(n1853) );
INVX6TS U716 ( .A(n671), .Y(n672) );
NOR2BX1TS U717 ( .AN(n612), .B(n633), .Y(n1068) );
NAND2X2TS U718 ( .A(n3097), .B(n2949), .Y(n709) );
XNOR2X2TS U719 ( .A(n645), .B(n671), .Y(n2039) );
CLKXOR2X4TS U720 ( .A(n753), .B(n2238), .Y(n1582) );
XNOR2X2TS U721 ( .A(n969), .B(n691), .Y(n726) );
BUFX8TS U722 ( .A(n1500), .Y(n714) );
BUFX6TS U723 ( .A(n1293), .Y(n2318) );
NAND2X2TS U724 ( .A(n1690), .B(n1691), .Y(n544) );
NAND2X6TS U725 ( .A(n1235), .B(n1234), .Y(n1260) );
INVX12TS U726 ( .A(n2486), .Y(n767) );
BUFX3TS U727 ( .A(n633), .Y(n1813) );
AND2X6TS U728 ( .A(n1205), .B(n2991), .Y(n1209) );
CLKBUFX2TS U729 ( .A(n1733), .Y(n430) );
NOR2X2TS U730 ( .A(n2323), .B(n2322), .Y(n453) );
INVX12TS U731 ( .A(n1281), .Y(n792) );
BUFX16TS U732 ( .A(n621), .Y(n1869) );
INVX8TS U733 ( .A(n754), .Y(n2238) );
INVX12TS U734 ( .A(n901), .Y(n2330) );
BUFX6TS U735 ( .A(mult_x_19_n28), .Y(n2223) );
INVX12TS U736 ( .A(n2486), .Y(n768) );
AND2X4TS U737 ( .A(n1211), .B(n3019), .Y(n1849) );
INVX2TS U738 ( .A(n464), .Y(n465) );
BUFX16TS U739 ( .A(n1817), .Y(n842) );
NAND2X6TS U740 ( .A(n729), .B(n730), .Y(n1691) );
BUFX12TS U741 ( .A(n673), .Y(n2319) );
NAND2BX2TS U742 ( .AN(n612), .B(n780), .Y(n1151) );
NAND2X2TS U743 ( .A(n569), .B(n2987), .Y(n1991) );
NAND2X6TS U744 ( .A(n1229), .B(n1235), .Y(n1254) );
NOR2X4TS U745 ( .A(n1642), .B(n1638), .Y(n1181) );
XNOR2X2TS U746 ( .A(n464), .B(n736), .Y(n1115) );
NAND2X2TS U747 ( .A(n577), .B(n2982), .Y(n1643) );
BUFX6TS U748 ( .A(n744), .Y(n970) );
BUFX6TS U749 ( .A(n679), .Y(n1674) );
XNOR2X2TS U750 ( .A(n694), .B(n749), .Y(n1150) );
BUFX6TS U751 ( .A(n1300), .Y(n437) );
NAND3X6TS U752 ( .A(n637), .B(n2124), .C(n480), .Y(n479) );
NOR2X4TS U753 ( .A(n677), .B(n2324), .Y(n454) );
NOR2X4TS U754 ( .A(n1634), .B(n1663), .Y(n1176) );
BUFX16TS U755 ( .A(n691), .Y(n2221) );
BUFX6TS U756 ( .A(n600), .Y(n601) );
INVX4TS U757 ( .A(n552), .Y(n553) );
BUFX12TS U758 ( .A(n754), .Y(n881) );
BUFX16TS U759 ( .A(n686), .Y(n2476) );
BUFX12TS U760 ( .A(n654), .Y(n884) );
INVX12TS U761 ( .A(n897), .Y(n406) );
BUFX16TS U762 ( .A(n646), .Y(n786) );
NOR2X6TS U763 ( .A(mult_x_19_n764), .B(n1187), .Y(n1932) );
XNOR2X2TS U764 ( .A(n1761), .B(n870), .Y(n1036) );
BUFX8TS U765 ( .A(n600), .Y(n2313) );
INVX8TS U766 ( .A(n554), .Y(n556) );
INVX8TS U767 ( .A(n613), .Y(n789) );
INVX8TS U768 ( .A(n554), .Y(n555) );
BUFX12TS U769 ( .A(n1293), .Y(n1762) );
NOR2X6TS U770 ( .A(n580), .B(n2964), .Y(n1199) );
NAND2X2TS U771 ( .A(n574), .B(n3005), .Y(n2116) );
NAND2X2TS U772 ( .A(n576), .B(n3042), .Y(n1734) );
XNOR2X2TS U773 ( .A(n728), .B(n639), .Y(n1033) );
XNOR2X2TS U774 ( .A(n1090), .B(n798), .Y(n1027) );
BUFX8TS U775 ( .A(mult_x_19_n52), .Y(n2322) );
BUFX12TS U776 ( .A(mult_x_19_n28), .Y(n2314) );
XNOR2X2TS U777 ( .A(n753), .B(n2794), .Y(n2324) );
OR2X4TS U778 ( .A(n1300), .B(n1162), .Y(n745) );
NAND2X4TS U779 ( .A(n1213), .B(n1848), .Y(n1215) );
NAND2X2TS U780 ( .A(n3118), .B(Op_MY[26]), .Y(n1234) );
NOR2X6TS U781 ( .A(n579), .B(n2978), .Y(n1197) );
BUFX12TS U782 ( .A(n548), .Y(n523) );
INVX12TS U783 ( .A(n918), .Y(n666) );
BUFX4TS U784 ( .A(n727), .Y(n1090) );
BUFX16TS U785 ( .A(n594), .Y(n804) );
INVX4TS U786 ( .A(n624), .Y(n798) );
BUFX12TS U787 ( .A(n623), .Y(n2793) );
NOR2X6TS U788 ( .A(n574), .B(n2975), .Y(n2117) );
OR2X4TS U789 ( .A(n3033), .B(n3034), .Y(n2671) );
BUFX12TS U790 ( .A(n847), .Y(n2048) );
NAND2X4TS U791 ( .A(n2006), .B(n2970), .Y(n474) );
NOR2X4TS U792 ( .A(n1941), .B(n575), .Y(n1213) );
BUFX12TS U793 ( .A(n738), .Y(n548) );
INVX8TS U794 ( .A(n1761), .Y(n2239) );
BUFX6TS U795 ( .A(n1091), .Y(n594) );
INVX12TS U796 ( .A(n627), .Y(n2241) );
INVX12TS U797 ( .A(n2801), .Y(n762) );
INVX6TS U798 ( .A(n638), .Y(n639) );
CLKINVX6TS U799 ( .A(n627), .Y(n628) );
BUFX12TS U800 ( .A(n679), .Y(n2468) );
INVX6TS U801 ( .A(n563), .Y(n2801) );
OAI22X2TS U802 ( .A0(n695), .A1(n2476), .B0(n715), .B1(n786), .Y(n1557) );
ADDFHX2TS U803 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2498), .S(n2493) );
NAND2X6TS U804 ( .A(n2284), .B(n2283), .Y(n2285) );
AND2X6TS U805 ( .A(n2287), .B(n2286), .Y(n2909) );
ADDFHX4TS U806 ( .A(n2043), .B(n2044), .CI(n2042), .CO(n2089), .S(n2103) );
NOR2X2TS U807 ( .A(n2532), .B(n2538), .Y(mult_x_19_n165) );
NAND2X8TS U808 ( .A(n2536), .B(n2535), .Y(mult_x_19_n179) );
NAND2X4TS U809 ( .A(n2681), .B(n266), .Y(n3349) );
OAI22X2TS U810 ( .A0(n677), .A1(n2473), .B0(n2472), .B1(n799), .Y(n2549) );
OAI22X2TS U811 ( .A0(n2041), .A1(n1514), .B0(n801), .B1(n645), .Y(n1595) );
ADDFHX4TS U812 ( .A(n2440), .B(n2439), .CI(n2438), .CO(n2461), .S(n2508) );
OAI2BB1X4TS U813 ( .A0N(n913), .A1N(n1891), .B0(n912), .Y(n2439) );
MX2X4TS U814 ( .A(n2601), .B(P_Sgf[5]), .S0(n424), .Y(n243) );
NAND2X4TS U815 ( .A(n776), .B(n2680), .Y(n3333) );
NAND2X4TS U816 ( .A(n2734), .B(n2690), .Y(n2691) );
NOR2X4TS U817 ( .A(n2716), .B(n2689), .Y(n2690) );
NAND2X8TS U818 ( .A(n531), .B(n3267), .Y(n2680) );
XOR2X4TS U819 ( .A(n2761), .B(n2760), .Y(n2762) );
NAND2X6TS U820 ( .A(n532), .B(n3268), .Y(n531) );
NAND2X8TS U821 ( .A(n455), .B(n3264), .Y(n2678) );
NAND2X8TS U822 ( .A(n501), .B(n3257), .Y(n2685) );
NAND2X8TS U823 ( .A(n441), .B(n3271), .Y(n2684) );
NAND2X6TS U824 ( .A(n2658), .B(n3258), .Y(n501) );
AOI2BB2X4TS U825 ( .B0(n2700), .B1(n263), .A0N(n805), .A1N(n1995), .Y(n1997)
);
MX2X6TS U826 ( .A(n1646), .B(n3240), .S0(n586), .Y(n263) );
NAND2X4TS U827 ( .A(mult_x_19_n555), .B(n2282), .Y(mult_x_19_n114) );
OAI22X2TS U828 ( .A0(n1786), .A1(n2051), .B0(n2307), .B1(n1823), .Y(n1829)
);
NAND3X6TS U829 ( .A(n3180), .B(n3179), .C(n3178), .Y(n2851) );
XOR2X4TS U830 ( .A(n2756), .B(n2755), .Y(n2758) );
XNOR2X4TS U831 ( .A(n615), .B(n2285), .Y(Sgf_operation_Result[7]) );
MXI2X8TS U832 ( .A(n3135), .B(n3107), .S0(n434), .Y(n1267) );
AOI2BB2X4TS U833 ( .B0(n2784), .B1(n267), .A0N(n807), .A1N(n3145), .Y(n3350)
);
ADDFHX4TS U834 ( .A(n1509), .B(n1508), .CI(n1507), .CO(n1522), .S(n2491) );
CLKINVX12TS U835 ( .A(n680), .Y(n1508) );
OAI2BB1X4TS U836 ( .A0N(n2189), .A1N(n2188), .B0(n919), .Y(mult_x_19_n691)
);
ADDFHX2TS U837 ( .A(n1512), .B(n1511), .CI(n1510), .CO(n2501), .S(n2490) );
AO22X4TS U838 ( .A0(n2946), .A1(n622), .B0(n2474), .B1(n3051), .Y(n2475) );
NAND2X4TS U839 ( .A(n2946), .B(n2801), .Y(n483) );
AO22X4TS U840 ( .A0(n2474), .A1(n3095), .B0(n2946), .B1(n733), .Y(n1611) );
INVX8TS U841 ( .A(n462), .Y(n707) );
OAI22X4TS U842 ( .A0(n2312), .A1(n2899), .B0(n1026), .B1(n1016), .Y(n1021)
);
OAI21X2TS U843 ( .A0(n2258), .A1(n2260), .B0(n2214), .Y(n378) );
MXI2X8TS U844 ( .A(n996), .B(n3113), .S0(n434), .Y(n1259) );
BUFX20TS U845 ( .A(FSM_selector_A), .Y(n434) );
NAND2X2TS U846 ( .A(n776), .B(n2640), .Y(n3352) );
NAND2X8TS U847 ( .A(n2640), .B(n502), .Y(n2687) );
AOI21X4TS U848 ( .A0(n2121), .A1(n2120), .B0(n2119), .Y(n2126) );
INVX6TS U849 ( .A(n1968), .Y(n1969) );
OAI21X2TS U850 ( .A0(n766), .A1(n2254), .B0(n2253), .Y(n2255) );
NAND2X8TS U851 ( .A(n1393), .B(n1392), .Y(n2192) );
OAI22X2TS U852 ( .A0(n784), .A1(n1501), .B0(n1514), .B1(n800), .Y(n1519) );
OAI21X4TS U853 ( .A0(n766), .A1(n2653), .B0(n2652), .Y(n2657) );
OAI22X4TS U854 ( .A0(n784), .A1(n1505), .B0(n1501), .B1(n801), .Y(n1509) );
INVX16TS U855 ( .A(n2312), .Y(n989) );
OAI22X4TS U856 ( .A0(n804), .A1(n1092), .B0(n1103), .B1(n2314), .Y(n1126) );
XNOR2X4TS U857 ( .A(n878), .B(n2904), .Y(n1092) );
NAND2X8TS U858 ( .A(n2651), .B(n1217), .Y(n1219) );
OAI22X4TS U859 ( .A0(n1762), .A1(n1028), .B0(n1022), .B1(n757), .Y(n1023) );
NAND2X8TS U860 ( .A(n1402), .B(n1401), .Y(n1968) );
INVX6TS U861 ( .A(n818), .Y(n1586) );
NAND2X2TS U862 ( .A(n2681), .B(n265), .Y(n1671) );
NAND2X4TS U863 ( .A(n1039), .B(n1038), .Y(n2778) );
NAND3X8TS U864 ( .A(n564), .B(n3181), .C(n3182), .Y(n2686) );
NOR2X4TS U865 ( .A(n1197), .B(n1199), .Y(n1201) );
INVX8TS U866 ( .A(n1219), .Y(n432) );
ADDFHX2TS U867 ( .A(n2495), .B(n2494), .CI(n2493), .CO(n2496), .S(
mult_x_19_n626) );
ADDFHX4TS U868 ( .A(n2516), .B(n2515), .CI(n2514), .CO(n2354), .S(n2525) );
NOR2X4TS U869 ( .A(n2281), .B(n2433), .Y(mult_x_19_n465) );
NAND2X8TS U870 ( .A(n528), .B(n3250), .Y(n2638) );
NAND3X4TS U871 ( .A(n2627), .B(n2626), .C(n2625), .Y(n205) );
NAND2X4TS U872 ( .A(mult_x_19_n451), .B(n707), .Y(mult_x_19_n111) );
INVX4TS U873 ( .A(n765), .Y(n1621) );
NAND2X4TS U874 ( .A(n2248), .B(n1369), .Y(n1371) );
OAI21X4TS U875 ( .A0(n2188), .A1(n2189), .B0(n540), .Y(n919) );
NOR2X6TS U876 ( .A(n1259), .B(n1260), .Y(n1423) );
NAND2X4TS U877 ( .A(n2110), .B(n2109), .Y(n2111) );
OAI21X4TS U878 ( .A0(n1847), .A1(n765), .B0(n1846), .Y(n1851) );
INVX8TS U879 ( .A(mult_x_19_n453), .Y(mult_x_19_n451) );
INVX6TS U880 ( .A(n1420), .Y(n1437) );
AOI21X2TS U881 ( .A0(n1929), .A1(n1921), .B0(n1923), .Y(n1652) );
OAI22X4TS U882 ( .A0(n804), .A1(n1103), .B0(n1109), .B1(n2314), .Y(n1141) );
OAI22X2TS U883 ( .A0(n1502), .A1(n667), .B0(n970), .B1(n1513), .Y(n1518) );
NAND2X4TS U884 ( .A(n2265), .B(n3099), .Y(mult_x_19_n109) );
INVX6TS U885 ( .A(n634), .Y(n2265) );
INVX16TS U886 ( .A(n1917), .Y(n2248) );
OAI21X2TS U887 ( .A0(n2118), .A1(n2117), .B0(n2116), .Y(n2119) );
OAI22X2TS U888 ( .A0(n1894), .A1(n509), .B0(n2038), .B1(n744), .Y(n2079) );
ADDFHX4TS U889 ( .A(n2368), .B(n2367), .CI(n2366), .CO(n2413), .S(n2391) );
ADDFHX4TS U890 ( .A(n2420), .B(n2419), .CI(n2418), .CO(n2521), .S(n2412) );
INVX6TS U891 ( .A(n2192), .Y(n2193) );
INVX6TS U892 ( .A(n960), .Y(n982) );
INVX16TS U893 ( .A(n669), .Y(n787) );
OR2X8TS U894 ( .A(n2312), .B(n1161), .Y(n729) );
NAND2X2TS U895 ( .A(n1053), .B(n2598), .Y(n487) );
NAND2X4TS U896 ( .A(n463), .B(n3099), .Y(mult_x_19_n430) );
ADDFHX2TS U897 ( .A(n1132), .B(n1131), .CI(n1130), .CO(n1145), .S(n1977) );
NAND2X4TS U898 ( .A(n519), .B(n632), .Y(mult_x_19_n108) );
NAND2X2TS U899 ( .A(n3102), .B(n978), .Y(n977) );
OAI22X2TS U900 ( .A0(n2051), .A1(n1583), .B0(n499), .B1(n706), .Y(n1590) );
OAI22X2TS U901 ( .A0(n499), .A1(n498), .B0(n2051), .B1(n706), .Y(n1550) );
INVX2TS U902 ( .A(n1493), .Y(n397) );
NAND3BX4TS U903 ( .AN(n397), .B(n1492), .C(n1491), .Y(n222) );
NAND2X4TS U904 ( .A(n2248), .B(n565), .Y(n1484) );
BUFX8TS U905 ( .A(n399), .Y(n429) );
BUFX12TS U906 ( .A(n791), .Y(n969) );
ADDFHX2TS U907 ( .A(n1890), .B(n1888), .CI(n1889), .CO(n2440), .S(n1871) );
CLKINVX12TS U908 ( .A(Op_MY[5]), .Y(n848) );
INVX12TS U909 ( .A(n848), .Y(n398) );
INVX12TS U910 ( .A(n848), .Y(n399) );
INVX2TS U911 ( .A(n401), .Y(n403) );
CLKINVX1TS U912 ( .A(n401), .Y(n405) );
OAI22X2TS U913 ( .A0(n406), .A1(n1110), .B0(n555), .B1(n917), .Y(n1152) );
INVX16TS U914 ( .A(n738), .Y(n897) );
OAI22X4TS U915 ( .A0(n760), .A1(mult_x_19_n1585), .B0(n2073), .B1(n2468),
.Y(n2092) );
OA21X1TS U916 ( .A0(n2664), .A1(n2663), .B0(n2662), .Y(n2665) );
INVX2TS U917 ( .A(n2665), .Y(n408) );
INVX2TS U918 ( .A(n409), .Y(n410) );
NAND2X6TS U919 ( .A(n442), .B(n587), .Y(n441) );
NAND2X6TS U920 ( .A(n456), .B(n587), .Y(n455) );
AO21X1TS U921 ( .A0(n1367), .A1(n581), .B0(n2936), .Y(n1368) );
XNOR2X1TS U922 ( .A(n628), .B(n870), .Y(n1018) );
INVX2TS U923 ( .A(n673), .Y(n674) );
XNOR2X2TS U924 ( .A(n693), .B(n2794), .Y(n1703) );
NAND2X2TS U925 ( .A(n1923), .B(n1189), .Y(n482) );
NOR2X2TS U926 ( .A(n2117), .B(n428), .Y(n637) );
NOR2BX2TS U927 ( .AN(n789), .B(n757), .Y(n1032) );
INVX4TS U928 ( .A(n701), .Y(n799) );
AO21X1TS U929 ( .A0(n768), .A1(n2485), .B0(n2889), .Y(n2545) );
NAND2X1TS U930 ( .A(n3358), .B(n2831), .Y(n2587) );
INVX6TS U931 ( .A(n660), .Y(n519) );
NAND2BX1TS U932 ( .AN(n3151), .B(n2873), .Y(n1277) );
NAND2BX1TS U933 ( .AN(n418), .B(n3242), .Y(n503) );
OA21X4TS U934 ( .A0(n2122), .A1(n2116), .B0(n2123), .Y(n416) );
OR2X8TS U935 ( .A(n510), .B(n505), .Y(n417) );
AND2X8TS U936 ( .A(n1525), .B(n2284), .Y(n422) );
AND2X8TS U937 ( .A(n1410), .B(n1409), .Y(n423) );
NOR2X4TS U938 ( .A(n527), .B(n526), .Y(n3353) );
NAND2X2TS U939 ( .A(n2681), .B(n2680), .Y(n3334) );
NAND2X2TS U940 ( .A(n776), .B(n2684), .Y(n3321) );
NAND2X2TS U941 ( .A(n2679), .B(n2678), .Y(n3314) );
NAND2X2TS U942 ( .A(n2684), .B(n2701), .Y(n3322) );
NAND2X2TS U943 ( .A(n796), .B(n2674), .Y(n3301) );
NAND2X2TS U944 ( .A(n2673), .B(n796), .Y(n3341) );
NAND2X2TS U945 ( .A(n776), .B(n2683), .Y(n3325) );
NAND2X2TS U946 ( .A(n2701), .B(n2673), .Y(n3342) );
NAND2X2TS U947 ( .A(n2681), .B(n2676), .Y(n3338) );
NAND2X2TS U948 ( .A(n2681), .B(n2674), .Y(n3302) );
NAND2X2TS U949 ( .A(n2681), .B(n2683), .Y(n3326) );
NAND2X2TS U950 ( .A(n796), .B(n2676), .Y(n3337) );
NAND2X2TS U951 ( .A(n776), .B(n2699), .Y(n3345) );
NAND2X2TS U952 ( .A(n2679), .B(n2699), .Y(n3346) );
NAND2X6TS U953 ( .A(n439), .B(n438), .Y(n260) );
NAND2X4TS U954 ( .A(n2113), .B(n420), .Y(n439) );
INVX2TS U955 ( .A(n2286), .Y(n1617) );
INVX4TS U956 ( .A(n2537), .Y(n1618) );
NAND2X4TS U957 ( .A(n484), .B(n1051), .Y(n490) );
INVX8TS U958 ( .A(n1647), .Y(n2679) );
OR2X4TS U959 ( .A(n2564), .B(n2563), .Y(n3092) );
INVX8TS U960 ( .A(n1647), .Y(n2681) );
INVX6TS U961 ( .A(n2611), .Y(n2792) );
NOR2X4TS U962 ( .A(n2540), .B(n2539), .Y(mult_x_19_n145) );
MX2X2TS U963 ( .A(n2762), .B(Add_result[22]), .S0(n2771), .Y(n287) );
BUFX20TS U964 ( .A(n425), .Y(n3275) );
MX2X2TS U965 ( .A(n2767), .B(n808), .S0(n2771), .Y(n291) );
MX2X2TS U966 ( .A(n2745), .B(n811), .S0(n2771), .Y(n288) );
MX2X2TS U967 ( .A(n2772), .B(n810), .S0(n2771), .Y(n289) );
INVX8TS U968 ( .A(n425), .Y(n3274) );
MX2X2TS U969 ( .A(n2752), .B(n812), .S0(n2771), .Y(n290) );
INVX4TS U970 ( .A(n353), .Y(n2943) );
BUFX8TS U971 ( .A(n2839), .Y(n2853) );
INVX4TS U972 ( .A(n363), .Y(n2932) );
INVX4TS U973 ( .A(n452), .Y(n450) );
INVX4TS U974 ( .A(mult_x_19_n49), .Y(n2929) );
INVX4TS U975 ( .A(mult_x_19_n19), .Y(n2922) );
INVX4TS U976 ( .A(n344), .Y(n2962) );
BUFX4TS U977 ( .A(n2839), .Y(n2829) );
XNOR2X1TS U978 ( .A(n349), .B(mult_x_19_n593), .Y(n596) );
XOR2X1TS U979 ( .A(mult_x_19_n7), .B(n346), .Y(n2963) );
MX2X2TS U980 ( .A(n2620), .B(Add_result[7]), .S0(n2757), .Y(n302) );
INVX4TS U981 ( .A(n349), .Y(n2925) );
NAND2X8TS U982 ( .A(n535), .B(FS_Module_state_reg[1]), .Y(n1486) );
OR4X4TS U983 ( .A(n252), .B(n253), .C(n254), .D(n251), .Y(n562) );
NAND2X4TS U984 ( .A(n832), .B(n831), .Y(n2046) );
INVX8TS U985 ( .A(n478), .Y(n476) );
INVX6TS U986 ( .A(n1263), .Y(n1242) );
MX2X6TS U987 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n2263), .Y(n349) );
MX2X2TS U988 ( .A(n2196), .B(n3232), .S0(n588), .Y(n253) );
MX2X6TS U989 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n2568), .Y(n363) );
BUFX12TS U990 ( .A(n771), .Y(n3278) );
NAND2X4TS U991 ( .A(n1196), .B(n1274), .Y(n535) );
NAND2X4TS U992 ( .A(n971), .B(n925), .Y(n2546) );
CLKMX2X3TS U993 ( .A(Data_MY[2]), .B(n828), .S0(n2795), .Y(n314) );
CLKMX2X3TS U994 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n2800), .Y(n342) );
CLKMX2X3TS U995 ( .A(Data_MY[4]), .B(n798), .S0(n2795), .Y(n316) );
CLKMX2X3TS U996 ( .A(Data_MY[9]), .B(n762), .S0(n2802), .Y(n321) );
MX2X2TS U997 ( .A(n2597), .B(Add_result[6]), .S0(n2757), .Y(n303) );
NAND2X6TS U998 ( .A(n1175), .B(n1274), .Y(n1003) );
MX2X6TS U999 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n2263), .Y(n355) );
NOR2X4TS U1000 ( .A(n2799), .B(n793), .Y(n534) );
CLKMX2X3TS U1001 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n2800), .Y(n367) );
NAND2X4TS U1002 ( .A(n1256), .B(n1255), .Y(n1412) );
NAND2X4TS U1003 ( .A(n924), .B(n972), .Y(n923) );
MX2X2TS U1004 ( .A(n2194), .B(n3234), .S0(n588), .Y(n252) );
OAI22X2TS U1005 ( .A0(n2219), .A1(n1813), .B0(n2330), .B1(n1744), .Y(n663)
);
NAND2X4TS U1006 ( .A(n896), .B(n709), .Y(n905) );
NAND2X6TS U1007 ( .A(n559), .B(n1944), .Y(n1947) );
NOR2X1TS U1008 ( .A(n2719), .B(n2716), .Y(n2705) );
OAI21X1TS U1009 ( .A0(n2858), .A1(n2617), .B0(n2616), .Y(n2619) );
NAND2X4TS U1010 ( .A(n954), .B(n953), .Y(n2078) );
BUFX4TS U1011 ( .A(n2797), .Y(n2798) );
INVX4TS U1012 ( .A(n1195), .Y(n1196) );
OAI21X1TS U1013 ( .A0(n2858), .A1(n2859), .B0(n2631), .Y(n2596) );
INVX2TS U1014 ( .A(n1923), .Y(n1926) );
AND2X2TS U1015 ( .A(n2213), .B(n1364), .Y(n502) );
INVX8TS U1016 ( .A(n3361), .Y(n770) );
NAND2X2TS U1017 ( .A(n1654), .B(n1924), .Y(n1655) );
INVX2TS U1018 ( .A(n560), .Y(n2373) );
INVX3TS U1019 ( .A(n1325), .Y(n978) );
NAND2X8TS U1020 ( .A(n3119), .B(n1174), .Y(n2258) );
INVX2TS U1021 ( .A(n2108), .Y(n2110) );
INVX2TS U1022 ( .A(n2577), .Y(n2579) );
MX2X2TS U1023 ( .A(n2202), .B(n3230), .S0(n588), .Y(n251) );
INVX2TS U1024 ( .A(n2831), .Y(overflow_flag) );
NAND2X4TS U1025 ( .A(n2842), .B(n2840), .Y(n2689) );
INVX2TS U1026 ( .A(n2843), .Y(n2736) );
NAND2X6TS U1027 ( .A(n2838), .B(n2848), .Y(n2728) );
INVX2TS U1028 ( .A(n2836), .Y(n2729) );
NAND2X4TS U1029 ( .A(n2836), .B(n2845), .Y(n2688) );
NAND2X4TS U1030 ( .A(n2851), .B(n640), .Y(n2631) );
INVX2TS U1031 ( .A(n2854), .Y(n2760) );
INVX2TS U1032 ( .A(n2662), .Y(n1202) );
CLKBUFX2TS U1033 ( .A(Add_result[9]), .Y(n809) );
INVX2TS U1034 ( .A(n2989), .Y(n440) );
NOR2X6TS U1035 ( .A(n3040), .B(n3041), .Y(n1854) );
CLKBUFX2TS U1036 ( .A(Add_result[18]), .Y(n808) );
OR3X6TS U1037 ( .A(n750), .B(n751), .C(n752), .Y(n2847) );
INVX2TS U1038 ( .A(n640), .Y(n641) );
NAND3X4TS U1039 ( .A(n3200), .B(n3199), .C(n3198), .Y(n2850) );
NAND3X4TS U1040 ( .A(n3212), .B(n3211), .C(n3210), .Y(n2843) );
NOR2X4TS U1041 ( .A(exp_oper_result_8_), .B(Exp_module_Overflow_flag_A), .Y(
n2831) );
NAND2X2TS U1042 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n2590) );
CLKBUFX2TS U1043 ( .A(Add_result[20]), .Y(n810) );
NOR2X4TS U1044 ( .A(n576), .B(n2990), .Y(n1733) );
MX2X4TS U1045 ( .A(n731), .B(Op_MX[30]), .S0(n3121), .Y(n699) );
INVX2TS U1046 ( .A(n2903), .Y(n953) );
INVX8TS U1047 ( .A(n612), .Y(n613) );
BUFX8TS U1048 ( .A(n732), .Y(n863) );
INVX2TS U1049 ( .A(n618), .Y(n619) );
INVX6TS U1050 ( .A(n774), .Y(n499) );
CLKBUFX2TS U1051 ( .A(Add_result[19]), .Y(n812) );
NAND2X2TS U1052 ( .A(n2687), .B(n2686), .Y(n3355) );
NAND2X4TS U1053 ( .A(n2260), .B(n964), .Y(n2261) );
INVX8TS U1054 ( .A(mult_x_19_n439), .Y(n463) );
NAND2X2TS U1055 ( .A(n2679), .B(n2628), .Y(n3293) );
NAND3X4TS U1056 ( .A(n1986), .B(n1480), .C(n1739), .Y(n3357) );
NAND2X2TS U1057 ( .A(n776), .B(n2685), .Y(n3317) );
NAND2X2TS U1058 ( .A(n2679), .B(n2685), .Y(n3318) );
NAND2X6TS U1059 ( .A(n938), .B(n939), .Y(n1982) );
NAND2X2TS U1060 ( .A(n2701), .B(n2675), .Y(n3306) );
NAND2X2TS U1061 ( .A(n796), .B(n2639), .Y(n3296) );
NAND3X2TS U1062 ( .A(n1998), .B(n1997), .C(n1996), .Y(n203) );
NAND2X4TS U1063 ( .A(n681), .B(n2679), .Y(n1491) );
NAND2X6TS U1064 ( .A(mult_x_19_n648), .B(mult_x_19_n661), .Y(mult_x_19_n267)
);
NAND2X6TS U1065 ( .A(n472), .B(n585), .Y(n471) );
NAND2X4TS U1066 ( .A(n529), .B(n585), .Y(n528) );
NAND2X6TS U1067 ( .A(n488), .B(n487), .Y(n486) );
NAND2X4TS U1068 ( .A(n1397), .B(n2788), .Y(n1402) );
NAND2X2TS U1069 ( .A(n2268), .B(n2267), .Y(mult_x_19_n115) );
NAND2X2TS U1070 ( .A(mult_x_19_n465), .B(n2437), .Y(mult_x_19_n458) );
INVX4TS U1071 ( .A(mult_x_19_n179), .Y(mult_x_19_n181) );
INVX4TS U1072 ( .A(n2281), .Y(mult_x_19_n555) );
INVX8TS U1073 ( .A(n1966), .Y(n1978) );
XOR2X2TS U1074 ( .A(n875), .B(n2294), .Y(mult_x_19_n810) );
AND2X2TS U1075 ( .A(n2541), .B(mult_x_19_n146), .Y(n2910) );
NAND2X6TS U1076 ( .A(n823), .B(n2185), .Y(n822) );
MX2X4TS U1077 ( .A(n1637), .B(n3243), .S0(n586), .Y(n264) );
NAND2X6TS U1078 ( .A(n490), .B(n489), .Y(n1052) );
MX2X2TS U1079 ( .A(n2867), .B(P_Sgf[4]), .S0(n424), .Y(n242) );
NAND2X4TS U1080 ( .A(n2701), .B(n267), .Y(n2702) );
MX2X2TS U1081 ( .A(n2758), .B(Add_result[23]), .S0(n2757), .Y(n286) );
INVX2TS U1082 ( .A(n2607), .Y(n2609) );
INVX6TS U1083 ( .A(n2598), .Y(n2606) );
AND2X2TS U1084 ( .A(n3092), .B(n2566), .Y(n2911) );
NAND2X6TS U1085 ( .A(n930), .B(n436), .Y(n2348) );
NAND2X6TS U1086 ( .A(n827), .B(n826), .Y(n2296) );
NAND2X2TS U1087 ( .A(n2564), .B(n2563), .Y(n2566) );
MX2X2TS U1088 ( .A(n2782), .B(P_Sgf[3]), .S0(n424), .Y(n241) );
NAND2X6TS U1089 ( .A(n2604), .B(n485), .Y(n484) );
ADDFHX2TS U1090 ( .A(n2402), .B(n2401), .CI(n2400), .CO(mult_x_19_n651), .S(
n1572) );
NAND2X2TS U1091 ( .A(n2540), .B(n2539), .Y(mult_x_19_n146) );
NAND2BX2TS U1092 ( .AN(n591), .B(n2937), .Y(n595) );
NAND2X2TS U1093 ( .A(n720), .B(n719), .Y(n2176) );
INVX8TS U1094 ( .A(n2611), .Y(n2827) );
OAI2BB1X2TS U1095 ( .A0N(n947), .A1N(n1865), .B0(n948), .Y(n2504) );
NAND2X6TS U1096 ( .A(n449), .B(n448), .Y(n2411) );
INVX12TS U1097 ( .A(n3275), .Y(n776) );
INVX8TS U1098 ( .A(n2611), .Y(n2828) );
NAND2X6TS U1099 ( .A(n432), .B(n2667), .Y(n431) );
INVX2TS U1100 ( .A(n1376), .Y(n1379) );
NAND2X4TS U1101 ( .A(n1435), .B(n1434), .Y(n1438) );
INVX4TS U1102 ( .A(n1428), .Y(n1439) );
INVX2TS U1103 ( .A(n1377), .Y(n1378) );
NAND2X6TS U1104 ( .A(n1486), .B(n534), .Y(n1647) );
NAND2X6TS U1105 ( .A(n545), .B(n544), .Y(n739) );
AO22X2TS U1106 ( .A0(n2853), .A1(n2837), .B0(final_result_ieee[7]), .B1(
n2849), .Y(n193) );
AO22X2TS U1107 ( .A0(n2829), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n2855), .Y(n200) );
XOR2X1TS U1108 ( .A(n2939), .B(mult_x_19_n1791), .Y(n3065) );
ADDFHX2TS U1109 ( .A(n1089), .B(n1088), .CI(n1087), .CO(n1144), .S(n1096) );
MX2X2TS U1110 ( .A(n2724), .B(Add_result[15]), .S0(n2771), .Y(n294) );
MX2X2TS U1111 ( .A(n2738), .B(Add_result[12]), .S0(n2757), .Y(n297) );
MX2X2TS U1112 ( .A(n2733), .B(Add_result[11]), .S0(n2757), .Y(n298) );
MX2X2TS U1113 ( .A(n2715), .B(Add_result[13]), .S0(n2757), .Y(n296) );
MX2X2TS U1114 ( .A(n2708), .B(Add_result[14]), .S0(n2757), .Y(n295) );
XOR2X1TS U1115 ( .A(n357), .B(n2567), .Y(n3068) );
AO22X2TS U1116 ( .A0(n2829), .A1(n2846), .B0(final_result_ieee[17]), .B1(
n2849), .Y(n183) );
INVX2TS U1117 ( .A(n1380), .Y(n1382) );
AO22X2TS U1118 ( .A0(n2829), .A1(n2840), .B0(final_result_ieee[15]), .B1(
n2855), .Y(n185) );
AO22X2TS U1119 ( .A0(n2829), .A1(n2842), .B0(final_result_ieee[14]), .B1(
n2849), .Y(n186) );
AO22X2TS U1120 ( .A0(n2829), .A1(n2850), .B0(final_result_ieee[13]), .B1(
n2849), .Y(n187) );
AO22X2TS U1121 ( .A0(n2829), .A1(n2843), .B0(final_result_ieee[12]), .B1(
n2849), .Y(n188) );
AO22X2TS U1122 ( .A0(n2829), .A1(n2845), .B0(final_result_ieee[11]), .B1(
n2849), .Y(n189) );
AO22X2TS U1123 ( .A0(n2853), .A1(n2836), .B0(final_result_ieee[10]), .B1(
n2849), .Y(n190) );
AO22X2TS U1124 ( .A0(n2853), .A1(n2848), .B0(final_result_ieee[9]), .B1(
n2849), .Y(n191) );
AO22X2TS U1125 ( .A0(n2853), .A1(n2838), .B0(final_result_ieee[8]), .B1(
n2849), .Y(n192) );
AO22X2TS U1126 ( .A0(n2853), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n2849), .Y(n194) );
AO22X2TS U1127 ( .A0(n2853), .A1(n664), .B0(final_result_ieee[1]), .B1(n2852), .Y(n199) );
AND2X2TS U1128 ( .A(n2574), .B(n2573), .Y(n2912) );
MX2X2TS U1129 ( .A(n2748), .B(Add_result[17]), .S0(n2771), .Y(n292) );
XOR2X2TS U1130 ( .A(n2707), .B(n2706), .Y(n2708) );
XOR2X2TS U1131 ( .A(n2732), .B(n2731), .Y(n2733) );
OR2X2TS U1132 ( .A(n2572), .B(n2571), .Y(n2574) );
XOR2X2TS U1133 ( .A(n2744), .B(n2743), .Y(n2745) );
INVX6TS U1134 ( .A(n1266), .Y(n1243) );
MX2X2TS U1135 ( .A(n2740), .B(Add_result[16]), .S0(n2771), .Y(n293) );
XOR2X2TS U1136 ( .A(n2710), .B(n2709), .Y(n2711) );
XOR2X2TS U1137 ( .A(n2722), .B(n2721), .Y(n2724) );
XOR2X2TS U1138 ( .A(n2770), .B(n3141), .Y(n2772) );
XOR2X2TS U1139 ( .A(n2714), .B(n2713), .Y(n2715) );
INVX3TS U1140 ( .A(mult_x_19_n7), .Y(n2923) );
NAND2X6TS U1141 ( .A(n979), .B(n977), .Y(n988) );
ADDFHX2TS U1142 ( .A(n1829), .B(n1828), .CI(n1827), .CO(n2135), .S(n1824) );
AO22X2TS U1143 ( .A0(n2839), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n2855), .Y(n180) );
AO22X2TS U1144 ( .A0(n2839), .A1(n2844), .B0(final_result_ieee[19]), .B1(
n2855), .Y(n181) );
AO22X2TS U1145 ( .A0(n2839), .A1(n2841), .B0(final_result_ieee[18]), .B1(
n2855), .Y(n182) );
AO22X2TS U1146 ( .A0(n2839), .A1(n2847), .B0(final_result_ieee[16]), .B1(
n2855), .Y(n184) );
INVX2TS U1147 ( .A(n1403), .Y(n1388) );
XOR2X2TS U1148 ( .A(n2747), .B(n2746), .Y(n2748) );
OR2X6TS U1149 ( .A(n3278), .B(beg_FSM), .Y(n2581) );
MX2X4TS U1150 ( .A(Data_MY[3]), .B(n3112), .S0(n2795), .Y(mult_x_19_n1791)
);
MX2X4TS U1151 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n2802), .Y(mult_x_19_n723)
);
MX2X4TS U1152 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n2791), .Y(n344) );
MX2X4TS U1153 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n2568), .Y(n358) );
INVX2TS U1154 ( .A(n2773), .Y(n2775) );
INVX6TS U1155 ( .A(n1256), .Y(n1230) );
NOR2X2TS U1156 ( .A(n2799), .B(n998), .Y(n1485) );
MX2X4TS U1157 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n2791), .Y(n346) );
CLKMX2X3TS U1158 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n2795), .Y(n343) );
INVX3TS U1159 ( .A(n748), .Y(n2759) );
MX2X6TS U1160 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n2568), .Y(n357) );
INVX2TS U1161 ( .A(n1470), .Y(n1459) );
NAND3X1TS U1162 ( .A(n2723), .B(n3356), .C(FSM_selector_B_1_), .Y(n1374) );
MX2X4TS U1163 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n2263), .Y(mult_x_19_n7)
);
MX2X4TS U1164 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n2791), .Y(
mult_x_19_n593) );
CLKMX2X3TS U1165 ( .A(n2583), .B(Add_result[1]), .S0(n2723), .Y(n308) );
NOR2X8TS U1166 ( .A(n2855), .B(n2587), .Y(n2839) );
CLKMX2X3TS U1167 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n2795), .Y(n381) );
ADDFHX2TS U1168 ( .A(n2238), .B(n1516), .CI(n1515), .CO(n1600), .S(n1521) );
CLKMX2X3TS U1169 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n2795), .Y(n335) );
MX2X4TS U1170 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n2568), .Y(n362) );
MX2X4TS U1171 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n2263), .Y(n350) );
MX2X4TS U1172 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n2795), .Y(n312) );
MX2X4TS U1173 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n2263), .Y(n356) );
MX2X4TS U1174 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n2263), .Y(n353) );
MX2X4TS U1175 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n2568), .Y(n366) );
ADDHX2TS U1176 ( .A(n1069), .B(n1070), .CO(n1084), .S(n1071) );
MX2X4TS U1177 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n2791), .Y(
mult_x_19_n1773) );
MX2X4TS U1178 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n2802), .Y(
mult_x_19_n633) );
CLKMX2X4TS U1179 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n2791), .Y(
mult_x_19_n611) );
CLKMX2X3TS U1180 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n2800), .Y(n338) );
CLKMX2X2TS U1181 ( .A(n2826), .B(zero_flag), .S0(n3356), .Y(n311) );
BUFX8TS U1182 ( .A(n2799), .Y(n777) );
CLKMX2X3TS U1183 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n2798), .Y(n374) );
CLKMX2X3TS U1184 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n2798), .Y(n373) );
CLKMX2X3TS U1185 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n2798), .Y(n372) );
CLKMX2X3TS U1186 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n2798), .Y(n371) );
CLKMX2X3TS U1187 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n2800), .Y(n370) );
CLKMX2X3TS U1188 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n2800), .Y(n369) );
CLKMX2X3TS U1189 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n2800), .Y(n368) );
ADDFHX2TS U1190 ( .A(n1566), .B(n1564), .CI(n1565), .CO(n2402), .S(n1574) );
CLKMX2X3TS U1191 ( .A(Data_MY[12]), .B(n646), .S0(n2802), .Y(n324) );
MX2X4TS U1192 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n2802), .Y(
mult_x_19_n689) );
CLKMX2X3TS U1193 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n2800), .Y(n341) );
CLKMX2X3TS U1194 ( .A(Data_MY[11]), .B(n601), .S0(n2802), .Y(n323) );
CLKMX2X3TS U1195 ( .A(Data_MY[1]), .B(n736), .S0(n2795), .Y(n313) );
CLKMX2X3TS U1196 ( .A(Data_MY[15]), .B(n781), .S0(n2802), .Y(n327) );
BUFX20TS U1197 ( .A(n1003), .Y(n425) );
CLKMX2X3TS U1198 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n2800), .Y(n337) );
CLKMX2X3TS U1199 ( .A(Data_MY[7]), .B(n673), .S0(n2802), .Y(n319) );
CLKMX2X3TS U1200 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n2800), .Y(n340) );
CLKMX2X3TS U1201 ( .A(Data_MY[13]), .B(n686), .S0(n2802), .Y(n325) );
CLKMX2X3TS U1202 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n2800), .Y(n339) );
CLKMX2X3TS U1203 ( .A(Data_MY[6]), .B(n691), .S0(n2802), .Y(n318) );
BUFX12TS U1204 ( .A(n2797), .Y(n2802) );
BUFX16TS U1205 ( .A(n2797), .Y(n2263) );
BUFX16TS U1206 ( .A(n2797), .Y(n2568) );
INVX2TS U1207 ( .A(n661), .Y(n1989) );
NOR2X1TS U1208 ( .A(n2719), .B(n2736), .Y(n2712) );
NOR2X1TS U1209 ( .A(n2719), .B(n2718), .Y(n2720) );
XNOR2X2TS U1210 ( .A(n2195), .B(n2955), .Y(n2196) );
NOR2X6TS U1211 ( .A(n2741), .B(n2753), .Y(n748) );
NAND2BX2TS U1212 ( .AN(ack_FSM), .B(ready), .Y(n2582) );
INVX12TS U1213 ( .A(n770), .Y(n771) );
INVX12TS U1214 ( .A(n666), .Y(n505) );
INVX12TS U1215 ( .A(n1651), .Y(n426) );
NAND2X4TS U1216 ( .A(n509), .B(n744), .Y(n929) );
BUFX16TS U1217 ( .A(n2797), .Y(n2791) );
BUFX8TS U1218 ( .A(n2797), .Y(n2795) );
INVX2TS U1219 ( .A(n2552), .Y(n515) );
INVX2TS U1220 ( .A(n1793), .Y(n851) );
NAND2X4TS U1221 ( .A(n1195), .B(FS_Module_state_reg[1]), .Y(n1175) );
NAND2X6TS U1222 ( .A(n652), .B(n653), .Y(n1354) );
BUFX12TS U1223 ( .A(n1176), .Y(n1921) );
NAND2X1TS U1224 ( .A(n2213), .B(n1364), .Y(n853) );
NAND2X6TS U1225 ( .A(n609), .B(n610), .Y(n1342) );
INVX1TS U1226 ( .A(n2258), .Y(n2259) );
AND2X2TS U1227 ( .A(n2769), .B(n2695), .Y(n2696) );
INVX4TS U1228 ( .A(n2734), .Y(n2719) );
INVX4TS U1229 ( .A(n2769), .Y(n2741) );
NAND2X4TS U1230 ( .A(n2264), .B(n1363), .Y(n3356) );
NAND2X8TS U1231 ( .A(n2213), .B(n2264), .Y(n2797) );
NAND2X6TS U1232 ( .A(n447), .B(n446), .Y(n2235) );
INVX2TS U1233 ( .A(n2641), .Y(n2644) );
OA21X4TS U1234 ( .A0(n1932), .A1(n1924), .B0(n1933), .Y(n1188) );
INVX3TS U1235 ( .A(n1269), .Y(n1247) );
AOI2BB1X2TS U1236 ( .A0N(round_mode[0]), .A1N(round_mode[1]), .B0(n2212),
.Y(n965) );
INVX3TS U1237 ( .A(n1319), .Y(n980) );
INVX8TS U1238 ( .A(n550), .Y(n551) );
NOR2X1TS U1239 ( .A(n2593), .B(Sgf_normalized_result[2]), .Y(n2594) );
INVX6TS U1240 ( .A(n1497), .Y(n1208) );
INVX4TS U1241 ( .A(underflow_flag), .Y(n3358) );
INVX2TS U1242 ( .A(n2716), .Y(n2717) );
INVX2TS U1243 ( .A(n1545), .Y(n1538) );
NOR2X1TS U1244 ( .A(n2729), .B(n2728), .Y(n2730) );
INVX2TS U1245 ( .A(n1925), .Y(n1654) );
NOR2X1TS U1246 ( .A(n2765), .B(n2763), .Y(n2749) );
NOR2X1TS U1247 ( .A(n2753), .B(n2694), .Y(n2695) );
NOR2X4TS U1248 ( .A(n2584), .B(n3120), .Y(n2585) );
INVX2TS U1249 ( .A(n1658), .Y(n1659) );
NAND2X6TS U1250 ( .A(n2264), .B(n2577), .Y(n3361) );
INVX2TS U1251 ( .A(n2642), .Y(n2643) );
INVX2TS U1252 ( .A(n1663), .Y(n1665) );
NAND2X2TS U1253 ( .A(n1193), .B(n1198), .Y(n1194) );
NAND2X4TS U1254 ( .A(n491), .B(n2241), .Y(n1016) );
NAND2X6TS U1255 ( .A(n898), .B(mult_x_19_n4), .Y(n738) );
CLKMX2X2TS U1256 ( .A(round_mode[1]), .B(round_mode[0]), .S0(n2830), .Y(
n2212) );
INVX8TS U1257 ( .A(n2686), .Y(n1228) );
OA21X4TS U1258 ( .A0(n2197), .A1(n3026), .B0(n3027), .Y(n1004) );
NAND2X6TS U1259 ( .A(n1059), .B(n2068), .Y(n662) );
INVX2TS U1260 ( .A(n1854), .Y(n2003) );
CLKINVX6TS U1261 ( .A(n2114), .Y(n428) );
INVX2TS U1262 ( .A(n2117), .Y(n1999) );
NOR2X4TS U1263 ( .A(FS_Module_state_reg[1]), .B(n1938), .Y(n2577) );
INVX2TS U1264 ( .A(n1475), .Y(n1476) );
NAND2X6TS U1265 ( .A(n1182), .B(n578), .Y(n1658) );
INVX12TS U1266 ( .A(n521), .Y(n1642) );
NOR4X2TS U1267 ( .A(n246), .B(n245), .C(P_Sgf[5]), .D(P_Sgf[6]), .Y(n2210)
);
INVX2TS U1268 ( .A(n1197), .Y(n2646) );
INVX6TS U1269 ( .A(n740), .Y(n685) );
NAND3X4TS U1270 ( .A(n3170), .B(n3169), .C(n3168), .Y(n2844) );
NOR2X4TS U1271 ( .A(n568), .B(n2965), .Y(n2660) );
MX2X2TS U1272 ( .A(n3220), .B(n3219), .S0(n3218), .Y(n310) );
NAND3X4TS U1273 ( .A(n3203), .B(n3202), .C(n3201), .Y(n2840) );
BUFX16TS U1274 ( .A(n626), .Y(n870) );
INVX4TS U1275 ( .A(n654), .Y(n655) );
NAND2X4TS U1276 ( .A(n2995), .B(n2996), .Y(n1732) );
INVX6TS U1277 ( .A(n623), .Y(n624) );
NAND3X4TS U1278 ( .A(n3175), .B(n3174), .C(n3173), .Y(n2848) );
INVX2TS U1279 ( .A(Add_result[1]), .Y(n1995) );
NAND2X2TS U1280 ( .A(n580), .B(n3028), .Y(n1198) );
NAND3X4TS U1281 ( .A(n3194), .B(n3193), .C(n3192), .Y(n2836) );
INVX2TS U1282 ( .A(Op_MY[18]), .Y(n2809) );
NAND3X4TS U1283 ( .A(n3209), .B(n3208), .C(n3207), .Y(n2841) );
NAND3X4TS U1284 ( .A(n3215), .B(n3214), .C(n3213), .Y(n2846) );
NAND2X2TS U1285 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n2578) );
NAND3X4TS U1286 ( .A(n3188), .B(n3187), .C(n3186), .Y(n2837) );
OR2X6TS U1287 ( .A(n3024), .B(n572), .Y(n2659) );
AOI21X2TS U1288 ( .A0(n2667), .A1(n2666), .B0(n408), .Y(n2668) );
OR2X8TS U1289 ( .A(n1207), .B(n1206), .Y(n616) );
AOI21X4TS U1290 ( .A0(n2252), .A1(n584), .B0(n571), .Y(n1487) );
NAND2X8TS U1291 ( .A(n1218), .B(n431), .Y(n2252) );
NAND2BX2TS U1292 ( .AN(n2211), .B(n2207), .Y(n967) );
OAI2BB1X4TS U1293 ( .A0N(n1000), .A1N(n1931), .B0(n1930), .Y(n1936) );
XNOR2X4TS U1294 ( .A(n644), .B(n2904), .Y(n1682) );
INVX16TS U1295 ( .A(n2892), .Y(n2237) );
OAI21X4TS U1296 ( .A0(n2296), .A1(n2295), .B0(n2294), .Y(n874) );
OAI21X4TS U1297 ( .A0(n2348), .A1(n2349), .B0(n2347), .Y(n538) );
NAND2X2TS U1298 ( .A(n2422), .B(n2423), .Y(n436) );
OAI22X2TS U1299 ( .A0(n767), .A1(n2036), .B0(n2035), .B1(n2034), .Y(n2098)
);
INVX12TS U1300 ( .A(n2894), .Y(n2013) );
XOR2X4TS U1301 ( .A(n2894), .B(n2221), .Y(n1692) );
NAND2X4TS U1302 ( .A(n2257), .B(n2537), .Y(mult_x_19_n82) );
BUFX20TS U1303 ( .A(n1814), .Y(n500) );
NAND2BX2TS U1304 ( .AN(n914), .B(n1892), .Y(n912) );
OAI21X4TS U1305 ( .A0(n1466), .A1(n1465), .B0(n1464), .Y(n1467) );
OAI22X2TS U1306 ( .A0(n466), .A1(n2048), .B0(n1806), .B1(n2051), .Y(n1805)
);
XNOR2X4TS U1307 ( .A(n492), .B(n2907), .Y(n466) );
NAND2BX4TS U1308 ( .AN(n420), .B(n3239), .Y(n438) );
OAI22X4TS U1309 ( .A0(n2051), .A1(n2050), .B0(n2049), .B1(n2048), .Y(n2086)
);
OAI22X4TS U1310 ( .A0(n1164), .A1(n756), .B0(n1116), .B1(n1796), .Y(n1156)
);
INVX6TS U1311 ( .A(n2122), .Y(n2124) );
OAI21X4TS U1312 ( .A0(n1728), .A1(n1727), .B0(n1726), .Y(n872) );
NOR2X8TS U1313 ( .A(n2621), .B(n430), .Y(n2641) );
NOR2BX4TS U1314 ( .AN(n440), .B(n2988), .Y(n2621) );
XNOR2X4TS U1315 ( .A(n443), .B(n2672), .Y(n442) );
OAI21X4TS U1316 ( .A0(n766), .A1(n2669), .B0(n2668), .Y(n443) );
INVX12TS U1317 ( .A(n2905), .Y(n1807) );
OAI21X4TS U1318 ( .A0(n714), .A1(n2793), .B0(n444), .Y(n1808) );
NAND2X2TS U1319 ( .A(n696), .B(n2905), .Y(n444) );
OAI21X4TS U1320 ( .A0(n1732), .A1(n1733), .B0(n1734), .Y(n2642) );
XOR2X4TS U1321 ( .A(n2235), .B(n887), .Y(n886) );
OAI22X4TS U1322 ( .A0(n1759), .A1(n804), .B0(n2224), .B1(n2223), .Y(n887) );
XOR2X4TS U1323 ( .A(n2894), .B(n762), .Y(n2224) );
XNOR2X4TS U1324 ( .A(n688), .B(n654), .Y(n899) );
OR2X8TS U1325 ( .A(n2240), .B(n734), .Y(n447) );
XNOR2X4TS U1326 ( .A(n688), .B(n1869), .Y(n2240) );
OAI21X4TS U1327 ( .A0(n2387), .A1(n450), .B0(n2386), .Y(n449) );
XNOR2X4TS U1328 ( .A(n451), .B(n2386), .Y(n2407) );
XOR2X4TS U1329 ( .A(n2387), .B(n452), .Y(n451) );
NOR2X8TS U1330 ( .A(n454), .B(n453), .Y(n452) );
XNOR2X4TS U1331 ( .A(n457), .B(n1499), .Y(n456) );
OAI21X4TS U1332 ( .A0(n765), .A1(n459), .B0(n458), .Y(n457) );
AOI21X4TS U1333 ( .A0(n2667), .A1(n1496), .B0(n1495), .Y(n458) );
NAND2X2TS U1334 ( .A(n2661), .B(n1496), .Y(n459) );
XOR2X4TS U1335 ( .A(n2894), .B(n671), .Y(n1759) );
AOI21X4TS U1336 ( .A0(mult_x_19_n453), .A1(n3101), .B0(n697), .Y(n2913) );
OAI21X4TS U1337 ( .A0(n1764), .A1(n1765), .B0(n1763), .Y(n952) );
OAI22X4TS U1338 ( .A0(n1108), .A1(n804), .B0(n460), .B1(n2223), .Y(n1153) );
OAI22X4TS U1339 ( .A0(n1693), .A1(n2314), .B0(n460), .B1(n838), .Y(n546) );
XOR2X4TS U1340 ( .A(n2894), .B(n2793), .Y(n460) );
NAND2X8TS U1341 ( .A(n707), .B(n3101), .Y(mult_x_19_n439) );
NOR2X8TS U1342 ( .A(n1971), .B(n1970), .Y(n461) );
NOR2X8TS U1343 ( .A(n1965), .B(n1964), .Y(n462) );
BUFX12TS U1344 ( .A(n758), .Y(n464) );
XOR2X4TS U1345 ( .A(n2904), .B(n465), .Y(n1099) );
OAI22X4TS U1346 ( .A0(n2051), .A1(n466), .B0(n1786), .B1(n499), .Y(n1789) );
OAI2BB1X4TS U1347 ( .A0N(n2018), .A1N(n469), .B0(n467), .Y(n1791) );
OAI21X4TS U1348 ( .A0(n2018), .A1(n469), .B0(n2017), .Y(n467) );
XOR2X4TS U1349 ( .A(n468), .B(n2017), .Y(n2088) );
XOR2X4TS U1350 ( .A(n2018), .B(n469), .Y(n468) );
OAI22X4TS U1351 ( .A0(n678), .A1(n2016), .B0(n2322), .B1(n1772), .Y(n469) );
NAND2X8TS U1352 ( .A(mult_x_19_n52), .B(n470), .Y(n1283) );
XOR2X4TS U1353 ( .A(n625), .B(n618), .Y(n470) );
OAI21X4TS U1354 ( .A0(n766), .A1(n1484), .B0(n820), .Y(n473) );
NAND2X8TS U1355 ( .A(n471), .B(n3252), .Y(n2628) );
XOR2X4TS U1356 ( .A(n473), .B(n2917), .Y(n472) );
NAND2X8TS U1357 ( .A(n474), .B(n1004), .Y(n480) );
NAND2X6TS U1358 ( .A(n1006), .B(n2115), .Y(n481) );
NAND4X8TS U1359 ( .A(n477), .B(n1188), .C(n475), .D(n482), .Y(n2670) );
NAND3X8TS U1360 ( .A(n426), .B(n476), .C(n1931), .Y(n475) );
NAND3X8TS U1361 ( .A(n479), .B(n416), .C(n481), .Y(n1931) );
OR2X8TS U1362 ( .A(n1632), .B(n478), .Y(n477) );
NAND2X8TS U1363 ( .A(n1921), .B(n1189), .Y(n478) );
AOI21X4TS U1364 ( .A0(n1988), .A1(n1181), .B0(n1180), .Y(n1632) );
NAND2X8TS U1365 ( .A(n1987), .B(n1181), .Y(n1651) );
OAI21X4TS U1366 ( .A0(n715), .A1(n671), .B0(n483), .Y(n2156) );
NAND2X8TS U1367 ( .A(n486), .B(n422), .Y(n939) );
OR2X8TS U1368 ( .A(n1080), .B(n1079), .Y(n1525) );
NAND2X1TS U1369 ( .A(n1051), .B(n1050), .Y(n2608) );
NAND3X2TS U1370 ( .A(n1049), .B(n1048), .C(n1050), .Y(n489) );
NOR2X8TS U1371 ( .A(n2607), .B(n2605), .Y(n1053) );
CLKINVX6TS U1372 ( .A(n2904), .Y(n491) );
OAI2BB1X4TS U1373 ( .A0N(n2107), .A1N(n2106), .B0(n493), .Y(mult_x_19_n763)
);
OAI21X4TS U1374 ( .A0(n2106), .A1(n2107), .B0(n2105), .Y(n493) );
OAI21X4TS U1375 ( .A0(n2298), .A1(n2299), .B0(n2297), .Y(n494) );
NAND2BX4TS U1376 ( .AN(n967), .B(n496), .Y(n966) );
NOR3X6TS U1377 ( .A(n260), .B(P_Sgf[0]), .C(n259), .Y(n496) );
OAI22X4TS U1378 ( .A0(n543), .A1(n2048), .B0(n1684), .B1(n1300), .Y(n1688)
);
XNOR2X4TS U1379 ( .A(n2237), .B(n2793), .Y(n543) );
OAI21X4TS U1380 ( .A0(n1782), .A1(n1781), .B0(n891), .Y(n889) );
NOR2X4TS U1381 ( .A(n2579), .B(n2578), .Y(ready) );
OAI21X2TS U1382 ( .A0(n3354), .A1(n3119), .B0(FS_Module_state_reg[3]), .Y(
n2790) );
BUFX12TS U1383 ( .A(n797), .Y(n497) );
XNOR2X4TS U1384 ( .A(n867), .B(n1761), .Y(n1164) );
XOR2X4TS U1385 ( .A(n630), .B(n621), .Y(n1705) );
OAI22X4TS U1386 ( .A0(n2309), .A1(n2310), .B0(n2308), .B1(n2307), .Y(n2364)
);
NAND4BX4TS U1387 ( .AN(n423), .B(n1447), .C(n1968), .D(n2192), .Y(n1480) );
NAND2X8TS U1388 ( .A(n854), .B(n3253), .Y(n2640) );
XOR2X4TS U1389 ( .A(n2422), .B(n2423), .Y(n931) );
AOI21X4TS U1390 ( .A0(n1469), .A1(n1461), .B0(n1463), .Y(n1399) );
OAI21X4TS U1391 ( .A0(n504), .A1(n586), .B0(n503), .Y(n262) );
XOR2X4TS U1392 ( .A(n1994), .B(n1993), .Y(n504) );
INVX16TS U1393 ( .A(n1283), .Y(n675) );
NAND3X4TS U1394 ( .A(n2614), .B(n2613), .C(n2612), .Y(n202) );
OAI22X4TS U1395 ( .A0(n2151), .A1(n1289), .B0(n1282), .B1(n505), .Y(n1286)
);
NAND2X8TS U1396 ( .A(n506), .B(n744), .Y(n918) );
XOR2X4TS U1397 ( .A(n635), .B(n759), .Y(n506) );
OAI2BB1X4TS U1398 ( .A0N(n1298), .A1N(n1297), .B0(n507), .Y(n611) );
OAI21X4TS U1399 ( .A0(n1297), .A1(n1298), .B0(n1296), .Y(n507) );
XOR2X4TS U1400 ( .A(n508), .B(n1291), .Y(n1296) );
XOR2X4TS U1401 ( .A(n1290), .B(n941), .Y(n508) );
OAI22X4TS U1402 ( .A0(n1308), .A1(n548), .B0(n555), .B1(n2947), .Y(n941) );
XNOR2X4TS U1403 ( .A(n3095), .B(n511), .Y(n1513) );
OAI22X4TS U1404 ( .A0(n505), .A1(n991), .B0(n2151), .B1(n1543), .Y(n1554) );
OAI22X4TS U1405 ( .A0(n1556), .A1(n2151), .B0(n509), .B1(n1543), .Y(n1565)
);
OAI22X4TS U1406 ( .A0(n1556), .A1(n505), .B0(n2151), .B1(n2484), .Y(n518) );
OAI22X4TS U1407 ( .A0(n1504), .A1(n2151), .B0(n509), .B1(n2483), .Y(n2467)
);
OAI22X4TS U1408 ( .A0(n2152), .A1(n2151), .B0(n505), .B1(n2153), .Y(n922) );
OAI22X4TS U1409 ( .A0(n726), .A1(n970), .B0(n509), .B1(n2038), .Y(n2097) );
OAI22X4TS U1410 ( .A0(n1597), .A1(n970), .B0(n1513), .B1(n509), .Y(n1596) );
OAI22X4TS U1411 ( .A0(n744), .A1(n510), .B0(n505), .B1(n1779), .Y(n1833) );
XOR2X4TS U1412 ( .A(n867), .B(n511), .Y(n510) );
INVX12TS U1413 ( .A(n791), .Y(n511) );
XOR2X4TS U1414 ( .A(n2182), .B(n512), .Y(n2169) );
XOR2X4TS U1415 ( .A(n2183), .B(n2184), .Y(n512) );
INVX2TS U1416 ( .A(n518), .Y(n516) );
XOR2X4TS U1417 ( .A(n2552), .B(n518), .Y(n517) );
NAND2X4TS U1418 ( .A(n2348), .B(n2349), .Y(n537) );
NOR2X8TS U1419 ( .A(n520), .B(n1215), .Y(n1217) );
NOR2X2TS U1420 ( .A(n1940), .B(n520), .Y(n1845) );
OAI21X1TS U1421 ( .A0(n1948), .A1(n520), .B0(n558), .Y(n1844) );
NAND2X8TS U1422 ( .A(n2655), .B(n616), .Y(n520) );
OR2X8TS U1423 ( .A(n2971), .B(n577), .Y(n521) );
AOI21X4TS U1424 ( .A0(n1498), .A1(n1209), .B0(n1208), .Y(n1210) );
NAND2X4TS U1425 ( .A(n1206), .B(n1207), .Y(n1497) );
NAND2BX4TS U1426 ( .AN(n1207), .B(n522), .Y(n1498) );
CLKINVX6TS U1427 ( .A(n1206), .Y(n522) );
OAI22X4TS U1428 ( .A0(n406), .A1(n1054), .B0(n556), .B1(n942), .Y(n1065) );
OAI22X4TS U1429 ( .A0(n523), .A1(n1033), .B0(n553), .B1(n1027), .Y(n1042) );
OAI22X4TS U1430 ( .A0(n1111), .A1(n523), .B0(n556), .B1(n1110), .Y(n1112) );
OAI22X4TS U1431 ( .A0(n1111), .A1(n553), .B0(n523), .B1(n1102), .Y(n1127) );
AND2X8TS U1432 ( .A(n1078), .B(n1077), .Y(n1523) );
OR2X6TS U1433 ( .A(n988), .B(n525), .Y(n708) );
NAND2X2TS U1434 ( .A(n988), .B(n525), .Y(n987) );
OAI22X4TS U1435 ( .A0(n764), .A1(n992), .B0(n993), .B1(n1674), .Y(n525) );
AOI2BB2X4TS U1436 ( .B0(n2638), .B1(n2700), .A0N(n806), .A1N(n3122), .Y(
n3290) );
XOR2X4TS U1437 ( .A(n530), .B(n2919), .Y(n529) );
OAI21X4TS U1438 ( .A0(n766), .A1(n1221), .B0(n1220), .Y(n530) );
OAI21X4TS U1439 ( .A0(n3098), .A1(n870), .B0(n715), .Y(n1295) );
OAI21X4TS U1440 ( .A0(n1663), .A1(n1658), .B0(n1664), .Y(n1923) );
NOR2X8TS U1441 ( .A(n1184), .B(n1183), .Y(n1663) );
XOR2X4TS U1442 ( .A(n2890), .B(n2801), .Y(n894) );
AOI2BB2X4TS U1443 ( .B0(n2680), .B1(n1483), .A0N(n807), .A1N(n3133), .Y(
n3339) );
XNOR2X4TS U1444 ( .A(n533), .B(n1194), .Y(n532) );
OAI21X4TS U1445 ( .A0(n766), .A1(n1192), .B0(n1191), .Y(n533) );
NOR2X8TS U1446 ( .A(n1186), .B(n1185), .Y(n1925) );
NAND2X8TS U1447 ( .A(n1482), .B(FS_Module_state_reg[1]), .Y(n2799) );
OAI2BB1X4TS U1448 ( .A0N(n2354), .A1N(n2353), .B0(n536), .Y(n2359) );
OAI21X4TS U1449 ( .A0(n2353), .A1(n2354), .B0(n857), .Y(n536) );
NAND2X6TS U1450 ( .A(n538), .B(n537), .Y(n857) );
XNOR2X4TS U1451 ( .A(n539), .B(n2378), .Y(n620) );
XNOR2X4TS U1452 ( .A(n2377), .B(n2379), .Y(n539) );
XOR2X4TS U1453 ( .A(n540), .B(n2189), .Y(n920) );
NAND2X8TS U1454 ( .A(n822), .B(n846), .Y(n540) );
OAI22X4TS U1455 ( .A0(n783), .A1(n541), .B0(n1883), .B1(n2479), .Y(n1892) );
OAI22X4TS U1456 ( .A0(n783), .A1(n975), .B0(n2479), .B1(n541), .Y(n1291) );
XOR2X4TS U1457 ( .A(n398), .B(n542), .Y(n541) );
OAI22X4TS U1458 ( .A0(n1704), .A1(n2307), .B0(n437), .B1(n543), .Y(n1709) );
OAI21X4TS U1459 ( .A0(n1690), .A1(n1691), .B0(n546), .Y(n545) );
XOR2X4TS U1460 ( .A(n547), .B(n546), .Y(n1909) );
XOR2X4TS U1461 ( .A(n1690), .B(n1691), .Y(n547) );
XNOR2X4TS U1462 ( .A(n706), .B(n839), .Y(n944) );
OAI2BB1X1TS U1463 ( .A0N(n658), .A1N(n1898), .B0(n946), .Y(mult_x_19_n853)
);
ADDHX4TS U1464 ( .A(n1357), .B(n1358), .CO(n1312), .S(n2301) );
OAI21X4TS U1465 ( .A0(n1306), .A1(n667), .B0(n923), .Y(n1358) );
INVX6TS U1466 ( .A(n1305), .Y(n924) );
NOR2BX4TS U1467 ( .AN(n789), .B(n2485), .Y(n1154) );
NAND2X4TS U1468 ( .A(n1008), .B(n1007), .Y(n1178) );
CLKINVX6TS U1469 ( .A(n1500), .Y(n550) );
OAI22X2TS U1470 ( .A0(n804), .A1(n1675), .B0(n1759), .B1(n590), .Y(n1757) );
OAI22X2TS U1471 ( .A0(n804), .A1(n2224), .B0(n2321), .B1(n2314), .Y(n2368)
);
XNOR2X4TS U1472 ( .A(n2052), .B(n671), .Y(n1117) );
NOR2X6TS U1473 ( .A(n562), .B(n966), .Y(n860) );
AOI21X4TS U1474 ( .A0(n2671), .A1(n1202), .B0(n3100), .Y(n1203) );
CLKINVX12TS U1475 ( .A(n862), .Y(n554) );
ADDFHX2TS U1476 ( .A(n1902), .B(n1901), .CI(n1900), .CO(mult_x_19_n851), .S(
mult_x_19_n852) );
OR2X4TS U1477 ( .A(n970), .B(n2153), .Y(n557) );
NAND2X8TS U1478 ( .A(n417), .B(n557), .Y(n2160) );
INVX2TS U1479 ( .A(n1987), .Y(n1990) );
NOR2X6TS U1480 ( .A(n2108), .B(n1179), .Y(n1987) );
AOI21X4TS U1481 ( .A0(n1209), .A1(n1498), .B0(n1208), .Y(n558) );
XNOR2X4TS U1482 ( .A(n2898), .B(n839), .Y(n1714) );
XNOR2X4TS U1483 ( .A(n1372), .B(n421), .Y(n1373) );
NAND2X4TS U1484 ( .A(n850), .B(n849), .Y(n2012) );
OAI21X2TS U1485 ( .A0(n2112), .A1(n1641), .B0(n1640), .Y(n1645) );
AOI21X2TS U1486 ( .A0(n661), .A1(n1992), .B0(n1639), .Y(n1640) );
ADDFHX4TS U1487 ( .A(n1725), .B(n1724), .CI(n1723), .CO(n1717), .S(n1911) );
NAND2BX2TS U1488 ( .AN(n613), .B(n561), .Y(n560) );
BUFX16TS U1489 ( .A(mult_x_19_n58), .Y(n855) );
OAI22X4TS U1490 ( .A0(n1714), .A1(n790), .B0(mult_x_19_n1687), .B1(n1813),
.Y(n1724) );
OAI22X4TS U1491 ( .A0(n2055), .A1(n1713), .B0(n1712), .B1(n1014), .Y(n1725)
);
OAI22X4TS U1492 ( .A0(n803), .A1(n2321), .B0(n2320), .B1(n2223), .Y(n2387)
);
OAI22X2TS U1493 ( .A0(n760), .A1(n2326), .B0(n2325), .B1(n1674), .Y(n2386)
);
NAND2X4TS U1494 ( .A(mult_x_19_n995), .B(mult_x_19_n1010), .Y(mult_x_19_n418) );
NAND2X4TS U1495 ( .A(n572), .B(n3003), .Y(n2662) );
OAI21X1TS U1496 ( .A0(n583), .A1(n575), .B0(n3029), .Y(n1212) );
NOR2X6TS U1497 ( .A(n1182), .B(n578), .Y(n1634) );
XNOR2X1TS U1498 ( .A(n582), .B(n2993), .Y(n2205) );
NAND2X2TS U1499 ( .A(n1534), .B(n583), .Y(n1535) );
NAND2X1TS U1500 ( .A(n584), .B(n3048), .Y(n1918) );
XOR2X4TS U1501 ( .A(n765), .B(n2623), .Y(n2624) );
CLKMX2X2TS U1502 ( .A(n3228), .B(n3227), .S0(n588), .Y(n246) );
CLKMX2X2TS U1503 ( .A(n3172), .B(n3171), .S0(n588), .Y(n245) );
CLKMX2X4TS U1504 ( .A(n1860), .B(n3238), .S0(n589), .Y(n257) );
CLKMX2X2TS U1505 ( .A(n2200), .B(n3236), .S0(n589), .Y(n254) );
CLKMX2X2TS U1506 ( .A(n2005), .B(n3235), .S0(n589), .Y(n256) );
CLKMX2X2TS U1507 ( .A(n2009), .B(n3233), .S0(n589), .Y(n255) );
CLKMX2X2TS U1508 ( .A(n1013), .B(n3241), .S0(n589), .Y(n261) );
CLKMX2X4TS U1509 ( .A(n2002), .B(n3249), .S0(n589), .Y(n258) );
NAND2X4TS U1510 ( .A(n2534), .B(n2533), .Y(mult_x_19_n198) );
NAND2X2TS U1511 ( .A(mult_x_19_n764), .B(n1187), .Y(n1933) );
NOR2X6TS U1512 ( .A(n2985), .B(n2986), .Y(n1941) );
NAND2X1TS U1513 ( .A(n2622), .B(n1732), .Y(n2623) );
OAI21X4TS U1514 ( .A0(n765), .A1(n2621), .B0(n1732), .Y(n1737) );
INVX2TS U1515 ( .A(n2621), .Y(n2622) );
XNOR2X4TS U1516 ( .A(n2237), .B(n732), .Y(n1822) );
XOR2X4TS U1517 ( .A(n692), .B(n2237), .Y(n945) );
XNOR2X4TS U1518 ( .A(n2237), .B(n650), .Y(n1806) );
INVX4TS U1519 ( .A(n650), .Y(n651) );
OAI22X4TS U1520 ( .A0(n1300), .A1(n2308), .B0(mult_x_19_n1635), .B1(n2307),
.Y(n2336) );
OR2X4TS U1521 ( .A(n1684), .B(n2048), .Y(n746) );
XNOR2X4TS U1522 ( .A(n706), .B(n671), .Y(n2309) );
INVX4TS U1523 ( .A(n355), .Y(n3046) );
NAND2BX2TS U1524 ( .AN(n2904), .B(n706), .Y(n1100) );
CLKINVX12TS U1525 ( .A(mult_x_19_n28), .Y(n592) );
XOR2X2TS U1526 ( .A(n2943), .B(n352), .Y(n591) );
XNOR2X4TS U1527 ( .A(mult_x_19_n19), .B(n352), .Y(n2937) );
OAI2BB2X2TS U1528 ( .B0(n594), .B1(n705), .A0N(n592), .A1N(n593), .Y(n2157)
);
BUFX16TS U1529 ( .A(n804), .Y(n838) );
OAI22X4TS U1530 ( .A0(n803), .A1(n1821), .B0(n590), .B1(n445), .Y(n2149) );
OAI2BB1X1TS U1531 ( .A0N(n594), .A1N(n2314), .B0(n593), .Y(n1585) );
OAI22X4TS U1532 ( .A0(n1685), .A1(n785), .B0(n1705), .B1(n555), .Y(n1679) );
OAI22X4TS U1533 ( .A0(n1019), .A1(n406), .B0(n1054), .B1(n555), .Y(n1067) );
ADDFHX4TS U1534 ( .A(n2246), .B(n2245), .CI(n2244), .CO(n2377), .S(n1985) );
OAI2BB2X4TS U1535 ( .B0(n556), .B1(mult_x_19_n1749), .A0N(n704), .A1N(n897),
.Y(n1314) );
XNOR2X4TS U1536 ( .A(n878), .B(n881), .Y(n1867) );
BUFX20TS U1537 ( .A(n2895), .Y(n878) );
BUFX4TS U1538 ( .A(n1861), .Y(n682) );
XOR2X2TS U1539 ( .A(n464), .B(n647), .Y(n1301) );
INVX16TS U1540 ( .A(n714), .Y(n2474) );
OAI21X4TS U1541 ( .A0(n766), .A1(n1629), .B0(n1628), .Y(n999) );
AOI21X2TS U1542 ( .A0(n2667), .A1(n1627), .B0(n1626), .Y(n1628) );
OAI22X4TS U1543 ( .A0(n1100), .A1(n499), .B0(n2891), .B1(n2051), .Y(n1120)
);
OAI22X4TS U1544 ( .A0(n2330), .A1(n2896), .B0(n2068), .B1(n1062), .Y(n1069)
);
OAI22X4TS U1545 ( .A0(n768), .A1(mult_x_19_n1603), .B0(n1819), .B1(n2034),
.Y(n1835) );
OAI21X4TS U1546 ( .A0(n766), .A1(n1952), .B0(n1951), .Y(n1954) );
OAI22X2TS U1547 ( .A0(n1807), .A1(n600), .B0(n715), .B1(n2908), .Y(n1549) );
OR2X6TS U1548 ( .A(n1713), .B(n1014), .Y(n730) );
OAI2BB2X4TS U1549 ( .B0(n769), .B1(n2332), .A0N(n602), .A1N(n608), .Y(n2337)
);
OAI22X2TS U1550 ( .A0(n743), .A1(n1819), .B0(n1818), .B1(n842), .Y(n2142) );
AND2X8TS U1551 ( .A(n939), .B(n938), .Y(n603) );
NAND2X2TS U1552 ( .A(n776), .B(n2677), .Y(n3329) );
INVX12TS U1553 ( .A(n735), .Y(n756) );
AOI2BB2X4TS U1554 ( .B0(n607), .B1(n608), .A0N(n986), .A1N(n742), .Y(n606)
);
OR2X4TS U1555 ( .A(n2314), .B(n1344), .Y(n610) );
NAND2X4TS U1556 ( .A(n3004), .B(n1005), .Y(n2123) );
AOI21X4TS U1557 ( .A0(n2121), .A1(n2114), .B0(n2115), .Y(n2001) );
NOR2X8TS U1558 ( .A(n1855), .B(n1854), .Y(n2114) );
NAND2X2TS U1559 ( .A(n2681), .B(n2677), .Y(n3330) );
INVX12TS U1560 ( .A(n759), .Y(n1281) );
NOR2X4TS U1561 ( .A(n1797), .B(n744), .Y(n643) );
ADDFHX4TS U1562 ( .A(n2376), .B(n2374), .CI(n2375), .CO(n2418), .S(n2381) );
OAI22X2TS U1563 ( .A0(n1762), .A1(n2240), .B0(n2306), .B1(n757), .Y(n2375)
);
ADDHX4TS U1564 ( .A(n1044), .B(n1045), .CO(n1046), .S(n1039) );
OAI22X4TS U1565 ( .A0(n1762), .A1(n1036), .B0(n1035), .B1(n757), .Y(n1044)
);
AND2X8TS U1566 ( .A(n936), .B(n933), .Y(n614) );
AO21X4TS U1567 ( .A0(n2598), .A1(n1053), .B0(n1052), .Y(n615) );
BUFX20TS U1568 ( .A(n1288), .Y(n2312) );
NAND2X8TS U1569 ( .A(n1015), .B(n1014), .Y(n1288) );
AOI21X2TS U1570 ( .A0(n2667), .A1(n1845), .B0(n1844), .Y(n1846) );
XOR2X4TS U1571 ( .A(n1859), .B(n1858), .Y(n1860) );
BUFX20TS U1572 ( .A(n698), .Y(n617) );
XNOR2X2TS U1573 ( .A(n464), .B(n755), .Y(n1786) );
XNOR2X2TS U1574 ( .A(n758), .B(n2476), .Y(n1345) );
XNOR2X2TS U1575 ( .A(n758), .B(n1869), .Y(n2050) );
OAI21X2TS U1576 ( .A0(n2146), .A1(n721), .B0(n2145), .Y(n720) );
NAND2X2TS U1577 ( .A(n2609), .B(n2608), .Y(n2610) );
AOI2BB2X2TS U1578 ( .B0(n2700), .B1(n2639), .A0N(n807), .A1N(n3124), .Y(
n3299) );
NAND2X4TS U1579 ( .A(n702), .B(n897), .Y(n896) );
ADDFHX4TS U1580 ( .A(n1590), .B(n1589), .CI(n1588), .CO(n1593), .S(n2174) );
ADDFHX2TS U1581 ( .A(n1086), .B(n1085), .CI(n1084), .CO(n1976), .S(n1094) );
XNOR2X4TS U1582 ( .A(n2052), .B(n691), .Y(n1083) );
OAI22X4TS U1583 ( .A0(n2318), .A1(n2306), .B0(n2317), .B1(n757), .Y(n2365)
);
ADDFHX4TS U1584 ( .A(n2305), .B(n2304), .CI(n2303), .CO(n2300), .S(n2423) );
NOR2X6TS U1585 ( .A(n1925), .B(n1932), .Y(n1189) );
NAND2XLTS U1586 ( .A(n616), .B(n1497), .Y(n1499) );
NOR2X8TS U1587 ( .A(n2969), .B(n1205), .Y(n1494) );
ADDFHX4TS U1588 ( .A(n1141), .B(n1140), .CI(n1139), .CO(n1134), .S(n1974) );
OAI22X2TS U1589 ( .A0(n1796), .A1(n1105), .B0(n1117), .B1(n734), .Y(n1139)
);
INVX16TS U1590 ( .A(n675), .Y(n677) );
OAI22X4TS U1591 ( .A0(n676), .A1(n1582), .B0(n799), .B1(n1552), .Y(n1587) );
OAI22X4TS U1592 ( .A0(n2041), .A1(n2039), .B0(n2015), .B1(n2479), .Y(n2043)
);
BUFX20TS U1593 ( .A(n783), .Y(n2041) );
MXI2X8TS U1594 ( .A(n1479), .B(n1478), .S0(n427), .Y(n1739) );
NOR2X4TS U1595 ( .A(n1376), .B(n1245), .Y(n1448) );
NAND2X2TS U1596 ( .A(n3118), .B(Op_MY[24]), .Y(n1227) );
INVX2TS U1597 ( .A(n991), .Y(n819) );
NAND2X2TS U1598 ( .A(n3118), .B(Op_MY[27]), .Y(n1224) );
NAND2X2TS U1599 ( .A(n3118), .B(Op_MY[28]), .Y(n1225) );
INVX2TS U1600 ( .A(n1366), .Y(n1369) );
CLKINVX12TS U1601 ( .A(n662), .Y(n901) );
INVX6TS U1602 ( .A(n686), .Y(n687) );
NOR2X2TS U1603 ( .A(FS_Module_state_reg[2]), .B(n3120), .Y(n1362) );
NAND2X2TS U1604 ( .A(n3118), .B(Op_MY[25]), .Y(n1233) );
ADDFHX2TS U1605 ( .A(n638), .B(n2796), .CI(n1808), .CO(n1803), .S(n2045) );
INVX2TS U1606 ( .A(n1463), .Y(n1466) );
NAND2X2TS U1607 ( .A(n1243), .B(n1265), .Y(n1244) );
NOR2X4TS U1608 ( .A(n1263), .B(n1264), .Y(n1387) );
NAND2X2TS U1609 ( .A(n3118), .B(Op_MY[29]), .Y(n1226) );
NOR2X4TS U1610 ( .A(n1246), .B(n1267), .Y(n1452) );
NAND2X4TS U1611 ( .A(n1254), .B(n1442), .Y(n1416) );
INVX2TS U1612 ( .A(n1411), .Y(n1413) );
NOR2X2TS U1613 ( .A(mult_x_19_n1678), .B(n790), .Y(n916) );
INVX2TS U1614 ( .A(n2182), .Y(n956) );
OAI21X2TS U1615 ( .A0(n970), .A1(n1607), .B0(n973), .Y(n1606) );
OAI22X2TS U1616 ( .A0(n990), .A1(n2055), .B0(n2311), .B1(n981), .Y(n2243) );
OAI22X2TS U1617 ( .A0(n769), .A1(n700), .B0(n2485), .B1(n894), .Y(n2302) );
NAND2X4TS U1618 ( .A(n1616), .B(n1615), .Y(n2286) );
NAND2X2TS U1619 ( .A(n929), .B(n969), .Y(n2561) );
NAND3X4TS U1620 ( .A(n1673), .B(n1672), .C(n1671), .Y(n206) );
NAND2X2TS U1621 ( .A(n2768), .B(n2754), .Y(n2756) );
INVX4TS U1622 ( .A(n1258), .Y(n1236) );
INVX2TS U1623 ( .A(n693), .Y(n694) );
NOR2X6TS U1624 ( .A(n667), .B(n2037), .Y(n642) );
OAI22X2TS U1625 ( .A0(n2051), .A1(n1301), .B0(n1345), .B1(n2048), .Y(n1287)
);
INVX2TS U1626 ( .A(n753), .Y(n657) );
INVX2TS U1627 ( .A(n2804), .Y(n2807) );
INVX2TS U1628 ( .A(n1423), .Y(n1425) );
ADDFHX2TS U1629 ( .A(n1555), .B(n1554), .CI(n1553), .CO(n1558), .S(n1579) );
OAI22X2TS U1630 ( .A0(n1796), .A1(n2316), .B0(n757), .B1(n1323), .Y(n1313)
);
NOR2BX2TS U1631 ( .AN(n612), .B(n3098), .Y(n1337) );
OAI21X2TS U1632 ( .A0(n1868), .A1(n870), .B0(n905), .Y(n903) );
OAI22X2TS U1633 ( .A0(n2219), .A1(n841), .B0(n2329), .B1(n2327), .Y(n2385)
);
OAI22X2TS U1634 ( .A0(n802), .A1(n1712), .B0(n1676), .B1(n1014), .Y(n1677)
);
NOR2X4TS U1635 ( .A(n2322), .B(n1582), .Y(n724) );
NOR2X4TS U1636 ( .A(n678), .B(n1816), .Y(n725) );
INVX2TS U1637 ( .A(n1792), .Y(n852) );
NAND2X4TS U1638 ( .A(n674), .B(n2905), .Y(n716) );
OAI22X2TS U1639 ( .A0(n2311), .A1(n994), .B0(n802), .B1(n976), .Y(n2363) );
OAI22X2TS U1640 ( .A0(n841), .A1(n2328), .B0(n1321), .B1(n2327), .Y(n2416)
);
INVX2TS U1641 ( .A(n1465), .Y(n1394) );
AOI21X2TS U1642 ( .A0(n1469), .A1(n1468), .B0(n1467), .Y(n1471) );
NOR2X2TS U1643 ( .A(n1462), .B(n1465), .Y(n1468) );
INVX2TS U1644 ( .A(n1461), .Y(n1462) );
INVX2TS U1645 ( .A(n1456), .Y(n1458) );
OAI21X2TS U1646 ( .A0(n636), .A1(n1452), .B0(n1451), .Y(n1453) );
INVX2TS U1647 ( .A(n1448), .Y(n1449) );
NOR2X4TS U1648 ( .A(n1268), .B(n1267), .Y(n1465) );
NOR2X4TS U1649 ( .A(n2117), .B(n2122), .Y(n1006) );
INVX2TS U1650 ( .A(n2660), .Y(n1627) );
NAND2X1TS U1651 ( .A(n2661), .B(n1627), .Y(n1629) );
INVX2TS U1652 ( .A(n1417), .Y(n1415) );
INVX2TS U1653 ( .A(n1438), .Y(n1436) );
OAI21X1TS U1654 ( .A0(n922), .A1(n2178), .B0(n2177), .Y(n921) );
OAI21X2TS U1655 ( .A0(n2236), .A1(n844), .B0(n2235), .Y(n885) );
INVX2TS U1656 ( .A(n1638), .Y(n1992) );
INVX4TS U1657 ( .A(n1929), .Y(n1633) );
INVX2TS U1658 ( .A(n2591), .Y(n2593) );
INVX2TS U1659 ( .A(n2841), .Y(n2765) );
INVX2TS U1660 ( .A(n965), .Y(n859) );
INVX2TS U1661 ( .A(n697), .Y(n2262) );
INVX2TS U1662 ( .A(n2862), .Y(n2864) );
INVX2TS U1663 ( .A(mult_x_19_n723), .Y(n2565) );
XOR2X1TS U1664 ( .A(n357), .B(n356), .Y(n3023) );
XOR2X1TS U1665 ( .A(n355), .B(n354), .Y(n2941) );
INVX2TS U1666 ( .A(n345), .Y(n2931) );
INVX2TS U1667 ( .A(mult_x_19_n633), .Y(n2879) );
INVX2TS U1668 ( .A(n713), .Y(n710) );
CLKBUFX3TS U1669 ( .A(n3360), .Y(n3081) );
ADDFHX2TS U1670 ( .A(n2405), .B(n2404), .CI(n2403), .CO(mult_x_19_n649), .S(
n1570) );
ADDFHX2TS U1671 ( .A(n2525), .B(n2524), .CI(n2523), .CO(mult_x_19_n940), .S(
mult_x_19_n941) );
CLKBUFX3TS U1672 ( .A(n3360), .Y(n3277) );
CLKBUFX3TS U1673 ( .A(n3360), .Y(n3082) );
INVX2TS U1674 ( .A(n2924), .Y(n3050) );
BUFX3TS U1675 ( .A(n3157), .Y(n3090) );
BUFX3TS U1676 ( .A(n3167), .Y(n3280) );
CLKBUFX3TS U1677 ( .A(n3157), .Y(n3089) );
CLKBUFX3TS U1678 ( .A(n2576), .Y(n3083) );
CLKINVX3TS U1679 ( .A(rst), .Y(n794) );
CLKBUFX2TS U1680 ( .A(n2576), .Y(n3085) );
CLKBUFX3TS U1681 ( .A(n3157), .Y(n3088) );
CLKBUFX3TS U1682 ( .A(n3085), .Y(n3091) );
CLKBUFX3TS U1683 ( .A(n2575), .Y(n3076) );
CLKBUFX3TS U1684 ( .A(n3279), .Y(n3166) );
AND2X2TS U1685 ( .A(n1477), .B(n1475), .Y(n1275) );
NAND2X4TS U1686 ( .A(n1486), .B(n1222), .Y(n3287) );
CLKINVX3TS U1687 ( .A(n770), .Y(n795) );
CLKINVX3TS U1688 ( .A(n770), .Y(n817) );
CLKINVX3TS U1689 ( .A(n770), .Y(n816) );
BUFX3TS U1690 ( .A(n3276), .Y(n3157) );
OAI21X2TS U1691 ( .A0(n1662), .A1(n2112), .B0(n1661), .Y(n1667) );
NAND2X2TS U1692 ( .A(n796), .B(n2629), .Y(n3288) );
INVX2TS U1693 ( .A(rst), .Y(n3360) );
NAND2X2TS U1694 ( .A(n796), .B(n2628), .Y(n3292) );
NAND2X2TS U1695 ( .A(n776), .B(n2678), .Y(n3313) );
CLKBUFX3TS U1696 ( .A(n3276), .Y(n3160) );
CLKBUFX2TS U1697 ( .A(n3277), .Y(n3158) );
CLKBUFX3TS U1698 ( .A(n2576), .Y(n3086) );
CLKBUFX3TS U1699 ( .A(n3277), .Y(n3161) );
BUFX3TS U1700 ( .A(n3153), .Y(n3282) );
BUFX3TS U1701 ( .A(n3155), .Y(n3281) );
CLKBUFX3TS U1702 ( .A(n773), .Y(n3167) );
CLKINVX3TS U1703 ( .A(n770), .Y(n815) );
INVX6TS U1704 ( .A(n1632), .Y(n1929) );
XOR2X4TS U1705 ( .A(n2203), .B(n2958), .Y(n2204) );
AOI21X4TS U1706 ( .A0(n582), .A1(n2998), .B0(n2999), .Y(n2203) );
OAI22X2TS U1707 ( .A0(n437), .A1(n1870), .B0(n2050), .B1(n2048), .Y(n2076)
);
OAI2BB1X2TS U1708 ( .A0N(n1782), .A1N(n1781), .B0(n889), .Y(n1826) );
XOR2X4TS U1709 ( .A(n629), .B(n761), .Y(n1702) );
XNOR2X4TS U1710 ( .A(n891), .B(n606), .Y(n890) );
OR2X8TS U1711 ( .A(n1770), .B(n1769), .Y(n631) );
OR2X8TS U1712 ( .A(n1770), .B(n1769), .Y(n632) );
NOR2X4TS U1713 ( .A(n2632), .B(n2859), .Y(n2634) );
NOR2X4TS U1714 ( .A(n2632), .B(n2631), .Y(n2633) );
NAND2X4TS U1715 ( .A(Sgf_normalized_result[6]), .B(n2837), .Y(n2632) );
OA21X4TS U1716 ( .A0(n1245), .A1(n1377), .B0(n1244), .Y(n636) );
OAI22X2TS U1717 ( .A0(n2330), .A1(n1320), .B0(n1299), .B1(n2327), .Y(n1356)
);
OAI22X4TS U1718 ( .A0(n2330), .A1(n1118), .B0(n1163), .B1(n1813), .Y(n1157)
);
NAND3X4TS U1719 ( .A(n2704), .B(n2703), .C(n2702), .Y(n208) );
AOI2BB2X4TS U1720 ( .B0(n2700), .B1(n2699), .A0N(n805), .A1N(n3143), .Y(
n2703) );
NOR2X8TS U1721 ( .A(n573), .B(n2992), .Y(n1855) );
ADDFHX4TS U1722 ( .A(n1801), .B(n1800), .CI(n1799), .CO(n1811), .S(n2019) );
OAI22X4TS U1723 ( .A0(n2041), .A1(n2015), .B0(n1771), .B1(n800), .Y(n1799)
);
CLKBUFX3TS U1724 ( .A(n1988), .Y(n661) );
OAI21X4TS U1725 ( .A0(n1239), .A1(n1421), .B0(n1238), .Y(n1240) );
AND2X6TS U1726 ( .A(n1770), .B(n1769), .Y(n660) );
OR2X8TS U1727 ( .A(n642), .B(n643), .Y(n2057) );
NOR2X4TS U1728 ( .A(n1422), .B(n1239), .Y(n1241) );
BUFX4TS U1729 ( .A(n1875), .Y(n656) );
INVX8TS U1730 ( .A(n1620), .Y(n2667) );
INVX8TS U1731 ( .A(n646), .Y(n647) );
OAI22X2TS U1732 ( .A0(n803), .A1(n1785), .B0(n1784), .B1(n2314), .Y(n1788)
);
XNOR2X4TS U1733 ( .A(n878), .B(n824), .Y(n1785) );
OR2X8TS U1734 ( .A(n803), .B(n968), .Y(n652) );
OAI2BB1X2TS U1735 ( .A0N(n852), .A1N(n851), .B0(n1791), .Y(n850) );
ADDFHX2TS U1736 ( .A(n2149), .B(n2148), .CI(n2147), .CO(n2171), .S(n2139) );
OAI22X2TS U1737 ( .A0(n677), .A1(n2886), .B0(n2471), .B1(n1746), .Y(n2225)
);
XOR2X4TS U1738 ( .A(n1884), .B(n696), .Y(n1353) );
OAI22X4TS U1739 ( .A0(n838), .A1(n2014), .B0(n1785), .B1(n590), .Y(n2017) );
XNOR2X4TS U1740 ( .A(n657), .B(n647), .Y(n1772) );
OAI22X2TS U1741 ( .A0(n678), .A1(n1353), .B0(n2471), .B1(n985), .Y(n1326) );
XOR2X4TS U1742 ( .A(n1814), .B(n2950), .Y(n1771) );
XNOR2X2TS U1743 ( .A(n2241), .B(n648), .Y(n1056) );
ADDFHX4TS U1744 ( .A(n1129), .B(n1128), .CI(n1127), .CO(n1135), .S(n1146) );
OAI22X4TS U1745 ( .A0(n784), .A1(n2481), .B0(n2480), .B1(n800), .Y(n2547) );
XNOR2X4TS U1746 ( .A(n1814), .B(n755), .Y(n2480) );
NAND2X2TS U1747 ( .A(n2248), .B(n1365), .Y(n1221) );
ADDFHX4TS U1748 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2101), .S(n2441) );
INVX16TS U1749 ( .A(n666), .Y(n667) );
XNOR2X4TS U1750 ( .A(n644), .B(n1869), .Y(n951) );
ADDFHX2TS U1751 ( .A(n2012), .B(n2011), .CI(n2010), .CO(n1843), .S(n2033) );
AOI21X4TS U1752 ( .A0(n1217), .A1(n2650), .B0(n1216), .Y(n1218) );
NAND2X8TS U1753 ( .A(n2191), .B(n2190), .Y(n2282) );
CLKXOR2X2TS U1754 ( .A(n2290), .B(n2289), .Y(n877) );
NAND2X6TS U1755 ( .A(n1373), .B(n3254), .Y(n854) );
ADDFHX4TS U1756 ( .A(n2144), .B(n2143), .CI(n2142), .CO(n2173), .S(n2140) );
OAI22X2TS U1757 ( .A0(n2041), .A1(n1780), .B0(n1815), .B1(n2479), .Y(n1832)
);
OAI21X4TS U1758 ( .A0(n766), .A1(n1533), .B0(n1532), .Y(n1536) );
OAI21X2TS U1759 ( .A0(n1948), .A1(n1529), .B0(n1528), .Y(n1530) );
OAI21X1TS U1760 ( .A0(n658), .A1(n1898), .B0(n892), .Y(n946) );
BUFX12TS U1761 ( .A(n633), .Y(n2068) );
NAND2X2TS U1762 ( .A(n2679), .B(n2629), .Y(n3289) );
XNOR2X2TS U1763 ( .A(n2218), .B(n626), .Y(n1061) );
XNOR2X1TS U1764 ( .A(n792), .B(n626), .Y(n1306) );
NAND2X4TS U1765 ( .A(n1979), .B(n1980), .Y(n2267) );
NOR2X8TS U1766 ( .A(n1957), .B(n1956), .Y(n665) );
INVX16TS U1767 ( .A(n665), .Y(n3099) );
ADDFHX4TS U1768 ( .A(n2083), .B(n2082), .CI(n2081), .CO(n2458), .S(n2442) );
INVX16TS U1769 ( .A(n668), .Y(n669) );
XNOR2X4TS U1770 ( .A(n690), .B(n824), .Y(n2069) );
NAND2X2TS U1771 ( .A(n2681), .B(n2630), .Y(n3298) );
OAI22X4TS U1772 ( .A0(n803), .A1(n2074), .B0(n2014), .B1(n590), .Y(n2044) );
XNOR2X4TS U1773 ( .A(n878), .B(n755), .Y(n2014) );
NOR3X4TS U1774 ( .A(n3137), .B(FSM_selector_B_1_), .C(n2686), .Y(n1269) );
NOR2X4TS U1775 ( .A(n1230), .B(n1255), .Y(n1232) );
OAI22X2TS U1776 ( .A0(n1796), .A1(n1117), .B0(n1116), .B1(n756), .Y(n1124)
);
OAI21X4TS U1777 ( .A0(n1948), .A1(n1947), .B0(n1946), .Y(n1949) );
AOI21X4TS U1778 ( .A0(n1945), .A1(n1944), .B0(n1943), .Y(n1946) );
XNOR2X4TS U1779 ( .A(n1361), .B(n960), .Y(n984) );
OAI22X2TS U1780 ( .A0(n767), .A1(n1893), .B0(n2036), .B1(n2034), .Y(n2080)
);
OA22X2TS U1781 ( .A0(n676), .A1(n1506), .B0(n2471), .B1(n1884), .Y(n680) );
BUFX20TS U1782 ( .A(n1288), .Y(n2055) );
CMPR22X2TS U1783 ( .A(n1021), .B(n1020), .CO(n1075), .S(n1024) );
NAND2X4TS U1784 ( .A(n989), .B(n980), .Y(n979) );
OAI2BB1X4TS U1785 ( .A0N(n587), .A1N(n1490), .B0(n3269), .Y(n681) );
XOR2X4TS U1786 ( .A(n644), .B(n687), .Y(n1802) );
ADDFHX4TS U1787 ( .A(n2336), .B(n2335), .CI(n2334), .CO(n2519), .S(n2409) );
ADDFHX2TS U1788 ( .A(n1068), .B(n1067), .CI(n1066), .CO(n1072), .S(n1074) );
OA22X4TS U1789 ( .A0(n2312), .A1(n1325), .B0(n1324), .B1(n1026), .Y(n683) );
INVX12TS U1790 ( .A(n1494), .Y(n2655) );
NAND2X4TS U1791 ( .A(n2248), .B(n584), .Y(n1488) );
XNOR2X4TS U1792 ( .A(n684), .B(n685), .Y(n1279) );
OAI22X4TS U1793 ( .A0(n676), .A1(n2323), .B0(n1359), .B1(n2322), .Y(n2304)
);
NAND2BX2TS U1794 ( .AN(n789), .B(n645), .Y(n1318) );
INVX16TS U1795 ( .A(n782), .Y(n784) );
NOR2X4TS U1796 ( .A(n1008), .B(n1007), .Y(n2108) );
OAI21X4TS U1797 ( .A0(n1863), .A1(n682), .B0(n1862), .Y(n893) );
OAI22X2TS U1798 ( .A0(n803), .A1(n2893), .B0(n590), .B1(n1093), .Y(n1125) );
OAI22X1TS U1799 ( .A0(n783), .A1(n645), .B0(n2479), .B1(n2884), .Y(n1602) );
ADDFHX4TS U1800 ( .A(n1755), .B(n1754), .CI(n1753), .CO(n2234), .S(n1750) );
XNOR2X2TS U1801 ( .A(n645), .B(n2319), .Y(n2040) );
OAI22X2TS U1802 ( .A0(n2318), .A1(n1886), .B0(n757), .B1(n2052), .Y(n2091)
);
OAI22X4TS U1803 ( .A0(n2310), .A1(n1309), .B0(n1301), .B1(n2048), .Y(n1355)
);
ADDFHX4TS U1804 ( .A(n1354), .B(n1355), .CI(n1356), .CO(n1331), .S(n2345) );
XNOR2X4TS U1805 ( .A(n617), .B(n399), .Y(n1104) );
OAI22X4TS U1806 ( .A0(n767), .A1(n1304), .B0(n1893), .B1(n2034), .Y(n1882)
);
XNOR2X4TS U1807 ( .A(n617), .B(n762), .Y(n1713) );
ADDFHX4TS U1808 ( .A(n672), .B(n2158), .CI(n2157), .CO(n2179), .S(n2183) );
ADDFHX4TS U1809 ( .A(n2046), .B(n2047), .CI(n2045), .CO(n2062), .S(n2102) );
XNOR2X4TS U1810 ( .A(n617), .B(n671), .Y(n1161) );
OAI22X4TS U1811 ( .A0(n678), .A1(n1778), .B0(mult_x_19_n1556), .B1(n2322),
.Y(n1834) );
ADDFHX4TS U1812 ( .A(n1286), .B(n1285), .CI(n1287), .CO(n1872), .S(n1297) );
NOR2X4TS U1813 ( .A(mult_x_19_n423), .B(mult_x_19_n439), .Y(mult_x_19_n421)
);
XNOR2X2TS U1814 ( .A(n617), .B(n2221), .Y(n1107) );
BUFX3TS U1815 ( .A(n771), .Y(n3285) );
BUFX3TS U1816 ( .A(n3278), .Y(n3154) );
INVX2TS U1817 ( .A(n734), .Y(n735) );
AND2X8TS U1818 ( .A(n3274), .B(n3356), .Y(n2785) );
INVX2TS U1819 ( .A(n715), .Y(n833) );
BUFX8TS U1820 ( .A(mult_x_19_n52), .Y(n2471) );
INVX12TS U1821 ( .A(n2470), .Y(n763) );
CLKINVX12TS U1822 ( .A(n962), .Y(n2006) );
BUFX12TS U1823 ( .A(n734), .Y(n757) );
INVX6TS U1824 ( .A(n970), .Y(n972) );
BUFX3TS U1825 ( .A(n2575), .Y(n3075) );
CLKBUFX2TS U1826 ( .A(n3277), .Y(n3162) );
CLKBUFX3TS U1827 ( .A(n3360), .Y(n3080) );
CLKBUFX2TS U1828 ( .A(n3276), .Y(n3156) );
CLKBUFX3TS U1829 ( .A(n778), .Y(n3165) );
BUFX3TS U1830 ( .A(n3279), .Y(n3164) );
CLKINVX3TS U1831 ( .A(n770), .Y(n773) );
CLKINVX3TS U1832 ( .A(n770), .Y(n772) );
BUFX3TS U1833 ( .A(n3153), .Y(n3283) );
BUFX3TS U1834 ( .A(n3284), .Y(n3279) );
BUFX3TS U1835 ( .A(n3153), .Y(n778) );
XOR2X4TS U1836 ( .A(n1002), .B(n712), .Y(n2551) );
XNOR2X4TS U1837 ( .A(n713), .B(n647), .Y(n712) );
AOI2BB2X4TS U1838 ( .B0(n2474), .B1(n687), .A0N(n695), .A1N(n884), .Y(n713)
);
OAI22X4TS U1839 ( .A0(n1807), .A1(n2793), .B0(n551), .B1(n638), .Y(n837) );
OAI22X4TS U1840 ( .A0(n1807), .A1(n2794), .B0(n715), .B1(n736), .Y(n1868) );
OAI22X4TS U1841 ( .A0(n1807), .A1(n2221), .B0(n715), .B1(n399), .Y(n1795) );
OAI22X4TS U1842 ( .A0(n1807), .A1(n2796), .B0(n715), .B1(n870), .Y(n1294) );
OAI2BB1X4TS U1843 ( .A0N(n2410), .A1N(n2411), .B0(n717), .Y(n2347) );
OAI21X4TS U1844 ( .A0(n2411), .A1(n2410), .B0(n2409), .Y(n717) );
XNOR2X4TS U1845 ( .A(n718), .B(n2411), .Y(n2428) );
XNOR2X4TS U1846 ( .A(n2410), .B(n2409), .Y(n718) );
XNOR2X4TS U1847 ( .A(n722), .B(n2145), .Y(n2172) );
XOR2X4TS U1848 ( .A(n2146), .B(n723), .Y(n722) );
NOR2X8TS U1849 ( .A(n725), .B(n724), .Y(n723) );
INVX2TS U1850 ( .A(n727), .Y(n728) );
BUFX20TS U1851 ( .A(n1026), .Y(n1014) );
OAI22X2TS U1852 ( .A0(n743), .A1(n780), .B0(n842), .B1(n2889), .Y(n1002) );
OAI21X2TS U1853 ( .A0(n1653), .A1(n2112), .B0(n1652), .Y(n1656) );
OAI22X2TS U1854 ( .A0(n556), .A1(n1019), .B0(n1027), .B1(n785), .Y(n1025) );
INVX2TS U1855 ( .A(n732), .Y(n733) );
ADDFHX2TS U1856 ( .A(n2550), .B(n2549), .CI(n2548), .CO(n2494), .S(n2558) );
BUFX20TS U1857 ( .A(n2794), .Y(n828) );
ADDFHX4TS U1858 ( .A(n1742), .B(n1741), .CI(n1740), .CO(n2246), .S(n1763) );
NAND2BX2TS U1859 ( .AN(n2904), .B(n2013), .Y(n1093) );
XNOR2X4TS U1860 ( .A(n1667), .B(n1666), .Y(n1668) );
OAI22X4TS U1861 ( .A0(n841), .A1(n1321), .B0(n1320), .B1(n2327), .Y(n2340)
);
OAI22X4TS U1862 ( .A0(n678), .A1(mult_x_19_n1556), .B0(n1816), .B1(n2322),
.Y(n2143) );
XNOR2X4TS U1863 ( .A(n753), .B(n1869), .Y(n1816) );
ADDFHX4TS U1864 ( .A(n1328), .B(n1327), .CI(n1326), .CO(n1298), .S(n1349) );
ADDFHX4TS U1865 ( .A(n1707), .B(n1708), .CI(n1706), .CO(n1719), .S(n1905) );
OAI22X2TS U1866 ( .A0(n1796), .A1(n1696), .B0(n1695), .B1(n756), .Y(n1706)
);
ADDFHX4TS U1867 ( .A(n2343), .B(n2342), .CI(n2341), .CO(n2346), .S(n2514) );
NAND2X6TS U1868 ( .A(n910), .B(n909), .Y(n892) );
XOR2X4TS U1869 ( .A(n741), .B(n1862), .Y(n1896) );
XOR2X4TS U1870 ( .A(n1863), .B(n1861), .Y(n741) );
NAND2X8TS U1871 ( .A(mult_x_19_n1800), .B(n1817), .Y(n742) );
NAND2X8TS U1872 ( .A(n745), .B(n746), .Y(n1690) );
OAI22X4TS U1873 ( .A0(n768), .A1(n1548), .B0(n1545), .B1(n842), .Y(n1563) );
XOR2X4TS U1874 ( .A(n922), .B(n747), .Y(n2170) );
XOR2X4TS U1875 ( .A(n2177), .B(n2178), .Y(n747) );
BUFX20TS U1876 ( .A(n2906), .Y(n824) );
NOR2X4TS U1877 ( .A(n2763), .B(n2693), .Y(n2769) );
ADDFHX4TS U1878 ( .A(n2337), .B(n2338), .CI(n2339), .CO(n2516), .S(n2421) );
BUFX20TS U1879 ( .A(n2907), .Y(n879) );
ADDFHX4TS U1880 ( .A(n1315), .B(n1314), .CI(n1313), .CO(n1310), .S(n2518) );
CLKINVX12TS U1881 ( .A(n1280), .Y(n2470) );
OAI22X4TS U1882 ( .A0(n760), .A1(n1303), .B0(mult_x_19_n1585), .B1(n1674),
.Y(n1890) );
ADDFHX4TS U1883 ( .A(n1689), .B(n1688), .CI(n1687), .CO(n1697), .S(n1906) );
ADDFHX4TS U1884 ( .A(n624), .B(n1795), .CI(n1794), .CO(n1792), .S(n2021) );
OAI22X4TS U1885 ( .A0(n407), .A1(n1743), .B0(n2228), .B1(n2227), .Y(n2216)
);
OAI22X4TS U1886 ( .A0(n802), .A1(n1081), .B0(n1104), .B1(n1014), .Y(n1132)
);
OAI22X2TS U1887 ( .A0(n551), .A1(n650), .B0(n1807), .B1(n879), .Y(n1516) );
INVX12TS U1888 ( .A(n1931), .Y(n2112) );
ADDFHX4TS U1889 ( .A(n1606), .B(n1605), .CI(n1604), .CO(n1609), .S(n2530) );
ADDFHX2TS U1890 ( .A(n3066), .B(n1603), .CI(n1602), .CO(n1610), .S(n1605) );
CLKINVX12TS U1891 ( .A(n2901), .Y(n2052) );
OAI22X2TS U1892 ( .A0(n2318), .A1(n1695), .B0(n1680), .B1(n734), .Y(n1699)
);
INVX12TS U1893 ( .A(n897), .Y(n785) );
ADDFHX4TS U1894 ( .A(n1679), .B(n1678), .CI(n1677), .CO(n1765), .S(n1731) );
OAI22X4TS U1895 ( .A0(n764), .A1(n1682), .B0(n1681), .B1(n2227), .Y(n1701)
);
ADDFHX4TS U1896 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1912), .S(n1908) );
OAI22X4TS U1897 ( .A0(n790), .A1(n1163), .B0(n1714), .B1(n1813), .Y(n1722)
);
INVX16TS U1898 ( .A(n2670), .Y(n765) );
INVX16TS U1899 ( .A(n2670), .Y(n766) );
INVX16TS U1900 ( .A(n1820), .Y(n2486) );
INVX16TS U1901 ( .A(n2486), .Y(n769) );
ADDFHX2TS U1902 ( .A(n1614), .B(n1613), .CI(n1612), .CO(n2128), .S(n1608) );
OAI22X4TS U1903 ( .A0(n1308), .A1(n553), .B0(n785), .B1(mult_x_19_n1749),
.Y(n1335) );
ADDFHX4TS U1904 ( .A(n1332), .B(n1333), .CI(n1334), .CO(n1863), .S(n1330) );
OAI22X2TS U1905 ( .A0(n764), .A1(mult_x_19_n1587), .B0(n1303), .B1(n1674),
.Y(n1333) );
OAI22X2TS U1906 ( .A0(n767), .A1(mult_x_19_n1610), .B0(n1304), .B1(n842),
.Y(n1332) );
XOR2X4TS U1907 ( .A(n2241), .B(n3095), .Y(n1887) );
BUFX8TS U1908 ( .A(n2799), .Y(n3273) );
OAI22X2TS U1909 ( .A0(n2325), .A1(n760), .B0(n1674), .B1(n992), .Y(n2334) );
INVX8TS U1910 ( .A(n779), .Y(n780) );
INVX16TS U1911 ( .A(n2482), .Y(n782) );
INVX16TS U1912 ( .A(n782), .Y(n783) );
INVX2TS U1913 ( .A(n770), .Y(n788) );
INVX12TS U1914 ( .A(n1281), .Y(n791) );
XNOR2X2TS U1915 ( .A(n791), .B(n755), .Y(n1502) );
AO22X2TS U1916 ( .A0(n2857), .A1(n2854), .B0(final_result_ieee[22]), .B1(
n2855), .Y(n178) );
NAND2X2TS U1917 ( .A(n2854), .B(n310), .Y(n2694) );
XNOR2X2TS U1918 ( .A(n617), .B(n2319), .Y(n1106) );
NOR4X2TS U1919 ( .A(Op_MX[13]), .B(Op_MX[15]), .C(Op_MX[1]), .D(Op_MX[3]),
.Y(n2820) );
MXI2X4TS U1920 ( .A(n1739), .B(n3106), .S0(n2785), .Y(n226) );
NOR2X2TS U1921 ( .A(n3121), .B(n3106), .Y(n1475) );
AO22X2TS U1922 ( .A0(n2853), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n2852), .Y(n198) );
AO22X2TS U1923 ( .A0(n2853), .A1(n640), .B0(final_result_ieee[4]), .B1(n2852), .Y(n196) );
AO22X2TS U1924 ( .A0(n2853), .A1(n2851), .B0(final_result_ieee[5]), .B1(
n2852), .Y(n195) );
AO22X2TS U1925 ( .A0(n2853), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n2852), .Y(n197) );
CLKBUFX2TS U1926 ( .A(n2576), .Y(n3084) );
BUFX3TS U1927 ( .A(n3278), .Y(n3155) );
CLKBUFX3TS U1928 ( .A(n3278), .Y(n3153) );
BUFX3TS U1929 ( .A(n3153), .Y(n3079) );
BUFX3TS U1930 ( .A(n772), .Y(n3078) );
NAND2X2TS U1931 ( .A(n796), .B(n2630), .Y(n3297) );
NAND2X2TS U1932 ( .A(n796), .B(n2638), .Y(n3286) );
OAI22X2TS U1933 ( .A0(n1823), .A1(n2051), .B0(n1822), .B1(n499), .Y(n2148)
);
XNOR2X4TS U1934 ( .A(n500), .B(n787), .Y(n1514) );
OAI22X4TS U1935 ( .A0(n715), .A1(n762), .B0(n3098), .B1(n2908), .Y(n2158) );
OAI22X2TS U1936 ( .A0(n969), .A1(n505), .B0(n970), .B1(n1281), .Y(n2131) );
ADDFHX4TS U1937 ( .A(n2319), .B(n2221), .CI(n2156), .CO(n2184), .S(n2147) );
BUFX20TS U1938 ( .A(n855), .Y(n801) );
OAI22X4TS U1939 ( .A0(n784), .A1(n1883), .B0(n2040), .B1(n2479), .Y(n2094)
);
BUFX20TS U1940 ( .A(n855), .Y(n2479) );
INVX16TS U1941 ( .A(n989), .Y(n802) );
OAI22X4TS U1942 ( .A0(n802), .A1(n1056), .B0(n1055), .B1(n2311), .Y(n1064)
);
OAI22X4TS U1943 ( .A0(n802), .A1(n1055), .B0(n1081), .B1(n2311), .Y(n1088)
);
OAI22X2TS U1944 ( .A0(n803), .A1(n2320), .B0(n590), .B1(n2315), .Y(n2339) );
AND2X8TS U1945 ( .A(n1485), .B(n1486), .Y(n2783) );
CLKINVX6TS U1946 ( .A(n2783), .Y(n805) );
AOI2BB2X2TS U1947 ( .B0(n2784), .B1(n2674), .A0N(n806), .A1N(n3126), .Y(
n3307) );
AOI2BB2X2TS U1948 ( .B0(n2784), .B1(n2682), .A0N(n807), .A1N(n3128), .Y(
n3315) );
AOI2BB2X2TS U1949 ( .B0(n2700), .B1(n2683), .A0N(n807), .A1N(n3132), .Y(
n3331) );
AOI2BB2X2TS U1950 ( .B0(n1483), .B1(n2673), .A0N(n806), .A1N(n3144), .Y(
n3347) );
AOI2BB2X2TS U1951 ( .B0(n2784), .B1(n2684), .A0N(n806), .A1N(n3131), .Y(
n3327) );
AOI2BB2X2TS U1952 ( .B0(n2784), .B1(n2685), .A0N(n807), .A1N(n3130), .Y(
n3323) );
AOI2BB2X2TS U1953 ( .B0(n2784), .B1(n2676), .A0N(n806), .A1N(n3142), .Y(
n3343) );
AOI22X2TS U1954 ( .A0(n2827), .A1(Add_result[13]), .B0(n2843), .B1(n2799),
.Y(n3328) );
CLKBUFX2TS U1955 ( .A(Add_result[21]), .Y(n811) );
AOI22X2TS U1956 ( .A0(n2792), .A1(Add_result[12]), .B0(n2845), .B1(n2799),
.Y(n3332) );
AOI22X2TS U1957 ( .A0(n2792), .A1(Add_result[15]), .B0(n2842), .B1(n2799),
.Y(n3320) );
CLKBUFX2TS U1958 ( .A(Add_result[2]), .Y(n813) );
NOR3X1TS U1959 ( .A(Op_MX[4]), .B(Op_MX[23]), .C(Op_MX[24]), .Y(n2818) );
MX2X4TS U1960 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n2791), .Y(
mult_x_19_n1777) );
NOR3X1TS U1961 ( .A(Op_MY[17]), .B(Op_MY[23]), .C(Op_MY[24]), .Y(n2805) );
INVX2TS U1962 ( .A(n2868), .Y(n1444) );
MXI2X4TS U1963 ( .A(n1432), .B(n1431), .S0(n427), .Y(n2602) );
MXI2X4TS U1964 ( .A(n1441), .B(n1440), .S0(n427), .Y(n2603) );
NAND2X4TS U1965 ( .A(n1408), .B(n427), .Y(n1409) );
MXI2X4TS U1966 ( .A(n1276), .B(n1275), .S0(n427), .Y(n1278) );
INVX4TS U1967 ( .A(n2778), .Y(n1040) );
AOI2BB2X4TS U1968 ( .B0(n819), .B1(n972), .A0N(n2152), .A1N(n667), .Y(n818)
);
ADDFHX4TS U1969 ( .A(n1337), .B(n1336), .CI(n1335), .CO(n1348), .S(n1311) );
NOR2BX2TS U1970 ( .AN(n789), .B(n744), .Y(n2305) );
BUFX4TS U1971 ( .A(n1026), .Y(n2311) );
ADDFHX4TS U1972 ( .A(n1758), .B(n1756), .CI(n1757), .CO(n2233), .S(n1764) );
AOI21X4TS U1973 ( .A0(n2252), .A1(n565), .B0(n2921), .Y(n820) );
OAI2BB1X4TS U1974 ( .A0N(n1906), .A1N(n739), .B0(n821), .Y(n1729) );
OAI21X4TS U1975 ( .A0(n739), .A1(n1906), .B0(n1905), .Y(n821) );
AOI21X4TS U1976 ( .A0(n860), .A1(n2208), .B0(n859), .Y(n2260) );
AOI2BB2X4TS U1977 ( .B0(n2628), .B1(n2700), .A0N(n805), .A1N(n3123), .Y(
n1492) );
OAI22X2TS U1978 ( .A0(n742), .A1(n1818), .B0(n1584), .B1(n842), .Y(n2145) );
ADDFHX4TS U1979 ( .A(n1882), .B(n1881), .CI(n1880), .CO(n2455), .S(n1877) );
NAND2X8TS U1980 ( .A(n695), .B(n689), .Y(n1500) );
XOR2X4TS U1981 ( .A(n825), .B(n2444), .Y(n2459) );
XOR2X4TS U1982 ( .A(n2445), .B(n2446), .Y(n825) );
NAND2X4TS U1983 ( .A(n2445), .B(n2446), .Y(n826) );
OAI21X4TS U1984 ( .A0(n2445), .A1(n2446), .B0(n2444), .Y(n827) );
XOR2X4TS U1985 ( .A(n2297), .B(n829), .Y(mult_x_19_n786) );
CLKXOR2X2TS U1986 ( .A(n836), .B(n837), .Y(n2448) );
OAI2BB1X4TS U1987 ( .A0N(n736), .A1N(n649), .B0(n837), .Y(n832) );
AO22X4TS U1988 ( .A0(n435), .A1(n639), .B0(n833), .B1(n649), .Y(n2077) );
XOR2X4TS U1989 ( .A(n834), .B(n1791), .Y(n2022) );
XOR2X4TS U1990 ( .A(n1792), .B(n1793), .Y(n834) );
XNOR2X2TS U1991 ( .A(n792), .B(n1869), .Y(n1556) );
XOR2X4TS U1992 ( .A(n932), .B(n835), .Y(n1768) );
INVX2TS U1993 ( .A(n1765), .Y(n835) );
AOI21X4TS U1994 ( .A0(n1455), .A1(n1454), .B0(n1453), .Y(n1460) );
OAI22X4TS U1995 ( .A0(n1676), .A1(n2312), .B0(n990), .B1(n1026), .Y(n1742)
);
OAI22X4TS U1996 ( .A0(n677), .A1(n1772), .B0(n1778), .B1(n2322), .Y(n891) );
ADDFHX4TS U1997 ( .A(n2365), .B(n2364), .CI(n2363), .CO(n2422), .S(n2414) );
OAI22X2TS U1998 ( .A0(n1762), .A1(n1083), .B0(n1105), .B1(n757), .Y(n1130)
);
BUFX20TS U1999 ( .A(n2908), .Y(n867) );
XOR2X4TS U2000 ( .A(n840), .B(n1905), .Y(n1963) );
XOR2X4TS U2001 ( .A(n1906), .B(n739), .Y(n840) );
OAI22X2TS U2002 ( .A0(n2331), .A1(n555), .B0(mult_x_19_n1753), .B1(n785),
.Y(n2371) );
OAI22X2TS U2003 ( .A0(n838), .A1(n1867), .B0(n2075), .B1(n590), .Y(n2452) );
NAND2X8TS U2004 ( .A(n734), .B(mult_x_19_n1805), .Y(n1293) );
CMPR22X2TS U2005 ( .A(n2369), .B(n2370), .CO(n2415), .S(n2420) );
XNOR2X4TS U2006 ( .A(n797), .B(n870), .Y(n1317) );
XNOR2X4TS U2007 ( .A(n843), .B(n2443), .Y(n2460) );
XNOR2X4TS U2008 ( .A(n2442), .B(n2441), .Y(n843) );
XOR2X4TS U2009 ( .A(n2185), .B(n845), .Y(n2165) );
XOR2X4TS U2010 ( .A(n2186), .B(n2187), .Y(n845) );
NAND2X2TS U2011 ( .A(n2186), .B(n2187), .Y(n846) );
OAI22X4TS U2012 ( .A0(n803), .A1(n1692), .B0(n1675), .B1(n2314), .Y(n1678)
);
OAI22X4TS U2013 ( .A0(n2318), .A1(n1323), .B0(n1322), .B1(n734), .Y(n1339)
);
OAI22X4TS U2014 ( .A0(n2151), .A1(n1894), .B0(n1289), .B1(n667), .Y(n1888)
);
NAND2X8TS U2015 ( .A(n1817), .B(mult_x_19_n1800), .Y(n1820) );
OAI22X4TS U2016 ( .A0(n743), .A1(mult_x_19_n1617), .B0(n895), .B1(n2034),
.Y(n1754) );
XNOR2X4TS U2017 ( .A(n2241), .B(n786), .Y(n990) );
BUFX12TS U2018 ( .A(n2914), .Y(n847) );
OAI22X2TS U2019 ( .A0(n678), .A1(n2220), .B0(n2324), .B1(n2322), .Y(n2384)
);
OAI22X4TS U2020 ( .A0(n768), .A1(n1694), .B0(n1703), .B1(n2034), .Y(n1707)
);
NAND2X1TS U2021 ( .A(n1792), .B(n1793), .Y(n849) );
AND2X8TS U2022 ( .A(n1964), .B(n1965), .Y(mult_x_19_n453) );
OAI22X2TS U2023 ( .A0(n802), .A1(n1106), .B0(n1161), .B1(n1014), .Y(n1167)
);
XNOR2X1TS U2024 ( .A(n856), .B(n2348), .Y(mult_x_19_n943) );
XNOR2X1TS U2025 ( .A(n2347), .B(n2349), .Y(n856) );
XOR2X1TS U2026 ( .A(n858), .B(n857), .Y(mult_x_19_n921) );
ADDFHX4TS U2027 ( .A(n2458), .B(n2457), .CI(n2456), .CO(n2299), .S(n2463) );
OAI22X4TS U2028 ( .A0(n677), .A1(n1284), .B0(n1885), .B1(n2471), .Y(n1891)
);
OAI22X4TS U2029 ( .A0(n1693), .A1(n804), .B0(n1692), .B1(n2223), .Y(n1708)
);
XNOR2X2TS U2030 ( .A(n792), .B(n668), .Y(n1607) );
OAI22X2TS U2031 ( .A0(n790), .A1(n1783), .B0(n2068), .B1(n2898), .Y(n1790)
);
NAND2X6TS U2032 ( .A(n1279), .B(n2468), .Y(n1280) );
ADDFHX4TS U2033 ( .A(n2061), .B(n2060), .CI(n2059), .CO(n2064), .S(n2099) );
INVX16TS U2034 ( .A(n3102), .Y(n1026) );
XNOR2X4TS U2035 ( .A(n628), .B(n1869), .Y(n994) );
OAI22X4TS U2036 ( .A0(n2330), .A1(mult_x_19_n1687), .B0(n1702), .B1(n1813),
.Y(n1711) );
ADDFHX2TS U2037 ( .A(n1790), .B(n1789), .CI(n1788), .CO(n1825), .S(n2023) );
OAI2BB1X4TS U2038 ( .A0N(n2362), .A1N(n2361), .B0(n864), .Y(mult_x_19_n994)
);
OAI21X2TS U2039 ( .A0(n2362), .A1(n2361), .B0(n620), .Y(n864) );
XOR2X4TS U2040 ( .A(n865), .B(n620), .Y(mult_x_19_n995) );
XOR2X4TS U2041 ( .A(n2362), .B(n2361), .Y(n865) );
XNOR2X4TS U2042 ( .A(n866), .B(n914), .Y(n1873) );
XOR2X4TS U2043 ( .A(n1892), .B(n1891), .Y(n866) );
BUFX6TS U2044 ( .A(n755), .Y(n868) );
OAI2BB1X4TS U2045 ( .A0N(n2441), .A1N(n2442), .B0(n869), .Y(n2456) );
OAI21X4TS U2046 ( .A0(n2441), .A1(n2442), .B0(n2443), .Y(n869) );
XOR2X4TS U2047 ( .A(n871), .B(n2340), .Y(n2515) );
OAI22X2TS U2048 ( .A0(n2312), .A1(n2054), .B0(n2053), .B1(n1026), .Y(n2084)
);
OAI22X2TS U2049 ( .A0(n838), .A1(n2075), .B0(n2074), .B1(n2314), .Y(n2449)
);
OAI22X2TS U2050 ( .A0(n2330), .A1(n1299), .B0(mult_x_19_n1678), .B1(n2068),
.Y(n1341) );
OAI2BB1X4TS U2051 ( .A0N(n1728), .A1N(n1727), .B0(n872), .Y(n1910) );
XOR2X4TS U2052 ( .A(n873), .B(n1727), .Y(n1915) );
XOR2X4TS U2053 ( .A(n1726), .B(n1728), .Y(n873) );
XOR2X4TS U2054 ( .A(n779), .B(n2793), .Y(n895) );
OAI2BB1X4TS U2055 ( .A0N(n2295), .A1N(n2296), .B0(n874), .Y(n2297) );
ADDFHX4TS U2056 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n2410), .S(n2406) );
OAI2BB1X4TS U2057 ( .A0N(n2290), .A1N(n2289), .B0(n876), .Y(n2355) );
OAI21X4TS U2058 ( .A0(n2289), .A1(n2290), .B0(n2288), .Y(n876) );
XOR2X4TS U2059 ( .A(n2288), .B(n877), .Y(mult_x_19_n923) );
ADDFHX4TS U2060 ( .A(n2058), .B(n2057), .CI(n2056), .CO(n2020), .S(n2100) );
OAI22X4TS U2061 ( .A0(n1307), .A1(n970), .B0(n505), .B1(n511), .Y(n1357) );
ADDFHX4TS U2062 ( .A(n1343), .B(n1342), .CI(n1341), .CO(n1878), .S(n1346) );
XNOR2X4TS U2063 ( .A(n2890), .B(n732), .Y(n1548) );
XOR2X4TS U2064 ( .A(n882), .B(n2350), .Y(n2360) );
XOR2X4TS U2065 ( .A(n2351), .B(n2352), .Y(n882) );
BUFX6TS U2066 ( .A(n618), .Y(n883) );
OAI22X4TS U2067 ( .A0(n2055), .A1(n628), .B0(n1014), .B1(n2899), .Y(n1794)
);
OAI22X4TS U2068 ( .A0(n769), .A1(n1703), .B0(mult_x_19_n1617), .B1(n2034),
.Y(n1710) );
OAI2BB1X4TS U2069 ( .A0N(n2236), .A1N(n844), .B0(n885), .Y(n2382) );
XOR2X4TS U2070 ( .A(n886), .B(n2236), .Y(n2232) );
OAI22X4TS U2071 ( .A0(n888), .A1(n800), .B0(n1542), .B1(n784), .Y(n1568) );
OAI22X4TS U2072 ( .A0(n2041), .A1(n888), .B0(n2481), .B1(n801), .Y(n2544) );
XNOR2X4TS U2073 ( .A(n497), .B(n650), .Y(n888) );
XNOR2X4TS U2074 ( .A(n2902), .B(n755), .Y(n1323) );
XNOR2X4TS U2075 ( .A(n2902), .B(n879), .Y(n2316) );
XOR2X4TS U2076 ( .A(n890), .B(n1781), .Y(n1810) );
OAI22X4TS U2077 ( .A0(n790), .A1(mult_x_19_n1674), .B0(n1783), .B1(n2068),
.Y(n2018) );
OAI22X4TS U2078 ( .A0(n841), .A1(n1101), .B0(n1119), .B1(n2327), .Y(n1128)
);
OAI22X2TS U2079 ( .A0(n2069), .A1(n2068), .B0(n2330), .B1(mult_x_19_n1676),
.Y(n2083) );
XOR2X4TS U2080 ( .A(n892), .B(n1899), .Y(n911) );
XNOR2X4TS U2081 ( .A(n1869), .B(n2895), .Y(n1344) );
OAI2BB1X4TS U2082 ( .A0N(n1863), .A1N(n682), .B0(n893), .Y(n1899) );
OAI22X4TS U2083 ( .A0(n768), .A1(n894), .B0(n2485), .B1(mult_x_19_n1610),
.Y(n1340) );
OAI22X4TS U2084 ( .A0(n2222), .A1(n2485), .B0(n768), .B1(n895), .Y(n2217) );
XOR2X4TS U2085 ( .A(n1864), .B(n949), .Y(n1861) );
XOR2X4TS U2086 ( .A(n904), .B(n1868), .Y(n1864) );
OAI22X4TS U2087 ( .A0(n2318), .A1(n2317), .B0(n756), .B1(n2316), .Y(n2338)
);
XOR2X4TS U2088 ( .A(n599), .B(n727), .Y(n898) );
OAI22X4TS U2089 ( .A0(n1762), .A1(n1680), .B0(n757), .B1(n899), .Y(n1756) );
XNOR2X4TS U2090 ( .A(n1764), .B(n1763), .Y(n932) );
OR2X8TS U2091 ( .A(n1098), .B(n1097), .Y(n1966) );
XOR2X4TS U2092 ( .A(n1865), .B(n1866), .Y(n949) );
OAI22X4TS U2093 ( .A0(n804), .A1(n1344), .B0(n1867), .B1(n2223), .Y(n1866)
);
OAI22X4TS U2094 ( .A0(n2310), .A1(n1345), .B0(n2048), .B1(n1870), .Y(n1865)
);
XNOR2X4TS U2095 ( .A(n464), .B(n884), .Y(n1870) );
OAI22X4TS U2096 ( .A0(n406), .A1(n1029), .B0(n1034), .B1(n555), .Y(n902) );
XOR2X4TS U2097 ( .A(n905), .B(n870), .Y(n904) );
OAI22X4TS U2098 ( .A0(n975), .A1(n801), .B0(n784), .B1(mult_x_19_n1542), .Y(
n1336) );
OAI22X4TS U2099 ( .A0(n801), .A1(n1542), .B0(n1544), .B1(n783), .Y(n1555) );
OAI22X4TS U2100 ( .A0(n1352), .A1(n784), .B0(n855), .B1(mult_x_19_n1542),
.Y(n2342) );
OAI22X4TS U2101 ( .A0(n1316), .A1(n783), .B0(n1352), .B1(n801), .Y(n2335) );
OAI22X4TS U2102 ( .A0(n801), .A1(n2155), .B0(n1815), .B1(n783), .Y(n2144) );
OAI22X4TS U2103 ( .A0(n2154), .A1(n2041), .B0(n800), .B1(n1544), .Y(n1589)
);
OAI22X4TS U2104 ( .A0(n2154), .A1(n801), .B0(n2155), .B1(n2482), .Y(n2177)
);
OAI22X4TS U2105 ( .A0(n1317), .A1(n2482), .B0(n800), .B1(n1316), .Y(n2370)
);
OAI22X4TS U2106 ( .A0(n556), .A1(mult_x_19_n1753), .B0(n1760), .B1(n548),
.Y(n2236) );
INVX16TS U2107 ( .A(n906), .Y(n1300) );
AND2X8TS U2108 ( .A(n2914), .B(mult_x_19_n1801), .Y(n906) );
OAI22X4TS U2109 ( .A0(n2310), .A1(n2049), .B0(n499), .B1(n1806), .Y(n2047)
);
OAI22X4TS U2110 ( .A0(n2051), .A1(n1822), .B0(n499), .B1(n1583), .Y(n2146)
);
OAI22X4TS U2111 ( .A0(n2310), .A1(mult_x_19_n1635), .B0(n499), .B1(n1309),
.Y(n1315) );
OAI2BB1X4TS U2112 ( .A0N(n1593), .A1N(n1592), .B0(n907), .Y(n1577) );
OAI21X4TS U2113 ( .A0(n1593), .A1(n1592), .B0(n1591), .Y(n907) );
XOR2X4TS U2114 ( .A(n908), .B(n1593), .Y(n2275) );
XOR2X4TS U2115 ( .A(n1591), .B(n1592), .Y(n908) );
INVX16TS U2116 ( .A(n2885), .Y(n1814) );
NAND2X4TS U2117 ( .A(n611), .B(n1874), .Y(n909) );
OAI21X4TS U2118 ( .A0(n1876), .A1(n1874), .B0(n1875), .Y(n910) );
XOR2X4TS U2119 ( .A(n911), .B(n1898), .Y(n1900) );
XOR2X4TS U2120 ( .A(n2885), .B(n881), .Y(n1542) );
XNOR2X4TS U2121 ( .A(n732), .B(n878), .Y(n1784) );
XOR2X4TS U2122 ( .A(n702), .B(n646), .Y(n917) );
OAI22X4TS U2123 ( .A0(n406), .A1(n2331), .B0(n555), .B1(mult_x_19_n1751),
.Y(n2389) );
OAI22X4TS U2124 ( .A0(n406), .A1(n1034), .B0(n555), .B1(n1033), .Y(n1045) );
OAI22X4TS U2125 ( .A0(n1774), .A1(n744), .B0(n1797), .B1(n918), .Y(n1801) );
XOR2X4TS U2126 ( .A(n920), .B(n2188), .Y(mult_x_19_n692) );
OAI2BB1X4TS U2127 ( .A0N(n2178), .A1N(n922), .B0(n921), .Y(n2271) );
OAI22X4TS U2128 ( .A0(n2151), .A1(n1282), .B0(n1305), .B1(n667), .Y(n1327)
);
OAI22X1TS U2129 ( .A0(n1607), .A1(n667), .B0(n970), .B1(n969), .Y(n1614) );
OAI21X4TS U2130 ( .A0(n927), .A1(n424), .B0(n926), .Y(n244) );
XOR2X4TS U2131 ( .A(n2610), .B(n928), .Y(n927) );
OAI21X4TS U2132 ( .A0(n2606), .A1(n2605), .B0(n2604), .Y(n928) );
OAI22X4TS U2133 ( .A0(n1030), .A1(n785), .B0(n556), .B1(n1029), .Y(n2870) );
OAI21X4TS U2134 ( .A0(n2423), .A1(n2422), .B0(n2421), .Y(n930) );
XOR2X4TS U2135 ( .A(n931), .B(n2421), .Y(n2520) );
OAI22X4TS U2136 ( .A0(n1685), .A1(n553), .B0(n1686), .B1(n785), .Y(n1687) );
NAND2X8TS U2137 ( .A(n1982), .B(n937), .Y(n936) );
NOR2X8TS U2138 ( .A(n1978), .B(n2266), .Y(n937) );
NOR2X8TS U2139 ( .A(n1980), .B(n1979), .Y(n2266) );
OAI21X4TS U2140 ( .A0(n1291), .A1(n941), .B0(n1290), .Y(n940) );
XNOR2X4TS U2141 ( .A(n839), .B(n1090), .Y(n942) );
OAI22X4TS U2142 ( .A0(n959), .A1(n2468), .B0(n1812), .B1(n764), .Y(n2161) );
OAI2BB1X4TS U2143 ( .A0N(n2379), .A1N(n2378), .B0(n943), .Y(n2395) );
OAI22X4TS U2144 ( .A0(n2310), .A1(n944), .B0(n2307), .B1(n2309), .Y(n2376)
);
OAI22X4TS U2145 ( .A0(n2310), .A1(n945), .B0(n2307), .B1(n944), .Y(n2215) );
OAI22X4TS U2146 ( .A0(n1704), .A1(n437), .B0(n2307), .B1(n945), .Y(n1741) );
XOR2X4TS U2147 ( .A(n598), .B(n597), .Y(mult_x_19_n764) );
XOR2X4TS U2148 ( .A(n2106), .B(n2107), .Y(n950) );
OAI22X4TS U2149 ( .A0(n1773), .A1(n763), .B0(n951), .B1(n2227), .Y(n1777) );
OAI22X4TS U2150 ( .A0(n1812), .A1(n2227), .B0(n760), .B1(n951), .Y(n1836) );
OAI2BB1X4TS U2151 ( .A0N(n1764), .A1N(n1765), .B0(n952), .Y(n2229) );
OAI22X4TS U2152 ( .A0(n1031), .A1(n555), .B0(n785), .B1(n2903), .Y(n2869) );
OAI2BB2X4TS U2153 ( .B0(n956), .B1(n955), .A0N(n2183), .A1N(n2184), .Y(n2269) );
NAND2BX4TS U2154 ( .AN(n2183), .B(n958), .Y(n957) );
OAI22X4TS U2155 ( .A0(n2150), .A1(n2227), .B0(n764), .B1(n959), .Y(n2178) );
XOR2X4TS U2156 ( .A(n433), .B(n651), .Y(n959) );
ADDFHX4TS U2157 ( .A(n2293), .B(n2292), .CI(n2291), .CO(n2107), .S(
mult_x_19_n788) );
OAI22X2TS U2158 ( .A0(n2055), .A1(n1292), .B0(n1887), .B1(n1026), .Y(n1889)
);
XNOR2X4TS U2159 ( .A(n961), .B(n656), .Y(n960) );
XOR2X4TS U2160 ( .A(n1874), .B(n611), .Y(n961) );
XOR2X4TS U2161 ( .A(n786), .B(n3013), .Y(n2315) );
XOR2X4TS U2162 ( .A(n3013), .B(n2313), .Y(n2320) );
NAND2X1TS U2163 ( .A(n963), .B(n2197), .Y(n2199) );
OA21X4TS U2164 ( .A0(n3037), .A1(n3036), .B0(n3038), .Y(n962) );
NAND2X8TS U2165 ( .A(n631), .B(n3099), .Y(mult_x_19_n423) );
OAI22X4TS U2166 ( .A0(n2315), .A1(n803), .B0(n590), .B1(n968), .Y(n2343) );
XOR2X4TS U2167 ( .A(n3013), .B(n2476), .Y(n968) );
OAI2BB1X4TS U2168 ( .A0N(n1361), .A1N(n982), .B0(n983), .Y(mult_x_19_n874)
);
OAI22X4TS U2169 ( .A0(n802), .A1(n981), .B0(n2311), .B1(n976), .Y(n2374) );
XNOR2X4TS U2170 ( .A(n628), .B(n650), .Y(n1325) );
XNOR2X4TS U2171 ( .A(n2241), .B(n881), .Y(n1319) );
OAI21X4TS U2172 ( .A0(n982), .A1(n1361), .B0(n1360), .Y(n983) );
XOR2X4TS U2173 ( .A(n984), .B(n1360), .Y(mult_x_19_n875) );
OAI22X4TS U2174 ( .A0(n676), .A1(n985), .B0(n2471), .B1(n1284), .Y(n1290) );
XNOR2X4TS U2175 ( .A(n691), .B(n1884), .Y(n985) );
OAI22X4TS U2176 ( .A0(n1798), .A1(n742), .B0(n986), .B1(n2034), .Y(n1804) );
XOR2X4TS U2177 ( .A(n2238), .B(n693), .Y(n986) );
OAI2BB1X4TS U2178 ( .A0N(n708), .A1N(n2340), .B0(n987), .Y(n1351) );
XNOR2X4TS U2179 ( .A(n791), .B(n2476), .Y(n991) );
XNOR2X4TS U2180 ( .A(n2948), .B(n881), .Y(n1760) );
XOR2X4TS U2181 ( .A(n2221), .B(n605), .Y(n992) );
OAI22X4TS U2182 ( .A0(n993), .A1(n764), .B0(n1674), .B1(mult_x_19_n1587),
.Y(n1328) );
XOR2X4TS U2183 ( .A(n2319), .B(n605), .Y(n993) );
OAI22X2TS U2184 ( .A0(n1319), .A1(n2311), .B0(n2055), .B1(n994), .Y(n2417)
);
OAI2BB1X4TS U2185 ( .A0N(n2351), .A1N(n2352), .B0(n995), .Y(n1895) );
OAI21X4TS U2186 ( .A0(n2351), .A1(n2352), .B0(n2350), .Y(n995) );
OAI22X4TS U2187 ( .A0(n2055), .A1(n1324), .B0(n1292), .B1(n1014), .Y(n1343)
);
XOR2X4TS U2188 ( .A(n627), .B(n755), .Y(n1292) );
XOR2X4TS U2189 ( .A(n2947), .B(n2950), .Y(n1111) );
NAND2X2TS U2190 ( .A(n699), .B(n1247), .Y(n1248) );
OAI21X2TS U2191 ( .A0(n1642), .A1(n1991), .B0(n1643), .Y(n1180) );
INVX8TS U2192 ( .A(n1386), .Y(n1469) );
INVX6TS U2193 ( .A(n1260), .Y(n1237) );
AOI21X2TS U2194 ( .A0(n2667), .A1(n1531), .B0(n1530), .Y(n1532) );
ADDFHX2TS U2195 ( .A(n2449), .B(n2448), .CI(n2447), .CO(n2457), .S(n2507) );
AO22X4TS U2196 ( .A0(n2946), .A1(n651), .B0(n2474), .B1(n2238), .Y(n1503) );
NAND2X4TS U2197 ( .A(n2262), .B(n3101), .Y(mult_x_19_n110) );
AOI2BB2X2TS U2198 ( .B0(n2700), .B1(n2677), .A0N(n806), .A1N(n1625), .Y(
n3335) );
AOI21X4TS U2199 ( .A0(n1455), .A1(n1379), .B0(n1378), .Y(n1384) );
XNOR2X4TS U2200 ( .A(n492), .B(n398), .Y(n1704) );
XNOR2X4TS U2201 ( .A(n604), .B(n399), .Y(n2325) );
AOI21X4TS U2202 ( .A0(n2635), .A1(n2634), .B0(n2633), .Y(n2692) );
ADDFHX4TS U2203 ( .A(n1112), .B(n1113), .CI(n1114), .CO(n1160), .S(n1133) );
ADDFHX2TS U2204 ( .A(n1124), .B(n1123), .CI(n1122), .CO(n1158), .S(n1138) );
OAI21X4TS U2205 ( .A0(n1210), .A1(n1215), .B0(n1214), .Y(n1216) );
ADDFHX4TS U2206 ( .A(n1043), .B(n1042), .CI(n1041), .CO(n1048), .S(n1047) );
NAND2X8TS U2207 ( .A(n1904), .B(n1903), .Y(n2537) );
XNOR2X4TS U2208 ( .A(n1761), .B(n786), .Y(n1695) );
XNOR2X4TS U2209 ( .A(n1761), .B(n2476), .Y(n1680) );
ADDFHX4TS U2210 ( .A(n1835), .B(n1836), .CI(n1837), .CO(n2162), .S(n1839) );
ADDFHX4TS U2211 ( .A(n1775), .B(n1777), .CI(n1776), .CO(n1840), .S(n1809) );
OAI22X2TS U2212 ( .A0(n1762), .A1(n1035), .B0(n1028), .B1(n756), .Y(n1041)
);
OAI22X2TS U2213 ( .A0(n1762), .A1(n1057), .B0(n1058), .B1(n734), .Y(n1063)
);
OAI22X4TS U2214 ( .A0(n1796), .A1(n2900), .B0(n756), .B1(n1037), .Y(n1038)
);
OAI22X2TS U2215 ( .A0(n1762), .A1(n1022), .B0(n1057), .B1(n734), .Y(n1066)
);
OAI22X2TS U2216 ( .A0(n676), .A1(n2070), .B0(n2016), .B1(n799), .Y(n2042) );
OAI22X4TS U2217 ( .A0(n676), .A1(n2071), .B0(n2070), .B1(n2471), .Y(n2082)
);
ADDFHX4TS U2218 ( .A(n1811), .B(n1809), .CI(n1810), .CO(n2011), .S(n2025) );
OAI22X4TS U2219 ( .A0(n2041), .A1(n1771), .B0(n1780), .B1(n800), .Y(n1781)
);
ADDFHX4TS U2220 ( .A(n1803), .B(n1804), .CI(n1805), .CO(n2024), .S(n2063) );
OAI22X2TS U2221 ( .A0(n551), .A1(n601), .B0(n695), .B1(n646), .Y(n1551) );
XNOR2X4TS U2222 ( .A(n628), .B(n2313), .Y(n1676) );
XNOR2X4TS U2223 ( .A(n753), .B(n2313), .Y(n2016) );
INVX8TS U2224 ( .A(n2538), .Y(n2257) );
NOR2X8TS U2225 ( .A(n1904), .B(n1903), .Y(n2538) );
OAI21X4TS U2226 ( .A0(n1437), .A1(n1422), .B0(n1421), .Y(n1427) );
INVX6TS U2227 ( .A(n2692), .Y(n2735) );
XNOR2X4TS U2228 ( .A(n792), .B(n762), .Y(n1779) );
ADDFHX4TS U2229 ( .A(n1157), .B(n1156), .CI(n1155), .CO(n1726), .S(n1159) );
ADDFHX2TS U2230 ( .A(n2555), .B(n2554), .CI(n2553), .CO(mult_x_19_n639), .S(
n2556) );
ADDFHX4TS U2231 ( .A(n2101), .B(n2100), .CI(n2099), .CO(n2292), .S(n2295) );
OAI21X4TS U2232 ( .A0(n765), .A1(n1488), .B0(n1487), .Y(n1489) );
OAI22X4TS U2233 ( .A0(n1796), .A1(n1164), .B0(n1696), .B1(n734), .Y(n1721)
);
NAND2BX2TS U2234 ( .AN(n2904), .B(n2947), .Y(n1031) );
AOI21X4TS U2235 ( .A0(n2667), .A1(n1950), .B0(n1949), .Y(n1951) );
NOR2X4TS U2236 ( .A(n1940), .B(n1947), .Y(n1950) );
ADDFHX4TS U2237 ( .A(n1154), .B(n1153), .CI(n1152), .CO(n1727), .S(n1165) );
NAND2X2TS U2238 ( .A(n796), .B(n2675), .Y(n3305) );
AOI2BB2X2TS U2239 ( .B0(n1483), .B1(n2675), .A0N(n807), .A1N(n3127), .Y(
n3311) );
INVX8TS U2240 ( .A(n1483), .Y(n1669) );
ADDFHX4TS U2241 ( .A(n1167), .B(n1166), .CI(n1165), .CO(n1907), .S(n1170) );
INVX8TS U2242 ( .A(n1375), .Y(n1455) );
XNOR2X4TS U2243 ( .A(n365), .B(n366), .Y(n2924) );
XNOR2X4TS U2244 ( .A(n1884), .B(n2319), .Y(n1284) );
NAND2X4TS U2245 ( .A(n1404), .B(n1403), .Y(n1407) );
INVX4TS U2246 ( .A(n1387), .Y(n1404) );
OAI22X2TS U2247 ( .A0(n769), .A1(n2035), .B0(n1798), .B1(n2034), .Y(n2056)
);
BUFX20TS U2248 ( .A(n1817), .Y(n2034) );
NAND2X4TS U2249 ( .A(n2994), .B(n1009), .Y(n1177) );
ADDFHX4TS U2250 ( .A(n1135), .B(n1134), .CI(n1133), .CO(n1169), .S(n1136) );
XOR2X4TS U2251 ( .A(n1527), .B(n1526), .Y(Sgf_operation_Result[8]) );
AOI21X2TS U2252 ( .A0(n2251), .A1(n2252), .B0(n2250), .Y(n2253) );
NOR2X4TS U2253 ( .A(n1433), .B(n1423), .Y(n1262) );
MX2X6TS U2254 ( .A(n1657), .B(n3246), .S0(n586), .Y(n266) );
ADDFHX2TS U2255 ( .A(n2544), .B(n2543), .CI(n2542), .CO(n2554), .S(n2400) );
AO21X4TS U2256 ( .A0(n1796), .A1(n756), .B0(n2900), .Y(n2058) );
OAI22X4TS U2257 ( .A0(n838), .A1(n1109), .B0(n1108), .B1(n590), .Y(n1113) );
ADDFHX4TS U2258 ( .A(n1878), .B(n1877), .CI(n1879), .CO(n2510), .S(n1874) );
AOI21X4TS U2259 ( .A0(n2252), .A1(n1369), .B0(n1368), .Y(n1370) );
XNOR2X4TS U2260 ( .A(n2052), .B(n399), .Y(n1058) );
NOR2X4TS U2261 ( .A(n569), .B(n2979), .Y(n1638) );
XNOR2X4TS U2262 ( .A(n433), .B(n787), .Y(n2469) );
OAI22X2TS U2263 ( .A0(n802), .A1(n1107), .B0(n1106), .B1(n2311), .Y(n1114)
);
NAND2X4TS U2264 ( .A(n1246), .B(n1267), .Y(n1451) );
NAND2X4TS U2265 ( .A(n1268), .B(n1267), .Y(n1464) );
CMPR22X2TS U2266 ( .A(n2226), .B(n2225), .CO(n2367), .S(n2242) );
OAI22X2TS U2267 ( .A0(n677), .A1(n1745), .B0(n2220), .B1(n2322), .Y(n2226)
);
ADDFHX2TS U2268 ( .A(n2098), .B(n2097), .CI(n2096), .CO(n2104), .S(n2444) );
OAI22X4TS U2269 ( .A0(n2053), .A1(n2055), .B0(n1026), .B1(n2241), .Y(n2060)
);
OAI22X4TS U2270 ( .A0(n802), .A1(n1104), .B0(n1107), .B1(n1026), .Y(n1140)
);
AO21X4TS U2271 ( .A0(n2312), .A1(n1014), .B0(n2899), .Y(n1775) );
OAI22X2TS U2272 ( .A0(n802), .A1(n1017), .B0(n1056), .B1(n2311), .Y(n1076)
);
XOR2X4TS U2273 ( .A(n2865), .B(n2866), .Y(n2867) );
NAND2X2TS U2274 ( .A(n2864), .B(n2863), .Y(n2866) );
ADDFHX4TS U2275 ( .A(n2501), .B(n2500), .CI(n2499), .CO(n2534), .S(
mult_x_19_n604) );
ADDFHX4TS U2276 ( .A(n1522), .B(n1521), .CI(n1520), .CO(n2526), .S(n2500) );
ADDFHX4TS U2277 ( .A(n2492), .B(n2491), .CI(n2490), .CO(n2499), .S(n2497) );
NAND2X4TS U2278 ( .A(n2437), .B(n2436), .Y(mult_x_19_n112) );
CMPR22X2TS U2279 ( .A(n1120), .B(n1121), .CO(n1166), .S(n1122) );
NAND2X6TS U2280 ( .A(n1264), .B(n1263), .Y(n1403) );
NOR2X4TS U2281 ( .A(n1242), .B(n1264), .Y(n1376) );
NAND3X6TS U2282 ( .A(n3206), .B(n3205), .C(n3204), .Y(n2845) );
XNOR2X4TS U2283 ( .A(n2947), .B(n2476), .Y(n1686) );
ADDFHX2TS U2284 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2492), .S(n2495) );
ADDFHX2TS U2285 ( .A(n2217), .B(n2216), .CI(n2215), .CO(n2393), .S(n2245) );
NOR2X8TS U2286 ( .A(n1009), .B(n2984), .Y(n1179) );
ADDFHX4TS U2287 ( .A(n2161), .B(n2160), .CI(n2159), .CO(n2182), .S(n2141) );
NAND2X4TS U2288 ( .A(n2599), .B(n2604), .Y(n2600) );
NAND2X4TS U2289 ( .A(n2261), .B(n998), .Y(n375) );
NAND2X4TS U2290 ( .A(n1242), .B(n1264), .Y(n1377) );
NAND2X4TS U2291 ( .A(n2582), .B(n2581), .Y(n3354) );
NOR2X4TS U2292 ( .A(n1243), .B(n1265), .Y(n1245) );
ADDFHX4TS U2293 ( .A(n2426), .B(n2424), .CI(n2425), .CO(n2431), .S(n2394) );
ADDFHX4TS U2294 ( .A(n2408), .B(n2407), .CI(n2406), .CO(n2429), .S(n2425) );
NOR2X8TS U2295 ( .A(FSM_selector_B_1_), .B(n1228), .Y(n1223) );
XNOR2X4TS U2296 ( .A(n1474), .B(n1475), .Y(n1479) );
NOR2X4TS U2297 ( .A(n1474), .B(n1475), .Y(n1276) );
MXI2X4TS U2298 ( .A(n1419), .B(n1418), .S0(n427), .Y(n2786) );
XNOR2X4TS U2299 ( .A(n2947), .B(n601), .Y(n1110) );
ADDFHX4TS U2300 ( .A(n2382), .B(n2381), .CI(n2380), .CO(n2426), .S(n2378) );
BUFX3TS U2301 ( .A(n772), .Y(n3284) );
XNOR2X4TS U2302 ( .A(n1430), .B(n1429), .Y(n1431) );
OAI21X4TS U2303 ( .A0(n1439), .A1(n1433), .B0(n1434), .Y(n1430) );
ADDFHX4TS U2304 ( .A(n1025), .B(n1023), .CI(n1024), .CO(n1050), .S(n1049) );
OAI21X4TS U2305 ( .A0(n2249), .A1(n2967), .B0(n2968), .Y(n1367) );
AOI21X4TS U2306 ( .A0(n570), .A1(n571), .B0(n2983), .Y(n2249) );
OAI22X2TS U2307 ( .A0(n407), .A1(n2150), .B0(n1547), .B1(n2468), .Y(n1588)
);
OAI22X4TS U2308 ( .A0(n407), .A1(n1547), .B0(n1546), .B1(n2468), .Y(n1562)
);
OAI22X2TS U2309 ( .A0(n407), .A1(n1546), .B0(n1540), .B1(n2468), .Y(n1569)
);
OAI22X4TS U2310 ( .A0(n764), .A1(n1802), .B0(n1773), .B1(n2227), .Y(n1800)
);
OAI22X2TS U2311 ( .A0(n760), .A1(n2073), .B0(n2072), .B1(n2227), .Y(n2081)
);
OAI22X2TS U2312 ( .A0(n407), .A1(n604), .B0(n2468), .B1(n2888), .Y(n2477) );
OAI22X4TS U2313 ( .A0(n764), .A1(n1681), .B0(n1743), .B1(n2227), .Y(n1758)
);
OAI22X4TS U2314 ( .A0(n2072), .A1(n763), .B0(n1802), .B1(n2227), .Y(n2061)
);
OAI22X4TS U2315 ( .A0(n407), .A1(n2228), .B0(n2326), .B1(n2227), .Y(n2372)
);
ADDFHX2TS U2316 ( .A(n2385), .B(n2384), .CI(n2383), .CO(n2408), .S(n2392) );
ADDFHX4TS U2317 ( .A(n1826), .B(n1825), .CI(n1824), .CO(n2137), .S(n2030) );
ADDFHX2TS U2318 ( .A(n655), .B(n2478), .CI(n2477), .CO(n1510), .S(n2488) );
ADDFHX2TS U2319 ( .A(n1569), .B(n1568), .CI(n1567), .CO(n2401), .S(n1573) );
NOR2X2TS U2320 ( .A(n664), .B(Sgf_normalized_result[0]), .Y(n2591) );
XNOR2X4TS U2321 ( .A(n2052), .B(n828), .Y(n1028) );
XNOR2X4TS U2322 ( .A(n791), .B(n2794), .Y(n1282) );
ADDFHX4TS U2323 ( .A(n2141), .B(n2140), .CI(n2139), .CO(n2187), .S(n2138) );
XNOR2X4TS U2324 ( .A(n797), .B(n786), .Y(n1815) );
XNOR2X4TS U2325 ( .A(n797), .B(n2476), .Y(n2155) );
ADDFHX4TS U2326 ( .A(n2346), .B(n2345), .CI(n2344), .CO(n2350), .S(n2353) );
NOR2X8TS U2327 ( .A(n1443), .B(n1442), .Y(n1414) );
INVX6TS U2328 ( .A(n1254), .Y(n1443) );
XNOR2X4TS U2329 ( .A(n2013), .B(n398), .Y(n1693) );
XNOR2X4TS U2330 ( .A(n999), .B(n1630), .Y(n1631) );
XNOR2X4TS U2331 ( .A(n2241), .B(n2796), .Y(n1017) );
XNOR2X4TS U2332 ( .A(n1536), .B(n1535), .Y(n1537) );
ADDFHX4TS U2333 ( .A(n1147), .B(n1146), .CI(n1145), .CO(n1137), .S(n1972) );
NAND3X4TS U2334 ( .A(n3223), .B(n3222), .C(n3221), .Y(n2856) );
ADDFHX2TS U2335 ( .A(n2547), .B(n2546), .CI(n2545), .CO(n2487), .S(n2553) );
AOI21X4TS U2336 ( .A0(n1213), .A1(n1849), .B0(n1212), .Y(n1214) );
ADDFHX4TS U2337 ( .A(n2271), .B(n2270), .CI(n2269), .CO(n2280), .S(n2272) );
AOI2BB2X4TS U2338 ( .B0(n2700), .B1(n265), .A0N(n806), .A1N(n3146), .Y(n2626) );
OAI21X4TS U2339 ( .A0(n2198), .A1(n2976), .B0(n2007), .Y(n2008) );
ADDFHX4TS U2340 ( .A(n2461), .B(n2460), .CI(n2459), .CO(n2462), .S(
mult_x_19_n832) );
ADDFHX4TS U2341 ( .A(n2357), .B(n2356), .CI(n2355), .CO(n1361), .S(n2358) );
ADDFHX4TS U2342 ( .A(n1331), .B(n1330), .CI(n1329), .CO(n1897), .S(n2356) );
ADDFHX2TS U2343 ( .A(n1575), .B(n1574), .CI(n1573), .CO(n2403), .S(n2399) );
ADDFHX4TS U2344 ( .A(n2519), .B(n2518), .CI(n2517), .CO(n2289), .S(n2524) );
XNOR2X4TS U2345 ( .A(n2218), .B(n2313), .Y(n2219) );
OR2X8TS U2346 ( .A(n1616), .B(n1615), .Y(n2287) );
ADDFHX4TS U2347 ( .A(n1610), .B(n1608), .CI(n1609), .CO(n1616), .S(n1903) );
NOR2X6TS U2348 ( .A(n1939), .B(n1941), .Y(n1944) );
ADDFHX2TS U2349 ( .A(n398), .B(n798), .CI(n1787), .CO(n1828), .S(n1793) );
XNOR2X4TS U2350 ( .A(n2052), .B(n2793), .Y(n1057) );
OAI22X2TS U2351 ( .A0(n768), .A1(n2222), .B0(n2333), .B1(n2485), .Y(n2383)
);
OAI22X2TS U2352 ( .A0(n769), .A1(n2889), .B0(n1151), .B1(n842), .Y(n1715) );
OAI22X2TS U2353 ( .A0(n767), .A1(n2333), .B0(n2332), .B1(n2485), .Y(n2388)
);
XNOR2X4TS U2354 ( .A(n878), .B(n867), .Y(n2321) );
NOR2X8TS U2355 ( .A(n1149), .B(n1148), .Y(n2433) );
ADDFHX4TS U2356 ( .A(n1711), .B(n1710), .CI(n1709), .CO(n1751), .S(n1718) );
ADDFHX4TS U2357 ( .A(n2021), .B(n2020), .CI(n2019), .CO(n2027), .S(n2087) );
NOR2X8TS U2358 ( .A(n1204), .B(n2660), .Y(n2651) );
NAND2X6TS U2359 ( .A(n2671), .B(n2659), .Y(n1204) );
NAND2X4TS U2360 ( .A(n2843), .B(n2850), .Y(n2716) );
NOR2X8TS U2361 ( .A(n1005), .B(n2977), .Y(n2122) );
ADDFHX4TS U2362 ( .A(n2455), .B(n2454), .CI(n2453), .CO(n2505), .S(n2509) );
XNOR2X4TS U2363 ( .A(n792), .B(n786), .Y(n2152) );
OAI22X2TS U2364 ( .A0(n1885), .A1(n676), .B0(n2071), .B1(n799), .Y(n2093) );
XNOR2X4TS U2365 ( .A(n1884), .B(n762), .Y(n2071) );
NAND2BX2TS U2366 ( .AN(n789), .B(n969), .Y(n1307) );
ADDFHX2TS U2367 ( .A(n663), .B(n2243), .CI(n2242), .CO(n2380), .S(n2244) );
NOR2X4TS U2368 ( .A(n1452), .B(n1249), .Y(n1251) );
NOR2X4TS U2369 ( .A(n699), .B(n1247), .Y(n1249) );
OAI21X2TS U2370 ( .A0(n1942), .A1(n1941), .B0(n583), .Y(n1943) );
ADDFHX4TS U2371 ( .A(n1909), .B(n1908), .CI(n1907), .CO(n1962), .S(n1913) );
ADDFHX2TS U2372 ( .A(n1581), .B(n1580), .CI(n1579), .CO(n1576), .S(n2277) );
NAND2X4TS U2373 ( .A(n2435), .B(n2434), .Y(mult_x_19_n113) );
XNOR2X4TS U2374 ( .A(n2218), .B(n881), .Y(n1299) );
ADDFHX4TS U2375 ( .A(n2173), .B(n2172), .CI(n2171), .CO(n2274), .S(n2186) );
AOI21X2TS U2376 ( .A0(n1929), .A1(n1928), .B0(n1927), .Y(n1930) );
NOR2X4TS U2377 ( .A(n1922), .B(n1925), .Y(n1928) );
ADDFHX4TS U2378 ( .A(n1731), .B(n1730), .CI(n1729), .CO(n1767), .S(n1958) );
OAI22X4TS U2379 ( .A0(n1796), .A1(n1302), .B0(n1886), .B1(n756), .Y(n1881)
);
XNOR2X4TS U2380 ( .A(n791), .B(n638), .Y(n1289) );
XNOR2X4TS U2381 ( .A(n705), .B(n638), .Y(n1108) );
XNOR2X4TS U2382 ( .A(n2218), .B(n1869), .Y(n1320) );
XNOR2X4TS U2383 ( .A(n2947), .B(n879), .Y(n2331) );
XNOR2X4TS U2384 ( .A(n604), .B(n762), .Y(n1303) );
AOI21X2TS U2385 ( .A0(n1929), .A1(n1660), .B0(n1659), .Y(n1661) );
ADDFHX4TS U2386 ( .A(n2175), .B(n2174), .CI(n2176), .CO(n2276), .S(n2273) );
ADDFHX4TS U2387 ( .A(n2024), .B(n2023), .CI(n2022), .CO(n2029), .S(n2066) );
ADDFHX2TS U2388 ( .A(n2373), .B(n2372), .CI(n2371), .CO(n2419), .S(n2366) );
OAI21X4TS U2389 ( .A0(n1855), .A1(n567), .B0(n1856), .Y(n2115) );
NAND2X4TS U2390 ( .A(n573), .B(n3061), .Y(n1856) );
ADDFHX4TS U2391 ( .A(n1718), .B(n1719), .CI(n1717), .CO(n1747), .S(n1960) );
ADDFHX4TS U2392 ( .A(n2164), .B(n2163), .CI(n2162), .CO(n2168), .S(n2134) );
ADDFHX4TS U2393 ( .A(n1834), .B(n1833), .CI(n1832), .CO(n2163), .S(n1838) );
XNOR2X4TS U2394 ( .A(n1814), .B(n2313), .Y(n1780) );
OAI21X4TS U2395 ( .A0(n2865), .A1(n2862), .B0(n2863), .Y(n2598) );
AOI21X4TS U2396 ( .A0(n2780), .A1(n2779), .B0(n1040), .Y(n2865) );
XNOR2X4TS U2397 ( .A(n787), .B(n690), .Y(n1783) );
XNOR2X4TS U2398 ( .A(n753), .B(n2476), .Y(n1778) );
ADDFHX4TS U2399 ( .A(n2504), .B(n2503), .CI(n2502), .CO(n2513), .S(n1898) );
XNOR2X4TS U2400 ( .A(n2948), .B(n668), .Y(n1308) );
XOR2X4TS U2401 ( .A(n2255), .B(n2918), .Y(n2256) );
ADDFHX4TS U2402 ( .A(n2089), .B(n2088), .CI(n2087), .CO(n2067), .S(n2298) );
AND2X8TS U2403 ( .A(n2586), .B(n2585), .Y(n2835) );
OAI22X2TS U2404 ( .A0(n437), .A1(n1115), .B0(n1162), .B1(n2048), .Y(n1155)
);
OAI22X2TS U2405 ( .A0(n1300), .A1(n1099), .B0(n1115), .B1(n2048), .Y(n1121)
);
INVX6TS U2406 ( .A(n2635), .Y(n2858) );
OAI21X4TS U2407 ( .A0(n2591), .A1(n3138), .B0(n2590), .Y(n2635) );
XNOR2X4TS U2408 ( .A(n2902), .B(n650), .Y(n2317) );
AO21X4TS U2409 ( .A0(n841), .A1(n1813), .B0(n2896), .Y(n2159) );
OAI22X2TS U2410 ( .A0(n2330), .A1(n2069), .B0(mult_x_19_n1674), .B1(n2068),
.Y(n2059) );
OAI22X2TS U2411 ( .A0(n790), .A1(n1702), .B0(n1744), .B1(n1813), .Y(n1740)
);
OAI22X2TS U2412 ( .A0(n841), .A1(n1119), .B0(n1118), .B1(n1813), .Y(n1123)
);
OAI22X2TS U2413 ( .A0(n790), .A1(n1082), .B0(n1101), .B1(n2327), .Y(n1131)
);
OAI22X2TS U2414 ( .A0(n790), .A1(n2329), .B0(n2328), .B1(n2327), .Y(n2390)
);
OAI22X2TS U2415 ( .A0(n790), .A1(mult_x_19_n1677), .B0(mult_x_19_n1676),
.B1(n2068), .Y(n2095) );
XNOR2X4TS U2416 ( .A(n2218), .B(n646), .Y(n2329) );
XNOR2X4TS U2417 ( .A(n1761), .B(n2796), .Y(n1035) );
ADDFHX4TS U2418 ( .A(n2528), .B(n2526), .CI(n2527), .CO(n2536), .S(n2533) );
XOR2X4TS U2419 ( .A(n619), .B(n824), .Y(n2473) );
XOR2X4TS U2420 ( .A(n2952), .B(n824), .Y(n1823) );
XNOR2X4TS U2421 ( .A(n500), .B(n824), .Y(n1505) );
XOR2X4TS U2422 ( .A(n2951), .B(n824), .Y(n1322) );
ADDFHX4TS U2423 ( .A(n2064), .B(n2062), .CI(n2063), .CO(n2026), .S(n2291) );
ADDFHX4TS U2424 ( .A(n1351), .B(n1349), .CI(n1350), .CO(n2351), .S(n2288) );
XNOR2X4TS U2425 ( .A(n2239), .B(n639), .Y(n1022) );
XNOR2X4TS U2426 ( .A(n1884), .B(n638), .Y(n2323) );
ADDFHX4TS U2427 ( .A(n2234), .B(n2233), .CI(n2232), .CO(n2379), .S(n2230) );
AO21X4TS U2428 ( .A0(n2310), .A1(n2307), .B0(n2891), .Y(n1564) );
ADDFHX4TS U2429 ( .A(n1977), .B(n1976), .CI(n1975), .CO(n1979), .S(n1098) );
ADDFHX2TS U2430 ( .A(n2417), .B(n2416), .CI(n2415), .CO(n2517), .S(n2522) );
ADDFHX2TS U2431 ( .A(n671), .B(n762), .CI(n1549), .CO(n1561), .S(n2180) );
XNOR2X4TS U2432 ( .A(n1884), .B(n671), .Y(n1885) );
XNOR2X4TS U2433 ( .A(n693), .B(n2313), .Y(n1304) );
OAI22X2TS U2434 ( .A0(n2055), .A1(n1018), .B0(n1017), .B1(n2311), .Y(n1020)
);
XNOR2X4TS U2435 ( .A(n693), .B(n2796), .Y(n1694) );
ADDFHX4TS U2436 ( .A(n2170), .B(n2169), .CI(n2168), .CO(n2189), .S(n2185) );
INVX4TS U2437 ( .A(n2433), .Y(n2435) );
OAI21X4TS U2438 ( .A0(n2433), .A1(n2282), .B0(n2434), .Y(mult_x_19_n466) );
XNOR2X4TS U2439 ( .A(n1623), .B(n1622), .Y(n1624) );
MX2X6TS U2440 ( .A(n1668), .B(n3245), .S0(n586), .Y(n265) );
ADDFHX2TS U2441 ( .A(n737), .B(n2077), .CI(n2076), .CO(n2447), .S(n2450) );
ADDFHX2TS U2442 ( .A(n2080), .B(n2078), .CI(n2079), .CO(n2443), .S(n2438) );
ADDFHX4TS U2443 ( .A(n1572), .B(n1571), .CI(n1570), .CO(mult_x_19_n647), .S(
mult_x_19_n648) );
XNOR2X4TS U2444 ( .A(n2948), .B(n828), .Y(n1034) );
XNOR2X4TS U2445 ( .A(n2218), .B(n828), .Y(n1082) );
XOR2X4TS U2446 ( .A(n690), .B(n659), .Y(n1059) );
OAI22X2TS U2447 ( .A0(n2330), .A1(n2898), .B0(n2068), .B1(n2896), .Y(n1830)
);
NAND2BX2TS U2448 ( .AN(n2904), .B(n2898), .Y(n1062) );
XNOR2X4TS U2449 ( .A(n2898), .B(n638), .Y(n1101) );
ADDFHX4TS U2450 ( .A(n1563), .B(n1562), .CI(n1561), .CO(n1575), .S(n1592) );
ADDFHX2TS U2451 ( .A(n1519), .B(n1518), .CI(n1517), .CO(n1599), .S(n1520) );
ADDFHX4TS U2452 ( .A(n2030), .B(n2029), .CI(n2028), .CO(n1842), .S(n2031) );
ADDFHX4TS U2453 ( .A(n2027), .B(n2026), .CI(n2025), .CO(n2028), .S(n2065) );
OAI21X2TS U2454 ( .A0(n1199), .A1(n2645), .B0(n1198), .Y(n1200) );
NAND2X4TS U2455 ( .A(n579), .B(n2997), .Y(n2645) );
XNOR2X4TS U2456 ( .A(n1761), .B(n2313), .Y(n1696) );
INVX16TS U2457 ( .A(n2901), .Y(n1761) );
XNOR2X4TS U2458 ( .A(n511), .B(n672), .Y(n1774) );
NOR2X6TS U2459 ( .A(n1236), .B(n1257), .Y(n1422) );
NAND2X4TS U2460 ( .A(n1236), .B(n1257), .Y(n1421) );
ADDFHX4TS U2461 ( .A(n2280), .B(n2279), .CI(n2278), .CO(mult_x_19_n675), .S(
mult_x_19_n676) );
ADDFHX4TS U2462 ( .A(n2277), .B(n2276), .CI(n2275), .CO(n2397), .S(n2278) );
XNOR2X4TS U2463 ( .A(n1814), .B(n1869), .Y(n1544) );
XNOR2X4TS U2464 ( .A(n693), .B(n786), .Y(n1893) );
ADDFHX4TS U2465 ( .A(n1298), .B(n1297), .CI(n1296), .CO(n1876), .S(n2357) );
ADDFHX4TS U2466 ( .A(n1872), .B(n1873), .CI(n1871), .CO(n2502), .S(n1875) );
ADDFHX2TS U2467 ( .A(n692), .B(n1831), .CI(n1830), .CO(n2164), .S(n1827) );
XNOR2X4TS U2468 ( .A(n792), .B(n601), .Y(n2153) );
XOR2X4TS U2469 ( .A(n1437), .B(n1436), .Y(n1441) );
OR2X8TS U2470 ( .A(n1172), .B(n1171), .Y(n2437) );
ADDFHX4TS U2471 ( .A(n1915), .B(n1914), .CI(n1913), .CO(n1965), .S(n1172) );
XNOR2X4TS U2472 ( .A(n2892), .B(n639), .Y(n1684) );
XNOR2X4TS U2473 ( .A(n2902), .B(n668), .Y(n1886) );
ADDFHX4TS U2474 ( .A(n1752), .B(n1751), .CI(n1750), .CO(n2231), .S(n1748) );
ADDFHX4TS U2475 ( .A(n2396), .B(n2395), .CI(n2394), .CO(mult_x_19_n976), .S(
mult_x_19_n977) );
ADDFHX4TS U2476 ( .A(n2414), .B(n2413), .CI(n2412), .CO(n2427), .S(n2396) );
XNOR2X4TS U2477 ( .A(n464), .B(n828), .Y(n1162) );
XNOR2X4TS U2478 ( .A(n2948), .B(n884), .Y(n1685) );
XNOR2X4TS U2479 ( .A(n693), .B(n884), .Y(n2035) );
XNOR2X4TS U2480 ( .A(n497), .B(n884), .Y(n2154) );
XNOR2X4TS U2481 ( .A(n644), .B(n884), .Y(n1773) );
OAI22X2TS U2482 ( .A0(n767), .A1(n1584), .B0(n1548), .B1(n842), .Y(n2181) );
OAI21X4TS U2483 ( .A0(n2664), .A1(n1204), .B0(n1203), .Y(n2650) );
OAI2BB2X2TS U2484 ( .B0(n3098), .B1(n671), .A0N(n2474), .A1N(n674), .Y(n1831) );
ADDFHX4TS U2485 ( .A(n1897), .B(n1896), .CI(n1895), .CO(n1901), .S(n1360) );
ADDFHX4TS U2486 ( .A(n2498), .B(n2497), .CI(n2496), .CO(mult_x_19_n613), .S(
mult_x_19_n614) );
XNOR2X4TS U2487 ( .A(n2218), .B(n884), .Y(n1321) );
OAI22X2TS U2488 ( .A0(n790), .A1(n1061), .B0(n1060), .B1(n2327), .Y(n1070)
);
XNOR2X4TS U2489 ( .A(n2898), .B(n2221), .Y(n1163) );
XNOR2X4TS U2490 ( .A(n792), .B(n2319), .Y(n1797) );
XNOR2X4TS U2491 ( .A(n969), .B(n798), .Y(n1894) );
XNOR2X4TS U2492 ( .A(n791), .B(n429), .Y(n2038) );
XNOR2X4TS U2493 ( .A(n645), .B(n761), .Y(n2015) );
XNOR2X4TS U2494 ( .A(n693), .B(n1869), .Y(n1798) );
ADDFHX4TS U2495 ( .A(n3056), .B(n3055), .CI(n3057), .CO(n1007), .S(n1005) );
XNOR2X4TS U2496 ( .A(n2898), .B(n398), .Y(n1118) );
ADDFHX4TS U2497 ( .A(n2138), .B(n2137), .CI(n2136), .CO(n2166), .S(n1841) );
ADDFHX2TS U2498 ( .A(n868), .B(n1611), .CI(n879), .CO(n2130), .S(n1612) );
XNOR2X4TS U2499 ( .A(n433), .B(n879), .Y(n2150) );
XNOR2X4TS U2500 ( .A(n500), .B(n879), .Y(n2481) );
XNOR2X4TS U2501 ( .A(n2013), .B(n879), .Y(n2074) );
NAND2X8TS U2502 ( .A(n1235), .B(n1227), .Y(n1256) );
INVX16TS U2503 ( .A(n1223), .Y(n1235) );
XNOR2X4TS U2504 ( .A(n792), .B(n2221), .Y(n2037) );
NOR2X4TS U2505 ( .A(n1047), .B(n1046), .Y(n2862) );
XNOR2X4TS U2506 ( .A(n645), .B(n2221), .Y(n1883) );
XNOR2X4TS U2507 ( .A(n2218), .B(n736), .Y(n1060) );
ADDFHX4TS U2508 ( .A(n1348), .B(n1346), .CI(n1347), .CO(n1862), .S(n2352) );
NOR2X8TS U2509 ( .A(n2728), .B(n2688), .Y(n2734) );
XNOR2X4TS U2510 ( .A(n791), .B(n2796), .Y(n1305) );
ADDFHX4TS U2511 ( .A(n2393), .B(n2392), .CI(n2391), .CO(n2424), .S(n2362) );
XNOR2X4TS U2512 ( .A(n433), .B(n868), .Y(n1547) );
ADDFHX4TS U2513 ( .A(n1076), .B(n1075), .CI(n1074), .CO(n1077), .S(n1051) );
ADDFHX4TS U2514 ( .A(n2360), .B(n2359), .CI(n2358), .CO(mult_x_19_n896), .S(
mult_x_19_n897) );
XNOR2X4TS U2515 ( .A(n1090), .B(n2221), .Y(n1054) );
XNOR2X4TS U2516 ( .A(n2237), .B(n761), .Y(n2308) );
ADDFHX4TS U2517 ( .A(n3030), .B(n3031), .CI(n3032), .CO(n1187), .S(n1186) );
XNOR2X4TS U2518 ( .A(n2218), .B(n686), .Y(n2328) );
INVX16TS U2519 ( .A(n2897), .Y(n2218) );
ADDFHX4TS U2520 ( .A(n2274), .B(n2273), .CI(n2272), .CO(n2279), .S(n2188) );
OAI22X2TS U2521 ( .A0(n784), .A1(n2884), .B0(n800), .B1(n1318), .Y(n2369) );
NAND2X8TS U2522 ( .A(mult_x_19_n1797), .B(mult_x_19_n58), .Y(n2482) );
NAND2X4TS U2523 ( .A(n2870), .B(n2869), .Y(n2871) );
XNOR2X4TS U2524 ( .A(n1090), .B(n399), .Y(n1019) );
ADDFHX2TS U2525 ( .A(n863), .B(n824), .CI(n2562), .CO(n2569), .S(n2560) );
XNOR2X4TS U2526 ( .A(n883), .B(n863), .Y(n2472) );
XNOR2X4TS U2527 ( .A(n433), .B(n863), .Y(n1540) );
XNOR2X4TS U2528 ( .A(n500), .B(n732), .Y(n1501) );
XNOR2X4TS U2529 ( .A(n2902), .B(n732), .Y(n1302) );
XNOR2X4TS U2530 ( .A(mult_x_19_n1697), .B(n863), .Y(n2054) );
XNOR2X4TS U2531 ( .A(n1814), .B(n2794), .Y(n1352) );
XOR2X4TS U2532 ( .A(n2890), .B(n3066), .Y(n1819) );
XNOR2X4TS U2533 ( .A(n2890), .B(n398), .Y(n2222) );
XNOR2X4TS U2534 ( .A(n780), .B(n691), .Y(n2333) );
XNOR2X4TS U2535 ( .A(n780), .B(n839), .Y(n2332) );
XNOR2X4TS U2536 ( .A(n755), .B(n2890), .Y(n1818) );
XOR2X4TS U2537 ( .A(n2890), .B(n669), .Y(n1545) );
XNOR2X4TS U2538 ( .A(n2890), .B(n2906), .Y(n1584) );
ADDFHX4TS U2539 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n1904), .S(n2535) );
XNOR2X4TS U2540 ( .A(n644), .B(n2796), .Y(n1681) );
ADDFHX4TS U2541 ( .A(n2399), .B(n2398), .CI(n2397), .CO(mult_x_19_n661), .S(
mult_x_19_n662) );
ADDFHX4TS U2542 ( .A(n1960), .B(n1959), .CI(n1958), .CO(n1956), .S(n1971) );
OAI21X4TS U2543 ( .A0(n1179), .A1(n1178), .B0(n1177), .Y(n1988) );
NAND2X4TS U2544 ( .A(n1149), .B(n1148), .Y(n2434) );
ADDFHX4TS U2545 ( .A(n1170), .B(n1169), .CI(n1168), .CO(n1171), .S(n1149) );
XNOR2X4TS U2546 ( .A(n2947), .B(n2796), .Y(n1029) );
BUFX20TS U2547 ( .A(n736), .Y(n2796) );
ADDFHX4TS U2548 ( .A(n3020), .B(n3021), .CI(n3022), .CO(n1009), .S(n1008) );
XNOR2X4TS U2549 ( .A(n1761), .B(n762), .Y(n1116) );
BUFX20TS U2550 ( .A(n1293), .Y(n1796) );
XNOR2X4TS U2551 ( .A(n705), .B(n2319), .Y(n1675) );
ADDFHX4TS U2552 ( .A(n1073), .B(n1072), .CI(n1071), .CO(n1079), .S(n1078) );
OR2X8TS U2553 ( .A(n1486), .B(n998), .Y(n2611) );
ADDFHX4TS U2554 ( .A(n1974), .B(n1973), .CI(n1972), .CO(n2190), .S(n1980) );
ADDFHX2TS U2555 ( .A(n601), .B(n867), .CI(n1557), .CO(n2552), .S(n1560) );
XNOR2X4TS U2556 ( .A(n2218), .B(n2908), .Y(n1744) );
XNOR2X4TS U2557 ( .A(mult_x_19_n1697), .B(n867), .Y(n1712) );
XNOR2X4TS U2558 ( .A(n753), .B(n867), .Y(n2070) );
XNOR2X4TS U2559 ( .A(n878), .B(n668), .Y(n1821) );
ADDFHX4TS U2560 ( .A(n2432), .B(n2431), .CI(n2430), .CO(mult_x_19_n958), .S(
mult_x_19_n959) );
XNOR2X4TS U2561 ( .A(n878), .B(n2796), .Y(n1103) );
XNOR2X4TS U2562 ( .A(n1884), .B(n2793), .Y(n1359) );
INVX16TS U2563 ( .A(n2887), .Y(n1884) );
XNOR2X4TS U2564 ( .A(n1814), .B(n736), .Y(n1316) );
ADDFHX4TS U2565 ( .A(n1962), .B(n1963), .CI(n1961), .CO(n1970), .S(n1964) );
XNOR2X4TS U2566 ( .A(n433), .B(n824), .Y(n1546) );
CMPR22X2TS U2567 ( .A(n1126), .B(n1125), .CO(n1147), .S(n1142) );
XNOR2X4TS U2568 ( .A(n464), .B(n2313), .Y(n1309) );
XNOR2X4TS U2569 ( .A(n2239), .B(n2238), .Y(n2306) );
MXI2X4TS U2570 ( .A(n3136), .B(n3103), .S0(FSM_selector_A), .Y(n1442) );
MXI2X4TS U2571 ( .A(n3117), .B(n3104), .S0(FSM_selector_A), .Y(n1257) );
MXI2X4TS U2572 ( .A(n3115), .B(n3105), .S0(n434), .Y(n1265) );
INVX2TS U2573 ( .A(n1398), .Y(n1395) );
ADDFHX4TS U2574 ( .A(n1138), .B(n1137), .CI(n1136), .CO(n1148), .S(n2191) );
OAI2BB2X2TS U2575 ( .B0(n714), .B1(n868), .A0N(n2946), .A1N(n3095), .Y(n1603) );
ADDFHX4TS U2576 ( .A(n2067), .B(n2066), .CI(n2065), .CO(n2032), .S(n2106) );
XNOR2X4TS U2577 ( .A(n1427), .B(n1426), .Y(n1432) );
XNOR2X4TS U2578 ( .A(n878), .B(n2794), .Y(n1109) );
BUFX20TS U2579 ( .A(n648), .Y(n2794) );
XNOR2X4TS U2580 ( .A(n2898), .B(n2793), .Y(n1119) );
CMPR22X2TS U2581 ( .A(n1715), .B(n1716), .CO(n1723), .S(n1728) );
OAI22X2TS U2582 ( .A0(n767), .A1(n1150), .B0(n1694), .B1(n2034), .Y(n1716)
);
ADDFHX4TS U2583 ( .A(n3009), .B(n3010), .CI(n3011), .CO(n1185), .S(n1184) );
OR2X8TS U2584 ( .A(n1211), .B(n2974), .Y(n1848) );
AND2X4TS U2585 ( .A(n1928), .B(n426), .Y(n1000) );
XOR2X1TS U2586 ( .A(mult_x_19_n7), .B(n348), .Y(n1001) );
BUFX3TS U2587 ( .A(n817), .Y(n2575) );
INVX2TS U2588 ( .A(n2631), .Y(n2615) );
NAND2X4TS U2589 ( .A(n1406), .B(n2788), .Y(n1410) );
INVX2TS U2590 ( .A(n2266), .Y(n2268) );
XOR2X2TS U2591 ( .A(n2737), .B(n2736), .Y(n2738) );
INVX2TS U2592 ( .A(n2566), .Y(mult_x_19_n135) );
INVX2TS U2593 ( .A(mult_x_19_n43), .Y(n2926) );
NAND2X4TS U2594 ( .A(n1374), .B(n2687), .Y(n235) );
NOR2X8TS U2595 ( .A(n3217), .B(n3216), .Y(n1938) );
NOR2X8TS U2596 ( .A(n2584), .B(FS_Module_state_reg[1]), .Y(n2213) );
MX2X4TS U2597 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n2263), .Y(n348) );
AOI21X4TS U2604 ( .A0(n3058), .A1(n3059), .B0(n3060), .Y(n2197) );
CLKBUFX2TS U2605 ( .A(n1178), .Y(n2109) );
CLKINVX1TS U2606 ( .A(n1179), .Y(n1010) );
NAND2X1TS U2607 ( .A(n1010), .B(n1177), .Y(n1011) );
XNOR2X4TS U2608 ( .A(n1012), .B(n1011), .Y(n1013) );
XOR2X4TS U2609 ( .A(n617), .B(n670), .Y(n1015) );
NOR2BX1TS U2610 ( .AN(n789), .B(n1014), .Y(n1043) );
XNOR2X1TS U2611 ( .A(n2948), .B(n870), .Y(n1030) );
OAI21X4TS U2612 ( .A0(n2773), .A1(n2871), .B0(n2774), .Y(n2780) );
NAND2BX1TS U2613 ( .AN(n2904), .B(n2052), .Y(n1037) );
ADDFHX4TS U2614 ( .A(n1096), .B(n1095), .CI(n1094), .CO(n1097), .S(n1080) );
OAI21X4TS U2615 ( .A0(n1978), .A1(n603), .B0(n1981), .Y(mult_x_19_n480) );
BUFX8TS U2616 ( .A(n1817), .Y(n2485) );
ADDFHX4TS U2617 ( .A(n1142), .B(n1143), .CI(n1144), .CO(n1973), .S(n1975) );
BUFX20TS U2618 ( .A(n2915), .Y(n1817) );
INVX2TS U2619 ( .A(n2436), .Y(n1173) );
AOI21X4TS U2620 ( .A0(mult_x_19_n466), .A1(n2437), .B0(n1173), .Y(
mult_x_19_n459) );
NOR2X8TS U2621 ( .A(n2258), .B(n2697), .Y(n1195) );
ADDFHX4TS U2622 ( .A(n3006), .B(n3007), .CI(n3008), .CO(n1183), .S(n1182) );
NAND2X1TS U2623 ( .A(n2641), .B(n2646), .Y(n1192) );
INVX2TS U2624 ( .A(n2645), .Y(n1190) );
AOI21X1TS U2625 ( .A0(n2642), .A1(n2646), .B0(n1190), .Y(n1191) );
INVX2TS U2626 ( .A(n1199), .Y(n1193) );
NAND2X4TS U2627 ( .A(n2641), .B(n1201), .Y(n1619) );
ADDFHX4TS U2628 ( .A(n3000), .B(n3001), .CI(n3002), .CO(n1206), .S(n1205) );
ADDFHX4TS U2629 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n1211), .S(n1207) );
OR2X8TS U2630 ( .A(n1219), .B(n1619), .Y(n1917) );
NAND2X4TS U2631 ( .A(n570), .B(n584), .Y(n2247) );
NOR2X2TS U2632 ( .A(n2247), .B(n3025), .Y(n1365) );
AOI21X4TS U2633 ( .A0(n2642), .A1(n1201), .B0(n1200), .Y(n1620) );
AOI21X4TS U2634 ( .A0(n2252), .A1(n1365), .B0(n1367), .Y(n1220) );
MXI2X4TS U2635 ( .A(n2638), .B(Add_result[23]), .S0(n793), .Y(n1222) );
INVX2TS U2636 ( .A(n1268), .Y(n1246) );
NAND2X2TS U2637 ( .A(n1448), .B(n1251), .Y(n1253) );
MXI2X4TS U2638 ( .A(n997), .B(n3114), .S0(FSM_selector_A), .Y(n1255) );
OAI21X2TS U2639 ( .A0(Op_MY[23]), .A1(FSM_selector_B_1_), .B0(n1228), .Y(
n1229) );
NAND2X2TS U2640 ( .A(n1230), .B(n1255), .Y(n1231) );
OAI21X4TS U2641 ( .A0(n1232), .A1(n1414), .B0(n1231), .Y(n1420) );
NAND2X8TS U2642 ( .A(n1235), .B(n1233), .Y(n1258) );
AOI21X4TS U2643 ( .A0(n1420), .A1(n1241), .B0(n1240), .Y(n1375) );
AOI21X4TS U2644 ( .A0(n1251), .A1(n1450), .B0(n1250), .Y(n1252) );
OAI21X4TS U2645 ( .A0(n1253), .A1(n1375), .B0(n1252), .Y(n1474) );
NOR2X8TS U2646 ( .A(n1380), .B(n1387), .Y(n1461) );
NOR2X2TS U2647 ( .A(n1465), .B(n1456), .Y(n1271) );
NAND2X2TS U2648 ( .A(n1461), .B(n1271), .Y(n1273) );
OAI21X4TS U2649 ( .A0(n1411), .A1(n1416), .B0(n1412), .Y(n1428) );
OAI21X4TS U2650 ( .A0(n1423), .A1(n1434), .B0(n1424), .Y(n1261) );
AOI21X4TS U2651 ( .A0(n1262), .A1(n1428), .B0(n1261), .Y(n1386) );
OAI21X4TS U2652 ( .A0(n1380), .A1(n1403), .B0(n1381), .Y(n1463) );
OAI21X1TS U2653 ( .A0(n1456), .A1(n1464), .B0(n1457), .Y(n1270) );
AOI21X2TS U2654 ( .A0(n1271), .A1(n1463), .B0(n1270), .Y(n1272) );
OAI21X4TS U2655 ( .A0(n1273), .A1(n1386), .B0(n1272), .Y(n1477) );
OAI21X4TS U2656 ( .A0(n1278), .A1(n2873), .B0(n1277), .Y(n225) );
ADDFHX4TS U2657 ( .A(n1312), .B(n1311), .CI(n1310), .CO(n1329), .S(n2290) );
ADDFHX2TS U2658 ( .A(n1340), .B(n1339), .CI(n1338), .CO(n1347), .S(n1350) );
NOR2X2TS U2659 ( .A(n2584), .B(n3139), .Y(n1363) );
NAND2X4TS U2660 ( .A(n1365), .B(n581), .Y(n1366) );
OAI21X4TS U2661 ( .A0(n766), .A1(n1371), .B0(n1370), .Y(n1372) );
XOR2X4TS U2662 ( .A(n1384), .B(n1383), .Y(n1385) );
NAND2X6TS U2663 ( .A(n1385), .B(n2788), .Y(n1393) );
AOI21X4TS U2664 ( .A0(n1469), .A1(n1404), .B0(n1388), .Y(n1390) );
XOR2X4TS U2665 ( .A(n1390), .B(n1389), .Y(n1391) );
AOI21X4TS U2666 ( .A0(n1455), .A1(n1448), .B0(n1450), .Y(n1396) );
XOR2X4TS U2667 ( .A(n1396), .B(n1395), .Y(n1397) );
XOR2X4TS U2668 ( .A(n1399), .B(n1398), .Y(n1400) );
INVX2TS U2669 ( .A(n1407), .Y(n1405) );
XNOR2X4TS U2670 ( .A(n1455), .B(n1405), .Y(n1406) );
NAND2X4TS U2671 ( .A(n1413), .B(n1412), .Y(n1417) );
XOR2X1TS U2672 ( .A(n1417), .B(n1416), .Y(n1418) );
NAND2X4TS U2673 ( .A(n1425), .B(n1424), .Y(n1429) );
OR2X4TS U2674 ( .A(n2786), .B(n2602), .Y(n1446) );
XOR2X1TS U2675 ( .A(n1443), .B(n1442), .Y(n2868) );
NOR2X4TS U2676 ( .A(n1446), .B(n1445), .Y(n1447) );
XOR2X4TS U2677 ( .A(n1460), .B(n1459), .Y(n1473) );
XOR2X4TS U2678 ( .A(n1471), .B(n1470), .Y(n1472) );
MXI2X4TS U2679 ( .A(n1473), .B(n1472), .S0(n427), .Y(n1986) );
XNOR2X4TS U2680 ( .A(n1477), .B(n1476), .Y(n1478) );
AOI22X1TS U2681 ( .A0(n2792), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n3273), .Y(n1493) );
XNOR2X4TS U2682 ( .A(n1489), .B(n2916), .Y(n1490) );
OAI2BB1X4TS U2683 ( .A0N(n587), .A1N(n1490), .B0(n3269), .Y(n2639) );
INVX4TS U2684 ( .A(n2651), .Y(n1940) );
OAI22X1TS U2685 ( .A0(n677), .A1(n2472), .B0(n1506), .B1(n799), .Y(n2465) );
OAI22X1TS U2686 ( .A0(n715), .A1(n879), .B0(n695), .B1(n868), .Y(n1598) );
AOI21X4TS U2687 ( .A0(n615), .A1(n2284), .B0(n1523), .Y(n1527) );
INVX2TS U2688 ( .A(n1941), .Y(n1534) );
OAI2BB1X4TS U2689 ( .A0N(n587), .A1N(n1537), .B0(n3262), .Y(n2675) );
CLKINVX1TS U2690 ( .A(n769), .Y(n1539) );
OAI2BB2X2TS U2691 ( .B0(n842), .B1(n780), .A0N(n1539), .A1N(n1538), .Y(n1567) );
OAI22X1TS U2692 ( .A0(n677), .A1(n1541), .B0(n2473), .B1(n799), .Y(n2542) );
ADDFHX4TS U2693 ( .A(n1578), .B(n1577), .CI(n1576), .CO(n1571), .S(n2398) );
CMPR32X2TS U2694 ( .A(n1595), .B(n1596), .C(n1594), .CO(n2531), .S(n2528) );
CMPR32X2TS U2695 ( .A(n650), .B(n881), .C(n1598), .CO(n1604), .S(n1601) );
AO21X4TS U2696 ( .A0(n1618), .A1(n2287), .B0(n1617), .Y(n3094) );
OAI2BB1X4TS U2697 ( .A0N(n1621), .A1N(n2661), .B0(n1620), .Y(n1623) );
NAND2X2TS U2698 ( .A(n1627), .B(n2664), .Y(n1622) );
OAI2BB1X4TS U2699 ( .A0N(n3256), .A1N(n1624), .B0(n3255), .Y(n2677) );
INVX2TS U2700 ( .A(Add_result[10]), .Y(n1625) );
INVX2TS U2701 ( .A(n2664), .Y(n1626) );
OAI2BB1X4TS U2702 ( .A0N(n585), .A1N(n1631), .B0(n3272), .Y(n2683) );
OAI21X4TS U2703 ( .A0(n2112), .A1(n1651), .B0(n1633), .Y(n1636) );
NAND2X1TS U2704 ( .A(n1660), .B(n1658), .Y(n1635) );
XNOR2X4TS U2705 ( .A(n1636), .B(n1635), .Y(n1637) );
NAND2X1TS U2706 ( .A(n1987), .B(n1992), .Y(n1641) );
INVX2TS U2707 ( .A(n1991), .Y(n1639) );
NAND2X1TS U2708 ( .A(n521), .B(n1643), .Y(n1644) );
XNOR2X4TS U2709 ( .A(n1645), .B(n1644), .Y(n1646) );
AOI22X1TS U2710 ( .A0(n2792), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n777), .Y(n1650) );
AOI2BB2X2TS U2711 ( .B0(n2700), .B1(n264), .A0N(n805), .A1N(n3147), .Y(n1649) );
NAND2X2TS U2712 ( .A(n2681), .B(n263), .Y(n1648) );
NAND3X2TS U2713 ( .A(n1650), .B(n1649), .C(n1648), .Y(n204) );
NAND2X1TS U2714 ( .A(n426), .B(n1921), .Y(n1653) );
XNOR2X4TS U2715 ( .A(n1656), .B(n1655), .Y(n1657) );
NAND2X1TS U2716 ( .A(n426), .B(n1660), .Y(n1662) );
NAND2X1TS U2717 ( .A(n1665), .B(n1664), .Y(n1666) );
AOI22X1TS U2718 ( .A0(n2828), .A1(Add_result[5]), .B0(n640), .B1(n777), .Y(
n1673) );
INVX2TS U2719 ( .A(Add_result[4]), .Y(n1670) );
AOI2BB2X4TS U2720 ( .B0(n2784), .B1(n266), .A0N(n807), .A1N(n1670), .Y(n1672) );
NAND2BX1TS U2721 ( .AN(n612), .B(n604), .Y(n1683) );
ADDFHX4TS U2722 ( .A(n1699), .B(n1698), .CI(n1697), .CO(n1749), .S(n1730) );
INVX2TS U2723 ( .A(n430), .Y(n1735) );
NAND2X1TS U2724 ( .A(n1735), .B(n1734), .Y(n1736) );
XNOR2X4TS U2725 ( .A(n1737), .B(n1736), .Y(n1738) );
OAI2BB1X4TS U2726 ( .A0N(n3260), .A1N(n1738), .B0(n3259), .Y(n2673) );
XNOR2X1TS U2727 ( .A(n753), .B(n626), .Y(n1745) );
NAND2BX1TS U2728 ( .AN(n612), .B(n1884), .Y(n1746) );
ADDFHX4TS U2729 ( .A(n1749), .B(n1748), .CI(n1747), .CO(n1984), .S(n1766) );
ADDFHX4TS U2730 ( .A(n1768), .B(n1767), .CI(n1766), .CO(n1769), .S(n1957) );
AOI21X4TS U2731 ( .A0(n632), .A1(n634), .B0(n660), .Y(mult_x_19_n424) );
ADDFHX4TS U2732 ( .A(n1843), .B(n1842), .CI(n1841), .CO(mult_x_19_n725), .S(
mult_x_19_n726) );
NAND2X1TS U2733 ( .A(n2661), .B(n1845), .Y(n1847) );
NAND2BX2TS U2734 ( .AN(n1939), .B(n1942), .Y(n1850) );
XNOR2X4TS U2735 ( .A(n1851), .B(n1850), .Y(n1852) );
OAI2BB1X4TS U2736 ( .A0N(n587), .A1N(n1852), .B0(n3263), .Y(n2682) );
NAND2X1TS U2737 ( .A(n1857), .B(n1856), .Y(n1858) );
ADDFHX4TS U2738 ( .A(n1912), .B(n1911), .CI(n1910), .CO(n1959), .S(n1961) );
OAI21X4TS U2739 ( .A0(n765), .A1(n1917), .B0(n1916), .Y(n1919) );
XNOR2X4TS U2740 ( .A(n1919), .B(n1918), .Y(n1920) );
OAI2BB1X4TS U2741 ( .A0N(n587), .A1N(n1920), .B0(n3270), .Y(n2630) );
AOI2BB2X2TS U2742 ( .B0(n2784), .B1(n2630), .A0N(n806), .A1N(n3125), .Y(
n3303) );
MXI2X4TS U2743 ( .A(n423), .B(n2588), .S0(n2785), .Y(n230) );
OAI21X2TS U2744 ( .A0(n1926), .A1(n1925), .B0(n1924), .Y(n1927) );
INVX2TS U2745 ( .A(n1932), .Y(n1934) );
NAND2X1TS U2746 ( .A(n1934), .B(n1933), .Y(n1935) );
XNOR2X4TS U2747 ( .A(n1936), .B(n1935), .Y(n1937) );
MX2X6TS U2748 ( .A(n1937), .B(n3244), .S0(n589), .Y(n267) );
NAND2X1TS U2749 ( .A(n2661), .B(n1950), .Y(n1952) );
NAND2X1TS U2750 ( .A(n3043), .B(n3044), .Y(n1953) );
XNOR2X4TS U2751 ( .A(n1954), .B(n1953), .Y(n1955) );
OAI2BB1X4TS U2752 ( .A0N(n587), .A1N(n1955), .B0(n3261), .Y(n2674) );
XOR2X4TS U2753 ( .A(n603), .B(n1967), .Y(Sgf_operation_Result[9]) );
MXI2X4TS U2754 ( .A(n1969), .B(n3107), .S0(n2785), .Y(n228) );
ADDFHX4TS U2755 ( .A(n1985), .B(n1984), .CI(n1983), .CO(mult_x_19_n1010),
.S(n1770) );
MXI2X4TS U2756 ( .A(n1986), .B(n3108), .S0(n2785), .Y(n227) );
OAI21X4TS U2757 ( .A0(n2112), .A1(n1990), .B0(n1989), .Y(n1994) );
NAND2X1TS U2758 ( .A(n1992), .B(n1991), .Y(n1993) );
AOI22X1TS U2759 ( .A0(n2828), .A1(Add_result[2]), .B0(n664), .B1(n777), .Y(
n1998) );
NAND2X1TS U2760 ( .A(n2701), .B(n262), .Y(n1996) );
XOR2X1TS U2761 ( .A(n2001), .B(n2000), .Y(n2002) );
NAND2X1TS U2762 ( .A(n2003), .B(n3039), .Y(n2004) );
XNOR2X1TS U2763 ( .A(n2121), .B(n2004), .Y(n2005) );
AOI21X1TS U2764 ( .A0(n3093), .A1(n2980), .B0(n2981), .Y(n2007) );
XNOR2X1TS U2765 ( .A(n2008), .B(n2956), .Y(n2009) );
AOI2BB2X2TS U2766 ( .B0(n2700), .B1(n2678), .A0N(n807), .A1N(n3129), .Y(
n3319) );
ADDFHX4TS U2767 ( .A(n2033), .B(n2032), .CI(n2031), .CO(mult_x_19_n743), .S(
mult_x_19_n744) );
OAI22X1TS U2768 ( .A0(n2041), .A1(n2040), .B0(n2039), .B1(n2479), .Y(n2096)
);
XOR2X4TS U2769 ( .A(n2112), .B(n2111), .Y(n2113) );
NOR2X1TS U2770 ( .A(n428), .B(n2117), .Y(n2120) );
NAND2X1TS U2771 ( .A(n2124), .B(n2123), .Y(n2125) );
XOR2X4TS U2772 ( .A(n2126), .B(n2125), .Y(n2127) );
NOR2X1TS U2773 ( .A(n551), .B(n787), .Y(n2562) );
CMPR32X2TS U2774 ( .A(n3095), .B(n2132), .C(n2131), .CO(n2559), .S(n2129) );
MXI2X4TS U2775 ( .A(n2193), .B(n3105), .S0(n2785), .Y(n229) );
XOR2X1TS U2776 ( .A(n2198), .B(n2954), .Y(n2194) );
XNOR2X2TS U2777 ( .A(n2199), .B(n2930), .Y(n2200) );
AOI21X1TS U2778 ( .A0(n582), .A1(n3014), .B0(n3015), .Y(n2201) );
XOR2X1TS U2779 ( .A(n2201), .B(n2959), .Y(n2202) );
CLKMX2X2TS U2780 ( .A(n2204), .B(n3231), .S0(n588), .Y(n250) );
CLKMX2X2TS U2781 ( .A(n2205), .B(n3229), .S0(n588), .Y(n249) );
CLKMX2X2TS U2782 ( .A(n3225), .B(n3224), .S0(n588), .Y(n247) );
XNOR2X1TS U2783 ( .A(n3072), .B(n3073), .Y(n2206) );
CLKMX2X2TS U2784 ( .A(n2206), .B(n3226), .S0(n588), .Y(n248) );
NOR4X4TS U2785 ( .A(n257), .B(n258), .C(n256), .D(n255), .Y(n2208) );
NOR4X1TS U2786 ( .A(n250), .B(n249), .C(n247), .D(n248), .Y(n2207) );
NAND2X1TS U2787 ( .A(n2210), .B(n2209), .Y(n2211) );
XNOR2X1TS U2788 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n2830) );
NOR2X4TS U2789 ( .A(n3139), .B(FS_Module_state_reg[2]), .Y(n2586) );
AOI22X1TS U2790 ( .A0(n2213), .A1(n2578), .B0(n2586), .B1(n2584), .Y(n2214)
);
ADDFHX4TS U2791 ( .A(n2231), .B(n2229), .CI(n2230), .CO(n2361), .S(n1983) );
INVX2TS U2792 ( .A(n2247), .Y(n2251) );
INVX2TS U2793 ( .A(n2249), .Y(n2250) );
OAI2BB1X4TS U2794 ( .A0N(n585), .A1N(n2256), .B0(n3251), .Y(n2629) );
AOI2BB2X2TS U2795 ( .B0(n2784), .B1(n2629), .A0N(n806), .A1N(n3134), .Y(
n3294) );
MX2X4TS U2796 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n2263), .Y(n354) );
XNOR2X1TS U2797 ( .A(n353), .B(n354), .Y(n2927) );
XNOR2X1TS U2798 ( .A(n355), .B(n356), .Y(n2934) );
MX2X6TS U2799 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n2791), .Y(n345) );
XNOR2X1TS U2800 ( .A(n345), .B(n346), .Y(n2935) );
XNOR2X1TS U2801 ( .A(n349), .B(n350), .Y(n2933) );
INVX2TS U2802 ( .A(n357), .Y(n2939) );
XNOR2X1TS U2803 ( .A(n357), .B(mult_x_19_n689), .Y(n3067) );
XOR2X1TS U2804 ( .A(n2931), .B(mult_x_19_n579), .Y(n2945) );
XNOR2X1TS U2805 ( .A(n357), .B(n358), .Y(n2938) );
MX2X4TS U2806 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n2791), .Y(
mult_x_19_n1775) );
XNOR2X1TS U2807 ( .A(n345), .B(mult_x_19_n1775), .Y(n3049) );
XNOR2X1TS U2808 ( .A(n345), .B(mult_x_19_n1773), .Y(n2957) );
XNOR2X1TS U2809 ( .A(n345), .B(mult_x_19_n1777), .Y(n3012) );
MX2X4TS U2810 ( .A(Data_MX[20]), .B(n410), .S0(n2568), .Y(n364) );
XNOR2X1TS U2811 ( .A(n363), .B(n364), .Y(n2953) );
MX2X6TS U2812 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n2263), .Y(mult_x_19_n19)
);
XOR2X1TS U2813 ( .A(n363), .B(n362), .Y(n2960) );
XNOR2X1TS U2814 ( .A(mult_x_19_n19), .B(mult_x_19_n723), .Y(n3053) );
XNOR2X1TS U2815 ( .A(mult_x_19_n19), .B(mult_x_19_n1777), .Y(n3052) );
MX2X6TS U2816 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n2568), .Y(mult_x_19_n43) );
XNOR2X1TS U2817 ( .A(mult_x_19_n43), .B(mult_x_19_n723), .Y(n3054) );
BUFX3TS U2818 ( .A(n3158), .Y(n2576) );
CLKBUFX3TS U2819 ( .A(n3080), .Y(n3159) );
OAI22X1TS U2820 ( .A0(n760), .A1(n2469), .B0(n2468), .B1(n604), .Y(n2550) );
CMPR32X2TS U2821 ( .A(n2558), .B(n2557), .C(n2556), .CO(mult_x_19_n637), .S(
mult_x_19_n638) );
CMPR32X2TS U2822 ( .A(n2561), .B(n2560), .C(n2559), .CO(n2564), .S(n2539) );
XNOR2X1TS U2823 ( .A(n357), .B(n2565), .Y(n3069) );
XNOR2X1TS U2824 ( .A(n355), .B(mult_x_19_n689), .Y(n3045) );
XNOR2X1TS U2825 ( .A(n363), .B(mult_x_19_n1791), .Y(n3070) );
INVX2TS U2826 ( .A(mult_x_19_n1777), .Y(n2567) );
XNOR2X1TS U2827 ( .A(n353), .B(mult_x_19_n633), .Y(n3063) );
XNOR2X1TS U2828 ( .A(mult_x_19_n19), .B(mult_x_19_n1775), .Y(n2942) );
XNOR2X1TS U2829 ( .A(mult_x_19_n19), .B(mult_x_19_n593), .Y(n3047) );
XNOR2X1TS U2830 ( .A(mult_x_19_n19), .B(mult_x_19_n1773), .Y(n3064) );
MX2X6TS U2831 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n2568), .Y(mult_x_19_n49) );
XNOR2X1TS U2832 ( .A(mult_x_19_n49), .B(n362), .Y(n2961) );
MX2X4TS U2833 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n2568), .Y(n360) );
XNOR2X1TS U2834 ( .A(mult_x_19_n43), .B(n360), .Y(n2966) );
XNOR2X1TS U2835 ( .A(mult_x_19_n43), .B(mult_x_19_n689), .Y(n2944) );
XNOR2X1TS U2836 ( .A(mult_x_19_n49), .B(mult_x_19_n633), .Y(n3071) );
XNOR2X1TS U2837 ( .A(mult_x_19_n49), .B(mult_x_19_n593), .Y(n2928) );
CMPR32X2TS U2838 ( .A(n669), .B(n435), .C(n2569), .CO(n2572), .S(n2563) );
AND2X2TS U2839 ( .A(n551), .B(n3098), .Y(n2570) );
XNOR2X2TS U2840 ( .A(n2570), .B(n787), .Y(n2571) );
NAND2X1TS U2841 ( .A(n2572), .B(n2571), .Y(n2573) );
INVX2TS U2842 ( .A(n366), .Y(n3062) );
AOI22X1TS U2843 ( .A0(n1364), .A1(n3139), .B0(n2586), .B1(n1938), .Y(n2580)
);
NAND2X1TS U2844 ( .A(n2582), .B(n2580), .Y(n377) );
XNOR2X1TS U2845 ( .A(n664), .B(Sgf_normalized_result[0]), .Y(n2583) );
MXI2X4TS U2846 ( .A(n3177), .B(n3176), .S0(n564), .Y(underflow_flag) );
INVX12TS U2847 ( .A(n2835), .Y(n2855) );
BUFX8TS U2848 ( .A(n2839), .Y(n2857) );
AOI2BB2X1TS U2849 ( .B0(n2857), .B1(n2588), .A0N(n2834), .A1N(
final_result_ieee[27]), .Y(n173) );
XNOR2X1TS U2850 ( .A(n2593), .B(Sgf_normalized_result[2]), .Y(n2589) );
CLKMX2X2TS U2851 ( .A(n2589), .B(n813), .S0(n2723), .Y(n307) );
XOR2X1TS U2852 ( .A(n2858), .B(n640), .Y(n2592) );
CLKMX2X2TS U2853 ( .A(n2592), .B(Add_result[4]), .S0(n2723), .Y(n305) );
XOR2X1TS U2854 ( .A(n2594), .B(n3138), .Y(n2595) );
CLKMX2X2TS U2855 ( .A(n2595), .B(Add_result[3]), .S0(n2771), .Y(n306) );
INVX2TS U2856 ( .A(n2851), .Y(n2859) );
XNOR2X1TS U2857 ( .A(n2596), .B(n3148), .Y(n2597) );
XOR2X4TS U2858 ( .A(n2606), .B(n2600), .Y(n2601) );
MXI2X1TS U2859 ( .A(n2602), .B(n3113), .S0(n2785), .Y(n231) );
MXI2X1TS U2860 ( .A(n2603), .B(n3104), .S0(n2785), .Y(n232) );
AOI22X1TS U2861 ( .A0(n2827), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n777), .Y(n2614) );
INVX2TS U2862 ( .A(Add_result[0]), .Y(n2787) );
NAND2X4TS U2863 ( .A(n2679), .B(n261), .Y(n2612) );
NAND2X1TS U2864 ( .A(n2851), .B(Sgf_normalized_result[6]), .Y(n2617) );
NAND2X1TS U2865 ( .A(n2615), .B(Sgf_normalized_result[6]), .Y(n2616) );
INVX2TS U2866 ( .A(n2837), .Y(n2618) );
XNOR2X1TS U2867 ( .A(n2619), .B(n2618), .Y(n2620) );
OAI2BB1X4TS U2868 ( .A0N(n3248), .A1N(n2624), .B0(n3247), .Y(n2699) );
AOI22X1TS U2869 ( .A0(n2827), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n777), .Y(n2627) );
NAND2X1TS U2870 ( .A(n2681), .B(n264), .Y(n2625) );
INVX2TS U2871 ( .A(n2838), .Y(n2636) );
XNOR2X1TS U2872 ( .A(n2735), .B(n2636), .Y(n2637) );
CLKMX2X2TS U2873 ( .A(n2637), .B(Add_result[8]), .S0(n2757), .Y(n301) );
OAI21X4TS U2874 ( .A0(n765), .A1(n2644), .B0(n2643), .Y(n2648) );
XNOR2X4TS U2875 ( .A(n2648), .B(n2647), .Y(n2649) );
OAI2BB1X4TS U2876 ( .A0N(n3266), .A1N(n2649), .B0(n3265), .Y(n2676) );
NAND2X1TS U2877 ( .A(n2651), .B(n2661), .Y(n2653) );
AOI21X1TS U2878 ( .A0(n2667), .A1(n2651), .B0(n2650), .Y(n2652) );
NAND2X2TS U2879 ( .A(n2655), .B(n2654), .Y(n2656) );
XNOR2X4TS U2880 ( .A(n2657), .B(n2656), .Y(n2658) );
NOR2X1TS U2881 ( .A(n2660), .B(n2663), .Y(n2666) );
NAND2X1TS U2882 ( .A(n2661), .B(n2666), .Y(n2669) );
NAND2X2TS U2883 ( .A(n2671), .B(n2940), .Y(n2672) );
NAND2X1TS U2884 ( .A(n796), .B(n2682), .Y(n3309) );
NAND2X1TS U2885 ( .A(n2701), .B(n2682), .Y(n3310) );
NOR2X8TS U2886 ( .A(n2692), .B(n2691), .Y(n2768) );
NAND2X4TS U2887 ( .A(n2847), .B(n2846), .Y(n2763) );
NAND2X1TS U2888 ( .A(n2841), .B(n2844), .Y(n2693) );
NAND2X1TS U2889 ( .A(n2768), .B(n2696), .Y(n2698) );
MXI2X1TS U2890 ( .A(n2698), .B(n2697), .S0(n2723), .Y(n285) );
AOI22X1TS U2891 ( .A0(n2827), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n777), .Y(n2704) );
NAND2X1TS U2892 ( .A(n2735), .B(n2705), .Y(n2707) );
INVX2TS U2893 ( .A(n2842), .Y(n2706) );
NAND2X1TS U2894 ( .A(n2735), .B(n2838), .Y(n2710) );
INVX2TS U2895 ( .A(n2848), .Y(n2709) );
CLKMX2X2TS U2896 ( .A(n2711), .B(n809), .S0(n2757), .Y(n300) );
NAND2X1TS U2897 ( .A(n2735), .B(n2712), .Y(n2714) );
INVX2TS U2898 ( .A(n2850), .Y(n2713) );
NAND2X1TS U2899 ( .A(n2717), .B(n2842), .Y(n2718) );
NAND2X1TS U2900 ( .A(n2735), .B(n2720), .Y(n2722) );
INVX2TS U2901 ( .A(n2840), .Y(n2721) );
BUFX8TS U2902 ( .A(n2723), .Y(n2771) );
INVX2TS U2903 ( .A(n2728), .Y(n2725) );
XOR2X1TS U2904 ( .A(n2726), .B(n2729), .Y(n2727) );
CLKMX2X2TS U2905 ( .A(n2727), .B(Add_result[10]), .S0(n2757), .Y(n299) );
NAND2X1TS U2906 ( .A(n2735), .B(n2730), .Y(n2732) );
INVX2TS U2907 ( .A(n2845), .Y(n2731) );
NAND2X1TS U2908 ( .A(n2735), .B(n2734), .Y(n2737) );
INVX2TS U2909 ( .A(n2847), .Y(n2739) );
XNOR2X1TS U2910 ( .A(n2768), .B(n2739), .Y(n2740) );
NAND2X1TS U2911 ( .A(n2768), .B(n2742), .Y(n2744) );
INVX2TS U2912 ( .A(n2856), .Y(n2743) );
NAND2X1TS U2913 ( .A(n2847), .B(n2768), .Y(n2747) );
INVX2TS U2914 ( .A(n2846), .Y(n2746) );
NAND2X1TS U2915 ( .A(n2768), .B(n2749), .Y(n2751) );
INVX2TS U2916 ( .A(n2844), .Y(n2750) );
XOR2X1TS U2917 ( .A(n2751), .B(n2750), .Y(n2752) );
NOR2X4TS U2918 ( .A(n2759), .B(n2760), .Y(n2754) );
INVX2TS U2919 ( .A(n310), .Y(n2755) );
NAND2X1TS U2920 ( .A(n2768), .B(n748), .Y(n2761) );
INVX2TS U2921 ( .A(n2763), .Y(n2764) );
NAND2X1TS U2922 ( .A(n2768), .B(n2764), .Y(n2766) );
XOR2X1TS U2923 ( .A(n2766), .B(n2765), .Y(n2767) );
NAND2X1TS U2924 ( .A(n2769), .B(n2768), .Y(n2770) );
NAND2X1TS U2925 ( .A(n2775), .B(n2774), .Y(n2776) );
XOR2X1TS U2926 ( .A(n2776), .B(n2871), .Y(n2777) );
CLKMX2X2TS U2927 ( .A(n2777), .B(P_Sgf[2]), .S0(n424), .Y(n240) );
NAND2X1TS U2928 ( .A(n2778), .B(n2779), .Y(n2781) );
XNOR2X1TS U2929 ( .A(n2781), .B(n2780), .Y(n2782) );
MXI2X1TS U2930 ( .A(n2786), .B(n3114), .S0(n2785), .Y(n233) );
NAND2X1TS U2931 ( .A(n3356), .B(n3121), .Y(n376) );
MXI2X1TS U2932 ( .A(Sgf_normalized_result[0]), .B(n2787), .S0(n2723), .Y(
n309) );
NAND2X1TS U2933 ( .A(n2788), .B(zero_flag), .Y(n2789) );
NAND3X1TS U2934 ( .A(n2790), .B(n777), .C(n2789), .Y(n380) );
BUFX8TS U2935 ( .A(n2797), .Y(n2800) );
CLKMX2X3TS U2936 ( .A(Data_MY[22]), .B(n787), .S0(n2791), .Y(n334) );
AOI22X1TS U2937 ( .A0(n2792), .A1(Add_result[6]), .B0(n2851), .B1(n777), .Y(
n3351) );
AOI22X1TS U2938 ( .A0(n2792), .A1(n809), .B0(n2838), .B1(n2799), .Y(n3344)
);
AOI22X1TS U2939 ( .A0(n2792), .A1(n808), .B0(n2846), .B1(n3273), .Y(n3308)
);
AOI22X1TS U2940 ( .A0(n2828), .A1(Add_result[8]), .B0(n2837), .B1(n777), .Y(
n3348) );
NOR2BX1TS U2941 ( .AN(n789), .B(n556), .Y(n2803) );
NOR4X1TS U2942 ( .A(Op_MY[26]), .B(Op_MY[25]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n2808) );
NAND4BBX1TS U2943 ( .AN(Op_MY[10]), .BN(Op_MY[8]), .C(n624), .D(n647), .Y(
n2804) );
NOR4X1TS U2944 ( .A(Op_MY[29]), .B(n668), .C(Op_MY[0]), .D(Op_MY[30]), .Y(
n2806) );
NAND4X1TS U2945 ( .A(n2808), .B(n2807), .C(n2806), .D(n2805), .Y(n2825) );
AND4X2TS U2946 ( .A(n649), .B(n737), .C(n3109), .D(n2809), .Y(n2813) );
AND4X2TS U2947 ( .A(n3110), .B(n687), .C(n3149), .D(n622), .Y(n2812) );
NOR4X1TS U2948 ( .A(n600), .B(Op_MY[19]), .C(n673), .D(Op_MY[5]), .Y(n2811)
);
AND4X2TS U2949 ( .A(n3111), .B(n692), .C(n2801), .D(n3150), .Y(n2810) );
NAND4X1TS U2950 ( .A(n2813), .B(n2812), .C(n2811), .D(n2810), .Y(n2824) );
NOR4X1TS U2951 ( .A(Op_MX[20]), .B(Op_MX[8]), .C(Op_MX[10]), .D(Op_MX[16]),
.Y(n2817) );
NOR4X1TS U2952 ( .A(Op_MX[18]), .B(Op_MX[14]), .C(Op_MX[2]), .D(Op_MX[6]),
.Y(n2816) );
NOR4X1TS U2953 ( .A(Op_MX[11]), .B(Op_MX[19]), .C(Op_MX[7]), .D(Op_MX[17]),
.Y(n2815) );
NOR4X1TS U2954 ( .A(Op_MX[22]), .B(Op_MX[12]), .C(Op_MX[0]), .D(Op_MX[5]),
.Y(n2814) );
NAND4X1TS U2955 ( .A(n2817), .B(n2816), .C(n2815), .D(n2814), .Y(n2823) );
NOR4X1TS U2956 ( .A(Op_MX[26]), .B(Op_MX[25]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n2821) );
NOR4X1TS U2957 ( .A(Op_MX[29]), .B(Op_MX[9]), .C(Op_MX[21]), .D(Op_MX[30]),
.Y(n2819) );
NAND4X1TS U2958 ( .A(n2821), .B(n2820), .C(n2819), .D(n2818), .Y(n2822) );
OAI22X1TS U2959 ( .A0(n2825), .A1(n2824), .B0(n2823), .B1(n2822), .Y(n2826)
);
AOI22X1TS U2960 ( .A0(n2827), .A1(n812), .B0(n2841), .B1(n3273), .Y(n3304)
);
AOI22X1TS U2961 ( .A0(n2827), .A1(Add_result[10]), .B0(n2848), .B1(n3273),
.Y(n3340) );
AOI22X1TS U2962 ( .A0(n2827), .A1(Add_result[22]), .B0(n2856), .B1(n3273),
.Y(n3295) );
AOI22X1TS U2963 ( .A0(n2827), .A1(Add_result[16]), .B0(n2840), .B1(n3273),
.Y(n3316) );
AOI22X1TS U2964 ( .A0(n2828), .A1(Add_result[14]), .B0(n2850), .B1(n3273),
.Y(n3324) );
AOI22X1TS U2965 ( .A0(n2828), .A1(n810), .B0(n2844), .B1(n3273), .Y(n3300)
);
AOI22X1TS U2966 ( .A0(n2828), .A1(Add_result[17]), .B0(n2847), .B1(n2799),
.Y(n3312) );
AOI22X1TS U2967 ( .A0(n2828), .A1(Add_result[11]), .B0(n2836), .B1(n777),
.Y(n3336) );
AOI22X1TS U2968 ( .A0(n2828), .A1(Add_result[23]), .B0(n2854), .B1(n3273),
.Y(n3291) );
NAND2X1TS U2969 ( .A(n2830), .B(n3358), .Y(n2832) );
NAND2X1TS U2970 ( .A(n2832), .B(n2831), .Y(n2833) );
MXI2X1TS U2971 ( .A(n2833), .B(n3152), .S0(n2855), .Y(n168) );
AOI2BB2X1TS U2972 ( .B0(n2857), .B1(n3105), .A0N(n2834), .A1N(
final_result_ieee[28]), .Y(n172) );
AOI2BB2X1TS U2973 ( .B0(n2857), .B1(n3114), .A0N(n2834), .A1N(
final_result_ieee[24]), .Y(n176) );
AOI2BB2X1TS U2974 ( .B0(n2857), .B1(n3108), .A0N(n2834), .A1N(
final_result_ieee[30]), .Y(n170) );
AOI2BB2X1TS U2975 ( .B0(n2857), .B1(n3113), .A0N(n2834), .A1N(
final_result_ieee[26]), .Y(n174) );
AOI2BB2X1TS U2976 ( .B0(n2857), .B1(n3107), .A0N(n2834), .A1N(
final_result_ieee[29]), .Y(n171) );
AOI2BB2X1TS U2977 ( .B0(n2857), .B1(n3104), .A0N(n2834), .A1N(
final_result_ieee[25]), .Y(n175) );
AOI2BB2X1TS U2978 ( .B0(n2857), .B1(n3103), .A0N(n2834), .A1N(
final_result_ieee[23]), .Y(n177) );
AO22X2TS U2979 ( .A0(n2857), .A1(n2856), .B0(final_result_ieee[21]), .B1(
n2855), .Y(n179) );
NAND2X1TS U2980 ( .A(n2858), .B(n641), .Y(n2860) );
XNOR2X1TS U2981 ( .A(n2860), .B(n2859), .Y(n2861) );
CLKMX2X2TS U2982 ( .A(n2861), .B(Add_result[5]), .S0(n2723), .Y(n304) );
MXI2X1TS U2983 ( .A(n2868), .B(n3103), .S0(n2785), .Y(n234) );
OR2X2TS U2984 ( .A(n2870), .B(n2869), .Y(n2872) );
AND2X2TS U2985 ( .A(n2872), .B(n2871), .Y(n2874) );
CLKMX2X2TS U2986 ( .A(n2874), .B(P_Sgf[1]), .S0(n2873), .Y(n3140) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_DW_1STAGE_syn.sdf");
endmodule
|
module hdrram (
input clk,
input [3:0] addr0,
input we,
input [31:0] data0_in,
input [3:0] addr1,
output [31:0] data1_out
);
wire [31:0] dummy;
RAM16X1D ram16x1_0 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[0]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[0]), .DPO(data1_out[0])
);
RAM16X1D ram16x1_1 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[1]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[1]), .DPO(data1_out[1])
);
RAM16X1D ram16x1_2 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[2]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[2]), .DPO(data1_out[2])
);
RAM16X1D ram16x1_3 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[3]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[3]), .DPO(data1_out[3])
);
RAM16X1D ram16x1_4 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[4]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[4]), .DPO(data1_out[4])
);
RAM16X1D ram16x1_5 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[5]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[5]), .DPO(data1_out[5])
);
RAM16X1D ram16x1_6 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[6]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[6]), .DPO(data1_out[6])
);
RAM16X1D ram16x1_7 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[7]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[7]), .DPO(data1_out[7])
);
RAM16X1D ram16x1_8 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[8]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[8]), .DPO(data1_out[8])
);
RAM16X1D ram16x1_9 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[9]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[9]), .DPO(data1_out[9])
);
RAM16X1D ram16x1_10 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[10]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[10]), .DPO(data1_out[10])
);
RAM16X1D ram16x1_11 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[11]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[11]), .DPO(data1_out[11])
);
RAM16X1D ram16x1_12 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[12]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[12]), .DPO(data1_out[12])
);
RAM16X1D ram16x1_13 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[13]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[13]), .DPO(data1_out[13])
);
RAM16X1D ram16x1_14 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[14]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[14]), .DPO(data1_out[14])
);
RAM16X1D ram16x1_15 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[15]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[15]), .DPO(data1_out[15])
);
RAM16X1D ram16x1_16 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[16]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[16]), .DPO(data1_out[16])
);
RAM16X1D ram16x1_17 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[17]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[17]), .DPO(data1_out[17])
);
RAM16X1D ram16x1_18 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[18]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[18]), .DPO(data1_out[18])
);
RAM16X1D ram16x1_19 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[19]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[19]), .DPO(data1_out[19])
);
RAM16X1D ram16x1_20 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[20]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[20]), .DPO(data1_out[20])
);
RAM16X1D ram16x1_21 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[21]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[21]), .DPO(data1_out[21])
);
RAM16X1D ram16x1_22 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[22]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[22]), .DPO(data1_out[22])
);
RAM16X1D ram16x1_23 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[23]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[23]), .DPO(data1_out[23])
);
RAM16X1D ram16x1_24 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[24]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[24]), .DPO(data1_out[24])
);
RAM16X1D ram16x1_25 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[25]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[25]), .DPO(data1_out[25])
);
RAM16X1D ram16x1_26 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[26]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[26]), .DPO(data1_out[26])
);
RAM16X1D ram16x1_27 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[27]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[27]), .DPO(data1_out[27])
);
RAM16X1D ram16x1_28 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[28]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[28]), .DPO(data1_out[28])
);
RAM16X1D ram16x1_29 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[29]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[29]), .DPO(data1_out[29])
);
RAM16X1D ram16x1_30 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[30]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[30]), .DPO(data1_out[30])
);
RAM16X1D ram16x1_31 (
.A0(addr0[0]), .A1(addr0[1]), .A2(addr0[2]), .A3(addr0[3]),
.D(data0_in[31]), .WCLK(clk), .WE(we),
.DPRA0(addr1[0]), .DPRA1(addr1[1]), .DPRA2(addr1[2]),
.DPRA3(addr1[3]),
.SPO(dummy[31]), .DPO(data1_out[31])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_4_V
`define SKY130_FD_SC_LP__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`include "verilated.v"
module t;
// Note $sscanf already tested elsewhere
reg [3:0] n;
reg [63:0] q;
reg [16*8:1] wide;
reg [8:1] ochar;
reg [48*8:1] str;
reg [48*8:1] str2;
string str3;
real r;
initial begin
n = 4'b1100;
q = 64'h1234_5678_abcd_0123;
wide = "hello-there12345";
$sformat(str, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
q = {q[62:0],1'b1};
$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
str3 = $sformatf("n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif
if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
$swrite(str2, "e=%e", r);
$swrite(str2, "e=%f", r);
$swrite(str2, "e=%g", r);
r = 0.01;
$swrite(str2, "e=%e f=%f g=%g", r, r, r);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
$swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator
if (str2 !== "mod=top.v") $stop;
`else
if (str2 !== "mod=top.t") $stop;
`endif
$swrite(str2, "lib=%l");
`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif
if (str2 !== "lib=t") $stop;
str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable
`ifdef TEST_VERBOSE $display("chku %0x %s",str3,str3); `endif
if (str3 !== "u=dcba") $stop;
str3 = $sformatf("v=%v", {"a","b","c","d"}); // Value selected so is printable
`ifdef TEST_VERBOSE $display("chkv %0x %s",str3,str3); `endif
$sformat(ochar,"%s","c");
if (ochar != "c") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: rxuartlite.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: Receive and decode inputs from a single UART line.
//
//
// To interface with this module, connect it to your system clock,
// and a UART input. Set the parameter to the number of clocks per
// baud. When data becomes available, the o_wr line will be asserted
// for one clock cycle.
//
// This interface only handles 8N1 serial port communications. It does
// not handle the break, parity, or frame error conditions.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
// }}}
module rxuartlite #(
// {{{
parameter TIMER_BITS = 10,
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 MBaud at 100MHz
`endif
localparam TB = TIMER_BITS,
//
localparam [3:0] RXUL_BIT_ZERO = 4'h0,
// Verilator lint_off UNUSED
// These are used by the formal solver
localparam [3:0] RXUL_BIT_ONE = 4'h1,
localparam [3:0] RXUL_BIT_TWO = 4'h2,
localparam [3:0] RXUL_BIT_THREE = 4'h3,
localparam [3:0] RXUL_BIT_FOUR = 4'h4,
localparam [3:0] RXUL_BIT_FIVE = 4'h5,
localparam [3:0] RXUL_BIT_SIX = 4'h6,
localparam [3:0] RXUL_BIT_SEVEN = 4'h7,
// Verilator lint_on UNUSED
localparam [3:0] RXUL_STOP = 4'h8,
localparam [3:0] RXUL_WAIT = 4'h9,
localparam [3:0] RXUL_IDLE = 4'hf
// }}}
) (
// {{{
input wire i_clk,
input wire i_uart_rx,
output reg o_wr,
output reg [7:0] o_data
// }}}
);
// Signal/register declarations
// {{{
wire [(TB-1):0] half_baud;
reg [3:0] state;
assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] };
reg [(TB-1):0] baud_counter;
reg zero_baud_counter;
reg q_uart, qq_uart, ck_uart;
reg [(TB-1):0] chg_counter;
reg half_baud_time;
reg [7:0] data_reg;
// }}}
// ck_uart
// {{{
// Since this is an asynchronous receiver, we need to register our
// input a couple of clocks over to avoid any problems with
// metastability. We do that here, and then ignore all but the
// ck_uart wire.
initial q_uart = 1'b1;
initial qq_uart = 1'b1;
initial ck_uart = 1'b1;
always @(posedge i_clk)
{ ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx };
// }}}
// chg_counter
// {{{
// Keep track of the number of clocks since the last change.
//
// This is used to determine if we are in either a break or an idle
// condition, as discussed further below.
initial chg_counter = {(TB){1'b1}};
always @(posedge i_clk)
if (qq_uart != ck_uart)
chg_counter <= 0;
else if (chg_counter != { (TB){1'b1} })
chg_counter <= chg_counter + 1;
// }}}
// half_baud_time
// {{{
// Are we in the middle of a baud iterval? Specifically, are we
// in the middle of a start bit? Set this to high if so. We'll use
// this within our state machine to transition out of the IDLE
// state.
initial half_baud_time = 0;
always @(posedge i_clk)
half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1);
// }}}
// state
// {{{
initial state = RXUL_IDLE;
always @(posedge i_clk)
if (state == RXUL_IDLE)
begin // Idle state, independent of baud counter
// {{{
// By default, just stay in the IDLE state
state <= RXUL_IDLE;
if ((!ck_uart)&&(half_baud_time))
// UNLESS: We are in the center of a valid
// start bit
state <= RXUL_BIT_ZERO;
// }}}
end else if ((state >= RXUL_WAIT)&&(ck_uart))
state <= RXUL_IDLE;
else if (zero_baud_counter)
begin
// {{{
if (state <= RXUL_STOP)
// Data arrives least significant bit first.
// By the time this is clocked in, it's what
// you'll have.
state <= state + 1;
// }}}
end
// }}}
// data_reg
// {{{
// Data bit capture logic.
//
// This is drastically simplified from the state machine above, based
// upon: 1) it doesn't matter what it is until the end of a captured
// byte, and 2) the data register will flush itself of any invalid
// data in all other cases. Hence, let's keep it real simple.
always @(posedge i_clk)
if ((zero_baud_counter)&&(state != RXUL_STOP))
data_reg <= { qq_uart, data_reg[7:1] };
// }}}
// o_wr, o_data
// {{{
// Our data bit logic doesn't need nearly the complexity of all that
// work above. Indeed, we only need to know if we are at the end of
// a stop bit, in which case we copy the data_reg into our output
// data register, o_data, and tell others (for one clock) that data is
// available.
//
initial o_wr = 1'b0;
initial o_data = 8'h00;
always @(posedge i_clk)
if ((zero_baud_counter)&&(state == RXUL_STOP)&&(ck_uart))
begin
o_wr <= 1'b1;
o_data <= data_reg;
end else
o_wr <= 1'b0;
// }}}
// baud_counter -- The baud counter
// {{{
// This is used as a "clock divider" if you will, but the clock needs
// to be reset before any byte can be decoded. In all other respects,
// we set ourselves up for CLOCKS_PER_BAUD counts between baud
// intervals.
initial baud_counter = 0;
always @(posedge i_clk)
if (((state==RXUL_IDLE))&&(!ck_uart)&&(half_baud_time))
baud_counter <= CLOCKS_PER_BAUD-1'b1;
else if (state == RXUL_WAIT)
baud_counter <= 0;
else if ((zero_baud_counter)&&(state < RXUL_STOP))
baud_counter <= CLOCKS_PER_BAUD-1'b1;
else if (!zero_baud_counter)
baud_counter <= baud_counter-1'b1;
// }}}
// zero_baud_counter
// {{{
// Rather than testing whether or not (baud_counter == 0) within our
// (already too complicated) state transition tables, we use
// zero_baud_counter to pre-charge that test on the clock
// before--cleaning up some otherwise difficult timing dependencies.
initial zero_baud_counter = 1'b1;
always @(posedge i_clk)
if ((state == RXUL_IDLE)&&(!ck_uart)&&(half_baud_time))
zero_baud_counter <= 1'b0;
else if (state == RXUL_WAIT)
zero_baud_counter <= 1'b1;
else if ((zero_baud_counter)&&(state < RXUL_STOP))
zero_baud_counter <= 1'b0;
else if (baud_counter == 1)
zero_baud_counter <= 1'b1;
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal properties
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Declarations
// {{{
`ifdef FORMAL
`define FORMAL_VERILATOR
`else
`ifdef VERILATOR
`define FORMAL_VERILATOR
`endif
`endif
`ifdef FORMAL
`define ASSUME assume
`define ASSERT assert
`ifdef VERIFIC
// We need this to use $global_clock below
(* gclk *) wire gbl_clk;
global clocking @(posedge gbl_clk); endclocking
`endif
localparam F_CKRES = 10;
(* anyseq *) wire f_tx_start;
(* anyconst *) wire [(F_CKRES-1):0] f_tx_step;
reg f_tx_zclk;
reg [(TB-1):0] f_tx_timer;
wire [7:0] f_rx_newdata;
reg [(TB-1):0] f_tx_baud;
wire f_tx_zbaud;
wire [(TB-1):0] f_max_baud_difference;
reg [(TB-1):0] f_baud_difference;
reg [(TB+3):0] f_tx_count, f_rx_count;
(* anyseq *) wire [7:0] f_tx_data;
wire f_txclk;
reg [1:0] f_rx_clock;
reg [(F_CKRES-1):0] f_tx_clock;
reg f_past_valid, f_past_valid_tx;
reg [9:0] f_tx_reg;
reg f_tx_busy;
// }}}
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
initial f_rx_clock = 3'h0;
always @($global_clock)
f_rx_clock <= f_rx_clock + 1'b1;
always @(*)
assume(i_clk == f_rx_clock[1]);
////////////////////////////////////////////////////////////////////////
//
// Assume a transmitted signal
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// First, calculate the transmit clock
localparam [(F_CKRES-1):0] F_MIDSTEP = { 2'b01, {(F_CKRES-2){1'b0}} };
//
// Need to allow us to slip by half a baud clock over 10 baud intervals
//
// (F_STEP / (2^F_CKRES)) * (CLOCKS_PER_BAUD)*10 < CLOCKS_PER_BAUD/2
// F_STEP * 2 * 10 < 2^F_CKRES
localparam [(F_CKRES-1):0] F_HALFSTEP= F_MIDSTEP/32;
localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1;
localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1;
initial assert(F_MINSTEP <= F_MIDSTEP);
initial assert(F_MIDSTEP <= F_MAXSTEP);
// assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));
//
//
always @(*) assume((f_tx_step == F_MINSTEP)
||(f_tx_step == F_MIDSTEP)
||(f_tx_step == F_MAXSTEP));
always @($global_clock)
f_tx_clock <= f_tx_clock + f_tx_step;
assign f_txclk = f_tx_clock[F_CKRES-1];
//
initial f_past_valid_tx = 1'b0;
always @(posedge f_txclk)
f_past_valid_tx <= 1'b1;
initial assume(i_uart_rx);
////////////////////////////////////////////////////////////////////////
//
// The simulated timing generator
always @(*)
if (f_tx_busy)
assume(!f_tx_start);
initial f_tx_baud = 0;
always @(posedge f_txclk)
if ((f_tx_zbaud)&&((f_tx_busy)||(f_tx_start)))
f_tx_baud <= CLOCKS_PER_BAUD-1'b1;
else if (!f_tx_zbaud)
f_tx_baud <= f_tx_baud - 1'b1;
always @(*)
`ASSERT(f_tx_baud < CLOCKS_PER_BAUD);
always @(*)
if (!f_tx_busy)
`ASSERT(f_tx_baud == 0);
assign f_tx_zbaud = (f_tx_baud == 0);
// But only if we aren't busy
initial assume(f_tx_data == 0);
always @(posedge f_txclk)
if ((!f_tx_zbaud)||(f_tx_busy)||(!f_tx_start))
assume(f_tx_data == $past(f_tx_data));
// Force the data to change on a clock only
always @($global_clock)
if ((f_past_valid)&&(!$rose(f_txclk)))
assume($stable(f_tx_data));
else if (f_tx_busy)
assume($stable(f_tx_data));
//
always @($global_clock)
if ((!f_past_valid)||(!$rose(f_txclk)))
begin
assume($stable(f_tx_start));
assume($stable(f_tx_data));
end
//
//
//
// Here's the transmitter itself (roughly)
initial f_tx_busy = 1'b0;
initial f_tx_reg = 0;
always @(posedge f_txclk)
if (!f_tx_zbaud)
begin
`ASSERT(f_tx_busy);
end else begin
f_tx_reg <= { 1'b0, f_tx_reg[9:1] };
if (f_tx_start)
f_tx_reg <= { 1'b1, f_tx_data, 1'b0 };
end
// Create a busy flag that we'll use
always @(*)
if (!f_tx_zbaud)
f_tx_busy <= 1'b1;
else if (|f_tx_reg)
f_tx_busy <= 1'b1;
else
f_tx_busy <= 1'b0;
//
// Tie the TX register to the TX data
always @(posedge f_txclk)
if (f_tx_reg[9])
`ASSERT(f_tx_reg[8:0] == { f_tx_data, 1'b0 });
else if (f_tx_reg[8])
`ASSERT(f_tx_reg[7:0] == f_tx_data[7:0] );
else if (f_tx_reg[7])
`ASSERT(f_tx_reg[6:0] == f_tx_data[7:1] );
else if (f_tx_reg[6])
`ASSERT(f_tx_reg[5:0] == f_tx_data[7:2] );
else if (f_tx_reg[5])
`ASSERT(f_tx_reg[4:0] == f_tx_data[7:3] );
else if (f_tx_reg[4])
`ASSERT(f_tx_reg[3:0] == f_tx_data[7:4] );
else if (f_tx_reg[3])
`ASSERT(f_tx_reg[2:0] == f_tx_data[7:5] );
else if (f_tx_reg[2])
`ASSERT(f_tx_reg[1:0] == f_tx_data[7:6] );
else if (f_tx_reg[1])
`ASSERT(f_tx_reg[0] == f_tx_data[7]);
// Our counter since we start
initial f_tx_count = 0;
always @(posedge f_txclk)
if (!f_tx_busy)
f_tx_count <= 0;
else
f_tx_count <= f_tx_count + 1'b1;
always @(*)
if (f_tx_reg == 10'h0)
assume(i_uart_rx);
else
assume(i_uart_rx == f_tx_reg[0]);
//
// Make sure the absolute transmit clock timer matches our state
//
always @(posedge f_txclk)
if (!f_tx_busy)
begin
if ((!f_past_valid_tx)||(!$past(f_tx_busy)))
`ASSERT(f_tx_count == 0);
end else if (f_tx_reg[9])
`ASSERT(f_tx_count ==
CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[8])
`ASSERT(f_tx_count ==
2 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[7])
`ASSERT(f_tx_count ==
3 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[6])
`ASSERT(f_tx_count ==
4 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[5])
`ASSERT(f_tx_count ==
5 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[4])
`ASSERT(f_tx_count ==
6 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[3])
`ASSERT(f_tx_count ==
7 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[2])
`ASSERT(f_tx_count ==
8 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[1])
`ASSERT(f_tx_count ==
9 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else if (f_tx_reg[0])
`ASSERT(f_tx_count ==
10 * CLOCKS_PER_BAUD -1 -f_tx_baud);
else
`ASSERT(f_tx_count ==
11 * CLOCKS_PER_BAUD -1 -f_tx_baud);
// }}}
////////////////////////////////////////////////////////////////////////
//
// Receiver
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// Count RX clocks since the start of the first stop bit, measured in
// rx clocks
initial f_rx_count = 0;
always @(posedge i_clk)
if (state == RXUL_IDLE)
f_rx_count = (!ck_uart) ? (chg_counter+2) : 0;
else
f_rx_count <= f_rx_count + 1'b1;
always @(posedge i_clk)
if (state == 0)
`ASSERT(f_rx_count
== half_baud + (CLOCKS_PER_BAUD-baud_counter));
else if (state == 1)
`ASSERT(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 2)
`ASSERT(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 3)
`ASSERT(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 4)
`ASSERT(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 5)
`ASSERT(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 6)
`ASSERT(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 7)
`ASSERT(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD
- baud_counter);
else if (state == 8)
`ASSERT((f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD
- baud_counter)
||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD
- baud_counter));
always @(*)
`ASSERT( ((!zero_baud_counter)
&&(state == RXUL_IDLE)
&&(baud_counter == 0))
||((zero_baud_counter)&&(baud_counter == 0))
||((!zero_baud_counter)&&(baud_counter != 0)));
always @(posedge i_clk)
if (!f_past_valid)
`ASSERT((state == RXUL_IDLE)&&(baud_counter == 0)
&&(zero_baud_counter));
always @(*)
begin
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h2);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h4);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h5);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h6);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h9);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'ha);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hb);
`ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hd);
end
always @(posedge i_clk)
if ((f_past_valid)&&($past(state) >= RXUL_WAIT)&&($past(ck_uart)))
`ASSERT(state == RXUL_IDLE);
always @(posedge i_clk)
if ((f_past_valid)&&($past(state) >= RXUL_WAIT)
&&(($past(state) != RXUL_IDLE)||(state == RXUL_IDLE)))
`ASSERT(zero_baud_counter);
// Calculate an absolute value of the difference between the two baud
// clocks
always @(posedge i_clk)
if ((f_past_valid)&&($past(state)==RXUL_IDLE)&&(state == RXUL_IDLE))
begin
`ASSERT(($past(ck_uart))
||(chg_counter <=
{ 1'b0, CLOCKS_PER_BAUD[(TB-1):1] }));
end
always @(posedge f_txclk)
if (!f_past_valid_tx)
`ASSERT((state == RXUL_IDLE)&&(baud_counter == 0)
&&(zero_baud_counter)&&(!f_tx_busy));
wire [(TB+3):0] f_tx_count_two_clocks_ago;
assign f_tx_count_two_clocks_ago = f_tx_count - 2;
always @(*)
if (f_tx_count >= f_rx_count + 2)
f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count;
else
f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago;
localparam F_SYNC_DLY = 8;
reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference;
reg [F_CKRES-1:0] ck_tx_clock;
reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock;
reg [TB+3:0] ck_tx_count;
reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count;
initial q_tx_count = 0;
initial ck_tx_count = 0;
initial q_tx_clock = 0;
initial ck_tx_clock = 0;
always @($global_clock)
{ ck_tx_clock, q_tx_clock } <= { q_tx_clock, f_tx_clock };
always @($global_clock)
{ ck_tx_count, q_tx_count } <= { q_tx_count, f_tx_count };
reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time;
always @(*)
f_ck_tx_time = { ck_tx_count, !ck_tx_clock[F_CKRES-1],
ck_tx_clock[F_CKRES-2:0] };
always @(*)
f_rx_time = { f_rx_count, !f_rx_clock[1], f_rx_clock[0],
{(F_CKRES-2){1'b0}} };
reg [TB+4+F_CKRES-1:0] f_signed_difference;
always @(*)
f_signed_difference = f_ck_tx_time - f_rx_time;
always @(*)
if (f_signed_difference[TB+4+F_CKRES-1])
f_sub_baud_difference = -f_signed_difference;
else
f_sub_baud_difference = f_signed_difference;
always @($global_clock)
if (state == RXUL_WAIT)
`ASSERT((!f_tx_busy)||(f_tx_reg[9:1] == 0));
always @($global_clock)
if (state == RXUL_IDLE)
begin
`ASSERT((!f_tx_busy)||(f_tx_reg[9])||(f_tx_reg[9:1]==0));
if (!ck_uart)
;//`PHASE_TWO_ASSERT((f_rx_count < 4)||(f_sub_baud_difference <= ((CLOCKS_PER_BAUD<<F_CKRES)/20)));
else
`ASSERT((f_tx_reg[9:1]==0)||(f_tx_count < (3 + CLOCKS_PER_BAUD/2)));
end else if (state == 0)
`ASSERT(f_sub_baud_difference
<= 2 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 1)
`ASSERT(f_sub_baud_difference
<= 3 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 2)
`ASSERT(f_sub_baud_difference
<= 4 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 3)
`ASSERT(f_sub_baud_difference
<= 5 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 4)
`ASSERT(f_sub_baud_difference
<= 6 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 5)
`ASSERT(f_sub_baud_difference
<= 7 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 6)
`ASSERT(f_sub_baud_difference
<= 8 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 7)
`ASSERT(f_sub_baud_difference
<= 9 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
else if (state == 8)
`ASSERT(f_sub_baud_difference
<= 10 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
always @(posedge i_clk)
if (o_wr)
`ASSERT(o_data == $past(f_tx_data,4));
// always @(posedge i_clk)
// if ((zero_baud_counter)&&(state != 4'hf)&&(CLOCKS_PER_BAUD > 6))
// assert(i_uart_rx == ck_uart);
// Make sure the data register matches
always @(posedge i_clk)
// if ((f_past_valid)&&(state != $past(state)))
begin
if (state == 4'h0)
`ASSERT(!data_reg[7]);
if (state == 4'h1)
`ASSERT((data_reg[7]
== $past(f_tx_data[0]))&&(!data_reg[6]));
if (state == 4'h2)
`ASSERT(data_reg[7:6]
== $past(f_tx_data[1:0]));
if (state == 4'h3)
`ASSERT(data_reg[7:5] == $past(f_tx_data[2:0]));
if (state == 4'h4)
`ASSERT(data_reg[7:4] == $past(f_tx_data[3:0]));
if (state == 4'h5)
`ASSERT(data_reg[7:3] == $past(f_tx_data[4:0]));
if (state == 4'h6)
`ASSERT(data_reg[7:2] == $past(f_tx_data[5:0]));
if (state == 4'h7)
`ASSERT(data_reg[7:1] == $past(f_tx_data[6:0]));
if (state == 4'h8)
`ASSERT(data_reg[7:0] == $past(f_tx_data[7:0]));
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Cover properties
// {{{{
////////////////////////////////////////////////////////////////////////
//
always @(posedge i_clk)
cover(o_wr); // Step 626, takes about 20mins
always @(posedge i_clk)
begin
cover(!ck_uart);
cover((f_past_valid)&&($rose(ck_uart))); // 82
cover((zero_baud_counter)&&(state == RXUL_BIT_ZERO)); // 110
cover((zero_baud_counter)&&(state == RXUL_BIT_ONE)); // 174
cover((zero_baud_counter)&&(state == RXUL_BIT_TWO)); // 238
cover((zero_baud_counter)&&(state == RXUL_BIT_THREE));// 302
cover((zero_baud_counter)&&(state == RXUL_BIT_FOUR)); // 366
cover((zero_baud_counter)&&(state == RXUL_BIT_FIVE)); // 430
cover((zero_baud_counter)&&(state == RXUL_BIT_SIX)); // 494
cover((zero_baud_counter)&&(state == RXUL_BIT_SEVEN));// 558
cover((zero_baud_counter)&&(state == RXUL_STOP)); // 622
cover((zero_baud_counter)&&(state == RXUL_WAIT)); // 626
end
`endif
// }}}
////////////////////////////////////////////////////////////////////////
//
// Properties to test via Verilator *and* formal
// {{{
////////////////////////////////////////////////////////////////////////
//
`ifdef FORMAL_VERILATOR
// FORMAL properties which can be tested via Verilator as well as
// Yosys FORMAL
always @(*)
assert((state == 4'hf)||(state <= RXUL_WAIT));
always @(*)
assert(zero_baud_counter == (baud_counter == 0)? 1'b1:1'b0);
always @(*)
assert(baud_counter <= CLOCKS_PER_BAUD-1'b1);
// }}}
`endif
// }}}
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Thu Oct 13 08:24:14 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2006/01/19 09:18:57 wig Exp $
// $Date: 2006/01/19 09:18:57 $
// $Log: ent_a.v,v $
// Revision 1.2 2006/01/19 09:18:57 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.37 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No `defines in this module
`define const_17_c 8'b00000000 // __I_ConvConstant: 0x0
module ent_a
//
// Generated module inst_a
//
(
const_p_19, // Constant on inst_a
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Module parameters:
parameter generic_15 = 4660;
// Generated Module Inputs:
input [15:0] const_p_19;
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire [15:0] const_p_19;
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] const_17;
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign const_17 = `const_17_c;
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment ...
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.const_p_17(const_17), // Constant
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment ...
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
`ifdef MODEL_TECH
`mti_v2k_int_delays_on
`endif
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive HARDCOPYIII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive HARDCOPYIII_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive HARDCOPYIII_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module hardcopyiii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
HARDCOPYIII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** hardcopyiii_mux21
module hardcopyiii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** hardcopyiii_mux41
module hardcopyiii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** hardcopyiii_and1
module hardcopyiii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** hardcopyiii_and16
module hardcopyiii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** hardcopyiii_bmux21
module hardcopyiii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** hardcopyiii_b17mux21
module hardcopyiii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** hardcopyiii_nmux21
module hardcopyiii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** hardcopyiii_b5mux21
module hardcopyiii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_lcell_comb
//
// Description : HARDCOPYIII LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_lcell_comb (
dataa,
datab,
datac,
datad,
datae,
dataf,
datag,
cin,
sharein,
combout,
sumout,
cout,
shareout
);
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
input datag;
input cin;
input sharein;
output combout;
output sumout;
output cout;
output shareout;
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter shared_arith = "off";
parameter extended_lut = "off";
parameter dont_touch = "off";
parameter lpm_type = "hardcopyiii_lcell_comb";
// sub masks
wire [15:0] f0_mask;
wire [15:0] f1_mask;
wire [15:0] f2_mask;
wire [15:0] f3_mask;
// sub lut outputs
reg f0_out;
reg f1_out;
reg f2_out;
reg f3_out;
// mux output for extended mode
reg g0_out;
reg g1_out;
// either datac or datag
reg f2_input3;
// F2 output using dataf
reg f2_f;
// second input to the adder
reg adder_input2;
// tmp output variables
reg combout_tmp;
reg sumout_tmp;
reg cout_tmp;
// integer representations for string parameters
reg ishared_arith;
reg iextended_lut;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
// 5-input LUT function
function lut5;
input [31:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
reg e0_lut;
reg e1_lut;
reg [15:0] e0_mask;
reg [31:16] e1_mask;
begin
e0_mask = mask[15:0];
e1_mask = mask[31:16];
begin
e0_lut = lut4(e0_mask, dataa, datab, datac, datad);
e1_lut = lut4(e1_mask, dataa, datab, datac, datad);
if (datae === 1'bX) // X propogation
begin
if (e0_lut == e1_lut)
begin
lut5 = e0_lut;
end
else
begin
lut5 = 1'bX;
end
end
else
begin
lut5 = (datae == 1'b1) ? e1_lut : e0_lut;
end
end
end
endfunction
// 6-input LUT function
function lut6;
input [63:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
reg f0_lut;
reg f1_lut;
reg [31:0] f0_mask;
reg [63:32] f1_mask ;
begin
f0_mask = mask[31:0];
f1_mask = mask[63:32];
begin
lut6 = mask[{dataf, datae, datad, datac, datab, dataa}];
if (lut6 === 1'bX)
begin
f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae);
f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae);
if (dataf === 1'bX) // X propogation
begin
if (f0_lut == f1_lut)
begin
lut6 = f0_lut;
end
else
begin
lut6 = 1'bX;
end
end
else
begin
lut6 = (dataf == 1'b1) ? f1_lut : f0_lut;
end
end
end
end
endfunction
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire datae_in;
wire dataf_in;
wire datag_in;
wire cin_in;
wire sharein_in;
buf(dataa_in, dataa);
buf(datab_in, datab);
buf(datac_in, datac);
buf(datad_in, datad);
buf(datae_in, datae);
buf(dataf_in, dataf);
buf(datag_in, datag);
buf(cin_in, cin);
buf(sharein_in, sharein);
specify
(dataa => combout) = (0, 0);
(datab => combout) = (0, 0);
(datac => combout) = (0, 0);
(datad => combout) = (0, 0);
(datae => combout) = (0, 0);
(dataf => combout) = (0, 0);
(datag => combout) = (0, 0);
(dataa => sumout) = (0, 0);
(datab => sumout) = (0, 0);
(datac => sumout) = (0, 0);
(datad => sumout) = (0, 0);
(dataf => sumout) = (0, 0);
(cin => sumout) = (0, 0);
(sharein => sumout) = (0, 0);
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(datac => cout) = (0, 0);
(datad => cout) = (0, 0);
(dataf => cout) = (0, 0);
(cin => cout) = (0, 0);
(sharein => cout) = (0, 0);
(dataa => shareout) = (0, 0);
(datab => shareout) = (0, 0);
(datac => shareout) = (0, 0);
(datad => shareout) = (0, 0);
endspecify
initial
begin
if (shared_arith == "on")
ishared_arith = 1;
else
ishared_arith = 0;
if (extended_lut == "on")
iextended_lut = 1;
else
iextended_lut = 0;
f0_out = 1'b0;
f1_out = 1'b0;
f2_out = 1'b0;
f3_out = 1'b0;
g0_out = 1'b0;
g1_out = 1'b0;
f2_input3 = 1'b0;
adder_input2 = 1'b0;
f2_f = 1'b0;
combout_tmp = 1'b0;
sumout_tmp = 1'b0;
cout_tmp = 1'b0;
end
// sub masks and outputs
assign f0_mask = lut_mask[15:0];
assign f1_mask = lut_mask[31:16];
assign f2_mask = lut_mask[47:32];
assign f3_mask = lut_mask[63:48];
always @(datag_in or dataf_in or datae_in or datad_in or datac_in or
datab_in or dataa_in or cin_in or sharein_in)
begin
// check for extended LUT mode
if (iextended_lut == 1)
f2_input3 = datag_in;
else
f2_input3 = datac_in;
f0_out = lut4(f0_mask, dataa_in, datab_in, datac_in, datad_in);
f1_out = lut4(f1_mask, dataa_in, datab_in, f2_input3, datad_in);
f2_out = lut4(f2_mask, dataa_in, datab_in, datac_in, datad_in);
f3_out = lut4(f3_mask, dataa_in, datab_in, f2_input3, datad_in);
// combout is the 6-input LUT
if (iextended_lut == 1)
begin
if (datae_in == 1'b0)
begin
g0_out = f0_out;
g1_out = f2_out;
end
else if (datae_in == 1'b1)
begin
g0_out = f1_out;
g1_out = f3_out;
end
else
begin
if (f0_out == f1_out)
g0_out = f0_out;
else
g0_out = 1'bX;
if (f2_out == f3_out)
g1_out = f2_out;
else
g1_out = 1'bX;
end
if (dataf_in == 1'b0)
combout_tmp = g0_out;
else if ((dataf_in == 1'b1) || (g0_out == g1_out))
combout_tmp = g1_out;
else
combout_tmp = 1'bX;
end
else
combout_tmp = lut6(lut_mask, dataa_in, datab_in, datac_in,
datad_in, datae_in, dataf_in);
// check for shareed arithmetic mode
if (ishared_arith == 1)
adder_input2 = sharein_in;
else
begin
f2_f = lut4(f2_mask, dataa_in, datab_in, datac_in, dataf_in);
adder_input2 = !f2_f;
end
// sumout & cout
sumout_tmp = cin_in ^ f0_out ^ adder_input2;
cout_tmp = (cin_in & f0_out) | (cin_in & adder_input2) |
(f0_out & adder_input2);
end
and (combout, combout_tmp, 1'b1);
and (sumout, sumout_tmp, 1'b1);
and (cout, cout_tmp, 1'b1);
and (shareout, f2_out, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module hardcopyiii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // hardcopyiii_routing_wire
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_tx_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module hardcopyiii_lvds_tx_reg (q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1))
q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // hardcopyiii_lvds_tx_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_tx_parallel_register
//
// Description : Register for the 10 data input channels of the HARDCOPYIII
// LVDS Tx
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_tx_parallel_register (clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or enable_ipd or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd))
begin
if (enable_ipd === 1'b1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end // always
assign dataout_opd = dataout_tmp;
endmodule //hardcopyiii_lvds_tx_parallel_register
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_tx_out_block
//
// Description : Negative edge triggered register on the Tx output.
// Also, optionally generates an identical/inverted output clock
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_tx_out_block (clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// BUFFER INPUTS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
// TEST PARAMETER VALUES
assign falling_clk_out = (use_falling_clock_edge == "true")?1'b1:1'b0;
assign bypass_mode = (bypass_serializer == "true")?1'b1:1'b0;
assign invert_mode = (invert_clock == "true")?1'b1:1'b0;
// TIMING PATHS
specify
if (bypass_mode == 1'b1)
(clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 0;
end
else begin
if (bypass_serializer == "false")
begin
if (use_falling_clock_edge == "false")
dataout_tmp <= datain_in;
if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
begin
if (use_falling_clock_edge == "true")
dataout_tmp <= datain_in;
end
end // bypass is off
else begin
// generate clk_out
if (invert_clock == "false")
dataout_tmp <= clk_in;
else
dataout_tmp <= !clk_in;
end // clk output
end
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule //hardcopyiii_lvds_tx_out_block
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_transmitter
//
// Description : Timing simulation model for the HARDCOPYIII LVDS Tx WYSIWYG.
// It instantiates the following sub-modules :
// 1) primitive DFFE
// 2) HARDCOPYIII_lvds_tx_parallel_register and
// 3) HARDCOPYIII_lvds_tx_out_block
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_transmitter (clk0,
enable0,
datain,
serialdatain,
postdpaserialdatain,
dataout,
serialfdbkout,
dpaclkin,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
parameter use_serial_data_input = "false";
parameter use_post_dpa_serial_data_input = "false";
parameter is_used_as_outclk = "false";
parameter tx_output_path_delay_engineering_bits = -1;
parameter enable_dpaclk_to_lvdsout = "off";
parameter preemphasis_setting = 0;
parameter vod_setting = 0;
parameter differential_drive = 0;
parameter lpm_type = "hardcopyiii_lvds_transmitter";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk0;
input enable0;
input serialdatain;
input postdpaserialdatain;
input devclrn;
input devpor;
input dpaclkin;
// OUTPUT PORTS
output dataout;
output serialfdbkout;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES AND NETS
integer i;
wire dataout_tmp;
wire dataout_wire;
wire shift_out;
reg clk0_last_value;
wire [channel_width - 1:0] input_data;
reg [channel_width - 1:0] shift_data;
wire txload0;
reg [channel_width - 1:0] datain_dly;
wire bypass_mode;
wire [channel_width - 1:0] datain_in;
wire serial_din_mode;
wire postdpa_serial_din_mode;
wire enable_dpaclk_to_lvdsout_signal;
wire clk0_in;
wire serialdatain_in;
wire postdpaserialdatain_in;
buf (clk0_in, clk0);
buf datain_buf [channel_width - 1:0] (datain_in, datain);
buf (serialdatain_in, serialdatain);
buf (postdpaserialdatain_in, postdpaserialdatain);
// TEST PARAMETER VALUES
assign serial_din_mode = (use_serial_data_input == "true") ? 1'b1 : 1'b0;
assign postdpa_serial_din_mode = (use_post_dpa_serial_data_input == "true") ? 1'b1 : 1'b0;
assign enable_dpaclk_to_lvdsout_signal = (enable_dpaclk_to_lvdsout == "on") ? 1'b1 : 1'b0;
// TIMING PATHS
specify
if (serial_din_mode == 1'b1)
(serialdatain => dataout) = (0, 0);
if (postdpa_serial_din_mode == 1'b1)
(postdpaserialdatain => dataout) = (0, 0);
if (enable_dpaclk_to_lvdsout_signal == 1'b1)
(dpaclkin => dataout) = (0, 0);
endspecify
initial
begin
i = 0;
clk0_last_value = 0;
shift_data = 'b0;
end
hardcopyiii_lvds_tx_reg txload0_reg (.d(enable0),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(clk0_in),
.q(txload0)
);
hardcopyiii_lvds_tx_out_block output_module (.clk(clk0_in),
.datain(shift_out),
.dataout(dataout_tmp),
.devclrn(devclrn),
.devpor(devpor)
);
defparam output_module.bypass_serializer = bypass_serializer;
defparam output_module.invert_clock = invert_clock;
defparam output_module.use_falling_clock_edge = use_falling_clock_edge;
hardcopyiii_lvds_tx_parallel_register input_reg (.clk(txload0),
.enable(1'b1),
.datain(datain_dly),
.dataout(input_data),
.devclrn(devclrn),
.devpor(devpor)
);
defparam input_reg.channel_width = channel_width;
always @(datain_in)
begin
datain_dly <= #1 datain_in;
end
assign shift_out = shift_data[channel_width - 1];
always @(clk0_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
shift_data <= 'b0;
end
else begin
if (bypass_serializer == "false")
begin
if ((clk0_in === 1'b1) && (clk0_last_value !== clk0_in))
begin
if (txload0 === 1'b1)
begin
for (i = 0; i < channel_width; i = i + 1)
shift_data[i] <= input_data[i];
end
else begin
for (i = (channel_width - 1); i > 0; i = i - 1 )
shift_data[i] <= shift_data[i-1];
end
end
end // bypass is off
end // devpor
clk0_last_value <= clk0_in;
end // always
assign dataout_wire = (use_serial_data_input == "true") ? serialdatain_in :
(use_post_dpa_serial_data_input == "true") ? postdpaserialdatain_in :
(enable_dpaclk_to_lvdsout == "on") ? dpaclkin:
dataout_tmp;
and (dataout, dataout_wire, 1'b1);
and (serialfdbkout, dataout_wire, 1'b1);
endmodule // hardcopyiii_lvds_transmitter
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module hardcopyiii_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
eccstatus,
portadataout,
portbdataout
,dftout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter enable_ecc = "false";
parameter width_eccstatus = 3;
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "hardcopyiii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2048'b0;
parameter mem_init2 = 2048'b0;
parameter mem_init3 = 2048'b0;
parameter mem_init4 = 2048'b0;
parameter mem_init5 = 2048'b0;
parameter mem_init6 = 2048'b0;
parameter mem_init7 = 2048'b0;
parameter mem_init8 = 2048'b0;
parameter mem_init9 = 2048'b0;
parameter mem_init10 = 2048'b0;
parameter mem_init11 = 2048'b0;
parameter mem_init12 = 2048'b0;
parameter mem_init13 = 2048'b0;
parameter mem_init14 = 2048'b0;
parameter mem_init15 = 2048'b0;
parameter mem_init16 = 2048'b0;
parameter mem_init17 = 2048'b0;
parameter mem_init18 = 2048'b0;
parameter mem_init19 = 2048'b0;
parameter mem_init20 = 2048'b0;
parameter mem_init21 = 2048'b0;
parameter mem_init22 = 2048'b0;
parameter mem_init23 = 2048'b0;
parameter mem_init24 = 2048'b0;
parameter mem_init25 = 2048'b0;
parameter mem_init26 = 2048'b0;
parameter mem_init27 = 2048'b0;
parameter mem_init28 = 2048'b0;
parameter mem_init29 = 2048'b0;
parameter mem_init30 = 2048'b0;
parameter mem_init31 = 2048'b0;
parameter mem_init32 = 2048'b0;
parameter mem_init33 = 2048'b0;
parameter mem_init34 = 2048'b0;
parameter mem_init35 = 2048'b0;
parameter mem_init36 = 2048'b0;
parameter mem_init37 = 2048'b0;
parameter mem_init38 = 2048'b0;
parameter mem_init39 = 2048'b0;
parameter mem_init40 = 2048'b0;
parameter mem_init41 = 2048'b0;
parameter mem_init42 = 2048'b0;
parameter mem_init43 = 2048'b0;
parameter mem_init44 = 2048'b0;
parameter mem_init45 = 2048'b0;
parameter mem_init46 = 2048'b0;
parameter mem_init47 = 2048'b0;
parameter mem_init48 = 2048'b0;
parameter mem_init49 = 2048'b0;
parameter mem_init50 = 2048'b0;
parameter mem_init51 = 2048'b0;
parameter mem_init52 = 2048'b0;
parameter mem_init53 = 2048'b0;
parameter mem_init54 = 2048'b0;
parameter mem_init55 = 2048'b0;
parameter mem_init56 = 2048'b0;
parameter mem_init57 = 2048'b0;
parameter mem_init58 = 2048'b0;
parameter mem_init59 = 2048'b0;
parameter mem_init60 = 2048'b0;
parameter mem_init61 = 2048'b0;
parameter mem_init62 = 2048'b0;
parameter mem_init63 = 2048'b0;
parameter mem_init64 = 2048'b0;
parameter mem_init65 = 2048'b0;
parameter mem_init66 = 2048'b0;
parameter mem_init67 = 2048'b0;
parameter mem_init68 = 2048'b0;
parameter mem_init69 = 2048'b0;
parameter mem_init70 = 2048'b0;
parameter mem_init71 = 2048'b0;
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// Hardware write modes
parameter dual_clock = ((operation_mode == "dual_port") ||
(operation_mode == "bidir_dual_port")) &&
(port_b_address_clock == "clock1");
parameter both_new_data_same_port = (
((port_a_read_during_write_mode == "new_data_no_nbe_read") ||
(port_a_read_during_write_mode == "dont_care")) &&
((port_b_read_during_write_mode == "new_data_no_nbe_read") ||
(port_b_read_during_write_mode == "dont_care"))
) ? 1'b1 : 1'b0;
parameter hw_write_mode_a = (
((port_a_read_during_write_mode == "old_data") ||
(port_a_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter hw_write_mode_b = (
((port_b_read_during_write_mode == "old_data") ||
(port_b_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter delay_write_pulse_a = (mode_is_dp && mixed_port_feed_through_mode == "dont_care") ? 1'b0 : ((hw_write_mode_a != "FW") ? 1'b1 : 1'b0);
parameter delay_write_pulse_b = (hw_write_mode_b != "FW") ? 1'b1 : 1'b0;
parameter be_mask_write_a = (port_a_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter be_mask_write_b = (port_b_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter old_data_write_a = (port_a_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter old_data_write_b = (port_b_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter read_before_write_a = (hw_write_mode_a == "R+W") ? 1'b1 : 1'b0;
parameter read_before_write_b = (hw_write_mode_b == "R+W") ? 1'b1 : 1'b0;
parameter clock_duty_cycle_dependence = "ON";
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
output [width_eccstatus - 1:0] eccstatus;
output [8:0] dftout;
tri0 portawe_int;
assign portawe_int = portawe;
tri1 portare_int;
assign portare_int = portare;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbwe_int;
assign portbwe_int = portbwe;
tri1 portbre_int;
assign portbre_int = portbre;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 ena2_int,ena3_int;
assign ena2_int = ena2;
assign ena3_int = ena3;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_a_rena, clk_a_wena;
wire clk_a_core;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire clk_b_rena, clk_b_wena;
wire clk_b_core;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire dataout_a_clr_reg, dataout_b_clr_reg;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr, re_a_clr, we_b_clr, re_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in, re_a_clr_in, we_b_clr_in, re_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire re_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire we_b_reg, re_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire rw_pulse_a, rw_pulse_b;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
wire rw_pulse_prime, rw_pulse_sec;
reg read_pulse_prime_last_value, read_pulse_sec_last_value;
reg rw_pulse_prime_last_value, rw_pulse_sec_last_value;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a_in, active_b_in;
wire active_a_core,active_a_core_in,active_b_core,active_b_core_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = 0;
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {
mem_init71 , mem_init70 , mem_init69 , mem_init68 , mem_init67 ,
mem_init66 , mem_init65 , mem_init64 , mem_init63 , mem_init62 ,
mem_init61 , mem_init60 , mem_init59 , mem_init58 , mem_init57 ,
mem_init56 , mem_init55 , mem_init54 , mem_init53 , mem_init52 ,
mem_init51 , mem_init50 , mem_init49 , mem_init48 , mem_init47 ,
mem_init46 , mem_init45 , mem_init44 , mem_init43 , mem_init42 ,
mem_init41 , mem_init40 , mem_init39 , mem_init38 , mem_init37 ,
mem_init36 , mem_init35 , mem_init34 , mem_init33 , mem_init32 ,
mem_init31 , mem_init30 , mem_init29 , mem_init28 , mem_init27 ,
mem_init26 , mem_init25 , mem_init24 , mem_init23 , mem_init22 ,
mem_init21 , mem_init20 , mem_init19 , mem_init18 , mem_init17 ,
mem_init16 , mem_init15 , mem_init14 , mem_init13 , mem_init12 ,
mem_init11 , mem_init10 , mem_init9 , mem_init8 , mem_init7 ,
mem_init6 , mem_init5 ,
mem_init4 , mem_init3 , mem_init2 ,
mem_init1 , mem_init0
};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_wena = (port_a_write_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_rena = (port_a_read_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_wena = (port_b_write_enable_clock == "none") ? 1'b0 : (
(port_b_write_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_rena = (port_b_read_enable_clock == "none") ? 1'b0 : (
(port_b_read_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = 1'b0;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = 1'b0;
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = 1'b0;
assign byteena_b_clr_in = 1'b0;
assign we_a_clr_in = 1'b0;
assign re_a_clr_in = 1'b0;
assign we_b_clr_in = 1'b0;
assign re_b_clr_in = 1'b0;
assign active_a_in = (clk0_input_clock_enable == "none") ? 1'b1 : (
(clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_a_core_in = (clk0_core_clock_enable == "none") ? 1'b1 : (
(clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_b_in = (port_b_address_clock == "clock0") ? (
(clk0_input_clock_enable == "none") ? 1'b1 : ((clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_input_clock_enable == "none") ? 1'b1 : ((clk1_input_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_b_core_in = (port_b_address_clock == "clock0") ? (
(clk0_core_clock_enable == "none") ? 1'b1 : ((clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_core_clock_enable == "none") ? 1'b1 : ((clk1_core_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_write_a = (byteena_a_reg !== 'b0);
assign active_write_b = (byteena_b_reg !== 'b0);
// Store core clock enable value for delayed write
// port A core active
hardcopyiii_ram_register active_core_port_a (
.d(active_a_core_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a_core),.aclrout()
);
defparam active_core_port_a.width = 1;
// port B core active
hardcopyiii_ram_register active_core_port_b (
.d(active_b_core_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b_core),.aclrout()
);
defparam active_core_port_b.width = 1;
// ------- A input registers -------
// write enable
hardcopyiii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_wena),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_core_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// read enable
hardcopyiii_ram_register re_a_register (
.d(portare_int),
.clk(clk_a_rena),
.aclr(re_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_core_in),
.q(re_a_reg),
.aclrout(re_a_clr)
);
// address
hardcopyiii_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
hardcopyiii_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
hardcopyiii_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// write enable
hardcopyiii_ram_register we_b_register (
.d(portbwe_int),
.clk(clk_b_wena),
.aclr(we_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_core_in),
.q(we_b_reg),
.aclrout(we_b_clr)
);
defparam we_b_register.width = 1;
defparam we_b_register.preset = 1'b0;
// read enable
hardcopyiii_ram_register re_b_register (
.d(portbre_int),
.clk(clk_b_rena),
.aclr(re_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_core_in),
.q(re_b_reg),
.aclrout(re_b_clr)
);
defparam re_b_register.width = 1;
defparam re_b_register.preset = 1'b0;
// address
hardcopyiii_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
hardcopyiii_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
hardcopyiii_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Hardware Write Modes
// HARDCOPYIII
// Write pulse generation
hardcopyiii_ram_pulse_generator wpgen_a (
.clk(clk_a_in),
.ena(active_a_core & active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
defparam wpgen_a.delay_pulse = delay_write_pulse_a;
hardcopyiii_ram_pulse_generator wpgen_b (
.clk(clk_b_in),
.ena(active_b_core & active_write_b & mode_is_bdp & we_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
defparam wpgen_b.delay_pulse = delay_write_pulse_b;
// Read pulse generation
hardcopyiii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & ~we_a_reg),
.pulse(read_pulse_a),
.cycle(clk_a_core)
);
hardcopyiii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~we_b_reg),
.pulse(read_pulse_b),
.cycle(clk_b_core)
);
// Read during write pulse generation
hardcopyiii_ram_pulse_generator rwpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & we_a_reg & read_before_write_a),
.pulse(rw_pulse_a),.cycle()
);
hardcopyiii_ram_pulse_generator rwpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & re_b_reg & we_b_reg & read_before_write_b),
.pulse(rw_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign rw_pulse_prime = (primary_port_is_a) ? rw_pulse_a : rw_pulse_b;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
assign rw_pulse_sec = (primary_port_is_a) ? rw_pulse_b : rw_pulse_a;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
or posedge rw_pulse_prime or posedge rw_pulse_sec
)
begin
// Read before Write stage 1 : read data from memory
if (rw_pulse_prime && (rw_pulse_prime !== rw_pulse_prime_last_value))
begin
read_data_latch = mem[addr_prime_reg];
rw_pulse_prime_last_value = rw_pulse_prime;
end
if (rw_pulse_sec && (rw_pulse_sec !== rw_pulse_sec_last_value))
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
rw_pulse_sec_last_value = rw_pulse_sec;
end
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
if ((row_sec == addr_prime_reg) && (read_pulse_sec))
begin
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime && read_pulse_prime !== read_pulse_prime_last_value)
begin
read_data_latch = mem[addr_prime_reg];
read_pulse_prime_last_value = read_pulse_prime;
end
if (read_pulse_sec && read_pulse_sec !== read_pulse_sec_last_value)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
read_pulse_sec_last_value = read_pulse_sec;
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
always @(negedge read_pulse_prime) read_pulse_prime_last_value = 1'b0;
always @(negedge read_pulse_sec) read_pulse_sec_last_value = 1'b0;
always @(negedge rw_pulse_prime) rw_pulse_prime_last_value = 1'b0;
always @(negedge rw_pulse_sec) rw_pulse_sec_last_value = 1'b0;
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Read during Write stage 2 : Send data to output
always @(negedge rw_pulse_prime)
begin
if (primary_port_is_a)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_a[i] = read_data_latch[i];
end
else
dataout_a = read_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_b[i] = read_data_latch[i];
end
else
dataout_b = read_data_latch;
end
end
always @(negedge rw_pulse_sec)
begin
if (primary_port_is_b)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_a[i] = read_unit_data_latch[i];
end
else
dataout_a = read_unit_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_b[i] = read_unit_data_latch[i];
end
else
dataout_b = read_unit_data_latch;
end
end
// Same port feed through
hardcopyiii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a_core & ~mode_is_dp & ~old_data_write_a & we_a_reg & re_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
hardcopyiii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & ~old_data_write_b & we_b_reg & re_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_a[i] = datain_prime_reg[i];
end
else
dataout_a = datain_prime_reg ^ mask_vector_prime;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_b[i] = datain_prime_reg[i];
end
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_a[i] = datain_sec_reg[i];
end
else
dataout_a = datain_sec_reg ^ mask_vector_sec;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_b[i] = datain_sec_reg[i];
end
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a_core & re_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge we_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
mem_invalidate = 1'b1;
else if ((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg)
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge we_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Aclr mux registers (Latch Clear) --------
// port A
hardcopyiii_ram_register aclr__a__mux_register (
.d(dataout_a_clr),
.clk(clk_a_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_a_clr_reg),.aclrout()
);
// port B
hardcopyiii_ram_register aclr__b__mux_register (
.d(dataout_b_clr),
.clk(clk_b_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_b_clr_reg),.aclrout()
);
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
hardcopyiii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
reg [port_a_data_width - 1:0] portadataout_clr;
reg [port_b_data_width - 1:0] portbdataout_clr;
initial
begin
portadataout_clr = 'b0;
portbdataout_clr = 'b0;
end
assign portadataout = (out_a_is_reg) ? dataout_a_reg : (
(dataout_a_clr || dataout_a_clr_reg) ? portadataout_clr : dataout_a
);
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
hardcopyiii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : (
(dataout_b_clr || dataout_b_clr_reg) ? portbdataout_clr : dataout_b
);
assign eccstatus = {width_eccstatus{1'b0}};
endmodule // hardcopyiii_ram_block
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_ff
//
// Description : HARDCOPYIII FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "hardcopyiii_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_clkselect
//
// Description : HARDCOPYIII CLKSELECT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_clkselect
(
inclk,
clkselect,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
output outclk;
parameter lpm_type = "hardcopyiii_clkselect";
wire clkmux_out; // output of CLK mux
specify
(inclk[3] => outclk) = (0, 0);
(inclk[2] => outclk) = (0, 0);
(inclk[1] => outclk) = (0, 0);
(inclk[0] => outclk) = (0, 0);
(clkselect[1] => outclk) = (0, 0);
(clkselect[0] => outclk) = (0, 0);
endspecify
hardcopyiii_mux41 clk_mux (
.MO(clkmux_out),
.IN0(inclk[0]),
.IN1(inclk[1]),
.IN2(inclk[2]),
.IN3(inclk[3]),
.S({clkselect[1], clkselect[0]}));
and (outclk, clkmux_out, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_and2
//
// Description : Simulation model for a simple 2-inputs AND gate.
// This is used for the storing delays for HARDCOPYIII CLKENA.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module hardcopyiii_and2 (
IN1,
IN2,
Y
);
input IN1;
input IN2;
output Y;
specify
(IN1 => Y) = (0, 0);
(IN2 => Y) = (0, 0);
endspecify
and (Y, IN1, IN2);
endmodule
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module hardcopyiii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk;
end
always @ (clk or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk === 1'b1) & (ena == 1'b1))
q_tmp <= d;
clk_last_value = clk;
end
and (q, q_tmp, 1'b1);
endmodule // hardcopyiii_ena_reg
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_clkena
//
// Description : HARDCOPYIII CLKENA Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_clkena (
inclk,
ena,
devpor,
devclrn,
enaout,
outclk
);
// INPUT PORTS
input inclk;
input ena;
input devpor;
input devclrn;
// OUTPUT PORTS
output enaout;
output outclk;
parameter clock_type = "Auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "hardcopyiii_clkena";
tri1 devclrn;
tri1 devpor;
wire cereg1_out; // output of ENA register1
wire cereg2_out; // output of ENA register2
wire ena_out; // choice of registered ENA or none.
hardcopyiii_ena_reg extena_reg1(
.clk(!inclk),
.ena(1'b1),
.d(ena),
.clrn(1'b1),
.prn(devpor),
.q(cereg1_out)
);
hardcopyiii_ena_reg extena_reg2(
.clk(!inclk),
.ena(1'b1),
.d(cereg1_out),
.clrn(1'b1),
.prn(devpor),
.q(cereg2_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg1_out :
((ena_register_mode == "none") ? ena : cereg2_out);
hardcopyiii_and2 outclk_and(
.IN1(inclk),
.IN2(ena_out),
.Y(outclk)
);
hardcopyiii_and2 enaout_and(
.IN1(1'b1),
.IN2(ena_out),
.Y(enaout)
);
endmodule
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_hram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_hram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(1) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_hram
// Description : Main RAM module
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_hram
(
portadatain,
portaaddr,
portabyteenamasks,
portbaddr,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
devclrn,
devpor,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter logical_ram_name = "hram";
parameter logical_ram_depth = 0;
parameter logical_ram_width = 0;
parameter first_address = 0;
parameter last_address = 0;
parameter first_bit_number = 0;
parameter init_file = "NONE";
parameter data_width = 20;
parameter address_width = 6;
parameter byte_enable_mask_width = 1;
parameter byte_size = 1;
parameter port_b_address_clock = "none";
parameter port_b_address_clear = "none";
parameter port_b_data_out_clock = "none";
parameter port_b_data_out_clear = "none";
parameter lpm_type = "hardcopyiii_hram";
parameter lpm_hint = "true";
parameter mem_init0 = 640'b0; // 64x10 OR 32x20
parameter mixed_port_feed_through_mode = "dont_care";
// -------- PORT DECLARATIONS ---------
input [data_width - 1:0] portadatain;
input [address_width - 1:0] portaaddr;
input [byte_enable_mask_width - 1:0] portabyteenamasks;
input [address_width - 1:0] portbaddr;
input clk0;
input clk1;
input ena0;
input ena1;
input ena2;
input ena3;
input clr0;
input clr1;
input devclrn;
input devpor;
output [data_width - 1:0] portbdataout;
tri1 devclrn;
tri1 devpor;
tri0 [data_width - 1:0] portadatain;
tri0 [address_width - 1:0] portaaddr;
tri1 [byte_enable_mask_width - 1:0] portabyteenamasks;
tri0 clr0,clr1;
tri0 clk0,clk1;
tri1 ena0,ena1;
tri1 ena2,ena3;
// LOCAL_PARAMETERS_BEGIN
parameter port_byte_size = (data_width / byte_enable_mask_width) + (data_width % byte_enable_mask_width);
parameter num_rows = 1 << address_width;
parameter num_cols = 1;
// LOCAL_PARAMETERS_END
reg ena0_reg;
reg ena1_reg;
reg ena2_reg;
reg ena3_reg;
specify
(portbaddr *> portbdataout) = (0,0);
endspecify
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in, clk_b_in;
wire clk_b_out;
// asynch clear
wire addr_b_clr_in;
wire dataout_b_clr_in;
wire dataout_b_clr;
wire addr_b_clr;
wire addr_a_clr;
wire datain_a_clr;
wire byteena_a_clr;
// port A registers
wire [address_width - 1:0] addr_a_reg;
wire [data_width - 1:0] datain_a_reg;
wire [byte_enable_mask_width - 1:0] byteena_a_reg;
// port B registers
wire [address_width - 1:0] addr_b_reg;
wire [data_width - 1:0] dataout_b;
wire [data_width - 1:0] dataout_b_reg;
wire [data_width - 1:0] portbdataout_tmp;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
// pulses for A/B ports (no read pulse)
wire write_pulse;
wire write_cycle;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
reg [data_width - 1:0] mask_vector, mask_vector_int;
// memory initialization
integer i,j,k;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(last_address - first_address + 1)*data_width - 1:0] mem_init;
// port active for read/write
wire active_a,active_a_in;
wire active_write_a;
initial
begin
ena0_reg = 1'b0;
ena1_reg = 1'b0;
ena2_reg = 1'b0;
ena3_reg = 1'b0;
// powerup output to 0
for (i = 0; i < num_rows; i = i + 1)
mem[i] = {data_width{1'b0}};
mem_init = mem_init0;
addr_range_init = last_address - first_address + 1;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
assign clk_a_in = clk0;
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0 : port_b_address_clock == "clock1" ? clk1 : 1'b0;
assign clk_b_out = (port_b_data_out_clock == "clock1") ? clk1 : 1'b0;
always @(posedge clk_a_in) ena0_reg <= ena0;
always @(posedge clk_b_out) ena1_reg <= ena1;
always @(posedge clk_a_in) ena2_reg <= ena2;
always @(posedge clk_b_in) ena3_reg <= ena3;
assign addr_b_clr_in = (port_b_address_clear == "clear0") ? clr0 : 1'b0;
assign dataout_b_clr_in = (port_b_data_out_clear == "clear1") ? clr1 : 1'b0;
// Port A registers
// address register
hardcopyiii_ram_register addr_a_register(
.d(portaaddr),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(ena2),
.stall(1'b0),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = address_width;
// data register
hardcopyiii_ram_register datain_a_register(
.d(portadatain),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(ena2),
.stall(1'b0),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = data_width;
// byte enable register
hardcopyiii_ram_register byteena_a_register(
.d(portabyteenamasks),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(ena2),
.stall(1'b0),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = byte_enable_mask_width;
// Port B registers
// address register
hardcopyiii_ram_register addr_b_register(
.d(portbaddr),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(ena3),
.stall(1'b0),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = address_width;
// data register
hardcopyiii_ram_register data_b_register(
.d(dataout_b),
.clk(clk_b_out),
.aclr(dataout_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(ena1),
.stall(1'b0),
.q(dataout_b_reg),
.aclrout(dataout_b_clr)
);
defparam data_b_register.width = data_width;
// Write pulse generation
hardcopyiii_hram_pulse_generator wpgen_a (
.clk(~clk_a_in),
.ena(ena0_reg),
.pulse(write_pulse),
.cycle(write_cycle)
);
// Read pulse generation
// -- none --
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < data_width; i = i + 1)
begin
if (byteena_a_reg[i/port_byte_size] === 1'b1)
mask_vector[i] = 1'b0;
else
mask_vector[i] = 1'bx;
if (byteena_a_reg[i/port_byte_size] === 1'b0)
mask_vector_int[i] = 1'b0;
else
mask_vector_int[i] = 1'bx;
end
end
always @(posedge write_pulse)
begin
// Write stage 1 : write X to memory
if (write_pulse)
begin
mem_data = mem[addr_a_reg] ^ mask_vector_int;
mem[addr_a_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector[i] == 1'b0)
mem_data[i] = datain_a_reg[i];
mem[addr_a_reg] = mem_data;
end
// Read stage : asynchronous continuous read
assign dataout_b = (port_b_address_clock == "none") ? mem[portbaddr] : mem[addr_b_reg];
assign portbdataout_tmp = (port_b_data_out_clock == "clock1") ? dataout_b_reg : dataout_b;
assign portbdataout = portbdataout_tmp;
endmodule // hardcopyiii_hram
//////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_io_ibuf //
//Description: Simulation model for HARDCOPYIII IO Input Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_io_ibuf (
i,
ibar,
dynamicterminationcontrol,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "hardcopyiii_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
input dynamicterminationcontrol;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_io_obuf //
//Description: Simulation model for HARDCOPYIII IO Output Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "hardcopyiii_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input dynamicterminationcontrol;
input [13:0] seriesterminationcontrol;
input [13:0] parallelterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = ((oe == 1'b1) && (dynamicterminationcontrol == 1'b1) && (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx :(devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar =((oe == 1'b1) && (dynamicterminationcontrol == 1'b1)&& (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx : (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_ddio_out //
//Description: Simulation model for HARDCOPYIII DDIO Output //
// //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter half_rate_mode = "false";
parameter use_new_clocking_model = "false";
parameter lpm_type = "hardcopyiii_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output [1:0] dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire dffhi1_tmp;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
wire clk_hr;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi[0] = dffhi_tmp;
assign dffhi[1] = dffhi1_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
muxsel_tmp <= mux_sel;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
dffeas ddioreg_hi(
.d(datainhi_tmp),
.clk(clk_hi),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
dffeas ddioreg_hi1(
.d(dffhi_tmp),
.clk(!clk_hr),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi1_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi1.power_up = power_up;
assign clk_hr = (use_new_clocking_model == "true") ? clkhi : clk;
//registered output selection
hardcopyiii_mux21 sel_mux(
.MO(dataout),
.A(sel_mux_lo_in),
.B(sel_mux_hi_in),
.S(muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = (half_rate_mode == "true") ? dffhi1_tmp : dffhi_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_ddio_oe //
//Description: Simulation model for HARDCOPYIII DDIO OE //
// //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "hardcopyiii_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
hardcopyiii_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_ddio_in
//Description: Simulation model for HARDCOPYIII DDIO IN
//
////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_ddio_in (
datain,
clk,
clkn,
ena,
areset,
sreset,
regoutlo,
regouthi,
dfflo,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_clkn = "false";
parameter lpm_type = "hardcopyiii_ddio_in";
//Input Ports Declaration
input datain;
input clk;
input clkn;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output regoutlo;
output regouthi;
//burried port;
output dfflo;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
wire ddioreg_clk;
wire dfflo_tmp;
wire regout_tmp_hi;
wire regout_tmp_lo;
wire dff_ena;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign ddioreg_clk = (use_clkn == "false") ? !clk : clkn;
//Decode the control values for the DDIO registers
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO high Register
dffeas ddioreg_hi(
.d(datain),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_hi),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datain),
.clk(ddioreg_clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
dffeas ddioreg_lo1(
.d(dfflo_tmp),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_lo),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo1.power_up = power_up;
assign regouthi = regout_tmp_hi;
assign regoutlo = regout_tmp_lo;
assign dfflo = dfflo_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_mac_register //
// Description: HARDCOPYIII MAC variable width register //
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_mac_register (
datain,
clk,
aclr,
sload,
bypass_register,
dataout
);
//PARAMETER
parameter data_width = 18;
//INPUT PORTS
input[data_width -1 :0] datain;
input clk;
input aclr;
input sload;
input bypass_register;
//OUTPUT PORTS
output [data_width -1 :0] dataout;
//INTERNAL SIGNALS
reg [data_width -1:0] dataout_tmp;
reg viol_notifier;
reg prev_clk_val;
//TIMING SPECIFICATION
specify
specparam TSU = 0; // Set up time
specparam TH = 0; // Hold time
specparam TCO = 0; // Clock to Output time
specparam TCLR = 0; // Clear time
specparam TCLR_MIN_PW = 0; // Minimum pulse width of clear
specparam TPRE = 0; // Preset time
specparam TPRE_MIN_PW = 0; // Minimum pulse width of preset
specparam TCLK_MIN_PW = 0; // Minimum pulse width of clock
specparam TCE_MIN_PW = 0; // Minimum pulse width of clock enable
specparam TCLKL = 0; // Minimum clock low time
specparam TCLKH = 0; // Minimum clock high time
$setup (datain, posedge clk, 0, viol_notifier);
$hold (posedge clk, datain, 0, viol_notifier);
$setup (sload, posedge clk, 0, viol_notifier );
$hold (posedge clk, sload, 0, viol_notifier );
(posedge aclr => (dataout +: 'b0)) = (0,0);
(posedge clk => (dataout +: dataout_tmp)) = (0,0);
endspecify
initial
begin
dataout_tmp = 0;
prev_clk_val = 1'b0;
end
always @(clk or posedge aclr or bypass_register or datain)
begin
if(bypass_register == 1'b1)
dataout_tmp <= datain;
else
begin
if (aclr == 1'b1)
dataout_tmp <= 0;
else if (prev_clk_val == 1'b0 && clk == 1'b1)
begin
if(sload == 1'b1)
dataout_tmp <= datain;
else
dataout_tmp <= dataout_tmp;
end
end
prev_clk_val = clk;
end
assign dataout = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_mac_multiplier //
// Description: HARDCOPYIII MAC signed multiplier //
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_mac_multiplier (
dataa,
datab,
signa,
signb,
dataout
);
//PARAMETER
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
//OUTPUT PORTS
output [dataout_width -1 :0] dataout;
//INTERNAL SIGNALS
wire [dataout_width -1:0] product; //product of dataa and datab
wire [dataout_width -1:0] abs_product; //|product| of dataa and datab
wire [dataa_width-1:0] abs_a; //absolute value of dataa
wire [datab_width-1:0] abs_b; //absolute value of dadab
wire product_sign; // product sign bit
wire dataa_sign; //dataa sign bit
wire datab_sign; //datab sign bit
//TIMING SPECIFICATION
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
//Outputassignment
assign dataa_sign = dataa[dataa_width-1] && signa;
assign datab_sign = datab[datab_width-1] && signb;
assign product_sign = dataa_sign ^ datab_sign;
assign abs_a = dataa_sign ? (~dataa + 1'b1) : dataa;
assign abs_b = datab_sign ? (~datab + 1'b1) : datab;
assign abs_product = abs_a * abs_b;
assign product = product_sign ? (~abs_product + 1) : abs_product;
assign dataout = product;
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_mac_mult_atom //
// Description: Simulation model for hardcopyiii mac mult atom. //
// This model instantiates the following components. //
// 1.hardcopyiii_mac_register. //
// 2.hardcopyiii_mac_multiplier. //
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_mac_mult(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
scanouta,
devclrn,
devpor
);
//PARAMETERS
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter scanouta_clock = "none";
parameter dataa_clear = "none";
parameter datab_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter scanouta_clear = "none";
parameter signa_internally_grounded = "false";
parameter signb_internally_grounded = "false";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
parameter lpm_type = "hardcopyiii_mac_mult";
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
//OUTPUT PORTS
output [dataout_width-1:0] dataout;
output [dataa_width-1:0] scanouta;
tri1 devclrn;
tri1 devpor;
//Internal signals to instantiate the dataa input register unit
wire [3:0] dataa_clk_value;
wire [3:0] dataa_aclr_value;
wire dataa_clk;
wire dataa_aclr;
wire dataa_sload;
wire dataa_bypass_register;
wire [dataa_width-1:0] dataa_in_reg;
//Internal signals to instantiate the datab input register unit
wire [3:0] datab_clk_value;
wire [3:0] datab_aclr_value;
wire datab_clk;
wire datab_aclr;
wire datab_sload;
wire datab_bypass_register;
wire [datab_width-1:0] datab_in_reg;
//Internal signals to instantiate the signa input register unit
wire [3:0] signa_clk_value;
wire [3:0] signa_aclr_value;
wire signa_clk;
wire signa_aclr;
wire signa_sload;
wire signa_bypass_register;
wire signa_in_reg;
//Internal signbls to instantiate the signb input register unit
wire [3:0] signb_clk_value;
wire [3:0] signb_aclr_value;
wire signb_clk;
wire signb_aclr;
wire signb_sload;
wire signb_bypass_register;
wire signb_in_reg;
//Internal scanoutals to instantiate the scanouta input register unit
wire [3:0] scanouta_clk_value;
wire [3:0] scanouta_aclr_value;
wire scanouta_clk;
wire scanouta_aclr;
wire scanouta_sload;
wire scanouta_bypass_register;
wire [dataa_width -1 :0] scanouta_in_reg;
//Internal Signals to instantiate the mac multiplier
wire signa_mult;
wire signb_mult;
//Instantiate the dataa input Register
hardcopyiii_mac_register dataa_input_register (
.datain(dataa),
.clk(dataa_clk),
.aclr(dataa_aclr),
.sload(dataa_sload),
.bypass_register(dataa_bypass_register),
.dataout(dataa_in_reg)
);
defparam dataa_input_register.data_width = dataa_width;
//decode the clk and aclr values
assign dataa_clk_value = (dataa_clock == "0") ? 4'b0000 :
(dataa_clock == "1") ? 4'b0001 :
(dataa_clock == "2") ? 4'b0010 :
(dataa_clock == "3") ? 4'b0011 : 4'b0000;
assign dataa_aclr_value =(dataa_clear == "0") ? 4'b0000 :
(dataa_clear == "1") ? 4'b0001 :
(dataa_clear == "2") ? 4'b0010 :
(dataa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign dataa_clk = clk[dataa_clk_value] ? 1'b1 : 1'b0;
assign dataa_aclr = aclr[dataa_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign dataa_sload = ena[dataa_clk_value] ? 1'b1 : 1'b0;
assign dataa_bypass_register = (dataa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the datab input Register
hardcopyiii_mac_register datab_input_register (
.datain(datab),
.clk(datab_clk),
.aclr(datab_aclr),
.sload(datab_sload),
.bypass_register(datab_bypass_register),
.dataout(datab_in_reg)
);
defparam datab_input_register.data_width = datab_width;
//decode the clk and aclr values
assign datab_clk_value = (datab_clock == "0") ? 4'b0000 :
(datab_clock == "1") ? 4'b0001 :
(datab_clock == "2") ? 4'b0010 :
(datab_clock == "3") ? 4'b0011 : 4'b0000;
assign datab_aclr_value = (datab_clear == "0") ? 4'b0000 :
(datab_clear == "1") ? 4'b0001 :
(datab_clear == "2") ? 4'b0010 :
(datab_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign datab_clk = clk[datab_clk_value] ? 1'b1 : 1'b0;
assign datab_aclr = aclr[datab_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign datab_sload = ena[datab_clk_value] ? 1'b1 : 1'b0;
assign datab_bypass_register = (datab_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa input Register
hardcopyiii_mac_register signa_input_register (
.datain(signa),
.clk(signa_clk),
.aclr(signa_aclr),
.sload(signa_sload),
.bypass_register(signa_bypass_register),
.dataout(signa_in_reg)
);
defparam signa_input_register.data_width = 1;
//decode the clk and aclr values
assign signa_clk_value =(signa_clock == "0") ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclr_value = (signa_clear == "0") ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk = clk[signa_clk_value] ? 1'b1 : 1'b0;
assign signa_aclr = aclr[signa_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload = ena[signa_clk_value] ? 1'b1 : 1'b0;
assign signa_bypass_register = (signa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb input Register
hardcopyiii_mac_register signb_input_register (
.datain(signb),
.clk(signb_clk),
.aclr(signb_aclr),
.sload(signb_sload),
.bypass_register(signb_bypass_register),
.dataout(signb_in_reg)
);
defparam signb_input_register.data_width = 1;
//decode the clk and aclr values
assign signb_clk_value =(signb_clock == "0") ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclr_value = (signb_clear == "0") ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk = clk[signb_clk_value] ? 1'b1 : 1'b0;
assign signb_aclr = aclr[signb_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload = ena[signb_clk_value] ? 1'b1 : 1'b0;
assign signb_bypass_register = (signb_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the scanouta input Register
hardcopyiii_mac_register scanouta_input_register (
.datain(dataa_in_reg),
.clk(scanouta_clk),
.aclr(scanouta_aclr),
.sload(scanouta_sload),
.bypass_register(scanouta_bypass_register),
.dataout(scanouta)
);
defparam scanouta_input_register.data_width = dataa_width;
//decode the clk and aclr values
assign scanouta_clk_value =(scanouta_clock == "0") ? 4'b0000 :
(scanouta_clock == "1") ? 4'b0001 :
(scanouta_clock == "2") ? 4'b0010 :
(scanouta_clock == "3") ? 4'b0011 : 4'b0000;
assign scanouta_aclr_value = (scanouta_clear == "0") ? 4'b0000 :
(scanouta_clear == "1") ? 4'b0001 :
(scanouta_clear == "2") ? 4'b0010 :
(scanouta_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign scanouta_clk = clk[scanouta_clk_value] ? 1'b1 : 1'b0;
assign scanouta_aclr = aclr[scanouta_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign scanouta_sload = ena[scanouta_clk_value] ? 1'b1 : 1'b0;
assign scanouta_bypass_register = (scanouta_clock == "none") ? 1'b1 : 1'b0;
//Instantiate mac_multiplier block
hardcopyiii_mac_multiplier mac_multiplier (
.dataa(dataa_in_reg),
.datab(datab_in_reg),
.signa(signa_mult),
.signb(signb_mult),
.dataout(dataout)
);
defparam mac_multiplier.dataa_width = dataa_width;
defparam mac_multiplier.datab_width = datab_width;
assign signa_mult = (signa_internally_grounded == "true")? 1'b0 : signa_in_reg;
assign signb_mult = (signb_internally_grounded == "true")? 1'b0 : signb_in_reg;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_fsa_isse //
// Description: HARDCOPYIII first stage adder input selection and sign extension block. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_fsa_isse(
dataa,
datab,
datac,
datad,
chainin,
signa,
signb,
dataa_out,
datab_out,
datac_out,
datad_out,
chainin_out,
operation
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter chainin_width = 44;
parameter operation_mode = "output_only";
parameter multa_signa_internally_grounded = "false";
parameter multa_signb_internally_grounded = "false";
parameter multb_signa_internally_grounded = "false";
parameter multb_signb_internally_grounded = "false";
parameter multc_signa_internally_grounded = "false";
parameter multc_signb_internally_grounded = "false";
parameter multd_signa_internally_grounded = "false";
parameter multd_signb_internally_grounded = "false";
input [dataa_width -1:0] dataa;
input [datab_width -1:0] datab;
input [datac_width -1:0] datac;
input [datad_width -1:0] datad;
input [chainin_width -1 :0] chainin;
input signa;
input signb;
output [71:0] dataa_out;
output [71:0] datab_out;
output [71:0] datac_out;
output [71:0] datad_out;
output [71:0] chainin_out;
output [3:0] operation;
wire sign;
wire [71:0] datab_out_fun;
wire [71:0] datac_out_fun;
wire [71:0] datad_out_fun;
wire [71:0] datab_out_tim;
wire [71:0] datac_out_tim;
wire [71:0] datad_out_tim;
assign sign = signa | signb;
//Decode the operation value depending on the mode of operation
assign operation = (operation_mode == "output_only") ? 4'b0000 :
(operation_mode == "one_level_adder") ? 4'b0001 :
(operation_mode == "loopback") ? 4'b0010 :
(operation_mode == "accumulator") ? 4'b0011 :
(operation_mode == "accumulator_chain_out") ? 4'b0100 :
(operation_mode == "two_level_adder") ? 4'b0101 :
(operation_mode == "two_level_adder_chain_out") ? 4'b0110 :
(operation_mode == "36_bit_multiply") ? 4'b0111 :
(operation_mode == "shift") ? 4'b1000 :
(operation_mode == "double") ? 4'b1001 : 4'b0000;
wire active_signb, active_signc, active_signd;
wire read_new_param;
assign read_new_param = ( multa_signa_internally_grounded == "false" && multa_signb_internally_grounded == "false"
&& multb_signa_internally_grounded == "false" && multb_signb_internally_grounded == "false"
&& multc_signa_internally_grounded == "false" && multc_signb_internally_grounded == "false"
&& multd_signa_internally_grounded == "false" && multd_signb_internally_grounded == "false") ? 1'b0 : 1'b1;
assign active_signb = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multb_signb_internally_grounded == "false" && multb_signa_internally_grounded == "true") ? signb
:((multb_signb_internally_grounded == "true" && multb_signa_internally_grounded == "false" )? signa
:((multb_signb_internally_grounded == "false" && multb_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign active_signc = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multc_signb_internally_grounded == "false" && multc_signa_internally_grounded == "true") ? signb
:((multc_signb_internally_grounded == "true" && multc_signa_internally_grounded == "false" )? signa
:((multc_signb_internally_grounded == "false" && multc_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign active_signd = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multd_signb_internally_grounded == "false" && multd_signa_internally_grounded == "true") ? signb
:((multd_signb_internally_grounded == "true" && multd_signa_internally_grounded == "false" )? signa
:((multd_signb_internally_grounded == "false" && multd_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign dataa_out = (dataa[dataa_width-1]&& sign)
?{{(72-dataa_width){1'b1}},dataa[dataa_width -1 : 0]}
:{{(72-dataa_width){1'b0}},dataa[dataa_width -1 : 0]} ;
assign datab_out_tim = (datab[datab_width-1]&& active_signb)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]} ;
assign datac_out_tim = (datac[datac_width-1]&& active_signc)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]} ;
assign datad_out_tim = (datad[datad_width-1]&& active_signd)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]} ;
assign datab_out_fun = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?((datab[datab_width-1]&& signb)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]})
:(operation_mode == "double")
?((datab[datab_width-1]&& signa)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]})
:((datab[datab_width-1]&& sign)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]}) ;
assign datac_out_fun =((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?((datac[datac_width-1]&& signa)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]} )
:((datac[datac_width-1]&& sign)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]}) ;
assign datad_out_fun = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]}
:(operation_mode == "double")
?((datad[datad_width-1]&& signa)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]} )
:((datad[datad_width-1]&& sign)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]}) ;
assign datab_out = (read_new_param == 1'b1) ? datab_out_tim : datab_out_fun;
assign datac_out = (read_new_param == 1'b1) ? datac_out_tim : datac_out_fun;
assign datad_out = (read_new_param == 1'b1) ? datad_out_tim : datad_out_fun;
assign chainin_out = (chainin[chainin_width-1])
?{{(72-chainin_width){1'b1}},chainin[chainin_width -1 : 0]}
:{{(72-chainin_width){1'b0}},chainin[chainin_width -1 : 0]} ;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_first_stage_add_sub //
// Description: HARDCOPYIII First Stage Adder Subtractor Unit //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_first_stage_add_sub(
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output [71: 0] dataout;
//INTERNAL SIGNALS
reg[71 :0] dataout_tmp;
reg[71:0] abs_b;
reg[71:0] abs_a;
reg sign_a;
reg sign_b;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
always @(dataa or datab or sign or operation)
begin
if((operation == 4'b0111) ||(operation == 4'b1000)|| (operation == 4'b1001)) //36 bit multiply, shift and add
begin
dataout_tmp = {dataa[53:36],dataa[35:0],18'b0} + datab;
end
else
begin
sign_a = (sign && dataa[dataa_width -1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if (fsa_mode == "add")
dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ?-abs_b : abs_b);
else
dataout_tmp = (sign_a ? -abs_a : abs_a) - (sign_b ?-abs_b : abs_b);
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_second_stage_add_accum //
// Description: HARDCOPYIII Second stage Adder and Accumulator/Decimator Unit //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_second_stage_add_accum(
dataa,
datab,
accumin,
sign,
operation,
dataout,
overflow
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter accum_width = dataa_width + 8;
parameter ssa_mode = "add";
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
input [71 : 0] accumin;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output overflow;
output [71 :0] dataout;
//INTERNAL SIGNALS
reg[71 :0] dataout_tmp;
reg [71:0] dataa_tmp;
reg [71:0] datab_tmp;
reg[71:0] accum_tmp;
reg sign_a;
reg sign_b;
reg sign_accum;
reg sign_out;
reg overflow_tmp;
reg [71 :0] abs_a;
reg [71 :0] abs_b;
reg [71 :0] abs_accum;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
(dataa *> overflow) = (0, 0);
(datab *> overflow) = (0, 0);
(sign *> overflow) = (0, 0);
if(operation == 4'b0011 || operation == 4'b0100 )
(accumin *> dataout) = (0, 0);
if(operation == 4'b0011 || operation == 4'b0100 )
(accumin *> overflow) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
assign overflow = overflow_tmp;
always@(dataa or datab or sign or accumin or operation)
begin
sign_accum = (sign && accumin[accum_width -1]);
abs_accum = (sign_accum) ? (~accumin + 1'b1) : accumin;
sign_a = (sign && dataa[dataa_width-1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if(operation == 4'b0011 || operation == 4'b0100 )//Accumultor or Accumulator chainout
begin
if (ssa_mode == "add")
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) + (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) + (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
else
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) - (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) - (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
if(sign)
overflow_tmp = dataout_tmp[accum_width] ^ dataout_tmp[accum_width -1];
else
begin
if(ssa_mode == "add")
overflow_tmp = dataout_tmp[accum_width];
else
overflow_tmp = 1'bX;
end
end
else if( operation == 4'b0101 || operation == 4'b0110)// two level adder or two level with chainout
begin
dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ?-abs_b : abs_b);
overflow_tmp = 'b0;
end
else if(( operation == 4'b0111) ||(operation == 4'b1000)) //36 bit multiply; shift and add
begin
dataout_tmp[71:0] = {dataa[53:0],18'b0} + datab;
overflow_tmp = 'b0;
end
else if(( operation == 4'b1001) ) //double mode
begin
dataout_tmp[71:0] = dataa + datab;
overflow_tmp = 'b0;
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_round_block //
// Description: HARDCOPYIII round block //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_round_block(
datain,
round,
datain_width,
dataout
);
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
parameter round_width = 15;
input [71 :0 ] datain;
input round;
input [7:0] datain_width;
output [71 : 0] dataout;
reg sign;
reg [71 :0] result_tmp;
reg [71:0] dataout_tmp;
reg [71 :0 ] dataout_value;
integer i,j;
initial
begin
result_tmp = {(72){1'b0}};
end
assign dataout = dataout_value;
always@(datain or round)
begin
if(round == 1'b0)
dataout_value = datain;
else
begin
j = 0;
sign = 0;
dataout_value = datain;
if(datain_width > round_width)
begin
for(i = datain_width - round_width ; i < datain_width ; i = i+1)
begin
result_tmp[j]= datain[i];
j = j +1;
end
for (i = 0; i < datain_width - round_width -1 ; i = i +1)
begin
sign = sign | datain[i];
dataout_value[i] = 1'bX;
end
dataout_value[datain_width - round_width -1] = 1'bX;
//rounding logic
if(datain[datain_width - round_width -1 ] == 1'b0)// fractional < 0.5
begin
dataout_tmp = result_tmp;
end
else if((datain[datain_width - round_width -1 ] == 1'b1) && (sign == 1'b1))//fractional > 0.5
begin
dataout_tmp = result_tmp + 1'b1;
end
else
begin
if(round_mode == "nearest_even")//unbiased rounding
begin
if(result_tmp % 2) //check for odd integer
dataout_tmp = result_tmp + 1'b1;
else
dataout_tmp = result_tmp;
end
else //biased rounding
begin
dataout_tmp = result_tmp + 1'b1;
end
end
j = 0;
for(i = datain_width - round_width ; i < datain_width ; i = i+1)
begin
dataout_value[i]= dataout_tmp[j];
j = j+1;
end
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_saturation_block //
// Description: HARDCOPYIII saturation block //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_saturate_block(
datain,
saturate,
round,
signa,
signb,
datain_width,
dataout,
saturation_overflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter round_width = 15;
parameter saturate_width = 1;
parameter accum_width = dataa_width + 8;
parameter saturate_mode = " asymmetric";
parameter operation_mode = "output_only";
input [71:0] datain;
input saturate;
input round;
input signa;
input signb;
input [7:0] datain_width;
output[71 :0 ] dataout;
output saturation_overflow;
//Internal signals
reg [71 : 0] dataout_tmp;
reg saturation_overflow_tmp;
wire msb;
wire sign;
integer i;
reg [71 :0] max;
reg [71 :0] min;
reg sign_tmp;
reg data_tmp;
initial
begin
max = {(72){1'b0}};
min = {(72){1'b1}};
sign_tmp = 1'b1;
data_tmp = 1'b0;
end
assign sign = signa | signb;
assign msb = ((operation_mode == "accumulator")
||(operation_mode == "accumulator_chain_out")
||(operation_mode == "two_level_adder_chain_out")) ? datain[accum_width] :
(operation_mode == "two_level_adder") ? datain[dataa_width + 1] :
((operation_mode == "one_level_adder")||(operation_mode == "loopback")) ? datain[dataa_width] : datain[dataa_width -1];
assign dataout = dataout_tmp;
assign saturation_overflow = saturation_overflow_tmp;
always @(datain or datain_width or sign or round or msb or saturate)
begin
if(saturate == 1'b0)
begin
dataout_tmp = datain;
saturation_overflow_tmp = 1'b0;
end
else
begin
saturation_overflow_tmp = 1'b0;
data_tmp = 1'b0;
sign_tmp = 1'b1;
// "X" when round is asserted.
if((round == 1'b1))
begin
for(i = 0; i < datain_width - round_width; i = i +1)
begin
min[i] = 1'bX;
max[i] = 1'bX;
end
end
// "X" for symmetric saturation, only if data is negative
if(( saturate_mode == "symmetric"))
begin
for(i = 0; i < datain_width - round_width; i = i +1)
begin
if(round == 1'b1)
begin
max[i] = 1'bX;
min[i] = 1'bX;
end
else
begin
max[i] = 1'b1;
min[i] = 1'b0;
end
end
for( i= datain_width - round_width; i < datain_width - saturate_width; i = i+1)
begin
data_tmp = data_tmp | datain[i];
max[i] = 1'b1;
min[i] = 1'b0;
end
if (round == 1'b1)
min[datain_width - round_width] = 1'b1;
else
min[0] = 1'b1;
end
if(( saturate_mode == "asymmetric"))
begin
for( i= 0; i < datain_width -saturate_width; i = i+1)
begin
max[i] = 1'b1;
min[i] = 1'b0;
end
end
//check for overflow
if((saturate_width ==1))
begin
if(msb != datain[datain_width-1])
saturation_overflow_tmp = 1'b1;
else
sign_tmp = sign_tmp & datain[datain_width-1];
end
else
begin
for (i = datain_width - saturate_width; i < datain_width ; i = i + 1)
begin
sign_tmp = sign_tmp & datain[i];
if(datain[datain_width -1 ] != datain[i])
saturation_overflow_tmp = 1'b1;
end
end
// Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp == 1'b1) && (data_tmp == 1'b0) && (saturate_mode == "symmetric"))
saturation_overflow_tmp = 1'b1;
if(saturation_overflow_tmp)
begin
if((operation_mode == "output_only") || (operation_mode == "accumulator_chain_out") || (operation_mode == "two_level_adder_chain_out"))
begin
if(msb)
dataout_tmp = min;
else
dataout_tmp = max;
end
else
begin
if (sign)
begin
if(msb)
dataout_tmp = min;
else
dataout_tmp = max;
end
else
dataout_tmp = 72'bX;
end
end
else
dataout_tmp = datain;
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_round_saturate_block //
// Description: HARDCOPYIII round and saturation Unit. //
// This unit instantiated the following components. //
// 1.hardcopyiii_round_block. //
// 2.hardcopyiii_saturate_block. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_round_saturate_block(
datain,
round,
saturate,
signa,
signb,
datain_width,
dataout,
saturationoverflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter saturate_width = 15;
parameter round_width = 15;
parameter saturate_mode = " asymmetric";
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
input [71:0] datain;
input round;
input saturate;
input signa;
input signb;
input [7:0] datain_width;
output[71:0] dataout;
output saturationoverflow;
wire [71:0] dataout_round;
wire [7:0] datain_width;
wire [7:0] fraction_width;
wire[7:0] datasize;
specify
(datain *> dataout) = (0, 0);
(round *> dataout) = (0, 0);
(saturate *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
(datain *> saturationoverflow) = (0, 0);
(round *> saturationoverflow) = (0, 0);
(saturate *> saturationoverflow) = (0, 0);
(signa *> saturationoverflow) = (0, 0);
(signb *> saturationoverflow) = (0, 0);
endspecify
hardcopyiii_round_block round_unit (
.datain(datain),
.round(round),
.datain_width(datain_width),
.dataout(dataout_round)
);
defparam round_unit.round_mode = round_mode;
defparam round_unit.operation_mode = operation_mode;
defparam round_unit.round_width = round_width;
hardcopyiii_saturate_block saturate_unit(
.datain(dataout_round),
.saturate(saturate),
.round(round),
.signa(signa),
.signb(signb),
.datain_width(datain_width),
.dataout(dataout),
.saturation_overflow(saturationoverflow)
);
defparam saturate_unit.dataa_width = dataa_width;
defparam saturate_unit.datab_width = datab_width;
defparam saturate_unit.round_width = round_width;
defparam saturate_unit.saturate_width = saturate_width;
defparam saturate_unit.saturate_mode = saturate_mode;
defparam saturate_unit.operation_mode = operation_mode;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_rotate_shift_block //
// Description: HARDCOPYIII rotate and shift Unit. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_rotate_shift_block(
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire sign;
output [71:0] dataout;
reg[71:0] dataout_tmp;
specify
(datain *> dataout) = (0, 0);
(rotate *> dataout) = (0, 0);
(shiftright*> dataout) = (0, 0);
endspecify
assign sign = signa ^ signb;
assign dataout = dataout_tmp;
always@(datain or rotate or shiftright)
begin
dataout_tmp = datain;
if((rotate == 0) && (shiftright == 0))
dataout_tmp[39:8] = datain[39:8];
else if((rotate == 0) && (shiftright == 1))
dataout_tmp[39:8]= datain[71:40];
else if ((rotate == 1) && (shiftright == 0))
dataout_tmp[39:8] = datain[71:40] | datain[39:8];
else
dataout_tmp = datain;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_carry_chain_adder //
// Description: HARDCOPYIII carry chain adder Unit. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_carry_chain_adder(
dataa,
datab,
dataout
);
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
// OUTPUT PORTS
output [71 :0] dataout;
reg[71:0] dataout_tmp;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
endspecify
assign dataout = dataout_tmp;
initial
begin
dataout_tmp = 72'b0;
end
always@(dataa or datab)
begin
dataout_tmp = {dataa[43],dataa[43:0]} + {datab[43],datab[43:0]};
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Module Name: hardcopyiii_mac_out_atom //
// Description: Simulation model for hardcopyiii mac out atom //
// This model instantiates the following components //
// 1.hardcopyiii_mac_bit_register //
// 2.hardcopyiii_mac_register //
// 3.hardcopyiii_fsa_isse //
// 4.hardcopyiii_first_stage_add_sub //
// 5.hardcopyiii_second_stage_add_accum //
// 6.hardcopyiii_round_saturate_block //
// 7.hardcopyiii_rotate_shift_block //
// 8.hardcopyiii_carry_chain_adder //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_mac_out(
dataa,
datab,
datac,
datad,
signa,
signb,
chainin,
round,
saturate,
zeroacc,
roundchainout,
saturatechainout,
zerochainout,
zeroloopback,
rotate,
shiftright,
clk,
ena,
aclr,
loopbackout,
dataout,
overflow,
dftout,
saturatechainoutoverflow,
devpor,
devclrn
);
//Parameter declaration
parameter operation_mode = "output_only";
parameter dataa_width = 1;
parameter datab_width = 1;
parameter datac_width = 1;
parameter datad_width = 1;
parameter chainin_width = 1;
parameter round_width = 15;
parameter round_chain_out_width = 15;
parameter saturate_width = 15;
parameter saturate_chain_out_width = 15;
parameter first_adder0_clock = "none";
parameter first_adder0_clear = "none";
parameter first_adder1_clock = "none";
parameter first_adder1_clear = "none";
parameter second_adder_clock = "none";
parameter second_adder_clear = "none";
parameter output_clock = "none";
parameter output_clear = "none";
parameter signa_clock = "none";
parameter signa_clear = "none";
parameter signb_clock = "none";
parameter signb_clear = "none";
parameter round_clock = "none";
parameter round_clear = "none";
parameter roundchainout_clock = "none";
parameter roundchainout_clear = "none";
parameter saturate_clock = "none";
parameter saturate_clear = "none";
parameter saturatechainout_clock = "none";
parameter saturatechainout_clear = "none";
parameter zeroacc_clock = "none";
parameter zeroacc_clear = "none";
parameter zeroloopback_clock = "none";
parameter zeroloopback_clear = "none";
parameter rotate_clock = "none";
parameter rotate_clear = "none";
parameter shiftright_clock = "none";
parameter shiftright_clear = "none";
parameter signa_pipeline_clock = "none";
parameter signa_pipeline_clear = "none";
parameter signb_pipeline_clock = "none";
parameter signb_pipeline_clear = "none";
parameter round_pipeline_clock = "none";
parameter round_pipeline_clear = "none";
parameter roundchainout_pipeline_clock = "none";
parameter roundchainout_pipeline_clear = "none";
parameter saturate_pipeline_clock = "none";
parameter saturate_pipeline_clear = "none";
parameter saturatechainout_pipeline_clock = "none";
parameter saturatechainout_pipeline_clear = "none";
parameter zeroacc_pipeline_clock = "none";
parameter zeroacc_pipeline_clear = "none";
parameter zeroloopback_pipeline_clock = "none";
parameter zeroloopback_pipeline_clear = "none";
parameter rotate_pipeline_clock = "none";
parameter rotate_pipeline_clear = "none";
parameter shiftright_pipeline_clock = "none";
parameter shiftright_pipeline_clear = "none";
parameter roundchainout_output_clock = "none";
parameter roundchainout_output_clear = "none";
parameter saturatechainout_output_clock = "none";
parameter saturatechainout_output_clear = "none";
parameter zerochainout_output_clock = "none";
parameter zerochainout_output_clear = "none";
parameter zeroloopback_output_clock = "none";
parameter zeroloopback_output_clear = "none";
parameter rotate_output_clock = "none";
parameter rotate_output_clear = "none";
parameter shiftright_output_clock = "none";
parameter shiftright_output_clear = "none";
parameter first_adder0_mode = "add";
parameter first_adder1_mode = "add";
parameter acc_adder_operation = "add";
parameter round_mode = "nearest_integer";
parameter round_chain_out_mode = "nearest_integer";
parameter saturate_mode = "asymmetric";
parameter saturate_chain_out_mode = "asymmetric";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter multa_signa_internally_grounded = "false";
parameter multa_signb_internally_grounded = "false";
parameter multb_signa_internally_grounded = "false";
parameter multb_signb_internally_grounded = "false";
parameter multc_signa_internally_grounded = "false";
parameter multc_signb_internally_grounded = "false";
parameter multd_signa_internally_grounded = "false";
parameter multd_signb_internally_grounded = "false";
// SIMULATION_ONLY_PARAMETERS_END
parameter lpm_type = "hardcopyiii_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = 72;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width -1 :0] dataa;
input [datab_width -1 :0] datab;
input [datac_width -1 :0] datac;
input [datad_width -1 :0] datad;
input signa;
input signb;
input [chainin_width -1 : 0] chainin;
input round;
input saturate;
input roundchainout;
input saturatechainout;
input zeroacc;
input zerochainout;
input zeroloopback;
input rotate;
input shiftright;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devpor;
input devclrn;
output [17:0] loopbackout;
output [71:0] dataout;
output overflow;
output saturatechainoutoverflow;
output dftout;
tri1 devclrn;
tri1 devpor;
//signals for zeroloopback input register
wire [3:0] zeroloopback_clkval_ir;
wire [3:0] zeroloopback_aclrval_ir;
wire zeroloopback_clk_ir;
wire zeroloopback_aclr_ir;
wire zeroloopback_sload_ir;
wire zeroloopback_bypass_register_ir;
wire zeroloopback_in_reg;
//signals for zeroacc input register
wire [3:0] zeroacc_clkval_ir;
wire [3:0] zeroacc_aclrval_ir;
wire zeroacc_clk_ir;
wire zeroacc_aclr_ir;
wire zeroacc_sload_ir;
wire zeroacc_bypass_register_ir;
wire zeroacc_in_reg;
//Signals for signa input register
wire [3:0] signa_clkval_ir;
wire [3:0] signa_aclrval_ir;
wire signa_clk_ir;
wire signa_aclr_ir;
wire signa_sload_ir;
wire signa_bypass_register_ir;
wire signa_in_reg;
//signals for signb input register
wire [3:0] signb_clkval_ir;
wire [3:0] signb_aclrval_ir;
wire signb_clk_ir;
wire signb_aclr_ir;
wire signb_sload_ir;
wire signb_bypass_register_ir;
wire signb_in_reg;
//signals for rotate input register
wire [3:0] rotate_clkval_ir;
wire [3:0] rotate_aclrval_ir;
wire rotate_clk_ir;
wire rotate_aclr_ir;
wire rotate_sload_ir;
wire rotate_bypass_register_ir;
wire rotate_in_reg;
//signals for shiftright input register
wire [3:0] shiftright_clkval_ir;
wire [3:0] shiftright_aclrval_ir;
wire shiftright_clk_ir;
wire shiftright_aclr_ir;
wire shiftright_sload_ir;
wire shiftright_bypass_register_ir;
wire shiftright_in_reg;
//signals for round input register
wire [3:0] round_clkval_ir;
wire [3:0] round_aclrval_ir;
wire round_clk_ir;
wire round_aclr_ir;
wire round_sload_ir;
wire round_bypass_register_ir;
wire round_in_reg;
//signals for saturate input register
wire [3:0] saturate_clkval_ir;
wire [3:0] saturate_aclrval_ir;
wire saturate_clk_ir;
wire saturate_aclr_ir;
wire saturate_sload_ir;
wire saturate_bypass_register_ir;
wire saturate_in_reg;
//signals for roundchainout input register
wire [3:0] roundchainout_clkval_ir;
wire [3:0] roundchainout_aclrval_ir;
wire roundchainout_clk_ir;
wire roundchainout_aclr_ir;
wire roundchainout_sload_ir;
wire roundchainout_bypass_register_ir;
wire roundchainout_in_reg;
//signals for saturatechainout input register
wire [3:0] saturatechainout_clkval_ir;
wire [3:0] saturatechainout_aclrval_ir;
wire saturatechainout_clk_ir;
wire saturatechainout_aclr_ir;
wire saturatechainout_sload_ir;
wire saturatechainout_bypass_register_ir;
wire saturatechainout_in_reg;
//signals for fsa_input_interface
wire [71:0] dataa_fsa_in;
wire [71:0] datab_fsa_in;
wire [71:0] datac_fsa_in;
wire [71:0] datad_fsa_in;
wire [71:0] chainin_coa_in;
wire sign;
wire [3:0]operation;
//Signals for First Stage Adder units
wire [71:0] dataout_fsa0;
wire [71:0] fsa_pip_datain1;
wire [71:0] dataout_fsa1;
wire overflow_fsa0;
wire overflow_fsa1;
//signals for zeroloopback pipeline register
wire [3:0] zeroloopback_clkval_pip;
wire [3:0] zeroloopback_aclrval_pip;
wire zeroloopback_clk_pip;
wire zeroloopback_aclr_pip;
wire zeroloopback_sload_pip;
wire zeroloopback_bypass_register_pip;
wire zeroloopback_pip_reg;
//signals for zeroacc pipeline register
wire [3:0] zeroacc_clkval_pip;
wire [3:0] zeroacc_aclrval_pip;
wire zeroacc_clk_pip;
wire zeroacc_aclr_pip;
wire zeroacc_sload_pip;
wire zeroacc_bypass_register_pip;
wire zeroacc_pip_reg;
//Signals for signa pipeline register
wire [3:0] signa_clkval_pip;
wire [3:0] signa_aclrval_pip;
wire signa_clk_pip;
wire signa_aclr_pip;
wire signa_sload_pip;
wire signa_bypass_register_pip;
wire signa_pip_reg;
//signals for signb pipeline register
wire [3:0] signb_clkval_pip;
wire [3:0] signb_aclrval_pip;
wire signb_clk_pip;
wire signb_aclr_pip;
wire signb_sload_pip;
wire signb_bypass_register_pip;
wire signb_pip_reg;
//signals for rotate pipeline register
wire [3:0] rotate_clkval_pip;
wire [3:0] rotate_aclrval_pip;
wire rotate_clk_pip;
wire rotate_aclr_pip;
wire rotate_sload_pip;
wire rotate_bypass_register_pip;
wire rotate_pip_reg;
//signals for shiftright pipeline register
wire [3:0] shiftright_clkval_pip;
wire [3:0] shiftright_aclrval_pip;
wire shiftright_clk_pip;
wire shiftright_aclr_pip;
wire shiftright_sload_pip;
wire shiftright_bypass_register_pip;
wire shiftright_pip_reg;
//signals for round pipeline register
wire [3:0] round_clkval_pip;
wire [3:0] round_aclrval_pip;
wire round_clk_pip;
wire round_aclr_pip;
wire round_sload_pip;
wire round_bypass_register_pip;
wire round_pip_reg;
//signals for saturate pipeline register
wire [3:0] saturate_clkval_pip;
wire [3:0] saturate_aclrval_pip;
wire saturate_clk_pip;
wire saturate_aclr_pip;
wire saturate_sload_pip;
wire saturate_bypass_register_pip;
wire saturate_pip_reg;
//signals for roundchainout pipeline register
wire [3:0] roundchainout_clkval_pip;
wire [3:0] roundchainout_aclrval_pip;
wire roundchainout_clk_pip;
wire roundchainout_aclr_pip;
wire roundchainout_sload_pip;
wire roundchainout_bypass_register_pip;
wire roundchainout_pip_reg;
//signals for saturatechainout pipeline register
wire [3:0] saturatechainout_clkval_pip;
wire [3:0] saturatechainout_aclrval_pip;
wire saturatechainout_clk_pip;
wire saturatechainout_aclr_pip;
wire saturatechainout_sload_pip;
wire saturatechainout_bypass_register_pip;
wire saturatechainout_pip_reg;
//signals for fsa0 pipeline register
wire [3:0] fsa0_clkval_pip;
wire [3:0] fsa0_aclrval_pip;
wire fsa0_clk_pip;
wire fsa0_aclr_pip;
wire fsa0_sload_pip;
wire fsa0_bypass_register_pip;
wire[71:0] fsa0_pip_reg;
//signals for fsa1 pipeline register
wire [3:0] fsa1_clkval_pip;
wire [3:0] fsa1_aclrval_pip;
wire fsa1_clk_pip;
wire fsa1_aclr_pip;
wire fsa1_sload_pip;
wire fsa1_bypass_register_pip;
wire[71:0] fsa1_pip_reg;
//Signals for second stage adder
wire [71:0] ssa_accum_in;
wire ssa_sign;
wire [71:0] ssa_dataout;
wire ssa_overflow;
//Signals for RS block
wire[71:0] rs_datain;
wire [71:0] rs_dataout;
reg [71:0] rs_dataout_of;
wire [71:0] rs_dataout_tmp;
wire rs_saturation_overflow;
wire [7:0] ssa_datain_width;
wire [7:0] ssa_datain_width_tmp;
wire [3:0] ssa_round_width;
wire [7:0] ssa_fraction_width;
//signals for zeroloopback output register
wire [3:0] zeroloopback_clkval_or;
wire [3:0] zeroloopback_aclrval_or;
wire zeroloopback_clk_or;
wire zeroloopback_aclr_or;
wire zeroloopback_sload_or;
wire zeroloopback_bypass_register_or;
wire zeroloopback_out_reg;
//signals for zerochainout output register
wire [3:0] zerochainout_clkval_or;
wire [3:0] zerochainout_aclrval_or;
wire zerochainout_clk_or;
wire zerochainout_aclr_or;
wire zerochainout_sload_or;
wire zerochainout_bypass_register_or;
wire zerochainout_out_reg;
//Signals for saturation_overflow output register
wire [3:0] saturation_overflow_clkval_or;
wire [3:0] saturation_overflow_aclrval_or;
wire saturation_overflow_clk_or;
wire saturation_overflow_aclr_or;
wire saturation_overflow_sload_or;
wire saturation_overflow_bypass_register_or;
wire saturation_overflow_out_reg;
//signals for rs_dataout output register
wire [71:0] rs_dataout_in;
wire [3:0] rs_dataout_clkval_or;
wire [3:0] rs_dataout_aclrval_or;
wire [3:0] rs_dataout_clkval_or_co;
wire [3:0] rs_dataout_aclrval_or_co;
wire [3:0] rs_dataout_clkval_or_o;
wire [3:0] rs_dataout_aclrval_or_o;
wire rs_dataout_clk_or;
wire rs_dataout_aclr_or;
wire rs_dataout_sload_or;
wire rs_dataout_bypass_register_or;
wire rs_dataout_bypass_register_or_co;
wire rs_dataout_bypass_register_or_o;
wire[71:0] rs_dataout_out_reg;
wire rs_saturation_overflow_out_reg;
wire rs_saturation_overflow_in;
//signals for rotate output register
wire [3:0] rotate_clkval_or;
wire [3:0] rotate_aclrval_or;
wire rotate_clk_or;
wire rotate_aclr_or;
wire rotate_sload_or;
wire rotate_bypass_register_or;
wire rotate_out_reg;
//signals for shiftright output register
wire [3:0] shiftright_clkval_or;
wire [3:0] shiftright_aclrval_or;
wire shiftright_clk_or;
wire shiftright_aclr_or;
wire shiftright_sload_or;
wire shiftright_bypass_register_or;
wire shiftright_out_reg;
//signals for roundchainout output register
wire [3:0] roundchainout_clkval_or;
wire [3:0] roundchainout_aclrval_or;
wire roundchainout_clk_or;
wire roundchainout_aclr_or;
wire roundchainout_sload_or;
wire roundchainout_bypass_register_or;
wire roundchainout_out_reg;
//signals for saturatechainout output register
wire [3:0] saturatechainout_clkval_or;
wire [3:0] saturatechainout_aclrval_or;
wire saturatechainout_clk_or;
wire saturatechainout_aclr_or;
wire saturatechainout_sload_or;
wire saturatechainout_bypass_register_or;
wire saturatechainout_out_reg;
//Signals for chainout Adder RS Block
wire [71:0] coa_dataout;
wire [7:0] coa_datain_width;
wire [3:0] coa_round_width;
wire [7:0] coa_fraction_width;
wire [71:0] coa_rs_dataout;
wire coa_rs_saturation_overflow;
//signals for control signals for COA output register
wire [3:0] coa_reg_clkval_or;
wire [3:0] coa_reg_aclrval_or;
wire coa_reg_clk_or;
wire coa_reg_aclr_or;
wire coa_reg_sload_or;
wire coa_reg_bypass_register_or;
wire coa_reg_out_reg;
wire coa_rs_saturation_overflow_out_reg;
wire coa_rs_saturationchainout_overflow_out_reg;
wire [71:0] coa_rs_dataout_out_reg;
wire [71:0] dataout_shift_rot ;
reg [5:0] dataa_width_local;
wire [71:0] dataout_tmp;
wire [71:0] loopbackout_tmp;
always@(rs_dataout or rs_saturation_overflow or saturate_pip_reg)
begin
rs_dataout_of = rs_dataout;
rs_dataout_of[dataa_width -1] = (((operation_mode == "output_only")||(operation_mode == "one_level_adder") ||(operation_mode == "loopback"))
&&(dataa_width > 1) && (saturate_pip_reg == 1'b1))? rs_saturation_overflow : rs_dataout[dataa_width -1];
end
//Instantiate the zeroloopback input Register
hardcopyiii_mac_register zeroloopback_input_register (
.datain(zeroloopback),
.clk(zeroloopback_clk_ir),
.aclr(zeroloopback_aclr_ir),
.sload(zeroloopback_sload_ir),
.bypass_register(zeroloopback_bypass_register_ir),
.dataout(zeroloopback_in_reg)
);
defparam zeroloopback_input_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_ir = (zeroloopback_clock == "0") ? 4'b0000 :
(zeroloopback_clock == "1") ? 4'b0001 :
(zeroloopback_clock == "2") ? 4'b0010 :
(zeroloopback_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_ir = (zeroloopback_clear == "0") ? 4'b0000 :
(zeroloopback_clear == "1") ? 4'b0001 :
(zeroloopback_clear == "2") ? 4'b0010 :
(zeroloopback_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_ir = clk[zeroloopback_clkval_ir] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_ir = aclr[zeroloopback_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_ir = ena[zeroloopback_clkval_ir] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_ir = (zeroloopback_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zeroacc input Register
hardcopyiii_mac_register zeroacc_input_register (
.datain(zeroacc),
.clk(zeroacc_clk_ir),
.aclr(zeroacc_aclr_ir),
.sload(zeroacc_sload_ir),
.bypass_register(zeroacc_bypass_register_ir),
.dataout(zeroacc_in_reg)
);
defparam zeroacc_input_register.data_width = 1;
//decode the clk and aclr values
assign zeroacc_clkval_ir =(zeroacc_clock == "0") ? 4'b0000 :
(zeroacc_clock == "1") ? 4'b0001 :
(zeroacc_clock == "2") ? 4'b0010 :
(zeroacc_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_aclrval_ir = (zeroacc_clear == "0") ? 4'b0000 :
(zeroacc_clear == "1") ? 4'b0001 :
(zeroacc_clear == "2") ? 4'b0010 :
(zeroacc_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_clk_ir = clk[zeroacc_clkval_ir] ? 1'b1 : 1'b0;
assign zeroacc_aclr_ir = aclr[zeroacc_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroacc_sload_ir = ena[zeroacc_clkval_ir] ? 1'b1 : 1'b0;
assign zeroacc_bypass_register_ir = (zeroacc_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa input Register
hardcopyiii_mac_register signa_input_register (
.datain(signa),
.clk(signa_clk_ir),
.aclr(signa_aclr_ir),
.sload(signa_sload_ir),
.bypass_register(signa_bypass_register_ir),
.dataout(signa_in_reg)
);
defparam signa_input_register.data_width = 1;
//decode the clk and aclr values
assign signa_clkval_ir =(signa_clock == "0") ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclrval_ir = (signa_clear == "0") ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk_ir = clk[signa_clkval_ir] ? 1'b1 : 1'b0;
assign signa_aclr_ir = aclr[signa_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload_ir = ena[signa_clkval_ir] ? 1'b1 : 1'b0;
assign signa_bypass_register_ir = (signa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb input Register
hardcopyiii_mac_register signb_input_register (
.datain(signb),
.clk(signb_clk_ir),
.aclr(signb_aclr_ir),
.sload(signb_sload_ir),
.bypass_register(signb_bypass_register_ir),
.dataout(signb_in_reg)
);
defparam signb_input_register.data_width = 1;
//decode the clk and aclr values
assign signb_clkval_ir =(signb_clock == "0") ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclrval_ir = (signb_clear == "0") ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk_ir = clk[signb_clkval_ir] ? 1'b1 : 1'b0;
assign signb_aclr_ir = aclr[signb_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload_ir = ena[signb_clkval_ir] ? 1'b1 : 1'b0;
assign signb_bypass_register_ir = (signb_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the rotate input Register
hardcopyiii_mac_register rotate_input_register (
.datain(rotate),
.clk(rotate_clk_ir),
.aclr(rotate_aclr_ir),
.sload(rotate_sload_ir),
.bypass_register(rotate_bypass_register_ir),
.dataout(rotate_in_reg)
);
defparam rotate_input_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_ir =(rotate_clock == "0") ? 4'b0000 :
(rotate_clock == "1") ? 4'b0001 :
(rotate_clock == "2") ? 4'b0010 :
(rotate_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_ir = (rotate_clear == "0") ? 4'b0000 :
(rotate_clear == "1") ? 4'b0001 :
(rotate_clear == "2") ? 4'b0010 :
(rotate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_ir = clk[rotate_clkval_ir] ? 1'b1 : 1'b0;
assign rotate_aclr_ir = aclr[rotate_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_ir = ena[rotate_clkval_ir] ? 1'b1 : 1'b0;
assign rotate_bypass_register_ir = (rotate_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright input Register
hardcopyiii_mac_register shiftright_input_register (
.datain(shiftright),
.clk(shiftright_clk_ir),
.aclr(shiftright_aclr_ir),
.sload(shiftright_sload_ir),
.bypass_register(shiftright_bypass_register_ir),
.dataout(shiftright_in_reg)
);
defparam shiftright_input_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_ir =(shiftright_clock == "0") ? 4'b0000 :
(shiftright_clock == "1") ? 4'b0001 :
(shiftright_clock == "2") ? 4'b0010 :
(shiftright_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_ir = (shiftright_clear == "0") ? 4'b0000 :
(shiftright_clear == "1") ? 4'b0001 :
(shiftright_clear == "2") ? 4'b0010 :
(shiftright_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_ir = clk[shiftright_clkval_ir] ? 1'b1 : 1'b0;
assign shiftright_aclr_ir = aclr[shiftright_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_ir = ena[shiftright_clkval_ir] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_ir = (shiftright_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the round input Register
hardcopyiii_mac_register round_input_register (
.datain(round),
.clk(round_clk_ir),
.aclr(round_aclr_ir),
.sload(round_sload_ir),
.bypass_register(round_bypass_register_ir),
.dataout(round_in_reg)
);
defparam round_input_register.data_width = 1;
//decode the clk and aclr values
assign round_clkval_ir =(round_clock == "0") ? 4'b0000 :
(round_clock == "1") ? 4'b0001 :
(round_clock == "2") ? 4'b0010 :
(round_clock == "3") ? 4'b0011 : 4'b0000;
assign round_aclrval_ir = (round_clear == "0") ? 4'b0000 :
(round_clear == "1") ? 4'b0001 :
(round_clear == "2") ? 4'b0010 :
(round_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round_clk_ir = clk[round_clkval_ir] ? 1'b1 : 1'b0;
assign round_aclr_ir = aclr[round_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign round_sload_ir = ena[round_clkval_ir] ? 1'b1 : 1'b0;
assign round_bypass_register_ir = (round_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturate input Register
hardcopyiii_mac_register saturate_input_register (
.datain(saturate),
.clk(saturate_clk_ir),
.aclr(saturate_aclr_ir),
.sload(saturate_sload_ir),
.bypass_register(saturate_bypass_register_ir),
.dataout(saturate_in_reg)
);
defparam saturate_input_register.data_width = 1;
//decode the clk and aclr values
assign saturate_clkval_ir =(saturate_clock == "0") ? 4'b0000 :
(saturate_clock == "1") ? 4'b0001 :
(saturate_clock == "2") ? 4'b0010 :
(saturate_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_aclrval_ir = (saturate_clear == "0") ? 4'b0000 :
(saturate_clear == "1") ? 4'b0001 :
(saturate_clear == "2") ? 4'b0010 :
(saturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_clk_ir = clk[saturate_clkval_ir] ? 1'b1 : 1'b0;
assign saturate_aclr_ir = aclr[saturate_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturate_sload_ir = ena[saturate_clkval_ir] ? 1'b1 : 1'b0;
assign saturate_bypass_register_ir = (saturate_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout input Register
hardcopyiii_mac_register roundchainout_input_register (
.datain(roundchainout),
.clk(roundchainout_clk_ir),
.aclr(roundchainout_aclr_ir),
.sload(roundchainout_sload_ir),
.bypass_register(roundchainout_bypass_register_ir),
.dataout(roundchainout_in_reg)
);
defparam roundchainout_input_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_ir =(roundchainout_clock == "0") ? 4'b0000 :
(roundchainout_clock == "1") ? 4'b0001 :
(roundchainout_clock == "2") ? 4'b0010 :
(roundchainout_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_ir = (roundchainout_clear == "0") ? 4'b0000 :
(roundchainout_clear == "1") ? 4'b0001 :
(roundchainout_clear == "2") ? 4'b0010 :
(roundchainout_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_ir = clk[roundchainout_clkval_ir] ? 1'b1 : 1'b0;
assign roundchainout_aclr_ir = aclr[roundchainout_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_ir = ena[roundchainout_clkval_ir] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_ir = (roundchainout_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout input Register
hardcopyiii_mac_register saturatechainout_input_register (
.datain(saturatechainout),
.clk(saturatechainout_clk_ir),
.aclr(saturatechainout_aclr_ir),
.sload(saturatechainout_sload_ir),
.bypass_register(saturatechainout_bypass_register_ir),
.dataout(saturatechainout_in_reg)
);
defparam saturatechainout_input_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_ir =(saturatechainout_clock == "0") ? 4'b0000 :
(saturatechainout_clock == "1") ? 4'b0001 :
(saturatechainout_clock == "2") ? 4'b0010 :
(saturatechainout_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_ir =(saturatechainout_clear == "0") ? 4'b0000 :
(saturatechainout_clear == "1") ? 4'b0001 :
(saturatechainout_clear == "2") ? 4'b0010 :
(saturatechainout_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_ir = clk[saturatechainout_clkval_ir] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_ir = aclr[saturatechainout_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_ir = ena[saturatechainout_clkval_ir] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_ir = (saturatechainout_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the First level adder interface and sign extension block
hardcopyiii_fsa_isse fsa_interface(
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.chainin(chainin),
.signa(signa_in_reg),
.signb(signb_in_reg),
.dataa_out(dataa_fsa_in),
.datab_out(datab_fsa_in),
.datac_out(datac_fsa_in),
.datad_out(datad_fsa_in),
.chainin_out(chainin_coa_in),
.operation(operation)
);
defparam fsa_interface.dataa_width = dataa_width;
defparam fsa_interface.datab_width = datab_width;
defparam fsa_interface.datac_width = datac_width;
defparam fsa_interface.datad_width = datad_width;
defparam fsa_interface.chainin_width = chainin_width;
defparam fsa_interface.operation_mode = operation_mode;
defparam fsa_interface.multa_signa_internally_grounded = multa_signa_internally_grounded;
defparam fsa_interface.multa_signb_internally_grounded = multa_signb_internally_grounded;
defparam fsa_interface.multb_signa_internally_grounded = multb_signa_internally_grounded;
defparam fsa_interface.multb_signb_internally_grounded = multb_signb_internally_grounded;
defparam fsa_interface.multc_signa_internally_grounded = multc_signa_internally_grounded;
defparam fsa_interface.multc_signb_internally_grounded = multc_signb_internally_grounded;
defparam fsa_interface.multd_signa_internally_grounded = multd_signa_internally_grounded;
defparam fsa_interface.multd_signb_internally_grounded = multd_signb_internally_grounded;
assign sign = signa_in_reg | signb_in_reg;
//Instantiate First Stage Adder/Subtractor Unit0
hardcopyiii_first_stage_add_sub fsaunit0(
.dataa(dataa_fsa_in),
.datab(datab_fsa_in),
.sign(sign),
.operation(operation),
.dataout(dataout_fsa0)
);
defparam fsaunit0.dataa_width = dataa_width;
defparam fsaunit0.datab_width = datab_width;
defparam fsaunit0.fsa_mode = first_adder0_mode;
//Instantiate First Stage Adder/Subtractor Unit1
hardcopyiii_first_stage_add_sub fsaunit1(
.dataa(datac_fsa_in),
.datab(datad_fsa_in),
.sign(sign),
.operation(operation),
.dataout(dataout_fsa1)
);
defparam fsaunit1.dataa_width = datac_width;
defparam fsaunit1.datab_width = datad_width;
defparam fsaunit1.fsa_mode = first_adder1_mode;
//Instantiate the zeroloopback pipeline Register
hardcopyiii_mac_register zeroloopback_pipeline_register (
.datain(zeroloopback_in_reg),
.clk(zeroloopback_clk_pip),
.aclr(zeroloopback_aclr_pip),
.sload(zeroloopback_sload_pip),
.bypass_register(zeroloopback_bypass_register_pip),
.dataout(zeroloopback_pip_reg)
);
defparam zeroloopback_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_pip =(zeroloopback_pipeline_clock == "0") ? 4'b0000 :
(zeroloopback_pipeline_clock == "1") ? 4'b0001 :
(zeroloopback_pipeline_clock == "2") ? 4'b0010 :
(zeroloopback_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_pip = (zeroloopback_pipeline_clear == "0") ? 4'b0000 :
(zeroloopback_pipeline_clear == "1") ? 4'b0001 :
(zeroloopback_pipeline_clear == "2") ? 4'b0010 :
(zeroloopback_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_pip = clk[zeroloopback_clkval_pip] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_pip = aclr[zeroloopback_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_pip = ena[zeroloopback_clkval_pip] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_pip = (zeroloopback_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zeroacc pipeline Register
hardcopyiii_mac_register zeroacc_pipeline_register (
.datain(zeroacc_in_reg),
.clk(zeroacc_clk_pip),
.aclr(zeroacc_aclr_pip),
.sload(zeroacc_sload_pip),
.bypass_register(zeroacc_bypass_register_pip),
.dataout(zeroacc_pip_reg)
);
defparam zeroacc_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign zeroacc_clkval_pip =(zeroacc_pipeline_clock == "0") ? 4'b0000 :
(zeroacc_pipeline_clock == "1") ? 4'b0001 :
(zeroacc_pipeline_clock == "2") ? 4'b0010 :
(zeroacc_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_aclrval_pip = (zeroacc_pipeline_clear == "0") ? 4'b0000 :
(zeroacc_pipeline_clear == "1") ? 4'b0001 :
(zeroacc_pipeline_clear == "2") ? 4'b0010 :
(zeroacc_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_clk_pip = clk[zeroacc_clkval_pip] ? 1'b1 : 1'b0;
assign zeroacc_aclr_pip = aclr[zeroacc_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroacc_sload_pip = ena[zeroacc_clkval_pip] ? 1'b1 : 1'b0;
assign zeroacc_bypass_register_pip = (zeroacc_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa pipeline Register
hardcopyiii_mac_register signa_pipeline_register (
.datain(signa_in_reg),
.clk(signa_clk_pip),
.aclr(signa_aclr_pip),
.sload(signa_sload_pip),
.bypass_register(signa_bypass_register_pip),
.dataout(signa_pip_reg)
);
defparam signa_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign signa_clkval_pip =(signa_pipeline_clock == "0") ? 4'b0000 :
(signa_pipeline_clock == "1") ? 4'b0001 :
(signa_pipeline_clock == "2") ? 4'b0010 :
(signa_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclrval_pip = (signa_pipeline_clear == "0") ? 4'b0000 :
(signa_pipeline_clear == "1") ? 4'b0001 :
(signa_pipeline_clear == "2") ? 4'b0010 :
(signa_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk_pip = clk[signa_clkval_pip] ? 1'b1 : 1'b0;
assign signa_aclr_pip = aclr[signa_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload_pip = ena[signa_clkval_pip] ? 1'b1 : 1'b0;
assign signa_bypass_register_pip = (signa_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb pipeline Register
hardcopyiii_mac_register signb_pipeline_register (
.datain(signb_in_reg),
.clk(signb_clk_pip),
.aclr(signb_aclr_pip),
.sload(signb_sload_pip),
.bypass_register(signb_bypass_register_pip),
.dataout(signb_pip_reg)
);
defparam signb_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign signb_clkval_pip = (signb_pipeline_clock == "0") ? 4'b0000 :
(signb_pipeline_clock == "1") ? 4'b0001 :
(signb_pipeline_clock == "2") ? 4'b0010 :
(signb_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclrval_pip = (signb_pipeline_clear == "0") ? 4'b0000 :
(signb_pipeline_clear == "1") ? 4'b0001 :
(signb_pipeline_clear == "2") ? 4'b0010 :
(signb_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk_pip = clk[signb_clkval_pip] ? 1'b1 : 1'b0;
assign signb_aclr_pip = aclr[signb_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload_pip = ena[signb_clkval_pip] ? 1'b1 : 1'b0;
assign signb_bypass_register_pip = (signb_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the rotate pipeline Register
hardcopyiii_mac_register rotate_pipeline_register (
.datain(rotate_in_reg),
.clk(rotate_clk_pip),
.aclr(rotate_aclr_pip),
.sload(rotate_sload_pip),
.bypass_register(rotate_bypass_register_pip),
.dataout(rotate_pip_reg)
);
defparam rotate_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_pip =(rotate_pipeline_clock == "0") ? 4'b0000 :
(rotate_pipeline_clock == "1") ? 4'b0001 :
(rotate_pipeline_clock == "2") ? 4'b0010 :
(rotate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_pip =(rotate_pipeline_clear == "0") ? 4'b0000 :
(rotate_pipeline_clear == "1") ? 4'b0001 :
(rotate_pipeline_clear == "2") ? 4'b0010 :
(rotate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_pip = clk[rotate_clkval_pip] ? 1'b1 : 1'b0;
assign rotate_aclr_pip = aclr[rotate_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_pip = ena[rotate_clkval_pip] ? 1'b1 : 1'b0;
assign rotate_bypass_register_pip = (rotate_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright pipeline Register
hardcopyiii_mac_register shiftright_pipeline_register (
.datain(shiftright_in_reg),
.clk(shiftright_clk_pip),
.aclr(shiftright_aclr_pip),
.sload(shiftright_sload_pip),
.bypass_register(shiftright_bypass_register_pip),
.dataout(shiftright_pip_reg)
);
defparam shiftright_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_pip =(shiftright_pipeline_clock == "0") ? 4'b0000 :
(shiftright_pipeline_clock == "1") ? 4'b0001 :
(shiftright_pipeline_clock == "2") ? 4'b0010 :
(shiftright_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_pip = (shiftright_pipeline_clear == "0") ? 4'b0000 :
(shiftright_pipeline_clear == "1") ? 4'b0001 :
(shiftright_pipeline_clear == "2") ? 4'b0010 :
(shiftright_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_pip = clk[shiftright_clkval_pip] ? 1'b1 : 1'b0;
assign shiftright_aclr_pip = aclr[shiftright_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_pip = ena[shiftright_clkval_pip] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_pip = (shiftright_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the round pipeline Register
hardcopyiii_mac_register round_pipeline_register (
.datain(round_in_reg),
.clk(round_clk_pip),
.aclr(round_aclr_pip),
.sload(round_sload_pip),
.bypass_register(round_bypass_register_pip),
.dataout(round_pip_reg)
);
defparam round_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign round_clkval_pip = (round_pipeline_clock == "0") ? 4'b0000 :
(round_pipeline_clock == "1") ? 4'b0001 :
(round_pipeline_clock == "2") ? 4'b0010 :
(round_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign round_aclrval_pip = (round_pipeline_clear == "0") ? 4'b0000 :
(round_pipeline_clear == "1") ? 4'b0001 :
(round_pipeline_clear == "2") ? 4'b0010 :
(round_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round_clk_pip = clk[round_clkval_pip] ? 1'b1 : 1'b0;
assign round_aclr_pip = aclr[round_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign round_sload_pip = ena[round_clkval_pip] ? 1'b1 : 1'b0;
assign round_bypass_register_pip = (round_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturate pipeline Register
hardcopyiii_mac_register saturate_pipeline_register (
.datain(saturate_in_reg),
.clk(saturate_clk_pip),
.aclr(saturate_aclr_pip),
.sload(saturate_sload_pip),
.bypass_register(saturate_bypass_register_pip),
.dataout(saturate_pip_reg)
);
defparam saturate_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign saturate_clkval_pip =(saturate_pipeline_clock == "0") ? 4'b0000 :
(saturate_pipeline_clock == "1") ? 4'b0001 :
(saturate_pipeline_clock == "2") ? 4'b0010 :
(saturate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_aclrval_pip = (saturate_pipeline_clear == "0") ? 4'b0000 :
(saturate_pipeline_clear == "1") ? 4'b0001 :
(saturate_pipeline_clear == "2") ? 4'b0010 :
(saturate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_clk_pip = clk[saturate_clkval_pip] ? 1'b1 : 1'b0;
assign saturate_aclr_pip = aclr[saturate_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturate_sload_pip = ena[saturate_clkval_pip] ? 1'b1 : 1'b0;
assign saturate_bypass_register_pip = (saturate_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout pipeline Register
hardcopyiii_mac_register roundchainout_pipeline_register (
.datain(roundchainout_in_reg),
.clk(roundchainout_clk_pip),
.aclr(roundchainout_aclr_pip),
.sload(roundchainout_sload_pip),
.bypass_register(roundchainout_bypass_register_pip),
.dataout(roundchainout_pip_reg)
);
defparam roundchainout_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_pip = (roundchainout_pipeline_clock == "0") ? 4'b0000 :
(roundchainout_pipeline_clock == "1") ? 4'b0001 :
(roundchainout_pipeline_clock == "2") ? 4'b0010 :
(roundchainout_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_pip = (roundchainout_pipeline_clear == "0") ? 4'b0000 :
(roundchainout_pipeline_clear == "1") ? 4'b0001 :
(roundchainout_pipeline_clear == "2") ? 4'b0010 :
(roundchainout_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_pip = clk[roundchainout_clkval_pip] ? 1'b1 : 1'b0;
assign roundchainout_aclr_pip = aclr[roundchainout_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_pip = ena[roundchainout_clkval_pip] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_pip = (roundchainout_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout pipeline Register
hardcopyiii_mac_register saturatechainout_pipeline_register (
.datain(saturatechainout_in_reg),
.clk(saturatechainout_clk_pip),
.aclr(saturatechainout_aclr_pip),
.sload(saturatechainout_sload_pip),
.bypass_register(saturatechainout_bypass_register_pip),
.dataout(saturatechainout_pip_reg)
);
defparam saturatechainout_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_pip =(saturatechainout_pipeline_clock == "0") ? 4'b0000 :
(saturatechainout_pipeline_clock == "1") ? 4'b0001 :
(saturatechainout_pipeline_clock == "2") ? 4'b0010 :
(saturatechainout_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_pip = (saturatechainout_pipeline_clear == "0") ? 4'b0000 :
(saturatechainout_pipeline_clear == "1") ? 4'b0001 :
(saturatechainout_pipeline_clear == "2") ? 4'b0010 :
(saturatechainout_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_pip = clk[saturatechainout_clkval_pip] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_pip = aclr[saturatechainout_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_pip = ena[saturatechainout_clkval_pip] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_pip = (saturatechainout_pipeline_clock == "none") ? 1'b1 : 1'b0;
// Instantiate fsa0 dataout pipline register
hardcopyiii_mac_register fsa0_pipeline_register (
.datain(fsa_pip_datain1),
.clk(fsa0_clk_pip),
.aclr(fsa0_aclr_pip),
.sload(fsa0_sload_pip),
.bypass_register(fsa0_bypass_register_pip),
.dataout(fsa0_pip_reg)
);
defparam fsa0_pipeline_register.data_width = 72;
assign fsa_pip_datain1 = (operation_mode == "output_only") ? dataa_fsa_in : dataout_fsa0;
//decode the clk and aclr values
assign fsa0_clkval_pip =(first_adder0_clock == "0") ? 4'b0000 :
(first_adder0_clock == "1") ? 4'b0001 :
(first_adder0_clock == "2") ? 4'b0010 :
(first_adder0_clock == "3") ? 4'b0011 : 4'b0000;
assign fsa0_aclrval_pip = (first_adder0_clear == "0") ? 4'b0000 :
(first_adder0_clear == "1") ? 4'b0001 :
(first_adder0_clear == "2") ? 4'b0010 :
(first_adder0_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign fsa0_clk_pip = clk[fsa0_clkval_pip] ? 1'b1 : 1'b0;
assign fsa0_aclr_pip = aclr[fsa0_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign fsa0_sload_pip = ena[fsa0_clkval_pip] ? 1'b1 : 1'b0;
assign fsa0_bypass_register_pip = (first_adder0_clock == "none") ? 1'b1 : 1'b0;
// Instantiate fsa1 dataout pipline register
hardcopyiii_mac_register fsa1_pipeline_register (
.datain(dataout_fsa1),
.clk(fsa1_clk_pip),
.aclr(fsa1_aclr_pip),
.sload(fsa1_sload_pip),
.bypass_register(fsa1_bypass_register_pip),
.dataout(fsa1_pip_reg)
);
defparam fsa1_pipeline_register.data_width = 72;
//decode the clk and aclr values
assign fsa1_clkval_pip =(first_adder1_clock == "0") ? 4'b0000 :
(first_adder1_clock == "1") ? 4'b0001 :
(first_adder1_clock == "2") ? 4'b0010 :
(first_adder1_clock == "3") ? 4'b0011 : 4'b0000;
assign fsa1_aclrval_pip = (first_adder1_clear == "0") ? 4'b0000 :
(first_adder1_clear == "1") ? 4'b0001 :
(first_adder1_clear == "2") ? 4'b0010 :
(first_adder1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign fsa1_clk_pip = clk[fsa1_clkval_pip] ? 1'b1 : 1'b0;
assign fsa1_aclr_pip = aclr[fsa1_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign fsa1_sload_pip = ena[fsa1_clkval_pip] ? 1'b1 : 1'b0;
assign fsa1_bypass_register_pip = (first_adder1_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the second level adder/accumulator block
hardcopyiii_second_stage_add_accum ssa_unit(
.dataa(fsa0_pip_reg),
.datab(fsa1_pip_reg),
.accumin(ssa_accum_in),
.sign(ssa_sign),
.operation(operation),
.dataout(ssa_dataout),
.overflow(ssa_overflow)
);
defparam ssa_unit.dataa_width = dataa_width +1;
defparam ssa_unit.datab_width = datac_width + 1;
defparam ssa_unit.accum_width = dataa_width + 8;
defparam ssa_unit.ssa_mode = acc_adder_operation;
assign ssa_accum_in = (!zeroacc_pip_reg) ? rs_dataout_out_reg : 0;
assign ssa_sign = signa_pip_reg | signb_pip_reg;
// Instantiate round and saturation block
hardcopyiii_round_saturate_block rs_block(
.datain(rs_datain),
.round(round_pip_reg),
.saturate(saturate_pip_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.datain_width(ssa_datain_width),
.dataout(rs_dataout),
.saturationoverflow(rs_saturation_overflow)
);
defparam rs_block.dataa_width = dataa_width;
defparam rs_block.datab_width = datab_width;
defparam rs_block.saturate_width = saturate_width;
defparam rs_block.round_width = round_width;
defparam rs_block.saturate_mode = saturate_mode;
defparam rs_block.round_mode = round_mode;
defparam rs_block.operation_mode = operation_mode;
assign rs_datain = ((operation_mode == "output_only") ||
(operation_mode == "one_level_adder")||
(operation_mode == "loopback")) ? fsa0_pip_reg :ssa_dataout ;
assign ssa_datain_width_tmp = (((operation_mode == "accumulator")||(operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out")) ? (dataa_width[7:0] + 4'h8) :
(operation_mode == "two_level_adder") ? (dataa_width[7:0] + 4'h2) :
((operation_mode == "shift" ) || (operation_mode == "36_bit_multiply" )) ? (dataa_width[7:0] + datab_width[7:0]):
((operation_mode == "double" )) ? (dataa_width[7:0] + 4'h8) : dataa_width[7:0]);
assign ssa_datain_width = (ssa_datain_width_tmp >= round_width) ? ssa_datain_width_tmp : round_width[7:0];
//Instantiate the zeroloopback output Register
hardcopyiii_mac_register zeroloopback_output_register (
.datain(zeroloopback_pip_reg),
.clk(zeroloopback_clk_or),
.aclr(zeroloopback_aclr_or),
.sload(zeroloopback_sload_or),
.bypass_register(zeroloopback_bypass_register_or),
.dataout(zeroloopback_out_reg)
);
defparam zeroloopback_output_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_or =(zeroloopback_output_clock == "0") ? 4'b0000 :
(zeroloopback_output_clock == "1") ? 4'b0001 :
(zeroloopback_output_clock == "2") ? 4'b0010 :
(zeroloopback_output_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_or =(zeroloopback_output_clear == "0") ? 4'b0000 :
(zeroloopback_output_clear == "1") ? 4'b0001 :
(zeroloopback_output_clear == "2") ? 4'b0010 :
(zeroloopback_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_or = clk[zeroloopback_clkval_or] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_or = aclr[zeroloopback_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_or = ena[zeroloopback_clkval_or] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_or = (zeroloopback_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zerochainout output Register
hardcopyiii_mac_register zerochainout_output_register (
.datain(zerochainout),
.clk(zerochainout_clk_or),
.aclr(zerochainout_aclr_or),
.sload(zerochainout_sload_or),
.bypass_register(zerochainout_bypass_register_or),
.dataout(zerochainout_out_reg)
);
defparam zerochainout_output_register.data_width = 1;
//decode the clk and aclr values
assign zerochainout_clkval_or =(zerochainout_output_clock == "0") ? 4'b0000 :
(zerochainout_output_clock == "1") ? 4'b0001 :
(zerochainout_output_clock == "2") ? 4'b0010 :
(zerochainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign zerochainout_aclrval_or =(zerochainout_output_clear == "0") ? 4'b0000 :
(zerochainout_output_clear == "1") ? 4'b0001 :
(zerochainout_output_clear == "2") ? 4'b0010 :
(zerochainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zerochainout_clk_or = clk[zerochainout_clkval_or] ? 1'b1 : 1'b0;
assign zerochainout_aclr_or = aclr[zerochainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zerochainout_sload_or = ena[zerochainout_clkval_or] ? 1'b1 : 1'b0;
assign zerochainout_bypass_register_or = (zerochainout_output_clock == "none") ? 1'b1 : 1'b0;
// Instantiate Round_Saturate dataout output register
hardcopyiii_mac_register rs_dataout_output_register (
.datain(rs_dataout_in),
.clk(rs_dataout_clk_or),
.aclr(rs_dataout_aclr_or),
.sload(rs_dataout_sload_or),
.bypass_register(rs_dataout_bypass_register_or),
.dataout(rs_dataout_out_reg)
);
defparam rs_dataout_output_register.data_width = 72;
assign rs_dataout_in = ((operation_mode == "36_bit_multiply" )||(operation_mode == "shift")) ?
ssa_dataout : rs_dataout_of;
// Instantiate Round_Saturate saturation_overflow output register
hardcopyiii_mac_register rs_saturation_overflow_output_register (
.datain(rs_saturation_overflow_in),
.clk(rs_dataout_clk_or),
.aclr(rs_dataout_aclr_or),
.sload(rs_dataout_sload_or),
.bypass_register(rs_dataout_bypass_register_or),
.dataout(rs_saturation_overflow_out_reg)
);
defparam rs_saturation_overflow_output_register.data_width = 1;
// rs_dataout and the saturation_overflow uses the same control signals "second_adder_clock/clear" in chainout mode else output_clock/clear
//decode the clk and aclr values
assign rs_saturation_overflow_in = (saturate_pip_reg == 1'b1) ? rs_saturation_overflow : ssa_overflow;
assign rs_dataout_clkval_or_co = (second_adder_clock == "0") ? 4'b0000 :
(second_adder_clock == "1") ? 4'b0001 :
(second_adder_clock == "2") ? 4'b0010 :
(second_adder_clock == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_aclrval_or_co = (second_adder_clear == "0") ? 4'b0000 :
(second_adder_clear == "1") ? 4'b0001 :
(second_adder_clear == "2") ? 4'b0010 :
(second_adder_clear == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_clkval_or_o = (output_clock == "0") ? 4'b0000 :
(output_clock == "1") ? 4'b0001 :
(output_clock == "2") ? 4'b0010 :
(output_clock == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_aclrval_or_o = (output_clear == "0") ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_clkval_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_clkval_or_co : rs_dataout_clkval_or_o;
assign rs_dataout_aclrval_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_aclrval_or_co : rs_dataout_aclrval_or_o;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rs_dataout_clk_or = clk[rs_dataout_clkval_or] ? 1'b1 : 1'b0;
assign rs_dataout_aclr_or = aclr[rs_dataout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rs_dataout_sload_or = ena[rs_dataout_clkval_or] ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or_co = (second_adder_clock == "none") ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or_o = (output_clock == "none") ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_bypass_register_or_co : rs_dataout_bypass_register_or_o;
//Instantiate the rotate output Register
hardcopyiii_mac_register rotate_output_register (
.datain(rotate_pip_reg),
.clk(rotate_clk_or),
.aclr(rotate_aclr_or),
.sload(rotate_sload_or),
.bypass_register(rotate_bypass_register_or),
.dataout(rotate_out_reg)
);
defparam rotate_output_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_or = (rotate_output_clock == "0") ? 4'b0000 :
(rotate_output_clock == "1") ? 4'b0001 :
(rotate_output_clock == "2") ? 4'b0010 :
(rotate_output_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_or = (rotate_output_clear == "0") ? 4'b0000 :
(rotate_output_clear == "1") ? 4'b0001 :
(rotate_output_clear == "2") ? 4'b0010 :
(rotate_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_or = clk[rotate_clkval_or] ? 1'b1 : 1'b0;
assign rotate_aclr_or = aclr[rotate_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_or = ena[rotate_clkval_or] ? 1'b1 : 1'b0;
assign rotate_bypass_register_or = (rotate_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright output Register
hardcopyiii_mac_register shiftright_output_register (
.datain(shiftright_pip_reg),
.clk(shiftright_clk_or),
.aclr(shiftright_aclr_or),
.sload(shiftright_sload_or),
.bypass_register(shiftright_bypass_register_or),
.dataout(shiftright_out_reg)
);
defparam shiftright_output_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_or = (shiftright_output_clock == "0") ? 4'b0000 :
(shiftright_output_clock == "1") ? 4'b0001 :
(shiftright_output_clock == "2") ? 4'b0010 :
(shiftright_output_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_or = (shiftright_output_clear == "0") ? 4'b0000 :
(shiftright_output_clear == "1") ? 4'b0001 :
(shiftright_output_clear == "2") ? 4'b0010 :
(shiftright_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_or = clk[shiftright_clkval_or] ? 1'b1 : 1'b0;
assign shiftright_aclr_or = aclr[shiftright_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_or = ena[shiftright_clkval_or] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_or = (shiftright_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout output Register
hardcopyiii_mac_register roundchainout_output_register (
.datain(roundchainout_pip_reg),
.clk(roundchainout_clk_or),
.aclr(roundchainout_aclr_or),
.sload(roundchainout_sload_or),
.bypass_register(roundchainout_bypass_register_or),
.dataout(roundchainout_out_reg)
);
defparam roundchainout_output_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_or =(roundchainout_output_clock == "0") ? 4'b0000 :
(roundchainout_output_clock == "1") ? 4'b0001 :
(roundchainout_output_clock == "2") ? 4'b0010 :
(roundchainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_or = (roundchainout_output_clear == "0") ? 4'b0000 :
(roundchainout_output_clear == "1") ? 4'b0001 :
(roundchainout_output_clear == "2") ? 4'b0010 :
(roundchainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_or = clk[roundchainout_clkval_or] ? 1'b1 : 1'b0;
assign roundchainout_aclr_or = aclr[roundchainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_or = ena[roundchainout_clkval_or] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_or = (roundchainout_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout output Register
hardcopyiii_mac_register saturatechainout_output_register (
.datain(saturatechainout_pip_reg),
.clk(saturatechainout_clk_or),
.aclr(saturatechainout_aclr_or),
.sload(saturatechainout_sload_or),
.bypass_register(saturatechainout_bypass_register_or),
.dataout(saturatechainout_out_reg)
);
defparam saturatechainout_output_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_or =(saturatechainout_output_clock == "0") ? 4'b0000 :
(saturatechainout_output_clock == "1") ? 4'b0001 :
(saturatechainout_output_clock == "2") ? 4'b0010 :
(saturatechainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_or = (saturatechainout_output_clear == "0") ? 4'b0000 :
(saturatechainout_output_clear == "1") ? 4'b0001 :
(saturatechainout_output_clear == "2") ? 4'b0010 :
(saturatechainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_or = clk[saturatechainout_clkval_or] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_or = aclr[saturatechainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_or = ena[saturatechainout_clkval_or] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_or = (saturatechainout_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the Carry chainout Adder
hardcopyiii_carry_chain_adder chainout_adder(
.dataa(rs_dataout_out_reg),
.datab(chainin_coa_in),
.dataout(coa_dataout)
);
//Instantiate the carry chainout adder RS Block
hardcopyiii_round_saturate_block coa_rs_block(
.datain(coa_dataout),
.round(roundchainout_out_reg),
.saturate(saturatechainout_out_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.datain_width(coa_datain_width),
.dataout(coa_rs_dataout),
.saturationoverflow(coa_rs_saturation_overflow)
);
defparam coa_rs_block.dataa_width = dataa_width;
defparam coa_rs_block.datab_width = datab_width;
defparam coa_rs_block.saturate_width = saturate_chain_out_width;
defparam coa_rs_block.round_width =round_width;
defparam coa_rs_block.saturate_mode = saturate_chain_out_mode;
defparam coa_rs_block.round_mode = round_chain_out_mode;
defparam coa_rs_block.operation_mode = operation_mode;
assign coa_datain_width = ssa_datain_width;
assign coa_round_width = round_chain_out_width[3:0];
assign coa_fraction_width = coa_datain_width - saturate_chain_out_width[7:0];
//Instantiate the rs_saturation_overflow output register (after COA)
hardcopyiii_mac_register coa_rs_saturation_overflow_register (
.datain(rs_saturation_overflow_out_reg),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(1'b1),
.dataout(coa_rs_saturation_overflow_out_reg)
);
defparam coa_rs_saturation_overflow_register.data_width = 1;
//Instantiate the rs_saturationchainout_overflow output register
hardcopyiii_mac_register coa_rs_saturationchainout_overflow_register (
.datain(coa_rs_saturation_overflow),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(coa_reg_bypass_register_or),
.dataout(coa_rs_saturationchainout_overflow_out_reg)
);
defparam coa_rs_saturationchainout_overflow_register.data_width = 1;
// Instantiate the coa_rs_dataout output register
hardcopyiii_mac_register coa_rs_dataout_register (
.datain(coa_rs_dataout),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(coa_reg_bypass_register_or),
.dataout(coa_rs_dataout_out_reg)
);
defparam coa_rs_dataout_register.data_width = 72;
//decode the clk and aclr values
assign coa_reg_clkval_or =(output_clock == "0") ? 4'b0000 :
(output_clock == "1") ? 4'b0001 :
(output_clock == "2") ? 4'b0010 :
(output_clock == "3") ? 4'b0011 : 4'b0000;
assign coa_reg_aclrval_or =(output_clear == "0") ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign coa_reg_clk_or = clk[coa_reg_clkval_or] ? 1'b1 : 1'b0;
assign coa_reg_aclr_or = aclr[coa_reg_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign coa_reg_sload_or = ena[coa_reg_clkval_or] ? 1'b1 : 1'b0;
assign coa_reg_bypass_register_or = (output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the Shift/Rotate Unit
hardcopyiii_rotate_shift_block shift_rot_unit(
.datain(rs_dataout_out_reg),
.rotate(rotate_out_reg),
.shiftright(shiftright_out_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.dataout(dataout_shift_rot)
);
defparam shift_rot_unit.dataa_width = dataa_width;
defparam shift_rot_unit.datab_width = datab_width;
//Assign the dataout depending on the mode of operation
assign dataout_tmp = ((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_dataout_out_reg :
(operation_mode == "shift") ? dataout_shift_rot : rs_dataout_out_reg;
//Assign the loopbackout for loopback mode
assign loopbackout_tmp = ((operation_mode == "loopback") && (!zeroloopback_out_reg)) ? rs_dataout_out_reg : 0;
//Assign the saturation overflow output
assign overflow = ((operation_mode == "accumulator") ||(operation_mode == "two_level_adder"))
? rs_saturation_overflow_out_reg :
((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_saturation_overflow_out_reg : 1'b0;
//Assign the saturationchainout overflow output
assign saturatechainoutoverflow = ((operation_mode == "accumulator_chain_out") ||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_saturationchainout_overflow_out_reg : 1'b0;
assign dataout = (((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out")) &&(zerochainout_out_reg == 1'b1)) ? 72'b0 :dataout_tmp;
assign loopbackout = loopbackout_tmp[35:18];
endmodule
// begin_ddr
//-----------------------------------------------------------------------------
// Module Name: hardcopyiii_ddr_gray_decoder
// Description: auxilary module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign bout = breg;
always @(gin)
begin
breg[width-1] = gin[width-1];
if (width > 1)
begin
for (i=width-2; i >= 0; i=i-1)
breg[i] = breg[i+1] ^ gin[i];
end
end
endmodule
//-----------------------------------------------------------------------------
// Module Name: hardcopyiii_ddr_delay_chain_s
// Description: auxilary module - delay chain-setting
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_ddr_delay_chain_s (
clk,
delayctrlin,
phasectrlin,
delayed_clkout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter sim_buffer_intrinsic_delay = 350;
parameter sim_buffer_delay_increment = 10;
parameter phasectrlin_limit = 7;
input clk;
input [5 : 0] delayctrlin;
input [3 : 0] phasectrlin;
output delayed_clkout;
// decoded counter
wire [5:0] delayctrl_bin;
// cell delay
integer acell_delay;
integer delay_chain_len;
integer clk_delay;
// int signals
reg delayed_clk;
// filtering X/U etc.
wire [5 : 0] delayctrlin_in;
wire [3 : 0] phasectrlin_in;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
initial
begin
acell_delay = 0;
delay_chain_len = 0;
clk_delay = 0;
delayed_clk = 1'b0;
end
hardcopyiii_ddr_gray_decoder m_delayctrl_in_dec(delayctrlin_in, delayctrl_bin);
always @(delayctrl_bin or phasectrlin_in)
begin
// cell
acell_delay = sim_buffer_intrinsic_delay + delayctrl_bin * sim_buffer_delay_increment;
// no of cells
if (use_phasectrlin == "false")
delay_chain_len = phase_setting;
else
delay_chain_len = (phasectrlin_in > phasectrlin_limit) ? 0 : phasectrlin_in;
// total delay - added extra 1 ps for resolving racing
clk_delay = delay_chain_len * acell_delay + 1;
if ((use_phasectrlin == "true") && (phasectrlin_in > phasectrlin_limit))
begin
$display($time, " Warning: DDR phasesetting %m has invalid setting %b", phasectrlin_in);
end
end
// delayed clock
always @(clk)
delayed_clk <= #(clk_delay) clk;
assign delayed_clkout = delayed_clk;
endmodule
//-----------------------------------------------------------------------------
// Module Name: hardcopyiii_ddr_io_reg
// Description: io register model based on dffeas with
// input port 'rpt_viloation' addition
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module hardcopyiii_ddr_io_reg (
d,
clk,
ena,
clrn,
prn,
aload,
asdata,
sclr,
sload,
devclrn,
devpor,
rpt_violation,
q
);
// GLOBAL PARAMETER DECLARATION
parameter power_up = "DONT_CARE";
parameter is_wysiwyg = "false";
// LOCAL_PARAMETERS_BEGIN
parameter x_on_violation = "on";
// LOCAL_PARAMETERS_END
input d;
input clk;
input ena;
input clrn;
input prn;
input aload;
input asdata;
input sclr;
input sload;
input devclrn;
input devpor;
input rpt_violation;
output q;
wire q_tmp;
wire reset;
reg viol;
wire nosloadsclr;
wire sloaddata;
assign reset = devpor && devclrn && clrn && ena && rpt_violation;
assign nosloadsclr = reset && (~sload && ~sclr);
assign sloaddata = reset && sload;
assign q = q_tmp;
dffeas ddr_reg (
.d(d),
.clk(clk),
.clrn(clrn),
.aload(aload),
.sclr(sclr),
.sload(sload),
.asdata(asdata),
.ena(ena),
.prn(prn),
.q(q_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddr_reg.power_up = power_up;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, viol) ;
(posedge clk => (q +: d)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge prn => (q +: 1'b1)) = (0, 0) ;
(posedge aload => (q +: d)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_dll
//
// Description : HARDCOPYIII Delay Locked Loop
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dll (
clk,
aload,
upndnin,
upndninclkena,
devclrn,
devpor,
offsetdelayctrlout,
offsetdelayctrlclkout,
delayctrlout,
dqsupdate,
upndnout
);
// GLOBAL PARAMETERS - total 12
parameter input_frequency = "0 ps";
parameter delay_buffer_mode = "low"; // consistent with dqs
parameter delay_chain_length = 12;
parameter delayctrlout_mode = "normal";
parameter jitter_reduction = "false";
parameter use_upndnin = "false";
parameter use_upndninclkena = "false";
parameter sim_valid_lock = 16;
parameter sim_valid_lockcount = 0; // 0 = 350 + 10*dllcounter
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter static_delay_ctrl = 0; // for test
parameter dual_phase_comparators = "true"; // new in hardcopyiii
parameter lpm_type = "hardcopyiii_dll";
// LOCAL_PARAMETERS_BEGIN
parameter sim_buffer_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
// INPUT PORTS
input aload;
input clk;
input upndnin;
input upndninclkena;
input devclrn;
input devpor;
// OUTPUT PORTS
output [5:0] delayctrlout;
output dqsupdate;
output [5:0] offsetdelayctrlout;
output offsetdelayctrlclkout;
output upndnout;
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
// TMP OUTPUTS
wire [5:0] delayctrl_out;
wire [5:0] offsetdelayctrl_out;
wire dqsupdate_out;
wire upndn_out;
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction // str2int
// Const VARIABLES to represent string parameters
reg [1:0] para_delay_buffer_mode;
reg [1:0] para_delayctrlout_mode;
reg [5:0] para_static_delay_ctrl;
reg para_jitter_reduction;
reg para_use_upndnin;
reg para_use_upndninclkena;
// INTERNAL NETS AND VARIABLES
// for functionality - by modules
// two reg on the de-assertion of dll
wire aload_in;
reg aload_reg1;
reg aload_reg2;
// delay and offset control out resolver
wire [5:0] dr_delayctrl_out;
wire [5:0] dr_delayctrl_int;
wire [5:0] dr_offsetctrl_out;
wire [5:0] dr_dllcount_in;
wire dr_clk8_in;
wire dr_aload_in;
reg [5:0] dr_reg_dllcount;
// delay chain setting counter
wire [5:0] dc_dllcount_out;
wire [5:0] dc_dllcount_out_gray;
wire dc_upndn_in;
wire dc_aload_in;
wire dc_upndnclkena_in;
wire dc_clk8_in;
wire dc_clk1_in;
wire dc_dlltolock_in;
reg [5:0] dc_reg_dllcount;
reg dc_reg_dlltolock_pulse;
// jitter reduction counter
wire jc_upndn_out;
wire jc_upndnclkena_out;
wire jc_clk8_in;
wire jc_upndn_in;
wire jc_aload_in;
wire jc_clkena_in; // new in hardcopyiii
integer jc_count;
reg jc_reg_upndn;
reg jc_reg_upndnclkena;
// phase comparator
wire pc_lock; // new in hardcopyiii
wire pc_upndn_out;
wire [5:0] pc_dllcount_in;
wire pc_clk1_in;
wire pc_clk8_in;
wire pc_aload_in;
reg pc_reg_upndn;
integer pc_delay;
reg pc_lock_reg; // new in hardcopyiii
integer pc_comp_range; // new in hardcopyiii
// clock generator
wire cg_clk_in;
wire cg_aload_in;
wire cg_clk1_out;
wire cg_clk8a_out;
wire cg_clk8b_out;
reg cg_reg_1;
reg cg_rega_2;
reg cg_rega_3;
reg cg_regb_2;
reg cg_regb_3;
// for violation checks
reg clk_in_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg per_violation;
reg duty_violation;
reg sent_per_violation;
reg sent_duty_violation;
reg dll_to_lock; // exported signal
time clk_in_last_rising_edge;
time clk_in_last_falling_edge;
integer input_period;
integer clk_per_tolerance;
integer duty_cycle;
integer half_cycles_to_lock;
integer clk_in_period;
integer clk_in_duty_cycle;
// Timing hooks
// BUFFER INPUTS
wire clk_in;
wire aload_in_buf;
wire upndn_in;
wire upndninclkena_in;
assign clk_in = clk;
assign aload_in_buf = (aload === 1'b1) ? 1'b1 : 1'b0;
assign upndn_in = (upndnin === 1'b1) ? 1'b1 : 1'b0;
assign upndninclkena_in = (upndninclkena === 1'b1) ? 1'b1 : 1'b0;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (delayctrlout[0] +: delayctrl_out[0])) = (0, 0);
(posedge clk => (delayctrlout[1] +: delayctrl_out[1])) = (0, 0);
(posedge clk => (delayctrlout[2] +: delayctrl_out[2])) = (0, 0);
(posedge clk => (delayctrlout[3] +: delayctrl_out[3])) = (0, 0);
(posedge clk => (delayctrlout[4] +: delayctrl_out[4])) = (0, 0);
(posedge clk => (delayctrlout[5] +: delayctrl_out[5])) = (0, 0);
(posedge clk => (upndnout +: upndn_out)) = (0, 0);
$setuphold(posedge clk, upndnin, 0, 0);
$setuphold(posedge clk, upndninclkena, 0, 0);
endspecify
// DRIVERs FOR outputs
and (delayctrlout[0], delayctrl_out[0], 1'b1);
and (delayctrlout[1], delayctrl_out[1], 1'b1);
and (delayctrlout[2], delayctrl_out[2], 1'b1);
and (delayctrlout[3], delayctrl_out[3], 1'b1);
and (delayctrlout[4], delayctrl_out[4], 1'b1);
and (delayctrlout[5], delayctrl_out[5], 1'b1);
and (offsetdelayctrlout[5], offsetdelayctrl_out[5], 1'b1);
and (offsetdelayctrlout[0], offsetdelayctrl_out[0], 1'b1);
and (offsetdelayctrlout[1], offsetdelayctrl_out[1], 1'b1);
and (offsetdelayctrlout[2], offsetdelayctrl_out[2], 1'b1);
and (offsetdelayctrlout[3], offsetdelayctrl_out[3], 1'b1);
and (offsetdelayctrlout[4], offsetdelayctrl_out[4], 1'b1);
and (offsetdelayctrlout[5], offsetdelayctrl_out[5], 1'b1);
and (dqsupdate, dqsupdate_out, 1'b1);
and (upndnout, upndn_out, 1'b1);
// INITIAL BLOCK - info messsage and legaity checks
initial
begin
input_period = str2int(input_frequency);
$display("Note: DLL instance %m has input frequency %0d ps", input_period);
$display(" sim_valid_lock %0d", sim_valid_lock);
$display(" sim_valid_lockcount %0d", sim_valid_lockcount);
$display(" sim_low_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" sim_high_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" delay_buffer_mode %0s", delay_buffer_mode);
$display(" sim_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" sim_buffer_delay_increment %0d", sim_buffer_delay_increment);
$display(" delay_chain_length %0d", delay_chain_length);
clk_in_last_value = 0;
clk_in_last_rising_edge = 0;
clk_in_last_falling_edge = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
per_violation = 1'b0;
duty_violation = 1'b0;
sent_per_violation = 1'b0;
sent_duty_violation = 1'b0;
duty_cycle = input_period/2;
clk_per_tolerance = 2;
clk_in_period = 0;
clk_in_duty_cycle = 0;
dll_to_lock = 0;
half_cycles_to_lock = 0;
// Resolve string parameters
para_delay_buffer_mode = delay_buffer_mode == "auto" ? 2'b00 :
delay_buffer_mode == "low" ? 2'b01 : 2'b10;
para_delayctrlout_mode = delayctrlout_mode == "test" ? 2'b01 :
delayctrlout_mode == "normal" ? 2'b10 :
delayctrlout_mode == "static" ? 2'b11 : 2'b00;
para_static_delay_ctrl = static_delay_ctrl;
para_jitter_reduction = jitter_reduction == "true" ? 1'b1 : 1'b0;
para_use_upndnin = use_upndnin == "true" ? 1'b1 : 1'b0;
para_use_upndninclkena = use_upndninclkena == "true" ? 1'b1 : 1'b0;
$display(" delayctrlout_mode %0s", delayctrlout_mode);
$display(" static_delay_ctrl %0d", para_static_delay_ctrl);
$display(" use_jitter_reduction %0s", jitter_reduction);
$display(" use_upndnin %0s", use_upndnin);
$display(" use_upndninclkena %0s", use_upndninclkena);
end
// CLOCK PERIOD and DUTY CYCLE VIOLATION CHECKS and DLL_TO_LOCK
// exported signals to outside of this block:
// - dll_to_lock
always @(clk_in)
begin
if (clk_in == 1'b1 && clk_in != clk_in_last_value) // rising edge
begin
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge <= 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
else // subsequent rising edge
begin
// check for clk_period violation and duty cycle violation
clk_in_period = $time - clk_in_last_rising_edge;
clk_in_duty_cycle = $time - clk_in_last_falling_edge;
if ( (clk_in_period < (input_period - clk_per_tolerance)) ||
(clk_in_period > (input_period + clk_per_tolerance)) )
begin
per_violation = 1'b1;
if (sent_per_violation != 1'b1)
begin
$display($time, " Warning : Input frequency violation on DLL instance %m. Specified input period is %0d ps but actual is %0d ps",
input_period, clk_in_period);
sent_per_violation = 1'b1;
end
end
else if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
begin
if (per_violation === 1'b1)
begin
$display($time, " Note : Input frequency on DLL instance %m now matches with specified clock frequency.");
sent_per_violation = 1'b0;
end
per_violation = 1'b0;
duty_violation = 1'b0;
end
if ((duty_violation == 1'b0) && (per_violation == 1'b0) && (dll_to_lock == 1'b0))
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
end
clk_in_last_rising_edge = $time;
end
else if (clk_in == 1'b0 && clk_in != clk_in_last_value) // falling edge
begin
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
clk_in_duty_cycle = $time - clk_in_last_rising_edge;
if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
duty_violation = 1'b0;
if (dll_to_lock == 1'b0 && duty_violation == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_in_last_falling_edge = $time;
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// 1 or 0 to X transitions - illegal
// reset lock and unlock counters
half_cycles_to_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
if (dll_to_lock)
begin
dll_to_lock <= 0;
$display($time, " Warning : clock switches from 0/1 to X. DLL instance %m will lose lock.");
end
else
begin
$display($time, " Warning : clock switches from 0/1 to X on DLL instance %m");
end
end
clk_in_last_value <= clk_in;
end
// CONNCECTING the DLL outputs ------------------------------------------------
assign delayctrl_out = dr_delayctrl_out;
assign offsetdelayctrl_out = dr_offsetctrl_out;
assign offsetdelayctrlclkout = dr_clk8_in;
assign dqsupdate_out = cg_clk8a_out;
assign upndn_out = pc_upndn_out;
// two reg on the de-assertion of dll -----------------------------------------
assign aload_in = aload_in_buf | aload_reg2;
initial begin
aload_reg1 = 1'b1;
aload_reg2 = 1'b1;
end
always @(negedge clk_in)
begin
aload_reg1 <= aload_in_buf;
aload_reg2 <= aload_reg1;
end
// Delay and offset ctrl out resolver -----------------------------------------
// inputs
assign dr_clk8_in = ~cg_clk8b_out; // inverted
assign dr_dllcount_in = dc_dllcount_out_gray; // gray-coded for all outputs
assign dr_aload_in = aload_in;
// outputs
// ,addnsub,
assign dr_delayctrl_out = (delayctrlout_mode == "test") ? {cg_clk1_out,aload,1'bx,dr_reg_dllcount[2:0]}
: dr_reg_dllcount; // both static and normal
assign dr_offsetctrl_out = dr_delayctrl_int; // non-registered of delayout_out
// model
// assumed para_static_delay_ctrl is gray-coded
assign dr_delayctrl_int = (delayctrlout_mode == "static") ? para_static_delay_ctrl : dr_dllcount_in;
// por
initial
begin
dr_reg_dllcount = 6'b000000;
end
always @(posedge dr_clk8_in or posedge dr_aload_in )
begin
if (dr_aload_in === 1'b1)
dr_reg_dllcount <= 6'b000000;
else
dr_reg_dllcount <= dr_delayctrl_int;
end
// Delay Setting Control Counter ----------------------------------------------
//inputs
assign dc_dlltolock_in = dll_to_lock;
assign dc_aload_in = aload_in;
assign dc_clk1_in = cg_clk1_out;
assign dc_clk8_in = ~cg_clk8b_out; // inverted
assign dc_upndnclkena_in = (para_use_upndninclkena === 1'b1) ? upndninclkena :
(para_jitter_reduction === 1'b1) ? jc_upndnclkena_out :
(dual_phase_comparators == "true") ? ~pc_lock : 1'b1; // new in hardcopyiii
assign dc_upndn_in = (para_use_upndnin === 1'b1) ? upndnin :
(para_jitter_reduction === 1'b1) ? jc_upndn_out : pc_upndn_out;
// outputs
assign dc_dllcount_out_gray = dc_reg_dllcount ^ (dc_reg_dllcount >> 1);
assign dc_dllcount_out = dc_reg_dllcount;
// parameters used
// sim_valid_lockcount - ideal dll count value
// delay_buffer_mode -
// Model - registers to 0 in hardware by POR
initial
begin
// low=32=6'b100000 others=16
dc_reg_dllcount = (delay_buffer_mode == "low") ? 6'b000000 : 6'b000000;
dc_reg_dlltolock_pulse = 1'b0;
end
// dll counter logic - binary
always @(posedge dc_clk8_in or posedge dc_aload_in or posedge dc_dlltolock_in)
begin
if (dc_aload_in === 1'b1)
dc_reg_dllcount <= delay_buffer_mode == "low" ? 6'b100000 : 6'b010000;
else if (dc_dlltolock_in === 1'b1 && dc_upndnclkena_in === 1'b1 &&
para_use_upndnin === 1'b0 && dc_reg_dlltolock_pulse != 1'b1)
begin
dc_reg_dllcount <= sim_valid_lockcount;
dc_reg_dlltolock_pulse <= 1'b1;
end
else if (dc_upndnclkena_in === 1'b1) // posedge clk
begin
if (dc_upndn_in === 1'b1)
begin
if ((para_delay_buffer_mode == 2'b01 && dc_reg_dllcount < 6'b111111) ||
(para_delay_buffer_mode != 2'b01 && dc_reg_dllcount < 6'b011111))
dc_reg_dllcount <= dc_reg_dllcount + 1'b1;
end
else if (dc_upndn_in === 1'b0)
begin
if (dc_reg_dllcount > 6'b000000)
dc_reg_dllcount <= dc_reg_dllcount - 1'b1;
end
end
end
// Jitter reduction counter ---------------------------------------------------
// inputs
assign jc_clk8_in = ~cg_clk8b_out; // inverted
assign jc_upndn_in = pc_upndn_out;
assign jc_aload_in = aload_in;
// new in hardcopyiii
assign jc_clkena_in = (dual_phase_comparators == "false") ? 1'b1 : ~pc_lock;
// outputs
assign jc_upndn_out = jc_reg_upndn;
assign jc_upndnclkena_out = jc_reg_upndnclkena;
// Model
initial
begin
jc_count = 8;
jc_reg_upndnclkena = 1'b0;
jc_reg_upndn = 1'b0;
end
always @(posedge jc_clk8_in or posedge jc_aload_in)
begin
if (jc_aload_in === 1'b1)
jc_count <= 8;
else if (jc_clkena_in === 1'b1)
begin
if (jc_count == 12)
begin
jc_reg_upndn <= 1'b1;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else if (jc_count == 4)
begin
jc_reg_upndn <= 1'b0;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else // increment/decrement counter
begin
jc_reg_upndnclkena <= 1'b0;
if (jc_upndn_in === 1'b1)
jc_count <= jc_count + 1;
else if (jc_upndn_in === 1'b0)
jc_count <= jc_count - 1;
end
end
else
jc_reg_upndnclkena <= 1'b0;
end
// Phase comparator -----------------------------------------------------------
// inputs
assign pc_clk1_in = cg_clk1_out;
assign pc_clk8_in = cg_clk8b_out; // positive edge
assign pc_dllcount_in = dc_dllcount_out; // for phase loop calculation: binary
assign pc_aload_in = aload_in;
// outputs
assign pc_upndn_out = pc_reg_upndn;
assign pc_lock = pc_lock_reg;
// parameter used
// sim_loop_intrinsic_delay, sim_buffer_delay_increment
// Model
initial
begin
pc_reg_upndn = 1'b1;
pc_delay = 0;
pc_lock_reg = 1'b0;
pc_comp_range = (3*delay_chain_length*sim_buffer_delay_increment)/2;
end
always @(posedge pc_clk8_in or posedge pc_aload_in)
begin
if (pc_aload_in === 1'b1)
pc_reg_upndn <= 1'b1;
else
begin
pc_delay = delay_chain_length *(sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
if (dual_phase_comparators == "false")
begin
pc_lock_reg <= 1'b0;
if (pc_delay > input_period)
pc_reg_upndn <= 1'b0;
else
pc_reg_upndn <= 1'b1;
end
else
begin
if (pc_delay < (input_period - pc_comp_range/2))
begin
pc_reg_upndn <= 1'b1;
pc_lock_reg <= 1'b0;
end
else if ( pc_delay <= (input_period + pc_comp_range/2) )
begin
pc_lock_reg <= 1'b1;
pc_reg_upndn <= 1'b0;
end
else
begin
pc_lock_reg <= 1'b0;
pc_reg_upndn <= 1'b0;
end
end
end
end
// Clock Generator -----------------------------------------------------------
// inputs
assign cg_clk_in = clk_in;
assign cg_aload_in = aload_in;
// outputs
assign cg_clk8a_out = cg_rega_3;
assign cg_clk8b_out = cg_regb_3;
assign cg_clk1_out = (cg_aload_in === 1'b1) ? 1'b0 : cg_clk_in;
// Model
// por
initial
begin
cg_reg_1 = 1'b0;
cg_rega_2 = 1'b0;
cg_rega_3 = 1'b0;
cg_regb_2 = 1'b1;
cg_regb_3 = 1'b0;
end
always @(posedge cg_clk1_out or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_reg_1 <= 1'b0;
else
cg_reg_1 <= ~cg_reg_1;
end
always @(posedge cg_reg_1 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
begin
cg_rega_2 <= 1'b0;
cg_regb_2 <= 1'b1;
end
else
begin
cg_rega_2 <= ~cg_rega_2;
cg_regb_2 <= ~cg_regb_2;
end
end
always @(posedge cg_rega_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_rega_3 <= 1'b0;
else
cg_rega_3 <= ~cg_rega_3;
end
always @(posedge cg_regb_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_regb_3 <= 1'b0;
else if ($time != 0)
cg_regb_3 <= ~cg_regb_3;
end
endmodule // hardcopyiii_dll
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_offset_ctrl
//
// Description : HARDCOPYIII Delay Locked Loop Offset Control
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dll_offset_ctrl (
clk,
aload,
offsetdelayctrlin,
offset,
addnsub,
devclrn,
devpor,
offsettestout,
offsetctrlout
);
parameter use_offset = "false";
parameter static_offset = "0";
parameter delay_buffer_mode = "low"; // consistent with dqs
parameter lpm_type = "hardcopyiii_dll_offset_ctrl";
// INPUT PORTS
input clk;
input aload;
input [5:0] offsetdelayctrlin;
input [5:0] offset;
input addnsub;
input devclrn;
input devpor;
// OUTPUT PORTS
output [5:0] offsetctrlout;
output [5:0] offsettestout;
tri1 devclrn;
tri1 devpor;
// TMP OUTPUTS
wire [5:0] offsetctrl_out;
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction // str2int
// Const VARIABLES to represent string parameters
reg [1:0] para_delay_buffer_mode;
reg [1:0] para_use_offset;
integer para_static_offset;
// INTERNAL NETS AND VARIABLES
// for functionality - by modules
// two reg on the de-assertion of dll
reg aload_reg1;
reg aload_reg2;
// delay and offset control out resolver
wire [5:0] dr_offsettest_out;
wire [5:0] dr_offsetctrl_out;
wire [5:0] dr_offsetctrl_out_gray;
wire dr_clk8_in;
wire dr_aload_in;
wire dr_addnsub_in;
wire [5:0] dr_offset_in_gray;
wire [5:0] dr_delayctrl_in_gray;
wire [5:0] para_static_offset_gray;
//decoder
wire [5:0] dr_delayctrl_in_bin;
wire [5:0] dr_offset_in_bin;
wire [5:0] dr_offset_in_bin_pos;
wire [5:0] para_static_offset_bin;
wire [5:0] para_static_offset_bin_pos;
reg [5:0] dr_reg_offset;
// Timing hooks
// BUFFER INPUTS
wire clk_in;
wire aload_in;
wire offset_in5;
wire offset_in4;
wire offset_in3;
wire offset_in2;
wire offset_in1;
wire offset_in0;
wire addnsub_in;
wire [5:0] offsetdelayctrlin_in;
wire [5:0] offset_in;
assign clk_in = clk;
assign aload_in = (aload === 1'b1) ? 1'b1 : 1'b0;
assign offset_in5 = (offset[5] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in4 = (offset[4] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in3 = (offset[3] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in2 = (offset[2] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in1 = (offset[1] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in0 = (offset[0] === 1'b1) ? 1'b1 : 1'b0;
assign addnsub_in = (addnsub === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[5] = (offsetdelayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[4] = (offsetdelayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[3] = (offsetdelayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[2] = (offsetdelayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[1] = (offsetdelayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[0] = (offsetdelayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in = {offset_in5, offset_in4,
offset_in3, offset_in2,
offset_in1, offset_in0};
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
// These timing paths existed from HARDCOPYIII, currently not modeled in hardcopyiii
specify
(posedge clk => (offsetctrlout[0] +: offsetctrl_out[0])) = (0, 0);
(posedge clk => (offsetctrlout[1] +: offsetctrl_out[1])) = (0, 0);
(posedge clk => (offsetctrlout[2] +: offsetctrl_out[2])) = (0, 0);
(posedge clk => (offsetctrlout[3] +: offsetctrl_out[3])) = (0, 0);
(posedge clk => (offsetctrlout[4] +: offsetctrl_out[4])) = (0, 0);
(posedge clk => (offsetctrlout[5] +: offsetctrl_out[5])) = (0, 0);
(offset => offsetctrlout) = (0, 0);
$setuphold(posedge clk, offset[0], 0, 0);
$setuphold(posedge clk, offset[1], 0, 0);
$setuphold(posedge clk, offset[2], 0, 0);
$setuphold(posedge clk, offset[3], 0, 0);
$setuphold(posedge clk, offset[4], 0, 0);
$setuphold(posedge clk, offset[5], 0, 0);
$setuphold(posedge clk, addnsub, 0, 0);
endspecify
// DRIVERs FOR outputs
and (offsetctrlout[0], offsetctrl_out[0], 1'b1);
and (offsetctrlout[1], offsetctrl_out[1], 1'b1);
and (offsetctrlout[2], offsetctrl_out[2], 1'b1);
and (offsetctrlout[3], offsetctrl_out[3], 1'b1);
and (offsetctrlout[4], offsetctrl_out[4], 1'b1);
and (offsetctrlout[5], offsetctrl_out[5], 1'b1);
// INITIAL BLOCK - info messsage and legaity checks
initial
begin
// Resolve string parameters
para_delay_buffer_mode = delay_buffer_mode == "low" ? 2'b01 : 2'b00;
para_use_offset = use_offset == "true" ? 2'b01 : 2'b00;
para_static_offset = str2int(static_offset);
$display("Note: DLL_offset_ctrl instance %m has delay_buffer_mode %0s", delay_buffer_mode);
$display(" use_offset %0s", use_offset);
$display(" static_offset %0d", para_static_offset);
end
// CONNCECTING primary outputs ------------------------------------------------
assign offsetctrl_out = dr_offsetctrl_out_gray;
assign offsettestout = dr_offsettest_out;
// ----------------------------------------------------------------------------
// offset ctrl out resolver:
// adding offset_in into offsetdelayin according to offsetctrlout_mode
// ----------------------------------------------------------------------------
// two reg on the de-assertion of dll -----------------------------------------
// it is the clk feeding into DLL, not /8 clock.
initial begin
aload_reg1 = 1'b1;
aload_reg2 = 1'b1;
end
always @(negedge clk_in)
begin
aload_reg1 <= aload_in;
aload_reg2 <= aload_reg1;
end
// inputs
assign dr_clk8_in = clk_in;
assign dr_aload_in = aload_in; // aload_in | aload_reg2;
assign dr_addnsub_in = addnsub_in;
assign dr_delayctrl_in_gray = offsetdelayctrlin_in;
// ------------------------------------------------------------------------
// substraction flow:
// - decode
// - ADD or (2's complement then sub - better for overflow check)
//Addtion flow:
// - decode
// - add
//------------------------------------------------------------------------
assign dr_offset_in_gray = offset_in;
assign para_static_offset_gray = para_static_offset[5:0];
// for counter overflow check - getting the binary abs() of the binary para_static
assign para_static_offset_bin_pos = (para_static_offset > 0) ? para_static_offset_bin :
(6'b111111 - para_static_offset_bin + 6'b000001);
assign dr_offset_in_bin_pos = ((use_offset == "true") && (dr_addnsub_in === 1'b0)) ?
(6'b111111 - dr_offset_in_bin + 6'b000001) : dr_offset_in_bin;
// outputs
assign dr_offsetctrl_out = dr_reg_offset;
assign dr_offsetctrl_out_gray = dr_reg_offset ^ (dr_reg_offset >> 1);
assign dr_offsettest_out = (use_offset == "false") ? para_static_offset[5:0] : offset_in;
// model
// gray decoder
hardcopyiii_ddr_gray_decoder mdr_delayctrl_in_dec(dr_delayctrl_in_gray, dr_delayctrl_in_bin);
hardcopyiii_ddr_gray_decoder mdr_offset_in_dec(dr_offset_in_gray, dr_offset_in_bin);
hardcopyiii_ddr_gray_decoder mpara_static_offset_dec(para_static_offset_gray, para_static_offset_bin);
// por
initial
begin
dr_reg_offset = 6'b000000;
end
// based on dr_delayctrl_in and dr_offset_in_bin (for dynamic) and para_static_offset_bin
always @(posedge dr_clk8_in or posedge dr_aload_in)
begin
if (dr_aload_in === 1'b1)
begin
dr_reg_offset <= 6'b000000;
end
else if (use_offset == "true") // addnsub
begin
if (dr_addnsub_in === 1'b1)
if (dr_delayctrl_in_bin < 6'b111111 - dr_offset_in_bin)
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= 6'b111111;
else if (dr_addnsub_in === 1'b0)
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos)
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; // same as - _pos
else
dr_reg_offset <= 6'b000000;
end
else // static
begin
if (para_static_offset >= 0)
if (para_static_offset_bin < 64 && para_static_offset_bin < 6'b111111 - dr_delayctrl_in_bin)
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= 6'b111111;
else // donot use a_vec - b_vec >=0 as it is always true
if (para_static_offset_bin_pos < 63 && dr_delayctrl_in_bin > para_static_offset_bin_pos)
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; // same as - *_pos
else
dr_reg_offset <= 6'b000000;
end
end
endmodule // hardcopyiii_offset_ctrl
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_dqs_delay_chain
//
// Description : HARDCOPYIII DQS Delay Chain (within DQS I/O)
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dqs_delay_chain (
dqsin,
delayctrlin,
offsetctrlin,
dqsupdateen,
phasectrlin,
devclrn,
devpor,
dffin,
dqsbusout
);
parameter dqs_input_frequency = "unused" ; // not used
parameter use_phasectrlin = "false"; // rev 1.21
parameter phase_setting = 0; // <0 - 4>
parameter delay_buffer_mode = "low";
parameter dqs_phase_shift = 0; // <0..36000> for TAN only
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
// test parameters added in WYS 1.33
parameter test_enable = "false";
parameter test_select = 0;
// Simulation parameters
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "hardcopyiii_dqs_delay_chain";
// INPUT PORTS
input dqsin;
input [5:0] delayctrlin;
input [5:0] offsetctrlin;
input dqsupdateen;
input [2:0] phasectrlin;
input devclrn, devpor;
// OUTPUT PORTS
output dqsbusout;
output dffin; // buried
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// decoded counter
wire [5:0] delayctrl_bin;
wire [5:0] offsetctrl_bin;
// offsetctrl after "dqs_offsetctrl_enable" mux
wire [5:0] offsetctrl_mux;
// reged outputs of delay count
reg [5:0] delayctrl_reg;
reg [5:0] offsetctrl_reg;
// delay count after latch enable mux
wire [5:0] delayctrl_reg_mux;
wire [5:0] offsetctrl_reg_mux;
// single cell delay
integer tmp_delayctrl;
integer tmp_offsetctrl;
integer acell_delay;
integer aoffsetcell_delay;
integer delay_chain_len;
integer dqs_delay;
reg tmp_dqsbusout;
// Buffer Layer
wire dqsin_in;
wire [5:0] delayctrlin_in;
wire [5:0] offsetctrlin_in;
wire dqsupdateen_in;
wire [2:0] phasectrlin_in;
wire [12:0] test_bus;
wire test_lpbk;
wire tmp_dqsin; // after and with test_loopback
assign dqsin_in = dqsin;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[5] = (offsetctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[4] = (offsetctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[3] = (offsetctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[2] = (offsetctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[1] = (offsetctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[0] = (offsetctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign dqsupdateen_in = (dqsupdateen === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
specify
(dqsin => dqsbusout) = (0,0);
$setuphold(posedge dqsupdateen, delayctrlin[0], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[1], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[2], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[3], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[4], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[5], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[0], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[1], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[2], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[3], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[4], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[5], 0, 0);
endspecify
// reg
initial begin
delayctrl_reg = 6'b111111;
offsetctrl_reg = 6'b111111;
tmp_delayctrl = 0;
tmp_offsetctrl = 0;
acell_delay = 0;
end
always @(posedge dqsupdateen_in)
begin
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
end
assign offsetctrl_mux = (dqs_offsetctrl_enable == "true") ? offsetctrlin_in : delayctrlin_in;
// mux after reg
assign delayctrl_reg_mux = (dqs_ctrl_latches_enable == "true") ? delayctrl_reg : delayctrlin_in;
assign offsetctrl_reg_mux = (dqs_ctrl_latches_enable == "true") ? offsetctrl_reg : offsetctrl_mux;
// decode
hardcopyiii_ddr_gray_decoder m_delayctrl_in_dec (delayctrl_reg_mux, delayctrl_bin);
hardcopyiii_ddr_gray_decoder m_offsetctrl_in_dec(offsetctrl_reg_mux, offsetctrl_bin);
always @(delayctrl_bin or offsetctrl_bin or phasectrlin_in)
begin
tmp_delayctrl = (delay_buffer_mode == "high" && delayctrl_bin[5] == 1'b1) ? 31 : delayctrl_bin;
tmp_offsetctrl = (delay_buffer_mode == "high" && offsetctrl_bin[5] == 1'b1) ? 31 : offsetctrl_bin;
// cell
acell_delay = sim_intrinsic_delay + tmp_delayctrl * sim_buffer_delay_increment;
if (dqs_offsetctrl_enable == "true")
aoffsetcell_delay = sim_intrinsic_delay + tmp_offsetctrl * sim_buffer_delay_increment;
else
aoffsetcell_delay = acell_delay;
// no of cells
if (use_phasectrlin == "false")
delay_chain_len = phase_setting;
else if (phasectrlin_in[2] === 1'b1)
delay_chain_len = 0;
else
delay_chain_len = phasectrlin_in + 3'b001;
// total delay
if (delay_chain_len == 0)
dqs_delay = 0;
else
dqs_delay = (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
end
// test bus loopback
assign test_bus = {~dqsupdateen_in, offsetctrl_reg_mux, delayctrl_reg_mux};
assign test_lpbk = (0 <= test_select && test_select <= 12) ? test_bus[test_select] : 1'bz;
assign tmp_dqsin = (test_enable == "true") ? (test_lpbk & dqsin_in) : dqsin_in;
always @(tmp_dqsin)
tmp_dqsbusout <= #(dqs_delay) tmp_dqsin;
pmos (dqsbusout, tmp_dqsbusout, 1'b0);
endmodule // hardcopyiii_dqs_delay_chain
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_dqs_enable
//
// Description : HARDCOPYIII DQS Enable
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dqs_enable (
dqsin,
dqsenable,
devclrn,
devpor,
dqsbusout
);
parameter lpm_type = "hardcopyiii_dqs_enable";
// INPUT PORTS
input dqsin;
input dqsenable;
input devclrn;
input devpor;
// OUTPUT PORTS
output dqsbusout;
tri1 devclrn;
tri1 devpor;
wire tmp_dqsbusout;
reg ena_reg;
// BUFFER wrapper
wire dqsin_in;
wire dqsenable_in;
assign dqsin_in = dqsin;
assign dqsenable_in = (dqsenable === 1'b1) ? 1'b1 : 1'b0;
specify
(dqsin => dqsbusout) = (0,0);
(dqsenable => dqsbusout) = (0,0); // annotated on the dqsenable port
endspecify
initial ena_reg = 1'b1;
assign tmp_dqsbusout = ena_reg & dqsin_in;
always @(negedge tmp_dqsbusout or posedge dqsenable_in)
begin
if (dqsenable_in === 1'b1)
ena_reg <= 1'b1;
else
ena_reg <= 1'b0;
end
pmos (dqsbusout, tmp_dqsbusout, 1'b0);
endmodule // hardcopyiii_dqs_enable
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_dqs_enable_ctrl
//
// Description : HARDCOPYIII DQS Enable Control
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dqs_enable_ctrl (
dqsenablein,
clk,
delayctrlin,
phasectrlin,
enaphasetransferreg,
phaseinvertctrl,
devclrn, devpor,
dffin,
dffextenddqsenable,
dqsenableout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter delay_buffer_mode = "high";
parameter level_dqs_enable = "false";
parameter delay_dqs_enable_by_half_cycle = "false";
parameter add_phase_transfer_reg = "false";
parameter invert_phase = "false";
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "hardcopyiii_dqs_enable_ctrl";
// INPUT PORTS
input dqsenablein;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input enaphasetransferreg;
input phaseinvertctrl;
input devclrn;
input devpor;
// OUTPUT PORTS
output dqsenableout;
output dffin;
output dffextenddqsenable; // buried
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// decoded counter
wire [5:0] delayctrl_bin;
// cell delay
integer acell_delay;
integer delay_chain_len;
integer clk_delay;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
wire dqsenablein_reg_q;
wire dqsenablein_level_ena;
// transfer delay
wire dqsenablein_reg_dly;
wire phasetransferdelay_mux_out;
wire dqsenable_delayed_regp;
wire dqsenable_delayed_regn;
wire tmp_dqsenableout;
// BUFFER wrapper
wire dqsenablein_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire enaphasetransferreg_in;
wire phaseinvertctrl_in;
wire devclrn_in, devpor_in;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign dqsenablein_in = (dqsenablein === 1'b1) ? 1'b1 : 1'b0;
assign clk_in = clk;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// no top-level timing delays
// specify
// (dqsenablein => dqsenableout) = (0,0);
// endspecify
// delay chain
hardcopyiii_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// disable data path
hardcopyiii_ddr_io_reg dqsenablein_reg(
.d(dqsenablein_in),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dqsenablein_reg_q)
);
hardcopyiii_ddr_io_reg dqsenable_transfer_reg(
.d(dqsenablein_reg_q),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dqsenablein_reg_dly)
);
// add phase transfer mux
assign phasetransferdelay_mux_out =
(add_phase_transfer_reg == "true") ? dqsenablein_reg_dly :
(add_phase_transfer_reg == "false") ? dqsenablein_reg_q :
(enaphasetransferreg_in === 1'b1) ? dqsenablein_reg_dly : dqsenablein_reg_q;
assign dqsenablein_level_ena = (level_dqs_enable == "true") ? phasetransferdelay_mux_out : dqsenablein_in;
hardcopyiii_ddr_io_reg dqsenableout_reg(
.d(dqsenablein_level_ena),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dqsenable_delayed_regp)
);
hardcopyiii_ddr_io_reg dqsenableout_extend_reg(
.d(dqsenable_delayed_regp),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dqsenable_delayed_regn)
);
assign tmp_dqsenableout = (delay_dqs_enable_by_half_cycle == "false") ? dqsenable_delayed_regp
: (dqsenable_delayed_regp & dqsenable_delayed_regn);
assign dqsenableout = tmp_dqsenableout;
endmodule // hardcopyiii_dqs_enable_ctrl
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_delay_chain
//
// Description : HARDCOPYIII Delay Chain (dynamic adjustable delay chain)
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_delay_chain (
datain,
delayctrlin,
finedelayctrlin,
devclrn,
devpor,
dataout
);
parameter sim_delayctrlin_rising_delay_0 = 0;
parameter sim_delayctrlin_rising_delay_1 = 50;
parameter sim_delayctrlin_rising_delay_2 = 100;
parameter sim_delayctrlin_rising_delay_3 = 150;
parameter sim_delayctrlin_rising_delay_4 = 200;
parameter sim_delayctrlin_rising_delay_5 = 250;
parameter sim_delayctrlin_rising_delay_6 = 300;
parameter sim_delayctrlin_rising_delay_7 = 350;
parameter sim_delayctrlin_rising_delay_8 = 400;
parameter sim_delayctrlin_rising_delay_9 = 450;
parameter sim_delayctrlin_rising_delay_10 = 500;
parameter sim_delayctrlin_rising_delay_11 = 550;
parameter sim_delayctrlin_rising_delay_12 = 600;
parameter sim_delayctrlin_rising_delay_13 = 650;
parameter sim_delayctrlin_rising_delay_14 = 700;
parameter sim_delayctrlin_rising_delay_15 = 750;
parameter sim_delayctrlin_falling_delay_0 = 0;
parameter sim_delayctrlin_falling_delay_1 = 50;
parameter sim_delayctrlin_falling_delay_2 = 100;
parameter sim_delayctrlin_falling_delay_3 = 150;
parameter sim_delayctrlin_falling_delay_4 = 200;
parameter sim_delayctrlin_falling_delay_5 = 250;
parameter sim_delayctrlin_falling_delay_6 = 300;
parameter sim_delayctrlin_falling_delay_7 = 350;
parameter sim_delayctrlin_falling_delay_8 = 400;
parameter sim_delayctrlin_falling_delay_9 = 450;
parameter sim_delayctrlin_falling_delay_10 = 500;
parameter sim_delayctrlin_falling_delay_11 = 550;
parameter sim_delayctrlin_falling_delay_12 = 600;
parameter sim_delayctrlin_falling_delay_13 = 650;
parameter sim_delayctrlin_falling_delay_14 = 700;
parameter sim_delayctrlin_falling_delay_15 = 750;
//new STRATIXIV - ww30.2008
parameter sim_finedelayctrlin_falling_delay_0 = 0 ;
parameter sim_finedelayctrlin_falling_delay_1 = 25 ;
parameter sim_finedelayctrlin_rising_delay_0 = 0 ;
parameter sim_finedelayctrlin_rising_delay_1 = 25 ;
parameter use_finedelayctrlin = "false";
parameter lpm_type = "hardcopyiii_delay_chain";
// parameter removed in rev 1.23
parameter use_delayctrlin = "true";
parameter delay_setting = 0; // <0 - 15>
// INPUT PORTS
input datain;
input [3:0] delayctrlin;
input devclrn;
input devpor;
input finedelayctrlin; //new STRATIXIV - ww30.2008
// OUTPUT PORTS
output dataout;
tri1 devclrn;
tri1 devpor;
// delays
integer dly_table_rising[0:15];
integer dly_table_falling[0:15];
integer finedly_table_rising[0:1];
integer finedly_table_falling[0:1];
integer dly_setting;
integer rising_dly, falling_dly;
reg tmp_dataout;
//Buffer layers
wire datain_in;
wire [3:0] delayctrlin_in;
wire finedelayctrlin_in;
assign datain_in = datain;
specify
(datain => dataout) = (0,0);
endspecify
// filtering X/U etc.
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign finedelayctrlin_in = (finedelayctrlin === 1'b1) ? 1'b1 : 1'b0;
initial
begin
dly_table_rising[0] = sim_delayctrlin_rising_delay_0;
dly_table_rising[1] = sim_delayctrlin_rising_delay_1;
dly_table_rising[2] = sim_delayctrlin_rising_delay_2;
dly_table_rising[3] = sim_delayctrlin_rising_delay_3;
dly_table_rising[4] = sim_delayctrlin_rising_delay_4;
dly_table_rising[5] = sim_delayctrlin_rising_delay_5;
dly_table_rising[6] = sim_delayctrlin_rising_delay_6;
dly_table_rising[7] = sim_delayctrlin_rising_delay_7;
dly_table_rising[8] = sim_delayctrlin_rising_delay_8;
dly_table_rising[9] = sim_delayctrlin_rising_delay_9;
dly_table_rising[10] = sim_delayctrlin_rising_delay_10;
dly_table_rising[11] = sim_delayctrlin_rising_delay_11;
dly_table_rising[12] = sim_delayctrlin_rising_delay_12;
dly_table_rising[13] = sim_delayctrlin_rising_delay_13;
dly_table_rising[14] = sim_delayctrlin_rising_delay_14;
dly_table_rising[15] = sim_delayctrlin_rising_delay_15;
dly_table_falling[0] = sim_delayctrlin_falling_delay_0;
dly_table_falling[1] = sim_delayctrlin_falling_delay_1;
dly_table_falling[2] = sim_delayctrlin_falling_delay_2;
dly_table_falling[3] = sim_delayctrlin_falling_delay_3;
dly_table_falling[4] = sim_delayctrlin_falling_delay_4;
dly_table_falling[5] = sim_delayctrlin_falling_delay_5;
dly_table_falling[6] = sim_delayctrlin_falling_delay_6;
dly_table_falling[7] = sim_delayctrlin_falling_delay_7;
dly_table_falling[8] = sim_delayctrlin_falling_delay_8;
dly_table_falling[9] = sim_delayctrlin_falling_delay_9;
dly_table_falling[10] = sim_delayctrlin_falling_delay_10;
dly_table_falling[11] = sim_delayctrlin_falling_delay_11;
dly_table_falling[12] = sim_delayctrlin_falling_delay_12;
dly_table_falling[13] = sim_delayctrlin_falling_delay_13;
dly_table_falling[14] = sim_delayctrlin_falling_delay_14;
dly_table_falling[15] = sim_delayctrlin_falling_delay_15;
finedly_table_rising[0] = sim_finedelayctrlin_rising_delay_0;
finedly_table_rising[1] = sim_finedelayctrlin_rising_delay_1;
finedly_table_falling[0] = sim_finedelayctrlin_falling_delay_0;
finedly_table_falling[1] = sim_finedelayctrlin_falling_delay_1;
dly_setting = 0;
rising_dly = 0;
falling_dly = 0;
tmp_dataout = 1'bx;
end
always @(delayctrlin_in or finedelayctrlin_in)
begin
if (use_delayctrlin == "false")
dly_setting = delay_setting;
else
dly_setting = delayctrlin_in;
if (use_finedelayctrlin == "true")
begin
rising_dly = dly_table_rising[dly_setting] + finedly_table_rising[finedelayctrlin_in];
falling_dly = dly_table_falling[dly_setting] + finedly_table_falling[finedelayctrlin_in];
end
else
begin
rising_dly = dly_table_rising[dly_setting];
falling_dly = dly_table_falling[dly_setting];
end
end
always @(datain_in)
begin
if (datain_in === 1'b0)
tmp_dataout <= #(falling_dly) datain_in;
else
tmp_dataout <= #(rising_dly) datain_in;
end
assign dataout = tmp_dataout;
endmodule // hardcopyiii_delay_chain
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_io_clock_divider
//
// Description : HARDCOPYIII I/O Clock Divider
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_io_clock_divider (
clk,
phaseselect,
delayctrlin,
phasectrlin,
masterin,
phaseinvertctrl,
devclrn,
devpor,
clkout,
slaveout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0; // <0 - 7>
parameter delay_buffer_mode = "high";
parameter use_masterin = "false"; // new in 1.19
parameter invert_phase = "false";
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "hardcopyiii_io_clock_divider";
// INPUT PORTS
input clk;
input phaseselect;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input phaseinvertctrl;
input masterin;
input devclrn;
input devpor;
// OUTPUT PORTS
output clkout;
output slaveout;
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
wire divided_clk_in;
reg divided_clk;
wire tmp_clkout;
// input buffer layer
wire clk_in, phaseselect_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire masterin_in;
wire phaseinvertctrl_in;
assign clk_in = clk;
assign phaseselect_in = (phaseselect === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign masterin_in = masterin;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
specify
(clk => clkout) = (0,0);
endspecify
// delay chain
hardcopyiii_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = 7;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
initial
divided_clk = 1'b0;
assign divided_clk_in = (use_masterin == "true") ? masterin_in : divided_clk;
always @(posedge delayed_clk)
begin
if (delayed_clk == 'b1)
divided_clk <= ~divided_clk_in;
end
assign tmp_clkout = (phaseselect_in === 1'b1) ? ~divided_clk : divided_clk;
assign clkout = tmp_clkout;
assign slaveout = divided_clk;
endmodule // hardcopyiii_io_clock_divider
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_output_phase_alignment
//
// Description : output phase alignment
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_output_phase_alignment (
datain,
clk,
delayctrlin,
phasectrlin,
areset,
sreset,
clkena,
enaoutputcycledelay,
enaphasetransferreg,
phaseinvertctrl,
delaymode,
dutycycledelayctrlin,
devclrn,
devpor,
dffin,
dff1t,
dffddiodataout,
dataout
);
parameter operation_mode = "ddio_out";
parameter use_phasectrlin = "true";
parameter phase_setting = 0; // <0..10>
parameter delay_buffer_mode = "high";
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter add_output_cycle_delay = "false";
parameter use_delayed_clock = "false"; // new in 1.21
parameter add_phase_transfer_reg = "false"; // <false,true,dynamic>
parameter use_phasectrl_clock = "true"; // new in 1.21
parameter use_primary_clock = "true"; // new in 1.21
parameter invert_phase = "false"; // new in 1.26
parameter phase_setting_for_delayed_clock = 2; // new in 1.28
parameter bypass_input_register = "false"; // new in 1.36
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
// new in STRATIXIV: ww30.2008
parameter duty_cycle_delay_mode = "none";
parameter sim_dutycycledelayctrlin_falling_delay_0 = 0 ;
parameter sim_dutycycledelayctrlin_falling_delay_1 = 25 ;
parameter sim_dutycycledelayctrlin_falling_delay_10 = 250 ;
parameter sim_dutycycledelayctrlin_falling_delay_11 = 275 ;
parameter sim_dutycycledelayctrlin_falling_delay_12 = 300 ;
parameter sim_dutycycledelayctrlin_falling_delay_13 = 325 ;
parameter sim_dutycycledelayctrlin_falling_delay_14 = 350 ;
parameter sim_dutycycledelayctrlin_falling_delay_15 = 375 ;
parameter sim_dutycycledelayctrlin_falling_delay_2 = 50 ;
parameter sim_dutycycledelayctrlin_falling_delay_3 = 75 ;
parameter sim_dutycycledelayctrlin_falling_delay_4 = 100 ;
parameter sim_dutycycledelayctrlin_falling_delay_5 = 125 ;
parameter sim_dutycycledelayctrlin_falling_delay_6 = 150 ;
parameter sim_dutycycledelayctrlin_falling_delay_7 = 175 ;
parameter sim_dutycycledelayctrlin_falling_delay_8 = 200 ;
parameter sim_dutycycledelayctrlin_falling_delay_9 = 225 ;
parameter sim_dutycycledelayctrlin_rising_delay_0 = 0 ;
parameter sim_dutycycledelayctrlin_rising_delay_1 = 25 ;
parameter sim_dutycycledelayctrlin_rising_delay_10 = 250 ;
parameter sim_dutycycledelayctrlin_rising_delay_11 = 275 ;
parameter sim_dutycycledelayctrlin_rising_delay_12 = 300 ;
parameter sim_dutycycledelayctrlin_rising_delay_13 = 325 ;
parameter sim_dutycycledelayctrlin_rising_delay_14 = 350 ;
parameter sim_dutycycledelayctrlin_rising_delay_15 = 375 ;
parameter sim_dutycycledelayctrlin_rising_delay_2 = 50 ;
parameter sim_dutycycledelayctrlin_rising_delay_3 = 75 ;
parameter sim_dutycycledelayctrlin_rising_delay_4 = 100 ;
parameter sim_dutycycledelayctrlin_rising_delay_5 = 125 ;
parameter sim_dutycycledelayctrlin_rising_delay_6 = 150 ;
parameter sim_dutycycledelayctrlin_rising_delay_7 = 175 ;
parameter sim_dutycycledelayctrlin_rising_delay_8 = 200 ;
parameter sim_dutycycledelayctrlin_rising_delay_9 = 225 ;
parameter lpm_type = "hardcopyiii_output_phase_alignment";
// INPUT PORTS
input [1:0] datain;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input areset;
input sreset;
input clkena;
input enaoutputcycledelay;
input enaphasetransferreg;
input phaseinvertctrl;
// new in STRATIXIV: ww30.2008
input delaymode;
input [3:0] dutycycledelayctrlin;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
output [1:0] dffin; // buried port
output [1:0] dff1t; // buried port
output dffddiodataout; // buried port
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals on clock paths
wire clk_in_delayed;
wire clk_in_mux;
wire phasectrl_clkout;
wire phaseinvertctrl_out;
// IO registers
// common
reg adatasdata_in_r; //sync reset - common for transfer and output reg
reg sclr_in_r;
reg sload_in_r;
wire sclr_in;
wire sload_in;
wire adatasdata_in;
reg clrn_in_r; //async reset - common for all registers
reg prn_in_r;
wire datain_q;
wire ddio_datain_q;
wire cycledelay_q;
wire ddio_cycledelay_q;
wire cycledelay_mux_out;
wire ddio_cycledelay_mux_out;
wire bypass_input_reg_mux_out;
wire ddio_bypass_input_reg_mux_out;
// transfer delay now by negative clk
wire transfer_q;
wire ddio_transfer_q;
// Duty Cycle Delay
wire dcd_in;
wire dcd_out;
wire dcd_both;
reg dcd_both_gnd;
reg dcd_both_vcc;
wire dcd_fallnrise;
reg dcd_fallnrise_gnd;
reg dcd_fallnrise_vcc;
integer dcd_table_rising[0:15];
integer dcd_table_falling[0:15];
integer dcd_dly_setting;
integer dcd_rising_dly;
integer dcd_falling_dly;
wire dlyclk_clk;
wire dlyclk_d;
wire dlyclk_q;
wire ddio_dlyclk_d;
wire ddio_dlyclk_q;
wire ddio_out_clk_mux;
wire ddio_out_lo_q;
wire ddio_out_hi_q;
wire dlyclk_clkena_in; // shared
wire dlyclk_extended_q;
wire dlyclk_extended_clk;
wire normal_dataout;
wire extended_dataout;
wire ddio_dataout;
wire tmp_dataout;
// buffer layer
wire [1:0] datain_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire areset_in;
wire sreset_in;
wire clkena_in;
wire enaoutputcycledelay_in;
wire enaphasetransferreg_in;
wire devclrn_in, devpor_in;
wire phaseinvertctrl_in;
wire delaymode_in;
wire [3:0] dutycycledelayctrlin_in;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
assign datain_in = datain;
assign clk_in = clk;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign sreset_in = (sreset === 1'b1) ? 1'b1 : 1'b0;
assign clkena_in = (clkena === 1'b1) ? 1'b1 : 1'b0;
assign enaoutputcycledelay_in = (enaoutputcycledelay === 1'b1) ? 1'b1 : 1'b0;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign delaymode_in = (delaymode === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[0] = (dutycycledelayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[1] = (dutycycledelayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[2] = (dutycycledelayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[3] = (dutycycledelayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
// delay chain for clk_in delay
hardcopyiii_ddr_delay_chain_s m_clk_in_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(clk_in_delayed)
);
defparam m_clk_in_delay_chain.phase_setting = phase_setting_for_delayed_clock;
defparam m_clk_in_delay_chain.use_phasectrlin = "false";
defparam m_clk_in_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_clk_in_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
// clock source for datain and cycle delay registers
assign clk_in_mux = (use_delayed_clock == "true") ? clk_in_delayed : clk_in;
// delay chain for phase control
hardcopyiii_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = (use_primary_clock == "true") ? 10 : 7;
// primary outputs
assign normal_dataout = dlyclk_q;
assign extended_dataout = dlyclk_q | dlyclk_extended_q; // oe port is active low
assign ddio_dataout = (ddio_out_clk_mux === 1'b1) ? ddio_out_hi_q : ddio_out_lo_q;
assign tmp_dataout = (operation_mode == "ddio_out") ? ddio_dataout :
(operation_mode == "extended_oe" || operation_mode == "extended_rtena") ? extended_dataout :
(operation_mode == "output" || operation_mode == "oe" || operation_mode == "rtena") ? normal_dataout
: 1'bz;
assign dataout = tmp_dataout;
assign #1 ddio_out_clk_mux = dlyclk_clk; // symbolic T4 to remove glitch on data_h
assign #2 ddio_out_lo_q = dlyclk_q; // symbolic 2 T4 to remove glitch on data_l
assign ddio_out_hi_q = ddio_dlyclk_q;
// resolve reset/areset modes
initial begin
adatasdata_in_r = (sync_mode == "preset") ? 1'b1: 1'b0;
sclr_in_r = 1'b0;
sload_in_r = 1'b0;
clrn_in_r = 1'b1;
prn_in_r = 1'b1;
end
always @(areset_in)
begin
if (async_mode == "clear")
begin
clrn_in_r = ~areset_in;
end
else if (async_mode == "preset")
begin
prn_in_r = ~areset_in;
end
end
always @(sreset_in)
begin
if (sync_mode == "clear")
begin
sclr_in_r = sreset_in;
end
else if(sync_mode == "preset")
begin
sload_in_r = sreset_in;
end
end
assign sclr_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b0 : sclr_in_r;
assign sload_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b0 : sload_in_r;
assign adatasdata_in = adatasdata_in_r;
assign dlyclk_clkena_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b1 : clkena_in;
// Datain Register
hardcopyiii_ddr_io_reg datain_reg(
.d(datain_in[0]),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(datain_q)
);
defparam datain_reg.power_up = power_up;
// DDIO Datain Register
hardcopyiii_ddr_io_reg ddio_datain_reg(
.d(datain_in[1]),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(ddio_datain_q)
);
defparam ddio_datain_reg.power_up = power_up;
// Cycle Delay Register
hardcopyiii_ddr_io_reg cycledelay_reg(
.d(datain_q),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_q)
);
defparam cycledelay_reg.power_up = power_up;
// DDIO Cycle Delay Register
hardcopyiii_ddr_io_reg ddio_cycledelay_reg(
.d(ddio_datain_q),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_cycledelay_q)
);
defparam ddio_cycledelay_reg.power_up = power_up;
// enaoutputcycledelay data path mux
assign cycledelay_mux_out = (add_output_cycle_delay == "true") ? cycledelay_q :
(add_output_cycle_delay == "false") ? datain_q :
(enaoutputcycledelay_in === 1'b1) ? cycledelay_q : datain_q;
// input register bypass mux
assign bypass_input_reg_mux_out = (bypass_input_register == "true") ? datain_in[0] : cycledelay_mux_out;
//assign #300 transfer_q = cycledelay_mux_out;
// transfer delay is implemented with negative register in rev1.26
hardcopyiii_ddr_io_reg transferdelay_reg(
.d(bypass_input_reg_mux_out),
.clk(~clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(transfer_q)
);
defparam transferdelay_reg.power_up = power_up;
// add phase transfer (true/false/dynamic) data path mux
assign dlyclk_d = (add_phase_transfer_reg == "true") ? transfer_q :
(add_phase_transfer_reg == "false") ? bypass_input_reg_mux_out :
(enaphasetransferreg_in === 1'b1) ? transfer_q : bypass_input_reg_mux_out;
// clock mux for the output register
assign phaseinvertctrl_out = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// Duty Cycle Delay
assign dcd_in = (use_phasectrl_clock == "true") ? phaseinvertctrl_out : clk_in_mux;
initial
begin
dcd_table_rising[0] = sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising[1] = sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising[2] = sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising[3] = sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising[4] = sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising[5] = sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising[6] = sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising[7] = sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising[8] = sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising[9] = sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising[10] = sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising[11] = sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising[12] = sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising[13] = sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising[14] = sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising[15] = sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling[0] = sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling[1] = sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling[2] = sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling[3] = sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling[4] = sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling[5] = sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling[6] = sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling[7] = sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling[8] = sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling[9] = sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling[10] = sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling[11] = sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling[12] = sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling[13] = sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling[14] = sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling[15] = sim_dutycycledelayctrlin_falling_delay_15;
dcd_dly_setting = 0;
dcd_rising_dly = 0;
dcd_falling_dly = 0;
end
always @(dutycycledelayctrlin_in)
begin
dcd_dly_setting = dutycycledelayctrlin_in;
dcd_rising_dly = dcd_table_rising[dcd_dly_setting];
dcd_falling_dly = dcd_table_falling[dcd_dly_setting];
end
always @(dcd_in)
begin
dcd_both_gnd <= dcd_in;
if (dcd_in === 1'b0)
begin
dcd_both_vcc <= #(dcd_falling_dly) dcd_in;
dcd_fallnrise_gnd <= #(dcd_falling_dly) dcd_in;
dcd_fallnrise_vcc <= dcd_in;
end
else
begin
dcd_both_vcc <= #(dcd_rising_dly) dcd_in;
dcd_fallnrise_gnd <= dcd_in;
dcd_fallnrise_vcc <= #(dcd_rising_dly) dcd_in;
end
end
assign dcd_both = (delaymode_in === 1'b1) ? dcd_both_vcc : dcd_both_gnd;
assign dcd_fallnrise = (delaymode_in === 1'b1) ? dcd_fallnrise_vcc : dcd_fallnrise_gnd;
assign dlyclk_clk = (duty_cycle_delay_mode == "both") ? dcd_both :
(duty_cycle_delay_mode == "fallnrise") ? dcd_fallnrise : dcd_in;
// Output Register clocked by phasectrl_clk
hardcopyiii_ddr_io_reg dlyclk_reg(
.d(dlyclk_d),
.clk(dlyclk_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_q)
);
defparam dlyclk_reg.power_up = power_up;
// enaoutputcycledelay data path mux - DDIO
assign ddio_cycledelay_mux_out = (add_output_cycle_delay == "true") ? ddio_cycledelay_q :
(add_output_cycle_delay == "false") ? ddio_datain_q :
(enaoutputcycledelay_in === 1'b1) ? ddio_cycledelay_q : ddio_datain_q;
// input register bypass mux
assign ddio_bypass_input_reg_mux_out = (bypass_input_register == "true") ? datain_in[1] : ddio_cycledelay_mux_out;
//assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
// transfer delay is implemented with negative register in rev1.26
hardcopyiii_ddr_io_reg ddio_transferdelay_reg(
.d(ddio_bypass_input_reg_mux_out),
.clk(~clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_transfer_q)
);
defparam ddio_transferdelay_reg.power_up = power_up;
// add phase transfer data path mux
assign ddio_dlyclk_d = (add_phase_transfer_reg == "true") ? ddio_transfer_q :
(add_phase_transfer_reg == "false") ? ddio_bypass_input_reg_mux_out :
(enaphasetransferreg_in === 1'b1) ? ddio_transfer_q : ddio_bypass_input_reg_mux_out;
// Output Register clocked by phasectrl_clk
hardcopyiii_ddr_io_reg ddio_dlyclk_reg(
.d(ddio_dlyclk_d),
.clk(dlyclk_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_dlyclk_q)
);
defparam ddio_dlyclk_reg.power_up = power_up;
// Extension Register
assign dlyclk_extended_clk = ~dlyclk_clk;
hardcopyiii_ddr_io_reg dlyclk_extended_reg(
.d(dlyclk_q),
.clk(dlyclk_extended_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_extended_q)
);
defparam dlyclk_extended_reg.power_up = power_up;
endmodule // hardcopyiii_output_phase_alignment
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_input_phase_alignment
//
// Description : input phase alignment
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_input_phase_alignment (
datain,
clk,
delayctrlin,
phasectrlin,
areset,
enainputcycledelay,
enaphasetransferreg, // new in 1.19
phaseinvertctrl,
devclrn,
devpor,
dffin,
dff1t,
dataout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter delay_buffer_mode = "high";
parameter power_up = "low";
parameter async_mode = "none";
parameter add_input_cycle_delay = "false";
parameter bypass_output_register = "false";
parameter add_phase_transfer_reg = "false"; // new in 1.19
parameter invert_phase = "false"; // new in 1.26
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "hardcopyiii_input_phase_alignment";
input datain;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input areset;
input enainputcycledelay;
input enaphasetransferreg;
input phaseinvertctrl;
input devclrn;
input devpor;
output dataout;
output dffin; // buried port
output dff1t; // buried port
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
// IO registers
// common
reg adatasdata_in_r;
reg aload_in_r;
wire datain_q;
wire cycledelay_q;
wire cycledelay_mux_out;
wire cycledelay_mux_out_dly;
wire dlyclk_d;
wire dlyclk_q;
wire tmp_dataout;
// buffer layer
wire datain_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire areset_in;
wire enainputcycledelay_in;
wire enaphasetransferreg_in;
wire devclrn_in, devpor_in;
wire phaseinvertctrl_in;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign datain_in = (datain === 1'b1) ? 1'b1 : 1'b0;
assign clk_in = clk;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign enainputcycledelay_in = (enainputcycledelay === 1'b1) ? 1'b1 : 1'b0;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// delay chain
hardcopyiii_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = 7;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// primary output
assign dataout = tmp_dataout;
assign tmp_dataout = (bypass_output_register == "true") ? dlyclk_d : dlyclk_q;
// add phase transfer data path mux
assign dlyclk_d = (add_phase_transfer_reg == "true") ? cycledelay_mux_out_dly :
(add_phase_transfer_reg == "false") ? cycledelay_mux_out :
(enaphasetransferreg_in === 1'b1) ? cycledelay_mux_out_dly : cycledelay_mux_out;
// enaoutputcycledelay data path mux
assign cycledelay_mux_out = (add_input_cycle_delay == "true") ? cycledelay_q :
(add_input_cycle_delay == "false") ? datain_q :
(enainputcycledelay_in === 1'b1) ? cycledelay_q : datain_q;
// resolve reset modes
always @(areset_in)
begin
if(async_mode == "clear")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b0;
end
else if(async_mode == "preset")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b1;
end
else // async_mode == "none"
begin
aload_in_r = 1'b0;
adatasdata_in_r = 1'b0;
end
end
// Datain Register
hardcopyiii_ddr_io_reg datain_reg(
.d(datain_in),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(datain_q)
);
defparam datain_reg.power_up = power_up;
// Cycle Delay Register
hardcopyiii_ddr_io_reg cycledelay_reg(
.d(datain_q),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_q)
);
defparam cycledelay_reg.power_up = power_up;
// assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
// Transfer Register - clocked by negative edge
hardcopyiii_ddr_io_reg transfer_reg(
.d(cycledelay_mux_out),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_mux_out_dly)
);
defparam transfer_reg.power_up = power_up;
// Register clocked by actually by clk_in
hardcopyiii_ddr_io_reg dlyclk_reg(
.d(dlyclk_d),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_q)
);
defparam dlyclk_reg.power_up = power_up;
endmodule // hardcopyiii_input_phase_alignment
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_half_rate_input
//
// Description : HARDCOPYIII half rate input
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_half_rate_input (
datain,
directin,
clk,
areset,
dataoutbypass,
devclrn,
devpor,
dffin,
dataout
);
parameter power_up = "low";
parameter async_mode = "none";
parameter use_dataoutbypass = "false";
parameter lpm_type = "hardcopyiii_half_rate_input";
input [1:0] datain;
input directin;
input clk;
input areset;
input dataoutbypass;
input devclrn;
input devpor;
output [3:0] dataout;
output [1:0] dffin; // buried
tri1 devclrn;
tri1 devpor;
// delayed version to ensure one cycle of latency in functional as expected
wire [1:0] datain_in;
// IO registers
// common
wire neg_clk_in;
reg adatasdata_in_r;
reg aload_in_r;
// low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
// high_bank = {3, 2} - output of register datain at rising
wire [1:0] high_bank;
wire [1:0] low_bank;
wire low_bank_low;
wire low_bank_high;
wire high_bank_low;
wire high_bank_high;
wire [1:0] dataout_reg_n;
wire [3:0] tmp_dataout;
// buffer layer
wire [1:0] datain_ipd;
wire directin_in;
wire clk_in;
wire areset_in;
wire dataoutbypass_in;
wire devclrn_in, devpor_in;
assign datain_ipd = datain;
assign directin_in = directin;
assign clk_in = clk;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign dataoutbypass_in = (dataoutbypass === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// primary input
assign #2 datain_in = datain_ipd;
// primary output
assign dataout = tmp_dataout;
assign tmp_dataout[3] = (dataoutbypass_in === 1'b0 && use_dataoutbypass == "true") ? directin_in : high_bank_high;
assign tmp_dataout[2] = (dataoutbypass_in === 1'b0 && use_dataoutbypass == "true") ? directin_in : high_bank_low;
assign tmp_dataout[1] = low_bank[1];
assign tmp_dataout[0] = low_bank[0];
assign low_bank = {low_bank_high, low_bank_low};
assign high_bank = {high_bank_high, high_bank_low};
// resolve reset modes
always @(areset_in)
begin
if(async_mode == "clear")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b0;
end
else if(async_mode == "preset")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b1;
end
else // async_mode == "none"
begin
aload_in_r = 1'b0;
adatasdata_in_r = 1'b0;
end
end
assign neg_clk_in = ~clk_in;
// datain_1 - H
hardcopyiii_ddr_io_reg reg1_h(
.d(datain_in[1]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(high_bank_high)
);
defparam reg1_h.power_up = power_up;
// datain_0 - H
hardcopyiii_ddr_io_reg reg0_h(
.d(datain_in[0]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(high_bank_low)
);
defparam reg0_h.power_up = power_up;
// datain_1 - L (n)
hardcopyiii_ddr_io_reg reg1_l_n(
.d(datain_in[1]),
.clk(neg_clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dataout_reg_n[1])
);
defparam reg1_l_n.power_up = power_up;
// datain_1 - L
hardcopyiii_ddr_io_reg reg1_l(
.d(dataout_reg_n[1]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(low_bank_high)
);
defparam reg1_l.power_up = power_up;
// datain_0 - L (n)
hardcopyiii_ddr_io_reg reg0_l_n(
.d(datain_in[0]),
.clk(neg_clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dataout_reg_n[0])
);
defparam reg0_l_n.power_up = power_up;
// datain_0 - L
hardcopyiii_ddr_io_reg reg0_l(
.d(dataout_reg_n[0]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(low_bank_low)
);
defparam reg0_l.power_up = power_up;
endmodule // hardcopyiii_half_rate_input
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_io_config
//
// Description : HARDCOPYIII I/O Configuration Register
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_io_config (
datain,
clk,
ena,
update,
devclrn,
devpor,
padtoinputregisterdelaysetting,
outputdelaysetting1,
outputdelaysetting2,
dutycycledelaymode,
dutycycledelaysettings,
outputfinedelaysetting1,
outputfinedelaysetting2,
outputonlydelaysetting2,
outputonlyfinedelaysetting2,
padtoinputregisterfinedelaysetting,
dataout
);
parameter enhanced_mode = "false";
parameter lpm_type = "hardcopyiii_io_config";
input datain;
input clk;
input ena;
input update;
input devclrn;
input devpor;
output [3:0] padtoinputregisterdelaysetting;
output [3:0] outputdelaysetting1;
output [2:0] outputdelaysetting2;
output dataout;
// new STRATIXIV: ww30.2008
output dutycycledelaymode;
output [3:0] dutycycledelaysettings;
output outputfinedelaysetting1;
output outputfinedelaysetting2;
output [2:0] outputonlydelaysetting2;
output outputonlyfinedelaysetting2;
output padtoinputregisterfinedelaysetting;
tri1 devclrn;
tri1 devpor;
reg [10:0] shift_reg;
reg [10:0] output_reg;
wire tmp_dataout;
wire [10:0] tmp_output;
reg [22:0] enhance_shift_reg;
reg [22:0] enhance_output_reg;
wire [22:0] enhance_tmp_output;
// buffer layer
wire datain_in;
wire clk_in;
wire ena_in;
wire update_in;
wire devclrn_in, devpor_in;
assign datain_in = datain;
assign clk_in = clk;
assign ena_in = (ena === 1'b1) ? 1'b1 : 1'b0;
assign update_in = (update === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (dataout +: tmp_dataout)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
// DRIVERs FOR outputs
and (dataout, tmp_dataout, 1'b1);
// primary outputs
assign tmp_dataout = (enhanced_mode == "true") ? enhance_shift_reg[22] : shift_reg[10];
// bit order changed in wys revision 1.32
assign outputdelaysetting1 = (enhanced_mode == "true") ? enhance_tmp_output[3:0] : tmp_output[3:0];
assign outputdelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[6:4] : tmp_output[6:4];
assign padtoinputregisterdelaysetting = (enhanced_mode == "true") ? enhance_tmp_output[10:7] : tmp_output[10:7];
assign outputfinedelaysetting1 = (enhanced_mode == "true") ? enhance_tmp_output[11] : 1'b0;
assign outputfinedelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[12] : 1'b0;
assign padtoinputregisterfinedelaysetting = (enhanced_mode == "true") ? enhance_tmp_output[13] : 1'b0;
assign outputonlyfinedelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[14] : 1'b0;
assign outputonlydelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[17:15] : 3'b000;
assign dutycycledelaymode = (enhanced_mode == "true") ? enhance_tmp_output[18] : 1'b0;
assign dutycycledelaysettings = (enhanced_mode == "true") ? enhance_tmp_output[22:19] : 4'h0;
assign tmp_output = output_reg;
assign enhance_tmp_output = enhance_output_reg;
initial
begin
shift_reg = 'b0;
output_reg = 'b0;
enhance_shift_reg = 'b0;
enhance_output_reg = 'b0;
end
always @(posedge clk_in)
begin
if (ena_in === 1'b1)
begin
shift_reg[0] <= datain_in;
shift_reg[10:1] <= shift_reg[9:0];
enhance_shift_reg[0] <= datain_in;
enhance_shift_reg[22:1] <= enhance_shift_reg[21:0];
end
end
always @(posedge clk_in)
begin
if (update_in === 1'b1)
begin
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end
end
endmodule // hardcopyiii_io_config
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_dqs_config
//
// Description : HARDCOPYIII DQS Configuration Register
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_dqs_config (
datain,
clk,
ena,
update,
devclrn,
devpor,
dqsbusoutdelaysetting,
dqsinputphasesetting,
dqsenablectrlphasesetting,
dqsoutputphasesetting,
dqoutputphasesetting,
resyncinputphasesetting,
dividerphasesetting,
enaoctcycledelaysetting,
enainputcycledelaysetting,
enaoutputcycledelaysetting,
dqsenabledelaysetting,
octdelaysetting1,
octdelaysetting2,
enadataoutbypass,
enadqsenablephasetransferreg, // new in 1.23
enaoctphasetransferreg, // new in 1.23
enaoutputphasetransferreg, // new in 1.23
enainputphasetransferreg, // new in 1.23
resyncinputphaseinvert, // new in 1.26
dqsenablectrlphaseinvert, // new in 1.26
dqoutputphaseinvert, // new in 1.26
dqsoutputphaseinvert, // new in 1.26
dqsbusoutfinedelaysetting,
dqsenablefinedelaysetting,
dataout
);
parameter enhanced_mode = "false";
parameter lpm_type = "hardcopyiii_dqs_config";
// INPUT PORTS
input datain;
input clk;
input ena;
input update;
input devclrn;
input devpor;
// OUTPUT PORTS
output [3:0] dqsbusoutdelaysetting;
output [2:0] dqsinputphasesetting;
output [3:0] dqsenablectrlphasesetting;
output [3:0] dqsoutputphasesetting;
output [3:0] dqoutputphasesetting;
output [3:0] resyncinputphasesetting;
output dividerphasesetting;
output enaoctcycledelaysetting;
output enainputcycledelaysetting;
output enaoutputcycledelaysetting;
output [2:0] dqsenabledelaysetting;
output [3:0] octdelaysetting1;
output [2:0] octdelaysetting2;
output enadataoutbypass;
output enadqsenablephasetransferreg; // new in 1.23
output enaoctphasetransferreg; // new in 1.23
output enaoutputphasetransferreg; // new in 1.23
output enainputphasetransferreg; // new in 1.23
output resyncinputphaseinvert; // new in 1.26
output dqsenablectrlphaseinvert; // new in 1.26
output dqoutputphaseinvert; // new in 1.26
output dqsoutputphaseinvert; // new in 1.26
output dqsbusoutfinedelaysetting; // new in 1.39
output dqsenablefinedelaysetting; // new in 1.39
output dataout;
tri1 devclrn;
tri1 devpor;
reg [47:0] shift_reg;
reg [47:0] output_reg;
wire tmp_dataout;
wire [47:0] tmp_output;
// buffer layer
wire datain_in;
wire clk_in;
wire ena_in;
wire update_in;
wire devclrn_in, devpor_in;
assign datain_in = datain;
assign clk_in = clk;
assign ena_in = (ena === 1'b1) ? 1'b1 : 1'b0;
assign update_in = (update === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (dataout +: tmp_dataout)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
// DRIVERs FOR outputs
and (dataout, tmp_dataout, 1'b1);
// primary outputs
assign tmp_dataout = (enhanced_mode == "true") ? shift_reg[47] : shift_reg[45];
assign dqsbusoutdelaysetting = tmp_output[3 : 0];
assign dqsinputphasesetting = tmp_output[6 : 4];
assign dqsenablectrlphasesetting = tmp_output[10 : 7];
assign dqsoutputphasesetting = tmp_output[14 : 11];
assign dqoutputphasesetting = tmp_output[18 : 15];
assign resyncinputphasesetting = tmp_output[22 : 19];
assign dividerphasesetting = tmp_output[23];
assign enaoctcycledelaysetting = tmp_output[24];
assign enainputcycledelaysetting = tmp_output[25];
assign enaoutputcycledelaysetting= tmp_output[26];
assign dqsenabledelaysetting = tmp_output[29 : 27];
assign octdelaysetting1 = tmp_output[33 : 30];
assign octdelaysetting2 = tmp_output[36 : 34];
assign enadataoutbypass = tmp_output[37];
assign enadqsenablephasetransferreg = tmp_output[38]; // new in 1.23
assign enaoctphasetransferreg = tmp_output[39]; // new in 1.23
assign enaoutputphasetransferreg = tmp_output[40]; // new in 1.23
assign enainputphasetransferreg = tmp_output[41]; // new in 1.23
assign resyncinputphaseinvert = tmp_output[42]; // new in 1.26
assign dqsenablectrlphaseinvert = tmp_output[43]; // new in 1.26
assign dqoutputphaseinvert = tmp_output[44]; // new in 1.26
assign dqsoutputphaseinvert = tmp_output[45]; // new in 1.26
// new in STRATIXIV: ww30.2008
assign dqsbusoutfinedelaysetting = (enhanced_mode == "true") ? tmp_output[46] : 1'b0;
assign dqsenablefinedelaysetting = (enhanced_mode == "true") ? tmp_output[47] : 1'b0;
assign tmp_output = output_reg;
initial
begin
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge clk_in)
begin
if (ena_in === 1'b1)
begin
shift_reg[0] <= datain_in;
shift_reg[47:1] <= shift_reg[46:0];
end
end
always @(posedge clk_in)
begin
if (update_in === 1'b1)
output_reg <= shift_reg;
end
endmodule // hardcopyiii_dqs_config
// end_ddr
// --------------------------------------------------------------------
// Module Name: hardcopyiii_rt_sm
// Description: Parallel Termination State Machine
// --------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_rt_sm (
rup,rdn,clk,clken,clr,rtena,rscaldone,
rtoffsetp,rtoffsetn,caldone,
sel_rup_vref,sel_rdn_vref
);
input rup;
input rdn;
input clk;
input clken;
input clr;
input rtena;
input rscaldone;
output [3:0] rtoffsetp;
output [3:0] rtoffsetn;
output caldone;
output [2:0] sel_rup_vref;
output [2:0] sel_rdn_vref;
parameter HARDCOPYIII_RTOCT_WAIT = 5'b00000;
parameter RUP_VREF_M_RDN_VER_M = 5'b00001;
parameter RUP_VREF_L_RDN_VER_L = 5'b00010;
parameter RUP_VREF_H_RDN_VER_H = 5'b00011;
parameter RUP_VREF_L_RDN_VER_H = 5'b00100;
parameter RUP_VREF_H_RDN_VER_L = 5'b00101;
parameter HARDCOPYIII_RTOCT_INC_PN = 5'b01000;
parameter HARDCOPYIII_RTOCT_DEC_PN = 5'b01001;
parameter HARDCOPYIII_RTOCT_INC_P = 5'b01010;
parameter HARDCOPYIII_RTOCT_DEC_P = 5'b01011;
parameter HARDCOPYIII_RTOCT_INC_N = 5'b01100;
parameter HARDCOPYIII_RTOCT_DEC_N = 5'b01101;
parameter HARDCOPYIII_RTOCT_SWITCH_REG = 5'b10001;
parameter HARDCOPYIII_RTOCT_DONE = 5'b11111;
// interface
wire nclr; // for synthesis
wire rtcalclk;
// sm
reg [4:0] current_state, next_state;
reg sel_rup_vref_h_d, sel_rup_vref_h;
reg sel_rup_vref_m_d, sel_rup_vref_m;
reg sel_rup_vref_l_d, sel_rup_vref_l;
reg sel_rdn_vref_h_d, sel_rdn_vref_h;
reg sel_rdn_vref_m_d, sel_rdn_vref_m;
reg sel_rdn_vref_l_d, sel_rdn_vref_l;
reg switch_region_d, switch_region;
reg cmpup, cmpdn;
reg rt_sm_done_d, rt_sm_done;
// cnt
reg [2:0] p_cnt_d, p_cnt, n_cnt_d, n_cnt;
reg p_cnt_sub_d,p_cnt_sub,n_cnt_sub_d,n_cnt_sub;
// primary output - MSB is sign bit
assign rtoffsetp = {p_cnt_sub, p_cnt};
assign rtoffsetn = {n_cnt_sub, n_cnt};
assign caldone = (rtena == 1'b1) ? rt_sm_done : 1'b1;
assign sel_rup_vref = {sel_rup_vref_h,sel_rup_vref_m,sel_rup_vref_l};
assign sel_rdn_vref = {sel_rdn_vref_h,sel_rdn_vref_m,sel_rdn_vref_l};
// input interface
assign nclr = ~clr;
assign rtcalclk = (rscaldone & clken & ~caldone & clk);
// latch registers - rising on everything except cmpup and cmpdn
// cmpup/dn
always @(negedge rtcalclk or negedge nclr)
begin
if (nclr == 1'b0)
begin
cmpup <= 1'b0;
cmpdn <= 1'b0;
end
else
begin
cmpup <= rup;
cmpdn <= rdn;
end
end
// other regisers
always @(posedge rtcalclk or posedge clr)
begin
if (clr == 1'b1)
begin
current_state <= HARDCOPYIII_RTOCT_WAIT;
switch_region <= 1'b0;
rt_sm_done <= 1'b0;
p_cnt <= 3'b000;
p_cnt_sub <= 1'b0;
n_cnt <= 3'b000;
n_cnt_sub <= 1'b0;
sel_rup_vref_h <= 1'b0;
sel_rup_vref_m <= 1'b1;
sel_rup_vref_l <= 1'b0;
sel_rdn_vref_h <= 1'b0;
sel_rdn_vref_m <= 1'b1;
sel_rdn_vref_l <= 1'b0;
end
else
begin
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
end
end
// state machine
always @(current_state or rtena or cmpup or cmpdn or p_cnt or n_cnt or switch_region)
begin
p_cnt_d = p_cnt;
n_cnt_d = n_cnt;
p_cnt_sub_d = 1'b0;
n_cnt_sub_d = 1'b0;
case (current_state)
HARDCOPYIII_RTOCT_WAIT :
if (rtena == 1'b0)
next_state = HARDCOPYIII_RTOCT_WAIT;
else
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
RUP_VREF_M_RDN_VER_M :
if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_INC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DEC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
RUP_VREF_L_RDN_VER_L :
if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DONE;
end
else if (cmpup == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_DEC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_INC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
end
RUP_VREF_H_RDN_VER_H :
if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_DONE;
end
else if (cmpup == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_INC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DEC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
end
RUP_VREF_L_RDN_VER_H :
if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_DONE;
end
else if (cmpup == 1'b1 && switch_region == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DEC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b0 && switch_region == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DEC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if ((switch_region == 1'b0) && (cmpup == 1'b0 || cmpdn == 1'b1))
begin
next_state = HARDCOPYIII_RTOCT_SWITCH_REG;
switch_region_d = 1'b1;
end
RUP_VREF_H_RDN_VER_L :
if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DONE;
end
else if (cmpup == 1'b1 && switch_region == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_INC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && switch_region == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_INC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
end
else if ((switch_region == 1'b0) && (cmpup == 1'b1 || cmpdn == 1'b0))
begin
next_state = HARDCOPYIII_RTOCT_SWITCH_REG;
switch_region_d = 1'b1;
end
HARDCOPYIII_RTOCT_INC_PN :
if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = HARDCOPYIII_RTOCT_INC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
HARDCOPYIII_RTOCT_DEC_PN :
if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DEC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
HARDCOPYIII_RTOCT_INC_P,HARDCOPYIII_RTOCT_DEC_P,HARDCOPYIII_RTOCT_INC_N,HARDCOPYIII_RTOCT_DEC_N :
if (switch_region == 1'b1)
begin
next_state = HARDCOPYIII_RTOCT_DONE;
end
else if (switch_region == 1'b0)
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
HARDCOPYIII_RTOCT_SWITCH_REG :
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
HARDCOPYIII_RTOCT_DONE :
begin
next_state = HARDCOPYIII_RTOCT_DONE;
rt_sm_done_d = 1'b1;
end
default :
next_state = HARDCOPYIII_RTOCT_WAIT;
endcase // case(current_state)
end // always
// initial registers for simulations
initial begin
current_state = HARDCOPYIII_RTOCT_WAIT;
next_state = HARDCOPYIII_RTOCT_WAIT;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_h = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_m = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rup_vref_l = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_h = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_m = 1'b1;
sel_rdn_vref_l_d = 1'b0;
sel_rdn_vref_l = 1'b0;
switch_region_d = 1'b0;
switch_region = 1'b0;
cmpup = 1'b0;
cmpdn = 1'b0;
rt_sm_done_d = 1'b0;
rt_sm_done = 1'b0;
p_cnt = 1'b0;
n_cnt = 1'b0;
p_cnt_sub = 1'b0;
n_cnt_sub = 1'b0;
end
endmodule
// --------------------------------------------------------------------
// Module Name: hardcopyiii_termination_aux_clock_div
// Description: auxilary clock divider
// --------------------------------------------------------------------
`timescale 1 ps / 1 ps
module hardcopyiii_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges,m;
reg [2*extra_latency:0] div_n_register;
initial
begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(posedge clk or negedge clk or posedge reset)
begin
if (reset === 1'b1)
begin
clk_edges = -1;
div_n_register <= 'b0;
end
else
begin
if (clk_edges == -1)
begin
div_n_register[0] <= clk;
if (clk == 1'b1)
clk_edges = 0;
end
else if (clk_edges % clk_divide_by == 0)
div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1)
clk_edges = (clk_edges + 1) % (2*clk_divide_by) ;
end
for (m = 0; m < 2*extra_latency; m=m+1)
div_n_register[m+1] <= div_n_register[m];
end
assign clkout = div_n_register[2*extra_latency];
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_termination
//
// Description : HARDCOPYIII Termination Atom
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_termination (
rup,rdn,terminationclock,terminationclear,terminationenable,
serializerenable,terminationcontrolin,
scanin, scanen,
otherserializerenable,
devclrn,devpor,
incrup,incrdn,
serializerenableout,
terminationcontrol,terminationcontrolprobe,
scanout,
shiftregisterprobe
);
parameter runtime_control = "false";
parameter allow_serial_data_from_core = "false";
parameter power_down = "true";
parameter test_mode = "false";
parameter enable_parallel_termination = "false";
parameter enable_calclk_divider= "false"; // replaced by below to remove
parameter clock_divider_enable = "false";
parameter enable_pwrupmode_enser_for_usrmode = "false"; // to remove
parameter bypass_enser_logic = "false"; // to remove
parameter bypass_rt_calclk = "false"; //RTEST3
parameter enable_rt_scan_mode = "false"; // to remove
parameter enable_loopback = "false";
parameter force_rtcalen_for_pllbiasen = "false";
parameter enable_rt_sm_loopback = "false"; // RTEST4
parameter select_vrefl_values = 0;
parameter select_vrefh_values = 0;
parameter divide_intosc_by = 2;
parameter use_usrmode_clear_for_configmode = "false";
parameter lpm_type = "hardcopyiii_termination";
input rup;
input rdn;
input terminationclock;
input terminationclear;
input terminationenable;
input serializerenable; // ENSERUSR
input terminationcontrolin;
input scanin; // to remove
input scanen;
input [8:0] otherserializerenable;
input devclrn;
input devpor;
output incrup;
output incrdn;
output serializerenableout;
output terminationcontrol;
output terminationcontrolprobe;
output shiftregisterprobe;
output scanout;
tri1 devclrn;
tri1 devpor;
// HW outputs
wire compout_rup_core, compout_rdn_core;
wire ser_data_io, ser_data_core;
// HW inputs
wire usr_clk, cal_clk, rscal_clk, cal_clken, cal_nclr;
// gated user control
reg enserusr_reg, clkenusr_reg, nclrusr_reg; // registered by neg clk
wire enserusr_gated; // (enserusr & !clkenusr) - for P2S, S2P to shift
wire clkenusr_gated; // (enserusr & clkenusr) - for calibration
wire nclrusr_gated; // (enserusr | nclrusr): enserusr = 1 forces no clear
// clk divider
wire clkdiv_out;
// generating calclk and clkenout - 1 cycle latency
reg calclken_reg;
//wire clkenout;
// legality check on enser
reg enser_checked;
// Shift Register
reg [6:0] sreg_bit_out;
reg sreg_bit_BIT_0;
reg sreg_vshift_bit_out;
reg sreg_bit0_next;
reg sreg_vshift_bit_tmp;
reg sreg_rscaldone_prev, sreg_rscaldone_prev1, sregn_rscaldone_out;
reg sreg_bit6_prev;
// nreg before SA-ADC
wire regn_rup_in, regn_rdn_in;
reg [6:0] regn_compout_rup, regn_compout_rdn;
reg regn_compout_rup_extra, regn_compout_rdn_extra; // extra is bit[8] accomodate last move
// SA-ADC
wire [6:0] sa_octcaln_out_tmp; // this + _extra ==> code
wire [6:0] sa_octcalp_out_tmp;
wire [6:0] sa_octcaln_out_tmp_extra;
wire [6:0] sa_octcalp_out_tmp_extra;
wire [6:0] sa_octcaln_out; // RUP - NMOS
wire [6:0] sa_octcalp_out; // RDN - PMOS
wire [6:0] sa_octcaln_in, sa_octcalp_in;
// ENSER
wire enser_out;
wire enser_gen_out;
reg [5:0] enser_cnt;
reg enser_gen_usr_out;
// RT State Machine
wire rtsm_rup_in, rtsm_rdn_in;
wire rtsm_rtena_in, rtsm_rscaldone_in;
wire rtsm_caldone_out;
wire [3:0] rtsm_rtoffsetp_out, rtsm_rtoffsetn_out;
wire [2:0] rtsm_sel_rup_vref_out, rtsm_sel_rdn_vref_out;
// RT State Machine Scan Chain
wire rtsm_sc_clk;
wire rtsm_sc_in;
reg [17:0] rtsm_sc_out_reg;
wire [17:0] rtsm_sc_out_reg_d;
wire [17:0] rtsm_sc_lpbk_mux;
// RT Adder/Sub
wire [6:0] rtas_rs_rpcdp_in, rtas_rs_rpcdn_in;
wire [6:0] rtas_rtoffsetp_in, rtas_rtoffsetn_in;
wire [6:0] rtas_rs_rpcdp_out, rtas_rs_rpcdn_out;
wire [6:0] rtas_rt_rpcdp_out, rtas_rt_rpcdn_out;
// P2S
wire [6:0] p2s_rs_rpcdp_in, p2s_rs_rpcdn_in;
wire [6:0] p2s_rt_rpcdp_in, p2s_rt_rpcdn_in;
wire p2s_ser_data_out;
wire p2s_clk_ser_data;
reg p2s_enser_reg;
wire [27:0] p2s_parallel_code;
wire [27:0] p2s_shift_d;
reg [27:0] p2s_shift_regs;
// timing
wire rup_ipd;
wire rdn_ipd;
wire terminationclock_ipd;
wire terminationclear_ipd;
wire terminationenable_ipd;
wire serializerenable_ipd;
wire terminationcontrolin_ipd;
wire [8:0] otherserializerenable_ipd;
// primary outputs
assign incrup = (enable_loopback == "true") ? terminationenable_ipd : compout_rup_core;
assign incrdn = (enable_loopback == "true") ? terminationclear_ipd : compout_rdn_core;
assign serializerenableout = (enable_loopback == "true") ? serializerenable : enser_gen_usr_out;
assign terminationcontrol = ser_data_io;
assign terminationcontrolprobe = (enable_loopback == "true") ? serializerenable_ipd : ser_data_core;
assign shiftregisterprobe = (enable_loopback == "true") ? terminationclock_ipd : sreg_vshift_bit_out;
// disabled comparator when calibration is not enabled
assign compout_rup_core = (calclken_reg === 1'b1) ? rup : 1'bx;
assign compout_rdn_core = (calclken_reg === 1'b1) ? rdn : 1'bx;
assign ser_data_io = (allow_serial_data_from_core == "true") ? terminationcontrolin : p2s_ser_data_out;
assign ser_data_core = p2s_ser_data_out;
// primary inputs
assign usr_clk = terminationclock_ipd;
// gating the enserusr, clken and nclrusr ----------------------------------------------------
initial begin
enserusr_reg = 1'b0;
clkenusr_reg = 1'b0;
nclrusr_reg = 1'b1;
end
always @(negedge usr_clk)
begin
if (serializerenable_ipd === 1'b1)
enserusr_reg <= 1'b1;
else
enserusr_reg <= 1'b0;
if (terminationenable_ipd === 1'b1)
clkenusr_reg <= 1'b1;
else
clkenusr_reg <= 1'b0;
if (terminationclear_ipd === 1'b1) // active low to high
nclrusr_reg <= 1'b0;
else
nclrusr_reg <= 1'b1;
end
assign enserusr_gated = enserusr_reg & ~clkenusr_reg; // code transfer (P2S and S2P)
assign clkenusr_gated = enserusr_reg & clkenusr_reg; // calibration
assign nclrusr_gated = enserusr_reg | nclrusr_reg; // active low
// clk divider ----------------------------------------------------------------
hardcopyiii_termination_aux_clock_div m_gen_calclk (
.clk(usr_clk),
.reset(~clkenusr_gated),
.clkout(clkdiv_out));
defparam m_gen_calclk.clk_divide_by = 20; // user clock is of 20 Mhz updated from 100;
defparam m_gen_calclk.extra_latency = 4; // 5th rising edge after reset
// generating clkenout - a registered version of clkensur_gated ---------------
initial calclken_reg = 1'b0;
always @(negedge clkdiv_out or negedge clkenusr_gated)
begin
if (clkenusr_gated == 1'b0)
calclken_reg <= 1'b0;
else
calclken_reg <= 1'b1;
end
//assign clkenout = calclken_reg;
// generating cal_clkout - 1 cycle latency of divided clock ---------------
assign cal_clk = calclken_reg & clkdiv_out;
assign cal_nclr = nclrusr_gated; // active low
assign cal_clken = clkenusr_gated;
assign rscal_clk = cal_clk & (~sregn_rscaldone_out);
// legality check on enser
initial begin
enser_checked = 1'b0;
end
always @(posedge usr_clk)
begin
if (serializerenable === 1'b1 && terminationenable === 1'b0)
begin
if (otherserializerenable[0] === 1'b1 || otherserializerenable[1] === 1'b1 ||
otherserializerenable[2] === 1'b1 || otherserializerenable[3] === 1'b1 ||
otherserializerenable[4] === 1'b1 || otherserializerenable[5] === 1'b1 ||
otherserializerenable[6] === 1'b1 || otherserializerenable[7] === 1'b1 ||
otherserializerenable[8] === 1'b1)
begin
if (enser_checked === 1'b0)
begin
$display ("Warning: serializizerable and some bits of otherserializerenable are asserted at time %t ps. This is not allowed in hardware data transfer time", $realtime);
$display ("Time: %0t Instance: %m", $time);
enser_checked <= 1'b1;
end
end
else
begin
enser_checked <= 1'b0; // for another check
end
end
else
begin
enser_checked <= 1'b0; // for another check
end
end
// SHIFT regiter
// ICD BIT_7 .. BIT_1 ===> sreg_bit_out[6..0];
// ICD BIT_0 ===> sreg_bit_BIT_0;
initial begin
sreg_bit6_prev = 1'b1;
sreg_bit_out = 6'b000000;
sreg_bit0_next = 1'b0;
sreg_bit_BIT_0 = 1'b0;
sreg_vshift_bit_tmp = 1'b0;
sreg_vshift_bit_out = 1'b0; // sending to shiftreg_probe
sregn_rscaldone_out = 1'b0;
sreg_rscaldone_prev = 1'b0;
sreg_rscaldone_prev1 = 1'b0;
end
always @(posedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
begin
sreg_bit6_prev <= 1'b1;
sreg_bit_out <= 6'b000000;
sreg_bit0_next <= 1'b0;
sreg_bit_BIT_0 <= 1'b0;
sreg_vshift_bit_tmp <= 1'b0;
sreg_vshift_bit_out <= 1'b0;
sreg_rscaldone_prev <= 1'b0;
sreg_rscaldone_prev1 <= 1'b0;
end
else if (cal_clken == 1'b1)
begin
sreg_bit_out[6] <= sreg_bit6_prev;
sreg_bit_out[5:0] <= sreg_bit_out[6:1];
sreg_bit0_next <= sreg_bit_out[0]; // extra latency for ICD BIT_0
sreg_bit_BIT_0 <= sreg_bit0_next;
sreg_vshift_bit_tmp <= sreg_bit_out[0];
sreg_vshift_bit_out <= sreg_bit_out[0] | sreg_vshift_bit_tmp;
sreg_bit6_prev <= 1'b0;
end
// might falling outside of 10 cycles
if (sreg_vshift_bit_tmp == 1'b1)
sreg_rscaldone_prev <= 1'b1;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
end
always @(negedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
sregn_rscaldone_out <= 1'b0;
else // if (cal_clken == 1'b1) - outside of 10 cycles
begin
if (sreg_rscaldone_prev1 == 1'b1 && sregn_rscaldone_out == 1'b0)
sregn_rscaldone_out <= 1'b1;
end
end
// nreg and SA-ADC:
//
// RDN_vol < ref_voltage < RUP_voltage
// after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
// at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
// RDN=GND so voltage compare out for RDN = 0
assign regn_rup_in = rup;
assign regn_rdn_in = ~rdn; // inverted --------------------------
initial begin
regn_compout_rup = 6'b00000;
regn_compout_rdn = 6'b00000;
regn_compout_rup_extra = 1'b0;
regn_compout_rdn_extra = 1'b0;
end
always @(negedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
begin
regn_compout_rup <= 6'b00000;
regn_compout_rdn <= 6'b00000;
regn_compout_rup_extra <= 1'b0;
regn_compout_rdn_extra <= 1'b0;
end
else
begin
// rup
if (sreg_bit_BIT_0 == 1'b1)
regn_compout_rup_extra <= regn_rup_in;
if (sreg_bit_out[0] == 1'b1)
regn_compout_rup[0] <= regn_rup_in;
if (sreg_bit_out[1] == 1'b1)
regn_compout_rup[1] <= regn_rup_in;
if (sreg_bit_out[2] == 1'b1)
regn_compout_rup[2] <= regn_rup_in;
if (sreg_bit_out[3] == 1'b1)
regn_compout_rup[3] <= regn_rup_in;
if (sreg_bit_out[4] == 1'b1)
regn_compout_rup[4] <= regn_rup_in;
if (sreg_bit_out[5] == 1'b1)
regn_compout_rup[5] <= regn_rup_in;
if (sreg_bit_out[6] == 1'b1)
regn_compout_rup[6] <= regn_rup_in;
// rdn
if (sreg_bit_BIT_0 == 1'b1)
regn_compout_rdn_extra <= regn_rdn_in;
if (sreg_bit_out[0] == 1'b1)
regn_compout_rdn[0] <= regn_rdn_in;
if (sreg_bit_out[1] == 1'b1)
regn_compout_rdn[1] <= regn_rdn_in;
if (sreg_bit_out[2] == 1'b1)
regn_compout_rdn[2] <= regn_rdn_in;
if (sreg_bit_out[3] == 1'b1)
regn_compout_rdn[3] <= regn_rdn_in;
if (sreg_bit_out[4] == 1'b1)
regn_compout_rdn[4] <= regn_rdn_in;
if (sreg_bit_out[5] == 1'b1)
regn_compout_rdn[5] <= regn_rdn_in;
if (sreg_bit_out[6] == 1'b1)
regn_compout_rdn[6] <= regn_rdn_in;
end
end
assign sa_octcaln_in = sreg_bit_out;
assign sa_octcalp_in = sreg_bit_out;
// RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
assign sa_octcaln_out_tmp_extra = (cal_nclr == 1'b0) ? 1'b0 :
(sreg_bit_BIT_0 == 1'b1) ? 1'b1: regn_compout_rup_extra;
assign sa_octcaln_out_tmp[0] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[0] == 1'b1) ? 1'b1: regn_compout_rup[0];
assign sa_octcaln_out_tmp[1] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[1] == 1'b1) ? 1'b1: regn_compout_rup[1];
assign sa_octcaln_out_tmp[2] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[2] == 1'b1) ? 1'b1: regn_compout_rup[2];
assign sa_octcaln_out_tmp[3] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[3] == 1'b1) ? 1'b1: regn_compout_rup[3];
assign sa_octcaln_out_tmp[4] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[4] == 1'b1) ? 1'b1: regn_compout_rup[4];
assign sa_octcaln_out_tmp[5] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[5] == 1'b1) ? 1'b1: regn_compout_rup[5];
assign sa_octcaln_out_tmp[6] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[6] == 1'b1) ? 1'b1: regn_compout_rup[6];
// RDN - octcalp_in == 1 = (pin_voltage > ref_voltage): clear the bit setting
assign sa_octcalp_out_tmp_extra = (cal_nclr == 1'b0) ? 1'b0 :
(sreg_bit_BIT_0 == 1'b1) ? 1'b1: regn_compout_rdn_extra;
assign sa_octcalp_out_tmp[0] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[0] == 1'b1) ? 1'b1: regn_compout_rdn[0];
assign sa_octcalp_out_tmp[1] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[1] == 1'b1) ? 1'b1: regn_compout_rdn[1];
assign sa_octcalp_out_tmp[2] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[2] == 1'b1) ? 1'b1: regn_compout_rdn[2];
assign sa_octcalp_out_tmp[3] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[3] == 1'b1) ? 1'b1: regn_compout_rdn[3];
assign sa_octcalp_out_tmp[4] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[4] == 1'b1) ? 1'b1: regn_compout_rdn[4];
assign sa_octcalp_out_tmp[5] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[5] == 1'b1) ? 1'b1: regn_compout_rdn[5];
assign sa_octcalp_out_tmp[6] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[6] == 1'b1) ? 1'b1: regn_compout_rdn[6];
assign sa_octcaln_out = sa_octcaln_out_tmp + sa_octcaln_out_tmp_extra;
assign sa_octcalp_out = sa_octcalp_out_tmp + sa_octcalp_out_tmp_extra;
// ENSER
assign enser_out = (runtime_control == "true") ? enser_gen_usr_out : enser_gen_out;
// user mode
initial enser_gen_usr_out = 1'b0;
always @(negedge usr_clk)
begin
enser_gen_usr_out <= serializerenable;
end
// for powerup mode
assign enser_gen_out = (enser_cnt > 6'd00 && enser_cnt < 6'd31) ? 1'b1 : 1'b0;
initial begin
enser_cnt = 'b0;
end
always @(posedge usr_clk or posedge sregn_rscaldone_out)
begin
if (sregn_rscaldone_out == 1'b0)
enser_cnt <= 6'b000000;
else if (enser_cnt < 6'd63)
enser_cnt <= enser_cnt + 6'b000001;
end
// RT SM
assign rtsm_rup_in = rup;
assign rtsm_rdn_in = rdn;
assign rtsm_rtena_in = (enable_parallel_termination == "true") ? 1'b1 : 1'b0;
assign rtsm_rscaldone_in = sregn_rscaldone_out;
hardcopyiii_rt_sm m_rt_sm(
.rup(rtsm_rup_in),
.rdn(rtsm_rdn_in),
.clk(cal_clk),
.clken(cal_clken),
.clr(~cal_nclr),
.rtena(rtsm_rtena_in),
.rscaldone(rtsm_rscaldone_in),
.rtoffsetp(rtsm_rtoffsetp_out),
.rtoffsetn(rtsm_rtoffsetn_out),
.caldone(rtsm_caldone_out),
.sel_rup_vref(rtsm_sel_rup_vref_out),
.sel_rdn_vref(rtsm_sel_rdn_vref_out)
);
// RT State Machine Scan Chain
initial rtsm_sc_out_reg = 'b0;
assign rtsm_sc_clk = (bypass_rt_calclk == "true") ? cal_clk : cal_clk; // : rtcal_clk
assign rtsm_sc_in = terminationcontrolin_ipd;
//TEST4&RTEST3 not implemented - requires identical RT_SM
assign rtsm_sc_lpbk_mux = (bypass_rt_calclk == "true" && enable_rt_sm_loopback == "true") ?
18'bx : 18'bx;
assign rtsm_sc_out_reg_d[17] = (bypass_rt_calclk == "true" && scanen === 1'b0) ? rtsm_sc_in
: rtsm_sc_lpbk_mux[17];
assign rtsm_sc_out_reg_d[16:0] = (bypass_rt_calclk == "true" && scanen === 1'b0) ? rtsm_sc_out_reg[17:1]
: rtsm_sc_lpbk_mux[16:0];
assign scanout = rtsm_sc_out_reg[0];
always @(posedge rtsm_sc_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
rtsm_sc_out_reg <= 'b0;
else
rtsm_sc_out_reg <= rtsm_sc_out_reg_d;
end
// RT Adder/Sub
assign rtas_rs_rpcdp_in = sa_octcalp_out;
assign rtas_rs_rpcdn_in = sa_octcaln_out;
assign rtas_rtoffsetp_in = {4'b0000, rtsm_rtoffsetp_out[2:0]};
assign rtas_rtoffsetn_in = {4'b0000, rtsm_rtoffsetn_out[2:0]};
assign rtas_rs_rpcdp_out = rtas_rs_rpcdp_in;
assign rtas_rs_rpcdn_out = rtas_rs_rpcdn_in;
assign rtas_rt_rpcdn_out = (rtsm_rtoffsetn_out[3] == 1'b0) ? (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) :
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
assign rtas_rt_rpcdp_out = (rtsm_rtoffsetp_out[3] == 1'b0) ? (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) :
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
// P2S ------------------------------------------------------------------------
// during calibration - enser_reg = 0
// - enser_reg is low D inputs of shfit_reg select parallel code
// caldone generating a rising pulse on clk_ser_data: shift_regs read in D (parallel_load)
// during serial shift - enser_reg = 1 for 28 cycles
// - clk_ser_data = clkusr
// 28-bit are barrel-shifting
//
assign p2s_rs_rpcdp_in = rtas_rs_rpcdp_out;
assign p2s_rs_rpcdn_in = rtas_rs_rpcdn_out;
assign p2s_rt_rpcdp_in = rtas_rt_rpcdp_out;
assign p2s_rt_rpcdn_in = rtas_rt_rpcdn_out;
// serial shift clock
assign p2s_clk_ser_data = (enserusr_gated === 1'b1) ? (~usr_clk) : // serial mode
(calclken_reg === 1'b1) ? (rtsm_caldone_out & sregn_rscaldone_out) : 1'b1; // one pulse for pload
// load D of shift register through - mux selection enser_reg
initial p2s_enser_reg = 1'b1; // load parallel code into D of shift reg - cleared by pllbiasen
always @(negedge usr_clk)
begin
p2s_enser_reg <= ~calclken_reg;
end
assign p2s_parallel_code = {p2s_rs_rpcdp_in,p2s_rs_rpcdn_in,p2s_rt_rpcdp_in,p2s_rt_rpcdn_in};
assign p2s_shift_d = (p2s_enser_reg === 1'b1) ? {p2s_shift_regs[26:0], p2s_shift_regs[27]} : p2s_parallel_code;
// shifting - cleared by PLLBIASEN
initial p2s_shift_regs = 'b0;
always @(posedge p2s_clk_ser_data)
begin
p2s_shift_regs <= p2s_shift_d;
end
assign p2s_ser_data_out = (enserusr_gated === 1'b1) ? p2s_shift_regs[27] : 1'bx;
// timing - input path
buf buf_rup_ipd (rup_ipd,rup);
buf buf_rdn_ipd (rdn_ipd,rdn);
buf buf_terminationclock_ipd (terminationclock_ipd,terminationclock);
buf buf_terminationclear_ipd (terminationclear_ipd,terminationclear);
buf buf_terminationenable_ipd (terminationenable_ipd, terminationenable);
buf buf_serializerenable_ipd (serializerenable_ipd,serializerenable);
buf buf_terminationcontrolin_ipd (terminationcontrolin_ipd,terminationcontrolin);
buf buf_otherserializerenable_ipd [8:0] (otherserializerenable_ipd,otherserializerenable);
endmodule // hardcopyiii_termination
//-----------------------------------------------------------------------------
//
// Module Name : hardcopyiii_termination_logic
//
// Description : HARDCOPYIII Termination Logic Atom
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_termination_logic (
serialloadenable,terminationclock,parallelloadenable,terminationdata,
devclrn,devpor,
seriesterminationcontrol,parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "hardcopyiii_termination_logic";
input serialloadenable;
input terminationclock;
input parallelloadenable;
input terminationdata;
input devclrn;
input devpor;
output [13:0] seriesterminationcontrol;
output [13:0] parallelterminationcontrol;
tri1 devclrn;
tri1 devpor;
wire usr_clk;
wire shift_clk;
wire pload_clk;
reg [27:0] shift_reg;
reg [27:0] output_reg;
assign seriesterminationcontrol = output_reg[27:14];
assign parallelterminationcontrol = output_reg[13:0];
assign #11 usr_clk = terminationclock;
assign shift_clk = (serialloadenable === 1'b0) ? 1'b0 : usr_clk; // serena & clk
assign pload_clk = (parallelloadenable === 1'b1) ? 1'b1 : 1'b0; // ploaden
initial begin
// does not get reset so whatever power-up values
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge shift_clk)
shift_reg <= {shift_reg[26:0], terminationdata};
always @(posedge pload_clk)
output_reg <= shift_reg;
endmodule // hardcopyiii_termination_logic
//--------------------------------------------------------------------------
// Module Name : hardcopyiii_io_pad
// Description : Simulation model for hardcopyiii IO pad
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_io_pad (
padin,
padout
);
parameter lpm_type = "hardcopyiii_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the HARDCOPYIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module hardcopyiii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // hardcopyiii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the HARDCOPYIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module hardcopyiii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // hardcopyiii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0-C9
// output counters of the HARDCOPYIII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module hardcopyiii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // hardcopyiii_scale_cntr
//BEGIN MF PORTING DELETE
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module hardcopyiii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // hardcopyiii_pll_reg
//END MF PORTING DELETE
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_pll
//
// Description : Timing simulation model for the HARDCOPYIII PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
// New Features : The list below outlines key new features in HARDCOPYIII:
// 1. Dynamic Phase Reconfiguration
// 2. Dynamic PLL Reconfiguration (different protocol)
// 3. More output counters
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module hardcopyiii_pll (inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange
);
parameter operation_mode = "normal";
parameter pll_type = "auto"; // auto,fast(left_right),enhanced(top_bottom)
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter dpa_multiply_by = 0;
parameter dpa_divide_by = 0;
parameter dpa_divider = 0; // 0, 1, 2, 4
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0; // 0 .. 4095
parameter lock_low = 0; // 0 .. 7
parameter lock_window_ui = "0.05"; // "0.05", "0.1", "0.15", "0.2"
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 0;
parameter clk5_divide_by = 0;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter clk6_output_frequency = 0;
parameter clk6_multiply_by = 0;
parameter clk6_divide_by = 0;
parameter clk6_phase_shift = "0";
parameter clk6_duty_cycle = 50;
parameter clk7_output_frequency = 0;
parameter clk7_multiply_by = 0;
parameter clk7_divide_by = 0;
parameter clk7_phase_shift = "0";
parameter clk7_duty_cycle = 50;
parameter clk8_output_frequency = 0;
parameter clk8_multiply_by = 0;
parameter clk8_divide_by = 0;
parameter clk8_phase_shift = "0";
parameter clk8_duty_cycle = 50;
parameter clk9_output_frequency = 0;
parameter clk9_multiply_by = 0;
parameter clk9_divide_by = 0;
parameter clk9_phase_shift = "0";
parameter clk9_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter c6_high = 1;
parameter c6_low = 1;
parameter c6_initial = 1;
parameter c6_mode = "bypass";
parameter c6_ph = 0;
parameter c7_high = 1;
parameter c7_low = 1;
parameter c7_initial = 1;
parameter c7_mode = "bypass";
parameter c7_ph = 0;
parameter c8_high = 1;
parameter c8_low = 1;
parameter c8_initial = 1;
parameter c8_mode = "bypass";
parameter c8_ph = 0;
parameter c9_high = 1;
parameter c9_low = 1;
parameter c9_initial = 1;
parameter c9_mode = "bypass";
parameter c9_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter clk5_counter = "unused";
parameter clk6_counter = "unused";
parameter clk7_counter = "unused";
parameter clk8_counter = "unused";
parameter clk9_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter c6_use_casc_in = "off";
parameter c7_use_casc_in = "off";
parameter c8_use_casc_in = "off";
parameter c9_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter c5_test_source = -1;
parameter c6_test_source = -1;
parameter c7_test_source = -1;
parameter c8_test_source = -1;
parameter c9_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1; // 1 .. 2
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; // "1.0", "2.0", "4.0", "6.0", "8.0", "12.0", "16.0", "20.0"
parameter loop_filter_c = 0; // 0 , 2 , 4
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "hardcopyiii_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter lock_c = 4;
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk3_phase_shift_num = 0;
parameter clk4_phase_shift_num = 0;
parameter family_name = "HARDCOPYIII";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk6_use_even_counter_mode = "off";
parameter clk7_use_even_counter_mode = "off";
parameter clk8_use_even_counter_mode = "off";
parameter clk9_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
parameter clk6_use_even_counter_value = "off";
parameter clk7_use_even_counter_value = "off";
parameter clk8_use_even_counter_value = "off";
parameter clk9_use_even_counter_value = "off";
// TEST ONLY
parameter init_block_reset_a_count = 1;
parameter init_block_reset_b_count = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter phase_counter_select_width = 4;
parameter lock_window = 5;
parameter inclk0_freq = inclk0_input_frequency;
parameter inclk1_freq = inclk1_input_frequency;
parameter charge_pump_current_bits = 0;
parameter lock_window_ui_bits = 0;
parameter loop_filter_c_bits = 0;
parameter loop_filter_r_bits = 0;
parameter test_counter_c0_delay_chain_bits = 0;
parameter test_counter_c1_delay_chain_bits = 0;
parameter test_counter_c2_delay_chain_bits = 0;
parameter test_counter_c3_delay_chain_bits = 0;
parameter test_counter_c4_delay_chain_bits = 0;
parameter test_counter_c5_delay_chain_bits = 0;
parameter test_counter_c6_delay_chain_bits = 0;
parameter test_counter_c7_delay_chain_bits = 0;
parameter test_counter_c8_delay_chain_bits = 0;
parameter test_counter_c9_delay_chain_bits = 0;
parameter test_counter_m_delay_chain_bits = 0;
parameter test_counter_n_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter test_input_comp_delay_chain_bits = 0;
parameter test_volt_reg_output_mode_bits = 0;
parameter test_volt_reg_output_voltage_bits = 0;
parameter test_volt_reg_test_mode = "false";
parameter vco_range_detector_high_bits = -1;
parameter vco_range_detector_low_bits = -1;
parameter scan_chain_mif_file = "";
parameter test_counter_c3_sclk_delay_chain_bits = -1;
parameter test_counter_c4_sclk_delay_chain_bits = -1;
parameter test_counter_c5_lden_delay_chain_bits = -1;
parameter test_counter_c6_lden_delay_chain_bits = -1;
parameter auto_settings = "true";
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
// OUTPUT PORTS
output [9:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
// TIMING CHECKS
specify
$setuphold(negedge scanclk, scandata, 0, 0);
$setuphold(negedge scanclk, scanclkena, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
reg [8*6:1] clk_num[0:9];
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
reg switch_clock;
reg [31:0] real_lock_high;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg locked_tmp;
reg areset_last_value;
reg pfdena_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
// Test bypass lock detect
reg pfd_locked;
integer cycles_pfd_low, cycles_pfd_high;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:9];
reg [31:0] c_low_val[0:9];
reg [8*6:1] c_mode_val[0:9];
reg [31:0] c_initial_val[0:9];
integer c_ph_val[0:9];
reg [31:0] c_val; // placeholder for c_high,c_low values
// VCO Frequency Range control
reg vco_over, vco_under;
// temporary registers for reprogramming
integer c_ph_val_tmp[0:9];
reg [31:0] c_high_val_tmp[0:9];
reg [31:0] c_hval[0:9];
reg [31:0] c_low_val_tmp[0:9];
reg [31:0] c_lval[0:9];
reg [8*6:1] c_mode_val_tmp[0:9];
// hold registers for reprogramming
integer c_ph_val_hold[0:9];
reg [31:0] c_high_val_hold[0:9];
reg [31:0] c_low_val_hold[0:9];
reg [8*6:1] c_mode_val_hold[0:9];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:9];
reg [31:0] c_low_val_old[0:9];
reg [8*6:1] c_mode_val_old[0:9];
integer c_ph_val_old[0:9];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
integer vco_cur;
integer vco_old;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [1:2] lfc_val_bit_setting, lfc_val_old_bit_setting;
reg vco_val_bit_setting, vco_val_old_bit_setting;
reg [3:7] lfr_val_bit_setting, lfr_val_old_bit_setting;
reg [14:16] cp_curr_bit_setting, cp_curr_old_bit_setting;
// Setting on - display real values
// Setting off - display only bits
reg pll_reconfig_display_full_setting;
reg [7:0] m_hi;
reg [7:0] m_lo;
reg [7:0] n_hi;
reg [7:0] n_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:9];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg inclk_man;
reg inclk_es;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
wire inclk_c6;
wire inclk_c7;
wire inclk_c8;
wire inclk_c9;
wire inclk_c0_from_vco;
wire inclk_c1_from_vco;
wire inclk_c2_from_vco;
wire inclk_c3_from_vco;
wire inclk_c4_from_vco;
wire inclk_c5_from_vco;
wire inclk_c6_from_vco;
wire inclk_c7_from_vco;
wire inclk_c8_from_vco;
wire inclk_c9_from_vco;
wire inclk_m_from_vco;
wire inclk_m;
wire pfdena_wire;
wire [9:0] clk_tmp, clk_out_pfd;
wire [9:0] clk_out;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
wire c6_clk;
wire c7_clk;
wire c8_clk;
wire c9_clk;
reg first_schedule;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// Self Reset
wire reset_self;
// Clock Switchover
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandata_in, scandata_out; // hold scan data in negative-edge triggered ff (on either side on chain)
reg scandone_tmp;
reg initiate_reconfig;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
wire update_conf_latches;
reg update_conf_latches_reg;
reg [-1:232] scan_data;
reg scanclkena_reg; // register scanclkena on negative edge of scanclk
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg c6_rising_edge_transfer_done;
reg c7_rising_edge_transfer_done;
reg c8_rising_edge_transfer_done;
reg c9_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// Phase reconfig
reg [3:0] phasecounterselect_reg;
reg phaseupdown_reg;
reg phasestep_reg;
integer select_counter;
integer phasestep_high_count;
reg update_phase;
// LOCAL_PARAMETERS_BEGIN
parameter SCAN_CHAIN = 144;
parameter GPP_SCAN_CHAIN = 234;
parameter FAST_SCAN_CHAIN = 180;
// primary clk is always inclk0
parameter num_phase_taps = 8;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_clk6_mult_by;
integer i_clk6_div_by;
integer i_clk7_mult_by;
integer i_clk7_div_by;
integer i_clk8_mult_by;
integer i_clk8_div_by;
integer i_clk9_mult_by;
integer i_clk9_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
integer i_clk3_phase_shift;
integer i_clk4_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_c_high[0:9];
integer i_c_low[0:9];
integer i_c_initial[0:9];
integer i_c_ph[0:9];
reg [8*6:1] i_c_mode[0:9];
integer i_vco_min;
integer i_vco_max;
integer i_vco_min_no_division;
integer i_vco_max_no_division;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk9_counter;
reg [8*2:1] i_clk8_counter;
reg [8*2:1] i_clk7_counter;
reg [8*2:1] i_clk6_counter;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_has_just_been_reconfigured;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_vco_frequency_control;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_self_reset_on_loss_lock;
integer current_clock;
integer current_clock_man;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg ic6_use_casc_in;
reg ic7_use_casc_in;
reg ic8_use_casc_in;
reg ic9_use_casc_in;
reg init;
reg tap0_is_active;
real inclk0_period, last_inclk0_period,inclk1_period, last_inclk1_period;
real last_inclk0_edge,last_inclk1_edge,diff_percent_period;
reg first_inclk0_edge_detect,first_inclk1_edge_detect;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = (numerator == 0) ? 1 : numerator;
den = (denominator == 0) ? 1 : denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
fraction_num = m_value;
fraction_div = d_value;
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, C6, C6_mode, C7, C7_mode, C8, C8_mode, C9, C9_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5, C6, C7, C8, C9;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode, C6_mode, C7_mode, C8_mode, C9_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if (C6 > max_modulus && C6_mode != "bypass" && C6_mode != " off")
max_modulus = C6;
if (C7 > max_modulus && C7_mode != "bypass" && C7_mode != " off")
max_modulus = C7;
if (C8 > max_modulus && C8_mode != "bypass" && C8_mode != " off")
max_modulus = C8;
if (C9 > max_modulus && C9_mode != "bypass" && C9_mode != " off")
max_modulus = C9;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the M and N values for Manual phase based on the following 5 criterias:
// 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
// 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
// 3. M is less than 512
// 4. N is less than 512
// 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
// of the desired vco-phase-shift-step
task find_m_and_n_4_manual_phase;
input inclock_period;
input vco_phase_shift_step;
input clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
input clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
input clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
input clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
input clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
input clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
output m;
output n;
parameter max_m = 511;
parameter max_n = 511;
parameter max_pfd = 720;
parameter min_pfd = 5;
parameter max_vco = 1600; // max vco frequency. (in mHz)
parameter min_vco = 300; // min vco frequency. (in mHz)
parameter max_offset = 0.004;
reg[160:1] clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
reg[160:1] clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
integer inclock_period;
integer vco_phase_shift_step;
integer clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
integer clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
integer clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
integer clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
integer m;
integer n;
integer pre_m;
integer pre_n;
integer m_out;
integer n_out;
integer closest_vco_step_value;
integer vco_period;
integer pfd_freq;
integer vco_freq;
integer vco_ps_step_value;
real clk0_div_factor_real;
real clk1_div_factor_real;
real clk2_div_factor_real;
real clk3_div_factor_real;
real clk4_div_factor_real;
real clk5_div_factor_real;
real clk6_div_factor_real;
real clk7_div_factor_real;
real clk8_div_factor_real;
real clk9_div_factor_real;
real clk0_div_factor_diff;
real clk1_div_factor_diff;
real clk2_div_factor_diff;
real clk3_div_factor_diff;
real clk4_div_factor_diff;
real clk5_div_factor_diff;
real clk6_div_factor_diff;
real clk7_div_factor_diff;
real clk8_div_factor_diff;
real clk9_div_factor_diff;
integer clk0_div_factor_int;
integer clk1_div_factor_int;
integer clk2_div_factor_int;
integer clk3_div_factor_int;
integer clk4_div_factor_int;
integer clk5_div_factor_int;
integer clk6_div_factor_int;
integer clk7_div_factor_int;
integer clk8_div_factor_int;
integer clk9_div_factor_int;
begin
vco_period = vco_phase_shift_step * 8;
pre_m = 0;
pre_n = 0;
closest_vco_step_value = 0;
begin : LOOP_1
for (n_out = 1; n_out < max_n; n_out = n_out +1)
begin
for (m_out = 1; m_out < max_m; m_out = m_out +1)
begin
clk0_div_factor_real = (clk0_div * m_out * 1.0 ) / (clk0_mult * n_out);
clk1_div_factor_real = (clk1_div * m_out * 1.0) / (clk1_mult * n_out);
clk2_div_factor_real = (clk2_div * m_out * 1.0) / (clk2_mult * n_out);
clk3_div_factor_real = (clk3_div * m_out * 1.0) / (clk3_mult * n_out);
clk4_div_factor_real = (clk4_div * m_out * 1.0) / (clk4_mult * n_out);
clk5_div_factor_real = (clk5_div * m_out * 1.0) / (clk5_mult * n_out);
clk6_div_factor_real = (clk6_div * m_out * 1.0) / (clk6_mult * n_out);
clk7_div_factor_real = (clk7_div * m_out * 1.0) / (clk7_mult * n_out);
clk8_div_factor_real = (clk8_div * m_out * 1.0) / (clk8_mult * n_out);
clk9_div_factor_real = (clk9_div * m_out * 1.0) / (clk9_mult * n_out);
clk0_div_factor_int = clk0_div_factor_real;
clk1_div_factor_int = clk1_div_factor_real;
clk2_div_factor_int = clk2_div_factor_real;
clk3_div_factor_int = clk3_div_factor_real;
clk4_div_factor_int = clk4_div_factor_real;
clk5_div_factor_int = clk5_div_factor_real;
clk6_div_factor_int = clk6_div_factor_real;
clk7_div_factor_int = clk7_div_factor_real;
clk8_div_factor_int = clk8_div_factor_real;
clk9_div_factor_int = clk9_div_factor_real;
clk0_div_factor_diff = (clk0_div_factor_real - clk0_div_factor_int < 0) ? (clk0_div_factor_real - clk0_div_factor_int) * -1.0 : clk0_div_factor_real - clk0_div_factor_int;
clk1_div_factor_diff = (clk1_div_factor_real - clk1_div_factor_int < 0) ? (clk1_div_factor_real - clk1_div_factor_int) * -1.0 : clk1_div_factor_real - clk1_div_factor_int;
clk2_div_factor_diff = (clk2_div_factor_real - clk2_div_factor_int < 0) ? (clk2_div_factor_real - clk2_div_factor_int) * -1.0 : clk2_div_factor_real - clk2_div_factor_int;
clk3_div_factor_diff = (clk3_div_factor_real - clk3_div_factor_int < 0) ? (clk3_div_factor_real - clk3_div_factor_int) * -1.0 : clk3_div_factor_real - clk3_div_factor_int;
clk4_div_factor_diff = (clk4_div_factor_real - clk4_div_factor_int < 0) ? (clk4_div_factor_real - clk4_div_factor_int) * -1.0 : clk4_div_factor_real - clk4_div_factor_int;
clk5_div_factor_diff = (clk5_div_factor_real - clk5_div_factor_int < 0) ? (clk5_div_factor_real - clk5_div_factor_int) * -1.0 : clk5_div_factor_real - clk5_div_factor_int;
clk6_div_factor_diff = (clk6_div_factor_real - clk6_div_factor_int < 0) ? (clk6_div_factor_real - clk6_div_factor_int) * -1.0 : clk6_div_factor_real - clk6_div_factor_int;
clk7_div_factor_diff = (clk7_div_factor_real - clk7_div_factor_int < 0) ? (clk7_div_factor_real - clk7_div_factor_int) * -1.0 : clk7_div_factor_real - clk7_div_factor_int;
clk8_div_factor_diff = (clk8_div_factor_real - clk8_div_factor_int < 0) ? (clk8_div_factor_real - clk8_div_factor_int) * -1.0 : clk8_div_factor_real - clk8_div_factor_int;
clk9_div_factor_diff = (clk9_div_factor_real - clk9_div_factor_int < 0) ? (clk9_div_factor_real - clk9_div_factor_int) * -1.0 : clk9_div_factor_real - clk9_div_factor_int;
if (((clk0_div_factor_diff < max_offset) || (clk0_used == "unused")) &&
((clk1_div_factor_diff < max_offset) || (clk1_used == "unused")) &&
((clk2_div_factor_diff < max_offset) || (clk2_used == "unused")) &&
((clk3_div_factor_diff < max_offset) || (clk3_used == "unused")) &&
((clk4_div_factor_diff < max_offset) || (clk4_used == "unused")) &&
((clk5_div_factor_diff < max_offset) || (clk5_used == "unused")) &&
((clk6_div_factor_diff < max_offset) || (clk6_used == "unused")) &&
((clk7_div_factor_diff < max_offset) || (clk7_used == "unused")) &&
((clk8_div_factor_diff < max_offset) || (clk8_used == "unused")) &&
((clk9_div_factor_diff < max_offset) || (clk9_used == "unused")) )
begin
if ((m_out != 0) && (n_out != 0))
begin
pfd_freq = 1000000 / (inclock_period * n_out);
vco_freq = (1000000 * m_out) / (inclock_period * n_out);
vco_ps_step_value = (inclock_period * n_out) / (8 * m_out);
if ( (m_out < max_m) && (n_out < max_n) && (pfd_freq >= min_pfd) && (pfd_freq <= max_pfd) &&
(vco_freq >= min_vco) && (vco_freq <= max_vco) )
begin
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
begin
pre_m = m_out;
pre_n = n_out;
disable LOOP_1;
end
else
begin
if ((closest_vco_step_value == 0) || (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
begin
pre_m = m_out;
pre_n = n_out;
closest_vco_step_value = vco_ps_step_value;
end
end
end
end
end
end
end
end
if ((pre_m != 0) && (pre_n != 0))
begin
find_simple_integer_fraction(pre_m, pre_n,
max_n, m, n);
end
else
begin
n = 1;
m = lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end
end
endtask // find_m_and_n_4_manual_phase
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
real r;
integer r_int;
begin
r = (clk_divide * M * 1.0)/(clk_mult * N);
r_int = r;
output_counter_value = r_int;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360.0 * n)) + 0.6;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45.0;
if (counter_ph == 8)
counter_ph = 0;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for hardcopyiii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_freq;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
scandata_out = 1'b0;
first_inclk0_edge_detect = 1'b0;
first_inclk1_edge_detect = 1'b0;
pll_reconfig_display_full_setting = 1'b0;
initiate_reconfig = 1'b0;
switch_over_count = 0;
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_compensate_clock = alpha_tolower(compensate_clock);
l_switch_over_type = alpha_tolower(switch_over_type);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_vco_frequency_control = alpha_tolower(vco_frequency_control);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_self_reset_on_loss_lock = alpha_tolower(self_reset_on_loss_lock);
real_lock_high = (l_sim_gate_lock_device_behavior == "on") ? lock_high : 0;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 0;
loop_filter_c_arr[1] = 0;
loop_filter_c_arr[2] = 0;
loop_filter_c_arr[3] = 0;
fpll_loop_filter_c_arr[0] = 0;
fpll_loop_filter_c_arr[1] = 0;
fpll_loop_filter_c_arr[2] = 0;
fpll_loop_filter_c_arr[3] = 0;
charge_pump_curr_arr[0] = 0;
charge_pump_curr_arr[1] = 0;
charge_pump_curr_arr[2] = 0;
charge_pump_curr_arr[3] = 0;
charge_pump_curr_arr[4] = 0;
charge_pump_curr_arr[5] = 0;
charge_pump_curr_arr[6] = 0;
charge_pump_curr_arr[7] = 0;
charge_pump_curr_arr[8] = 0;
charge_pump_curr_arr[9] = 0;
charge_pump_curr_arr[10] = 0;
charge_pump_curr_arr[11] = 0;
charge_pump_curr_arr[12] = 0;
charge_pump_curr_arr[13] = 0;
charge_pump_curr_arr[14] = 0;
charge_pump_curr_arr[15] = 0;
i_vco_max = vco_max;
i_vco_min = vco_min;
if(vco_post_scale == 1)
begin
i_vco_max_no_division = vco_max * 2;
i_vco_min_no_division = vco_min * 2;
end
else
begin
i_vco_max_no_division = vco_max;
i_vco_min_no_division = vco_min;
end
if (m == 0)
begin
i_clk9_counter = "c9";
i_clk8_counter = "c8";
i_clk7_counter = "c7";
i_clk6_counter = "c6";
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk9_counter = alpha_tolower(clk9_counter);
i_clk8_counter = alpha_tolower(clk8_counter);
i_clk7_counter = alpha_tolower(clk7_counter);
i_clk6_counter = alpha_tolower(clk6_counter);
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
// convert user parameters to advanced
if (l_vco_frequency_control == "manual_phase")
begin
find_m_and_n_4_manual_phase(inclk0_freq, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
i_clk5_mult_by,
i_clk6_mult_by, i_clk7_mult_by,
i_clk8_mult_by, i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,i_clk4_div_by,
i_clk5_div_by,
i_clk6_div_by, i_clk7_div_by,
i_clk8_div_by, i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,clk4_counter,
clk5_counter,
clk6_counter, clk7_counter,
clk8_counter, clk9_counter,
i_m, i_n);
end
else if (((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
if (((l_pll_type == "fast") || (l_pll_type == "left_right")) && (l_compensate_clock == "lvdsclk"))
i_m = i_clk0_mult_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
i_clk5_mult_by,
i_clk6_mult_by, i_clk7_mult_by,
i_clk8_mult_by, i_clk9_mult_by,
inclk0_freq);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high[6] = counter_high (output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high[7] = counter_high (output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high[8] = counter_high (output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high[9] = counter_high (output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[6] = counter_low (output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low[7] = counter_low (output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low[8] = counter_low (output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low[9] = counter_low (output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
i_clk3_phase_shift = 0;
i_clk4_phase_shift = 0;
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
i_clk3_phase_shift = get_int_phase_shift(clk3_phase_shift, clk3_phase_shift_num);
i_clk4_phase_shift = get_int_phase_shift(clk4_phase_shift, clk4_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
i_clk3_phase_shift,
i_clk4_phase_shift,
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(i_clk3_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(i_clk4_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[6] = counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[7] = counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[8] = counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[9] = counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle,output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode[6] = counter_mode(clk6_duty_cycle,output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode[7] = counter_mode(clk7_duty_cycle,output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode[8] = counter_mode(clk8_duty_cycle,output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode[9] = counter_mode(clk9_duty_cycle,output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(i_clk3_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(i_clk4_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[6] = counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[7] = counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[8] = counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[9] = counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs)), i_m, i_n);
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_high[6] = c6_high;
i_c_high[7] = c7_high;
i_c_high[8] = c8_high;
i_c_high[9] = c9_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_low[6] = c6_low;
i_c_low[7] = c7_low;
i_c_low[8] = c8_low;
i_c_low[9] = c9_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_initial[6] = c6_initial;
i_c_initial[7] = c7_initial;
i_c_initial[8] = c8_initial;
i_c_initial[9] = c9_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_mode[6] = translate_string(alpha_tolower(c6_mode));
i_c_mode[7] = translate_string(alpha_tolower(c7_mode));
i_c_mode[8] = translate_string(alpha_tolower(c8_mode));
i_c_mode[9] = translate_string(alpha_tolower(c9_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_c_ph[6] = c6_ph;
i_c_ph[7] = c7_ph;
i_c_ph[8] = c8_ph;
i_c_ph[9] = c9_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
switch_clock = 1'b0;
refclk_period = inclk0_freq * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
inclk_es = 0;
inclk_man = 0;
cycle_to_adjust = 0;
m_delay = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
inclk_out_of_range = 0;
scandone_tmp = 1'b0;
schedule_vco_last_value = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 7;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 10;
end
phasestep_high_count = 0;
update_phase = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 10; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_hval[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
c_lval[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
vco_cur = vco_post_scale;
i = 0;
j = 0;
inclk_last_value = 0;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
current_clock = 0;
current_clock_man = 0;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast" || (l_pll_type == "left_right"))
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch === 1'b1)
begin
current_clock_man = 1;
active_clock = 1;
end
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
c_high_val[6]+c_low_val[6], c_mode_val[6],
c_high_val[7]+c_low_val[7], c_mode_val[7],
c_high_val[8]+c_low_val[8], c_mode_val[8],
c_high_val[9]+c_low_val[9], c_mode_val[9],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
c6_rising_edge_transfer_done = 0;
c7_rising_edge_transfer_done = 0;
c8_rising_edge_transfer_done = 0;
c9_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
vco_over = 1'b0;
vco_under = 1'b0;
// Initialize the scan chain
// LF unused : bit 1
scan_data[-1:0] = 2'b00;
// LF Capacitance : bits 1,2 : all values are legal
scan_data[1:2] = loop_filter_c_bits;
// LF Resistance : bits 3-7
scan_data[3:7] = loop_filter_r_bits;
// VCO post scale
if(vco_post_scale == 1)
begin
scan_data[8] = 1'b1;
vco_val_old_bit_setting = 1'b1;
end
else
begin
scan_data[8] = 1'b0;
vco_val_old_bit_setting = 1'b0;
end
scan_data[9:13] = 5'b00000;
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
scan_data[14:16] = charge_pump_current_bits;
// store as old values
cp_curr_old_bit_setting = charge_pump_current_bits;
lfc_val_old_bit_setting = loop_filter_c_bits;
lfr_val_old_bit_setting = loop_filter_r_bits;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (c_mode_val[i] == "bypass")
begin
scan_data[53 + i*18 + 0] = 1'b1;
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
else
begin
scan_data[53 + i*18 + 0] = 1'b0;
// 3. Mode - odd/even
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
// 2. Hi
c_val = c_high_val[i];
for (j = 1; j <= 8; j = j + 1)
scan_data[53 + i*18 + j] = c_val[8 - j];
// 4. Low
c_val = c_low_val[i];
for (j = 10; j <= 17; j = j + 1)
scan_data[53 + i*18 + j] = c_val[17 - j];
end
// M counter
// 1. Mode - bypass (bit 17)
if (m_mode_val[0] == "bypass")
scan_data[17] = 1'b1;
else
scan_data[17] = 1'b0; // set bypass bit to 0
// 2. High (bit 18-25)
// 3. Mode - odd/even (bit 26)
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[18:25] = m_val[0]/2;
scan_data[26] = 1'b0;
end
else
begin
// M is odd : M high = low + 1
scan_data[18:25] = m_val[0]/2 + 1;
scan_data[26] = 1'b1;
end
// 4. Low (bit 27-34)
scan_data[27:34] = m_val[0]/2;
// N counter
// 1. Mode - bypass (bit 35)
if (n_mode_val[0] == "bypass")
scan_data[35] = 1'b1;
else
scan_data[35] = 1'b0; // set bypass bit to 0
// 2. High (bit 36-43)
// 3. Mode - odd/even (bit 44)
if (n_val[0] % 2 == 0)
begin
// N is an even no. : set N high = low,
// set odd/even bit to 0
scan_data[36:43] = n_val[0]/2;
scan_data[44] = 1'b0;
end
else
begin // N is odd : N high = N low + 1
scan_data[36:43] = n_val[0]/2 + 1;
scan_data[44] = 1'b1;
end
// 4. Low (bit 45-52)
scan_data[45:52] = n_val[0]/2;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
no_warn = 1'b0;
pfd_locked = 1'b0;
cycles_pfd_high = 0;
cycles_pfd_low = 0;
// check if pll is in test mode
if (m_test_source != -1 || c0_test_source != -1 || c1_test_source != -1 || c2_test_source != -1 || c3_test_source != -1 || c4_test_source != -1 || c5_test_source != -1 || c6_test_source != -1 || c7_test_source != -1 || c8_test_source != -1 || c9_test_source != -1)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_has_just_been_reconfigured = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
if (c6_use_casc_in == "on")
ic6_use_casc_in = 1;
else
ic6_use_casc_in = 0;
if (c7_use_casc_in == "on")
ic7_use_casc_in = 1;
else
ic7_use_casc_in = 0;
if (c8_use_casc_in == "on")
ic8_use_casc_in = 1;
else
ic8_use_casc_in = 0;
if (c9_use_casc_in == "on")
ic9_use_casc_in = 1;
else
ic9_use_casc_in = 0;
tap0_is_active = 1;
// To display clock mapping
case( i_clk0_counter)
"c0" : clk_num[0] = " clk0";
"c1" : clk_num[0] = " clk1";
"c2" : clk_num[0] = " clk2";
"c3" : clk_num[0] = " clk3";
"c4" : clk_num[0] = " clk4";
"c5" : clk_num[0] = " clk5";
"c6" : clk_num[0] = " clk6";
"c7" : clk_num[0] = " clk7";
"c8" : clk_num[0] = " clk8";
"c9" : clk_num[0] = " clk9";
default:clk_num[0] = "unused";
endcase
case( i_clk1_counter)
"c0" : clk_num[1] = " clk0";
"c1" : clk_num[1] = " clk1";
"c2" : clk_num[1] = " clk2";
"c3" : clk_num[1] = " clk3";
"c4" : clk_num[1] = " clk4";
"c5" : clk_num[1] = " clk5";
"c6" : clk_num[1] = " clk6";
"c7" : clk_num[1] = " clk7";
"c8" : clk_num[1] = " clk8";
"c9" : clk_num[1] = " clk9";
default:clk_num[1] = "unused";
endcase
case( i_clk2_counter)
"c0" : clk_num[2] = " clk0";
"c1" : clk_num[2] = " clk1";
"c2" : clk_num[2] = " clk2";
"c3" : clk_num[2] = " clk3";
"c4" : clk_num[2] = " clk4";
"c5" : clk_num[2] = " clk5";
"c6" : clk_num[2] = " clk6";
"c7" : clk_num[2] = " clk7";
"c8" : clk_num[2] = " clk8";
"c9" : clk_num[2] = " clk9";
default:clk_num[2] = "unused";
endcase
case( i_clk3_counter)
"c0" : clk_num[3] = " clk0";
"c1" : clk_num[3] = " clk1";
"c2" : clk_num[3] = " clk2";
"c3" : clk_num[3] = " clk3";
"c4" : clk_num[3] = " clk4";
"c5" : clk_num[3] = " clk5";
"c6" : clk_num[3] = " clk6";
"c7" : clk_num[3] = " clk7";
"c8" : clk_num[3] = " clk8";
"c9" : clk_num[3] = " clk9";
default:clk_num[3] = "unused";
endcase
case( i_clk4_counter)
"c0" : clk_num[4] = " clk0";
"c1" : clk_num[4] = " clk1";
"c2" : clk_num[4] = " clk2";
"c3" : clk_num[4] = " clk3";
"c4" : clk_num[4] = " clk4";
"c5" : clk_num[4] = " clk5";
"c6" : clk_num[4] = " clk6";
"c7" : clk_num[4] = " clk7";
"c8" : clk_num[4] = " clk8";
"c9" : clk_num[4] = " clk9";
default:clk_num[4] = "unused";
endcase
case( i_clk5_counter)
"c0" : clk_num[5] = " clk0";
"c1" : clk_num[5] = " clk1";
"c2" : clk_num[5] = " clk2";
"c3" : clk_num[5] = " clk3";
"c4" : clk_num[5] = " clk4";
"c5" : clk_num[5] = " clk5";
"c6" : clk_num[5] = " clk6";
"c7" : clk_num[5] = " clk7";
"c8" : clk_num[5] = " clk8";
"c9" : clk_num[5] = " clk9";
default:clk_num[5] = "unused";
endcase
case( i_clk6_counter)
"c0" : clk_num[6] = " clk0";
"c1" : clk_num[6] = " clk1";
"c2" : clk_num[6] = " clk2";
"c3" : clk_num[6] = " clk3";
"c4" : clk_num[6] = " clk4";
"c5" : clk_num[6] = " clk5";
"c6" : clk_num[6] = " clk6";
"c7" : clk_num[6] = " clk7";
"c8" : clk_num[6] = " clk8";
"c9" : clk_num[6] = " clk9";
default:clk_num[6] = "unused";
endcase
case( i_clk7_counter)
"c0" : clk_num[7] = " clk0";
"c1" : clk_num[7] = " clk1";
"c2" : clk_num[7] = " clk2";
"c3" : clk_num[7] = " clk3";
"c4" : clk_num[7] = " clk4";
"c5" : clk_num[7] = " clk5";
"c6" : clk_num[7] = " clk6";
"c7" : clk_num[7] = " clk7";
"c8" : clk_num[7] = " clk8";
"c9" : clk_num[7] = " clk9";
default:clk_num[7] = "unused";
endcase
case( i_clk8_counter)
"c0" : clk_num[8] = " clk0";
"c1" : clk_num[8] = " clk1";
"c2" : clk_num[8] = " clk2";
"c3" : clk_num[8] = " clk3";
"c4" : clk_num[8] = " clk4";
"c5" : clk_num[8] = " clk5";
"c6" : clk_num[8] = " clk6";
"c7" : clk_num[8] = " clk7";
"c8" : clk_num[8] = " clk8";
"c9" : clk_num[8] = " clk9";
default:clk_num[8] = "unused";
endcase
case( i_clk9_counter)
"c0" : clk_num[9] = " clk0";
"c1" : clk_num[9] = " clk1";
"c2" : clk_num[9] = " clk2";
"c3" : clk_num[9] = " clk3";
"c4" : clk_num[9] = " clk4";
"c5" : clk_num[9] = " clk5";
"c6" : clk_num[9] = " clk6";
"c7" : clk_num[9] = " clk7";
"c8" : clk_num[9] = " clk8";
"c9" : clk_num[9] = " clk9";
default:clk_num[9] = "unused";
endcase
end
// Clock Switchover
always @(clkswitch)
begin
if (clkswitch === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if(clkswitch === 1'b1)
switch_clock = 1'b1;
else
switch_clock = 1'b0;
end
end
always @(posedge inclk[0])
begin
// Determine the inclk0 frequency
if (first_inclk0_edge_detect == 1'b0)
begin
first_inclk0_edge_detect = 1'b1;
end
else
begin
last_inclk0_period = inclk0_period;
inclk0_period = $realtime - last_inclk0_edge;
end
last_inclk0_edge = $realtime;
end
always @(posedge inclk[1])
begin
// Determine the inclk1 frequency
if (first_inclk1_edge_detect == 1'b0)
begin
first_inclk1_edge_detect = 1'b1;
end
else
begin
last_inclk1_period = inclk1_period;
inclk1_period = $realtime - last_inclk1_edge;
end
last_inclk1_edge = $realtime;
end
always @(inclk[0] or inclk[1])
begin
if(switch_clock == 1'b1)
begin
if(current_clock_man == 0)
begin
current_clock_man = 1;
active_clock = 1;
end
else
begin
current_clock_man = 0;
active_clock = 0;
end
switch_clock = 1'b0;
end
if (current_clock_man == 0)
inclk_man = inclk[0];
else
inclk_man = inclk[1];
// save the inclk event value
if (inclk[0] !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk[0];
end
if (inclk[1] !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk[1];
end
// check if either input clk is bad
if (inclk[0] === 1'b1 && inclk[0] !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk[1] === 1'b1 && inclk[1] !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk[0] !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[0] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[0];
end
end
else inclk_es = inclk[0];
end
if ((inclk[1] !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[1] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[1];
end
end
else inclk_es = inclk[1];
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (primary_clk_is_bad && (clkswitch !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
if (areset === 1'b0)
begin
if ((inclk0_period > inclk1_period) && (inclk1_period != 0))
diff_percent_period = (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else if (inclk0_period != 0)
diff_percent_period = (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
if((diff_percent_period > 20)&& (l_switch_over_type == "auto"))
begin
$display ("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.");
$display ("Time: %0t Instance: %m", $time);
end
end
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
else if(l_switch_over_type == "auto")
begin
if(current_clock == 0 && clk0_is_bad == 1'b1 && clk1_is_bad == 1'b0 )
begin
current_clock = 1;
active_clock = ~active_clock;
end
if(current_clock == 1 && clk1_is_bad == 1'b1 && clk0_is_bad == 1'b0 )
begin
current_clock = 0;
active_clock = ~active_clock;
end
end
end
if(l_switch_over_type == "manual")
inclk_n = inclk_man;
else
inclk_n = inclk_es;
inclk0_last_value = inclk[0];
inclk1_last_value = inclk[1];
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
assign inclk_m = (m_test_source == 0) ? fbclk : (m_test_source == 1) ? refclk : inclk_m_from_vco;
hardcopyiii_m_cntr m1 (.clk(inclk_m),
.reset(areset || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
hardcopyiii_n_cntr n1 (.clk(inclk_n),
.reset(areset),
.cout(refclk),
.modulus(n_val[0]));
// Update clock on /o counters from corresponding VCO tap
assign inclk_m_from_vco = vco_tap[m_ph_val];
assign inclk_c0_from_vco = vco_tap[c_ph_val[0]];
assign inclk_c1_from_vco = vco_tap[c_ph_val[1]];
assign inclk_c2_from_vco = vco_tap[c_ph_val[2]];
assign inclk_c3_from_vco = vco_tap[c_ph_val[3]];
assign inclk_c4_from_vco = vco_tap[c_ph_val[4]];
assign inclk_c5_from_vco = vco_tap[c_ph_val[5]];
assign inclk_c6_from_vco = vco_tap[c_ph_val[6]];
assign inclk_c7_from_vco = vco_tap[c_ph_val[7]];
assign inclk_c8_from_vco = vco_tap[c_ph_val[8]];
assign inclk_c9_from_vco = vco_tap[c_ph_val[9]];
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// Update phase taps for C/M counters on negative edge of VCO clock output
if (update_phase == 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y < 10; y = y + 1)
begin
if (c_ph_val_tmp[y] == x)
c_ph_val[y] = c_ph_val_tmp[y];
end
if (m_ph_val_tmp == x)
m_ph_val = m_ph_val_tmp;
end
end
update_phase <= #(0.5*scanclk_period) 1'b0;
end
// On reset, set all C/M counter phase taps to POF programmed values
if (areset === 1'b1)
begin
m_ph_val = m_ph_val_orig;
m_ph_val_tmp = m_ph_val_orig;
for (i=0; i<= 9; i=i+1)
begin
c_ph_val[i] = c_ph_val_orig[i];
c_ph_val_tmp[i] = c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 0) ? fbclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
hardcopyiii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
// Update /o counters mode and duty cycle immediately after configupdate is asserted
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? fbclk : (c1_test_source == 1) ? refclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
hardcopyiii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? fbclk : (c2_test_source == 1) ? refclk :(ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
hardcopyiii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? fbclk : (c3_test_source == 1) ? refclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
hardcopyiii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? fbclk : (c4_test_source == 1) ? refclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
hardcopyiii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign inclk_c5 = (c5_test_source == 0) ? fbclk : (c5_test_source == 1) ? refclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco;
hardcopyiii_scale_cntr c5 (.clk(inclk_c5),
.reset(areset || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[5] <= c_high_val_tmp[5];
c_mode_val[5] <= c_mode_val_tmp[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val[5] <= c_low_val_tmp[5];
end
end
assign inclk_c6 = ((c6_test_source == 0) ? fbclk : (c6_test_source == 1) ? refclk : (ic6_use_casc_in == 1) ? c5_clk : inclk_c6_from_vco);
hardcopyiii_scale_cntr c6 (.clk(inclk_c6),
.reset(areset || stop_vco),
.cout(c6_clk),
.high(c_high_val[6]),
.low(c_low_val[6]),
.initial_value(c_initial_val[6]),
.mode(c_mode_val[6]),
.ph_tap(c_ph_val[6]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[6] <= c_high_val_tmp[6];
c_mode_val[6] <= c_mode_val_tmp[6];
c6_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c6_rising_edge_transfer_done)
begin
c_low_val[6] <= c_low_val_tmp[6];
end
end
assign inclk_c7 = ((c7_test_source == 0) ? fbclk : (c7_test_source == 1) ? refclk : (ic7_use_casc_in == 1) ? c6_clk : inclk_c7_from_vco);
hardcopyiii_scale_cntr c7 (.clk(inclk_c7),
.reset(areset || stop_vco),
.cout(c7_clk),
.high(c_high_val[7]),
.low(c_low_val[7]),
.initial_value(c_initial_val[7]),
.mode(c_mode_val[7]),
.ph_tap(c_ph_val[7]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[7] <= c_high_val_tmp[7];
c_mode_val[7] <= c_mode_val_tmp[7];
c7_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c7_rising_edge_transfer_done)
begin
c_low_val[7] <= c_low_val_tmp[7];
end
end
assign inclk_c8 = ((c8_test_source == 0) ? fbclk : (c8_test_source == 1) ? refclk : (ic8_use_casc_in == 1) ? c7_clk : inclk_c8_from_vco);
hardcopyiii_scale_cntr c8 (.clk(inclk_c8),
.reset(areset || stop_vco),
.cout(c8_clk),
.high(c_high_val[8]),
.low(c_low_val[8]),
.initial_value(c_initial_val[8]),
.mode(c_mode_val[8]),
.ph_tap(c_ph_val[8]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[8] <= c_high_val_tmp[8];
c_mode_val[8] <= c_mode_val_tmp[8];
c8_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c8_rising_edge_transfer_done)
begin
c_low_val[8] <= c_low_val_tmp[8];
end
end
assign inclk_c9 = ((c9_test_source == 0) ? fbclk : (c9_test_source == 1) ? refclk : (ic9_use_casc_in == 1) ? c8_clk : inclk_c9_from_vco);
hardcopyiii_scale_cntr c9 (.clk(inclk_c9),
.reset(areset || stop_vco),
.cout(c9_clk),
.high(c_high_val[9]),
.low(c_low_val[9]),
.initial_value(c_initial_val[9]),
.mode(c_mode_val[9]),
.ph_tap(c_ph_val[9]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[9] <= c_high_val_tmp[9];
c_mode_val[9] <= c_mode_val_tmp[9];
c9_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c9_rising_edge_transfer_done)
begin
c_low_val[9] <= c_low_val_tmp[9];
end
end
assign locked = (test_bypass_lock_detect == "on") ? pfd_locked : locked_tmp;
// Register scanclk enable
always @(negedge scanclk)
scanclkena_reg <= scanclkena;
// Negative edge flip-flop in front of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_in <= scandata;
end
end
// Scan chain
always @(posedge scanclk)
begin
if (got_first_scanclk === 1'b0)
got_first_scanclk = 1'b1;
else
scanclk_period = $time - scanclk_last_rising_edge;
if (scanclkena_reg)
begin
for (j = scan_chain_length-2; j >= 0; j = j - 1)
scan_data[j] = scan_data[j - 1];
scan_data[-1] <= scandata_in;
end
scanclk_last_rising_edge = $realtime;
end
// Scan output
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right") ? scan_data[FAST_SCAN_CHAIN-2] : scan_data[GPP_SCAN_CHAIN-2];
// Negative edge flip-flop in rear of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_out <= scandataout_tmp;
end
end
// Scan complete
always @(negedge scandone_tmp)
begin
if (got_first_scanclk === 1'b1)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" %s : C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s)", clk_num[i],i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i]);
end
// display Charge pump and loop filter values
if (pll_reconfig_display_full_setting == 1'b1)
begin
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
$display (" VCO_Post_Scale = %0d (%0d) ", vco_cur, vco_old);
end
else
begin
$display (" Charge Pump Current = %0d (%0d) ", cp_curr_bit_setting, cp_curr_old_bit_setting);
$display (" Loop Filter Capacitor = %0d (%0d) ", lfc_val_bit_setting, lfc_val_old_bit_setting);
$display (" Loop Filter Resistor = %0d (%0d) ", lfr_val_bit_setting, lfr_val_old_bit_setting);
$display (" VCO_Post_Scale = %b (%b) ", vco_val_bit_setting, vco_val_old_bit_setting);
end
cp_curr_old_bit_setting = cp_curr_bit_setting;
lfc_val_old_bit_setting = lfc_val_bit_setting;
lfr_val_old_bit_setting = lfr_val_bit_setting;
vco_val_old_bit_setting = vco_val_bit_setting;
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
// ************ PLL Phase Reconfiguration ************* //
// Latch updown,counter values at pos edge of scan clock
always @(posedge scanclk)
begin
if (phasestep_reg == 1'b1)
begin
if (phasestep_high_count == 1)
begin
phasecounterselect_reg <= phasecounterselect;
phaseupdown_reg <= phaseupdown;
// start reconfiguration
if (phasecounterselect < 4'b1100) // no counters selected
begin
if (phasecounterselect == 0) // all output counters selected
begin
for (i = 0; i < num_output_cntrs; i = i + 1)
c_ph_val_tmp[i] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[i] + 1) % num_phase_taps :
(c_ph_val_tmp[i] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[i] - 1) % num_phase_taps ;
end
else if (phasecounterselect == 1) // select M counter
begin
m_ph_val_tmp = (phaseupdown == 1'b1) ?
(m_ph_val + 1) % num_phase_taps :
(m_ph_val == 0) ? num_phase_taps - 1 : (m_ph_val - 1) % num_phase_taps ;
end
else // select C counters
begin
select_counter = phasecounterselect - 2;
c_ph_val_tmp[select_counter] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[select_counter] + 1) % num_phase_taps :
(c_ph_val_tmp[select_counter] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[select_counter] - 1) % num_phase_taps ;
end
update_phase <= 1'b1;
end
end
phasestep_high_count = phasestep_high_count + 1;
end
end
// Latch phase enable (same as phasestep) on neg edge of scan clock
always @(negedge scanclk)
begin
phasestep_reg <= phasestep;
end
always @(posedge phasestep)
begin
if (update_phase == 1'b0) phasestep_high_count = 0; // phase adjustments must be 1 cycle apart
// if not, next phasestep cycle is skipped
end
// ************ PLL Full Reconfiguration ************* //
assign update_conf_latches = configupdate;
// reset counter transfer flags
always @(negedge scandone_tmp)
begin
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
c6_rising_edge_transfer_done = 0;
c7_rising_edge_transfer_done = 0;
c8_rising_edge_transfer_done = 0;
c9_rising_edge_transfer_done = 0;
update_conf_latches_reg <= 1'b0;
end
always @(posedge update_conf_latches)
begin
initiate_reconfig <= 1'b1;
end
always @(posedge areset)
begin
if (scandone_tmp == 1'b1) scandone_tmp = 1'b0;
end
always @(posedge scanclk)
begin
if (initiate_reconfig == 1'b1)
begin
initiate_reconfig <= 1'b0;
$display ("NOTE : PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
scandone_tmp <= #(scanclk_period) 1'b1;
update_conf_latches_reg <= update_conf_latches;
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
vco_old = vco_cur;
// save old values of bit settings
cp_curr_bit_setting = scan_data[14:16];
lfc_val_bit_setting = scan_data[1:2];
lfr_val_bit_setting = scan_data[3:7];
vco_val_bit_setting = scan_data[8];
// LF unused : bit 1
// LF Capacitance : bits 1,2 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
lfc_val = fpll_loop_filter_c_arr[scan_data[1:2]];
else
lfc_val = loop_filter_c_arr[scan_data[1:2]];
// LF Resistance : bits 3-7
// valid values - 00000,00100,10000,10100,11000,11011,11100,11110
if (((scan_data[3:7] == 5'b00000) || (scan_data[3:7] == 5'b00100)) ||
((scan_data[3:7] == 5'b10000) || (scan_data[3:7] == 5'b10100)) ||
((scan_data[3:7] == 5'b11000) || (scan_data[3:7] == 5'b11011)) ||
((scan_data[3:7] == 5'b11100) || (scan_data[3:7] == 5'b11110))
)
begin
lfr_val = (scan_data[3:7] == 5'b00000) ? "20" :
(scan_data[3:7] == 5'b00100) ? "16" :
(scan_data[3:7] == 5'b10000) ? "12" :
(scan_data[3:7] == 5'b10100) ? "8" :
(scan_data[3:7] == 5'b11000) ? "6" :
(scan_data[3:7] == 5'b11011) ? "4" :
(scan_data[3:7] == 5'b11100) ? "2" : "1";
end
//VCO post scale value
if (scan_data[8] === 1'b1) // vco_post_scale = 1
begin
i_vco_max = i_vco_max_no_division/2;
i_vco_min = i_vco_min_no_division/2;
vco_cur = 1;
end
else
begin
i_vco_max = vco_max;
i_vco_min = vco_min;
vco_cur = 2;
end
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
cp_curr_val = scan_data[14:16];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
for (i=0; i< num_output_cntrs; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// M counter
// 1. Mode - bypass (bit 17)
if (scan_data[17] == 1'b1)
m_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 26)
else if (scan_data[26] == 1'b1)
m_mode_val[0] = " odd";
else
m_mode_val[0] = " even";
// 2. High (bit 18-25)
m_hi = scan_data[18:25];
// 4. Low (bit 27-34)
m_lo = scan_data[27:34];
// N counter
// 1. Mode - bypass (bit 35)
if (scan_data[35] == 1'b1)
n_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 44)
else if (scan_data[44] == 1'b1)
n_mode_val[0] = " odd";
else
n_mode_val[0] = " even";
// 2. High (bit 36-43)
n_hi = scan_data[36:43];
// 4. Low (bit 45-52)
n_lo = scan_data[45:52];
//Update the current M and N counter values if the counters are NOT bypassed
if (m_mode_val[0] != "bypass")
m_val[0] = m_hi + m_lo;
if (n_mode_val[0] != "bypass")
n_val[0] = n_hi + n_lo;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (scan_data[53 + i*18 + 0] == 1'b1)
c_mode_val_tmp[i] = "bypass";
// 3. Mode - odd/even
else if (scan_data[53 + i*18 + 9] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
// 2. Hi
for (j = 1; j <= 8; j = j + 1)
c_val[8-j] = scan_data[53 + i*18 + j];
c_hval[i] = c_val[7:0];
if (c_hval[i] !== 32'h00000000)
c_high_val_tmp[i] = c_hval[i];
else
c_high_val_tmp[i] = 9'b100000000;
// 4. Low
for (j = 10; j <= 17; j = j + 1)
c_val[17 - j] = scan_data[53 + i*18 + j];
c_lval[i] = c_val[7:0];
if (c_lval[i] !== 32'h00000000)
c_low_val_tmp[i] = c_lval[i];
else
c_low_val_tmp[i] = 9'b100000000;
end
// Legality Checks
if (m_mode_val[0] != "bypass")
begin
if ((m_hi !== m_lo) && (m_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (m_hi !== 8'b00000000)
begin
// counter value
m_val_tmp[0] = m_hi + m_lo;
end
else
m_val_tmp[0] = 9'b100000000;
end
else
m_val_tmp[0] = 8'b00000001;
if (n_mode_val[0] != "bypass")
begin
if ((n_hi !== n_lo) && (n_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The N counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (n_hi !== 8'b00000000)
begin
// counter value
n_val[0] = n_hi + n_lo;
end
else
n_val[0] = 9'b100000000;
end
else
n_val[0] = 8'b00000001;
// TODO : Give warnings/errors in the following cases?
// 1. Illegal counter values (error)
// 2. Change of mode (warning)
// 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
end
end
// Self reset on loss of lock
assign reset_self = (l_self_reset_on_loss_lock == "on") ? ~pll_is_locked : 1'b0;
always @(posedge reset_self)
begin
$display (" Note : %s PLL self reset due to loss of lock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// Phase shift on /o counters
always @(schedule_vco or areset)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset === 1'b1 && areset_last_value !== areset)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
tap0_is_active = 0;
phase_adjust_was_scheduled = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// illegal value on areset
if (areset === 1'bx && (areset_last_value === 1'b0 || areset_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((areset == 1'b1))
begin
pll_is_in_reset = 1;
got_first_refclk = 0;
got_second_refclk = 0;
end
if ((schedule_vco !== schedule_vco_last_value) && (areset == 1'b1 || stop_vco == 1'b1))
begin
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end else if (areset === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset === 1'b0 && areset_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
locked_tmp = 1'b0;
end
pll_is_in_reset = 0;
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
pull_back_M = initial_delay + fbk_phase;
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_last_value = areset;
schedule_vco_last_value = schedule_vco;
end
assign pfdena_wire = (pfdena === 1'b0) ? 1'b0 : 1'b1;
// PFD enable
always @(pfdena_wire)
begin
if (pfdena_wire === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_wire === 1'b1 && pfdena_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_last_value = pfdena_wire;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
// Bypass lock detect
always @(posedge refclk)
begin
if (test_bypass_lock_detect == "on")
begin
if (pfdena_wire === 1'b1)
begin
cycles_pfd_low = 0;
if (pfd_locked == 1'b0)
begin
if (cycles_pfd_high == lock_high)
begin
$display ("Note : %s PLL locked in test mode on PFD enable assert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b1;
end
cycles_pfd_high = cycles_pfd_high + 1;
end
end
if (pfdena_wire === 1'b0)
begin
cycles_pfd_high = 0;
if (pfd_locked == 1'b1)
begin
if (cycles_pfd_low == lock_low)
begin
$display ("Note : %s PLL lost lock in test mode on PFD enable deassert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b0;
end
cycles_pfd_low = cycles_pfd_low + 1;
end
end
end
end
always @(posedge scandone_tmp or posedge locked_tmp)
begin
if(scandone_tmp == 1)
pll_has_just_been_reconfigured <= 1;
else
pll_has_just_been_reconfigured <= 0;
end
// VCO Frequency Range check
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((i_vco_max != 0 && i_vco_min != 0) && (pfdena_wire === 1'b1) &&
((refclk_period/loop_xplier > i_vco_max) ||
(refclk_period/loop_xplier < i_vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
vco_over = 1'b0;
vco_under = 1'b0;
inclk_out_of_range = 0;
no_warn = 1'b0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
// Update M counter value on feedback clock edge
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (update_conf_latches === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_wire === 1'b1 && pll_is_locked === 1'b1) ||
( ($time - refclk_time > 5 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 0) ) ||
( ($time - refclk_time > 50 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 1) ) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.", family_name);
if ((i_vco_max == 0) && (i_vco_min == 0))
$display ("Note : Please run timing simulation to check whether the input clock is operating within the supported VCO range or not.");
$display ("Time: %0t Instance: %m", $time);
end
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
// Core lock functionality
if (got_second_refclk && pfdena_wire === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= lock_window || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
// considered in phase
if (cycles_to_lock == real_lock_high)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == lock_low)
begin
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = abs(m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = abs(m_times_vco_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : i_clk0_counter == "c6" ? c6_clk : i_clk0_counter == "c7" ? c7_clk : i_clk0_counter == "c8" ? c8_clk : i_clk0_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : i_clk1_counter == "c6" ? c6_clk : i_clk1_counter == "c7" ? c7_clk : i_clk1_counter == "c8" ? c8_clk : i_clk1_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : i_clk2_counter == "c6" ? c6_clk : i_clk2_counter == "c7" ? c7_clk : i_clk2_counter == "c8" ? c8_clk : i_clk2_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : i_clk3_counter == "c6" ? c6_clk : i_clk3_counter == "c7" ? c7_clk : i_clk3_counter == "c8" ? c8_clk : i_clk3_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : i_clk4_counter == "c6" ? c6_clk : i_clk4_counter == "c7" ? c7_clk : i_clk4_counter == "c8" ? c8_clk : i_clk4_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : i_clk5_counter == "c6" ? c6_clk : i_clk5_counter == "c7" ? c7_clk : i_clk5_counter == "c8" ? c8_clk : i_clk5_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[6] = i_clk6_counter == "c0" ? c0_clk : i_clk6_counter == "c1" ? c1_clk : i_clk6_counter == "c2" ? c2_clk : i_clk6_counter == "c3" ? c3_clk : i_clk6_counter == "c4" ? c4_clk : i_clk6_counter == "c5" ? c5_clk : i_clk6_counter == "c6" ? c6_clk : i_clk6_counter == "c7" ? c7_clk : i_clk6_counter == "c8" ? c8_clk : i_clk6_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[7] = i_clk7_counter == "c0" ? c0_clk : i_clk7_counter == "c1" ? c1_clk : i_clk7_counter == "c2" ? c2_clk : i_clk7_counter == "c3" ? c3_clk : i_clk7_counter == "c4" ? c4_clk : i_clk7_counter == "c5" ? c5_clk : i_clk7_counter == "c6" ? c6_clk : i_clk7_counter == "c7" ? c7_clk : i_clk7_counter == "c8" ? c8_clk : i_clk7_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[8] = i_clk8_counter == "c0" ? c0_clk : i_clk8_counter == "c1" ? c1_clk : i_clk8_counter == "c2" ? c2_clk : i_clk8_counter == "c3" ? c3_clk : i_clk8_counter == "c4" ? c4_clk : i_clk8_counter == "c5" ? c5_clk : i_clk8_counter == "c6" ? c6_clk : i_clk8_counter == "c7" ? c7_clk : i_clk8_counter == "c8" ? c8_clk : i_clk8_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[9] = i_clk9_counter == "c0" ? c0_clk : i_clk9_counter == "c1" ? c1_clk : i_clk9_counter == "c2" ? c2_clk : i_clk9_counter == "c3" ? c3_clk : i_clk9_counter == "c4" ? c4_clk : i_clk9_counter == "c5" ? c5_clk : i_clk9_counter == "c6" ? c6_clk : i_clk9_counter == "c7" ? c7_clk : i_clk9_counter == "c8" ? c8_clk : i_clk9_counter == "c9" ? c9_clk : 1'b0;
assign clk_out_pfd[0] = (pfd_locked == 1'b1) ? clk_tmp[0] : 1'bx;
assign clk_out_pfd[1] = (pfd_locked == 1'b1) ? clk_tmp[1] : 1'bx;
assign clk_out_pfd[2] = (pfd_locked == 1'b1) ? clk_tmp[2] : 1'bx;
assign clk_out_pfd[3] = (pfd_locked == 1'b1) ? clk_tmp[3] : 1'bx;
assign clk_out_pfd[4] = (pfd_locked == 1'b1) ? clk_tmp[4] : 1'bx;
assign clk_out_pfd[5] = (pfd_locked == 1'b1) ? clk_tmp[5] : 1'bx;
assign clk_out_pfd[6] = (pfd_locked == 1'b1) ? clk_tmp[6] : 1'bx;
assign clk_out_pfd[7] = (pfd_locked == 1'b1) ? clk_tmp[7] : 1'bx;
assign clk_out_pfd[8] = (pfd_locked == 1'b1) ? clk_tmp[8] : 1'bx;
assign clk_out_pfd[9] = (pfd_locked == 1'b1) ? clk_tmp[9] : 1'bx;
assign clk_out[0] = (test_bypass_lock_detect == "on") ? clk_out_pfd[0] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx);
assign clk_out[1] = (test_bypass_lock_detect == "on") ? clk_out_pfd[1] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx);
assign clk_out[2] = (test_bypass_lock_detect == "on") ? clk_out_pfd[2] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx);
assign clk_out[3] = (test_bypass_lock_detect == "on") ? clk_out_pfd[3] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx);
assign clk_out[4] = (test_bypass_lock_detect == "on") ? clk_out_pfd[4] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx);
assign clk_out[5] = (test_bypass_lock_detect == "on") ? clk_out_pfd[5] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[5] : 1'bx);
assign clk_out[6] = (test_bypass_lock_detect == "on") ? clk_out_pfd[6] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[6] : 1'bx);
assign clk_out[7] = (test_bypass_lock_detect == "on") ? clk_out_pfd[7] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[7] : 1'bx);
assign clk_out[8] = (test_bypass_lock_detect == "on") ? clk_out_pfd[8] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[8] : 1'bx);
assign clk_out[9] = (test_bypass_lock_detect == "on") ? clk_out_pfd[9] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[9] : 1'bx);
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (clk[5], 1'b1, clk_out[5]);
and (clk[6], 1'b1, clk_out[6]);
and (clk[7], 1'b1, clk_out[7]);
and (clk[8], 1'b1, clk_out[8]);
and (clk[9], 1'b1, clk_out[9]);
and (scandataout, 1'b1, scandata_out);
and (scandone, 1'b1, scandone_tmp);
assign fbout = fbclk;
assign vcooverrange = (vco_range_detector_high_bits == -1) ? 1'bz : vco_over;
assign vcounderrange = (vco_range_detector_low_bits == -1) ? 1'bz :vco_under;
assign phasedone = ~update_phase;
endmodule // hardcopyiii_pll
//---------------------------------------------------------------------
//
// Module Name : hardcopyiii_asmiblock
//
// Description : HARDCOPYIII ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_asmiblock
(
dclkin,
scein,
sdoin,
data0in,
oe,
dclkout,
sceout,
sdoout,
data0out
);
input dclkin;
input scein;
input sdoin;
input data0in;
input oe;
output dclkout;
output sceout;
output sdoout;
output data0out;
parameter lpm_type = "hardcopyiii_asmiblock";
endmodule // hardcopyiii_asmiblock
//---------------------------------------------------------------------
//
// Module Name : hardcopyiii_tsdblock
//
// Description : HARDCOPYIII TSDBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_tsdblock
(
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output [7:0] tsdcalo;
output tsdcaldone;
output tsdcompout;
output [5:0] offsetout;
parameter poi_cal_temperature = 85;
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter user_offset_enable = "off";
parameter lpm_type = "hardcopyiii_tsdblock";
endmodule // hardcopyiii_tsdblock
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_rx_fifo_sync_ram
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg [0:5] ram_d;
reg [0:5] ram_q;
wire [0:5] data_reg;
integer i;
initial
begin
dataout_tmp = 0;
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
// Write port
always @(posedge clk or posedge write_reset)
begin
if(write_reset == 1'b1)
begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
else begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= ram_d[i];
end
end
always @(we or data_reg or ram_q)
begin
if(we === 1'b1)
begin
ram_d <= data_reg;
end
else begin
ram_d <= ram_q;
end
end
// Read port
assign data_reg[0] = ( waddr == 3'b000 ) ? datain : ram_q[0];
assign data_reg[1] = ( waddr == 3'b001 ) ? datain : ram_q[1];
assign data_reg[2] = ( waddr == 3'b010 ) ? datain : ram_q[2];
assign data_reg[3] = ( waddr == 3'b011 ) ? datain : ram_q[3];
assign data_reg[4] = ( waddr == 3'b100 ) ? datain : ram_q[4];
assign data_reg[5] = ( waddr == 3'b101 ) ? datain : ram_q[5];
always @(ram_q or we or waddr or raddr)
begin
case ( raddr )
3'b000 : dataout_tmp = ram_q[0];
3'b001 : dataout_tmp = ram_q[1];
3'b010 : dataout_tmp = ram_q[2];
3'b011 : dataout_tmp = ram_q[3];
3'b100 : dataout_tmp = ram_q[4];
3'b101 : dataout_tmp = ram_q[5];
default : dataout_tmp = 0;
endcase
end
// set output
assign dataout = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_rx_fifo
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
wire data_out;
integer i;
reg ram_datain;
wire ram_dataout;
reg [2:0] wrPtr,rdPtr; // writer pointer, read pointer
wire [2:0] rdAddr; // read address
reg ram_we;
reg wclk_last_value, rclk_last_value;
reg write_side_sync_reset;
reg read_side_sync_reset;
specify
(posedge rclk => (dataout +: data_out)) = (0, 0);
(posedge dparst => (dataout +: data_out)) = (0, 0);
endspecify
initial
begin
dataout_tmp = 0;
wrPtr = 2'b00;
rdPtr = 2'b11;
write_side_sync_reset = 1'b0;
read_side_sync_reset = 1'b0;
end
assign rdAddr = rdPtr;
hardcopyiii_lvds_rx_fifo_sync_ram s_fifo_ram (
.clk(wclk),
.datain(ram_datain),
.write_reset(write_side_sync_reset),
.waddr(wrPtr),
.raddr(rdAddr), // rdPtr ??
.we(ram_we),
.dataout(ram_dataout)
);
// update pointer and RAM input
always @(wclk or dparst)
begin
if (dparst === 1'b1 || (fiforst === 1'b1 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b1;
ram_datain <= 1'b0;
wrPtr <= 0;
ram_we <= 'b0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b0;
end
if (wclk === 1'b1 && wclk_last_value === 1'b0 && write_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
ram_datain <= datain; // input register
ram_we <= 'b1;
wrPtr <= wrPtr + 1;
if (wrPtr == 5)
wrPtr <= 0;
end
wclk_last_value = wclk;
end
always @(rclk or dparst)
begin
if (dparst === 1'b1 || (fiforst === 1'b1 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 1'b1;
rdPtr <= 3;
dataout_tmp <= 0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 0;
end
if (rclk === 1'b1 && rclk_last_value === 1'b0 && read_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
rdPtr <= rdPtr + 1;
if (rdPtr == 5)
rdPtr <= 0;
dataout_tmp <= ram_dataout; // output register
end
rclk_last_value = rclk;
end
assign data_out = dataout_tmp;
buf (dataout, data_out);
endmodule // hardcopyiii_lvds_rx_fifo
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_rx_bitslip
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_rx_bitslip (
clk0,
bslipcntl,
bsliprst,
datain,
bslipmax,
dataout
);
parameter channel_width = 10;
parameter bitslip_rollover = 12;
parameter x_on_bitslip = "on";
// INPUT PORTS
input clk0;
input bslipcntl;
input bsliprst;
input datain;
// OUTPUT PORTS
output bslipmax;
output dataout;
// INTERNAL VARIABLES AND NETS
integer slip_count;
integer i, j;
wire dataout_tmp;
wire dataout_wire;
wire bslipmax_wire;
reg clk0_last_value;
reg bsliprst_last_value;
reg bslipcntl_last_value;
reg start_corrupt_bits;
reg [1:0] num_corrupt_bits;
reg [11:0] bitslip_arr;
reg bslipmax_tmp;
reg ix_on_bitslip;
wire bslipcntl_reg;
// TIMING PATHS
specify
(posedge clk0 => (bslipmax +: bslipmax_tmp)) = (0, 0);
(posedge bsliprst => (bslipmax +: bslipmax_tmp)) = (0, 0);
endspecify
initial
begin
slip_count = 0;
bslipmax_tmp = 0;
bitslip_arr = 12'b0;
start_corrupt_bits = 0;
num_corrupt_bits = 0;
if (x_on_bitslip == "on")
ix_on_bitslip = 1;
else
ix_on_bitslip = 0;
end
hardcopyiii_lvds_reg bslipcntlreg (
.d(bslipcntl),
.clk(clk0),
.ena(1'b1),
.clrn(!bsliprst),
.prn(1'b1),
.q(bslipcntl_reg)
);
// 4-bit slip counter
always @(bslipcntl_reg or bsliprst)
begin
if (bsliprst === 1'b1)
begin
slip_count <= 0;
bslipmax_tmp <= 1'b0;
if (bsliprst === 1'b1 && bsliprst_last_value === 1'b0)
begin
$display("Note: Bit Slip Circuit was reset. Serial Data stream will have 0 latency");
$display("Time: %0t, Instance: %m", $time);
end
end
else if (bslipcntl_reg === 1'b1 && bslipcntl_last_value === 1'b0)
begin
if (ix_on_bitslip == 1)
start_corrupt_bits <= 1;
num_corrupt_bits <= 0;
if (slip_count == bitslip_rollover)
begin
$display("Note: Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency.");
$display("Time: %0t, Instance: %m", $time);
slip_count <= 0;
bslipmax_tmp <= 1'b0;
end
else
begin
slip_count <= slip_count + 1;
if ((slip_count+1) == bitslip_rollover)
begin
$display("Note: The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip.");
$display("Time: %0t, Instance: %m", $time);
bslipmax_tmp <= 1'b1;
end
end
end
else if (bslipcntl_reg === 1'b0 && bslipcntl_last_value === 1'b1)
begin
start_corrupt_bits <= 0;
num_corrupt_bits <= 0;
end
bslipcntl_last_value <= bslipcntl_reg;
bsliprst_last_value <= bsliprst;
end
// Bit Slip shift register
always @(clk0)
begin
if (clk0 === 1'b1 && clk0_last_value === 1'b0)
begin
bitslip_arr[0] <= datain;
for (i = 0; i < bitslip_rollover; i=i+1)
bitslip_arr[i+1] <= bitslip_arr[i];
if (start_corrupt_bits == 1'b1)
num_corrupt_bits <= num_corrupt_bits + 1;
if (num_corrupt_bits+1 == 3)
start_corrupt_bits <= 0;
end
clk0_last_value <= clk0;
end
hardcopyiii_lvds_reg dataoutreg (
.d(bitslip_arr[slip_count]),
.clk(clk0),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(dataout_tmp)
);
assign dataout_wire = (start_corrupt_bits == 1'b0) ? dataout_tmp : (num_corrupt_bits < 3) ? 1'bx : dataout_tmp;
assign bslipmax_wire = bslipmax_tmp;
and (dataout, dataout_wire, 1'b1);
and (bslipmax, bslipmax_wire, 1'b1);
endmodule // hardcopyiii_lvds_rx_bitslip
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_rx_deser
//
// Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
// Deserializer. This module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_rx_deser (
clk,
datain,
devclrn,
devpor,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input clk;
input datain;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg [channel_width - 1:0] dataout_tmp;
reg clk_last_value;
integer i;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devclrn or devpor)
begin
if (devclrn === 1'b0 || devpor === 1'b0)
begin
dataout_tmp <= 'b0;
end
else if (clk === 1'b1 && clk_last_value === 1'b0)
begin
for (i = (channel_width-1); i > 0; i=i-1)
dataout_tmp[i] <= dataout_tmp[i-1];
dataout_tmp[0] <= datain;
end
clk_last_value <= clk;
end
assign dataout = dataout_tmp;
endmodule //hardcopyiii_lvds_rx_deser
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_rx_parallel_reg
//
// Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
// PARALLEL REGISTER. The data width equals max. channel width,
// which is 10.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk === 1) && (clk_last_value !== clk))
begin
if (enable === 1)
begin
dataout_tmp <= datain;
end
end
end
clk_last_value <= clk;
end //always
assign dataout = dataout_tmp;
endmodule //hardcopyiii_lvds_rx_parallel_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_lvds_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module hardcopyiii_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk == 1) & (ena == 1'b1))
q_tmp <= d;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // hardcopyiii_lvds_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_pclk_divider
//
// Description : Simulation model for a clock divider
// output clock is divided by value specified
// in the parameter clk_divide_by
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module hardcopyiii_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by =1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg[4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin :clkout_tmp;
assign lloaden = lloaden_tmp;
initial
begin
clkout_tmp = 1'b0;
cnt = 5'b00000;
start = 1'b0;
count = 1'b0;
lloaden_tmp = 1'b0;
end
always @(clkin)
begin
if (clkin == 1'b1 )
begin
count = 1'b1;
end
if(count == 1'b1)
begin
if(cnt < clk_divide_by)
begin
clkout_tmp = 1'b0;
cnt = cnt + 1'b1;
end
else
begin
if(cnt == 2*clk_divide_by -1)
cnt = 0;
else
begin
clkout_tmp = 1'b1;
cnt = cnt + 1;
end
end
end
end
always@( clkin or cnt )
begin
if( cnt == 2*clk_divide_by -2)
lloaden_tmp = 1'b1;
else if(cnt == 0)
lloaden_tmp = 1'b0;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_select_ini_phase_dpaclk
//
// Description : Simulation model for selecting the initial phase of the dpa clock
//
//
///////////////////////////////////////////////////////////////////////////////
module hardcopyiii_select_ini_phase_dpaclk(
clkin,
loaden,
enable,
clkout,
loadenout
);
parameter initial_phase_select = 0;
input clkin;
input enable;
input loaden;
output clkout;
output loadenout;
wire clkout_tmp;
wire loadenout_tmp;
real clk_period, last_clk_period;
real last_clkin_edge;
reg first_clkin_edge_detect;
reg clk0_tmp;
reg clk1_tmp;
reg clk2_tmp;
reg clk3_tmp;
reg clk4_tmp;
reg clk5_tmp;
reg clk6_tmp;
reg clk7_tmp;
reg loaden0_tmp;
reg loaden1_tmp;
reg loaden2_tmp;
reg loaden3_tmp;
reg loaden4_tmp;
reg loaden5_tmp;
reg loaden6_tmp;
reg loaden7_tmp;
assign clkout_tmp = (initial_phase_select == 1) ? clk1_tmp :
(initial_phase_select == 2) ? clk2_tmp :
(initial_phase_select == 3) ? clk3_tmp :
(initial_phase_select == 4) ? clk4_tmp :
(initial_phase_select == 5) ? clk5_tmp :
(initial_phase_select == 6) ? clk6_tmp :
(initial_phase_select == 7) ? clk7_tmp :
clk0_tmp;
assign loadenout_tmp = (initial_phase_select == 1) ? loaden1_tmp :
(initial_phase_select == 2) ? loaden2_tmp :
(initial_phase_select == 3) ? loaden3_tmp :
(initial_phase_select == 4) ? loaden4_tmp :
(initial_phase_select == 5) ? loaden5_tmp :
(initial_phase_select == 6) ? loaden6_tmp :
(initial_phase_select == 7) ? loaden7_tmp :
loaden0_tmp;
assign clkout = (enable == 1'b1) ? clkout_tmp : clkin;
assign loadenout = (enable == 1'b1) ? loadenout_tmp : loaden;
initial
begin
first_clkin_edge_detect = 1'b0;
end
always @(posedge clkin)
begin
// Determine the clock frequency
if (first_clkin_edge_detect == 1'b0)
begin
first_clkin_edge_detect = 1'b1;
end
else
begin
last_clk_period = clk_period;
clk_period = $realtime - last_clkin_edge;
end
last_clkin_edge = $realtime;
end
//assign phase shifted clock and data values
always@(clkin)
begin
clk0_tmp <= clkin;
clk1_tmp <= #(clk_period * 0.125) clkin;
clk2_tmp <= #(clk_period * 0.25) clkin;
clk3_tmp <= #(clk_period * 0.375) clkin;
clk4_tmp <= #(clk_period * 0.5) clkin;
clk5_tmp <= #(clk_period * 0.625) clkin;
clk6_tmp <= #(clk_period * 0.75) clkin;
clk7_tmp <= #(clk_period * 0.875) clkin;
end
always@(loaden)
begin
loaden0_tmp <= loaden;
loaden1_tmp <= #(clk_period * 0.125) loaden;
loaden2_tmp <= #(clk_period * 0.25) loaden;
loaden3_tmp <= #(clk_period * 0.375) loaden;
loaden4_tmp <= #(clk_period * 0.5) loaden;
loaden5_tmp <= #(clk_period * 0.625) loaden;
loaden6_tmp <= #(clk_period * 0.75) loaden;
loaden7_tmp <= #(clk_period * 0.875) loaden;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_dpa_retime_block
//
// Description : Simulation model for generating the retimed clock,data and loaden.
// Each of the signals has 8 different phase shifted versions.
//
//
///////////////////////////////////////////////////////////////////////////////
module hardcopyiii_dpa_retime_block(
clkin,
datain,
reset,
clk0,
clk1,
clk2,
clk3,
clk4,
clk5,
clk6,
clk7,
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
lock
);
input clkin;
input datain;
input reset;
output clk0;
output clk1;
output clk2;
output clk3;
output clk4;
output clk5;
output clk6;
output clk7;
output data0;
output data1;
output data2;
output data3;
output data4;
output data5;
output data6;
output data7;
output lock;
real clk_period, last_clk_period;
real last_clkin_edge;
reg first_clkin_edge_detect;
reg clk0_tmp;
reg clk1_tmp;
reg clk2_tmp;
reg clk3_tmp;
reg clk4_tmp;
reg clk5_tmp;
reg clk6_tmp;
reg clk7_tmp;
reg data0_tmp;
reg data1_tmp;
reg data2_tmp;
reg data3_tmp;
reg data4_tmp;
reg data5_tmp;
reg data6_tmp;
reg data7_tmp;
reg lock_tmp;
assign clk0 = (reset == 1'b1) ? 1'b0 : clk0_tmp;
assign clk1 = (reset == 1'b1) ? 1'b0 : clk1_tmp;
assign clk2 = (reset == 1'b1) ? 1'b0 : clk2_tmp;
assign clk3 = (reset == 1'b1) ? 1'b0 : clk3_tmp;
assign clk4 = (reset == 1'b1) ? 1'b0 : clk4_tmp;
assign clk5 = (reset == 1'b1) ? 1'b0 : clk5_tmp;
assign clk6 = (reset == 1'b1) ? 1'b0 : clk6_tmp;
assign clk7 = (reset == 1'b1) ? 1'b0 : clk7_tmp;
assign data0 =(reset == 1'b1) ? 1'b0 : data0_tmp;
assign data1 =(reset == 1'b1) ? 1'b0 : data1_tmp;
assign data2 =(reset == 1'b1) ? 1'b0 : data2_tmp;
assign data3 =(reset == 1'b1) ? 1'b0 : data3_tmp;
assign data4 =(reset == 1'b1) ? 1'b0 : data4_tmp;
assign data5 =(reset == 1'b1) ? 1'b0 : data5_tmp;
assign data6 =(reset == 1'b1) ? 1'b0 : data6_tmp;
assign data7 =(reset == 1'b1) ? 1'b0 : data7_tmp;
assign lock = (reset == 1'b1) ? 1'b0 : lock_tmp;
initial
begin
first_clkin_edge_detect = 1'b0;
lock_tmp = 1'b0;
end
always @(posedge clkin)
begin
// Determine the clock frequency
if (first_clkin_edge_detect == 1'b0)
begin
first_clkin_edge_detect = 1'b1;
end
else
begin
last_clk_period = clk_period;
clk_period = $realtime - last_clkin_edge;
end
last_clkin_edge = $realtime;
//assign dpa lock
if(((clk_period ==last_clk_period) ||(clk_period == last_clk_period-1) || (clk_period ==last_clk_period +1)) && (clk_period != 0) && (last_clk_period != 0))
lock_tmp = 1'b1;
else
lock_tmp = 1'b0;
end
//assign phase shifted clock and data values
always@(clkin)
begin
clk0_tmp <= clkin;
clk1_tmp <= #(clk_period * 0.125) clkin;
clk2_tmp <= #(clk_period * 0.25) clkin;
clk3_tmp <= #(clk_period * 0.375) clkin;
clk4_tmp <= #(clk_period * 0.5) clkin;
clk5_tmp <= #(clk_period * 0.625) clkin;
clk6_tmp <= #(clk_period * 0.75) clkin;
clk7_tmp <= #(clk_period * 0.875) clkin;
end
always@(datain)
begin
data0_tmp <= datain;
data1_tmp <= #(clk_period * 0.125) datain;
data2_tmp <= #(clk_period * 0.25) datain;
data3_tmp <= #(clk_period * 0.375) datain;
data4_tmp <= #(clk_period * 0.5) datain;
data5_tmp <= #(clk_period * 0.625) datain;
data6_tmp <= #(clk_period * 0.75) datain;
data7_tmp <= #(clk_period * 0.875) datain;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_dpa_block
//
// Description : Simulation model for selecting the retimed data, clock and loaden
// depending on the PPM varaiation and direction of shift.
//
///////////////////////////////////////////////////////////////////////////////
module hardcopyiii_dpa_block(clkin,
dpareset,
dpahold,
datain,
clkout,
dataout,
dpalock
);
parameter net_ppm_variation = 0;
parameter is_negative_ppm_drift = "off";
parameter enable_soft_cdr_mode= "on";
input clkin ;
input dpareset ;
input dpahold ;
input datain ;
output clkout;
output dataout;
output dpalock;
wire clk0_tmp;
wire clk1_tmp;
wire clk2_tmp;
wire clk3_tmp;
wire clk4_tmp;
wire clk5_tmp;
wire clk6_tmp;
wire clk7_tmp;
wire data0_tmp;
wire data1_tmp;
wire data2_tmp;
wire data3_tmp;
wire data4_tmp;
wire data5_tmp;
wire data6_tmp;
wire data7_tmp;
reg[2:0] select;
reg clkout_tmp ;
reg dataout_tmp;
real counter_reset_value;
integer count_value;
integer i;
initial
begin
if(net_ppm_variation != 0)
begin
counter_reset_value = 1000000/(net_ppm_variation * 8);
count_value = counter_reset_value;
end
i = 0;
select = 3'b000;
clkout_tmp = clkin;
dataout_tmp = datain;
end
assign dataout = (enable_soft_cdr_mode == "on") ? dataout_tmp : datain;
assign clkout = (enable_soft_cdr_mode == "on") ? clkout_tmp : clkin;
hardcopyiii_dpa_retime_block data_clock_retime(
.clkin(clkin),
.datain(datain),
.reset(dpareset),
.clk0(clk0_tmp),
.clk1(clk1_tmp),
.clk2(clk2_tmp),
.clk3(clk3_tmp),
.clk4(clk4_tmp),
.clk5(clk5_tmp),
.clk6(clk6_tmp),
.clk7(clk7_tmp),
.data0(data0_tmp),
.data1(data1_tmp),
.data2(data2_tmp),
.data3(data3_tmp),
.data4(data4_tmp),
.data5(data5_tmp),
.data6(data6_tmp),
.data7(data7_tmp),
.lock (dpalock)
);
always@(posedge clkin or posedge dpareset or posedge dpahold)
begin
if(net_ppm_variation == 0)
begin
select = 3'b000;
end
else
begin
if(dpareset == 1'b1)
begin
i = 0;
select = 3'b000;
end
else
begin
if(dpahold == 1'b0)
begin
if(i < count_value)
begin
i = i + 1;
end
else
begin
select = select + 1'b1;
i = 0;
end
end
end
end
end
always@(select or clk0_tmp or clk1_tmp or clk2_tmp or clk3_tmp or
clk4_tmp or clk5_tmp or clk6_tmp or clk7_tmp or
data0_tmp or data1_tmp or data2_tmp or data3_tmp or
data4_tmp or data5_tmp or data6_tmp or data7_tmp )
begin
case(select)
3'b000 :
begin
clkout_tmp = clk0_tmp;
dataout_tmp = data0_tmp;
end
3'b001:
begin
clkout_tmp = (is_negative_ppm_drift == "off") ? clk1_tmp : clk7_tmp ;
dataout_tmp =( is_negative_ppm_drift == "off") ? data1_tmp : data7_tmp ;
end
3'b010:
begin
clkout_tmp = (is_negative_ppm_drift == "off") ? clk2_tmp : clk6_tmp ;
dataout_tmp =( is_negative_ppm_drift == "off") ? data2_tmp : data6_tmp ;
end
3'b011:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk3_tmp : clk5_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data3_tmp : data5_tmp ;
end
3'b100:
begin
clkout_tmp = clk4_tmp ;
dataout_tmp = data4_tmp ;
end
3'b101:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk5_tmp : clk3_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data5_tmp : data3_tmp ;
end
3'b110:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk6_tmp : clk2_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data6_tmp : data2_tmp ;
end
3'b111:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk7_tmp : clk1_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data7_tmp : data1_tmp ;
end
default:
begin
clkout_tmp = clk0_tmp;
dataout_tmp = data0_tmp;
end
endcase
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : hardcopyiii_LVDS_RECEIVER
//
// Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
// atom. This module instantiates the following sub-modules :
// 1) hardcopyiii_lvds_rx_fifo
// 2) hardcopyiii_lvds_rx_bitslip
// 3) DFFEs for the LOADEN signals
// 4) hardcopyiii_lvds_rx_deser
// 5) hardcopyiii_lvds_rx_parallel_reg
// 6) hardcopyiii_select_ini_phase_dpaclk
// 7)hardcopyiii_dpa_block
// 8) hardcopyiii_pclk_divider
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_lvds_receiver (
clk0,
datain,
enable0,
dpareset,
dpahold,
dpaswitch,
fiforeset,
bitslip,
bitslipreset,
serialfbk,
dataout,
dpalock,
bitslipmax,
serialdataout,
postdpaserialdataout,
divfwdclk,
dpaclkout,
devclrn,
devpor
);
parameter data_align_rollover = 2;
parameter enable_dpa = "off";
parameter lose_lock_on_one_change = "off";
parameter reset_fifo_at_first_lock = "on";
parameter align_to_rising_edge_only = "on";
parameter use_serial_feedback_input = "off";
parameter dpa_debug = "off";
parameter x_on_bitslip = "on";
parameter enable_soft_cdr = "off";
parameter dpa_output_clock_phase_shift = 0;
parameter enable_dpa_initial_phase_selection = "off";
parameter dpa_initial_phase_value = 0;
parameter enable_dpa_align_to_rising_edge_only = "off";
parameter net_ppm_variation = 0;
parameter is_negative_ppm_drift = "off";
parameter rx_input_path_delay_engineering_bits = -1;
parameter lpm_type = "hardcopyiii_lvds_receiver";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input clk0;
input datain;
input enable0;
input dpareset;
input dpahold;
input dpaswitch;
input fiforeset;
input bitslip;
input bitslipreset;
input serialfbk;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
output dpalock;
output bitslipmax;
output serialdataout;
output postdpaserialdataout;
output divfwdclk;
output dpaclkout;
tri1 devclrn;
tri1 devpor;
// Input registers
wire in_reg_data;
wire datain_reg;
wire datain_reg_neg;
wire datain_reg_tmp;
// dpa phase select
wire ini_phase_select_enable;
wire ini_dpa_clk;
wire ini_dpa_load;
// dpa circuit
wire dpareg0_out;
wire dpareg1_out;
wire dpa_clk_shift;
wire dpa_data_shift;
wire dpa_enable0_shift;
wire dpa_clk;
wire dpa_rst;
wire lock_tmp;
// fifo
wire fifo_wclk;
wire fifo_rclk;
wire fifo_datain;
wire fifo_dataout;
wire fifo_reset;
reg reset_fifo;
// bitslip
wire slip_datain;
wire slip_dataout;
wire bitslip_reset;
wire slip_datain_tmp;
wire s_bitslip_clk;
//deserializer
wire [channel_width - 1:0] deser_dataout;
wire postdpaserialdataout_tmp;
wire dpalock_tmp;
wire rxload;
wire loaden;
wire lloaden;
wire divfwdclk_tmp;
wire gnd;
integer i;
// TIMING PATHS
specify
(posedge clk0 => (dpalock +: dpalock_tmp)) = (0, 0);
endspecify
assign gnd = 1'b0;
initial
begin
if (reset_fifo_at_first_lock == "on")
reset_fifo = 1;
else
reset_fifo = 0;
end
// reset_fifo at
always @(lock_tmp)
begin
reset_fifo = !lock_tmp;
end
// input register in non-DPA mode for sampling incoming data
hardcopyiii_lvds_reg in_reg (
.d(in_reg_data),
.clk(clk0),
.ena(1'b1),
.clrn(devclrn || devpor),
.prn(1'b1),
.q(datain_reg)
);
assign in_reg_data = (use_serial_feedback_input == "on") ? serialfbk : datain;
hardcopyiii_lvds_reg neg_reg (
.d(in_reg_data),
.clk(!clk0),
.ena(1'b1),
.clrn(devclrn || devpor),
.prn(1'b1),
.q(datain_reg_neg)
);
assign datain_reg_tmp = (align_to_rising_edge_only == "on") ? datain_reg : datain_reg_neg;
// Initial DPA clock phase select
hardcopyiii_select_ini_phase_dpaclk ini_clk_phase_select(
.clkin(clk0),
.enable(ini_phase_select_enable),
.loaden(enable0),
.clkout(ini_dpa_clk),
.loadenout(ini_dpa_load)
);
defparam ini_clk_phase_select.initial_phase_select = dpa_initial_phase_value;
assign ini_phase_select_enable = (enable_dpa_initial_phase_selection == "on") ? 1'b1 : 1'b0;
// DPA Circuitary
hardcopyiii_lvds_reg dpareg0 (
.d(in_reg_data),
.clk(ini_dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg0_out)
);
hardcopyiii_lvds_reg dpareg1 (
.d(dpareg0_out),
.clk(ini_dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg1_out)
);
hardcopyiii_dpa_block dpa_circuit(
.clkin(ini_dpa_clk),
.dpareset(dpa_rst),
.dpahold(dpahold),
.datain(dpareg1_out),
.clkout(dpa_clk_shift),
.dataout(dpa_data_shift),
.dpalock (lock_tmp)
);
defparam dpa_circuit.net_ppm_variation = net_ppm_variation;
defparam dpa_circuit.is_negative_ppm_drift = is_negative_ppm_drift;
defparam dpa_circuit.enable_soft_cdr_mode= enable_soft_cdr;
assign dpa_clk = ((enable_soft_cdr == "on")|| (enable_dpa == "on")) ? dpa_clk_shift : 1'b0;
assign dpa_rst = ((enable_soft_cdr == "on")|| (enable_dpa == "on")) ? dpareset : 1'b0;
// DPA clock divide and generate lloaden for soft CDR mode
hardcopyiii_pclk_divider clk_forward(
.clkin(dpa_clk),
.lloaden(lloaden),
.clkout(divfwdclk_tmp)
);
defparam clk_forward.clk_divide_by = channel_width;
// FIFO
hardcopyiii_lvds_rx_fifo s_fifo (
.wclk(dpa_clk),
.rclk(fifo_rclk),
.fiforst(fifo_reset),
.dparst(dpa_rst),
.datain(fifo_datain),
.dataout(fifo_dataout)
);
defparam s_fifo.channel_width = channel_width;
assign fifo_rclk = (enable_dpa == "on") ? clk0 : gnd;
assign fifo_wclk = dpa_clk;
assign fifo_datain = (enable_dpa == "on") ? dpa_data_shift : gnd;
assign fifo_reset = (!devpor) || (!devclrn) || fiforeset || reset_fifo || dpa_rst;
// BIT SLIP
hardcopyiii_lvds_rx_bitslip s_bslip (
.clk0(s_bitslip_clk),
.bslipcntl(bitslip),
.bsliprst(bitslip_reset),
.datain(slip_datain),
.bslipmax(bitslipmax),
.dataout(slip_dataout)
);
defparam s_bslip.channel_width = channel_width;
defparam s_bslip.bitslip_rollover = data_align_rollover;
defparam s_bslip.x_on_bitslip = x_on_bitslip;
assign bitslip_reset = (!devpor) || (!devclrn) || bitslipreset;
assign slip_datain_tmp = (enable_dpa == "on" && dpaswitch === 1'b1) ? fifo_dataout : datain_reg_tmp;
assign slip_datain = (enable_soft_cdr == "on") ? dpa_data_shift : slip_datain_tmp;
assign s_bitslip_clk = (enable_soft_cdr == "on") ? dpa_clk : clk0;
// DESERIALISER
hardcopyiii_lvds_reg rxload_reg (
.d(loaden),
.clk(s_bitslip_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(rxload)
);
assign loaden = (enable_soft_cdr == "on") ? lloaden : ini_dpa_load;
hardcopyiii_lvds_rx_deser s_deser (
.clk(s_bitslip_clk),
.datain(slip_dataout),
.devclrn(devclrn),
.devpor(devpor),
.dataout(deser_dataout)
);
defparam s_deser.channel_width = channel_width;
hardcopyiii_lvds_rx_parallel_reg output_reg (
.clk(s_bitslip_clk),
.enable(rxload),
.datain(deser_dataout),
.devpor(devpor),
.devclrn(devclrn),
.dataout(dataout)
);
defparam output_reg.channel_width = channel_width;
// generate outputs
assign dpalock_tmp = gnd;
assign postdpaserialdataout_tmp = dpa_data_shift;
assign divfwdclk = divfwdclk_tmp;
assign dpaclkout = dpa_clk_shift;
and (postdpaserialdataout, postdpaserialdataout_tmp, 1'b1);
and (serialdataout, datain, 1'b1);
and (dpalock, dpalock_tmp, 1'b1);
endmodule // hardcopyiii_lvds_receiver
//////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_pseudo_diff_out //
//Description: Simulation model for HARDCOPYIII Pseudo Differential //
// Output Buffer //
//////////////////////////////////////////////////////////////////////////////////
module hardcopyiii_pseudo_diff_out(
i,
o,
obar
);
parameter lpm_type = "hardcopyiii_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
// -----------------------------------------------------------
//
// Module Name : hardcopyiii_bias_logic
//
// Description : HARDCOPYIII Bias Block's Logic Block
// Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk)
begin
case ({captnupdt, shiftnld})
2'b10, 2'b11 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00 :
begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule // hardcopyiii_bias_logic
// -----------------------------------------------------------
//
// Module Name : hardcopyiii_bias_generator
//
// Description : HARDCOPYIII Bias Generator Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 100;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg [TOTAL_REG - 1:0];
reg update_reg [TOTAL_REG - 1:0];
integer i;
initial
begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg [i] <= 'b0;
update_reg [i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk)
begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk)
begin
dout_tmp <= update_reg[TOTAL_REG - 1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1)
begin
update_reg[i] <= update_reg[i - 1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule // hardcopyiii_bias_generator
// -----------------------------------------------------------
//
// Module Name : hardcopyiii_bias_block
//
// Description : HARDCOPYIII Bias Block Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_bias_block(
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "hardcopyiii_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold (posedge clk, din, 0, 0, din_viol) ;
$setuphold (posedge clk, shiftnld, 0, 0, shiftnld_viol) ;
$setuphold (posedge clk, captnupdt, 0, 0, captnupdt_viol) ;
(posedge clk => (dout +: dout_tmp)) = 0 ;
endspecify
hardcopyiii_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
hardcopyiii_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule // hardcopyiii_bias_block
//--------------------------------------------------------------------
//
// Module Name : hardcopyiii_jtag
//
// Description : Hcx JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "hardcopyiii_jtag";
endmodule
//------------------------------------------------------------------
//
// Module Name : hardcopyiii_lcell_hsadder
//
// Description : Hardcopy III High Speed Adder Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module hardcopyiii_lcell_hsadder (
dataa,
datab,
cin,
sumout,
cout
);
parameter dataa_width = 2;
parameter datab_width = 2;
parameter cin_inverted = "off";
parameter lpm_type = "hardcopyiii_lcell_hsadder";
// LOCAL_PARAMETERS_BEGIN
parameter sumout_width = (dataa_width >= datab_width) ? (dataa_width + 1) : (datab_width + 1);
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [dataa_width - 1 : 0] dataa;
input [datab_width - 1 : 0] datab;
input cin;
// OUTPUT PORTS
output [sumout_width - 1 : 0] sumout;
output cout;
// internal variable
wire cin_sel;
// tmp output variables
reg [sumout_width : 0] sumout_tmp;
specify
(dataa *> sumout) = (0, 0);
(datab *> sumout) = (0, 0);
(cin *> sumout) = (0, 0);
(dataa *> cout) = (0, 0);
(datab *> cout) = (0, 0);
(cin *> cout) = (0, 0);
endspecify
assign cin_sel = (cin_inverted == "on") ? !cin : cin;
always @(datab or dataa or cin_sel)
begin
sumout_tmp = dataa + datab + cin_sel;
end
assign sumout = sumout_tmp[sumout_width - 1 : 0];
assign cout = sumout_tmp[sumout_width - 1];
endmodule
////////////////////////////////////////////////////////////////////////////////////
//Module Name: hardcopyiii_otp
//Description: Simulation model for HARDCOPYIII OTP (One Time Programmable)
//
////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module hardcopyiii_otp (
otpclken,
otpclk,
otpshiftnld,
otpdout
);
//PARAMETER
parameter data_width = 128;
parameter lpm_file = "init_file.hex";
parameter lpm_type = "hardcopyiii_otp";
parameter lpm_hint = "true";
parameter init_data = 128'h0;
//Input Ports Declaration
input otpclken;
input otpclk;
input otpshiftnld;
//Output Ports Declaration
output otpdout;
//Internal Signals
reg otpdout_tmp;
reg viol_notifier;
reg first_use;
integer prev_loc;
integer current_loc;
wire reset;
specify
$setup (otpshiftnld, negedge otpclk &&& reset, 0, viol_notifier);
$hold (negedge otpclk &&& reset, otpshiftnld, 0, viol_notifier);
(otpshiftnld *> otpdout) = (0,0);
endspecify
initial
begin
prev_loc = -1;
current_loc = 0;
otpdout_tmp = 1'b0;
first_use = 1'b1;
end
assign otpdout = otpdout_tmp;
always @(prev_loc)
begin
current_loc = prev_loc + 1;
end
always @(posedge otpclk)
begin
// operation only if clock enable is high
if(otpclken == 1'b1)
begin
// shift data
if (otpshiftnld == 1'b1 && first_use == 1'b0)
begin
// shifting out '0' if otp_clken and otp_shiftnld is high beyond 128 clock cycles
if (prev_loc == 127)
begin
otpdout_tmp <= 1'b0;
end
// shifting out the data bit by bit
else
begin
otpdout_tmp <= init_data[current_loc];
prev_loc <= current_loc;
end
end
// load data
else if (otpshiftnld == 1'b0)
begin
otpdout_tmp <= init_data[0];
first_use <= 1'b0;
prev_loc <= 0;
end
end
end
endmodule // hardcopyiii_otp
`ifdef MODEL_TECH
`mti_v2k_int_delays_off
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:49:08 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n698, n699, n701, n702, n704, n705, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, DP_OP_15J58_123_4652_n8,
DP_OP_15J58_123_4652_n7, DP_OP_15J58_123_4652_n6,
DP_OP_15J58_123_4652_n5, DP_OP_15J58_123_4652_n4, intadd_65_B_4_,
intadd_65_B_3_, intadd_65_B_2_, intadd_65_B_1_, intadd_65_B_0_,
intadd_65_CI, intadd_65_SUM_4_, intadd_65_SUM_3_, intadd_65_SUM_2_,
intadd_65_SUM_1_, intadd_65_SUM_0_, intadd_65_n5, intadd_65_n4,
intadd_65_n3, intadd_65_n2, intadd_65_n1, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1750,
n1751, n1752;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1707), .Q(
Shift_reg_FLAGS_7_6), .QN(n929) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1711), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1720), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1144), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1141), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1142), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1143), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1140), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1141), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1719), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1718), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1144), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1141), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1720), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1142), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1143), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1140), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1140), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1719), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1718), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1144), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1141), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1720), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1142), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1721), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1721), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1721), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1721), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1721), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1721), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1721), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1143), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1140), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1141), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1719), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1718), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1700), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1144), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1699), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1141), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1698), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1697), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1720), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1142), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1143), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1140), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1141), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1719), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1718), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1140), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1719), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1718), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1723), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1723), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1723), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1723), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1723), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1724), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1724), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1724), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1724), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1724), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1724), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1724), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1724), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1724), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1724), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1725), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1725), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1725), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1725), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1725), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1725), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1725), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1725), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1725), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1725), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1726), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1726), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1726), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1726), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1726), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1726), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1726), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1726), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1726), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1726), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1727), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1727), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1727), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1727), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1727), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1727), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1727), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1727), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1727), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1727), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1728), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1728), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1728), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1728), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1728), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1728), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1730), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1730), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1730), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1730), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1730), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1733), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1733), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1733), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1733), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1733), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1734), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1696), .CK(clk), .RN(n1745), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1734), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1734), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1734), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1734), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1734), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[0]), .QN(n926) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[1]), .QN(n921) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[4]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[5]), .QN(n923) );
CMPR32X2TS intadd_65_U6 ( .A(n1682), .B(intadd_65_B_0_), .C(intadd_65_CI),
.CO(intadd_65_n5), .S(intadd_65_SUM_0_) );
CMPR32X2TS intadd_65_U5 ( .A(n1681), .B(intadd_65_B_1_), .C(intadd_65_n5),
.CO(intadd_65_n4), .S(intadd_65_SUM_1_) );
CMPR32X2TS intadd_65_U4 ( .A(n1680), .B(intadd_65_B_2_), .C(intadd_65_n4),
.CO(intadd_65_n3), .S(intadd_65_SUM_2_) );
CMPR32X2TS intadd_65_U3 ( .A(n1691), .B(intadd_65_B_3_), .C(intadd_65_n3),
.CO(intadd_65_n2), .S(intadd_65_SUM_3_) );
CMPR32X2TS intadd_65_U2 ( .A(n1615), .B(intadd_65_B_4_), .C(intadd_65_n2),
.CO(intadd_65_n1), .S(intadd_65_SUM_4_) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1711),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1733), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1733), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1735), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1735), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1735), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1736), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1737), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1738), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1737), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1738), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1738), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1738), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1738), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1738), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1738), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1738), .Q(
final_result_ieee[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1640) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1694) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[1]), .QN(n1752) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1735), .Q(
final_result_ieee[9]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1707), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1622) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1734), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1678) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1707), .Q(
n1617), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[4]), .QN(n1618) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[23]), .QN(n1672) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[22]), .QN(n1626) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[21]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[30]), .QN(n1673) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[29]), .QN(n1627) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[26]), .QN(n1670) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[25]), .QN(n1657) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[24]), .QN(n1687) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[25]), .QN(n1630) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[20]), .QN(n1669) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[14]), .QN(n1667) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[13]), .QN(n1661) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[12]), .QN(n1666) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[18]), .QN(n1675) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[17]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[15]), .QN(n1625) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[11]), .QN(n1643) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1712), .Q(
intDY_EWSW[8]), .QN(n1663) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[3]), .QN(n1658) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[16]), .QN(n1636) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[7]), .QN(n1619) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[6]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[5]), .QN(n1632) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1689) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1655) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1714), .Q(
Data_array_SWR[25]), .QN(n1703) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1641) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1734), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1677) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1620) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1746), .Q(
n930), .QN(n1747) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1707), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1751) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1656) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[23]), .QN(n1683) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1714), .Q(
Data_array_SWR[24]), .QN(n1704) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[14]), .QN(n1686) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[12]), .QN(n1685) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1736), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1734), .Q(
final_result_ieee[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1745), .Q(
DMP_SFG[5]), .QN(n1691) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1712), .Q(
intDY_EWSW[6]), .QN(n1648) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1142), .Q(
DMP_EXP_EWSW[24]), .QN(n1629) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[15]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1717), .Q(
shift_value_SHT2_EWR[4]), .QN(n879) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1714), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[15]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1707), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1711),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1721), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1743), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1743), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1746), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1743), .Q(
DMP_SFG[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1732), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1731), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1731), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1732), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1728), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1729), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1728), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1731), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1743), .Q(
DMP_SFG[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1732), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1729), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1728), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1745), .Q(
OP_FLAG_SFG) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1744), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1746), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1746), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1746), .Q(
DMP_SFG[9]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1744), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1743), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1746), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1746), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1746), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1744), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1743), .Q(
DMP_SFG[18]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[26]), .QN(n887) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1721), .Q(
DMP_SFG[0]), .QN(n878) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1707), .Q(
Shift_reg_FLAGS_7[3]), .QN(n886) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1742), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1709),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1708), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1708),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1707), .Q(
intDX_EWSW[0]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1143), .Q(
DMP_EXP_EWSW[25]), .QN(n924) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1729), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1732), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1140), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1729), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1731), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1729), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1731), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1728), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[23]), .QN(n925) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1732), .Q(
DmP_EXP_EWSW[24]), .QN(n885) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1717), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1717), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1717), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1717), .Q(
Data_array_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1735), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1735), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1736), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1736), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1736), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1736), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1736), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1736), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1736), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1736), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1737), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1737), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1735), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1735), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1735), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1735), .Q(
final_result_ieee[13]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n1740), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1679) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1676) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1653) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1644) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1690) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1621) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1707), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1650) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1734), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1634) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1745), .Q(
DMP_SFG[6]), .QN(n1615) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[27]), .QN(n1674) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[24]), .QN(n1616) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1714),
.Q(intDY_EWSW[28]), .QN(n1671) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1712), .Q(
intDY_EWSW[7]), .QN(n1649) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[26]), .QN(n1692) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[19]), .QN(n1628) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1712),
.Q(intDY_EWSW[10]), .QN(n1635) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[0]), .QN(n1624) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1712), .Q(
intDY_EWSW[9]), .QN(n1660) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[2]), .QN(n1664) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[16]), .QN(n1668) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[4]), .QN(n1665) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1711), .Q(
intDY_EWSW[5]), .QN(n1623) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1714), .Q(
shift_value_SHT2_EWR[3]), .QN(n1633) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1710),
.Q(intDX_EWSW[28]), .QN(n1639) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1638) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1642) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1651) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1737), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1652) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[21]), .QN(n1701) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[17]), .QN(n1702) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1684) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1722), .Q(
DMP_SFG[3]), .QN(n1681) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1720), .Q(
DMP_SFG[2]), .QN(n1682) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1739), .Q(
LZD_output_NRM2_EW[3]), .QN(n1645) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1738), .Q(
LZD_output_NRM2_EW[1]), .QN(n1646) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1739), .Q(
LZD_output_NRM2_EW[4]), .QN(n1654) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1739), .Q(
LZD_output_NRM2_EW[2]), .QN(n1647) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[10]), .QN(n1693) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[16]), .QN(n1706) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[20]), .QN(n1705) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[25]), .QN(n1688) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1144), .Q(
DMP_EXP_EWSW[26]), .QN(n1631) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1716), .Q(
Data_array_SWR[13]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1141), .Q(
DMP_EXP_EWSW[23]) );
ADDFX1TS DP_OP_15J58_123_4652_U8 ( .A(n1646), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J58_123_4652_n8), .CO(DP_OP_15J58_123_4652_n7), .S(
exp_rslt_NRM2_EW1[1]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1738), .Q(
LZD_output_NRM2_EW[0]), .QN(n877) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1745), .Q(
DMP_SFG[4]), .QN(n1680) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1707), .Q(
n1748), .QN(n1750) );
CMPR32X2TS DP_OP_15J58_123_4652_U7 ( .A(n1647), .B(DMP_exp_NRM2_EW[2]), .C(
DP_OP_15J58_123_4652_n7), .CO(DP_OP_15J58_123_4652_n6), .S(
exp_rslt_NRM2_EW1[2]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1707), .Q(
Shift_reg_FLAGS_7[1]), .QN(n874) );
CMPR32X2TS DP_OP_15J58_123_4652_U6 ( .A(n1645), .B(DMP_exp_NRM2_EW[3]), .C(
DP_OP_15J58_123_4652_n6), .CO(DP_OP_15J58_123_4652_n5), .S(
exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J58_123_4652_U5 ( .A(n1654), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J58_123_4652_n5), .CO(DP_OP_15J58_123_4652_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1711), .Q(
left_right_SHT2), .QN(n875) );
OAI221X1TS U897 ( .A0(left_right_SHT2), .A1(n1399), .B0(n910), .B1(n1401),
.C0(n1138), .Y(n1389) );
OAI221X1TS U898 ( .A0(n912), .A1(n1396), .B0(n1606), .B1(n1397), .C0(n1390),
.Y(n1590) );
OAI221X1TS U899 ( .A0(n912), .A1(n1393), .B0(n910), .B1(n1394), .C0(n1135),
.Y(n1391) );
BUFX3TS U900 ( .A(n1320), .Y(n1291) );
AOI222X4TS U901 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n909), .B0(n918), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1373), .C1(DmP_mant_SHT1_SW[21]), .Y(n1331) );
AND2X2TS U902 ( .A(beg_OP), .B(n1503), .Y(n1508) );
CLKINVX6TS U903 ( .A(n888), .Y(n873) );
NAND2X2TS U904 ( .A(n1000), .B(n999), .Y(n1001) );
NAND2X1TS U905 ( .A(n1676), .B(n1067), .Y(n1093) );
NAND2X1TS U906 ( .A(n986), .B(n985), .Y(n1000) );
INVX2TS U907 ( .A(n1565), .Y(n1244) );
BUFX3TS U908 ( .A(Shift_reg_FLAGS_7_6), .Y(n1565) );
NAND2X1TS U909 ( .A(n1653), .B(n1062), .Y(n1066) );
NOR2X1TS U910 ( .A(n1430), .B(n1434), .Y(n1052) );
OAI211X1TS U911 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1006), .B0(n1484), .C0(
n1638), .Y(n1007) );
OAI21XLTS U912 ( .A0(intDX_EWSW[3]), .A1(n1658), .B0(intDX_EWSW[2]), .Y(n955) );
OAI211XLTS U913 ( .A0(n1658), .A1(intDX_EWSW[3]), .B0(n954), .C0(n953), .Y(
n957) );
OAI21XLTS U914 ( .A0(intDX_EWSW[23]), .A1(n1672), .B0(intDX_EWSW[22]), .Y(
n976) );
OAI21XLTS U915 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1011), .B0(n1010), .Y(n1012) );
AOI31XLTS U916 ( .A0(n1013), .A1(Raw_mant_NRM_SWR[16]), .A2(n1655), .B0(
n1012), .Y(n1014) );
OR2X1TS U917 ( .A(n1606), .B(n1099), .Y(n882) );
CLKINVX3TS U918 ( .A(n1535), .Y(n1358) );
OAI21XLTS U919 ( .A0(n1579), .A1(DMP_SFG[1]), .B0(n1190), .Y(intadd_65_B_0_)
);
INVX2TS U920 ( .A(n1090), .Y(n1070) );
INVX2TS U921 ( .A(n1495), .Y(n1494) );
CLKINVX3TS U922 ( .A(n1316), .Y(n1564) );
CLKINVX3TS U923 ( .A(n1320), .Y(n1566) );
OAI21XLTS U924 ( .A0(n1525), .A1(n915), .B0(n1037), .Y(n787) );
OAI211XLTS U925 ( .A0(n1279), .A1(n914), .B0(n1278), .C0(n1277), .Y(n772) );
OAI21XLTS U926 ( .A0(n1385), .A1(n907), .B0(n1384), .Y(n789) );
OAI21XLTS U927 ( .A0(n1241), .A1(n1231), .B0(n1230), .Y(n467) );
OAI21XLTS U928 ( .A0(n1594), .A1(n1414), .B0(n1201), .Y(n480) );
OAI211XLTS U929 ( .A0(n1355), .A1(n914), .B0(n1354), .C0(n1353), .Y(n786) );
OAI21XLTS U930 ( .A0(n1643), .A1(n1266), .B0(n1258), .Y(n588) );
OAI21XLTS U931 ( .A0(n1627), .A1(n1566), .B0(n1290), .Y(n724) );
OAI21X1TS U932 ( .A0(n1521), .A1(n906), .B0(n1372), .Y(n792) );
OAI21X1TS U933 ( .A0(n1620), .A1(n1528), .B0(n1523), .Y(n1524) );
INVX4TS U934 ( .A(n1080), .Y(n1377) );
OAI21X1TS U935 ( .A0(n1684), .A1(n1528), .B0(n1527), .Y(n1529) );
AOI211X1TS U936 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n905), .B0(n1081), .C0(
n1330), .Y(n1519) );
AND2X2TS U937 ( .A(n1035), .B(n1535), .Y(n876) );
NAND4X1TS U938 ( .A(n1132), .B(n1131), .C(n1212), .D(n1486), .Y(n1133) );
AO22X1TS U939 ( .A0(final_result_ieee[10]), .A1(n1589), .B0(n1592), .B1(
n1587), .Y(n511) );
AO22X1TS U940 ( .A0(n1592), .A1(n1588), .B0(final_result_ieee[9]), .B1(n1589), .Y(n509) );
AO22X1TS U941 ( .A0(n1592), .A1(n1389), .B0(final_result_ieee[13]), .B1(
n1589), .Y(n506) );
AO22X1TS U942 ( .A0(n1592), .A1(n1391), .B0(final_result_ieee[11]), .B1(
n1589), .Y(n510) );
AO22X1TS U943 ( .A0(n1494), .A1(n1493), .B0(final_result_ieee[30]), .B1(
n1501), .Y(n754) );
AO22X1TS U944 ( .A0(n1592), .A1(n1590), .B0(final_result_ieee[12]), .B1(
n1589), .Y(n508) );
AO22X1TS U945 ( .A0(n1592), .A1(n1591), .B0(final_result_ieee[8]), .B1(n1600), .Y(n507) );
AND2X2TS U946 ( .A(n1493), .B(n1092), .Y(n927) );
AND2X2TS U947 ( .A(n1679), .B(n1094), .Y(n1095) );
INVX4TS U948 ( .A(n1550), .Y(n1238) );
OAI21X1TS U949 ( .A0(n1024), .A1(n1023), .B0(n1022), .Y(n1026) );
NOR2X1TS U950 ( .A(n987), .B(intDY_EWSW[24]), .Y(n988) );
INVX4TS U951 ( .A(n1584), .Y(n1468) );
AOI211X1TS U952 ( .A0(intDY_EWSW[28]), .A1(n1639), .B0(n995), .C0(n993), .Y(
n997) );
NOR2X1TS U953 ( .A(n932), .B(intDY_EWSW[10]), .Y(n933) );
NOR2X1TS U954 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1387) );
OAI21X1TS U955 ( .A0(n1532), .A1(n907), .B0(n1380), .Y(n779) );
OAI21X1TS U956 ( .A0(n1385), .A1(n914), .B0(n1041), .Y(n791) );
OAI21X1TS U957 ( .A0(n1634), .A1(n1080), .B0(n1333), .Y(n793) );
OAI211X1TS U958 ( .A0(n1367), .A1(n915), .B0(n1366), .C0(n1365), .Y(n788) );
OAI211X1TS U959 ( .A0(n1337), .A1(n914), .B0(n1283), .C0(n1282), .Y(n775) );
OAI211X1TS U960 ( .A0(n1350), .A1(n914), .B0(n1349), .C0(n1348), .Y(n780) );
OAI211X1TS U961 ( .A0(n1341), .A1(n907), .B0(n1340), .C0(n1339), .Y(n774) );
OAI211X1TS U962 ( .A0(n1378), .A1(n907), .B0(n1344), .C0(n1343), .Y(n777) );
OAI211X1TS U963 ( .A0(n1362), .A1(n915), .B0(n1361), .C0(n1360), .Y(n782) );
OAI211X1TS U964 ( .A0(n1359), .A1(n915), .B0(n1357), .C0(n1356), .Y(n784) );
OAI21X1TS U965 ( .A0(n1677), .A1(n1528), .B0(n1019), .Y(n1020) );
OAI21X1TS U966 ( .A0(n1690), .A1(n888), .B0(n1368), .Y(n1369) );
AOI222X1TS U967 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n909), .B0(n918), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1373), .C1(DmP_mant_SHT1_SW[20]), .Y(n1370) );
AOI222X1TS U968 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n909), .B0(n918), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1522), .C1(DmP_mant_SHT1_SW[18]), .Y(n1364) );
AOI222X1TS U969 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n909), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1373), .C0(n918), .C1(DmP_mant_SHT1_SW[13]), .Y(n1355) );
OAI211X1TS U970 ( .A0(n1535), .A1(n879), .B0(n1483), .C0(n1217), .Y(n767) );
OAI21X1TS U971 ( .A0(n1640), .A1(n888), .B0(n1374), .Y(n1375) );
OAI21X1TS U972 ( .A0(n1648), .A1(n1289), .B0(n1285), .Y(n747) );
OAI21X1TS U973 ( .A0(n1623), .A1(n1289), .B0(n1287), .Y(n748) );
OAI21X1TS U974 ( .A0(n1665), .A1(n1289), .B0(n1288), .Y(n749) );
OAI21X1TS U975 ( .A0(n1658), .A1(n1289), .B0(n1057), .Y(n750) );
OAI21X1TS U976 ( .A0(n1661), .A1(n1308), .B0(n1002), .Y(n740) );
OAI21X1TS U977 ( .A0(n1663), .A1(n1308), .B0(n1300), .Y(n745) );
OAI21X1TS U978 ( .A0(n1660), .A1(n1308), .B0(n1307), .Y(n744) );
OAI21X1TS U979 ( .A0(n1626), .A1(n1315), .B0(n1311), .Y(n731) );
OAI21X1TS U980 ( .A0(n1675), .A1(n1315), .B0(n1292), .Y(n735) );
OAI21X1TS U981 ( .A0(n1662), .A1(n1315), .B0(n1314), .Y(n732) );
OAI21X1TS U982 ( .A0(n1664), .A1(n1289), .B0(n1286), .Y(n751) );
OAI21X1TS U983 ( .A0(n1643), .A1(n1308), .B0(n1299), .Y(n742) );
OAI21X1TS U984 ( .A0(n1624), .A1(n1315), .B0(n1310), .Y(n753) );
OAI21X1TS U985 ( .A0(n1635), .A1(n1308), .B0(n1303), .Y(n743) );
OAI21X1TS U986 ( .A0(n1669), .A1(n1315), .B0(n1312), .Y(n733) );
OAI21X1TS U987 ( .A0(n1669), .A1(n1564), .B0(n1317), .Y(n570) );
OAI21X1TS U988 ( .A0(n1628), .A1(n1564), .B0(n1321), .Y(n572) );
OAI21X1TS U989 ( .A0(n1671), .A1(n1566), .B0(n1274), .Y(n725) );
OAI21X1TS U990 ( .A0(n1626), .A1(n1564), .B0(n1318), .Y(n566) );
OAI21X1TS U991 ( .A0(n1752), .A1(n1566), .B0(n1284), .Y(n752) );
OAI21X1TS U992 ( .A0(n1658), .A1(n1262), .B0(n1252), .Y(n604) );
OAI21X1TS U993 ( .A0(n1623), .A1(n1262), .B0(n1248), .Y(n600) );
OAI21X1TS U994 ( .A0(n1662), .A1(n1564), .B0(n1319), .Y(n568) );
OAI21X1TS U995 ( .A0(n1752), .A1(n1262), .B0(n1251), .Y(n608) );
OAI21X1TS U996 ( .A0(n1666), .A1(n1266), .B0(n1259), .Y(n586) );
OAI21X1TS U997 ( .A0(n1667), .A1(n1266), .B0(n1257), .Y(n582) );
OAI21X1TS U998 ( .A0(n1660), .A1(n1262), .B0(n1261), .Y(n592) );
OAI211X1TS U999 ( .A0(n1078), .A1(n1751), .B0(n1567), .C0(n1077), .Y(n758)
);
OAI21X1TS U1000 ( .A0(n1649), .A1(n1262), .B0(n1254), .Y(n596) );
OAI21X1TS U1001 ( .A0(n1675), .A1(n1266), .B0(n1255), .Y(n574) );
OAI211X1TS U1002 ( .A0(n1195), .A1(n1600), .B0(n1567), .C0(n1194), .Y(n760)
);
OAI21X1TS U1003 ( .A0(n1635), .A1(n1266), .B0(n1256), .Y(n590) );
OAI211X1TS U1004 ( .A0(n1076), .A1(n1600), .B0(n1567), .C0(n1075), .Y(n759)
);
OAI211X1TS U1005 ( .A0(n1070), .A1(n1751), .B0(n1567), .C0(n1069), .Y(n756)
);
OAI21X1TS U1006 ( .A0(n1271), .A1(n1549), .B0(n1268), .Y(n1269) );
OAI211X1TS U1007 ( .A0(n1193), .A1(n1600), .B0(n1567), .C0(n1192), .Y(n761)
);
OAI211X1TS U1008 ( .A0(n1074), .A1(n1600), .B0(n1567), .C0(n1073), .Y(n757)
);
OAI211X1TS U1009 ( .A0(n1072), .A1(n1751), .B0(n1567), .C0(n1071), .Y(n755)
);
INVX1TS U1010 ( .A(n1293), .Y(n1268) );
BUFX4TS U1011 ( .A(n1246), .Y(n1320) );
OAI21X1TS U1012 ( .A0(n1593), .A1(n1414), .B0(n1198), .Y(n479) );
NAND2BX1TS U1013 ( .AN(n1091), .B(n1065), .Y(n1068) );
NAND3X1TS U1014 ( .A(n1413), .B(n1412), .C(n1411), .Y(n1597) );
INVX1TS U1015 ( .A(n1091), .Y(n1072) );
OAI21X1TS U1016 ( .A0(n1602), .A1(n1414), .B0(n1227), .Y(n464) );
NAND3X1TS U1017 ( .A(n1406), .B(n1405), .C(n1404), .Y(n1595) );
AOI222X1TS U1018 ( .A0(n1115), .A1(n910), .B0(n899), .B1(Data_array_SWR[5]),
.C0(n1114), .C1(n1409), .Y(n1613) );
OAI221X1TS U1019 ( .A0(left_right_SHT2), .A1(n1397), .B0(n910), .B1(n1396),
.C0(n1395), .Y(n1588) );
OAI221X1TS U1020 ( .A0(n912), .A1(n1394), .B0(n910), .B1(n1393), .C0(n1392),
.Y(n1587) );
NAND2BX1TS U1021 ( .AN(n911), .B(n1402), .Y(n1406) );
NAND3X1TS U1022 ( .A(n1748), .B(Shift_amount_SHT1_EWR[4]), .C(n905), .Y(
n1217) );
OAI21X1TS U1023 ( .A0(n1219), .A1(n1241), .B0(n1218), .Y(n465) );
NOR2X1TS U1024 ( .A(n1064), .B(n1090), .Y(n1065) );
OAI21X1TS U1025 ( .A0(n1207), .A1(n1414), .B0(n1206), .Y(n463) );
OAI21X1TS U1026 ( .A0(n968), .A1(n967), .B0(n966), .Y(n982) );
NAND2BX1TS U1027 ( .AN(n1403), .B(n1409), .Y(n1405) );
BUFX3TS U1028 ( .A(n1081), .Y(n1373) );
INVX2TS U1029 ( .A(n882), .Y(n901) );
AO22XLTS U1030 ( .A0(n1511), .A1(add_subt), .B0(n1509), .B1(intAS), .Y(n830)
);
NAND2BX1TS U1031 ( .AN(n1410), .B(n1409), .Y(n1412) );
NAND4BX1TS U1032 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1063), .C(n1078), .D(n1076), .Y(n1064) );
AOI222X1TS U1033 ( .A0(n1117), .A1(n910), .B0(n899), .B1(Data_array_SWR[4]),
.C0(n1116), .C1(n1409), .Y(n1611) );
AOI2BB2X1TS U1034 ( .B0(n998), .B1(n997), .A0N(n996), .A1N(n995), .Y(n999)
);
AOI222X1TS U1035 ( .A0(Data_array_SWR[14]), .A1(n1086), .B0(
Data_array_SWR[22]), .B1(n894), .C0(Data_array_SWR[18]), .C1(n896),
.Y(n1401) );
CLKBUFX3TS U1036 ( .A(n1086), .Y(n897) );
OR2X2TS U1037 ( .A(n911), .B(n1099), .Y(n884) );
NOR2BX4TS U1038 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n903), .Y(n1081) );
INVX3TS U1039 ( .A(n910), .Y(n912) );
INVX3TS U1040 ( .A(n1558), .Y(n1612) );
OAI211X1TS U1041 ( .A0(intDX_EWSW[8]), .A1(n1663), .B0(n947), .C0(n946), .Y(
n948) );
INVX2TS U1042 ( .A(n1558), .Y(n1241) );
INVX2TS U1043 ( .A(n880), .Y(n917) );
NOR2X1TS U1044 ( .A(n1191), .B(exp_rslt_NRM2_EW1[1]), .Y(n1063) );
INVX2TS U1045 ( .A(n881), .Y(n896) );
NOR2X4TS U1046 ( .A(shift_value_SHT2_EWR[4]), .B(n1123), .Y(n1086) );
OAI211X2TS U1047 ( .A0(intDX_EWSW[12]), .A1(n1666), .B0(n943), .C0(n934),
.Y(n945) );
INVX1TS U1048 ( .A(n1126), .Y(n1128) );
NAND3X1TS U1049 ( .A(n1670), .B(n989), .C(intDX_EWSW[26]), .Y(n991) );
OAI211X2TS U1050 ( .A0(intDX_EWSW[20]), .A1(n1669), .B0(n980), .C0(n964),
.Y(n975) );
INVX3TS U1051 ( .A(n1557), .Y(n1414) );
OR2X2TS U1052 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n880) );
INVX3TS U1053 ( .A(n1747), .Y(n1586) );
NAND3X1TS U1054 ( .A(shift_value_SHT2_EWR[2]), .B(n879), .C(
shift_value_SHT2_EWR[3]), .Y(n883) );
NAND2BX1TS U1055 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n947) );
NAND3X1TS U1056 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1622), .C(
n1650), .Y(n1496) );
NAND2BX1TS U1057 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n989) );
NAND2BX1TS U1058 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n990) );
NAND2BX1TS U1059 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n983) );
NAND2BX1TS U1060 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n972) );
NAND2BX1TS U1061 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n964) );
OAI21X1TS U1062 ( .A0(intDX_EWSW[15]), .A1(n1625), .B0(intDX_EWSW[14]), .Y(
n939) );
NAND2BX1TS U1063 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n934) );
NAND2X6TS U1064 ( .A(n1029), .B(n1620), .Y(n1015) );
NOR2X6TS U1065 ( .A(Raw_mant_NRM_SWR[13]), .B(n1130), .Y(n1029) );
OAI21X1TS U1066 ( .A0(n1638), .A1(n1528), .B0(n1038), .Y(n1039) );
OAI21X2TS U1067 ( .A0(n1431), .A1(n1434), .B0(n1435), .Y(n1051) );
BUFX16TS U1068 ( .A(n1388), .Y(n1053) );
AND4X1TS U1069 ( .A(n1091), .B(n1090), .C(exp_rslt_NRM2_EW1[4]), .D(n1089),
.Y(n1092) );
NAND3XLTS U1070 ( .A(n1663), .B(n947), .C(intDX_EWSW[8]), .Y(n935) );
NAND2BXLTS U1071 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n936) );
NAND2BXLTS U1072 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n953) );
INVX2TS U1073 ( .A(n944), .Y(n968) );
NOR2BX1TS U1074 ( .AN(n963), .B(n962), .Y(n967) );
NOR2BX1TS U1075 ( .AN(n949), .B(n948), .Y(n963) );
OAI32X1TS U1076 ( .A0(n961), .A1(n960), .A2(n959), .B0(n958), .B1(n960), .Y(
n962) );
NOR2BX1TS U1077 ( .AN(n965), .B(n970), .Y(n966) );
AOI211X2TS U1078 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1017), .B0(n1491), .C0(
n1016), .Y(n1018) );
NOR2X1TS U1079 ( .A(n1024), .B(Raw_mant_NRM_SWR[19]), .Y(n1489) );
CLKAND2X2TS U1080 ( .A(n1026), .B(n1025), .Y(n1033) );
INVX4TS U1081 ( .A(n1528), .Y(n908) );
NAND2X1TS U1082 ( .A(Raw_mant_NRM_SWR[12]), .B(n1029), .Y(n1131) );
NAND3X1TS U1083 ( .A(n1129), .B(n1485), .C(Raw_mant_NRM_SWR[1]), .Y(n1212)
);
AO21XLTS U1084 ( .A0(n1620), .A1(n1684), .B0(n1130), .Y(n1486) );
AOI222X1TS U1085 ( .A0(Data_array_SWR[23]), .A1(n894), .B0(
Data_array_SWR[19]), .B1(n896), .C0(Data_array_SWR[15]), .C1(n1086),
.Y(n1397) );
NAND2X1TS U1086 ( .A(n1441), .B(n1443), .Y(n1430) );
XOR2X1TS U1087 ( .A(n1053), .B(DmP_mant_SFG_SWR[19]), .Y(n1050) );
INVX2TS U1088 ( .A(n910), .Y(n911) );
AOI222X1TS U1089 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n909), .B0(n917), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1522), .C1(DmP_mant_SHT1_SW[4]), .Y(n1341)
);
AOI222X1TS U1090 ( .A0(n909), .A1(Raw_mant_NRM_SWR[21]), .B0(n1522), .B1(
DmP_mant_SHT1_SW[3]), .C0(n918), .C1(DmP_mant_SHT1_SW[2]), .Y(n1337)
);
AOI222X1TS U1091 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n908), .B0(n917), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1522), .C1(DmP_mant_SHT1_SW[16]), .Y(n1367) );
BUFX3TS U1092 ( .A(n1053), .Y(n1480) );
NAND2X1TS U1093 ( .A(n1644), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J58_123_4652_n8) );
NOR2X4TS U1094 ( .A(n928), .B(n1495), .Y(n1592) );
AOI222X1TS U1095 ( .A0(n1199), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n901), .C0(n1222), .C1(n1124), .Y(n1229) );
INVX2TS U1096 ( .A(n1431), .Y(n1432) );
INVX2TS U1097 ( .A(n1430), .Y(n1433) );
INVX2TS U1098 ( .A(n1434), .Y(n1436) );
NOR2X1TS U1099 ( .A(n1447), .B(n1449), .Y(n1441) );
INVX2TS U1100 ( .A(n1293), .Y(n1266) );
INVX2TS U1101 ( .A(n1293), .Y(n1262) );
NAND4XLTS U1102 ( .A(n1174), .B(n1173), .C(n1172), .D(n1171), .Y(n1184) );
NAND4XLTS U1103 ( .A(n1158), .B(n1157), .C(n1156), .D(n1155), .Y(n1186) );
NAND4XLTS U1104 ( .A(n1182), .B(n1181), .C(n1180), .D(n1179), .Y(n1183) );
INVX2TS U1105 ( .A(n1291), .Y(n1308) );
BUFX3TS U1106 ( .A(n1293), .Y(n1306) );
INVX2TS U1107 ( .A(n1291), .Y(n1315) );
AO22XLTS U1108 ( .A0(n1506), .A1(Data_X[10]), .B0(n1505), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1109 ( .A0(n1507), .A1(Data_X[30]), .B0(n1509), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1110 ( .A0(n1506), .A1(Data_X[22]), .B0(n1517), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1111 ( .A0(n1508), .A1(Data_X[14]), .B0(n1505), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1112 ( .A0(n1507), .A1(Data_X[20]), .B0(n1517), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1113 ( .A0(n1506), .A1(Data_X[12]), .B0(n1505), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1114 ( .A0(n1507), .A1(Data_X[31]), .B0(n1509), .B1(intDX_EWSW[31]), .Y(n831) );
AO22XLTS U1115 ( .A0(n1506), .A1(Data_X[19]), .B0(n1517), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1116 ( .A0(n1507), .A1(Data_X[29]), .B0(n1509), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1117 ( .A0(n1518), .A1(Data_X[18]), .B0(n1517), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1118 ( .A0(n1507), .A1(Data_X[9]), .B0(n1505), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1119 ( .A0(n1506), .A1(Data_X[11]), .B0(n1505), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1120 ( .A0(n1507), .A1(Data_X[8]), .B0(n1505), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1121 ( .A0(n1506), .A1(Data_X[17]), .B0(n1517), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1122 ( .A0(n1506), .A1(Data_X[15]), .B0(n1517), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1123 ( .A0(n1506), .A1(Data_X[13]), .B0(n1505), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1124 ( .A0(n1507), .A1(Data_X[21]), .B0(n1517), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1125 ( .A0(n1510), .A1(intDY_EWSW[6]), .B0(n1513), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1126 ( .A0(n1514), .A1(Data_X[5]), .B0(n1505), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1127 ( .A0(n1514), .A1(Data_X[6]), .B0(n1505), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1128 ( .A0(n1507), .A1(Data_X[7]), .B0(n1505), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1129 ( .A0(n1506), .A1(Data_X[16]), .B0(n1517), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1130 ( .A0(n1510), .A1(intDY_EWSW[3]), .B0(n1513), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1131 ( .A0(n1510), .A1(intDY_EWSW[8]), .B0(n1514), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1132 ( .A0(n1512), .A1(intDY_EWSW[11]), .B0(n1514), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1133 ( .A0(n1512), .A1(intDY_EWSW[15]), .B0(n1515), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1134 ( .A0(n1512), .A1(intDY_EWSW[17]), .B0(n1515), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1135 ( .A0(n1512), .A1(intDY_EWSW[18]), .B0(n1515), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1136 ( .A0(n1512), .A1(intDY_EWSW[12]), .B0(n1513), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1137 ( .A0(n1512), .A1(intDY_EWSW[13]), .B0(n1515), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1138 ( .A0(n1512), .A1(intDY_EWSW[14]), .B0(n1515), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1139 ( .A0(n1512), .A1(intDY_EWSW[20]), .B0(n1513), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1140 ( .A0(n1516), .A1(intDY_EWSW[29]), .B0(n1515), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1141 ( .A0(n1516), .A1(intDY_EWSW[30]), .B0(n1515), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1142 ( .A0(n1516), .A1(intDY_EWSW[21]), .B0(n1513), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1143 ( .A0(n1516), .A1(intDY_EWSW[22]), .B0(n1514), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1144 ( .A0(n1506), .A1(Data_X[28]), .B0(n1509), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1145 ( .A0(n1510), .A1(intDY_EWSW[5]), .B0(n1513), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1146 ( .A0(n1510), .A1(intDY_EWSW[4]), .B0(n1513), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1147 ( .A0(n1512), .A1(intDY_EWSW[16]), .B0(n1515), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1148 ( .A0(n1510), .A1(intDY_EWSW[2]), .B0(n1513), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1149 ( .A0(n1510), .A1(intDY_EWSW[9]), .B0(n1514), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1150 ( .A0(n1510), .A1(intDY_EWSW[0]), .B0(n1514), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1151 ( .A0(n1510), .A1(intDY_EWSW[1]), .B0(n1513), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1152 ( .A0(n1510), .A1(intDY_EWSW[10]), .B0(n1514), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1153 ( .A0(n1512), .A1(intDY_EWSW[19]), .B0(n1515), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1154 ( .A0(n1509), .A1(intDY_EWSW[7]), .B0(n1513), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1155 ( .A0(n1516), .A1(intDY_EWSW[28]), .B0(n1511), .B1(Data_Y[28]), .Y(n800) );
OAI2BB2XLTS U1156 ( .B0(n938), .B1(n945), .A0N(n937), .A1N(n946), .Y(n941)
);
AOI222X1TS U1157 ( .A0(intDY_EWSW[4]), .A1(n1618), .B0(n957), .B1(n956),
.C0(intDY_EWSW[5]), .C1(n1632), .Y(n959) );
AOI2BB2XLTS U1158 ( .B0(intDX_EWSW[3]), .B1(n1658), .A0N(intDY_EWSW[2]),
.A1N(n955), .Y(n956) );
INVX2TS U1159 ( .A(n945), .Y(n949) );
AOI2BB1XLTS U1160 ( .A0N(n1008), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n1011) );
CLKAND2X2TS U1161 ( .A(n1107), .B(shift_value_SHT2_EWR[4]), .Y(n1118) );
NAND2X1TS U1162 ( .A(n1107), .B(n879), .Y(n1099) );
INVX2TS U1163 ( .A(n1107), .Y(n1122) );
NAND2X1TS U1164 ( .A(n982), .B(n981), .Y(n986) );
INVX2TS U1165 ( .A(n984), .Y(n985) );
AOI2BB2XLTS U1166 ( .B0(intDX_EWSW[7]), .B1(n1649), .A0N(n1649), .A1N(
intDX_EWSW[7]), .Y(n1155) );
NAND4XLTS U1167 ( .A(n1166), .B(n1165), .C(n1164), .D(n1163), .Y(n1185) );
AO22XLTS U1168 ( .A0(n1081), .A1(DmP_mant_SHT1_SW[1]), .B0(n916), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1082) );
OAI22X1TS U1169 ( .A0(n1044), .A1(n1043), .B0(n1061), .B1(DMP_SFG[6]), .Y(
n1045) );
OAI211XLTS U1170 ( .A0(n1489), .A1(n1488), .B0(n1487), .C0(n1486), .Y(n1490)
);
OAI21XLTS U1171 ( .A0(n1621), .A1(n1213), .B0(n1212), .Y(n1214) );
NOR2XLTS U1172 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1211)
);
INVX2TS U1173 ( .A(n1498), .Y(n1497) );
INVX2TS U1174 ( .A(n1518), .Y(n1516) );
AO21XLTS U1175 ( .A0(n1579), .A1(DMP_SFG[1]), .B0(n1578), .Y(n1190) );
AOI222X1TS U1176 ( .A0(n1117), .A1(n912), .B0(Data_array_SWR[4]), .B1(n901),
.C0(n1116), .C1(n1124), .Y(n1231) );
AOI222X1TS U1177 ( .A0(n1115), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n901), .C0(n1114), .C1(n1124), .Y(n1237) );
AO22XLTS U1178 ( .A0(n898), .A1(Data_array_SWR[8]), .B0(n1199), .B1(n1606),
.Y(n1200) );
AO22XLTS U1179 ( .A0(n898), .A1(Data_array_SWR[9]), .B0(n1196), .B1(n1606),
.Y(n1197) );
INVX2TS U1180 ( .A(n1558), .Y(n1569) );
INVX2TS U1181 ( .A(n891), .Y(n892) );
AO21XLTS U1182 ( .A0(LZD_output_NRM2_EW[0]), .A1(n874), .B0(n873), .Y(n515)
);
MX2X1TS U1183 ( .A(n1597), .B(DmP_mant_SFG_SWR[6]), .S0(n1414), .Y(n482) );
AO22XLTS U1184 ( .A0(n1561), .A1(DmP_EXP_EWSW[0]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U1185 ( .A0(n920), .A1(DmP_EXP_EWSW[13]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U1186 ( .A0(n920), .A1(DmP_EXP_EWSW[14]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1187 ( .A0(n920), .A1(DmP_EXP_EWSW[11]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[11]), .Y(n587) );
AO22XLTS U1188 ( .A0(n920), .A1(DmP_EXP_EWSW[9]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[9]), .Y(n591) );
AO22XLTS U1189 ( .A0(n1617), .A1(DmP_EXP_EWSW[6]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U1190 ( .A0(n920), .A1(DmP_EXP_EWSW[15]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1191 ( .A0(n920), .A1(DmP_EXP_EWSW[8]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U1192 ( .A0(n1571), .A1(DmP_EXP_EWSW[22]), .B0(n1568), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1193 ( .A0(n920), .A1(DmP_EXP_EWSW[12]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U1194 ( .A0(n920), .A1(DmP_EXP_EWSW[10]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1195 ( .A0(n920), .A1(DmP_EXP_EWSW[7]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AOI2BB2XLTS U1196 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1377), .A0N(n1362),
.A1N(n907), .Y(n1348) );
AO22XLTS U1197 ( .A0(n1518), .A1(Data_X[0]), .B0(n1504), .B1(intDX_EWSW[0]),
.Y(n862) );
AO22XLTS U1198 ( .A0(n1518), .A1(Data_X[2]), .B0(n1504), .B1(intDX_EWSW[2]),
.Y(n860) );
MX2X1TS U1199 ( .A(n1591), .B(DmP_mant_SFG_SWR[10]), .S0(n1414), .Y(n478) );
MX2X1TS U1200 ( .A(n1588), .B(DmP_mant_SFG_SWR[11]), .S0(n1414), .Y(n477) );
MX2X1TS U1201 ( .A(n1587), .B(DmP_mant_SFG_SWR[12]), .S0(n1414), .Y(n476) );
MX2X1TS U1202 ( .A(n1391), .B(DmP_mant_SFG_SWR[13]), .S0(n1612), .Y(n475) );
MX2X1TS U1203 ( .A(n1590), .B(DmP_mant_SFG_SWR[14]), .S0(n1414), .Y(n474) );
MX2X1TS U1204 ( .A(n1389), .B(DmP_mant_SFG_SWR[15]), .S0(n1612), .Y(n473) );
AO22XLTS U1205 ( .A0(n1518), .A1(Data_Y[31]), .B0(n1517), .B1(intDY_EWSW[31]), .Y(n797) );
AO22XLTS U1206 ( .A0(n1502), .A1(busy), .B0(n1500), .B1(Shift_reg_FLAGS_7[3]), .Y(n866) );
AO22XLTS U1207 ( .A0(n1558), .A1(DMP_SHT2_EWSW[0]), .B0(n1569), .B1(
DMP_SFG[0]), .Y(n717) );
OAI21XLTS U1208 ( .A0(n1241), .A1(n1229), .B0(n1228), .Y(n471) );
MX2X1TS U1209 ( .A(n1595), .B(DmP_mant_SFG_SWR[7]), .S0(n1414), .Y(n481) );
MX2X1TS U1210 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1557), .Y(n663)
);
MX2X1TS U1211 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1557), .Y(n657)
);
MX2X1TS U1212 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1614), .Y(n693)
);
MX2X1TS U1213 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1614), .Y(n687)
);
MX2X1TS U1214 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1614), .Y(n681)
);
MX2X1TS U1215 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1557), .Y(n660)
);
MX2X1TS U1216 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1558), .Y(n654)
);
MX2X1TS U1217 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1218 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n904),
.Y(n636) );
MX2X1TS U1219 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1220 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n903),
.Y(n626) );
MX2X1TS U1221 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1550), .Y(n690)
);
MX2X1TS U1222 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1614), .Y(n684)
);
MX2X1TS U1223 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1558), .Y(n678)
);
MX2X1TS U1224 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1558), .Y(n651)
);
MX2X1TS U1225 ( .A(n1388), .B(OP_FLAG_SHT2), .S0(n1550), .Y(n549) );
AO22XLTS U1226 ( .A0(n1547), .A1(n1542), .B0(n1570), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
AO22XLTS U1227 ( .A0(n1561), .A1(DmP_EXP_EWSW[1]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AOI2BB2XLTS U1228 ( .B0(n1571), .B1(n1538), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1547), .Y(n766) );
AO22XLTS U1229 ( .A0(n1561), .A1(DmP_EXP_EWSW[5]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[5]), .Y(n599) );
AO22XLTS U1230 ( .A0(n1571), .A1(DmP_EXP_EWSW[19]), .B0(n1568), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
MX2X1TS U1231 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1557), .Y(n669)
);
AO22XLTS U1232 ( .A0(n1571), .A1(DmP_EXP_EWSW[18]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1233 ( .A0(n1561), .A1(DmP_EXP_EWSW[2]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1234 ( .A0(n1561), .A1(DmP_EXP_EWSW[4]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[4]), .Y(n601) );
AO22XLTS U1235 ( .A0(n1561), .A1(DmP_EXP_EWSW[3]), .B0(n1562), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U1236 ( .A0(n1571), .A1(DmP_EXP_EWSW[21]), .B0(n1568), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1237 ( .A0(n1571), .A1(DmP_EXP_EWSW[16]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1238 ( .A0(n1571), .A1(DmP_EXP_EWSW[17]), .B0(n1563), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1239 ( .A0(n1571), .A1(DmP_EXP_EWSW[20]), .B0(n1568), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
MX2X1TS U1240 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1558), .Y(n675)
);
MX2X1TS U1241 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1558), .Y(n696)
);
MX2X1TS U1242 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1550), .Y(n672)
);
MX2X1TS U1243 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1550), .Y(n666)
);
AO22XLTS U1244 ( .A0(n1550), .A1(DMP_SHT2_EWSW[1]), .B0(n1569), .B1(
DMP_SFG[1]), .Y(n714) );
OAI211XLTS U1245 ( .A0(n1341), .A1(n915), .B0(n1329), .C0(n1328), .Y(n776)
);
AO22XLTS U1246 ( .A0(n1507), .A1(Data_X[27]), .B0(n1509), .B1(intDX_EWSW[27]), .Y(n835) );
MX2X1TS U1247 ( .A(Raw_mant_NRM_SWR[10]), .B(n1478), .S0(n1482), .Y(n532) );
MX2X1TS U1248 ( .A(Raw_mant_NRM_SWR[12]), .B(n1475), .S0(n1482), .Y(n530) );
AO22XLTS U1249 ( .A0(n1518), .A1(Data_X[1]), .B0(n1504), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1250 ( .A0(n1507), .A1(Data_X[23]), .B0(n1517), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1251 ( .A0(n1518), .A1(Data_X[3]), .B0(n1504), .B1(intDX_EWSW[3]),
.Y(n859) );
MX2X1TS U1252 ( .A(DMP_SFG[5]), .B(DMP_SHT2_EWSW[5]), .S0(n1614), .Y(n702)
);
CLKMX2X2TS U1253 ( .A(Raw_mant_NRM_SWR[25]), .B(n1056), .S0(n1586), .Y(n517)
);
XNOR2X1TS U1254 ( .A(n1055), .B(n1054), .Y(n1056) );
MX2X1TS U1255 ( .A(Raw_mant_NRM_SWR[20]), .B(n1429), .S0(n1468), .Y(n522) );
MX2X1TS U1256 ( .A(Raw_mant_NRM_SWR[21]), .B(n1426), .S0(n1468), .Y(n521) );
AO21XLTS U1257 ( .A0(LZD_output_NRM2_EW[1]), .A1(n905), .B0(n1492), .Y(n513)
);
AOI2BB1XLTS U1258 ( .A0N(n903), .A1N(LZD_output_NRM2_EW[3]), .B0(n1537), .Y(
n516) );
AO22XLTS U1259 ( .A0(n1612), .A1(DMP_SFG[2]), .B0(n1550), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1260 ( .A0(n1612), .A1(DMP_SFG[3]), .B0(n1550), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
MX2X1TS U1261 ( .A(Raw_mant_NRM_SWR[13]), .B(n1469), .S0(n1468), .Y(n529) );
MX2X1TS U1262 ( .A(Raw_mant_NRM_SWR[11]), .B(n1472), .S0(n1482), .Y(n531) );
MX2X1TS U1263 ( .A(Raw_mant_NRM_SWR[17]), .B(n1454), .S0(n1468), .Y(n525) );
AO22XLTS U1264 ( .A0(n1509), .A1(intDX_EWSW[25]), .B0(n1514), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1265 ( .A0(n1509), .A1(intDX_EWSW[24]), .B0(n1515), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1266 ( .A0(n1516), .A1(intDY_EWSW[25]), .B0(n1511), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1267 ( .A0(n1516), .A1(intDY_EWSW[26]), .B0(n1511), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1268 ( .A0(n1516), .A1(intDY_EWSW[23]), .B0(n1511), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1269 ( .A0(n1518), .A1(Data_X[4]), .B0(n1504), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1270 ( .A0(n1509), .A1(intDX_EWSW[26]), .B0(n1514), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1271 ( .A0(n1516), .A1(intDY_EWSW[24]), .B0(n1511), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1272 ( .A0(n1516), .A1(intDY_EWSW[27]), .B0(n1508), .B1(Data_Y[27]), .Y(n801) );
MX2X1TS U1273 ( .A(Raw_mant_NRM_SWR[14]), .B(n1465), .S0(n1468), .Y(n528) );
MX2X1TS U1274 ( .A(DMP_SFG[4]), .B(DMP_SHT2_EWSW[4]), .S0(n1550), .Y(n705)
);
MX2X1TS U1275 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1557), .Y(n699)
);
AO21XLTS U1276 ( .A0(n1576), .A1(n878), .B0(n1579), .Y(n1577) );
OAI21XLTS U1277 ( .A0(n1498), .A1(n1058), .B0(n1496), .Y(n870) );
AOI2BB2XLTS U1278 ( .B0(beg_OP), .B1(n1622), .A0N(n1622), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1058) );
MX2X1TS U1279 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n903),
.Y(n646) );
MX2X1TS U1280 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1281 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n903),
.Y(n616) );
MX2X1TS U1282 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
AO22XLTS U1283 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1589), .B1(zero_flag), .Y(n552) );
MX2X1TS U1284 ( .A(Raw_mant_NRM_SWR[24]), .B(n1423), .S0(n1586), .Y(n518) );
MX2X1TS U1285 ( .A(Raw_mant_NRM_SWR[23]), .B(n1420), .S0(n1586), .Y(n519) );
MX2X1TS U1286 ( .A(Raw_mant_NRM_SWR[22]), .B(n1417), .S0(n1468), .Y(n520) );
MX2X1TS U1287 ( .A(Raw_mant_NRM_SWR[19]), .B(n1439), .S0(n1468), .Y(n523) );
MX2X1TS U1288 ( .A(Raw_mant_NRM_SWR[18]), .B(n1446), .S0(n1468), .Y(n524) );
MX2X1TS U1289 ( .A(Raw_mant_NRM_SWR[16]), .B(n1462), .S0(n1468), .Y(n526) );
MX2X1TS U1290 ( .A(Raw_mant_NRM_SWR[15]), .B(n1457), .S0(n1468), .Y(n527) );
AO22XLTS U1291 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n905),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AO22XLTS U1292 ( .A0(n930), .A1(SIGN_FLAG_SFG), .B0(n1584), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1293 ( .A0(n1608), .A1(SIGN_FLAG_SHT2), .B0(n1573), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1294 ( .A0(n1748), .A1(SIGN_FLAG_SHT1), .B0(n1750), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1295 ( .A0(n920), .A1(SIGN_FLAG_EXP), .B0(n1572), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1296 ( .A0(n1748), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n1553), .Y(n1696) );
AO22XLTS U1297 ( .A0(n1571), .A1(OP_FLAG_EXP), .B0(n1570), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1298 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n902),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1299 ( .A0(n930), .A1(ZERO_FLAG_SFG), .B0(n1747), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1300 ( .A0(n1550), .A1(ZERO_FLAG_SHT2), .B0(n1569), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1301 ( .A0(n1748), .A1(ZERO_FLAG_SHT1), .B0(n1750), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1302 ( .A0(n1571), .A1(ZERO_FLAG_EXP), .B0(n1568), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
OAI21XLTS U1303 ( .A0(n1659), .A1(n1266), .B0(n1242), .Y(n576) );
OAI21XLTS U1304 ( .A0(n1668), .A1(n1266), .B0(n1245), .Y(n578) );
OAI21XLTS U1305 ( .A0(n1625), .A1(n1266), .B0(n1265), .Y(n580) );
OAI21XLTS U1306 ( .A0(n1661), .A1(n1266), .B0(n1264), .Y(n584) );
OAI21XLTS U1307 ( .A0(n1663), .A1(n1262), .B0(n1260), .Y(n594) );
OAI21XLTS U1308 ( .A0(n1648), .A1(n1262), .B0(n1247), .Y(n598) );
OAI21XLTS U1309 ( .A0(n1665), .A1(n1262), .B0(n1249), .Y(n602) );
OAI21XLTS U1310 ( .A0(n1664), .A1(n1262), .B0(n1250), .Y(n606) );
OAI21XLTS U1311 ( .A0(n1624), .A1(n1262), .B0(n1243), .Y(n610) );
AO22XLTS U1312 ( .A0(n930), .A1(DMP_SFG[30]), .B0(n1747), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1313 ( .A0(n1608), .A1(DMP_SHT2_EWSW[30]), .B0(n1569), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1314 ( .A0(n891), .A1(DMP_SHT1_EWSW[30]), .B0(n1560), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1315 ( .A0(n1561), .A1(DMP_EXP_EWSW[30]), .B0(n1562), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1316 ( .A0(n930), .A1(DMP_SFG[29]), .B0(n1747), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1317 ( .A0(n1608), .A1(DMP_SHT2_EWSW[29]), .B0(n1569), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1318 ( .A0(n891), .A1(DMP_SHT1_EWSW[29]), .B0(n1750), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1319 ( .A0(n1561), .A1(DMP_EXP_EWSW[29]), .B0(n1572), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1320 ( .A0(n930), .A1(DMP_SFG[28]), .B0(n1747), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1321 ( .A0(n1608), .A1(DMP_SHT2_EWSW[28]), .B0(n1569), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1322 ( .A0(n891), .A1(DMP_SHT1_EWSW[28]), .B0(n1750), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1323 ( .A0(n1561), .A1(DMP_EXP_EWSW[28]), .B0(n1572), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1324 ( .A0(n1586), .A1(DMP_SFG[27]), .B0(n1747), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1325 ( .A0(n1608), .A1(DMP_SHT2_EWSW[27]), .B0(n1569), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1326 ( .A0(n891), .A1(DMP_SHT1_EWSW[27]), .B0(n1750), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1327 ( .A0(n1561), .A1(DMP_EXP_EWSW[27]), .B0(n1572), .B1(
DMP_SHT1_EWSW[27]), .Y(n630) );
AO22XLTS U1328 ( .A0(n1586), .A1(DMP_SFG[26]), .B0(n1747), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1329 ( .A0(n1608), .A1(DMP_SHT2_EWSW[26]), .B0(n1569), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1330 ( .A0(n891), .A1(DMP_SHT1_EWSW[26]), .B0(n1750), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1331 ( .A0(n1547), .A1(DMP_EXP_EWSW[26]), .B0(n1572), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1332 ( .A0(n930), .A1(DMP_SFG[25]), .B0(n1584), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1333 ( .A0(n1608), .A1(DMP_SHT2_EWSW[25]), .B0(n1569), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1334 ( .A0(n1559), .A1(DMP_SHT1_EWSW[25]), .B0(n1560), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1335 ( .A0(n1617), .A1(DMP_EXP_EWSW[25]), .B0(n1572), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1336 ( .A0(n1586), .A1(DMP_SFG[24]), .B0(n1747), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1337 ( .A0(n1608), .A1(DMP_SHT2_EWSW[24]), .B0(n1569), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1338 ( .A0(n891), .A1(DMP_SHT1_EWSW[24]), .B0(n1750), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1339 ( .A0(n1617), .A1(DMP_EXP_EWSW[24]), .B0(n1572), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1340 ( .A0(n1586), .A1(DMP_SFG[23]), .B0(n1747), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1341 ( .A0(n1608), .A1(DMP_SHT2_EWSW[23]), .B0(n1573), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1342 ( .A0(n891), .A1(DMP_SHT1_EWSW[23]), .B0(n1750), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1343 ( .A0(n1617), .A1(DMP_EXP_EWSW[23]), .B0(n1572), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1344 ( .A0(n891), .A1(DMP_SHT1_EWSW[22]), .B0(n1750), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1345 ( .A0(n1617), .A1(DMP_EXP_EWSW[22]), .B0(n1572), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1346 ( .A0(n891), .A1(DMP_SHT1_EWSW[21]), .B0(n1556), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1347 ( .A0(n1617), .A1(DMP_EXP_EWSW[21]), .B0(n1572), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1348 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1556), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1349 ( .A0(n1617), .A1(DMP_EXP_EWSW[20]), .B0(n1555), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1350 ( .A0(n1559), .A1(DMP_SHT1_EWSW[19]), .B0(n1556), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1351 ( .A0(n1617), .A1(DMP_EXP_EWSW[19]), .B0(n1555), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1352 ( .A0(n1559), .A1(DMP_SHT1_EWSW[18]), .B0(n1556), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1353 ( .A0(n1617), .A1(DMP_EXP_EWSW[18]), .B0(n1555), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1354 ( .A0(n1559), .A1(DMP_SHT1_EWSW[17]), .B0(n1556), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1355 ( .A0(n1554), .A1(DMP_EXP_EWSW[17]), .B0(n1555), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1356 ( .A0(n1559), .A1(DMP_SHT1_EWSW[16]), .B0(n1556), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1357 ( .A0(n1554), .A1(DMP_EXP_EWSW[16]), .B0(n1555), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1358 ( .A0(n1559), .A1(DMP_SHT1_EWSW[15]), .B0(n1556), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1359 ( .A0(n1554), .A1(DMP_EXP_EWSW[15]), .B0(n1555), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1360 ( .A0(n1559), .A1(DMP_SHT1_EWSW[14]), .B0(n1556), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1361 ( .A0(n1554), .A1(DMP_EXP_EWSW[14]), .B0(n1555), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1362 ( .A0(n1559), .A1(DMP_SHT1_EWSW[13]), .B0(n1556), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1363 ( .A0(n1554), .A1(DMP_EXP_EWSW[13]), .B0(n1555), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1364 ( .A0(n1559), .A1(DMP_SHT1_EWSW[12]), .B0(n1556), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1365 ( .A0(n1554), .A1(DMP_EXP_EWSW[12]), .B0(n1555), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1366 ( .A0(n1559), .A1(DMP_SHT1_EWSW[11]), .B0(n1553), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1367 ( .A0(n1554), .A1(DMP_EXP_EWSW[11]), .B0(n1555), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1368 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n1553), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1369 ( .A0(n1554), .A1(DMP_EXP_EWSW[10]), .B0(n1552), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1370 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1553), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1371 ( .A0(n1554), .A1(DMP_EXP_EWSW[9]), .B0(n1552), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1372 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1553), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1373 ( .A0(n1554), .A1(DMP_EXP_EWSW[8]), .B0(n1552), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1374 ( .A0(n1748), .A1(DMP_SHT1_EWSW[7]), .B0(DMP_SHT2_EWSW[7]),
.B1(n1560), .Y(n1697) );
AO22XLTS U1375 ( .A0(n1551), .A1(DMP_EXP_EWSW[7]), .B0(n1552), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1376 ( .A0(n1748), .A1(DMP_SHT1_EWSW[6]), .B0(DMP_SHT2_EWSW[6]),
.B1(n1560), .Y(n1698) );
AO22XLTS U1377 ( .A0(n1551), .A1(DMP_EXP_EWSW[6]), .B0(n1552), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1378 ( .A0(n1748), .A1(DMP_SHT1_EWSW[5]), .B0(DMP_SHT2_EWSW[5]),
.B1(n1560), .Y(n1699) );
AO22XLTS U1379 ( .A0(n1551), .A1(DMP_EXP_EWSW[5]), .B0(n1552), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1380 ( .A0(n1748), .A1(DMP_SHT1_EWSW[4]), .B0(DMP_SHT2_EWSW[4]),
.B1(n892), .Y(n1700) );
AO22XLTS U1381 ( .A0(n1551), .A1(DMP_EXP_EWSW[4]), .B0(n1552), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1382 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1553), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1383 ( .A0(n1551), .A1(DMP_EXP_EWSW[3]), .B0(n1552), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1384 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1553), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1385 ( .A0(n1551), .A1(DMP_EXP_EWSW[2]), .B0(n1552), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1386 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1553), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1387 ( .A0(n1551), .A1(DMP_EXP_EWSW[1]), .B0(n1552), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1388 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1560), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
AO22XLTS U1389 ( .A0(n1551), .A1(DMP_EXP_EWSW[0]), .B0(n1695), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1390 ( .A0(n1272), .A1(n1548), .B0(ZERO_FLAG_EXP), .B1(n1549), .Y(
n721) );
AO21XLTS U1391 ( .A0(OP_FLAG_EXP), .A1(n1549), .B0(n1548), .Y(n722) );
OAI21XLTS U1392 ( .A0(n1673), .A1(n1315), .B0(n1295), .Y(n723) );
OAI21XLTS U1393 ( .A0(n1628), .A1(n1315), .B0(n1309), .Y(n734) );
OAI21XLTS U1394 ( .A0(n1659), .A1(n1315), .B0(n1301), .Y(n736) );
OAI21XLTS U1395 ( .A0(n1668), .A1(n1308), .B0(n1304), .Y(n737) );
OAI21XLTS U1396 ( .A0(n1625), .A1(n1308), .B0(n1003), .Y(n738) );
OAI21XLTS U1397 ( .A0(n1667), .A1(n1308), .B0(n1297), .Y(n739) );
OAI21XLTS U1398 ( .A0(n1666), .A1(n1308), .B0(n1298), .Y(n741) );
OAI21XLTS U1399 ( .A0(n1649), .A1(n1308), .B0(n1302), .Y(n746) );
AO22XLTS U1400 ( .A0(n1551), .A1(n1151), .B0(n1695), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
AO22XLTS U1401 ( .A0(n1551), .A1(n1146), .B0(n1695), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
AO22XLTS U1402 ( .A0(n1547), .A1(n1546), .B0(n1695), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AO22XLTS U1403 ( .A0(n1500), .A1(n1565), .B0(n1502), .B1(n1503), .Y(n869) );
NAND2X4TS U1404 ( .A(n1079), .B(n873), .Y(n1080) );
NOR2X2TS U1405 ( .A(n1079), .B(n888), .Y(n1363) );
NAND2X4TS U1406 ( .A(Shift_reg_FLAGS_7[1]), .B(n1018), .Y(n1528) );
INVX4TS U1407 ( .A(n1327), .Y(n906) );
INVX2TS U1408 ( .A(n903), .Y(n1574) );
INVX2TS U1409 ( .A(n911), .Y(n1606) );
INVX4TS U1410 ( .A(n1526), .Y(n888) );
INVX2TS U1411 ( .A(n1528), .Y(n1376) );
AND2X4TS U1412 ( .A(n1565), .B(n1001), .Y(n1293) );
BUFX3TS U1413 ( .A(n1293), .Y(n1316) );
OR3X1TS U1414 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1633), .Y(n881) );
INVX2TS U1415 ( .A(left_right_SHT2), .Y(n910) );
INVX2TS U1416 ( .A(n1750), .Y(n891) );
CLKINVX3TS U1417 ( .A(rst), .Y(n1139) );
INVX2TS U1418 ( .A(n1363), .Y(n889) );
INVX2TS U1419 ( .A(n889), .Y(n890) );
INVX2TS U1420 ( .A(n883), .Y(n893) );
INVX2TS U1421 ( .A(n883), .Y(n894) );
INVX2TS U1422 ( .A(n881), .Y(n895) );
INVX2TS U1423 ( .A(n884), .Y(n898) );
INVX2TS U1424 ( .A(n884), .Y(n899) );
INVX2TS U1425 ( .A(n882), .Y(n900) );
INVX2TS U1426 ( .A(Shift_reg_FLAGS_7[1]), .Y(n902) );
INVX2TS U1427 ( .A(n902), .Y(n903) );
INVX2TS U1428 ( .A(n1574), .Y(n904) );
INVX2TS U1429 ( .A(n904), .Y(n905) );
INVX4TS U1430 ( .A(n1327), .Y(n907) );
INVX4TS U1431 ( .A(n1528), .Y(n909) );
INVX2TS U1432 ( .A(n876), .Y(n913) );
INVX2TS U1433 ( .A(n876), .Y(n914) );
INVX2TS U1434 ( .A(n876), .Y(n915) );
INVX2TS U1435 ( .A(n880), .Y(n916) );
INVX2TS U1436 ( .A(n880), .Y(n918) );
NAND2X1TS U1437 ( .A(n1085), .B(n1084), .Y(n771) );
OAI21XLTS U1438 ( .A0(n1674), .A1(n1266), .B0(n1253), .Y(n560) );
OAI211XLTS U1439 ( .A0(n1337), .A1(n906), .B0(n1336), .C0(n1335), .Y(n773)
);
BUFX3TS U1440 ( .A(n1139), .Y(n1141) );
BUFX3TS U1441 ( .A(n1139), .Y(n1140) );
CLKBUFX3TS U1442 ( .A(n1139), .Y(n1143) );
OAI21XLTS U1443 ( .A0(n1748), .A1(n1606), .B0(n902), .Y(n829) );
AOI222X1TS U1444 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n908), .B0(n917), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1522), .C1(DmP_mant_SHT1_SW[12]), .Y(n1359) );
AOI222X1TS U1445 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n908), .B0(n917), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1522), .C1(DmP_mant_SHT1_SW[10]), .Y(n1362)
);
AOI222X1TS U1446 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n908), .B0(n916), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1373), .C1(DmP_mant_SHT1_SW[7]), .Y(n1378)
);
AOI222X1TS U1447 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n909), .B0(n917), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1522), .C1(DmP_mant_SHT1_SW[8]), .Y(n1350)
);
OAI21XLTS U1448 ( .A0(n1674), .A1(n1315), .B0(n1294), .Y(n726) );
OAI21XLTS U1449 ( .A0(DmP_EXP_EWSW[25]), .A1(n924), .B0(n1543), .Y(n1544) );
AOI22X2TS U1450 ( .A0(Data_array_SWR[22]), .A1(n1102), .B0(
Data_array_SWR[18]), .B1(n1107), .Y(n1403) );
AOI221X1TS U1451 ( .A0(n1635), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1643), .C0(n1168), .Y(n1173) );
AOI221X1TS U1452 ( .A0(intDX_EWSW[30]), .A1(n1673), .B0(intDX_EWSW[29]),
.B1(n1627), .C0(n994), .Y(n996) );
AOI221X1TS U1453 ( .A0(n1673), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1659), .C0(n1159), .Y(n1166) );
NOR2X1TS U1454 ( .A(n1673), .B(intDX_EWSW[30]), .Y(n995) );
AOI221X1TS U1455 ( .A0(n1664), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1658), .C0(n1176), .Y(n1181) );
AOI221X1TS U1456 ( .A0(n1626), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1672), .C0(n1162), .Y(n1163) );
AOI221X1TS U1457 ( .A0(n1667), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1625), .C0(n1170), .Y(n1171) );
AOI221X1TS U1458 ( .A0(n1669), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1662), .C0(n1161), .Y(n1164) );
AOI221X1TS U1459 ( .A0(n1666), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1661), .C0(n1169), .Y(n1172) );
INVX2TS U1460 ( .A(n1592), .Y(n919) );
INVX2TS U1461 ( .A(n1592), .Y(n1601) );
OAI21XLTS U1462 ( .A0(n1241), .A1(n1235), .B0(n1234), .Y(n472) );
OAI21XLTS U1463 ( .A0(n1241), .A1(n1237), .B0(n1236), .Y(n468) );
OAI21XLTS U1464 ( .A0(n1221), .A1(n1241), .B0(n1220), .Y(n466) );
XOR2X1TS U1465 ( .A(n1480), .B(DmP_mant_SFG_SWR[17]), .Y(n1047) );
OAI21XLTS U1466 ( .A0(n1241), .A1(n1233), .B0(n1232), .Y(n469) );
OAI31XLTS U1467 ( .A0(n1272), .A1(n1271), .A2(n1566), .B0(n1270), .Y(n720)
);
AFHCINX2TS U1468 ( .CIN(n1470), .B(n1471), .A(DMP_SFG[9]), .S(n1472), .CO(
n1473) );
AFHCINX2TS U1469 ( .CIN(n1466), .B(n1467), .A(DMP_SFG[11]), .S(n1469), .CO(
n1463) );
AFHCINX2TS U1470 ( .CIN(n1421), .B(n1422), .A(DMP_SFG[22]), .S(n1423), .CO(
n1055) );
BUFX3TS U1471 ( .A(OP_FLAG_SFG), .Y(n1388) );
NOR2X2TS U1472 ( .A(n925), .B(DMP_EXP_EWSW[23]), .Y(n1541) );
AOI21X2TS U1473 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n905), .B0(n1492), .Y(
n1035) );
XNOR2X2TS U1474 ( .A(DMP_exp_NRM2_EW[0]), .B(n877), .Y(n1191) );
BUFX3TS U1475 ( .A(n1139), .Y(n1144) );
AOI222X4TS U1476 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n909), .B0(n917), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1522), .C1(DmP_mant_SHT1_SW[17]), .Y(n1381) );
AFHCINX2TS U1477 ( .CIN(n1045), .B(n1582), .A(DMP_SFG[7]), .CO(n1476) );
OAI21XLTS U1478 ( .A0(n1267), .A1(intDX_EWSW[31]), .B0(n1565), .Y(n1187) );
OAI211XLTS U1479 ( .A0(n1350), .A1(n906), .B0(n1347), .C0(n1346), .Y(n778)
);
AOI22X2TS U1480 ( .A0(Data_array_SWR[23]), .A1(n1102), .B0(
Data_array_SWR[19]), .B1(n1107), .Y(n1410) );
AOI221X1TS U1481 ( .A0(n1675), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1628), .C0(n1160), .Y(n1165) );
AOI32X1TS U1482 ( .A0(n1675), .A1(n972), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1628), .Y(n973) );
NOR2X1TS U1483 ( .A(n1627), .B(intDX_EWSW[29]), .Y(n993) );
OAI2BB2XLTS U1484 ( .B0(intDY_EWSW[0]), .B1(n952), .A0N(intDX_EWSW[1]),
.A1N(n1752), .Y(n954) );
NOR2XLTS U1485 ( .A(n1643), .B(intDX_EWSW[11]), .Y(n932) );
NOR2X1TS U1486 ( .A(n1659), .B(intDX_EWSW[17]), .Y(n970) );
BUFX3TS U1487 ( .A(n1617), .Y(n920) );
NOR2X4TS U1488 ( .A(shift_value_SHT2_EWR[4]), .B(n1606), .Y(n1409) );
OA22X1TS U1489 ( .A0(n1667), .A1(intDX_EWSW[14]), .B0(n1625), .B1(
intDX_EWSW[15]), .Y(n943) );
OAI21XLTS U1490 ( .A0(intDX_EWSW[13]), .A1(n1661), .B0(intDX_EWSW[12]), .Y(
n931) );
OAI21XLTS U1491 ( .A0(intDX_EWSW[21]), .A1(n1662), .B0(intDX_EWSW[20]), .Y(
n969) );
OA22X1TS U1492 ( .A0(n1626), .A1(intDX_EWSW[22]), .B0(n1672), .B1(
intDX_EWSW[23]), .Y(n980) );
NOR2X2TS U1493 ( .A(n1068), .B(n1493), .Y(n928) );
BUFX3TS U1494 ( .A(n1508), .Y(n1511) );
OAI21XLTS U1495 ( .A0(intDX_EWSW[1]), .A1(n1752), .B0(intDX_EWSW[0]), .Y(
n952) );
NOR2XLTS U1496 ( .A(n970), .B(intDY_EWSW[16]), .Y(n971) );
NOR2XLTS U1497 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1021) );
NOR3X1TS U1498 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1126) );
NOR2BX1TS U1499 ( .AN(n1061), .B(n1615), .Y(n1043) );
INVX2TS U1500 ( .A(n1449), .Y(n1451) );
OR2X1TS U1501 ( .A(n1048), .B(DMP_SFG[16]), .Y(n1443) );
NOR2X2TS U1502 ( .A(n1079), .B(n1574), .Y(n1492) );
AOI21X1TS U1503 ( .A0(n1134), .A1(Raw_mant_NRM_SWR[10]), .B0(n1133), .Y(
n1537) );
NOR2XLTS U1504 ( .A(n928), .B(SIGN_FLAG_SHT1SHT2), .Y(n1386) );
AFHCINX2TS U1505 ( .CIN(n1415), .B(n1416), .A(DMP_SFG[20]), .S(n1417), .CO(
n1418) );
BUFX3TS U1506 ( .A(n1508), .Y(n1518) );
OAI21XLTS U1507 ( .A0(n1241), .A1(n1240), .B0(n1239), .Y(n470) );
OAI21XLTS U1508 ( .A0(n1672), .A1(n1315), .B0(n1296), .Y(n730) );
OAI2BB2XLTS U1509 ( .B0(intDY_EWSW[12]), .B1(n931), .A0N(intDX_EWSW[13]),
.A1N(n1661), .Y(n942) );
AOI22X1TS U1510 ( .A0(intDX_EWSW[11]), .A1(n1643), .B0(intDX_EWSW[10]), .B1(
n933), .Y(n938) );
AOI21X1TS U1511 ( .A0(n936), .A1(n935), .B0(n945), .Y(n937) );
OAI22X1TS U1512 ( .A0(n1635), .A1(intDX_EWSW[10]), .B0(n1643), .B1(
intDX_EWSW[11]), .Y(n1168) );
INVX2TS U1513 ( .A(n1168), .Y(n946) );
OAI2BB2XLTS U1514 ( .B0(intDY_EWSW[14]), .B1(n939), .A0N(intDX_EWSW[15]),
.A1N(n1625), .Y(n940) );
AOI211X1TS U1515 ( .A0(n943), .A1(n942), .B0(n941), .C0(n940), .Y(n944) );
OAI2BB1X1TS U1516 ( .A0N(n1632), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n950) );
OAI22X1TS U1517 ( .A0(intDY_EWSW[4]), .A1(n950), .B0(n1632), .B1(
intDY_EWSW[5]), .Y(n961) );
OAI2BB1X1TS U1518 ( .A0N(n1619), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n951) );
OAI22X1TS U1519 ( .A0(intDY_EWSW[6]), .A1(n951), .B0(n1619), .B1(
intDY_EWSW[7]), .Y(n960) );
AOI22X1TS U1520 ( .A0(intDY_EWSW[7]), .A1(n1619), .B0(intDY_EWSW[6]), .B1(
n1637), .Y(n958) );
OAI21X2TS U1521 ( .A0(intDX_EWSW[18]), .A1(n1675), .B0(n972), .Y(n1160) );
AOI211X1TS U1522 ( .A0(intDY_EWSW[16]), .A1(n1636), .B0(n975), .C0(n1160),
.Y(n965) );
OAI2BB2XLTS U1523 ( .B0(intDY_EWSW[20]), .B1(n969), .A0N(intDX_EWSW[21]),
.A1N(n1662), .Y(n979) );
AOI22X1TS U1524 ( .A0(intDX_EWSW[17]), .A1(n1659), .B0(intDX_EWSW[16]), .B1(
n971), .Y(n974) );
OAI32X1TS U1525 ( .A0(n1160), .A1(n975), .A2(n974), .B0(n973), .B1(n975),
.Y(n978) );
OAI2BB2XLTS U1526 ( .B0(intDY_EWSW[22]), .B1(n976), .A0N(intDX_EWSW[23]),
.A1N(n1672), .Y(n977) );
AOI211X1TS U1527 ( .A0(n980), .A1(n979), .B0(n978), .C0(n977), .Y(n981) );
OAI21X2TS U1528 ( .A0(intDX_EWSW[26]), .A1(n1670), .B0(n989), .Y(n1153) );
NOR2X1TS U1529 ( .A(n1657), .B(intDX_EWSW[25]), .Y(n987) );
NAND4BBX1TS U1530 ( .AN(n1153), .BN(n987), .C(n997), .D(n983), .Y(n984) );
AOI22X1TS U1531 ( .A0(intDX_EWSW[25]), .A1(n1657), .B0(intDX_EWSW[24]), .B1(
n988), .Y(n992) );
OAI211X1TS U1532 ( .A0(n992), .A1(n1153), .B0(n991), .C0(n990), .Y(n998) );
NOR3X1TS U1533 ( .A(n1639), .B(n993), .C(intDY_EWSW[28]), .Y(n994) );
BUFX3TS U1534 ( .A(n1244), .Y(n1549) );
NOR2X4TS U1535 ( .A(n1001), .B(n1549), .Y(n1246) );
CLKBUFX2TS U1536 ( .A(n1244), .Y(n1273) );
BUFX3TS U1537 ( .A(n1273), .Y(n1305) );
AOI22X1TS U1538 ( .A0(intDX_EWSW[13]), .A1(n1322), .B0(DMP_EXP_EWSW[13]),
.B1(n1305), .Y(n1002) );
AOI22X1TS U1539 ( .A0(intDX_EWSW[15]), .A1(n1322), .B0(DMP_EXP_EWSW[15]),
.B1(n1305), .Y(n1003) );
NOR2X2TS U1540 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(
n1025) );
NOR2X2TS U1541 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1022) );
NAND2X2TS U1542 ( .A(n1025), .B(n1022), .Y(n1488) );
INVX2TS U1543 ( .A(n1488), .Y(n1004) );
OR2X4TS U1544 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[21]), .Y(n1024) );
NAND2X2TS U1545 ( .A(n1004), .B(n1489), .Y(n1005) );
NOR2X4TS U1546 ( .A(Raw_mant_NRM_SWR[18]), .B(n1005), .Y(n1127) );
NAND2X2TS U1547 ( .A(n1127), .B(n1126), .Y(n1009) );
OR2X4TS U1548 ( .A(n1009), .B(Raw_mant_NRM_SWR[14]), .Y(n1130) );
NOR2X8TS U1549 ( .A(Raw_mant_NRM_SWR[12]), .B(n1015), .Y(n1134) );
NAND2BX4TS U1550 ( .AN(Raw_mant_NRM_SWR[10]), .B(n1134), .Y(n1210) );
NOR3X6TS U1551 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1210),
.Y(n1027) );
NAND2X6TS U1552 ( .A(n1027), .B(n1642), .Y(n1208) );
INVX2TS U1553 ( .A(n1208), .Y(n1017) );
INVX2TS U1554 ( .A(n1005), .Y(n1013) );
AOI22X1TS U1555 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1013), .B0(n1134), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1030) );
OAI32X1TS U1556 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1621), .B0(n1634), .B1(Raw_mant_NRM_SWR[3]), .Y(n1006) );
NOR2X8TS U1557 ( .A(Raw_mant_NRM_SWR[6]), .B(n1208), .Y(n1484) );
NAND3X2TS U1558 ( .A(n1030), .B(n1007), .C(n1131), .Y(n1491) );
AOI21X1TS U1559 ( .A0(n1656), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n1008) );
NOR2X2TS U1560 ( .A(n1640), .B(n1009), .Y(n1034) );
INVX2TS U1561 ( .A(n1034), .Y(n1010) );
OAI31X1TS U1562 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1015), .A2(n1641), .B0(
n1014), .Y(n1016) );
NOR2X8TS U1563 ( .A(n1018), .B(n1574), .Y(n1526) );
BUFX3TS U1564 ( .A(n1373), .Y(n1522) );
AOI22X1TS U1565 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n873), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1522), .Y(n1019) );
AOI21X1TS U1566 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n917), .B0(n1020), .Y(n1525) );
AOI21X1TS U1567 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1021), .B0(
Raw_mant_NRM_SWR[19]), .Y(n1023) );
NOR2X1TS U1568 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1129)
);
NOR2X1TS U1569 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1209)
);
NAND2X4TS U1570 ( .A(n1484), .B(n1209), .Y(n1213) );
OAI21X1TS U1571 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1027), .Y(n1028) );
OAI21X2TS U1572 ( .A0(n1129), .A1(n1213), .B0(n1028), .Y(n1215) );
INVX2TS U1573 ( .A(n1029), .Y(n1031) );
OAI31X1TS U1574 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1620), .A2(n1031), .B0(
n1030), .Y(n1032) );
NOR4X4TS U1575 ( .A(n1034), .B(n1033), .C(n1215), .D(n1032), .Y(n1079) );
BUFX3TS U1576 ( .A(n892), .Y(n1553) );
NAND2X4TS U1577 ( .A(n902), .B(n1553), .Y(n1535) );
CLKBUFX2TS U1578 ( .A(n1358), .Y(n1125) );
BUFX3TS U1579 ( .A(n1125), .Y(n1383) );
NOR2X4TS U1580 ( .A(n1383), .B(n1035), .Y(n1327) );
OAI22X1TS U1581 ( .A0(n1381), .A1(n907), .B0(n1689), .B1(n889), .Y(n1036) );
AOI21X1TS U1582 ( .A0(n1383), .A1(Data_array_SWR[16]), .B0(n1036), .Y(n1037)
);
AOI22X1TS U1583 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n873), .B0(n1081), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1038) );
AOI21X1TS U1584 ( .A0(n918), .A1(DmP_mant_SHT1_SW[18]), .B0(n1039), .Y(n1385) );
OAI22X1TS U1585 ( .A0(n1331), .A1(n906), .B0(n1634), .B1(n889), .Y(n1040) );
AOI21X1TS U1586 ( .A0(n1383), .A1(Data_array_SWR[20]), .B0(n1040), .Y(n1041)
);
XOR2X1TS U1587 ( .A(n1053), .B(DmP_mant_SFG_SWR[24]), .Y(n1422) );
XOR2X1TS U1588 ( .A(n1053), .B(DmP_mant_SFG_SWR[23]), .Y(n1419) );
XOR2X1TS U1589 ( .A(n1053), .B(DmP_mant_SFG_SWR[22]), .Y(n1416) );
XOR2X1TS U1590 ( .A(n1053), .B(DmP_mant_SFG_SWR[21]), .Y(n1425) );
XOR2X1TS U1591 ( .A(n1053), .B(DmP_mant_SFG_SWR[20]), .Y(n1428) );
XOR2X1TS U1592 ( .A(n1388), .B(DmP_mant_SFG_SWR[15]), .Y(n1456) );
XOR2X1TS U1593 ( .A(n1388), .B(DmP_mant_SFG_SWR[14]), .Y(n1464) );
XOR2X1TS U1594 ( .A(n1388), .B(DmP_mant_SFG_SWR[13]), .Y(n1467) );
XOR2X1TS U1595 ( .A(n1388), .B(DmP_mant_SFG_SWR[12]), .Y(n1474) );
XOR2X1TS U1596 ( .A(n1388), .B(DmP_mant_SFG_SWR[11]), .Y(n1471) );
XOR2X1TS U1597 ( .A(n1053), .B(DmP_mant_SFG_SWR[10]), .Y(n1477) );
CLKXOR2X2TS U1598 ( .A(n1388), .B(DmP_mant_SFG_SWR[9]), .Y(n1582) );
CLKXOR2X2TS U1599 ( .A(n1388), .B(DmP_mant_SFG_SWR[7]), .Y(n1060) );
XOR2X1TS U1600 ( .A(OP_FLAG_SFG), .B(DmP_mant_SFG_SWR[6]), .Y(n1059) );
NAND2X1TS U1601 ( .A(n1059), .B(DMP_SFG[4]), .Y(n1042) );
AFHCINX2TS U1602 ( .CIN(n1042), .B(n1060), .A(DMP_SFG[5]), .CO(n1044) );
CLKXOR2X2TS U1603 ( .A(n1388), .B(DmP_mant_SFG_SWR[8]), .Y(n1061) );
XOR2X1TS U1604 ( .A(n1480), .B(DmP_mant_SFG_SWR[16]), .Y(n1046) );
NOR2X1TS U1605 ( .A(n1046), .B(DMP_SFG[14]), .Y(n1447) );
NOR2X2TS U1606 ( .A(n1047), .B(DMP_SFG[15]), .Y(n1449) );
XOR2X1TS U1607 ( .A(n1053), .B(DmP_mant_SFG_SWR[18]), .Y(n1048) );
NOR2X2TS U1608 ( .A(n1050), .B(DMP_SFG[17]), .Y(n1434) );
NAND2X1TS U1609 ( .A(n1046), .B(DMP_SFG[14]), .Y(n1458) );
NAND2X1TS U1610 ( .A(n1047), .B(DMP_SFG[15]), .Y(n1450) );
OAI21X1TS U1611 ( .A0(n1449), .A1(n1458), .B0(n1450), .Y(n1440) );
NAND2X1TS U1612 ( .A(n1048), .B(DMP_SFG[16]), .Y(n1442) );
INVX2TS U1613 ( .A(n1442), .Y(n1049) );
AOI21X1TS U1614 ( .A0(n1440), .A1(n1443), .B0(n1049), .Y(n1431) );
NAND2X1TS U1615 ( .A(n1050), .B(DMP_SFG[17]), .Y(n1435) );
AOI21X4TS U1616 ( .A0(n1461), .A1(n1052), .B0(n1051), .Y(n1427) );
XOR2X1TS U1617 ( .A(n1053), .B(DmP_mant_SFG_SWR[25]), .Y(n1054) );
INVX2TS U1618 ( .A(n1291), .Y(n1289) );
AOI22X1TS U1619 ( .A0(intDX_EWSW[3]), .A1(n1306), .B0(DMP_EXP_EWSW[3]), .B1(
n1549), .Y(n1057) );
NOR2X2TS U1620 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1650), .Y(n1498) );
INVX2TS U1621 ( .A(n1059), .Y(intadd_65_B_2_) );
INVX2TS U1622 ( .A(n1060), .Y(intadd_65_B_3_) );
INVX2TS U1623 ( .A(n1061), .Y(intadd_65_B_4_) );
XNOR2X2TS U1624 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J58_123_4652_n4), .Y(
n1090) );
INVX2TS U1625 ( .A(DP_OP_15J58_123_4652_n4), .Y(n1062) );
XNOR2X2TS U1626 ( .A(DMP_exp_NRM2_EW[6]), .B(n1066), .Y(n1091) );
INVX2TS U1627 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1078) );
INVX2TS U1628 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1076) );
INVX2TS U1629 ( .A(n1066), .Y(n1067) );
XNOR2X2TS U1630 ( .A(DMP_exp_NRM2_EW[7]), .B(n1093), .Y(n1493) );
NAND2X2TS U1631 ( .A(n928), .B(Shift_reg_FLAGS_7[0]), .Y(n1567) );
BUFX3TS U1632 ( .A(n1751), .Y(n1501) );
NAND2X1TS U1633 ( .A(n1501), .B(final_result_ieee[28]), .Y(n1069) );
NAND2X1TS U1634 ( .A(n1501), .B(final_result_ieee[29]), .Y(n1071) );
INVX2TS U1635 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1074) );
NAND2X1TS U1636 ( .A(n1501), .B(final_result_ieee[27]), .Y(n1073) );
NAND2X1TS U1637 ( .A(n1501), .B(final_result_ieee[25]), .Y(n1075) );
NAND2X1TS U1638 ( .A(n1501), .B(final_result_ieee[26]), .Y(n1077) );
AOI22X1TS U1639 ( .A0(n1377), .A1(Raw_mant_NRM_SWR[24]), .B0(n1358), .B1(
Data_array_SWR[0]), .Y(n1085) );
AOI21X1TS U1640 ( .A0(n873), .A1(Raw_mant_NRM_SWR[22]), .B0(n1082), .Y(n1083) );
OAI2BB1X1TS U1641 ( .A0N(Raw_mant_NRM_SWR[23]), .A1N(n909), .B0(n1083), .Y(
n1334) );
AOI22X1TS U1642 ( .A0(n1327), .A1(n1334), .B0(n1376), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1084) );
BUFX3TS U1643 ( .A(n892), .Y(n1560) );
INVX2TS U1644 ( .A(n1560), .Y(busy) );
NAND2X2TS U1645 ( .A(shift_value_SHT2_EWR[2]), .B(n1633), .Y(n1123) );
AOI22X1TS U1646 ( .A0(Data_array_SWR[12]), .A1(n896), .B0(Data_array_SWR[8]),
.B1(n1086), .Y(n1088) );
INVX2TS U1647 ( .A(n1123), .Y(n1102) );
NOR2X4TS U1648 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1107) );
AO22X1TS U1649 ( .A0(Data_array_SWR[24]), .A1(n1102), .B0(Data_array_SWR[20]), .B1(n1107), .Y(n1114) );
AOI22X1TS U1650 ( .A0(Data_array_SWR[16]), .A1(n894), .B0(
shift_value_SHT2_EWR[4]), .B1(n1114), .Y(n1087) );
NAND2X1TS U1651 ( .A(n1088), .B(n1087), .Y(n1117) );
AOI22X1TS U1652 ( .A0(Data_array_SWR[21]), .A1(n1107), .B0(
Data_array_SWR[25]), .B1(n1102), .Y(n1098) );
INVX2TS U1653 ( .A(n1098), .Y(n1116) );
AND4X1TS U1654 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n1191), .D(exp_rslt_NRM2_EW1[1]), .Y(n1089) );
INVX2TS U1655 ( .A(n1093), .Y(n1094) );
OAI2BB1X2TS U1656 ( .A0N(n927), .A1N(n1095), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1495) );
BUFX3TS U1657 ( .A(n1751), .Y(n1598) );
OAI2BB2XLTS U1658 ( .B0(n1611), .B1(n1601), .A0N(final_result_ieee[2]),
.A1N(n1598), .Y(n495) );
AOI22X1TS U1659 ( .A0(Data_array_SWR[13]), .A1(n896), .B0(Data_array_SWR[9]),
.B1(n897), .Y(n1097) );
NAND2X1TS U1660 ( .A(Data_array_SWR[17]), .B(n894), .Y(n1096) );
OAI211X1TS U1661 ( .A0(n1098), .A1(n879), .B0(n1097), .C0(n1096), .Y(n1115)
);
OAI2BB2XLTS U1662 ( .B0(n1613), .B1(n1601), .A0N(final_result_ieee[3]),
.A1N(n1598), .Y(n497) );
AOI22X1TS U1663 ( .A0(Data_array_SWR[15]), .A1(n893), .B0(Data_array_SWR[11]), .B1(n895), .Y(n1101) );
INVX2TS U1664 ( .A(n1099), .Y(n1223) );
AOI22X1TS U1665 ( .A0(Data_array_SWR[7]), .A1(n897), .B0(Data_array_SWR[3]),
.B1(n1223), .Y(n1100) );
OAI211X1TS U1666 ( .A0(n1410), .A1(n879), .B0(n1101), .C0(n1100), .Y(n1136)
);
AOI22X1TS U1667 ( .A0(Data_array_SWR[22]), .A1(n901), .B0(n875), .B1(n1136),
.Y(n1610) );
BUFX3TS U1668 ( .A(n1751), .Y(n1589) );
OAI2BB2XLTS U1669 ( .B0(n1610), .B1(n919), .A0N(final_result_ieee[1]), .A1N(
n1589), .Y(n493) );
AOI22X1TS U1670 ( .A0(Data_array_SWR[14]), .A1(n893), .B0(Data_array_SWR[10]), .B1(n895), .Y(n1104) );
AOI22X1TS U1671 ( .A0(Data_array_SWR[6]), .A1(n1086), .B0(Data_array_SWR[2]),
.B1(n1223), .Y(n1103) );
OAI211X1TS U1672 ( .A0(n1403), .A1(n879), .B0(n1104), .C0(n1103), .Y(n1137)
);
AOI22X1TS U1673 ( .A0(Data_array_SWR[23]), .A1(n901), .B0(n1606), .B1(n1137),
.Y(n1609) );
OAI2BB2XLTS U1674 ( .B0(n1609), .B1(n1601), .A0N(final_result_ieee[0]),
.A1N(n1589), .Y(n492) );
AOI22X1TS U1675 ( .A0(Data_array_SWR[17]), .A1(n895), .B0(Data_array_SWR[13]), .B1(n897), .Y(n1106) );
AOI22X1TS U1676 ( .A0(Data_array_SWR[21]), .A1(n893), .B0(Data_array_SWR[25]), .B1(n1118), .Y(n1105) );
NAND2X1TS U1677 ( .A(n1106), .B(n1105), .Y(n1196) );
OR2X1TS U1678 ( .A(shift_value_SHT2_EWR[2]), .B(n1633), .Y(n1121) );
OAI222X4TS U1679 ( .A0(n1704), .A1(n1121), .B0(n1705), .B1(n1123), .C0(n1706), .C1(n1122), .Y(n1202) );
NOR2X4TS U1680 ( .A(shift_value_SHT2_EWR[4]), .B(n912), .Y(n1124) );
AOI222X1TS U1681 ( .A0(n1196), .A1(left_right_SHT2), .B0(Data_array_SWR[9]),
.B1(n901), .C0(n1202), .C1(n1124), .Y(n1235) );
OAI2BB2XLTS U1682 ( .B0(n1235), .B1(n1601), .A0N(final_result_ieee[14]),
.A1N(n1598), .Y(n504) );
AOI22X1TS U1683 ( .A0(Data_array_SWR[14]), .A1(n895), .B0(Data_array_SWR[10]), .B1(n897), .Y(n1109) );
AOI22X1TS U1684 ( .A0(Data_array_SWR[22]), .A1(n1118), .B0(
Data_array_SWR[18]), .B1(n893), .Y(n1108) );
NAND2X1TS U1685 ( .A(n1109), .B(n1108), .Y(n1407) );
INVX2TS U1686 ( .A(n1410), .Y(n1110) );
AOI222X1TS U1687 ( .A0(n1407), .A1(n912), .B0(Data_array_SWR[6]), .B1(n900),
.C0(n1110), .C1(n1124), .Y(n1233) );
OAI2BB2XLTS U1688 ( .B0(n1233), .B1(n1601), .A0N(final_result_ieee[17]),
.A1N(n1598), .Y(n498) );
AOI22X1TS U1689 ( .A0(Data_array_SWR[15]), .A1(n895), .B0(Data_array_SWR[11]), .B1(n897), .Y(n1112) );
AOI22X1TS U1690 ( .A0(Data_array_SWR[23]), .A1(n1118), .B0(
Data_array_SWR[19]), .B1(n893), .Y(n1111) );
NAND2X1TS U1691 ( .A(n1112), .B(n1111), .Y(n1402) );
INVX2TS U1692 ( .A(n1403), .Y(n1113) );
AOI222X1TS U1693 ( .A0(n1402), .A1(n912), .B0(Data_array_SWR[7]), .B1(n901),
.C0(n1113), .C1(n1124), .Y(n1240) );
OAI2BB2XLTS U1694 ( .B0(n1240), .B1(n1601), .A0N(final_result_ieee[16]),
.A1N(n1598), .Y(n500) );
OAI2BB2XLTS U1695 ( .B0(n1237), .B1(n1601), .A0N(final_result_ieee[18]),
.A1N(n1598), .Y(n496) );
OAI2BB2XLTS U1696 ( .B0(n1231), .B1(n1601), .A0N(final_result_ieee[19]),
.A1N(n1598), .Y(n494) );
AOI22X1TS U1697 ( .A0(Data_array_SWR[12]), .A1(n897), .B0(Data_array_SWR[16]), .B1(n895), .Y(n1120) );
AOI22X1TS U1698 ( .A0(Data_array_SWR[24]), .A1(n1118), .B0(
Data_array_SWR[20]), .B1(n893), .Y(n1119) );
NAND2X1TS U1699 ( .A(n1120), .B(n1119), .Y(n1199) );
OAI222X4TS U1700 ( .A0(n1701), .A1(n1123), .B0(n1702), .B1(n1122), .C0(n1703), .C1(n1121), .Y(n1222) );
OAI2BB2XLTS U1701 ( .B0(n1229), .B1(n1601), .A0N(final_result_ieee[15]),
.A1N(n1598), .Y(n502) );
AOI21X1TS U1702 ( .A0(n908), .A1(Raw_mant_NRM_SWR[0]), .B0(n918), .Y(n1520)
);
OAI2BB2XLTS U1703 ( .B0(n1520), .B1(n914), .A0N(n1125), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI32X1TS U1704 ( .A0(n874), .A1(Raw_mant_NRM_SWR[14]), .A2(n1128), .B0(
n1127), .B1(n905), .Y(n1132) );
INVX2TS U1705 ( .A(n1213), .Y(n1485) );
AOI222X1TS U1706 ( .A0(Data_array_SWR[21]), .A1(n896), .B0(
Data_array_SWR[17]), .B1(n1086), .C0(Data_array_SWR[25]), .C1(n894),
.Y(n1393) );
AOI222X1TS U1707 ( .A0(Data_array_SWR[24]), .A1(n894), .B0(
Data_array_SWR[20]), .B1(n896), .C0(Data_array_SWR[16]), .C1(n1086),
.Y(n1394) );
AOI22X1TS U1708 ( .A0(Data_array_SWR[12]), .A1(n900), .B0(Data_array_SWR[13]), .B1(n899), .Y(n1135) );
AOI22X1TS U1709 ( .A0(Data_array_SWR[22]), .A1(n899), .B0(n912), .B1(n1136),
.Y(n1221) );
OAI2BB2XLTS U1710 ( .B0(n1221), .B1(n919), .A0N(final_result_ieee[20]),
.A1N(n1589), .Y(n491) );
AOI22X1TS U1711 ( .A0(Data_array_SWR[23]), .A1(n899), .B0(left_right_SHT2),
.B1(n1137), .Y(n1219) );
OAI2BB2XLTS U1712 ( .B0(n1219), .B1(n919), .A0N(final_result_ieee[21]),
.A1N(n1589), .Y(n490) );
AOI22X1TS U1713 ( .A0(Data_array_SWR[23]), .A1(n896), .B0(Data_array_SWR[19]), .B1(n1086), .Y(n1399) );
AOI22X1TS U1714 ( .A0(Data_array_SWR[10]), .A1(n900), .B0(Data_array_SWR[15]), .B1(n899), .Y(n1138) );
BUFX3TS U1715 ( .A(n1722), .Y(n1724) );
BUFX3TS U1716 ( .A(n1718), .Y(n1725) );
BUFX3TS U1717 ( .A(n1719), .Y(n1726) );
BUFX3TS U1718 ( .A(n1139), .Y(n1727) );
BUFX3TS U1719 ( .A(n1718), .Y(n1729) );
BUFX3TS U1720 ( .A(n1719), .Y(n1730) );
BUFX3TS U1721 ( .A(n1141), .Y(n1731) );
BUFX3TS U1722 ( .A(n1720), .Y(n1732) );
CLKBUFX2TS U1723 ( .A(n1139), .Y(n1142) );
BUFX3TS U1724 ( .A(n1719), .Y(n1716) );
BUFX3TS U1725 ( .A(n1718), .Y(n1717) );
BUFX3TS U1726 ( .A(n1139), .Y(n1718) );
BUFX3TS U1727 ( .A(n1139), .Y(n1719) );
BUFX3TS U1728 ( .A(n1139), .Y(n1720) );
BUFX3TS U1729 ( .A(n1141), .Y(n1721) );
BUFX3TS U1730 ( .A(n1139), .Y(n1722) );
BUFX3TS U1731 ( .A(n1720), .Y(n1723) );
BUFX3TS U1732 ( .A(n1140), .Y(n1746) );
BUFX3TS U1733 ( .A(n1722), .Y(n1715) );
BUFX3TS U1734 ( .A(n1720), .Y(n1743) );
BUFX3TS U1735 ( .A(n1144), .Y(n1709) );
BUFX3TS U1736 ( .A(n1722), .Y(n1710) );
BUFX3TS U1737 ( .A(n1144), .Y(n1745) );
BUFX3TS U1738 ( .A(n1718), .Y(n1712) );
BUFX3TS U1739 ( .A(n1722), .Y(n1714) );
BUFX3TS U1740 ( .A(n1722), .Y(n1742) );
BUFX3TS U1741 ( .A(n1144), .Y(n1734) );
BUFX3TS U1742 ( .A(n1719), .Y(n1738) );
BUFX3TS U1743 ( .A(n1143), .Y(n1739) );
BUFX3TS U1744 ( .A(n1140), .Y(n1737) );
BUFX3TS U1745 ( .A(n1144), .Y(n1728) );
BUFX3TS U1746 ( .A(n1719), .Y(n1707) );
BUFX3TS U1747 ( .A(n1143), .Y(n1736) );
BUFX3TS U1748 ( .A(n1143), .Y(n1711) );
BUFX3TS U1749 ( .A(n1140), .Y(n1741) );
BUFX3TS U1750 ( .A(n1142), .Y(n1740) );
BUFX3TS U1751 ( .A(n1720), .Y(n1735) );
BUFX3TS U1752 ( .A(n1143), .Y(n1744) );
BUFX3TS U1753 ( .A(n1720), .Y(n1713) );
BUFX3TS U1754 ( .A(n1718), .Y(n1733) );
BUFX3TS U1755 ( .A(n1144), .Y(n1708) );
CLKBUFX2TS U1756 ( .A(n1695), .Y(n1570) );
INVX2TS U1757 ( .A(n1570), .Y(n1551) );
NAND2X1TS U1758 ( .A(DmP_EXP_EWSW[25]), .B(n924), .Y(n1543) );
NOR2X1TS U1759 ( .A(n885), .B(DMP_EXP_EWSW[24]), .Y(n1539) );
OAI22X1TS U1760 ( .A0(n1541), .A1(n1539), .B0(DmP_EXP_EWSW[24]), .B1(n1629),
.Y(n1545) );
AOI22X1TS U1761 ( .A0(DMP_EXP_EWSW[25]), .A1(n1688), .B0(n1543), .B1(n1545),
.Y(n1147) );
NOR2X1TS U1762 ( .A(n887), .B(DMP_EXP_EWSW[26]), .Y(n1148) );
AOI21X1TS U1763 ( .A0(DMP_EXP_EWSW[26]), .A1(n887), .B0(n1148), .Y(n1145) );
XNOR2X1TS U1764 ( .A(n1147), .B(n1145), .Y(n1146) );
OAI22X1TS U1765 ( .A0(n1148), .A1(n1147), .B0(DmP_EXP_EWSW[26]), .B1(n1631),
.Y(n1150) );
XNOR2X1TS U1766 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1149) );
XOR2X1TS U1767 ( .A(n1150), .B(n1149), .Y(n1151) );
OAI22X1TS U1768 ( .A0(n1752), .A1(intDX_EWSW[1]), .B0(n1657), .B1(
intDX_EWSW[25]), .Y(n1152) );
AOI221X1TS U1769 ( .A0(n1752), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1657), .C0(n1152), .Y(n1158) );
AOI221X1TS U1770 ( .A0(n1670), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1674), .C0(n1153), .Y(n1157) );
OAI22X1TS U1771 ( .A0(n1671), .A1(intDX_EWSW[28]), .B0(n1627), .B1(
intDX_EWSW[29]), .Y(n1154) );
AOI221X1TS U1772 ( .A0(n1671), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1627), .C0(n1154), .Y(n1156) );
OAI22X1TS U1773 ( .A0(n1673), .A1(intDX_EWSW[30]), .B0(n1659), .B1(
intDX_EWSW[17]), .Y(n1159) );
OAI22X1TS U1774 ( .A0(n1669), .A1(intDX_EWSW[20]), .B0(n1662), .B1(
intDX_EWSW[21]), .Y(n1161) );
OAI22X1TS U1775 ( .A0(n1626), .A1(intDX_EWSW[22]), .B0(n1672), .B1(
intDX_EWSW[23]), .Y(n1162) );
OAI22X1TS U1776 ( .A0(n1616), .A1(intDX_EWSW[24]), .B0(n1660), .B1(
intDX_EWSW[9]), .Y(n1167) );
AOI221X1TS U1777 ( .A0(n1616), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1660), .C0(n1167), .Y(n1174) );
OAI22X1TS U1778 ( .A0(n1666), .A1(intDX_EWSW[12]), .B0(n1661), .B1(
intDX_EWSW[13]), .Y(n1169) );
OAI22X1TS U1779 ( .A0(n1667), .A1(intDX_EWSW[14]), .B0(n1625), .B1(
intDX_EWSW[15]), .Y(n1170) );
OAI22X1TS U1780 ( .A0(n1668), .A1(intDX_EWSW[16]), .B0(n1624), .B1(
intDX_EWSW[0]), .Y(n1175) );
AOI221X1TS U1781 ( .A0(n1668), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1624), .C0(n1175), .Y(n1182) );
OAI22X1TS U1782 ( .A0(n1664), .A1(intDX_EWSW[2]), .B0(n1658), .B1(
intDX_EWSW[3]), .Y(n1176) );
OAI22X1TS U1783 ( .A0(n1665), .A1(intDX_EWSW[4]), .B0(n1623), .B1(
intDX_EWSW[5]), .Y(n1177) );
AOI221X1TS U1784 ( .A0(n1665), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1623), .C0(n1177), .Y(n1180) );
OAI22X1TS U1785 ( .A0(n1663), .A1(intDX_EWSW[8]), .B0(n1648), .B1(
intDX_EWSW[6]), .Y(n1178) );
AOI221X1TS U1786 ( .A0(n1663), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1648), .C0(n1178), .Y(n1179) );
NOR4X1TS U1787 ( .A(n1186), .B(n1185), .C(n1184), .D(n1183), .Y(n1272) );
CLKXOR2X2TS U1788 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1267) );
AOI21X1TS U1789 ( .A0(n1267), .A1(intDX_EWSW[31]), .B0(n1187), .Y(n1548) );
NAND2X1TS U1790 ( .A(n1480), .B(DmP_mant_SFG_SWR[2]), .Y(n1188) );
OAI21X1TS U1791 ( .A0(n1480), .A1(DmP_mant_SFG_SWR[2]), .B0(n1188), .Y(n1576) );
NOR2X2TS U1792 ( .A(n1576), .B(n878), .Y(n1579) );
NOR2BX1TS U1793 ( .AN(n1652), .B(n1480), .Y(n1189) );
AOI21X1TS U1794 ( .A0(n1480), .A1(DmP_mant_SFG_SWR[3]), .B0(n1189), .Y(n1578) );
INVX2TS U1795 ( .A(n1191), .Y(n1193) );
CLKBUFX2TS U1796 ( .A(n1751), .Y(n1600) );
NAND2X1TS U1797 ( .A(n1501), .B(final_result_ieee[23]), .Y(n1192) );
INVX2TS U1798 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1195) );
NAND2X1TS U1799 ( .A(n1501), .B(final_result_ieee[24]), .Y(n1194) );
AOI21X1TS U1800 ( .A0(n1202), .A1(n1409), .B0(n1197), .Y(n1593) );
NOR2X4TS U1801 ( .A(n886), .B(Shift_reg_FLAGS_7[0]), .Y(n1557) );
NAND2X1TS U1802 ( .A(n1238), .B(DmP_mant_SFG_SWR[9]), .Y(n1198) );
AOI21X1TS U1803 ( .A0(n1222), .A1(n1409), .B0(n1200), .Y(n1594) );
NAND2X1TS U1804 ( .A(n1238), .B(DmP_mant_SFG_SWR[8]), .Y(n1201) );
INVX2TS U1805 ( .A(n1202), .Y(n1205) );
AOI22X1TS U1806 ( .A0(Data_array_SWR[12]), .A1(n894), .B0(Data_array_SWR[8]),
.B1(n896), .Y(n1204) );
AOI22X1TS U1807 ( .A0(Data_array_SWR[4]), .A1(n1086), .B0(Data_array_SWR[0]),
.B1(n1223), .Y(n1203) );
OAI211X1TS U1808 ( .A0(n1205), .A1(n879), .B0(n1204), .C0(n1203), .Y(n1603)
);
AOI22X1TS U1809 ( .A0(Data_array_SWR[25]), .A1(n899), .B0(n912), .B1(n1603),
.Y(n1207) );
NAND2X1TS U1810 ( .A(n1238), .B(DmP_mant_SFG_SWR[25]), .Y(n1206) );
OAI22X1TS U1811 ( .A0(n1211), .A1(n1210), .B0(n1209), .B1(n1208), .Y(n1216)
);
OAI31X1TS U1812 ( .A0(n1216), .A1(n1215), .A2(n1214), .B0(n904), .Y(n1483)
);
NAND2X1TS U1813 ( .A(n1238), .B(DmP_mant_SFG_SWR[23]), .Y(n1218) );
NAND2X1TS U1814 ( .A(n1241), .B(DmP_mant_SFG_SWR[22]), .Y(n1220) );
INVX2TS U1815 ( .A(n1222), .Y(n1226) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[13]), .A1(n894), .B0(Data_array_SWR[9]),
.B1(n895), .Y(n1225) );
AOI22X1TS U1817 ( .A0(Data_array_SWR[5]), .A1(n897), .B0(Data_array_SWR[1]),
.B1(n1223), .Y(n1224) );
OAI211X1TS U1818 ( .A0(n1226), .A1(n879), .B0(n1225), .C0(n1224), .Y(n1605)
);
AOI22X1TS U1819 ( .A0(Data_array_SWR[24]), .A1(n899), .B0(left_right_SHT2),
.B1(n1605), .Y(n1602) );
NAND2X1TS U1820 ( .A(n1241), .B(DmP_mant_SFG_SWR[24]), .Y(n1227) );
NAND2X1TS U1821 ( .A(n1238), .B(DmP_mant_SFG_SWR[17]), .Y(n1228) );
NAND2X1TS U1822 ( .A(n1238), .B(DmP_mant_SFG_SWR[21]), .Y(n1230) );
NAND2X1TS U1823 ( .A(n1238), .B(DmP_mant_SFG_SWR[19]), .Y(n1232) );
NAND2X1TS U1824 ( .A(n1238), .B(DmP_mant_SFG_SWR[16]), .Y(n1234) );
NAND2X1TS U1825 ( .A(n1238), .B(DmP_mant_SFG_SWR[20]), .Y(n1236) );
NAND2X1TS U1826 ( .A(n1238), .B(DmP_mant_SFG_SWR[18]), .Y(n1239) );
BUFX3TS U1827 ( .A(n1273), .Y(n1499) );
AOI22X1TS U1828 ( .A0(intDX_EWSW[17]), .A1(n1320), .B0(DmP_EXP_EWSW[17]),
.B1(n1499), .Y(n1242) );
AOI22X1TS U1829 ( .A0(intDX_EWSW[0]), .A1(n1320), .B0(DmP_EXP_EWSW[0]), .B1(
n1244), .Y(n1243) );
BUFX3TS U1830 ( .A(n1244), .Y(n1263) );
AOI22X1TS U1831 ( .A0(intDX_EWSW[16]), .A1(n1320), .B0(DmP_EXP_EWSW[16]),
.B1(n1263), .Y(n1245) );
BUFX3TS U1832 ( .A(n1246), .Y(n1323) );
AOI22X1TS U1833 ( .A0(intDX_EWSW[6]), .A1(n1323), .B0(DmP_EXP_EWSW[6]), .B1(
n1244), .Y(n1247) );
AOI22X1TS U1834 ( .A0(intDX_EWSW[5]), .A1(n1323), .B0(DmP_EXP_EWSW[5]), .B1(
n1263), .Y(n1248) );
AOI22X1TS U1835 ( .A0(intDX_EWSW[4]), .A1(n1323), .B0(DmP_EXP_EWSW[4]), .B1(
n1244), .Y(n1249) );
AOI22X1TS U1836 ( .A0(intDX_EWSW[2]), .A1(n1323), .B0(DmP_EXP_EWSW[2]), .B1(
n1273), .Y(n1250) );
AOI22X1TS U1837 ( .A0(intDX_EWSW[1]), .A1(n1323), .B0(DmP_EXP_EWSW[1]), .B1(
n929), .Y(n1251) );
AOI22X1TS U1838 ( .A0(intDX_EWSW[3]), .A1(n1323), .B0(DmP_EXP_EWSW[3]), .B1(
n929), .Y(n1252) );
AOI22X1TS U1839 ( .A0(DmP_EXP_EWSW[27]), .A1(n1499), .B0(intDX_EWSW[27]),
.B1(n1323), .Y(n1253) );
AOI22X1TS U1840 ( .A0(intDX_EWSW[7]), .A1(n1246), .B0(DmP_EXP_EWSW[7]), .B1(
n1263), .Y(n1254) );
AOI22X1TS U1841 ( .A0(intDX_EWSW[18]), .A1(n1246), .B0(DmP_EXP_EWSW[18]),
.B1(n1263), .Y(n1255) );
AOI22X1TS U1842 ( .A0(intDX_EWSW[10]), .A1(n1246), .B0(DmP_EXP_EWSW[10]),
.B1(n1549), .Y(n1256) );
AOI22X1TS U1843 ( .A0(intDX_EWSW[14]), .A1(n1246), .B0(DmP_EXP_EWSW[14]),
.B1(n1263), .Y(n1257) );
AOI22X1TS U1844 ( .A0(intDX_EWSW[11]), .A1(n1246), .B0(DmP_EXP_EWSW[11]),
.B1(n1263), .Y(n1258) );
AOI22X1TS U1845 ( .A0(intDX_EWSW[12]), .A1(n1246), .B0(DmP_EXP_EWSW[12]),
.B1(n1263), .Y(n1259) );
AOI22X1TS U1846 ( .A0(intDX_EWSW[8]), .A1(n1320), .B0(DmP_EXP_EWSW[8]), .B1(
n1263), .Y(n1260) );
AOI22X1TS U1847 ( .A0(intDX_EWSW[9]), .A1(n1246), .B0(DmP_EXP_EWSW[9]), .B1(
n1263), .Y(n1261) );
AOI22X1TS U1848 ( .A0(intDX_EWSW[13]), .A1(n1323), .B0(DmP_EXP_EWSW[13]),
.B1(n1263), .Y(n1264) );
AOI22X1TS U1849 ( .A0(intDX_EWSW[15]), .A1(n1323), .B0(DmP_EXP_EWSW[15]),
.B1(n1499), .Y(n1265) );
INVX2TS U1850 ( .A(n1267), .Y(n1271) );
AOI22X1TS U1851 ( .A0(intDX_EWSW[31]), .A1(n1269), .B0(SIGN_FLAG_EXP), .B1(
n1244), .Y(n1270) );
BUFX3TS U1852 ( .A(n1273), .Y(n1313) );
AOI22X1TS U1853 ( .A0(intDX_EWSW[28]), .A1(n1316), .B0(DMP_EXP_EWSW[28]),
.B1(n1313), .Y(n1274) );
AOI22X1TS U1854 ( .A0(n1376), .A1(Raw_mant_NRM_SWR[24]), .B0(n1373), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1279) );
AOI22X1TS U1855 ( .A0(n873), .A1(Raw_mant_NRM_SWR[21]), .B0(n1081), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1276) );
AOI22X1TS U1856 ( .A0(n908), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[1]), .B1(n917), .Y(n1275) );
NAND2X1TS U1857 ( .A(n1276), .B(n1275), .Y(n1338) );
AOI22X1TS U1858 ( .A0(n1358), .A1(Data_array_SWR[1]), .B0(n1327), .B1(n1338),
.Y(n1278) );
NAND2X1TS U1859 ( .A(n1377), .B(Raw_mant_NRM_SWR[23]), .Y(n1277) );
AOI22X1TS U1860 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n873), .B0(n1081), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1281) );
AOI22X1TS U1861 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n908), .B0(n916), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1280) );
NAND2X1TS U1862 ( .A(n1281), .B(n1280), .Y(n1342) );
AOI22X1TS U1863 ( .A0(n1358), .A1(Data_array_SWR[4]), .B0(n1327), .B1(n1342),
.Y(n1283) );
NAND2X1TS U1864 ( .A(Raw_mant_NRM_SWR[20]), .B(n1377), .Y(n1282) );
AOI22X1TS U1865 ( .A0(intDX_EWSW[1]), .A1(n1306), .B0(DMP_EXP_EWSW[1]), .B1(
n1549), .Y(n1284) );
AOI22X1TS U1866 ( .A0(intDX_EWSW[6]), .A1(n1306), .B0(DMP_EXP_EWSW[6]), .B1(
n1305), .Y(n1285) );
AOI22X1TS U1867 ( .A0(intDX_EWSW[2]), .A1(n1306), .B0(DMP_EXP_EWSW[2]), .B1(
n1549), .Y(n1286) );
AOI22X1TS U1868 ( .A0(intDX_EWSW[5]), .A1(n1306), .B0(DMP_EXP_EWSW[5]), .B1(
n1305), .Y(n1287) );
AOI22X1TS U1869 ( .A0(intDX_EWSW[4]), .A1(n1293), .B0(DMP_EXP_EWSW[4]), .B1(
n1305), .Y(n1288) );
AOI22X1TS U1870 ( .A0(intDX_EWSW[29]), .A1(n1316), .B0(DMP_EXP_EWSW[29]),
.B1(n1273), .Y(n1290) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[18]), .A1(n1293), .B0(DMP_EXP_EWSW[18]),
.B1(n1313), .Y(n1292) );
CLKBUFX2TS U1872 ( .A(n1293), .Y(n1322) );
AOI22X1TS U1873 ( .A0(DMP_EXP_EWSW[27]), .A1(n1499), .B0(intDX_EWSW[27]),
.B1(n1322), .Y(n1294) );
AOI22X1TS U1874 ( .A0(intDX_EWSW[30]), .A1(n1316), .B0(DMP_EXP_EWSW[30]),
.B1(n1273), .Y(n1295) );
AOI22X1TS U1875 ( .A0(DMP_EXP_EWSW[23]), .A1(n1499), .B0(intDX_EWSW[23]),
.B1(n1306), .Y(n1296) );
AOI22X1TS U1876 ( .A0(intDX_EWSW[14]), .A1(n1316), .B0(DMP_EXP_EWSW[14]),
.B1(n1313), .Y(n1297) );
AOI22X1TS U1877 ( .A0(intDX_EWSW[12]), .A1(n1316), .B0(DMP_EXP_EWSW[12]),
.B1(n1305), .Y(n1298) );
AOI22X1TS U1878 ( .A0(intDX_EWSW[11]), .A1(n1322), .B0(DMP_EXP_EWSW[11]),
.B1(n1313), .Y(n1299) );
AOI22X1TS U1879 ( .A0(intDX_EWSW[8]), .A1(n1306), .B0(DMP_EXP_EWSW[8]), .B1(
n1305), .Y(n1300) );
AOI22X1TS U1880 ( .A0(intDX_EWSW[17]), .A1(n1293), .B0(DMP_EXP_EWSW[17]),
.B1(n1313), .Y(n1301) );
AOI22X1TS U1881 ( .A0(intDX_EWSW[7]), .A1(n1306), .B0(DMP_EXP_EWSW[7]), .B1(
n1305), .Y(n1302) );
AOI22X1TS U1882 ( .A0(intDX_EWSW[10]), .A1(n1306), .B0(DMP_EXP_EWSW[10]),
.B1(n1305), .Y(n1303) );
AOI22X1TS U1883 ( .A0(intDX_EWSW[16]), .A1(n1293), .B0(DMP_EXP_EWSW[16]),
.B1(n1313), .Y(n1304) );
AOI22X1TS U1884 ( .A0(intDX_EWSW[9]), .A1(n1306), .B0(DMP_EXP_EWSW[9]), .B1(
n1305), .Y(n1307) );
AOI22X1TS U1885 ( .A0(intDX_EWSW[19]), .A1(n1322), .B0(DMP_EXP_EWSW[19]),
.B1(n1313), .Y(n1309) );
AOI22X1TS U1886 ( .A0(intDX_EWSW[0]), .A1(n1316), .B0(DMP_EXP_EWSW[0]), .B1(
n1549), .Y(n1310) );
AOI22X1TS U1887 ( .A0(intDX_EWSW[22]), .A1(n1316), .B0(DMP_EXP_EWSW[22]),
.B1(n1313), .Y(n1311) );
AOI22X1TS U1888 ( .A0(intDX_EWSW[20]), .A1(n1316), .B0(DMP_EXP_EWSW[20]),
.B1(n1313), .Y(n1312) );
AOI22X1TS U1889 ( .A0(intDX_EWSW[21]), .A1(n1316), .B0(DMP_EXP_EWSW[21]),
.B1(n1313), .Y(n1314) );
AOI22X1TS U1890 ( .A0(intDX_EWSW[20]), .A1(n1320), .B0(DmP_EXP_EWSW[20]),
.B1(n1499), .Y(n1317) );
AOI22X1TS U1891 ( .A0(intDX_EWSW[22]), .A1(n1320), .B0(DmP_EXP_EWSW[22]),
.B1(n1499), .Y(n1318) );
AOI22X1TS U1892 ( .A0(intDX_EWSW[21]), .A1(n1320), .B0(DmP_EXP_EWSW[21]),
.B1(n1499), .Y(n1319) );
AOI22X1TS U1893 ( .A0(intDX_EWSW[19]), .A1(n1320), .B0(DmP_EXP_EWSW[19]),
.B1(n1499), .Y(n1321) );
AOI222X1TS U1894 ( .A0(n1323), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1549), .C0(intDY_EWSW[23]), .C1(n1322), .Y(n1324) );
INVX2TS U1895 ( .A(n1324), .Y(n564) );
AOI22X1TS U1896 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n873), .B0(n1081), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1326) );
AOI22X1TS U1897 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n908), .B0(n916), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1325) );
NAND2X1TS U1898 ( .A(n1326), .B(n1325), .Y(n1345) );
AOI22X1TS U1899 ( .A0(n1358), .A1(Data_array_SWR[5]), .B0(n1327), .B1(n1345),
.Y(n1329) );
NAND2X1TS U1900 ( .A(Raw_mant_NRM_SWR[19]), .B(n1377), .Y(n1328) );
OAI22X1TS U1901 ( .A0(n1690), .A1(n1528), .B0(n1621), .B1(n888), .Y(n1330)
);
OAI22X1TS U1902 ( .A0(n1519), .A1(n907), .B0(n1331), .B1(n913), .Y(n1332) );
AOI21X1TS U1903 ( .A0(n1125), .A1(Data_array_SWR[22]), .B0(n1332), .Y(n1333)
);
AOI22X1TS U1904 ( .A0(n1358), .A1(Data_array_SWR[2]), .B0(n876), .B1(n1334),
.Y(n1336) );
NAND2X1TS U1905 ( .A(Raw_mant_NRM_SWR[20]), .B(n890), .Y(n1335) );
AOI22X1TS U1906 ( .A0(n1358), .A1(Data_array_SWR[3]), .B0(n876), .B1(n1338),
.Y(n1340) );
NAND2X1TS U1907 ( .A(Raw_mant_NRM_SWR[19]), .B(n890), .Y(n1339) );
AOI22X1TS U1908 ( .A0(n1383), .A1(Data_array_SWR[6]), .B0(n876), .B1(n1342),
.Y(n1344) );
NAND2X1TS U1909 ( .A(Raw_mant_NRM_SWR[16]), .B(n890), .Y(n1343) );
AOI22X1TS U1910 ( .A0(n1358), .A1(Data_array_SWR[7]), .B0(n876), .B1(n1345),
.Y(n1347) );
NAND2X1TS U1911 ( .A(Raw_mant_NRM_SWR[15]), .B(n890), .Y(n1346) );
AOI22X1TS U1912 ( .A0(n1358), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1363), .Y(n1349) );
AOI22X1TS U1913 ( .A0(n1383), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n890), .Y(n1352) );
OA22X1TS U1914 ( .A0(n1638), .A1(n1080), .B0(n1370), .B1(n907), .Y(n1351) );
OAI211X1TS U1915 ( .A0(n1364), .A1(n915), .B0(n1352), .C0(n1351), .Y(n790)
);
AOI22X1TS U1916 ( .A0(n1383), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n890), .Y(n1354) );
OA22X1TS U1917 ( .A0(n1677), .A1(n1080), .B0(n1367), .B1(n906), .Y(n1353) );
AOI22X1TS U1918 ( .A0(n1383), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1363), .Y(n1357) );
OA22X1TS U1919 ( .A0(n1620), .A1(n1080), .B0(n1355), .B1(n906), .Y(n1356) );
AOI22X1TS U1920 ( .A0(n1358), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1363), .Y(n1361) );
OA22X1TS U1921 ( .A0(n1684), .A1(n1080), .B0(n1359), .B1(n906), .Y(n1360) );
AOI22X1TS U1922 ( .A0(n1383), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n890), .Y(n1366) );
OA22X1TS U1923 ( .A0(n1642), .A1(n1080), .B0(n1364), .B1(n906), .Y(n1365) );
AOI22X1TS U1924 ( .A0(n916), .A1(DmP_mant_SHT1_SW[21]), .B0(n1081), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1368) );
AOI21X1TS U1925 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1376), .B0(n1369), .Y(n1521) );
OAI22X1TS U1926 ( .A0(n1370), .A1(n913), .B0(n1678), .B1(n1080), .Y(n1371)
);
AOI21X1TS U1927 ( .A0(n1125), .A1(Data_array_SWR[21]), .B0(n1371), .Y(n1372)
);
AOI22X1TS U1928 ( .A0(n916), .A1(DmP_mant_SHT1_SW[8]), .B0(n1373), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1374) );
AOI21X1TS U1929 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n909), .B0(n1375), .Y(n1532) );
OAI2BB2XLTS U1930 ( .B0(n1378), .B1(n913), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n1377), .Y(n1379) );
AOI21X1TS U1931 ( .A0(n1383), .A1(Data_array_SWR[8]), .B0(n1379), .Y(n1380)
);
OAI22X1TS U1932 ( .A0(n1381), .A1(n913), .B0(n1689), .B1(n1080), .Y(n1382)
);
AOI21X1TS U1933 ( .A0(n1383), .A1(Data_array_SWR[18]), .B0(n1382), .Y(n1384)
);
OAI2BB2XLTS U1934 ( .B0(n1386), .B1(n1495), .A0N(final_result_ieee[31]),
.A1N(n1501), .Y(n543) );
BUFX3TS U1935 ( .A(n1747), .Y(n1584) );
AOI32X4TS U1936 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1387), .B1(n1650), .Y(n1502)
);
MXI2X1TS U1937 ( .A(n1584), .B(n886), .S0(n1502), .Y(n865) );
BUFX3TS U1938 ( .A(n1557), .Y(n1558) );
BUFX3TS U1939 ( .A(n1557), .Y(n1614) );
BUFX3TS U1940 ( .A(n1557), .Y(n1550) );
AOI22X1TS U1941 ( .A0(Data_array_SWR[22]), .A1(n896), .B0(Data_array_SWR[18]), .B1(n1086), .Y(n1396) );
AOI22X1TS U1942 ( .A0(Data_array_SWR[14]), .A1(n898), .B0(Data_array_SWR[11]), .B1(n900), .Y(n1390) );
AOI22X1TS U1943 ( .A0(Data_array_SWR[12]), .A1(n898), .B0(Data_array_SWR[13]), .B1(n900), .Y(n1392) );
AOI22X1TS U1944 ( .A0(Data_array_SWR[14]), .A1(n900), .B0(Data_array_SWR[11]), .B1(n899), .Y(n1395) );
AOI22X1TS U1945 ( .A0(Data_array_SWR[10]), .A1(n898), .B0(Data_array_SWR[15]), .B1(n900), .Y(n1398) );
OA21XLTS U1946 ( .A0(n1399), .A1(n875), .B0(n1398), .Y(n1400) );
OAI21X1TS U1947 ( .A0(left_right_SHT2), .A1(n1401), .B0(n1400), .Y(n1591) );
NAND2X1TS U1948 ( .A(n898), .B(Data_array_SWR[7]), .Y(n1404) );
NAND2BX1TS U1949 ( .AN(n912), .B(n1407), .Y(n1413) );
NAND2X1TS U1950 ( .A(n898), .B(Data_array_SWR[6]), .Y(n1411) );
AFHCONX2TS U1951 ( .A(DMP_SFG[21]), .B(n1419), .CI(n1418), .CON(n1421), .S(
n1420) );
AFHCONX2TS U1952 ( .A(DMP_SFG[19]), .B(n1425), .CI(n1424), .CON(n1415), .S(
n1426) );
AFHCINX2TS U1953 ( .CIN(n1427), .B(n1428), .A(DMP_SFG[18]), .S(n1429), .CO(
n1424) );
AOI21X1TS U1954 ( .A0(n1461), .A1(n1433), .B0(n1432), .Y(n1438) );
NAND2X1TS U1955 ( .A(n1436), .B(n1435), .Y(n1437) );
XOR2X1TS U1956 ( .A(n1438), .B(n1437), .Y(n1439) );
AOI21X1TS U1957 ( .A0(n1461), .A1(n1441), .B0(n1440), .Y(n1445) );
NAND2X1TS U1958 ( .A(n1443), .B(n1442), .Y(n1444) );
XOR2X1TS U1959 ( .A(n1445), .B(n1444), .Y(n1446) );
INVX2TS U1960 ( .A(n1447), .Y(n1459) );
INVX2TS U1961 ( .A(n1458), .Y(n1448) );
AOI21X1TS U1962 ( .A0(n1461), .A1(n1459), .B0(n1448), .Y(n1453) );
NAND2X1TS U1963 ( .A(n1451), .B(n1450), .Y(n1452) );
XOR2X1TS U1964 ( .A(n1453), .B(n1452), .Y(n1454) );
AFHCINX4TS U1965 ( .CIN(n1455), .B(n1456), .A(DMP_SFG[13]), .S(n1457), .CO(
n1461) );
NAND2X1TS U1966 ( .A(n1459), .B(n1458), .Y(n1460) );
XNOR2X1TS U1967 ( .A(n1461), .B(n1460), .Y(n1462) );
AFHCONX2TS U1968 ( .A(DMP_SFG[12]), .B(n1464), .CI(n1463), .CON(n1455), .S(
n1465) );
INVX4TS U1969 ( .A(n1584), .Y(n1482) );
AFHCONX2TS U1970 ( .A(DMP_SFG[10]), .B(n1474), .CI(n1473), .CON(n1466), .S(
n1475) );
AFHCONX2TS U1971 ( .A(DMP_SFG[8]), .B(n1477), .CI(n1476), .CON(n1470), .S(
n1478) );
MXI2X1TS U1972 ( .A(DmP_mant_SFG_SWR[5]), .B(n923), .S0(n1480), .Y(
intadd_65_B_1_) );
MXI2X1TS U1973 ( .A(DmP_mant_SFG_SWR[4]), .B(n922), .S0(n1480), .Y(
intadd_65_CI) );
MXI2X1TS U1974 ( .A(n1641), .B(intadd_65_SUM_4_), .S0(n1482), .Y(n534) );
MXI2X1TS U1975 ( .A(n1642), .B(intadd_65_SUM_3_), .S0(n1482), .Y(n535) );
MXI2X1TS U1976 ( .A(DmP_mant_SFG_SWR[1]), .B(n921), .S0(n1480), .Y(n1479) );
MXI2X1TS U1977 ( .A(n1690), .B(n1479), .S0(n1482), .Y(n541) );
MXI2X1TS U1978 ( .A(DmP_mant_SFG_SWR[0]), .B(n926), .S0(n1480), .Y(n1481) );
MXI2X1TS U1979 ( .A(n1621), .B(n1481), .S0(n1482), .Y(n542) );
MXI2X1TS U1980 ( .A(n1689), .B(intadd_65_SUM_2_), .S0(n1482), .Y(n536) );
MXI2X1TS U1981 ( .A(n1694), .B(intadd_65_SUM_0_), .S0(n1482), .Y(n538) );
MXI2X1TS U1982 ( .A(n1638), .B(intadd_65_SUM_1_), .S0(n1482), .Y(n537) );
OAI2BB1X1TS U1983 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n905), .B0(n1483), .Y(
n512) );
AOI22X1TS U1984 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1485), .B0(n1484), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1487) );
OAI21X1TS U1985 ( .A0(n1491), .A1(n1490), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1533) );
OAI2BB1X1TS U1986 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n905), .B0(n1533), .Y(
n514) );
OA21XLTS U1987 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1495),
.Y(n558) );
AOI22X1TS U1988 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1497), .B1(n1622), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1989 ( .A(n1497), .B(n1496), .Y(n871) );
INVX2TS U1990 ( .A(n1502), .Y(n1500) );
AOI22X1TS U1991 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1498), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1622), .Y(n1503) );
BUFX3TS U1992 ( .A(n1695), .Y(n1568) );
AOI22X1TS U1993 ( .A0(n1502), .A1(n1499), .B0(n1568), .B1(n1500), .Y(n868)
);
AOI22X1TS U1994 ( .A0(n1502), .A1(n1568), .B0(n1553), .B1(n1500), .Y(n867)
);
AOI22X1TS U1995 ( .A0(n1502), .A1(n1584), .B0(n902), .B1(n1500), .Y(n864) );
AOI22X1TS U1996 ( .A0(n1502), .A1(n902), .B0(n1501), .B1(n1500), .Y(n863) );
INVX2TS U1997 ( .A(n1508), .Y(n1504) );
BUFX3TS U1998 ( .A(n1508), .Y(n1514) );
INVX2TS U1999 ( .A(n1518), .Y(n1505) );
BUFX3TS U2000 ( .A(n1508), .Y(n1507) );
BUFX3TS U2001 ( .A(n1511), .Y(n1506) );
INVX2TS U2002 ( .A(n1518), .Y(n1517) );
INVX2TS U2003 ( .A(n1511), .Y(n1509) );
BUFX3TS U2004 ( .A(n1508), .Y(n1515) );
INVX2TS U2005 ( .A(n1511), .Y(n1510) );
BUFX3TS U2006 ( .A(n1508), .Y(n1513) );
INVX2TS U2007 ( .A(n1511), .Y(n1512) );
OAI2BB2XLTS U2008 ( .B0(n1519), .B1(n915), .A0N(n1125), .A1N(
Data_array_SWR[24]), .Y(n795) );
OAI222X1TS U2009 ( .A0(n1683), .A1(n1535), .B0(n914), .B1(n1521), .C0(n907),
.C1(n1520), .Y(n794) );
AOI22X1TS U2010 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n873), .B0(n1522), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1523) );
AOI21X1TS U2011 ( .A0(n918), .A1(DmP_mant_SHT1_SW[12]), .B0(n1524), .Y(n1530) );
OAI222X1TS U2012 ( .A0(n1535), .A1(n1686), .B0(n915), .B1(n1530), .C0(n906),
.C1(n1525), .Y(n785) );
AOI22X1TS U2013 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n873), .B0(n1373), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1527) );
AOI21X1TS U2014 ( .A0(n917), .A1(DmP_mant_SHT1_SW[10]), .B0(n1529), .Y(n1531) );
OAI222X1TS U2015 ( .A0(n1685), .A1(n1535), .B0(n914), .B1(n1531), .C0(n906),
.C1(n1530), .Y(n783) );
OAI222X1TS U2016 ( .A0(n1693), .A1(n1535), .B0(n914), .B1(n1532), .C0(n907),
.C1(n1531), .Y(n781) );
AOI32X1TS U2017 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1535), .A2(n905), .B0(
shift_value_SHT2_EWR[2]), .B1(n1125), .Y(n1534) );
NAND2X1TS U2018 ( .A(n1534), .B(n1533), .Y(n770) );
AOI21X1TS U2019 ( .A0(n1748), .A1(Shift_amount_SHT1_EWR[3]), .B0(n903), .Y(
n1536) );
OAI22X1TS U2020 ( .A0(n1537), .A1(n1536), .B0(n1535), .B1(n1633), .Y(n769)
);
INVX2TS U2021 ( .A(n1568), .Y(n1571) );
AOI21X1TS U2022 ( .A0(DMP_EXP_EWSW[23]), .A1(n925), .B0(n1541), .Y(n1538) );
INVX2TS U2023 ( .A(n1570), .Y(n1547) );
AOI21X1TS U2024 ( .A0(DMP_EXP_EWSW[24]), .A1(n885), .B0(n1539), .Y(n1540) );
XNOR2X1TS U2025 ( .A(n1541), .B(n1540), .Y(n1542) );
XNOR2X1TS U2026 ( .A(n1545), .B(n1544), .Y(n1546) );
OAI222X1TS U2027 ( .A0(n1564), .A1(n1687), .B0(n1629), .B1(n1565), .C0(n1616), .C1(n1566), .Y(n729) );
OAI222X1TS U2028 ( .A0(n1564), .A1(n1630), .B0(n924), .B1(n1565), .C0(n1657),
.C1(n1566), .Y(n728) );
OAI222X1TS U2029 ( .A0(n1564), .A1(n1692), .B0(n1631), .B1(n1565), .C0(n1670), .C1(n1566), .Y(n727) );
BUFX3TS U2030 ( .A(n1695), .Y(n1552) );
INVX2TS U2031 ( .A(n1570), .Y(n1554) );
BUFX3TS U2032 ( .A(n1695), .Y(n1555) );
INVX2TS U2033 ( .A(n1560), .Y(n1559) );
BUFX3TS U2034 ( .A(n1560), .Y(n1556) );
BUFX3TS U2035 ( .A(n1695), .Y(n1572) );
BUFX3TS U2036 ( .A(n1557), .Y(n1608) );
INVX2TS U2037 ( .A(n1558), .Y(n1573) );
INVX2TS U2038 ( .A(n1568), .Y(n1561) );
BUFX3TS U2039 ( .A(n1570), .Y(n1562) );
BUFX3TS U2040 ( .A(n1568), .Y(n1563) );
OAI222X1TS U2041 ( .A0(n1566), .A1(n1687), .B0(n885), .B1(n1565), .C0(n1616),
.C1(n1564), .Y(n563) );
OAI222X1TS U2042 ( .A0(n1566), .A1(n1630), .B0(n1688), .B1(n1565), .C0(n1657), .C1(n1564), .Y(n562) );
OAI222X1TS U2043 ( .A0(n1566), .A1(n1692), .B0(n887), .B1(n1565), .C0(n1670),
.C1(n1564), .Y(n561) );
OAI2BB1X1TS U2044 ( .A0N(underflow_flag), .A1N(n1600), .B0(n1567), .Y(n559)
);
AOI22X1TS U2045 ( .A0(n1586), .A1(n1577), .B0(n1634), .B1(n1584), .Y(n540)
);
XOR2X1TS U2046 ( .A(n1578), .B(DMP_SFG[1]), .Y(n1580) );
XNOR2X1TS U2047 ( .A(n1580), .B(n1579), .Y(n1581) );
AOI22X1TS U2048 ( .A0(n1586), .A1(n1581), .B0(n1678), .B1(n1584), .Y(n539)
);
XNOR2X1TS U2049 ( .A(n1582), .B(DMP_SFG[7]), .Y(n1583) );
XNOR2X1TS U2050 ( .A(intadd_65_n1), .B(n1583), .Y(n1585) );
AOI22X1TS U2051 ( .A0(n1586), .A1(n1585), .B0(n1677), .B1(n1584), .Y(n533)
);
OAI2BB2XLTS U2052 ( .B0(n1593), .B1(n919), .A0N(final_result_ieee[7]), .A1N(
n1751), .Y(n505) );
OAI2BB2XLTS U2053 ( .B0(n1594), .B1(n919), .A0N(final_result_ieee[6]), .A1N(
n1751), .Y(n503) );
INVX2TS U2054 ( .A(n1595), .Y(n1596) );
OAI2BB2XLTS U2055 ( .B0(n1596), .B1(n919), .A0N(final_result_ieee[5]), .A1N(
n1598), .Y(n501) );
INVX2TS U2056 ( .A(n1597), .Y(n1599) );
OAI2BB2XLTS U2057 ( .B0(n1599), .B1(n919), .A0N(final_result_ieee[4]), .A1N(
n1598), .Y(n499) );
OAI2BB2XLTS U2058 ( .B0(n1602), .B1(n919), .A0N(final_result_ieee[22]),
.A1N(n1600), .Y(n489) );
AOI22X1TS U2059 ( .A0(Data_array_SWR[25]), .A1(n901), .B0(n910), .B1(n1603),
.Y(n1604) );
AOI22X1TS U2060 ( .A0(n1614), .A1(n1604), .B0(n926), .B1(n1612), .Y(n488) );
AOI22X1TS U2061 ( .A0(Data_array_SWR[24]), .A1(n901), .B0(n1606), .B1(n1605),
.Y(n1607) );
AOI22X1TS U2062 ( .A0(n1608), .A1(n1607), .B0(n921), .B1(n1612), .Y(n487) );
AOI22X1TS U2063 ( .A0(n1614), .A1(n1609), .B0(n1651), .B1(n1612), .Y(n486)
);
AOI22X1TS U2064 ( .A0(n1614), .A1(n1610), .B0(n1652), .B1(n1612), .Y(n485)
);
AOI22X1TS U2065 ( .A0(n1614), .A1(n1611), .B0(n922), .B1(n1612), .Y(n484) );
AOI22X1TS U2066 ( .A0(n1614), .A1(n1613), .B0(n923), .B1(n1612), .Y(n483) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_GeArN16R6P4_syn.sdf");
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=10,PIXEL0_INDEX=63,PIXEL1_INDEX=511,PIXEL2_INDEX=1000,PIXEL0_FREQUENCY0=5000,PIXEL0_FREQUENCY1=10000,PIXEL1_FREQUENCY0=15000,PIXEL1_FREQUENCY1=20000,PIXEL2_FREQUENCY0=40000,PIXEL2_FREQ\
UENCY1=50000,FREQUENCY_DEVIATION=20,CLOCK_FREQUENCY=100000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [9 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [9 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(10),
.PIXEL0_INDEX(63),
.PIXEL1_INDEX(511),
.PIXEL2_INDEX(1000),
.PIXEL0_FREQUENCY0(5000),
.PIXEL0_FREQUENCY1(10000),
.PIXEL1_FREQUENCY0(15000),
.PIXEL1_FREQUENCY1(20000),
.PIXEL2_FREQUENCY0(40000),
.PIXEL2_FREQUENCY1(50000),
.FREQUENCY_DEVIATION(20),
.CLOCK_FREQUENCY(100000000)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Implements the "identity" (often abbreviated as ident) function for 8-bit
// inputs. That is, buffers up four bytes and then sends them back.
`include "xls/uncore_rtl/ice40/uart_receiver.v"
`include "xls/uncore_rtl/ice40/uart_transmitter.v"
module top(
input wire clk,
input wire rx_in,
output wire tx_out,
output wire clear_to_send_out_n
);
parameter ClocksPerBaud = `DEFAULT_CLOCKS_PER_BAUD;
localparam
StateIdle = 2'd0,
StateGotByte = 2'd1,
StateError = 2'd2;
localparam StateBits = 2;
wire rst_n;
assign rst_n = 1;
reg rx_byte_done = 0;
reg rx_byte_done_next;
reg [StateBits-1:0] state = StateIdle;
reg [StateBits-1:0] state_next;
reg [7:0] tx_byte = 8'hff;
reg [7:0] tx_byte_next;
reg tx_byte_valid = 0;
reg tx_byte_valid_next;
wire tx_byte_done;
wire [7:0] rx_byte;
wire rx_byte_valid;
wire clear_to_send;
assign clear_to_send_out_n = ~clear_to_send;
uart_receiver #(
.ClocksPerBaud (ClocksPerBaud)
) rx(
.clk (clk),
.rst_n (rst_n),
.rx (rx_in),
.rx_byte_out (rx_byte),
.rx_byte_valid_out(rx_byte_valid),
.rx_byte_done (rx_byte_done),
.clear_to_send_out(clear_to_send)
);
uart_transmitter #(
.ClocksPerBaud (ClocksPerBaud)
) tx(
.clk (clk),
.rst_n (rst_n),
.tx_byte (tx_byte),
.tx_byte_valid (tx_byte_valid),
.tx_byte_done_out(tx_byte_done),
.tx_out (tx_out)
);
// State manipulation.
always @(*) begin // verilog_lint: waive always-comb b/72410891
state_next = state;
case (state)
StateIdle: begin
if (rx_byte_valid) begin
state_next = tx_byte_done ? StateGotByte : StateError;
end
end
StateGotByte: begin
state_next = StateIdle;
end
endcase
end
// Non-state updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
rx_byte_done_next = rx_byte_done;
tx_byte_next = tx_byte;
tx_byte_valid_next = tx_byte_valid;
case (state)
StateIdle: begin
tx_byte_valid_next = 0;
end
StateGotByte: begin
tx_byte_next = rx_byte;
tx_byte_valid_next = 1;
rx_byte_done_next = 1;
end
endcase
end
// Note: our version of iverilog has no support for always_ff.
always @ (posedge clk) begin
rx_byte_done <= rx_byte_done_next;
state <= state_next;
tx_byte <= tx_byte_next;
tx_byte_valid <= tx_byte_valid_next;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg3_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg3_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg3-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg3-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg3_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// (c) COPYRIGHT 2007 ALTERA CORPORATION
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V9.1
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 256
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 14
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 256
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR9.1
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 14;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 14;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 8;
parameter gLOCAL_DATA_BITS = 256;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 256;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 150;
parameter gMEM_IF_TRCD_NS = 13.125;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.125;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_CHIPSELS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b1 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_4_V
`define SKY130_FD_SC_HS__O2111AI_4_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111ai_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:59:16 05/22/2016
// Design Name:
// Module Name: Deteccion_Tecla
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Deteccion_Tecla(
input clk,
input reset,
input ps2d,
input ps2c,
input reset_escritura,
input [7:0] Segundos_RTC,
input [7:0] Minutos_RTC,
input [7:0] Horas_RTC,
output [7:0] Senal,
output Senal_2_ren,
output [7:0] Parametro,
output [7:0] Salida_1,
output [7:0] Salida_2,
output [7:0] Salida_3,
output [7:0] VGA_1,
output [7:0] VGA_2,
output [7:0] VGA_3,
output Flag_VGA,
output [7:0] Flag_Pico,
output [7:0] Salida_G
);
wire rx_done_tick;
wire [7:0] dout;
wire [7:0] Salida;
wire [1:0] Cuenta_ID;
wire [5:0] Cuenta_Segundos;
wire [5:0] Cuenta_Minutos;
wire [4:0] Cuenta_Horas;
wire [4:0] Cuenta_Year;
wire [3:0] Cuenta_Mes;
wire [6:0] Cuenta_Dia;
wire [7:0] Segundos_R;
wire [7:0] Minutos_R;
wire [7:0] Horas_R;
wire [7:0] Salida_Guardar;
wire [7:0] Salida_Estado_Cronometro;
wire reset_crono;
wire Salida_Reset;
assign Parametro = Salida;
assign Salida_G = Salida_Guardar;
ps2_rx F1 (
.clk(clk),
.reset(reset),
.ps2d(ps2d),
.ps2c(ps2c),
.rx_en(1'b1),
.rx_done_tick(rx_done_tick),
.dout(dout)
);
kb_code F2 (
.clk(clk),
.reset(reset),
.scan_done_tick(rx_done_tick),
.scan_out(dout),
.got_code_tick(got_code_tick)
);
Contador_ID F3 (
.rst(reset),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_ID)
);
Contador_AD_Segundos F4 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Segundos)
);
Contador_AD_Minutos F5 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Minutos)
);
Contador_AD_Horas F6 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Horas)
);
Contador_AD_Year F7(
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Year)
);
Contador_AD_Mes F8(
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Mes)
);
Contador_AD_Dia F9 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Dia)
);
Registro F10 (
.clk(clk),
.reset(reset),
.en(got_code_tick),
.codigo(dout),
.Salida(Salida)
);
MUX F11 (
.clk(clk),
.Estado(Salida),
.Cuenta_Segundos(Cuenta_Segundos),
.Cuenta_Minutos(Cuenta_Minutos),
.Cuenta_Horas(Cuenta_Horas),
.Cuenta_Year(Cuenta_Year),
.Cuenta_Mes(Cuenta_Mes),
.Cuenta_Dia(Cuenta_Dia),
.Salida_1(Salida_1),
.Salida_2(Salida_2),
.Salida_3(Salida_3)
);
Senal_Escritura F12 (
.Tecla(dout),
.got_data (got_code_tick),
.reset_escritura (reset_escritura),
.clk(clk),
.Senal(Senal)
);
Control_de_modo F13 (
.Tecla(dout),
.reset_escritura(Senal),
.clk(clk),
.got_data(got_code_tick),
.Senal(Senal_2_ren)
);
Decodificador_VGA F14 (
.clk(clk),
.Contador_1(Salida_1),
.Contador_2(Salida_2),
.Contador_3(Salida_3),
.VGA_1(VGA_1),
.VGA_2(VGA_2),
.VGA_3(VGA_3)
);
Registro_Contadores_Cronometro F15(
.clk(clk),
.Segundos(VGA_1),
.Minutos(VGA_2),
.Horas(VGA_3),
.Tecla(Salida_Estado_Cronometro),
.Segundos_R(Segundos_R),
.Minutos_R(Minutos_R),
.Horas_R(Horas_R)
);
Registro_Guardar F16 (
.Tecla(dout),
.clk(clk),
.reset(reset),
.Salida_Guardar(Salida_Guardar)
);
Registro_Estado_Cronometro F17 (
.Tecla(dout),
.clk(clk),
.reset(Salida_Reset),
.Salida_Estado_Cronometro(Salida_Estado_Cronometro)
);
Banderas_Alarma F18 (
.Segundos(Segundos_R),
.Minutos(Minutos_R),
.Horas(Horas_R),
.Segundos_RTC(Segundos_RTC),
.Minutos_RTC(Minutos_RTC),
.Horas_RTC(Horas_RTC),
.Estado(Salida_Estado_Cronometro),
.Guardar(Salida_Guardar),
.clk(clk),
.reset(reset),
.Flag_Pico(Flag_Pico)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V |
/*
* period_count_tb.v: Test bench for period_count.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 100
`endif
`ifndef RESOLUTION
`define RESOLUTION 0.1
`endif
module period_count_tb ();
reg RST;
reg PWRDWN;
reg clk;
wire [31:0] period_length_1000;
reg [31:0] clk_period;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 5;
period_count #(
.RESOLUTION(`RESOLUTION))
dut(
.RST(RST),
.PWRDWN(PWRDWN),
.clk(clk),
.period_length_1000(period_length_1000));
initial begin
$dumpfile("period_count_tb.vcd");
$dumpvars(0, period_count_tb);
RST = 0;
PWRDWN = 0;
clk = 0;
clk_period = 10;
pass_count = 0;
fail_count = 0;
#10;
RST = 1;
#10;
if (period_length_1000 === 0) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
RST = 0;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 10");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 10");
fail_count = fail_count + 1;
end
clk_period = 13;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 13");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 13");
fail_count = fail_count + 1;
end
clk_period = 1;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 1");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 1");
fail_count = fail_count + 1;
end
clk_period = (`WAIT_INTERVAL / 2);
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == `WAIT_INTERVAL / 2) begin
$display("PASSED: period = %0d", (`WAIT_INTERVAL / 2));
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = %0d", (`WAIT_INTERVAL / 2));
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(clk_period / 2.0) clk <= ~clk;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10036
module ddr3_s4_uniphy_p0_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_oct_ena,
dqs_enable_ctrl,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
ddio_phy_dq,
read_capture_clk,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter DQS_ENABLE_CTRL_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter FAST_SIM_MODEL = "";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
localparam HALF_AFI_DQS_WIDTH = AFI_DQS_WIDTH / 2;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input phy_ddio_addr_cmd_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
input [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
input [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [DQS_ENABLE_CTRL_WIDTH-1:0] dqs_enable_ctrl;
input [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
input [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output [DOUBLE_MEM_DQ_WIDTH-1:0] ddio_phy_dq;
output [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_afi_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_int = phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_int = phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_int = phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_int = phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_int = phy_ddio_oct_ena;
ddr3_s4_uniphy_p0_addr_cmd_pads uaddr_cmd_pads(
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.phy_ddio_addr_cmd_clk (phy_ddio_addr_cmd_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_l;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_h;
assign phy_ddio_oe_l = phy_ddio_wrdata_en_int[HALF_AFI_DQS_WIDTH-1:0];
assign phy_ddio_oe_h = phy_ddio_wrdata_en_int[AFI_DQS_WIDTH-1:HALF_AFI_DQS_WIDTH];
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq_int bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slow and subordered by
// DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The following extracts write data targeting the current DQS
// group.
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS_WITH_DM)];
ddr3_s4_uniphy_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (1'b0),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (hr_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.strobe_ena_clock_in (pll_dqs_ena_clk),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dq [(2*DQDQS_DATA_WIDTH*(i+1)-1) : 2*DQDQS_DATA_WIDTH*i]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.write_oe_in ({ {DQDQS_DATA_WIDTH{phy_ddio_oe_h[i]}}, {DQDQS_DATA_WIDTH{phy_ddio_oe_l[i]}} }),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena ({phy_ddio_dqs_en_int[i+NUM_OF_DQDQS], phy_ddio_dqs_en_int[i]}),
.oct_ena_in ({phy_ddio_oct_ena_int[i+NUM_OF_DQDQS], phy_ddio_oct_ena_int[i]}),
.capture_strobe_ena ({dqs_enable_ctrl[i+NUM_OF_DQDQS], dqs_enable_ctrl[i]}),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.dll_delayctrl_in (dll_phy_delayctrl)
);
defparam ubidir_dq_dqs.ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = FAST_SIM_MODEL;
assign read_capture_clk[i] = ~dqs_busout;
end
endgenerate
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_register_slice_v2_1_7_axi_register_slice,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_m00_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "zc702_m00_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=13,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m00_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [12 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [12 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [12 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [12 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(13),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: VGA experments
// modifed by BRL4 for SRAM; Displays a color grid
// VGA controller, PLL, and reset are from DE2 distribution CD
// --------------------------------------------------------------------
module DE2_Default
(
//////////////////// Clock Input ////////////////////
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
HEX4, // Seven Segment Digit 4
HEX5, // Seven Segment Digit 5
HEX6, // Seven Segment Digit 6
HEX7, // Seven Segment Digit 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 22 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // Toggle Switch[17:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
output [6:0] HEX4; // Seven Segment Digit 4
output [6:0] HEX5; // Seven Segment Digit 5
output [6:0] HEX6; // Seven Segment Digit 6
output [6:0] HEX7; // Seven Segment Digit 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM High-byte Data Mask
output SRAM_LB_N; // SRAM Low-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
output/*inout*/ AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// LCD ON
assign LCD_ON = 1'b0;
assign LCD_BLON = 1'b0;
// All inout port turn to tri-state
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign OTG_DATA = 16'hzzzz;
assign SD_DAT = 1'bz;
assign ENET_DATA = 16'hzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire [31:0] mSEG7_DIG;
reg [31:0] Cont;
wire VGA_CTRL_CLK;
wire AUD_CTRL_CLK;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
wire [19:0] mVGA_ADDR; //video memory address
wire [9:0] Coord_X, Coord_Y; //display coods
wire DLY_RST;
wire [3:0] RED;
wire [3:0] GREEN;
wire [3:0] BLUE;
reg FSMCLK;
//always@(posedge CLOCK_50 or negedge KEY[0])
//begin
// if(!KEY[0])
// Cont <= 0;
// else
// Cont <= Cont+1;
//end
assign TD_RESET = 1'b1; // Allow 27 MHz input
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
assign LEDR = 18'h0;
assign LEDG = 8'h0;
//assign mVGA_G = (mVGA_ADDR<20'h0ffff)? 10'd1000:0;
//assign mVGA_R = 10'd0000;
//assign mVGA_B = 10'd0000;
Reset_Delay r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );
VGA_Audio_PLL p1 ( .areset(~DLY_RST),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK) );
VGA_Controller u1 ( // Host Side
.iCursor_RGB_EN(4'b0111),
.oAddress(mVGA_ADDR),
.oCoord_X(Coord_X),
.oCoord_Y(Coord_Y),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST) );
video_generator video_generator(.Coord_X(Coord_X), .Coord_Y(Coord_Y), .SW(SW), .FSMCLK(VGA_VS), .RED(RED), .GREEN(GREEN), .BLUE(BLUE));
//Down sample to 512x512 and use coordinates to get memory address
assign SRAM_ADDR = {Coord_X[9:1],Coord_Y[9:1]} ; // [17:0]
//assign SRAM_ADDR = mVGA_ADDR[19:2];
assign SRAM_UB_N = 0; // hi byte select enabled
assign SRAM_LB_N = 0; // lo byte select enabled
assign SRAM_CE_N = 0; // chip is enabled
//assign SRAM_WE_N = 1; // write when ZERO
assign SRAM_OE_N = 0; //output enable is overidden by WE
// If KEY1 is not pressed, then float bus, so that SRAM can drive it (READ)
assign SRAM_WE_N = (KEY[1]? 1'b1 : 1'b0);
// If KEY1 is pressed, drive it with data from SWITCHES[15:0] to be stored in SRAM (WRITE)
//assign SRAM_DQ = (KEY[1]? 16'hzzzz : SW[15:0]);
assign SRAM_DQ = {RED,GREEN,BLUE,4'b0};
// Show memory on the LEDs and 7-seg display
assign mVGA_R = {SRAM_DQ[15:12], 6'b0} ;
assign mVGA_G = {SRAM_DQ[11:8], 6'b0} ;
assign mVGA_B = {SRAM_DQ[7:4], 6'b0} ;
endmodule //top module |
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK keyboard
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
// Modified by: Andy Karpov <[email protected]>
// Added PS2Controller with debouncer and error checking
//
// Design File: rk_kbd.v
//
module rk_kbd(
input clk,
input reset,
inout ps2_clk,
inout ps2_dat,
input[7:0] addr,
output reg[7:0] odata,
output[2:0] shift);
reg scancode_ready;
reg[9:0] scancode;
reg[2:0] shifts;
assign shift = shifts[2:0];
Keyboard kbd(
.Reset(reset), .Clock(clk),
.PS2Clock(ps2_clk), .PS2Data(ps2_dat),
.CodeReady(scancode_ready), .ScanCode(scancode)
);
reg[7:0] keymatrix[7:0]; // multi-dimensional array of key matrix
always @(addr,keymatrix) begin
odata =
(keymatrix[0] & {8{addr[0]}})|
(keymatrix[1] & {8{addr[1]}})|
(keymatrix[2] & {8{addr[2]}})|
(keymatrix[3] & {8{addr[3]}})|
(keymatrix[4] & {8{addr[4]}})|
(keymatrix[5] & {8{addr[5]}})|
(keymatrix[6] & {8{addr[6]}})|
(keymatrix[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
always @(*) begin
case (scancode[7:0])
8'h6C: {c,r} = 7'h00; // 7 home
8'h7D: {c,r} = 7'h10; // 9 pgup
8'h76: {c,r} = 7'h20; // esc
8'h05: {c,r} = 7'h30; // F1
8'h06: {c,r} = 7'h40; // F2
8'h04: {c,r} = 7'h50; // F3
8'h0C: {c,r} = 7'h60; // F4
8'h03: {c,r} = 7'h70; // F5
8'h0D: {c,r} = 7'h01; // tab
8'h71: {c,r} = 7'h11; // . del
8'h5A: {c,r} = 7'h21; // enter
8'h66: {c,r} = 7'h31; // bksp
8'h6B: {c,r} = 7'h41; // 4 left
8'h75: {c,r} = 7'h51; // 8 up
8'h74: {c,r} = 7'h61; // 6 right
8'h72: {c,r} = 7'h71; // 2 down
8'h45: {c,r} = 7'h02; // 0
8'h16: {c,r} = 7'h12; // 1
8'h1E: {c,r} = 7'h22; // 2
8'h26: {c,r} = 7'h32; // 3
8'h25: {c,r} = 7'h42; // 4
8'h2E: {c,r} = 7'h52; // 5
8'h36: {c,r} = 7'h62; // 6
8'h3D: {c,r} = 7'h72; // 7
8'h3E: {c,r} = 7'h03; // 8
8'h46: {c,r} = 7'h13; // 9
8'h55: {c,r} = 7'h23; // =
8'h0E: {c,r} = 7'h33; // `
8'h41: {c,r} = 7'h43; // ,
8'h4E: {c,r} = 7'h53; // -
8'h49: {c,r} = 7'h63; // .
8'h4A: {c,r} = 7'h73; // gray/ + /
8'h4C: {c,r} = 7'h04; // ;
8'h1C: {c,r} = 7'h14; // A
8'h32: {c,r} = 7'h24; // B
8'h21: {c,r} = 7'h34; // C
8'h23: {c,r} = 7'h44; // D
8'h24: {c,r} = 7'h54; // E
8'h2B: {c,r} = 7'h64; // F
8'h34: {c,r} = 7'h74; // G
8'h33: {c,r} = 7'h05; // H
8'h43: {c,r} = 7'h15; // I
8'h3B: {c,r} = 7'h25; // J
8'h42: {c,r} = 7'h35; // K
8'h4B: {c,r} = 7'h45; // L
8'h3A: {c,r} = 7'h55; // M
8'h31: {c,r} = 7'h65; // N
8'h44: {c,r} = 7'h75; // O
8'h4D: {c,r} = 7'h06; // P
8'h15: {c,r} = 7'h16; // Q
8'h2D: {c,r} = 7'h26; // R
8'h1B: {c,r} = 7'h36; // S
8'h2C: {c,r} = 7'h46; // T
8'h3C: {c,r} = 7'h56; // U
8'h2A: {c,r} = 7'h66; // V
8'h1D: {c,r} = 7'h76; // W
8'h22: {c,r} = 7'h07; // X
8'h35: {c,r} = 7'h17; // Y
8'h1A: {c,r} = 7'h27; // Z
8'h54: {c,r} = 7'h37; // [
8'h52: {c,r} = 7'h47; // '
8'h5B: {c,r} = 7'h57; // ]
8'h5D: {c,r} = 7'h67; // \!
8'h29: {c,r} = 7'h77; // space
8'h12: {c,r} = 7'h08; // lshift
8'h59: {c,r} = 7'h08; // rshift
8'h14: {c,r} = 7'h18; // rctrl + lctrl
8'h11: {c,r} = 7'h28; // lalt
/* 8'h0B: {c,r} = 7'h50; // F6
8'h83: {c,r} = 7'h70; // F7
8'h0A: {c,r} = 7'h12; // F8
8'h01: {c,r} = 7'h33; // F9
8'h07: {c,r} = 7'h56; // F12 - stop
8'h7C: {c,r} = 7'h46; // gray*
8'h7B: {c,r} = 7'h66; // gray-
8'h78: {c,r} = 7'h67; // F11 - rus
8'h73: {c,r} = 7'h28; // 5 center
8'h7A: {c,r} = 7'h48; // 3 pgdn
8'h69: {c,r} = 7'h68; // 1 end
8'h70: {c,r} = 7'h78; // 0 ins
*/ default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
keymatrix[0] <= 0;
keymatrix[1] <= 0;
keymatrix[2] <= 0;
keymatrix[3] <= 0;
keymatrix[4] <= 0;
keymatrix[5] <= 0;
keymatrix[6] <= 0;
keymatrix[7] <= 0;
shifts[2:0] <= 3'b0;
end else begin
if(r!=4'hF && scancode_ready) keymatrix[r][c] <= ~scancode[8];
if (scancode_ready) // extended e0
begin
case (scancode[7:0])
8'h12: shifts[0] = ~scancode[8]; // lshift
8'h59: shifts[0] = ~scancode[8]; // rshift
8'h14: shifts[1] = ~scancode[8]; // rctrl + lctrl
8'h11: shifts[2] = ~scancode[8]; // lalt
//default:
// shifts[2:0] = 3'b0;
endcase
end
end
end
endmodule
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module Coprocessor(
input clk,
input rst,
input [4:0] reg_R_addr,
input [4:0] reg_W_addr,
input [31:0] wdata,
input [31:0] pc_i,
input reg_we,
input EPCWrite,
input CauseWrite,
input [1:0] IntCause,
output [31:0] rdata,
output [31:0] epc_o
);
reg [31:0] register[12:14];
integer i;
assign rdata = register[reg_R_addr];
assign epc_o = register[14];
always @(posedge clk or posedge rst)
if (rst == 1)begin
for (i=12;i<14;i=i+1)
register[i] <= 0;
end else begin
if (reg_we)
register[reg_W_addr] <= wdata;
if (EPCWrite == 1)
register[14] <= pc_i;
if (CauseWrite == 1)
register[13] <= IntCause;
end
endmodule
|
module stimulus;
parameter cyc = 10;
parameter delay = 1;
reg clk, rst_n, mode, ivalid;
reg [`WIDTH-1:0] DATA;
wire ovalid;
wire [8:0] zeros;
reg debug_level;
reg [8*128-1:0] fsdbfile, inputfile, goldenfile;
reg [`WIDTH+1:0] input_vector[0:30000];
reg [8:0] golden_vector[0:30000];
integer i, j, error;
LZC #(
.width(`WIDTH),
.word(`WORD))
lzc1 (
.CLK(clk),
.RST_N(rst_n),
.MODE(mode),
.IVALID(ivalid),
.DATA(DATA),
.OVALID(ovalid),
.ZEROS(zeros)
);
always #(cyc/2) clk = ~clk;
// fsdb filename
initial begin
if ($value$plusargs("fsdbfile=%s", fsdbfile)) begin
$fsdbDumpfile(fsdbfile);
end else begin
$fsdbDumpfile("lzc.fsdb");
end
$fsdbDumpvars;
end
// debug mode
initial begin
if ($value$plusargs("DEBUG=%d", debug_level)) begin
if (debug_level == 1) begin
$monitor("clk=%d,OVALID=%b,ZEROS=%d", $time, ovalid, zeros);
end
end
end
// test pattern
initial begin
if ($value$plusargs("pattern=%s", inputfile)) begin
$readmemb(inputfile, input_vector);
end
if ($value$plusargs("golden=%s", goldenfile)) begin
$readmemb(goldenfile, golden_vector);
end
end
// testbench
initial begin
clk = 1;
rst_n = 1;
j = 0;
error = 0;
#(cyc);
#(delay) rst_n = 0;
#(cyc*4) rst_n = 1;
for (i = 0; i < 30000; i = i + 1) begin
#(cyc) apply_pattern(input_vector[i]);
end
#(cyc*3);
$display("%d errors in %s", error, inputfile);
$finish;
end
// count error
always @(posedge clk) begin
if (ovalid) begin
if (zeros != golden_vector[j]) begin
error = error + 1;
end
j = j + 1;
end
end
// apply pattern task
task apply_pattern;
input [`WIDTH+1:0] pattern;
begin
{mode, ivalid, DATA} = pattern;
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V |
`define bsg_tielo_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_TIELBWP_b``bits tielo (.o); \
end
module bsg_tielo #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
)
(output [width_p-1:0] o
);
`bsg_tielo_macro(34) else
`bsg_tielo_macro(33) else
`bsg_tielo_macro(32) else
`bsg_tielo_macro(31) else
`bsg_tielo_macro(30) else
`bsg_tielo_macro(29) else
`bsg_tielo_macro(28) else
`bsg_tielo_macro(27) else
`bsg_tielo_macro(26) else
`bsg_tielo_macro(25) else
`bsg_tielo_macro(24) else
`bsg_tielo_macro(23) else
`bsg_tielo_macro(22) else
`bsg_tielo_macro(21) else
`bsg_tielo_macro(20) else
`bsg_tielo_macro(19) else
`bsg_tielo_macro(18) else
`bsg_tielo_macro(17) else
`bsg_tielo_macro(16) else
`bsg_tielo_macro(15) else
`bsg_tielo_macro(14) else
`bsg_tielo_macro(13) else
`bsg_tielo_macro(12) else
`bsg_tielo_macro(11) else
`bsg_tielo_macro(10) else
`bsg_tielo_macro(9) else
`bsg_tielo_macro(8) else
`bsg_tielo_macro(7) else
`bsg_tielo_macro(6) else
`bsg_tielo_macro(5) else
`bsg_tielo_macro(4) else
`bsg_tielo_macro(3) else
`bsg_tielo_macro(2) else
`bsg_tielo_macro(1) else
begin :notmacro
assign o = { width_p {1'b0} };
// synopsys translate_off
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
// synopsys translate_on
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_tielo)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_TB_V
`define SKY130_FD_SC_HD__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_SYMBOL_V
`define SKY130_FD_SC_MS__A222O_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:02:36 12/01/2015
// Design Name: Datapath1
// Module Name: C:/Users/Juanjo/Documents/Juanjo/Facu/Arquitectura/Trabajo Final/finalArquitectura/TestDatapathPart1/PipeAndDebug/DebugAndPathTest.v
// Project Name: PipeAndDebug
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Datapath1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DebugAndPathTest;
// Inputs
reg clock;
reg resetGral;
wire uartRxPin;
// Outputs
wire uartTxPin;
wire ALUzero;
wire ALUOverflow;
localparam uart_COUNT = 651;
reg txStart=1;
reg[7:0] dataPC;
// Instantiate the Unit Under Test (UUT)
Datapath1 uut (
.clock(clock),
.resetGral(resetGral),
.uartRxPin(uartRxPin),
.uartTxPin(uartTxPin),
.ALUzero(ALUzero),
.ALUOverflow(ALUOverflow)
);
UART_baud_rate_generator #(.COUNT(uart_COUNT*16)) tx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_tx)
);
UART_tx transmisorPC(
.clock(clock), // clock de la placa a 50MHz
.reset(resetGral),
.s_tick(baud_rate_tx), // del baud rate generator a 9600bps
.tx_start(txStart), // flag de comienzo de envío (LÓGICA NEGATIVA)
.data_in(dataPC), // buffer de entrada de datos paralelo
.tx(uartRxPin), // salida serie de datos
.tx_done(txDone) // flag de finalización de envío
);
initial begin
// Initialize Inputs
clock = 0;
resetGral = 1;
txStart=1;
// Wait 100 ns for global reset to finish
#100;
resetGral=0;
#100;
dataPC=115;
#10;
txStart=0;
#5;
txStart=1;
#500000;
dataPC=110;
#10;
txStart=0;
#5;
txStart=1;
// Add stimulus here
end
always begin
clock=~clock;
#1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_TB_V
`define SKY130_FD_SC_HS__DFSTP_TB_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfstp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 SET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 SET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 SET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 SET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_TB_V
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_soft_calibration_top.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:25:50 $
// \ \ / \ Date Created: Mon Feb 9 2009
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Xilinx reference design top-level simulation
// wrapper file for input termination calibration
//Reference:
//
// Revision: Date: Comment
// 1.0: 2/06/09: Initial version for MIG wrapper.
// 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
// 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
// 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
// 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
// 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
// 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
// 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
//
// End Revision
//**********************************************************************************
`timescale 1ps/1ps
module mcb_soft_calibration_top # (
parameter C_MEM_TZQINIT_MAXCNT = 10'h512, // DDR3 Minimum delay between resets
parameter C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, and does dynamic recal,
// if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* no dynamic recal will be done
parameter SKIP_IN_TERM_CAL = 1'b0, // provides option to skip the input termination calibration
parameter SKIP_DYNAMIC_CAL = 1'b0, // provides option to skip the dynamic delay calibration
parameter SKIP_DYN_IN_TERM = 1'b0, // provides option to skip the input termination calibration
parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented
parameter C_MEM_TYPE = "DDR" // provides the memory device used for the design
)
(
input wire UI_CLK, // Input - global clock to be used for input_term_tuner and IODRP clock
input wire RST, // Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for IODRP (sub)controller
input wire IOCLK, // Input - IOCLK input to the IODRP's
output wire DONE_SOFTANDHARD_CAL, // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete)
input wire PLL_LOCK, // Lock signal from PLL
input wire SELFREFRESH_REQ,
input wire SELFREFRESH_MCB_MODE,
output wire SELFREFRESH_MCB_REQ ,
output wire SELFREFRESH_MODE,
output wire MCB_UIADD, // to MCB's UIADD port
output wire MCB_UISDI, // to MCB's UISDI port
input wire MCB_UOSDO,
input wire MCB_UODONECAL,
input wire MCB_UOREFRSHFLAG,
output wire MCB_UICS,
output wire MCB_UIDRPUPDATE,
output wire MCB_UIBROADCAST,
output wire [4:0] MCB_UIADDR,
output wire MCB_UICMDEN,
output wire MCB_UIDONECAL,
output wire MCB_UIDQLOWERDEC,
output wire MCB_UIDQLOWERINC,
output wire MCB_UIDQUPPERDEC,
output wire MCB_UIDQUPPERINC,
output wire MCB_UILDQSDEC,
output wire MCB_UILDQSINC,
output wire MCB_UIREAD,
output wire MCB_UIUDQSDEC,
output wire MCB_UIUDQSINC,
output wire MCB_RECAL,
output wire MCB_SYSRST,
output wire MCB_UICMD,
output wire MCB_UICMDIN,
output wire [3:0] MCB_UIDQCOUNT,
input wire [7:0] MCB_UODATA,
input wire MCB_UODATAVALID,
input wire MCB_UOCMDREADY,
input wire MCB_UO_CAL_START,
inout wire RZQ_Pin,
inout wire ZIO_Pin,
output wire CKE_Train
);
wire IODRP_ADD;
wire IODRP_SDI;
wire RZQ_IODRP_SDO;
wire RZQ_IODRP_CS;
wire ZIO_IODRP_SDO;
wire ZIO_IODRP_CS;
wire IODRP_SDO;
wire IODRP_CS;
wire IODRP_BKST;
wire RZQ_ZIO_ODATAIN;
wire RZQ_ZIO_TRISTATE;
wire RZQ_TOUT;
wire ZIO_TOUT;
wire [7:0] Max_Value;
assign RZQ_ZIO_ODATAIN = ~RST;
assign RZQ_ZIO_TRISTATE = ~RST;
assign IODRP_BKST = 1'b0; //future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration #(
.C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT),
.C_MC_CALIBRATION_MODE(C_MC_CALIBRATION_MODE),
.SKIP_IN_TERM_CAL (SKIP_IN_TERM_CAL),
.SKIP_DYNAMIC_CAL (SKIP_DYNAMIC_CAL),
.SKIP_DYN_IN_TERM (SKIP_DYN_IN_TERM),
.C_SIMULATION (C_SIMULATION),
.C_MEM_TYPE (C_MEM_TYPE)
)
mcb_soft_calibration_inst (
.UI_CLK (UI_CLK), // main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB CLK pins
.RST (RST), // main system reset for both this Soft Calibration block - also will act as a passthrough to MCB's SYSRST
.PLL_LOCK (PLL_LOCK), //lock signal from PLL
.SELFREFRESH_REQ (SELFREFRESH_REQ),
.SELFREFRESH_MCB_MODE (SELFREFRESH_MCB_MODE),
.SELFREFRESH_MCB_REQ (SELFREFRESH_MCB_REQ ),
.SELFREFRESH_MODE (SELFREFRESH_MODE),
.DONE_SOFTANDHARD_CAL (DONE_SOFTANDHARD_CAL),// active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) .IODRP_ADD(IODRP_ADD), // RZQ and ZIO IODRP ADD port, and MCB's UIADD port
.IODRP_ADD (IODRP_ADD), // RZQ and ZIO IODRP ADD port
.IODRP_SDI (IODRP_SDI), // RZQ and ZIO IODRP SDI port, and MCB's UISDI port
.RZQ_IN (RZQ_IN), // RZQ pin from board - expected to have a 2*R resistor to ground
.RZQ_IODRP_SDO (RZQ_IODRP_SDO), // RZQ IODRP's SDO port
.RZQ_IODRP_CS (RZQ_IODRP_CS), // RZQ IODRP's CS port
.ZIO_IN (ZIO_IN), // Z-stated IO pin - garanteed not to be driven externally
.ZIO_IODRP_SDO (ZIO_IODRP_SDO), // ZIO IODRP's SDO port
.ZIO_IODRP_CS (ZIO_IODRP_CS), // ZIO IODRP's CS port
.MCB_UIADD (MCB_UIADD), // to MCB's UIADD port
.MCB_UISDI (MCB_UISDI), // to MCB's UISDI port
.MCB_UOSDO (MCB_UOSDO), // from MCB's UOSDO port (User output SDO)
.MCB_UODONECAL (MCB_UODONECAL), // indicates when MCB hard calibration process is complete
.MCB_UOREFRSHFLAG (MCB_UOREFRSHFLAG), //high during refresh cycle and time when MCB is innactive
.MCB_UICS (MCB_UICS), // to MCB's UICS port (User Input CS)
.MCB_UIDRPUPDATE (MCB_UIDRPUPDATE), // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent
.MCB_UIBROADCAST (MCB_UIBROADCAST), // to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
.MCB_UIADDR (MCB_UIADDR), //to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
.MCB_UICMDEN (MCB_UICMDEN), //set to take control of UI interface - removes control from internal calib block
.MCB_UIDONECAL (MCB_UIDONECAL),
.MCB_UIDQLOWERDEC (MCB_UIDQLOWERDEC),
.MCB_UIDQLOWERINC (MCB_UIDQLOWERINC),
.MCB_UIDQUPPERDEC (MCB_UIDQUPPERDEC),
.MCB_UIDQUPPERINC (MCB_UIDQUPPERINC),
.MCB_UILDQSDEC (MCB_UILDQSDEC),
.MCB_UILDQSINC (MCB_UILDQSINC),
.MCB_UIREAD (MCB_UIREAD), //enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
.MCB_UIUDQSDEC (MCB_UIUDQSDEC),
.MCB_UIUDQSINC (MCB_UIUDQSINC),
.MCB_RECAL (MCB_RECAL), //when high initiates a hard re-calibration sequence
.MCB_UICMD (MCB_UICMD ),
.MCB_UICMDIN (MCB_UICMDIN ),
.MCB_UIDQCOUNT (MCB_UIDQCOUNT ),
.MCB_UODATA (MCB_UODATA ),
.MCB_UODATAVALID (MCB_UODATAVALID ),
.MCB_UOCMDREADY (MCB_UOCMDREADY ),
.MCB_UO_CAL_START (MCB_UO_CAL_START),
.MCB_SYSRST (MCB_SYSRST ), //drives the MCB's SYSRST pin - the main reset for MCB
.Max_Value (Max_Value ), // Maximum Tap Value from calibrated IOI
.CKE_Train (CKE_Train)
);
IOBUF IOBUF_RZQ (
.O (RZQ_IN),
.IO (RZQ_Pin),
.I (RZQ_OUT),
.T (RZQ_TOUT)
);
IODRP2 IODRP2_RZQ (
.DATAOUT(),
.DATAOUT2(),
.DOUT(RZQ_OUT),
.SDO(RZQ_IODRP_SDO),
.TOUT(RZQ_TOUT),
.ADD(IODRP_ADD),
.BKST(IODRP_BKST),
.CLK(UI_CLK),
.CS(RZQ_IODRP_CS),
.IDATAIN(RZQ_IN),
.IOCLK0(IOCLK),
.IOCLK1(1'b1),
.ODATAIN(RZQ_ZIO_ODATAIN),
.SDI(IODRP_SDI),
.T(RZQ_ZIO_TRISTATE)
);
generate
if ((C_MEM_TYPE == "DDR" || C_MEM_TYPE == "DDR2" || C_MEM_TYPE == "DDR3") &&
(SKIP_IN_TERM_CAL == 1'b0)
) begin : gen_zio
IOBUF IOBUF_ZIO (
.O (ZIO_IN),
.IO (ZIO_Pin),
.I (ZIO_OUT),
.T (ZIO_TOUT)
);
IODRP2 IODRP2_ZIO (
.DATAOUT(),
.DATAOUT2(),
.DOUT(ZIO_OUT),
.SDO(ZIO_IODRP_SDO),
.TOUT(ZIO_TOUT),
.ADD(IODRP_ADD),
.BKST(IODRP_BKST),
.CLK(UI_CLK),
.CS(ZIO_IODRP_CS),
.IDATAIN(ZIO_IN),
.IOCLK0(IOCLK),
.IOCLK1(1'b1),
.ODATAIN(RZQ_ZIO_ODATAIN),
.SDI(IODRP_SDI),
.T(RZQ_ZIO_TRISTATE)
);
end
endgenerate
endmodule
|
`include "hrfp_defs.vh"
module hrfp_compare
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] op_a, op_b,
output reg b_is_bigger,
output reg [`MSBBIT:0] op1_a, op1_b);
genvar i;
wire [35:0] propagate;
wire [35:0] newcarry;
wire [35:0] carrychain;
wire [35:0] A = {1'b0,op_a[34:0]};
wire [35:0] B = {1'b0,op_b[34:0]};
// This was necessary to create a comparator using 1 LUT per 2 bits
// which can be configured to either compare for either "less than
// or equal" or "less than" (selected by op_a`SIGN as input to
// carry chain)
generate
for(i=0; i <= 35; i = i + 2) begin : COMP
// Ok: If identical, we should propagate carry
// If A is less than B, we should generate carry
// if A larger than B, we should kill carry
LUT6_2 #(.INIT({32'b00000000000000001000010000100001,
32'b00000000000000000111001100010000}))
lut(.I0(A[i]),.I1(A[i+1]),.I2(B[i]),.I3(B[i+1]),.I4(1'b0),.I5(1'b1),.O6(propagate[i/2]),.O5(newcarry[i/2]));
if((i & 3) == 0) begin
CARRY4 chain(.CO(carrychain[i+3:i]),
.O(),
.DI(newcarry[i+3:i]),
.S(propagate[i+3:i]),
.CYINIT(i==0 ? op_a`SIGN : 1'b0),
.CI(i != 0 ? carrychain[i-1] : 1'b0));
end
end
endgenerate
// Move rounding here?
always @(posedge clk) begin
`ifdef DEBUG
$display("\n\n*************************** CARRYSTUFF *****************************");
$display(" A: %b",A);
$display(" B: %b",B);
$display(" propagate: %b",propagate);
$display(" newcarry: %b",newcarry);
$display(" carrychain: %b",carrychain);
$display("********************************************************************\n\n");
`endif
op1_a <= op_a;
op1_b <= op_b;
b_is_bigger <= carrychain[17];
// This test ensures that we handle plus/minus 0 correctly in such a way that
// -0 + +0 = +0 and +0 + -0 = +0
// FIXME - how to handle x-x = +0? (note: probably handled already...)
// Code present before hand instantiation above:
// if(op_a`SIGN) begin
// if(op_a[34:0] <= op_b[34:0]) begin
// b_is_bigger <= 1;
// end
// end else begin
// if(op_a[34:0] < op_b[34:0]) begin
// b_is_bigger <= 1;
// end
// end
// Note: If we write the above as this the synthesis tool fits everything into
// one LUT / 2 bits instead of two such structures followed by a mux
if(op_a[34:0] < op_b[34:0]+ op_a`SIGN ) begin
// Commented out because b_is_bigger is generated above in
// hand instantiated code instead. This if statement is now
// only used as a sanity check of the hand instantiated code
// instead.
// b_is_bigger <= 1;
if(carrychain[17] !== 1'b1) begin
$display("%m: Carrychain 17 is not correct (val is %b, should be 1)",carrychain[17]);
$stop;
end
end else begin
if(carrychain[17] !== 1'b0) begin
$display("%m: Carrychain 17 is not correct (val is %b, should be 0)",carrychain[17]);
end
end
end
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* Final reminder: Please do not put solutions to the exercises in
publicly accessible places. Thank you!! *)
(* Suppress some annoying warnings from Coq: *)
Set Warnings "-notation-overridden,-parsing,-deprecated-hint-without-locality".
From LF Require Export Lists.
(* ################################################################# *)
(** * Polymorphism *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data). We begin with polymorphism. *)
(* ================================================================= *)
(** ** Polymorphic Lists *)
(** For the last chapter, we've been working with lists
containing just numbers. Obviously, interesting programs also
need to be able to manipulate lists with elements from other
types -- lists of booleans, lists of lists, etc. We _could_ just
define a new inductive datatype for each of these, for
example... *)
Inductive boollist : Type :=
| bool_nil
| bool_cons (b : bool) (l : boollist).
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) and all
their properties ([rev_length], [app_assoc], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil
| cons (x : X) (l : list X).
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the function header on the first line,
and the occurrences of [natlist] in the types of the constructors
have been replaced by [list X].
What sort of thing is [list] itself? A good way to think about it
is that the definition of [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it more concisely, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is the [Inductive]ly defined set of lists whose
elements are of type [X]. *)
Check list : Type -> Type.
(** The [X] in the definition of [list] automatically becomes a
parameter to the constructors [nil] and [cons] -- that is, [nil]
and [cons] are now polymorphic constructors; when we use them, we
must now provide a first argument that is the type of the list
they are building. For example, [nil nat] constructs the empty
list of type [nat]. *)
Check (nil nat) : list nat.
(** Similarly, [cons nat] adds an element of type [nat] to a list of
type [list nat]. Here is an example of forming a list containing
just the natural number 3. *)
Check (cons nat 3 (nil nat)) : list nat.
(** What might the type of [nil] be? We can read off the type
[list X] from the definition, but this omits the binding for [X]
which is the parameter to [list]. [Type -> list X] does not
explain the meaning of [X]. [(X : Type) -> list X] comes
closer. Coq's notation for this situation is [forall X : Type,
list X]. *)
Check nil : forall X : Type, list X.
(** Similarly, the type of [cons] from the definition looks like
[X -> list X -> list X], but using this convention to explain the
meaning of [X] results in the type [forall X, X -> list X -> list
X]. *)
Check cons : forall X : Type, X -> list X -> list X.
(** (A side note on notations: In .v files, the "forall"
quantifier is spelled out in letters. In the corresponding HTML
files (and in the way some IDEs show .v files, depending on the
settings of their display controls), [forall] is usually typeset
as the standard mathematical "upside down A," though you'll still
see the spelled-out "forall" in a few places. This is just a
quirk of typesetting -- there is no difference in meaning.) *)
(** Having to supply a type argument for every single use of a
list constructor would be rather burdensome; we will soon see ways
of reducing this annotation burden. *)
Check (cons nat 2 (cons nat 1 (nil nat)))
: list nat.
(** We can now go back and make polymorphic versions of all the
list-processing functions that we wrote before. Here is [repeat],
for example: *)
Fixpoint repeat (X : Type) (x : X) (count : nat) : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat X x count')
end.
(** As with [nil] and [cons], we can use [repeat] by applying it
first to a type and then to an element of this type (and a number): *)
Example test_repeat1 :
repeat nat 4 2 = cons nat 4 (cons nat 4 (nil nat)).
Proof. reflexivity. Qed.
(** To use [repeat] to build other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_repeat2 :
repeat bool false 1 = cons bool false (nil bool).
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars, standard (mumble_grumble)
Consider the following two inductively defined types. *)
Module MumbleGrumble.
Inductive mumble : Type :=
| a
| b (x : mumble) (y : nat)
| c.
Inductive grumble (X:Type) : Type :=
| d (m : mumble)
| e (x : X).
(** Which of the following are well-typed elements of [grumble X] for
some type [X]? (Add YES or NO to each line.)
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c] *)
(* FILL IN HERE *)
End MumbleGrumble.
(* Do not modify the following line: *)
Definition manual_grade_for_mumble_grumble : option (nat*string) := None.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [repeat] again, but this time we
won't specify the types of any of the arguments. Will Coq still
accept it? *)
Fixpoint repeat' X x count : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat' X x count')
end.
(** Indeed it will. Let's see what type Coq has assigned to [repeat']: *)
Check repeat'
: forall X : Type, X -> nat -> list X.
Check repeat
: forall X : Type, X -> nat -> list X.
(** It has exactly the same type as [repeat]. Coq was able to
use _type inference_ to deduce what the types of [X], [x], and
[count] must be, based on how they are used. For example, since
[X] is used as an argument to [cons], it must be a [Type], since
[cons] expects a [Type] as its first argument; matching [count]
with [0] and [S] means it must be a [nat]; and so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations can still be quite useful as documentation and sanity
checks, so we will continue to use them much of the time. *)
(* ----------------------------------------------------------------- *)
(** *** Type Argument Synthesis *)
(** To use a polymorphic function, we need to pass it one or
more types in addition to its other arguments. For example, the
recursive call in the body of the [repeat] function above must
pass along the type [X]. But since the second argument to
[repeat] is an element of [X], it seems entirely obvious that the
first argument can only be [X] -- why should we have to write it
explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write a "hole" [_], which can be
read as "Please try to figure out for yourself what belongs here."
More precisely, when Coq encounters a [_], it will attempt to
_unify_ all locally available information -- the type of the
function being applied, the types of the other arguments, and the
type expected by the context in which the application appears --
to determine what concrete type should replace the [_].
This may sound similar to type annotation inference -- and, indeed,
the two procedures rely on the same underlying mechanisms. Instead
of simply omitting the types of some arguments to a function, like
repeat' X x count : list X :=
we can also replace the types with holes
repeat' (X : _) (x : _) (count : _) : list X :=
to tell Coq to attempt to infer the missing information.
Using holes, the [repeat] function can be written like this: *)
Fixpoint repeat'' X x count : list X :=
match count with
| 0 => nil _
| S count' => cons _ x (repeat'' _ x count')
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference in both keystrokes and
readability is nontrivial. For example, suppose we want to write
down a list containing the numbers [1], [2], and [3]. Instead of
this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use holes to write this: *)
Definition list123' :=
cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ----------------------------------------------------------------- *)
(** *** Implicit Arguments *)
(** In fact, we can go further and even avoid writing [_]'s in most
cases by telling Coq _always_ to infer the type argument(s) of a
given function.
The [Arguments] directive specifies the name of the function (or
constructor) and then lists the (leading) argument names to be
treated as implicit, each surrounded by curly braces. *)
Arguments nil {X}.
Arguments cons {X}.
Arguments repeat {X}.
(** Now we don't have to supply type arguments at all: *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
(** Alternatively, we can declare an argument to be implicit
when defining the function itself, by surrounding it in curly
braces instead of parens. For example: *)
Fixpoint repeat''' {X : Type} (x : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => cons x (repeat''' x count')
end.
(** (Note that we didn't even have to provide a type argument to the
recursive call to [repeat''']. Indeed, it would be invalid to
provide one, because Coq is not expecting it.)
We will use the latter style whenever possible, but we will
continue to use explicit [Argument] declarations for [Inductive]
constructors. The reason for this is that marking the parameter
of an inductive type as implicit causes it to become implicit for
the type itself, not just for its constructors. For instance,
consider the following alternative definition of the [list]
type: *)
Inductive list' {X:Type} : Type :=
| nil'
| cons' (x : X) (l : list').
(** Because [X] is declared as implicit for the _entire_ inductive
definition including [list'] itself, we now have to write just
[list'] whether we are talking about lists of numbers or booleans
or anything else, rather than [list' nat] or [list' bool] or
whatever; this is a step too far. *)
(** Let's finish by re-implementing a few other standard list
functions on our new polymorphic lists... *)
Fixpoint app {X : Type} (l1 l2 : list X) : list X :=
match l1 with
| nil => l2
| cons h t => cons h (app t l2)
end.
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => nil
| cons h t => app (rev t) (cons h nil)
end.
Fixpoint length {X : Type} (l : list X) : nat :=
match l with
| nil => 0
| cons _ l' => S (length l')
end.
Example test_rev1 :
rev (cons 1 (cons 2 nil)) = (cons 2 (cons 1 nil)).
Proof. reflexivity. Qed.
Example test_rev2:
rev (cons true nil) = cons true nil.
Proof. reflexivity. Qed.
Example test_length1: length (cons 1 (cons 2 (cons 3 nil))) = 3.
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Supplying Type Arguments Explicitly *)
(** One small problem with declaring arguments [Implicit] is
that, once in a while, Coq does not have enough local information
to determine a type argument; in such cases, we need to tell Coq
that we want to give the argument explicitly just this time. For
example, suppose we write this: *)
Fail Definition mynil := nil.
(** (The [Fail] qualifier that appears before [Definition] can be
used with _any_ command, and is used to ensure that that command
indeed fails when executed. If the command does fail, Coq prints
the corresponding error message, but continues processing the rest
of the file.)
Here, Coq gives us an error because it doesn't know what type
argument to supply to [nil]. We can help it by providing an
explicit type declaration (so that Coq has more information
available when it gets to the "application" of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil : forall X : Type, list X.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 2 stars, standard, optional (poly_exercises)
Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Complete the proofs
below. *)
Theorem app_nil_r : forall (X:Type), forall l:list X,
l ++ [] = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem app_assoc : forall A (l m n:list A),
l ++ m ++ n = (l ++ m) ++ n.
Proof.
(* FILL IN HERE *) Admitted.
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (more_poly_exercises)
Here are some slightly more interesting ones... *)
Theorem rev_app_distr: forall X (l1 l2 : list X),
rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the definition for pairs of
numbers that we gave in the last chapter can be generalized to
_polymorphic pairs_, often called _products_: *)
Inductive prod (X Y : Type) : Type :=
| pair (x : X) (y : Y).
Arguments pair {X} {Y}.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for product _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should only be used when parsing types, not when parsing
expressions. This avoids a clash with the multiplication
symbol.) *)
(** It is easy at first to get [(x,y)] and [X*Y] confused.
Remember that [(x,y)] is a _value_ built from two other values,
while [X*Y] is a _type_ built from two other types. If [x] has
type [X] and [y] has type [Y], then [(x,y)] has type [X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with
| (x, y) => x
end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with
| (x, y) => y
end.
(** The following function takes two lists and combines them
into a list of pairs. In other functional languages, it is often
called [zip]; we call it [combine] for consistency with Coq's
standard library. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx, ly with
| [], _ => []
| _, [] => []
| x :: tx, y :: ty => (x, y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, standard, optional (combine_checks)
Try answering the following questions on paper and
checking your answers in Coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Compute (combine [1;2] [false;false;true;true]).
print?
[] *)
(** **** Exercise: 2 stars, standard, especially useful (split)
The function [split] is the right inverse of [combine]: it takes a
list of pairs and returns a pair of lists. In many functional
languages, it is called [unzip].
Fill in the definition of [split] below. Make sure it passes the
given unit test. *)
Fixpoint split {X Y : Type} (l : list (X*Y)) : (list X) * (list Y)
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Options *)
(** Our last polymorphic type for now is _polymorphic options_,
which generalize [natoption] from the previous chapter. (We put
the definition inside a module because the standard library
already defines [option] and it's this one that we want to use
below.) *)
Module OptionPlayground.
Inductive option (X:Type) : Type :=
| Some (x : X)
| None.
Arguments Some {X}.
Arguments None {X}.
End OptionPlayground.
(** We can now rewrite the [nth_error] function so that it works
with any type of lists. *)
Fixpoint nth_error {X : Type} (l : list X) (n : nat)
: option X :=
match l with
| nil => None
| a :: l' => match n with
| O => Some a
| S n' => nth_error l' n'
end
end.
Example test_nth_error1 : nth_error [4;5;6;7] 0 = Some 4.
Proof. reflexivity. Qed.
Example test_nth_error2 : nth_error [[1];[2]] 1 = Some [2].
Proof. reflexivity. Qed.
Example test_nth_error3 : nth_error [true] 2 = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, standard, optional (hd_error_poly)
Complete the definition of a polymorphic version of the
[hd_error] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_error {X : Type} (l : list X) : option X
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_error : forall X : Type, list X -> option X.
Example test_hd_error1 : hd_error [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_error2 : hd_error [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Functions as Data *)
(** Like most modern programming languages -- especially other
"functional" languages, including OCaml, Haskell, Racket, Scala,
Clojure, etc. -- Coq treats functions as first-class citizens,
allowing them to be passed as arguments to other functions,
returned as results, stored in data structures, etc. *)
(* ================================================================= *)
(** ** Higher-Order Functions *)
(** Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X : Type} (f : X->X) (n : X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times : forall X : Type, (X -> X) -> X -> X.
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Filter *)
(** Here is a more useful higher-order function, taking a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filtering" the list, returning a new list containing just
those elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X) : list X :=
match l with
| [] => []
| h :: t =>
if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [even]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter even [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
(length l) =? 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter odd l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Anonymous Functions *)
(** It is arguably a little sad, in the example just above, to
be forced to define the function [length_is_1] and give it a name
just to be able to pass it as an argument to [filter], since we
will probably never use it again. Moreover, this is not an
isolated example: when using higher-order functions, we often want
to pass as arguments "one-off" functions that we will never use
again; having to give each of these functions a name would be
tedious.
Fortunately, there is a better way. We can construct a function
"on the fly" without declaring it at the top level or giving it a
name. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** The expression [(fun n => n * n)] can be read as "the function
that, given a number [n], yields [n * n]." *)
(** Here is the [filter] example, rewritten to use an anonymous
function. *)
Example test_filter2':
filter (fun l => (length l) =? 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars, standard (filter_even_gt7)
Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (partition)
Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a predicate of type [X -> bool] and a [list X],
[partition] should return a pair of lists. The first member of the
pair is the sublist of the original list containing the elements
that satisfy the test, and the second is the sublist containing
those that fail the test. The order of elements in the two
sublists should be the same as their order in the original list. *)
Definition partition {X : Type}
(test : X -> bool)
(l : list X)
: list X * list X
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_partition1: partition odd [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y : Type} (f : X->Y) (l : list X) : list Y :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same, since [map] takes _two_ type arguments, [X] and [Y]; it
can thus be applied to a list of numbers and a function from
numbers to booleans to yield a list of booleans: *)
Example test_map2:
map odd [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a _list of lists_ of booleans: *)
Example test_map3:
map (fun n => [even n;odd n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 3 stars, standard (map_rev)
Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (flat_map)
The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y: Type} (f: X -> list Y) (l: list X)
: list Y
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type for which [map] makes sense.
Here is a [map] for the [option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, standard, optional (implicit_args)
The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.)
*)
(** [] *)
(* ================================================================= *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y: Type} (f : X->Y->Y) (l : list X) (b : Y)
: Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Some more examples: *)
Check (fold andb) : list bool -> bool -> bool.
Example fold_example1 :
fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 :
fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 :
fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different)
Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_fold_types_different : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Functions That Construct Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as arguments. Let's look at some examples that
involve _returning_ functions as the results of other functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat -> X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus : nat -> nat -> nat.
(** Each [->] in this expression is actually a _binary_ operator
on types. This operator is _right-associative_, so the type of
[plus] is really a shorthand for [nat -> (nat -> nat)] -- i.e., it
can be read as saying that "[plus] is a one-argument function that
takes a [nat] and returns a one-argument function that takes
another [nat] and returns a [nat]." In the examples above, we
have always applied [plus] to both of its arguments at once, but
if we like we can supply just the first. This is called _partial
application_. *)
Definition plus3 := plus 3.
Check plus3 : nat -> nat.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Additional Exercises *)
Module Exercises.
(** **** Exercise: 2 stars, standard (fold_length)
Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. (Hint: It may help to
know that [reflexivity] simplifies expressions a bit more
aggressively than [simpl] does -- i.e., you may find yourself in a
situation where [simpl] does nothing but [reflexivity] solves the
goal.) *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (fold_map)
We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y: Type} (f: X -> Y) (l: list X) : list Y
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. (Hint: again, remember that
[reflexivity] simplifies expressions a bit more aggressively than
[simpl].) *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_fold_map : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, advanced (currying)
In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** As a (trivial) example of the usefulness of currying, we can use it
to shorten one of the examples that we saw above: *)
Example test_map1': map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** Thought exercise: before running the following commands, can you
calculate the types of [prod_curry] and [prod_uncurry]? *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type)
(f : X -> Y -> Z)
x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (nth_error_informal)
Recall the definition of the [nth_error] function:
Fixpoint nth_error {X : Type} (l : list X) (n : nat) : option X :=
match l with
| [] => None
| a :: l' => if n =? O then Some a else nth_error l' (pred n)
end.
Write an informal proof of the following theorem:
forall X l n, length l = n -> @nth_error X l n = None
*)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_informal_proof : option (nat*string) := None.
(** [] *)
(** The following exercises explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. *)
Module Church.
Definition cnat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Iterating
a function once should be the same as just applying it. Thus: *)
Definition one : cnat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** Similarly, [two] should apply [f] twice to its argument: *)
Definition two : cnat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** Defining [zero] is somewhat trickier: how can we "apply a function
zero times"? The answer is actually simple: just return the
argument untouched. *)
Definition zero : cnat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] can be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in
particular how the [doit3times] function we've defined previously
is actually just the Church representation of [3]. *)
Definition three : cnat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** **** Exercise: 1 star, advanced (church_succ) *)
(** Successor of a natural number: given a Church numeral [n],
the successor [succ n] is a function that iterates its
argument once more than [n]. *)
Definition succ (n : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, advanced (church_plus) *)
(** Addition of two natural numbers: *)
Definition plus (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (church_mult) *)
(** Multiplication: *)
Definition mult (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (church_exp) *)
(** Exponentiation: *)
(** (_Hint_: Polymorphism plays a crucial role here. However,
choosing the right type to iterate over can be tricky. If you hit
a "Universe inconsistency" error, try iterating over a different
type. Iterating over [cnat] itself is usually problematic.) *)
Definition exp (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Church.
End Exercises.
(* 2021-08-11 15:08 *)
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
wire valid_start_state;
wire valid_next_state;
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_start_state = ~((^start_state)^(^start_state));
assign valid_next_state = ~((^next_state)^(^next_state));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_next_state, r_start_state;
reg assert_state;
`ifdef OVL_SYNTHESIS
`else
initial begin
assert_state = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_start_state == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_state contains X or Z");
end
if (valid_next_state == 1'b1)
begin
// Do nothing
end
else
begin
if (start_state != test_expr)
begin
// Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"next_state contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (assert_state == 1'b0) begin // INIT_STATE
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
end
else begin // CHECK_STATE
if (test_expr == r_next_state) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Test expression transitioned from value equal to start_state to a value equal to next_state"); // test_expr moves to unexpected state
`endif // OVL_ASSERT_ON
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0;
end
else if (test_expr != r_start_state) begin
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0; // done ok.
end
end
end
else begin
assert_state <= 1'b0;
r_start_state <= {width{1'b0}};
r_next_state <= {width{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
/*
* cpc_core - the top level CPC rtl
*
* This is the actual CPC rtl
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`define LO 1'b0
`define HI 1'b1
module cpc_core (
input clk_16,
input clk_4,
input clk_1,
input nreset_i,
// UART Connection to Supervisor
output uart_tx_o,
input uart_rx_i,
// Video signals
input video_clk_i,
input [15:0] video_A_o,
output [7:0] video_D_o,
output [15:0] video_offset_o,
// Keyboard signals
input [79:0] keyboard_i,
output [7:0] audio_o,
// Shared ROM data
input [7:0] romram_data_i,
output [7:0] romram_data_o,
output /*reg*/ [23:0] romram_addr_o,
output romram_enable_o,
output romram_rd_o,
output romram_wr_o,
input romram_valid_i,
input [63:0] romflags_i, // Which ROMs are populated?
// FDC Interface
output reg fdc_motor = 0,
output fdc_activity,
// Support CPU Signals for FDC
input S_clk_i,
input [3:0] S_A_i,
input [7:0] S_D_i,
output [7:0] S_D_o,
input S_rd_i,
input S_wr_i,
input S_enable_i,
output S_fdc_int_o,
// Debug trigger connection
output [7:0] debug_trigger_o
);
// Wire definitions ===========================================================================
wire [15:0] A;
wire [7:0] DO, DI, u_rom_o, u_rom0_o, ram_o, vram_o, Dpio, D8255_o, Dfdc;
wire [7:0] ppia_o, ppia_i, ppic_o, u_rom5_o, u_rom6_o, u_rom7_o, fdc_o;
wire nWR, nRD, nMREQ, nIORQ, nROMEN, nM1, cpu_int, l_rom_e, u_rom_e, ram_e, u_ram_e, fdc_e;
wire vsync_signal, hsync_signal;
wire nIORD = (nIORQ | nRD);
wire nIOWR = (nIORQ | nWR);
wire nMEMRD = (nMREQ | nRD);
wire nMEMWR = (nMREQ | nWR);
wire [5:0] romsel_o; // TODO: Expanded by 1 bit to 64 pages of rom (1M)
wire [8:0] ramsel_o; // Expanded by 3 bits to 256 pages of ram (4M)
wire [7:0] ram_page; // Mapping to actual ram page
// CRTC / Video data
wire [13:0]MA;
wire [4:0]RA;
wire [23:0] color_dat;
wire video_border;
wire [2:0] pixel_num;
// PIO signals
wire printer_port_e = (A[12] == `LO);
wire [1:0] pio_selected_port;
wire [7:0] portc_dat; // Used to split port
wire D8255_e = ( A[11] == `LO );
// Registers ==================================================================================
// reg BUSWAIT = 1'b1;
reg [4:0] clockdiv = 0;
reg [7:0] ramrom_D_store;
// Assignments ================================================================================
assign romram_data_o = DO;
assign romram_enable_o = ~nMREQ & ((u_rom_e & romflags_i[romsel_o]) | l_rom_e | u_ram_e);
assign romram_rd_o = ~nMEMRD;
assign romram_wr_o = ~nMEMWR;
// Extended RAM, including 4M expansion
assign ram_page = ( ramsel_o[8] ) ? ramsel_o[7:0] :
5'd0; // TODO: More!!!
// Rules for paging in extended RAM
assign u_ram_e = ~nMREQ &
(ramsel_o[8] & (A[15:14] == 2'b01));
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
// always @(negedge clk_16)
// BUSWAIT <= (u_rom_e & ~romram_valid_i) && (romsel_o != 5'd0) && romflags_i[romsel_o]; // TODO: Removed
// Record the ROM address
//always @(negedge clk_16)
assign romram_addr_o = {1'd0, u_rom_e | l_rom_e, (u_rom_e) ? {2'b00, romsel_o} : (l_rom_e) ? 8'h40 : ram_page, A[13:0]};
// TODO:WAS romram_addr_o <= {1'd0, u_rom_e, (u_rom_e) ? {2'b00, romsel_o} : ram_page, A[13:0]};
//TODO:HERE - LOOK AT ME - LAST CHANGE 20181125
// tv80s cpu(
tv80n cpu(
// Clock and reset control
.clk(clk_4),
.reset_n( nreset_i ),
// System lines
.int_n(cpu_int),
.nmi_n(1'b1),
.busrq_n(1'b1),
.wait_n(1'b1/*~BUSWAIT*/), // TODO: Removed wait - will this work?????
// Data and address lines
.di(DI),
.dout(DO),
.A(A),
// control lines
.wr_n(nWR),
.rd_n(nRD),
.mreq_n(nMREQ),
.iorq_n(nIORQ),
.m1_n(nM1),
.rfsh_n(),
.halt_n(),
.busak_n()
);
/*
// TODO: Debug module - check romram stability
wire mrq = ~nMREQ & ~nRD;
reg [15:0] startA;
reg [7:0] startD;
reg faultA = 0, faultD = 0;
always @(negedge nMREQ) startA <= A;
always @(posedge romram_valid_i) startD <= DI;
assign debug_trigger_o[0] = faultA;
assign debug_trigger_o[1] = faultD;
always @(posedge nMREQ) if(startA != A) faultA = 1'b1; else faultA = 1'b0;
always @(negedge mrq) if(startD != DI) faultD = 1'b1; else faultD = 1'b0;
// END TODO
*/ /*
reg track_memrd, track_valid;
wire memrd_rise, valid_rise;
wire memrd = ~nMREQ & ~nRD;
assign memrd_rise = ({track_memrd,memrd} == 2'b01);
assign valid_rise = ({track_valid,(memrd_rise) ? 1'b0 : romram_valid_i } == 2'b01);
always @(posedge clk_16) track_memrd <= memrd;
always @(posedge clk_16) track_valid <= (memrd_rise) ? 1'b0 : romram_valid_i;
always @(negedge clk_16) if( valid_rise ) ramrom_D_store <= romram_data_i;
assign debug_trigger_o[0] = memrd_rise;
assign debug_trigger_o[1] = valid_rise;
*/
// Data bus arbiter, data latched on falling edge
dat_i_arbiter di_arbiter(
.clock_i( clk_16 ),
.D( DI ),
// LROM
.l_rom(/*ramrom_D_store*/romram_data_i),
.l_rom_e(l_rom_e),
// UROM
.u_rom(u_rom_o),
.u_rom_e(u_rom_e),
// Extended RAM
.eram(/*ramrom_D_store*/romram_data_i),
.u_ram_e(u_ram_e),
// RAM
.ram(ram_o),
.ram_e(ram_e),
// PIO
.pio8255(D8255_o),
.pio8255_e( /*~nIORD &*/ D8255_e ),
// Printer
.io(Dpio),
.io_e(/*~nIORD &*/ printer_port_e),
// FDC
.fdc(fdc_o),
.fdc_e(/*~nIORD &*/ fdc_e)
);
// Arbiter rules
assign ram_e = ~nMREQ; //~nMEMRD;
assign l_rom_e = (A[15:14] == 2'b00) && (nROMEN == 0) && ram_e;
assign u_rom_e = (A[15:14] == 2'b11) && (nROMEN == 0) && ram_e;
assign fdc_e = (A[15:1] == (16'hfb7f>>1)) && ~nIORD;
// CPC Ram
dpram cpc_ram(
.address_a(A),
.address_b(video_A_o),
.data_a(DO),
.data_b(8'b0),
.clock_a(clk_16),
.clock_b(video_clk_i),
.wren_a(nMEMWR == `LO),
.wren_b(1'b0),
.q_a(ram_o),
.q_b(video_D_o)
);
/*
// Fast ROM - Default to CPC464+Basic1.0
rom_builtin rom_builtin (
.rdclock ( clk_16 ),
.rdaddress ( {~l_rom_e,A[13:0]} ),
.q ( l_rom_o ),
// Write port for replacement of ROM - TODO: Write New Rom
.wrclock ( 1'b0 ),
.wraddress ( 15'd0 ),
.wren ( 1'b0 ),
.data ( )
);
*/
// Rom data if not rom zero
assign u_rom_o = (romflags_i[romsel_o]) ? /*ramrom_D_store*/romram_data_i : 8'hff;
// CRTC 6845
reg crtc_e = 1'b1;
always @(negedge clk_1) crtc_e <= (nIORD & nIOWR);
crtc6845 crtc(
.I_CLK(clk_1),
.I_RSTn(nreset_i),
.I_CSn(A[14]),
.I_RWn(A[9]),
.I_RS(A[8]),
.I_E(!(nIORD & nIOWR)/*crtc_e*/),
.I_DI(DO),
.O_RA(RA),
.O_MA(MA),
// TODO: Fix this
.O_H_SYNC(hsync_signal),
.O_V_SYNC(vsync_signal),
.O_DISPTMG(),
.video_offset_o(video_offset_o)
);
// Amstrad gate array emulator
a40010 gate_array (
.nreset_i(nreset_i),
.clk_i(clk_16),
// .slowclk_i(clk_1),
.a_i(A),
.d_i( DO ),
.dv_i( video_D_o ),
.nWR_i(nWR),
.nRD_i(nRD),
.nMREQ_i(nMREQ),
.nIORQ_i(nIORQ),
.nM1(nM1), // TODO: Added to enable lower rom on int ack
.nint_o(cpu_int),
.nROMEN_o(nROMEN),
.romsel_o(romsel_o[5:0]),
.ramsel_o(ramsel_o),
.video_pixel_i(pixel_num),
.border_i(video_border),
.color_dat_o(color_dat),
.vsync_i(vsync_signal),
.hsync_i(hsync_signal)
);
// Fake Keyboard Handler
assign ppia_i = (ppic_o[3:0] == 4'd0) ? keyboard_i[7:0] :
(ppic_o[3:0] == 4'd1) ? keyboard_i[15:8] :
(ppic_o[3:0] == 4'd2) ? keyboard_i[23:16]:
(ppic_o[3:0] == 4'd3) ? keyboard_i[31:24] :
(ppic_o[3:0] == 4'd4) ? keyboard_i[39:32] :
(ppic_o[3:0] == 4'd5) ? keyboard_i[47:40] :
(ppic_o[3:0] == 4'd6) ? keyboard_i[55:48] :
(ppic_o[3:0] == 4'd7) ? keyboard_i[63:56] :
(ppic_o[3:0] == 4'd8) ? keyboard_i[71:64] :
(ppic_o[3:0] == 4'd9) ? keyboard_i[79:72] :
8'd255;
// Fake PPIO - fixed directional ports
ppi_fake ppi8255(
.nreset_i(nreset_i),
.clk_i(clk_16),
.nCS_i(A[11]),
.a0(A[8]),
.a1(A[9]),
.nIORD_i(nIORD),
.nIOWR_i(nIOWR),
.d_i(DO),
.d_o(D8255_o),
.a_i(ppia_i),
.a_o(ppia_o),
.b_i({7'd127,vsync_signal}), // Tape in, printer busy, ~EXP pin, 4xManufacturer, syncin
.c_o(ppic_o)
);
// HDMI Module driver
/*
hdmi_video video(
.CLOCK_50_i(CLOCK_50_B6A),
.reset_i( !nreset_i ),
.hdmi_clk_o(HDMI_TX_CLK),
.hdmi_de_o(HDMI_TX_DE),
.hdmi_vs_o(HDMI_TX_VS),
.hdmi_hs_o(HDMI_TX_HS),
.hdmi_d_o(HDMI_TX_D),
.a_o(Av),
.vram_clk_o(vram_clk),
.color_dat_i(color_dat),
.video_pixel_o(pixel_num),
.border_o(video_border),
.video_offset_i(video_offset)
);
*/
`ifndef SIM
// Sound / keyboard module
YM2149 sounddev(
// data bus
.I_DA(ppia_o), // Output only, keyboard doesn't go through the sound module
.O_DA(),
.O_DA_OE_L(),
// control
.I_A9_L(`LO), // Not used
.I_A8(`HI), // Not used
.I_BDIR(ppic_o[7]),
.I_BC2(`HI),
.I_BC1(ppic_o[6]),
.I_SEL_L(`HI), // Default - clock divisor select - none
.O_AUDIO(audio_o),
// port a
.I_IOA(8'hff),
.O_IOA(),
.O_IOA_OE_L(),
// port b
.I_IOB(8'hff),
.O_IOB(),
.O_IOB_OE_L(),
//
.ENA(`HI), // Check this clock enable for higher speed operation
.RESET_L(nreset_i),
.CLK(clk_1)
);
`endif
// FDC Logic
fdc floppy (
// CPC Interface
.clk_i(clk_4),
.reset_i(~nreset_i),
.enable_i(A[15:1] == (16'hfb7f>>1)),
.data_i(DO),
.data_o(fdc_o),
.regsel_i(A[0]),
.rd_i(!nIORD),
.wr_i(!nIOWR),
.activity_o(fdc_activity),
.motor_i(fdc_motor),
// Drive interface
.sup_clk_i(S_clk_i),
.A(S_A_i),
.D_i(S_D_i),
.D_o(S_D_o),
.sup_rd_i(S_rd_i),
.sup_wr_i(S_wr_i),
.sup_enable_i(S_enable_i),
.sup_int_o(S_fdc_int_o) // Interrupt
);
// Motor control
reg [1:0] track_motor_rise = 2'd0;
always @(posedge clk_16)
track_motor_rise = {track_motor_rise[0], !nIOWR && (A[15:0] == 16'hfa7e)};
wire motor_rise = (track_motor_rise == 2'b01);
always @(negedge clk_16)
if( motor_rise ) fdc_motor <= DO[0];
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: tryagain.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tryagain (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/tryagain.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/tryagain.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/tryagain.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/* ring32b_bidir.v
Philip Watts
6th April 2010
Chip-to-chip module for the BEE3 based on the microsoft DDR2 code
This version hides the clock inversion control from the top level
*/
`timescale 1ns / 1ps
module ring32b_bidir(
// Clocks and resets
input CLK, // Main interface clock
input swClk0, // Unbuffered calibration clock
input swClk180, // Unbuffered cal clock, 180 deg out of phase
input Reset,
// Data interface with fabric
input [63:0] din,
output[63:0] dout,
//Pin signals
output [31:0] RING_OUT,
input [31:0] RING_IN,
//Control signals
input lock_in,
output lock_out,
input partner_ready,
output [31:0] test_sigs
);
//Each CLK, we send four 32-bit words.
//The testing requires Chipscope.
reg Equalx;
reg Equal;
reg Zerox;
reg Zero;
reg [63:0] TxD;
reg [63:0] RxD;
wire [31:0] outData;
wire [31:0] bankData; //data from the input pin
wire [31:0] bankDataDly; //data from the IDELAY
wire [63:0] isData; //data out of the ISERDES
reg [63:0] nextPoly; //the next received value we expect
(* KEEP = "TRUE" *) reg incDelay;
(* KEEP = "TRUE" *) reg resetDelay;
reg[6:0] currentTap;
reg[5:0] candWS; //candidate window start
reg candSW;
reg[5:0] candWW; //candidate window width
reg[5:0] WW; //window width
reg[5:0] WS; //window start
reg realSW;
reg[2:0] ringState;
//wire [35:0] control0;
//wire [255:0] cscope_sigs;
reg lock_out_int;
reg [63:0] dout_int;
wire switchClock;
wire swClock;
localparam Unlocked = 0;
localparam DecWS = 1;
localparam DecWW = 3;
localparam Locked = 2;
localparam NormOp = 6;
assign test_sigs = {26'b0, Equal, Zero, ringState, switchClock};
// Generate clocks for C2C phase alignment
// Switchable between 0 and 180 degrees phase
BUFGMUX_CTRL swClkbuf1 (
.O(swClock), // Clock MUX output
.I0(swClk0), // Clock0 input
.I1(swClk180), // Clock1 input
.S(switchClock)); // Clock select input
// Hold in reset until communicating partner is ready. Then send a test pattern
// until calibration has finished
always @(posedge CLK) begin
if(Reset)
TxD <= 63'h1;
else if (ringState==NormOp)
TxD <= din;
else
TxD <= {TxD[62:0], (TxD[63] ^ TxD[62] ^ TxD[60] ^ TxD[59])};
end
// The transmit pins
genvar pin;
generate
for(pin = 0; pin < 32; pin = pin + 1)
begin: makePin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) dataPin (
.Q (outData[pin] ),
.C (CLK ),
.CE (1'b1 ),
.D1 (TxD[2*pin + 1]),
.D2 (TxD[2*pin] ),
.R (1'b0 ),
.S (1'b0 )
);
OBUF pinBuf(
.I(outData[pin]),
.O(RING_OUT[pin])
);
end
endgenerate
//The receiver pins
genvar inPin;
generate
for(inPin = 0; inPin < 32; inPin = inPin + 1)
begin: makeInPin
IBUF rPinBuf(.I(RING_IN[inPin]), .O(bankData[inPin]));
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"), // "DEFAULT", "FIXED" or "VARIABLE"
.IOBDELAY_VALUE(0) // Any value from 0 to 63
) rPinDly (
.O(bankDataDly[inPin]), // 1-bit output
.C(CLK), // 1-bit clock input
.CE(incDelay), // 1-bit clock enable input
.I(bankData[inPin]), // 1-bit data input
.INC(incDelay), // 1-bit increment input
.RST(resetDelay) // 1-bit reset input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
.INIT_Q1(1'b0), // Initial value of Q1: 1?b0 or 1?b1
.INIT_Q2(1'b0), // Initial value of Q2: 1?b0 or 1?b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) rcvIddr (
.Q1(isData[2 * inPin + 1]), // 1-bit output for positive edge of clock
.Q2(isData[2 * inPin]), // 1-bit output for negative edge of clock
.C(swClock), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(bankDataDly[inPin]), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
end
endgenerate
// Calibration process
// Finds the maximum-width window (sequence of taps for which Equal is true).
always @(posedge CLK) begin
if(Reset) begin
ringState <= Unlocked;
WS <= 0;
WW <= 0;
realSW <= 0;
candWS <= 0;
candWW <= 0;
candSW <= 0;
currentTap <= 0;
resetDelay <= 1;
incDelay <= 0;
lock_out_int <= 0;
end
else begin case(ringState)
Unlocked: begin
resetDelay <= 0;
incDelay <= 1;
currentTap <= currentTap + 1;
if( (currentTap == 127) & ({1'b0, WW} > 8)) begin // IDELAY has 64 taps x 2 phase states = 128 'taps'
resetDelay <= 1;
ringState <= DecWS;
end
else if(Equal & ~Zero & currentTap[5:0] != 31) candWW <= candWW + 1;
else begin
if({1'b0,candWW} >= {1'b0,WW}) begin
WW <= candWW;
realSW <= candSW;
WS <= candWS;
end
candWS <= currentTap[5:0];
candSW <= currentTap[6];
candWW <= 0;
end
end
DecWS: begin
resetDelay <= 0;
if(WS == 0) begin
ringState <= DecWW;
WW <= WW/2;
end
else WS <= WS - 1;
end
DecWW: begin
if(WW == 0) begin
ringState <= Locked;
incDelay <= 0;
end
else WW <= WW - 1;
end
Locked: begin
lock_out_int <= 1;
if (lock_in == 1) ringState <= NormOp;
// if(~Equal | Zero) begin
// ringState <= Unlocked;
// WS <= 0;
// WW <= 0;
// realSW <= 0;
// candWS <= 0;
// candWW <= 0;
// candSW <= 0;
// currentTap <= 0;
// resetDelay <= 1;
// incDelay <= 0;
// end
end
NormOp: begin
if (lock_in == 0) ringState <= Locked;
end
endcase
end
end
assign switchClock = ringState == Unlocked ? currentTap[6]: realSW;
always @(posedge swClock) RxD <= isData;
always @(posedge swClock) nextPoly <= {RxD[62:0], (RxD[63] ^ RxD[62] ^RxD[60] ^ RxD[59])};
always @(posedge swClock) Equalx <= nextPoly == RxD;
always @(posedge swClock) Zerox <= RxD == 0;
always @(posedge CLK) Equal <= Equalx;
always @(posedge CLK) Zero <= Zerox;
always @(posedge CLK) dout_int <= RxD;
assign dout = dout_int;
assign lock_out = lock_out_int;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_gmii_clk,
input wire phy_gmii_rst,
input wire phy_gmii_clk_en,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign ledu = 0;
assign ledl = 0;
assign ledd = 0;
assign ledr = 0;
assign ledc = 0;
assign led = led_reg;
assign phy_reset_n = !rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rx_clk(phy_gmii_clk),
.rx_rst(phy_gmii_rst),
.tx_clk(phy_gmii_clk),
.tx_rst(phy_gmii_rst),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(phy_gmii_rxd),
.gmii_rx_dv(phy_gmii_rx_dv),
.gmii_rx_er(phy_gmii_rx_er),
.gmii_txd(phy_gmii_txd),
.gmii_tx_en(phy_gmii_tx_en),
.gmii_tx_er(phy_gmii_tx_er),
.rx_clk_enable(phy_gmii_clk_en),
.tx_clk_enable(phy_gmii_clk_en),
.rx_mii_select(1'b0),
.tx_mii_select(1'b0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_TB_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_TB_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s25.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__clkdlybuf4s25 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_BLACKBOX_V
`define SKY130_FD_IO__TOP_REFGEN_BLACKBOX_V
/**
* top_refgen: The REFGEN block (sky130_fd_io__top_refgen) is used to
* provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
* Verilog HDL for "sky130_fd_io",
* "sky130_fd_io_top_refgen" "behavioral_tmp".
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen (
VINREF ,
VOUTREF ,
REFLEAK_BIAS,
HLD_H_N ,
IBUF_SEL ,
OD_H ,
VOHREF ,
VREF_SEL ,
VREG_EN ,
VTRIP_SEL
);
output VINREF ;
output VOUTREF ;
inout REFLEAK_BIAS;
input HLD_H_N ;
input IBUF_SEL ;
input OD_H ;
input VOHREF ;
input VREF_SEL ;
input VREG_EN ;
input VTRIP_SEL ;
// Voltage supply signals
wire VCCD ;
wire VCCHIB ;
wire VDDA ;
wire VDDIO ;
wire VDDIO_Q;
wire VSSD ;
wire VSSIO ;
wire VSSIO_Q;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
tx_ref_clk_p,
tx_ref_clk_n,
tx_clk_p,
tx_clk_n,
tx_frame_p,
tx_frame_n,
tx_data_p,
tx_data_n,
gpio_adc_fdb,
gpio_adc_fda,
gpio_dac_irqn,
gpio_clkd_status,
gpio_clkd_pdn,
gpio_clkd_syncn,
gpio_resetn,
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
spi_clk,
spi_sdio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
input rx_sysref_p;
input rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 1:0] rx_data_p;
input [ 1:0] rx_data_n;
input tx_ref_clk_p;
input tx_ref_clk_n;
output tx_clk_p;
output tx_clk_n;
output tx_frame_p;
output tx_frame_n;
output [15:0] tx_data_p;
output [15:0] tx_data_n;
inout gpio_adc_fdb;
inout gpio_adc_fda;
inout gpio_dac_irqn;
inout [ 1:0] gpio_clkd_status;
inout gpio_clkd_pdn;
inout gpio_clkd_syncn;
inout gpio_resetn;
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire [ 2:0] spi_csn;
wire adc_clk;
wire [31:0] adc_data_a;
wire [31:0] adc_data_b;
wire adc_enable_a;
wire adc_enable_b;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
// pack & unpack data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= 1'b1;
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
2'b01: begin
dac_drd <= ~dac_drd;
dac_ddata_1 <= 64'd0;
dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
end
2'b10: begin
dac_drd <= ~dac_drd;
dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
dac_ddata_0 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_1 <= 64'd0;
dac_ddata_0 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_b, adc_enable_a})
2'b11: begin
adc_dwr <= 1'b1;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_a[31:16];
adc_ddata[31:16] <= adc_data_b[15: 0];
adc_ddata[15: 0] <= adc_data_a[15: 0];
end
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_b[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_a[31:16];
adc_ddata[47:32] <= adc_data_a[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
default: begin
adc_dwr <= 1'b0;
adc_ddata[63:48] <= 16'd0;
adc_ddata[47:32] <= 16'd0;
adc_ddata[31:16] <= 16'd0;
adc_ddata[15: 0] <= 16'd0;
end
endcase
end
// instantiations
assign spi_csn_adc = spi_csn[2];
assign spi_csn_dac = spi_csn[1];
assign spi_csn_clk = spi_csn[0];
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_rx_sysref (
.I (rx_sysref_p),
.IB (rx_sysref_n),
.O (rx_sysref));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
daq1_spi i_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(23)) i_iobuf (
.dio_t({gpio_t[39:32], gpio_t[14:0]}),
.dio_i({gpio_o[39:32], gpio_o[14:0]}),
.dio_o({gpio_i[39:32], gpio_i[14:0]}),
.dio_p({gpio_adc_fdb, // 39
gpio_adc_fda, // 38
gpio_dac_irqn, // 37
gpio_clkd_status, // 36:35
gpio_clkd_pdn, // 34
gpio_clkd_syncn, // 33
gpio_resetn, // 32
gpio_bd})); // 14:0
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a),
.adc_data_b (adc_data_b),
.adc_ddata (adc_ddata),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.adc_enable_a (adc_enable_a),
.adc_enable_b (adc_enable_b),
.adc_valid_a (),
.adc_valid_b (),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_valid_0 (),
.dac_valid_1 (),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn[0]),
.spi0_csn_1_o (spi_csn[1]),
.spi0_csn_2_o (spi_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.tx_clk_n (tx_clk_n),
.tx_clk_p (tx_clk_p),
.tx_data_n (tx_data_n),
.tx_data_p (tx_data_p),
.tx_frame_n (tx_frame_n),
.tx_frame_p (tx_frame_p),
.tx_ref_clk_n (tx_ref_clk_n),
.tx_ref_clk_p (tx_ref_clk_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:33 09/09/2014
// Design Name:
// Module Name: sevensegdecoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sevensegdecoder(
input [4:0] nIn,
output reg [6:0] ssOut
);
always @(nIn)
case (nIn)
5'h0: ssOut = 7'b1000000;
5'h1: ssOut = 7'b1111001;
5'h2: ssOut = 7'b0100100;
5'h3: ssOut = 7'b0110000;
5'h4: ssOut = 7'b0011001;
5'h5: ssOut = 7'b0010010;
5'h6: ssOut = 7'b0000010;
5'h7: ssOut = 7'b1111000;
5'h8: ssOut = 7'b0000000;
5'h9: ssOut = 7'b0011000;
5'hA: ssOut = 7'b0001000;
5'hB: ssOut = 7'b0000011;
5'hC: ssOut = 7'b1000110;
5'hD: ssOut = 7'b0100001;
5'hE: ssOut = 7'b0000110;
5'hF: ssOut = 7'b0001110;
5'h10: ssOut = 7'b0101111;
5'h11: ssOut = 7'b0001100;
5'h12: ssOut = 7'b0000110;
5'h13: ssOut = 7'b1111111;
default: ssOut = 7'b1001001;
endcase
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat Jun 03 23:38:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_overlay_0_0 -prefix
// system_vga_overlay_0_0_ system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.