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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CLOCK MODULE */
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the ACLK and SMCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer mclk_counter;
always @ (negedge mclk)
mclk_counter <= mclk_counter+1;
integer aclk_counter;
always @ (negedge mclk)
if (aclk_en) aclk_counter <= aclk_counter+1;
integer smclk_counter;
always @ (negedge mclk)
if (smclk_en) smclk_counter <= smclk_counter+1;
reg [15:0] reg_val;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef ASIC_CLOCKING
tb_skip_finish("| (this test is not supported in ASIC mode) |");
`else
// ACLK GENERATION
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h0001);
@(negedge aclk_en);
mclk_counter = 0;
aclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
if (aclk_counter !== 24) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
// ------- Divider /2 ----------
@(r15 === 16'h0002);
@(negedge aclk_en);
mclk_counter = 0;
aclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
if (aclk_counter !== 12) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
// ------- Divider /4 ----------
@(r15 === 16'h0003);
@(negedge aclk_en);
mclk_counter = 0;
aclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
if (aclk_counter !== 6) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
// ------- Divider /8 ----------
@(r15 === 16'h0004);
@(negedge aclk_en);
mclk_counter = 0;
aclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
if (aclk_counter !== 3) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
// SMCLK GENERATION - LFXT_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h1001);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
if (smclk_counter !== 24) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
// ------- Divider /2 ----------
@(r15 === 16'h1002);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
if (smclk_counter !== 12) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
// ------- Divider /4 ----------
@(r15 === 16'h1003);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
if (smclk_counter !== 6) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
// ------- Divider /8 ----------
@(r15 === 16'h1004);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(735) @(posedge mclk);
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
if (smclk_counter !== 3) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
// SMCLK GENERATION - DCO_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h2001);
mclk_counter = 0;
smclk_counter = 0;
repeat(600) @(posedge mclk);
if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
// ------- Divider /2 ----------
@(r15 === 16'h2002);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(600) @(posedge mclk);
if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
// ------- Divider /4 ----------
@(r15 === 16'h2003);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(600) @(posedge mclk);
if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
// ------- Divider /8 ----------
@(r15 === 16'h2004);
@(negedge smclk_en);
mclk_counter = 0;
smclk_counter = 0;
repeat(600) @(posedge mclk);
if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
// CPU ENABLE - CPU_EN INPUT
//--------------------------------------------------------
@(r15 === 16'h3000);
repeat(50) @(posedge mclk);
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
cpu_en = 1'b0;
repeat(3) @(posedge mclk);
reg_val = r14; // Read R14 register & initialize aclk/smclk counters
aclk_counter = 0;
smclk_counter = 0;
repeat(3) @(posedge mclk);
if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
repeat(500) @(posedge mclk); // Make sure that the CPU is stopped
if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 4) =====");
if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 5) =====");
if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) =====");
cpu_en = 1'b1;
repeat(500) @(posedge mclk); // Make sure that the CPU runs again
if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 8) =====");
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 9) =====");
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
// RD/WR ACCESS TO REGISTERS
//--------------------------------------------------------
@(r15 === 16'h5000);
if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
`ifdef DMA_IF_EN
if (r6 !== 16'h003A) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
`else
if (r6 !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
`endif
if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
`endif
stimulus_done = 1;
end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_4_V
`define SKY130_FD_SC_LP__DFSTP_4_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_4 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_4 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_4_V
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Wed Nov 28 10:36:14 EST 2012
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wtiS0_SThreadBusy O 1 reg
// wtiS0_SReset_n O 1
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// dac0_dap O 12
// dac0_dan O 12
// dac0_dbp O 12
// dac0_dbn O 12
// dac0_dcp O 12
// dac0_dcn O 12
// dac0_ddp O 12
// dac0_ddn O 12
// dac0_dacClkDiv O 1 reg
// dac0_dacDelay O 1 reg
// dac0_dacRf O 1 reg
// dac0_dacRz O 1 reg
// dac0_dacCal O 1 reg
// dac0_syncOutp O 1
// dac0_syncOutn O 1
// dac0_syncMutep O 1
// dac0_syncMuten O 1
// CLK_dac0_dacSdrClk O 1 clock
// CLK_GATE_dac0_dacSdrClk O 1 const
// RST_N_dac0_dacSdrRst O 1 reset
// CLK_dac_clk I 1 clock
// RST_N_dac_rst I 1 reset
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wtiS0_req I 67 reg
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDACWorker(CLK_dac_clk,
RST_N_dac_rst,
wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wtiS0_req,
wtiS0_SThreadBusy,
wtiS0_SReset_n,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
dac0_dap,
dac0_dan,
dac0_dbp,
dac0_dbn,
dac0_dcp,
dac0_dcn,
dac0_ddp,
dac0_ddn,
dac0_dacClkDiv,
dac0_dacDelay,
dac0_dacRf,
dac0_dacRz,
dac0_dacCal,
dac0_syncOutp,
dac0_syncOutn,
dac0_syncMutep,
dac0_syncMuten,
CLK_dac0_dacSdrClk,
CLK_GATE_dac0_dacSdrClk,
RST_N_dac0_dacSdrRst);
parameter [0 : 0] hasDebugLogic = 1'b0;
input CLK_dac_clk;
input RST_N_dac_rst;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wtiS0_put
input [66 : 0] wtiS0_req;
// value method wtiS0_sThreadBusy
output wtiS0_SThreadBusy;
// value method wtiS0_sReset_n
output wtiS0_SReset_n;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method dac0_dap
output [11 : 0] dac0_dap;
// value method dac0_dan
output [11 : 0] dac0_dan;
// value method dac0_dbp
output [11 : 0] dac0_dbp;
// value method dac0_dbn
output [11 : 0] dac0_dbn;
// value method dac0_dcp
output [11 : 0] dac0_dcp;
// value method dac0_dcn
output [11 : 0] dac0_dcn;
// value method dac0_ddp
output [11 : 0] dac0_ddp;
// value method dac0_ddn
output [11 : 0] dac0_ddn;
// value method dac0_dacClkDiv
output dac0_dacClkDiv;
// value method dac0_dacDelay
output dac0_dacDelay;
// value method dac0_dacRf
output dac0_dacRf;
// value method dac0_dacRz
output dac0_dacRz;
// value method dac0_dacCal
output dac0_dacCal;
// value method dac0_syncOutp
output dac0_syncOutp;
// value method dac0_syncOutn
output dac0_syncOutn;
// value method dac0_syncMutep
output dac0_syncMutep;
// value method dac0_syncMuten
output dac0_syncMuten;
// oscillator and gates for output clock CLK_dac0_dacSdrClk
output CLK_dac0_dacSdrClk;
output CLK_GATE_dac0_dacSdrClk;
// output resets
output RST_N_dac0_dacSdrRst;
// signals for module outputs
wire [31 : 0] wciS0_SData;
wire [11 : 0] dac0_dan,
dac0_dap,
dac0_dbn,
dac0_dbp,
dac0_dcn,
dac0_dcp,
dac0_ddn,
dac0_ddp;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire CLK_GATE_dac0_dacSdrClk,
CLK_dac0_dacSdrClk,
RST_N_dac0_dacSdrRst,
dac0_dacCal,
dac0_dacClkDiv,
dac0_dacDelay,
dac0_dacRf,
dac0_dacRz,
dac0_syncMuten,
dac0_syncMutep,
dac0_syncOutn,
dac0_syncOutp,
wciS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wtiS0_SReset_n,
wtiS0_SThreadBusy;
// inlined wires
wire [191 : 0] dacCore0_sampF_wDataIn$wget, dacCore0_sampF_wDataOut$wget;
wire [95 : 0] wsiS_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [66 : 0] wti_wtiReq$wget;
wire [60 : 0] wsiS_wsiReq$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] wci_wci_Es_mAddr_w$wget,
wci_wci_Es_mData_w$wget,
wsi_Es_mData_w$wget;
wire [15 : 0] fcDac_grayCounter_wdCounterCrossing$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [10 : 0] dacCore0_sampF_rRdPtr_wdCounterCrossing$wget,
dacCore0_sampF_rWrPtr_wdCounterCrossing$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] dacCore0_dacCtrl_s$wget,
wci_wci_Es_mByteEn_w$wget,
wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget,
wci_wslv_wEdge$wget,
wsi_Es_mCmd_w$wget;
wire dacCore0_ddrSDrv_dcmLock$wget,
dacCore0_emitEn_pw$whas,
dacCore0_iseqFsm_abort$wget,
dacCore0_iseqFsm_abort$whas,
dacCore0_iseqFsm_start_reg_1_1$wget,
dacCore0_iseqFsm_start_reg_1_1$whas,
dacCore0_iseqFsm_start_wire$wget,
dacCore0_iseqFsm_start_wire$whas,
dacCore0_iseqFsm_state_fired_1$wget,
dacCore0_iseqFsm_state_fired_1$whas,
dacCore0_iseqFsm_state_overlap_pw$whas,
dacCore0_iseqFsm_state_set_pw$whas,
dacCore0_sampF_pwDequeue$whas,
dacCore0_sampF_pwEnqueue$whas,
dacCore0_sampF_rRdPtr_pwDecrement$whas,
dacCore0_sampF_rRdPtr_pwIncrement$whas,
dacCore0_sampF_rWrPtr_pwDecrement$whas,
dacCore0_sampF_rWrPtr_pwIncrement$whas,
dacCore0_sampF_wDataIn$whas,
dacCore0_sampF_wDataOut$whas,
dacCore0_toneEn_pw$whas,
fcDac_grayCounter_pwDecrement$whas,
fcDac_grayCounter_pwIncrement$whas,
fcDac_pulseAction_1$wget,
fcDac_pulseAction_1$whas,
oneKHz_decAction$whas,
oneKHz_incAction$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas,
wti_operateD_1$wget,
wti_operateD_1$whas,
wti_wtiReq$whas;
// register dacControl
reg [31 : 0] dacControl;
wire [31 : 0] dacControl$D_IN;
wire dacControl$EN;
// register dacCore0_calBit
reg dacCore0_calBit;
wire dacCore0_calBit$D_IN, dacCore0_calBit$EN;
// register dacCore0_dacCount
reg [7 : 0] dacCore0_dacCount;
wire [7 : 0] dacCore0_dacCount$D_IN;
wire dacCore0_dacCount$EN;
// register dacCore0_dacCtrl_w
reg [3 : 0] dacCore0_dacCtrl_w;
wire [3 : 0] dacCore0_dacCtrl_w$D_IN;
wire dacCore0_dacCtrl_w$EN;
// register dacCore0_ddrSDrv_isReset_isInReset
reg dacCore0_ddrSDrv_isReset_isInReset;
wire dacCore0_ddrSDrv_isReset_isInReset$D_IN,
dacCore0_ddrSDrv_isReset_isInReset$EN;
// register dacCore0_emit
reg dacCore0_emit;
wire dacCore0_emit$D_IN, dacCore0_emit$EN;
// register dacCore0_emitCnt
reg [31 : 0] dacCore0_emitCnt;
wire [31 : 0] dacCore0_emitCnt$D_IN;
wire dacCore0_emitCnt$EN;
// register dacCore0_emitD
reg dacCore0_emitD;
wire dacCore0_emitD$D_IN, dacCore0_emitD$EN;
// register dacCore0_iseqFsm_jj_delay_count
reg [12 : 0] dacCore0_iseqFsm_jj_delay_count;
wire [12 : 0] dacCore0_iseqFsm_jj_delay_count$D_IN;
wire dacCore0_iseqFsm_jj_delay_count$EN;
// register dacCore0_iseqFsm_start_reg
reg dacCore0_iseqFsm_start_reg;
wire dacCore0_iseqFsm_start_reg$D_IN, dacCore0_iseqFsm_start_reg$EN;
// register dacCore0_iseqFsm_start_reg_1
reg dacCore0_iseqFsm_start_reg_1;
wire dacCore0_iseqFsm_start_reg_1$D_IN, dacCore0_iseqFsm_start_reg_1$EN;
// register dacCore0_iseqFsm_state_can_overlap
reg dacCore0_iseqFsm_state_can_overlap;
wire dacCore0_iseqFsm_state_can_overlap$D_IN,
dacCore0_iseqFsm_state_can_overlap$EN;
// register dacCore0_iseqFsm_state_fired
reg dacCore0_iseqFsm_state_fired;
wire dacCore0_iseqFsm_state_fired$D_IN, dacCore0_iseqFsm_state_fired$EN;
// register dacCore0_iseqFsm_state_mkFSMstate
reg [3 : 0] dacCore0_iseqFsm_state_mkFSMstate;
reg [3 : 0] dacCore0_iseqFsm_state_mkFSMstate$D_IN;
wire dacCore0_iseqFsm_state_mkFSMstate$EN;
// register dacCore0_muteDAC
reg dacCore0_muteDAC;
wire dacCore0_muteDAC$D_IN, dacCore0_muteDAC$EN;
// register dacCore0_sampF_rRdPtr_rdCounter
reg [10 : 0] dacCore0_sampF_rRdPtr_rdCounter;
wire [10 : 0] dacCore0_sampF_rRdPtr_rdCounter$D_IN;
wire dacCore0_sampF_rRdPtr_rdCounter$EN;
// register dacCore0_sampF_rRdPtr_rdCounterPre
reg [10 : 0] dacCore0_sampF_rRdPtr_rdCounterPre;
wire [10 : 0] dacCore0_sampF_rRdPtr_rdCounterPre$D_IN;
wire dacCore0_sampF_rRdPtr_rdCounterPre$EN;
// register dacCore0_sampF_rRdPtr_rsCounter
reg [10 : 0] dacCore0_sampF_rRdPtr_rsCounter;
wire [10 : 0] dacCore0_sampF_rRdPtr_rsCounter$D_IN;
wire dacCore0_sampF_rRdPtr_rsCounter$EN;
// register dacCore0_sampF_rWrPtr_rdCounter
reg [10 : 0] dacCore0_sampF_rWrPtr_rdCounter;
wire [10 : 0] dacCore0_sampF_rWrPtr_rdCounter$D_IN;
wire dacCore0_sampF_rWrPtr_rdCounter$EN;
// register dacCore0_sampF_rWrPtr_rdCounterPre
reg [10 : 0] dacCore0_sampF_rWrPtr_rdCounterPre;
wire [10 : 0] dacCore0_sampF_rWrPtr_rdCounterPre$D_IN;
wire dacCore0_sampF_rWrPtr_rdCounterPre$EN;
// register dacCore0_sampF_rWrPtr_rsCounter
reg [10 : 0] dacCore0_sampF_rWrPtr_rsCounter;
wire [10 : 0] dacCore0_sampF_rWrPtr_rsCounter$D_IN;
wire dacCore0_sampF_rWrPtr_rsCounter$EN;
// register dacCore0_syncMute
reg dacCore0_syncMute;
wire dacCore0_syncMute$D_IN, dacCore0_syncMute$EN;
// register dacCore0_syncOut
reg dacCore0_syncOut;
wire dacCore0_syncOut$D_IN, dacCore0_syncOut$EN;
// register dacCore0_tone
reg dacCore0_tone;
wire dacCore0_tone$D_IN, dacCore0_tone$EN;
// register dacCore0_undCount
reg [31 : 0] dacCore0_undCount;
wire [31 : 0] dacCore0_undCount$D_IN;
wire dacCore0_undCount$EN;
// register fcDac_countNow
reg [15 : 0] fcDac_countNow;
wire [15 : 0] fcDac_countNow$D_IN;
wire fcDac_countNow$EN;
// register fcDac_countPast
reg [15 : 0] fcDac_countPast;
wire [15 : 0] fcDac_countPast$D_IN;
wire fcDac_countPast$EN;
// register fcDac_frequency
reg [15 : 0] fcDac_frequency;
wire [15 : 0] fcDac_frequency$D_IN;
wire fcDac_frequency$EN;
// register fcDac_grayCounter_rdCounter
reg [15 : 0] fcDac_grayCounter_rdCounter;
wire [15 : 0] fcDac_grayCounter_rdCounter$D_IN;
wire fcDac_grayCounter_rdCounter$EN;
// register fcDac_grayCounter_rdCounterPre
reg [15 : 0] fcDac_grayCounter_rdCounterPre;
wire [15 : 0] fcDac_grayCounter_rdCounterPre$D_IN;
wire fcDac_grayCounter_rdCounterPre$EN;
// register fcDac_grayCounter_rsCounter
reg [15 : 0] fcDac_grayCounter_rsCounter;
wire [15 : 0] fcDac_grayCounter_rsCounter$D_IN;
wire fcDac_grayCounter_rsCounter$EN;
// register fcDac_pulseAction
reg fcDac_pulseAction;
wire fcDac_pulseAction$D_IN, fcDac_pulseAction$EN;
// register fcDac_sampleCount
reg [15 : 0] fcDac_sampleCount;
wire [15 : 0] fcDac_sampleCount$D_IN;
wire fcDac_sampleCount$EN;
// register firstUnderflowMesg
reg [31 : 0] firstUnderflowMesg;
wire [31 : 0] firstUnderflowMesg$D_IN;
wire firstUnderflowMesg$EN;
// register hasUnderflowed
reg hasUnderflowed;
wire hasUnderflowed$D_IN, hasUnderflowed$EN;
// register initOpInFlight
reg initOpInFlight;
wire initOpInFlight$D_IN, initOpInFlight$EN;
// register mesgStart
reg [31 : 0] mesgStart;
wire [31 : 0] mesgStart$D_IN;
wire mesgStart$EN;
// register oneKHz_value
reg [17 : 0] oneKHz_value;
wire [17 : 0] oneKHz_value$D_IN;
wire oneKHz_value$EN;
// register opcode
reg [8 : 0] opcode;
wire [8 : 0] opcode$D_IN;
wire opcode$EN;
// register rf
reg [11 : 0] rf;
wire [11 : 0] rf$D_IN;
wire rf$EN;
// register rf_1
reg [11 : 0] rf_1;
wire [11 : 0] rf_1$D_IN;
wire rf_1$EN;
// register rf_10
reg [11 : 0] rf_10;
wire [11 : 0] rf_10$D_IN;
wire rf_10$EN;
// register rf_11
reg [11 : 0] rf_11;
wire [11 : 0] rf_11$D_IN;
wire rf_11$EN;
// register rf_12
reg [11 : 0] rf_12;
wire [11 : 0] rf_12$D_IN;
wire rf_12$EN;
// register rf_13
reg [11 : 0] rf_13;
wire [11 : 0] rf_13$D_IN;
wire rf_13$EN;
// register rf_14
reg [11 : 0] rf_14;
wire [11 : 0] rf_14$D_IN;
wire rf_14$EN;
// register rf_15
reg [11 : 0] rf_15;
wire [11 : 0] rf_15$D_IN;
wire rf_15$EN;
// register rf_2
reg [11 : 0] rf_2;
wire [11 : 0] rf_2$D_IN;
wire rf_2$EN;
// register rf_3
reg [11 : 0] rf_3;
wire [11 : 0] rf_3$D_IN;
wire rf_3$EN;
// register rf_4
reg [11 : 0] rf_4;
wire [11 : 0] rf_4$D_IN;
wire rf_4$EN;
// register rf_5
reg [11 : 0] rf_5;
wire [11 : 0] rf_5$D_IN;
wire rf_5$EN;
// register rf_6
reg [11 : 0] rf_6;
wire [11 : 0] rf_6$D_IN;
wire rf_6$EN;
// register rf_7
reg [11 : 0] rf_7;
wire [11 : 0] rf_7$D_IN;
wire rf_7$EN;
// register rf_8
reg [11 : 0] rf_8;
wire [11 : 0] rf_8$D_IN;
wire rf_8$EN;
// register rf_9
reg [11 : 0] rf_9;
wire [11 : 0] rf_9$D_IN;
wire rf_9$EN;
// register sFlagState
reg sFlagState;
wire sFlagState$D_IN, sFlagState$EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight$D_IN, splitReadInFlight$EN;
// register srcCnt
reg [1 : 0] srcCnt;
wire [1 : 0] srcCnt$D_IN;
wire srcCnt$EN;
// register stageCount
reg [31 : 0] stageCount;
wire [31 : 0] stageCount$D_IN;
wire stageCount$EN;
// register syncCount
reg [31 : 0] syncCount;
wire [31 : 0] syncCount$D_IN;
wire syncCount$EN;
// register takeEven
reg takeEven;
wire takeEven$D_IN, takeEven$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wordsConsumed
reg [7 : 0] wordsConsumed;
wire [7 : 0] wordsConsumed$D_IN;
wire wordsConsumed$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// register wti_isReset_isInReset
reg wti_isReset_isInReset;
wire wti_isReset_isInReset$D_IN, wti_isReset_isInReset$EN;
// register wti_nowReq
reg [66 : 0] wti_nowReq;
wire [66 : 0] wti_nowReq$D_IN;
wire wti_nowReq$EN;
// register wti_operateD
reg wti_operateD;
wire wti_operateD$D_IN, wti_operateD$EN;
// ports of submodule dacCore0_dcmLck_cc
wire dacCore0_dcmLck_cc$dD_OUT,
dacCore0_dcmLck_cc$sD_IN,
dacCore0_dcmLck_cc$sEN;
// ports of submodule dacCore0_ddrSDrv_ddrV
wire [11 : 0] dacCore0_ddrSDrv_ddrV$dan,
dacCore0_ddrSDrv_ddrV$dap,
dacCore0_ddrSDrv_ddrV$dbn,
dacCore0_ddrSDrv_ddrV$dbp,
dacCore0_ddrSDrv_ddrV$dcn,
dacCore0_ddrSDrv_ddrV$dcp,
dacCore0_ddrSDrv_ddrV$ddn,
dacCore0_ddrSDrv_ddrV$ddp,
dacCore0_ddrSDrv_ddrV$sdrData0,
dacCore0_ddrSDrv_ddrV$sdrData1,
dacCore0_ddrSDrv_ddrV$sdrData2,
dacCore0_ddrSDrv_ddrV$sdrData3,
dacCore0_ddrSDrv_ddrV$sdrData4,
dacCore0_ddrSDrv_ddrV$sdrData5,
dacCore0_ddrSDrv_ddrV$sdrData6,
dacCore0_ddrSDrv_ddrV$sdrData7,
dacCore0_ddrSDrv_ddrV$sdrData8,
dacCore0_ddrSDrv_ddrV$sdrData9,
dacCore0_ddrSDrv_ddrV$sdrDataA,
dacCore0_ddrSDrv_ddrV$sdrDataB,
dacCore0_ddrSDrv_ddrV$sdrDataC,
dacCore0_ddrSDrv_ddrV$sdrDataD,
dacCore0_ddrSDrv_ddrV$sdrDataE,
dacCore0_ddrSDrv_ddrV$sdrDataF;
wire dacCore0_ddrSDrv_ddrV$dcmLocked, dacCore0_ddrSDrv_ddrV$sdrClk;
// ports of submodule dacCore0_emitCntCC
wire [31 : 0] dacCore0_emitCntCC$dD_OUT, dacCore0_emitCntCC$sD_IN;
wire dacCore0_emitCntCC$sEN, dacCore0_emitCntCC$sRDY;
// ports of submodule dacCore0_emitEn_d
wire dacCore0_emitEn_d$dD_OUT,
dacCore0_emitEn_d$sD_IN,
dacCore0_emitEn_d$sEN;
// ports of submodule dacCore0_iSeqDone
wire dacCore0_iSeqDone$dD_OUT,
dacCore0_iSeqDone$sD_IN,
dacCore0_iSeqDone$sEN;
// ports of submodule dacCore0_sampF_memory
wire [191 : 0] dacCore0_sampF_memory$DIA,
dacCore0_sampF_memory$DIB,
dacCore0_sampF_memory$DOB;
wire [9 : 0] dacCore0_sampF_memory$ADDRA, dacCore0_sampF_memory$ADDRB;
wire dacCore0_sampF_memory$ENA,
dacCore0_sampF_memory$ENB,
dacCore0_sampF_memory$WEA,
dacCore0_sampF_memory$WEB;
// ports of submodule dacCore0_sdrRst
wire dacCore0_sdrRst$OUT_RST;
// ports of submodule dacCore0_startIseqF
wire dacCore0_startIseqF$dDEQ,
dacCore0_startIseqF$sD_IN,
dacCore0_startIseqF$sENQ,
dacCore0_startIseqF$sFULL_N;
// ports of submodule dacCore0_syncMute_obuf
wire dacCore0_syncMute_obuf$I,
dacCore0_syncMute_obuf$O,
dacCore0_syncMute_obuf$OB;
// ports of submodule dacCore0_syncOut_obuf
wire dacCore0_syncOut_obuf$I,
dacCore0_syncOut_obuf$O,
dacCore0_syncOut_obuf$OB;
// ports of submodule dacCore0_toneEn_d
wire dacCore0_toneEn_d$dD_OUT,
dacCore0_toneEn_d$sD_IN,
dacCore0_toneEn_d$sEN;
// ports of submodule dacCore0_undCountCC
wire [31 : 0] dacCore0_undCountCC$dD_OUT, dacCore0_undCountCC$sD_IN;
wire dacCore0_undCountCC$sEN, dacCore0_undCountCC$sRDY;
// ports of submodule fcDac_testRst
wire fcDac_testRst$OUT_RST;
// ports of submodule stageF
wire [31 : 0] stageF$D_IN, stageF$D_OUT;
wire stageF$CLR, stageF$DEQ, stageF$EMPTY_N, stageF$ENQ, stageF$FULL_N;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13,
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10,
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13,
WILL_FIRE_RL_dacCore0_iseqFsm_action_np,
WILL_FIRE_RL_dacCore0_iseqFsm_fsm_start,
WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15,
WILL_FIRE_RL_emit_mesgConsume,
WILL_FIRE_RL_init_complete_ok,
WILL_FIRE_RL_process_staged_data,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
wire [17 : 0] MUX_oneKHz_value$write_1__VAL_1;
wire [15 : 0] MUX_fcDac_grayCounter_rsCounter$write_1__VAL_1;
wire [12 : 0] MUX_dacCore0_iseqFsm_jj_delay_count$write_1__VAL_1;
wire [11 : 0] MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr3_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr8_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdr9_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdrA_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdrB_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdrC_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdrD_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdrE_1__VAL_2,
MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_1,
MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_2;
wire [10 : 0] MUX_dacCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1,
MUX_dacCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1;
wire [8 : 0] MUX_opcode$write_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2;
wire MUX_opcode$write_1__SEL_1,
MUX_opcode$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h3702, v__h3877, v__h4021, v__h75623, v__h75780;
reg [31 : 0] CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1;
wire [31 : 0] IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1111,
IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1112,
IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1108,
IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1109,
IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_OR__ETC___d1115,
IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_ETC___d1116,
_theResult____h75764,
dacStatusLs__h75699,
rdat__h75871,
rdat__h75948,
result__h66758;
wire [15 : 0] x__h57357, y__h58614;
wire [10 : 0] dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011,
x__h18426,
x__h6959,
x__h9261,
x_dReadBin__h11074,
x_sReadBin__h11071,
y__h10148,
y__h7846;
wire [9 : 0] x2__h18395;
wire [5 : 0] x__h75926;
wire NOT_dacCore0_sampF_rWrPtr_rsCounter_64_EQ_dacC_ETC___d1092,
dacCore0_iseqFsm_abort_whas__60_AND_dacCore0_i_ETC___d417,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1000,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1001,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1002,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1008,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1009,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1026,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1027,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1028,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d999,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_XO_ETC___d1064,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1004,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1010,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1012,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1017,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1018,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1019,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1031,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d991,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d992,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d993,
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_XO_ETC___d1063,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1003,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1013,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1014,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1015,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1016,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d987,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d988,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d989,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d990,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1005,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1006,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1007,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1020,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1021,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1022,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1023,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1024,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1025,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d994,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d995,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d996,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d997,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d998,
fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_fc_ETC___d1065,
z__h10192,
z__h10199,
z__h10206,
z__h10213,
z__h10220,
z__h10227,
z__h10234,
z__h10241,
z__h10248,
z__h57377,
z__h57384,
z__h57391,
z__h57398,
z__h57405,
z__h57412,
z__h57419,
z__h57426,
z__h57433,
z__h57440,
z__h57447,
z__h57454,
z__h57461,
z__h57468,
z__h7890,
z__h7897,
z__h7904,
z__h7911,
z__h7918,
z__h7925,
z__h7932,
z__h7939,
z__h7946;
// oscillator and gates for output clock CLK_dac0_dacSdrClk
assign CLK_dac0_dacSdrClk = dacCore0_ddrSDrv_ddrV$sdrClk ;
assign CLK_GATE_dac0_dacSdrClk = 1'b1 ;
// output resets
assign RST_N_dac0_dacSdrRst = dacCore0_sdrRst$OUT_RST ;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wtiS0_sThreadBusy
assign wtiS0_SThreadBusy = wti_isReset_isInReset ;
// value method wtiS0_sReset_n
assign wtiS0_SReset_n = !wti_isReset_isInReset && wti_operateD ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method dac0_dap
assign dac0_dap = dacCore0_ddrSDrv_ddrV$dap ;
// value method dac0_dan
assign dac0_dan = dacCore0_ddrSDrv_ddrV$dan ;
// value method dac0_dbp
assign dac0_dbp = dacCore0_ddrSDrv_ddrV$dbp ;
// value method dac0_dbn
assign dac0_dbn = dacCore0_ddrSDrv_ddrV$dbn ;
// value method dac0_dcp
assign dac0_dcp = dacCore0_ddrSDrv_ddrV$dcp ;
// value method dac0_dcn
assign dac0_dcn = dacCore0_ddrSDrv_ddrV$dcn ;
// value method dac0_ddp
assign dac0_ddp = dacCore0_ddrSDrv_ddrV$ddp ;
// value method dac0_ddn
assign dac0_ddn = dacCore0_ddrSDrv_ddrV$ddn ;
// value method dac0_dacClkDiv
assign dac0_dacClkDiv = dacCore0_dacCtrl_w[3] ;
// value method dac0_dacDelay
assign dac0_dacDelay = dacCore0_dacCtrl_w[2] ;
// value method dac0_dacRf
assign dac0_dacRf = dacCore0_dacCtrl_w[0] ;
// value method dac0_dacRz
assign dac0_dacRz = dacCore0_dacCtrl_w[1] ;
// value method dac0_dacCal
assign dac0_dacCal = dacCore0_calBit ;
// value method dac0_syncOutp
assign dac0_syncOutp = dacCore0_syncOut_obuf$O ;
// value method dac0_syncOutn
assign dac0_syncOutn = dacCore0_syncOut_obuf$OB ;
// value method dac0_syncMutep
assign dac0_syncMutep = dacCore0_syncMute_obuf$O ;
// value method dac0_syncMuten
assign dac0_syncMuten = dacCore0_syncMute_obuf$OB ;
// submodule dacCore0_dcmLck_cc
SyncBit #(.init(1'd0)) dacCore0_dcmLck_cc(.sCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(dacCore0_sdrRst$OUT_RST),
.sD_IN(dacCore0_dcmLck_cc$sD_IN),
.sEN(dacCore0_dcmLck_cc$sEN),
.dD_OUT(dacCore0_dcmLck_cc$dD_OUT));
// submodule dacCore0_ddrSDrv_ddrV
ddrOutput2 dacCore0_ddrSDrv_ddrV(.dcmResetN(wciS0_MReset_n),
.ddrClk(CLK_dac_clk),
.sdrData0(dacCore0_ddrSDrv_ddrV$sdrData0),
.sdrData1(dacCore0_ddrSDrv_ddrV$sdrData1),
.sdrData2(dacCore0_ddrSDrv_ddrV$sdrData2),
.sdrData3(dacCore0_ddrSDrv_ddrV$sdrData3),
.sdrData4(dacCore0_ddrSDrv_ddrV$sdrData4),
.sdrData5(dacCore0_ddrSDrv_ddrV$sdrData5),
.sdrData6(dacCore0_ddrSDrv_ddrV$sdrData6),
.sdrData7(dacCore0_ddrSDrv_ddrV$sdrData7),
.sdrData8(dacCore0_ddrSDrv_ddrV$sdrData8),
.sdrData9(dacCore0_ddrSDrv_ddrV$sdrData9),
.sdrDataA(dacCore0_ddrSDrv_ddrV$sdrDataA),
.sdrDataB(dacCore0_ddrSDrv_ddrV$sdrDataB),
.sdrDataC(dacCore0_ddrSDrv_ddrV$sdrDataC),
.sdrDataD(dacCore0_ddrSDrv_ddrV$sdrDataD),
.sdrDataE(dacCore0_ddrSDrv_ddrV$sdrDataE),
.sdrDataF(dacCore0_ddrSDrv_ddrV$sdrDataF),
.ddp(dacCore0_ddrSDrv_ddrV$ddp),
.ddn(dacCore0_ddrSDrv_ddrV$ddn),
.dcmLocked(dacCore0_ddrSDrv_ddrV$dcmLocked),
.dap(dacCore0_ddrSDrv_ddrV$dap),
.dan(dacCore0_ddrSDrv_ddrV$dan),
.dbp(dacCore0_ddrSDrv_ddrV$dbp),
.dbn(dacCore0_ddrSDrv_ddrV$dbn),
.dcp(dacCore0_ddrSDrv_ddrV$dcp),
.dcn(dacCore0_ddrSDrv_ddrV$dcn),
.sdrClk(dacCore0_ddrSDrv_ddrV$sdrClk));
// submodule dacCore0_emitCntCC
SyncRegister #(.width(32'd32),
.init(32'd0)) dacCore0_emitCntCC(.sCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(dacCore0_sdrRst$OUT_RST),
.sD_IN(dacCore0_emitCntCC$sD_IN),
.sEN(dacCore0_emitCntCC$sEN),
.dD_OUT(dacCore0_emitCntCC$dD_OUT),
.sRDY(dacCore0_emitCntCC$sRDY));
// submodule dacCore0_emitEn_d
SyncBit #(.init(1'd0)) dacCore0_emitEn_d(.sCLK(wciS0_Clk),
.dCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(dacCore0_emitEn_d$sD_IN),
.sEN(dacCore0_emitEn_d$sEN),
.dD_OUT(dacCore0_emitEn_d$dD_OUT));
// submodule dacCore0_iSeqDone
SyncBit #(.init(1'd0)) dacCore0_iSeqDone(.sCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(dacCore0_sdrRst$OUT_RST),
.sD_IN(dacCore0_iSeqDone$sD_IN),
.sEN(dacCore0_iSeqDone$sEN),
.dD_OUT(dacCore0_iSeqDone$dD_OUT));
// submodule dacCore0_sampF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd192),
.MEMSIZE(11'd1024)) dacCore0_sampF_memory(.CLKA(wciS0_Clk),
.CLKB(dacCore0_ddrSDrv_ddrV$sdrClk),
.ADDRA(dacCore0_sampF_memory$ADDRA),
.ADDRB(dacCore0_sampF_memory$ADDRB),
.DIA(dacCore0_sampF_memory$DIA),
.DIB(dacCore0_sampF_memory$DIB),
.WEA(dacCore0_sampF_memory$WEA),
.WEB(dacCore0_sampF_memory$WEB),
.ENA(dacCore0_sampF_memory$ENA),
.ENB(dacCore0_sampF_memory$ENB),
.DOA(),
.DOB(dacCore0_sampF_memory$DOB));
// submodule dacCore0_sdrRst
SyncResetA #(.RSTDELAY(32'd0)) dacCore0_sdrRst(.CLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(dacCore0_sdrRst$OUT_RST));
// submodule dacCore0_startIseqF
SyncFIFO #(.dataWidth(32'd1),
.depth(32'd2),
.indxWidth(32'd1)) dacCore0_startIseqF(.sCLK(wciS0_Clk),
.dCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(dacCore0_startIseqF$sD_IN),
.sENQ(dacCore0_startIseqF$sENQ),
.dDEQ(dacCore0_startIseqF$dDEQ),
.dD_OUT(),
.sFULL_N(dacCore0_startIseqF$sFULL_N),
.dEMPTY_N());
// submodule dacCore0_syncMute_obuf
OBUFDS dacCore0_syncMute_obuf(.I(dacCore0_syncMute_obuf$I),
.O(dacCore0_syncMute_obuf$O),
.OB(dacCore0_syncMute_obuf$OB));
// submodule dacCore0_syncOut_obuf
OBUFDS dacCore0_syncOut_obuf(.I(dacCore0_syncOut_obuf$I),
.O(dacCore0_syncOut_obuf$O),
.OB(dacCore0_syncOut_obuf$OB));
// submodule dacCore0_toneEn_d
SyncBit #(.init(1'd0)) dacCore0_toneEn_d(.sCLK(wciS0_Clk),
.dCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(dacCore0_toneEn_d$sD_IN),
.sEN(dacCore0_toneEn_d$sEN),
.dD_OUT(dacCore0_toneEn_d$dD_OUT));
// submodule dacCore0_undCountCC
SyncRegister #(.width(32'd32),
.init(32'd0)) dacCore0_undCountCC(.sCLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(dacCore0_sdrRst$OUT_RST),
.sD_IN(dacCore0_undCountCC$sD_IN),
.sEN(dacCore0_undCountCC$sEN),
.dD_OUT(dacCore0_undCountCC$dD_OUT),
.sRDY(dacCore0_undCountCC$sRDY));
// submodule fcDac_testRst
SyncResetA #(.RSTDELAY(32'd1)) fcDac_testRst(.CLK(dacCore0_ddrSDrv_ddrV$sdrClk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(fcDac_testRst$OUT_RST));
// submodule stageF
FIFO2 #(.width(32'd32), .guarded(32'd1)) stageF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(stageF$D_IN),
.ENQ(stageF$ENQ),
.DEQ(stageF$DEQ),
.CLR(stageF$CLR),
.D_OUT(stageF$D_OUT),
.FULL_N(stageF$FULL_N),
.EMPTY_N(stageF$EMPTY_N));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_dacCore0_iseqFsm_action_l102c10
assign WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 =
dacCore0_ddrSDrv_ddrV$dcmLocked &&
dacCore0_iseqFsm_state_mkFSMstate == 4'd2 ;
// rule RL_dacCore0_iseqFsm_action_np
assign WILL_FIRE_RL_dacCore0_iseqFsm_action_np =
dacCore0_iseqFsm_jj_delay_count != 13'd4095 &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd5 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd6) ;
// rule RL_dacCore0_iseqFsm_action_l105c13
assign WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13 =
dacCore0_iseqFsm_jj_delay_count == 13'd4095 &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd5 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd6) ;
// rule RL_dacCore0_iseqFsm_fsm_start
assign WILL_FIRE_RL_dacCore0_iseqFsm_fsm_start =
dacCore0_iseqFsm_abort_whas__60_AND_dacCore0_i_ETC___d417 &&
dacCore0_iseqFsm_start_reg ;
// rule RL_dacCore0_iseqFsm_action_l100c13
assign WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 =
dacCore0_iseqFsm_start_wire$whas &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd0 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd7) ;
// rule RL_dacCore0_iseqFsm_idle_l99c15
assign WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15 =
!dacCore0_iseqFsm_start_wire$whas &&
dacCore0_iseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_emit_mesgConsume
assign WILL_FIRE_RL_emit_mesgConsume =
wsiS_reqFifo$EMPTY_N && stageF$FULL_N &&
wci_wslv_cState == 3'd2 &&
opcode[8] ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_process_staged_data
assign WILL_FIRE_RL_process_staged_data =
stageF$EMPTY_N &&
(dacControl[5] ?
NOT_dacCore0_sampF_rWrPtr_rsCounter_64_EQ_dacC_ETC___d1092 :
srcCnt != 2'h3 ||
NOT_dacCore0_sampF_rWrPtr_rsCounter_64_EQ_dacC_ETC___d1092) &&
wci_wslv_cState == 3'd2 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_init_complete_ok
assign WILL_FIRE_RL_init_complete_ok =
initOpInFlight && dacCore0_iSeqDone$dD_OUT ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
dacCore0_startIseqF$sFULL_N && wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq || WILL_FIRE_RL_emit_mesgConsume ;
// inputs to muxes for submodule ports
assign MUX_opcode$write_1__SEL_1 =
WILL_FIRE_RL_emit_mesgConsume && wsiS_reqFifo$D_OUT[57] ;
assign MUX_opcode$write_1__SEL_2 =
wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 && !opcode[8] ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_1 =
dacCore0_tone ? 12'd3902 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[11:0] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_1 =
dacCore0_tone ? 12'd3467 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[23:12] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_1 =
dacCore0_tone ? 12'd2816 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[35:24] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr3_1__VAL_1 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[47:36] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_1 =
dacCore0_tone ? 12'd1280 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[59:48] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_1 =
dacCore0_tone ? 12'd629 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[71:60] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_1 =
dacCore0_tone ? 12'd194 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[83:72] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_1 =
dacCore0_tone ? 12'd41 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[95:84] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr8_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[107:96] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdr9_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[119:108] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrA_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[131:120] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrB_1__VAL_1 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[143:132] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrC_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[155:144] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrD_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[167:156] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrE_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[179:168] ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_1 =
dacCore0_tone ? 12'd4055 : 12'd2048 ;
assign MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_2 =
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ?
12'd2048 :
dacCore0_sampF_memory$DOB[191:180] ;
assign MUX_dacCore0_iseqFsm_jj_delay_count$write_1__VAL_1 =
dacCore0_iseqFsm_jj_delay_count + 13'd1 ;
assign MUX_dacCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1 =
(~dacCore0_sampF_rRdPtr_rsCounter[IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1111[3:0]]) ?
dacCore0_sampF_rRdPtr_rsCounter | x__h9261 :
dacCore0_sampF_rRdPtr_rsCounter & y__h10148 ;
assign MUX_dacCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1 =
(~dacCore0_sampF_rWrPtr_rsCounter[IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1108[3:0]]) ?
dacCore0_sampF_rWrPtr_rsCounter | x__h6959 :
dacCore0_sampF_rWrPtr_rsCounter & y__h7846 ;
assign MUX_fcDac_grayCounter_rsCounter$write_1__VAL_1 =
(~fcDac_grayCounter_rsCounter[IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_ETC___d1116[3:0]]) ?
fcDac_grayCounter_rsCounter | x__h57357 :
fcDac_grayCounter_rsCounter & y__h58614 ;
assign MUX_oneKHz_value$write_1__VAL_1 =
(oneKHz_value == 18'd124999) ? 18'd0 : oneKHz_value + 18'd1 ;
assign MUX_opcode$write_1__VAL_2 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 =
{ 2'd1, _theResult____h75764 } ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ;
assign wci_wslv_respF_x_wire$whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'd1 ;
assign wci_wslv_sFlagReg_1$whas = sFlagState ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd2 ||
WILL_FIRE_RL_init_complete_ok ||
WILL_FIRE_RL_wci_ctrl_OrE ||
WILL_FIRE_RL_wci_ctrl_IsO ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign wti_wtiReq$wget = 67'h0 ;
assign wti_wtiReq$whas = 1'b0 ;
assign wti_operateD_1$wget = 1'b0 ;
assign wti_operateD_1$whas = 1'b0 ;
assign dacCore0_sampF_wDataIn$wget =
dacControl[5] ?
(takeEven ?
{16{stageF$D_OUT[15:4]}} :
{16{stageF$D_OUT[31:20]}}) :
{ rf_15,
rf_14,
rf_13,
rf_12,
rf_11,
rf_10,
rf_9,
rf_8,
rf_7,
rf_6,
rf_5,
rf_4,
rf_3,
rf_2,
rf_1,
rf } ;
assign dacCore0_sampF_wDataIn$whas = dacCore0_sampF_pwEnqueue$whas ;
assign dacCore0_sampF_wDataOut$wget = dacCore0_sampF_memory$DOB ;
assign dacCore0_sampF_wDataOut$whas = 1'd1 ;
assign dacCore0_iseqFsm_start_wire$wget = 1'd1 ;
assign dacCore0_iseqFsm_start_wire$whas =
WILL_FIRE_RL_dacCore0_iseqFsm_fsm_start ||
dacCore0_iseqFsm_start_reg_1 && !dacCore0_iseqFsm_state_fired ;
assign dacCore0_iseqFsm_start_reg_1_1$wget = 1'd1 ;
assign dacCore0_iseqFsm_start_reg_1_1$whas =
dacCore0_iseqFsm_start_wire$whas ;
assign dacCore0_iseqFsm_abort$wget = 1'b0 ;
assign dacCore0_iseqFsm_abort$whas = 1'b0 ;
assign dacCore0_iseqFsm_state_fired_1$wget = 1'd1 ;
assign dacCore0_iseqFsm_state_fired_1$whas =
dacCore0_iseqFsm_state_set_pw$whas ;
assign fcDac_pulseAction_1$wget = 1'd1 ;
assign fcDac_pulseAction_1$whas = oneKHz_value == 18'd124999 ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign dacCore0_sampF_rWrPtr_pwIncrement$whas =
dacCore0_sampF_pwEnqueue$whas ;
assign dacCore0_sampF_rWrPtr_pwDecrement$whas = 1'b0 ;
assign dacCore0_sampF_rRdPtr_pwIncrement$whas =
dacCore0_sampF_pwDequeue$whas ;
assign dacCore0_sampF_rRdPtr_pwDecrement$whas = 1'b0 ;
assign dacCore0_sampF_pwDequeue$whas =
dacCore0_emit &&
!dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ;
assign dacCore0_sampF_pwEnqueue$whas =
WILL_FIRE_RL_process_staged_data &&
(dacControl[5] || srcCnt == 2'h3) ;
assign dacCore0_emitEn_pw$whas =
wci_wslv_cState == 3'd2 && dacControl[4] &&
wordsConsumed > 8'd127 ;
assign dacCore0_toneEn_pw$whas = wci_wslv_cState == 3'd2 && dacControl[7] ;
assign dacCore0_iseqFsm_state_set_pw$whas =
WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 ;
assign dacCore0_iseqFsm_state_overlap_pw$whas = 1'b0 ;
assign fcDac_grayCounter_pwIncrement$whas = 1'd1 ;
assign fcDac_grayCounter_pwDecrement$whas = 1'b0 ;
assign oneKHz_incAction$whas = 1'd1 ;
assign oneKHz_decAction$whas = 1'b0 ;
assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_emit_mesgConsume ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_emit_mesgConsume ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign dacCore0_ddrSDrv_dcmLock$wget = dacCore0_ddrSDrv_ddrV$dcmLocked ;
assign dacCore0_sampF_rWrPtr_wdCounterCrossing$wget =
dacCore0_sampF_rWrPtr_rsCounter ;
assign dacCore0_sampF_rRdPtr_wdCounterCrossing$wget =
dacCore0_sampF_rRdPtr_rsCounter ;
assign dacCore0_dacCtrl_s$wget = dacCore0_dacCtrl_w ;
assign fcDac_grayCounter_wdCounterCrossing$wget =
fcDac_grayCounter_rsCounter ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
// register dacControl
assign dacControl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dacControl$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h0C ;
// register dacCore0_calBit
assign dacCore0_calBit$D_IN = dacCore0_iseqFsm_state_mkFSMstate != 4'd1 ;
assign dacCore0_calBit$EN =
dacCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ;
// register dacCore0_dacCount
assign dacCore0_dacCount$D_IN = dacCore0_dacCount + 8'd1 ;
assign dacCore0_dacCount$EN = 1'd1 ;
// register dacCore0_dacCtrl_w
assign dacCore0_dacCtrl_w$D_IN = dacControl[3:0] ;
assign dacCore0_dacCtrl_w$EN = 1'd1 ;
// register dacCore0_ddrSDrv_isReset_isInReset
assign dacCore0_ddrSDrv_isReset_isInReset$D_IN = 1'd0 ;
assign dacCore0_ddrSDrv_isReset_isInReset$EN =
dacCore0_ddrSDrv_isReset_isInReset ;
// register dacCore0_emit
assign dacCore0_emit$D_IN = dacCore0_emitEn_d$dD_OUT ;
assign dacCore0_emit$EN = 1'd1 ;
// register dacCore0_emitCnt
assign dacCore0_emitCnt$D_IN = dacCore0_emitCnt + 32'd1 ;
assign dacCore0_emitCnt$EN = dacCore0_sampF_pwDequeue$whas ;
// register dacCore0_emitD
assign dacCore0_emitD$D_IN = dacCore0_emit ;
assign dacCore0_emitD$EN = 1'd1 ;
// register dacCore0_iseqFsm_jj_delay_count
assign dacCore0_iseqFsm_jj_delay_count$D_IN =
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ?
MUX_dacCore0_iseqFsm_jj_delay_count$write_1__VAL_1 :
13'd0 ;
assign dacCore0_iseqFsm_jj_delay_count$EN =
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ;
// register dacCore0_iseqFsm_start_reg
assign dacCore0_iseqFsm_start_reg$D_IN = 1'd0 ;
assign dacCore0_iseqFsm_start_reg$EN =
WILL_FIRE_RL_dacCore0_iseqFsm_fsm_start ;
// register dacCore0_iseqFsm_start_reg_1
assign dacCore0_iseqFsm_start_reg_1$D_IN =
dacCore0_iseqFsm_start_wire$whas ;
assign dacCore0_iseqFsm_start_reg_1$EN = 1'd1 ;
// register dacCore0_iseqFsm_state_can_overlap
assign dacCore0_iseqFsm_state_can_overlap$D_IN =
dacCore0_iseqFsm_state_set_pw$whas ||
dacCore0_iseqFsm_state_can_overlap ;
assign dacCore0_iseqFsm_state_can_overlap$EN = 1'd1 ;
// register dacCore0_iseqFsm_state_fired
assign dacCore0_iseqFsm_state_fired$D_IN =
dacCore0_iseqFsm_state_set_pw$whas ;
assign dacCore0_iseqFsm_state_fired$EN = 1'd1 ;
// register dacCore0_iseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15 or
WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 or
dacCore0_iseqFsm_state_mkFSMstate or
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 or
WILL_FIRE_RL_dacCore0_iseqFsm_action_np or
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd1;
dacCore0_iseqFsm_state_mkFSMstate == 4'd1:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd2;
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd3;
dacCore0_iseqFsm_state_mkFSMstate == 4'd3:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd4;
dacCore0_iseqFsm_state_mkFSMstate == 4'd4:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_dacCore0_iseqFsm_action_np:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13:
dacCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd7;
default: dacCore0_iseqFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign dacCore0_iseqFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_dacCore0_iseqFsm_idle_l99c15 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13 ;
// register dacCore0_muteDAC
assign dacCore0_muteDAC$D_IN =
!WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13 ;
assign dacCore0_muteDAC$EN =
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 ;
// register dacCore0_sampF_rRdPtr_rdCounter
assign dacCore0_sampF_rRdPtr_rdCounter$D_IN =
dacCore0_sampF_rRdPtr_rdCounterPre ;
assign dacCore0_sampF_rRdPtr_rdCounter$EN = 1'd1 ;
// register dacCore0_sampF_rRdPtr_rdCounterPre
assign dacCore0_sampF_rRdPtr_rdCounterPre$D_IN =
dacCore0_sampF_rRdPtr_rsCounter ;
assign dacCore0_sampF_rRdPtr_rdCounterPre$EN = 1'd1 ;
// register dacCore0_sampF_rRdPtr_rsCounter
assign dacCore0_sampF_rRdPtr_rsCounter$D_IN =
MUX_dacCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1 ;
assign dacCore0_sampF_rRdPtr_rsCounter$EN = dacCore0_sampF_pwDequeue$whas ;
// register dacCore0_sampF_rWrPtr_rdCounter
assign dacCore0_sampF_rWrPtr_rdCounter$D_IN =
dacCore0_sampF_rWrPtr_rdCounterPre ;
assign dacCore0_sampF_rWrPtr_rdCounter$EN = 1'd1 ;
// register dacCore0_sampF_rWrPtr_rdCounterPre
assign dacCore0_sampF_rWrPtr_rdCounterPre$D_IN =
dacCore0_sampF_rWrPtr_rsCounter ;
assign dacCore0_sampF_rWrPtr_rdCounterPre$EN = 1'd1 ;
// register dacCore0_sampF_rWrPtr_rsCounter
assign dacCore0_sampF_rWrPtr_rsCounter$D_IN =
MUX_dacCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1 ;
assign dacCore0_sampF_rWrPtr_rsCounter$EN = dacCore0_sampF_pwEnqueue$whas ;
// register dacCore0_syncMute
assign dacCore0_syncMute$D_IN = 1'b0 ;
assign dacCore0_syncMute$EN = 1'b0 ;
// register dacCore0_syncOut
assign dacCore0_syncOut$D_IN = dacCore0_dacCount == 8'd0 ;
assign dacCore0_syncOut$EN = 1'd1 ;
// register dacCore0_tone
assign dacCore0_tone$D_IN = dacCore0_toneEn_d$dD_OUT ;
assign dacCore0_tone$EN = 1'd1 ;
// register dacCore0_undCount
assign dacCore0_undCount$D_IN = dacCore0_undCount + 32'd1 ;
assign dacCore0_undCount$EN =
dacCore0_emit &&
dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 ;
// register fcDac_countNow
assign fcDac_countNow$D_IN =
{ fcDac_grayCounter_rdCounter[15],
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1021,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1020,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1022,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d994,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d995,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d998,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1005,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d996,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1006,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d997,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1023,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1025,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1024,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1007,
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1007 ^
fcDac_grayCounter_rdCounter[0] } ;
assign fcDac_countNow$EN = fcDac_pulseAction ;
// register fcDac_countPast
assign fcDac_countPast$D_IN = fcDac_countNow ;
assign fcDac_countPast$EN = fcDac_pulseAction ;
// register fcDac_frequency
assign fcDac_frequency$D_IN = fcDac_countNow - fcDac_countPast ;
assign fcDac_frequency$EN = fcDac_pulseAction ;
// register fcDac_grayCounter_rdCounter
assign fcDac_grayCounter_rdCounter$D_IN = fcDac_grayCounter_rdCounterPre ;
assign fcDac_grayCounter_rdCounter$EN = 1'd1 ;
// register fcDac_grayCounter_rdCounterPre
assign fcDac_grayCounter_rdCounterPre$D_IN = fcDac_grayCounter_rsCounter ;
assign fcDac_grayCounter_rdCounterPre$EN = 1'd1 ;
// register fcDac_grayCounter_rsCounter
assign fcDac_grayCounter_rsCounter$D_IN =
MUX_fcDac_grayCounter_rsCounter$write_1__VAL_1 ;
assign fcDac_grayCounter_rsCounter$EN = 1'b1 ;
// register fcDac_pulseAction
assign fcDac_pulseAction$D_IN = oneKHz_value == 18'd124999 ;
assign fcDac_pulseAction$EN = 1'd1 ;
// register fcDac_sampleCount
assign fcDac_sampleCount$D_IN = fcDac_sampleCount + 16'd1 ;
assign fcDac_sampleCount$EN = fcDac_pulseAction ;
// register firstUnderflowMesg
assign firstUnderflowMesg$D_IN = mesgStart ;
assign firstUnderflowMesg$EN =
wci_wslv_cState == 3'd2 && !hasUnderflowed &&
dacCore0_undCountCC$dD_OUT != 32'd0 ;
// register hasUnderflowed
assign hasUnderflowed$D_IN = 1'd1 ;
assign hasUnderflowed$EN =
wci_wslv_cState == 3'd2 && !hasUnderflowed &&
dacCore0_undCountCC$dD_OUT != 32'd0 ;
// register initOpInFlight
assign initOpInFlight$D_IN = WILL_FIRE_RL_wci_ctrl_EiI ;
assign initOpInFlight$EN =
WILL_FIRE_RL_init_complete_ok || WILL_FIRE_RL_wci_ctrl_EiI ;
// register mesgStart
assign mesgStart$D_IN = mesgStart + 32'd1 ;
assign mesgStart$EN = MUX_opcode$write_1__SEL_2 ;
// register oneKHz_value
assign oneKHz_value$D_IN = MUX_oneKHz_value$write_1__VAL_1 ;
assign oneKHz_value$EN = 1'b1 ;
// register opcode
assign opcode$D_IN =
MUX_opcode$write_1__SEL_1 ? 9'd170 : MUX_opcode$write_1__VAL_2 ;
assign opcode$EN =
WILL_FIRE_RL_emit_mesgConsume && wsiS_reqFifo$D_OUT[57] ||
wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 && !opcode[8] ;
// register rf
assign rf$D_IN = stageF$D_OUT[15:4] ;
assign rf$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h0 ;
// register rf_1
assign rf_1$D_IN = stageF$D_OUT[15:4] ;
assign rf_1$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h0 ;
// register rf_10
assign rf_10$D_IN = stageF$D_OUT[31:20] ;
assign rf_10$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h2 ;
// register rf_11
assign rf_11$D_IN = stageF$D_OUT[31:20] ;
assign rf_11$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h2 ;
// register rf_12
assign rf_12$D_IN = stageF$D_OUT[15:4] ;
assign rf_12$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h3 ;
// register rf_13
assign rf_13$D_IN = stageF$D_OUT[15:4] ;
assign rf_13$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h3 ;
// register rf_14
assign rf_14$D_IN = stageF$D_OUT[31:20] ;
assign rf_14$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h3 ;
// register rf_15
assign rf_15$D_IN = stageF$D_OUT[31:20] ;
assign rf_15$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h3 ;
// register rf_2
assign rf_2$D_IN = stageF$D_OUT[31:20] ;
assign rf_2$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h0 ;
// register rf_3
assign rf_3$D_IN = stageF$D_OUT[31:20] ;
assign rf_3$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h0 ;
// register rf_4
assign rf_4$D_IN = stageF$D_OUT[15:4] ;
assign rf_4$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h1 ;
// register rf_5
assign rf_5$D_IN = stageF$D_OUT[15:4] ;
assign rf_5$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h1 ;
// register rf_6
assign rf_6$D_IN = stageF$D_OUT[31:20] ;
assign rf_6$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h1 ;
// register rf_7
assign rf_7$D_IN = stageF$D_OUT[31:20] ;
assign rf_7$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h1 ;
// register rf_8
assign rf_8$D_IN = stageF$D_OUT[15:4] ;
assign rf_8$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h2 ;
// register rf_9
assign rf_9$D_IN = stageF$D_OUT[15:4] ;
assign rf_9$EN =
WILL_FIRE_RL_process_staged_data && !dacControl[5] &&
srcCnt == 2'h2 ;
// register sFlagState
assign sFlagState$D_IN = 1'b0 ;
assign sFlagState$EN = 1'b0 ;
// register splitReadInFlight
assign splitReadInFlight$D_IN = 1'b0 ;
assign splitReadInFlight$EN = 1'b0 ;
// register srcCnt
assign srcCnt$D_IN = srcCnt + 2'd1 ;
assign srcCnt$EN = WILL_FIRE_RL_process_staged_data && !dacControl[5] ;
// register stageCount
assign stageCount$D_IN = stageCount + 32'd1 ;
assign stageCount$EN = dacCore0_sampF_pwEnqueue$whas ;
// register syncCount
assign syncCount$D_IN = 32'h0 ;
assign syncCount$EN = 1'b0 ;
// register takeEven
assign takeEven$D_IN = !takeEven ;
assign takeEven$EN = WILL_FIRE_RL_process_staged_data && dacControl[5] ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
assign wci_wslv_illegalEdge$EN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
MUX_wci_wslv_respF_q_0$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
MUX_wci_wslv_respF_q_0$write_1__SEL_2:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_1 or
MUX_wci_wslv_respF_q_1$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1;
MUX_wci_wslv_respF_q_1$write_1__SEL_2:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = sFlagState ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wordsConsumed
assign wordsConsumed$D_IN = wordsConsumed + 8'd1 ;
assign wordsConsumed$EN =
WILL_FIRE_RL_emit_mesgConsume && wordsConsumed != 8'd255 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'b0 ;
assign wsiS_errorSticky$EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[57] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq != WILL_FIRE_RL_emit_mesgConsume ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_emit_mesgConsume || WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wti_isReset_isInReset
assign wti_isReset_isInReset$D_IN = 1'd0 ;
assign wti_isReset_isInReset$EN = wti_isReset_isInReset ;
// register wti_nowReq
assign wti_nowReq$D_IN = wtiS0_req ;
assign wti_nowReq$EN = 1'd1 ;
// register wti_operateD
assign wti_operateD$D_IN = 1'b1 ;
assign wti_operateD$EN = 1'd1 ;
// submodule dacCore0_dcmLck_cc
assign dacCore0_dcmLck_cc$sD_IN = dacCore0_ddrSDrv_ddrV$dcmLocked ;
assign dacCore0_dcmLck_cc$sEN = 1'd1 ;
// submodule dacCore0_ddrSDrv_ddrV
assign dacCore0_ddrSDrv_ddrV$sdrData0 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData1 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData2 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData3 =
dacCore0_emit ?
MUX_dacCore0_ddrSDrv_ddrV$sdr3_1__VAL_1 :
12'd2048 ;
assign dacCore0_ddrSDrv_ddrV$sdrData4 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData5 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData6 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData7 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr7_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData8 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr6_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr8_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrData9 =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr5_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdr9_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataA =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr4_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdrA_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataB =
dacCore0_emit ?
MUX_dacCore0_ddrSDrv_ddrV$sdrB_1__VAL_1 :
12'd2048 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataC =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr2_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdrC_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataD =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr1_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdrD_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataE =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdr0_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdrE_1__VAL_2 ;
assign dacCore0_ddrSDrv_ddrV$sdrDataF =
(!dacCore0_emit) ?
MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_1 :
MUX_dacCore0_ddrSDrv_ddrV$sdrF_1__VAL_2 ;
// submodule dacCore0_emitCntCC
assign dacCore0_emitCntCC$sD_IN = dacCore0_emitCnt ;
assign dacCore0_emitCntCC$sEN = dacCore0_emitCntCC$sRDY ;
// submodule dacCore0_emitEn_d
assign dacCore0_emitEn_d$sD_IN = dacCore0_emitEn_pw$whas ;
assign dacCore0_emitEn_d$sEN = 1'd1 ;
// submodule dacCore0_iSeqDone
assign dacCore0_iSeqDone$sD_IN =
dacCore0_iseqFsm_abort_whas__60_AND_dacCore0_i_ETC___d417 &&
!dacCore0_iseqFsm_start_reg ;
assign dacCore0_iSeqDone$sEN = 1'd1 ;
// submodule dacCore0_sampF_memory
assign dacCore0_sampF_memory$ADDRA =
{ dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1013,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1015,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1014,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d987,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1003,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d988,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1016,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d990,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d989,
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d989 ^
dacCore0_sampF_rWrPtr_rsCounter[0] } ;
assign dacCore0_sampF_memory$ADDRB =
dacCore0_sampF_pwDequeue$whas ? x__h18426[9:0] : x2__h18395 ;
assign dacCore0_sampF_memory$DIA =
dacCore0_sampF_pwEnqueue$whas ?
dacCore0_sampF_wDataIn$wget :
192'd0 ;
assign dacCore0_sampF_memory$DIB =
192'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign dacCore0_sampF_memory$WEA = dacCore0_sampF_pwEnqueue$whas ;
assign dacCore0_sampF_memory$WEB = 1'd0 ;
assign dacCore0_sampF_memory$ENA = 1'd1 ;
assign dacCore0_sampF_memory$ENB = 1'd1 ;
// submodule dacCore0_startIseqF
assign dacCore0_startIseqF$sD_IN = 1'b0 ;
assign dacCore0_startIseqF$sENQ = WILL_FIRE_RL_wci_ctrl_EiI ;
assign dacCore0_startIseqF$dDEQ = 1'b0 ;
// submodule dacCore0_syncMute_obuf
assign dacCore0_syncMute_obuf$I = dacCore0_syncMute ;
// submodule dacCore0_syncOut_obuf
assign dacCore0_syncOut_obuf$I = dacCore0_syncOut ;
// submodule dacCore0_toneEn_d
assign dacCore0_toneEn_d$sD_IN = dacCore0_toneEn_pw$whas ;
assign dacCore0_toneEn_d$sEN = 1'd1 ;
// submodule dacCore0_undCountCC
assign dacCore0_undCountCC$sD_IN = dacCore0_undCount ;
assign dacCore0_undCountCC$sEN = dacCore0_undCountCC$sRDY ;
// submodule stageF
assign stageF$D_IN =
dacControl[6] ? result__h66758 : wsiS_reqFifo$D_OUT[43:12] ;
assign stageF$ENQ = WILL_FIRE_RL_emit_mesgConsume ;
assign stageF$DEQ =
WILL_FIRE_RL_process_staged_data &&
(!takeEven || !dacControl[5]) ;
assign stageF$CLR = 1'b0 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_emit_mesgConsume ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1111 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_XO_ETC___d1064 ?
IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1112 :
32'd0 ;
assign IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1112 =
(dacCore0_sampF_rRdPtr_rsCounter[0] ||
dacCore0_sampF_rRdPtr_rsCounter[1] ||
dacCore0_sampF_rRdPtr_rsCounter[2] ||
dacCore0_sampF_rRdPtr_rsCounter[3] ||
dacCore0_sampF_rRdPtr_rsCounter[4] ||
dacCore0_sampF_rRdPtr_rsCounter[5] ||
dacCore0_sampF_rRdPtr_rsCounter[6] ||
dacCore0_sampF_rRdPtr_rsCounter[7] ||
dacCore0_sampF_rRdPtr_rsCounter[8] ||
dacCore0_sampF_rRdPtr_rsCounter[9]) ?
(dacCore0_sampF_rRdPtr_rsCounter[0] ?
32'd1 :
(dacCore0_sampF_rRdPtr_rsCounter[1] ?
32'd2 :
(dacCore0_sampF_rRdPtr_rsCounter[2] ?
32'd3 :
(dacCore0_sampF_rRdPtr_rsCounter[3] ?
32'd4 :
(dacCore0_sampF_rRdPtr_rsCounter[4] ?
32'd5 :
(dacCore0_sampF_rRdPtr_rsCounter[5] ?
32'd6 :
(dacCore0_sampF_rRdPtr_rsCounter[6] ?
32'd7 :
(dacCore0_sampF_rRdPtr_rsCounter[7] ?
32'd8 :
(dacCore0_sampF_rRdPtr_rsCounter[8] ?
32'd9 :
(dacCore0_sampF_rRdPtr_rsCounter[9] ?
32'd10 :
(dacCore0_sampF_rRdPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1108 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_XO_ETC___d1063 ?
IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1109 :
32'd0 ;
assign IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1109 =
(dacCore0_sampF_rWrPtr_rsCounter[0] ||
dacCore0_sampF_rWrPtr_rsCounter[1] ||
dacCore0_sampF_rWrPtr_rsCounter[2] ||
dacCore0_sampF_rWrPtr_rsCounter[3] ||
dacCore0_sampF_rWrPtr_rsCounter[4] ||
dacCore0_sampF_rWrPtr_rsCounter[5] ||
dacCore0_sampF_rWrPtr_rsCounter[6] ||
dacCore0_sampF_rWrPtr_rsCounter[7] ||
dacCore0_sampF_rWrPtr_rsCounter[8] ||
dacCore0_sampF_rWrPtr_rsCounter[9]) ?
(dacCore0_sampF_rWrPtr_rsCounter[0] ?
32'd1 :
(dacCore0_sampF_rWrPtr_rsCounter[1] ?
32'd2 :
(dacCore0_sampF_rWrPtr_rsCounter[2] ?
32'd3 :
(dacCore0_sampF_rWrPtr_rsCounter[3] ?
32'd4 :
(dacCore0_sampF_rWrPtr_rsCounter[4] ?
32'd5 :
(dacCore0_sampF_rWrPtr_rsCounter[5] ?
32'd6 :
(dacCore0_sampF_rWrPtr_rsCounter[6] ?
32'd7 :
(dacCore0_sampF_rWrPtr_rsCounter[7] ?
32'd8 :
(dacCore0_sampF_rWrPtr_rsCounter[8] ?
32'd9 :
(dacCore0_sampF_rWrPtr_rsCounter[9] ?
32'd10 :
(dacCore0_sampF_rWrPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_OR__ETC___d1115 =
(fcDac_grayCounter_rsCounter[0] ||
fcDac_grayCounter_rsCounter[1] ||
fcDac_grayCounter_rsCounter[2] ||
fcDac_grayCounter_rsCounter[3] ||
fcDac_grayCounter_rsCounter[4] ||
fcDac_grayCounter_rsCounter[5] ||
fcDac_grayCounter_rsCounter[6] ||
fcDac_grayCounter_rsCounter[7] ||
fcDac_grayCounter_rsCounter[8] ||
fcDac_grayCounter_rsCounter[9] ||
fcDac_grayCounter_rsCounter[10] ||
fcDac_grayCounter_rsCounter[11] ||
fcDac_grayCounter_rsCounter[12] ||
fcDac_grayCounter_rsCounter[13] ||
fcDac_grayCounter_rsCounter[14]) ?
(fcDac_grayCounter_rsCounter[0] ?
32'd1 :
(fcDac_grayCounter_rsCounter[1] ?
32'd2 :
(fcDac_grayCounter_rsCounter[2] ?
32'd3 :
(fcDac_grayCounter_rsCounter[3] ?
32'd4 :
(fcDac_grayCounter_rsCounter[4] ?
32'd5 :
(fcDac_grayCounter_rsCounter[5] ?
32'd6 :
(fcDac_grayCounter_rsCounter[6] ?
32'd7 :
(fcDac_grayCounter_rsCounter[7] ?
32'd8 :
(fcDac_grayCounter_rsCounter[8] ?
32'd9 :
(fcDac_grayCounter_rsCounter[9] ?
32'd10 :
(fcDac_grayCounter_rsCounter[10] ?
32'd11 :
(fcDac_grayCounter_rsCounter[11] ?
32'd12 :
(fcDac_grayCounter_rsCounter[12] ?
32'd13 :
(fcDac_grayCounter_rsCounter[13] ?
32'd14 :
(fcDac_grayCounter_rsCounter[14] ?
32'd15 :
(fcDac_grayCounter_rsCounter[15] ?
32'd16 :
32'd17)))))))))))))))) :
32'd15 ;
assign IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_ETC___d1116 =
fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_fc_ETC___d1065 ?
IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_OR__ETC___d1115 :
32'd0 ;
assign NOT_dacCore0_sampF_rWrPtr_rsCounter_64_EQ_dacC_ETC___d1092 =
dacCore0_sampF_rWrPtr_rsCounter !=
{ dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[10],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[10] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[9],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[9] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[8],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[8] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[7],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[7] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[6],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[6] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[5],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[5] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[4],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[4] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[3],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[3] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[2],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[2] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[1],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[1] ^
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011[0] } ;
assign _theResult____h75764 =
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 :
32'd0 ;
assign dacCore0_iseqFsm_abort_whas__60_AND_dacCore0_i_ETC___d417 =
(dacCore0_iseqFsm_state_mkFSMstate == 4'd0 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd7) &&
(!dacCore0_iseqFsm_start_reg_1 || dacCore0_iseqFsm_state_fired) ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_C_ETC___d1011 =
x_dReadBin__h11074 + 11'd512 ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1000 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1027 ^
dacCore0_sampF_rRdPtr_rdCounter[5] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1001 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1000 ^
dacCore0_sampF_rRdPtr_rdCounter[4] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1002 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1009 ^
dacCore0_sampF_rRdPtr_rdCounter[1] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1008 =
dacCore0_sampF_rRdPtr_rdCounter[10] ^
dacCore0_sampF_rRdPtr_rdCounter[9] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1009 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1028 ^
dacCore0_sampF_rRdPtr_rdCounter[2] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1026 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d999 ^
dacCore0_sampF_rRdPtr_rdCounter[7] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1027 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1026 ^
dacCore0_sampF_rRdPtr_rdCounter[6] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1028 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1001 ^
dacCore0_sampF_rRdPtr_rdCounter[3] ;
assign dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d999 =
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1008 ^
dacCore0_sampF_rRdPtr_rdCounter[8] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_XO_ETC___d1064 =
z__h10248 ^ dacCore0_sampF_rRdPtr_rsCounter[10] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1004 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1018 ^
dacCore0_sampF_rRdPtr_rsCounter[2] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1010 =
dacCore0_sampF_rRdPtr_rsCounter[10] ^
dacCore0_sampF_rRdPtr_rsCounter[9] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1012 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1010 ^
dacCore0_sampF_rRdPtr_rsCounter[8] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1017 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d991 ^
dacCore0_sampF_rRdPtr_rsCounter[6] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1018 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d993 ^
dacCore0_sampF_rRdPtr_rsCounter[3] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1019 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1004 ^
dacCore0_sampF_rRdPtr_rsCounter[1] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1031 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1019 ^
dacCore0_sampF_rRdPtr_rsCounter[0] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d991 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1012 ^
dacCore0_sampF_rRdPtr_rsCounter[7] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d992 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1017 ^
dacCore0_sampF_rRdPtr_rsCounter[5] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d993 =
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d992 ^
dacCore0_sampF_rRdPtr_rsCounter[4] ;
assign dacCore0_sampF_rRdPtr_rsCounter_33_EQ_dacCore0_ETC___d1133 =
dacCore0_sampF_rRdPtr_rsCounter ==
dacCore0_sampF_rWrPtr_rdCounter ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_XO_ETC___d1063 =
z__h7946 ^ dacCore0_sampF_rWrPtr_rsCounter[10] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1003 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d987 ^
dacCore0_sampF_rWrPtr_rsCounter[5] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1013 =
dacCore0_sampF_rWrPtr_rsCounter[10] ^
dacCore0_sampF_rWrPtr_rsCounter[9] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1014 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1015 ^
dacCore0_sampF_rWrPtr_rsCounter[7] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1015 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1013 ^
dacCore0_sampF_rWrPtr_rsCounter[8] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1016 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d988 ^
dacCore0_sampF_rWrPtr_rsCounter[3] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d987 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1014 ^
dacCore0_sampF_rWrPtr_rsCounter[6] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d988 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1003 ^
dacCore0_sampF_rWrPtr_rsCounter[4] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d989 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d990 ^
dacCore0_sampF_rWrPtr_rsCounter[1] ;
assign dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d990 =
dacCore0_sampF_rWrPtr_rsCounter_64_BIT_10_90_X_ETC___d1016 ^
dacCore0_sampF_rWrPtr_rsCounter[2] ;
assign dacStatusLs__h75699 = { 26'd0, x__h75926 } ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1005 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d998 ^
fcDac_grayCounter_rdCounter[8] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1006 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d996 ^
fcDac_grayCounter_rdCounter[6] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1007 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1024 ^
fcDac_grayCounter_rdCounter[1] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1020 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1021 ^
fcDac_grayCounter_rdCounter[13] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1021 =
fcDac_grayCounter_rdCounter[15] ^
fcDac_grayCounter_rdCounter[14] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1022 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1020 ^
fcDac_grayCounter_rdCounter[12] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1023 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d997 ^
fcDac_grayCounter_rdCounter[4] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1024 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1025 ^
fcDac_grayCounter_rdCounter[2] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1025 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1023 ^
fcDac_grayCounter_rdCounter[3] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d994 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1022 ^
fcDac_grayCounter_rdCounter[11] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d995 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d994 ^
fcDac_grayCounter_rdCounter[10] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d996 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1005 ^
fcDac_grayCounter_rdCounter[7] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d997 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d1006 ^
fcDac_grayCounter_rdCounter[5] ;
assign fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d998 =
fcDac_grayCounter_rdCounter_71_BIT_15_72_XOR_f_ETC___d995 ^
fcDac_grayCounter_rdCounter[9] ;
assign fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_fc_ETC___d1065 =
z__h57468 ^ fcDac_grayCounter_rsCounter[15] ;
assign rdat__h75871 = { 24'd0, wsiS_statusR } ;
assign rdat__h75948 = { 16'd0, fcDac_frequency } ;
assign result__h66758 =
{ ~wsiS_reqFifo$D_OUT[43],
wsiS_reqFifo$D_OUT[42:28],
~wsiS_reqFifo$D_OUT[27],
wsiS_reqFifo$D_OUT[26:12] } ;
assign x2__h18395 =
{ dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1010,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1012,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d991,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1017,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d992,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d993,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1018,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1004,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1019,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1031 } ;
assign x__h18426 = x_sReadBin__h11071 + 11'd1 ;
assign x__h57357 =
16'd1 <<
IF_fcDac_grayCounter_rsCounter_81_BIT_0_88_XOR_ETC___d1116 ;
assign x__h6959 =
11'd1 <<
IF_dacCore0_sampF_rWrPtr_rsCounter_64_BIT_0_71_ETC___d1108 ;
assign x__h75926 =
{ splitReadInFlight,
initOpInFlight,
2'd2,
dacCore0_dcmLck_cc$dD_OUT,
dacCore0_iSeqDone$dD_OUT } ;
assign x__h9261 =
11'd1 <<
IF_dacCore0_sampF_rRdPtr_rsCounter_33_BIT_0_40_ETC___d1111 ;
assign x_dReadBin__h11074 =
{ dacCore0_sampF_rRdPtr_rdCounter[10],
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1008,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d999,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1026,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1027,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1000,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1001,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1028,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1009,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1002,
dacCore0_sampF_rRdPtr_rdCounter_39_BIT_10_40_X_ETC___d1002 ^
dacCore0_sampF_rRdPtr_rdCounter[0] } ;
assign x_sReadBin__h11071 =
{ dacCore0_sampF_rRdPtr_rsCounter[10],
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1010,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1012,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d991,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1017,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d992,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d993,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1018,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1004,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1019,
dacCore0_sampF_rRdPtr_rsCounter_33_BIT_10_59_X_ETC___d1031 } ;
assign y__h10148 = ~x__h9261 ;
assign y__h58614 = ~x__h57357 ;
assign y__h7846 = ~x__h6959 ;
assign z__h10192 =
dacCore0_sampF_rRdPtr_rsCounter[0] ^
dacCore0_sampF_rRdPtr_rsCounter[1] ;
assign z__h10199 = z__h10192 ^ dacCore0_sampF_rRdPtr_rsCounter[2] ;
assign z__h10206 = z__h10199 ^ dacCore0_sampF_rRdPtr_rsCounter[3] ;
assign z__h10213 = z__h10206 ^ dacCore0_sampF_rRdPtr_rsCounter[4] ;
assign z__h10220 = z__h10213 ^ dacCore0_sampF_rRdPtr_rsCounter[5] ;
assign z__h10227 = z__h10220 ^ dacCore0_sampF_rRdPtr_rsCounter[6] ;
assign z__h10234 = z__h10227 ^ dacCore0_sampF_rRdPtr_rsCounter[7] ;
assign z__h10241 = z__h10234 ^ dacCore0_sampF_rRdPtr_rsCounter[8] ;
assign z__h10248 = z__h10241 ^ dacCore0_sampF_rRdPtr_rsCounter[9] ;
assign z__h57377 =
fcDac_grayCounter_rsCounter[0] ^ fcDac_grayCounter_rsCounter[1] ;
assign z__h57384 = z__h57377 ^ fcDac_grayCounter_rsCounter[2] ;
assign z__h57391 = z__h57384 ^ fcDac_grayCounter_rsCounter[3] ;
assign z__h57398 = z__h57391 ^ fcDac_grayCounter_rsCounter[4] ;
assign z__h57405 = z__h57398 ^ fcDac_grayCounter_rsCounter[5] ;
assign z__h57412 = z__h57405 ^ fcDac_grayCounter_rsCounter[6] ;
assign z__h57419 = z__h57412 ^ fcDac_grayCounter_rsCounter[7] ;
assign z__h57426 = z__h57419 ^ fcDac_grayCounter_rsCounter[8] ;
assign z__h57433 = z__h57426 ^ fcDac_grayCounter_rsCounter[9] ;
assign z__h57440 = z__h57433 ^ fcDac_grayCounter_rsCounter[10] ;
assign z__h57447 = z__h57440 ^ fcDac_grayCounter_rsCounter[11] ;
assign z__h57454 = z__h57447 ^ fcDac_grayCounter_rsCounter[12] ;
assign z__h57461 = z__h57454 ^ fcDac_grayCounter_rsCounter[13] ;
assign z__h57468 = z__h57461 ^ fcDac_grayCounter_rsCounter[14] ;
assign z__h7890 =
dacCore0_sampF_rWrPtr_rsCounter[0] ^
dacCore0_sampF_rWrPtr_rsCounter[1] ;
assign z__h7897 = z__h7890 ^ dacCore0_sampF_rWrPtr_rsCounter[2] ;
assign z__h7904 = z__h7897 ^ dacCore0_sampF_rWrPtr_rsCounter[3] ;
assign z__h7911 = z__h7904 ^ dacCore0_sampF_rWrPtr_rsCounter[4] ;
assign z__h7918 = z__h7911 ^ dacCore0_sampF_rWrPtr_rsCounter[5] ;
assign z__h7925 = z__h7918 ^ dacCore0_sampF_rWrPtr_rsCounter[6] ;
assign z__h7932 = z__h7925 ^ dacCore0_sampF_rWrPtr_rsCounter[7] ;
assign z__h7939 = z__h7932 ^ dacCore0_sampF_rWrPtr_rsCounter[8] ;
assign z__h7946 = z__h7939 ^ dacCore0_sampF_rWrPtr_rsCounter[9] ;
always@(wci_wslv_reqF$D_OUT or
rdat__h75871 or
dacStatusLs__h75699 or
dacControl or
rdat__h75948 or
dacCore0_emitCntCC$dD_OUT or
firstUnderflowMesg or
syncCount or
mesgStart or
dacCore0_undCountCC$dD_OUT or stageCount or wsiS_extStatusW$wget)
begin
case (wci_wslv_reqF$D_OUT[39:32])
8'h0:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
rdat__h75871;
8'h04:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
dacStatusLs__h75699;
8'h0C:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 = dacControl;
8'h10:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
rdat__h75948;
8'h14:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
dacCore0_emitCntCC$dD_OUT;
8'h24:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
firstUnderflowMesg;
8'h30:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 = syncCount;
8'h34:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 = mesgStart;
8'h38:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
dacCore0_undCountCC$dD_OUT;
8'h3C:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 = stageCount;
8'h48:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
wsiS_extStatusW$wget[95:64];
8'h4C:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
wsiS_extStatusW$wget[63:32];
8'h50:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 =
wsiS_extStatusW$wget[31:0];
default: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_r_ETC__q1 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
dacControl <= `BSV_ASSIGNMENT_DELAY 32'h00000008;
dacCore0_dacCtrl_w <= `BSV_ASSIGNMENT_DELAY 4'h8;
fcDac_countNow <= `BSV_ASSIGNMENT_DELAY 16'd65535;
fcDac_countPast <= `BSV_ASSIGNMENT_DELAY 16'd65535;
fcDac_frequency <= `BSV_ASSIGNMENT_DELAY 16'd65535;
fcDac_pulseAction <= `BSV_ASSIGNMENT_DELAY 1'd0;
fcDac_sampleCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
firstUnderflowMesg <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
hasUnderflowed <= `BSV_ASSIGNMENT_DELAY 1'd0;
initOpInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
mesgStart <= `BSV_ASSIGNMENT_DELAY 32'd0;
oneKHz_value <= `BSV_ASSIGNMENT_DELAY 18'd0;
opcode <= `BSV_ASSIGNMENT_DELAY 9'd170;
rf <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_1 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_10 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_11 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_12 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_13 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_14 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_15 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_2 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_3 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_4 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_5 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_6 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_7 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_8 <= `BSV_ASSIGNMENT_DELAY 12'd0;
rf_9 <= `BSV_ASSIGNMENT_DELAY 12'd0;
sFlagState <= `BSV_ASSIGNMENT_DELAY 1'd0;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
srcCnt <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
syncCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
takeEven <= `BSV_ASSIGNMENT_DELAY 1'd1;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wordsConsumed <= `BSV_ASSIGNMENT_DELAY 8'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (dacControl$EN)
dacControl <= `BSV_ASSIGNMENT_DELAY dacControl$D_IN;
if (dacCore0_dacCtrl_w$EN)
dacCore0_dacCtrl_w <= `BSV_ASSIGNMENT_DELAY dacCore0_dacCtrl_w$D_IN;
if (fcDac_countNow$EN)
fcDac_countNow <= `BSV_ASSIGNMENT_DELAY fcDac_countNow$D_IN;
if (fcDac_countPast$EN)
fcDac_countPast <= `BSV_ASSIGNMENT_DELAY fcDac_countPast$D_IN;
if (fcDac_frequency$EN)
fcDac_frequency <= `BSV_ASSIGNMENT_DELAY fcDac_frequency$D_IN;
if (fcDac_pulseAction$EN)
fcDac_pulseAction <= `BSV_ASSIGNMENT_DELAY fcDac_pulseAction$D_IN;
if (fcDac_sampleCount$EN)
fcDac_sampleCount <= `BSV_ASSIGNMENT_DELAY fcDac_sampleCount$D_IN;
if (firstUnderflowMesg$EN)
firstUnderflowMesg <= `BSV_ASSIGNMENT_DELAY firstUnderflowMesg$D_IN;
if (hasUnderflowed$EN)
hasUnderflowed <= `BSV_ASSIGNMENT_DELAY hasUnderflowed$D_IN;
if (initOpInFlight$EN)
initOpInFlight <= `BSV_ASSIGNMENT_DELAY initOpInFlight$D_IN;
if (mesgStart$EN) mesgStart <= `BSV_ASSIGNMENT_DELAY mesgStart$D_IN;
if (oneKHz_value$EN)
oneKHz_value <= `BSV_ASSIGNMENT_DELAY oneKHz_value$D_IN;
if (opcode$EN) opcode <= `BSV_ASSIGNMENT_DELAY opcode$D_IN;
if (rf$EN) rf <= `BSV_ASSIGNMENT_DELAY rf$D_IN;
if (rf_1$EN) rf_1 <= `BSV_ASSIGNMENT_DELAY rf_1$D_IN;
if (rf_10$EN) rf_10 <= `BSV_ASSIGNMENT_DELAY rf_10$D_IN;
if (rf_11$EN) rf_11 <= `BSV_ASSIGNMENT_DELAY rf_11$D_IN;
if (rf_12$EN) rf_12 <= `BSV_ASSIGNMENT_DELAY rf_12$D_IN;
if (rf_13$EN) rf_13 <= `BSV_ASSIGNMENT_DELAY rf_13$D_IN;
if (rf_14$EN) rf_14 <= `BSV_ASSIGNMENT_DELAY rf_14$D_IN;
if (rf_15$EN) rf_15 <= `BSV_ASSIGNMENT_DELAY rf_15$D_IN;
if (rf_2$EN) rf_2 <= `BSV_ASSIGNMENT_DELAY rf_2$D_IN;
if (rf_3$EN) rf_3 <= `BSV_ASSIGNMENT_DELAY rf_3$D_IN;
if (rf_4$EN) rf_4 <= `BSV_ASSIGNMENT_DELAY rf_4$D_IN;
if (rf_5$EN) rf_5 <= `BSV_ASSIGNMENT_DELAY rf_5$D_IN;
if (rf_6$EN) rf_6 <= `BSV_ASSIGNMENT_DELAY rf_6$D_IN;
if (rf_7$EN) rf_7 <= `BSV_ASSIGNMENT_DELAY rf_7$D_IN;
if (rf_8$EN) rf_8 <= `BSV_ASSIGNMENT_DELAY rf_8$D_IN;
if (rf_9$EN) rf_9 <= `BSV_ASSIGNMENT_DELAY rf_9$D_IN;
if (sFlagState$EN)
sFlagState <= `BSV_ASSIGNMENT_DELAY sFlagState$D_IN;
if (splitReadInFlight$EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
if (srcCnt$EN) srcCnt <= `BSV_ASSIGNMENT_DELAY srcCnt$D_IN;
if (stageCount$EN)
stageCount <= `BSV_ASSIGNMENT_DELAY stageCount$D_IN;
if (syncCount$EN) syncCount <= `BSV_ASSIGNMENT_DELAY syncCount$D_IN;
if (takeEven$EN) takeEven <= `BSV_ASSIGNMENT_DELAY takeEven$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wordsConsumed$EN)
wordsConsumed <= `BSV_ASSIGNMENT_DELAY wordsConsumed$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
always@(posedge CLK_dac_clk)
begin
if (RST_N_dac_rst == `BSV_RESET_VALUE)
begin
wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wti_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wti_nowReq$EN)
wti_nowReq <= `BSV_ASSIGNMENT_DELAY wti_nowReq$D_IN;
if (wti_operateD$EN)
wti_operateD <= `BSV_ASSIGNMENT_DELAY wti_operateD$D_IN;
end
end
always@(posedge dacCore0_ddrSDrv_ddrV$sdrClk)
begin
if (dacCore0_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
dacCore0_calBit <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_emit <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_emitCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
dacCore0_emitD <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 13'd0;
dacCore0_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
dacCore0_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
dacCore0_muteDAC <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_syncMute <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_syncOut <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_tone <= `BSV_ASSIGNMENT_DELAY 1'd0;
dacCore0_undCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (dacCore0_calBit$EN)
dacCore0_calBit <= `BSV_ASSIGNMENT_DELAY dacCore0_calBit$D_IN;
if (dacCore0_emit$EN)
dacCore0_emit <= `BSV_ASSIGNMENT_DELAY dacCore0_emit$D_IN;
if (dacCore0_emitCnt$EN)
dacCore0_emitCnt <= `BSV_ASSIGNMENT_DELAY dacCore0_emitCnt$D_IN;
if (dacCore0_emitD$EN)
dacCore0_emitD <= `BSV_ASSIGNMENT_DELAY dacCore0_emitD$D_IN;
if (dacCore0_iseqFsm_jj_delay_count$EN)
dacCore0_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_jj_delay_count$D_IN;
if (dacCore0_iseqFsm_start_reg$EN)
dacCore0_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_start_reg$D_IN;
if (dacCore0_iseqFsm_start_reg_1$EN)
dacCore0_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_start_reg_1$D_IN;
if (dacCore0_iseqFsm_state_can_overlap$EN)
dacCore0_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_state_can_overlap$D_IN;
if (dacCore0_iseqFsm_state_fired$EN)
dacCore0_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_state_fired$D_IN;
if (dacCore0_iseqFsm_state_mkFSMstate$EN)
dacCore0_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
dacCore0_iseqFsm_state_mkFSMstate$D_IN;
if (dacCore0_muteDAC$EN)
dacCore0_muteDAC <= `BSV_ASSIGNMENT_DELAY dacCore0_muteDAC$D_IN;
if (dacCore0_syncMute$EN)
dacCore0_syncMute <= `BSV_ASSIGNMENT_DELAY dacCore0_syncMute$D_IN;
if (dacCore0_syncOut$EN)
dacCore0_syncOut <= `BSV_ASSIGNMENT_DELAY dacCore0_syncOut$D_IN;
if (dacCore0_tone$EN)
dacCore0_tone <= `BSV_ASSIGNMENT_DELAY dacCore0_tone$D_IN;
if (dacCore0_undCount$EN)
dacCore0_undCount <= `BSV_ASSIGNMENT_DELAY dacCore0_undCount$D_IN;
end
if (dacCore0_dacCount$EN)
dacCore0_dacCount <= `BSV_ASSIGNMENT_DELAY dacCore0_dacCount$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
dacCore0_ddrSDrv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
dacCore0_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
dacCore0_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
dacCore0_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
fcDac_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY 16'd0;
fcDac_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (dacCore0_ddrSDrv_isReset_isInReset$EN)
dacCore0_ddrSDrv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
dacCore0_ddrSDrv_isReset_isInReset$D_IN;
if (dacCore0_sampF_rRdPtr_rdCounter$EN)
dacCore0_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rRdPtr_rdCounter$D_IN;
if (dacCore0_sampF_rRdPtr_rdCounterPre$EN)
dacCore0_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rRdPtr_rdCounterPre$D_IN;
if (dacCore0_sampF_rWrPtr_rsCounter$EN)
dacCore0_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rWrPtr_rsCounter$D_IN;
if (fcDac_grayCounter_rdCounter$EN)
fcDac_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY
fcDac_grayCounter_rdCounter$D_IN;
if (fcDac_grayCounter_rdCounterPre$EN)
fcDac_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
fcDac_grayCounter_rdCounterPre$D_IN;
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wsiS_isReset_isInReset$EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset$D_IN;
end
always@(posedge CLK_dac_clk or `BSV_RESET_EDGE RST_N_dac_rst)
if (RST_N_dac_rst == `BSV_RESET_VALUE)
begin
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wti_isReset_isInReset$EN)
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wti_isReset_isInReset$D_IN;
end
always@(posedge dacCore0_ddrSDrv_ddrV$sdrClk or
`BSV_RESET_EDGE fcDac_testRst$OUT_RST)
if (fcDac_testRst$OUT_RST == `BSV_RESET_VALUE)
begin
fcDac_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY 16'd0;
end
else
begin
if (fcDac_grayCounter_rsCounter$EN)
fcDac_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY
fcDac_grayCounter_rsCounter$D_IN;
end
always@(posedge dacCore0_ddrSDrv_ddrV$sdrClk or
`BSV_RESET_EDGE dacCore0_sdrRst$OUT_RST)
if (dacCore0_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
dacCore0_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
dacCore0_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
dacCore0_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
end
else
begin
if (dacCore0_sampF_rRdPtr_rsCounter$EN)
dacCore0_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rRdPtr_rsCounter$D_IN;
if (dacCore0_sampF_rWrPtr_rdCounter$EN)
dacCore0_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rWrPtr_rdCounter$D_IN;
if (dacCore0_sampF_rWrPtr_rdCounterPre$EN)
dacCore0_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
dacCore0_sampF_rWrPtr_rdCounterPre$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
dacControl = 32'hAAAAAAAA;
dacCore0_calBit = 1'h0;
dacCore0_dacCount = 8'hAA;
dacCore0_dacCtrl_w = 4'hA;
dacCore0_ddrSDrv_isReset_isInReset = 1'h0;
dacCore0_emit = 1'h0;
dacCore0_emitCnt = 32'hAAAAAAAA;
dacCore0_emitD = 1'h0;
dacCore0_iseqFsm_jj_delay_count = 13'h0AAA;
dacCore0_iseqFsm_start_reg = 1'h0;
dacCore0_iseqFsm_start_reg_1 = 1'h0;
dacCore0_iseqFsm_state_can_overlap = 1'h0;
dacCore0_iseqFsm_state_fired = 1'h0;
dacCore0_iseqFsm_state_mkFSMstate = 4'hA;
dacCore0_muteDAC = 1'h0;
dacCore0_sampF_rRdPtr_rdCounter = 11'h2AA;
dacCore0_sampF_rRdPtr_rdCounterPre = 11'h2AA;
dacCore0_sampF_rRdPtr_rsCounter = 11'h2AA;
dacCore0_sampF_rWrPtr_rdCounter = 11'h2AA;
dacCore0_sampF_rWrPtr_rdCounterPre = 11'h2AA;
dacCore0_sampF_rWrPtr_rsCounter = 11'h2AA;
dacCore0_syncMute = 1'h0;
dacCore0_syncOut = 1'h0;
dacCore0_tone = 1'h0;
dacCore0_undCount = 32'hAAAAAAAA;
fcDac_countNow = 16'hAAAA;
fcDac_countPast = 16'hAAAA;
fcDac_frequency = 16'hAAAA;
fcDac_grayCounter_rdCounter = 16'hAAAA;
fcDac_grayCounter_rdCounterPre = 16'hAAAA;
fcDac_grayCounter_rsCounter = 16'hAAAA;
fcDac_pulseAction = 1'h0;
fcDac_sampleCount = 16'hAAAA;
firstUnderflowMesg = 32'hAAAAAAAA;
hasUnderflowed = 1'h0;
initOpInFlight = 1'h0;
mesgStart = 32'hAAAAAAAA;
oneKHz_value = 18'h2AAAA;
opcode = 9'h0AA;
rf = 12'hAAA;
rf_1 = 12'hAAA;
rf_10 = 12'hAAA;
rf_11 = 12'hAAA;
rf_12 = 12'hAAA;
rf_13 = 12'hAAA;
rf_14 = 12'hAAA;
rf_15 = 12'hAAA;
rf_2 = 12'hAAA;
rf_3 = 12'hAAA;
rf_4 = 12'hAAA;
rf_5 = 12'hAAA;
rf_6 = 12'hAAA;
rf_7 = 12'hAAA;
rf_8 = 12'hAAA;
rf_9 = 12'hAAA;
sFlagState = 1'h0;
splitReadInFlight = 1'h0;
srcCnt = 2'h2;
stageCount = 32'hAAAAAAAA;
syncCount = 32'hAAAAAAAA;
takeEven = 1'h0;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wordsConsumed = 8'hAA;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
wti_isReset_isInReset = 1'h0;
wti_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wti_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3702 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3702,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h75780 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h75780,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
_theResult____h75764);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h75623 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h75623,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
wci_wslv_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DACWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4021 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4021,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3877 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3877,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
// synopsys translate_off
always@(negedge dacCore0_ddrSDrv_ddrV$sdrClk)
begin
#0;
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (dacCore0_iseqFsm_state_mkFSMstate == 4'd1 &&
(WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13))
$display("Error: \"bsv/dev/Max19692.bsv\", line 101, column 13: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_dacCore0_iseqFsm_action_l101c13] and\n [RL_dacCore0_iseqFsm_action_l102c10, RL_dacCore0_iseqFsm_action_l103c13,\n RL_dacCore0_iseqFsm_action_d_init_np, RL_dacCore0_iseqFsm_action_np,\n RL_dacCore0_iseqFsm_action_l105c13] ) fired in the same clock cycle.\n");
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13))
$display("Error: \"bsv/dev/Max19692.bsv\", line 102, column 10: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_dacCore0_iseqFsm_action_l102c10] and\n [RL_dacCore0_iseqFsm_action_l103c13, RL_dacCore0_iseqFsm_action_d_init_np,\n RL_dacCore0_iseqFsm_action_np, RL_dacCore0_iseqFsm_action_l105c13] ) fired\n in the same clock cycle.\n");
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (dacCore0_iseqFsm_state_mkFSMstate == 4'd3 &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13))
$display("Error: \"bsv/dev/Max19692.bsv\", line 103, column 13: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_dacCore0_iseqFsm_action_l103c13] and\n [RL_dacCore0_iseqFsm_action_d_init_np, RL_dacCore0_iseqFsm_action_np,\n RL_dacCore0_iseqFsm_action_l105c13] ) fired in the same clock cycle.\n");
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (dacCore0_iseqFsm_state_mkFSMstate == 4'd4 &&
(WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_dacCore0_iseqFsm_action_d_init_np] and [RL_dacCore0_iseqFsm_action_np,\n RL_dacCore0_iseqFsm_action_l105c13] ) fired in the same clock cycle.\n");
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dacCore0_iseqFsm_action_np &&
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13)
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_dacCore0_iseqFsm_action_np]\n and [RL_dacCore0_iseqFsm_action_l105c13] ) fired in the same clock cycle.\n");
if (dacCore0_sdrRst$OUT_RST != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dacCore0_iseqFsm_action_l100c13 &&
(dacCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l102c10 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
dacCore0_iseqFsm_state_mkFSMstate == 4'd4 ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_np ||
WILL_FIRE_RL_dacCore0_iseqFsm_action_l105c13))
$display("Error: \"bsv/dev/Max19692.bsv\", line 100, column 13: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_dacCore0_iseqFsm_action_l100c13] and\n [RL_dacCore0_iseqFsm_action_l101c13, RL_dacCore0_iseqFsm_action_l102c10,\n RL_dacCore0_iseqFsm_action_l103c13, RL_dacCore0_iseqFsm_action_d_init_np,\n RL_dacCore0_iseqFsm_action_np, RL_dacCore0_iseqFsm_action_l105c13] ) fired\n in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkDACWorker
|
// =================================================
//
// ================ HPS FPGA ====================
//
// =================================================
`define ENABLE_HPS
module HPSFPGA(
///////// ADC /////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
///////// ARDUINO /////////
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`ifdef ENABLE_CLK
///////// CLK /////////
output CLK_I2C_SCL,
inout CLK_I2C_SDA,
`endif //ENABLE_CLK
///////// FPGA /////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif // ENABLE_HPS
///////// KEY /////////
input [1:0] KEY,
///////// LED /////////
output [7:0] LED,
///////// SW /////////
input [3:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire hps_fpga_reset_n;
//=======================================================
// Structural coding
//=======================================================
soc_system u0 (
//Clock & Reset
.clk_clk ( FPGA_CLK1_50 ),
.reset_reset_n ( 1'b1 ),
//HPS ddr3
.memory_mem_a ( HPS_DDR3_ADDR ),
.memory_mem_ba ( HPS_DDR3_BA ),
.memory_mem_ck ( HPS_DDR3_CK_P ),
.memory_mem_ck_n ( HPS_DDR3_CK_N ),
.memory_mem_cke ( HPS_DDR3_CKE ),
.memory_mem_cs_n ( HPS_DDR3_CS_N ),
.memory_mem_ras_n ( HPS_DDR3_RAS_N ),
.memory_mem_cas_n ( HPS_DDR3_CAS_N ),
.memory_mem_we_n ( HPS_DDR3_WE_N ),
.memory_mem_reset_n ( HPS_DDR3_RESET_N ),
.memory_mem_dq ( HPS_DDR3_DQ ),
.memory_mem_dqs ( HPS_DDR3_DQS_P ),
.memory_mem_dqs_n ( HPS_DDR3_DQS_N ),
.memory_mem_odt ( HPS_DDR3_ODT ),
.memory_mem_dm ( HPS_DDR3_DM ),
.memory_oct_rzqin ( HPS_DDR3_RZQ ),
//HPS ethernet
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK ),
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ),
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ),
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ),
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV ),
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN ),
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK ),
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ),
//HPS SD card
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ),
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ),
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ),
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ),
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ),
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ),
//HPS USB
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ),
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ),
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ),
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ),
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ),
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ),
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ),
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ),
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ),
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ),
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ),
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ),
//HPS SPI
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ),
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ),
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ),
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ),
//HPS UART
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ),
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ),
//HPS I2C1
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C0_SDAT ),
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C0_SCLK ),
//HPS I2C2
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C1_SDAT ),
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C1_SCLK ),
//FPGA Partion
.custom_leds_0_leds_leds ( LED ),
.dipsw_pio_external_connection_export ( SW ),
.button_pio_external_connection_export ( KEY ),
.hps_0_h2f_reset_reset_n ( hps_fpga_reset_n )
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_rdmatctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sctag.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module sctag_rdmatctl( /*AUTOARG*/
// Outputs
rdmat_wr_entry_s1, or_rdmat_valid, rdmat_pick_vec,
rdmatctl_hit_unqual_c2, rdmatctl_mbctl_dep_rdy_en,
rdmatctl_mbctl_dep_mbid, rdmat_wr_wl_s2, sctag_scbuf_fbwr_wl_r2,
sctag_scbuf_fbrd_en_c3, sctag_scbuf_fbrd_wl_c3,
sctag_scbuf_word_vld_c7, sctag_scbuf_ctag_en_c7,
sctag_scbuf_req_en_c7, sctag_scbuf_word_c7, rdmard_cerr_c12,
rdmard_uerr_c12, ev_uerr_r6, ev_cerr_r6, so,
sctag_scbuf_fbwr_wen_r2, sctag_scbuf_fbd_stdatasel_c3,
sctag_scbuf_ctag_c7,
// Inputs
rdmatag_wr_en_s2, reset_rdmat_vld, set_rdmat_acked,
rdmat_cam_match_c2, arbctl_wbctl_inst_vld_c2,
arbctl_wbctl_hit_off_c1, arbdp_rdma_entry_c3, mbctl_wbctl_mbid_c4,
mbctl_hit_c4, tagctl_rdma_ev_en_c4, scbuf_fbd_stdatasel_c3,
scbuf_fbwr_wen_r2, rst_tri_en, arst_l, grst_l, rclk, si, se,
scbuf_sctag_rdma_cerr_c10, scbuf_sctag_rdma_uerr_c10,
scbuf_sctag_ev_uerr_r5, scbuf_sctag_ev_cerr_r5, arbdec_ctag_c6,
tagctl_inc_rdma_cnt_c4, tagctl_set_rdma_reg_vld_c4,
tagctl_jbi_req_en_c6, arbdp_rdmatctl_addr_c6, fbctl_fbd_rd_en_c2,
fbctl_fbd_rd_entry_c2, fbctl_fbd_wr_entry_r1
);
output [1:0] rdmat_wr_entry_s1; // to snp ctl.
output or_rdmat_valid; // to wbctl
output [3:0] rdmat_pick_vec; // to wbctl
output rdmatctl_hit_unqual_c2 ; // to mbctl
output rdmatctl_mbctl_dep_rdy_en;// to mbctl
output [3:0] rdmatctl_mbctl_dep_mbid; // to mbctl
output [3:0] rdmat_wr_wl_s2;
output [2:0] sctag_scbuf_fbwr_wl_r2; // NEW_PIN
output sctag_scbuf_fbrd_en_c3; // NEW_PIN
output [2:0] sctag_scbuf_fbrd_wl_c3; // NEW_PIN
output sctag_scbuf_word_vld_c7; // NEW_PIN
output sctag_scbuf_ctag_en_c7; // NEW_PIN
output sctag_scbuf_req_en_c7; // NEW_PIN
output [3:0] sctag_scbuf_word_c7; // NEW_PIN
output rdmard_cerr_c12, rdmard_uerr_c12; // NEW_PIN
output ev_uerr_r6, ev_cerr_r6; // NEW_PIN
output so;
input rdmatag_wr_en_s2 ; // from snpctl.
input [3:0] reset_rdmat_vld; // comes from wbctl
input [3:0] set_rdmat_acked; // from wbctl
input [3:0] rdmat_cam_match_c2; // from cm2
input arbctl_wbctl_inst_vld_c2 ; // from arbctl.
input arbctl_wbctl_hit_off_c1 ; // from arbctl.
input [1:0] arbdp_rdma_entry_c3; // mbid
input [3:0] mbctl_wbctl_mbid_c4; // mbctl
input mbctl_hit_c4; // mbctl
input tagctl_rdma_ev_en_c4; // generated in tagctl;
input scbuf_fbd_stdatasel_c3;
input [15:0] scbuf_fbwr_wen_r2;
output [15:0] sctag_scbuf_fbwr_wen_r2 ;
output sctag_scbuf_fbd_stdatasel_c3 ;
input rst_tri_en ;
input arst_l;
input grst_l;
input rclk;
input si, se;
// from scbuf
input scbuf_sctag_rdma_cerr_c10; // NEW_PIN
input scbuf_sctag_rdma_uerr_c10; // NEW_PIN
// from scbuf
input scbuf_sctag_ev_uerr_r5; // NEW_PIN
input scbuf_sctag_ev_cerr_r5; // NEW_PIN
input [14:0] arbdec_ctag_c6; // NEW_PIN POST_3.3 Bottom
output [14:0] sctag_scbuf_ctag_c7; // NEW_PIN POST_3.3 TOp
// from tagctl.
input tagctl_inc_rdma_cnt_c4; // NEW_PIN
input tagctl_set_rdma_reg_vld_c4 ; // NEW_PIN
input tagctl_jbi_req_en_c6; // NEW_PIN
// from arbaddr
input [5:2] arbdp_rdmatctl_addr_c6; // NEW_PIN
// from fbctl
input fbctl_fbd_rd_en_c2; // rd en for fbdata NEW_PIN
input [2:0] fbctl_fbd_rd_entry_c2; // rd entry for fbdata NEW_PIN
input [2:0] fbctl_fbd_wr_entry_r1; // entry for fbdata wr NEW_PIN
wire jbi_req_en_c7;
wire inc_rdma_cnt_c5, inc_rdma_cnt_c6, inc_rdma_cnt_c7 ;
wire set_rdma_reg_vld_c5 , set_rdma_reg_vld_c6, set_rdma_reg_vld_c7 ;
wire [3:0] rdma_state_in, rdma_state_plus1 , rdma_state ;
wire inc_state_en;
wire rdma_state_en;
wire [3:0] rdma_wr_ptr_s1, rdma_wr_ptr_s2;
wire [3:0] rdma_valid_prev, rdma_valid ;
wire [3:0] rdma_cam_hit_vec_c2, rdma_cam_hit_vec_c3, rdma_cam_hit_vec_c4;
wire rdmatctl_hit_qual_c2, rdmatctl_hit_qual_c3, rdmatctl_hit_qual_c4;
wire mbid_wr_en ;
wire [3:0] sel_insert_mbid_c4;
wire [3:0] mbid0, mbid1, mbid2, mbid3;
wire [3:0] rdma_mbid_vld_in, rdma_mbid_vld ;
wire [3:0] sel_mbid;
wire sel_def_mbid;
wire [3:0] enc_mbid;
wire [3:0] rdma_acked_in, rdma_acked;
wire [3:0] rdma_dram_req_in, rdma_dram_req ;
wire [3:0] noalloc_evict_dram_c4;
wire or_rdma_mbid_vld;
wire [1:0] rdma_entry_c4;
wire arbctl_wbctl_hit_off_c2;
wire [3:0] sel_mbid_rst;
wire dbb_rst_l;
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
assign sctag_scbuf_fbd_stdatasel_c3 = scbuf_fbd_stdatasel_c3 ;
assign sctag_scbuf_fbwr_wen_r2 = scbuf_fbwr_wen_r2 ;
//assign jbi_req_vld_buf = jbi_sctag_req_vld;
//assign jbi_req_buf = jbi_sctag_req;
/////////////////////////////////////////
// Repeater for ctag from arbdec.
/////////////////////////////////////////
dff_s #(15) ff_sctag_scbuf_ctag_c7 (.din(arbdec_ctag_c6[14:0]), .clk(rclk),
.q(sctag_scbuf_ctag_c7[14:0]), .se(se), .si(), .so());
/////////////////////////////////////////
// Generating the wr ptr for rdmat
/////////////////////////////////////////
assign rdma_wr_ptr_s1[0] = ~rdma_valid[0] ;
assign rdma_wr_ptr_s1[1] = rdma_valid[0] & ~rdma_valid[1];
assign rdma_wr_ptr_s1[2] = (rdma_valid[0] & rdma_valid[1]) & ~rdma_valid[2] ;
assign rdma_wr_ptr_s1[3] = ( rdma_valid[0] & rdma_valid[1] & rdma_valid[2])
& ~rdma_valid[3] ;
assign rdmat_wr_entry_s1[0] = ( rdma_wr_ptr_s1[1] | rdma_wr_ptr_s1[3] ) ;
assign rdmat_wr_entry_s1[1] = ( rdma_wr_ptr_s1[2] | rdma_wr_ptr_s1[3] ) ;
dff_s #(4) ff_rdma_wr_ptr_s2 (.din(rdma_wr_ptr_s1[3:0]), .clk(rclk),
.q(rdma_wr_ptr_s2[3:0]), .se(se), .si(), .so());
assign rdmat_wr_wl_s2 = rdma_wr_ptr_s2 ;
///////////////////////////////////////////////////////////////////
// Pipeline for setting and resetting the valid bits
// for the rdmat
//
// Set Pipeline.
//-----------------------------------------------------------------
// S1 S2 S3
//-----------------------------------------------------------------
// xmit wr entry snpctl
// pick to generates
// snpctl rdmat/rdmad vld=1
// wren and wrwl
//
//
// set valid bit
//-----------------------------------------------------------------
//
//
// Reset Pipeline
//-----------------------------------------------------------------
// R0 R5 ..... R11 R12
//-----------------------------------------------------------------
// evict evict evict
// data1 data7 data8
//
// reset valid=0
// valid.
//-----------------------------------------------------------------
///////////////////////////////////////////////////////////////////
assign rdma_valid_prev = ( rdma_wr_ptr_s2 & {4{rdmatag_wr_en_s2}}
| rdma_valid )
& ~reset_rdmat_vld ;
dffrl_s #(4) ff_valid_bit (.din(rdma_valid_prev[3:0]), .clk(rclk),
.rst_l(dbb_rst_l),
.q(rdma_valid[3:0]), .se(se), .si(), .so());
////////////////////////////////////////////////////////////////////
// Hit calculation.
// RDMA hit is asserted only under the following conditions.
// wb_valid = 1
// wb_dram_req = 1 => that the Wr64 corresponding to that entry
// has cleared all dependencies and successfully
// completed an issue down the pipe.
// wb_acked = 1 => an ack was received for the Wr req sent to
// dram.
////////////////////////////////////////////////////////////////////
dff_s #(1) ff_arbctl_wbctl_hit_off_c2
(.q (arbctl_wbctl_hit_off_c2),
.din (arbctl_wbctl_hit_off_c1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign rdma_cam_hit_vec_c2 = ( rdmat_cam_match_c2 &
rdma_valid & rdma_dram_req &
~( rdma_acked | {4{arbctl_wbctl_hit_off_c2}} ) );
assign rdmatctl_hit_unqual_c2 = |( rdma_cam_hit_vec_c2 ) ;
dff_s #(4) ff_rdma_cam_hit_vec_c3
(.q (rdma_cam_hit_vec_c3[3:0]),
.din (rdma_cam_hit_vec_c2[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_rdma_cam_hit_vec_c4
(.q (rdma_cam_hit_vec_c4[3:0]),
.din (rdma_cam_hit_vec_c3[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign rdmatctl_hit_qual_c2 = rdmatctl_hit_unqual_c2 &
arbctl_wbctl_inst_vld_c2 ;
dff_s #(1) ff_rdmatctl_hit_qual_c3
(.q (rdmatctl_hit_qual_c3),
.din (rdmatctl_hit_qual_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_rdmatctl_hit_qual_c4
(.q (rdmatctl_hit_qual_c4),
.din (rdmatctl_hit_qual_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// MBID and MBID_vld.
// Written in the C4 cycle of a non-dependent instruction that hits
// the rdma buffer.
//
// When an ack is received from DRAM for the entry with mbid_vld,
// the corresponding mbid is used to wake up the miss buffer entry
// that depends on the write.The ack may be received when the instruction
// is in flight i.e in C2, C3 otr C4 and yet to set mbid vld. But that is
// okay since the "acked" bit can only be set for one entry in the WBB at
// a time.
// MBID_vld is reset when an entry has mbid_vld =1 and acked=1
//
////////////////////////////////////////////////////////////////////////////////
assign mbid_wr_en = rdmatctl_hit_qual_c4 & ~mbctl_hit_c4;
assign sel_insert_mbid_c4 = {4{mbid_wr_en}} & rdma_cam_hit_vec_c4 ;
dffe_s #(4) ff_mbid0 (.din( mbctl_wbctl_mbid_c4[3:0]),
.en(sel_insert_mbid_c4[0]),
.clk(rclk), .q(mbid0[3:0]), .se(se), .si(), .so());
dffe_s #(4) ff_mbid1 (.din(mbctl_wbctl_mbid_c4[3:0]),
.en(sel_insert_mbid_c4[1]),
.clk(rclk), .q(mbid1[3:0]), .se(se), .si(), .so());
dffe_s #(4) ff_mbid2 (.din(mbctl_wbctl_mbid_c4[3:0]),
.en(sel_insert_mbid_c4[2]),
.clk(rclk), .q(mbid2[3:0]), .se(se), .si(), .so());
dffe_s #(4) ff_mbid3 (.din(mbctl_wbctl_mbid_c4[3:0]),
.en(sel_insert_mbid_c4[3]),
.clk(rclk), .q(mbid3[3:0]), .se(se), .si(), .so());
assign rdma_mbid_vld_in = ( rdma_mbid_vld | sel_insert_mbid_c4 ) &
~(sel_mbid[3:0]) ;
dffrl_s #(4) ff_rdma_mbid_vld (.din(rdma_mbid_vld_in[3:0]),
.clk(rclk),.rst_l(dbb_rst_l),
.q(rdma_mbid_vld[3:0]), .se(se), .si(), .so());
///////////////////////////////////////////////////////////////////
// Mbf dependent Ready logic.
///////////////////////////////////////////////////////////////////
assign sel_mbid = rdma_acked & rdma_mbid_vld ;
assign sel_def_mbid = ~( sel_mbid[2] | sel_mbid[1] | sel_mbid[0] ) ;
assign sel_mbid_rst[0] = sel_mbid[0] & ~rst_tri_en ;
assign sel_mbid_rst[1] = sel_mbid[1] & ~rst_tri_en ;
assign sel_mbid_rst[2] = sel_mbid[2] & ~rst_tri_en ;
assign sel_mbid_rst[3] = (sel_def_mbid | rst_tri_en ) ;
mux4ds #(4) rdma_mb_mbid (.dout (enc_mbid[3:0]),
.in0(mbid0[3:0]), .in1(mbid1[3:0]),
.in2(mbid2[3:0]), .in3(mbid3[3:0]),
.sel0(sel_mbid_rst[0]), .sel1(sel_mbid_rst[1]),
.sel2(sel_mbid_rst[2]), .sel3(sel_mbid_rst[3]));
assign rdmatctl_mbctl_dep_rdy_en = |(sel_mbid[3:0]);
assign rdmatctl_mbctl_dep_mbid = enc_mbid[3:0];
///////////////////////////////////////////////////////////////////////////////
// This bit indicates if an entry in the RDMA WR Buffer
// can be evicted to DRAM.
//
// The dram req bit of an entry is set in the C4 cycle of
// a WR64 instruction that completes successfully.
// A Wr64 instruction much like the RD64 instruction is
// followed by 2 bubbles. This means that an instruction
// following it 2 cycles later will see the dram_req
// bit without any need for bypassing.
///////////////////////////////////////////////////////////////////////////////
dff_s #(2) ff_rdma_entry_c4 (.din( arbdp_rdma_entry_c3[1:0]),
.clk(rclk), .q(rdma_entry_c4[1:0]), .se(se), .si(), .so());
assign noalloc_evict_dram_c4[0] = ( rdma_entry_c4[1:0] == 2'b00 ) &
tagctl_rdma_ev_en_c4 ;
assign noalloc_evict_dram_c4[1] = ( rdma_entry_c4[1:0] == 2'b01 ) &
tagctl_rdma_ev_en_c4 ;
assign noalloc_evict_dram_c4[2] = ( rdma_entry_c4[1:0] == 2'b10 ) &
tagctl_rdma_ev_en_c4 ;
assign noalloc_evict_dram_c4[3] = ( rdma_entry_c4[1:0] == 2'b11 ) &
tagctl_rdma_ev_en_c4 ;
assign rdma_dram_req_in = ( rdma_dram_req | noalloc_evict_dram_c4 )
& ~reset_rdmat_vld;
dffrl_s #(4) ff_dram_req (.din(rdma_dram_req_in[3:0]), .clk(rclk),
.rst_l(dbb_rst_l),
.q(rdma_dram_req[3:0]), .se(se), .si(), .so());
assign or_rdmat_valid = |( rdma_dram_req ) ;
assign or_rdma_mbid_vld = |( rdma_dram_req & rdma_mbid_vld);
mux2ds #(4) mux_pick_quad0_in
(.dout (rdmat_pick_vec[3:0]),
.in0 (rdma_dram_req[3:0]), .sel0 (~or_rdma_mbid_vld),
.in1 (rdma_mbid_vld[3:0]), .sel1 (or_rdma_mbid_vld)
) ;
///////////////////////////////////////////////////////////////////////////////
// ACKED bit
// Set when an entry is acked by the DRAM controller.
// Reset along with the valid bit.
///////////////////////////////////////////////////////////////////////////////
assign rdma_acked_in = ( rdma_acked | set_rdmat_acked ) &
~reset_rdmat_vld ;
dffrl_s #(4) ff_rdma_acked (.din(rdma_acked_in[3:0]), .clk(rclk),
.rst_l(dbb_rst_l),
.q(rdma_acked[3:0]), .se(se), .si(), .so());
dff_s #(1) ff_sctag_scbuf_fbrd_en_c3 (.din(fbctl_fbd_rd_en_c2), .clk(rclk),
.q(sctag_scbuf_fbrd_en_c3), .se(se), .si(), .so());
dff_s #(3) ff_sctag_scbuf_fbrd_wl_c3 (.din(fbctl_fbd_rd_entry_c2[2:0]),
.clk(rclk),
.q(sctag_scbuf_fbrd_wl_c3[2:0]), .se(se), .si(), .so());
dff_s #(3) ff_sctag_scbuf_fbwr_wl_r2 (.din(fbctl_fbd_wr_entry_r1[2:0]),
.clk(rclk),
.q(sctag_scbuf_fbwr_wl_r2[2:0]), .se(se), .si(), .so());
dff_s #(1) ff_inc_rdma_cnt_c5 (.din(tagctl_inc_rdma_cnt_c4), .clk(rclk),
.q(inc_rdma_cnt_c5), .se(se), .si(), .so());
dff_s #(1) ff_inc_rdma_cnt_c6 (.din(inc_rdma_cnt_c5), .clk(rclk),
.q(inc_rdma_cnt_c6), .se(se), .si(), .so());
dff_s #(1) ff_inc_rdma_cnt_c7 (.din(inc_rdma_cnt_c6), .clk(rclk),
.q(inc_rdma_cnt_c7), .se(se), .si(), .so());
assign sctag_scbuf_word_vld_c7 = inc_rdma_cnt_c7 ;
dff_s #(1) ff_set_rdma_reg_vld_c5 (.din(tagctl_set_rdma_reg_vld_c4), .clk(rclk),
.q(set_rdma_reg_vld_c5), .se(se), .si(), .so());
dff_s #(1) ff_set_rdma_reg_vld_c6 (.din(set_rdma_reg_vld_c5), .clk(rclk),
.q(set_rdma_reg_vld_c6), .se(se), .si(), .so());
dff_s #(1) ff_set_rdma_reg_vld_c7 (.din(set_rdma_reg_vld_c6), .clk(rclk),
.q(set_rdma_reg_vld_c7), .se(se), .si(), .so());
assign sctag_scbuf_ctag_en_c7 = set_rdma_reg_vld_c7 ;
dff_s #(1) ff_tagctl_jbi_req_en_c7 (.din(tagctl_jbi_req_en_c6), .clk(rclk),
.q(jbi_req_en_c7), .se(se), .si(), .so());
assign sctag_scbuf_req_en_c7 = jbi_req_en_c7 ;
/////////////////////////////////////////
// rdma state counter.
// streaming to jbi is done critical word
// first.
// The counter that determines the mux selects
// to do this is maintained here.
/////////////////////////////////////////
assign inc_state_en = inc_rdma_cnt_c6 & ~set_rdma_reg_vld_c6 ;
// implies ld64 beyond c6.
assign rdma_state_en = (inc_rdma_cnt_c6 | set_rdma_reg_vld_c6 );
assign rdma_state_plus1 = rdma_state + 4'b1;
mux2ds #(4) mux_rdma_state_in (.dout (rdma_state_in[3:0]),
.in0(rdma_state_plus1[3:0]),
.in1(arbdp_rdmatctl_addr_c6[5:2]),
.sel0(inc_state_en),
.sel1(~inc_state_en));
dffe_s #(4) ff_rdmard_st (.din(rdma_state_in[3:0]),
.en(rdma_state_en), .clk(rclk),
.q(rdma_state[3:0]), .se(se), .si(), .so());
assign sctag_scbuf_word_c7 = rdma_state ;
//////////////////////////////////////////////////////////////////////////
// Buffer repeater for the rdma rd err
// signals.
// These signals are actually C11 signals coming
// in from scbuf even though the suffix reads
// C10( rdmard operation is skewed by 1 cyc).
// Here's the pipeline.
//
//--------------------------------------------------------------------
// C5 C6 C7 C8 C9 C10 C11
//--------------------------------------------------------------------
// $rd $rd xmit xmit mux ecc xmit
// err
// to
// sctag
//--------------------------------------------------------------------
//
/////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_rdmard_cerr_c12 (.din(scbuf_sctag_rdma_cerr_c10), .clk(rclk),
.q(rdmard_cerr_c12), .se(se), .si(), .so());
dff_s #(1) ff_rdmard_uerr_c12 (.din(scbuf_sctag_rdma_uerr_c10), .clk(rclk),
.q(rdmard_uerr_c12), .se(se), .si(), .so());
dff_s #(1) ff_ev_uerr_r6 (.din(scbuf_sctag_ev_uerr_r5), .clk(rclk),
.q(ev_uerr_r6), .se(se), .si(), .so());
dff_s #(1) ff_ev_cerr_r6 (.din(scbuf_sctag_ev_cerr_r5), .clk(rclk),
.q(ev_cerr_r6), .se(se), .si(), .so());
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:58:43 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/system_vga_buffer_1_1_stub.v
// Design : system_vga_buffer_1_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_1(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V |
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_uart_0_tx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
do_force_break,
reset_n,
status_wr_strobe,
tx_data,
tx_wr_strobe,
// outputs:
tx_overrun,
tx_ready,
tx_shift_empty,
txd
)
;
output tx_overrun;
output tx_ready;
output tx_shift_empty;
output txd;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input do_force_break;
input reset_n;
input status_wr_strobe;
input [ 7: 0] tx_data;
input tx_wr_strobe;
reg baud_clk_en;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg do_load_shifter;
wire do_shift;
reg pre_txd;
wire shift_done;
wire [ 9: 0] tx_load_val;
reg tx_overrun;
reg tx_ready;
reg tx_shift_empty;
wire tx_shift_reg_out;
wire [ 9: 0] tx_shift_register_contents;
wire tx_wr_strobe_onset;
reg txd;
wire [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in;
reg [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
assign tx_load_val = {{1 {1'b1}},
tx_data,
1'b0};
assign shift_done = ~(|tx_shift_register_contents);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_load_shifter <= 0;
else if (clk_en)
do_load_shifter <= (~tx_ready) && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_ready <= 1'b1;
else if (clk_en)
if (tx_wr_strobe_onset)
tx_ready <= 0;
else if (do_load_shifter)
tx_ready <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
tx_overrun <= 0;
else if (~tx_ready && tx_wr_strobe_onset)
tx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_shift_empty <= 1'b1;
else if (clk_en)
tx_shift_empty <= tx_ready && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || do_load_shifter)
baud_rate_counter <= baud_divisor;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
baud_clk_en <= baud_rate_counter_is_zero;
end
assign do_shift = baud_clk_en &&
(~shift_done) &&
(~do_load_shifter);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pre_txd <= 1;
else if (~shift_done)
pre_txd <= tx_shift_reg_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
txd <= 1;
else if (clk_en)
txd <= pre_txd & ~do_force_break;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out <= 0;
else if (clk_en)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in;
end
assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in = (do_load_shifter)? tx_load_val :
(do_shift)? {1'b0,
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out[9 : 1]} :
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_uart_0_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
)
;
output source_rxd;
input [ 9: 0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [ 7: 0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire pickup_pulse;
wire source_rxd;
wire [ 7: 0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
nios_tester_uart_0_tx stimulus_transmitter
(
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe (1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_stim_data <= 0;
else if (do_send_stim_data)
d1_stim_data <= stim_data;
end
assign stim_data = 8'b0;
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en)
delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_uart_0_rx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
reset_n,
rx_rd_strobe,
rxd,
status_wr_strobe,
// outputs:
break_detect,
framing_error,
parity_error,
rx_char_ready,
rx_data,
rx_overrun
)
;
output break_detect;
output framing_error;
output parity_error;
output rx_char_ready;
output [ 7: 0] rx_data;
output rx_overrun;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input reset_n;
input rx_rd_strobe;
input rxd;
input status_wr_strobe;
reg baud_clk_en;
wire [ 9: 0] baud_load_value;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg break_detect;
reg delayed_unxrx_in_processxx3;
reg delayed_unxsync_rxdxx1;
reg delayed_unxsync_rxdxx2;
reg do_start_rx;
reg framing_error;
wire got_new_char;
wire [ 8: 0] half_bit_cell_divisor;
wire is_break;
wire is_framing_error;
wire parity_error;
wire [ 7: 0] raw_data_in;
reg rx_char_ready;
reg [ 7: 0] rx_data;
wire rx_in_process;
reg rx_overrun;
wire rx_rd_strobe_onset;
wire rxd_edge;
wire rxd_falling;
wire [ 9: 0] rxd_shift_reg;
wire sample_enable;
wire shift_reg_start_bit_n;
wire source_rxd;
wire stop_bit;
wire sync_rxd;
wire unused_start_bit;
wire [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in;
reg [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
nios_tester_uart_0_rx_stimulus_source the_nios_tester_uart_0_rx_stimulus_source
(
.baud_divisor (baud_divisor),
.clk (clk),
.clk_en (clk_en),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rxd (rxd),
.source_rxd (source_rxd)
);
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (source_rxd),
.dout (sync_rxd),
.reset_n (reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
//delayed_unxsync_rxdxx1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx1 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx1 <= sync_rxd;
end
assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1);
//delayed_unxsync_rxdxx2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx2 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx2 <= sync_rxd;
end
assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2);
assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
assign half_bit_cell_divisor = baud_divisor[9 : 1];
assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
baud_divisor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || rxd_edge)
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
if (rxd_edge)
baud_clk_en <= 0;
else
baud_clk_en <= baud_rate_counter_is_zero;
end
assign sample_enable = baud_clk_en && rx_in_process;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_start_rx <= 0;
else if (clk_en)
if (~rx_in_process && rxd_falling)
do_start_rx <= 1;
else
do_start_rx <= 0;
end
assign rx_in_process = shift_reg_start_bit_n;
assign {stop_bit,
raw_data_in,
unused_start_bit} = rxd_shift_reg;
assign is_break = ~(|rxd_shift_reg);
assign is_framing_error = ~stop_bit && ~is_break;
//delayed_unxrx_in_processxx3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_in_processxx3 <= 0;
else if (clk_en)
delayed_unxrx_in_processxx3 <= rx_in_process;
end
assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_data <= 0;
else if (got_new_char)
rx_data <= raw_data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
framing_error <= 0;
else if (clk_en)
if (status_wr_strobe)
framing_error <= 0;
else if (got_new_char && is_framing_error)
framing_error <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
break_detect <= 0;
else if (clk_en)
if (status_wr_strobe)
break_detect <= 0;
else if (got_new_char && is_break)
break_detect <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
rx_overrun <= 0;
else if (got_new_char && rx_char_ready)
rx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_char_ready <= 0;
else if (clk_en)
if (rx_rd_strobe_onset)
rx_char_ready <= 0;
else if (got_new_char)
rx_char_ready <= -1;
end
assign parity_error = 0;
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out <= 0;
else if (clk_en)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in;
end
assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in = (do_start_rx)? {10{1'b1}} :
(sample_enable)? {sync_rxd,
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out[9 : 1]} :
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_uart_0_regs (
// inputs:
address,
break_detect,
chipselect,
clk,
clk_en,
cts_n,
framing_error,
parity_error,
read_n,
reset_n,
rx_char_ready,
rx_data,
rx_overrun,
tx_overrun,
tx_ready,
tx_shift_empty,
write_n,
writedata,
// outputs:
baud_divisor,
dataavailable,
do_force_break,
irq,
readdata,
readyfordata,
rts_n,
rx_rd_strobe,
status_wr_strobe,
tx_data,
tx_wr_strobe
)
;
output [ 9: 0] baud_divisor;
output dataavailable;
output do_force_break;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rts_n;
output rx_rd_strobe;
output status_wr_strobe;
output [ 7: 0] tx_data;
output tx_wr_strobe;
input [ 2: 0] address;
input break_detect;
input chipselect;
input clk;
input clk_en;
input cts_n;
input framing_error;
input parity_error;
input read_n;
input reset_n;
input rx_char_ready;
input [ 7: 0] rx_data;
input rx_overrun;
input tx_overrun;
input tx_ready;
input tx_shift_empty;
input write_n;
input [ 15: 0] writedata;
wire any_error;
wire [ 9: 0] baud_divisor;
reg [ 12: 0] control_reg;
wire control_wr_strobe;
wire cts_edge;
reg cts_status_bit;
reg d1_rx_char_ready;
reg d1_tx_ready;
wire dataavailable;
reg dcts_status_bit;
reg delayed_unxcts_status_bitxx5;
reg delayed_unxtx_readyxx4;
wire [ 9: 0] divisor_constant;
wire do_force_break;
wire do_write_char;
wire eop_status_bit;
wire ie_any_error;
wire ie_break_detect;
wire ie_dcts;
wire ie_framing_error;
wire ie_parity_error;
wire ie_rx_char_ready;
wire ie_rx_overrun;
wire ie_tx_overrun;
wire ie_tx_ready;
wire ie_tx_shift_empty;
reg irq;
wire qualified_irq;
reg [ 15: 0] readdata;
wire readyfordata;
wire rts_control_bit;
wire rts_n;
wire rx_rd_strobe;
wire [ 15: 0] selected_read_data;
wire [ 12: 0] status_reg;
wire status_wr_strobe;
reg [ 7: 0] tx_data;
wire tx_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= selected_read_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq <= 0;
else if (clk_en)
irq <= qualified_irq;
end
assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0);
assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_data <= 0;
else if (tx_wr_strobe)
tx_data <= writedata[7 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_wr_strobe)
control_reg <= writedata[12 : 0];
end
assign baud_divisor = divisor_constant;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cts_status_bit <= 1;
else if (clk_en)
cts_status_bit <= ~cts_n;
end
//delayed_unxcts_status_bitxx5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcts_status_bitxx5 <= 0;
else if (clk_en)
delayed_unxcts_status_bitxx5 <= cts_status_bit;
end
assign cts_edge = (cts_status_bit) ^ (delayed_unxcts_status_bitxx5);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dcts_status_bit <= 0;
else if (clk_en)
if (status_wr_strobe)
dcts_status_bit <= 0;
else if (cts_edge)
dcts_status_bit <= -1;
end
assign rts_n = ~rts_control_bit;
assign {rts_control_bit,
ie_dcts,
do_force_break,
ie_any_error,
ie_rx_char_ready,
ie_tx_ready,
ie_tx_shift_empty,
ie_tx_overrun,
ie_rx_overrun,
ie_break_detect,
ie_framing_error,
ie_parity_error} = control_reg;
assign any_error = tx_overrun ||
rx_overrun ||
parity_error ||
framing_error ||
break_detect;
assign status_reg = {eop_status_bit,
cts_status_bit,
dcts_status_bit,
1'b0,
any_error,
rx_char_ready,
tx_ready,
tx_shift_empty,
tx_overrun,
rx_overrun,
break_detect,
framing_error,
parity_error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_rx_char_ready <= 0;
else if (clk_en)
d1_rx_char_ready <= rx_char_ready;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tx_ready <= 0;
else if (clk_en)
d1_tx_ready <= tx_ready;
end
assign dataavailable = d1_rx_char_ready;
assign readyfordata = d1_tx_ready;
assign eop_status_bit = 1'b0;
assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
({16 {(address == 3'd1)}} & tx_data) |
({16 {(address == 3'd2)}} & status_reg) |
({16 {(address == 3'd3)}} & control_reg);
assign qualified_irq = (ie_dcts && dcts_status_bit ) ||
(ie_any_error && any_error ) ||
(ie_tx_shift_empty && tx_shift_empty ) ||
(ie_tx_overrun && tx_overrun ) ||
(ie_rx_overrun && rx_overrun ) ||
(ie_break_detect && break_detect ) ||
(ie_framing_error && framing_error ) ||
(ie_parity_error && parity_error ) ||
(ie_rx_char_ready && rx_char_ready ) ||
(ie_tx_ready && tx_ready );
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//delayed_unxtx_readyxx4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxtx_readyxx4 <= 0;
else if (clk_en)
delayed_unxtx_readyxx4 <= tx_ready;
end
assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
always @(posedge clk)
begin
if (do_write_char)
$write("%c", tx_data);
end
assign divisor_constant = 4;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 543;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_uart_0 (
// inputs:
address,
begintransfer,
chipselect,
clk,
cts_n,
read_n,
reset_n,
rxd,
write_n,
writedata,
// outputs:
dataavailable,
irq,
readdata,
readyfordata,
rts_n,
txd
)
/* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
output dataavailable;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rts_n;
output txd;
input [ 2: 0] address;
input begintransfer;
input chipselect;
input clk;
input cts_n;
input read_n;
input reset_n;
input rxd;
input write_n;
input [ 15: 0] writedata;
wire [ 9: 0] baud_divisor;
wire break_detect;
wire clk_en;
wire dataavailable;
wire do_force_break;
wire framing_error;
wire irq;
wire parity_error;
wire [ 15: 0] readdata;
wire readyfordata;
wire rts_n;
wire rx_char_ready;
wire [ 7: 0] rx_data;
wire rx_overrun;
wire rx_rd_strobe;
wire status_wr_strobe;
wire [ 7: 0] tx_data;
wire tx_overrun;
wire tx_ready;
wire tx_shift_empty;
wire tx_wr_strobe;
wire txd;
assign clk_en = 1;
nios_tester_uart_0_tx the_nios_tester_uart_0_tx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.clk (clk),
.clk_en (clk_en),
.do_force_break (do_force_break),
.reset_n (reset_n),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.txd (txd)
);
nios_tester_uart_0_rx the_nios_tester_uart_0_rx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.break_detect (break_detect),
.clk (clk),
.clk_en (clk_en),
.framing_error (framing_error),
.parity_error (parity_error),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.rxd (rxd),
.status_wr_strobe (status_wr_strobe)
);
nios_tester_uart_0_regs the_nios_tester_uart_0_regs
(
.address (address),
.baud_divisor (baud_divisor),
.break_detect (break_detect),
.chipselect (chipselect),
.clk (clk),
.clk_en (clk_en),
.cts_n (cts_n),
.dataavailable (dataavailable),
.do_force_break (do_force_break),
.framing_error (framing_error),
.irq (irq),
.parity_error (parity_error),
.read_n (read_n),
.readdata (readdata),
.readyfordata (readyfordata),
.reset_n (reset_n),
.rts_n (rts_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.write_n (write_n),
.writedata (writedata)
);
//s1, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_BLACKBOX_V
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/18/2016
Founction: I2C Write and read
Note:
****************************************************************************/
module I2C_wr_subad(
sda,scl,ack,rst_n,clk,WR,RD,data
);
input rst_n,WR,RD,clk;
output scl,ack;
inout [7:0] data;
inout sda;
reg link_sda,link_data;
reg[7:0] data_buf;
reg scl,ack,WF,RF,FF;
reg wr_state;
reg head_state;
reg[8:0] sh8out_state;
reg[9:0] sh8in_state;
reg stop_state;
reg[6:0] main_state;
reg[7:0] data_from_rm;
reg[7:0] cnt_read;
reg[7:0] cnt_write;
/******************************************************************************
*use switch to control serial datas
*******************************************************************************/
assign sda = (link_sda) ? data_buf[7] : 1'bz;
assign data = (link_data) ? data_from_rm : 8'hz;
/******************************************************************************
*number of read and write
*******************************************************************************/
parameter page_write_num = 10'd34,
page_read_num = 10'd32;
/******************************************************************************
*main state machine state
*******************************************************************************/
parameter
idle = 10'b000_0001,
ready = 10'b000_0010,
write_start = 11'b000_0100,
addr_write = 11'b000_1000,
data_read = 11'b001_0000,
stop = 11'b010_0000,
ackn = 11'b100_0000;
/******************************************************************************
*parallel data change to serial data state machine state
*******************************************************************************/
parameter
bit7 = 9'b0_0000_0001,
bit6 = 9'b0_0000_0010,
bit5 = 9'b0_0000_0100,
bit4 = 9'b0_0000_1000,
bit3 = 9'b0_0001_0000,
bit2 = 9'b0_0010_0000,
bit1 = 9'b0_0100_0000,
bit0 = 9'b0_1000_0000,
bitend = 9'b1_0000_0000;
/******************************************************************************
*serial data change to parallel data state machine state
*******************************************************************************/
parameter
read_begin = 10'b00_0000_0001,
read_bit7 = 10'b00_0000_0010,
read_bit6 = 10'b00_0000_0100,
read_bit5 = 10'b00_0000_1000,
read_bit4 = 10'b00_0001_0000,
read_bit3 = 10'b00_0010_0000,
read_bit2 = 10'b00_0100_0000,
read_bit1 = 10'b00_1000_0000,
read_bit0 = 10'b01_0000_0000,
read_end = 10'b10_0000_0000;
/******************************************************************************
*generate scl
*******************************************************************************/
always @(negedge clk or negedge rst_n) begin
if(!rst_n)
scl <= 1'b0;
else
scl <= ~scl;
end
/******************************************************************************
*main state machine
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
link_sda <= 1'b0;
ack <= 1'b0;
RF <= 1'b0;
WF <= 1'b0;
FF <= 1'b0;
main_state <= idle;
head_state <= 'h0;
sh8out_state<= bit7;
sh8in_state <= read_begin;
stop_state <= 'h0;
cnt_read <= 'h1;
cnt_write <= 'h1;
end
else begin
case(main_state)
idle:begin
link_data <= 'h0;
link_sda <= 'h0;
if(WR) begin
WF <= 1'b1;
main_state <= ready;
end
else if(RD)begin
RF <= 1'b1;
main_state <= ready;
end
else begin
WF <= 1'b0;
RF <= 1'b0;
main_state <=idle;
end
end
ready:begin
FF <= 1'b0;
main_state <= write_start;
end
write_start:begin
if(FF==1'b0)
shift_head;
else begin
if(WF == 1'b1)
data_buf <= {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0};
else
data_buf <= {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b1};
FF <= 1'b0;
sh8out_state <= bit6;
main_state <= addr_write;
end
end
addr_write:begin
if(FF==1'b0)
shift8_out;
else begin
if(RF==1'b1)begin
data_buf <= 'h0;
link_sda <= 1'b0;
FF <= 1'b0;
cnt_read <= 1'b1;
main_state <= data_read;
end
else if(WF==1'b1)begin
FF <= 1'b0;
main_state <= data_read;
data_buf <= data;
cnt_write <= 1'b1;
end
end
end
data_read:begin
if(RF==1'b1)begin
if(cnt_read <= page_read_num)
shift8_in;
else begin
main_state <= stop;
FF <= 1'b0;
end
end
else if(WF==1'b1)begin
if(cnt_write <= page_write_num)
case(wr_state)
1'b0:begin
if(!scl)begin
data_buf <= data;
link_sda <= 1'b1;
sh8out_state<=bit6;
wr_state <= 1'b1;
ack <= 1'b0;
end
else
wr_state <= 1'b0;
end
1'b1:shift8_out;
endcase
else begin
main_state <= stop;
wr_state <= 1'b0;
FF <= 1'b0;
end
end
end
stop:begin
if(FF == 1'b0)
task_stop;
else begin
ack <= 1'b1;
FF <= 1'b0;
main_state <= ackn;
end
end
ackn:begin
ack <= 1'b0;
WF <= 1'b0;
RF <= 1'b0;
main_state <= idle;
end
default:main_state <= idle;
endcase
end
end
/******************************************************************************
*start task
*******************************************************************************/
task shift_head;
begin
case(head_state)
1'b0:begin
if(!scl)begin
link_sda <= 1'b1;
data_buf[7] <= 1'b1;
head_state <= 1'b1;
end
else
head_state <= 1'b0;
end
1'b1:begin
if(scl)begin
FF <= 1'b1;
data_buf[7] <= 1'b0;
head_state <= 1'b0;
end
else
head_state<= 1'b1;
end
endcase
end
endtask
/******************************************************************************
*output task
*******************************************************************************/
task shift8_out;
begin
case(sh8out_state)
bit7:begin
if(!scl) begin
link_sda <= 1'b1;
sh8out_state <= bit6;
end
else
sh8out_state <= bit7;
end
bit6:begin
if(!scl) begin
sh8out_state <= bit5;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit6;
end
bit5:begin
if(!scl) begin
sh8out_state <= bit4;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit5;
end
bit4:begin
if(!scl) begin
sh8out_state <= bit3;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit4;
end
bit3:begin
if(!scl) begin
sh8out_state <= bit2;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit3;
end
bit2:begin
if(!scl) begin
sh8out_state <= bit1;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit2;
end
bit1:begin
if(!scl) begin
sh8out_state <= bit0;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit1;
end
bit0:begin
if(!scl) begin
sh8out_state <= bitend;
data_buf <= data_buf<<1'b1;
end
else
sh8out_state <= bit0;
end
bitend:begin
if((scl == 1'b0) && (wr_state == 1'b1) ) begin
link_sda <= 1'b0;
sh8out_state <= bit7;
wr_state <= 1'b0;
FF <= 1'b1;
cnt_write <= cnt_write + 1'b1;
ack <= 1'b1;
end
else if(scl==0)begin
link_sda <= 1'b0;
sh8out_state <= bit7;
wr_state <= 1'b0;
FF <= 1'b1;
cnt_write <= cnt_write + 1'b1;
end
else;
end
endcase
end
endtask
/******************************************************************************
*input task
*******************************************************************************/
task shift8_in;
begin
case(sh8in_state)
read_begin:begin
sh8in_state <= read_bit7;
link_data <= 1'b0;
ack <= 1'b0;
end
read_bit7:begin
if(scl)begin
data_from_rm[7] <= sda;
sh8in_state <= read_bit6;
end
else begin
link_sda <= 1'b0;
sh8in_state <= read_bit7;
end
end
read_bit6:begin
if(scl)begin
data_from_rm[6] <= sda;
sh8in_state <= read_bit5;
end
else
sh8in_state <= read_bit6;
end
read_bit5:begin
if(scl)begin
data_from_rm[5] <= sda;
sh8in_state <= read_bit4;
end
else
sh8in_state <= read_bit5;
end
read_bit4:begin
if(scl)begin
data_from_rm[4] <= sda;
sh8in_state <= read_bit3;
end
else
sh8in_state <= read_bit4;
end
read_bit3:begin
if(scl)begin
data_from_rm[3] <= sda;
sh8in_state <= read_bit2;
end
else
sh8in_state <= read_bit3;
end
read_bit2:begin
if(scl)begin
data_from_rm[2] <= sda;
sh8in_state <= read_bit1;
end
else
sh8in_state <= read_bit2;
end
read_bit1:begin
if(scl)begin
data_from_rm[1] <= sda;
sh8in_state <= read_bit0;
end
else
sh8in_state <= read_bit1;
end
read_bit0:begin
if(scl)begin
data_from_rm[0] <= sda;
sh8in_state <= read_end;
end
else
sh8in_state <= read_bit0;
end
read_end:begin
if(cnt_read == page_read_num)begin
link_data <= 1'b1;
link_sda <= 1'b1;
sh8in_state <= read_begin;
FF <= 1'b1;
data_buf[7] <= 1'b1;
cnt_read <= cnt_read + 1'b1;
ack <= 1'b1;
end
else begin
link_data <= 1'b1;
link_sda <= 1'b1;
sh8in_state <= read_begin;
FF <= 1'b1;
data_buf[7] <= 1'b0;
cnt_read <= cnt_read + 1'b1;
ack <= 1'b1;
end
end
default:begin
sh8in_state <= read_begin;
end
endcase
end
endtask
/******************************************************************************
*stop task
*******************************************************************************/
task task_stop;
begin
case(stop_state)
1'b0:begin
if(!scl)begin
link_sda <= 1'b1;
stop_state <= 1'b1;
data_buf[7]<= 1'b0;
end
else
stop_state <= 1'b0;
end
1'b1:begin
if(scl)begin
data_buf[7] <= 1'b1;
FF <= 1'b1;
stop_state <= 1'b0;
end
else
stop_state <=1'b1;
end
endcase
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module ROM(input clk,
input wire [8:0] addr,
output reg [7:0] data);
reg [7:0] rom [0:127];
always @(negedge clk) begin
data <= rom[addr];
end
initial begin
rom[0] = 8'h0;
rom[1] = 8'h1;
rom[2] = 8'h2;
rom[3] = 8'h3;
rom[4] = 8'h4;
rom[5] = 8'h5;
rom[6] = 8'h6;
rom[7] = 8'h7;
rom[8] = 8'h8;
rom[9] = 8'h9;
rom[10] = 8'h10;
rom[11] = 8'h11;
rom[12] = 8'h12;
rom[13] = 8'h13;
rom[14] = 8'h14;
rom[15] = 8'h15;
rom[16] = 8'h16;
rom[17] = 8'h17;
rom[18] = 8'h18;
rom[19] = 8'h19;
rom[20] = 8'h20;
rom[21] = 8'h21;
rom[22] = 8'h22;
rom[23] = 8'h23;
rom[24] = 8'h24;
rom[25] = 8'h25;
rom[26] = 8'h26;
rom[27] = 8'h27;
rom[28] = 8'h28;
rom[29] = 8'h29;
rom[30] = 8'h30;
rom[31] = 8'h31;
rom[32] = 8'h32;
rom[33] = 8'h33;
rom[34] = 8'h34;
rom[35] = 8'h35;
rom[36] = 8'h36;
rom[37] = 8'h37;
rom[38] = 8'h38;
rom[39] = 8'h39;
rom[40] = 8'h40;
rom[41] = 8'h41;
rom[42] = 8'h42;
rom[43] = 8'h43;
rom[44] = 8'h44;
rom[45] = 8'h45;
rom[46] = 8'h46;
rom[47] = 8'h47;
rom[48] = 8'h48;
rom[49] = 8'h49;
rom[50] = 8'h50;
rom[51] = 8'h51;
rom[52] = 8'h52;
rom[53] = 8'h53;
rom[54] = 8'h54;
rom[55] = 8'h55;
rom[56] = 8'h56;
rom[57] = 8'h57;
rom[58] = 8'h58;
rom[59] = 8'h59;
rom[60] = 8'h60;
rom[61] = 8'h61;
rom[62] = 8'h62;
rom[63] = 8'h63;
rom[64] = 8'h64;
rom[65] = 8'h65;
rom[66] = 8'h66;
rom[67] = 8'h67;
rom[68] = 8'h68;
rom[69] = 8'h69;
rom[70] = 8'h70;
rom[71] = 8'h71;
rom[72] = 8'h72;
rom[73] = 8'h73;
rom[74] = 8'h74;
rom[75] = 8'h75;
rom[76] = 8'h76;
rom[77] = 8'h77;
rom[78] = 8'h78;
rom[79] = 8'h79;
rom[80] = 8'h80;
rom[81] = 8'h81;
rom[82] = 8'h82;
rom[83] = 8'h83;
rom[84] = 8'h84;
rom[85] = 8'h85;
rom[86] = 8'h86;
rom[87] = 8'h87;
rom[88] = 8'h88;
rom[89] = 8'h89;
rom[90] = 8'h90;
rom[91] = 8'h91;
rom[92] = 8'h92;
rom[93] = 8'h93;
rom[94] = 8'h94;
rom[95] = 8'h95;
rom[96] = 8'h96;
rom[97] = 8'h97;
rom[98] = 8'h98;
rom[99] = 8'h99;
rom[100] = 8'h100;
rom[101] = 8'h101;
rom[102] = 8'h102;
rom[103] = 8'h103;
rom[104] = 8'h104;
rom[105] = 8'h105;
rom[106] = 8'h106;
rom[107] = 8'h107;
rom[108] = 8'h108;
rom[109] = 8'h109;
rom[110] = 8'h110;
rom[111] = 8'h111;
rom[112] = 8'h112;
rom[113] = 8'h112;
rom[114] = 8'h114;
rom[115] = 8'h115;
rom[116] = 8'h116;
rom[117] = 8'h117;
rom[118] = 8'h118;
rom[119] = 8'h119;
rom[120] = 8'h120;
rom[121] = 8'h121;
rom[122] = 8'h122;
rom[123] = 8'h123;
rom[124] = 8'h124;
rom[125] = 8'h125;
rom[126] = 8'h126;
rom[127] = 8'h127;
end
endmodule |
`timescale 1ns / 1ps
/*
Instruction Fetch pipeline stage
*/
module if_stage( input clk, rst,
input if_id_write_en,
input pc_write,
input [1:0] pc_source,
input pstop_i,
output i_read_en,
output [31:0] i_addr,
input [31:0] i_instr_in,
input [31:0] jump_addr, branch_addr,
output reg [31:0] IF_ID_next_i_addr,
output reg [31:0] IF_ID_instruction );
reg [31:0] pc_reg, pc_next; // Program counter (PC)
wire [31:0] next_i_addr;
localparam LW = 6'b100011,
SW = 6'b101011;
wire mem_op = (IF_ID_instruction[31:26] == LW) || (IF_ID_instruction[31:26] == SW);
//logic
assign next_i_addr = pc_reg + 4;
assign i_read_en = 1;
assign i_addr = pc_reg >> 2;
always @* begin
pc_next = pc_reg;
case (pc_source)
2'b00: pc_next = next_i_addr;
2'b01: pc_next = branch_addr;
2'b10: pc_next = jump_addr;
endcase
end
always @(posedge clk) begin
if (rst)
pc_reg <= 0;
else begin
if (pc_write && !(pstop_i || mem_op))
pc_reg <= pc_next;
end
end
//IF/ID Pipeline register
always @(posedge clk) begin
if (rst) begin
IF_ID_next_i_addr <= 0;
IF_ID_instruction <= 0;
end
else begin
if ( if_id_write_en) begin
IF_ID_next_i_addr <= next_i_addr;
IF_ID_instruction <= !(pstop_i || mem_op)? i_instr_in: 0;
end
end
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
module deserializer #(
parameter LOG_DWIDTH=7,
parameter DWIDTH=64
)
(
input wire clk,
input wire res_n,
input wire fast_clk,
input wire bit_slip,
input wire data_in,
output wire [DWIDTH-1:0]data_out,
input wire lane_polarity
);
reg [DWIDTH-1:0] tmp_buffer;
reg [DWIDTH-1:0] buffer;
reg [DWIDTH-1:0] buffer2;
reg [DWIDTH-1:0] data_out_temp;
reg [LOG_DWIDTH-1:0]curr_bit = 'h0;
reg [5:0] bit_slip_cnt;
reg bit_slip_done = 1'b0;
reg d_in_dly;
assign data_out = lane_polarity ? data_out_temp^{DWIDTH{1'b1}} : data_out_temp;
// SEQUENTIAL PROCESS
always @ (posedge fast_clk) begin
if(!res_n) begin
curr_bit <= {LOG_DWIDTH{1'b0}};
bit_slip_done <= 1'b0;
end else begin
#1ps d_in_dly <= data_in;
if (!bit_slip || bit_slip_done) begin
if(curr_bit == DWIDTH-1) begin
curr_bit <= 0;
end else begin
curr_bit <= curr_bit + 1;
end
end
if (bit_slip && !bit_slip_done)
bit_slip_done <= 1'b1;
if (bit_slip_done && !bit_slip)
bit_slip_done <= 1'b0;
if (|curr_bit == 1'b0) begin
buffer <= tmp_buffer;
end
tmp_buffer[curr_bit] <= d_in_dly;
end
end
always @ (posedge clk) begin
if(!res_n) begin
bit_slip_cnt <= 6'h0;
end else begin
if(bit_slip)
bit_slip_cnt <= bit_slip_cnt + 1;
buffer2 <= buffer;
if(bit_slip_cnt < DWIDTH-1) begin
data_out_temp <= buffer2;
end else begin
data_out_temp <= buffer;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_SYMBOL_V
`define SKY130_FD_SC_HD__A221OI_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_SYMBOL_V
|
`include "trellis.vh"
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue_input
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Demuxes input TLPs into the appropriate slot/bucket/RAM-position according
// to its tag.
//
// Dependencies:
// reorder_queue.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module reorder_queue_input
#(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8, // Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5, // Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload data enable
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
output [C_NUM_TAGS-1:0] TAG_FINISH, // Bitmap of tags to finish
input [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] STORED_DATA_ADDR, // Address of stored packet data for RAMs
output [C_PCI_DATA_WIDTH-1:0] STORED_DATA, // Stored packet data for RAMs
output [C_PCI_DATA_WORD-1:0] STORED_DATA_EN, // Stored packet data enable for RAMs
output PKT_VALID, // Valid flag for packet data
output [C_TAG_WIDTH-1:0] PKT_TAG, // Tag for stored packet data
output [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of stored packet payload in DWs
output PKT_WORDS_LTE1, // True if total count of stored packet payload is <= 4 DWs
output PKT_WORDS_LTE2, // True if total count of stored packet payload is <= 8 DWs
output PKT_DONE, // Stored packet done flag
output PKT_ERR // Stored packet error flag
);
`include "functions.vh"
wire [C_PCI_DATA_COUNT_WIDTH-1:0] wDECount;
wire [C_PCI_DATA_WORD-1:0] wDE;
wire [C_PCI_DATA_WIDTH-1:0] wData;
wire [C_PCI_DATA_WORD-1:0] wStartMask;
wire [C_PCI_DATA_WORD-1:0] wEndMask;
reg [5:0] rValid=0;
reg [(C_PCI_DATA_WIDTH*5)-1:0] rData=0;
reg [(C_PCI_DATA_WORD*3)-1:0] rDE=0;
reg [(C_PCI_DATA_COUNT_WIDTH*2)-1:0] rDECount=0;
reg [5:0] rDone=0;
reg [5:0] rErr=0;
reg [(C_TAG_WIDTH*6)-1:0] rTag=0;
reg [C_PCI_DATA_WORD-1:0] rDEShift=0;
reg [(C_PCI_DATA_WORD*2)-1:0] rDEShifted=0;
reg rCountValid=0;
reg [C_NUM_TAGS-1:0] rCountRst=0;
reg [C_NUM_TAGS-1:0] rValidCount=0;
reg rUseCurrCount=0;
reg rUsePrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rPrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rCount=0;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCount;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCountClr = wCount & {C_TAG_DW_COUNT_WIDTH{rCountValid}};
reg [(C_TAG_DW_COUNT_WIDTH*3)-1:0] rWords=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShift=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShifted=0;
reg rPosValid=0;
reg [C_NUM_TAGS-1:0] rPosRst=0;
reg [C_NUM_TAGS-1:0] rValidPos=0;
reg rUseCurrPos=0;
reg rUsePrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPosNow=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPos=0;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPos;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPosClr = wPos & {C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD{rPosValid}};
reg [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] rAddr=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftUp=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftDown=0;
reg [C_DATA_ADDR_WIDTH-1:0] rBaseAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataShifted=0;
reg rLTE1Pkt=0;
reg rLTE2Pkt=0;
reg [C_NUM_TAGS-1:0] rFinish=0;
wire [31:0] wZero=32'd0;
integer i;
assign wDE = DATA_EN >> (DATA_START_FLAG ? DATA_START_OFFSET : 0);/* TODO: Could move this to the RX Engine*/
assign wData = DATA >> (DATA_START_FLAG ? {DATA_START_OFFSET,5'b0} : 0);
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wDECount = VALID ? 1 : 0;
end
if(C_PCI_DATA_WIDTH == 64) begin
assign wDECount = VALID ? DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 128) begin
assign wDECount = VALID ? DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 256) begin
assign wDECount = VALID ? DATA_EN[7] + DATA_EN[6] + DATA_EN[5] + DATA_EN[4] +
DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
endgenerate
assign TAG_FINISH = rFinish;
assign STORED_DATA_ADDR = rAddr;
assign STORED_DATA = rDataShifted;
assign STORED_DATA_EN = rDEShifted[1*C_PCI_DATA_WORD +:C_PCI_DATA_WORD];
assign PKT_VALID = rValid[5];
assign PKT_TAG = rTag[5*C_TAG_WIDTH +:C_TAG_WIDTH];
assign PKT_WORDS = rWords[2*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH];
assign PKT_WORDS_LTE1 = rLTE1Pkt;
assign PKT_WORDS_LTE2 = rLTE2Pkt;
assign PKT_DONE = rDone[5];
assign PKT_ERR = rErr[5];
// Pipeline the input and intermediate data
always @ (posedge CLK) begin
if (RST) begin
rValid <= #1 0;
rTag <= #1 0;
end
else begin
rValid <= #1 (rValid<<1) | VALID;
rTag <= #1 (rTag<<C_TAG_WIDTH) | TAG;
end
rData <= #1 (rData<<C_PCI_DATA_WIDTH) | wData;
rDE <= #1 (rDE<<C_PCI_DATA_WORD) | wDE;//DATA_EN;
rDECount <= #1 (rDECount<<C_PCI_DATA_COUNT_WIDTH) | wDECount;//DATA_EN_COUNT;
rDone <= #1 (rDone<<1) | DONE;
rErr <= #1 (rErr<<1) | ERR;
rDEShifted <= #1 (rDEShifted<<C_PCI_DATA_WORD) | rDEShift;
rWords <= #1 (rWords<<C_TAG_DW_COUNT_WIDTH) | rCount;
rShifted <= #1 (rShifted<<C_PCI_DATA_WORD_WIDTH) | rShift;
end
// Input processing pipeline
always @ (posedge CLK) begin
// STAGE 0: Register the incoming data
// STAGE 1: Request existing count from RAM
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rCount value if the tags match.
rUseCurrCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[1*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[1]);
rUsePrevCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[2]);
rPrevCount <= #1 rCount;
// See if we need to reset the count
rCountValid <= #1 (RST ? 1'd0 : rCountRst>>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidCount <= #1 (RST ? 0 : rValid[0]<<rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 2: Calculate new count (saves next cycle)
if (rUseCurrCount) begin
rShift <= #1 rCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else if (rUsePrevCount) begin
rShift <= #1 rPrevCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rPrevCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else begin
rShift <= #1 wCountClr[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 wCountClr + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
// STAGE 3: Request existing positions from RAM
// Barrel shift the DE
rDEShift <= #1 (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]<<rShift) |
(rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]>>(C_PCI_DATA_WORD-rShift));
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rPos values if the tags match.
rUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);
rUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
end
// See if we need to reset the positions
rPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidPos <= #1 (RST ? 0 : rValid[2]<<rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 4: Calculate new positions (saves next cycle)
if (rUseCurrPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else if (rUsePrevPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
// Calculate the base address offset
rBaseAddr <= #1 rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH]<<C_DATA_ADDR_STRIDE_WIDTH;
// Calculate the shift amounts for barrel shifting payload data
rShiftUp <= #1 rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH]<<5;
rShiftDown <= #1 (C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0] - rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH])<<5;
// STAGE 5: Prepare to write data, final info
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rAddr[C_DATA_ADDR_WIDTH*i +:C_DATA_ADDR_WIDTH] <= #1
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rBaseAddr;
end
rDataShifted <= #1 (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]<<rShiftUp) |
(rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]>>rShiftDown);
rLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);
rLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));
rFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<<rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH];
// STAGE 6: Write data, final info
end
// Reset the count and positions when needed
always @ (posedge CLK) begin
if (RST) begin
rCountRst <= #1 0;
rPosRst <= #1 0;
end
else begin
rCountRst <= #1 (rCountRst | rValidCount) & ~TAG_CLEAR;
rPosRst <= #1 (rPosRst | rValidPos) & ~TAG_CLEAR;
end
end
// RAM for counts
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
countRam
(
.CLK(CLK),
.ADDRA(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[2]),
.DINA(rCount),
.ADDRB(rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wCount)
);
// RAM for positions
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_PCI_DATA_WORD*C_DATA_ADDR_STRIDE_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
posRam
(
.CLK(CLK),
.ADDRA(rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[4]),
.DINA(rPos),
.ADDRB(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wPos)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_2 (
CLK,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign read_0 = wire_0;
assign read_1 = wire_1;
always @(posedge CLK) begin
r <= wire_2;
end
endmodule
|
/*
Author: Joe Krachey
Date: 01/03/2017
*/
module ece453(
// signals to connect to an Avalon clock source interface
clk,
reset,
// signals to connect to an Avalon-MM slave interface
slave_address,
slave_read,
slave_write,
slave_readdata,
slave_writedata,
slave_byteenable,
gpio_inputs,
gpio_outputs,
irq_out
);
// most of the set values will only be used by the component .tcl file. The DATA_WIDTH and MODE_X = 3 influence the hardware created.
// ENABLE_SYNC_SIGNALS isn't used by this hardware at all but it provided anyway so that it can be exposed in the component .tcl file
// to control the stubbing of certain signals.
//parameter ENABLE_SYNC_SIGNAL S = 0; // only used by the component .tcl file, 1 to expose user_chipselect/write/read, 0 to stub them
//*******************************************************************
// Module Interface
//*******************************************************************
input clk;
input reset;
// slave interface
input [3:0] slave_address;
input slave_read;
input slave_write;
output wire [31:0] slave_readdata;
input [31:0] slave_writedata;
input [3:0] slave_byteenable;
input [31:0] gpio_inputs;
output [31:0] gpio_outputs;
output wire irq_out;
`include "ece453.vh"
//*******************************************************************
// Register Set
//*******************************************************************
reg [31:0] dev_id_r;
reg [31:0] gpio_in_r;
reg [31:0] gpio_out_r;
//*******************************************************************
// Wires/Reg
//*******************************************************************
wire [31:0] gpio_in;
wire [31:0] gpio_out;
//*******************************************************************
// Register Read Assignments
//*******************************************************************
assign slave_readdata = ( (slave_address == DEV_ID_ADDR ) && slave_read ) ? dev_id_r :
( (slave_address == GPIO_IN_ADDR ) && slave_read ) ? gpio_in_r :
( (slave_address == GPIO_OUT_ADDR ) && slave_read ) ? gpio_out_r : 32'h00000000;
//*******************************************************************
// Output Assignments
//*******************************************************************
// IRQ indicating that an interrupt is active
assign irq_out = 0;
assign gpio_outputs = gpio_out_r;
//*******************************************************************
// Register Input Equations
//*******************************************************************
// Input signals for registers
assign gpio_in = gpio_inputs;
assign gpio_out = ( (slave_address == GPIO_OUT_ADDR ) && slave_write ) ? slave_writedata : gpio_out_r;
//*******************************************************************
// Registers
//*******************************************************************
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
dev_id_r <= 32'hECE45300;
gpio_in_r <= 32'h00000000;
gpio_out_r <= 32'h00000000;
end
else
begin
dev_id_r <= 32'hECE45300;
gpio_in_r <= gpio_in;
gpio_out_r <= gpio_out;
end
end
endmodule
|
// hub
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "hub_mem.v"
module hub
(
input clk_cog,
input ena_bus,
input nres,
input [7:0] bus_sel,
input bus_r,
input bus_e,
input bus_w,
input [1:0] bus_s,
input [15:0] bus_a,
input [31:0] bus_d,
output reg [31:0] bus_q,
output bus_c,
output [7:0] bus_ack,
output reg [7:0] cog_ena,
output [7:0] ptr_w,
output [27:0] ptr_d,
output reg [7:0] cfg
);
// latch bus signals from cog[n]
reg rc;
reg ec;
reg wc;
reg [1:0] sc;
reg [15:0] ac;
reg [31:0] dc;
always @(posedge clk_cog)
if (ena_bus)
rc <= bus_r;
always @(posedge clk_cog or negedge nres)
if (!nres)
ec <= 1'b0;
else if (ena_bus)
ec <= bus_e;
always @(posedge clk_cog)
if (ena_bus)
wc <= bus_w;
always @(posedge clk_cog)
if (ena_bus)
sc <= bus_s;
always @(posedge clk_cog)
if (ena_bus)
ac <= bus_a;
always @(posedge clk_cog)
if (ena_bus)
dc <= bus_d;
// connect hub memory to signals from cog[n-1]
wire mem_w = ec && ~&sc && wc;
wire [3:0] mem_wb = sc[1] ? 4'b1111 // wrlong
: sc[0] ? ac[1] ? 4'b1100 : 4'b0011 // wrword
: 4'b0001 << ac[1:0]; // wrbyte
wire [31:0] mem_d = sc[1] ? dc // wrlong
: sc[0] ? {2{dc[15:0]}} // wrword
: {4{dc[7:0]}}; // wrbyte
wire [31:0] mem_q;
hub_mem hub_mem_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.w (mem_w),
.wb (mem_wb),
.a (ac[15:2]),
.d (mem_d),
.q (mem_q) );
// latch bus signals from cog[n-1]
reg rd;
reg ed;
reg [1:0] sd;
reg [1:0] ad;
always @(posedge clk_cog)
if (ena_bus)
rd <= !rc && ac[15];
always @(posedge clk_cog or negedge nres)
if (!nres)
ed <= 1'b0;
else if (ena_bus)
ed <= ec;
always @(posedge clk_cog)
if (ena_bus)
sd <= sc;
always @(posedge clk_cog)
if (ena_bus)
ad <= ac[1:0];
// set bus output according to cog[n-2]
wire [31:0] ramq = !rd ? mem_q : {mem_q[03], mem_q[07], mem_q[21], mem_q[12], // unscramble rom data if cog loading
mem_q[06], mem_q[19], mem_q[04], mem_q[17],
mem_q[20], mem_q[15], mem_q[08], mem_q[11],
mem_q[00], mem_q[14], mem_q[30], mem_q[01],
mem_q[23], mem_q[31], mem_q[16], mem_q[05],
mem_q[09], mem_q[18], mem_q[25], mem_q[02],
mem_q[28], mem_q[22], mem_q[13], mem_q[27],
mem_q[29], mem_q[24], mem_q[26], mem_q[10]};
always @(posedge clk_cog)
bus_q <= sd[1] ? sd[0] ? {29'b0, sys_q} // cogid/coginit/locknew
: ramq // rdlong
: sd[0] ? ramq >> {ad[1], 4'b0} & 32'h0000FFFF // rdword
: ramq >> {ad[1:0], 3'b0} & 32'h000000FF; // rdbyte
assign bus_c = sys_c;
// generate bus acknowledge for cog[n-2]
assign bus_ack = ed ? {bus_sel[1:0], bus_sel[7:2]} : 8'b0;
// sys common logic
//
// ac in dc in num sys_q sys_c
// -----------------------------------------------------------------------------------------
// 000 CLKSET config(8) - - -
// 001 COGID - - [n-1] -
// 010 COGINIT ptr(28),newx,id(3) id(3)/newx id(3)/newx all
// 011 COGSTOP -,id(3) id(3) id(3) -
// 100 LOCKNEW - newx newx all
// 101 LOCKRET -,id(3) id(3) id(3) -
// 110 LOCKSET -,id(3) id(3) id(3) lock_state[id(3)]
// 111 LOCKCLR -,id(3) id(3) id(3) lock_state[id(3)]
wire sys = ec && (&sc);
wire [7:0] enc = ac[2] ? lock_e : cog_e;
wire all = &enc; // no free cogs/locks
wire [2:0] newx = &enc[3:0] ? &enc[5:4] ? enc[6] ? 3'b111 // x1111111 -> 111
: 3'b110 // x0111111 -> 110
: enc[4] ? 3'b101 // xx011111 -> 101
: 3'b100 // xxx01111 -> 100
: &enc[1:0] ? enc[2] ? 3'b011 // xxxx0111 -> 011
: 3'b010 // xxxxx011 -> 010
: enc[0] ? 3'b001 // xxxxxx01 -> 001
: 3'b000; // xxxxxxx0 -> 000
wire [2:0] num = ac[2:0] == 3'b010 && dc[3] || ac[2:0] == 3'b100 ? newx : dc[2:0];
wire [7:0] num_dcd = 1'b1 << num;
// cfg
always @(posedge clk_cog or negedge nres)
if (!nres)
cfg <= 8'b0;
else if (ena_bus && sys && ac[2:0] == 3'b000)
cfg <= dc[7:0];
// cogs
reg [7:0] cog_e;
wire cog_start = sys && ac[2:0] == 3'b010 && !(dc[3] && all);
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_e <= 8'b00000001;
else if (ena_bus && sys && ac[2:1] == 2'b01)
cog_e <= cog_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_ena <= 8'b0;
else if (ena_bus)
cog_ena <= cog_e & ~({8{cog_start}} & num_dcd);
assign ptr_w = {8{cog_start}} & num_dcd;
assign ptr_d = dc[31:4];
// locks
reg [7:0] lock_e;
reg [7:0] lock_state;
always @(posedge clk_cog or negedge nres)
if (!nres)
lock_e <= 8'b0;
else if (ena_bus && sys && ac[2:1] == 2'b10)
lock_e <= lock_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog)
if (ena_bus && sys && ac[2:1] == 2'b11)
lock_state <= lock_state & ~num_dcd | {8{!ac[0]}} & num_dcd;
wire lock_mux = lock_state[dc[2:0]];
// output
reg [2:0] sys_q;
reg sys_c;
always @(posedge clk_cog)
if (ena_bus && sys)
sys_q <= ac[2:0] == 3'b001 ? { bus_sel[7] || bus_sel[6] || bus_sel[5] || bus_sel[0], // cogid
bus_sel[7] || bus_sel[4] || bus_sel[3] || bus_sel[0],
bus_sel[6] || bus_sel[4] || bus_sel[2] || bus_sel[0] }
: num; // others
always @(posedge clk_cog)
if (ena_bus && sys)
sys_c <= ac[2:1] == 2'b11 ? lock_mux // lockset/lockclr
: all; // others
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: tes_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tes_pll (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire [0:0] sub_wire8 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire7),
.clk (sub_wire0),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 1,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 1,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=tes_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "tes_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog wrapper for lpflow_decapkapwr with size of 3 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_3 (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base (
.VPWR(VPWR),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_3 ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
|
module sockit_test (
input CLOCK_50,
input [3:0] KEY,
output [3:0] LED,
output [14:0] hps_memory_mem_a,
output [2:0] hps_memory_mem_ba,
output hps_memory_mem_ck,
output hps_memory_mem_ck_n,
output hps_memory_mem_cke,
output hps_memory_mem_cs_n,
output hps_memory_mem_ras_n,
output hps_memory_mem_cas_n,
output hps_memory_mem_we_n,
output hps_memory_mem_reset_n,
inout [39:0] hps_memory_mem_dq,
inout [4:0] hps_memory_mem_dqs,
inout [4:0] hps_memory_mem_dqs_n,
output hps_memory_mem_odt,
output [4:0] hps_memory_mem_dm,
input hps_memory_oct_rzqin
);
wire [3:0] key_os;
wire [3:0] delay;
wire main_clk = CLOCK_50;
oneshot os (
.clk (main_clk),
.edge_sig (KEY),
.level_sig (key_os)
);
blinker b (
.clk (main_clk),
.delay (delay),
.led (LED),
.reset (key_os[3]),
.pause (key_os[2])
);
soc_system soc (
.delay_ctrl_delay (delay),
.delay_ctrl_slower (key_os[0]),
.delay_ctrl_faster (key_os[1]),
.memory_mem_a (hps_memory_mem_a),
.memory_mem_ba (hps_memory_mem_ba),
.memory_mem_ck (hps_memory_mem_ck),
.memory_mem_ck_n (hps_memory_mem_ck_n),
.memory_mem_cke (hps_memory_mem_cke),
.memory_mem_cs_n (hps_memory_mem_cs_n),
.memory_mem_ras_n (hps_memory_mem_ras_n),
.memory_mem_cas_n (hps_memory_mem_cas_n),
.memory_mem_we_n (hps_memory_mem_we_n),
.memory_mem_reset_n (hps_memory_mem_reset_n),
.memory_mem_dq (hps_memory_mem_dq),
.memory_mem_dqs (hps_memory_mem_dqs),
.memory_mem_dqs_n (hps_memory_mem_dqs_n),
.memory_mem_odt (hps_memory_mem_odt),
.memory_mem_dm (hps_memory_mem_dm),
.memory_oct_rzqin (hps_memory_oct_rzqin),
.clk_clk (main_clk),
.reset_reset_n (!key_os[3])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_1_V
`define SKY130_FD_SC_HDLL__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_2_V
`define SKY130_FD_SC_LS__SDFRBP_2_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_2_V
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Galois Field multiplier.
//
//------------------------------------------------------------------------------
`ifndef _ZL_GF_MUL_V_
`define _ZL_GF_MUL_V_
module zl_gf_mul #
(
parameter Gf_width = 0,
parameter Gf_poly = 0
)
(
input [Gf_width-1:0] a,
input [Gf_width-1:0] b,
output [Gf_width-1:0] out
);
// compute a*b
function [Gf_width*2-2:0] a_conv_b;
input [Gf_width-1:0] a;
input [Gf_width-1:0] b;
//
reg [Gf_width*2-2:0] retval;
integer i,j;
begin
retval = 0;
for(i=0;i<Gf_width*2-1;i=i+1) begin
for(j=0;j<Gf_width;j=j+1) begin
if(i>=j && i-j<Gf_width) begin
retval[i] = retval[i] ^ (a[j]&b[i-j]);
end
end
end
a_conv_b = retval;
end
endfunction
// mod by gf poly
function [Gf_width-1:0] mod_gf;
input [Gf_width*2-2:0] f;
//
reg [Gf_width-1:0] retval;
integer i;
begin
retval = 0;
for(i=0;i<Gf_width*2-1;i=i+1) begin
retval =
{retval[Gf_width-2:0], f[Gf_width*2-2-i]}
^ ({Gf_width{retval[Gf_width-1]}}
& Gf_poly[Gf_width-1:0]);
end
mod_gf = retval;
end
endfunction
assign out = mod_gf(a_conv_b(a,b));
endmodule // zl_gf_mul
`endif // _ZL_GF_MUL_V_
|
/*
* syncgen.v: 同期信号発生器
*/
module syncgen (
input SYSCLK,
input RST,
output PCLK,
output reg HSYNC,
output reg VSYNC,
output [9:0] HCNT,
output [9:0] VCNT
);
`include "vgaparam.vh"
// 100MHz から 25MHz を作成する
reg cnt1 = 1'b0;
reg pclk0 = 1'b0;
assign PCLK = pclk0;
always @(posedge SYSCLK) begin
if (cnt1 == 1'b1) begin
pclk0 <= ~pclk0;
end
cnt1 <= ~cnt1;
end
reg [9:0] HCNT_o = 10'h0;
reg [9:0] VCNT_o = 10'h0;
// 水平カウンタがリセットされるタイミング
wire hs = (HCNT_o == HPERIOD - 10'd1);
// 水平カウンタ
always @(posedge PCLK) begin
if (RST | hs)
HCNT_o <= 10'h0;
else
HCNT_o <= HCNT_o + 10'd1;
end
always @(posedge PCLK) begin
HSYNC <= ~(HCNT_o >= HFRONT - 1 && HCNT_o < HFRONT + HWIDTH - 1);
end
// 垂直カウンタ
always @(posedge PCLK) begin
if (RST)
VCNT_o = 10'd0;
if (hs)
if (VCNT_o == VPERIOD - 10'd1)
VCNT_o = 10'd0;
else
VCNT_o <= VCNT_o + 10'd1;
end
always @(posedge PCLK) begin
VSYNC <= ~(VCNT_o >= VFRONT && VCNT_o < VFRONT + VWIDTH);
end
assign HCNT = HCNT_o;
assign VCNT = VCNT_o;
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
apply ST_Plus2.
apply ST_Plus2.
apply ST_PlusConstConst.
Qed.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
apply IHHy1 in H2.
rewrite H2.
reflexivity.
(* rewrite <- (IHHy1 t1'0). <-- Their proof of the same.
reflexivity. assumption. *)
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros t t1 t2 H1 H2.
generalize dependent t2.
step_cases (induction H1) Case; intros t step;
step_cases (inversion step) SCase; subst; try (solve by inversion 2).
reflexivity.
apply IHstep in H3. subst. reflexivity.
apply IHstep in H5. subst. reflexivity.
Qed.
(* inversion H2. rewrite <- H in H1. inversion H1.
That's the Plus1 / Plus2 case; inversion 2 solves this and the others. *)
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0.
Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (P (P (C 2) (C 3)) (C 6)).
split.
apply v_funny.
unfold not.
intros.
unfold normal_form in H.
apply H.
exists (P (C 5) (C 6)).
apply ST_Plus1.
apply ST_PlusConstConst.
Qed.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
intros.
exists (C 5).
split.
apply v_const.
unfold not.
intros.
unfold normal_form in H.
apply H.
exists (P (C 5) (C 0)).
apply ST_Funny.
Qed.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (P (C 5) (P (C 1) (C 2))).
split.
unfold not. intros.
inversion H.
unfold normal_form.
unfold not.
intros.
inversion H.
inversion H0.
inversion H4.
Qed.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* Not Provable *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* Not in a single step! *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
Theorem bool_step_prop3_steps : bool_step_prop3.
unfold bool_step_prop3.
apply ST_If.
apply ST_IfTrue.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
intros.
induction t; try (left; constructor).
right.
inversion IHt1.
inversion H.
exists t2.
apply ST_IfTrue.
exists t3.
apply ST_IfFalse.
inversion H as [t1' t1step].
exists (tif t1' t2 t3).
apply ST_If.
assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
intros.
unfold deterministic.
intros t t1 t2 t1step t2step.
generalize dependent t2.
induction t1step; intros t4 t4step;
inversion t4step; subst; try (solve by inversion 2); try (reflexivity).
apply IHt1step in H3.
subst. reflexivity.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
| ST_short : forall t1 t2 t3,
t2 = t3 ->
tif t1 t2 t3 ==> t2
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
apply ST_short.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Nope; if (if #t #t #t) #t #t can step as
==> #t
or as
==> if #t #t #t
We need an additional constraint (or something).
Optional: prove your answer correct in Coq.
*)
Theorem step_not_deterministic:
exists t t1 t2,
t ==> t1 ->
t ==> t2 ->
t1 <> t2.
Proof.
exists (tif (tif ttrue ttrue ttrue) tfalse tfalse).
exists tfalse.
exists (tif ttrue tfalse tfalse).
intros.
unfold not. intros.
inversion H1.
Qed.
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
It does: we've added an optimization, but every term that
could step before can still step.
Optional: prove your answer correct in Coq.
*)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
intros.
induction t; try (left; constructor).
right.
inversion IHt1.
inversion H.
exists t2; constructor.
exists t3; constructor.
inversion H as [t1' t1step].
exists (tif t1' t2 t3); constructor; assumption.
Qed.
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
Yes. We can easily make strong progress fail by removing, say,
ST_IfFalse. Then the only way to reduce a false in the predicate
position would be to use the short-circuit, which is not always
going to be possible.
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl.
Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_step with (C (0 + 3 + (2 + 4))).
apply ST_PlusConstConst.
apply multi_refl.
Qed.
(* You can just take one step, or you can bottom out at zero steps;
the original proof did this:
apply multi_R.
apply ST_PlusConstConst. Qed. *)
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step. apply ST_Plus2. constructor. apply ST_Plus2; constructor.
apply multi_step with (P (C 0) (C (2 + (0 + 3)))).
apply ST_Plus2. constructor. apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
multi_cases (induction P11) Case.
intros.
multi_cases (inversion P21) SCase.
SCase "multi_refl".
reflexivity.
SCase "multi_step".
subst.
unfold step_normal_form in P12.
unfold normal_form in P12.
apply ex_falso_quodlibet.
apply P12.
exists y. assumption.
Case "multi_step".
intros.
apply IHP11; try assumption.
multi_cases (inversion P21) SCase.
SCase "multi_refl".
subst.
unfold step_normal_form in P22.
unfold normal_form in P22.
apply ex_falso_quodlibet.
apply P22. exists y.
assumption.
SCase "multi_step".
subst.
assert (deterministic step).
apply step_deterministic.
unfold deterministic in H2.
apply H2 with (y1:=y) in H0; try assumption.
rewrite <- H0 in H1.
assumption.
Qed.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
intros t1 t2 t2' tv H.
multi_cases (induction H) Case.
apply multi_refl.
apply multi_step with (P t1 y).
apply ST_Plus2; assumption.
assumption.
Qed.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const.
Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
intros.
tm_cases (induction H) Case.
Case "C".
apply multi_refl.
Case "P".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. assumption.
apply multi_trans with (P (C n1) (C n2)).
apply multistep_congr_2.
apply v_const.
assumption.
apply multi_R.
apply ST_PlusConstConst.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
induction Hs.
intros.
inversion H.
subst.
repeat (constructor).
intros.
inversion H.
apply IHHs in H2.
apply E_Plus; try assumption.
intros.
inversion H0.
apply IHHs in H5.
apply E_Plus; try assumption.
Qed.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
intros t t' H.
induction H.
apply nf_is_value in H0.
inversion H0.
exists n.
split.
reflexivity.
induction H.
rewrite <- H1.
apply E_Const.
apply step__eval with (t':=y).
assumption.
apply IHmulti; assumption.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
intros.
split.
Case "->".
generalize dependent n.
induction t.
intros.
simpl in H; subst.
apply E_Const.
intros.
simpl in H.
inversion H.
apply E_Plus.
apply IHt1; reflexivity.
apply IHt2; reflexivity.
Case "<-".
generalize dependent n.
induction t.
intros.
inversion H.
simpl; reflexivity.
intros.
inversion H.
subst.
apply IHt1 in H2.
apply IHt2 in H4.
simpl.
subst.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic.
intros t t1 t2 t1step t2step.
generalize dependent t2.
step_cases (induction t1step) Case; intros; inversion t2step; subst;
try (solve by inversion 2); try (reflexivity).
apply IHt1step in H2. subst. reflexivity.
apply IHt1step in H4. subst. reflexivity.
apply IHt1step in H3. subst. reflexivity.
Qed.
(* Not sure how to phrase the following proof;
the idea is that tif (C 0) t1 t2 is stuck. *)
Theorem no_strong_progress :
forall (t : tm),
exists t', ~ (normal_form step t').
Admitted.
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
intros.
unfold par_loop.
eapply multi_step. apply CS_Par2. repeat (constructor). (* apply CS_While. *)
eapply multi_step. apply CS_Par2. repeat (constructor).
(* apply CS_IfStep. apply BS_Eq1. apply AS_Id. *)
eapply multi_step. apply CS_Par2. repeat (constructor).
destruct H as [Hx Hy]. rewrite Hy. simpl.
eapply multi_step. apply CS_Par2. repeat (constructor).
eapply multi_step. apply CS_Par2. repeat (constructor).
rewrite Hx.
eapply multi_step. apply CS_Par2. repeat (constructor).
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
fold par_loop.
assert ((n + 1) = S n) by omega.
rewrite H.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
intros.
induction n.
Case "n = 0".
exists st.
split.
apply multi_refl.
assumption.
Case "n = S n".
inversion IHn as [st' nstep].
destruct nstep as [nstep nstate].
exists (update st' X (S n)).
destruct nstate.
split.
apply multi_trans with (par_loop, st').
assumption.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. repeat (constructor).
eapply multi_step. apply CS_Par2. rewrite H1. repeat (constructor). simpl.
eapply multi_step. apply CS_Par2. constructor.
eapply multi_step. apply CS_Par2. apply CS_SeqStep. apply CS_AssStep.
apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep. rewrite H0.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2; apply CS_SeqStep. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
fold par_loop.
assert ((n + 1) = S n) by omega.
rewrite H2.
apply multi_refl.
split; simpl.
apply update_eq.
rewrite update_neq.
assumption.
intro XY; inversion XY.
Qed.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
forall st a n stack,
stack_multistep st (s_compile a, stack) ([], n::stack) <-> (multi (astep st)) a (ANum n).
Lemma multistep_aplus_cong_left :
forall st a1 a1' a2,
(multi (astep st)) a1 a1' ->
(multi (astep st)) (APlus a1 a2) (APlus a1' a2).
Proof.
intros.
induction H.
apply multi_refl.
apply multi_step with (APlus y a2).
apply AS_Plus1. assumption.
assumption.
Qed.
Ltac stack_step_destruct n m IH s :=
apply multi_trans with n;
try (apply multi_R; apply m);
try (apply IH; exists s; split; assumption).
Ltac split_stack_destruct mid H n m :=
exists mid; destruct H; split; try (assumption);
apply multi_trans with n; try (assumption); try (apply multi_R; apply m).
Theorem app_step_stack :
forall st stack e1 e2 stack1,
(exists stack2,
stack_multistep st (e1, stack1) ([], stack2) /\
stack_multistep st (e2, stack2) ([], stack)) <->
stack_multistep st (e1 ++ e2, stack1) ([], stack).
Proof.
intros.
split.
Case "->".
generalize dependent stack1.
induction e1.
SCase "[]".
intros stack2 StackH.
inversion StackH.
destruct H as [H H1].
simpl.
inversion H; try (solve by inversion).
subst.
assumption.
SCase "a :: e1".
intros stack1 stackH.
inversion stackH as [stack2 H].
simpl.
destruct H as [H H2].
inversion H; subst.
inversion H0; subst.
stack_step_destruct (e1 ++ e2, n :: stack1) SS_Push IHe1 stack2.
stack_step_destruct (e1 ++ e2, st i :: stack1) SS_Load IHe1 stack2.
stack_step_destruct (e1 ++ e2, m + n :: stk) SS_Plus IHe1 stack2.
stack_step_destruct (e1 ++ e2, m - n :: stk) SS_Minus IHe1 stack2.
stack_step_destruct (e1 ++ e2, m * n :: stk) SS_Mult IHe1 stack2.
Case "<-".
intros.
generalize dependent stack1.
induction e1.
SCase "[]".
intros.
inversion H; subst.
exists stack0. split; apply multi_refl.
exists stack1. split. apply multi_refl. assumption.
SCase "a :: e1".
intros.
inversion H. subst.
inversion H0; subst; apply IHe1 in H1; inversion H1 as [stackmid H2]; subst.
split_stack_destruct stackmid H2 (e1, n :: stack1) SS_Push.
split_stack_destruct stackmid H2 (e1, st i :: stack1) SS_Load.
split_stack_destruct stackmid H2 (e1, m + n :: stk) SS_Plus.
split_stack_destruct stackmid H2 (e1, m - n :: stk) SS_Minus.
split_stack_destruct stackmid H2 (e1, m * n :: stk) SS_Mult.
Qed.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
unfold compiler_is_correct_statement.
intros.
split.
Case "<-".
(*
intros.
generalize dependent st.
generalize dependent n.
aexp_cases (induction a) SCase; intros; simpl in H.
SCase "ANum".
inversion H. subst. inversion H0. subst. inversion H1. subst. apply multi_refl.
subst. inversion H2.
SCase "AId".
inversion H. subst. inversion H0; subst. inversion H1. subst.
apply multi_R. apply AS_Id.
apply multi_R. inversion H2.
SCase "APlus".
rewrite <- app_step_stack in H.
inversion H as [stack2 H0]; clear H.
destruct H0 as [H1 H2].
rewrite <- app_step_stack in H2.
inversion H2 as [stack0 H3]; clear H2.
destruct H3 as [H3 H4].
inversion H4.
inversion H. subst. inversion H0. subst.
apply multi_trans with (APlus (ANum m) a2).
apply multistep_aplus_cong_left.
apply IHa1.
inversion H3. *)
admit.
Case "->".
intros.
generalize dependent stack0.
generalize dependent st.
generalize dependent n.
aexp_cases (induction a) SCase; intros; simpl.
SCase "ANum".
inversion H; subst.
apply multi_R.
constructor.
inversion H0. subst.
SCase "AId".
inversion H; subst.
inversion H0. subst.
inversion H1. subst.
apply multi_R.
constructor.
inversion H2.
SCase "APlus".
inversion H. subst. inversion H0. subst.
rewrite <- app_step_stack.
exists (n1::stack0).
split.
apply IHa1.
apply multi_refl.
rewrite <- app_step_stack.
exists (n2 :: n1 :: stack0).
Abort.
(* It seems like the theorem is not in the right shape, but
I don't really want to sink more time into this right now. *)
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 4 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 4 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 4 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 4 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 4 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 4 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 4 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 4 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 4 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 4 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 4 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 4 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 4 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 4 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 4 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 4 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 4 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 4 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 4 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 4 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_2x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [3 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [3 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [3 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [3 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [3 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [3 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [3 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [3 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [3 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [3 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [3 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [3 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [3 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [3 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [3 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [3 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [3 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [3 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [3 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [3 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT;
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT;
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT;
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8687;
reg [31 : 0] v__h9062;
reg [31 : 0] v__h9437;
reg [31 : 0] v__h9882;
reg [31 : 0] v__h10251;
reg [31 : 0] v__h10620;
reg [31 : 0] v__h11696;
reg [31 : 0] v__h11942;
reg [31 : 0] v__h12322;
reg [31 : 0] v__h12568;
reg [31 : 0] v__h12945;
reg [31 : 0] v__h13237;
reg [31 : 0] v__h13529;
reg [31 : 0] v__h13832;
reg [31 : 0] v__h14098;
reg [31 : 0] v__h14364;
reg [31 : 0] v__h14628;
reg [31 : 0] v__h14854;
reg [31 : 0] v__h15283;
reg [31 : 0] v__h15639;
reg [31 : 0] v__h15995;
reg [31 : 0] v__h16412;
reg [31 : 0] v__h16744;
reg [31 : 0] v__h17076;
reg [31 : 0] v__h18092;
reg [31 : 0] v__h18343;
reg [31 : 0] v__h18718;
reg [31 : 0] v__h18959;
reg [31 : 0] v__h19334;
reg [31 : 0] v__h19575;
reg [31 : 0] v__h19937;
reg [31 : 0] v__h20188;
reg [31 : 0] v__h20518;
reg [31 : 0] v__h20759;
reg [31 : 0] v__h21089;
reg [31 : 0] v__h21330;
reg [31 : 0] v__h21843;
reg [31 : 0] v__h22244;
reg [31 : 0] v__h5716;
reg [31 : 0] v__h5710;
reg [31 : 0] v__h8681;
reg [31 : 0] v__h9056;
reg [31 : 0] v__h9431;
reg [31 : 0] v__h9876;
reg [31 : 0] v__h10245;
reg [31 : 0] v__h10614;
reg [31 : 0] v__h11690;
reg [31 : 0] v__h11936;
reg [31 : 0] v__h12316;
reg [31 : 0] v__h12562;
reg [31 : 0] v__h12939;
reg [31 : 0] v__h13231;
reg [31 : 0] v__h13523;
reg [31 : 0] v__h13826;
reg [31 : 0] v__h14092;
reg [31 : 0] v__h14358;
reg [31 : 0] v__h14622;
reg [31 : 0] v__h14848;
reg [31 : 0] v__h15277;
reg [31 : 0] v__h15633;
reg [31 : 0] v__h15989;
reg [31 : 0] v__h16406;
reg [31 : 0] v__h16738;
reg [31 : 0] v__h17070;
reg [31 : 0] v__h18086;
reg [31 : 0] v__h18337;
reg [31 : 0] v__h18712;
reg [31 : 0] v__h18953;
reg [31 : 0] v__h19328;
reg [31 : 0] v__h19569;
reg [31 : 0] v__h19931;
reg [31 : 0] v__h20182;
reg [31 : 0] v__h20512;
reg [31 : 0] v__h20753;
reg [31 : 0] v__h21083;
reg [31 : 0] v__h21324;
reg [31 : 0] v__h21837;
reg [31 : 0] v__h22238;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11847,
x__h12473,
x__h18229,
x__h18855,
x__h19471,
x__h21775,
x__h22176;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
x1_avValue_rresp__h18207,
x1_avValue_rresp__h18833,
x1_avValue_rresp__h19449;
wire _dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130,
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159,
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387,
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422,
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540,
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146,
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
8'd0 :
x__h18229 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
8'd0 :
x__h18855 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
8'd0 :
x__h19471 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ?
8'd0 :
x__h11847 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ?
8'd0 :
x__h12473 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ?
8'd0 :
x__h21775 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ?
8'd0 :
x__h22176 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
x1_avValue_rresp__h18207 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
x1_avValue_rresp__h18833 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
x1_avValue_rresp__h19449 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h18207 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18833 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h19449 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11847 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h12473 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h18229 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18855 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h19471 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21775 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h22176 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8687 = $stime;
#0;
end
v__h8681 = v__h8687 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8681,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9062 = $stime;
#0;
end
v__h9056 = v__h9062 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9056,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9437 = $stime;
#0;
end
v__h9431 = v__h9437 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9431,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9882 = $stime;
#0;
end
v__h9876 = v__h9882 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9876,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10251 = $stime;
#0;
end
v__h10245 = v__h10251 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10245,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10620 = $stime;
#0;
end
v__h10614 = v__h10620 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10614,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11696 = $stime;
#0;
end
v__h11690 = v__h11696 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11690,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11942 = $stime;
#0;
end
v__h11936 = v__h11942 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11936,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12322 = $stime;
#0;
end
v__h12316 = v__h12322 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h12316,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8],
fabric_v_rg_wd_beat_count_1,
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12568 = $stime;
#0;
end
v__h12562 = v__h12568 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12562,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12945 = $stime;
#0;
end
v__h12939 = v__h12945 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12939,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13237 = $stime;
#0;
end
v__h13231 = v__h13237 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13231,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13529 = $stime;
#0;
end
v__h13523 = v__h13529 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13523,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13832 = $stime;
#0;
end
v__h13826 = v__h13832 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13826,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14098 = $stime;
#0;
end
v__h14092 = v__h14098 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14092,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14364 = $stime;
#0;
end
v__h14358 = v__h14364 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14358,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14628 = $stime;
#0;
end
v__h14622 = v__h14628 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14622,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14854 = $stime;
#0;
end
v__h14848 = v__h14854 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14848,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15283 = $stime;
#0;
end
v__h15277 = v__h15283 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15277,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15639 = $stime;
#0;
end
v__h15633 = v__h15639 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15633,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15995 = $stime;
#0;
end
v__h15989 = v__h15995 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15989,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16412 = $stime;
#0;
end
v__h16406 = v__h16412 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16406,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16744 = $stime;
#0;
end
v__h16738 = v__h16744 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16738,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17076 = $stime;
#0;
end
v__h17070 = v__h17076 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h17070,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h18092 = $stime;
#0;
end
v__h18086 = v__h18092 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18086,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18343 = $stime;
#0;
end
v__h18337 = v__h18343 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18337,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h18718 = $stime;
#0;
end
v__h18712 = v__h18718 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18712,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18959 = $stime;
#0;
end
v__h18953 = v__h18959 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18953,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h19334 = $stime;
#0;
end
v__h19328 = v__h19334 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19328,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19575 = $stime;
#0;
end
v__h19569 = v__h19575 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19569,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h19937 = $stime;
#0;
end
v__h19931 = v__h19937 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19931,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20188 = $stime;
#0;
end
v__h20182 = v__h20188 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20182,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h20518 = $stime;
#0;
end
v__h20512 = v__h20518 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20512,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20759 = $stime;
#0;
end
v__h20753 = v__h20759 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20753,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h21089 = $stime;
#0;
end
v__h21083 = v__h21089 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h21083,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21330 = $stime;
#0;
end
v__h21324 = v__h21330 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h21324,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21843 = $stime;
#0;
end
v__h21837 = v__h21843 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21837,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h22244 = $stime;
#0;
end
v__h22238 = v__h22244 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h22238,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5716 = $stime;
#0;
end
v__h5710 = v__h5716 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5710);
end
// synopsys translate_on
endmodule // mkFabric_2x3
|
/********************************SATA COMMAND LAYER & TRANSPORT LAYER IMPLEMENTATION*****************************************
************************************************************************************************************/
module sata_transport (
input clk,
input reset,
input DMA_RQST, // host sets during DMA Read or Write operations
input [31:0] data_in, // from host : shadow register write data
input [4:0] addr_reg, // Address line
input [31:0] data_link_in, // from link layer to transport data_in
input LINK_DMA_ABORT, // Notification from Link layer that the DMA Abort primitive was received
input link_fis_recved_frm_dev, // from link layer to inform that new fis received from PHY
input phy_detect, // from link phy detection
input H_write, // from host to transport ...reg H_write
input H_read, // from host to transport ...reg H_read
input link_txr_rdy, // from link, link sends it satus when link receive txr rdy from transport
input r_ok, // from link successful reception
input r_error, // from link error in reception
input illegal_state, // from link link denotes illegal state transition to transport
input end_status, // from link eof
output [31:0] data_link_out, // from transport data out to link
output FRAME_END_T, // T-layer indicates all data for the frame has been transferred
output reg IPF, // interrupt bit is set by the device, TL set interrupt pending flag to host
output reg hold_L, // to link layer :To indicate that the RX Fifo is full
output WRITE_HOLD_U, // inform the host Layer that the TX Fifo is full or RX fifo is empty
output READ_HOLD_U,
output reg txr_rdy, // to link layer transport is H_ready to send pkt to link
output reg [31:0] data_out, // data read from transport to host
output reg EscapeCF_T, // During SRST Link layer shall be informed to send EscapeCF_TP by TL.
output reg UNRECGNZD_FIS_T, // to LL :asserted, when the host TL receives a FIS with unknown type
output reg FIS_ERR, // to link layer
output reg Good_status_T, // to LL : Asserted in return to getting the VALID_CRC_T from the LL
output reg cmd_done, // to host : inidicates that the given command is over
input [31:0] DMA_TX_DATA_IN, // from host : data line for DMA write operation
input DMA_TX_WEN, // from host : data write enable signal to TX FIFO during DMA write
output [31:0] DMA_RX_DATA_OUT, // to host : data line for DMA read operation
input DMA_RX_REN, // from host : data read enable signal to RX FIFO during DMA read
input VALID_CRC_T, // from LL : no CRC error
input data_out_vld_T, // from LL : valid data
input CRC_ERR_T, // from LL : CRC error
input DMA_INIT, // from host : completed DMA initialization
output reg DMA_END,
output DATA_RDY_T, // to LL : T-layer indicates the availability of next Dword
output RX_FIFO_RDY, // Receive FIFO ready
input data_link_rd_en_t, // read enable from link layer for tx data out
input PIO_CLK_IN, // Clock for PIO transfer
input DMA_CLK_IN, // Clock for DMA transfer
input CE, // Chip enable,
input RX_FIFO_RESET, // RX fifo reset
input TX_FIFO_RESET // TX fifo reset
);
parameter DMA_WR_MAX_COUNT = 'h2000; //'h200; //'d8192 bytes
reg [7:0 ] command_register;
reg [15:0] features_register;
reg [7:0 ] control_register;
reg [7:0 ] dev_head_register;
reg [7:0 ] error_register;
reg [15:0] lba_low_register; // lba [0:7] and for 48 bit adrssing prvs value lba[24:31]
reg [15:0] lba_mid_register; // lba [8:15] and for 48 bit adrssing prvs value lba[32:39]
reg [15:0] lba_high_register; // lba [0:7] and for 48 bit adrssing prvs value lba[40:47]
reg [15:0] sector_count_register;
reg [7:0 ] status_register;
reg [31:0] data_register_in;
wire [31:0] data_register_out;
/***********************************************************************************************************
/*-------------------------DEVISE CONTROL REGISTER--------------
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HOB | - | - | - | - | SRST | nIEN | 0 |
---------------------------------------------------------------
7.HOB : higher order byte is defined by the 48bit Address feature set.
A H_write to any Command register shall clear the HOB bit to zero.
2.SRST :software reset bit
1.nIEN :intrupt enable bit
/*-----------------DEVISE/HEAD REGISTER----------------------------------------
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | L | - | - | DEV | HS3 | HS1 | HS0 |
------------------------------------------------------------------------------
1.DEV : devise selection bit
2.HS3
3.HS2 : Head select bits. The HS3 through HS0 contain bits 24-27 of the LBA.
4.HS0 At command completion, these bits are updated to reflect the current LBA bits24-27
/*-----------------ERROR REGISTER-------------------------------------------
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ICRC | UNC | 0 | IDNF | 0 | ABRT | TKONF | AMNF |
----------------------------------------------------------------------------
ICRC : Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus
during a Ultra-DMA transfer.
UNC : Uncorrectable Data Error. UNC=1 indicates an uncorrectable
data error has been encountered.
IDNF : ID Not Found. IDN=1 indicates the requested sectors ID field cound not be found .
ABRT : Aborted Command. ABT=1 indicates the requested command has been aborted
due to a device status error or an invalid parameter in an output register.
TKONF : Track 0 Not Found. T0N=1 indicates track 0 was not found during a
Recalibrate command.
AMNF : Address Mark Not Found. When AMN=1, it indicates that the data address mark
has not been found after finding the correct ID field for the requested sector.
/*-----------------STATUS REGISTER----------------------------------- -------------
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BSY | DRDY | DF | DSC | DRQ | CORR | IDX | ERR |
-----------------------------------------------------------------------------------
Definition :
1.BSY : busy bit
2.DRDY : devise H_ready bit
3.DF : devise fault
4.DSC : devise seek complete
5.DRQ : data request
6.corr : corrected data
7.IDX : index
8.ERR : error
*********************************************************************************************************** */
/***********internal signals**********************/
reg [31:0] fis_reg_DW0;
reg [31:0] fis_reg_DW1;
reg [31:0] fis_reg_DW2;
reg [31:0] fis_reg_DW3;
reg [31:0] fis_reg_DW4;
reg [31:0] fis_reg_DW5;
reg [31:0] fis_reg_DW6;
reg [31:0] DMA_Buffer_Identifier_Low;
reg [31:0] DMA_Buffer_Identifier_High;
reg [31:0] DMA_Buffer_Offset;
reg [31:0] DMA_Transfer_Count;
reg [2:0] fis_count;
reg [4:0] state;
reg detection;
reg cmd_en;
reg ctrl_en;
reg tx_wen_pio;
reg [15:0] count;
reg [15:0] H_read_count;
reg rcv_fifo_wr_en;
reg [31:0] data_rcv_fifo;
reg prvs_pio;
reg Status_init;
reg Pending_DMA;
reg ctrl_srst_en;
reg [15:0] Transfer_cnt_PIO;
reg [15:0] recv_pio_dma_cnt;
reg rcv_fifo_rd_en_dly;
// added by Shameerudheen
reg [31:0] data_link_out_int;
reg data_link_out_wr_en;
reg tl_ll_tx_fifo_reset;
reg pio_rcv_flag;
reg tx_fifo_pio_rd_en;
reg [7:0] temp_status_reg;
reg direction_bit; //1 device to host; 0 host to device
reg tx_fifo_pio_wr_en;
reg [31:0] rcv_fifo_din;
//reg [31:0] Transfer_cnt_DMA;
reg DMA_rcv_flag;
reg [15:0] recv_dma_cnt;
reg tx_fifo_dma_rd_en;
reg [3:0] rst_delay_count;
reg [4:0] dest_state;
wire tx_fifo1_reset;
wire rx_fifo1_reset;
wire tx_fifo_empty;
wire[31:0] tx_fifo_dout;
wire rcv_fifo_full;
wire rcv_fifo_almost_empty;
wire [31:0] rcv_fifo_data_out;
wire tx_wen_fifo;
wire [31:0] tx_data_fifo;
wire rcv_fifo_rd_en;
wire rx_ren_pio;
wire txr_ren_pio;
//wire tx_fifo_dma_rd_en;
wire link_txr_rdy_PIO;
// added by Shameerudheen
wire tl_ll_tx_fifo_empty;
wire tl_ll_tx_fifo_almost_empty;
wire rcv_fifo_prog_full;
wire rx_fifo_pio_rd_en;
wire rx_fifo_rd_clk;
wire tx_fifo_prog_full;
wire tl_ll_tx_fifo_full;
wire tx_fifo_almost_empty;
wire [31:0] tx_fifo_din;
/*************************states************************************/
parameter HT_HostIdle = 5'h 0 ;
parameter HT_ChkTyp = 5'h 1 ;
parameter HT_CmdFIS = 5'h 2 ;
parameter HT_CntrlFIS = 5'h 3 ;
parameter HT_DMASTUPFIS = 5'h 4 ;
parameter HT_DMASTUPTransStatus = 5'h 5 ;
parameter HT_CtrlTransStatus = 5'h 6 ;
parameter HT_PIOOTrans2 = 5'h 7 ;
parameter HT_RegFIS = 5'h 8 ;
parameter HT_DB_FIS = 5'h 9 ;
parameter HT_DMA_FIS = 5'h A ;
parameter HT_PS_FIS = 5'h B ;
parameter HT_DS_FIS = 5'h C ;
parameter HT_RcvBIST = 5'h D ;
parameter HT_DMAITrans = 5'h E ;
parameter HT_PIOITrans1 = 5'h F ;
parameter HT_CmdTransStatus = 5'h 10 ;
parameter HT_RegTransStatus = 5'h 11 ;
parameter HT_PIOEnd = 5'h 12 ;
parameter HT_PIOOTrans1 = 5'h 13 ;
parameter HT_PIOITrans2 = 5'h 14 ;
parameter HT_DMAOTrans1 = 5'h 15 ;
parameter HT_DMAOTrans2 = 5'h 16 ;
parameter HT_DMAEnd = 5'h 17 ;
parameter HT_tl_ll_tx_fifo_rst_delay = 5'h 18;
/***************ADDRESS PARAMETER***************************************/
parameter cmd_reg = 8'd1 ;
parameter ctrl_reg = 8'd2 ;
parameter feature_reg = 8'd3 ;
parameter stuts_reg = 8'd4 ;
parameter head_reg = 8'd5 ;
parameter error_reg = 8'd6 ;
parameter lba_low = 8'd7 ;
parameter lba_mid = 8'd8 ;
parameter lba_high = 8'd9 ;
parameter sect_count = 8'd10 ;
parameter data_reg = 8'd11 ;
parameter DEVICE_RESET = 8'h08 ;
//assign Transfer_cnt_DMA = sector_count_register;
assign rx_ren_pio = (~rcv_fifo_almost_empty);
assign txr_ren_pio = (~tx_fifo_empty && link_txr_rdy_PIO && (state == HT_PIOOTrans2 ) && (count!= 'd2044));
assign link_txr_rdy_PIO = link_txr_rdy? 1'b1:txr_ren_pio;
//assign tx_fifo_dma_rd_en = (~tx_fifo_empty && link_txr_rdy_PIO && (state == HT_DMAOTrans2 ) && (count!= 'd2044));
always @(posedge clk)
begin
if(reset) begin
rcv_fifo_rd_en_dly <= 1'b0;
end
else begin
rcv_fifo_rd_en_dly <= rx_ren_pio;
end
end
//***************************** makindg PIO Data Transfer count *****************************
always @(posedge clk, posedge reset) begin
if(reset) begin
Transfer_cnt_PIO <= 1'b0 ;
end
else begin
if(state == HT_PIOITrans1 || state == HT_PIOOTrans1) begin
Transfer_cnt_PIO <= fis_reg_DW4[15:0] ;
end
else begin
Transfer_cnt_PIO <= Transfer_cnt_PIO ;
end
end
end
//***************************** makindg cmd _en & cntrl_en signals *****************************
always @(posedge clk) begin
if(reset) begin
cmd_en <= 1'b0 ;
ctrl_en <= 1'b0 ;
ctrl_srst_en <= 1'b0 ;
end
else if(addr_reg == cmd_reg && H_write && CE &&((!status_register[7] && !status_register[3]) || (data_in == DEVICE_RESET)))
cmd_en <= 1'b1 ;
else if(addr_reg == ctrl_reg && H_write && CE) begin
if(data_in[2] == 1'b1)
ctrl_srst_en <= 1'b1 ;
else
ctrl_en <= 1'b1 ;
end
else if(state == HT_CmdTransStatus && r_ok)
cmd_en <= 1'b0 ;
else if(state == HT_CtrlTransStatus && r_ok) begin
if(ctrl_srst_en)
ctrl_srst_en <= 1'b0 ;
else
ctrl_en <= 1'b0 ;
end
else begin
cmd_en <= cmd_en ;
ctrl_en <= ctrl_en ;
ctrl_srst_en <= ctrl_srst_en ;
end
end
//*****************************************status register updation******************************************************
always @(posedge clk, posedge reset)
begin
if(reset) begin
Status_init <= 1'b0 ;
detection <= 1'b0 ;
status_register <= 8'h80 ;
end
else if(phy_detect && !Status_init) begin
status_register <= 8'h80 ;
detection <= 1'b1 ;
Status_init <= 1'b1 ;
end
else if(!phy_detect && Status_init) begin
status_register <= 8'hff ;
detection <= 1'b0 ;
Status_init <= 1'b0 ;
end
else if(state == HT_RegTransStatus && VALID_CRC_T) begin
status_register <= fis_reg_DW0[23:16] ;
end
else if(H_write && (addr_reg == cmd_reg ) && CE) begin
status_register[7] <= 1'd1 ;
end
else if(H_write && CE && (addr_reg == ctrl_reg) && (data_in[2]== 1'b1)) begin
status_register[7] <= 1'd1 ;
end
else if(state == HT_PIOITrans1) begin
//status_register <= fis_reg_DW0[23:16] ;
status_register <= temp_status_reg ; // Updating initial status during PIO read
end
else if(state == HT_PIOOTrans1 ) begin
//status_register <= fis_reg_DW0[23:16];
status_register <= temp_status_reg; // Updating initial status during PIO write
end
else if(state == HT_PIOEnd ) begin
status_register[7:1] <= fis_reg_DW3[31:23]; //Ending status, error bit updating seperatly
//for PIO DATA transfer error reporting; need to check whether this bit has to be updated or any other bit.
if(illegal_state || r_error || CRC_ERR_T) begin
status_register[0] <= 1;
end
else if(r_ok || VALID_CRC_T) begin
status_register[0] <= 0;
end
else begin
status_register[0] <= status_register[0];
end
end
//for DMA DATA transfer error reporting; need to check whether this bit has to be updated or any other bit.
else if(state == HT_DMAEnd && (illegal_state || r_error || CRC_ERR_T) ) begin
status_register[0] <= 1;
status_register[7] <= 1'd0;
status_register[3] <= 1'd0;
end
else if(state == HT_DMAEnd && (r_ok || VALID_CRC_T) ) begin
status_register[0] <= 0;
end
else if (state == HT_PIOITrans1 || state == HT_PIOITrans2 || state == HT_PIOOTrans2 ||
state == HT_PIOOTrans1 || state == HT_DMAOTrans1 || state == HT_DMAOTrans2 || state == HT_DMAITrans) begin
if (illegal_state) begin
status_register[0] <= 1;
end
else begin
status_register[0] <= 0;
end
end
else begin
status_register <= status_register; //Ending status
end
end //always
//IPF Iterupt pending flag setting.
always @(posedge clk, posedge reset)
begin
if(reset) begin
IPF <= 0;
end
else begin
if((state == HT_RegTransStatus && VALID_CRC_T) ||
(state == HT_PIOITrans1) ||
(state == HT_PIOOTrans1) ) begin
IPF <= fis_reg_DW0[14];
end
else if(state == HT_DMAEnd && (r_ok || VALID_CRC_T) ) begin
IPF <= 1;
end
else if (H_write && addr_reg == cmd_reg && CE) begin
IPF <= 0;
end
else if (H_read && addr_reg == stuts_reg && CE) begin
IPF <= 0;
end
else begin
IPF <= IPF;
end
end
end //always
//*************************************************************************************************
//..................register writing for shadow registers and trigger generation..................*
//*************************************************************************************************
always @(posedge clk)
begin
if(reset) begin
command_register <= 8'hff ;
control_register <= 8'h00 ;
features_register <= 16'h0000 ;
dev_head_register <= 8'h00 ;
error_register <= 8'h00 ;
lba_low_register <= 16'h0000 ;
lba_mid_register <= 16'h0000 ;
lba_high_register <= 16'h0000 ;
sector_count_register <= 16'h0000 ;
data_register_in <= 32'd0 ;
//IPF <= 1'b0 ;
//HOLD_U <= 1'b0 ;
tx_wen_pio <= 1'b0 ;
tx_fifo_pio_wr_en <= 0;
end
// shadow register writing.........only bsy bit and drdy is proper........//
else begin
//if(H_write && !DMA_RQST) begin
if(H_write && CE) begin
case(addr_reg )
cmd_reg: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]) || (data_in == DEVICE_RESET) )begin
command_register <= data_in ;
end
else begin
command_register <= command_register ;
end
end
ctrl_reg: begin
control_register <= data_in ;
end
feature_reg: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
features_register <= data_in ;
end
else begin
features_register <= features_register ;
end
end
head_reg: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
dev_head_register <= data_in ;
end
else begin
dev_head_register <= dev_head_register ;
end
end
error_reg: begin
tx_fifo_pio_wr_en <= 0;
error_register <= data_in ;
end
lba_low: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
lba_low_register <= data_in ;
end
else begin
lba_low_register <= lba_low_register ;
end
end
lba_mid: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
lba_mid_register <= data_in ;
end
else begin
lba_mid_register <= lba_mid_register ;
end
end
lba_high: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
lba_high_register <= data_in ;
end
else begin
lba_high_register <= lba_high_register ;
end
end
sect_count: begin
tx_fifo_pio_wr_en <= 0;
if((!status_register[7] && !status_register[3]))begin
sector_count_register <= data_in;
end
else begin
sector_count_register <= sector_count_register;
end
end
data_reg: begin
//if((!status_register[7] && status_register[3]))begin
data_register_in <= data_in;
tx_fifo_pio_wr_en <= 1;
//end
//else begin
// data_register_in <= 32'h0;
// tx_fifo_pio_wr_en <= 0;
//end
end
endcase
end
else if((state == HT_RegTransStatus && VALID_CRC_T) ||
(state == HT_PIOITrans1) ||
(state == HT_PIOOTrans1) ) begin
//if (control_register[1] == 1) begin
// IPF <= 0;
//end
//else begin
// IPF <= fis_reg_DW0[14];
//end
error_register <= fis_reg_DW0[31:24];
dev_head_register <= fis_reg_DW1[31:24];
lba_low_register <= {fis_reg_DW2[7:0], fis_reg_DW1[7:0]};
lba_mid_register <= {fis_reg_DW2[15:8], fis_reg_DW1[15:8]};
lba_high_register <= {fis_reg_DW2[23:16], fis_reg_DW1[23:16]};
sector_count_register <= fis_reg_DW3[15:0];
tx_fifo_pio_wr_en <= 0;
end
else begin
tx_wen_pio <= 0;
tx_fifo_pio_wr_en <= 0;
//HOLD_U <= 1'b0;
end
end
end
//*********************************************************************
// ..........H_readING OF SHADOW REGISTER...............................*
//*********************************************************************
// shadow register H_reading.........only bsy bit and drdy is proper....//
//always @(posedge clk)
always @(*)
begin
if(H_read && detection && CE ) begin
case(addr_reg)
cmd_reg :
begin
data_out <= command_register;
end
ctrl_reg :
begin
data_out <= control_register;
end
feature_reg :
begin
data_out <= features_register;
end
head_reg :
begin
data_out <= dev_head_register;
end
error_reg :
begin
data_out <= error_register;
end
lba_low :
begin
data_out <= lba_low_register;
end
lba_mid :
begin
data_out <= lba_mid_register;
end
lba_high :
begin
data_out <= lba_high_register;
end
sect_count :
begin
data_out <= sector_count_register;
end
stuts_reg:
begin
data_out <= status_register;
end
data_reg:
begin
data_out <= data_register_out;
end
default:
begin
data_out <= 'h80;
end
endcase
end
else begin
data_out <= 'h80;
end
end
//*************************************************************************
//.....................MAIN STATE.........................................*
//*************************************************************************
always @(posedge clk) begin
if (reset) begin
txr_rdy <= 1'b0;
state <= HT_HostIdle ;
H_read_count <= 16'd0;
rcv_fifo_wr_en <= 1'b0;
data_rcv_fifo <= 32'd0;
data_link_out_int <= 32'd0;
//frame_end_T <= 1'b0;
FIS_ERR <= 1'b0;
UNRECGNZD_FIS_T <= 1'b0;
Good_status_T <= 1'b0;
hold_L <= 1'b0;
recv_pio_dma_cnt <= 16'd0;
count <= 16'b0;
cmd_done <= 1'd0;
prvs_pio <= 1'b0;
fis_reg_DW0 <= 32'b0;
fis_reg_DW1 <= 32'b0;
fis_reg_DW2 <= 32'b0;
fis_reg_DW3 <= 32'b0;
fis_reg_DW4 <= 32'b0;
fis_reg_DW5 <= 32'b0;
fis_reg_DW6 <= 32'b0;
fis_count <= 3'd0;
EscapeCF_T <= 1'b0;
//data_rdy_T <= 1'b0;
tl_ll_tx_fifo_reset <= 0;
data_link_out_wr_en <= 0;
pio_rcv_flag <= 0;
tx_fifo_pio_rd_en <= 0;
temp_status_reg <= 8'h00;
direction_bit <= 1;
//Transfer_cnt_DMA <= 32'b0;
DMA_rcv_flag <= 0;
recv_dma_cnt <= 16'h0;
rst_delay_count <= 3'h0;
end
else if(detection) begin
case(state)
HT_HostIdle: begin
data_rcv_fifo <= 32'd0;
FIS_ERR <= 1'b0;
UNRECGNZD_FIS_T <= 1'b0;
Good_status_T <= 1'b0;
EscapeCF_T <= 1'b0;
//data_link_out_wr_en <= 0;
//frame_end_T <= 1'b0;
pio_rcv_flag <= 0;
DMA_rcv_flag <= 0;
recv_dma_cnt <= 16'h0;
rst_delay_count <= 3'h0;
if(link_fis_recved_frm_dev ) begin
state <= HT_ChkTyp;
fis_count <= 3'd0;
end
else if(ctrl_srst_en) begin
dest_state <= HT_CntrlFIS;
state <= HT_tl_ll_tx_fifo_rst_delay;
//txr_rdy <= 1'b1;
fis_count <= 3'd0;
tl_ll_tx_fifo_reset <= 1;
end
else if(cmd_en) begin
dest_state <= HT_CmdFIS;
state <= HT_tl_ll_tx_fifo_rst_delay;
//txr_rdy <= 1'b1;
fis_count <= 3'd0;
tl_ll_tx_fifo_reset <= 1;
end
else if(ctrl_en) begin
//txr_rdy <= 1'b1;
dest_state <= HT_CntrlFIS;
state <= HT_tl_ll_tx_fifo_rst_delay;
fis_count <= 3'd0;
tl_ll_tx_fifo_reset <= 1;
end
else if(prvs_pio && !tx_fifo_empty ) begin //H_write && (addr_reg == data_reg)
tl_ll_tx_fifo_reset <= 0;
if(link_txr_rdy) begin
data_link_out_int <= 32'h0046;
data_link_out_wr_en <= 1;
tx_fifo_pio_rd_en <= 1;
txr_rdy <= 1'b0;
state <= HT_PIOOTrans2;
prvs_pio <= 1'b0;
end
else begin
state <= HT_HostIdle;
txr_rdy <= 1'b1;
prvs_pio <= 1'b1;
data_link_out_wr_en <= 0;
tx_fifo_pio_rd_en <= 0;
end
end
//else if(DMA_RQST || Pending_DMA) begin //hav to check later
else if(Pending_DMA) begin
state <= HT_DMASTUPFIS;
txr_rdy <= 1'b1;
tl_ll_tx_fifo_reset <= 1;
tx_fifo_pio_rd_en <= 0;
end
end
HT_tl_ll_tx_fifo_rst_delay: begin
rst_delay_count <= rst_delay_count + 1;
tl_ll_tx_fifo_reset <= 0;
if (rst_delay_count == 3'h 4) begin
state <= dest_state;
txr_rdy <= 1;
end
else begin
state <= HT_tl_ll_tx_fifo_rst_delay;
txr_rdy <= 0;
end
end
HT_ChkTyp:
begin
if(illegal_state) begin
state <= HT_HostIdle;
UNRECGNZD_FIS_T <= 0;
end
else if(data_out_vld_T) begin
fis_count <= fis_count + 1'b 1;
fis_reg_DW0 <= data_link_in;
if(data_link_in[7:0] == 8'h34) begin //Reg FIS
state <= HT_RegFIS;
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'hA1) begin //Set Device Bits FIS Device to Host
state <= HT_DB_FIS;
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'h39) begin //DMA Active FIS Device to Host
state <= HT_DMA_FIS;
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'h5F) begin //PIO Setup FIS Device to Host
state <= HT_PS_FIS;
prvs_pio <= 1'b1;
UNRECGNZD_FIS_T <= 0;
temp_status_reg <= data_link_in[23:16];
end
else if(data_link_in[7:0] == 8'h41) begin //DMA Setup FIS -- Bidirectional
state <= HT_HostIdle; // HT_DS_FIS; not implemented
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'h58) begin //BIST Active FIS Bi-Directional
state <= HT_HostIdle; //HT_RcvBIST; not implemented
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'h46 && prvs_pio) begin //DATA FIS Biderectional and previous PIO FIS
state <= HT_PIOITrans1;
rcv_fifo_wr_en <= 0;
recv_pio_dma_cnt <= recv_pio_dma_cnt + 'd4;
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
end
else if(data_link_in[7:0] == 8'h46) begin //DATA FIS Biderectional no previous PIO (for DMA)
state <= HT_DMAITrans;
prvs_pio <= 1'b0;
UNRECGNZD_FIS_T <= 0;
recv_dma_cnt <= 16'h0;
rcv_fifo_wr_en <= 0;
DMA_rcv_flag <= 1;
//Transfer_cnt_DMA <= Transfer_cnt_DMA - 'd4;
end
else begin
state <= HT_HostIdle;
UNRECGNZD_FIS_T <= 1;
end
end
else begin
state <= state;
UNRECGNZD_FIS_T <= 0;
end
end
HT_CmdFIS: begin
tl_ll_tx_fifo_reset <= 0;
if(link_fis_recved_frm_dev) begin
state <= HT_ChkTyp; // new Fis is received in the linklayer from device
fis_count <= 0;
data_link_out_wr_en <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle;
fis_count <= 0;
data_link_out_wr_en <= 0;
end
else if(link_txr_rdy) begin
txr_rdy <= 0;
data_link_out_int <= {features_register[7:0],command_register,8'h80,8'h27};
fis_count <= fis_count + 1;
//data_rdy_T <= 1'b1;
state <= state;
data_link_out_wr_en <= 1;
end
else if(fis_count == 1) begin
data_link_out_int <= {dev_head_register,lba_high_register[7:0],lba_mid_register[7:0],lba_low_register[7:0]};
fis_count <= fis_count + 1;
state <= state ;
data_link_out_wr_en <= 1;
end
else if(fis_count == 2) begin
data_link_out_int <= {features_register[15:8],lba_high_register[15:8],lba_mid_register[15:8],lba_low_register[15:8]} ;
fis_count <= fis_count + 1 ;
state <= state ;
data_link_out_wr_en <= 1;
end
else if(fis_count == 3) begin
data_link_out_int <= {control_register,8'd0,sector_count_register[15:8],sector_count_register[7:0]} ;
fis_count <= fis_count + 1;
//data_rdy_T <= 1'b0;
state <= state;
data_link_out_wr_en <= 1;
//Transfer_cnt_DMA <= {7'b0, sector_count_register[15:0], 9'b0};
end
else if(fis_count == 4) begin
data_link_out_int <= {32'h00};
fis_count <= 0;
state <= HT_CmdTransStatus;
data_link_out_wr_en <= 1;
//frame_end_T <= 1'b1;
end
else begin
state <= state;
data_link_out_wr_en <= 0;
end
end
HT_CmdTransStatus: begin
data_link_out_wr_en <= 0;
if(r_ok) begin
state <= HT_HostIdle ;
cmd_done <= 1'b1;
end
else if(r_error || illegal_state) begin
state <= HT_HostIdle ;
cmd_done <= 1'b0;
end
else begin
state <= state ;
end
end
HT_CntrlFIS:
begin
tl_ll_tx_fifo_reset <= 0;
if(link_fis_recved_frm_dev) begin
state <= HT_ChkTyp ; // new Fis is received in the linklayer from device
fis_count <= 3'd0 ;
end
else if(illegal_state) begin
state <= HT_HostIdle ;
data_link_out_wr_en <= 0;
end
else if(link_txr_rdy) begin
txr_rdy <= 1'b0 ;
//data_link_out_int <= {features_register[7:0],command_register,8'h00,8'h27} ;
data_link_out_int <= {24'h 0, 8'h 27};
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
//data_rdy_T <= 1'b1 ;
state <= state ;
end
else if(fis_count==3'd1) begin
//data_link_out_int <= {dev_head_register,lba_high_register[7:0],lba_mid_register[7:0],lba_low_register[7:0]} ;
data_link_out_int <= 32'h 0;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd2) begin
//data_link_out_int <= {features_register[15:8],lba_high_register[15:8],lba_mid_register[15:8],lba_low_register[15:8]} ;
data_link_out_int <= 32'h 0;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd3) begin
//data_link_out_int <= {control_register,8'd0,sector_count_register[15:8],sector_count_register[7:0]} ;
data_link_out_int <= {control_register, 24'h 0};
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
//data_rdy_T <= 1'b0 ;
state <= state ;
end
else if(fis_count==3'd4) begin
data_link_out_int <= {32'h00} ;
data_link_out_wr_en <= 1;
fis_count <= 3'd0 ;
state <= HT_CtrlTransStatus ;
//frame_end_T <= 1'b1 ;
end
else begin
state <= state ;
data_link_out_wr_en <= 0;
end
end
HT_CtrlTransStatus:
begin
data_link_out_wr_en <= 0;
if(r_ok) begin
state <= HT_HostIdle ;
end
else if(r_error || illegal_state) begin
state <= HT_HostIdle ;
end
else begin
state <= state ;
end
end
HT_DMASTUPFIS:
begin
tl_ll_tx_fifo_reset <= 0;
if(link_fis_recved_frm_dev) begin
state <= HT_ChkTyp ; // new Fis is received in the linklayer from device
fis_count <= 3'd0 ;
end
else if(illegal_state) begin
data_link_out_wr_en <= 0;
state <= HT_HostIdle ;
end
else if(link_txr_rdy) begin
txr_rdy <= 1'b0 ;
data_link_out_int <= {16'h0,8'h50,8'h41} ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
//data_rdy_T <= 1'b1 ;
state <= state ;
end
else if(fis_count==3'd1) begin
data_link_out_int <= DMA_Buffer_Identifier_Low ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd2) begin
data_link_out_int <= DMA_Buffer_Identifier_High ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd3) begin
data_link_out_int <= 32'h0 ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd4) begin
data_link_out_int <= DMA_Buffer_Offset ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
state <= state ;
end
else if(fis_count==3'd5) begin
data_link_out_int <= DMA_Transfer_Count ;
data_link_out_wr_en <= 1;
fis_count <= fis_count+1 ;
//data_rdy_T <= 1'b0 ;
state <= state ;
end
else if(fis_count==3'd6) begin
data_link_out_int <= 32'h0 ;
data_link_out_wr_en <= 1;
fis_count <= 3'd0 ;
state <= HT_DMASTUPTransStatus ;
//frame_end_T <= 1'b1 ;
end
else begin
state <= state ;
data_link_out_wr_en <= 0;
end
end
HT_DMASTUPTransStatus:
begin
data_link_out_wr_en <= 0;
if(r_error || illegal_state) begin
Pending_DMA <= 1'b1 ;
state <= HT_HostIdle ;
end
else if(r_ok) begin
Pending_DMA <= 1'b0 ;
state <= HT_HostIdle ;
end
else begin
Pending_DMA <= Pending_DMA ;
state <= state ;
end
end
HT_DMA_FIS: //DMA Activate FIS
begin
if(VALID_CRC_T) begin
Good_status_T <= 1'b1;
dest_state <= HT_DMAOTrans1;
state <= HT_tl_ll_tx_fifo_rst_delay;
tl_ll_tx_fifo_reset <= 1;
end
else if(CRC_ERR_T) begin
state <= HT_HostIdle ;
Good_status_T <= 1'b0;
end
else if(illegal_state) begin
state <= HT_HostIdle ;
Good_status_T <= 0;
end
else begin
state <= HT_DMA_FIS ;
Good_status_T <= 0;
end
end
HT_DMAOTrans1:
begin
Good_status_T <= 0;
tl_ll_tx_fifo_reset <= 0;
if(control_register[2] || (command_register == DEVICE_RESET)) begin
state <= HT_HostIdle;
EscapeCF_T <= 1'b1;
tl_ll_tx_fifo_reset <= 0;
tx_fifo_dma_rd_en <= 0;
end
//else if(!DMA_INIT) begin
else if(!DMA_RQST) begin
state <= HT_DMAOTrans1;
EscapeCF_T <= 1'b0;
tl_ll_tx_fifo_reset <= 0;
tx_fifo_dma_rd_en <= 0;
end
else if(DMA_RQST) begin
if(link_txr_rdy) begin
data_link_out_int <= 32'h0046;
data_link_out_wr_en <= 1;
tx_fifo_dma_rd_en <= 1;
txr_rdy <= 1'b0;
state <= HT_DMAOTrans2;
prvs_pio <= 1'b0;
end
else begin
state <= HT_DMAOTrans1;
txr_rdy <= 1'b1;
data_link_out_wr_en <= 0;
tx_fifo_dma_rd_en <= 0;
end
EscapeCF_T <= 1'b0;
recv_pio_dma_cnt <= 0;
end
else begin
state <= HT_DMAOTrans1;
EscapeCF_T <= 1'b0;
tl_ll_tx_fifo_reset <= 0;
tx_fifo_dma_rd_en <= 0;
end
end
HT_DMAOTrans2:
begin
tl_ll_tx_fifo_reset <= 0;
data_link_out_int <= tx_fifo_dout;
if(LINK_DMA_ABORT) begin
state <= HT_DMAEnd;
tx_fifo_dma_rd_en <= 0;
data_link_out_wr_en <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle;
tx_fifo_dma_rd_en <= 0;
data_link_out_wr_en <= 0;
end
else if(control_register[2] || (command_register == DEVICE_RESET)) begin
state <= HT_HostIdle;
EscapeCF_T <= 1'b1;
tx_fifo_dma_rd_en <= 0;
data_link_out_wr_en <= 0;
end
else if(tx_fifo_empty || recv_pio_dma_cnt == DMA_WR_MAX_COUNT ) begin
state <= HT_DMAEnd;
count <= 16'b0;
tx_fifo_dma_rd_en <= 0;
data_link_out_wr_en <= 0;
recv_pio_dma_cnt <= 16'b0;
end
else if(!tl_ll_tx_fifo_full && !tx_fifo_empty) begin
if (tx_fifo_almost_empty || recv_pio_dma_cnt == (DMA_WR_MAX_COUNT - 4)) begin
tx_fifo_dma_rd_en <= 0;
end
else begin
tx_fifo_dma_rd_en <= 1;
end
data_link_out_wr_en <= 1;
recv_pio_dma_cnt <= recv_pio_dma_cnt+'d4;
state <= HT_DMAOTrans2;
end
else begin
tx_fifo_dma_rd_en <= 0;
data_link_out_wr_en <= 0;
state <= HT_DMAOTrans2 ;
recv_pio_dma_cnt <= recv_pio_dma_cnt;
end
end
HT_DMAEnd:
begin
if (DMA_rcv_flag) begin
if (VALID_CRC_T) begin
Good_status_T <= 1;
state <= HT_HostIdle;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
else if (CRC_ERR_T || illegal_state) begin
Good_status_T <= 0;
state <= HT_HostIdle;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
else begin
Good_status_T <= 0;
state <= HT_DMAEnd;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
end
else begin
if (illegal_state) begin
Good_status_T <= 0;
state <= HT_HostIdle;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
else if (r_ok || r_error) begin
Good_status_T <= 0;
state <= HT_HostIdle;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
else begin
Good_status_T <= 0;
state <= HT_DMAEnd;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 0;
end
end
end
HT_DMAITrans:
begin
if (control_register[2]|| (command_register == DEVICE_RESET)) begin
EscapeCF_T <= 1;
state <= HT_HostIdle;
end
else if(illegal_state) begin
state <= HT_HostIdle;
EscapeCF_T <= 0;
end
else if (end_status) begin
EscapeCF_T <= 0;
state <= HT_DMAEnd;
rcv_fifo_wr_en <= 0;
end
else begin
if (data_out_vld_T) begin
data_rcv_fifo <= data_link_in;
state <= HT_DMAITrans;
EscapeCF_T <= 0;
rcv_fifo_wr_en <= 1;
end
else begin
rcv_fifo_wr_en <= 0;
EscapeCF_T <= 0;
state <= HT_DMAITrans;
end
end
end
HT_RegFIS:
begin
if(illegal_state) begin
state <= HT_HostIdle ;
end
else if(fis_count <= 3'd4 && data_out_vld_T ) begin
state <= state ;
fis_count <= fis_count+1'b 1 ;
if(fis_count == 'd1) begin
fis_reg_DW1 <= data_link_in ;
end
else if(fis_count =='d2) begin
fis_reg_DW2 <= data_link_in ;
end
else if(fis_count =='d3) begin
fis_reg_DW3 <= data_link_in ;
end
else if(fis_count =='d4) begin
fis_reg_DW4 <= data_link_in ;
end
end
else if(end_status) begin
state <= HT_RegTransStatus ;
end
else begin
state <= state ;
fis_count <= fis_count ;
end
end
HT_RegTransStatus:
begin
if(CRC_ERR_T || illegal_state) begin
FIS_ERR <= 1'b1 ;
state <= HT_HostIdle ;
Good_status_T <= 1'b0 ;
end
else if(VALID_CRC_T) begin
Good_status_T <= 1'b1 ;
state <= HT_HostIdle ;
end
else begin
state <= state ;
Good_status_T <= Good_status_T ;
end
end
HT_PS_FIS: begin
if(fis_count <= 3'd4 && data_out_vld_T) begin
fis_count <= fis_count+1;
state <= state;
if(fis_count == 'd1) begin
fis_reg_DW1 <= data_link_in;
end
else if(fis_count ==3'd2) begin
fis_reg_DW2 <= data_link_in;
end
else if(fis_count ==3'd3) begin
fis_reg_DW3 <= data_link_in;
end
else if(fis_count ==3'd4) begin
fis_reg_DW4 <= data_link_in;
end
end
else if(VALID_CRC_T) begin
Good_status_T <= 1'b1 ;
direction_bit <= fis_reg_DW0[13];
if(fis_reg_DW0[13] == 0) begin //data transfer Direction host to device
state <= HT_PIOOTrans1;
H_read_count <= 'd0;
end
else begin
state <= HT_HostIdle;
H_read_count <= 'd0;
end
end
else if(CRC_ERR_T) begin
FIS_ERR <= 1;
state <= HT_HostIdle;
Good_status_T <= 0;
prvs_pio <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle;
prvs_pio <= 0;
end
else begin
state <= state;
fis_count <= fis_count;
end
end
HT_PIOOTrans1:
begin
state <= HT_tl_ll_tx_fifo_rst_delay;
dest_state <= HT_HostIdle;
tl_ll_tx_fifo_reset <= 1;
end
HT_PIOOTrans2:
begin
tl_ll_tx_fifo_reset <= 0;
if(LINK_DMA_ABORT) begin
state <= HT_PIOEnd;
tx_fifo_pio_rd_en <= 0;
data_link_out_wr_en <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle;
tx_fifo_pio_rd_en <= 0;
data_link_out_wr_en <= 0;
end
else if(control_register[2] || (command_register == DEVICE_RESET)) begin
state <= HT_HostIdle;
EscapeCF_T <= 1'b1;
tx_fifo_pio_rd_en <= 0;
data_link_out_wr_en <= 0;
end
//else if(link_txr_rdy) begin
// data_link_out_int <= 32'h0046;
// txr_rdy <= 1'b0;
// state <= state;
//data_rdy_T <= 1'b1;
//end
else if(recv_pio_dma_cnt == Transfer_cnt_PIO || recv_pio_dma_cnt == 'd2048 ) begin
state <= HT_PIOEnd;
hold_L <= 1'b0;
//frame_end_T <= 1'b1;
count <= 16'b0;
tx_fifo_pio_rd_en <= 0;
data_link_out_wr_en <= 0;
if((recv_pio_dma_cnt == 'd2048)) begin
recv_pio_dma_cnt <= recv_pio_dma_cnt;
end
else begin
recv_pio_dma_cnt <= 16'b0;
end
end
else if(recv_pio_dma_cnt < Transfer_cnt_PIO && !tl_ll_tx_fifo_full && !tx_fifo_empty) begin
hold_L <= 1'b0 ;
data_link_out_int <= tx_fifo_dout;
if (recv_pio_dma_cnt < (Transfer_cnt_PIO - 'd4)) begin
tx_fifo_pio_rd_en <= 1;
end
else begin
tx_fifo_pio_rd_en <= 0;
end
data_link_out_wr_en <= 1;
recv_pio_dma_cnt <= recv_pio_dma_cnt+'d4 ;
count <= count+'d4 ;
state <= state ;
end
else begin
tx_fifo_pio_rd_en <= 0;
data_link_out_wr_en <= 0;
state <= state ;
recv_pio_dma_cnt <= recv_pio_dma_cnt;
end
end
HT_PIOEnd: begin
rcv_fifo_wr_en <= 0;
if (pio_rcv_flag == 1) begin
if (VALID_CRC_T) begin
state <= HT_HostIdle;
Good_status_T <= 1;
end
else if (CRC_ERR_T || illegal_state) begin
state <= HT_HostIdle;
Good_status_T <= 0;
end
else begin
state <= HT_PIOEnd;
Good_status_T <= 0;
end
end
else begin
if (illegal_state) begin
Good_status_T <= 0;
state <= HT_HostIdle;
end
else if (r_ok || r_error) begin
Good_status_T <= 0;
state <= HT_HostIdle;
end
else begin
Good_status_T <= 0;
state <= HT_PIOEnd;
end
end
end
HT_PIOITrans1: begin
if(data_out_vld_T) begin
state <= HT_PIOITrans2;
recv_pio_dma_cnt <= recv_pio_dma_cnt + 'd4;
rcv_fifo_wr_en <= 1;
end
else if(control_register[2] || (command_register == DEVICE_RESET)) begin
state <= HT_HostIdle;
EscapeCF_T <= 1'b1;
rcv_fifo_wr_en <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle ;
EscapeCF_T <= 1'b0;
rcv_fifo_wr_en <= 0;
end
else begin
EscapeCF_T <= 1'b0;
recv_pio_dma_cnt <= recv_pio_dma_cnt;
state <= HT_PIOITrans2;
rcv_fifo_wr_en <= 0;
end
end
HT_PIOITrans2: begin
if(LINK_DMA_ABORT) begin
pio_rcv_flag <= 1;
state <= HT_PIOEnd;
pio_rcv_flag <= 1'b0;
rcv_fifo_wr_en <= 0;
end
else if(illegal_state) begin
state <= HT_HostIdle;
pio_rcv_flag <= 0;
rcv_fifo_wr_en <= 0;
end
else if(control_register[2] || (command_register == DEVICE_RESET)) begin
state <= HT_HostIdle;
pio_rcv_flag <= 0;
rcv_fifo_wr_en <= 0;
end
else if((recv_pio_dma_cnt == 'd2048) || (recv_pio_dma_cnt > Transfer_cnt_PIO)) begin
rcv_fifo_wr_en <= 0;
state <= HT_PIOEnd;
pio_rcv_flag <= 1;
if((recv_pio_dma_cnt == 'd2048)) begin
recv_pio_dma_cnt <= recv_pio_dma_cnt;
end
else begin
recv_pio_dma_cnt <= 16'b0;
end
end
else if(recv_pio_dma_cnt <= Transfer_cnt_PIO) begin
state <= HT_PIOITrans2;
if (data_out_vld_T) begin
recv_pio_dma_cnt <= recv_pio_dma_cnt + 'd4;
rcv_fifo_wr_en <= 1;
end
else begin
recv_pio_dma_cnt <= recv_pio_dma_cnt;
rcv_fifo_wr_en <= 0;
end
end
else begin
state <= state;
Good_status_T <= 0;
rcv_fifo_wr_en <= 0;
end
end
endcase
end
end // main state machine end
// transmit fifo ...........................
assign tx_fifo_din = DMA_RQST ? DMA_TX_DATA_IN : data_register_in ; // transmit data from dma to tx fifo connected to sata_din
assign tx_fifo_wr_en = DMA_RQST ? (DMA_TX_WEN && CE) : tx_fifo_pio_wr_en;
assign tx_fifo_rd_en = DMA_RQST ? tx_fifo_dma_rd_en : tx_fifo_pio_rd_en;
//assign tx_fifo_pio_wr_en = H_write && (!status_register[7]) && status_register[3];
//receiver fifo...............................
assign DMA_RX_DATA_OUT = DMA_RQST ? rcv_fifo_data_out : 32'h0;
assign RX_FIFO_RDY = !rcv_fifo_prog_full;
assign data_register_out = rcv_fifo_data_out;
assign rx_fifo_pio_rd_en = H_read && detection && (addr_reg == data_reg) && CE; // && (!status_register[7]);
assign rcv_fifo_rd_en = DMA_RQST ? (DMA_RX_REN && CE) : rx_fifo_pio_rd_en;
//assign HOLD_U = direction_bit ? rcv_fifo_almost_empty : tx_fifo_prog_full;
assign WRITE_HOLD_U = tx_fifo_prog_full;
assign READ_HOLD_U = rcv_fifo_almost_empty;
always @(posedge clk)
begin
rcv_fifo_din <= data_link_in;
end
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
.O (rx_fifo_rd_clk ), // Clock MUX output
.I0(PIO_CLK_IN), // Clock0 input
.I1(DMA_CLK_IN), // Clock1 input
.S (DMA_RQST) // Clock select input
);
assign tx_fifo1_reset = reset || TX_FIFO_RESET;
//PIO and DMA Transmit FIO
fifo_generator_v8_3 TX_FIFO1 (
.rst (tx_fifo1_reset), // input rst
.wr_clk (rx_fifo_rd_clk), // input wr_clk
.rd_clk (clk), // input rd_clk
.din (tx_fifo_din), // input [31 : 0] din
.wr_en (tx_fifo_wr_en), // input wr_en
.rd_en (tx_fifo_rd_en), // input rd_en
.dout (tx_fifo_dout), // output [31 : 0] dout
.full (), // output full
.empty (tx_fifo_empty), // output empty
.almost_empty (tx_fifo_almost_empty),
.prog_full (tx_fifo_prog_full) // output prog_full
);
assign rx_fifo1_reset = reset || RX_FIFO_RESET;
//PIO and DMA Receive FIFO
RX_FIFO RX_FIFO1 (
.rst (rx_fifo1_reset), // input rst
.wr_clk (clk), // input wr_clk
.rd_clk (rx_fifo_rd_clk), // input rd_clk
.din (rcv_fifo_din), // input [31 : 0] din
.wr_en (rcv_fifo_wr_en), // input wr_en
.rd_en (rcv_fifo_rd_en), // input rd_en
.dout (rcv_fifo_data_out), // output [31 : 0] dout
.full (rcv_fifo_full), // output full
.empty (), // output empty
.almost_empty (rcv_fifo_almost_empty),
.prog_full (rcv_fifo_prog_full) // output prog_full
);
//General Transmit FIFO
TX_FIFO TL_LL_TX_FIFO (
.clk (clk), // input clk
.rst (tl_ll_tx_fifo_reset), // input rst
.din (data_link_out_int), // input [31 : 0] din
.wr_en (data_link_out_wr_en), // input wr_en
.rd_en (data_link_rd_en_t), // input rd_en
.dout (data_link_out), // output [31 : 0] dout
.full (tl_ll_tx_fifo_full), // output full
.empty (tl_ll_tx_fifo_empty), // output empty
.almost_full (), // output prog_full
.almost_empty (tl_ll_tx_fifo_almost_empty) // output prog_empty
);
assign FRAME_END_T = tl_ll_tx_fifo_empty;
assign DATA_RDY_T = !tl_ll_tx_fifo_almost_empty;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_TB_V
`define SKY130_FD_SC_HS__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B_N = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B_N = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B_N = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B_N = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_TB_V
|
module jump_addr(
input [25:0] inst,
input [3:0] pc_4,
output[31:0] j_addr);
buf (j_addr[0 ] ,inst[0 ]);
buf (j_addr[1 ] ,inst[1 ]);
buf (j_addr[2 ] ,inst[2 ]);
buf (j_addr[3 ] ,inst[3 ]);
buf (j_addr[4 ] ,inst[4 ]);
buf (j_addr[5 ] ,inst[5 ]);
buf (j_addr[6 ] ,inst[6 ]);
buf (j_addr[7 ] ,inst[7 ]);
buf (j_addr[8 ] ,inst[8 ]);
buf (j_addr[9 ] ,inst[9 ]);
buf (j_addr[10] ,inst[10]);
buf (j_addr[11] ,inst[11]);
buf (j_addr[12] ,inst[12]);
buf (j_addr[13] ,inst[13]);
buf (j_addr[14] ,inst[14]);
buf (j_addr[15] ,inst[15]);
buf (j_addr[16] ,inst[16]);
buf (j_addr[17] ,inst[17]);
buf (j_addr[18] ,inst[18]);
buf (j_addr[19] ,inst[19]);
buf (j_addr[20] ,inst[20]);
buf (j_addr[21] ,inst[21]);
buf (j_addr[22] ,inst[22]);
buf (j_addr[23] ,inst[23]);
buf (j_addr[24] ,inst[24]);
buf (j_addr[25] ,inst[25]);
buf (j_addr[26] ,1'b0 );
buf (j_addr[27] ,1'b0 );
buf (j_addr[28] ,pc_4[0 ]);
buf (j_addr[29] ,pc_4[1 ]);
buf (j_addr[30] ,pc_4[2 ]);
buf (j_addr[31] ,pc_4[3 ]);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
`timescale 1ns/100ps
module axi_hdmi_tx_vdma (
// hdmi interface
input hdmi_fs_toggle,
input [ 8:0] hdmi_raddr_g,
// vdma interface
input vdma_clk,
input vdma_rst,
input vdma_end_of_frame,
input vdma_valid,
input [63:0] vdma_data,
output reg vdma_ready,
output reg vdma_wr,
output reg [ 8:0] vdma_waddr,
output reg [47:0] vdma_wdata,
output reg vdma_fs_ret_toggle,
output reg [ 8:0] vdma_fs_waddr,
output reg vdma_tpm_oos,
output reg vdma_ovf,
output reg vdma_unf);
localparam BUF_THRESHOLD_LO = 9'd3;
localparam BUF_THRESHOLD_HI = 9'd509;
localparam RDY_THRESHOLD_LO = 9'd450;
localparam RDY_THRESHOLD_HI = 9'd500;
// internal registers
reg vdma_fs_toggle_m1 = 1'd0;
reg vdma_fs_toggle_m2 = 1'd0;
reg vdma_fs_toggle_m3 = 1'd0;
reg [22:0] vdma_tpm_data = 23'd0;
reg [ 8:0] vdma_raddr_g_m1 = 9'd0;
reg [ 8:0] vdma_raddr_g_m2 = 9'd0;
reg [ 8:0] vdma_raddr = 9'd0;
reg [ 8:0] vdma_addr_diff = 9'd0;
reg vdma_almost_full = 1'd0;
reg vdma_almost_empty = 1'd0;
reg hdmi_fs = 1'd0;
reg vdma_fs = 1'd0;
reg vdma_end_of_frame_d = 1'd0;
reg vdma_active_frame = 1'd0;
// internal wires
wire [47:0] vdma_tpm_data_s;
wire vdma_tpm_oos_s;
wire [ 9:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// grey to binary conversion
function [8:0] g2b;
input [8:0] g;
reg [8:0] b;
begin
b[8] = g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// hdmi frame sync
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_fs_toggle_m1 <= 1'd0;
vdma_fs_toggle_m2 <= 1'd0;
vdma_fs_toggle_m3 <= 1'd0;
end else begin
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
end
hdmi_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
end
// dma frame sync
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_end_of_frame_d <= 1'b0;
vdma_fs <= 1'b0;
end else begin
vdma_end_of_frame_d <= vdma_end_of_frame;
vdma_fs <= vdma_end_of_frame_d;
end
end
// sync dma and hdmi frames
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_fs_ret_toggle = 1'b0;
vdma_fs_waddr <= 9'b0;
end else begin
if (vdma_fs) begin
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
vdma_fs_waddr <= vdma_waddr ;
end
end
end
// accept new frame from dma
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_active_frame <= 1'b0;
end else begin
if ((vdma_active_frame == 1'b1) && (vdma_end_of_frame == 1'b1)) begin
vdma_active_frame <= 1'b0;
end else if ((vdma_active_frame == 1'b0) && (hdmi_fs == 1'b1)) begin
vdma_active_frame <= 1'b1;
end
end
end
// vdma write
always @(posedge vdma_clk) begin
vdma_wr <= vdma_valid & vdma_ready;
if (vdma_rst == 1'b1) begin
vdma_waddr <= 9'd0;
end else if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
end
// test error conditions
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
always @(posedge vdma_clk) begin
if ((vdma_rst == 1'b1) || (vdma_fs == 1'b1)) begin
vdma_tpm_data <= 23'd0;
vdma_tpm_oos <= 1'd0;
end else if (vdma_wr == 1'b1) begin
vdma_tpm_data <= vdma_tpm_data + 1'b1;
vdma_tpm_oos <= vdma_tpm_oos_s;
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_raddr_g_m1 <= 9'd0;
vdma_raddr_g_m2 <= 9'd0;
end else begin
vdma_raddr_g_m1 <= hdmi_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
end
end
always @(posedge vdma_clk) begin
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[8:0];
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
vdma_ready <= vdma_active_frame;
end
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
vdma_almost_full <= 1'b1;
end else begin
vdma_almost_full <= 1'b0;
end
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
vdma_almost_empty <= 1'b1;
end else begin
vdma_almost_empty <= 1'b0;
end
vdma_ovf <= vdma_ovf_s;
vdma_unf <= vdma_unf_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Beck Pang
// University of Washington, Seattle
// Apr. 6th, 2015
// EE 471, Lab 1
`include "DFlipFlop.v"
`include "JohnsonCounter.v"
// test bench running on gtkwave
module JohnsonCounter_testBench ();
// connext the two modules
wire clk, rst_n;
wire [3:0] out;
// declare an instance of the AND module
JohnsonCounter myCounter (clk, rst_n, out);
// Running the GUI part of simulation
JohnsonCounter_Tester aTester (clk, rst_n, out);
// file for gtkwave
initial
begin
$dumpfile("JohnsonCounter.vcd");
$dumpvars(1, myCounter);
end
endmodule
module JohnsonCounter_Tester (
output reg clk, rst_n,
input [3:0] out
);
parameter stimDelay = 20;
// generate a clock
always #(stimDelay/2) clk = ~clk;
initial // Response
begin
$display("\t\t clk rst_n \t out \t Time ");
$monitor("\t %b ", out, $time);
clk = 'b0;
end
always @(posedge clk) // Stimulus
begin
rst_n = 'b0;
#stimDelay rst_n = 'b1;
#(32*stimDelay) rst_n = 'b0;
#stimDelay clk = 'b1;
#(32*stimDelay) clk = 'b0;
#stimDelay clk = 'b1;
#(2*stimDelay);
$stop;
$finish;
end
endmodule |
module commit (
junk_p_3,
mio_data_wmask_p_3,
mio_data_rw_p_3,
mio_data_req_p_3,
mio_data_wdata_p_3,
mio_data_addr_p_3,
mio_instr_wmask_p_3,
mio_instr_rw_p_3,
mio_instr_req_p_3,
mio_instr_wdata_p_3,
mio_instr_addr_p_3,
branch_p_3,
f7_p_3,
f3_p_3,
rdco_p_3,
rdc_p_3,
sys_p_3,
fen_p_3,
opr_p_3,
opi_p_3,
st_p_3,
ld_p_3,
bra_p_3,
auipc_p_3,
lui_p_3,
trap_p_3,
insn_p_3,
instr_p_3,
imm_p_3,
rdm_p_3,
pc_p_3,
rdd_p_3,
jalr_p_3,
jal_p_3,
rd2_p_3,
rd1_p_3,
rad_zero_p_3,
ra2_zero_p_3,
ra1_zero_p_3,
rad_p_3,
ra2_p_3,
ra1_p_3,
clr,
clk,
pen_p_3,
pen,
ra1,
ra2,
rad,
ra1_zero,
ra2_zero,
rad_zero,
rd1,
rd2,
rdd,
rdm,
imm,
pc,
instr,
insn,
trap,
lui,
auipc,
jal,
jalr,
bra,
ld,
st,
opi,
opr,
fen,
sys,
rdc,
rdco,
f3,
f7,
branch,
rwe,
mio_instr_addr,
mio_instr_wdata,
mio_instr_req,
mio_instr_rw,
mio_instr_wmask,
mio_data_addr,
mio_data_wdata,
mio_data_req,
mio_data_rw,
mio_data_wmask,
junk
);
input junk_p_3;
input [3:0] mio_data_wmask_p_3;
input mio_data_rw_p_3;
input mio_data_req_p_3;
input [31:0] mio_data_wdata_p_3;
input [31:0] mio_data_addr_p_3;
input [3:0] mio_instr_wmask_p_3;
input mio_instr_rw_p_3;
input mio_instr_req_p_3;
input [31:0] mio_instr_wdata_p_3;
input [31:0] mio_instr_addr_p_3;
input branch_p_3;
input f7_p_3;
input [2:0] f3_p_3;
input [2:0] rdco_p_3;
input rdc_p_3;
input sys_p_3;
input fen_p_3;
input opr_p_3;
input opi_p_3;
input st_p_3;
input ld_p_3;
input bra_p_3;
input auipc_p_3;
input lui_p_3;
input trap_p_3;
input [47:0] insn_p_3;
input [31:0] instr_p_3;
input [31:0] imm_p_3;
input [31:0] rdm_p_3;
input [31:0] pc_p_3;
input [31:0] rdd_p_3;
input jalr_p_3;
input jal_p_3;
input [31:0] rd2_p_3;
input [31:0] rd1_p_3;
input rad_zero_p_3;
input ra2_zero_p_3;
input ra1_zero_p_3;
input [4:0] rad_p_3;
input [4:0] ra2_p_3;
input [4:0] ra1_p_3;
input clr;
input clk;
input pen_p_3;
output pen;
output [4:0] ra1;
output [4:0] ra2;
output [4:0] rad;
output ra1_zero;
output ra2_zero;
output rad_zero;
output [31:0] rd1;
output [31:0] rd2;
output [31:0] rdd;
output [31:0] rdm;
output [31:0] imm;
output [31:0] pc;
output [31:0] instr;
output [47:0] insn;
output trap;
output lui;
output auipc;
output jal;
output jalr;
output bra;
output ld;
output st;
output opi;
output opr;
output fen;
output sys;
output rdc;
output [2:0] rdco;
output [2:0] f3;
output f7;
output branch;
output rwe;
output [31:0] mio_instr_addr;
output [31:0] mio_instr_wdata;
output mio_instr_req;
output mio_instr_rw;
output [3:0] mio_instr_wmask;
output [31:0] mio_data_addr;
output [31:0] mio_data_wdata;
output mio_data_req;
output mio_data_rw;
output [3:0] mio_data_wmask;
output junk;
/* signal declarations */
wire _10835 = 1'b0;
wire _10836 = 1'b0;
wire _9420 = 1'b0;
wire _9421 = 1'b0;
reg _9422;
reg _10837;
wire [3:0] _10831 = 4'b0000;
wire [3:0] _10832 = 4'b0000;
wire [3:0] _9424 = 4'b0000;
wire [3:0] _9425 = 4'b0000;
reg [3:0] _9426;
reg [3:0] _10833;
wire _10827 = 1'b0;
wire _10828 = 1'b0;
wire _9428 = 1'b0;
wire _9429 = 1'b0;
reg _9430;
reg _10829;
wire _10823 = 1'b0;
wire _10824 = 1'b0;
wire _9432 = 1'b0;
wire _9433 = 1'b0;
reg _9434;
reg _10825;
wire [31:0] _10819 = 32'b00000000000000000000000000000000;
wire [31:0] _10820 = 32'b00000000000000000000000000000000;
wire [31:0] _9436 = 32'b00000000000000000000000000000000;
wire [31:0] _9437 = 32'b00000000000000000000000000000000;
reg [31:0] _9438;
reg [31:0] _10821;
wire [31:0] _10815 = 32'b00000000000000000000000000000000;
wire [31:0] _10816 = 32'b00000000000000000000000000000000;
wire [31:0] _9440 = 32'b00000000000000000000000000000000;
wire [31:0] _9441 = 32'b00000000000000000000000000000000;
reg [31:0] _9442;
reg [31:0] _10817;
wire [3:0] _10811 = 4'b0000;
wire [3:0] _10812 = 4'b0000;
wire [3:0] _9444 = 4'b0000;
wire [3:0] _9445 = 4'b0000;
reg [3:0] _9446;
reg [3:0] _10813;
wire _10807 = 1'b0;
wire _10808 = 1'b0;
wire _9448 = 1'b0;
wire _9449 = 1'b0;
reg _9450;
reg _10809;
wire _10803 = 1'b0;
wire _10804 = 1'b0;
wire _9452 = 1'b0;
wire _9453 = 1'b0;
reg _9454;
reg _10805;
wire [31:0] _10799 = 32'b00000000000000000000000000000000;
wire [31:0] _10800 = 32'b00000000000000000000000000000000;
wire [31:0] _9456 = 32'b00000000000000000000000000000000;
wire [31:0] _9457 = 32'b00000000000000000000000000000000;
reg [31:0] _9458;
reg [31:0] _10801;
wire [31:0] _10795 = 32'b00000000000000000000000000000000;
wire [31:0] _10796 = 32'b00000000000000000000000000000000;
wire [31:0] _9460 = 32'b00000000000000000000000000000000;
wire [31:0] _9461 = 32'b00000000000000000000000000000000;
reg [31:0] _9462;
reg [31:0] _10797;
wire _10791 = 1'b0;
wire _10792 = 1'b0;
wire _10658;
wire _10659;
wire _10660;
wire _10661;
wire _10662;
reg _10793;
wire _10787 = 1'b0;
wire _10788 = 1'b0;
wire _9468 = 1'b0;
wire _9469 = 1'b0;
reg _9470;
wire _10651;
wire _10652;
wire _10653;
reg _10789;
wire _10783 = 1'b0;
wire _10784 = 1'b0;
wire _9472 = 1'b0;
wire _9473 = 1'b0;
reg _9474;
reg _10785;
wire [2:0] _10779 = 3'b000;
wire [2:0] _10780 = 3'b000;
wire [2:0] _9476 = 3'b000;
wire [2:0] _9477 = 3'b000;
reg [2:0] _9478;
reg [2:0] _10781;
wire [2:0] _10775 = 3'b000;
wire [2:0] _10776 = 3'b000;
wire [2:0] _9480 = 3'b000;
wire [2:0] _9481 = 3'b000;
reg [2:0] _9482;
reg [2:0] _10777;
wire _10771 = 1'b0;
wire _10772 = 1'b0;
wire _9484 = 1'b0;
wire _9485 = 1'b0;
reg _9486;
reg _10773;
wire _10767 = 1'b0;
wire _10768 = 1'b0;
wire _9488 = 1'b0;
wire _9489 = 1'b0;
reg _9490;
reg _10769;
wire _10763 = 1'b0;
wire _10764 = 1'b0;
wire _9492 = 1'b0;
wire _9493 = 1'b0;
reg _9494;
reg _10765;
wire _10759 = 1'b0;
wire _10760 = 1'b0;
wire _9496 = 1'b0;
wire _9497 = 1'b0;
reg _9498;
reg _10761;
wire _10755 = 1'b0;
wire _10756 = 1'b0;
wire _9500 = 1'b0;
wire _9501 = 1'b0;
reg _9502;
reg _10757;
wire _10751 = 1'b0;
wire _10752 = 1'b0;
wire _9504 = 1'b0;
wire _9505 = 1'b0;
reg _9506;
reg _10753;
wire _10747 = 1'b0;
wire _10748 = 1'b0;
wire _9508 = 1'b0;
wire _9509 = 1'b0;
reg _9510;
reg _10749;
wire _10743 = 1'b0;
wire _10744 = 1'b0;
wire _9512 = 1'b0;
wire _9513 = 1'b0;
reg _9514;
reg _10745;
wire _10739 = 1'b0;
wire _10740 = 1'b0;
reg _10741;
wire _10735 = 1'b0;
wire _10736 = 1'b0;
reg _10737;
wire _10731 = 1'b0;
wire _10732 = 1'b0;
wire _9524 = 1'b0;
wire _9525 = 1'b0;
reg _9526;
reg _10733;
wire _10727 = 1'b0;
wire _10728 = 1'b0;
wire _9528 = 1'b0;
wire _9529 = 1'b0;
reg _9530;
reg _10729;
wire _10723 = 1'b0;
wire _10724 = 1'b0;
wire _9532 = 1'b0;
wire _9533 = 1'b0;
reg _9534;
reg _10725;
wire [47:0] _10719 = 48'b000000000000000000000000000000000000000000000000;
wire [47:0] _10720 = 48'b000000000000000000000000000000000000000000000000;
wire [47:0] _9536 = 48'b000000000000000000000000000000000000000000000000;
wire [47:0] _9537 = 48'b000000000000000000000000000000000000000000000000;
reg [47:0] _9538;
reg [47:0] _10721;
wire [31:0] _10715 = 32'b00000000000000000000000000000000;
wire [31:0] _10716 = 32'b00000000000000000000000000000000;
wire [31:0] _9540 = 32'b00000000000000000000000000000000;
wire [31:0] _9541 = 32'b00000000000000000000000000000000;
reg [31:0] _9542;
reg [31:0] _10717;
wire [31:0] _10711 = 32'b00000000000000000000000000000000;
wire [31:0] _10712 = 32'b00000000000000000000000000000000;
reg [31:0] _10713;
wire [31:0] _10707 = 32'b00000000000000000000000000000000;
wire [31:0] _10708 = 32'b00000000000000000000000000000000;
wire [31:0] _9548 = 32'b00000000000000000000000000000000;
wire [31:0] _9549 = 32'b00000000000000000000000000000000;
reg [31:0] _9550;
reg [31:0] _10709;
wire [31:0] _10703 = 32'b00000000000000000000000000000000;
wire [31:0] _10704 = 32'b00000000000000000000000000000000;
wire [31:0] _9552 = 32'b00000000000000000000000000000000;
wire [31:0] _9553 = 32'b00000000000000000000000000000000;
reg [31:0] _9554;
reg [31:0] _10705;
wire [31:0] _10699 = 32'b00000000000000000000000000000000;
wire [31:0] _10700 = 32'b00000000000000000000000000000000;
wire [31:0] _10654 = 32'b00000000000000000000000000000100;
wire [31:0] _9544 = 32'b00000000000000000000000000000000;
wire [31:0] _9545 = 32'b00000000000000000000000000000000;
reg [31:0] _9546;
wire [31:0] _10655;
wire [31:0] _9556 = 32'b00000000000000000000000000000000;
wire [31:0] _9557 = 32'b00000000000000000000000000000000;
reg [31:0] _9558;
wire _9516 = 1'b0;
wire _9517 = 1'b0;
reg _9518;
wire _9520 = 1'b0;
wire _9521 = 1'b0;
reg _9522;
wire _10656;
wire [31:0] _10657;
reg [31:0] _10701;
wire [31:0] _10695 = 32'b00000000000000000000000000000000;
wire [31:0] _10696 = 32'b00000000000000000000000000000000;
wire [31:0] _9560 = 32'b00000000000000000000000000000000;
wire [31:0] _9561 = 32'b00000000000000000000000000000000;
reg [31:0] _9562;
reg [31:0] _10697;
wire [31:0] _10691 = 32'b00000000000000000000000000000000;
wire [31:0] _10692 = 32'b00000000000000000000000000000000;
wire [31:0] _9564 = 32'b00000000000000000000000000000000;
wire [31:0] _9565 = 32'b00000000000000000000000000000000;
reg [31:0] _9566;
reg [31:0] _10693;
wire _10687 = 1'b0;
wire _10688 = 1'b0;
wire _9568 = 1'b0;
wire _9569 = 1'b0;
reg _9570;
reg _10689;
wire _10683 = 1'b0;
wire _10684 = 1'b0;
wire _9572 = 1'b0;
wire _9573 = 1'b0;
reg _9574;
reg _10685;
wire _10679 = 1'b0;
wire _10680 = 1'b0;
wire _9576 = 1'b0;
wire _9577 = 1'b0;
reg _9578;
reg _10681;
wire [4:0] _10675 = 5'b00000;
wire [4:0] _10676 = 5'b00000;
wire [4:0] _9580 = 5'b00000;
wire [4:0] _9581 = 5'b00000;
reg [4:0] _9582;
reg [4:0] _10677;
wire [4:0] _10671 = 5'b00000;
wire [4:0] _10672 = 5'b00000;
wire [4:0] _9584 = 5'b00000;
wire [4:0] _9585 = 5'b00000;
reg [4:0] _9586;
reg [4:0] _10673;
wire [4:0] _10667 = 5'b00000;
wire [4:0] _10668 = 5'b00000;
wire [4:0] _9588 = 5'b00000;
wire [4:0] _9589 = 5'b00000;
reg [4:0] _9590;
reg [4:0] _10669;
wire _10663 = 1'b0;
wire _10664 = 1'b0;
wire _9592 = 1'b0;
wire vdd = 1'b1;
wire _9593 = 1'b0;
reg _9594;
reg _10665;
/* logic */
always @(posedge clk) begin
if (clr)
_9422 <= _9420;
else
_9422 <= junk_p_3;
end
always @(posedge clk) begin
if (clr)
_10837 <= _10835;
else
_10837 <= _9422;
end
always @(posedge clk) begin
if (clr)
_9426 <= _9424;
else
_9426 <= mio_data_wmask_p_3;
end
always @(posedge clk) begin
if (clr)
_10833 <= _10831;
else
_10833 <= _9426;
end
always @(posedge clk) begin
if (clr)
_9430 <= _9428;
else
_9430 <= mio_data_rw_p_3;
end
always @(posedge clk) begin
if (clr)
_10829 <= _10827;
else
_10829 <= _9430;
end
always @(posedge clk) begin
if (clr)
_9434 <= _9432;
else
_9434 <= mio_data_req_p_3;
end
always @(posedge clk) begin
if (clr)
_10825 <= _10823;
else
_10825 <= _9434;
end
always @(posedge clk) begin
if (clr)
_9438 <= _9436;
else
_9438 <= mio_data_wdata_p_3;
end
always @(posedge clk) begin
if (clr)
_10821 <= _10819;
else
_10821 <= _9438;
end
always @(posedge clk) begin
if (clr)
_9442 <= _9440;
else
_9442 <= mio_data_addr_p_3;
end
always @(posedge clk) begin
if (clr)
_10817 <= _10815;
else
_10817 <= _9442;
end
always @(posedge clk) begin
if (clr)
_9446 <= _9444;
else
_9446 <= mio_instr_wmask_p_3;
end
always @(posedge clk) begin
if (clr)
_10813 <= _10811;
else
_10813 <= _9446;
end
always @(posedge clk) begin
if (clr)
_9450 <= _9448;
else
_9450 <= mio_instr_rw_p_3;
end
always @(posedge clk) begin
if (clr)
_10809 <= _10807;
else
_10809 <= _9450;
end
always @(posedge clk) begin
if (clr)
_9454 <= _9452;
else
_9454 <= mio_instr_req_p_3;
end
always @(posedge clk) begin
if (clr)
_10805 <= _10803;
else
_10805 <= _9454;
end
always @(posedge clk) begin
if (clr)
_9458 <= _9456;
else
_9458 <= mio_instr_wdata_p_3;
end
always @(posedge clk) begin
if (clr)
_10801 <= _10799;
else
_10801 <= _9458;
end
always @(posedge clk) begin
if (clr)
_9462 <= _9460;
else
_9462 <= mio_instr_addr_p_3;
end
always @(posedge clk) begin
if (clr)
_10797 <= _10795;
else
_10797 <= _9462;
end
assign _10658 = _9534 | _9514;
assign _10659 = _10658 | _9506;
assign _10660 = _10659 | _9494;
assign _10661 = _10660 | _9486;
assign _10662 = ~ _10661;
always @(posedge clk) begin
if (clr)
_10793 <= _10791;
else
_10793 <= _10662;
end
always @(posedge clk) begin
if (clr)
_9470 <= _9468;
else
_9470 <= branch_p_3;
end
assign _10651 = _9514 & _9470;
assign _10652 = _9522 | _9518;
assign _10653 = _10652 | _10651;
always @(posedge clk) begin
if (clr)
_10789 <= _10787;
else
_10789 <= _10653;
end
always @(posedge clk) begin
if (clr)
_9474 <= _9472;
else
_9474 <= f7_p_3;
end
always @(posedge clk) begin
if (clr)
_10785 <= _10783;
else
_10785 <= _9474;
end
always @(posedge clk) begin
if (clr)
_9478 <= _9476;
else
_9478 <= f3_p_3;
end
always @(posedge clk) begin
if (clr)
_10781 <= _10779;
else
_10781 <= _9478;
end
always @(posedge clk) begin
if (clr)
_9482 <= _9480;
else
_9482 <= rdco_p_3;
end
always @(posedge clk) begin
if (clr)
_10777 <= _10775;
else
_10777 <= _9482;
end
always @(posedge clk) begin
if (clr)
_9486 <= _9484;
else
_9486 <= rdc_p_3;
end
always @(posedge clk) begin
if (clr)
_10773 <= _10771;
else
_10773 <= _9486;
end
always @(posedge clk) begin
if (clr)
_9490 <= _9488;
else
_9490 <= sys_p_3;
end
always @(posedge clk) begin
if (clr)
_10769 <= _10767;
else
_10769 <= _9490;
end
always @(posedge clk) begin
if (clr)
_9494 <= _9492;
else
_9494 <= fen_p_3;
end
always @(posedge clk) begin
if (clr)
_10765 <= _10763;
else
_10765 <= _9494;
end
always @(posedge clk) begin
if (clr)
_9498 <= _9496;
else
_9498 <= opr_p_3;
end
always @(posedge clk) begin
if (clr)
_10761 <= _10759;
else
_10761 <= _9498;
end
always @(posedge clk) begin
if (clr)
_9502 <= _9500;
else
_9502 <= opi_p_3;
end
always @(posedge clk) begin
if (clr)
_10757 <= _10755;
else
_10757 <= _9502;
end
always @(posedge clk) begin
if (clr)
_9506 <= _9504;
else
_9506 <= st_p_3;
end
always @(posedge clk) begin
if (clr)
_10753 <= _10751;
else
_10753 <= _9506;
end
always @(posedge clk) begin
if (clr)
_9510 <= _9508;
else
_9510 <= ld_p_3;
end
always @(posedge clk) begin
if (clr)
_10749 <= _10747;
else
_10749 <= _9510;
end
always @(posedge clk) begin
if (clr)
_9514 <= _9512;
else
_9514 <= bra_p_3;
end
always @(posedge clk) begin
if (clr)
_10745 <= _10743;
else
_10745 <= _9514;
end
always @(posedge clk) begin
if (clr)
_10741 <= _10739;
else
_10741 <= _9518;
end
always @(posedge clk) begin
if (clr)
_10737 <= _10735;
else
_10737 <= _9522;
end
always @(posedge clk) begin
if (clr)
_9526 <= _9524;
else
_9526 <= auipc_p_3;
end
always @(posedge clk) begin
if (clr)
_10733 <= _10731;
else
_10733 <= _9526;
end
always @(posedge clk) begin
if (clr)
_9530 <= _9528;
else
_9530 <= lui_p_3;
end
always @(posedge clk) begin
if (clr)
_10729 <= _10727;
else
_10729 <= _9530;
end
always @(posedge clk) begin
if (clr)
_9534 <= _9532;
else
_9534 <= trap_p_3;
end
always @(posedge clk) begin
if (clr)
_10725 <= _10723;
else
_10725 <= _9534;
end
always @(posedge clk) begin
if (clr)
_9538 <= _9536;
else
_9538 <= insn_p_3;
end
always @(posedge clk) begin
if (clr)
_10721 <= _10719;
else
_10721 <= _9538;
end
always @(posedge clk) begin
if (clr)
_9542 <= _9540;
else
_9542 <= instr_p_3;
end
always @(posedge clk) begin
if (clr)
_10717 <= _10715;
else
_10717 <= _9542;
end
always @(posedge clk) begin
if (clr)
_10713 <= _10711;
else
_10713 <= _9558;
end
always @(posedge clk) begin
if (clr)
_9550 <= _9548;
else
_9550 <= imm_p_3;
end
always @(posedge clk) begin
if (clr)
_10709 <= _10707;
else
_10709 <= _9550;
end
always @(posedge clk) begin
if (clr)
_9554 <= _9552;
else
_9554 <= rdm_p_3;
end
always @(posedge clk) begin
if (clr)
_10705 <= _10703;
else
_10705 <= _9554;
end
always @(posedge clk) begin
if (clr)
_9546 <= _9544;
else
_9546 <= pc_p_3;
end
assign _10655 = _9546 + _10654;
always @(posedge clk) begin
if (clr)
_9558 <= _9556;
else
_9558 <= rdd_p_3;
end
always @(posedge clk) begin
if (clr)
_9518 <= _9516;
else
_9518 <= jalr_p_3;
end
always @(posedge clk) begin
if (clr)
_9522 <= _9520;
else
_9522 <= jal_p_3;
end
assign _10656 = _9522 | _9518;
assign _10657 = _10656 ? _10655 : _9558;
always @(posedge clk) begin
if (clr)
_10701 <= _10699;
else
_10701 <= _10657;
end
always @(posedge clk) begin
if (clr)
_9562 <= _9560;
else
_9562 <= rd2_p_3;
end
always @(posedge clk) begin
if (clr)
_10697 <= _10695;
else
_10697 <= _9562;
end
always @(posedge clk) begin
if (clr)
_9566 <= _9564;
else
_9566 <= rd1_p_3;
end
always @(posedge clk) begin
if (clr)
_10693 <= _10691;
else
_10693 <= _9566;
end
always @(posedge clk) begin
if (clr)
_9570 <= _9568;
else
_9570 <= rad_zero_p_3;
end
always @(posedge clk) begin
if (clr)
_10689 <= _10687;
else
_10689 <= _9570;
end
always @(posedge clk) begin
if (clr)
_9574 <= _9572;
else
_9574 <= ra2_zero_p_3;
end
always @(posedge clk) begin
if (clr)
_10685 <= _10683;
else
_10685 <= _9574;
end
always @(posedge clk) begin
if (clr)
_9578 <= _9576;
else
_9578 <= ra1_zero_p_3;
end
always @(posedge clk) begin
if (clr)
_10681 <= _10679;
else
_10681 <= _9578;
end
always @(posedge clk) begin
if (clr)
_9582 <= _9580;
else
_9582 <= rad_p_3;
end
always @(posedge clk) begin
if (clr)
_10677 <= _10675;
else
_10677 <= _9582;
end
always @(posedge clk) begin
if (clr)
_9586 <= _9584;
else
_9586 <= ra2_p_3;
end
always @(posedge clk) begin
if (clr)
_10673 <= _10671;
else
_10673 <= _9586;
end
always @(posedge clk) begin
if (clr)
_9590 <= _9588;
else
_9590 <= ra1_p_3;
end
always @(posedge clk) begin
if (clr)
_10669 <= _10667;
else
_10669 <= _9590;
end
always @(posedge clk) begin
if (clr)
_9594 <= _9592;
else
_9594 <= pen_p_3;
end
always @(posedge clk) begin
if (clr)
_10665 <= _10663;
else
_10665 <= _9594;
end
/* aliases */
/* output assignments */
assign pen = _10665;
assign ra1 = _10669;
assign ra2 = _10673;
assign rad = _10677;
assign ra1_zero = _10681;
assign ra2_zero = _10685;
assign rad_zero = _10689;
assign rd1 = _10693;
assign rd2 = _10697;
assign rdd = _10701;
assign rdm = _10705;
assign imm = _10709;
assign pc = _10713;
assign instr = _10717;
assign insn = _10721;
assign trap = _10725;
assign lui = _10729;
assign auipc = _10733;
assign jal = _10737;
assign jalr = _10741;
assign bra = _10745;
assign ld = _10749;
assign st = _10753;
assign opi = _10757;
assign opr = _10761;
assign fen = _10765;
assign sys = _10769;
assign rdc = _10773;
assign rdco = _10777;
assign f3 = _10781;
assign f7 = _10785;
assign branch = _10789;
assign rwe = _10793;
assign mio_instr_addr = _10797;
assign mio_instr_wdata = _10801;
assign mio_instr_req = _10805;
assign mio_instr_rw = _10809;
assign mio_instr_wmask = _10813;
assign mio_data_addr = _10817;
assign mio_data_wdata = _10821;
assign mio_data_req = _10825;
assign mio_data_rw = _10829;
assign mio_data_wmask = _10833;
assign junk = _10837;
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011-2012, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
//
// Ken Chapman - Xilinx Ltd.
//
// 30th April 2012 - Conversion from original VHDL version (30th April 2012).
// 30th July 2014 - Corrections to comment only.
//
// This reference design provides a simple UART communication example.
// Please see 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' for more detailed
// descriptions.
//
// The code in this example is set to implement a 115200 baud rate when using a 50MHz
// clock. Whilst the design is presented as a working example for the XC6VLX240T-1FF1156
// device on the ML605 Evaluation Board (www.xilinx.com) it is a simple reference design
// that is easily adapted or incorporated into a design for use with any hardware platform.
//
//
//////////////////////////////////////////////////////////////////////////////////////////-
//
//
module uart6_ml605 ( input uart_rx,
input clk200_p,
input clk200_n,
output uart_tx );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to create 50MHz clock from 200MHz differential clock
//
wire clk200;
wire clk;
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [4:0] baud_count;
reg en_16_x_baud;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Create 50MHz clock from 200MHz differential clock
/////////////////////////////////////////////////////////////////////////////////////////
IBUFGDS diff_clk_buffer(
.I(clk200_p),
.IB(clk200_n),
.O(clk200));
// BUFR used to divide by 4 and create a regional clock
BUFR #(
.BUFR_DIVIDE("4"),
.SIM_DEVICE("VIRTEX6"))
clock_divide (
.I(clk200),
.O(clk),
.CE(1'b1),
.CLR(1'b0));
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter.
//
kcpsm6 #(
.interrupt_vector (12'h7F0),
.scratch_pad_memory_size(64),
.hwbuild (8'h42)) // 42 hex is ASCII Character "B"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset connected to JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl;
// Unused signals tied off until required.
assign kcpsm6_sleep = 1'b0;
assign interrupt = interrupt_ack;
// Development Program Memory
// JTAG Loader enabled for rapid code development.
uart_control #(
.C_FAMILY ("V6"),
.C_RAM_SIZE_KWORDS (2),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 27.13 cycles at 50MHz. In this implementation
// a pulse is generated every 27 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 5'b11010) begin // counts 27 states including zero
baud_count <= 5'b00000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 5'b00001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the transmitter and receiver. The second is used to read the data from the
// receiver and generate the 'buffer_read' pulse.
//
always @ (posedge clk)
begin
case (port_id[0])
// Read UART status at port address 00 hex
1'b0 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
1'b1 : in_port <= uart_rx_data_out;
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[0] == 1'b1)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there is only one output port and that it involves writing
// directly to the FIFO buffer within 'uart_tx6'. As such the only requirements are to
// connect the 'out_port' to the transmitter macro and generate the write pulse.
//
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
// END OF FILE uart6_ml605.v
///////////////////////////////////////////////////////////////////////////////////////////
//
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:06 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_stub.v
// Design : system_microblaze_0_axi_intc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_intc,Vivado 2016.4" *)
module system_microblaze_0_axi_intc_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, processor_clk, processor_rst, irq,
processor_ack, interrupt_address)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[6:0],processor_clk,processor_rst,irq,processor_ack[1:0],interrupt_address[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [6:0]intr;
input processor_clk;
input processor_rst;
output irq;
input [1:0]processor_ack;
output [31:0]interrupt_address;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND3_PP_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_TB_V
/**
* udp_dlatch$PR_pp$PG: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_pr_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PR_pp$PG dut (.D(D), .RESET(RESET), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_TB_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module MakeResetA (
CLK,
RST_N,
ASSERT_IN,
ASSERT_OUT,
DST_CLK,
OUT_RST_N
);
parameter RSTDELAY = 2 ; // Width of reset shift reg
parameter init = 1 ;
input CLK ;
input RST_N ;
input ASSERT_IN ;
output ASSERT_OUT ;
input DST_CLK ;
output OUT_RST_N ;
reg rst ;
wire OUT_RST_N ;
assign ASSERT_OUT = !rst ;
SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK),
.IN_RST_N(rst),
.OUT_RST_N(OUT_RST_N));
always@(posedge CLK or negedge RST_N) begin
if (RST_N == 0)
rst <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (ASSERT_IN)
rst <= `BSV_ASSIGNMENT_DELAY 1'b0;
else // if (rst == 1'b0)
rst <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
#0 ;
rst = 1'b1 ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // MakeResetA
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:45:28 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/gcd_zynq_snick_auto_pc_0_stub.v
// Design : gcd_zynq_snick_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module gcd_zynq_snick_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_dout; // RAM data output
// INPUTs
//============
input [ADDR_MSB:0] ram_addr; // RAM address
input ram_cen; // RAM chip enable (low active)
input ram_clk; // RAM clock
input [15:0] ram_din; // RAM data input
input [1:0] ram_wen; // RAM write enable (low active)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
wire [15:0] mem_val = mem[ram_addr];
always @(posedge ram_clk)
if (~ram_cen & ram_addr<(MEM_SIZE/2))
begin
if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
ram_addr_reg <= ram_addr;
end
assign ram_dout = mem[ram_addr_reg];
endmodule // ram
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:41:38 09/19/2015
// Design Name: hw2problem3
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/hw2problem3/hw2problem3Test.v
// Project Name: hw2problem3
////////////////////////////////////////////////////////////////////////////////
module hw2problem3Test;
reg X, RESET, CLOCK;
wire Y;
wire [1:0] CurrentState;
hw2problem3 uut(X, Y, RESET, CLOCK, CurrentState);
always #5 CLOCK = ~CLOCK;
initial begin
CLOCK = 0; RESET = 0; X = 0; #1;
RESET = 1; #13; // Start at 00
X = 1; #10; // Go to 01
X = 1; #10; // Go to 11
X = 1; #10; // Go to 10
X = 1; #10; // Stay at 10
X = 0; #10; // Go to 00
X = 0; #10; // Stay at 00
X = 1; #10; // Go to 01
X = 0; #10; // Go to 00
X = 1; #10; // Go to 01
X = 1; #10; // Go to 11
X = 0; #10; // Go to 00
X = 1; #7; // Go to 01
RESET = 0; #10 // Reset to 00 asynchronously
$stop;
end
endmodule
|
/* 同步 FIFO 16*16 */
// 一种2bit 16深度的 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
module fifo(clock,reset,read,write,fifo_in,fifo_out,fifo_empty,fifo_full);
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [15:0]fifo_in; // FIFO 数据输入
output[15:0]fifo_out; // FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
reg [15:0]fifo_out; // 数据输出寄存器
reg [15:0]ram[15:0]; // 16深度 16宽度的RAM 寄存器
reg [3:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为4 2^4 = 16
wire fifo_empty,fifo_full; // 空标志,满标志
always@(posedge clock) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // 相应读写开关
2'b00: //没有读写指令
counter=counter;
2'b01: //写指令，数据输入FIFO
begin
ram[write_ptr] = fifo_in;
counter = counter+1;
write_ptr = (write_ptr == 15)?0:write_ptr + 1;
end
2'b10: //读指令，数据读出FIFO
begin
fifo_out = ram[read_ptr];
counter = counter - 1;
read_ptr = (read_ptr == 15)?0:read_ptr + 1;
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
fifo_out = fifo_in;
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
write_ptr=(write_ptr==15)?0:write_ptr+1;
read_ptr=(read_ptr==15)?0:write_ptr+1;
end
end
endcase
assign fifo_empty = (counter == 0); //标志位赋值
assign fifo_full = (counter == 15);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; Loos OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE PoosIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module up_hdmi_rx (
// hdmi interface
hdmi_clk,
hdmi_rst,
hdmi_edge_sel,
hdmi_bgr,
hdmi_packed,
hdmi_csc_bypass,
hdmi_vs_count,
hdmi_hs_count,
hdmi_dma_ovf,
hdmi_dma_unf,
hdmi_tpm_oos,
hdmi_vs_oos,
hdmi_hs_oos,
hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs,
hdmi_hs,
hdmi_clk_ratio,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00040063;
parameter ID = 0;
// hdmi interface
input hdmi_clk;
output hdmi_rst;
output hdmi_edge_sel;
output hdmi_bgr;
output hdmi_packed;
output hdmi_csc_bypass;
output [15:0] hdmi_vs_count;
output [15:0] hdmi_hs_count;
input hdmi_dma_ovf;
input hdmi_dma_unf;
input hdmi_tpm_oos;
input hdmi_vs_oos;
input hdmi_hs_oos;
input hdmi_vs_mismatch;
input hdmi_hs_mismatch;
input [15:0] hdmi_vs;
input [15:0] hdmi_hs;
input [31:0] hdmi_clk_ratio;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_core_preset = 'd0;
reg up_resetn = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_edge_sel = 'd0;
reg up_bgr = 'd0;
reg up_packed = 'd0;
reg up_csc_bypass = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_tpm_oos = 'd0;
reg up_vs_oos = 'd0;
reg up_hs_oos = 'd0;
reg up_vs_mismatch = 'd0;
reg up_hs_mismatch = 'd0;
reg [15:0] up_vs_count = 'd0;
reg [15:0] up_hs_count = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
wire up_vs_oos_s;
wire up_hs_oos_s;
wire up_vs_mismatch_s;
wire up_hs_mismatch_s;
wire [15:0] up_vs_s;
wire [15:0] up_hs_s;
wire [31:0] up_clk_count_s;
// decode block select
assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_core_preset <= 1'd1;
up_resetn <= 'd0;
up_wack <= 'd0;
up_scratch <= 'd0;
up_edge_sel <= 'd0;
up_bgr <= 'd0;
up_packed <= 'd0;
up_csc_bypass <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
up_tpm_oos <= 'd0;
up_vs_oos <= 'd0;
up_hs_oos <= 'd0;
up_vs_mismatch <= 'd0;
up_hs_mismatch <= 'd0;
up_vs_count <= 'd0;
up_hs_count <= 'd0;
end else begin
up_wack <= up_wreq_s;
up_core_preset <= ~up_resetn;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_edge_sel <= up_wdata[3];
up_bgr <= up_wdata[2];
up_packed <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[0];
end
if (up_tpm_oos_s == 1'b1) begin
up_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_tpm_oos <= up_tpm_oos & ~up_wdata[1];
end
if (up_vs_oos_s == 1'b1) begin
up_vs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_oos <= up_vs_oos & ~up_wdata[3];
end
if (up_hs_oos_s == 1'b1) begin
up_hs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_oos <= up_hs_oos & ~up_wdata[2];
end
if (up_vs_mismatch_s == 1'b1) begin
up_vs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_mismatch <= up_vs_mismatch & ~up_wdata[1];
end
if (up_hs_mismatch_s == 1'b1) begin
up_hs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_mismatch <= up_hs_mismatch & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_vs_count <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if(up_rreq_s == 1'b1) begin
case (up_raddr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'h0, up_resetn};
12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
12'h015: up_rdata <= up_clk_count_s;
12'h016: up_rdata <= hdmi_clk_ratio;
12'h018: up_rdata <= {30'h0, up_dma_ovf, up_dma_unf};
12'h019: up_rdata <= {30'h0, up_tpm_oos, 1'b0};
12'h020: up_rdata <= {28'h0, up_vs_oos, up_hs_oos,
up_vs_mismatch, up_hs_mismatch};
12'h100: up_rdata <= {up_vs_count, up_hs_count};
12'h101: up_rdata <= {up_vs_s, up_hs_s};
default: up_rdata <= 0;
endcase
end
end
end
// resets
ad_rst i_hdmi_rst_reg (
.preset (up_core_preset),
.clk (hdmi_clk),
.rst (hdmi_rst));
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(36)) i_hdmi_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_edge_sel,
up_bgr,
up_packed,
up_csc_bypass,
up_vs_count,
up_hs_count}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_edge_sel,
hdmi_bgr,
hdmi_packed,
hdmi_csc_bypass,
hdmi_vs_count,
hdmi_hs_count}));
up_xfer_status #(.DATA_WIDTH(39)) i_hdmi_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({ up_dma_ovf_s,
up_dma_unf_s,
up_tpm_oos_s,
up_vs_oos_s,
up_hs_oos_s,
up_vs_mismatch_s,
up_hs_mismatch_s,
up_vs_s,
up_hs_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ hdmi_dma_ovf,
hdmi_dma_unf,
hdmi_tpm_oos,
hdmi_vs_oos,
hdmi_hs_oos,
hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs,
hdmi_hs}));
up_clock_mon i_hdmi_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_clk_count_s),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// bsg_rp_clk_gen_coarse_delay_element
//
// (o is inverting on even start_tap_p
// worst_o is non-inverting)
//
// o contains controllably delayed signal
// worst_o contains worst-case delayed signal (for delay matching)
//
//
// we use sed to substitute parameters because the netlist reader
// does not like them, and we need the netlist reader for rp_groups
//
// module bsg_clk_gen_coarse_delay_element #(parameter `BSG_INV_PARAM(start_tap_p))
//
module bsg_rp_clk_gen_atomic_delay_tuner
(input i
, input sel_i
, input we_i
, input async_reset_neg_i
, output o
);
wire [1:0] sel_r;
wire [8:0] signal;
assign signal[0] = i;
// synopsys rp_group (bsg_clk_gen_adt)
// synopsys rp_fill (13 2 LX)
CLKINVX2 I1 (.A(signal[0]), .Y(signal[1]) );
CLKINVX2 I2 (.A(signal[1]), .Y(signal[2]) );
CLKINVX4 I2a (.A(signal[1]), .Y() );
CLKINVX2 I3 (.A(signal[2]), .Y(signal[3]) );
CLKINVX2 I4 (.A(signal[3]), .Y(signal[4]) );
CLKINVX4 I4a (.A(signal[3]), .Y() );
CLKINVX2 I4b (.A(signal[3]), .Y() ); // this is an extra gate because
// we are not attaching to the mux
// cap tries to match that of mux input
CLKINVX2 I5 (.A(signal[4]), .Y(signal[5]) );
CLKINVX2 I6 (.A(signal[5]), .Y(signal[6]) );
CLKINVX4 I6a (.A(signal[5]), .Y() );
CLKINVX2 I7 (.A(signal[6]), .Y(signal[7]) );
CLKINVX2 I8 (.A(signal[7]), .Y(signal[8]) );
CLKINVX4 I8a (.A(signal[7]), .Y() );
CLKINVX3 I8b (.A(signal[7]), .Y() ); // fudge factor capacitance
// synopsys rp_fill (0 1 RX)
wire zero_bit;
MXI4X4 M1 ( .A(signal[8])
,.B(signal[6])
,.C(zero_bit)
,.D(signal[0])
,.S0(sel_r[0])
,.S1(sel_r[1])
,.Y (o )
);
wire [1:0] mux_lo;
// synopsys rp_fill (0 0 RX)
// this gate picks input 01 when async reset is low, initializing the oscillator
NAND2BX2 NB (.AN(sel_r[0]), .B(async_reset_neg_i), .Y(sel_r[1]));
TIELO ZB (.Y(zero_bit));
wire sel_r_0_inv, sel_i_inv;
DFFRX4 sel_r_reg_0 (.D(mux_lo[0]), .CK(o) ,.RN(async_reset_neg_i), .Q(sel_r[0]), .QN(sel_r_0_inv));
CLKINVX2 I_MX (.A(sel_i), .Y(sel_i_inv));
// we invert both inputs of this mux to optimize the select-to-output path by 40 ps
MXI2X1 MX1 (.A(sel_r_0_inv) , .B(sel_i_inv) ,.S0(we_i), .Y(mux_lo[0]));
// synopsys rp_endgroup (bsg_clk_gen_adt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_atomic_delay_tuner)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdlclkp (
VPWR,
VGND,
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
input VPWR;
input VGND;
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (m0 , SCE_GATE, clkn, VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_PP_V |
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*
########################################################################
A SIMPLE COUNTER
########################################################################
*/
module emon_counter (/*AUTOARG*/
// Outputs
emon_reg, emon_zero_flag,
// Inputs
clk, reset, emon_vector, emon_sel, reg_write, reg_data
);
/**************************************************************************/
/*PARAMETERS */
/**************************************************************************/
parameter RFAW = 6;
parameter DW = 32;
/**************************************************************************/
/*BASIC INTERFACE */
/**************************************************************************/
input clk;
input reset;
/**************************************************************************/
/*CONFIGURATION */
/**************************************************************************/
input [15:0] emon_vector; //different events to count
input [3:0] emon_sel; //mode selector
/**************************************************************************/
/*REGISTER WRITE INTERFACE */
/**************************************************************************/
input reg_write;
input [DW-1:0] reg_data;
/*********************************************************************** */
/*MONITOR OUTPUTS */
/*************************************************************************/
output [DW-1:0] emon_reg; //register value
output emon_zero_flag;//monitor is zero
/*************************************************************************/
/*REGISTERS */
/*************************************************************************/
reg [DW-1:0] emon_reg;
reg emon_input;
/*************************************************************************/
/*INPUT MUX */
/*************************************************************************/
always @(posedge clk)
emon_input <= emon_vector[emon_sel[3:0]];
/*************************************************************************/
/*COUNTER */
/*************************************************************************/
always @(posedge clk)
if(reset)
emon_reg[DW-1:0] <= {(DW){1'b1}}; //initialize with max value
else if(reg_write)
emon_reg[DW-1:0] <= reg_data[DW-1:0];//writeable interface
else
emon_reg[DW-1:0] <= emon_reg[DW-1:0] - {31'b0,emon_input};
/************************************************************************ */
/*OUTPUTS */
/**************************************************************************/
//Detecting zero on counter
assign emon_zero_flag = ~(|emon_reg[DW-1:0]);
endmodule // ctimer
|
//
// Copyright (C) 2015 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define TRUE 1'b1
`define FALSE 1'b0
`define HI 1'b1
`define LO 1'b0
`define LINEMULT_DISABLE 2'h0
`define LINEMULT_DOUBLE 2'h1
`define LINEMULT_TRIPLE 2'h2
`define LINETRIPLE_M0 2'h0
`define LINETRIPLE_M1 2'h1
`define LINETRIPLE_M2 2'h2
`define LINETRIPLE_M3 2'h3
`define VSYNCGEN_LEN 6
`define VSYNCGEN_GENMID_BIT 0
`define VSYNCGEN_CHOPMID_BIT 1
`define FID_EVEN 1'b0
`define FID_ODD 1'b1
module scanconverter (
input [7:0] R_in,
input [7:0] G_in,
input [7:0] B_in,
input FID_in,
input VSYNC_in,
input HSYNC_in,
input PCLK_in,
input [31:0] h_info,
input [31:0] v_info,
output reg [7:0] R_out,
output reg [7:0] G_out,
output reg [7:0] B_out,
output reg HSYNC_out,
output reg VSYNC_out,
output PCLK_out,
output reg DATA_enable,
output [1:0] FID_ID,
output h_unstable,
output reg [1:0] fpga_vsyncgen,
output [2:0] pclk_lock,
output [2:0] pll_lock_lost,
output [10:0] lines_out
);
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_3x_h1x, pclk_3x_h4x, pclk_3x_h5x;
wire pclk_out_1x, pclk_out_2x, pclk_out_3x, pclk_out_4x, pclk_out_3x_h4x, pclk_out_3x_h5x;
wire linebuf_rdclock;
wire pclk_act;
wire [1:0] slid_act;
wire pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock;
wire HSYNC_act, VSYNC_act;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_3x_h1x, HSYNC_pp1;
reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
reg [11:0] HSYNC_start;
wire DATA_enable_act;
reg DATA_enable_pp1;
reg FID_prev;
wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
wire [11:0] hcnt_act;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_h1x, hcnt_3x_h4x, hcnt_3x_h5x;
wire [10:0] vcnt_act;
reg [10:0] vcnt_1x, vcnt_2x, vcnt_1x_tvp, lines_1x, lines_2x; //max. 2047
reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x, lines_3x_h1x; //max. 1023
reg h_enable_3x_prev4x, h_enable_3x_prev3x_h4x, h_enable_3x_prev3x_h5x;
reg [1:0] hcnt_3x_h4x_ctr;
reg [1:0] hcnt_3x_h5x_ctr;
reg pclk_1x_prev3x, pclk_1x_prev3x_h1x, pclk_1x_prev3x_h4x;
reg [1:0] pclk_3x_cnt, pclk_3x_h1x_cnt;
reg [3:0] pclk_3x_h4x_cnt;
// Data enable
reg h_enable_1x, v_enable_1x;
reg h_enable_2x, v_enable_2x;
reg h_enable_3x, h_enable_3x_h1x, v_enable_3x, v_enable_3x_h1x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
reg line_idx;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x, warn_pll_lock_lost_3x_lowfreq;
reg [10:0] H_ACTIVE; //max. 2047
reg [7:0] H_BACKPORCH; //max. 255
reg [10:0] V_ACTIVE; //max. 2047
reg [5:0] V_BACKPORCH; //max. 63
reg V_MISMODE;
reg V_SCANLINES;
reg V_SCANLINEDIR;
reg V_SCANLINEID;
reg [7:0] V_SCANLINESTR;
reg [5:0] V_MASK;
reg [1:0] H_LINEMULT;
reg [1:0] H_L3MODE;
reg [5:0] H_MASK;
//8 bits per component -> 16.7M colors
reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
wire [7:0] R_act, G_act, B_act;
assign pclk_1x = PCLK_in;
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock};
//Output sampled at the rising edge of active pclk
assign pclk_out_1x = PCLK_in;
assign pclk_out_2x = pclk_2x;
assign pclk_out_3x = pclk_3x;
assign pclk_out_4x = pclk_4x;
assign pclk_out_3x_h4x = pclk_3x_h4x;
assign pclk_out_3x_h5x = pclk_3x_h5x;
assign FID_ID[1] = ~FID_in;
assign FID_ID[0] = FID_in;
//Scanline generation
function [8:0] apply_scanlines;
input enable;
input dir;
input [8:0] data;
input [8:0] str;
input [1:0] actid;
input [1:0] lineid;
input pixid;
begin
if (enable & (dir == 1'b0) & (actid == lineid))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if (enable & (dir == 1'b1) & (actid == pixid))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else
apply_scanlines = data;
end
endfunction
//Border masking
function [8:0] apply_mask;
input enable;
input [8:0] data;
input [11:0] hoffset;
input [11:0] hstart;
input [11:0] hend;
input [10:0] voffset;
input [10:0] vstart;
input [10:0] vend;
begin
if (enable & ((hoffset < hstart) | (hoffset >= hend) | (voffset < vstart) | (voffset >= vend)))
apply_mask = 8'h00;
else
apply_mask = data;
//apply_mask = (hoffset[0] ^ voffset[0]) ? 8'b11111111 : 8'b00000000;
end
endfunction
//Mux for active data selection
//
//Possible clock transfers:
//
// L3_MODE1: pclk_3x -> pclk_4x
// L3_MODE2: pclk_3x_h1x -> pclk_3x_h4x
// L3_MODE3: pclk_3x_h1x -> pclk_3x_h5x
//
//List of critical signals:
// DATA_enable_act, HSYNC_act
//
//Non-critical signals and inactive clock combinations filtered out in SDC
always @(*)
begin
case (H_LINEMULT)
`LINEMULT_DISABLE: begin
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
DATA_enable_act = (h_enable_1x & v_enable_1x);
PCLK_out = pclk_out_1x;
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
lines_out = lines_1x;
linebuf_rdclock = 0;
linebuf_hoffset = 0;
pclk_act = pclk_1x;
slid_act = {1'b0, vcnt_1x[0]};
hcnt_act = hcnt_1x;
vcnt_act = vcnt_1x;
end
`LINEMULT_DOUBLE: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
DATA_enable_act = (h_enable_2x & v_enable_2x);
PCLK_out = pclk_out_2x;
HSYNC_act = HSYNC_2x;
VSYNC_act = VSYNC_2x;
lines_out = lines_2x;
linebuf_rdclock = pclk_2x;
linebuf_hoffset = hcnt_2x;
pclk_act = pclk_2x;
slid_act = {1'b0, vcnt_2x[0]};
hcnt_act = hcnt_2x;
vcnt_act = vcnt_2x>>1;
end
`LINEMULT_TRIPLE: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
VSYNC_act = VSYNC_1x;
case (H_L3MODE)
`LINETRIPLE_M0: begin
DATA_enable_act = (h_enable_3x & v_enable_3x);
PCLK_out = pclk_out_3x;
HSYNC_act = HSYNC_3x;
lines_out = {1'b0, lines_3x};
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
vcnt_act = vcnt_3x/2'h3; //divider generated
slid_act = (vcnt_3x % 2'h3);
end
`LINETRIPLE_M1: begin
DATA_enable_act = (h_enable_3x & v_enable_3x);
PCLK_out = pclk_out_4x;
HSYNC_act = HSYNC_3x;
lines_out = {1'b0, lines_3x};
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x;
vcnt_act = vcnt_3x/2'h3; //divider generated
slid_act = (vcnt_3x % 2'h3);
end
`LINETRIPLE_M2: begin
DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
PCLK_out = pclk_out_3x_h4x;
HSYNC_act = HSYNC_3x_h1x;
lines_out = {1'b0, lines_3x_h1x};
linebuf_rdclock = pclk_3x_h4x;
linebuf_hoffset = hcnt_3x_h4x;
pclk_act = pclk_3x_h4x;
hcnt_act = hcnt_3x_h4x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
slid_act = (vcnt_3x_h1x % 2'h3);
end
`LINETRIPLE_M3: begin
DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
PCLK_out = pclk_out_3x_h5x;
HSYNC_act = HSYNC_3x_h1x;
lines_out = {1'b0, lines_3x_h1x};
linebuf_rdclock = pclk_3x_h5x;
linebuf_hoffset = hcnt_3x_h5x;
pclk_act = pclk_3x_h5x;
hcnt_act = hcnt_3x_h5x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
slid_act = (vcnt_3x_h1x % 2'h3);
end
endcase
end
default: begin
R_act = 0;
G_act = 0;
B_act = 0;
DATA_enable_act = 0;
PCLK_out = 0;
HSYNC_act = 0;
VSYNC_act = VSYNC_1x;
lines_out = 0;
linebuf_rdclock = 0;
linebuf_hoffset = 0;
pclk_act = 0;
slid_act = 0;
hcnt_act = 0;
vcnt_act = 0;
end
endcase
end
pll_2x pll_linedouble (
.areset ( (H_LINEMULT != `LINEMULT_DOUBLE) ),
.inclk0 ( PCLK_in ),
.c0 ( pclk_2x ),
.locked ( pclk_2x_lock )
);
pll_3x pll_linetriple (
.areset ( ((H_LINEMULT != `LINEMULT_TRIPLE) | H_L3MODE[1]) ),
.inclk0 ( PCLK_in ),
.c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9)
.c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect)
.locked ( pclk_3x_lock )
);
pll_3x_lowfreq pll_linetriple_lowfreq (
.areset ( (H_LINEMULT != `LINEMULT_TRIPLE) | ~H_L3MODE[1]),
.inclk0 ( PCLK_in ),
.c0 ( pclk_3x_h1x ), // sampling clock for 240p: 320 or 256 samples
.c1 ( pclk_3x_h4x ), // MODE2: 1280 output pixels from 320 input samples (960 drawn -> 4:3 aspect)
.c2 ( pclk_3x_h5x ), // MODE3: 1280 output pixels from 256 input samples (1024 drawn -> 5:4 aspect)
.locked ( pclk_3x_lowfreq_lock )
);
//TODO: add secondary buffers for interlaced signals with alternative field order
linebuf linebuf_rgb (
.data ( {R_1x, G_1x, B_1x} ), //or *_in?
.rdaddress ( linebuf_hoffset + (~line_idx << 11) ),
.rdclock ( linebuf_rdclock ),
.wraddress ( hcnt_1x + (line_idx << 11) ),
.wrclock ( pclk_1x ),
.wren ( 1'b1 ),
.q ( {R_lbuf, G_lbuf, B_lbuf} )
);
//Postprocess pipeline
always @(posedge pclk_act /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
R_pp1 <= apply_mask(1, R_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
G_pp1 <= apply_mask(1, G_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
B_pp1 <= apply_mask(1, B_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
HSYNC_pp1 <= HSYNC_act;
VSYNC_pp1 <= VSYNC_act;
DATA_enable_pp1 <= DATA_enable_act;
R_out <= apply_scanlines(V_SCANLINES, V_SCANLINEDIR, R_pp1, V_SCANLINESTR, {1'b0, V_SCANLINEID}, slid_act, hcnt_act[0]);
G_out <= apply_scanlines(V_SCANLINES, V_SCANLINEDIR, G_pp1, V_SCANLINESTR, {1'b0, V_SCANLINEID}, slid_act, hcnt_act[0]);
B_out <= apply_scanlines(V_SCANLINES, V_SCANLINEDIR, B_pp1, V_SCANLINESTR, {1'b0, V_SCANLINEID}, slid_act, hcnt_act[0]);
HSYNC_out <= HSYNC_pp1;
VSYNC_out <= VSYNC_pp1;
DATA_enable <= DATA_enable_pp1;
end
end
//Generate a warning signal from horizontal instability or PLL sync loss
always @(posedge pclk_1x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
if (hmax[0] != hmax[1])
warn_h_unstable <= 1;
else if (warn_h_unstable != 0)
warn_h_unstable <= warn_h_unstable + 1'b1;
if ((H_LINEMULT == `LINEMULT_DOUBLE) & ~pclk_2x_lock)
warn_pll_lock_lost <= 1;
else if (warn_pll_lock_lost != 0)
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
if ((H_LINEMULT == `LINEMULT_TRIPLE) & ~H_L3MODE[1] & ~pclk_3x_lock)
warn_pll_lock_lost_3x <= 1;
else if (warn_pll_lock_lost_3x != 0)
warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
if ((H_LINEMULT == `LINEMULT_TRIPLE) & H_L3MODE[1] & ~pclk_3x_lowfreq_lock)
warn_pll_lock_lost_3x_lowfreq <= 1;
else if (warn_pll_lock_lost_3x_lowfreq != 0)
warn_pll_lock_lost_3x_lowfreq <= warn_pll_lock_lost_3x_lowfreq + 1'b1;
end
end
assign h_unstable = (warn_h_unstable != 0);
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), (warn_pll_lock_lost_3x_lowfreq != 0)};
//Buffer the inputs using input pixel clock and generate 1x signals
always @(posedge pclk_1x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
if ((prev_hs == 1'b0) & (HSYNC_in == 1'b1))
begin
hcnt_1x <= 0;
hmax[line_idx] <= hcnt_1x;
line_idx <= line_idx ^ 1'b1;
vcnt_1x <= vcnt_1x + 1'b1;
vcnt_1x_tvp <= vcnt_1x_tvp + 1'b1;
end
else
begin
hcnt_1x <= hcnt_1x + 1'b1;
end
// detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs).
// FID is updated at leading edge of VSYNC, so trailing edge has the status of current field.
if ((prev_vs == `LO) & (VSYNC_in == `HI))
begin
vcnt_1x_tvp <= 0;
FID_prev <= FID_in;
if (FID_in == FID_prev)
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= 1'b0;
else if (FID_in == `FID_EVEN) // TVP7002 falsely indicates even field (vcnt < active_lines)
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_1x_tvp < 200) ? 1'b1 : 1'b0;
end
if ((prev_vs == 1'b0) & (VSYNC_in == 1'b1) & (V_MISMODE ? (FID_in == 1'b0) : 1'b1)) //should be checked at every pclk_1x?
begin
vcnt_1x <= 0;
lines_1x <= vcnt_1x;
//Read configuration data from CPU
H_ACTIVE <= h_info[26:16]; // Horizontal active length from by the CPU - 11bits (0...2047)
H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255)
H_LINEMULT <= h_info[31:30]; // Horizontal line multiply mode
H_L3MODE <= h_info[29:28]; // Horizontal line triple mode
H_MASK <= {h_info[11:8], 2'b00};
V_ACTIVE <= v_info[23:13]; // Vertical active length from by the CPU, 11bits (0...2047)
V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64)
V_MISMODE <= v_info[31];
V_SCANLINES <= v_info[29];
V_SCANLINEDIR <= v_info[28];
V_SCANLINEID <= v_info[27];
V_SCANLINESTR <= ((v_info[26:24]+8'h01)<<5)-1'b1;
V_MASK <= {v_info[9:6], 2'b00};
end
prev_hs <= HSYNC_in;
prev_vs <= VSYNC_in;
// record start position of HSYNC
if ((prev_hs == 1'b1) & (HSYNC_in == 1'b0))
HSYNC_start <= hcnt_1x;
R_1x <= R_in;
G_1x <= G_in;
B_1x <= B_in;
HSYNC_1x <= HSYNC_in;
// Ignore possible invalid vsyncs generated by TVP7002
if (vcnt_1x > V_ACTIVE)
VSYNC_1x <= VSYNC_in;
// Check if extra vsync needed
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= (lines_1x > ({1'b0, V_ACTIVE} << 1)) ? 1'b1 : 1'b0;
h_enable_1x <= ((hcnt_1x >= H_BACKPORCH) & (hcnt_1x < H_BACKPORCH + H_ACTIVE));
v_enable_1x <= ((vcnt_1x >= V_BACKPORCH) & (vcnt_1x < V_BACKPORCH + V_ACTIVE)); //- FID_in ???
/*HSYNC_out_debug <= HSYNC_in;
VSYNC_out_debug <= VSYNC_in;*/
end
end
//Generate 2x signals for linedouble
always @(posedge pclk_2x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
if ((pclk_1x == 1'b0) & (prev_hs == 1'b0) & (HSYNC_in == 1'b1)) //sync with posedge of pclk_1x
hcnt_2x <= 0;
else if (hcnt_2x == hmax[~line_idx]) //line_idx_prev?
hcnt_2x <= 0;
else
hcnt_2x <= hcnt_2x + 1'b1;
if (hcnt_2x == 0)
vcnt_2x <= vcnt_2x + 1'b1;
if ((pclk_1x == 1'b0) & (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1))
begin
if ((prev_vs == 1'b0) & (VSYNC_in == 1'b1))
vcnt_2x <= 0;
else if (vcnt_2x == lines_1x)
begin
vcnt_2x <= 0;
lines_2x <= vcnt_2x;
end
end
else if ((pclk_1x == 1'b0) & (prev_vs == 1'b0) & (VSYNC_in == 1'b1) & (V_MISMODE ? (FID_in == 1'b0) : 1'b1)) //sync with posedge of pclk_1x
begin
vcnt_2x <= 0;
lines_2x <= vcnt_2x;
end
if (pclk_1x == 1'b0)
begin
if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1)
VSYNC_2x <= (vcnt_2x >= lines_1x - `VSYNCGEN_LEN) ? 1'b0 : 1'b1;
else if (vcnt_1x > V_ACTIVE)
VSYNC_2x <= VSYNC_in;
end
HSYNC_2x <= ~(hcnt_2x >= HSYNC_start);
//TODO: VSYNC_2x
h_enable_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE));
v_enable_2x <= ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1)));
end
end
//Generate 3x signals for linetriple M0
always @(posedge pclk_3x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
if ((pclk_3x_cnt == 0) & (prev_hs == 1'b0) & (HSYNC_in == 1'b1)) //sync with posedge of pclk_1x
hcnt_3x <= 0;
else if (hcnt_3x == hmax[~line_idx]) //line_idx_prev?
hcnt_3x <= 0;
else
hcnt_3x <= hcnt_3x + 1'b1;
if (hcnt_3x == 0)
vcnt_3x <= vcnt_3x + 1'b1;
if ((pclk_3x_cnt == 0) & (prev_vs == 1'b0) & (VSYNC_in == 1'b1) & (V_MISMODE ? (FID_in == 1'b0) : 1'b1)) //sync with posedge of pclk_1x
begin
vcnt_3x <= 0;
lines_3x <= vcnt_3x;
end
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
//TODO: VSYNC_3x
h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE));
v_enable_3x <= ((vcnt_3x >= (3*V_BACKPORCH)) & (vcnt_3x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!!
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
else
pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
pclk_1x_prev3x <= pclk_1x;
end
end
//Generate 4x signals for linetriple M1
always @(posedge pclk_4x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
// Can we sync reliably to h_enable_3x???
if ((h_enable_3x == 1) & (h_enable_3x_prev4x == 0))
hcnt_4x <= hcnt_3x - 160;
else
hcnt_4x <= hcnt_4x + 1'b1;
h_enable_3x_prev4x <= h_enable_3x;
end
end
//Generate 3x_h1x signals for linetriple M2 and M3
always @(posedge pclk_3x_h1x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
if ((pclk_3x_h1x_cnt == 0) & (prev_hs == 1'b0) & (HSYNC_in == 1'b1)) //sync with posedge of pclk_1x
hcnt_3x_h1x <= 0;
else if (hcnt_3x_h1x == hmax[~line_idx]) //line_idx_prev?
hcnt_3x_h1x <= 0;
else
hcnt_3x_h1x <= hcnt_3x_h1x + 1'b1;
if (hcnt_3x_h1x == 0)
vcnt_3x_h1x <= vcnt_3x_h1x + 1'b1;
if ((pclk_3x_h1x_cnt == 0) & (prev_vs == 1'b0) & (VSYNC_in == 1'b1) & (V_MISMODE ? (FID_in == 1'b0) : 1'b1)) //sync with posedge of pclk_1x
begin
vcnt_3x_h1x <= 0;
lines_3x_h1x <= vcnt_3x_h1x;
end
HSYNC_3x_h1x <= ~(hcnt_3x_h1x >= HSYNC_start);
//TODO: VSYNC_3x_h1x
h_enable_3x_h1x <= ((hcnt_3x_h1x >= H_BACKPORCH) & (hcnt_3x_h1x < H_BACKPORCH + H_ACTIVE));
v_enable_3x_h1x <= ((vcnt_3x_h1x >= (3*V_BACKPORCH)) & (vcnt_3x_h1x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!!
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x_h1x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_h1x_cnt == 2'h2))
pclk_3x_h1x_cnt <= 0;
else
pclk_3x_h1x_cnt <= pclk_3x_h1x_cnt + 1'b1;
pclk_1x_prev3x_h1x <= pclk_1x;
end
end
//Generate 3x_h4x signals for for linetriple M2
always @(posedge pclk_3x_h4x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
// Can we sync reliably to h_enable_3x???
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0))
hcnt_3x_h4x <= hcnt_3x_h1x - (160/3);
else if (hcnt_3x_h4x_ctr == 2'h0)
hcnt_3x_h4x <= hcnt_3x_h4x + 1'b1;
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0))
hcnt_3x_h4x_ctr <= 2'h1;
else if (hcnt_3x_h4x_ctr == 2'h2)
hcnt_3x_h4x_ctr <= 2'h0;
else
hcnt_3x_h4x_ctr <= hcnt_3x_h4x_ctr + 1'b1;
h_enable_3x_prev3x_h4x <= h_enable_3x_h1x;
end
end
//Generate 3x_h5x signals for for linetriple M3
always @(posedge pclk_3x_h5x /*or negedge reset_n*/)
begin
/*if (!reset_n)
begin
end
else*/
begin
// Can we sync reliably to h_enable_3x???
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0))
hcnt_3x_h5x <= hcnt_3x_h1x - (128/4);
else if (hcnt_3x_h5x_ctr == 2'h0)
hcnt_3x_h5x <= hcnt_3x_h5x + 1'b1;
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0))
hcnt_3x_h5x_ctr <= 2'h2;
else
hcnt_3x_h5x_ctr <= hcnt_3x_h5x_ctr + 1'b1;
h_enable_3x_prev3x_h5x <= h_enable_3x_h1x;
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* Byte wide asynchronous fifo for use in SPDR module.
*
*/
module spdr_fifo
(
input rst_in,
input clk_in,
input clk_out,
input [7:0] din,
input push,
output full,
output [7:0] dout,
input pop,
output empty
);
reg [1:0] cross_in;
reg [3:0] head_in;
reg [3:0] head_snapshot;
reg [3:0] tail_in;
reg [1:0] cross_out;
reg [3:0] head_out;
reg [3:0] tail_out;
reg [3:0] tail_snapshot;
always @ (posedge clk_in)
cross_in <= cross_out;
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
cross_out <= 2'b00;
else
case (cross_in)
2'b00: cross_out <= 2'b01;
2'b01: cross_out <= 2'b11;
2'b11: cross_out <= 2'b10;
default: cross_out <= 2'b00;
endcase
wire [3:0] head_in_next = head_in + 4'd1;
wire fifo_full = (head_in_next == tail_in);
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
begin
head_in <= 4'd0;
head_snapshot <= 4'd0;
tail_in <= 4'd0;
end
else
begin
if (push && !fifo_full)
head_in <= head_in_next;
case (cross_in)
2'b01: head_snapshot <= head_in;
2'b10: tail_in <= tail_snapshot;
endcase
end
wire [3:0] tail_out_next = tail_out + 4'd1;
wire fifo_empty = (tail_out == head_out);
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
begin
head_out <= 4'd0;
tail_out <= 4'd0;
tail_snapshot <= 4'd0;
end
else
begin
if (pop && !fifo_empty)
tail_out <= tail_out_next;
case (cross_out)
2'b01: tail_snapshot <= tail_out;
2'b10: head_out <= head_snapshot;
endcase
end
reg [7:0] fifo[15:0];
always @ (posedge clk_in)
if (push)
fifo[head_in] <= din[7:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign dout = fifo[tail_out];
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
/**
* top_ground_hvc_wpad: Ground pad.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_hvc_wpad (
//# {{data|Data Signals}}
inout G_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout G_CORE ,
inout VSWITCH ,
inout DRN_HVC ,
inout OGC_HVC ,
inout SRC_BDY_HVC,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/sensorfsm.v:3" *)
module \$paramod\SensorFSM\DataWidth=8 (Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorValue_o, MeasureFSM_Start_o, MeasureFSM_Done_i, MeasureFSM_Error_i, MeasureFSM_Byte0_i, MeasureFSM_Byte1_i, ParamThreshold_i, ParamCounterPreset_i);
(* src = "../../verilog/sensorfsm.v:145" *)
wire [15:0] \$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$2\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$3\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$3\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$4\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$5\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$5\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$6\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$7\SensorFSM_NextState[2:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire [2:0] \$8\SensorFSM_NextState[2:0] ;
wire \$procmux$195_CMP ;
wire \$procmux$202_CMP ;
wire \$procmux$207_CMP ;
wire \$procmux$210_CMP ;
wire \$procmux$257_CMP ;
wire [15:0] \$procmux$62_Y ;
(* src = "../../verilog/sensorfsm.v:159" *)
wire [15:0] \$sub$../../verilog/sensorfsm.v:159$51_Y ;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/sensorfsm.v:7" *)
input Clk_i;
(* src = "../../verilog/sensorfsm.v:10" *)
output CpuIntr_o;
(* src = "../../verilog/sensorfsm.v:183" *)
wire [16:0] DiffAB;
(* src = "../../verilog/sensorfsm.v:184" *)
wire [15:0] DiffBA;
(* src = "../../verilog/sensorfsm.v:9" *)
input Enable_i;
(* src = "../../verilog/sensorfsm.v:16" *)
input [7:0] MeasureFSM_Byte0_i;
(* src = "../../verilog/sensorfsm.v:17" *)
input [7:0] MeasureFSM_Byte1_i;
(* src = "../../verilog/sensorfsm.v:14" *)
input MeasureFSM_Done_i;
(* src = "../../verilog/sensorfsm.v:15" *)
input MeasureFSM_Error_i;
(* src = "../../verilog/sensorfsm.v:13" *)
output MeasureFSM_Start_o;
(* src = "../../verilog/sensorfsm.v:20" *)
input [15:0] ParamCounterPreset_i;
(* src = "../../verilog/sensorfsm.v:19" *)
input [15:0] ParamThreshold_i;
(* src = "../../verilog/sensorfsm.v:6" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:34" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/sensorfsm.v:30" *)
wire [2:0] SensorFSM_NextState;
(* src = "../../verilog/sensorfsm.v:29" *)
wire [2:0] SensorFSM_State;
(* src = "../../verilog/sensorfsm.v:35" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/sensorfsm.v:143" *)
wire [15:0] SensorFSM_Timer;
(* src = "../../verilog/sensorfsm.v:33" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/sensorfsm.v:31" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/sensorfsm.v:32" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] SensorValue;
(* src = "../../verilog/sensorfsm.v:11" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] Word0;
(* src = "../../verilog/sensorfsm.v:164" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/sensorfsm.v:164$52 (
.A(SensorFSM_Timer),
.B(16'b0000000000000000),
.Y(SensorFSM_TimerOvfl)
);
(* src = "../../verilog/sensorfsm.v:189" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/sensorfsm.v:189$59 (
.A(AbsDiffResult),
.B(ParamThreshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/sensorfsm.v:145" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2816 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[15:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/sensorfsm.v:168" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2817 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
(* src = "../../verilog/sensorfsm.v:47" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(3'b000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000011)
) \$procdff$2818 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(SensorFSM_NextState),
.Q(SensorFSM_State)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$194 (
.A(1'b0),
.B({ MeasureFSM_Error_i, 1'b1 }),
.S({ \$procmux$202_CMP , \$procmux$195_CMP }),
.Y(CpuIntr_o)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$195_CMP0 (
.A(SensorFSM_State),
.B(3'b011),
.Y(\$procmux$195_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$202_CMP0 (
.A(SensorFSM_State),
.B(3'b010),
.Y(\$procmux$202_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$207_CMP0 (
.A(SensorFSM_State),
.B(3'b001),
.Y(\$procmux$207_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$210_CMP0 (
.A(SensorFSM_State),
.B(3'b000),
.Y(\$procmux$210_CMP )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$227 (
.A(\$procmux$207_CMP ),
.B(\$2\MeasureFSM_Start_o[0:0] ),
.Y(MeasureFSM_Start_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$243 (
.A(\$procmux$202_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000101),
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$256 (
.A(SensorFSM_State),
.B({ \$2\SensorFSM_NextState[2:0] , \$3\SensorFSM_NextState[2:0] , \$5\SensorFSM_NextState[2:0] , 3'b001, \$8\SensorFSM_NextState[2:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP , \$procmux$195_CMP , \$procmux$257_CMP }),
.Y(SensorFSM_NextState)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$257_CMP0 (
.A(SensorFSM_State),
.B(3'b100),
.Y(\$procmux$257_CMP )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$285 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$306 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$334 (
.A(SensorFSM_State),
.B(3'b001),
.S(Enable_i),
.Y(\$2\SensorFSM_NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$356 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$397 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\MeasureFSM_Start_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$419 (
.A(3'b000),
.B(\$4\SensorFSM_NextState[2:0] ),
.S(Enable_i),
.Y(\$3\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$439 (
.A(SensorFSM_State),
.B(3'b010),
.S(SensorFSM_TimerOvfl),
.Y(\$4\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$482 (
.A(\$3\SensorFSM_StoreNewValue[0:0] ),
.B(1'b0),
.S(MeasureFSM_Error_i),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$526 (
.A(\$4\SensorFSM_TimerPreset[0:0] ),
.B(MeasureFSM_Error_i),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$548 (
.A(\$6\SensorFSM_NextState[2:0] ),
.B(3'b100),
.S(MeasureFSM_Error_i),
.Y(\$5\SensorFSM_NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$590 (
.A(SensorFSM_State),
.B(\$7\SensorFSM_NextState[2:0] ),
.S(MeasureFSM_Done_i),
.Y(\$6\SensorFSM_NextState[2:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$613 (
.A(MeasureFSM_Done_i),
.B(SensorFSM_DiffTooLarge),
.Y(\$3\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$62 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/sensorfsm.v:159$51_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$62_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$65 (
.A(\$procmux$62_Y ),
.B(ParamCounterPreset_i),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$659 (
.A(1'b1),
.B(\$5\SensorFSM_TimerPreset[0:0] ),
.S(MeasureFSM_Done_i),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$68 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$681 (
.A(3'b001),
.B(3'b011),
.S(SensorFSM_DiffTooLarge),
.Y(\$7\SensorFSM_NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$705 (
.A(SensorFSM_DiffTooLarge),
.Y(\$5\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$772 (
.A(3'b000),
.B(SensorFSM_State),
.S(Enable_i),
.Y(\$8\SensorFSM_NextState[2:0] )
);
(* src = "../../verilog/sensorfsm.v:159" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:159$51 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/sensorfsm.v:159$51_Y )
);
(* src = "../../verilog/sensorfsm.v:185" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/sensorfsm.v:185$56 (
.A({ 1'b0, MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/sensorfsm.v:186" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:186$57 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.Y(DiffBA)
);
(* src = "../../verilog/sensorfsm.v:187" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/sensorfsm.v:187$58 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue = { MeasureFSM_Byte1_i, MeasureFSM_Byte0_i };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/adt7410.v:1" *)
module ADT7410(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, PeriodCounterPreset_i, SensorValue_o, Threshold_i, WaitCounterPreset_i);
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/adt7410.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/adt7410.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/adt7410.v:7" *)
input Enable_i;
(* src = "../../verilog/adt7410.v:41" *)
wire [7:0] I2CFSM_Byte0_s;
(* src = "../../verilog/adt7410.v:42" *)
wire [7:0] I2CFSM_Byte1_s;
(* src = "../../verilog/adt7410.v:39" *)
wire I2CFSM_Done_s;
(* src = "../../verilog/adt7410.v:40" *)
wire I2CFSM_Error_s;
(* src = "../../verilog/adt7410.v:38" *)
wire I2CFSM_Start_s;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Busy" *)
(* src = "../../verilog/adt7410.v:17" *)
input I2C_Busy_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataOut" *)
(* src = "../../verilog/adt7410.v:25" *)
input [7:0] I2C_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataIn" *)
(* src = "../../verilog/adt7410.v:23" *)
output [7:0] I2C_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Error" *)
(* src = "../../verilog/adt7410.v:27" *)
input I2C_Error_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOReadNext" *)
(* src = "../../verilog/adt7410.v:19" *)
output I2C_FIFOReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOWrite" *)
(* src = "../../verilog/adt7410.v:21" *)
output I2C_FIFOWrite_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_ReadCount" *)
(* src = "../../verilog/adt7410.v:13" *)
output [7:0] I2C_ReadCount_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_ReceiveSend_n" *)
(* src = "../../verilog/adt7410.v:11" *)
output I2C_ReceiveSend_n_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_StartProcess" *)
(* src = "../../verilog/adt7410.v:15" *)
output I2C_StartProcess_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPreset_i" *)
(* src = "../../verilog/adt7410.v:29" *)
input [15:0] PeriodCounterPreset_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/adt7410.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/adt7410.v:31" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/adt7410.v:33" *)
input [15:0] Threshold_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPreset_i" *)
(* src = "../../verilog/adt7410.v:35" *)
input [15:0] WaitCounterPreset_i;
(* src = "../../verilog/adt7410.v:44" *)
I2CFSM I2CFSM_1 (
.Byte0_o(I2CFSM_Byte0_s),
.Byte1_o(I2CFSM_Byte1_s),
.Clk_i(Clk_i),
.Done_o(I2CFSM_Done_s),
.Error_o(I2CFSM_Error_s),
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_i(I2C_Data_i),
.I2C_Data_o(I2C_Data_o),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_o),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.ParamCounterPreset_i(WaitCounterPreset_i),
.Reset_n_i(Reset_n_i),
.Start_i(I2CFSM_Start_s)
);
(* src = "../../verilog/adt7410.v:70" *)
\$paramod\SensorFSM\DataWidth=8 SensorFSM_1 (
.Clk_i(Clk_i),
.CpuIntr_o(CpuIntr_o),
.Enable_i(Enable_i),
.MeasureFSM_Byte0_i(I2CFSM_Byte0_s),
.MeasureFSM_Byte1_i(I2CFSM_Byte1_s),
.MeasureFSM_Done_i(I2CFSM_Done_s),
.MeasureFSM_Error_i(I2CFSM_Error_s),
.MeasureFSM_Start_o(I2CFSM_Start_s),
.ParamCounterPreset_i(PeriodCounterPreset_i),
.ParamThreshold_i(Threshold_i),
.Reset_n_i(Reset_n_i),
.SensorValue_o(SensorValue_o)
);
endmodule
(* src = "../../verilog/i2cfsm.v:3" *)
module I2CFSM(Reset_n_i, Clk_i, Start_i, Done_o, Error_o, Byte0_o, Byte1_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, ParamCounterPreset_i);
(* src = "../../verilog/i2cfsm.v:240" *)
wire [7:0] \$0\Byte0_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:240" *)
wire [7:0] \$0\Byte1_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:270" *)
wire [15:0] \$0\I2C_FSM_Timer[15:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$2\I2C_FIFOReadNext_o[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$2\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$2\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$2\I2C_FSM_TimerPreset[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$3\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$4\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$4\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$5\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$6\I2C_FSM_NextState[3:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire [3:0] \$7\I2C_FSM_NextState[3:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2832 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2834 ;
wire \$procmux$1152_CMP ;
wire \$procmux$1153_CMP ;
wire \$procmux$1156_CMP ;
wire \$procmux$1157_CMP ;
wire \$procmux$1158_CMP ;
wire \$procmux$1161_CMP ;
wire \$procmux$1166_CMP ;
wire \$procmux$1167_CMP ;
wire \$procmux$1168_CMP ;
wire \$procmux$1169_CMP ;
wire \$procmux$1172_CMP ;
wire [15:0] \$procmux$803_Y ;
(* src = "../../verilog/i2cfsm.v:284" *)
wire [15:0] \$sub$../../verilog/i2cfsm.v:284$14_Y ;
(* src = "../../verilog/i2cfsm.v:10" *)
output [7:0] Byte0_o;
(* src = "../../verilog/i2cfsm.v:11" *)
output [7:0] Byte1_o;
(* src = "../../verilog/i2cfsm.v:5" *)
input Clk_i;
(* src = "../../verilog/i2cfsm.v:8" *)
output Done_o;
(* src = "../../verilog/i2cfsm.v:9" *)
output Error_o;
(* src = "../../verilog/i2cfsm.v:17" *)
input I2C_Busy_i;
(* src = "../../verilog/i2cfsm.v:22" *)
input [7:0] I2C_Data_i;
(* src = "../../verilog/i2cfsm.v:21" *)
output [7:0] I2C_Data_o;
(* src = "../../verilog/i2cfsm.v:24" *)
input I2C_Error_i;
(* src = "../../verilog/i2cfsm.v:19" *)
output I2C_FIFOReadNext_o;
(* src = "../../verilog/i2cfsm.v:20" *)
output I2C_FIFOWrite_o;
(* src = "../../verilog/i2cfsm.v:74" *)
wire [3:0] I2C_FSM_NextState;
(* src = "../../verilog/i2cfsm.v:73" *)
wire [3:0] I2C_FSM_State;
(* src = "../../verilog/i2cfsm.v:268" *)
wire [15:0] I2C_FSM_Timer;
(* src = "../../verilog/i2cfsm.v:77" *)
wire I2C_FSM_TimerEnable;
(* src = "../../verilog/i2cfsm.v:75" *)
wire I2C_FSM_TimerOvfl;
(* src = "../../verilog/i2cfsm.v:76" *)
wire I2C_FSM_TimerPreset;
(* src = "../../verilog/i2cfsm.v:79" *)
wire I2C_FSM_Wr0;
(* src = "../../verilog/i2cfsm.v:78" *)
wire I2C_FSM_Wr1;
(* src = "../../verilog/i2cfsm.v:15" *)
output [7:0] I2C_ReadCount_o;
(* src = "../../verilog/i2cfsm.v:14" *)
output I2C_ReceiveSend_n_o;
(* src = "../../verilog/i2cfsm.v:16" *)
output I2C_StartProcess_o;
(* src = "../../verilog/i2cfsm.v:26" *)
input [15:0] ParamCounterPreset_i;
(* src = "../../verilog/i2cfsm.v:4" *)
input Reset_n_i;
(* src = "../../verilog/i2cfsm.v:7" *)
input Start_i;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2827 (
.A({ \$procmux$1153_CMP , \$procmux$1152_CMP }),
.Y(I2C_ReceiveSend_n_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2831 (
.A({ \$procmux$1167_CMP , \$procmux$1157_CMP , \$procmux$1153_CMP }),
.Y(I2C_StartProcess_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2833 (
.A({ \$procmux$1172_CMP , \$procmux$1161_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2832 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2835 (
.A({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1158_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2834 )
);
(* src = "../../verilog/i2cfsm.v:289" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/i2cfsm.v:289$15 (
.A(I2C_FSM_Timer),
.B(16'b0000000000000000),
.Y(I2C_FSM_TimerOvfl)
);
(* src = "../../verilog/i2cfsm.v:240" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2819 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0_o[7:0] ),
.Q(Byte0_o)
);
(* src = "../../verilog/i2cfsm.v:240" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2820 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1_o[7:0] ),
.Q(Byte1_o)
);
(* src = "../../verilog/i2cfsm.v:270" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2821 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\I2C_FSM_Timer[15:0] ),
.Q(I2C_FSM_Timer)
);
(* src = "../../verilog/i2cfsm.v:85" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(4'b0000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000100)
) \$procdff$2822 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(I2C_FSM_NextState),
.Q(I2C_FSM_State)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1148_CMP0 (
.A(I2C_FSM_State),
.B(4'b1100),
.Y(Done_o)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1149_CMP0 (
.A(I2C_FSM_State),
.B(4'b1011),
.Y(I2C_FSM_Wr0)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1152_CMP0 (
.A(I2C_FSM_State),
.B(4'b1010),
.Y(\$procmux$1152_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1153_CMP0 (
.A(I2C_FSM_State),
.B(4'b1001),
.Y(\$procmux$1153_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1156_CMP0 (
.A(I2C_FSM_State),
.B(4'b1000),
.Y(\$procmux$1156_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1157_CMP0 (
.A(I2C_FSM_State),
.B(4'b0111),
.Y(\$procmux$1157_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1158_CMP0 (
.A(I2C_FSM_State),
.B(4'b0110),
.Y(\$procmux$1158_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1161_CMP0 (
.A(I2C_FSM_State),
.B(4'b0101),
.Y(\$procmux$1161_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1166_CMP0 (
.A(I2C_FSM_State),
.B(4'b0100),
.Y(\$procmux$1166_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1167_CMP0 (
.A(I2C_FSM_State),
.B(4'b0011),
.Y(\$procmux$1167_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1168_CMP0 (
.A(I2C_FSM_State),
.B(4'b0010),
.Y(\$procmux$1168_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1169_CMP0 (
.A(I2C_FSM_State),
.B(4'b0001),
.Y(\$procmux$1169_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1172_CMP0 (
.A(I2C_FSM_State),
.B(4'b0000),
.Y(\$procmux$1172_CMP )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1192 (
.A(\$procmux$1166_CMP ),
.B(I2C_Error_i),
.Y(Error_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1202 (
.A(1'b0),
.B({ \$2\I2C_FIFOReadNext_o[0:0] , 1'b1 }),
.S({ \$procmux$1152_CMP , I2C_FSM_Wr0 }),
.Y(I2C_FIFOReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1241 (
.A(1'b0),
.B({ \$2\I2C_FSM_TimerEnable[0:0] , \$4\I2C_FSM_TimerEnable[0:0] }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1268 (
.A(1'b1),
.B({ \$2\I2C_FSM_TimerPreset[0:0] , I2C_FSM_TimerOvfl }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerPreset)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1313 (
.A(\$procmux$1152_CMP ),
.B(\$2\I2C_FIFOReadNext_o[0:0] ),
.Y(I2C_FSM_Wr1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1340 (
.A(8'b00000000),
.B(8'b00000010),
.S(I2C_ReceiveSend_n_o),
.Y(I2C_ReadCount_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1425 (
.A(8'b00000000),
.B(52465809),
.S({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$auto$opt_reduce.cc:126:opt_mux$2832 , \$procmux$1156_CMP }),
.Y(I2C_Data_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1452 (
.A(1'b0),
.B({ Start_i, I2C_FSM_TimerOvfl, 1'b1, \$2\I2C_FIFOReadNext_o[0:0] }),
.S({ \$procmux$1172_CMP , \$procmux$1161_CMP , \$auto$opt_reduce.cc:126:opt_mux$2834 , \$procmux$1156_CMP }),
.Y(I2C_FIFOWrite_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000001101),
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1471 (
.A(I2C_FSM_State),
.B({ \$2\I2C_FSM_NextState[3:0] , 12'b001000110100, \$3\I2C_FSM_NextState[3:0] , \$5\I2C_FSM_NextState[3:0] , 8'b01111000, \$6\I2C_FSM_NextState[3:0] , 4'b1010, \$7\I2C_FSM_NextState[3:0] , 8'b11000000 }),
.S({ \$procmux$1172_CMP , \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1167_CMP , \$procmux$1166_CMP , \$procmux$1161_CMP , \$procmux$1158_CMP , \$procmux$1157_CMP , \$procmux$1156_CMP , \$procmux$1153_CMP , \$procmux$1152_CMP , I2C_FSM_Wr0, Done_o }),
.Y(I2C_FSM_NextState)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1521 (
.A(I2C_FSM_State),
.B(4'b0001),
.S(Start_i),
.Y(\$2\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1598 (
.A(\$2\I2C_FIFOReadNext_o[0:0] ),
.B(1'b0),
.S(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerEnable[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1626 (
.A(I2C_Busy_i),
.B(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1654 (
.A(\$4\I2C_FSM_NextState[3:0] ),
.B(4'b0000),
.S(I2C_Error_i),
.Y(\$3\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1708 (
.A(4'b0101),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$4\I2C_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1766 (
.A(I2C_Busy_i),
.Y(\$2\I2C_FIFOReadNext_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1820 (
.A(I2C_FSM_State),
.B(4'b0110),
.S(I2C_FSM_TimerOvfl),
.Y(\$5\I2C_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1876 (
.A(I2C_FSM_TimerOvfl),
.Y(\$4\I2C_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$1926 (
.A(4'b1001),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$6\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$2005 (
.A(4'b1011),
.B(I2C_FSM_State),
.S(I2C_Busy_i),
.Y(\$7\I2C_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$793 (
.A(Byte0_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr0),
.Y(\$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$800 (
.A(Byte1_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr1),
.Y(\$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$803 (
.A(I2C_FSM_Timer),
.B(\$sub$../../verilog/i2cfsm.v:284$14_Y ),
.S(I2C_FSM_TimerEnable),
.Y(\$procmux$803_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$806 (
.A(\$procmux$803_Y ),
.B(ParamCounterPreset_i),
.S(I2C_FSM_TimerPreset),
.Y(\$0\I2C_FSM_Timer[15:0] )
);
(* src = "../../verilog/i2cfsm.v:284" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/i2cfsm.v:284$14 (
.A(I2C_FSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/i2cfsm.v:284$14_Y )
);
endmodule
|
`timescale 1ns/1ps
`include "cpu_constants.vh"
module dma_controller(
input clk,
input rst,
input en,
output dma_status,
input [15:0] addr,
input [15:0] data_in,
input write_enable,
output reg [15:0] ram_addr,
output reg [15:0] ram_data_out,
output reg ram_we,
input [15:0] ram_data_in,
output reg [23:0] dram_addr,
output reg [31:0] dram_data_out,
output reg dram_req_read,
output reg dram_req_write,
input [31:0] dram_data_in,
input dram_data_valid,
input dram_write_complete
);
reg [2:0] dma_type = 0;
reg dma_in_progress = 0;
reg [15:0] local_addr = 0;
reg [23:0] remote_addr = 0;
reg [15:0] count = 2;
assign dma_status = dma_in_progress;
localparam STATE_BITS = 6;
localparam // auto enum dma_state
STATE_NOP = 6'b111111,
STATE_DRAM_WRITE = 6'b000000,
STATE_DRAM_READ = 6'b000001,
STATE_RESERVED = 6'b000111,
//write
STATE_DW_READ_LOW = 6'b001000,
STATE_DW_READ_HIGH = 6'b010000,
STATE_DW_WRITE_RAM = 6'b011000,
//read
STATE_DR_READ = 6'b001001,
STATE_DR_WRITE_LOW = 6'b010001,
STATE_DR_WRITE_HIGH = 6'b011001;
reg // auto enum dma_state
[STATE_BITS-1:0] state = STATE_NOP;
reg [31:0] ram_data = 0;
//configuration process
always @(posedge clk) begin
ram_addr <= local_addr;
if(rst == 1) begin
state <= STATE_NOP;
dma_in_progress <= 0;
ram_data_out <= 0;
ram_we <= 0;
dram_addr <= 0;
dram_data_out <= 0;
dram_req_read <= 0;
dram_req_write <= 0;
ram_data <= 0;
end
else if(en == 1 && write_enable == 1)
case({addr[14:0],1'b0})
`DMA_CONTROL_ADDR: begin
dma_type <= data_in[2:0];
dma_in_progress <= 1;
end
`DMA_LOCAL_ADDR: begin
local_addr <= data_in>>1;
end
`DMA_PERIPH_ADDR:
remote_addr <= {data_in,8'b0};
`DMA_COUNT_ADDR:
count <= data_in >> 2;
endcase
else
case(state)
STATE_DRAM_WRITE: begin
local_addr <= local_addr + 1;
ram_addr <= local_addr + 1;
state <= STATE_DW_READ_LOW;
end
STATE_DW_READ_LOW:begin
ram_data[15:0] <= ram_data_in;
local_addr <= local_addr + 1;
ram_addr <= local_addr + 1;
count <= count - 1;
state <= STATE_DW_READ_HIGH;
end
STATE_DW_READ_HIGH: begin
ram_data[31:16] <= ram_data_in;
dram_addr <= remote_addr;
remote_addr <= remote_addr + 2;
dram_req_write <= 1'b1;
dram_data_out[15:0] <= ram_data[15:0];
dram_data_out[31:16] <= ram_data_in;
state <= STATE_DW_WRITE_RAM;
end
STATE_DW_WRITE_RAM:
if(dram_write_complete == 1) begin
dram_req_write <= 1'b0;
if(count == 0) begin
state <= STATE_NOP;
dma_in_progress <= 0;
end
else begin
state <= STATE_DRAM_WRITE;
end
end
STATE_DRAM_READ: begin
ram_we <= 0;
dram_addr <= remote_addr;
dram_req_read <= 1;
remote_addr <= remote_addr + 2;
count <= count - 1;
state <= STATE_DR_READ;
end
STATE_DR_READ:begin
dram_req_read <= 0;
if(dram_data_valid == 1)begin
dram_req_read <= 0;
state <= STATE_DR_WRITE_LOW;
end
end
STATE_DR_WRITE_LOW:begin
local_addr <= local_addr + 1;
ram_we <= 1;
ram_data_out <= dram_data_in[15:0];
state <= STATE_DR_WRITE_HIGH;
end
STATE_DR_WRITE_HIGH:begin
local_addr <= local_addr + 1;
ram_data_out <=dram_data_in[31:16];
if(count == 0) begin
state <= STATE_NOP;
dma_in_progress <= 0;
end
else
state <= STATE_DRAM_READ;
end
STATE_NOP:begin
ram_we <= 0;
if(dma_in_progress)
state <= {2'b0,dma_type};
end
endcase
end
/*AUTOASCIIENUM("state", "state_ascii")*/
// Beginning of automatic ASCII enum decoding
reg [151:0] state_ascii; // Decode of state
always @(state) begin
case ({state})
STATE_NOP: state_ascii = "state_nop ";
STATE_DRAM_WRITE: state_ascii = "state_dram_write ";
STATE_DRAM_READ: state_ascii = "state_dram_read ";
STATE_RESERVED: state_ascii = "state_reserved ";
STATE_DW_READ_LOW: state_ascii = "state_dw_read_low ";
STATE_DW_READ_HIGH: state_ascii = "state_dw_read_high ";
STATE_DW_WRITE_RAM: state_ascii = "state_dw_write_ram ";
STATE_DR_READ: state_ascii = "state_dr_read ";
STATE_DR_WRITE_LOW: state_ascii = "state_dr_write_low ";
STATE_DR_WRITE_HIGH: state_ascii = "state_dr_write_high";
default: state_ascii = "%Error ";
endcase
end
// End of automatics
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_LP_V
`define SKY130_FD_SC_LP__A32O_LP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_LP_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sub_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// PentEvo project (c) NedoPC 2012
//
// SPI hub: arbitrating between AVR and Z80 accesses to SDcard via SPI.
`include "../include/tune.v"
module spihub(
input wire fclk,
input wire rst_n,
// pins to SDcard
output reg sdcs_n,
output wire sdclk,
output wire sddo,
input wire sddi,
// zports SDcard iface
input wire zx_sdcs_n_val,
input wire zx_sdcs_n_stb,
input wire zx_sd_start,
input wire [7:0] zx_sd_datain,
output wire [7:0] zx_sd_dataout,
// slavespi SDcard iface
input wire avr_lock_in,
output reg avr_lock_out,
input wire avr_sdcs_n,
input wire avr_sd_start,
input wire [7:0] avr_sd_datain,
output wire [7:0] avr_sd_dataout
);
// spi2 module control
wire [7:0] sd_datain;
wire [7:0] sd_dataout;
wire sd_start;
// single dataout to all ifaces
assign zx_sd_dataout = sd_dataout;
assign avr_sd_dataout = sd_dataout;
// spi2 module itself
spi2 spi2(
.clock(fclk),
.sck(sdclk),
.sdo(sddo ),
.sdi(sddi ),
.start(sd_start ),
.din (sd_datain ),
.dout (sd_dataout),
.speed(2'b00)
);
// control locking/arbitrating between ifaces
always @(posedge fclk, negedge rst_n)
if( !rst_n )
avr_lock_out <= 1'b0;
else // posedge fclk
begin
if( sdcs_n )
avr_lock_out <= avr_lock_in;
end
// control cs_n to SDcard
always @(posedge fclk, negedge rst_n)
if( !rst_n )
sdcs_n <= 1'b1;
else // posedge fclk
begin
if( avr_lock_out )
sdcs_n <= avr_sdcs_n;
else // !avr_lock_out
if( zx_sdcs_n_stb )
sdcs_n <= zx_sdcs_n_val;
end
// control start and outgoing data to spi2
assign sd_start = avr_lock_out ? avr_sd_start : zx_sd_start;
//
assign sd_datain = avr_lock_out ? avr_sd_datain : zx_sd_datain;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_TB_V
`define SKY130_FD_SC_HVL__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_TB_V
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Jul 11 2017
//Description: MBus Member Controller
// Structural verilog netlist using stdcell_dgh_tps65
//Update History: Jul 11 2017 - First created for MBus r04p2
//*******************************************************************************************
module lname_mbus_member_ctrl (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output COUT,
output DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output MBC_ISOLATE,
output MBC_ISOLATE_B,
output MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [3:0] ADDR_IN,
output [3:0] ADDR_OUT,
output ADDR_VALID,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// Internal Wire Declaration
//****************************************************************************
wire cin_b;
wire cin_buf;
wire mbc_sleep_b_int;
wire mbc_isolate_b_int;
wire mbc_reset_b_int;
wire next_mbc_isolate;
wire next_mbc_isolate_b;
wire sleep_req_isol;
wire sleep_req_b_isol;
wire mbc_isolate_int;
wire mbc_sleep_int;
wire goingsleep;
wire mbc_reset_int;
wire clr_ext_int_iso;
wire clr_ext_int_b;
wire RESETn_local;
wire RESETn_local2;
wire mbus_busy_b_isol;
wire int_busy;
wire int_busy_b;
wire ext_int_dout;
wire cout_from_bus_iso;
wire cout_int;
wire cout_unbuf;
wire dout_from_bus_iso;
wire dout_int_1;
wire dout_int_0;
wire dout_unbuf;
wire addr_clr_b_iso;
wire [3:0] addr_in_iso;
wire RESETn_local3;
wire addr_update;
// ---------------------------------------------
// NOTE: Functional Relationship:
// ---------------------------------------------
// MBC_ISOLATE = mbc_isolate_int
// MBC_ISOLATE_B = mbc_isolate_b_int
// MBC_RESET = mbc_reset_int
// MBC_RESET_B = mbc_reset_b_int
// MBC_SLEEP = mbc_sleep_int
// MBC_SLEEP_B = mbc_sleep_b_int
// ---------------------------------------------
// clr_ext_int_b = ~clr_ext_int_iso
// ---------------------------------------------
//****************************************************************************
// GLOBAL
//****************************************************************************
// CIN Buffer
INVX1DG_TJ65IOH INV_cin_b (.Y(cin_b), .A(CIN));
INVX2DG_TJ65IOH INV_cin_buf (.Y(cin_buf), .A(cin_b));
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
//assign MBC_SLEEP_B = ~MBC_SLEEP;
INVX1DG_TJ65IOH INV_mbc_sleep_b_int (.Y(mbc_sleep_b_int), .A(mbc_sleep_int));
INVX8DG_TJ65IOH INV_MBC_SLEEP (.Y(MBC_SLEEP), .A(mbc_sleep_b_int));
INVX8DG_TJ65IOH INV_MBC_SLEEP_B (.Y(MBC_SLEEP_B), .A(mbc_sleep_int));
//assign MBC_ISOLATE_B = ~MBC_ISOLATE;
INVX1DG_TJ65IOH INV_mbc_isolate_b_int (.Y(mbc_isolate_b_int), .A(mbc_isolate_int));
INVX8DG_TJ65IOH INV_MBC_ISOLATE (.Y(MBC_ISOLATE), .A(mbc_isolate_b_int));
INVX8DG_TJ65IOH INV_MBC_ISOLATE_B (.Y(MBC_ISOLATE_B), .A(mbc_isolate_int));
//assign MBC_RESET_B = ~MBC_RESET;
INVX1DG_TJ65IOH INV_mbc_reset_b_int (.Y(mbc_reset_b_int), .A(mbc_reset_int));
INVX8DG_TJ65IOH INV_MBC_RESET (.Y(MBC_RESET), .A(mbc_reset_b_int));
INVX8DG_TJ65IOH INV_MBC_RESET_B (.Y(MBC_RESET_B), .A(mbc_reset_int));
//assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
INVX1DG_TJ65IOH INV_next_mbc_isolate (.Y(next_mbc_isolate), .A(next_mbc_isolate_b));
NOR3X1DG_TJ65IOH NOR3_next_mbc_isolate_b (.C(goingsleep), .B(sleep_req_isol), .A(mbc_sleep_int), .Y(next_mbc_isolate_b));
//assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
INVX1DG_TJ65IOH INV_next_goingsleep (.Y(sleep_req_isol), .A(sleep_req_b_isol));
NAND2X1DG_TJ65IOH NAND2_next_goingsleep_b (.Y(sleep_req_b_isol), .A(SLEEP_REQ), .B(mbc_isolate_b_int));
// goingsleep, mbc_sleep_int, mbc_isolate_int, mbc_reset_int
DFFSRX1DG_TJ65IOH DFFSR_mbc_isolate_int (.SN(RESETn), .RN(1'b1), .CK(cin_buf), .Q(mbc_isolate_int), .QN(), .D(next_mbc_isolate));
DFFSRX1DG_TJ65IOH DFFSR_mbc_sleep_int (.SN(RESETn), .RN(1'b1), .CK(cin_buf), .Q(mbc_sleep_int), .QN(), .D(goingsleep));
DFFSRX1DG_TJ65IOH DFFSR_goingsleep (.SN(1'b1), .RN(RESETn), .CK(cin_buf), .Q(goingsleep), .QN(), .D(sleep_req_isol));
DFFSRX1DG_TJ65IOH DFFSR_mbc_reset_int (.SN(RESETn), .RN(1'b1), .CK(cin_b), .Q(mbc_reset_int), .QN(), .D(mbc_isolate_int));
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
//wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
AND2X1DG_TJ65IOH AND2_clr_ext_int_iso (.Y(clr_ext_int_iso), .A(MBC_ISOLATE_B), .B(CLR_EXT_INT));
INVX1DG_TJ65IOH INV_clr_ext_int_b (.Y(clr_ext_int_b), .A(clr_ext_int_iso));
//wire RESETn_local = RESETn & CIN;
AND2X1DG_TJ65IOH AND2_RESETn_local (.Y(RESETn_local), .A(CIN), .B(RESETn));
//wire RESETn_local2 = RESETn & clr_ext_int_b;
AND2X1DG_TJ65IOH AND2_RESETn_local2 (.Y(RESETn_local2), .A(clr_ext_int_b), .B(RESETn));
//wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
NAND2X1DG_TJ65IOH NAND2_mbus_busy_b_isol (.A(MBUS_BUSY), .B(mbc_reset_b_int), .Y(mbus_busy_b_isol));
//wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP)
NAND3X1DG_TJ65IOH NAND3_int_busy_b (.A(WAKEUP_REQ), .B(mbus_busy_b_isol), .C(LRC_SLEEP), .Y(int_busy_b));
INVX2DG_TJ65IOH INV_int_busy (.Y(int_busy), .A(int_busy_b));
// ext_int_dout
DFFRX1DG_TJ65IOH DFFR_ext_int_dout (.RN(RESETn_local), .CK(int_busy), .Q(ext_int_dout), .QN(), .D(1'b1));
// EXTERNAL_INT
DFFRX1DG_TJ65IOH DFFR_EXTERNAL_INT (.RN(RESETn_local2), .CK(int_busy), .Q(EXTERNAL_INT), .QN(), .D(1'b1));
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
// COUT
OR2X1DG_TJ65IOH OR2_cout_from_bus_iso (.Y(cout_from_bus_iso), .A(COUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1DG_TJ65IOH MUX2_cout_int (.S(MBC_ISOLATE), .A(cout_from_bus_iso), .Y(cout_int), .B(CIN));
MUX2X1DG_TJ65IOH MUX2_cout_unbuf (.S(RESETn), .A(1'b1), .Y(cout_unbuf), .B(cout_int));
BUFX4DG_TJ65IOH BUF_COUT (.A(cout_unbuf), .Y(COUT));
// DOUT
OR2X1DG_TJ65IOH OR2_dout_from_bus_iso (.Y(dout_from_bus_iso), .A(DOUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1DG_TJ65IOH MUX2_dout_int_1 (.S(MBC_ISOLATE), .A(dout_from_bus_iso), .Y(dout_int_1), .B(DIN));
MUX2X1DG_TJ65IOH MUX2_dout_int_0 (.S(ext_int_dout), .A(dout_int_1), .Y(dout_int_0), .B(1'b0));
MUX2X1DG_TJ65IOH MUX2_dout_unbuf (.S(RESETn), .A(1'b1), .Y(dout_unbuf), .B(dout_int_0));
BUFX4DG_TJ65IOH BUF_DOUT (.A(dout_unbuf), .Y(DOUT));
//****************************************************************************
// SHORT-PREFIX ADDRESS REGISTER
//****************************************************************************
// Isolation
OR2X1DG_TJ65IOH AND2_addr_clr_b_iso (.A(MBC_ISOLATE), .B(ADDR_CLR_B), .Y(addr_clr_b_iso));
AND2X1DG_TJ65IOH AND2_addr_in_iso_0 (.A(MBC_ISOLATE_B), .B(ADDR_IN[0]), .Y(addr_in_iso[0]));
AND2X1DG_TJ65IOH AND2_addr_in_iso_1 (.A(MBC_ISOLATE_B), .B(ADDR_IN[1]), .Y(addr_in_iso[1]));
AND2X1DG_TJ65IOH AND2_addr_in_iso_2 (.A(MBC_ISOLATE_B), .B(ADDR_IN[2]), .Y(addr_in_iso[2]));
AND2X1DG_TJ65IOH AND2_addr_in_iso_3 (.A(MBC_ISOLATE_B), .B(ADDR_IN[3]), .Y(addr_in_iso[3]));
//wire RESETn_local3 = (RESETn & ADDR_CLR_B);
AND2X1DG_TJ65IOH AND2_RESETn_local3 (.A(RESETn), .B(addr_clr_b_iso), .Y(RESETn_local3));
//wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
AND2X1DG_TJ65IOH AND2_addr_update (.A(MBC_ISOLATE_B), .B(ADDR_WR_EN), .Y(addr_update));
// ADDR_OUT, ADDR_VALID
DFFSX1DG_TJ65IOH DFFS_ADDR_OUT_0 (.CK(addr_update), .D(addr_in_iso[0]), .SN(RESETn_local3), .Q(ADDR_OUT[0]), .QN());
DFFSX1DG_TJ65IOH DFFS_ADDR_OUT_1 (.CK(addr_update), .D(addr_in_iso[1]), .SN(RESETn_local3), .Q(ADDR_OUT[1]), .QN());
DFFSX1DG_TJ65IOH DFFS_ADDR_OUT_2 (.CK(addr_update), .D(addr_in_iso[2]), .SN(RESETn_local3), .Q(ADDR_OUT[2]), .QN());
DFFSX1DG_TJ65IOH DFFS_ADDR_OUT_3 (.CK(addr_update), .D(addr_in_iso[3]), .SN(RESETn_local3), .Q(ADDR_OUT[3]), .QN());
DFFRX1DG_TJ65IOH DFFR_ADDR_VALID (.CK(addr_update), .D(1'b1), .RN(RESETn_local3), .Q(ADDR_VALID), .QN());
endmodule // lname_mbus_member_ctrl
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_PP_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlygate4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_TB_V
`define SKY130_FD_SC_LP__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_TB_V
|
/*
########################################################################
ELINK TX CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module etx_cfg (/*AUTOARG*/
// Outputs
mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,
gpio_data, ctrlmode, ctrlmode_bypass,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter PW = 104;
parameter RFAW = 6;
parameter DEFAULT_VERSION = 16'h0000;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset;
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr; // complete address (no shifting!)
input [31:0] mi_din; // (lower 2 bits not used)
output [31:0] mi_dout;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//tx (static configs)
output tx_enable; // enable signal for TX
output mmu_enable; // enables MMU on transmit path
output gpio_enable; // forces TX output pins to constants
output remap_enable; // enable address remapping
input [15:0] tx_status; // etx status signals
//sampled by tx_lclk (test)
output [8:0] gpio_data; // data for elink outputs (static)
//dynamic (control timing by use mode)
output [3:0] ctrlmode; // value for emesh ctrlmode tag
output ctrlmode_bypass; // selects ctrlmode
//registers
reg [15:0] ecfg_version_reg;
reg [10:0] ecfg_tx_config_reg;
reg [8:0] ecfg_tx_gpio_reg;
reg [2:0] ecfg_tx_status_reg;
reg [31:0] mi_dout;
reg ecfg_access;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_tx_config_write;
wire ecfg_tx_gpio_write;
wire ecfg_tx_test_write;
wire ecfg_tx_addr_write;
wire ecfg_tx_data_write;
wire loop_mode;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_version_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_VERSION);
assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_CFG);
assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_STATUS);
assign ecfg_tx_gpio_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_GPIO);
//###########################
//# TX CONFIG
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_config_reg[10:0] <= 11'b0;
else if (ecfg_tx_config_write)
ecfg_tx_config_reg[10:0] <= mi_din[10:0];
assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
assign mmu_enable = ecfg_tx_config_reg[1];
assign remap_enable = ecfg_tx_config_reg[3:2]==2'b01;
assign ctrlmode[3:0] = ecfg_tx_config_reg[7:4];
assign ctrlmode_bypass = ecfg_tx_config_reg[8];
assign gpio_enable = (ecfg_tx_config_reg[10:9]==2'b01);
//###########################
//# STATUS REGISTER
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_status_reg[2:0] <= 'd0;
else
ecfg_tx_status_reg[2:0]<= ecfg_tx_status_reg[2:0] | tx_status[2:0];
//###########################
//# GPIO DATA
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_gpio_reg[8:0] <= 'd0;
else if (ecfg_tx_gpio_write)
ecfg_tx_gpio_reg[8:0] <= mi_din[8:0];
assign gpio_data[8:0] = ecfg_tx_gpio_reg[8:0];
//###########################
//# VERSION
//###########################
always @ (posedge clk)
if(reset)
ecfg_version_reg[15:0] <= DEFAULT_VERSION;
else if (ecfg_version_write)
ecfg_version_reg[15:0] <= mi_din[15:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ETX_CFG: mi_dout[31:0] <= {21'b0, ecfg_tx_config_reg[10:0]};
`ETX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_tx_gpio_reg[8:0]};
`ETX_STATUS: mi_dout[31:0] <= {16'b0, tx_status[15:3],ecfg_tx_status_reg[2:0]};
`E_VERSION: mi_dout[31:0] <= {16'b0, ecfg_version_reg[15:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_tx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
module ram(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end // always @ (posedge clk)
endmodule // ram
module dram_256x16(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [DATA_WIDTH - 1 :0] mask,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 16;
localparam ADDR_WIDTH = 8;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
assign _d = d;
assign q = _q;
dram_#(
.MODE(0)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_256x16
module dram_512x8(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 9;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = d[i];
assign q[i] = _q[i * 2];
end
endgenerate
dram_#(
.MODE(1)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_256x16
module dram_1024x4(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 4;
localparam ADDR_WIDTH = 10;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = d[i];
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
assign q[i] = _q[i * 4 + 1];
end
endgenerate
dram_#(
.MODE(2)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_1024x4
module dram_2048x2(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 2;
localparam ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = waddr;
assign _raddr = raddr;
genvar i;
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = d[i];
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
assign q[i] = _q[i * 8 + 3];
end
dram_#(
.MODE(3)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_2048x2
module dram_(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [RAM_ADDR_WIDTH - 1 : 0] waddr,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
input [RAM_ADDR_WIDTH - 1 : 0] raddr,
output [RAM_DATA_WIDTH - 1 : 0] q
);
parameter MODE = -1;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(raddr),
.RCLK(r_clk),
.RCLKE(r_clk_en),
.RE(re),
.WADDR(waddr),
.WCLK(w_clk),
.WCLKE(w_clk_en),
.WDATA(d),
.WE(we),
.MASK(mask)
);
endmodule // dram_
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:51:52 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_A_S, intAS,
sign_final_result, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, DP_OP_42J154_122_8302_n26, DP_OP_42J154_122_8302_n25,
DP_OP_42J154_122_8302_n24, DP_OP_42J154_122_8302_n23,
DP_OP_42J154_122_8302_n22, DP_OP_42J154_122_8302_n21,
DP_OP_42J154_122_8302_n20, DP_OP_42J154_122_8302_n19,
DP_OP_42J154_122_8302_n18, DP_OP_42J154_122_8302_n17,
DP_OP_42J154_122_8302_n16, DP_OP_42J154_122_8302_n11,
DP_OP_42J154_122_8302_n10, DP_OP_42J154_122_8302_n9,
DP_OP_42J154_122_8302_n8, DP_OP_42J154_122_8302_n7,
DP_OP_42J154_122_8302_n6, DP_OP_42J154_122_8302_n5,
DP_OP_42J154_122_8302_n4, DP_OP_42J154_122_8302_n3,
DP_OP_42J154_122_8302_n2, DP_OP_42J154_122_8302_n1,
DP_OP_45J154_125_8406_n114, DP_OP_45J154_125_8406_n113,
DP_OP_45J154_125_8406_n112, DP_OP_45J154_125_8406_n111,
DP_OP_45J154_125_8406_n110, DP_OP_45J154_125_8406_n109,
DP_OP_45J154_125_8406_n108, DP_OP_45J154_125_8406_n107,
DP_OP_45J154_125_8406_n106, DP_OP_45J154_125_8406_n105,
DP_OP_45J154_125_8406_n104, DP_OP_45J154_125_8406_n103,
DP_OP_45J154_125_8406_n102, DP_OP_45J154_125_8406_n101,
DP_OP_45J154_125_8406_n100, DP_OP_45J154_125_8406_n99,
DP_OP_45J154_125_8406_n98, DP_OP_45J154_125_8406_n97,
DP_OP_45J154_125_8406_n96, DP_OP_45J154_125_8406_n95,
DP_OP_45J154_125_8406_n94, DP_OP_45J154_125_8406_n93,
DP_OP_45J154_125_8406_n92, DP_OP_45J154_125_8406_n91,
DP_OP_45J154_125_8406_n90, DP_OP_45J154_125_8406_n89,
DP_OP_45J154_125_8406_n88, DP_OP_45J154_125_8406_n87,
DP_OP_45J154_125_8406_n86, DP_OP_45J154_125_8406_n85,
DP_OP_45J154_125_8406_n84, DP_OP_45J154_125_8406_n83,
DP_OP_45J154_125_8406_n82, DP_OP_45J154_125_8406_n81,
DP_OP_45J154_125_8406_n80, DP_OP_45J154_125_8406_n79,
DP_OP_45J154_125_8406_n78, DP_OP_45J154_125_8406_n77,
DP_OP_45J154_125_8406_n76, DP_OP_45J154_125_8406_n75,
DP_OP_45J154_125_8406_n74, DP_OP_45J154_125_8406_n73,
DP_OP_45J154_125_8406_n72, DP_OP_45J154_125_8406_n71,
DP_OP_45J154_125_8406_n70, DP_OP_45J154_125_8406_n69,
DP_OP_45J154_125_8406_n68, DP_OP_45J154_125_8406_n67,
DP_OP_45J154_125_8406_n66, DP_OP_45J154_125_8406_n65,
DP_OP_45J154_125_8406_n64, DP_OP_45J154_125_8406_n63,
DP_OP_45J154_125_8406_n62, DP_OP_45J154_125_8406_n61,
DP_OP_45J154_125_8406_n60, DP_OP_45J154_125_8406_n55,
DP_OP_45J154_125_8406_n54, DP_OP_45J154_125_8406_n53,
DP_OP_45J154_125_8406_n52, DP_OP_45J154_125_8406_n51,
DP_OP_45J154_125_8406_n50, DP_OP_45J154_125_8406_n49,
DP_OP_45J154_125_8406_n48, DP_OP_45J154_125_8406_n47,
DP_OP_45J154_125_8406_n46, DP_OP_45J154_125_8406_n45,
DP_OP_45J154_125_8406_n44, DP_OP_45J154_125_8406_n43,
DP_OP_45J154_125_8406_n42, DP_OP_45J154_125_8406_n41,
DP_OP_45J154_125_8406_n40, DP_OP_45J154_125_8406_n39,
DP_OP_45J154_125_8406_n38, DP_OP_45J154_125_8406_n37,
DP_OP_45J154_125_8406_n36, DP_OP_45J154_125_8406_n35,
DP_OP_45J154_125_8406_n34, DP_OP_45J154_125_8406_n33,
DP_OP_45J154_125_8406_n32, DP_OP_45J154_125_8406_n31,
DP_OP_45J154_125_8406_n30, DP_OP_45J154_125_8406_n29,
DP_OP_45J154_125_8406_n28, DP_OP_45J154_125_8406_n27,
DP_OP_45J154_125_8406_n26, DP_OP_45J154_125_8406_n25,
DP_OP_45J154_125_8406_n24, DP_OP_45J154_125_8406_n23,
DP_OP_45J154_125_8406_n22, DP_OP_45J154_125_8406_n21,
DP_OP_45J154_125_8406_n20, DP_OP_45J154_125_8406_n19,
DP_OP_45J154_125_8406_n18, DP_OP_45J154_125_8406_n17,
DP_OP_45J154_125_8406_n16, DP_OP_45J154_125_8406_n15,
DP_OP_45J154_125_8406_n14, DP_OP_45J154_125_8406_n13,
DP_OP_45J154_125_8406_n12, DP_OP_45J154_125_8406_n11,
DP_OP_45J154_125_8406_n10, DP_OP_45J154_125_8406_n9,
DP_OP_45J154_125_8406_n8, DP_OP_45J154_125_8406_n7,
DP_OP_45J154_125_8406_n6, DP_OP_45J154_125_8406_n5,
DP_OP_45J154_125_8406_n4, DP_OP_45J154_125_8406_n3,
DP_OP_45J154_125_8406_n2, DP_OP_45J154_125_8406_n1, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1584, n1585, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [10:0] S_Oper_A_exp;
wire [4:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [54:0] S_A_S_Oper_A;
wire [3:0] FS_Module_state_reg;
wire [10:0] Exp_Operation_Module_Data_S;
wire [54:0] Add_Subt_Sgf_module_S_to_D;
wire [93:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(n1530), .CK(clk),
.RN(n3069), .QN(n1596) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1508), .CK(clk),
.RN(n3065), .QN(n1609) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n1500), .CK(
clk), .RN(n3061), .QN(n1603) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n1498), .CK(
clk), .RN(n3061), .QN(n1589) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n1496), .CK(
clk), .RN(n3064), .QN(n1608) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1436), .CK(clk),
.RN(n3061), .QN(n1606) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3047),
.QN(n1594) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3047),
.QN(n1614) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n1627),
.QN(n1613) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n1627),
.QN(n1611) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n1627),
.QN(n1615) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n1627),
.QN(n1610) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1627),
.QN(n1612) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1627),
.QN(n1616) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1627),
.QN(n1623) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1627),
.QN(n1622) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1627),
.QN(n1620) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1627),
.QN(n1618) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1627),
.QN(n1621) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1627),
.QN(n1619) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3063),
.QN(n1617) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3048),
.QN(n1624) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3048),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1426), .CK(clk), .RN(
n3050), .Q(underflow_flag) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n1425),
.CK(clk), .RN(n3050), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n1424),
.CK(clk), .RN(n3050), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n1423),
.CK(clk), .RN(n3050), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n1422),
.CK(clk), .RN(n3050), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n1421),
.CK(clk), .RN(n3050), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n1420),
.CK(clk), .RN(n3050), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n1419),
.CK(clk), .RN(n3050), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n1418),
.CK(clk), .RN(n3050), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n1417),
.CK(clk), .RN(n3050), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n1416),
.CK(clk), .RN(n3050), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n1415),
.CK(clk), .RN(n1685), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1414),
.CK(clk), .RN(n1685), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1413),
.CK(clk), .RN(n3051), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1412),
.CK(clk), .RN(n1580), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1411),
.CK(clk), .RN(n1580), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1410),
.CK(clk), .RN(n3051), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1409),
.CK(clk), .RN(n3051), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1408),
.CK(clk), .RN(n1685), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1407),
.CK(clk), .RN(n1580), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1406),
.CK(clk), .RN(n1580), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1405),
.CK(clk), .RN(n3055), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n1404),
.CK(clk), .RN(n1685), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n1403),
.CK(clk), .RN(n1628), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n1402),
.CK(clk), .RN(n1628), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n1401),
.CK(clk), .RN(n1628), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n1400),
.CK(clk), .RN(n1628), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n1399),
.CK(clk), .RN(n1628), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n1398),
.CK(clk), .RN(n1628), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n1397),
.CK(clk), .RN(n1628), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n1396),
.CK(clk), .RN(n1628), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n1395),
.CK(clk), .RN(n1628), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n1394),
.CK(clk), .RN(n1628), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n1393),
.CK(clk), .RN(n1628), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n1392),
.CK(clk), .RN(n1628), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n1391),
.CK(clk), .RN(n3053), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n1390),
.CK(clk), .RN(n3058), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n1389),
.CK(clk), .RN(n3048), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n1388),
.CK(clk), .RN(n1627), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n1387),
.CK(clk), .RN(n3053), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n1386),
.CK(clk), .RN(n3046), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n1385),
.CK(clk), .RN(n3048), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n1384),
.CK(clk), .RN(n3056), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n1383),
.CK(clk), .RN(n3053), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n1382),
.CK(clk), .RN(n3060), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n1381),
.CK(clk), .RN(n3048), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n1380),
.CK(clk), .RN(n1580), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n1379),
.CK(clk), .RN(n3051), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n1378),
.CK(clk), .RN(n1580), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n1377),
.CK(clk), .RN(n1580), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n1376),
.CK(clk), .RN(n3049), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n1375),
.CK(clk), .RN(n1685), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n1374),
.CK(clk), .RN(n3051), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n1373),
.CK(clk), .RN(n1580), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n1372),
.CK(clk), .RN(n1685), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n1371),
.CK(clk), .RN(n3051), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n1370),
.CK(clk), .RN(n1580), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n1369),
.CK(clk), .RN(n1685), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n1368),
.CK(clk), .RN(n3051), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n1367),
.CK(clk), .RN(n1580), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n1366),
.CK(clk), .RN(n1685), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n1365),
.CK(clk), .RN(n3051), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n1364),
.CK(clk), .RN(n1580), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n1363),
.CK(clk), .RN(n1685), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n1361),
.CK(clk), .RN(n3051), .Q(final_result_ieee[63]) );
DFFRXLTS ASRegister_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n3054), .Q(intAS) );
DFFRXLTS YRegister_Q_reg_63_ ( .D(n1231), .CK(clk), .RN(n1582), .Q(intDY[63]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1230), .CK(clk),
.RN(n3063), .Q(DMP[61]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1229), .CK(clk),
.RN(n3071), .Q(DMP[60]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1228), .CK(clk),
.RN(n3062), .Q(DMP[59]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1227), .CK(clk),
.RN(n3057), .Q(DMP[58]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1226), .CK(clk),
.RN(n3068), .Q(DMP[57]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1225), .CK(clk),
.RN(n3067), .Q(DMP[56]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1224), .CK(clk),
.RN(n3062), .Q(DMP[55]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1223), .CK(clk),
.RN(n3064), .Q(DMP[54]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1222), .CK(clk),
.RN(n3068), .Q(DMP[53]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1221), .CK(clk),
.RN(n3070), .Q(DMP[52]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1177), .CK(clk), .RN(
n3071), .Q(n1576) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1168), .CK(clk),
.RN(n3063), .Q(DMP[62]) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1167), .CK(clk),
.RN(n3065), .Q(sign_final_result) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1166), .CK(clk),
.RN(n3064), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1165), .CK(clk),
.RN(n3062), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1164), .CK(clk),
.RN(n3071), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1163), .CK(clk),
.RN(n3070), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1162), .CK(clk),
.RN(n3047), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1161), .CK(clk),
.RN(n3061), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1160), .CK(clk),
.RN(n3061), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1159), .CK(clk),
.RN(n3061), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1158), .CK(clk),
.RN(n3061), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1157), .CK(clk),
.RN(n3061), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1156), .CK(clk),
.RN(n3069), .Q(DmP[51]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1155), .CK(clk),
.RN(n1582), .Q(DmP[50]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1154), .CK(clk),
.RN(n3066), .Q(DmP[49]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1153), .CK(clk),
.RN(n3056), .Q(DmP[48]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1152), .CK(clk),
.RN(n3059), .Q(DmP[47]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1130), .CK(clk),
.RN(n3067), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1122), .CK(clk),
.RN(n3067), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1104), .CK(clk),
.RN(n3071), .Q(DmP[62]) );
CMPR32X2TS DP_OP_42J154_122_8302_U12 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .C(DP_OP_42J154_122_8302_n26), .CO(
DP_OP_42J154_122_8302_n11), .S(Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_42J154_122_8302_U11 ( .A(DP_OP_42J154_122_8302_n25), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J154_122_8302_n11), .CO(
DP_OP_42J154_122_8302_n10), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J154_122_8302_U10 ( .A(DP_OP_42J154_122_8302_n24), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J154_122_8302_n10), .CO(
DP_OP_42J154_122_8302_n9), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_42J154_122_8302_U9 ( .A(DP_OP_42J154_122_8302_n23), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J154_122_8302_n9), .CO(
DP_OP_42J154_122_8302_n8), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J154_122_8302_U8 ( .A(DP_OP_42J154_122_8302_n22), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J154_122_8302_n8), .CO(
DP_OP_42J154_122_8302_n7), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J154_122_8302_U7 ( .A(DP_OP_42J154_122_8302_n21), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J154_122_8302_n7), .CO(
DP_OP_42J154_122_8302_n6), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J154_122_8302_U6 ( .A(DP_OP_42J154_122_8302_n20), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J154_122_8302_n6), .CO(
DP_OP_42J154_122_8302_n5), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_42J154_122_8302_U5 ( .A(DP_OP_42J154_122_8302_n19), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J154_122_8302_n5), .CO(
DP_OP_42J154_122_8302_n4), .S(Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_42J154_122_8302_U4 ( .A(DP_OP_42J154_122_8302_n18), .B(
S_Oper_A_exp[8]), .C(DP_OP_42J154_122_8302_n4), .CO(
DP_OP_42J154_122_8302_n3), .S(Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_42J154_122_8302_U3 ( .A(DP_OP_42J154_122_8302_n17), .B(
S_Oper_A_exp[9]), .C(DP_OP_42J154_122_8302_n3), .CO(
DP_OP_42J154_122_8302_n2), .S(Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_42J154_122_8302_U2 ( .A(DP_OP_42J154_122_8302_n16), .B(
S_Oper_A_exp[10]), .C(DP_OP_42J154_122_8302_n2), .CO(
DP_OP_42J154_122_8302_n1), .S(Exp_Operation_Module_Data_S[10]) );
CMPR32X2TS DP_OP_45J154_125_8406_U56 ( .A(S_A_S_Oper_A[0]), .B(n3039), .C(
DP_OP_45J154_125_8406_n114), .CO(DP_OP_45J154_125_8406_n55), .S(
Add_Subt_Sgf_module_S_to_D[0]) );
CMPR32X2TS DP_OP_45J154_125_8406_U55 ( .A(DP_OP_45J154_125_8406_n113), .B(
S_A_S_Oper_A[1]), .C(DP_OP_45J154_125_8406_n55), .CO(
DP_OP_45J154_125_8406_n54), .S(Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_45J154_125_8406_U54 ( .A(DP_OP_45J154_125_8406_n112), .B(
S_A_S_Oper_A[2]), .C(DP_OP_45J154_125_8406_n54), .CO(
DP_OP_45J154_125_8406_n53), .S(Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_45J154_125_8406_U53 ( .A(DP_OP_45J154_125_8406_n111), .B(
S_A_S_Oper_A[3]), .C(DP_OP_45J154_125_8406_n53), .CO(
DP_OP_45J154_125_8406_n52), .S(Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_45J154_125_8406_U52 ( .A(DP_OP_45J154_125_8406_n110), .B(
S_A_S_Oper_A[4]), .C(DP_OP_45J154_125_8406_n52), .CO(
DP_OP_45J154_125_8406_n51), .S(Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_45J154_125_8406_U51 ( .A(DP_OP_45J154_125_8406_n109), .B(
S_A_S_Oper_A[5]), .C(DP_OP_45J154_125_8406_n51), .CO(
DP_OP_45J154_125_8406_n50), .S(Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_45J154_125_8406_U50 ( .A(DP_OP_45J154_125_8406_n108), .B(
S_A_S_Oper_A[6]), .C(DP_OP_45J154_125_8406_n50), .CO(
DP_OP_45J154_125_8406_n49), .S(Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_45J154_125_8406_U49 ( .A(DP_OP_45J154_125_8406_n107), .B(
S_A_S_Oper_A[7]), .C(DP_OP_45J154_125_8406_n49), .CO(
DP_OP_45J154_125_8406_n48), .S(Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_45J154_125_8406_U48 ( .A(DP_OP_45J154_125_8406_n106), .B(
S_A_S_Oper_A[8]), .C(DP_OP_45J154_125_8406_n48), .CO(
DP_OP_45J154_125_8406_n47), .S(Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_45J154_125_8406_U47 ( .A(DP_OP_45J154_125_8406_n105), .B(
S_A_S_Oper_A[9]), .C(DP_OP_45J154_125_8406_n47), .CO(
DP_OP_45J154_125_8406_n46), .S(Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_45J154_125_8406_U46 ( .A(DP_OP_45J154_125_8406_n104), .B(
S_A_S_Oper_A[10]), .C(DP_OP_45J154_125_8406_n46), .CO(
DP_OP_45J154_125_8406_n45), .S(Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_45J154_125_8406_U45 ( .A(DP_OP_45J154_125_8406_n103), .B(
S_A_S_Oper_A[11]), .C(DP_OP_45J154_125_8406_n45), .CO(
DP_OP_45J154_125_8406_n44), .S(Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_45J154_125_8406_U44 ( .A(DP_OP_45J154_125_8406_n102), .B(
S_A_S_Oper_A[12]), .C(DP_OP_45J154_125_8406_n44), .CO(
DP_OP_45J154_125_8406_n43), .S(Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_45J154_125_8406_U43 ( .A(DP_OP_45J154_125_8406_n101), .B(
S_A_S_Oper_A[13]), .C(DP_OP_45J154_125_8406_n43), .CO(
DP_OP_45J154_125_8406_n42), .S(Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_45J154_125_8406_U42 ( .A(DP_OP_45J154_125_8406_n100), .B(
S_A_S_Oper_A[14]), .C(DP_OP_45J154_125_8406_n42), .CO(
DP_OP_45J154_125_8406_n41), .S(Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_45J154_125_8406_U41 ( .A(DP_OP_45J154_125_8406_n99), .B(
S_A_S_Oper_A[15]), .C(DP_OP_45J154_125_8406_n41), .CO(
DP_OP_45J154_125_8406_n40), .S(Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_45J154_125_8406_U40 ( .A(DP_OP_45J154_125_8406_n98), .B(
S_A_S_Oper_A[16]), .C(DP_OP_45J154_125_8406_n40), .CO(
DP_OP_45J154_125_8406_n39), .S(Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_45J154_125_8406_U39 ( .A(DP_OP_45J154_125_8406_n97), .B(
S_A_S_Oper_A[17]), .C(DP_OP_45J154_125_8406_n39), .CO(
DP_OP_45J154_125_8406_n38), .S(Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_45J154_125_8406_U38 ( .A(DP_OP_45J154_125_8406_n96), .B(
S_A_S_Oper_A[18]), .C(DP_OP_45J154_125_8406_n38), .CO(
DP_OP_45J154_125_8406_n37), .S(Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_45J154_125_8406_U37 ( .A(DP_OP_45J154_125_8406_n95), .B(
S_A_S_Oper_A[19]), .C(DP_OP_45J154_125_8406_n37), .CO(
DP_OP_45J154_125_8406_n36), .S(Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_45J154_125_8406_U36 ( .A(DP_OP_45J154_125_8406_n94), .B(
S_A_S_Oper_A[20]), .C(DP_OP_45J154_125_8406_n36), .CO(
DP_OP_45J154_125_8406_n35), .S(Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_45J154_125_8406_U35 ( .A(DP_OP_45J154_125_8406_n93), .B(
S_A_S_Oper_A[21]), .C(DP_OP_45J154_125_8406_n35), .CO(
DP_OP_45J154_125_8406_n34), .S(Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_45J154_125_8406_U34 ( .A(DP_OP_45J154_125_8406_n92), .B(
S_A_S_Oper_A[22]), .C(DP_OP_45J154_125_8406_n34), .CO(
DP_OP_45J154_125_8406_n33), .S(Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_45J154_125_8406_U33 ( .A(DP_OP_45J154_125_8406_n91), .B(
S_A_S_Oper_A[23]), .C(DP_OP_45J154_125_8406_n33), .CO(
DP_OP_45J154_125_8406_n32), .S(Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_45J154_125_8406_U32 ( .A(DP_OP_45J154_125_8406_n90), .B(
S_A_S_Oper_A[24]), .C(DP_OP_45J154_125_8406_n32), .CO(
DP_OP_45J154_125_8406_n31), .S(Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_45J154_125_8406_U31 ( .A(DP_OP_45J154_125_8406_n89), .B(
S_A_S_Oper_A[25]), .C(DP_OP_45J154_125_8406_n31), .CO(
DP_OP_45J154_125_8406_n30), .S(Add_Subt_Sgf_module_S_to_D[25]) );
CMPR32X2TS DP_OP_45J154_125_8406_U30 ( .A(DP_OP_45J154_125_8406_n88), .B(
S_A_S_Oper_A[26]), .C(DP_OP_45J154_125_8406_n30), .CO(
DP_OP_45J154_125_8406_n29), .S(Add_Subt_Sgf_module_S_to_D[26]) );
CMPR32X2TS DP_OP_45J154_125_8406_U29 ( .A(DP_OP_45J154_125_8406_n87), .B(
S_A_S_Oper_A[27]), .C(DP_OP_45J154_125_8406_n29), .CO(
DP_OP_45J154_125_8406_n28), .S(Add_Subt_Sgf_module_S_to_D[27]) );
CMPR32X2TS DP_OP_45J154_125_8406_U28 ( .A(DP_OP_45J154_125_8406_n86), .B(
S_A_S_Oper_A[28]), .C(DP_OP_45J154_125_8406_n28), .CO(
DP_OP_45J154_125_8406_n27), .S(Add_Subt_Sgf_module_S_to_D[28]) );
CMPR32X2TS DP_OP_45J154_125_8406_U27 ( .A(DP_OP_45J154_125_8406_n85), .B(
S_A_S_Oper_A[29]), .C(DP_OP_45J154_125_8406_n27), .CO(
DP_OP_45J154_125_8406_n26), .S(Add_Subt_Sgf_module_S_to_D[29]) );
CMPR32X2TS DP_OP_45J154_125_8406_U26 ( .A(DP_OP_45J154_125_8406_n84), .B(
S_A_S_Oper_A[30]), .C(DP_OP_45J154_125_8406_n26), .CO(
DP_OP_45J154_125_8406_n25), .S(Add_Subt_Sgf_module_S_to_D[30]) );
CMPR32X2TS DP_OP_45J154_125_8406_U25 ( .A(DP_OP_45J154_125_8406_n83), .B(
S_A_S_Oper_A[31]), .C(DP_OP_45J154_125_8406_n25), .CO(
DP_OP_45J154_125_8406_n24), .S(Add_Subt_Sgf_module_S_to_D[31]) );
CMPR32X2TS DP_OP_45J154_125_8406_U24 ( .A(DP_OP_45J154_125_8406_n82), .B(
S_A_S_Oper_A[32]), .C(DP_OP_45J154_125_8406_n24), .CO(
DP_OP_45J154_125_8406_n23), .S(Add_Subt_Sgf_module_S_to_D[32]) );
CMPR32X2TS DP_OP_45J154_125_8406_U23 ( .A(DP_OP_45J154_125_8406_n81), .B(
S_A_S_Oper_A[33]), .C(DP_OP_45J154_125_8406_n23), .CO(
DP_OP_45J154_125_8406_n22), .S(Add_Subt_Sgf_module_S_to_D[33]) );
CMPR32X2TS DP_OP_45J154_125_8406_U22 ( .A(DP_OP_45J154_125_8406_n80), .B(
S_A_S_Oper_A[34]), .C(DP_OP_45J154_125_8406_n22), .CO(
DP_OP_45J154_125_8406_n21), .S(Add_Subt_Sgf_module_S_to_D[34]) );
CMPR32X2TS DP_OP_45J154_125_8406_U21 ( .A(DP_OP_45J154_125_8406_n79), .B(
S_A_S_Oper_A[35]), .C(DP_OP_45J154_125_8406_n21), .CO(
DP_OP_45J154_125_8406_n20), .S(Add_Subt_Sgf_module_S_to_D[35]) );
CMPR32X2TS DP_OP_45J154_125_8406_U20 ( .A(DP_OP_45J154_125_8406_n78), .B(
S_A_S_Oper_A[36]), .C(DP_OP_45J154_125_8406_n20), .CO(
DP_OP_45J154_125_8406_n19), .S(Add_Subt_Sgf_module_S_to_D[36]) );
CMPR32X2TS DP_OP_45J154_125_8406_U19 ( .A(DP_OP_45J154_125_8406_n77), .B(
S_A_S_Oper_A[37]), .C(DP_OP_45J154_125_8406_n19), .CO(
DP_OP_45J154_125_8406_n18), .S(Add_Subt_Sgf_module_S_to_D[37]) );
CMPR32X2TS DP_OP_45J154_125_8406_U18 ( .A(DP_OP_45J154_125_8406_n76), .B(
S_A_S_Oper_A[38]), .C(DP_OP_45J154_125_8406_n18), .CO(
DP_OP_45J154_125_8406_n17), .S(Add_Subt_Sgf_module_S_to_D[38]) );
CMPR32X2TS DP_OP_45J154_125_8406_U17 ( .A(DP_OP_45J154_125_8406_n75), .B(
S_A_S_Oper_A[39]), .C(DP_OP_45J154_125_8406_n17), .CO(
DP_OP_45J154_125_8406_n16), .S(Add_Subt_Sgf_module_S_to_D[39]) );
CMPR32X2TS DP_OP_45J154_125_8406_U16 ( .A(DP_OP_45J154_125_8406_n74), .B(
S_A_S_Oper_A[40]), .C(DP_OP_45J154_125_8406_n16), .CO(
DP_OP_45J154_125_8406_n15), .S(Add_Subt_Sgf_module_S_to_D[40]) );
CMPR32X2TS DP_OP_45J154_125_8406_U15 ( .A(DP_OP_45J154_125_8406_n73), .B(
S_A_S_Oper_A[41]), .C(DP_OP_45J154_125_8406_n15), .CO(
DP_OP_45J154_125_8406_n14), .S(Add_Subt_Sgf_module_S_to_D[41]) );
CMPR32X2TS DP_OP_45J154_125_8406_U14 ( .A(DP_OP_45J154_125_8406_n72), .B(
S_A_S_Oper_A[42]), .C(DP_OP_45J154_125_8406_n14), .CO(
DP_OP_45J154_125_8406_n13), .S(Add_Subt_Sgf_module_S_to_D[42]) );
CMPR32X2TS DP_OP_45J154_125_8406_U13 ( .A(DP_OP_45J154_125_8406_n71), .B(
S_A_S_Oper_A[43]), .C(DP_OP_45J154_125_8406_n13), .CO(
DP_OP_45J154_125_8406_n12), .S(Add_Subt_Sgf_module_S_to_D[43]) );
CMPR32X2TS DP_OP_45J154_125_8406_U12 ( .A(DP_OP_45J154_125_8406_n70), .B(
S_A_S_Oper_A[44]), .C(DP_OP_45J154_125_8406_n12), .CO(
DP_OP_45J154_125_8406_n11), .S(Add_Subt_Sgf_module_S_to_D[44]) );
CMPR32X2TS DP_OP_45J154_125_8406_U11 ( .A(DP_OP_45J154_125_8406_n69), .B(
S_A_S_Oper_A[45]), .C(DP_OP_45J154_125_8406_n11), .CO(
DP_OP_45J154_125_8406_n10), .S(Add_Subt_Sgf_module_S_to_D[45]) );
CMPR32X2TS DP_OP_45J154_125_8406_U10 ( .A(DP_OP_45J154_125_8406_n68), .B(
S_A_S_Oper_A[46]), .C(DP_OP_45J154_125_8406_n10), .CO(
DP_OP_45J154_125_8406_n9), .S(Add_Subt_Sgf_module_S_to_D[46]) );
CMPR32X2TS DP_OP_45J154_125_8406_U9 ( .A(DP_OP_45J154_125_8406_n67), .B(
S_A_S_Oper_A[47]), .C(DP_OP_45J154_125_8406_n9), .CO(
DP_OP_45J154_125_8406_n8), .S(Add_Subt_Sgf_module_S_to_D[47]) );
CMPR32X2TS DP_OP_45J154_125_8406_U8 ( .A(DP_OP_45J154_125_8406_n66), .B(
S_A_S_Oper_A[48]), .C(DP_OP_45J154_125_8406_n8), .CO(
DP_OP_45J154_125_8406_n7), .S(Add_Subt_Sgf_module_S_to_D[48]) );
CMPR32X2TS DP_OP_45J154_125_8406_U7 ( .A(DP_OP_45J154_125_8406_n65), .B(
S_A_S_Oper_A[49]), .C(DP_OP_45J154_125_8406_n7), .CO(
DP_OP_45J154_125_8406_n6), .S(Add_Subt_Sgf_module_S_to_D[49]) );
CMPR32X2TS DP_OP_45J154_125_8406_U6 ( .A(DP_OP_45J154_125_8406_n64), .B(
S_A_S_Oper_A[50]), .C(DP_OP_45J154_125_8406_n6), .CO(
DP_OP_45J154_125_8406_n5), .S(Add_Subt_Sgf_module_S_to_D[50]) );
CMPR32X2TS DP_OP_45J154_125_8406_U5 ( .A(DP_OP_45J154_125_8406_n63), .B(
S_A_S_Oper_A[51]), .C(DP_OP_45J154_125_8406_n5), .CO(
DP_OP_45J154_125_8406_n4), .S(Add_Subt_Sgf_module_S_to_D[51]) );
CMPR32X2TS DP_OP_45J154_125_8406_U4 ( .A(DP_OP_45J154_125_8406_n62), .B(
S_A_S_Oper_A[52]), .C(DP_OP_45J154_125_8406_n4), .CO(
DP_OP_45J154_125_8406_n3), .S(Add_Subt_Sgf_module_S_to_D[52]) );
CMPR32X2TS DP_OP_45J154_125_8406_U3 ( .A(DP_OP_45J154_125_8406_n61), .B(
S_A_S_Oper_A[53]), .C(DP_OP_45J154_125_8406_n3), .CO(
DP_OP_45J154_125_8406_n2), .S(Add_Subt_Sgf_module_S_to_D[53]) );
CMPR32X2TS DP_OP_45J154_125_8406_U2 ( .A(DP_OP_45J154_125_8406_n60), .B(
S_A_S_Oper_A[54]), .C(DP_OP_45J154_125_8406_n2), .CO(
DP_OP_45J154_125_8406_n1), .S(Add_Subt_Sgf_module_S_to_D[54]) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n1439), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[1]), .QN(n3037) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1503), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[0]), .QN(n3036) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1504), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[1]), .QN(n3035) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n1495), .CK(clk),
.RN(n1580), .Q(Sgf_normalized_result[53]), .QN(n3034) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1505), .CK(clk),
.RN(n3058), .Q(Add_Subt_result[2]), .QN(n3033) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(n3031) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]), .QN(n3030) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]), .QN(n3029) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(n3028) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]), .QN(n3027) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]), .QN(n3026) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3050),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]), .QN(n3025) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n1494), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[52]), .QN(n3024) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1509), .CK(clk),
.RN(n3066), .Q(Add_Subt_result[6]), .QN(n3016) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1506), .CK(clk),
.RN(n3056), .Q(Add_Subt_result[3]), .QN(n3014) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n1490), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[48]), .QN(n3005) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n1489), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[47]), .QN(n2995) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n1488), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[46]), .QN(n2994) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n1487), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[45]), .QN(n2983) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n1486), .CK(clk),
.RN(n3071), .Q(Sgf_normalized_result[44]), .QN(n2982) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n1485), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[43]), .QN(n2959) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n1483), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[41]), .QN(n2954) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n1482), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[40]), .QN(n2947) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n1481), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[39]), .QN(n2946) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n1480), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[38]), .QN(n2943) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n1479), .CK(clk),
.RN(n3067), .Q(Sgf_normalized_result[37]), .QN(n2942) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n1478), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[36]), .QN(n2938) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n1477), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[35]), .QN(n2937) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n1476), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[34]), .QN(n2936) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n1475), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[33]), .QN(n2935) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n1474), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[32]), .QN(n2934) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n1557), .CK(clk), .RN(n1360), .Q(FSM_selector_C), .QN(n2933) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n1472), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[30]), .QN(n2932) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n1471), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[29]), .QN(n2931) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n1470), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[28]), .QN(n2928) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n1469), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[27]), .QN(n2927) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1467), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[25]), .QN(n2925) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1464), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[22]), .QN(n2923) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1463), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[21]), .QN(n2922) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1462), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[20]), .QN(n2920) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1461), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[19]), .QN(n2919) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1460), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[18]), .QN(n2918) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1459), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[17]), .QN(n2917) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1458), .CK(clk),
.RN(n3064), .Q(Sgf_normalized_result[16]), .QN(n2915) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1457), .CK(clk),
.RN(n3071), .Q(Sgf_normalized_result[15]), .QN(n2914) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1456), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[14]), .QN(n2913) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1455), .CK(clk),
.RN(n3064), .Q(Sgf_normalized_result[13]), .QN(n2911) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1454), .CK(clk),
.RN(n3061), .Q(Sgf_normalized_result[12]), .QN(n2910) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1453), .CK(clk),
.RN(n3049), .Q(Sgf_normalized_result[11]), .QN(n2909) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1452), .CK(clk),
.RN(n3059), .Q(Sgf_normalized_result[10]), .QN(n2908) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1450), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[8]), .QN(n2905) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1449), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[7]), .QN(n2904) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1448), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[6]), .QN(n2903) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1443), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[1]), .QN(n2900) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1511), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[8]), .QN(n2897) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1447), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[5]), .QN(n2880) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1446), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[4]), .QN(n2879) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1445), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[3]), .QN(n2878) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1444), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[2]), .QN(n2877) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1442), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[0]), .QN(n2876) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n1468), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[26]), .QN(n2872) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1466), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[24]), .QN(n2871) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n1312), .CK(clk), .RN(n3047), .Q(intDX[15]), .QN(n3077) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n1631), .Q(intDX[11]), .QN(n3042) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n1323), .CK(clk), .RN(n3056), .Q(intDX[26]), .QN(n3041) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n1322), .CK(clk), .RN(n3048), .Q(intDX[25]), .QN(n3040) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n1320), .CK(clk), .RN(n1580), .Q(intDX[23]), .QN(n3075) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(n1328), .CK(clk), .RN(n3053), .Q(intDX[31]), .QN(n3074) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(n1352), .CK(clk), .RN(n1580), .Q(intDX[55]), .QN(n3072) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n3052), .Q(intDX[53]), .QN(n3073) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(n1347), .CK(clk), .RN(n3052), .Q(intDX[50]), .QN(n3045) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n1631), .Q(intDX[18]), .QN(n3076) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n1314), .CK(clk), .RN(n1631), .Q(intDX[17]), .QN(n3043) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n1493), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[51]), .QN(n3023) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n1492), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[50]), .QN(n3018) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n1491), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[49]), .QN(n3006) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n1473), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[31]), .QN(n2874) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1465), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[23]), .QN(n2870) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1512), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[9]), .QN(n3004) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]), .QN(n3032) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1513), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[10]), .QN(n3017) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1515), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[12]), .QN(n3015) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1517), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[14]) );
DFFRX1TS XRegister_Q_reg_40_ ( .D(n1337), .CK(clk), .RN(n3053), .Q(intDX[40]), .QN(n2991) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(n1321), .CK(clk), .RN(n3047), .Q(intDX[24]), .QN(n2972) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(n1307), .CK(clk), .RN(n1631), .Q(intDX[10]), .QN(n2978) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n1631), .Q(intDX[9]),
.QN(n2886) );
DFFRX1TS XRegister_Q_reg_44_ ( .D(n1341), .CK(clk), .RN(n3062), .Q(intDX[44]), .QN(n2990) );
DFFRX1TS XRegister_Q_reg_47_ ( .D(n1344), .CK(clk), .RN(n3052), .Q(intDX[47]), .QN(n2888) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(n1329), .CK(clk), .RN(n3048), .Q(intDX[32]), .QN(n2969) );
DFFRX1TS XRegister_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n3054), .Q(intDX[7]),
.QN(n2955) );
DFFRX1TS XRegister_Q_reg_62_ ( .D(n1359), .CK(clk), .RN(n1580), .Q(intDX[62]), .QN(n2894) );
DFFRX1TS XRegister_Q_reg_61_ ( .D(n1358), .CK(clk), .RN(n1685), .Q(intDX[61]), .QN(n2965) );
DFFRX1TS XRegister_Q_reg_56_ ( .D(n1353), .CK(clk), .RN(n3052), .Q(intDX[56]), .QN(n2966) );
DFFRX1TS XRegister_Q_reg_52_ ( .D(n1349), .CK(clk), .RN(n3052), .Q(intDX[52]), .QN(n2968) );
DFFRX1TS XRegister_Q_reg_48_ ( .D(n1345), .CK(clk), .RN(n3052), .Q(intDX[48]), .QN(n2988) );
DFFRX1TS XRegister_Q_reg_38_ ( .D(n1335), .CK(clk), .RN(n3048), .Q(intDX[38]), .QN(n2992) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(n1303), .CK(clk), .RN(n3054), .Q(intDX[6]),
.QN(n2979) );
DFFRX1TS XRegister_Q_reg_39_ ( .D(n1336), .CK(clk), .RN(n3054), .Q(intDX[39]), .QN(n2889) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(n1334), .CK(clk), .RN(n3053), .Q(intDX[37]), .QN(n2890) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(n1313), .CK(clk), .RN(n1631), .Q(intDX[16]), .QN(n2975) );
DFFRX1TS XRegister_Q_reg_5_ ( .D(n1302), .CK(clk), .RN(n3054), .Q(intDX[5]),
.QN(n2884) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3054), .Q(intDX[4]),
.QN(n2980) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n1299), .CK(clk), .RN(n3054), .Q(intDX[2]),
.QN(n2887) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n3054), .Q(intDX[1]),
.QN(n2893) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n3054), .Q(intDX[0]),
.QN(n2964) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1518), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[15]), .QN(n3022) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1519), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[16]), .QN(n2875) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1521), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[18]), .QN(n3021) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1523), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[20]), .QN(n3012) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n1526), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[23]), .QN(n2882) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n1527), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[24]), .QN(n3008) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n1528), .CK(clk),
.RN(n3069), .Q(Add_Subt_result[25]), .QN(n2930) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(n1529), .CK(clk),
.RN(n3058), .Q(Add_Subt_result[26]), .QN(n3010) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(n1531), .CK(clk),
.RN(n3069), .Q(Add_Subt_result[28]), .QN(n2926) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(n1533), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[30]), .QN(n2924) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(n1535), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[32]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(n1536), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[33]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(n1537), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[34]), .QN(n2921) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(n1538), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[35]), .QN(n3020) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(n1539), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[36]), .QN(n2916) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(n1540), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[37]), .QN(n3013) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(n1541), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[38]), .QN(n3011) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(n1542), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[39]), .QN(n2912) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(n1556), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[53]), .QN(n2899) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n1440), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[0]), .QN(n2953) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1507), .CK(clk),
.RN(n3056), .Q(Add_Subt_result[4]), .QN(n3019) );
DFFRX2TS YRegister_Q_reg_61_ ( .D(n1293), .CK(clk), .RN(n3055), .Q(intDY[61]), .QN(n2941) );
DFFRX2TS YRegister_Q_reg_48_ ( .D(n1280), .CK(clk), .RN(n3069), .Q(intDY[48]), .QN(n2948) );
DFFRX2TS YRegister_Q_reg_44_ ( .D(n1276), .CK(clk), .RN(n3062), .Q(intDY[44]), .QN(n2944) );
DFFRX2TS YRegister_Q_reg_38_ ( .D(n1270), .CK(clk), .RN(n3050), .Q(intDY[38]), .QN(n2945) );
DFFRX2TS YRegister_Q_reg_37_ ( .D(n1269), .CK(clk), .RN(n1631), .Q(intDY[37]), .QN(n2951) );
DFFRX2TS YRegister_Q_reg_52_ ( .D(n1284), .CK(clk), .RN(n3055), .Q(intDY[52]), .QN(n2950) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n3071), .Q(intDY[16]), .QN(n2956) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n1242), .CK(clk), .RN(n3064), .Q(intDY[10]), .QN(n2949) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n3056), .Q(intDY[7]),
.QN(n2885) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n3070), .Q(intDY[6]),
.QN(n2957) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n1237), .CK(clk), .RN(n3064), .Q(intDY[5]),
.QN(n2952) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n1685), .Q(intDY[4]),
.QN(n2883) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n1233), .CK(clk), .RN(n1582), .Q(intDY[1]),
.QN(n2939) );
DFFRX2TS XRegister_Q_reg_34_ ( .D(n1331), .CK(clk), .RN(n1580), .Q(intDX[34]), .QN(n2892) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n1311), .CK(clk), .RN(n1631), .Q(intDX[14]), .QN(n2976) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n1310), .CK(clk), .RN(n1631), .Q(intDX[13]), .QN(n2962) );
DFFRX2TS XRegister_Q_reg_12_ ( .D(n1309), .CK(clk), .RN(n1631), .Q(intDX[12]), .QN(n2977) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(n1305), .CK(clk), .RN(n3067), .Q(intDX[8]),
.QN(n2963) );
DFFRX2TS XRegister_Q_reg_46_ ( .D(n1343), .CK(clk), .RN(n3052), .Q(intDX[46]), .QN(n2989) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n3053), .Q(intDX[33]), .QN(n3000) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n1327), .CK(clk), .RN(n3055), .Q(intDX[30]), .QN(n2970) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n1325), .CK(clk), .RN(n3048), .Q(intDX[28]), .QN(n2971) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n1324), .CK(clk), .RN(n1685), .Q(intDX[27]), .QN(n2984) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(n1342), .CK(clk), .RN(n3052), .Q(intDX[45]), .QN(n2997) );
DFFRX2TS XRegister_Q_reg_42_ ( .D(n1339), .CK(clk), .RN(n3056), .Q(intDX[42]), .QN(n2891) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n3053), .Q(intDX[29]), .QN(n2961) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(n3046), .Q(intDX[22]), .QN(n2973) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n1317), .CK(clk), .RN(n1631), .Q(intDX[20]), .QN(n2974) );
DFFRX2TS XRegister_Q_reg_60_ ( .D(n1357), .CK(clk), .RN(n3051), .Q(intDX[60]), .QN(n3001) );
DFFRX2TS XRegister_Q_reg_59_ ( .D(n1356), .CK(clk), .RN(n1580), .Q(intDX[59]), .QN(n2895) );
DFFRX2TS XRegister_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n1685), .Q(intDX[58]), .QN(n3002) );
DFFRX2TS XRegister_Q_reg_57_ ( .D(n1354), .CK(clk), .RN(n3051), .Q(intDX[57]), .QN(n2996) );
DFFRX2TS XRegister_Q_reg_54_ ( .D(n1351), .CK(clk), .RN(n3052), .Q(intDX[54]), .QN(n2967) );
DFFRX2TS XRegister_Q_reg_51_ ( .D(n1348), .CK(clk), .RN(n3052), .Q(intDX[51]), .QN(n2986) );
DFFRX2TS XRegister_Q_reg_43_ ( .D(n1340), .CK(clk), .RN(n1631), .Q(intDX[43]), .QN(n2998) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(n1333), .CK(clk), .RN(n1627), .Q(intDX[36]), .QN(n3003) );
DFFRX2TS YRegister_Q_reg_62_ ( .D(n1294), .CK(clk), .RN(n3067), .Q(intDY[62]), .QN(n2993) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(n1332), .CK(clk), .RN(n1628), .Q(intDX[35]), .QN(n2999) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n1318), .CK(clk), .RN(n3048), .Q(intDX[21]), .QN(n2981) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n1316), .CK(clk), .RN(n1631), .Q(intDX[19]), .QN(n2985) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(n1300), .CK(clk), .RN(n3054), .Q(intDX[3]),
.QN(n2960) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n1558), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[2]), .QN(n2940) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n1560), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[0]), .QN(n2873) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n1561), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[3]), .QN(n2929) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n1559), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[1]), .QN(n2881) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(n1548), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[45]), .QN(n2896) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(n1553), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[50]), .QN(n3007) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(n1502), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[54]), .QN(n2898) );
DFFRX2TS YRegister_Q_reg_55_ ( .D(n1287), .CK(clk), .RN(n3055), .Q(intDY[55]) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n1235), .CK(clk), .RN(n3070), .Q(intDY[3])
);
DFFRX2TS YRegister_Q_reg_35_ ( .D(n1267), .CK(clk), .RN(n1631), .Q(intDY[35]) );
DFFRX2TS YRegister_Q_reg_43_ ( .D(n1275), .CK(clk), .RN(n3050), .Q(intDY[43]) );
DFFRX2TS YRegister_Q_reg_53_ ( .D(n1285), .CK(clk), .RN(n3055), .Q(intDY[53]) );
DFFRX2TS YRegister_Q_reg_41_ ( .D(n1273), .CK(clk), .RN(n3050), .Q(intDY[41]) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n1247), .CK(clk), .RN(n1631), .Q(intDY[15]) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n1255), .CK(clk), .RN(n3055), .Q(intDY[23]) );
DFFRX2TS YRegister_Q_reg_31_ ( .D(n1263), .CK(clk), .RN(n1631), .Q(intDY[31]) );
DFFRX2TS YRegister_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n1631), .Q(intDY[33]) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n3071), .Q(intDY[13]) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n1253), .CK(clk), .RN(n3060), .Q(intDY[21]) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n1261), .CK(clk), .RN(n1631), .Q(intDY[29]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(n1552), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[49]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n1525), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[22]) );
DFFRX2TS YRegister_Q_reg_46_ ( .D(n1278), .CK(clk), .RN(n3050), .Q(intDY[46]) );
DFFRX2TS YRegister_Q_reg_58_ ( .D(n1290), .CK(clk), .RN(n3055), .Q(intDY[58]) );
DFFRX2TS YRegister_Q_reg_60_ ( .D(n1292), .CK(clk), .RN(n3055), .Q(intDY[60]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(n1543), .CK(clk),
.RN(n3057), .Q(Add_Subt_result[40]) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n1243), .CK(clk), .RN(n1627), .Q(intDY[11]) );
DFFRX2TS YRegister_Q_reg_49_ ( .D(n1281), .CK(clk), .RN(n3065), .Q(intDY[49]) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n3046), .Q(intDY[18]) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n1631), .Q(intDY[26]) );
DFFRX2TS YRegister_Q_reg_39_ ( .D(n1271), .CK(clk), .RN(n1582), .Q(intDY[39]) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n1251), .CK(clk), .RN(n3058), .Q(intDY[19]) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(n1259), .CK(clk), .RN(n1631), .Q(intDY[27]) );
DFFRX2TS YRegister_Q_reg_51_ ( .D(n1283), .CK(clk), .RN(n3055), .Q(intDY[51]) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n1240), .CK(clk), .RN(n3064), .Q(intDY[8])
);
DFFRX2TS YRegister_Q_reg_47_ ( .D(n1279), .CK(clk), .RN(n3065), .Q(intDY[47]) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(n1241), .CK(clk), .RN(n3071), .Q(intDY[9])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(n1547), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[44]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1510), .CK(clk),
.RN(n3065), .Q(Add_Subt_result[7]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(n1532), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[29]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(n1555), .CK(clk),
.RN(n3067), .Q(Add_Subt_result[52]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1516), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(n1534), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[31]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n1562), .CK(
clk), .RN(n3063), .Q(add_overflow_flag) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n1232), .CK(clk), .RN(n3066), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1524), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[21]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1514), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[11]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1520), .CK(clk),
.RN(n3057), .Q(Add_Subt_result[17]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1522), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[19]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1438), .CK(clk),
.RN(n3070), .Q(exp_oper_result[0]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1435), .CK(clk),
.RN(n3071), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1434), .CK(clk),
.RN(n3068), .Q(exp_oper_result[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1433), .CK(clk),
.RN(n3057), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1427), .CK(clk), .RN(
n3049), .Q(overflow_flag) );
DFFRX1TS XRegister_Q_reg_63_ ( .D(n1296), .CK(clk), .RN(n3054), .Q(intDX[63]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n1497), .CK(
clk), .RN(n3061), .Q(LZA_output[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n1428), .CK(clk),
.RN(n3063), .Q(exp_oper_result[10]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n1429), .CK(clk),
.RN(n3063), .Q(exp_oper_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n1430), .CK(clk),
.RN(n3062), .Q(exp_oper_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1431), .CK(clk),
.RN(n3067), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1432), .CK(clk),
.RN(n3068), .Q(exp_oper_result[6]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3064),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1127), .CK(clk),
.RN(n3067), .Q(DmP[22]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1129), .CK(clk),
.RN(n3067), .Q(DmP[24]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1133), .CK(clk),
.RN(n3067), .Q(DmP[28]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1137), .CK(clk),
.RN(n1582), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1139), .CK(clk),
.RN(n1582), .Q(DmP[34]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1141), .CK(clk),
.RN(n3066), .Q(DmP[36]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1149), .CK(clk),
.RN(n3056), .Q(DmP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1170), .CK(clk), .RN(
n3063), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1171), .CK(clk), .RN(
n3057), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1173), .CK(clk), .RN(
n1582), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(
n1582), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1175), .CK(clk), .RN(
n3065), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1176), .CK(clk), .RN(
n3060), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1181), .CK(clk),
.RN(n3070), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1183), .CK(clk),
.RN(n3068), .Q(DMP[14]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1201), .CK(clk),
.RN(n3071), .Q(DMP[32]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1207), .CK(clk),
.RN(n3062), .Q(DMP[38]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1209), .CK(clk),
.RN(n3067), .Q(DMP[40]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1211), .CK(clk),
.RN(n3068), .Q(DMP[42]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1213), .CK(clk),
.RN(n3069), .Q(DMP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1214), .CK(clk),
.RN(n3058), .Q(DMP[45]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1217), .CK(clk),
.RN(n3069), .Q(DMP[48]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1219), .CK(clk),
.RN(n3056), .Q(DMP[50]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1106), .CK(clk), .RN(
n3058), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1107), .CK(clk), .RN(
n3069), .Q(DmP[2]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1109), .CK(clk), .RN(
n3058), .Q(DmP[4]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1111), .CK(clk), .RN(
n3069), .Q(DmP[6]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1112), .CK(clk), .RN(
n3058), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1115), .CK(clk),
.RN(n3068), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1119), .CK(clk),
.RN(n3057), .Q(DmP[14]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1121), .CK(clk),
.RN(n3062), .Q(DmP[16]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(n1544), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[41]) );
DFFRX2TS YRegister_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n3055), .Q(intDY[57]) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n1257), .CK(clk), .RN(n3063), .Q(intDY[25]) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n1249), .CK(clk), .RN(n3047), .Q(intDY[17]) );
DFFRX2TS YRegister_Q_reg_45_ ( .D(n1277), .CK(clk), .RN(n1582), .Q(intDY[45]) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n1256), .CK(clk), .RN(n3049), .Q(intDY[24]) );
DFFRX2TS YRegister_Q_reg_56_ ( .D(n1288), .CK(clk), .RN(n3055), .Q(intDY[56]) );
DFFRX2TS YRegister_Q_reg_36_ ( .D(n1268), .CK(clk), .RN(n1631), .Q(intDY[36]) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n1244), .CK(clk), .RN(n3070), .Q(intDY[12]) );
DFFRX2TS YRegister_Q_reg_54_ ( .D(n1286), .CK(clk), .RN(n3055), .Q(intDY[54]) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(n1260), .CK(clk), .RN(n1631), .Q(intDY[28]) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n1252), .CK(clk), .RN(n3061), .Q(intDY[20]) );
DFFRX2TS YRegister_Q_reg_50_ ( .D(n1282), .CK(clk), .RN(n3055), .Q(intDY[50]) );
DFFRX2TS YRegister_Q_reg_42_ ( .D(n1274), .CK(clk), .RN(n3065), .Q(intDY[42]) );
DFFRX2TS YRegister_Q_reg_34_ ( .D(n1266), .CK(clk), .RN(n1631), .Q(intDY[34]) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n1628), .Q(intDY[14]) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(n1234), .CK(clk), .RN(n3058), .Q(intDY[2])
);
DFFRX2TS YRegister_Q_reg_30_ ( .D(n1262), .CK(clk), .RN(n1631), .Q(intDY[30]) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n1254), .CK(clk), .RN(n3063), .Q(intDY[22]) );
DFFRX2TS YRegister_Q_reg_59_ ( .D(n1291), .CK(clk), .RN(n3055), .Q(intDY[59]) );
DFFRX2TS YRegister_Q_reg_40_ ( .D(n1272), .CK(clk), .RN(n3065), .Q(intDY[40]) );
DFFRX2TS YRegister_Q_reg_32_ ( .D(n1264), .CK(clk), .RN(n1631), .Q(intDY[32]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(n1554), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[51]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(n1551), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[48]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(n1545), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRXLTS XRegister_Q_reg_49_ ( .D(n1346), .CK(clk), .RN(n3052), .Q(intDX[49]), .QN(n3044) );
DFFRXLTS XRegister_Q_reg_41_ ( .D(n1338), .CK(clk), .RN(n3053), .Q(intDX[41]), .QN(n2987) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n1563), .CK(clk),
.RN(n3049), .Q(Sgf_normalized_result[54]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n1501), .CK(
clk), .RN(n3070), .Q(LZA_output[2]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(n1546), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[43]), .QN(n2907) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(n1549), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[46]), .QN(n3009) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(n1550), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[47]), .QN(n2901) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1188), .CK(clk),
.RN(n3070), .Q(DMP[19]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1187), .CK(clk),
.RN(n3070), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1186), .CK(clk),
.RN(n3070), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1185), .CK(clk),
.RN(n3070), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1184), .CK(clk),
.RN(n3070), .Q(DMP[15]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1437), .CK(clk),
.RN(n3071), .QN(n1601) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1580),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3053),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3068),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3048),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1580),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3053),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3061),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1151), .CK(clk),
.RN(n3065), .Q(DmP[46]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1150), .CK(clk),
.RN(n1582), .Q(DmP[45]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1148), .CK(clk),
.RN(n1582), .Q(DmP[43]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1147), .CK(clk),
.RN(n3066), .Q(DmP[42]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1146), .CK(clk),
.RN(n3056), .Q(DmP[41]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1145), .CK(clk),
.RN(n3061), .Q(DmP[40]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1144), .CK(clk),
.RN(n3065), .Q(DmP[39]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1143), .CK(clk),
.RN(n3071), .Q(DmP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1142), .CK(clk),
.RN(n3066), .Q(DmP[37]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1140), .CK(clk),
.RN(n3056), .Q(DmP[35]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1138), .CK(clk),
.RN(n3069), .Q(DmP[33]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1136), .CK(clk),
.RN(n3071), .Q(DmP[31]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1135), .CK(clk),
.RN(n3067), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1134), .CK(clk),
.RN(n3071), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1132), .CK(clk),
.RN(n3067), .Q(DmP[27]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1131), .CK(clk),
.RN(n3071), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1128), .CK(clk),
.RN(n3071), .Q(DmP[23]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1126), .CK(clk),
.RN(n3067), .Q(DmP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1125), .CK(clk),
.RN(n3071), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1124), .CK(clk),
.RN(n3057), .Q(DmP[19]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1123), .CK(clk),
.RN(n3062), .Q(DmP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1220), .CK(clk),
.RN(n3071), .Q(DMP[51]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1218), .CK(clk),
.RN(n3058), .Q(DMP[49]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1216), .CK(clk),
.RN(n3069), .Q(DMP[47]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1215), .CK(clk),
.RN(n3058), .Q(DMP[46]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1212), .CK(clk),
.RN(n3067), .Q(DMP[43]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1208), .CK(clk),
.RN(n3057), .Q(DMP[39]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1206), .CK(clk),
.RN(n3068), .Q(DMP[37]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1205), .CK(clk),
.RN(n3071), .Q(DMP[36]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1204), .CK(clk),
.RN(n3062), .Q(DMP[35]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1203), .CK(clk),
.RN(n3057), .Q(DMP[34]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1202), .CK(clk),
.RN(n3068), .Q(DMP[33]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1200), .CK(clk),
.RN(n3065), .Q(DMP[31]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1199), .CK(clk),
.RN(n1582), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1198), .CK(clk),
.RN(n3055), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1197), .CK(clk),
.RN(n3056), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1196), .CK(clk),
.RN(n3066), .Q(DMP[27]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1195), .CK(clk),
.RN(n1582), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1194), .CK(clk),
.RN(n3070), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1193), .CK(clk),
.RN(n3065), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1191), .CK(clk),
.RN(n3060), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1190), .CK(clk),
.RN(n3056), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1189), .CK(clk),
.RN(n3066), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1182), .CK(clk),
.RN(n3064), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1180), .CK(clk),
.RN(n1628), .Q(DMP[11]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1178), .CK(clk), .RN(
n3070), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1172), .CK(clk), .RN(
n3071), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1169), .CK(clk), .RN(
n3063), .Q(DMP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1120), .CK(clk),
.RN(n3068), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1118), .CK(clk),
.RN(n3057), .Q(DmP[13]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1117), .CK(clk),
.RN(n3062), .Q(DmP[12]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1116), .CK(clk),
.RN(n3071), .Q(DmP[11]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(
n3068), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1113), .CK(clk), .RN(
n3057), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1110), .CK(clk), .RN(
n3058), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1108), .CK(clk), .RN(
n3069), .Q(DmP[3]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1105), .CK(clk), .RN(
n3058), .Q(DmP[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1499), .CK(
clk), .RN(n3046), .Q(LZA_output[0]), .QN(n3038) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n1484), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[42]), .QN(n2958) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1451), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[9]), .QN(n2906) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1179), .CK(clk),
.RN(n3071), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1210), .CK(clk),
.RN(n3062), .Q(DMP[41]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1192), .CK(clk),
.RN(n1582), .Q(DMP[23]) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n1441), .CK(clk), .RN(n1360), .Q(n2869), .QN(
n2902) );
BUFX6TS U1759 ( .A(n1685), .Y(n3064) );
NAND2X4TS U1760 ( .A(n2164), .B(n2864), .Y(n2041) );
AOI222X1TS U1761 ( .A0(n2766), .A1(DmP[17]), .B0(Add_Subt_result[35]), .B1(
n2206), .C0(Add_Subt_result[19]), .C1(n2700), .Y(n1762) );
NOR2X6TS U1762 ( .A(n1776), .B(n1806), .Y(n2457) );
OR3X2TS U1763 ( .A(n1775), .B(n1841), .C(n1776), .Y(n2562) );
AND2X6TS U1764 ( .A(FSM_selector_C), .B(n1675), .Y(n2700) );
CLKINVX6TS U1765 ( .A(n2042), .Y(n2035) );
BUFX6TS U1766 ( .A(n2041), .Y(n1577) );
INVX4TS U1767 ( .A(n2581), .Y(n2753) );
INVX3TS U1768 ( .A(n2582), .Y(n1741) );
INVX6TS U1769 ( .A(n2590), .Y(n2671) );
INVX4TS U1770 ( .A(n2588), .Y(n1705) );
INVX6TS U1771 ( .A(n2483), .Y(n1578) );
INVX8TS U1772 ( .A(n1772), .Y(n1793) );
INVX6TS U1773 ( .A(n2485), .Y(n1770) );
BUFX4TS U1774 ( .A(n2575), .Y(n2574) );
INVX6TS U1775 ( .A(n2700), .Y(n1579) );
BUFX6TS U1776 ( .A(n3064), .Y(n1580) );
CLKINVX6TS U1777 ( .A(n2846), .Y(n1581) );
CLKBUFX2TS U1778 ( .A(n2987), .Y(n1652) );
CLKBUFX2TS U1779 ( .A(n3044), .Y(n1654) );
BUFX6TS U1780 ( .A(n1685), .Y(n1582) );
AOI211XLTS U1781 ( .A0(Add_Subt_result[2]), .A1(n2436), .B0(n2435), .C0(
n2434), .Y(n2438) );
AOI211XLTS U1782 ( .A0(Add_Subt_result[12]), .A1(n2401), .B0(n2830), .C0(
n2380), .Y(n2390) );
NOR3XLTS U1783 ( .A(n2375), .B(n2831), .C(n2380), .Y(n2371) );
NOR3X2TS U1784 ( .A(Add_Subt_result[22]), .B(Add_Subt_result[21]), .C(n2348),
.Y(n2424) );
INVX6TS U1785 ( .A(n2579), .Y(n2714) );
NAND2X4TS U1786 ( .A(n1767), .B(n1774), .Y(n1768) );
NOR2X4TS U1787 ( .A(n2114), .B(n2589), .Y(n1781) );
OR2X4TS U1788 ( .A(n2773), .B(n1770), .Y(n2483) );
OAI21X2TS U1789 ( .A0(n2926), .A1(n2723), .B0(n1736), .Y(n1602) );
INVX6TS U1790 ( .A(n2562), .Y(n1584) );
INVX6TS U1791 ( .A(n2467), .Y(n1585) );
OR2X2TS U1792 ( .A(n1673), .B(n1674), .Y(n1672) );
OAI21X2TS U1793 ( .A0(n2907), .A1(n1579), .B0(n1693), .Y(n1605) );
NOR2X4TS U1794 ( .A(n1776), .B(n1772), .Y(n1773) );
BUFX6TS U1795 ( .A(n1677), .Y(n2575) );
BUFX6TS U1796 ( .A(n1700), .Y(n2651) );
AO22X2TS U1797 ( .A0(n1637), .A1(n1686), .B0(exp_oper_result[5]), .B1(n2555),
.Y(n1776) );
CLKINVX6TS U1798 ( .A(n2902), .Y(n2572) );
OR2X2TS U1799 ( .A(n2881), .B(n1688), .Y(n1677) );
AND4X2TS U1800 ( .A(FS_Module_state_reg[0]), .B(n2929), .C(n2940), .D(n2881),
.Y(n2859) );
AND4X4TS U1801 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .D(n2881), .Y(n2846) );
NOR2X4TS U1802 ( .A(FSM_selector_B[1]), .B(n2953), .Y(n1686) );
BUFX6TS U1803 ( .A(n1685), .Y(n3070) );
BUFX6TS U1804 ( .A(n1685), .Y(n3071) );
INVX8TS U1805 ( .A(rst), .Y(n1631) );
CLKINVX6TS U1806 ( .A(rst), .Y(n1685) );
MX2X1TS U1807 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n2570), .Y(
S_A_S_Oper_A[43]) );
MX2X1TS U1808 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n2572), .Y(
S_A_S_Oper_A[48]) );
MX2X1TS U1809 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(n2572), .Y(
S_A_S_Oper_A[51]) );
MX2X1TS U1810 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n2537), .Y(
S_A_S_Oper_A[19]) );
MX2X1TS U1811 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n2566), .Y(
S_A_S_Oper_A[31]) );
MX2X1TS U1812 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n2533), .Y(
S_A_S_Oper_A[13]) );
NOR2XLTS U1813 ( .A(n2911), .B(n2533), .Y(n2529) );
MX2X1TS U1814 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(n2566), .Y(
S_A_S_Oper_A[29]) );
MX2X1TS U1815 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n2533), .Y(
S_A_S_Oper_A[7]) );
NOR2XLTS U1816 ( .A(n2904), .B(n2869), .Y(n2536) );
MX2X1TS U1817 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n2566), .Y(
S_A_S_Oper_A[22]) );
NOR2XLTS U1818 ( .A(n2923), .B(n2537), .Y(n2520) );
NAND2BXLTS U1819 ( .AN(Sgf_normalized_result[54]), .B(n2572), .Y(
S_A_S_Oper_A[54]) );
MX2X1TS U1820 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n2533), .Y(
S_A_S_Oper_A[4]) );
NOR2XLTS U1821 ( .A(n2879), .B(n2869), .Y(n2540) );
MX2X1TS U1822 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n2566), .Y(
S_A_S_Oper_A[25]) );
MX2X1TS U1823 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n2570), .Y(
S_A_S_Oper_A[46]) );
MX2X1TS U1824 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n2570), .Y(
S_A_S_Oper_A[41]) );
MX2X1TS U1825 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n2537), .Y(
S_A_S_Oper_A[17]) );
NOR2XLTS U1826 ( .A(n2917), .B(n2537), .Y(n2525) );
MX2X1TS U1827 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n2533), .Y(
S_A_S_Oper_A[11]) );
NOR2XLTS U1828 ( .A(n2909), .B(n2533), .Y(n2531) );
MX2X1TS U1829 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n2537), .Y(
S_A_S_Oper_A[21]) );
NOR2XLTS U1830 ( .A(n2922), .B(n2537), .Y(n2521) );
MX2X1TS U1831 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n2570), .Y(
S_A_S_Oper_A[44]) );
MX2X1TS U1832 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n2572), .Y(
S_A_S_Oper_A[49]) );
MX2X1TS U1833 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n2572), .Y(
S_A_S_Oper_A[53]) );
MX2X1TS U1834 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n2570), .Y(
S_A_S_Oper_A[39]) );
MX2X1TS U1835 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n2570), .Y(
S_A_S_Oper_A[37]) );
MX2X1TS U1836 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n2566), .Y(
S_A_S_Oper_A[35]) );
MX2X1TS U1837 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n2566), .Y(
S_A_S_Oper_A[33]) );
MX2X1TS U1838 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n2566), .Y(
S_A_S_Oper_A[28]) );
MX2X1TS U1839 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n2566), .Y(
S_A_S_Oper_A[26]) );
MX2X1TS U1840 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n2566), .Y(
S_A_S_Oper_A[24]) );
MX2X1TS U1841 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n2537), .Y(
S_A_S_Oper_A[15]) );
NOR2XLTS U1842 ( .A(n2914), .B(n2537), .Y(n2527) );
MX2X1TS U1843 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n2533), .Y(
S_A_S_Oper_A[9]) );
NOR2XLTS U1844 ( .A(n2906), .B(n2533), .Y(n2534) );
MX2X1TS U1845 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n2537), .Y(
S_A_S_Oper_A[3]) );
MX2X1TS U1846 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n2533), .Y(
S_A_S_Oper_A[6]) );
NOR2XLTS U1847 ( .A(n2903), .B(n2533), .Y(n2538) );
CLKAND2X2TS U1848 ( .A(n2570), .B(Sgf_normalized_result[1]), .Y(
S_A_S_Oper_A[1]) );
NOR2XLTS U1849 ( .A(n2869), .B(n2900), .Y(n2543) );
NAND2BXLTS U1850 ( .AN(intDY[2]), .B(intDX[2]), .Y(n1912) );
NAND2BXLTS U1851 ( .AN(intDY[51]), .B(intDX[51]), .Y(n2012) );
NAND2BXLTS U1852 ( .AN(intDY[19]), .B(intDX[19]), .Y(n1943) );
NAND2BXLTS U1853 ( .AN(intDY[27]), .B(intDX[27]), .Y(n1898) );
NAND2BXLTS U1854 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1923) );
NAND2BXLTS U1855 ( .AN(intDY[13]), .B(intDX[13]), .Y(n1907) );
NAND2BXLTS U1856 ( .AN(intDY[21]), .B(intDX[21]), .Y(n1906) );
OAI221X1TS U1857 ( .A0(n1654), .A1(intDY[49]), .B0(n3045), .B1(intDY[50]),
.C0(n2278), .Y(n2281) );
NAND2BXLTS U1858 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1974) );
NAND2BXLTS U1859 ( .AN(intDY[59]), .B(intDX[59]), .Y(n1963) );
NAND2BXLTS U1860 ( .AN(intDY[29]), .B(intDX[29]), .Y(n1896) );
NAND2BXLTS U1861 ( .AN(intDY[40]), .B(intDX[40]), .Y(n1891) );
NAND2BXLTS U1862 ( .AN(intDY[41]), .B(intDX[41]), .Y(n1892) );
NAND2BXLTS U1863 ( .AN(intDY[32]), .B(intDX[32]), .Y(n1893) );
AOI221X1TS U1864 ( .A0(n2891), .A1(intDY[42]), .B0(intDY[41]), .B1(n1652),
.C0(n2298), .Y(n2301) );
NAND3BXLTS U1865 ( .AN(n1667), .B(n2443), .C(n2926), .Y(n2363) );
MX2X1TS U1866 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n2572), .Y(
S_A_S_Oper_A[47]) );
AOI222X1TS U1867 ( .A0(n2605), .A1(n2629), .B0(n2613), .B1(n2628), .C0(n1630), .C1(n2626), .Y(n2252) );
AOI222X1TS U1868 ( .A0(n1605), .A1(n2629), .B0(n2620), .B1(n2628), .C0(n2617), .C1(n2626), .Y(n2615) );
AOI222X1TS U1869 ( .A0(n2616), .A1(n2629), .B0(n1636), .B1(n2628), .C0(n2630), .C1(n2626), .Y(n2625) );
AOI222X1TS U1870 ( .A0(n2623), .A1(n2629), .B0(n2630), .B1(n2628), .C0(n1605), .C1(n1739), .Y(n1713) );
AOI222X1TS U1871 ( .A0(n1636), .A1(n2629), .B0(n2637), .B1(n2628), .C0(n2616), .C1(n2626), .Y(n2632) );
AOI222X1TS U1872 ( .A0(n2620), .A1(n2629), .B0(n2623), .B1(n2628), .C0(n1605), .C1(n2626), .Y(n2619) );
MX2X1TS U1873 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n2570), .Y(
S_A_S_Oper_A[42]) );
MX2X1TS U1874 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n2572), .Y(
S_A_S_Oper_A[52]) );
MX2X1TS U1875 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n2570), .Y(
S_A_S_Oper_A[40]) );
MX2X1TS U1876 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n2572), .Y(
S_A_S_Oper_A[50]) );
MX2X1TS U1877 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n2570), .Y(
S_A_S_Oper_A[45]) );
MX2X1TS U1878 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n2570), .Y(
S_A_S_Oper_A[38]) );
MX2X1TS U1879 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n2566), .Y(
S_A_S_Oper_A[36]) );
MX2X1TS U1880 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n2566), .Y(
S_A_S_Oper_A[34]) );
MX2X1TS U1881 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n2566), .Y(
S_A_S_Oper_A[32]) );
MX2X1TS U1882 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(n2566), .Y(
S_A_S_Oper_A[30]) );
MX2X1TS U1883 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n2566), .Y(
S_A_S_Oper_A[23]) );
NOR2XLTS U1884 ( .A(n2869), .B(n2870), .Y(n2519) );
MX2X1TS U1885 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n2537), .Y(
S_A_S_Oper_A[20]) );
NOR2XLTS U1886 ( .A(n2920), .B(n2537), .Y(n2522) );
MX2X1TS U1887 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n2537), .Y(
S_A_S_Oper_A[18]) );
MX2X1TS U1888 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n2537), .Y(
S_A_S_Oper_A[16]) );
NOR2XLTS U1889 ( .A(n2915), .B(n2537), .Y(n2526) );
MX2X1TS U1890 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n2533), .Y(
S_A_S_Oper_A[14]) );
NOR2XLTS U1891 ( .A(n2913), .B(n2533), .Y(n2528) );
MX2X1TS U1892 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n2533), .Y(
S_A_S_Oper_A[12]) );
NOR2XLTS U1893 ( .A(n2910), .B(n2533), .Y(n2530) );
MX2X1TS U1894 ( .A(n1576), .B(Sgf_normalized_result[10]), .S0(n2533), .Y(
S_A_S_Oper_A[10]) );
NOR2XLTS U1895 ( .A(n2908), .B(n2533), .Y(n2532) );
MX2X1TS U1896 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n2533), .Y(
S_A_S_Oper_A[8]) );
AO22XLTS U1897 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n1855) );
AO22XLTS U1898 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1867) );
MX2X1TS U1899 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n2566), .Y(
S_A_S_Oper_A[2]) );
CLKAND2X2TS U1900 ( .A(n2572), .B(Sgf_normalized_result[0]), .Y(
S_A_S_Oper_A[0]) );
NOR2XLTS U1901 ( .A(n2869), .B(n2876), .Y(n2545) );
AOI222X1TS U1902 ( .A0(n1634), .A1(n2629), .B0(n1602), .B1(n2628), .C0(n1756), .C1(n1739), .Y(n2648) );
AOI222X1TS U1903 ( .A0(n1635), .A1(n2629), .B0(n1634), .B1(n2628), .C0(n1756), .C1(n2626), .Y(n2644) );
AOI222X1TS U1904 ( .A0(n1756), .A1(n2629), .B0(n1635), .B1(n2628), .C0(n2641), .C1(n2626), .Y(n2639) );
OAI211XLTS U1905 ( .A0(n2409), .A1(n3004), .B0(n2408), .C0(n2407), .Y(n2410)
);
AOI211X1TS U1906 ( .A0(n2439), .A1(n2901), .B0(Add_Subt_result[50]), .C0(
Add_Subt_result[49]), .Y(n2441) );
OAI211XLTS U1907 ( .A0(Add_Subt_result[40]), .A1(Add_Subt_result[42]), .B0(
n2357), .C0(n2907), .Y(n2358) );
AO22XLTS U1908 ( .A0(Add_Subt_result[30]), .A1(n2362), .B0(n2361), .B1(
Add_Subt_result[22]), .Y(n2428) );
MX2X1TS U1909 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n2533), .Y(
S_A_S_Oper_A[5]) );
NOR2XLTS U1910 ( .A(n2880), .B(n2869), .Y(n2539) );
MX2X1TS U1911 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n2566), .Y(
S_A_S_Oper_A[27]) );
AO22XLTS U1912 ( .A0(Add_Subt_Sgf_module_S_to_D[47]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[47]), .Y(n1550) );
AO22XLTS U1913 ( .A0(Add_Subt_Sgf_module_S_to_D[46]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[46]), .Y(n1549) );
AO22XLTS U1914 ( .A0(Add_Subt_Sgf_module_S_to_D[43]), .A1(n2805), .B0(n2576),
.B1(Add_Subt_result[43]), .Y(n1546) );
AO22XLTS U1915 ( .A0(Add_Subt_Sgf_module_S_to_D[42]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[42]), .Y(n1545) );
AO22XLTS U1916 ( .A0(Add_Subt_Sgf_module_S_to_D[48]), .A1(n2805), .B0(n2576),
.B1(Add_Subt_result[48]), .Y(n1551) );
AO22XLTS U1917 ( .A0(Add_Subt_Sgf_module_S_to_D[51]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[51]), .Y(n1554) );
AO22XLTS U1918 ( .A0(n2857), .A1(Data_Y[32]), .B0(n2850), .B1(intDY[32]),
.Y(n1264) );
AO22XLTS U1919 ( .A0(n2854), .A1(Data_Y[40]), .B0(n2855), .B1(intDY[40]),
.Y(n1272) );
AO22XLTS U1920 ( .A0(n2848), .A1(Data_Y[59]), .B0(n2855), .B1(intDY[59]),
.Y(n1291) );
AO22XLTS U1921 ( .A0(n2857), .A1(Data_Y[34]), .B0(n2849), .B1(intDY[34]),
.Y(n1266) );
AO22XLTS U1922 ( .A0(n2857), .A1(Data_Y[42]), .B0(n2851), .B1(intDY[42]),
.Y(n1274) );
AO22XLTS U1923 ( .A0(n2853), .A1(Data_Y[50]), .B0(n2850), .B1(intDY[50]),
.Y(n1282) );
AO22XLTS U1924 ( .A0(n2853), .A1(Data_Y[54]), .B0(n2850), .B1(intDY[54]),
.Y(n1286) );
AO22XLTS U1925 ( .A0(n2857), .A1(Data_Y[36]), .B0(n2850), .B1(intDY[36]),
.Y(n1268) );
AO22XLTS U1926 ( .A0(n2853), .A1(Data_Y[56]), .B0(n2850), .B1(intDY[56]),
.Y(n1288) );
AO22XLTS U1927 ( .A0(n2856), .A1(Data_Y[45]), .B0(n2855), .B1(intDY[45]),
.Y(n1277) );
AO22XLTS U1928 ( .A0(n2853), .A1(Data_Y[57]), .B0(n2849), .B1(intDY[57]),
.Y(n1289) );
AO22XLTS U1929 ( .A0(Add_Subt_Sgf_module_S_to_D[41]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[41]), .Y(n1544) );
AO22XLTS U1930 ( .A0(n2858), .A1(Data_X[63]), .B0(n2855), .B1(intDX[63]),
.Y(n1296) );
AO22XLTS U1931 ( .A0(Add_Subt_Sgf_module_S_to_D[19]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[19]), .Y(n1522) );
AO22XLTS U1932 ( .A0(Add_Subt_Sgf_module_S_to_D[17]), .A1(n2805), .B0(n2574),
.B1(Add_Subt_result[17]), .Y(n1520) );
AO22XLTS U1933 ( .A0(Add_Subt_Sgf_module_S_to_D[11]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[11]), .Y(n1514) );
AO22XLTS U1934 ( .A0(Add_Subt_Sgf_module_S_to_D[21]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[21]), .Y(n1524) );
AO22XLTS U1935 ( .A0(n2853), .A1(Data_Y[0]), .B0(n2860), .B1(intDY[0]), .Y(
n1232) );
AO22XLTS U1936 ( .A0(n2568), .A1(n2577), .B0(add_overflow_flag), .B1(n2575),
.Y(n1562) );
AO22XLTS U1937 ( .A0(Add_Subt_Sgf_module_S_to_D[31]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[31]), .Y(n1534) );
AO22XLTS U1938 ( .A0(Add_Subt_Sgf_module_S_to_D[52]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[52]), .Y(n1555) );
AO22XLTS U1939 ( .A0(Add_Subt_Sgf_module_S_to_D[29]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[29]), .Y(n1532) );
AO22XLTS U1940 ( .A0(Add_Subt_Sgf_module_S_to_D[7]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[7]), .Y(n1510) );
AO22XLTS U1941 ( .A0(Add_Subt_Sgf_module_S_to_D[44]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[44]), .Y(n1547) );
AO22XLTS U1942 ( .A0(n2854), .A1(Data_Y[47]), .B0(n2851), .B1(intDY[47]),
.Y(n1279) );
AO22XLTS U1943 ( .A0(n2853), .A1(Data_Y[51]), .B0(n2849), .B1(intDY[51]),
.Y(n1283) );
AO22XLTS U1944 ( .A0(n2853), .A1(Data_Y[49]), .B0(n2855), .B1(intDY[49]),
.Y(n1281) );
AO22XLTS U1945 ( .A0(Add_Subt_Sgf_module_S_to_D[40]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[40]), .Y(n1543) );
AO22XLTS U1946 ( .A0(n2852), .A1(Data_Y[60]), .B0(n2851), .B1(intDY[60]),
.Y(n1292) );
AO22XLTS U1947 ( .A0(n2853), .A1(Data_Y[58]), .B0(n2851), .B1(intDY[58]),
.Y(n1290) );
AO22XLTS U1948 ( .A0(n2856), .A1(Data_Y[46]), .B0(n2851), .B1(intDY[46]),
.Y(n1278) );
AO22XLTS U1949 ( .A0(Add_Subt_Sgf_module_S_to_D[22]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[22]), .Y(n1525) );
AO22XLTS U1950 ( .A0(Add_Subt_Sgf_module_S_to_D[49]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[49]), .Y(n1552) );
AO22XLTS U1951 ( .A0(n2857), .A1(Data_Y[33]), .B0(n2855), .B1(intDY[33]),
.Y(n1265) );
AO22XLTS U1952 ( .A0(n2857), .A1(Data_Y[31]), .B0(n2851), .B1(intDY[31]),
.Y(n1263) );
AO22XLTS U1953 ( .A0(n2853), .A1(Data_Y[41]), .B0(n2849), .B1(intDY[41]),
.Y(n1273) );
AO22XLTS U1954 ( .A0(n2853), .A1(Data_Y[53]), .B0(n2851), .B1(intDY[53]),
.Y(n1285) );
AO22XLTS U1955 ( .A0(n2857), .A1(Data_Y[43]), .B0(n2850), .B1(intDY[43]),
.Y(n1275) );
AO22XLTS U1956 ( .A0(n2857), .A1(Data_Y[35]), .B0(n2851), .B1(intDY[35]),
.Y(n1267) );
AO22XLTS U1957 ( .A0(n2853), .A1(Data_Y[55]), .B0(n2849), .B1(intDY[55]),
.Y(n1287) );
AO22XLTS U1958 ( .A0(Add_Subt_Sgf_module_S_to_D[54]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[54]), .Y(n1502) );
AO22XLTS U1959 ( .A0(Add_Subt_Sgf_module_S_to_D[50]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[50]), .Y(n1553) );
AO22XLTS U1960 ( .A0(Add_Subt_Sgf_module_S_to_D[45]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[45]), .Y(n1548) );
AOI211X1TS U1961 ( .A0(FS_Module_state_reg[1]), .A1(n1587), .B0(n1682), .C0(
n1681), .Y(n1684) );
AOI211XLTS U1962 ( .A0(FS_Module_state_reg[3]), .A1(n1587), .B0(n2809), .C0(
n2814), .Y(n2811) );
AOI211X1TS U1963 ( .A0(n2816), .A1(n2815), .B0(n2814), .C0(n2813), .Y(n2820)
);
AO22XLTS U1964 ( .A0(Add_Subt_Sgf_module_S_to_D[53]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[53]), .Y(n1556) );
AO22XLTS U1965 ( .A0(Add_Subt_Sgf_module_S_to_D[39]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[39]), .Y(n1542) );
AO22XLTS U1966 ( .A0(Add_Subt_Sgf_module_S_to_D[38]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[38]), .Y(n1541) );
AO22XLTS U1967 ( .A0(Add_Subt_Sgf_module_S_to_D[37]), .A1(n2805), .B0(n2574),
.B1(Add_Subt_result[37]), .Y(n1540) );
AO22XLTS U1968 ( .A0(Add_Subt_Sgf_module_S_to_D[36]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[36]), .Y(n1539) );
AO22XLTS U1969 ( .A0(Add_Subt_Sgf_module_S_to_D[35]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[35]), .Y(n1538) );
AO22XLTS U1970 ( .A0(n2853), .A1(Data_Y[63]), .B0(n2860), .B1(intDY[63]),
.Y(n1231) );
AO22XLTS U1971 ( .A0(n2852), .A1(add_subt), .B0(n2855), .B1(intAS), .Y(n1295) );
AO22XLTS U1972 ( .A0(n2709), .A1(n1752), .B0(n2659), .B1(n1705), .Y(n1763)
);
AOI31XLTS U1973 ( .A0(n2836), .A1(n2835), .A2(n2413), .B0(n2412), .Y(n1496)
);
NAND4XLTS U1974 ( .A(n2447), .B(n2446), .C(n2445), .D(n2444), .Y(n2448) );
AO22XLTS U1975 ( .A0(Add_Subt_Sgf_module_S_to_D[5]), .A1(n2577), .B0(n2576),
.B1(n1668), .Y(n1508) );
AO22XLTS U1976 ( .A0(Add_Subt_Sgf_module_S_to_D[27]), .A1(n2577), .B0(n1677),
.B1(n1667), .Y(n1530) );
OR2X1TS U1977 ( .A(n1670), .B(n1671), .Y(n1587) );
OR3X1TS U1978 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[1]), .Y(n1588) );
OA22X1TS U1979 ( .A0(n2265), .A1(n2721), .B0(n2873), .B1(n2810), .Y(n1590)
);
OA21XLTS U1980 ( .A0(n3008), .A1(n2723), .B0(n1740), .Y(n1591) );
OA21XLTS U1981 ( .A0(n2930), .A1(n2786), .B0(n1735), .Y(n1592) );
OA22X2TS U1982 ( .A0(Add_Subt_result[0]), .A1(n2786), .B0(
Add_Subt_result[54]), .B1(n1579), .Y(n1593) );
OR2X1TS U1983 ( .A(n1841), .B(n1774), .Y(n1597) );
OA21XLTS U1984 ( .A0(n3011), .A1(n1579), .B0(n1711), .Y(n1598) );
OA21XLTS U1985 ( .A0(n2924), .A1(n2723), .B0(n1734), .Y(n1599) );
OA21XLTS U1986 ( .A0(n2901), .A1(n1579), .B0(n1704), .Y(n1600) );
OA21XLTS U1987 ( .A0(n2882), .A1(n2723), .B0(n1748), .Y(n1604) );
OA21XLTS U1988 ( .A0(n3016), .A1(n1579), .B0(n2747), .Y(n1607) );
OAI2BB2X1TS U1989 ( .B0(n1973), .B1(n1972), .A0N(n1971), .A1N(n1970), .Y(
n2028) );
OAI21X1TS U1990 ( .A0(n1806), .A1(n3027), .B0(n1768), .Y(n1798) );
OAI21X1TS U1991 ( .A0(n1806), .A1(n3026), .B0(n1768), .Y(n1769) );
OAI21X1TS U1992 ( .A0(n1806), .A1(n3025), .B0(n1768), .Y(n1771) );
OAI21X1TS U1993 ( .A0(n1806), .A1(n3029), .B0(n1768), .Y(n1788) );
OAI21X1TS U1994 ( .A0(n1806), .A1(n3030), .B0(n1768), .Y(n1789) );
OAI21X1TS U1995 ( .A0(n1806), .A1(n3031), .B0(n1768), .Y(n1794) );
OAI21X1TS U1996 ( .A0(n1806), .A1(n3028), .B0(n1768), .Y(n1799) );
OAI21X1TS U1997 ( .A0(n1806), .A1(n3032), .B0(n1768), .Y(n1807) );
INVX2TS U1998 ( .A(n1593), .Y(n1625) );
OAI211XLTS U1999 ( .A0(n2433), .A1(n2432), .B0(n2431), .C0(n2430), .Y(n2434)
);
OAI21X1TS U2000 ( .A0(n2265), .A1(FSM_selector_C), .B0(n1679), .Y(n1680) );
MXI2X1TS U2001 ( .A(n2953), .B(add_overflow_flag), .S0(n2569), .Y(n1440) );
NOR3X1TS U2002 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .C(
n2929), .Y(n2569) );
NOR4X2TS U2003 ( .A(n1889), .B(n1961), .C(n1973), .D(n1965), .Y(n2018) );
INVX2TS U2004 ( .A(n1601), .Y(n1626) );
INVX2TS U2005 ( .A(n2786), .Y(n2773) );
CLKINVX6TS U2006 ( .A(n2786), .Y(n2206) );
BUFX4TS U2007 ( .A(n1675), .Y(n2786) );
INVX4TS U2008 ( .A(rst), .Y(n1627) );
INVX4TS U2009 ( .A(rst), .Y(n1628) );
BUFX4TS U2010 ( .A(n1580), .Y(n3050) );
AOI21X2TS U2011 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n1869), .Y(n2134)
);
AOI21X2TS U2012 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n1869), .Y(n1825)
);
BUFX4TS U2013 ( .A(n1580), .Y(n3049) );
CLKINVX6TS U2014 ( .A(n2858), .Y(n2850) );
CLKINVX6TS U2015 ( .A(n2858), .Y(n2851) );
CLKINVX6TS U2016 ( .A(n2858), .Y(n2849) );
CLKINVX6TS U2017 ( .A(n2858), .Y(n2855) );
BUFX4TS U2018 ( .A(n3046), .Y(n3061) );
BUFX4TS U2019 ( .A(n3070), .Y(n3068) );
BUFX4TS U2020 ( .A(n1582), .Y(n3063) );
BUFX4TS U2021 ( .A(n1582), .Y(n3058) );
BUFX4TS U2022 ( .A(n1582), .Y(n3069) );
BUFX4TS U2023 ( .A(n1580), .Y(n3046) );
BUFX4TS U2024 ( .A(n1580), .Y(n3047) );
BUFX4TS U2025 ( .A(n1582), .Y(n3060) );
BUFX4TS U2026 ( .A(n1685), .Y(n3065) );
BUFX4TS U2027 ( .A(n1580), .Y(n3056) );
BUFX4TS U2028 ( .A(n3065), .Y(n3059) );
INVX2TS U2029 ( .A(Add_Subt_result[14]), .Y(n1629) );
OAI21X2TS U2030 ( .A0(n3033), .A1(n1579), .B0(n2774), .Y(n2792) );
INVX2TS U2031 ( .A(n1600), .Y(n1630) );
BUFX4TS U2032 ( .A(n3069), .Y(n3055) );
BUFX4TS U2033 ( .A(n3064), .Y(n3057) );
BUFX4TS U2034 ( .A(n3070), .Y(n3062) );
BUFX4TS U2035 ( .A(n3071), .Y(n3067) );
INVX2TS U2036 ( .A(Add_Subt_result[32]), .Y(n1632) );
INVX2TS U2037 ( .A(Add_Subt_result[33]), .Y(n1633) );
AOI222X1TS U2038 ( .A0(n2646), .A1(n2629), .B0(n2636), .B1(n2628), .C0(n2627), .C1(n2626), .Y(n2645) );
AOI222X1TS U2039 ( .A0(n2627), .A1(n2629), .B0(n2646), .B1(n2628), .C0(n2642), .C1(n2626), .Y(n2640) );
OAI21X4TS U2040 ( .A0(n2921), .A1(n2723), .B0(n1717), .Y(n2646) );
INVX2TS U2041 ( .A(n1592), .Y(n1634) );
INVX2TS U2042 ( .A(n1599), .Y(n1635) );
INVX2TS U2043 ( .A(n1598), .Y(n1636) );
OAI21X4TS U2044 ( .A0(n3016), .A1(n2786), .B0(n1706), .Y(n2606) );
BUFX4TS U2045 ( .A(n1741), .Y(n2795) );
AOI211XLTS U2046 ( .A0(n2868), .A1(n2808), .B0(n2807), .C0(n2809), .Y(n2345)
);
OAI21X2TS U2047 ( .A0(n2721), .A1(n1720), .B0(n2818), .Y(n2809) );
BUFX4TS U2048 ( .A(n2933), .Y(n2815) );
BUFX6TS U2049 ( .A(n2933), .Y(n2766) );
OR2X4TS U2050 ( .A(n2816), .B(n1676), .Y(n2485) );
NOR3X2TS U2051 ( .A(n2873), .B(n1688), .C(FS_Module_state_reg[1]), .Y(n2816)
);
AOI211X2TS U2052 ( .A0(intDX[44]), .A1(n2944), .B0(n1975), .C0(n1984), .Y(
n1982) );
BUFX6TS U2053 ( .A(n2476), .Y(n2559) );
INVX2TS U2054 ( .A(n1608), .Y(n1637) );
AOI31XLTS U2055 ( .A0(n2390), .A1(n2835), .A2(n2389), .B0(n2388), .Y(n1501)
);
INVX2TS U2056 ( .A(n1590), .Y(n1638) );
AOI22X4TS U2057 ( .A0(n1648), .A1(n1686), .B0(n2555), .B1(n1626), .Y(n2665)
);
BUFX4TS U2058 ( .A(n1687), .Y(n2555) );
INVX2TS U2059 ( .A(n1588), .Y(n1639) );
BUFX4TS U2060 ( .A(n2856), .Y(n2852) );
INVX2TS U2061 ( .A(n1624), .Y(n1640) );
INVX2TS U2062 ( .A(n1617), .Y(n1641) );
INVX2TS U2063 ( .A(n1619), .Y(n1642) );
INVX2TS U2064 ( .A(n1621), .Y(n1643) );
INVX2TS U2065 ( .A(n1618), .Y(n1644) );
INVX2TS U2066 ( .A(n1620), .Y(n1645) );
INVX2TS U2067 ( .A(n1622), .Y(n1646) );
INVX2TS U2068 ( .A(n1623), .Y(n1647) );
INVX2TS U2069 ( .A(n1589), .Y(n1648) );
INVX2TS U2070 ( .A(n1603), .Y(n1649) );
AOI222X1TS U2071 ( .A0(n2636), .A1(n2629), .B0(n2641), .B1(n2628), .C0(n2627), .C1(n1739), .Y(n2649) );
AOI222X1TS U2072 ( .A0(n2642), .A1(n2629), .B0(n2627), .B1(n2628), .C0(n2637), .C1(n2626), .Y(n2635) );
OAI21X2TS U2073 ( .A0(n3020), .A1(n1579), .B0(n1716), .Y(n2627) );
OAI21X4TS U2074 ( .A0(n3009), .A1(n1579), .B0(n1702), .Y(n2605) );
OAI21X4TS U2075 ( .A0(n2930), .A1(n2723), .B0(n1742), .Y(n2672) );
INVX2TS U2076 ( .A(n1607), .Y(n1650) );
AOI222X1TS U2077 ( .A0(n2641), .A1(n2629), .B0(n1756), .B1(n2628), .C0(n2636), .C1(n2626), .Y(n2634) );
OAI21X2TS U2078 ( .A0(n2882), .A1(n1675), .B0(n1733), .Y(n1756) );
INVX2TS U2079 ( .A(n1604), .Y(n1651) );
OAI21X2TS U2080 ( .A0(n3014), .A1(n1579), .B0(n2767), .Y(n2797) );
INVX2TS U2081 ( .A(n1591), .Y(n1653) );
BUFX6TS U2082 ( .A(n1692), .Y(n2629) );
INVX2TS U2083 ( .A(n2858), .Y(n1655) );
INVX4TS U2084 ( .A(n1655), .Y(n1656) );
INVX2TS U2085 ( .A(n1597), .Y(n1657) );
AOI211X2TS U2086 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2478), .C0(n1867), .Y(n2113) );
AOI211X2TS U2087 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n1868), .B0(n2478), .C0(n1855), .Y(n2100) );
NOR2X4TS U2088 ( .A(n1768), .B(n1841), .Y(n2478) );
NAND2X6TS U2089 ( .A(n1872), .B(n1585), .Y(n2116) );
NAND2X6TS U2090 ( .A(n1578), .B(n2114), .Y(n2138) );
BUFX6TS U2091 ( .A(n2204), .Y(n2793) );
INVX3TS U2092 ( .A(n2813), .Y(n2573) );
CLKINVX6TS U2093 ( .A(n2035), .Y(n2218) );
CLKINVX6TS U2094 ( .A(n2035), .Y(n2239) );
AOI211XLTS U2095 ( .A0(n2671), .A1(n1593), .B0(n2256), .C0(n1725), .Y(n1726)
);
BUFX6TS U2096 ( .A(n1694), .Y(n2628) );
OAI21X2TS U2097 ( .A0(n3019), .A1(n1579), .B0(n2760), .Y(n2791) );
OAI21X2TS U2098 ( .A0(n1633), .A1(n2723), .B0(n1714), .Y(n2636) );
OAI21X2TS U2099 ( .A0(n3010), .A1(n2723), .B0(n1743), .Y(n2659) );
INVX4TS U2100 ( .A(n2852), .Y(n2860) );
INVX4TS U2101 ( .A(n2580), .Y(n2780) );
CLKINVX6TS U2102 ( .A(n2164), .Y(n2865) );
INVX6TS U2103 ( .A(n2164), .Y(n2238) );
INVX4TS U2104 ( .A(n2164), .Y(n2226) );
INVX2TS U2105 ( .A(n2846), .Y(n2838) );
CLKINVX6TS U2106 ( .A(n2846), .Y(n2844) );
CLKINVX3TS U2107 ( .A(n2041), .Y(n2074) );
CLKINVX6TS U2108 ( .A(n2041), .Y(n2189) );
CLKINVX6TS U2109 ( .A(n2041), .Y(n2162) );
CLKINVX3TS U2110 ( .A(n2786), .Y(n2693) );
CLKINVX6TS U2111 ( .A(n2868), .Y(n2190) );
INVX6TS U2112 ( .A(n2868), .Y(n2228) );
INVX6TS U2113 ( .A(n2868), .Y(n2223) );
INVX3TS U2114 ( .A(n2041), .Y(n2072) );
OR4X4TS U2115 ( .A(n2485), .B(n2578), .C(n2807), .D(n1680), .Y(
FSM_exp_operation_A_S) );
CLKINVX6TS U2116 ( .A(n2035), .Y(n2083) );
INVX6TS U2117 ( .A(n2574), .Y(n2578) );
INVX2TS U2118 ( .A(n1606), .Y(n1658) );
AOI21X2TS U2119 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n1769), .Y(n1786)
);
AOI21X2TS U2120 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n1798), .Y(n1831)
);
AOI21X2TS U2121 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n1788), .Y(n1828)
);
AOI21X2TS U2122 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n1794), .Y(n1837)
);
AOI21X2TS U2123 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n1789), .Y(n1834)
);
AOI21X2TS U2124 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n1799), .Y(n1840)
);
AOI211X1TS U2125 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n1781), .C0(n2470), .Y(n2473) );
AOI21X2TS U2126 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(n1771), .Y(n1819)
);
AOI211X2TS U2127 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2478), .C0(n1863), .Y(n2108) );
AOI211X1TS U2128 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n1781), .C0(n2563), .Y(n2565) );
AOI211X1TS U2129 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n2457), .B0(n1781), .C0(n2472), .Y(n2474) );
INVX2TS U2130 ( .A(n1616), .Y(n1659) );
AOI21X2TS U2131 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1807), .Y(n1822)
);
AOI211X1TS U2132 ( .A0(n2559), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1781), .C0(n2481), .Y(n2482) );
INVX2TS U2133 ( .A(n1594), .Y(n1660) );
AOI211X2TS U2134 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2478), .C0(n1847), .Y(n2087) );
AOI211X1TS U2135 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n1781), .C0(n2461), .Y(n2464) );
AOI211X2TS U2136 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2478), .C0(n1859), .Y(n2095) );
AOI211X1TS U2137 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n1781), .C0(n2456), .Y(n2466) );
AOI211X2TS U2138 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2478), .C0(n1843), .Y(n2091) );
AOI211X1TS U2139 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n1781), .C0(n2459), .Y(n2468) );
AOI211X2TS U2140 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2478), .C0(n1851), .Y(n2104) );
AOI211X1TS U2141 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n1781), .C0(n2463), .Y(n2465) );
INVX2TS U2142 ( .A(n1612), .Y(n1661) );
INVX2TS U2143 ( .A(n1610), .Y(n1662) );
INVX2TS U2144 ( .A(n1615), .Y(n1663) );
INVX2TS U2145 ( .A(n1611), .Y(n1664) );
INVX2TS U2146 ( .A(n1613), .Y(n1665) );
INVX2TS U2147 ( .A(n1614), .Y(n1666) );
INVX2TS U2148 ( .A(n1596), .Y(n1667) );
INVX2TS U2149 ( .A(n1609), .Y(n1668) );
NOR4X2TS U2150 ( .A(Add_Subt_result[48]), .B(Add_Subt_result[49]), .C(
Add_Subt_result[50]), .D(n2381), .Y(n2823) );
NOR3X1TS U2151 ( .A(Add_Subt_result[48]), .B(Add_Subt_result[49]), .C(
Add_Subt_result[50]), .Y(n2382) );
OAI31X1TS U2152 ( .A0(Add_Subt_result[51]), .A1(Add_Subt_result[52]), .A2(
n2441), .B0(n2440), .Y(n2446) );
OAI221XLTS U2153 ( .A0(n3074), .A1(intDY[31]), .B0(n2969), .B1(intDY[32]),
.C0(n2313), .Y(n2318) );
AOI221X1TS U2154 ( .A0(n2991), .A1(intDY[40]), .B0(intDY[39]), .B1(n2889),
.C0(n2289), .Y(n2294) );
AOI32X1TS U2155 ( .A0(n3002), .A1(n1963), .A2(intDY[58]), .B0(intDY[59]),
.B1(n2895), .Y(n1964) );
AOI221X1TS U2156 ( .A0(n3001), .A1(intDY[60]), .B0(intDY[59]), .B1(n2895),
.C0(n2275), .Y(n2285) );
OAI221X1TS U2157 ( .A0(n2981), .A1(intDY[21]), .B0(n2973), .B1(intDY[22]),
.C0(n2304), .Y(n2311) );
OAI221X1TS U2158 ( .A0(n2961), .A1(intDY[29]), .B0(n2970), .B1(intDY[30]),
.C0(n2312), .Y(n2319) );
OAI221X1TS U2159 ( .A0(n2887), .A1(intDY[2]), .B0(n2964), .B1(intDY[0]),
.C0(n2322), .Y(n2325) );
OAI221X1TS U2160 ( .A0(n2962), .A1(intDY[13]), .B0(n2976), .B1(intDY[14]),
.C0(n2328), .Y(n2335) );
AOI221X1TS U2161 ( .A0(n2892), .A1(intDY[34]), .B0(intDY[33]), .B1(n3000),
.C0(n2290), .Y(n2293) );
AOI32X1TS U2162 ( .A0(n3045), .A1(n2012), .A2(intDY[50]), .B0(intDY[51]),
.B1(n2986), .Y(n2013) );
OAI211X2TS U2163 ( .A0(intDY[20]), .A1(n2974), .B0(n1952), .C0(n1906), .Y(
n1946) );
OAI221XLTS U2164 ( .A0(n2985), .A1(intDY[19]), .B0(n2974), .B1(intDY[20]),
.C0(n2307), .Y(n2308) );
OAI211X2TS U2165 ( .A0(intDY[28]), .A1(n2971), .B0(n1905), .C0(n1896), .Y(
n1955) );
OAI221XLTS U2166 ( .A0(n2984), .A1(intDY[27]), .B0(n2971), .B1(intDY[28]),
.C0(n2315), .Y(n2316) );
OAI221X1TS U2167 ( .A0(n3073), .A1(intDY[53]), .B0(n2967), .B1(intDY[54]),
.C0(n2276), .Y(n2283) );
OAI211X2TS U2168 ( .A0(intDY[12]), .A1(n2977), .B0(n1933), .C0(n1907), .Y(
n1937) );
OAI221XLTS U2169 ( .A0(n3042), .A1(intDY[11]), .B0(n2977), .B1(intDY[12]),
.C0(n2331), .Y(n2332) );
AOI221X1TS U2170 ( .A0(n3003), .A1(intDY[36]), .B0(intDY[35]), .B1(n2999),
.C0(n2291), .Y(n2292) );
OAI221XLTS U2171 ( .A0(n3072), .A1(intDY[55]), .B0(n2966), .B1(intDY[56]),
.C0(n2277), .Y(n2282) );
OAI221XLTS U2172 ( .A0(n3075), .A1(intDY[23]), .B0(n2972), .B1(intDY[24]),
.C0(n2305), .Y(n2310) );
AOI221X1TS U2173 ( .A0(n2989), .A1(intDY[46]), .B0(intDY[45]), .B1(n2997),
.C0(n2296), .Y(n2303) );
OAI221X1TS U2174 ( .A0(n3043), .A1(intDY[17]), .B0(n3076), .B1(intDY[18]),
.C0(n2306), .Y(n2309) );
OAI221X1TS U2175 ( .A0(n3040), .A1(intDY[25]), .B0(n3041), .B1(intDY[26]),
.C0(n2314), .Y(n2317) );
AOI221X1TS U2176 ( .A0(n3002), .A1(intDY[58]), .B0(intDY[57]), .B1(n2996),
.C0(n2274), .Y(n2286) );
OAI221X1TS U2177 ( .A0(n2884), .A1(intDY[5]), .B0(n2979), .B1(intDY[6]),
.C0(n2320), .Y(n2327) );
NOR4X2TS U2178 ( .A(n2343), .B(n2342), .C(n2341), .D(n2340), .Y(n2861) );
OR2X1TS U2179 ( .A(Add_Subt_result[42]), .B(n2346), .Y(n2825) );
INVX2TS U2180 ( .A(n2825), .Y(n1669) );
NOR2XLTS U2181 ( .A(beg_FSM), .B(n1360), .Y(n1670) );
INVX2TS U2182 ( .A(n2817), .Y(n1671) );
NAND2X2TS U2183 ( .A(n1639), .B(n2940), .Y(n1360) );
NOR2XLTS U2184 ( .A(n2918), .B(n2533), .Y(n2524) );
NOR2XLTS U2185 ( .A(n2919), .B(n2537), .Y(n2523) );
OAI21X4TS U2186 ( .A0(n3015), .A1(n1675), .B0(n1701), .Y(n2620) );
OAI21X2TS U2187 ( .A0(n2912), .A1(n1579), .B0(n1698), .Y(n2616) );
BUFX6TS U2188 ( .A(n1773), .Y(n2560) );
BUFX6TS U2189 ( .A(n1782), .Y(n2136) );
AOI21X2TS U2190 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1(
n1793), .B0(n1869), .Y(n2139) );
AOI21X2TS U2191 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1869), .Y(n2125)
);
AOI21X2TS U2192 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1869), .Y(n2119)
);
AOI21X2TS U2193 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n1869), .Y(n2128)
);
AOI21X2TS U2194 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1869), .Y(n2122)
);
AOI21X2TS U2195 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1869), .Y(n2131)
);
NOR2X4TS U2196 ( .A(n1793), .B(n2589), .Y(n1869) );
AOI31XLTS U2197 ( .A0(n2453), .A1(n2835), .A2(n2438), .B0(n2437), .Y(n1497)
);
AOI31XLTS U2198 ( .A0(n2453), .A1(n2835), .A2(n2452), .B0(n2451), .Y(n1498)
);
NOR2X4TS U2199 ( .A(FS_Module_state_reg[0]), .B(n2819), .Y(n2835) );
AOI22X2TS U2200 ( .A0(LZA_output[4]), .A1(n1686), .B0(n2555), .B1(
exp_oper_result[4]), .Y(n1775) );
INVX3TS U2201 ( .A(n1700), .Y(n2650) );
NOR2XLTS U2202 ( .A(n2953), .B(n2557), .Y(n1673) );
NOR2XLTS U2203 ( .A(exp_oper_result[0]), .B(n2557), .Y(n1674) );
AOI22X2TS U2204 ( .A0(n1672), .A1(n2659), .B0(n1745), .B1(n1744), .Y(n2664)
);
AOI22X2TS U2205 ( .A0(n1672), .A1(n1745), .B0(n1602), .B1(n1744), .Y(n2658)
);
NOR2X4TS U2206 ( .A(n1672), .B(n2665), .Y(n1739) );
OR2X4TS U2207 ( .A(n1770), .B(n2786), .Y(n2467) );
INVX4TS U2208 ( .A(n2859), .Y(n2847) );
BUFX6TS U2209 ( .A(n2512), .Y(n2567) );
AOI32X1TS U2210 ( .A0(Add_Subt_result[11]), .A1(n2406), .A2(n3015), .B0(
Add_Subt_result[13]), .B1(n2406), .Y(n2377) );
BUFX6TS U2211 ( .A(n1752), .Y(n2790) );
BUFX6TS U2212 ( .A(n1705), .Y(n2800) );
BUFX6TS U2213 ( .A(n1770), .Y(n2564) );
OAI21X4TS U2214 ( .A0(n1638), .A1(n2809), .B0(add_overflow_flag), .Y(n2589)
);
NOR2X2TS U2215 ( .A(Add_Subt_result[13]), .B(n2376), .Y(n2401) );
NOR2X2TS U2216 ( .A(Add_Subt_result[29]), .B(n2432), .Y(n2443) );
OAI221X1TS U2217 ( .A0(n2886), .A1(intDY[9]), .B0(n2978), .B1(intDY[10]),
.C0(n2330), .Y(n2333) );
OAI221XLTS U2218 ( .A0(n2955), .A1(intDY[7]), .B0(n2963), .B1(intDY[8]),
.C0(n2321), .Y(n2326) );
OAI221XLTS U2219 ( .A0(n2986), .A1(intDY[51]), .B0(n2968), .B1(intDY[52]),
.C0(n2279), .Y(n2280) );
AOI32X1TS U2220 ( .A0(n3041), .A1(n1898), .A2(intDY[26]), .B0(intDY[27]),
.B1(n2984), .Y(n1899) );
AOI32X1TS U2221 ( .A0(n3076), .A1(n1943), .A2(intDY[18]), .B0(intDY[19]),
.B1(n2985), .Y(n1944) );
NOR2XLTS U2222 ( .A(Add_Subt_result[40]), .B(n2442), .Y(n2347) );
OAI221XLTS U2223 ( .A0(n3077), .A1(intDY[15]), .B0(n2975), .B1(intDY[16]),
.C0(n2329), .Y(n2334) );
OAI221XLTS U2224 ( .A0(n2960), .A1(intDY[3]), .B0(n2980), .B1(intDY[4]),
.C0(n2323), .Y(n2324) );
OR4X2TS U2225 ( .A(FS_Module_state_reg[1]), .B(add_overflow_flag), .C(n2721),
.D(n1688), .Y(n1675) );
OAI21XLTS U2226 ( .A0(intDX[1]), .A1(n2939), .B0(intDX[0]), .Y(n1910) );
OAI21XLTS U2227 ( .A0(intDY[35]), .A1(n2999), .B0(intDY[34]), .Y(n1993) );
NOR2XLTS U2228 ( .A(n2010), .B(intDX[48]), .Y(n2011) );
NOR2XLTS U2229 ( .A(n1941), .B(intDX[16]), .Y(n1942) );
OAI21XLTS U2230 ( .A0(n1985), .A1(n1984), .B0(n1983), .Y(n1987) );
NOR2XLTS U2231 ( .A(Add_Subt_result[4]), .B(n3014), .Y(n2350) );
NOR2XLTS U2232 ( .A(n3018), .B(n2572), .Y(n2490) );
NOR2XLTS U2233 ( .A(n2995), .B(n2570), .Y(n2493) );
NOR2XLTS U2234 ( .A(n2869), .B(n2871), .Y(n2518) );
NOR2XLTS U2235 ( .A(n2905), .B(n2533), .Y(n2535) );
NOR2XLTS U2236 ( .A(n2878), .B(n2869), .Y(n2541) );
NOR2XLTS U2237 ( .A(n2869), .B(n2931), .Y(n2513) );
OAI21XLTS U2238 ( .A0(n2562), .A1(n3028), .B0(n2462), .Y(n2463) );
AOI31XLTS U2239 ( .A0(n2345), .A1(n1588), .A2(n2344), .B0(n1587), .Y(n1560)
);
OAI21XLTS U2240 ( .A0(n2139), .A1(n2116), .B0(n2101), .Y(n1442) );
OAI21XLTS U2241 ( .A0(n1831), .A1(n2116), .B0(n1802), .Y(n1455) );
OAI211XLTS U2242 ( .A0(n2100), .A1(n2138), .B0(n1885), .C0(n2136), .Y(n1474)
);
OAI211XLTS U2243 ( .A0(n1786), .A1(n2138), .B0(n1783), .C0(n2136), .Y(n1488)
);
OAI21XLTS U2244 ( .A0(n2978), .A1(n2153), .B0(n2061), .Y(n1115) );
OAI21XLTS U2245 ( .A0(n2972), .A1(n2192), .B0(n2182), .Y(n1129) );
OAI21XLTS U2246 ( .A0(n2992), .A1(n2177), .B0(n2143), .Y(n1143) );
OAI21XLTS U2247 ( .A0(n2968), .A1(n2192), .B0(n2069), .Y(n1157) );
OAI21XLTS U2248 ( .A0(n2960), .A1(n2237), .B0(n2217), .Y(n1172) );
OAI21XLTS U2249 ( .A0(n2975), .A1(n2041), .B0(n2196), .Y(n1185) );
OAI21XLTS U2250 ( .A0(n2961), .A1(n2241), .B0(n2047), .Y(n1198) );
OAI21XLTS U2251 ( .A0(n2891), .A1(n1577), .B0(n2201), .Y(n1211) );
OAI21XLTS U2252 ( .A0(n3072), .A1(n2237), .B0(n2236), .Y(n1224) );
OAI211XLTS U2253 ( .A0(n2615), .A1(n2651), .B0(n2248), .C0(n2247), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI31XLTS U2254 ( .A0(n2371), .A1(n2835), .A2(n2370), .B0(n2369), .Y(n1500)
);
NAND2X1TS U2255 ( .A(n2929), .B(FS_Module_state_reg[2]), .Y(n1688) );
NAND4X1TS U2256 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.C(n2873), .D(n2881), .Y(n2818) );
INVX2TS U2257 ( .A(n2818), .Y(n1676) );
NAND3X1TS U2258 ( .A(FS_Module_state_reg[3]), .B(n2940), .C(n2881), .Y(n2819) );
NOR2X2TS U2259 ( .A(n2873), .B(n2819), .Y(n2807) );
NAND2BX1TS U2260 ( .AN(n2940), .B(n1639), .Y(n2265) );
AOI32X1TS U2261 ( .A0(FS_Module_state_reg[3]), .A1(n2940), .A2(
FS_Module_state_reg[0]), .B0(n2929), .B1(FS_Module_state_reg[2]), .Y(
n1678) );
NOR2BX1TS U2262 ( .AN(add_overflow_flag), .B(n1678), .Y(n1679) );
NOR4X1TS U2263 ( .A(FS_Module_state_reg[0]), .B(n2940), .C(n2929), .D(n2881),
.Y(ready) );
NAND2BXLTS U2264 ( .AN(ack_FSM), .B(ready), .Y(n2817) );
INVX2TS U2265 ( .A(n2816), .Y(n1720) );
NOR2XLTS U2266 ( .A(FSM_selector_C), .B(n1720), .Y(n1682) );
AND4X2TS U2267 ( .A(FS_Module_state_reg[1]), .B(n2873), .C(n2940), .D(n2929),
.Y(n2868) );
NAND3X1TS U2268 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]),
.C(n2940), .Y(n2810) );
NAND2BX1TS U2269 ( .AN(n2810), .B(n2873), .Y(n2344) );
NAND4XLTS U2270 ( .A(n2838), .B(n2228), .C(n2344), .D(n2847), .Y(n1681) );
CLKINVX1TS U2271 ( .A(sign_final_result), .Y(n2866) );
AOI22X1TS U2272 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2900), .B1(n2876),
.Y(n1683) );
OAI221X1TS U2273 ( .A0(sign_final_result), .A1(r_mode[1]), .B0(n2866), .B1(
r_mode[0]), .C0(n1683), .Y(n2806) );
NAND2BXLTS U2274 ( .AN(n2806), .B(n2807), .Y(n1731) );
OAI211XLTS U2275 ( .A0(n1677), .A1(n2873), .B0(n1684), .C0(n1731), .Y(n1559)
);
BUFX3TS U2276 ( .A(n1685), .Y(n3048) );
BUFX3TS U2277 ( .A(n3064), .Y(n3066) );
BUFX3TS U2278 ( .A(n3064), .Y(n3052) );
BUFX3TS U2279 ( .A(n1580), .Y(n3053) );
BUFX3TS U2280 ( .A(n3064), .Y(n3051) );
BUFX3TS U2281 ( .A(n3071), .Y(n3054) );
OAI21XLTS U2282 ( .A0(n2575), .A1(FS_Module_state_reg[0]), .B0(n2766), .Y(
n1557) );
INVX2TS U2283 ( .A(underflow_flag), .Y(n2843) );
NAND3BX1TS U2284 ( .AN(overflow_flag), .B(n2846), .C(n2843), .Y(n2839) );
CLKBUFX2TS U2285 ( .A(n2839), .Y(n2837) );
OAI2BB2XLTS U2286 ( .B0(n2995), .B1(n2837), .A0N(final_result_ieee[45]),
.A1N(n1581), .Y(n1369) );
OAI2BB2XLTS U2287 ( .B0(n2959), .B1(n2837), .A0N(final_result_ieee[41]),
.A1N(n1581), .Y(n1373) );
NOR2XLTS U2288 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n1687) );
AO22XLTS U2289 ( .A0(LZA_output[2]), .A1(n1686), .B0(n2555), .B1(n1658), .Y(
n1700) );
INVX4TS U2290 ( .A(n2651), .Y(n2666) );
AOI22X1TS U2291 ( .A0(Add_Subt_result[44]), .A1(n2700), .B0(DmP[42]), .B1(
n2815), .Y(n1689) );
OAI21X2TS U2292 ( .A0(n3017), .A1(n1675), .B0(n1689), .Y(n2617) );
NAND2X1TS U2293 ( .A(n1686), .B(LZA_output[0]), .Y(n1691) );
NAND2X1TS U2294 ( .A(n2953), .B(FSM_selector_B[1]), .Y(n1690) );
NAND2X1TS U2295 ( .A(n1691), .B(n1690), .Y(n2557) );
INVX2TS U2296 ( .A(n2665), .Y(n2255) );
NOR2XLTS U2297 ( .A(n1672), .B(n2255), .Y(n1692) );
AOI22X1TS U2298 ( .A0(Add_Subt_result[11]), .A1(n2773), .B0(DmP[41]), .B1(
n2721), .Y(n1693) );
INVX2TS U2299 ( .A(n1672), .Y(n1744) );
NOR2XLTS U2300 ( .A(n1744), .B(n2255), .Y(n1694) );
AOI22X1TS U2301 ( .A0(Add_Subt_result[9]), .A1(n2693), .B0(DmP[43]), .B1(
n2815), .Y(n1695) );
OAI21X2TS U2302 ( .A0(n2896), .A1(n1579), .B0(n1695), .Y(n2613) );
NOR2XLTS U2303 ( .A(n2665), .B(n1744), .Y(n1696) );
BUFX4TS U2304 ( .A(n1696), .Y(n2626) );
AOI222X1TS U2305 ( .A0(n2617), .A1(n2629), .B0(n1605), .B1(n2628), .C0(n2613), .C1(n2626), .Y(n2245) );
AOI22X1TS U2306 ( .A0(Add_Subt_result[40]), .A1(n2700), .B0(DmP[38]), .B1(
n2815), .Y(n1697) );
OAI21X2TS U2307 ( .A0(n1629), .A1(n2786), .B0(n1697), .Y(n2630) );
AOI22X1TS U2308 ( .A0(Add_Subt_result[15]), .A1(n2693), .B0(DmP[37]), .B1(
n2815), .Y(n1698) );
INVX2TS U2309 ( .A(Add_Subt_result[41]), .Y(n2702) );
BUFX4TS U2310 ( .A(n2933), .Y(n2721) );
AOI22X1TS U2311 ( .A0(Add_Subt_result[13]), .A1(n2693), .B0(DmP[39]), .B1(
n2721), .Y(n1699) );
OAI21X2TS U2312 ( .A0(n2702), .A1(n1579), .B0(n1699), .Y(n2623) );
AOI222X1TS U2313 ( .A0(n2630), .A1(n2629), .B0(n2616), .B1(n2628), .C0(n2623), .C1(n2626), .Y(n2622) );
NAND2X2TS U2314 ( .A(n2650), .B(n1739), .Y(n2590) );
AOI22X1TS U2315 ( .A0(Add_Subt_result[42]), .A1(n2700), .B0(DmP[40]), .B1(
n2815), .Y(n1701) );
NAND2X1TS U2316 ( .A(n2651), .B(n1739), .Y(n2588) );
AOI22X1TS U2317 ( .A0(Add_Subt_result[8]), .A1(n2773), .B0(DmP[44]), .B1(
n2815), .Y(n1702) );
AOI22X1TS U2318 ( .A0(n2671), .A1(n2620), .B0(n1705), .B1(n2605), .Y(n1703)
);
OAI221XLTS U2319 ( .A0(n2666), .A1(n2245), .B0(n2651), .B1(n2622), .C0(n1703), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U2320 ( .A0(Add_Subt_result[7]), .A1(n2206), .B0(DmP[45]), .B1(
n2721), .Y(n1704) );
AOI22X1TS U2321 ( .A0(Add_Subt_result[48]), .A1(n2700), .B0(DmP[46]), .B1(
n2721), .Y(n1706) );
AOI22X1TS U2322 ( .A0(n2800), .A1(n2606), .B0(n2671), .B1(n2617), .Y(n1707)
);
OAI221XLTS U2323 ( .A0(n2666), .A1(n2252), .B0(n2651), .B1(n2619), .C0(n1707), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X1TS U2324 ( .A0(n2613), .A1(n2629), .B0(n2617), .B1(n2628), .C0(n1630), .C1(n1739), .Y(n2211) );
NAND2X2TS U2325 ( .A(n2650), .B(n2626), .Y(n2584) );
INVX2TS U2326 ( .A(n2584), .Y(n2204) );
NAND2X1TS U2327 ( .A(n2651), .B(n2626), .Y(n2581) );
AOI22X1TS U2328 ( .A0(n2793), .A1(n2620), .B0(n2753), .B1(n2605), .Y(n1708)
);
OAI221XLTS U2329 ( .A0(n2666), .A1(n2211), .B0(n2651), .B1(n1713), .C0(n1708), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
AOI22X1TS U2330 ( .A0(Add_Subt_result[17]), .A1(n2693), .B0(DmP[35]), .B1(
n2721), .Y(n1709) );
OAI21X2TS U2331 ( .A0(n3013), .A1(n1579), .B0(n1709), .Y(n2637) );
AOI22X1TS U2332 ( .A0(Add_Subt_result[18]), .A1(n2206), .B0(DmP[34]), .B1(
n2766), .Y(n1710) );
OAI21X2TS U2333 ( .A0(n2916), .A1(n1579), .B0(n1710), .Y(n2642) );
AOI222X1TS U2334 ( .A0(n2637), .A1(n2629), .B0(n2642), .B1(n2628), .C0(n2616), .C1(n1739), .Y(n1719) );
AOI22X1TS U2335 ( .A0(Add_Subt_result[16]), .A1(n2206), .B0(DmP[36]), .B1(
n2721), .Y(n1711) );
AOI22X1TS U2336 ( .A0(n2793), .A1(n1636), .B0(n2753), .B1(n2620), .Y(n1712)
);
OAI221XLTS U2337 ( .A0(n2666), .A1(n1713), .B0(n2651), .B1(n1719), .C0(n1712), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
INVX4TS U2338 ( .A(n2700), .Y(n2723) );
AOI22X1TS U2339 ( .A0(Add_Subt_result[21]), .A1(n2773), .B0(DmP[31]), .B1(
n2721), .Y(n1714) );
AOI22X1TS U2340 ( .A0(Add_Subt_result[22]), .A1(n2693), .B0(DmP[30]), .B1(
n2766), .Y(n1715) );
OAI21X2TS U2341 ( .A0(n1632), .A1(n2723), .B0(n1715), .Y(n2641) );
AOI22X1TS U2342 ( .A0(Add_Subt_result[19]), .A1(n2773), .B0(DmP[33]), .B1(
n2766), .Y(n1716) );
BUFX4TS U2343 ( .A(n2753), .Y(n2796) );
AOI22X1TS U2344 ( .A0(Add_Subt_result[20]), .A1(n2206), .B0(DmP[32]), .B1(
n2766), .Y(n1717) );
AOI22X1TS U2345 ( .A0(n2753), .A1(n1636), .B0(n2793), .B1(n2646), .Y(n1718)
);
OAI221XLTS U2346 ( .A0(n2650), .A1(n1719), .B0(n2651), .B1(n2649), .C0(n1718), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
AOI222X4TS U2347 ( .A0(n2766), .A1(DmP[51]), .B0(Add_Subt_result[1]), .B1(
n2693), .C0(Add_Subt_result[53]), .C1(n2700), .Y(n2597) );
NAND2X2TS U2348 ( .A(n2666), .B(n2628), .Y(n2586) );
INVX2TS U2349 ( .A(n2589), .Y(n1767) );
NAND2X2TS U2350 ( .A(n2650), .B(n2629), .Y(n2582) );
AOI22X1TS U2351 ( .A0(n1767), .A1(n2255), .B0(n1741), .B1(n1593), .Y(n1722)
);
NOR2X2TS U2352 ( .A(n2666), .B(n2589), .Y(n2256) );
INVX2TS U2353 ( .A(n2256), .Y(n1721) );
OAI211XLTS U2354 ( .A0(n2597), .A1(n2586), .B0(n1722), .C0(n1721), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
BUFX4TS U2355 ( .A(n2859), .Y(n2858) );
AOI222X4TS U2356 ( .A0(n2766), .A1(DmP[50]), .B0(Add_Subt_result[2]), .B1(
n2206), .C0(Add_Subt_result[52]), .C1(n2700), .Y(n2596) );
OAI22X1TS U2357 ( .A0(n2596), .A1(n2586), .B0(n2584), .B1(n1625), .Y(n1723)
);
AOI211XLTS U2358 ( .A0(n1739), .A1(n1767), .B0(n2256), .C0(n1723), .Y(n1724)
);
OAI21XLTS U2359 ( .A0(n2597), .A1(n2582), .B0(n1724), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
AOI222X4TS U2360 ( .A0(n2766), .A1(DmP[49]), .B0(Add_Subt_result[3]), .B1(
n2693), .C0(Add_Subt_result[51]), .C1(n2700), .Y(n2591) );
OAI22X1TS U2361 ( .A0(n2591), .A1(n2586), .B0(n2597), .B1(n2584), .Y(n1725)
);
OAI21XLTS U2362 ( .A0(n2596), .A1(n2582), .B0(n1726), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
INVX2TS U2363 ( .A(n2628), .Y(n1729) );
NAND2X2TS U2364 ( .A(n2628), .B(n2651), .Y(n2579) );
OAI22X1TS U2365 ( .A0(n2591), .A1(n2582), .B0(n2579), .B1(n1625), .Y(n1728)
);
AOI222X4TS U2366 ( .A0(n2815), .A1(DmP[48]), .B0(Add_Subt_result[4]), .B1(
n2206), .C0(Add_Subt_result[50]), .C1(n2700), .Y(n2585) );
OAI22X1TS U2367 ( .A0(n2585), .A1(n2586), .B0(n2597), .B1(n2590), .Y(n1727)
);
AOI211XLTS U2368 ( .A0(n2256), .A1(n1729), .B0(n1728), .C0(n1727), .Y(n1730)
);
OAI21XLTS U2369 ( .A0(n2596), .A1(n2584), .B0(n1730), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
NAND2X1TS U2370 ( .A(n2902), .B(n1731), .Y(n1441) );
INVX2TS U2371 ( .A(n2835), .Y(n2833) );
NAND2BXLTS U2372 ( .AN(n2833), .B(add_overflow_flag), .Y(n1732) );
OAI211XLTS U2373 ( .A0(n2835), .A1(n3037), .B0(n2344), .C0(n1732), .Y(n1439)
);
AOI22X1TS U2374 ( .A0(Add_Subt_result[31]), .A1(n2700), .B0(DmP[29]), .B1(
n2815), .Y(n1733) );
AOI22X1TS U2375 ( .A0(Add_Subt_result[24]), .A1(n2206), .B0(DmP[28]), .B1(
n2721), .Y(n1734) );
AOI22X1TS U2376 ( .A0(Add_Subt_result[29]), .A1(n2700), .B0(DmP[27]), .B1(
n2721), .Y(n1735) );
AOI22X1TS U2377 ( .A0(n2671), .A1(n1635), .B0(n2204), .B1(n1634), .Y(n1738)
);
AO22XLTS U2378 ( .A0(FSM_selector_C), .A1(n1667), .B0(n2721), .B1(DmP[25]),
.Y(n1745) );
AOI22X1TS U2379 ( .A0(Add_Subt_result[26]), .A1(n2773), .B0(DmP[26]), .B1(
n2721), .Y(n1736) );
NOR2X1TS U2380 ( .A(n2255), .B(n2658), .Y(n1749) );
AOI22X1TS U2381 ( .A0(n2666), .A1(n1749), .B0(n1705), .B1(n2646), .Y(n1737)
);
OAI211XLTS U2382 ( .A0(n2666), .A1(n2634), .B0(n1738), .C0(n1737), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
INVX2TS U2383 ( .A(n2586), .Y(n1752) );
AOI22X1TS U2384 ( .A0(Add_Subt_result[30]), .A1(n2773), .B0(DmP[22]), .B1(
n2721), .Y(n1740) );
AOI22X1TS U2385 ( .A0(n2753), .A1(n1635), .B0(n1752), .B1(n1653), .Y(n1747)
);
AOI22X1TS U2386 ( .A0(Add_Subt_result[29]), .A1(n2206), .B0(DmP[23]), .B1(
n2766), .Y(n1742) );
AOI22X1TS U2387 ( .A0(Add_Subt_result[28]), .A1(n2773), .B0(DmP[24]), .B1(
n2721), .Y(n1743) );
NAND2X1TS U2388 ( .A(n2666), .B(n2255), .Y(n1753) );
AOI2BB2XLTS U2389 ( .B0(n1741), .B1(n2672), .A0N(n2664), .A1N(n1753), .Y(
n1746) );
OAI211XLTS U2390 ( .A0(n2666), .A1(n2648), .B0(n1747), .C0(n1746), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AOI22X1TS U2391 ( .A0(Add_Subt_result[31]), .A1(n2206), .B0(DmP[21]), .B1(
n2721), .Y(n1748) );
AOI222X1TS U2392 ( .A0(n1653), .A1(n2629), .B0(n1651), .B1(n2628), .C0(n2672), .C1(n2626), .Y(n1766) );
AOI22X1TS U2393 ( .A0(n2671), .A1(n2659), .B0(n2753), .B1(n1634), .Y(n1751)
);
AOI22X1TS U2394 ( .A0(n2800), .A1(n1635), .B0(n1749), .B1(n2651), .Y(n1750)
);
OAI211XLTS U2395 ( .A0(n1766), .A1(n2651), .B0(n1751), .C0(n1750), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U2396 ( .A0(n2790), .A1(n2672), .B0(n1741), .B1(n2659), .Y(n1755)
);
AOI2BB2XLTS U2397 ( .B0(n1705), .B1(n2641), .A0N(n2658), .A1N(n1753), .Y(
n1754) );
OAI211XLTS U2398 ( .A0(n2666), .A1(n2644), .B0(n1755), .C0(n1754), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U2399 ( .A0(n2671), .A1(n1634), .B0(n2793), .B1(n1602), .Y(n1758)
);
NOR2X1TS U2400 ( .A(n2255), .B(n2664), .Y(n2652) );
AOI22X1TS U2401 ( .A0(n2666), .A1(n2652), .B0(n1705), .B1(n2636), .Y(n1757)
);
OAI211XLTS U2402 ( .A0(n2666), .A1(n2639), .B0(n1758), .C0(n1757), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
AOI22X1TS U2403 ( .A0(Add_Subt_result[22]), .A1(n2700), .B0(DmP[20]), .B1(
n2766), .Y(n1759) );
OAI21X4TS U2404 ( .A0(n1632), .A1(n1675), .B0(n1759), .Y(n2688) );
AOI22X1TS U2405 ( .A0(Add_Subt_result[34]), .A1(n2206), .B0(DmP[18]), .B1(
n2766), .Y(n1760) );
OAI21X4TS U2406 ( .A0(n3012), .A1(n2723), .B0(n1760), .Y(n2703) );
AOI22X1TS U2407 ( .A0(n2671), .A1(n2688), .B0(n1741), .B1(n2703), .Y(n1765)
);
AOI22X1TS U2408 ( .A0(Add_Subt_result[21]), .A1(n2700), .B0(DmP[19]), .B1(
n2815), .Y(n1761) );
OAI21X4TS U2409 ( .A0(n1633), .A1(n2786), .B0(n1761), .Y(n2695) );
INVX2TS U2410 ( .A(n1762), .Y(n2709) );
AOI21X1TS U2411 ( .A0(n2204), .A1(n2695), .B0(n1763), .Y(n1764) );
OAI211XLTS U2412 ( .A0(n2666), .A1(n1766), .B0(n1765), .C0(n1764), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X2TS U2413 ( .A0(n1649), .A1(n1686), .B0(n2555), .B1(exp_oper_result[3]), .Y(n1841) );
NAND2X1TS U2414 ( .A(n1775), .B(n1841), .Y(n1772) );
INVX2TS U2415 ( .A(n1775), .Y(n1774) );
INVX2TS U2416 ( .A(n1657), .Y(n1806) );
INVX4TS U2417 ( .A(n1776), .Y(n1872) );
INVX4TS U2418 ( .A(n1776), .Y(n2114) );
NAND2X1TS U2419 ( .A(n1774), .B(n1841), .Y(n1842) );
NOR2X1TS U2420 ( .A(n1776), .B(n1842), .Y(n2454) );
BUFX3TS U2421 ( .A(n2454), .Y(n2476) );
AOI22X1TS U2422 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2559), .B1(n1659), .Y(n1778) );
AOI22X1TS U2423 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n1584), .B0(n1640), .B1(n2457), .Y(n1777) );
OAI211X1TS U2424 ( .A0(n2114), .A1(n1819), .B0(n1778), .C0(n1777), .Y(n1780)
);
AOI22X1TS U2425 ( .A0(n2564), .A1(Sgf_normalized_result[8]), .B0(n1578),
.B1(n1780), .Y(n1779) );
OAI21XLTS U2426 ( .A0(n1786), .A1(n2116), .B0(n1779), .Y(n1450) );
AOI22X1TS U2427 ( .A0(n1770), .A1(Sgf_normalized_result[46]), .B0(n1585),
.B1(n1780), .Y(n1783) );
NAND2X1TS U2428 ( .A(n1578), .B(n1781), .Y(n1782) );
AOI22X1TS U2429 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2559), .B1(n1666), .Y(n1785) );
BUFX4TS U2430 ( .A(n2457), .Y(n2110) );
AOI22X1TS U2431 ( .A0(n2110), .A1(n1646), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1784) );
OAI211X1TS U2432 ( .A0(n1872), .A1(n1786), .B0(n1785), .C0(n1784), .Y(n1817)
);
AOI22X1TS U2433 ( .A0(n2564), .A1(Sgf_normalized_result[14]), .B0(n1578),
.B1(n1817), .Y(n1787) );
OAI21XLTS U2434 ( .A0(n1819), .A1(n2116), .B0(n1787), .Y(n1456) );
AOI22X1TS U2435 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2559), .B1(n1664), .Y(n1791) );
AOI22X1TS U2436 ( .A0(n2110), .A1(n1644), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n1790) );
OAI211X1TS U2437 ( .A0(n1872), .A1(n1834), .B0(n1791), .C0(n1790), .Y(n1826)
);
AOI22X1TS U2438 ( .A0(n2564), .A1(Sgf_normalized_result[12]), .B0(n1578),
.B1(n1826), .Y(n1792) );
OAI21XLTS U2439 ( .A0(n1828), .A1(n2116), .B0(n1792), .Y(n1454) );
AOI22X1TS U2440 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2559), .B1(n1663), .Y(n1796) );
AOI22X1TS U2441 ( .A0(n2110), .A1(n1643), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1795) );
OAI211X1TS U2442 ( .A0(n1872), .A1(n1837), .B0(n1796), .C0(n1795), .Y(n1835)
);
AOI22X1TS U2443 ( .A0(n2564), .A1(Sgf_normalized_result[11]), .B0(n1578),
.B1(n1835), .Y(n1797) );
OAI21XLTS U2444 ( .A0(n1837), .A1(n2116), .B0(n1797), .Y(n1453) );
AOI22X1TS U2445 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2559), .B1(n1665), .Y(n1801) );
AOI22X1TS U2446 ( .A0(n2110), .A1(n1645), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1800) );
OAI211X1TS U2447 ( .A0(n1872), .A1(n1840), .B0(n1801), .C0(n1800), .Y(n1829)
);
AOI22X1TS U2448 ( .A0(n2564), .A1(Sgf_normalized_result[13]), .B0(n1578),
.B1(n1829), .Y(n1802) );
AOI22X1TS U2449 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2559), .B1(n1662), .Y(n1804) );
AOI22X1TS U2450 ( .A0(n2110), .A1(n1642), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1803) );
OAI211X1TS U2451 ( .A0(n1872), .A1(n1828), .B0(n1804), .C0(n1803), .Y(n1832)
);
AOI22X1TS U2452 ( .A0(n2564), .A1(Sgf_normalized_result[10]), .B0(n1578),
.B1(n1832), .Y(n1805) );
OAI21XLTS U2453 ( .A0(n1834), .A1(n2116), .B0(n1805), .Y(n1452) );
AOI22X1TS U2454 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(n2559), .B1(n1647), .Y(n1809) );
AOI22X1TS U2455 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n1584), .B1(n1660), .Y(n1808) );
OAI211X1TS U2456 ( .A0(n2114), .A1(n1822), .B0(n1809), .C0(n1808), .Y(n1823)
);
AOI22X1TS U2457 ( .A0(n2564), .A1(Sgf_normalized_result[7]), .B0(n1578),
.B1(n1823), .Y(n1810) );
OAI21XLTS U2458 ( .A0(n1825), .A1(n2116), .B0(n1810), .Y(n1449) );
AOI22X1TS U2459 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2559), .B1(n1661), .Y(n1812) );
AOI22X1TS U2460 ( .A0(n2110), .A1(n1641), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n1811) );
OAI211X1TS U2461 ( .A0(n2114), .A1(n1831), .B0(n1812), .C0(n1811), .Y(n1838)
);
AOI22X1TS U2462 ( .A0(n2564), .A1(Sgf_normalized_result[9]), .B0(n1578),
.B1(n1838), .Y(n1813) );
OAI21XLTS U2463 ( .A0(n1840), .A1(n2116), .B0(n1813), .Y(n1451) );
AOI22X1TS U2464 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2559), .B1(n1660), .Y(n1815) );
AOI22X1TS U2465 ( .A0(n2110), .A1(n1647), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n1814) );
OAI211X1TS U2466 ( .A0(n1872), .A1(n1825), .B0(n1815), .C0(n1814), .Y(n1820)
);
AOI22X1TS U2467 ( .A0(n2564), .A1(Sgf_normalized_result[15]), .B0(n1578),
.B1(n1820), .Y(n1816) );
OAI21XLTS U2468 ( .A0(n1822), .A1(n2116), .B0(n1816), .Y(n1457) );
AOI22X1TS U2469 ( .A0(n1770), .A1(Sgf_normalized_result[40]), .B0(n1585),
.B1(n1817), .Y(n1818) );
OAI211XLTS U2470 ( .A0(n1819), .A1(n2138), .B0(n1818), .C0(n2136), .Y(n1482)
);
AOI22X1TS U2471 ( .A0(n1770), .A1(Sgf_normalized_result[39]), .B0(n1585),
.B1(n1820), .Y(n1821) );
OAI211XLTS U2472 ( .A0(n1822), .A1(n2138), .B0(n1821), .C0(n2136), .Y(n1481)
);
AOI22X1TS U2473 ( .A0(n1770), .A1(Sgf_normalized_result[47]), .B0(n1585),
.B1(n1823), .Y(n1824) );
OAI211XLTS U2474 ( .A0(n2138), .A1(n1825), .B0(n1824), .C0(n2136), .Y(n1489)
);
AOI22X1TS U2475 ( .A0(n1770), .A1(Sgf_normalized_result[42]), .B0(n1585),
.B1(n1826), .Y(n1827) );
OAI211XLTS U2476 ( .A0(n1828), .A1(n2138), .B0(n1827), .C0(n2136), .Y(n1484)
);
AOI22X1TS U2477 ( .A0(n1770), .A1(Sgf_normalized_result[41]), .B0(n1585),
.B1(n1829), .Y(n1830) );
OAI211XLTS U2478 ( .A0(n1831), .A1(n2138), .B0(n1830), .C0(n2136), .Y(n1483)
);
AOI22X1TS U2479 ( .A0(n1770), .A1(Sgf_normalized_result[44]), .B0(n1585),
.B1(n1832), .Y(n1833) );
OAI211XLTS U2480 ( .A0(n1834), .A1(n2138), .B0(n1833), .C0(n2136), .Y(n1486)
);
AOI22X1TS U2481 ( .A0(n1770), .A1(Sgf_normalized_result[43]), .B0(n1585),
.B1(n1835), .Y(n1836) );
OAI211XLTS U2482 ( .A0(n1837), .A1(n2138), .B0(n1836), .C0(n2136), .Y(n1485)
);
AOI22X1TS U2483 ( .A0(n1770), .A1(Sgf_normalized_result[45]), .B0(n1585),
.B1(n1838), .Y(n1839) );
OAI211XLTS U2484 ( .A0(n1840), .A1(n2138), .B0(n1839), .C0(n2136), .Y(n1487)
);
INVX2TS U2485 ( .A(n1842), .Y(n1868) );
AO22XLTS U2486 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n1843) );
AOI22X1TS U2487 ( .A0(n2560), .A1(n1642), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1845) );
AOI22X1TS U2488 ( .A0(n2110), .A1(n1662), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1844) );
OAI211X1TS U2489 ( .A0(n1872), .A1(n2125), .B0(n1845), .C0(n1844), .Y(n1882)
);
AOI22X1TS U2490 ( .A0(n2564), .A1(Sgf_normalized_result[18]), .B0(n1578),
.B1(n1882), .Y(n1846) );
OAI21XLTS U2491 ( .A0(n2091), .A1(n2116), .B0(n1846), .Y(n1460) );
AO22XLTS U2492 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n1847) );
AOI22X1TS U2493 ( .A0(n2560), .A1(n1645), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1849) );
AOI22X1TS U2494 ( .A0(n2457), .A1(n1665), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1848) );
OAI211X1TS U2495 ( .A0(n1872), .A1(n2119), .B0(n1849), .C0(n1848), .Y(n1878)
);
AOI22X1TS U2496 ( .A0(n2564), .A1(Sgf_normalized_result[21]), .B0(n1578),
.B1(n1878), .Y(n1850) );
OAI21XLTS U2497 ( .A0(n2087), .A1(n2116), .B0(n1850), .Y(n1463) );
AO22XLTS U2498 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1851) );
AOI22X1TS U2499 ( .A0(n2560), .A1(n1641), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n1853) );
AOI22X1TS U2500 ( .A0(n2110), .A1(n1661), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n1852) );
OAI211X1TS U2501 ( .A0(n2114), .A1(n2128), .B0(n1853), .C0(n1852), .Y(n1880)
);
AOI22X1TS U2502 ( .A0(n2564), .A1(Sgf_normalized_result[17]), .B0(n1578),
.B1(n1880), .Y(n1854) );
OAI21XLTS U2503 ( .A0(n2104), .A1(n2116), .B0(n1854), .Y(n1459) );
AOI22X1TS U2504 ( .A0(n2110), .A1(n1666), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1857) );
AOI22X1TS U2505 ( .A0(n2560), .A1(n1646), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1856) );
OAI211X1TS U2506 ( .A0(n1872), .A1(n2139), .B0(n1857), .C0(n1856), .Y(n1884)
);
AOI22X1TS U2507 ( .A0(n2564), .A1(Sgf_normalized_result[22]), .B0(n1578),
.B1(n1884), .Y(n1858) );
OAI21XLTS U2508 ( .A0(n2100), .A1(n2116), .B0(n1858), .Y(n1464) );
AO22XLTS U2509 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1859) );
AOI22X1TS U2510 ( .A0(n2560), .A1(n1644), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n1861) );
AOI22X1TS U2511 ( .A0(n2110), .A1(n1664), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n1860) );
OAI211X1TS U2512 ( .A0(n1872), .A1(n2122), .B0(n1861), .C0(n1860), .Y(n1876)
);
AOI22X1TS U2513 ( .A0(n2564), .A1(Sgf_normalized_result[20]), .B0(n1578),
.B1(n1876), .Y(n1862) );
OAI21XLTS U2514 ( .A0(n2095), .A1(n2116), .B0(n1862), .Y(n1462) );
AO22XLTS U2515 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1863) );
AOI22X1TS U2516 ( .A0(n2560), .A1(n1643), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1865) );
AOI22X1TS U2517 ( .A0(n2110), .A1(n1663), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1864) );
OAI211X1TS U2518 ( .A0(n1872), .A1(n2131), .B0(n1865), .C0(n1864), .Y(n1874)
);
AOI22X1TS U2519 ( .A0(n2564), .A1(Sgf_normalized_result[19]), .B0(n1578),
.B1(n1874), .Y(n1866) );
OAI21XLTS U2520 ( .A0(n2108), .A1(n2116), .B0(n1866), .Y(n1461) );
AOI22X1TS U2521 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n2559), .B0(n1773), .B1(n1640), .Y(n1871) );
AOI22X1TS U2522 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n1584), .B0(n2457), .B1(n1659), .Y(n1870) );
OAI211X1TS U2523 ( .A0(n1872), .A1(n2134), .B0(n1871), .C0(n1870), .Y(n1886)
);
AOI22X1TS U2524 ( .A0(n2564), .A1(Sgf_normalized_result[16]), .B0(n1578),
.B1(n1886), .Y(n1873) );
OAI21XLTS U2525 ( .A0(n2113), .A1(n2116), .B0(n1873), .Y(n1458) );
AOI22X1TS U2526 ( .A0(n1770), .A1(Sgf_normalized_result[35]), .B0(n1585),
.B1(n1874), .Y(n1875) );
OAI211XLTS U2527 ( .A0(n2108), .A1(n2138), .B0(n1875), .C0(n2136), .Y(n1477)
);
AOI22X1TS U2528 ( .A0(n1770), .A1(Sgf_normalized_result[34]), .B0(n1585),
.B1(n1876), .Y(n1877) );
OAI211XLTS U2529 ( .A0(n2095), .A1(n2138), .B0(n1877), .C0(n2136), .Y(n1476)
);
AOI22X1TS U2530 ( .A0(n1770), .A1(Sgf_normalized_result[33]), .B0(n1585),
.B1(n1878), .Y(n1879) );
OAI211XLTS U2531 ( .A0(n2087), .A1(n2138), .B0(n1879), .C0(n2136), .Y(n1475)
);
AOI22X1TS U2532 ( .A0(n1770), .A1(Sgf_normalized_result[37]), .B0(n1585),
.B1(n1880), .Y(n1881) );
OAI211XLTS U2533 ( .A0(n2104), .A1(n2138), .B0(n1881), .C0(n2136), .Y(n1479)
);
AOI22X1TS U2534 ( .A0(n1770), .A1(Sgf_normalized_result[36]), .B0(n1585),
.B1(n1882), .Y(n1883) );
OAI211XLTS U2535 ( .A0(n2091), .A1(n2138), .B0(n1883), .C0(n2136), .Y(n1478)
);
AOI22X1TS U2536 ( .A0(n2564), .A1(Sgf_normalized_result[32]), .B0(n1585),
.B1(n1884), .Y(n1885) );
AOI22X1TS U2537 ( .A0(n1770), .A1(Sgf_normalized_result[38]), .B0(n1585),
.B1(n1886), .Y(n1887) );
OAI211XLTS U2538 ( .A0(n2113), .A1(n2138), .B0(n1887), .C0(n2136), .Y(n1480)
);
NOR2XLTS U2539 ( .A(n3073), .B(intDY[53]), .Y(n1888) );
OAI22X1TS U2540 ( .A0(n3072), .A1(intDY[55]), .B0(intDY[54]), .B1(n2967),
.Y(n2007) );
AOI211X1TS U2541 ( .A0(intDX[52]), .A1(n2950), .B0(n1888), .C0(n2007), .Y(
n2009) );
NOR2BX1TS U2542 ( .AN(intDX[56]), .B(intDY[56]), .Y(n1889) );
NOR2X1TS U2543 ( .A(n2996), .B(intDY[57]), .Y(n1961) );
NAND2BXLTS U2544 ( .AN(intDY[62]), .B(intDX[62]), .Y(n1971) );
NAND2X1TS U2545 ( .A(n2941), .B(intDX[61]), .Y(n1967) );
OAI211X1TS U2546 ( .A0(intDY[60]), .A1(n3001), .B0(n1971), .C0(n1967), .Y(
n1973) );
OAI21X1TS U2547 ( .A0(intDY[58]), .A1(n3002), .B0(n1963), .Y(n1965) );
NOR2X1TS U2548 ( .A(n1654), .B(intDY[49]), .Y(n2010) );
OAI21X1TS U2549 ( .A0(intDY[50]), .A1(n3045), .B0(n2012), .Y(n2016) );
AOI211X1TS U2550 ( .A0(intDX[48]), .A1(n2948), .B0(n2010), .C0(n2016), .Y(
n1890) );
NAND3X1TS U2551 ( .A(n2009), .B(n2018), .C(n1890), .Y(n2026) );
NOR2BX1TS U2552 ( .AN(intDX[39]), .B(intDY[39]), .Y(n2001) );
AOI21X1TS U2553 ( .A0(intDX[38]), .A1(n2945), .B0(n2001), .Y(n2000) );
NAND2X1TS U2554 ( .A(n2951), .B(intDX[37]), .Y(n1989) );
OAI211X1TS U2555 ( .A0(intDY[36]), .A1(n3003), .B0(n2000), .C0(n1989), .Y(
n1991) );
NOR2X1TS U2556 ( .A(n2997), .B(intDY[45]), .Y(n1975) );
OAI21X1TS U2557 ( .A0(intDY[46]), .A1(n2989), .B0(n1974), .Y(n1984) );
OA22X1TS U2558 ( .A0(n2891), .A1(intDY[42]), .B0(n2998), .B1(intDY[43]), .Y(
n1980) );
NAND4XLTS U2559 ( .A(n1982), .B(n1980), .C(n1892), .D(n1891), .Y(n2024) );
OA22X1TS U2560 ( .A0(n2892), .A1(intDY[34]), .B0(n2999), .B1(intDY[35]), .Y(
n1995) );
OAI211XLTS U2561 ( .A0(n3000), .A1(intDY[33]), .B0(n1893), .C0(n1995), .Y(
n1894) );
NOR4X1TS U2562 ( .A(n2026), .B(n1991), .C(n2024), .D(n1894), .Y(n2030) );
OA22X1TS U2563 ( .A0(n2970), .A1(intDY[30]), .B0(n3074), .B1(intDY[31]), .Y(
n1905) );
OAI21XLTS U2564 ( .A0(intDY[29]), .A1(n2961), .B0(intDY[28]), .Y(n1895) );
OAI2BB2XLTS U2565 ( .B0(intDX[28]), .B1(n1895), .A0N(intDY[29]), .A1N(n2961),
.Y(n1904) );
OAI21X1TS U2566 ( .A0(intDY[26]), .A1(n3041), .B0(n1898), .Y(n1956) );
NOR2X1TS U2567 ( .A(n3040), .B(intDY[25]), .Y(n1953) );
NOR2XLTS U2568 ( .A(n1953), .B(intDX[24]), .Y(n1897) );
AOI22X1TS U2569 ( .A0(n1897), .A1(intDY[24]), .B0(intDY[25]), .B1(n3040),
.Y(n1900) );
OAI32X1TS U2570 ( .A0(n1956), .A1(n1955), .A2(n1900), .B0(n1899), .B1(n1955),
.Y(n1903) );
OAI21XLTS U2571 ( .A0(intDY[31]), .A1(n3074), .B0(intDY[30]), .Y(n1901) );
OAI2BB2XLTS U2572 ( .B0(intDX[30]), .B1(n1901), .A0N(intDY[31]), .A1N(n3074),
.Y(n1902) );
AOI211X1TS U2573 ( .A0(n1905), .A1(n1904), .B0(n1903), .C0(n1902), .Y(n1960)
);
OA22X1TS U2574 ( .A0(n2973), .A1(intDY[22]), .B0(n3075), .B1(intDY[23]), .Y(
n1952) );
OA22X1TS U2575 ( .A0(n2976), .A1(intDY[14]), .B0(n3077), .B1(intDY[15]), .Y(
n1933) );
OAI2BB1X1TS U2576 ( .A0N(n2952), .A1N(intDX[5]), .B0(intDY[4]), .Y(n1908) );
OAI22X1TS U2577 ( .A0(intDX[4]), .A1(n1908), .B0(n2952), .B1(intDX[5]), .Y(
n1919) );
OAI2BB1X1TS U2578 ( .A0N(n2885), .A1N(intDX[7]), .B0(intDY[6]), .Y(n1909) );
OAI22X1TS U2579 ( .A0(intDX[6]), .A1(n1909), .B0(n2885), .B1(intDX[7]), .Y(
n1918) );
AOI2BB2XLTS U2580 ( .B0(intDX[1]), .B1(n2939), .A0N(intDY[0]), .A1N(n1910),
.Y(n1911) );
OAI211XLTS U2581 ( .A0(n2960), .A1(intDY[3]), .B0(n1912), .C0(n1911), .Y(
n1915) );
OAI21XLTS U2582 ( .A0(intDY[3]), .A1(n2960), .B0(intDY[2]), .Y(n1913) );
AOI2BB2XLTS U2583 ( .B0(intDY[3]), .B1(n2960), .A0N(intDX[2]), .A1N(n1913),
.Y(n1914) );
AOI222X1TS U2584 ( .A0(intDX[4]), .A1(n2883), .B0(intDX[5]), .B1(n2952),
.C0(n1915), .C1(n1914), .Y(n1917) );
AOI22X1TS U2585 ( .A0(intDX[7]), .A1(n2885), .B0(intDX[6]), .B1(n2957), .Y(
n1916) );
OAI32X1TS U2586 ( .A0(n1919), .A1(n1918), .A2(n1917), .B0(n1916), .B1(n1918),
.Y(n1936) );
NOR2X1TS U2587 ( .A(n3042), .B(intDY[11]), .Y(n1921) );
AOI21X1TS U2588 ( .A0(intDX[10]), .A1(n2949), .B0(n1921), .Y(n1926) );
OAI211XLTS U2589 ( .A0(intDY[8]), .A1(n2963), .B0(n1923), .C0(n1926), .Y(
n1935) );
OAI21XLTS U2590 ( .A0(intDY[13]), .A1(n2962), .B0(intDY[12]), .Y(n1920) );
OAI2BB2XLTS U2591 ( .B0(intDX[12]), .B1(n1920), .A0N(intDY[13]), .A1N(n2962),
.Y(n1932) );
NOR2XLTS U2592 ( .A(n1921), .B(intDX[10]), .Y(n1922) );
AOI22X1TS U2593 ( .A0(intDY[11]), .A1(n3042), .B0(intDY[10]), .B1(n1922),
.Y(n1928) );
NAND3XLTS U2594 ( .A(n2963), .B(n1923), .C(intDY[8]), .Y(n1925) );
NAND2BXLTS U2595 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1924) );
AOI21X1TS U2596 ( .A0(n1925), .A1(n1924), .B0(n1937), .Y(n1927) );
OAI2BB2XLTS U2597 ( .B0(n1928), .B1(n1937), .A0N(n1927), .A1N(n1926), .Y(
n1931) );
OAI21XLTS U2598 ( .A0(intDY[15]), .A1(n3077), .B0(intDY[14]), .Y(n1929) );
OAI2BB2XLTS U2599 ( .B0(intDX[14]), .B1(n1929), .A0N(intDY[15]), .A1N(n3077),
.Y(n1930) );
AOI211X1TS U2600 ( .A0(n1933), .A1(n1932), .B0(n1931), .C0(n1930), .Y(n1934)
);
OAI31X1TS U2601 ( .A0(n1937), .A1(n1936), .A2(n1935), .B0(n1934), .Y(n1939)
);
NOR2X1TS U2602 ( .A(n3043), .B(intDY[17]), .Y(n1941) );
OAI21X1TS U2603 ( .A0(intDY[18]), .A1(n3076), .B0(n1943), .Y(n1947) );
AOI211XLTS U2604 ( .A0(intDX[16]), .A1(n2956), .B0(n1941), .C0(n1947), .Y(
n1938) );
NAND3BXLTS U2605 ( .AN(n1946), .B(n1939), .C(n1938), .Y(n1959) );
OAI21XLTS U2606 ( .A0(intDY[21]), .A1(n2981), .B0(intDY[20]), .Y(n1940) );
OAI2BB2XLTS U2607 ( .B0(intDX[20]), .B1(n1940), .A0N(intDY[21]), .A1N(n2981),
.Y(n1951) );
AOI22X1TS U2608 ( .A0(n1942), .A1(intDY[16]), .B0(intDY[17]), .B1(n3043),
.Y(n1945) );
OAI32X1TS U2609 ( .A0(n1947), .A1(n1946), .A2(n1945), .B0(n1944), .B1(n1946),
.Y(n1950) );
OAI21XLTS U2610 ( .A0(intDY[23]), .A1(n3075), .B0(intDY[22]), .Y(n1948) );
OAI2BB2XLTS U2611 ( .B0(intDX[22]), .B1(n1948), .A0N(intDY[23]), .A1N(n3075),
.Y(n1949) );
AOI211X1TS U2612 ( .A0(n1952), .A1(n1951), .B0(n1950), .C0(n1949), .Y(n1958)
);
NOR2BX1TS U2613 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1954) );
OR4X2TS U2614 ( .A(n1956), .B(n1955), .C(n1954), .D(n1953), .Y(n1957) );
AOI32X1TS U2615 ( .A0(n1960), .A1(n1959), .A2(n1958), .B0(n1957), .B1(n1960),
.Y(n2029) );
NOR2XLTS U2616 ( .A(n1961), .B(intDX[56]), .Y(n1962) );
AOI22X1TS U2617 ( .A0(intDY[57]), .A1(n2996), .B0(intDY[56]), .B1(n1962),
.Y(n1966) );
OA21XLTS U2618 ( .A0(n1966), .A1(n1965), .B0(n1964), .Y(n1972) );
NAND2BXLTS U2619 ( .AN(intDX[62]), .B(intDY[62]), .Y(n1969) );
NAND3XLTS U2620 ( .A(n3001), .B(n1967), .C(intDY[60]), .Y(n1968) );
OAI211XLTS U2621 ( .A0(intDX[61]), .A1(n2941), .B0(n1969), .C0(n1968), .Y(
n1970) );
NOR2BX1TS U2622 ( .AN(n1974), .B(intDX[46]), .Y(n1988) );
NOR2XLTS U2623 ( .A(n1975), .B(intDX[44]), .Y(n1976) );
AOI22X1TS U2624 ( .A0(intDY[45]), .A1(n2997), .B0(intDY[44]), .B1(n1976),
.Y(n1985) );
OAI21XLTS U2625 ( .A0(intDY[41]), .A1(n1652), .B0(intDY[40]), .Y(n1977) );
OAI2BB2XLTS U2626 ( .B0(intDX[40]), .B1(n1977), .A0N(intDY[41]), .A1N(n1652),
.Y(n1981) );
OAI21XLTS U2627 ( .A0(intDY[43]), .A1(n2998), .B0(intDY[42]), .Y(n1978) );
OAI2BB2XLTS U2628 ( .B0(intDX[42]), .B1(n1978), .A0N(intDY[43]), .A1N(n2998),
.Y(n1979) );
AOI32X1TS U2629 ( .A0(n1982), .A1(n1981), .A2(n1980), .B0(n1979), .B1(n1982),
.Y(n1983) );
NOR2BX1TS U2630 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1986) );
AOI211X1TS U2631 ( .A0(intDY[46]), .A1(n1988), .B0(n1987), .C0(n1986), .Y(
n2025) );
NAND3XLTS U2632 ( .A(n3003), .B(n1989), .C(intDY[36]), .Y(n1990) );
OAI21XLTS U2633 ( .A0(intDX[37]), .A1(n2951), .B0(n1990), .Y(n1999) );
INVX2TS U2634 ( .A(n1991), .Y(n1997) );
OAI21XLTS U2635 ( .A0(intDY[33]), .A1(n3000), .B0(intDY[32]), .Y(n1992) );
OAI2BB2XLTS U2636 ( .B0(intDX[32]), .B1(n1992), .A0N(intDY[33]), .A1N(n3000),
.Y(n1996) );
OAI2BB2XLTS U2637 ( .B0(intDX[34]), .B1(n1993), .A0N(intDY[35]), .A1N(n2999),
.Y(n1994) );
AOI32X1TS U2638 ( .A0(n1997), .A1(n1996), .A2(n1995), .B0(n1994), .B1(n1997),
.Y(n1998) );
OAI2BB1X1TS U2639 ( .A0N(n2000), .A1N(n1999), .B0(n1998), .Y(n2005) );
NOR2BX1TS U2640 ( .AN(intDY[39]), .B(intDX[39]), .Y(n2004) );
NOR3X1TS U2641 ( .A(n2945), .B(n2001), .C(intDX[38]), .Y(n2003) );
INVX2TS U2642 ( .A(n2026), .Y(n2002) );
OAI31X1TS U2643 ( .A0(n2005), .A1(n2004), .A2(n2003), .B0(n2002), .Y(n2023)
);
OAI21XLTS U2644 ( .A0(intDY[53]), .A1(n3073), .B0(intDY[52]), .Y(n2006) );
AOI2BB2XLTS U2645 ( .B0(intDY[53]), .B1(n3073), .A0N(intDX[52]), .A1N(n2006),
.Y(n2008) );
NOR2XLTS U2646 ( .A(n2008), .B(n2007), .Y(n2021) );
INVX2TS U2647 ( .A(n2009), .Y(n2015) );
AOI22X1TS U2648 ( .A0(intDY[49]), .A1(n1654), .B0(intDY[48]), .B1(n2011),
.Y(n2014) );
OAI32X1TS U2649 ( .A0(n2016), .A1(n2015), .A2(n2014), .B0(n2013), .B1(n2015),
.Y(n2020) );
OAI21XLTS U2650 ( .A0(intDY[55]), .A1(n3072), .B0(intDY[54]), .Y(n2017) );
OAI2BB2XLTS U2651 ( .B0(intDX[54]), .B1(n2017), .A0N(intDY[55]), .A1N(n3072),
.Y(n2019) );
OAI31X1TS U2652 ( .A0(n2021), .A1(n2020), .A2(n2019), .B0(n2018), .Y(n2022)
);
OAI221X1TS U2653 ( .A0(n2026), .A1(n2025), .B0(n2024), .B1(n2023), .C0(n2022), .Y(n2027) );
AOI211X2TS U2654 ( .A0(n2030), .A1(n2029), .B0(n2028), .C0(n2027), .Y(n2864)
);
CLKBUFX2TS U2655 ( .A(n2868), .Y(n2164) );
NOR2X1TS U2656 ( .A(n2864), .B(n2865), .Y(n2042) );
AOI22X1TS U2657 ( .A0(n2072), .A1(intDY[3]), .B0(DmP[3]), .B1(n2223), .Y(
n2031) );
OAI21XLTS U2658 ( .A0(n2960), .A1(n2035), .B0(n2031), .Y(n1108) );
AOI22X1TS U2659 ( .A0(n2072), .A1(intDY[4]), .B0(DmP[4]), .B1(n2238), .Y(
n2032) );
OAI21XLTS U2660 ( .A0(n2980), .A1(n2035), .B0(n2032), .Y(n1109) );
AOI22X1TS U2661 ( .A0(n2072), .A1(intDY[2]), .B0(DmP[2]), .B1(n2238), .Y(
n2033) );
OAI21XLTS U2662 ( .A0(n2887), .A1(n2035), .B0(n2033), .Y(n1107) );
AOI22X1TS U2663 ( .A0(n2072), .A1(intDY[5]), .B0(DmP[5]), .B1(n2238), .Y(
n2034) );
OAI21XLTS U2664 ( .A0(n2884), .A1(n2035), .B0(n2034), .Y(n1110) );
AOI22X1TS U2665 ( .A0(n2083), .A1(intDY[12]), .B0(DMP[12]), .B1(n2238), .Y(
n2036) );
OAI21XLTS U2666 ( .A0(n2977), .A1(n2041), .B0(n2036), .Y(n1181) );
AOI22X1TS U2667 ( .A0(n2083), .A1(intDY[17]), .B0(DMP[17]), .B1(n2226), .Y(
n2037) );
OAI21XLTS U2668 ( .A0(n3043), .A1(n2041), .B0(n2037), .Y(n1186) );
AOI22X1TS U2669 ( .A0(n2083), .A1(intDY[11]), .B0(DMP[11]), .B1(n2228), .Y(
n2038) );
OAI21XLTS U2670 ( .A0(n3042), .A1(n2041), .B0(n2038), .Y(n1180) );
AOI22X1TS U2671 ( .A0(n2083), .A1(intDY[13]), .B0(DMP[13]), .B1(n2223), .Y(
n2039) );
OAI21XLTS U2672 ( .A0(n2962), .A1(n2041), .B0(n2039), .Y(n1182) );
AOI22X1TS U2673 ( .A0(n2083), .A1(intDY[15]), .B0(DMP[15]), .B1(n2223), .Y(
n2040) );
OAI21XLTS U2674 ( .A0(n3077), .A1(n2041), .B0(n2040), .Y(n1184) );
CLKBUFX3TS U2675 ( .A(n2041), .Y(n2237) );
AOI22X1TS U2676 ( .A0(n2042), .A1(intDY[1]), .B0(DMP[1]), .B1(n2223), .Y(
n2043) );
OAI21XLTS U2677 ( .A0(n2893), .A1(n2237), .B0(n2043), .Y(n1170) );
BUFX3TS U2678 ( .A(n2035), .Y(n2177) );
AOI22X1TS U2679 ( .A0(n2072), .A1(intDY[58]), .B0(DmP[58]), .B1(n2226), .Y(
n2044) );
OAI21XLTS U2680 ( .A0(n3002), .A1(n2177), .B0(n2044), .Y(n1163) );
AOI22X1TS U2681 ( .A0(n2072), .A1(intDY[0]), .B0(DmP[0]), .B1(n2226), .Y(
n2045) );
OAI21XLTS U2682 ( .A0(n2964), .A1(n2177), .B0(n2045), .Y(n1105) );
BUFX4TS U2683 ( .A(n2041), .Y(n2241) );
AOI22X1TS U2684 ( .A0(n2083), .A1(intDY[28]), .B0(DMP[28]), .B1(n2228), .Y(
n2046) );
OAI21XLTS U2685 ( .A0(n2971), .A1(n2241), .B0(n2046), .Y(n1197) );
AOI22X1TS U2686 ( .A0(n2083), .A1(intDY[29]), .B0(DMP[29]), .B1(n2223), .Y(
n2047) );
AOI22X1TS U2687 ( .A0(n2083), .A1(intDY[35]), .B0(DMP[35]), .B1(n2228), .Y(
n2048) );
OAI21XLTS U2688 ( .A0(n2999), .A1(n2241), .B0(n2048), .Y(n1204) );
AOI22X1TS U2689 ( .A0(n2083), .A1(intDY[32]), .B0(DMP[32]), .B1(n2228), .Y(
n2049) );
OAI21XLTS U2690 ( .A0(n2969), .A1(n2241), .B0(n2049), .Y(n1201) );
AOI22X1TS U2691 ( .A0(n2083), .A1(intDY[33]), .B0(DMP[33]), .B1(n2223), .Y(
n2050) );
OAI21XLTS U2692 ( .A0(n3000), .A1(n2241), .B0(n2050), .Y(n1202) );
AOI22X1TS U2693 ( .A0(n2083), .A1(intDY[31]), .B0(DMP[31]), .B1(n2228), .Y(
n2051) );
OAI21XLTS U2694 ( .A0(n3074), .A1(n2241), .B0(n2051), .Y(n1200) );
AOI22X1TS U2695 ( .A0(n2083), .A1(intDY[30]), .B0(DMP[30]), .B1(n2228), .Y(
n2052) );
OAI21XLTS U2696 ( .A0(n2970), .A1(n2241), .B0(n2052), .Y(n1199) );
AOI22X1TS U2697 ( .A0(n2083), .A1(intDY[34]), .B0(DMP[34]), .B1(n2223), .Y(
n2053) );
OAI21XLTS U2698 ( .A0(n2892), .A1(n2241), .B0(n2053), .Y(n1203) );
AOI22X1TS U2699 ( .A0(n2074), .A1(intDY[12]), .B0(DmP[12]), .B1(n2865), .Y(
n2054) );
OAI21XLTS U2700 ( .A0(n2977), .A1(n2177), .B0(n2054), .Y(n1117) );
AOI22X1TS U2701 ( .A0(n2074), .A1(intDY[57]), .B0(DmP[57]), .B1(n2238), .Y(
n2055) );
OAI21XLTS U2702 ( .A0(n2996), .A1(n2177), .B0(n2055), .Y(n1162) );
AOI22X1TS U2703 ( .A0(n2074), .A1(intDY[59]), .B0(DmP[59]), .B1(n2226), .Y(
n2056) );
OAI21XLTS U2704 ( .A0(n2895), .A1(n2177), .B0(n2056), .Y(n1164) );
AOI22X1TS U2705 ( .A0(n2074), .A1(intDY[60]), .B0(DmP[60]), .B1(n2238), .Y(
n2057) );
OAI21XLTS U2706 ( .A0(n3001), .A1(n2177), .B0(n2057), .Y(n1165) );
AOI22X1TS U2707 ( .A0(n2074), .A1(intDY[56]), .B0(DmP[56]), .B1(n2238), .Y(
n2058) );
OAI21XLTS U2708 ( .A0(n2966), .A1(n2177), .B0(n2058), .Y(n1161) );
BUFX3TS U2709 ( .A(n2035), .Y(n2153) );
AOI22X1TS U2710 ( .A0(n2072), .A1(intDY[11]), .B0(DmP[11]), .B1(n2865), .Y(
n2059) );
OAI21XLTS U2711 ( .A0(n3042), .A1(n2153), .B0(n2059), .Y(n1116) );
AOI22X1TS U2712 ( .A0(n2074), .A1(intDY[14]), .B0(DmP[14]), .B1(n2226), .Y(
n2060) );
OAI21XLTS U2713 ( .A0(n2976), .A1(n2153), .B0(n2060), .Y(n1119) );
AOI22X1TS U2714 ( .A0(n2072), .A1(intDY[10]), .B0(DmP[10]), .B1(n2226), .Y(
n2061) );
AOI22X1TS U2715 ( .A0(n2074), .A1(intDY[16]), .B0(DmP[16]), .B1(n2238), .Y(
n2062) );
OAI21XLTS U2716 ( .A0(n2975), .A1(n2153), .B0(n2062), .Y(n1121) );
AOI22X1TS U2717 ( .A0(n2074), .A1(intDY[15]), .B0(DmP[15]), .B1(n2226), .Y(
n2063) );
OAI21XLTS U2718 ( .A0(n3077), .A1(n2153), .B0(n2063), .Y(n1120) );
BUFX3TS U2719 ( .A(n2035), .Y(n2192) );
AOI22X1TS U2720 ( .A0(n2074), .A1(intDY[53]), .B0(DmP[53]), .B1(n2226), .Y(
n2064) );
OAI21XLTS U2721 ( .A0(n3073), .A1(n2192), .B0(n2064), .Y(n1158) );
BUFX3TS U2722 ( .A(n2035), .Y(n2188) );
AOI22X1TS U2723 ( .A0(n2074), .A1(intDY[62]), .B0(DmP[62]), .B1(n2223), .Y(
n2065) );
OAI21XLTS U2724 ( .A0(n2894), .A1(n2188), .B0(n2065), .Y(n1104) );
AOI22X1TS U2725 ( .A0(n2072), .A1(intDY[1]), .B0(DmP[1]), .B1(n2226), .Y(
n2066) );
OAI21XLTS U2726 ( .A0(n2893), .A1(n2188), .B0(n2066), .Y(n1106) );
AOI22X1TS U2727 ( .A0(n2072), .A1(intDY[7]), .B0(DmP[7]), .B1(n2238), .Y(
n2067) );
OAI21XLTS U2728 ( .A0(n2955), .A1(n2192), .B0(n2067), .Y(n1112) );
AOI22X1TS U2729 ( .A0(n2189), .A1(intDY[13]), .B0(DmP[13]), .B1(n2238), .Y(
n2068) );
OAI21XLTS U2730 ( .A0(n2962), .A1(n2188), .B0(n2068), .Y(n1118) );
AOI22X1TS U2731 ( .A0(n2074), .A1(intDY[52]), .B0(DmP[52]), .B1(n2226), .Y(
n2069) );
AOI22X1TS U2732 ( .A0(n2072), .A1(intDY[9]), .B0(DmP[9]), .B1(n2238), .Y(
n2070) );
OAI21XLTS U2733 ( .A0(n2886), .A1(n2188), .B0(n2070), .Y(n1114) );
AOI22X1TS U2734 ( .A0(n2072), .A1(intDY[8]), .B0(DmP[8]), .B1(n2238), .Y(
n2071) );
OAI21XLTS U2735 ( .A0(n2963), .A1(n2192), .B0(n2071), .Y(n1113) );
AOI22X1TS U2736 ( .A0(n2072), .A1(intDY[6]), .B0(DmP[6]), .B1(n2226), .Y(
n2073) );
OAI21XLTS U2737 ( .A0(n2979), .A1(n2192), .B0(n2073), .Y(n1111) );
AOI22X1TS U2738 ( .A0(n2162), .A1(intDY[54]), .B0(DmP[54]), .B1(n2238), .Y(
n2075) );
OAI21XLTS U2739 ( .A0(n2967), .A1(n2192), .B0(n2075), .Y(n1159) );
AOI22X1TS U2740 ( .A0(n2083), .A1(intDY[25]), .B0(DMP[25]), .B1(n2223), .Y(
n2076) );
OAI21XLTS U2741 ( .A0(n3040), .A1(n1577), .B0(n2076), .Y(n1194) );
AOI22X1TS U2742 ( .A0(n2083), .A1(intDY[23]), .B0(DMP[23]), .B1(n2228), .Y(
n2077) );
OAI21XLTS U2743 ( .A0(n3075), .A1(n1577), .B0(n2077), .Y(n1192) );
AOI22X1TS U2744 ( .A0(n2083), .A1(intDY[24]), .B0(DMP[24]), .B1(n2228), .Y(
n2078) );
OAI21XLTS U2745 ( .A0(n2972), .A1(n1577), .B0(n2078), .Y(n1193) );
AOI22X1TS U2746 ( .A0(n2083), .A1(intDY[20]), .B0(DMP[20]), .B1(n2228), .Y(
n2079) );
OAI21XLTS U2747 ( .A0(n2974), .A1(n1577), .B0(n2079), .Y(n1189) );
AOI22X1TS U2748 ( .A0(n2083), .A1(intDY[27]), .B0(DMP[27]), .B1(n2223), .Y(
n2080) );
OAI21XLTS U2749 ( .A0(n2984), .A1(n1577), .B0(n2080), .Y(n1196) );
AOI22X1TS U2750 ( .A0(n2083), .A1(intDY[18]), .B0(DMP[18]), .B1(n2223), .Y(
n2081) );
OAI21XLTS U2751 ( .A0(n3076), .A1(n1577), .B0(n2081), .Y(n1187) );
AOI22X1TS U2752 ( .A0(n2083), .A1(intDY[26]), .B0(DMP[26]), .B1(n2228), .Y(
n2082) );
OAI21XLTS U2753 ( .A0(n3041), .A1(n1577), .B0(n2082), .Y(n1195) );
AOI22X1TS U2754 ( .A0(n2083), .A1(intDY[21]), .B0(DMP[21]), .B1(n2190), .Y(
n2084) );
OAI21XLTS U2755 ( .A0(n2981), .A1(n1577), .B0(n2084), .Y(n1190) );
AOI22X1TS U2756 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n2559), .B1(n1641), .Y(n2086) );
AOI22X1TS U2757 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n1584), .B1(n1661), .Y(n2085) );
OAI211X1TS U2758 ( .A0(n2114), .A1(n2087), .B0(n2086), .C0(n2085), .Y(n2117)
);
AOI22X1TS U2759 ( .A0(n2564), .A1(Sgf_normalized_result[1]), .B0(n1578),
.B1(n2117), .Y(n2088) );
OAI21XLTS U2760 ( .A0(n2119), .A1(n2116), .B0(n2088), .Y(n1443) );
AOI22X1TS U2761 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n2476), .B1(n1644), .Y(n2090) );
AOI22X1TS U2762 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n1584), .B1(n1664), .Y(n2089) );
OAI211X1TS U2763 ( .A0(n2114), .A1(n2091), .B0(n2090), .C0(n2089), .Y(n2123)
);
AOI22X1TS U2764 ( .A0(n2564), .A1(Sgf_normalized_result[4]), .B0(n1578),
.B1(n2123), .Y(n2092) );
OAI21XLTS U2765 ( .A0(n2125), .A1(n2116), .B0(n2092), .Y(n1446) );
AOI22X1TS U2766 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n2476), .B1(n1642), .Y(n2094) );
AOI22X1TS U2767 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n1584), .B1(n1662), .Y(n2093) );
OAI211X1TS U2768 ( .A0(n2114), .A1(n2095), .B0(n2094), .C0(n2093), .Y(n2120)
);
AOI22X1TS U2769 ( .A0(n2564), .A1(Sgf_normalized_result[2]), .B0(n1578),
.B1(n2120), .Y(n2096) );
OAI21XLTS U2770 ( .A0(n2122), .A1(n2116), .B0(n2096), .Y(n1444) );
AOI22X1TS U2771 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n1584), .B1(n1659), .Y(n2099) );
AOI22X1TS U2772 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(n2559), .B1(n1640), .Y(n2098) );
OAI211X1TS U2773 ( .A0(n2114), .A1(n2100), .B0(n2099), .C0(n2098), .Y(n2135)
);
AOI22X1TS U2774 ( .A0(n2564), .A1(Sgf_normalized_result[0]), .B0(n1578),
.B1(n2135), .Y(n2101) );
AOI22X1TS U2775 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n2476), .B1(n1645), .Y(n2103) );
AOI22X1TS U2776 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n1584), .B1(n1665), .Y(n2102) );
OAI211X1TS U2777 ( .A0(n2114), .A1(n2104), .B0(n2103), .C0(n2102), .Y(n2126)
);
AOI22X1TS U2778 ( .A0(n2564), .A1(Sgf_normalized_result[5]), .B0(n1578),
.B1(n2126), .Y(n2105) );
OAI21XLTS U2779 ( .A0(n2128), .A1(n2116), .B0(n2105), .Y(n1447) );
AOI22X1TS U2780 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n2476), .B1(n1643), .Y(n2107) );
AOI22X1TS U2781 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n1584), .B1(n1663), .Y(n2106) );
OAI211X1TS U2782 ( .A0(n2114), .A1(n2108), .B0(n2107), .C0(n2106), .Y(n2129)
);
AOI22X1TS U2783 ( .A0(n2564), .A1(Sgf_normalized_result[3]), .B0(n1578),
.B1(n2129), .Y(n2109) );
OAI21XLTS U2784 ( .A0(n2131), .A1(n2116), .B0(n2109), .Y(n1445) );
AOI22X1TS U2785 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n2476), .B1(n1646), .Y(n2112) );
AOI22X1TS U2786 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n1584), .B1(n1666), .Y(n2111) );
OAI211X1TS U2787 ( .A0(n2114), .A1(n2113), .B0(n2112), .C0(n2111), .Y(n2132)
);
AOI22X1TS U2788 ( .A0(n2564), .A1(Sgf_normalized_result[6]), .B0(n1578),
.B1(n2132), .Y(n2115) );
OAI21XLTS U2789 ( .A0(n2134), .A1(n2116), .B0(n2115), .Y(n1448) );
AOI22X1TS U2790 ( .A0(n1770), .A1(Sgf_normalized_result[53]), .B0(n1585),
.B1(n2117), .Y(n2118) );
OAI211XLTS U2791 ( .A0(n2138), .A1(n2119), .B0(n2118), .C0(n2136), .Y(n1495)
);
AOI22X1TS U2792 ( .A0(n1770), .A1(Sgf_normalized_result[52]), .B0(n1585),
.B1(n2120), .Y(n2121) );
OAI211XLTS U2793 ( .A0(n2138), .A1(n2122), .B0(n2121), .C0(n2136), .Y(n1494)
);
AOI22X1TS U2794 ( .A0(n1770), .A1(Sgf_normalized_result[50]), .B0(n1585),
.B1(n2123), .Y(n2124) );
OAI211XLTS U2795 ( .A0(n2138), .A1(n2125), .B0(n2124), .C0(n2136), .Y(n1492)
);
AOI22X1TS U2796 ( .A0(n1770), .A1(Sgf_normalized_result[49]), .B0(n1585),
.B1(n2126), .Y(n2127) );
OAI211XLTS U2797 ( .A0(n2138), .A1(n2128), .B0(n2127), .C0(n2136), .Y(n1491)
);
AOI22X1TS U2798 ( .A0(n1770), .A1(Sgf_normalized_result[51]), .B0(n1585),
.B1(n2129), .Y(n2130) );
OAI211XLTS U2799 ( .A0(n2138), .A1(n2131), .B0(n2130), .C0(n2136), .Y(n1493)
);
AOI22X1TS U2800 ( .A0(n1770), .A1(Sgf_normalized_result[48]), .B0(n1585),
.B1(n2132), .Y(n2133) );
OAI211XLTS U2801 ( .A0(n2138), .A1(n2134), .B0(n2133), .C0(n2136), .Y(n1490)
);
AOI22X1TS U2802 ( .A0(n1770), .A1(Sgf_normalized_result[54]), .B0(n1585),
.B1(n2135), .Y(n2137) );
OAI211XLTS U2803 ( .A0(n2139), .A1(n2138), .B0(n2137), .C0(n2136), .Y(n1563)
);
AOI22X1TS U2804 ( .A0(n2162), .A1(intDY[61]), .B0(DmP[61]), .B1(n2238), .Y(
n2140) );
OAI21XLTS U2805 ( .A0(n2965), .A1(n2177), .B0(n2140), .Y(n1166) );
AOI22X1TS U2806 ( .A0(DmP[42]), .A1(n2190), .B0(intDY[42]), .B1(n2162), .Y(
n2141) );
OAI21XLTS U2807 ( .A0(n2891), .A1(n2035), .B0(n2141), .Y(n1147) );
AOI22X1TS U2808 ( .A0(n2223), .A1(DmP[48]), .B0(intDY[48]), .B1(n2162), .Y(
n2142) );
OAI21XLTS U2809 ( .A0(n2988), .A1(n2035), .B0(n2142), .Y(n1153) );
AOI22X1TS U2810 ( .A0(DmP[38]), .A1(n2228), .B0(intDY[38]), .B1(n2189), .Y(
n2143) );
AOI22X1TS U2811 ( .A0(DmP[40]), .A1(n2223), .B0(intDY[40]), .B1(n2162), .Y(
n2144) );
OAI21XLTS U2812 ( .A0(n2991), .A1(n2177), .B0(n2144), .Y(n1145) );
AOI22X1TS U2813 ( .A0(DmP[19]), .A1(n2228), .B0(intDY[19]), .B1(n2189), .Y(
n2145) );
OAI21XLTS U2814 ( .A0(n2985), .A1(n2153), .B0(n2145), .Y(n1124) );
AOI22X1TS U2815 ( .A0(n2189), .A1(intDY[55]), .B0(DmP[55]), .B1(n2238), .Y(
n2146) );
OAI21XLTS U2816 ( .A0(n3072), .A1(n2177), .B0(n2146), .Y(n1160) );
AOI22X1TS U2817 ( .A0(DmP[37]), .A1(n2865), .B0(intDY[37]), .B1(n2162), .Y(
n2147) );
OAI21XLTS U2818 ( .A0(n2890), .A1(n2153), .B0(n2147), .Y(n1142) );
AOI22X1TS U2819 ( .A0(DmP[35]), .A1(n2223), .B0(intDY[35]), .B1(n2189), .Y(
n2148) );
OAI21XLTS U2820 ( .A0(n2999), .A1(n2153), .B0(n2148), .Y(n1140) );
AOI22X1TS U2821 ( .A0(DmP[20]), .A1(n2190), .B0(intDY[20]), .B1(n2162), .Y(
n2149) );
OAI21XLTS U2822 ( .A0(n2974), .A1(n2153), .B0(n2149), .Y(n1125) );
AOI22X1TS U2823 ( .A0(DmP[36]), .A1(n2190), .B0(intDY[36]), .B1(n2162), .Y(
n2150) );
OAI21XLTS U2824 ( .A0(n3003), .A1(n2153), .B0(n2150), .Y(n1141) );
AOI22X1TS U2825 ( .A0(n2865), .A1(DmP[17]), .B0(intDY[17]), .B1(n2189), .Y(
n2151) );
OAI21XLTS U2826 ( .A0(n3043), .A1(n2153), .B0(n2151), .Y(n1122) );
AOI22X1TS U2827 ( .A0(DmP[18]), .A1(n2190), .B0(intDY[18]), .B1(n2189), .Y(
n2152) );
OAI21XLTS U2828 ( .A0(n3076), .A1(n2153), .B0(n2152), .Y(n1123) );
AOI22X1TS U2829 ( .A0(DmP[32]), .A1(n2190), .B0(intDY[32]), .B1(n2189), .Y(
n2154) );
OAI21XLTS U2830 ( .A0(n2969), .A1(n2188), .B0(n2154), .Y(n1137) );
AOI22X1TS U2831 ( .A0(DmP[34]), .A1(n2190), .B0(intDY[34]), .B1(n2162), .Y(
n2155) );
OAI21XLTS U2832 ( .A0(n2892), .A1(n2188), .B0(n2155), .Y(n1139) );
AOI22X1TS U2833 ( .A0(DmP[28]), .A1(n2190), .B0(intDY[28]), .B1(n2189), .Y(
n2156) );
OAI21XLTS U2834 ( .A0(n2971), .A1(n2188), .B0(n2156), .Y(n1133) );
AOI22X1TS U2835 ( .A0(DmP[31]), .A1(n2190), .B0(intDY[31]), .B1(n2162), .Y(
n2157) );
OAI21XLTS U2836 ( .A0(n3074), .A1(n2188), .B0(n2157), .Y(n1136) );
AOI22X1TS U2837 ( .A0(DmP[27]), .A1(n2190), .B0(intDY[27]), .B1(n2189), .Y(
n2158) );
OAI21XLTS U2838 ( .A0(n2984), .A1(n2188), .B0(n2158), .Y(n1132) );
AOI22X1TS U2839 ( .A0(DmP[33]), .A1(n2190), .B0(intDY[33]), .B1(n2162), .Y(
n2159) );
OAI21XLTS U2840 ( .A0(n3000), .A1(n2188), .B0(n2159), .Y(n1138) );
AOI22X1TS U2841 ( .A0(n2239), .A1(intDY[62]), .B0(DMP[62]), .B1(n2223), .Y(
n2160) );
OAI21XLTS U2842 ( .A0(n2894), .A1(n2237), .B0(n2160), .Y(n1168) );
AOI22X1TS U2843 ( .A0(n2239), .A1(intDY[10]), .B0(DMP[10]), .B1(n2223), .Y(
n2161) );
OAI21XLTS U2844 ( .A0(n2978), .A1(n2041), .B0(n2161), .Y(n1179) );
AOI22X1TS U2845 ( .A0(DmP[41]), .A1(n2228), .B0(intDY[41]), .B1(n2189), .Y(
n2163) );
OAI21XLTS U2846 ( .A0(n1652), .A1(n2153), .B0(n2163), .Y(n1146) );
AOI22X1TS U2847 ( .A0(n2239), .A1(intDY[48]), .B0(DMP[48]), .B1(n2865), .Y(
n2165) );
OAI21XLTS U2848 ( .A0(n2988), .A1(n2241), .B0(n2165), .Y(n1217) );
AOI22X1TS U2849 ( .A0(n2239), .A1(intDY[37]), .B0(DMP[37]), .B1(n2865), .Y(
n2166) );
OAI21XLTS U2850 ( .A0(n2890), .A1(n2241), .B0(n2166), .Y(n1206) );
AOI22X1TS U2851 ( .A0(n2239), .A1(intDY[5]), .B0(DMP[5]), .B1(n2223), .Y(
n2167) );
OAI21XLTS U2852 ( .A0(n2884), .A1(n2237), .B0(n2167), .Y(n1174) );
AOI22X1TS U2853 ( .A0(n2239), .A1(intDY[4]), .B0(DMP[4]), .B1(n2228), .Y(
n2168) );
OAI21XLTS U2854 ( .A0(n2980), .A1(n2237), .B0(n2168), .Y(n1173) );
AOI22X1TS U2855 ( .A0(n2239), .A1(intDY[38]), .B0(DMP[38]), .B1(n2865), .Y(
n2169) );
OAI21XLTS U2856 ( .A0(n2992), .A1(n1577), .B0(n2169), .Y(n1207) );
AOI22X1TS U2857 ( .A0(n2239), .A1(intDY[44]), .B0(DMP[44]), .B1(n2865), .Y(
n2170) );
OAI21XLTS U2858 ( .A0(n2990), .A1(n1577), .B0(n2170), .Y(n1213) );
AOI22X1TS U2859 ( .A0(DmP[45]), .A1(n2223), .B0(intDY[45]), .B1(n2189), .Y(
n2171) );
OAI21XLTS U2860 ( .A0(n2997), .A1(n2035), .B0(n2171), .Y(n1150) );
AOI22X1TS U2861 ( .A0(DmP[46]), .A1(n2228), .B0(intDY[46]), .B1(n2162), .Y(
n2172) );
OAI21XLTS U2862 ( .A0(n2989), .A1(n2035), .B0(n2172), .Y(n1151) );
AOI22X1TS U2863 ( .A0(n2190), .A1(DmP[49]), .B0(intDY[49]), .B1(n2162), .Y(
n2173) );
OAI21XLTS U2864 ( .A0(n1654), .A1(n2177), .B0(n2173), .Y(n1154) );
AOI22X1TS U2865 ( .A0(DmP[43]), .A1(n2223), .B0(intDY[43]), .B1(n2189), .Y(
n2174) );
OAI21XLTS U2866 ( .A0(n2998), .A1(n2035), .B0(n2174), .Y(n1148) );
AOI22X1TS U2867 ( .A0(n2228), .A1(DmP[47]), .B0(intDY[47]), .B1(n2162), .Y(
n2175) );
OAI21XLTS U2868 ( .A0(n2888), .A1(n2035), .B0(n2175), .Y(n1152) );
AOI22X1TS U2869 ( .A0(DmP[39]), .A1(n2228), .B0(intDY[39]), .B1(n2162), .Y(
n2176) );
OAI21XLTS U2870 ( .A0(n2889), .A1(n2177), .B0(n2176), .Y(n1144) );
AOI22X1TS U2871 ( .A0(DmP[44]), .A1(n2190), .B0(intDY[44]), .B1(n2189), .Y(
n2178) );
OAI21XLTS U2872 ( .A0(n2990), .A1(n2035), .B0(n2178), .Y(n1149) );
AOI22X1TS U2873 ( .A0(DmP[25]), .A1(n2223), .B0(intDY[25]), .B1(n2162), .Y(
n2179) );
OAI21XLTS U2874 ( .A0(n3040), .A1(n2192), .B0(n2179), .Y(n1130) );
AOI22X1TS U2875 ( .A0(n2223), .A1(DmP[50]), .B0(intDY[50]), .B1(n2189), .Y(
n2180) );
OAI21XLTS U2876 ( .A0(n3045), .A1(n2192), .B0(n2180), .Y(n1155) );
AOI22X1TS U2877 ( .A0(n2228), .A1(DmP[51]), .B0(intDY[51]), .B1(n2189), .Y(
n2181) );
OAI21XLTS U2878 ( .A0(n2986), .A1(n2192), .B0(n2181), .Y(n1156) );
AOI22X1TS U2879 ( .A0(DmP[24]), .A1(n2190), .B0(intDY[24]), .B1(n2162), .Y(
n2182) );
AOI22X1TS U2880 ( .A0(DmP[29]), .A1(n2190), .B0(intDY[29]), .B1(n2189), .Y(
n2183) );
OAI21XLTS U2881 ( .A0(n2961), .A1(n2188), .B0(n2183), .Y(n1134) );
AOI22X1TS U2882 ( .A0(DmP[21]), .A1(n2190), .B0(intDY[21]), .B1(n2162), .Y(
n2184) );
OAI21XLTS U2883 ( .A0(n2981), .A1(n2192), .B0(n2184), .Y(n1126) );
AOI22X1TS U2884 ( .A0(DmP[23]), .A1(n2190), .B0(intDY[23]), .B1(n2189), .Y(
n2185) );
OAI21XLTS U2885 ( .A0(n3075), .A1(n2192), .B0(n2185), .Y(n1128) );
AOI22X1TS U2886 ( .A0(DmP[30]), .A1(n2190), .B0(intDY[30]), .B1(n2162), .Y(
n2186) );
OAI21XLTS U2887 ( .A0(n2970), .A1(n2188), .B0(n2186), .Y(n1135) );
AOI22X1TS U2888 ( .A0(DmP[26]), .A1(n2190), .B0(intDY[26]), .B1(n2189), .Y(
n2187) );
OAI21XLTS U2889 ( .A0(n3041), .A1(n2188), .B0(n2187), .Y(n1131) );
AOI22X1TS U2890 ( .A0(DmP[22]), .A1(n2190), .B0(intDY[22]), .B1(n2189), .Y(
n2191) );
OAI21XLTS U2891 ( .A0(n2973), .A1(n2192), .B0(n2191), .Y(n1127) );
AOI22X1TS U2892 ( .A0(n2218), .A1(intDY[52]), .B0(DMP[52]), .B1(n2238), .Y(
n2193) );
OAI21XLTS U2893 ( .A0(n2968), .A1(n2241), .B0(n2193), .Y(n1221) );
AOI22X1TS U2894 ( .A0(n2218), .A1(intDY[7]), .B0(DMP[7]), .B1(n2228), .Y(
n2194) );
OAI21XLTS U2895 ( .A0(n2955), .A1(n2237), .B0(n2194), .Y(n1176) );
AOI22X1TS U2896 ( .A0(n2218), .A1(intDY[61]), .B0(DMP[61]), .B1(n2226), .Y(
n2195) );
OAI21XLTS U2897 ( .A0(n2965), .A1(n1577), .B0(n2195), .Y(n1230) );
AOI22X1TS U2898 ( .A0(n2218), .A1(intDY[16]), .B0(DMP[16]), .B1(n2228), .Y(
n2196) );
AOI22X1TS U2899 ( .A0(n2218), .A1(intDY[6]), .B0(DMP[6]), .B1(n2223), .Y(
n2197) );
OAI21XLTS U2900 ( .A0(n2979), .A1(n2237), .B0(n2197), .Y(n1175) );
AOI22X1TS U2901 ( .A0(n2239), .A1(intDY[19]), .B0(DMP[19]), .B1(n2228), .Y(
n2198) );
OAI21XLTS U2902 ( .A0(n2985), .A1(n1577), .B0(n2198), .Y(n1188) );
AOI22X1TS U2903 ( .A0(n2239), .A1(intDY[9]), .B0(DMP[9]), .B1(n2226), .Y(
n2199) );
OAI21XLTS U2904 ( .A0(n2886), .A1(n2041), .B0(n2199), .Y(n1178) );
AOI22X1TS U2905 ( .A0(n2239), .A1(intDY[47]), .B0(DMP[47]), .B1(n2865), .Y(
n2200) );
OAI21XLTS U2906 ( .A0(n2888), .A1(n1577), .B0(n2200), .Y(n1216) );
AOI22X1TS U2907 ( .A0(n2239), .A1(intDY[42]), .B0(DMP[42]), .B1(n2865), .Y(
n2201) );
AOI22X1TS U2908 ( .A0(n2239), .A1(intDY[39]), .B0(DMP[39]), .B1(n2865), .Y(
n2202) );
OAI21XLTS U2909 ( .A0(n2889), .A1(n1577), .B0(n2202), .Y(n1208) );
AOI22X1TS U2910 ( .A0(n2239), .A1(intDY[40]), .B0(DMP[40]), .B1(n2865), .Y(
n2203) );
OAI21XLTS U2911 ( .A0(n2991), .A1(n1577), .B0(n2203), .Y(n1209) );
INVX2TS U2912 ( .A(n2585), .Y(n2603) );
AOI22X1TS U2913 ( .A0(n2796), .A1(n2603), .B0(n2204), .B1(n2605), .Y(n2210)
);
INVX2TS U2914 ( .A(n2591), .Y(n2602) );
INVX2TS U2915 ( .A(n2606), .Y(n2587) );
AOI222X4TS U2916 ( .A0(n2815), .A1(DmP[47]), .B0(n1668), .B1(n2693), .C0(
Add_Subt_result[49]), .C1(n2700), .Y(n2583) );
INVX2TS U2917 ( .A(n2629), .Y(n2207) );
OR2X2TS U2918 ( .A(n2666), .B(n2207), .Y(n2580) );
OAI22X1TS U2919 ( .A0(n2587), .A1(n2579), .B0(n2583), .B1(n2580), .Y(n2208)
);
AOI21X1TS U2920 ( .A0(n1705), .A1(n2602), .B0(n2208), .Y(n2209) );
OAI211XLTS U2921 ( .A0(n2211), .A1(n2651), .B0(n2210), .C0(n2209), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
AOI22X1TS U2922 ( .A0(n2239), .A1(intDY[45]), .B0(DMP[45]), .B1(n2865), .Y(
n2212) );
OAI21XLTS U2923 ( .A0(n2997), .A1(n1577), .B0(n2212), .Y(n1214) );
AOI22X1TS U2924 ( .A0(n2239), .A1(intDY[36]), .B0(DMP[36]), .B1(n2228), .Y(
n2213) );
OAI21XLTS U2925 ( .A0(n3003), .A1(n2241), .B0(n2213), .Y(n1205) );
AOI22X1TS U2926 ( .A0(n2239), .A1(intDY[46]), .B0(DMP[46]), .B1(n2865), .Y(
n2214) );
OAI21XLTS U2927 ( .A0(n2989), .A1(n1577), .B0(n2214), .Y(n1215) );
AOI22X1TS U2928 ( .A0(n2239), .A1(intDY[43]), .B0(DMP[43]), .B1(n2865), .Y(
n2215) );
OAI21XLTS U2929 ( .A0(n2998), .A1(n1577), .B0(n2215), .Y(n1212) );
AOI22X1TS U2930 ( .A0(n2218), .A1(intDY[0]), .B0(DMP[0]), .B1(n2223), .Y(
n2216) );
OAI21XLTS U2931 ( .A0(n2964), .A1(n2237), .B0(n2216), .Y(n1169) );
AOI22X1TS U2932 ( .A0(n2239), .A1(intDY[3]), .B0(DMP[3]), .B1(n2238), .Y(
n2217) );
AOI22X1TS U2933 ( .A0(n2239), .A1(intDY[41]), .B0(DMP[41]), .B1(n2865), .Y(
n2219) );
OAI21XLTS U2934 ( .A0(n1652), .A1(n1577), .B0(n2219), .Y(n1210) );
AOI22X1TS U2935 ( .A0(n2218), .A1(intDY[2]), .B0(DMP[2]), .B1(n2228), .Y(
n2220) );
OAI21XLTS U2936 ( .A0(n2887), .A1(n2237), .B0(n2220), .Y(n1171) );
AOI22X1TS U2937 ( .A0(n2218), .A1(intDY[51]), .B0(DMP[51]), .B1(n2238), .Y(
n2221) );
OAI21XLTS U2938 ( .A0(n2986), .A1(n2241), .B0(n2221), .Y(n1220) );
AOI22X1TS U2939 ( .A0(n2218), .A1(intDY[14]), .B0(DMP[14]), .B1(n2223), .Y(
n2222) );
OAI21XLTS U2940 ( .A0(n2976), .A1(n2041), .B0(n2222), .Y(n1183) );
AOI22X1TS U2941 ( .A0(n2218), .A1(intDY[22]), .B0(DMP[22]), .B1(n2223), .Y(
n2224) );
OAI21XLTS U2942 ( .A0(n2973), .A1(n1577), .B0(n2224), .Y(n1191) );
AOI22X1TS U2943 ( .A0(n2218), .A1(intDY[59]), .B0(DMP[59]), .B1(n2226), .Y(
n2225) );
OAI21XLTS U2944 ( .A0(n2895), .A1(n1577), .B0(n2225), .Y(n1228) );
AOI22X1TS U2945 ( .A0(n2218), .A1(intDY[49]), .B0(DMP[49]), .B1(n2865), .Y(
n2227) );
OAI21XLTS U2946 ( .A0(n1654), .A1(n2241), .B0(n2227), .Y(n1218) );
AOI22X1TS U2947 ( .A0(n2218), .A1(intDY[8]), .B0(n1576), .B1(n2228), .Y(
n2229) );
OAI21XLTS U2948 ( .A0(n2963), .A1(n2041), .B0(n2229), .Y(n1177) );
AOI22X1TS U2949 ( .A0(n2218), .A1(intDY[57]), .B0(DMP[57]), .B1(n2238), .Y(
n2230) );
OAI21XLTS U2950 ( .A0(n2996), .A1(n2237), .B0(n2230), .Y(n1226) );
AOI22X1TS U2951 ( .A0(n2239), .A1(intDY[54]), .B0(DMP[54]), .B1(n2238), .Y(
n2231) );
OAI21XLTS U2952 ( .A0(n2967), .A1(n2241), .B0(n2231), .Y(n1223) );
AOI22X1TS U2953 ( .A0(n2218), .A1(intDY[56]), .B0(DMP[56]), .B1(n2238), .Y(
n2232) );
OAI21XLTS U2954 ( .A0(n2966), .A1(n2241), .B0(n2232), .Y(n1225) );
AOI22X1TS U2955 ( .A0(n2218), .A1(intDY[50]), .B0(DMP[50]), .B1(n2238), .Y(
n2233) );
OAI21XLTS U2956 ( .A0(n3045), .A1(n2241), .B0(n2233), .Y(n1219) );
AOI22X1TS U2957 ( .A0(n2218), .A1(intDY[58]), .B0(DMP[58]), .B1(n2226), .Y(
n2234) );
OAI21XLTS U2958 ( .A0(n3002), .A1(n1577), .B0(n2234), .Y(n1227) );
AOI22X1TS U2959 ( .A0(n2218), .A1(intDY[60]), .B0(DMP[60]), .B1(n2238), .Y(
n2235) );
OAI21XLTS U2960 ( .A0(n3001), .A1(n1577), .B0(n2235), .Y(n1229) );
AOI22X1TS U2961 ( .A0(n2218), .A1(intDY[55]), .B0(DMP[55]), .B1(n2226), .Y(
n2236) );
AOI22X1TS U2962 ( .A0(n2218), .A1(intDY[53]), .B0(DMP[53]), .B1(n2238), .Y(
n2240) );
OAI21XLTS U2963 ( .A0(n3073), .A1(n2241), .B0(n2240), .Y(n1222) );
BUFX4TS U2964 ( .A(n2671), .Y(n2798) );
AOI22X1TS U2965 ( .A0(n2780), .A1(n2606), .B0(n2798), .B1(n2605), .Y(n2244)
);
INVX2TS U2966 ( .A(n2583), .Y(n2607) );
AO22XLTS U2967 ( .A0(n2603), .A1(n1705), .B0(n1630), .B1(n2714), .Y(n2242)
);
AOI21X1TS U2968 ( .A0(n2796), .A1(n2607), .B0(n2242), .Y(n2243) );
OAI211XLTS U2969 ( .A0(n2245), .A1(n2651), .B0(n2244), .C0(n2243), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
AOI22X1TS U2970 ( .A0(n2780), .A1(n1630), .B0(n2671), .B1(n2613), .Y(n2248)
);
AO22XLTS U2971 ( .A0(n2607), .A1(n1705), .B0(n2605), .B1(n2714), .Y(n2246)
);
AOI21X1TS U2972 ( .A0(n2796), .A1(n2606), .B0(n2246), .Y(n2247) );
OAI22X1TS U2973 ( .A0(n2596), .A1(n2588), .B0(n2583), .B1(n2579), .Y(n2250)
);
OAI22X1TS U2974 ( .A0(n2585), .A1(n2580), .B0(n2587), .B1(n2590), .Y(n2249)
);
AOI211XLTS U2975 ( .A0(n2753), .A1(n2602), .B0(n2250), .C0(n2249), .Y(n2251)
);
OAI21XLTS U2976 ( .A0(n2252), .A1(n2651), .B0(n2251), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
OAI22X1TS U2977 ( .A0(n2597), .A1(n2579), .B0(n2583), .B1(n2586), .Y(n2254)
);
OAI22X1TS U2978 ( .A0(n2596), .A1(n2590), .B0(n2591), .B1(n2584), .Y(n2253)
);
AOI211X1TS U2979 ( .A0(n2256), .A1(n2255), .B0(n2254), .C0(n2253), .Y(n2258)
);
INVX2TS U2980 ( .A(n2580), .Y(n2788) );
NAND2X1TS U2981 ( .A(n1593), .B(n2788), .Y(n2257) );
OAI211XLTS U2982 ( .A0(n2585), .A1(n2582), .B0(n2258), .C0(n2257), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
XOR2X1TS U2983 ( .A(DP_OP_42J154_122_8302_n1), .B(FSM_exp_operation_A_S),
.Y(n2263) );
OR4X2TS U2984 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[1]), .C(Exp_Operation_Module_Data_S[0]),
.D(n1590), .Y(n2259) );
OR4X2TS U2985 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n2259), .Y(n2260) );
OR4X2TS U2986 ( .A(Exp_Operation_Module_Data_S[8]), .B(
Exp_Operation_Module_Data_S[7]), .C(Exp_Operation_Module_Data_S[6]),
.D(n2260), .Y(n2261) );
OR4X2TS U2987 ( .A(n2263), .B(Exp_Operation_Module_Data_S[10]), .C(
Exp_Operation_Module_Data_S[9]), .D(n2261), .Y(n2262) );
OAI21XLTS U2988 ( .A0(n1638), .A1(n2843), .B0(n2262), .Y(n1426) );
INVX2TS U2989 ( .A(n2263), .Y(n2271) );
INVX2TS U2990 ( .A(Exp_Operation_Module_Data_S[10]), .Y(n2270) );
NAND3BXLTS U2991 ( .AN(n2881), .B(n2940), .C(FS_Module_state_reg[0]), .Y(
n2264) );
NAND2X1TS U2992 ( .A(n2265), .B(n2264), .Y(n2813) );
CLKAND2X2TS U2993 ( .A(Exp_Operation_Module_Data_S[0]), .B(n2813), .Y(n2571)
);
NAND4XLTS U2994 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(n2571), .Y(n2266) );
NAND4BXLTS U2995 ( .AN(n2266), .B(Exp_Operation_Module_Data_S[6]), .C(
Exp_Operation_Module_Data_S[5]), .D(Exp_Operation_Module_Data_S[4]),
.Y(n2267) );
NAND4BXLTS U2996 ( .AN(n2267), .B(Exp_Operation_Module_Data_S[9]), .C(
Exp_Operation_Module_Data_S[8]), .D(Exp_Operation_Module_Data_S[7]),
.Y(n2269) );
NAND2X1TS U2997 ( .A(n2573), .B(overflow_flag), .Y(n2268) );
OAI31X1TS U2998 ( .A0(n2271), .A1(n2270), .A2(n2269), .B0(n2268), .Y(n1427)
);
AOI22X1TS U2999 ( .A0(n2893), .A1(intDY[1]), .B0(n2965), .B1(intDY[61]), .Y(
n2272) );
OAI221XLTS U3000 ( .A0(n2893), .A1(intDY[1]), .B0(n2965), .B1(intDY[61]),
.C0(n2272), .Y(n2273) );
AOI221X1TS U3001 ( .A0(intDX[62]), .A1(n2993), .B0(n2894), .B1(intDY[62]),
.C0(n2273), .Y(n2287) );
OAI22X1TS U3002 ( .A0(n3002), .A1(intDY[58]), .B0(n2996), .B1(intDY[57]),
.Y(n2274) );
OAI22X1TS U3003 ( .A0(n3001), .A1(intDY[60]), .B0(n2895), .B1(intDY[59]),
.Y(n2275) );
AOI22X1TS U3004 ( .A0(n3073), .A1(intDY[53]), .B0(n2967), .B1(intDY[54]),
.Y(n2276) );
AOI22X1TS U3005 ( .A0(n3072), .A1(intDY[55]), .B0(n2966), .B1(intDY[56]),
.Y(n2277) );
AOI22X1TS U3006 ( .A0(n1654), .A1(intDY[49]), .B0(n3045), .B1(intDY[50]),
.Y(n2278) );
AOI22X1TS U3007 ( .A0(n2986), .A1(intDY[51]), .B0(n2968), .B1(intDY[52]),
.Y(n2279) );
NOR4X1TS U3008 ( .A(n2283), .B(n2282), .C(n2281), .D(n2280), .Y(n2284) );
NAND4XLTS U3009 ( .A(n2287), .B(n2286), .C(n2285), .D(n2284), .Y(n2343) );
OAI22X1TS U3010 ( .A0(n2992), .A1(intDY[38]), .B0(n2890), .B1(intDY[37]),
.Y(n2288) );
AOI221X1TS U3011 ( .A0(n2992), .A1(intDY[38]), .B0(intDY[37]), .B1(n2890),
.C0(n2288), .Y(n2295) );
OAI22X1TS U3012 ( .A0(n2991), .A1(intDY[40]), .B0(n2889), .B1(intDY[39]),
.Y(n2289) );
OAI22X1TS U3013 ( .A0(n2892), .A1(intDY[34]), .B0(n3000), .B1(intDY[33]),
.Y(n2290) );
OAI22X1TS U3014 ( .A0(n3003), .A1(intDY[36]), .B0(n2999), .B1(intDY[35]),
.Y(n2291) );
NAND4XLTS U3015 ( .A(n2295), .B(n2294), .C(n2293), .D(n2292), .Y(n2342) );
OAI22X1TS U3016 ( .A0(n2989), .A1(intDY[46]), .B0(n2997), .B1(intDY[45]),
.Y(n2296) );
OAI22X1TS U3017 ( .A0(n2988), .A1(intDY[48]), .B0(n2888), .B1(intDY[47]),
.Y(n2297) );
AOI221X1TS U3018 ( .A0(n2988), .A1(intDY[48]), .B0(intDY[47]), .B1(n2888),
.C0(n2297), .Y(n2302) );
OAI22X1TS U3019 ( .A0(n2891), .A1(intDY[42]), .B0(n1652), .B1(intDY[41]),
.Y(n2298) );
OAI22X1TS U3020 ( .A0(n2990), .A1(intDY[44]), .B0(n2998), .B1(intDY[43]),
.Y(n2299) );
AOI221X1TS U3021 ( .A0(n2990), .A1(intDY[44]), .B0(intDY[43]), .B1(n2998),
.C0(n2299), .Y(n2300) );
NAND4XLTS U3022 ( .A(n2303), .B(n2302), .C(n2301), .D(n2300), .Y(n2341) );
AOI22X1TS U3023 ( .A0(n2981), .A1(intDY[21]), .B0(n2973), .B1(intDY[22]),
.Y(n2304) );
AOI22X1TS U3024 ( .A0(n3075), .A1(intDY[23]), .B0(n2972), .B1(intDY[24]),
.Y(n2305) );
AOI22X1TS U3025 ( .A0(n3043), .A1(intDY[17]), .B0(n3076), .B1(intDY[18]),
.Y(n2306) );
AOI22X1TS U3026 ( .A0(n2985), .A1(intDY[19]), .B0(n2974), .B1(intDY[20]),
.Y(n2307) );
NOR4X1TS U3027 ( .A(n2311), .B(n2310), .C(n2309), .D(n2308), .Y(n2339) );
AOI22X1TS U3028 ( .A0(n2961), .A1(intDY[29]), .B0(n2970), .B1(intDY[30]),
.Y(n2312) );
AOI22X1TS U3029 ( .A0(n3074), .A1(intDY[31]), .B0(n2969), .B1(intDY[32]),
.Y(n2313) );
AOI22X1TS U3030 ( .A0(n3040), .A1(intDY[25]), .B0(n3041), .B1(intDY[26]),
.Y(n2314) );
AOI22X1TS U3031 ( .A0(n2984), .A1(intDY[27]), .B0(n2971), .B1(intDY[28]),
.Y(n2315) );
NOR4X1TS U3032 ( .A(n2319), .B(n2318), .C(n2317), .D(n2316), .Y(n2338) );
AOI22X1TS U3033 ( .A0(n2884), .A1(intDY[5]), .B0(n2979), .B1(intDY[6]), .Y(
n2320) );
AOI22X1TS U3034 ( .A0(n2955), .A1(intDY[7]), .B0(n2963), .B1(intDY[8]), .Y(
n2321) );
AOI22X1TS U3035 ( .A0(n2887), .A1(intDY[2]), .B0(n2964), .B1(intDY[0]), .Y(
n2322) );
AOI22X1TS U3036 ( .A0(n2960), .A1(intDY[3]), .B0(n2980), .B1(intDY[4]), .Y(
n2323) );
NOR4X1TS U3037 ( .A(n2327), .B(n2326), .C(n2325), .D(n2324), .Y(n2337) );
AOI22X1TS U3038 ( .A0(n2962), .A1(intDY[13]), .B0(n2976), .B1(intDY[14]),
.Y(n2328) );
AOI22X1TS U3039 ( .A0(n3077), .A1(intDY[15]), .B0(n2975), .B1(intDY[16]),
.Y(n2329) );
AOI22X1TS U3040 ( .A0(n2886), .A1(intDY[9]), .B0(n2978), .B1(intDY[10]), .Y(
n2330) );
AOI22X1TS U3041 ( .A0(n3042), .A1(intDY[11]), .B0(n2977), .B1(intDY[12]),
.Y(n2331) );
NOR4X1TS U3042 ( .A(n2335), .B(n2334), .C(n2333), .D(n2332), .Y(n2336) );
NAND4XLTS U3043 ( .A(n2339), .B(n2338), .C(n2337), .D(n2336), .Y(n2340) );
XOR2X1TS U3044 ( .A(intDY[63]), .B(intAS), .Y(n2863) );
XOR2X1TS U3045 ( .A(n2863), .B(intDX[63]), .Y(n2391) );
NAND2X1TS U3046 ( .A(n2861), .B(n2391), .Y(n2808) );
OR4X2TS U3047 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .C(
Add_Subt_result[51]), .D(Add_Subt_result[52]), .Y(n2381) );
NAND2X1TS U3048 ( .A(n2823), .B(n2901), .Y(n2364) );
NOR4X2TS U3049 ( .A(Add_Subt_result[45]), .B(Add_Subt_result[46]), .C(
Add_Subt_result[44]), .D(n2364), .Y(n2357) );
NAND2X1TS U3050 ( .A(n2357), .B(n2907), .Y(n2346) );
NAND2X1TS U3051 ( .A(n1669), .B(n2702), .Y(n2442) );
NAND2X1TS U3052 ( .A(n2347), .B(n2912), .Y(n2425) );
NOR3X1TS U3053 ( .A(Add_Subt_result[37]), .B(Add_Subt_result[38]), .C(n2425),
.Y(n2417) );
NAND2X1TS U3054 ( .A(n2417), .B(n2916), .Y(n2828) );
NOR2X2TS U3055 ( .A(Add_Subt_result[35]), .B(n2828), .Y(n2429) );
NAND3X1TS U3056 ( .A(n2429), .B(n2921), .C(n1633), .Y(n2415) );
NOR3X1TS U3057 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .C(n2415),
.Y(n2362) );
NAND2X1TS U3058 ( .A(n2362), .B(n2924), .Y(n2432) );
NOR2X2TS U3059 ( .A(Add_Subt_result[26]), .B(n2363), .Y(n2354) );
NAND2X1TS U3060 ( .A(n2354), .B(n2930), .Y(n2419) );
NOR2X1TS U3061 ( .A(Add_Subt_result[24]), .B(n2419), .Y(n2361) );
NAND2X1TS U3062 ( .A(n2361), .B(n2882), .Y(n2348) );
INVX2TS U3063 ( .A(n2348), .Y(n2384) );
NAND2X1TS U3064 ( .A(n2384), .B(Add_Subt_result[21]), .Y(n2430) );
OAI32X1TS U3065 ( .A0(n2825), .A1(Add_Subt_result[40]), .A2(n2912), .B0(
n2702), .B1(n2825), .Y(n2349) );
AOI31XLTS U3066 ( .A0(Add_Subt_result[19]), .A1(n2424), .A2(n3012), .B0(
n2349), .Y(n2352) );
NOR2X1TS U3067 ( .A(Add_Subt_result[12]), .B(Add_Subt_result[11]), .Y(n2393)
);
NOR2X1TS U3068 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[19]), .Y(n2414)
);
NAND2X1TS U3069 ( .A(n2414), .B(n2424), .Y(n2403) );
NOR2X1TS U3070 ( .A(Add_Subt_result[18]), .B(n2403), .Y(n2392) );
NOR2BX1TS U3071 ( .AN(n2392), .B(Add_Subt_result[17]), .Y(n2449) );
NAND2X1TS U3072 ( .A(n2449), .B(n2875), .Y(n2394) );
NOR2X1TS U3073 ( .A(Add_Subt_result[15]), .B(n2394), .Y(n2383) );
NAND2X1TS U3074 ( .A(n2383), .B(n1629), .Y(n2376) );
NAND2X1TS U3075 ( .A(n2393), .B(n2401), .Y(n2360) );
NOR2X1TS U3076 ( .A(Add_Subt_result[10]), .B(n2360), .Y(n2353) );
NAND2X1TS U3077 ( .A(n2353), .B(n3004), .Y(n2397) );
NOR3X2TS U3078 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .C(n2397),
.Y(n2404) );
OAI211XLTS U3079 ( .A0(n1668), .A1(n2350), .B0(n2404), .C0(n3016), .Y(n2351)
);
OAI211X1TS U3080 ( .A0(Add_Subt_result[22]), .A1(n2430), .B0(n2352), .C0(
n2351), .Y(n2375) );
AOI21X1TS U3081 ( .A0(Add_Subt_result[7]), .A1(n2897), .B0(
Add_Subt_result[9]), .Y(n2356) );
INVX2TS U3082 ( .A(n2353), .Y(n2409) );
AOI32X1TS U3083 ( .A0(Add_Subt_result[23]), .A1(n2354), .A2(n3008), .B0(
Add_Subt_result[25]), .B1(n2354), .Y(n2355) );
NAND2X1TS U3084 ( .A(Add_Subt_result[43]), .B(n2357), .Y(n2444) );
OAI211X1TS U3085 ( .A0(n2356), .A1(n2409), .B0(n2355), .C0(n2444), .Y(n2831)
);
NOR2X1TS U3086 ( .A(Add_Subt_result[6]), .B(n1668), .Y(n2405) );
NAND2X1TS U3087 ( .A(n2404), .B(n2405), .Y(n2395) );
AOI22X1TS U3088 ( .A0(Add_Subt_result[20]), .A1(n2424), .B0(n2404), .B1(
Add_Subt_result[6]), .Y(n2359) );
OAI211X1TS U3089 ( .A0(n3019), .A1(n2395), .B0(n2359), .C0(n2358), .Y(n2380)
);
NOR2XLTS U3090 ( .A(n3008), .B(n2419), .Y(n2368) );
AOI21X1TS U3091 ( .A0(n3017), .A1(n2897), .B0(n2360), .Y(n2367) );
NOR3X1TS U3092 ( .A(Add_Subt_result[46]), .B(Add_Subt_result[45]), .C(
Add_Subt_result[44]), .Y(n2365) );
OAI22X1TS U3093 ( .A0(n2365), .A1(n2364), .B0(n3010), .B1(n2363), .Y(n2366)
);
NOR4X1TS U3094 ( .A(n2368), .B(n2367), .C(n2428), .D(n2366), .Y(n2370) );
INVX2TS U3095 ( .A(n2833), .Y(n2450) );
NOR2XLTS U3096 ( .A(n1649), .B(n2450), .Y(n2369) );
AOI21X1TS U3097 ( .A0(n1667), .A1(n2926), .B0(Add_Subt_result[29]), .Y(n2379) );
NAND2X1TS U3098 ( .A(Add_Subt_result[31]), .B(n1632), .Y(n2373) );
INVX2TS U3099 ( .A(n2429), .Y(n2372) );
AOI211X1TS U3100 ( .A0(n1633), .A1(n2373), .B0(Add_Subt_result[34]), .C0(
n2372), .Y(n2374) );
AOI211X1TS U3101 ( .A0(Add_Subt_result[47]), .A1(n2823), .B0(n2375), .C0(
n2374), .Y(n2378) );
INVX2TS U3102 ( .A(n2376), .Y(n2406) );
OAI211X1TS U3103 ( .A0(n2379), .A1(n2432), .B0(n2378), .C0(n2377), .Y(n2830)
);
OAI22X1TS U3104 ( .A0(n2382), .A1(n2381), .B0(n1632), .B1(n2415), .Y(n2387)
);
AOI22X1TS U3105 ( .A0(n2384), .A1(Add_Subt_result[22]), .B0(
Add_Subt_result[14]), .B1(n2383), .Y(n2385) );
OAI21XLTS U3106 ( .A0(n2432), .A1(n2926), .B0(n2385), .Y(n2386) );
AOI211XLTS U3107 ( .A0(n2429), .A1(Add_Subt_result[34]), .B0(n2387), .C0(
n2386), .Y(n2389) );
NOR2XLTS U3108 ( .A(LZA_output[2]), .B(n2450), .Y(n2388) );
AND2X4TS U3109 ( .A(n2391), .B(n2902), .Y(n2512) );
BUFX4TS U3110 ( .A(n2512), .Y(n3039) );
NOR3X1TS U3111 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .C(n2395),
.Y(n2436) );
NAND2X1TS U3112 ( .A(n2436), .B(n3033), .Y(n2402) );
NOR2X1TS U3113 ( .A(n3035), .B(n2402), .Y(n2435) );
AOI21X1TS U3114 ( .A0(n2392), .A1(Add_Subt_result[17]), .B0(n2435), .Y(n2836) );
INVX2TS U3115 ( .A(n2393), .Y(n2400) );
NOR2X1TS U3116 ( .A(n2394), .B(n3022), .Y(n2832) );
NOR2XLTS U3117 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .Y(n2398)
);
NOR2XLTS U3118 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .Y(n2396)
);
OAI22X1TS U3119 ( .A0(n2398), .A1(n2397), .B0(n2396), .B1(n2395), .Y(n2399)
);
AOI211X1TS U3120 ( .A0(n2401), .A1(n2400), .B0(n2832), .C0(n2399), .Y(n2447)
);
NOR3X1TS U3121 ( .A(Add_Subt_result[1]), .B(n2402), .C(n3036), .Y(n2422) );
AOI31XLTS U3122 ( .A0(n2875), .A1(n3021), .A2(n1629), .B0(n2403), .Y(n2411)
);
OAI2BB1X1TS U3123 ( .A0N(n2405), .A1N(n3033), .B0(n2404), .Y(n2408) );
OAI21XLTS U3124 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[13]), .B0(
n2406), .Y(n2407) );
NOR4BX1TS U3125 ( .AN(n2447), .B(n2422), .C(n2411), .D(n2410), .Y(n2413) );
NOR2XLTS U3126 ( .A(n1637), .B(n2450), .Y(n2412) );
INVX2TS U3127 ( .A(n2414), .Y(n2423) );
NOR2XLTS U3128 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .Y(n2416)
);
OAI2BB2XLTS U3129 ( .B0(n2416), .B1(n2415), .A0N(n1667), .A1N(n2443), .Y(
n2418) );
OAI31X1TS U3130 ( .A0(Add_Subt_result[36]), .A1(n2418), .A2(
Add_Subt_result[35]), .B0(n2417), .Y(n2420) );
AOI32X1TS U3131 ( .A0(n2882), .A1(n2420), .A2(n3008), .B0(n2419), .B1(n2420),
.Y(n2421) );
AOI211X1TS U3132 ( .A0(n2424), .A1(n2423), .B0(n2422), .C0(n2421), .Y(n2453)
);
NOR4X1TS U3133 ( .A(Add_Subt_result[26]), .B(Add_Subt_result[29]), .C(
Add_Subt_result[28]), .D(Add_Subt_result[25]), .Y(n2433) );
NOR2XLTS U3134 ( .A(Add_Subt_result[37]), .B(Add_Subt_result[38]), .Y(n2426)
);
OAI22X1TS U3135 ( .A0(n2426), .A1(n2425), .B0(n2828), .B1(n2921), .Y(n2427)
);
AOI211X1TS U3136 ( .A0(n2429), .A1(Add_Subt_result[33]), .B0(n2428), .C0(
n2427), .Y(n2431) );
NOR2XLTS U3137 ( .A(LZA_output[4]), .B(n2450), .Y(n2437) );
AOI31XLTS U3138 ( .A0(Add_Subt_result[44]), .A1(n3009), .A2(n2896), .B0(
Add_Subt_result[48]), .Y(n2439) );
NOR2XLTS U3139 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .Y(n2440)
);
NOR2X1TS U3140 ( .A(Add_Subt_result[39]), .B(Add_Subt_result[40]), .Y(n2824)
);
AOI2BB2XLTS U3141 ( .B0(n2443), .B1(Add_Subt_result[28]), .A0N(n2824), .A1N(
n2442), .Y(n2445) );
AOI21X1TS U3142 ( .A0(Add_Subt_result[16]), .A1(n2449), .B0(n2448), .Y(n2452) );
NOR2XLTS U3143 ( .A(n1648), .B(n2450), .Y(n2451) );
AOI22X1TS U3144 ( .A0(n2560), .A1(n1662), .B0(n2454), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2455) );
OAI21XLTS U3145 ( .A0(n2562), .A1(n3029), .B0(n2455), .Y(n2456) );
AOI22X1TS U3146 ( .A0(n2560), .A1(n1664), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2458) );
OAI21XLTS U3147 ( .A0(n2562), .A1(n3030), .B0(n2458), .Y(n2459) );
OAI222X1TS U3148 ( .A0(n2872), .A1(n2485), .B0(n2483), .B1(n2466), .C0(n2467), .C1(n2468), .Y(n1468) );
AOI22X1TS U3149 ( .A0(n2560), .A1(n1661), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2460) );
OAI21XLTS U3150 ( .A0(n2562), .A1(n3027), .B0(n2460), .Y(n2461) );
AOI22X1TS U3151 ( .A0(n2560), .A1(n1665), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2462) );
OAI222X1TS U3152 ( .A0(n2925), .A1(n2485), .B0(n2483), .B1(n2464), .C0(n2467), .C1(n2465), .Y(n1467) );
OAI222X1TS U3153 ( .A0(n2931), .A1(n2485), .B0(n2483), .B1(n2465), .C0(n2467), .C1(n2464), .Y(n1471) );
OAI222X1TS U3154 ( .A0(n2928), .A1(n2485), .B0(n2483), .B1(n2468), .C0(n2467), .C1(n2466), .Y(n1470) );
AOI22X1TS U3155 ( .A0(n2560), .A1(n1666), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2469) );
OAI21XLTS U3156 ( .A0(n3026), .A1(n2562), .B0(n2469), .Y(n2470) );
AOI22X1TS U3157 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n2476), .B0(n2560), .B1(n1659), .Y(n2471) );
OAI21XLTS U3158 ( .A0(n3025), .A1(n2562), .B0(n2471), .Y(n2472) );
OAI222X1TS U3159 ( .A0(n2932), .A1(n2485), .B0(n2483), .B1(n2473), .C0(n2467), .C1(n2474), .Y(n1472) );
OAI222X1TS U3160 ( .A0(n2871), .A1(n2485), .B0(n2483), .B1(n2474), .C0(n2467), .C1(n2473), .Y(n1466) );
AOI22X1TS U3161 ( .A0(n2560), .A1(n1660), .B0(n2457), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n2475) );
OAI2BB1X1TS U3162 ( .A0N(n2476), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2475), .Y(n2477)
);
NOR3X1TS U3163 ( .A(n1781), .B(n2478), .C(n2477), .Y(n2484) );
AOI22X1TS U3164 ( .A0(n2560), .A1(n1647), .B0(n2457), .B1(n1660), .Y(n2479)
);
OAI21XLTS U3165 ( .A0(n2562), .A1(n3032), .B0(n2479), .Y(n2481) );
OAI222X1TS U3166 ( .A0(n2485), .A1(n2874), .B0(n2483), .B1(n2484), .C0(n2467), .C1(n2482), .Y(n1473) );
OAI222X1TS U3167 ( .A0(n2870), .A1(n2485), .B0(n2467), .B1(n2484), .C0(n2483), .C1(n2482), .Y(n1465) );
INVX6TS U3168 ( .A(n2902), .Y(n2566) );
NOR2BX1TS U3169 ( .AN(Sgf_normalized_result[54]), .B(n2572), .Y(n2486) );
XOR2X1TS U3170 ( .A(n3039), .B(n2486), .Y(DP_OP_45J154_125_8406_n60) );
CLKINVX6TS U3171 ( .A(n2902), .Y(n2533) );
NOR2XLTS U3172 ( .A(n3034), .B(n2572), .Y(n2487) );
XOR2X1TS U3173 ( .A(n3039), .B(n2487), .Y(DP_OP_45J154_125_8406_n61) );
NOR2XLTS U3174 ( .A(n3024), .B(n2572), .Y(n2488) );
XOR2X1TS U3175 ( .A(n3039), .B(n2488), .Y(DP_OP_45J154_125_8406_n62) );
NOR2XLTS U3176 ( .A(n3023), .B(n2572), .Y(n2489) );
XOR2X1TS U3177 ( .A(n3039), .B(n2489), .Y(DP_OP_45J154_125_8406_n63) );
XOR2X1TS U3178 ( .A(n3039), .B(n2490), .Y(DP_OP_45J154_125_8406_n64) );
NOR2XLTS U3179 ( .A(n3006), .B(n2572), .Y(n2491) );
XOR2X1TS U3180 ( .A(n3039), .B(n2491), .Y(DP_OP_45J154_125_8406_n65) );
NOR2XLTS U3181 ( .A(n3005), .B(n2570), .Y(n2492) );
XOR2X1TS U3182 ( .A(n3039), .B(n2492), .Y(DP_OP_45J154_125_8406_n66) );
XOR2X1TS U3183 ( .A(n3039), .B(n2493), .Y(DP_OP_45J154_125_8406_n67) );
NOR2XLTS U3184 ( .A(n2994), .B(n2570), .Y(n2494) );
XOR2X1TS U3185 ( .A(n3039), .B(n2494), .Y(DP_OP_45J154_125_8406_n68) );
NOR2XLTS U3186 ( .A(n2983), .B(n2570), .Y(n2495) );
XOR2X1TS U3187 ( .A(n3039), .B(n2495), .Y(DP_OP_45J154_125_8406_n69) );
NOR2XLTS U3188 ( .A(n2982), .B(n2570), .Y(n2496) );
XOR2X1TS U3189 ( .A(n3039), .B(n2496), .Y(DP_OP_45J154_125_8406_n70) );
NOR2XLTS U3190 ( .A(n2959), .B(n2570), .Y(n2497) );
XOR2X1TS U3191 ( .A(n3039), .B(n2497), .Y(DP_OP_45J154_125_8406_n71) );
NOR2XLTS U3192 ( .A(n2958), .B(n2570), .Y(n2498) );
XOR2X1TS U3193 ( .A(n2567), .B(n2498), .Y(DP_OP_45J154_125_8406_n72) );
NOR2XLTS U3194 ( .A(n2954), .B(n2570), .Y(n2499) );
XOR2X1TS U3195 ( .A(n2567), .B(n2499), .Y(DP_OP_45J154_125_8406_n73) );
NOR2XLTS U3196 ( .A(n2947), .B(n2570), .Y(n2500) );
XOR2X1TS U3197 ( .A(n2567), .B(n2500), .Y(DP_OP_45J154_125_8406_n74) );
INVX4TS U3198 ( .A(n2902), .Y(n2537) );
NOR2XLTS U3199 ( .A(n2946), .B(n2566), .Y(n2501) );
XOR2X1TS U3200 ( .A(n2567), .B(n2501), .Y(DP_OP_45J154_125_8406_n75) );
NOR2XLTS U3201 ( .A(n2943), .B(n2566), .Y(n2502) );
XOR2X1TS U3202 ( .A(n2567), .B(n2502), .Y(DP_OP_45J154_125_8406_n76) );
NOR2XLTS U3203 ( .A(n2942), .B(n2566), .Y(n2503) );
XOR2X1TS U3204 ( .A(n3039), .B(n2503), .Y(DP_OP_45J154_125_8406_n77) );
NOR2XLTS U3205 ( .A(n2938), .B(n2566), .Y(n2504) );
XOR2X1TS U3206 ( .A(n3039), .B(n2504), .Y(DP_OP_45J154_125_8406_n78) );
NOR2XLTS U3207 ( .A(n2937), .B(n2566), .Y(n2505) );
XOR2X1TS U3208 ( .A(n2512), .B(n2505), .Y(DP_OP_45J154_125_8406_n79) );
NOR2XLTS U3209 ( .A(n2936), .B(n2566), .Y(n2506) );
XOR2X1TS U3210 ( .A(n2512), .B(n2506), .Y(DP_OP_45J154_125_8406_n80) );
NOR2XLTS U3211 ( .A(n2935), .B(n2566), .Y(n2507) );
XOR2X1TS U3212 ( .A(n3039), .B(n2507), .Y(DP_OP_45J154_125_8406_n81) );
NOR2XLTS U3213 ( .A(n2934), .B(n2566), .Y(n2508) );
XOR2X1TS U3214 ( .A(n3039), .B(n2508), .Y(DP_OP_45J154_125_8406_n82) );
NOR2XLTS U3215 ( .A(n2869), .B(n2874), .Y(n2510) );
XOR2X1TS U3216 ( .A(n2512), .B(n2510), .Y(DP_OP_45J154_125_8406_n83) );
NOR2XLTS U3217 ( .A(n2869), .B(n2932), .Y(n2511) );
XOR2X1TS U3218 ( .A(n2512), .B(n2511), .Y(DP_OP_45J154_125_8406_n84) );
XOR2X1TS U3219 ( .A(n2512), .B(n2513), .Y(DP_OP_45J154_125_8406_n85) );
NOR2XLTS U3220 ( .A(n2869), .B(n2928), .Y(n2514) );
XOR2X1TS U3221 ( .A(n2512), .B(n2514), .Y(DP_OP_45J154_125_8406_n86) );
NOR2XLTS U3222 ( .A(n2927), .B(n2566), .Y(n2515) );
XOR2X1TS U3223 ( .A(n2512), .B(n2515), .Y(DP_OP_45J154_125_8406_n87) );
NOR2XLTS U3224 ( .A(n2869), .B(n2872), .Y(n2516) );
XOR2X1TS U3225 ( .A(n2512), .B(n2516), .Y(DP_OP_45J154_125_8406_n88) );
NOR2XLTS U3226 ( .A(n2869), .B(n2925), .Y(n2517) );
XOR2X1TS U3227 ( .A(n2512), .B(n2517), .Y(DP_OP_45J154_125_8406_n89) );
XOR2X1TS U3228 ( .A(n2512), .B(n2518), .Y(DP_OP_45J154_125_8406_n90) );
XOR2X1TS U3229 ( .A(n2512), .B(n2519), .Y(DP_OP_45J154_125_8406_n91) );
XOR2X1TS U3230 ( .A(n2512), .B(n2520), .Y(DP_OP_45J154_125_8406_n92) );
XOR2X1TS U3231 ( .A(n2512), .B(n2521), .Y(DP_OP_45J154_125_8406_n93) );
XOR2X1TS U3232 ( .A(n2512), .B(n2522), .Y(DP_OP_45J154_125_8406_n94) );
XOR2X1TS U3233 ( .A(n2512), .B(n2523), .Y(DP_OP_45J154_125_8406_n95) );
XOR2X1TS U3234 ( .A(n2512), .B(n2524), .Y(DP_OP_45J154_125_8406_n96) );
XOR2X1TS U3235 ( .A(n2567), .B(n2525), .Y(DP_OP_45J154_125_8406_n97) );
XOR2X1TS U3236 ( .A(n2567), .B(n2526), .Y(DP_OP_45J154_125_8406_n98) );
XOR2X1TS U3237 ( .A(n2567), .B(n2527), .Y(DP_OP_45J154_125_8406_n99) );
XOR2X1TS U3238 ( .A(n2567), .B(n2528), .Y(DP_OP_45J154_125_8406_n100) );
XOR2X1TS U3239 ( .A(n2567), .B(n2529), .Y(DP_OP_45J154_125_8406_n101) );
XOR2X1TS U3240 ( .A(n2567), .B(n2530), .Y(DP_OP_45J154_125_8406_n102) );
XOR2X1TS U3241 ( .A(n2567), .B(n2531), .Y(DP_OP_45J154_125_8406_n103) );
XOR2X1TS U3242 ( .A(n2567), .B(n2532), .Y(DP_OP_45J154_125_8406_n104) );
XOR2X1TS U3243 ( .A(n2567), .B(n2534), .Y(DP_OP_45J154_125_8406_n105) );
XOR2X1TS U3244 ( .A(n2567), .B(n2535), .Y(DP_OP_45J154_125_8406_n106) );
XOR2X1TS U3245 ( .A(n2567), .B(n2536), .Y(DP_OP_45J154_125_8406_n107) );
XOR2X1TS U3246 ( .A(n2567), .B(n2538), .Y(DP_OP_45J154_125_8406_n108) );
XOR2X1TS U3247 ( .A(n2567), .B(n2539), .Y(DP_OP_45J154_125_8406_n109) );
XOR2X1TS U3248 ( .A(n2567), .B(n2540), .Y(DP_OP_45J154_125_8406_n110) );
XOR2X1TS U3249 ( .A(n2567), .B(n2541), .Y(DP_OP_45J154_125_8406_n111) );
NAND2X1TS U3250 ( .A(n2877), .B(n2902), .Y(n2542) );
XOR2X1TS U3251 ( .A(n2567), .B(n2542), .Y(DP_OP_45J154_125_8406_n112) );
XOR2X1TS U3252 ( .A(n2567), .B(n2543), .Y(DP_OP_45J154_125_8406_n113) );
XOR2X1TS U3253 ( .A(n3039), .B(n2545), .Y(DP_OP_45J154_125_8406_n114) );
CLKAND2X2TS U3254 ( .A(n2555), .B(DmP[62]), .Y(n2546) );
XOR2X1TS U3255 ( .A(FSM_exp_operation_A_S), .B(n2546), .Y(
DP_OP_42J154_122_8302_n16) );
CLKAND2X2TS U3256 ( .A(n2555), .B(DmP[61]), .Y(n2547) );
XOR2X1TS U3257 ( .A(FSM_exp_operation_A_S), .B(n2547), .Y(
DP_OP_42J154_122_8302_n17) );
CLKAND2X2TS U3258 ( .A(n2555), .B(DmP[60]), .Y(n2548) );
XOR2X1TS U3259 ( .A(FSM_exp_operation_A_S), .B(n2548), .Y(
DP_OP_42J154_122_8302_n18) );
CLKAND2X2TS U3260 ( .A(n2555), .B(DmP[59]), .Y(n2549) );
XOR2X1TS U3261 ( .A(FSM_exp_operation_A_S), .B(n2549), .Y(
DP_OP_42J154_122_8302_n19) );
CLKAND2X2TS U3262 ( .A(n2555), .B(DmP[58]), .Y(n2550) );
XOR2X1TS U3263 ( .A(FSM_exp_operation_A_S), .B(n2550), .Y(
DP_OP_42J154_122_8302_n20) );
AO22XLTS U3264 ( .A0(n1637), .A1(n1686), .B0(n2555), .B1(DmP[57]), .Y(n2551)
);
XOR2X1TS U3265 ( .A(FSM_exp_operation_A_S), .B(n2551), .Y(
DP_OP_42J154_122_8302_n21) );
AO22XLTS U3266 ( .A0(LZA_output[4]), .A1(n1686), .B0(n2555), .B1(DmP[56]),
.Y(n2552) );
XOR2X1TS U3267 ( .A(FSM_exp_operation_A_S), .B(n2552), .Y(
DP_OP_42J154_122_8302_n22) );
AO22XLTS U3268 ( .A0(n1649), .A1(n1686), .B0(n2555), .B1(DmP[55]), .Y(n2553)
);
XOR2X1TS U3269 ( .A(FSM_exp_operation_A_S), .B(n2553), .Y(
DP_OP_42J154_122_8302_n23) );
AO22XLTS U3270 ( .A0(LZA_output[2]), .A1(n1686), .B0(n2555), .B1(DmP[54]),
.Y(n2554) );
XOR2X1TS U3271 ( .A(FSM_exp_operation_A_S), .B(n2554), .Y(
DP_OP_42J154_122_8302_n24) );
AO22XLTS U3272 ( .A0(n1648), .A1(n1686), .B0(n2555), .B1(DmP[53]), .Y(n2556)
);
XOR2X1TS U3273 ( .A(FSM_exp_operation_A_S), .B(n2556), .Y(
DP_OP_42J154_122_8302_n25) );
AO21XLTS U3274 ( .A0(DmP[52]), .A1(n2953), .B0(n2557), .Y(n2558) );
XOR2X1TS U3275 ( .A(FSM_exp_operation_A_S), .B(n2558), .Y(
DP_OP_42J154_122_8302_n26) );
INVX6TS U3276 ( .A(n2902), .Y(n2570) );
AOI22X1TS U3277 ( .A0(n2560), .A1(n1663), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n2561) );
OAI21XLTS U3278 ( .A0(n2562), .A1(n3031), .B0(n2561), .Y(n2563) );
MXI2X1TS U3279 ( .A(n2565), .B(n2927), .S0(n2564), .Y(n1469) );
XOR2X1TS U3280 ( .A(DP_OP_45J154_125_8406_n1), .B(n2567), .Y(n2568) );
INVX2TS U3281 ( .A(n2574), .Y(n2805) );
MX2X1TS U3282 ( .A(Exp_Operation_Module_Data_S[10]), .B(exp_oper_result[10]),
.S0(n2573), .Y(n1428) );
MX2X1TS U3283 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n2572), .Y(
S_Oper_A_exp[10]) );
MX2X1TS U3284 ( .A(Exp_Operation_Module_Data_S[9]), .B(exp_oper_result[9]),
.S0(n2573), .Y(n1429) );
MX2X1TS U3285 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n2572), .Y(
S_Oper_A_exp[9]) );
MX2X1TS U3286 ( .A(Exp_Operation_Module_Data_S[8]), .B(exp_oper_result[8]),
.S0(n2573), .Y(n1430) );
MX2X1TS U3287 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n2572), .Y(
S_Oper_A_exp[8]) );
MX2X1TS U3288 ( .A(Exp_Operation_Module_Data_S[7]), .B(exp_oper_result[7]),
.S0(n2573), .Y(n1431) );
MX2X1TS U3289 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(n2572), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U3290 ( .A(Exp_Operation_Module_Data_S[6]), .B(exp_oper_result[6]),
.S0(n2573), .Y(n1432) );
MX2X1TS U3291 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n2572), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U3292 ( .A(Exp_Operation_Module_Data_S[5]), .B(exp_oper_result[5]),
.S0(n2573), .Y(n1433) );
MX2X1TS U3293 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n2572), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U3294 ( .A(Exp_Operation_Module_Data_S[4]), .B(exp_oper_result[4]),
.S0(n2573), .Y(n1434) );
MX2X1TS U3295 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n2570), .Y(
S_Oper_A_exp[4]) );
MX2X1TS U3296 ( .A(Exp_Operation_Module_Data_S[3]), .B(exp_oper_result[3]),
.S0(n2573), .Y(n1435) );
MX2X1TS U3297 ( .A(DMP[55]), .B(exp_oper_result[3]), .S0(n2570), .Y(
S_Oper_A_exp[3]) );
MX2X1TS U3298 ( .A(DMP[54]), .B(n1658), .S0(n2570), .Y(S_Oper_A_exp[2]) );
MX2X1TS U3299 ( .A(Exp_Operation_Module_Data_S[1]), .B(n1626), .S0(n2573),
.Y(n1437) );
MX2X1TS U3300 ( .A(DMP[53]), .B(n1626), .S0(n2570), .Y(S_Oper_A_exp[1]) );
AO21XLTS U3301 ( .A0(n2573), .A1(exp_oper_result[0]), .B0(n2571), .Y(n1438)
);
MX2X1TS U3302 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n2570), .Y(
S_Oper_A_exp[0]) );
MX2X1TS U3303 ( .A(Exp_Operation_Module_Data_S[2]), .B(n1658), .S0(n2573),
.Y(n1436) );
AO22XLTS U3304 ( .A0(Add_Subt_Sgf_module_S_to_D[0]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[0]), .Y(n1503) );
AO22XLTS U3305 ( .A0(Add_Subt_Sgf_module_S_to_D[1]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[1]), .Y(n1504) );
AO22XLTS U3306 ( .A0(Add_Subt_Sgf_module_S_to_D[2]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[2]), .Y(n1505) );
BUFX3TS U3307 ( .A(n2574), .Y(n2576) );
AO22XLTS U3308 ( .A0(Add_Subt_Sgf_module_S_to_D[3]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[3]), .Y(n1506) );
AO22XLTS U3309 ( .A0(Add_Subt_Sgf_module_S_to_D[4]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[4]), .Y(n1507) );
AO22XLTS U3310 ( .A0(Add_Subt_Sgf_module_S_to_D[6]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[6]), .Y(n1509) );
AO22XLTS U3311 ( .A0(Add_Subt_Sgf_module_S_to_D[8]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[8]), .Y(n1511) );
AO22XLTS U3312 ( .A0(Add_Subt_Sgf_module_S_to_D[9]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[9]), .Y(n1512) );
AO22XLTS U3313 ( .A0(Add_Subt_Sgf_module_S_to_D[10]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[10]), .Y(n1513) );
CLKINVX6TS U3314 ( .A(n2574), .Y(n2577) );
AO22XLTS U3315 ( .A0(Add_Subt_Sgf_module_S_to_D[12]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[12]), .Y(n1515) );
AO22XLTS U3316 ( .A0(Add_Subt_Sgf_module_S_to_D[13]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[13]), .Y(n1516) );
AO22XLTS U3317 ( .A0(Add_Subt_Sgf_module_S_to_D[14]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[14]), .Y(n1517) );
AO22XLTS U3318 ( .A0(Add_Subt_Sgf_module_S_to_D[15]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[15]), .Y(n1518) );
AO22XLTS U3319 ( .A0(Add_Subt_Sgf_module_S_to_D[16]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[16]), .Y(n1519) );
AO22XLTS U3320 ( .A0(Add_Subt_Sgf_module_S_to_D[18]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[18]), .Y(n1521) );
AO22XLTS U3321 ( .A0(Add_Subt_Sgf_module_S_to_D[20]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[20]), .Y(n1523) );
AO22XLTS U3322 ( .A0(Add_Subt_Sgf_module_S_to_D[34]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[34]), .Y(n1537) );
AO22XLTS U3323 ( .A0(Add_Subt_Sgf_module_S_to_D[33]), .A1(n2578), .B0(n1677),
.B1(Add_Subt_result[33]), .Y(n1536) );
AO22XLTS U3324 ( .A0(Add_Subt_Sgf_module_S_to_D[32]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[32]), .Y(n1535) );
AO22XLTS U3325 ( .A0(Add_Subt_Sgf_module_S_to_D[23]), .A1(n2578), .B0(n1677),
.B1(Add_Subt_result[23]), .Y(n1526) );
AO22XLTS U3326 ( .A0(Add_Subt_Sgf_module_S_to_D[24]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[24]), .Y(n1527) );
AO22XLTS U3327 ( .A0(Add_Subt_Sgf_module_S_to_D[30]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[30]), .Y(n1533) );
AO22XLTS U3328 ( .A0(Add_Subt_Sgf_module_S_to_D[25]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[25]), .Y(n1528) );
AO22XLTS U3329 ( .A0(Add_Subt_Sgf_module_S_to_D[26]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[26]), .Y(n1529) );
AO22XLTS U3330 ( .A0(Add_Subt_Sgf_module_S_to_D[28]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[28]), .Y(n1531) );
AOI22X1TS U3331 ( .A0(n2790), .A1(n1625), .B0(n2589), .B1(n2586), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
OAI22X1TS U3332 ( .A0(n2597), .A1(n2580), .B0(n2596), .B1(n2579), .Y(n2595)
);
OAI22X1TS U3333 ( .A0(n2583), .A1(n2582), .B0(n2581), .B1(n1625), .Y(n2594)
);
OAI22X1TS U3334 ( .A0(n2587), .A1(n2586), .B0(n2585), .B1(n2584), .Y(n2593)
);
OAI22X1TS U3335 ( .A0(n2591), .A1(n2590), .B0(n2589), .B1(n2588), .Y(n2592)
);
OR4X2TS U3336 ( .A(n2595), .B(n2594), .C(n2593), .D(n2592), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
INVX2TS U3337 ( .A(n2596), .Y(n2604) );
AOI22X1TS U3338 ( .A0(n2714), .A1(n2602), .B0(n2788), .B1(n2604), .Y(n2601)
);
INVX2TS U3339 ( .A(n2597), .Y(n2608) );
AOI22X1TS U3340 ( .A0(n2753), .A1(n2608), .B0(n1741), .B1(n2606), .Y(n2600)
);
AOI22X1TS U3341 ( .A0(n2793), .A1(n2607), .B0(n2790), .B1(n1630), .Y(n2599)
);
AOI22X1TS U3342 ( .A0(n1705), .A1(n1593), .B0(n2798), .B1(n2603), .Y(n2598)
);
NAND4XLTS U3343 ( .A(n2601), .B(n2600), .C(n2599), .D(n2598), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
AOI22X1TS U3344 ( .A0(n2714), .A1(n2603), .B0(n2788), .B1(n2602), .Y(n2612)
);
AOI22X1TS U3345 ( .A0(n2796), .A1(n2604), .B0(n1741), .B1(n1630), .Y(n2611)
);
AOI22X1TS U3346 ( .A0(n2793), .A1(n2606), .B0(n2790), .B1(n2605), .Y(n2610)
);
AOI22X1TS U3347 ( .A0(n1705), .A1(n2608), .B0(n2671), .B1(n2607), .Y(n2609)
);
NAND4XLTS U3348 ( .A(n2612), .B(n2611), .C(n2610), .D(n2609), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AOI22X1TS U3349 ( .A0(n2671), .A1(n2623), .B0(n1705), .B1(n2613), .Y(n2614)
);
OAI221XLTS U3350 ( .A0(n2650), .A1(n2615), .B0(n2651), .B1(n2625), .C0(n2614), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U3351 ( .A0(n1705), .A1(n2617), .B0(n2671), .B1(n2630), .Y(n2618)
);
OAI221XLTS U3352 ( .A0(n2650), .A1(n2619), .B0(n2651), .B1(n2632), .C0(n2618), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI22X1TS U3353 ( .A0(n2671), .A1(n1636), .B0(n1705), .B1(n2620), .Y(n2621)
);
OAI221XLTS U3354 ( .A0(n2650), .A1(n2622), .B0(n2651), .B1(n2635), .C0(n2621), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI22X1TS U3355 ( .A0(n2671), .A1(n2637), .B0(n1705), .B1(n2623), .Y(n2624)
);
OAI221XLTS U3356 ( .A0(n2650), .A1(n2625), .B0(n2651), .B1(n2640), .C0(n2624), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI22X1TS U3357 ( .A0(n1705), .A1(n2630), .B0(n2671), .B1(n2642), .Y(n2631)
);
OAI221XLTS U3358 ( .A0(n2650), .A1(n2632), .B0(n2651), .B1(n2645), .C0(n2631), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI22X1TS U3359 ( .A0(n2800), .A1(n1636), .B0(n2671), .B1(n2646), .Y(n2633)
);
OAI221XLTS U3360 ( .A0(n2650), .A1(n2635), .B0(n2651), .B1(n2634), .C0(n2633), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U3361 ( .A0(n2800), .A1(n2637), .B0(n2671), .B1(n2636), .Y(n2638)
);
OAI221XLTS U3362 ( .A0(n2650), .A1(n2640), .B0(n2651), .B1(n2639), .C0(n2638), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U3363 ( .A0(n2800), .A1(n2642), .B0(n2798), .B1(n2641), .Y(n2643)
);
OAI221XLTS U3364 ( .A0(n2650), .A1(n2645), .B0(n2651), .B1(n2644), .C0(n2643), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
AOI22X1TS U3365 ( .A0(n2753), .A1(n2646), .B0(n2793), .B1(n1635), .Y(n2647)
);
OAI221XLTS U3366 ( .A0(n2650), .A1(n2649), .B0(n2651), .B1(n2648), .C0(n2647), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U3367 ( .A0(n2671), .A1(n2672), .B0(n2204), .B1(n1653), .Y(n2656)
);
AOI22X1TS U3368 ( .A0(n2800), .A1(n1634), .B0(n2795), .B1(n1651), .Y(n2655)
);
AOI22X1TS U3369 ( .A0(n2796), .A1(n1602), .B0(n2790), .B1(n2688), .Y(n2654)
);
NAND2X1TS U3370 ( .A(n2652), .B(n2651), .Y(n2653) );
NAND4XLTS U3371 ( .A(n2656), .B(n2655), .C(n2654), .D(n2653), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U3372 ( .A0(n2671), .A1(n1653), .B0(n2793), .B1(n1651), .Y(n2657)
);
OAI31X1TS U3373 ( .A0(n2666), .A1(n2665), .A2(n2658), .B0(n2657), .Y(n2662)
);
AOI22X1TS U3374 ( .A0(n2714), .A1(n2672), .B0(n2780), .B1(n2659), .Y(n2661)
);
AOI22X1TS U3375 ( .A0(n2795), .A1(n2688), .B0(n2790), .B1(n2695), .Y(n2660)
);
NAND3BXLTS U3376 ( .AN(n2662), .B(n2661), .C(n2660), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U3377 ( .A0(n2671), .A1(n1651), .B0(n2793), .B1(n2688), .Y(n2663)
);
OAI31X1TS U3378 ( .A0(n2666), .A1(n2665), .A2(n2664), .B0(n2663), .Y(n2669)
);
AOI22X1TS U3379 ( .A0(n2714), .A1(n1653), .B0(n2780), .B1(n2672), .Y(n2668)
);
AOI22X1TS U3380 ( .A0(n2795), .A1(n2695), .B0(n2790), .B1(n2703), .Y(n2667)
);
NAND3BXLTS U3381 ( .AN(n2669), .B(n2668), .C(n2667), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI22X1TS U3382 ( .A0(n2714), .A1(n2688), .B0(n2788), .B1(n1651), .Y(n2676)
);
AOI22X1TS U3383 ( .A0(n2796), .A1(n1653), .B0(n2795), .B1(n2709), .Y(n2675)
);
AOI22X1TS U3384 ( .A0(Add_Subt_result[36]), .A1(n2206), .B0(DmP[16]), .B1(
n2766), .Y(n2670) );
OAI21X4TS U3385 ( .A0(n3021), .A1(n2723), .B0(n2670), .Y(n2716) );
AOI22X1TS U3386 ( .A0(n2793), .A1(n2703), .B0(n2790), .B1(n2716), .Y(n2674)
);
AOI22X1TS U3387 ( .A0(n2800), .A1(n2672), .B0(n2671), .B1(n2695), .Y(n2673)
);
NAND4XLTS U3388 ( .A(n2676), .B(n2675), .C(n2674), .D(n2673), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI22X1TS U3389 ( .A0(n2714), .A1(n2695), .B0(n2780), .B1(n2688), .Y(n2681)
);
AOI22X1TS U3390 ( .A0(n2796), .A1(n1651), .B0(n2795), .B1(n2716), .Y(n2680)
);
AOI22X1TS U3391 ( .A0(Add_Subt_result[17]), .A1(n2700), .B0(DmP[15]), .B1(
n2766), .Y(n2677) );
OAI21X4TS U3392 ( .A0(n3013), .A1(n2786), .B0(n2677), .Y(n2724) );
AOI22X1TS U3393 ( .A0(n2793), .A1(n2709), .B0(n1752), .B1(n2724), .Y(n2679)
);
AOI22X1TS U3394 ( .A0(n2800), .A1(n1653), .B0(n2671), .B1(n2703), .Y(n2678)
);
NAND4XLTS U3395 ( .A(n2681), .B(n2680), .C(n2679), .D(n2678), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U3396 ( .A0(n2714), .A1(n2703), .B0(n2788), .B1(n2695), .Y(n2686)
);
AOI22X1TS U3397 ( .A0(n2796), .A1(n2688), .B0(n2795), .B1(n2724), .Y(n2685)
);
AOI22X1TS U3398 ( .A0(Add_Subt_result[38]), .A1(n2206), .B0(DmP[14]), .B1(
n2815), .Y(n2682) );
OAI21X4TS U3399 ( .A0(n2875), .A1(n2723), .B0(n2682), .Y(n2730) );
AOI22X1TS U3400 ( .A0(n2793), .A1(n2716), .B0(n2790), .B1(n2730), .Y(n2684)
);
AOI22X1TS U3401 ( .A0(n2800), .A1(n1651), .B0(n2671), .B1(n2709), .Y(n2683)
);
NAND4XLTS U3402 ( .A(n2686), .B(n2685), .C(n2684), .D(n2683), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AOI22X1TS U3403 ( .A0(n2714), .A1(n2709), .B0(n2788), .B1(n2703), .Y(n2692)
);
AOI22X1TS U3404 ( .A0(n2796), .A1(n2695), .B0(n2795), .B1(n2730), .Y(n2691)
);
AOI22X1TS U3405 ( .A0(Add_Subt_result[39]), .A1(n2206), .B0(DmP[13]), .B1(
n2815), .Y(n2687) );
OAI21X4TS U3406 ( .A0(n3022), .A1(n1579), .B0(n2687), .Y(n2736) );
AOI22X1TS U3407 ( .A0(n2793), .A1(n2724), .B0(n2790), .B1(n2736), .Y(n2690)
);
AOI22X1TS U3408 ( .A0(n2800), .A1(n2688), .B0(n2671), .B1(n2716), .Y(n2689)
);
NAND4XLTS U3409 ( .A(n2692), .B(n2691), .C(n2690), .D(n2689), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U3410 ( .A0(n2714), .A1(n2716), .B0(n2788), .B1(n2709), .Y(n2699)
);
AOI22X1TS U3411 ( .A0(n2796), .A1(n2703), .B0(n2795), .B1(n2736), .Y(n2698)
);
AOI22X1TS U3412 ( .A0(Add_Subt_result[40]), .A1(n2206), .B0(DmP[12]), .B1(
n2815), .Y(n2694) );
OAI21X4TS U3413 ( .A0(n1629), .A1(n1579), .B0(n2694), .Y(n2742) );
AOI22X1TS U3414 ( .A0(n2793), .A1(n2730), .B0(n2790), .B1(n2742), .Y(n2697)
);
AOI22X1TS U3415 ( .A0(n2800), .A1(n2695), .B0(n2798), .B1(n2724), .Y(n2696)
);
NAND4XLTS U3416 ( .A(n2699), .B(n2698), .C(n2697), .D(n2696), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U3417 ( .A0(n2714), .A1(n2724), .B0(n2788), .B1(n2716), .Y(n2707)
);
AOI22X1TS U3418 ( .A0(n2796), .A1(n2709), .B0(n2795), .B1(n2742), .Y(n2706)
);
AOI22X1TS U3419 ( .A0(Add_Subt_result[13]), .A1(n2700), .B0(DmP[11]), .B1(
n2815), .Y(n2701) );
OAI21X4TS U3420 ( .A0(n2702), .A1(n2786), .B0(n2701), .Y(n2748) );
AOI22X1TS U3421 ( .A0(n2793), .A1(n2736), .B0(n2790), .B1(n2748), .Y(n2705)
);
AOI22X1TS U3422 ( .A0(n2800), .A1(n2703), .B0(n2798), .B1(n2730), .Y(n2704)
);
NAND4XLTS U3423 ( .A(n2707), .B(n2706), .C(n2705), .D(n2704), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U3424 ( .A0(n2714), .A1(n2730), .B0(n2788), .B1(n2724), .Y(n2713)
);
AOI22X1TS U3425 ( .A0(n2796), .A1(n2716), .B0(n1741), .B1(n2748), .Y(n2712)
);
AOI22X1TS U3426 ( .A0(Add_Subt_result[42]), .A1(n2206), .B0(DmP[10]), .B1(
n2766), .Y(n2708) );
OAI21X4TS U3427 ( .A0(n3015), .A1(n1579), .B0(n2708), .Y(n2755) );
AOI22X1TS U3428 ( .A0(n2793), .A1(n2742), .B0(n2790), .B1(n2755), .Y(n2711)
);
AOI22X1TS U3429 ( .A0(n2800), .A1(n2709), .B0(n2798), .B1(n2736), .Y(n2710)
);
NAND4XLTS U3430 ( .A(n2713), .B(n2712), .C(n2711), .D(n2710), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U3431 ( .A0(n2714), .A1(n2736), .B0(n2780), .B1(n2730), .Y(n2720)
);
AOI22X1TS U3432 ( .A0(n2753), .A1(n2724), .B0(n2795), .B1(n2755), .Y(n2719)
);
AOI22X1TS U3433 ( .A0(Add_Subt_result[11]), .A1(n2700), .B0(DmP[9]), .B1(
n2766), .Y(n2715) );
OAI21X4TS U3434 ( .A0(n2907), .A1(n1675), .B0(n2715), .Y(n2761) );
AOI22X1TS U3435 ( .A0(n2204), .A1(n2748), .B0(n2790), .B1(n2761), .Y(n2718)
);
AOI22X1TS U3436 ( .A0(n2800), .A1(n2716), .B0(n2798), .B1(n2742), .Y(n2717)
);
NAND4XLTS U3437 ( .A(n2720), .B(n2719), .C(n2718), .D(n2717), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U3438 ( .A0(n2714), .A1(n2742), .B0(n2780), .B1(n2736), .Y(n2728)
);
AOI22X1TS U3439 ( .A0(n2796), .A1(n2730), .B0(n1741), .B1(n2761), .Y(n2727)
);
AOI22X1TS U3440 ( .A0(Add_Subt_result[44]), .A1(n2206), .B0(DmP[8]), .B1(
n2766), .Y(n2722) );
OAI21X4TS U3441 ( .A0(n3017), .A1(n2723), .B0(n2722), .Y(n2768) );
AOI22X1TS U3442 ( .A0(n2204), .A1(n2755), .B0(n2790), .B1(n2768), .Y(n2726)
);
AOI22X1TS U3443 ( .A0(n2800), .A1(n2724), .B0(n2798), .B1(n2748), .Y(n2725)
);
NAND4XLTS U3444 ( .A(n2728), .B(n2727), .C(n2726), .D(n2725), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U3445 ( .A0(n2714), .A1(n2748), .B0(n2780), .B1(n2742), .Y(n2734)
);
AOI22X1TS U3446 ( .A0(n2753), .A1(n2736), .B0(n1741), .B1(n2768), .Y(n2733)
);
AOI22X1TS U3447 ( .A0(Add_Subt_result[45]), .A1(n2206), .B0(DmP[7]), .B1(
n2815), .Y(n2729) );
OAI21X4TS U3448 ( .A0(n3004), .A1(n1579), .B0(n2729), .Y(n2775) );
AOI22X1TS U3449 ( .A0(n2204), .A1(n2761), .B0(n2790), .B1(n2775), .Y(n2732)
);
AOI22X1TS U3450 ( .A0(n2800), .A1(n2730), .B0(n2798), .B1(n2755), .Y(n2731)
);
NAND4XLTS U3451 ( .A(n2734), .B(n2733), .C(n2732), .D(n2731), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U3452 ( .A0(n2714), .A1(n2755), .B0(n2780), .B1(n2748), .Y(n2740)
);
AOI22X1TS U3453 ( .A0(n2753), .A1(n2742), .B0(n1741), .B1(n2775), .Y(n2739)
);
AOI22X1TS U3454 ( .A0(Add_Subt_result[46]), .A1(n2693), .B0(DmP[6]), .B1(
n2815), .Y(n2735) );
OAI21X4TS U3455 ( .A0(n2897), .A1(n1579), .B0(n2735), .Y(n2781) );
AOI22X1TS U3456 ( .A0(n2204), .A1(n2768), .B0(n2790), .B1(n2781), .Y(n2738)
);
AOI22X1TS U3457 ( .A0(n2800), .A1(n2736), .B0(n2798), .B1(n2761), .Y(n2737)
);
NAND4XLTS U3458 ( .A(n2740), .B(n2739), .C(n2738), .D(n2737), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U3459 ( .A0(n2714), .A1(n2761), .B0(n2780), .B1(n2755), .Y(n2746)
);
AOI22X1TS U3460 ( .A0(n2753), .A1(n2748), .B0(n2795), .B1(n2781), .Y(n2745)
);
AOI22X1TS U3461 ( .A0(Add_Subt_result[7]), .A1(n2700), .B0(DmP[5]), .B1(
n2766), .Y(n2741) );
OAI21X4TS U3462 ( .A0(n2901), .A1(n2786), .B0(n2741), .Y(n2799) );
AOI22X1TS U3463 ( .A0(n2793), .A1(n2775), .B0(n2790), .B1(n2799), .Y(n2744)
);
AOI22X1TS U3464 ( .A0(n2800), .A1(n2742), .B0(n2798), .B1(n2768), .Y(n2743)
);
NAND4XLTS U3465 ( .A(n2746), .B(n2745), .C(n2744), .D(n2743), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U3466 ( .A0(n2714), .A1(n2768), .B0(n2780), .B1(n2761), .Y(n2752)
);
AOI22X1TS U3467 ( .A0(n2753), .A1(n2755), .B0(n2795), .B1(n2799), .Y(n2751)
);
AOI22X1TS U3468 ( .A0(Add_Subt_result[48]), .A1(n2206), .B0(DmP[4]), .B1(
n2721), .Y(n2747) );
AOI22X1TS U3469 ( .A0(n2793), .A1(n2781), .B0(n2790), .B1(n1650), .Y(n2750)
);
AOI22X1TS U3470 ( .A0(n2800), .A1(n2748), .B0(n2798), .B1(n2775), .Y(n2749)
);
NAND4XLTS U3471 ( .A(n2752), .B(n2751), .C(n2750), .D(n2749), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U3472 ( .A0(n2714), .A1(n2775), .B0(n2780), .B1(n2768), .Y(n2759)
);
AOI22X1TS U3473 ( .A0(n2753), .A1(n2761), .B0(n2795), .B1(n1650), .Y(n2758)
);
AOI22X1TS U3474 ( .A0(Add_Subt_result[49]), .A1(n2693), .B0(DmP[3]), .B1(
n2815), .Y(n2754) );
OAI2BB1X2TS U3475 ( .A0N(n1668), .A1N(n2700), .B0(n2754), .Y(n2787) );
AOI22X1TS U3476 ( .A0(n2793), .A1(n2799), .B0(n2790), .B1(n2787), .Y(n2757)
);
AOI22X1TS U3477 ( .A0(n2800), .A1(n2755), .B0(n2798), .B1(n2781), .Y(n2756)
);
NAND4XLTS U3478 ( .A(n2759), .B(n2758), .C(n2757), .D(n2756), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U3479 ( .A0(n2714), .A1(n2781), .B0(n2780), .B1(n2775), .Y(n2765)
);
AOI22X1TS U3480 ( .A0(n2796), .A1(n2768), .B0(n2795), .B1(n2787), .Y(n2764)
);
AOI22X1TS U3481 ( .A0(Add_Subt_result[50]), .A1(n2773), .B0(DmP[2]), .B1(
n2766), .Y(n2760) );
AOI22X1TS U3482 ( .A0(n2793), .A1(n1650), .B0(n2790), .B1(n2791), .Y(n2763)
);
AOI22X1TS U3483 ( .A0(n2800), .A1(n2761), .B0(n2798), .B1(n2799), .Y(n2762)
);
NAND4XLTS U3484 ( .A(n2765), .B(n2764), .C(n2763), .D(n2762), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U3485 ( .A0(n2714), .A1(n2799), .B0(n2780), .B1(n2781), .Y(n2772)
);
AOI22X1TS U3486 ( .A0(n2796), .A1(n2775), .B0(n2795), .B1(n2791), .Y(n2771)
);
AOI22X1TS U3487 ( .A0(Add_Subt_result[51]), .A1(n2206), .B0(DmP[1]), .B1(
n2766), .Y(n2767) );
AOI22X1TS U3488 ( .A0(n2793), .A1(n2787), .B0(n2790), .B1(n2797), .Y(n2770)
);
AOI22X1TS U3489 ( .A0(n2800), .A1(n2768), .B0(n2798), .B1(n1650), .Y(n2769)
);
NAND4XLTS U3490 ( .A(n2772), .B(n2771), .C(n2770), .D(n2769), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U3491 ( .A0(n2714), .A1(n1650), .B0(n2780), .B1(n2799), .Y(n2779)
);
AOI22X1TS U3492 ( .A0(Add_Subt_result[52]), .A1(n2693), .B0(DmP[0]), .B1(
n2815), .Y(n2774) );
AOI22X1TS U3493 ( .A0(n2796), .A1(n2781), .B0(n2790), .B1(n2792), .Y(n2778)
);
AOI22X1TS U3494 ( .A0(n2793), .A1(n2791), .B0(n1741), .B1(n2797), .Y(n2777)
);
AOI22X1TS U3495 ( .A0(n2800), .A1(n2775), .B0(n2798), .B1(n2787), .Y(n2776)
);
NAND4XLTS U3496 ( .A(n2779), .B(n2778), .C(n2777), .D(n2776), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U3497 ( .A0(n2714), .A1(n2787), .B0(n2780), .B1(n1650), .Y(n2785)
);
AOI22X1TS U3498 ( .A0(n2796), .A1(n2799), .B0(n2795), .B1(n2792), .Y(n2784)
);
OAI22X1TS U3499 ( .A0(n2899), .A1(n2786), .B0(n3035), .B1(n1579), .Y(n2794)
);
AOI22X1TS U3500 ( .A0(n2793), .A1(n2797), .B0(n2790), .B1(n2794), .Y(n2783)
);
AOI22X1TS U3501 ( .A0(n2800), .A1(n2781), .B0(n2798), .B1(n2791), .Y(n2782)
);
NAND4XLTS U3502 ( .A(n2785), .B(n2784), .C(n2783), .D(n2782), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI22X1TS U3503 ( .A0(n2898), .A1(n2786), .B0(n3036), .B1(n1579), .Y(n2789)
);
AOI22X1TS U3504 ( .A0(n2790), .A1(n2789), .B0(n2780), .B1(n2787), .Y(n2804)
);
AOI22X1TS U3505 ( .A0(n2793), .A1(n2792), .B0(n2714), .B1(n2791), .Y(n2803)
);
AOI22X1TS U3506 ( .A0(n2796), .A1(n1650), .B0(n1741), .B1(n2794), .Y(n2802)
);
AOI22X1TS U3507 ( .A0(n2800), .A1(n2799), .B0(n2798), .B1(n2797), .Y(n2801)
);
NAND4XLTS U3508 ( .A(n2804), .B(n2803), .C(n2802), .D(n2801), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
AOI21X1TS U3509 ( .A0(n2807), .A1(n2806), .B0(n2578), .Y(n2812) );
OAI21X1TS U3510 ( .A0(n2190), .A1(n2808), .B0(n2838), .Y(n2814) );
NAND3XLTS U3511 ( .A(n2812), .B(n2811), .C(n2810), .Y(n1561) );
NAND4XLTS U3512 ( .A(n2820), .B(n2819), .C(n2818), .D(n2817), .Y(n1558) );
AOI21X1TS U3513 ( .A0(Add_Subt_result[49]), .A1(n3007), .B0(
Add_Subt_result[51]), .Y(n2821) );
OAI32X1TS U3514 ( .A0(Add_Subt_result[54]), .A1(Add_Subt_result[52]), .A2(
n2821), .B0(n2899), .B1(Add_Subt_result[54]), .Y(n2822) );
AOI31XLTS U3515 ( .A0(n2823), .A1(Add_Subt_result[45]), .A2(n3009), .B0(
n2822), .Y(n2827) );
NAND4XLTS U3516 ( .A(Add_Subt_result[37]), .B(n1669), .C(n2824), .D(n3011),
.Y(n2826) );
OAI211XLTS U3517 ( .A0(n2828), .A1(n3020), .B0(n2827), .C0(n2826), .Y(n2829)
);
NOR4X1TS U3518 ( .A(n2832), .B(n2831), .C(n2830), .D(n2829), .Y(n2834) );
AOI32X1TS U3519 ( .A0(n2836), .A1(n2835), .A2(n2834), .B0(n3038), .B1(n2833),
.Y(n1499) );
OA22X1TS U3520 ( .A0(n2846), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n2837), .Y(n1425) );
BUFX4TS U3521 ( .A(n2837), .Y(n2840) );
OA22X1TS U3522 ( .A0(n1626), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[53]), .Y(n1424) );
OA22X1TS U3523 ( .A0(n2846), .A1(final_result_ieee[54]), .B0(n1658), .B1(
n2840), .Y(n1423) );
OA22X1TS U3524 ( .A0(exp_oper_result[3]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[55]), .Y(n1422) );
OA22X1TS U3525 ( .A0(exp_oper_result[4]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[56]), .Y(n1421) );
OA22X1TS U3526 ( .A0(n2846), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n2840), .Y(n1420) );
OA22X1TS U3527 ( .A0(exp_oper_result[6]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[58]), .Y(n1419) );
OA22X1TS U3528 ( .A0(exp_oper_result[7]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[59]), .Y(n1418) );
OA22X1TS U3529 ( .A0(exp_oper_result[8]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[60]), .Y(n1417) );
OA22X1TS U3530 ( .A0(exp_oper_result[9]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[61]), .Y(n1416) );
OA22X1TS U3531 ( .A0(exp_oper_result[10]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[62]), .Y(n1415) );
OAI2BB2XLTS U3532 ( .B0(n2877), .B1(n2840), .A0N(final_result_ieee[0]),
.A1N(n1581), .Y(n1414) );
OAI2BB2XLTS U3533 ( .B0(n2878), .B1(n2840), .A0N(final_result_ieee[1]),
.A1N(n2844), .Y(n1413) );
OAI2BB2XLTS U3534 ( .B0(n2879), .B1(n2840), .A0N(final_result_ieee[2]),
.A1N(n1581), .Y(n1412) );
OAI2BB2XLTS U3535 ( .B0(n2880), .B1(n2840), .A0N(final_result_ieee[3]),
.A1N(n2844), .Y(n1411) );
BUFX4TS U3536 ( .A(n2837), .Y(n2841) );
OAI2BB2XLTS U3537 ( .B0(n2903), .B1(n2841), .A0N(final_result_ieee[4]),
.A1N(n1581), .Y(n1410) );
OAI2BB2XLTS U3538 ( .B0(n2904), .B1(n2841), .A0N(final_result_ieee[5]),
.A1N(n2844), .Y(n1409) );
OAI2BB2XLTS U3539 ( .B0(n2905), .B1(n2841), .A0N(final_result_ieee[6]),
.A1N(n1581), .Y(n1408) );
OAI2BB2XLTS U3540 ( .B0(n2906), .B1(n2841), .A0N(final_result_ieee[7]),
.A1N(n1581), .Y(n1407) );
OAI2BB2XLTS U3541 ( .B0(n2908), .B1(n2841), .A0N(final_result_ieee[8]),
.A1N(n2844), .Y(n1406) );
OAI2BB2XLTS U3542 ( .B0(n2909), .B1(n2841), .A0N(final_result_ieee[9]),
.A1N(n1581), .Y(n1405) );
OAI2BB2XLTS U3543 ( .B0(n2910), .B1(n2841), .A0N(final_result_ieee[10]),
.A1N(n2844), .Y(n1404) );
OAI2BB2XLTS U3544 ( .B0(n2911), .B1(n2841), .A0N(final_result_ieee[11]),
.A1N(n1581), .Y(n1403) );
OAI2BB2XLTS U3545 ( .B0(n2913), .B1(n2841), .A0N(final_result_ieee[12]),
.A1N(n2844), .Y(n1402) );
OAI2BB2XLTS U3546 ( .B0(n2914), .B1(n2841), .A0N(final_result_ieee[13]),
.A1N(n2844), .Y(n1401) );
OAI2BB2XLTS U3547 ( .B0(n2915), .B1(n2841), .A0N(final_result_ieee[14]),
.A1N(n2844), .Y(n1400) );
OAI2BB2XLTS U3548 ( .B0(n2917), .B1(n2841), .A0N(final_result_ieee[15]),
.A1N(n1581), .Y(n1399) );
BUFX4TS U3549 ( .A(n2837), .Y(n2842) );
OAI2BB2XLTS U3550 ( .B0(n2918), .B1(n2842), .A0N(final_result_ieee[16]),
.A1N(n2844), .Y(n1398) );
OAI2BB2XLTS U3551 ( .B0(n2919), .B1(n2842), .A0N(final_result_ieee[17]),
.A1N(n2844), .Y(n1397) );
OAI2BB2XLTS U3552 ( .B0(n2920), .B1(n2842), .A0N(final_result_ieee[18]),
.A1N(n2844), .Y(n1396) );
OAI2BB2XLTS U3553 ( .B0(n2922), .B1(n2842), .A0N(final_result_ieee[19]),
.A1N(n2844), .Y(n1395) );
OAI2BB2XLTS U3554 ( .B0(n2923), .B1(n2842), .A0N(final_result_ieee[20]),
.A1N(n1581), .Y(n1394) );
OAI2BB2XLTS U3555 ( .B0(n2870), .B1(n2842), .A0N(final_result_ieee[21]),
.A1N(n2844), .Y(n1393) );
OAI2BB2XLTS U3556 ( .B0(n2871), .B1(n2842), .A0N(final_result_ieee[22]),
.A1N(n2844), .Y(n1392) );
OAI2BB2XLTS U3557 ( .B0(n2925), .B1(n2842), .A0N(final_result_ieee[23]),
.A1N(n2844), .Y(n1391) );
OAI2BB2XLTS U3558 ( .B0(n2872), .B1(n2842), .A0N(final_result_ieee[24]),
.A1N(n2844), .Y(n1390) );
OAI2BB2XLTS U3559 ( .B0(n2927), .B1(n2842), .A0N(final_result_ieee[25]),
.A1N(n2844), .Y(n1389) );
OAI2BB2XLTS U3560 ( .B0(n2928), .B1(n2842), .A0N(final_result_ieee[26]),
.A1N(n2838), .Y(n1388) );
OAI2BB2XLTS U3561 ( .B0(n2931), .B1(n2842), .A0N(final_result_ieee[27]),
.A1N(n2838), .Y(n1387) );
OAI2BB2XLTS U3562 ( .B0(n2932), .B1(n2840), .A0N(final_result_ieee[28]),
.A1N(n2838), .Y(n1386) );
OAI2BB2XLTS U3563 ( .B0(n2874), .B1(n2841), .A0N(final_result_ieee[29]),
.A1N(n2838), .Y(n1385) );
OAI2BB2XLTS U3564 ( .B0(n2934), .B1(n2842), .A0N(final_result_ieee[30]),
.A1N(n2838), .Y(n1384) );
OAI2BB2XLTS U3565 ( .B0(n2935), .B1(n2840), .A0N(final_result_ieee[31]),
.A1N(n2838), .Y(n1383) );
OAI2BB2XLTS U3566 ( .B0(n2936), .B1(n2841), .A0N(final_result_ieee[32]),
.A1N(n2838), .Y(n1382) );
OAI2BB2XLTS U3567 ( .B0(n2937), .B1(n2842), .A0N(final_result_ieee[33]),
.A1N(n2838), .Y(n1381) );
OAI2BB2XLTS U3568 ( .B0(n2938), .B1(n2841), .A0N(final_result_ieee[34]),
.A1N(n2844), .Y(n1380) );
OAI2BB2XLTS U3569 ( .B0(n2942), .B1(n2842), .A0N(final_result_ieee[35]),
.A1N(n1581), .Y(n1379) );
OAI2BB2XLTS U3570 ( .B0(n2943), .B1(n2841), .A0N(final_result_ieee[36]),
.A1N(n1581), .Y(n1378) );
OAI2BB2XLTS U3571 ( .B0(n2946), .B1(n2842), .A0N(final_result_ieee[37]),
.A1N(n1581), .Y(n1377) );
OAI2BB2XLTS U3572 ( .B0(n2947), .B1(n2841), .A0N(final_result_ieee[38]),
.A1N(n1581), .Y(n1376) );
OAI2BB2XLTS U3573 ( .B0(n2954), .B1(n2840), .A0N(final_result_ieee[39]),
.A1N(n2844), .Y(n1375) );
OAI2BB2XLTS U3574 ( .B0(n2958), .B1(n2842), .A0N(final_result_ieee[40]),
.A1N(n2844), .Y(n1374) );
OAI2BB2XLTS U3575 ( .B0(n2982), .B1(n2839), .A0N(final_result_ieee[42]),
.A1N(n1581), .Y(n1372) );
OAI2BB2XLTS U3576 ( .B0(n2983), .B1(n2839), .A0N(final_result_ieee[43]),
.A1N(n1581), .Y(n1371) );
OAI2BB2XLTS U3577 ( .B0(n2994), .B1(n2839), .A0N(final_result_ieee[44]),
.A1N(n2844), .Y(n1370) );
OAI2BB2XLTS U3578 ( .B0(n3005), .B1(n2840), .A0N(final_result_ieee[46]),
.A1N(n1581), .Y(n1368) );
OAI2BB2XLTS U3579 ( .B0(n3006), .B1(n2841), .A0N(final_result_ieee[47]),
.A1N(n2844), .Y(n1367) );
OAI2BB2XLTS U3580 ( .B0(n3018), .B1(n2842), .A0N(final_result_ieee[48]),
.A1N(n1581), .Y(n1366) );
OAI2BB2XLTS U3581 ( .B0(n3023), .B1(n2840), .A0N(final_result_ieee[49]),
.A1N(n2844), .Y(n1365) );
OAI2BB2XLTS U3582 ( .B0(n3024), .B1(n2841), .A0N(final_result_ieee[50]),
.A1N(n1581), .Y(n1364) );
OAI2BB2XLTS U3583 ( .B0(n3034), .B1(n2842), .A0N(final_result_ieee[51]),
.A1N(n1581), .Y(n1363) );
AOI21X1TS U3584 ( .A0(n2866), .A1(n2843), .B0(overflow_flag), .Y(n2845) );
AO22XLTS U3585 ( .A0(n2846), .A1(n2845), .B0(n1581), .B1(
final_result_ieee[63]), .Y(n1361) );
BUFX3TS U3586 ( .A(n2859), .Y(n2848) );
AO22XLTS U3587 ( .A0(n2847), .A1(intDX[62]), .B0(n2848), .B1(Data_X[62]),
.Y(n1359) );
AO22XLTS U3588 ( .A0(n2847), .A1(intDX[61]), .B0(n2848), .B1(Data_X[61]),
.Y(n1358) );
AO22XLTS U3589 ( .A0(n2847), .A1(intDX[60]), .B0(n2848), .B1(Data_X[60]),
.Y(n1357) );
AO22XLTS U3590 ( .A0(n2847), .A1(intDX[59]), .B0(n2848), .B1(Data_X[59]),
.Y(n1356) );
BUFX4TS U3591 ( .A(n2859), .Y(n2856) );
AO22XLTS U3592 ( .A0(n2847), .A1(intDX[58]), .B0(n2852), .B1(Data_X[58]),
.Y(n1355) );
AO22XLTS U3593 ( .A0(n2847), .A1(intDX[57]), .B0(n2852), .B1(Data_X[57]),
.Y(n1354) );
AO22XLTS U3594 ( .A0(n2847), .A1(intDX[56]), .B0(n2852), .B1(Data_X[56]),
.Y(n1353) );
AO22XLTS U3595 ( .A0(n2847), .A1(intDX[55]), .B0(n2852), .B1(Data_X[55]),
.Y(n1352) );
AO22XLTS U3596 ( .A0(n2847), .A1(intDX[54]), .B0(n2852), .B1(Data_X[54]),
.Y(n1351) );
AO22XLTS U3597 ( .A0(n2847), .A1(intDX[53]), .B0(n2852), .B1(Data_X[53]),
.Y(n1350) );
AO22XLTS U3598 ( .A0(n2847), .A1(intDX[52]), .B0(n2852), .B1(Data_X[52]),
.Y(n1349) );
AO22XLTS U3599 ( .A0(n2847), .A1(intDX[51]), .B0(n2852), .B1(Data_X[51]),
.Y(n1348) );
AO22XLTS U3600 ( .A0(n2847), .A1(intDX[50]), .B0(n2852), .B1(Data_X[50]),
.Y(n1347) );
AO22XLTS U3601 ( .A0(n2850), .A1(intDX[49]), .B0(n2852), .B1(Data_X[49]),
.Y(n1346) );
AO22XLTS U3602 ( .A0(n2851), .A1(intDX[48]), .B0(n2852), .B1(Data_X[48]),
.Y(n1345) );
AO22XLTS U3603 ( .A0(n2849), .A1(intDX[47]), .B0(n2848), .B1(Data_X[47]),
.Y(n1344) );
AO22XLTS U3604 ( .A0(n2850), .A1(intDX[46]), .B0(n2848), .B1(Data_X[46]),
.Y(n1343) );
BUFX4TS U3605 ( .A(n2859), .Y(n2857) );
AO22XLTS U3606 ( .A0(n2855), .A1(intDX[45]), .B0(n2857), .B1(Data_X[45]),
.Y(n1342) );
AO22XLTS U3607 ( .A0(n2855), .A1(intDX[44]), .B0(n2856), .B1(Data_X[44]),
.Y(n1341) );
AO22XLTS U3608 ( .A0(n2851), .A1(intDX[43]), .B0(n2852), .B1(Data_X[43]),
.Y(n1340) );
AO22XLTS U3609 ( .A0(n2849), .A1(intDX[42]), .B0(n2857), .B1(Data_X[42]),
.Y(n1339) );
AO22XLTS U3610 ( .A0(n2855), .A1(intDX[41]), .B0(n2857), .B1(Data_X[41]),
.Y(n1338) );
BUFX3TS U3611 ( .A(n2848), .Y(n2854) );
AO22XLTS U3612 ( .A0(n2850), .A1(intDX[40]), .B0(n2854), .B1(Data_X[40]),
.Y(n1337) );
BUFX3TS U3613 ( .A(n2859), .Y(n2853) );
AO22XLTS U3614 ( .A0(n2855), .A1(intDX[39]), .B0(n1656), .B1(Data_X[39]),
.Y(n1336) );
AO22XLTS U3615 ( .A0(n2851), .A1(intDX[38]), .B0(n2852), .B1(Data_X[38]),
.Y(n1335) );
AO22XLTS U3616 ( .A0(n2849), .A1(intDX[37]), .B0(n1656), .B1(Data_X[37]),
.Y(n1334) );
AO22XLTS U3617 ( .A0(n2850), .A1(intDX[36]), .B0(n2852), .B1(Data_X[36]),
.Y(n1333) );
AO22XLTS U3618 ( .A0(n2849), .A1(intDX[35]), .B0(n1656), .B1(Data_X[35]),
.Y(n1332) );
AO22XLTS U3619 ( .A0(n2855), .A1(intDX[34]), .B0(n2859), .B1(Data_X[34]),
.Y(n1331) );
AO22XLTS U3620 ( .A0(n2850), .A1(intDX[33]), .B0(n2848), .B1(Data_X[33]),
.Y(n1330) );
AO22XLTS U3621 ( .A0(n2849), .A1(intDX[32]), .B0(n2848), .B1(Data_X[32]),
.Y(n1329) );
AO22XLTS U3622 ( .A0(n2851), .A1(intDX[31]), .B0(n2848), .B1(Data_X[31]),
.Y(n1328) );
AO22XLTS U3623 ( .A0(n2849), .A1(intDX[30]), .B0(n2848), .B1(Data_X[30]),
.Y(n1327) );
AO22XLTS U3624 ( .A0(n2855), .A1(intDX[29]), .B0(n2857), .B1(Data_X[29]),
.Y(n1326) );
AO22XLTS U3625 ( .A0(n2850), .A1(intDX[28]), .B0(n2848), .B1(Data_X[28]),
.Y(n1325) );
AO22XLTS U3626 ( .A0(n2851), .A1(intDX[27]), .B0(n2848), .B1(Data_X[27]),
.Y(n1324) );
AO22XLTS U3627 ( .A0(n2849), .A1(intDX[26]), .B0(n2856), .B1(Data_X[26]),
.Y(n1323) );
AO22XLTS U3628 ( .A0(n2855), .A1(intDX[25]), .B0(n2856), .B1(Data_X[25]),
.Y(n1322) );
AO22XLTS U3629 ( .A0(n2855), .A1(intDX[24]), .B0(n2854), .B1(Data_X[24]),
.Y(n1321) );
AO22XLTS U3630 ( .A0(n2850), .A1(intDX[23]), .B0(n2856), .B1(Data_X[23]),
.Y(n1320) );
AO22XLTS U3631 ( .A0(n2851), .A1(intDX[22]), .B0(n2857), .B1(Data_X[22]),
.Y(n1319) );
AO22XLTS U3632 ( .A0(n2849), .A1(intDX[21]), .B0(n1656), .B1(Data_X[21]),
.Y(n1318) );
AO22XLTS U3633 ( .A0(n2855), .A1(intDX[20]), .B0(n2857), .B1(Data_X[20]),
.Y(n1317) );
AO22XLTS U3634 ( .A0(n2850), .A1(intDX[19]), .B0(n1656), .B1(Data_X[19]),
.Y(n1316) );
AO22XLTS U3635 ( .A0(n2851), .A1(intDX[18]), .B0(n1656), .B1(Data_X[18]),
.Y(n1315) );
AO22XLTS U3636 ( .A0(n2849), .A1(intDX[17]), .B0(n1656), .B1(Data_X[17]),
.Y(n1314) );
AO22XLTS U3637 ( .A0(n2850), .A1(intDX[16]), .B0(n1656), .B1(Data_X[16]),
.Y(n1313) );
AO22XLTS U3638 ( .A0(n2855), .A1(intDX[15]), .B0(n2854), .B1(Data_X[15]),
.Y(n1312) );
AO22XLTS U3639 ( .A0(n2850), .A1(intDX[14]), .B0(n2854), .B1(Data_X[14]),
.Y(n1311) );
AO22XLTS U3640 ( .A0(n2851), .A1(intDX[13]), .B0(n2854), .B1(Data_X[13]),
.Y(n1310) );
AO22XLTS U3641 ( .A0(n2849), .A1(intDX[12]), .B0(n2854), .B1(Data_X[12]),
.Y(n1309) );
AO22XLTS U3642 ( .A0(n2855), .A1(intDX[11]), .B0(n2854), .B1(Data_X[11]),
.Y(n1308) );
AO22XLTS U3643 ( .A0(n2851), .A1(intDX[10]), .B0(n2854), .B1(Data_X[10]),
.Y(n1307) );
AO22XLTS U3644 ( .A0(n2849), .A1(intDX[9]), .B0(n2854), .B1(Data_X[9]), .Y(
n1306) );
AO22XLTS U3645 ( .A0(n2850), .A1(intDX[8]), .B0(n2854), .B1(Data_X[8]), .Y(
n1305) );
AO22XLTS U3646 ( .A0(n2849), .A1(intDX[7]), .B0(n2856), .B1(Data_X[7]), .Y(
n1304) );
AO22XLTS U3647 ( .A0(n2860), .A1(intDX[6]), .B0(n2852), .B1(Data_X[6]), .Y(
n1303) );
AO22XLTS U3648 ( .A0(n2851), .A1(intDX[5]), .B0(n1656), .B1(Data_X[5]), .Y(
n1302) );
AO22XLTS U3649 ( .A0(n2860), .A1(intDX[4]), .B0(n1656), .B1(Data_X[4]), .Y(
n1301) );
AO22XLTS U3650 ( .A0(n2851), .A1(intDX[3]), .B0(n1656), .B1(Data_X[3]), .Y(
n1300) );
AO22XLTS U3651 ( .A0(n2850), .A1(intDX[2]), .B0(n1656), .B1(Data_X[2]), .Y(
n1299) );
AO22XLTS U3652 ( .A0(n2860), .A1(intDX[1]), .B0(n1656), .B1(Data_X[1]), .Y(
n1298) );
AO22XLTS U3653 ( .A0(n2855), .A1(intDX[0]), .B0(n1656), .B1(Data_X[0]), .Y(
n1297) );
AO22XLTS U3654 ( .A0(n2860), .A1(intDY[62]), .B0(n1656), .B1(Data_Y[62]),
.Y(n1294) );
AO22XLTS U3655 ( .A0(n2854), .A1(Data_Y[61]), .B0(n2851), .B1(intDY[61]),
.Y(n1293) );
AO22XLTS U3656 ( .A0(n2853), .A1(Data_Y[52]), .B0(n2850), .B1(intDY[52]),
.Y(n1284) );
AO22XLTS U3657 ( .A0(n2853), .A1(Data_Y[48]), .B0(n2855), .B1(intDY[48]),
.Y(n1280) );
AO22XLTS U3658 ( .A0(n2852), .A1(Data_Y[44]), .B0(n2851), .B1(intDY[44]),
.Y(n1276) );
AO22XLTS U3659 ( .A0(n1656), .A1(Data_Y[39]), .B0(n2849), .B1(intDY[39]),
.Y(n1271) );
AO22XLTS U3660 ( .A0(n1656), .A1(Data_Y[38]), .B0(n2849), .B1(intDY[38]),
.Y(n1270) );
AO22XLTS U3661 ( .A0(n2856), .A1(Data_Y[37]), .B0(n2855), .B1(intDY[37]),
.Y(n1269) );
AO22XLTS U3662 ( .A0(n2857), .A1(Data_Y[30]), .B0(n2851), .B1(intDY[30]),
.Y(n1262) );
AO22XLTS U3663 ( .A0(n2857), .A1(Data_Y[29]), .B0(n2860), .B1(intDY[29]),
.Y(n1261) );
AO22XLTS U3664 ( .A0(n2857), .A1(Data_Y[28]), .B0(n1655), .B1(intDY[28]),
.Y(n1260) );
AO22XLTS U3665 ( .A0(n2857), .A1(Data_Y[27]), .B0(n1655), .B1(intDY[27]),
.Y(n1259) );
AO22XLTS U3666 ( .A0(n2858), .A1(Data_Y[26]), .B0(n2847), .B1(intDY[26]),
.Y(n1258) );
AO22XLTS U3667 ( .A0(n2858), .A1(Data_Y[25]), .B0(n2847), .B1(intDY[25]),
.Y(n1257) );
AO22XLTS U3668 ( .A0(n2858), .A1(Data_Y[24]), .B0(n2847), .B1(intDY[24]),
.Y(n1256) );
AO22XLTS U3669 ( .A0(n2856), .A1(Data_Y[23]), .B0(n1655), .B1(intDY[23]),
.Y(n1255) );
AO22XLTS U3670 ( .A0(n2856), .A1(Data_Y[22]), .B0(n2850), .B1(intDY[22]),
.Y(n1254) );
AO22XLTS U3671 ( .A0(n2856), .A1(Data_Y[21]), .B0(n2860), .B1(intDY[21]),
.Y(n1253) );
AO22XLTS U3672 ( .A0(n2856), .A1(Data_Y[20]), .B0(n2847), .B1(intDY[20]),
.Y(n1252) );
AO22XLTS U3673 ( .A0(n2856), .A1(Data_Y[19]), .B0(n2850), .B1(intDY[19]),
.Y(n1251) );
AO22XLTS U3674 ( .A0(n2856), .A1(Data_Y[18]), .B0(n2860), .B1(intDY[18]),
.Y(n1250) );
AO22XLTS U3675 ( .A0(n2856), .A1(Data_Y[17]), .B0(n2851), .B1(intDY[17]),
.Y(n1249) );
AO22XLTS U3676 ( .A0(n2856), .A1(Data_Y[16]), .B0(n2860), .B1(intDY[16]),
.Y(n1248) );
AO22XLTS U3677 ( .A0(n2856), .A1(Data_Y[15]), .B0(n2849), .B1(intDY[15]),
.Y(n1247) );
AO22XLTS U3678 ( .A0(n2856), .A1(Data_Y[14]), .B0(n2860), .B1(intDY[14]),
.Y(n1246) );
AO22XLTS U3679 ( .A0(n2857), .A1(Data_Y[13]), .B0(n2850), .B1(intDY[13]),
.Y(n1245) );
AO22XLTS U3680 ( .A0(n2857), .A1(Data_Y[12]), .B0(n2860), .B1(intDY[12]),
.Y(n1244) );
AO22XLTS U3681 ( .A0(n2858), .A1(Data_Y[11]), .B0(n2855), .B1(intDY[11]),
.Y(n1243) );
AO22XLTS U3682 ( .A0(n2858), .A1(Data_Y[10]), .B0(n2860), .B1(intDY[10]),
.Y(n1242) );
AO22XLTS U3683 ( .A0(n2858), .A1(Data_Y[9]), .B0(n2849), .B1(intDY[9]), .Y(
n1241) );
AO22XLTS U3684 ( .A0(n2858), .A1(Data_Y[8]), .B0(n2860), .B1(intDY[8]), .Y(
n1240) );
AO22XLTS U3685 ( .A0(n2858), .A1(Data_Y[7]), .B0(n2849), .B1(intDY[7]), .Y(
n1239) );
AO22XLTS U3686 ( .A0(n2858), .A1(Data_Y[6]), .B0(n2860), .B1(intDY[6]), .Y(
n1238) );
AO22XLTS U3687 ( .A0(n2858), .A1(Data_Y[5]), .B0(n2850), .B1(intDY[5]), .Y(
n1237) );
AO22XLTS U3688 ( .A0(n2858), .A1(Data_Y[4]), .B0(n2860), .B1(intDY[4]), .Y(
n1236) );
AO22XLTS U3689 ( .A0(n2859), .A1(Data_Y[3]), .B0(n1655), .B1(intDY[3]), .Y(
n1235) );
AO22XLTS U3690 ( .A0(n2854), .A1(Data_Y[2]), .B0(n2855), .B1(intDY[2]), .Y(
n1234) );
AO22XLTS U3691 ( .A0(n2859), .A1(Data_Y[1]), .B0(n2849), .B1(intDY[1]), .Y(
n1233) );
NOR2XLTS U3692 ( .A(n2864), .B(n2861), .Y(n2862) );
OAI22X1TS U3693 ( .A0(n2864), .A1(n2863), .B0(n2862), .B1(intDX[63]), .Y(
n2867) );
AOI22X1TS U3694 ( .A0(n2868), .A1(n2867), .B0(n2866), .B1(n2238), .Y(n1167)
);
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_syn.sdf");
endmodule
|
// Check that operators in an assignment pattern are evaluated correctly. The
// result should be the same as assigning the expression to a variable with the
// same type as the base type of the assignment pattern target.
module test;
int d[];
int tmp;
bit failed = 1'b0;
`define check(expr) \
d = '{expr}; \
tmp = expr; \
if (d[0] !== tmp) begin \
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", d[0], tmp); \
failed = 1'b1; \
end
int x, y;
initial begin
x = -2;
y = 5;
`check(+x);
`check(-x);
`check(!x);
`check(~x);
`check(&x);
`check(~&x);
`check(|x);
`check(~|x);
`check(^x);
`check(~^x);
`check(x + y)
`check(x - y)
`check(x * y)
`check(x / y)
`check(x % y)
`check(x ** y)
`check(x & y)
`check(x | y)
`check(x ^ y)
`check(x ^~ y)
`check(x >> y);
`check(x << y);
`check(x >>> y);
`check(x <<< y);
`check(x == y);
`check(x != y);
`check(x === y);
`check(x !== y);
`check(x < y);
`check(x <= y);
`check(x > y);
`check(x >= y);
`check(x && y);
`check(x || y);
`check(x ? x : y);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A311O_BEHAVIORAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2010/12/02 09:36:30 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module clk_ibuf #
(
parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputisolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: nf2_reg_grp.v
// Project: NetFPGA
// Description: the top module for register decoding, muxing and
// demuxing for the cpu access buses to various targets
// within the nf2_core module
//
// Note: This module doesn't care how long the ack is held by
// the responding module (although it should be cleared by the
// time the next request arrives).
//
// Register access timeouts are handled by this module. There is
// NO need to handle timeouts in submodules. Submodules should
// only route or respond to requests.
//
///////////////////////////////////////////////////////////////////////////////
module nf2_reg_grp (
input fifo_empty,// functions like a bus_req signal
output reg fifo_rd_en,
input bus_rd_wr_L,
input [`CPCI_NF2_ADDR_WIDTH-1:0] bus_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] bus_wr_data,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] bus_rd_data,
output reg bus_rd_vld,
output wire out_ack,
// interface to core registers
output reg core_reg_req,
output reg core_reg_rd_wr_L,
output reg [`CORE_REG_ADDR_WIDTH-1:0] core_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] core_reg_wr_data,
input core_reg_ack,
input [`CPCI_NF2_DATA_WIDTH-1:0] core_reg_rd_data,
// interface to SRAM
output reg sram_reg_req,
output reg sram_reg_rd_wr_L,
output reg [`SRAM_REG_ADDR_WIDTH-1:0] sram_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] sram_reg_wr_data,
input sram_reg_ack,
input [`CPCI_NF2_DATA_WIDTH-1:0] sram_reg_rd_data,
// interface to user data path
output reg udp_reg_req,
output reg udp_reg_rd_wr_L,
output reg [`UDP_REG_ADDR_WIDTH-1:0] udp_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] udp_reg_wr_data,
input udp_reg_ack,
input [`CPCI_NF2_DATA_WIDTH-1:0] udp_reg_rd_data,
// Interface to DRAM random-access module
output reg dram_reg_req,
output reg dram_reg_rd_wr_L,
output reg [`DRAM_REG_ADDR_WIDTH - 1:0] dram_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] dram_reg_wr_data,
input dram_reg_ack,
input [`CPCI_NF2_DATA_WIDTH-1:0] dram_reg_rd_data,
input clk,
input reset);
//--------------------- Internal parameters -----------------------------------------------------------
// FIXME: Replace these with parameters from the global defines
localparam CORE_TAG_ADDR = { {(`CPCI_NF2_ADDR_WIDTH - 2 - `CORE_BLOCK_ADDR_WIDTH - `CORE_REG_ADDR_WIDTH){1'b0}},
`CORE_BLOCK_ADDR,
{(`CORE_REG_ADDR_WIDTH) {1'b?}}};
localparam SRAM_TAG_ADDR = { {(`CPCI_NF2_ADDR_WIDTH - 2 - `SRAM_BLOCK_ADDR_WIDTH - `SRAM_REG_ADDR_WIDTH){1'b0}},
`SRAM_BLOCK_ADDR,
{(`SRAM_REG_ADDR_WIDTH) {1'b?}}};
localparam UDP_TAG_ADDR = { {(`CPCI_NF2_ADDR_WIDTH - 2 - `UDP_BLOCK_ADDR_WIDTH - `UDP_REG_ADDR_WIDTH){1'b0}},
`UDP_BLOCK_ADDR,
{(`UDP_REG_ADDR_WIDTH) {1'b?}}};
localparam DRAM_TAG_ADDR = { {(`CPCI_NF2_ADDR_WIDTH - 2 - `DRAM_BLOCK_ADDR_WIDTH - `DRAM_REG_ADDR_WIDTH){1'b0}},
`DRAM_BLOCK_ADDR,
{(`DRAM_REG_ADDR_WIDTH) {1'b?}}};
localparam
IDLE_STATE = 2'h0,
GET_REQ_STATE = 2'h1,
WAIT_ACK_STATE = 2'h2;
localparam
TIMEOUT_COUNT_DOWN = 9'd511;
//--------------------- Wires/regs ---------------------
reg cpu_req, cpu_req_nxt;
reg cpu_rd_wr_L, cpu_rd_wr_L_nxt;
reg [`CPCI_NF2_ADDR_WIDTH -3: 0] cpu_addr, cpu_addr_nxt;
reg [`CPCI_NF2_DATA_WIDTH -1: 0] cpu_wr_data, cpu_wr_data_nxt;
reg cpu_ack;
reg [`CPCI_NF2_DATA_WIDTH -1: 0] cpu_rd_data;
reg [8:0] cpu_timeout_cnt_dn, cpu_timeout_cnt_dn_nxt;
reg [1:0] state, state_nxt;
//-------------------- Logic ----------------------------
always @(*) begin
fifo_rd_en = 1'b 0;
bus_rd_data = {`CPCI_NF2_DATA_WIDTH {1'b 0}};
bus_rd_vld = 1'b 0;
cpu_req_nxt = cpu_req;
cpu_rd_wr_L_nxt = cpu_rd_wr_L;
cpu_addr_nxt = cpu_addr;
cpu_wr_data_nxt = cpu_wr_data;
cpu_timeout_cnt_dn_nxt = cpu_timeout_cnt_dn;
state_nxt = state;
case (state)
IDLE_STATE: begin
if (! fifo_empty) begin
fifo_rd_en = 1'b1;
state_nxt = GET_REQ_STATE;
end // if (! fifo_empty)
end // IDLE_STATE
GET_REQ_STATE: begin
cpu_req_nxt = 1'b 1;
cpu_addr_nxt = bus_addr[`CPCI_NF2_ADDR_WIDTH-1:2];
// Drop the two LSBs as we
// want word aligned accesses
cpu_timeout_cnt_dn_nxt = TIMEOUT_COUNT_DOWN;
state_nxt = WAIT_ACK_STATE;
if (bus_rd_wr_L) begin // read
cpu_wr_data_nxt = {`CPCI_NF2_DATA_WIDTH {1'b 0}};
cpu_rd_wr_L_nxt = 1'b 1;
end // (if bus_rd_wr_L)
else begin // write
cpu_rd_wr_L_nxt = 1'b 0;
cpu_wr_data_nxt = bus_wr_data;
end // else
end // GET_REQ_STATE
WAIT_ACK_STATE: begin
cpu_timeout_cnt_dn_nxt = cpu_timeout_cnt_dn - 1;
if (cpu_ack || !(|cpu_timeout_cnt_dn)) begin
// synthesis translate_off
if(cpu_timeout_cnt_dn==0) begin
$display("%t %m ERROR: Timeout while waiting for ack for register access.", $time);
end
// synthesis translate_on
cpu_rd_wr_L_nxt = 1'b 1;
if (cpu_rd_wr_L) begin
bus_rd_data = (cpu_ack === 1'b1) ? cpu_rd_data : 'h deadbeef;
bus_rd_vld = 1'b 1;
end // if (cpu_rd_wr_L)
cpu_req_nxt = 1'b 0;
if (! fifo_empty) begin
fifo_rd_en = 1'b 1;
state_nxt = GET_REQ_STATE;
end
else
state_nxt = IDLE_STATE;
end // if (cpu_ack)
end // WAIT_ACK_STATE
endcase // case(state)
end // always @ (*)
always @(posedge clk) begin
if (reset) begin
state <= IDLE_STATE;
cpu_req <= 1'b 0;
cpu_rd_wr_L <= 1'b 0;
cpu_addr <= {(`CPCI_NF2_ADDR_WIDTH-2) {1'b 0}};
cpu_wr_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
cpu_timeout_cnt_dn <= 7'h 0;
end // if (reset)
else begin
state <= state_nxt;
cpu_req <= cpu_req_nxt;
cpu_rd_wr_L <= cpu_rd_wr_L_nxt;
cpu_addr <= cpu_addr_nxt;
cpu_wr_data <= cpu_wr_data_nxt;
cpu_timeout_cnt_dn <= cpu_timeout_cnt_dn_nxt;
end // else
end // always @ (posedge clk)
always @(posedge clk) begin
if(reset) begin
cpu_ack <= 1'b 0;
cpu_rd_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
core_reg_req <= 1'b 0;
core_reg_rd_wr_L <= 1'b 1;
core_reg_addr <= {`CORE_REG_ADDR_WIDTH {1'b 0}};
core_reg_wr_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
udp_reg_req <= 1'b 0;
udp_reg_rd_wr_L <= 1'b 1;
udp_reg_addr <= {`UDP_REG_ADDR_WIDTH {1'b 0}};
udp_reg_wr_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
sram_reg_req <= 1'b 0;
sram_reg_rd_wr_L <= 1'b 1;
sram_reg_addr <= {`SRAM_REG_ADDR_WIDTH {1'b 0}};
sram_reg_wr_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
dram_reg_req <= 1'b 0;
dram_reg_rd_wr_L <= 1'b 1;
dram_reg_addr <= {`DRAM_REG_ADDR_WIDTH {1'b 0}};
dram_reg_wr_data <= {`CPCI_NF2_DATA_WIDTH {1'b 0}};
end // if (reset)
else begin
casez (cpu_addr)
CORE_TAG_ADDR: begin
cpu_ack <= core_reg_ack;
cpu_rd_data <= core_reg_rd_data;
core_reg_req <= cpu_req;
core_reg_rd_wr_L <= cpu_rd_wr_L;
core_reg_addr <= cpu_addr[`CORE_REG_ADDR_WIDTH-1:0];
core_reg_wr_data <= cpu_wr_data;
end
UDP_TAG_ADDR: begin
cpu_ack <= udp_reg_ack;
cpu_rd_data <= udp_reg_rd_data;
udp_reg_req <= cpu_req;
udp_reg_rd_wr_L <= cpu_rd_wr_L;
udp_reg_addr <= cpu_addr[`UDP_REG_ADDR_WIDTH-1:0];
udp_reg_wr_data <= cpu_wr_data;
end
SRAM_TAG_ADDR: begin
cpu_ack <= sram_reg_ack;
cpu_rd_data <= sram_reg_rd_data;
sram_reg_req <= cpu_req;
sram_reg_rd_wr_L <= cpu_rd_wr_L;
sram_reg_addr <= cpu_addr[`SRAM_REG_ADDR_WIDTH-1:0];
sram_reg_wr_data <= cpu_wr_data;
end
DRAM_TAG_ADDR: begin
cpu_ack <= dram_reg_ack;
cpu_rd_data <= dram_reg_rd_data;
dram_reg_req <= cpu_req;
dram_reg_rd_wr_L <= cpu_rd_wr_L;
dram_reg_addr <= cpu_addr[`DRAM_REG_ADDR_WIDTH-1:0];
dram_reg_wr_data <= cpu_wr_data;
end
default: begin
cpu_ack <= cpu_req;
cpu_rd_data <= 32'h DEAD_BEEF;
end // case: default
endcase // casez (cpu_addr[CPCI_NF2_ADDR_WIDTH-1:NF2_REG_ADDR_BITS])
end // else: !if(reset)
end // always @ (posedge clk)
assign out_ack = cpu_ack;
endmodule // nf2_reg_grp
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* CPU instructions bus to OCP bus converter (version 2)
*/
`include "common.vh"
`include "ocp_const.vh"
/* CPU IBus-to-OCP */
module ibus2ocp2(
clk,
nrst,
/* CPU port */
i_IAddr,
i_IRdC,
o_IData,
o_IRdy,
o_IErr,
/* OCP port */
o_MAddr,
o_MCmd,
o_MData,
o_MByteEn,
i_SCmdAccept,
i_SData,
i_SResp
);
input wire clk;
input wire nrst;
/* CPU port */
input wire [`ADDR_WIDTH-1:0] i_IAddr;
input wire i_IRdC;
output reg [`DATA_WIDTH-1:0] o_IData;
output reg o_IRdy;
output reg o_IErr;
/* OCP port */
output reg [`ADDR_WIDTH-1:0] o_MAddr;
output reg [2:0] o_MCmd;
output reg [`DATA_WIDTH-1:0] o_MData; /* Not used */
output reg [`BEN_WIDTH-1:0] o_MByteEn;
input wire i_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_SData;
input wire [1:0] i_SResp;
/** Internal wires and registers **/
reg [`ADDR_WIDTH-1:0] maddr_r;
reg [2:0] mcmd_r;
reg naccept_r;
wire [2:0] ocp_cmd = (i_IRdC ? `OCP_CMD_READ : `OCP_CMD_IDLE);
/* FSM */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
maddr_r <= { (`ADDR_WIDTH){1'b0} };
mcmd_r <= `OCP_CMD_IDLE;
naccept_r <= 1'b0;
end
else if(i_IRdC && !i_SCmdAccept)
begin
maddr_r <= i_IAddr;
mcmd_r <= ocp_cmd;
naccept_r <= 1'b1;
end
else if(i_SCmdAccept)
begin
naccept_r <= 1'b0;
end
end
/* Output logic */
always @(*)
begin
o_MAddr = (!naccept_r ? i_IAddr : maddr_r);
o_MCmd = (!naccept_r ? ocp_cmd : mcmd_r);
o_MData = {(`DATA_WIDTH){1'b0}};
o_MByteEn = {(`BEN_WIDTH){1'b1}};
o_IData = i_SData;
o_IRdy = (i_SResp != `OCP_RESP_NULL ? 1'b1 : 1'b0);
o_IErr = (i_SResp == `OCP_RESP_ERR || i_SResp == `OCP_RESP_FAIL ? 1'b1 : 1'b0);
end
endmodule /* ibus2ocp2 */
|
// Copyright 2021 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module isqrt(num, out);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
(* src = "/tmp/sqrt.cc.v:2.21-2.24" *)
input [15:0] num;
(* src = "/tmp/sqrt.cc.v:3.21-3.24" *)
output [7:0] out;
inv _197_ (
.A(num[15]),
.Y(_126_)
);
inv _198_ (
.A(num[12]),
.Y(_127_)
);
inv _199_ (
.A(num[8]),
.Y(_128_)
);
inv _200_ (
.A(num[9]),
.Y(_129_)
);
inv _201_ (
.A(num[10]),
.Y(_130_)
);
inv _202_ (
.A(num[4]),
.Y(_131_)
);
inv _203_ (
.A(num[5]),
.Y(_132_)
);
inv _204_ (
.A(num[6]),
.Y(_133_)
);
inv _205_ (
.A(num[7]),
.Y(_134_)
);
inv _206_ (
.A(num[3]),
.Y(_135_)
);
inv _207_ (
.A(num[2]),
.Y(_136_)
);
orny2 _208_ (
.A(num[14]),
.B(num[15]),
.Y(_137_)
);
inv _209_ (
.A(_137_),
.Y(out[7])
);
nor2 _210_ (
.A(num[15]),
.B(num[14]),
.Y(_138_)
);
or2 _211_ (
.A(num[12]),
.B(num[13]),
.Y(_139_)
);
nand2 _212_ (
.A(_138_),
.B(_139_),
.Y(_140_)
);
inv _213_ (
.A(_140_),
.Y(out[6])
);
nand2 _214_ (
.A(_127_),
.B(_138_),
.Y(_141_)
);
and2 _215_ (
.A(num[13]),
.B(_141_),
.Y(_142_)
);
nand2 _216_ (
.A(_137_),
.B(_142_),
.Y(_143_)
);
or2 _217_ (
.A(num[10]),
.B(num[11]),
.Y(_144_)
);
or2 _218_ (
.A(num[13]),
.B(_137_),
.Y(_145_)
);
and2 _219_ (
.A(_144_),
.B(_145_),
.Y(_146_)
);
nand2 _220_ (
.A(_143_),
.B(_146_),
.Y(_147_)
);
nand2 _221_ (
.A(_127_),
.B(_147_),
.Y(_148_)
);
and2 _222_ (
.A(_126_),
.B(_148_),
.Y(_149_)
);
orny2 _223_ (
.A(num[12]),
.B(num[13]),
.Y(_150_)
);
nand2 _224_ (
.A(_149_),
.B(_150_),
.Y(_151_)
);
inv _225_ (
.A(_151_),
.Y(out[5])
);
andny2 _226_ (
.A(_151_),
.B(_130_),
.Y(_152_)
);
imux2 _227_ (
.A(_140_),
.B(_144_),
.S(_151_),
.Y(_153_)
);
xnor2 _228_ (
.A(num[12]),
.B(_153_),
.Y(_154_)
);
nand2 _229_ (
.A(_137_),
.B(_154_),
.Y(_155_)
);
xnor2 _230_ (
.A(out[7]),
.B(_154_),
.Y(_156_)
);
xnor2 _231_ (
.A(num[11]),
.B(_152_),
.Y(_157_)
);
inv _232_ (
.A(_157_),
.Y(_158_)
);
or2 _233_ (
.A(out[6]),
.B(_157_),
.Y(_159_)
);
xnor2 _234_ (
.A(_140_),
.B(_157_),
.Y(_160_)
);
nor2 _235_ (
.A(num[8]),
.B(num[9]),
.Y(_161_)
);
imux2 _236_ (
.A(out[5]),
.B(_161_),
.S(num[10]),
.Y(_162_)
);
inv _237_ (
.A(_162_),
.Y(_163_)
);
nand2 _238_ (
.A(_160_),
.B(_163_),
.Y(_164_)
);
nand2 _239_ (
.A(_159_),
.B(_164_),
.Y(_165_)
);
nand2 _240_ (
.A(_156_),
.B(_165_),
.Y(_166_)
);
orny2 _241_ (
.A(_142_),
.B(_149_),
.Y(_167_)
);
and2 _242_ (
.A(_155_),
.B(_167_),
.Y(_168_)
);
nand2 _243_ (
.A(_166_),
.B(_168_),
.Y(_169_)
);
nand2 _244_ (
.A(_126_),
.B(_169_),
.Y(_170_)
);
inv _245_ (
.A(_170_),
.Y(out[4])
);
xnor2 _246_ (
.A(_160_),
.B(_162_),
.Y(_171_)
);
imux2 _247_ (
.A(_158_),
.B(_171_),
.S(_170_),
.Y(_172_)
);
nand2 _248_ (
.A(_137_),
.B(_172_),
.Y(_173_)
);
xnor2 _249_ (
.A(out[7]),
.B(_172_),
.Y(_174_)
);
xnor2 _250_ (
.A(_130_),
.B(_151_),
.Y(_175_)
);
xnor2 _251_ (
.A(num[10]),
.B(_161_),
.Y(_176_)
);
imux2 _252_ (
.A(_175_),
.B(_176_),
.S(_170_),
.Y(_177_)
);
or2 _253_ (
.A(out[6]),
.B(_177_),
.Y(_178_)
);
xnor2 _254_ (
.A(out[6]),
.B(_177_),
.Y(_179_)
);
andny2 _255_ (
.A(_170_),
.B(_128_),
.Y(_180_)
);
xnor2 _256_ (
.A(_129_),
.B(_180_),
.Y(_181_)
);
nand2 _257_ (
.A(_151_),
.B(_181_),
.Y(_182_)
);
xnor2 _258_ (
.A(out[5]),
.B(_181_),
.Y(_183_)
);
nor2 _259_ (
.A(num[6]),
.B(num[7]),
.Y(_184_)
);
imux2 _260_ (
.A(out[4]),
.B(_184_),
.S(num[8]),
.Y(_185_)
);
inv _261_ (
.A(_185_),
.Y(_186_)
);
nand2 _262_ (
.A(_183_),
.B(_186_),
.Y(_187_)
);
and2 _263_ (
.A(_182_),
.B(_187_),
.Y(_188_)
);
or2 _264_ (
.A(_179_),
.B(_188_),
.Y(_189_)
);
nand2 _265_ (
.A(_178_),
.B(_189_),
.Y(_190_)
);
nand2 _266_ (
.A(_174_),
.B(_190_),
.Y(_191_)
);
xor2 _267_ (
.A(_156_),
.B(_165_),
.Y(_192_)
);
andny2 _268_ (
.A(_170_),
.B(_192_),
.Y(_193_)
);
orny2 _269_ (
.A(_154_),
.B(_169_),
.Y(_194_)
);
andny2 _270_ (
.A(_193_),
.B(_194_),
.Y(_195_)
);
and2 _271_ (
.A(_173_),
.B(_195_),
.Y(_196_)
);
nand2 _272_ (
.A(_191_),
.B(_196_),
.Y(_000_)
);
nand2 _273_ (
.A(_126_),
.B(_000_),
.Y(_001_)
);
inv _274_ (
.A(_001_),
.Y(out[3])
);
xnor2 _275_ (
.A(_179_),
.B(_188_),
.Y(_002_)
);
imux2 _276_ (
.A(_177_),
.B(_002_),
.S(_001_),
.Y(_003_)
);
or2 _277_ (
.A(out[7]),
.B(_003_),
.Y(_004_)
);
xnor2 _278_ (
.A(_137_),
.B(_003_),
.Y(_005_)
);
xnor2 _279_ (
.A(_183_),
.B(_185_),
.Y(_006_)
);
imux2 _280_ (
.A(_181_),
.B(_006_),
.S(_001_),
.Y(_007_)
);
inv _281_ (
.A(_007_),
.Y(_008_)
);
nand2 _282_ (
.A(_140_),
.B(_007_),
.Y(_009_)
);
xnor2 _283_ (
.A(_140_),
.B(_007_),
.Y(_010_)
);
xnor2 _284_ (
.A(_128_),
.B(_170_),
.Y(_011_)
);
xnor2 _285_ (
.A(num[8]),
.B(_184_),
.Y(_012_)
);
imux2 _286_ (
.A(_011_),
.B(_012_),
.S(_001_),
.Y(_013_)
);
or2 _287_ (
.A(out[5]),
.B(_013_),
.Y(_014_)
);
andny2 _288_ (
.A(_001_),
.B(_133_),
.Y(_015_)
);
xnor2 _289_ (
.A(_134_),
.B(_015_),
.Y(_016_)
);
inv _290_ (
.A(_016_),
.Y(_017_)
);
nand2 _291_ (
.A(_170_),
.B(_016_),
.Y(_018_)
);
xnor2 _292_ (
.A(out[4]),
.B(_016_),
.Y(_019_)
);
nor2 _293_ (
.A(num[4]),
.B(num[5]),
.Y(_020_)
);
imux2 _294_ (
.A(out[3]),
.B(_020_),
.S(num[6]),
.Y(_021_)
);
inv _295_ (
.A(_021_),
.Y(_022_)
);
nand2 _296_ (
.A(_019_),
.B(_022_),
.Y(_023_)
);
nand2 _297_ (
.A(_018_),
.B(_023_),
.Y(_024_)
);
xnor2 _298_ (
.A(_151_),
.B(_013_),
.Y(_025_)
);
nand2 _299_ (
.A(_024_),
.B(_025_),
.Y(_026_)
);
and2 _300_ (
.A(_014_),
.B(_026_),
.Y(_027_)
);
or2 _301_ (
.A(_010_),
.B(_027_),
.Y(_028_)
);
nand2 _302_ (
.A(_009_),
.B(_028_),
.Y(_029_)
);
nand2 _303_ (
.A(_005_),
.B(_029_),
.Y(_030_)
);
xor2 _304_ (
.A(_174_),
.B(_190_),
.Y(_031_)
);
imux2 _305_ (
.A(_172_),
.B(_031_),
.S(_001_),
.Y(_032_)
);
andyn2 _306_ (
.A(_004_),
.B(_032_),
.Y(_033_)
);
nand2 _307_ (
.A(_030_),
.B(_033_),
.Y(_034_)
);
nand2 _308_ (
.A(_126_),
.B(_034_),
.Y(_035_)
);
inv _309_ (
.A(_035_),
.Y(out[2])
);
xnor2 _310_ (
.A(_024_),
.B(_025_),
.Y(_036_)
);
imux2 _311_ (
.A(_013_),
.B(_036_),
.S(_035_),
.Y(_037_)
);
inv _312_ (
.A(_037_),
.Y(_038_)
);
or2 _313_ (
.A(out[6]),
.B(_037_),
.Y(_039_)
);
xnor2 _314_ (
.A(_140_),
.B(_037_),
.Y(_040_)
);
inv _315_ (
.A(_040_),
.Y(_041_)
);
xnor2 _316_ (
.A(_019_),
.B(_022_),
.Y(_042_)
);
imux2 _317_ (
.A(_017_),
.B(_042_),
.S(_035_),
.Y(_043_)
);
inv _318_ (
.A(_043_),
.Y(_044_)
);
or2 _319_ (
.A(out[5]),
.B(_043_),
.Y(_045_)
);
xnor2 _320_ (
.A(_151_),
.B(_043_),
.Y(_046_)
);
inv _321_ (
.A(_046_),
.Y(_047_)
);
xnor2 _322_ (
.A(_133_),
.B(_001_),
.Y(_048_)
);
xnor2 _323_ (
.A(num[6]),
.B(_020_),
.Y(_049_)
);
imux2 _324_ (
.A(_048_),
.B(_049_),
.S(_035_),
.Y(_050_)
);
inv _325_ (
.A(_050_),
.Y(_051_)
);
or2 _326_ (
.A(out[4]),
.B(_050_),
.Y(_052_)
);
xnor2 _327_ (
.A(_170_),
.B(_050_),
.Y(_053_)
);
inv _328_ (
.A(_053_),
.Y(_054_)
);
andny2 _329_ (
.A(_035_),
.B(_131_),
.Y(_055_)
);
xnor2 _330_ (
.A(_132_),
.B(_055_),
.Y(_056_)
);
nand2 _331_ (
.A(_001_),
.B(_056_),
.Y(_057_)
);
xnor2 _332_ (
.A(out[3]),
.B(_056_),
.Y(_058_)
);
nor2 _333_ (
.A(num[3]),
.B(num[2]),
.Y(_059_)
);
imux2 _334_ (
.A(out[2]),
.B(_059_),
.S(num[4]),
.Y(_060_)
);
inv _335_ (
.A(_060_),
.Y(_061_)
);
nand2 _336_ (
.A(_058_),
.B(_061_),
.Y(_062_)
);
and2 _337_ (
.A(_057_),
.B(_062_),
.Y(_063_)
);
or2 _338_ (
.A(_054_),
.B(_063_),
.Y(_064_)
);
and2 _339_ (
.A(_052_),
.B(_064_),
.Y(_065_)
);
or2 _340_ (
.A(_047_),
.B(_065_),
.Y(_066_)
);
and2 _341_ (
.A(_045_),
.B(_066_),
.Y(_067_)
);
or2 _342_ (
.A(_041_),
.B(_067_),
.Y(_068_)
);
nand2 _343_ (
.A(_039_),
.B(_068_),
.Y(_069_)
);
xnor2 _344_ (
.A(_010_),
.B(_027_),
.Y(_070_)
);
imux2 _345_ (
.A(_008_),
.B(_070_),
.S(_035_),
.Y(_071_)
);
or2 _346_ (
.A(out[7]),
.B(_071_),
.Y(_072_)
);
xnor2 _347_ (
.A(_137_),
.B(_071_),
.Y(_073_)
);
nand2 _348_ (
.A(_069_),
.B(_073_),
.Y(_074_)
);
xnor2 _349_ (
.A(_005_),
.B(_029_),
.Y(_075_)
);
imux2 _350_ (
.A(_003_),
.B(_075_),
.S(_035_),
.Y(_076_)
);
and2 _351_ (
.A(_072_),
.B(_076_),
.Y(_077_)
);
nand2 _352_ (
.A(_074_),
.B(_077_),
.Y(_078_)
);
nand2 _353_ (
.A(_126_),
.B(_078_),
.Y(_079_)
);
inv _354_ (
.A(_079_),
.Y(out[1])
);
xnor2 _355_ (
.A(_040_),
.B(_067_),
.Y(_080_)
);
imux2 _356_ (
.A(_038_),
.B(_080_),
.S(_079_),
.Y(_081_)
);
or2 _357_ (
.A(_137_),
.B(_081_),
.Y(_082_)
);
xnor2 _358_ (
.A(_046_),
.B(_065_),
.Y(_083_)
);
imux2 _359_ (
.A(_044_),
.B(_083_),
.S(_079_),
.Y(_084_)
);
nand2 _360_ (
.A(_140_),
.B(_084_),
.Y(_085_)
);
xnor2 _361_ (
.A(num[4]),
.B(_035_),
.Y(_086_)
);
xnor2 _362_ (
.A(_131_),
.B(_059_),
.Y(_087_)
);
imux2 _363_ (
.A(_086_),
.B(_087_),
.S(_079_),
.Y(_088_)
);
nand2 _364_ (
.A(_001_),
.B(_088_),
.Y(_089_)
);
nor2 _365_ (
.A(num[0]),
.B(num[1]),
.Y(_090_)
);
nand2 _366_ (
.A(_136_),
.B(_090_),
.Y(_091_)
);
nand2 _367_ (
.A(_035_),
.B(_091_),
.Y(_092_)
);
xnor2 _368_ (
.A(_135_),
.B(_079_),
.Y(_093_)
);
nand2 _369_ (
.A(_092_),
.B(_093_),
.Y(_094_)
);
or2 _370_ (
.A(_035_),
.B(_091_),
.Y(_095_)
);
andny2 _371_ (
.A(num[3]),
.B(num[2]),
.Y(_096_)
);
andny2 _372_ (
.A(_079_),
.B(_096_),
.Y(_097_)
);
andyn2 _373_ (
.A(_095_),
.B(_097_),
.Y(_098_)
);
nand2 _374_ (
.A(_094_),
.B(_098_),
.Y(_099_)
);
nand2 _375_ (
.A(_089_),
.B(_099_),
.Y(_100_)
);
xnor2 _376_ (
.A(_058_),
.B(_060_),
.Y(_101_)
);
imux2 _377_ (
.A(_056_),
.B(_101_),
.S(_079_),
.Y(_102_)
);
or2 _378_ (
.A(_170_),
.B(_102_),
.Y(_103_)
);
or2 _379_ (
.A(_001_),
.B(_088_),
.Y(_104_)
);
and2 _380_ (
.A(_103_),
.B(_104_),
.Y(_105_)
);
nand2 _381_ (
.A(_100_),
.B(_105_),
.Y(_106_)
);
xnor2 _382_ (
.A(_053_),
.B(_063_),
.Y(_107_)
);
imux2 _383_ (
.A(_051_),
.B(_107_),
.S(_079_),
.Y(_108_)
);
nand2 _384_ (
.A(_151_),
.B(_108_),
.Y(_109_)
);
nand2 _385_ (
.A(_170_),
.B(_102_),
.Y(_110_)
);
and2 _386_ (
.A(_109_),
.B(_110_),
.Y(_111_)
);
nand2 _387_ (
.A(_106_),
.B(_111_),
.Y(_112_)
);
or2 _388_ (
.A(_140_),
.B(_084_),
.Y(_113_)
);
or2 _389_ (
.A(_151_),
.B(_108_),
.Y(_114_)
);
and2 _390_ (
.A(_113_),
.B(_114_),
.Y(_115_)
);
nand2 _391_ (
.A(_112_),
.B(_115_),
.Y(_116_)
);
nand2 _392_ (
.A(_085_),
.B(_116_),
.Y(_117_)
);
nand2 _393_ (
.A(_082_),
.B(_117_),
.Y(_118_)
);
nand2 _394_ (
.A(_137_),
.B(_081_),
.Y(_119_)
);
xnor2 _395_ (
.A(_069_),
.B(_073_),
.Y(_120_)
);
and2 _396_ (
.A(_071_),
.B(_076_),
.Y(_121_)
);
and2 _397_ (
.A(_126_),
.B(_121_),
.Y(_122_)
);
imux2 _398_ (
.A(_122_),
.B(_120_),
.S(_079_),
.Y(_123_)
);
and2 _399_ (
.A(_119_),
.B(_123_),
.Y(_124_)
);
nand2 _400_ (
.A(_118_),
.B(_124_),
.Y(_125_)
);
and2 _401_ (
.A(_126_),
.B(_125_),
.Y(out[0])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_2_V
`define SKY130_FD_SC_HD__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_2_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_8_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H0000000043c100000000000043c00000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000004),
.C_S_AXI_READ_ACCEPTANCE(32'H00000004),
.C_M_AXI_WRITE_ISSUING(64'H0000000800000008),
.C_M_AXI_READ_ISSUING(64'H0000000800000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// CLOCK_MODULE
//
//
// Description: A module provided as a convenience for desingners using 2/4-byte
// lane Aurora Modules. This module takes the GT reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 1 ps
(* core_generation_info = "aur1,aurora_8b10b_v5_1,{backchannel_mode=Sidebands, c_aurora_lanes=4, c_column_used=left, c_gt_clock_1=GTPD7, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=3, c_gt_loc_14=4, c_gt_loc_15=1, c_gt_loc_16=2, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=X, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=156.25, c_simplex=false, c_simplex_mode=TX, c_stream=true, c_ufc=false, flow_mode=None, interface_mode=Streaming, dataflow_config=Duplex,}" *)
module aur1_CLOCK_MODULE #
(
parameter MULT = 2,
parameter DIVIDE = 1,
parameter CLK_PERIOD = 3.2,
parameter OUT0_DIVIDE = 4,
parameter OUT1_DIVIDE = 2,
parameter OUT2_DIVIDE = 4,
parameter OUT3_DIVIDE = 2
)
(
GT_CLK,
GT_CLK_LOCKED,
USER_CLK,
SYNC_CLK,
PLL_NOT_LOCKED
);
`define DLY #1
//***********************************Port Declarations*******************************
input GT_CLK;
input GT_CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output PLL_NOT_LOCKED;
//*********************************Wire Declarations**********************************
wire clkfb_w;
wire clkout0_o;
wire clkout1_o;
wire clkout2_o;
wire clkout3_o;
wire locked_w;
//*********************************Main Body of Code**********************************
// Instantiate a PLL module to divide the reference clock.
PLL_ADV #
(
.CLKFBOUT_MULT (MULT),
.DIVCLK_DIVIDE (DIVIDE),
.CLKFBOUT_PHASE (0),
.CLKIN1_PERIOD (CLK_PERIOD),
.CLKIN2_PERIOD (10), //Not used
.CLKOUT0_DIVIDE (OUT0_DIVIDE),
.CLKOUT0_PHASE (0),
.CLKOUT1_DIVIDE (OUT1_DIVIDE),
.CLKOUT1_PHASE (0),
.CLKOUT2_DIVIDE (OUT2_DIVIDE),
.CLKOUT2_PHASE (0),
.CLKOUT3_DIVIDE (OUT3_DIVIDE),
.CLKOUT3_PHASE (0)
)
pll_adv_i
(
.CLKIN1 (GT_CLK),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.CLKFBIN (clkfb_w),
.CLKOUT0 (clkout0_o),
.CLKOUT1 (clkout1_o),
.CLKOUT2 (clkout2_o),
.CLKOUT3 (clkout3_o),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKFBOUT (clkfb_w),
.CLKFBDCM (),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.DO (),
.DRDY (),
.DADDR (5'd0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'd0),
.DWE (1'b0),
.REL (1'b0),
.LOCKED (locked_w),
.RST (!GT_CLK_LOCKED)
);
// The PLL_NOT_LOCKED signal is created by inverting the PLL's locked signal.
assign PLL_NOT_LOCKED = ~locked_w;
// The User Clock is distributed on a global clock net.
BUFG user_clk_net_i
(
.I(clkout0_o),
.O(USER_CLK)
);
BUFG sync_clk_net_i
(
.I(clkout1_o),
.O(SYNC_CLK)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_32s_39_3_Mul3S_1(clk, ce, a, b, p);
input clk;
input ce;
input[7 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[39 - 1 : 0] p;
reg [7 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [39 - 1 : 0] tmp_product;
reg signed [39 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = $signed({1'b0, a_reg0}) * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_32s_39_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
feedforward_mul_7ns_32s_39_3_Mul3S_1 feedforward_mul_7ns_32s_39_3_Mul3S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetRegVec_1(
input clock,
input reset,
input [4:0] io_d,
output [4:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire [1:0] T_13;
wire [1:0] T_14;
wire [2:0] T_15;
wire [4:0] T_16;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
assign io_q = T_16;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = {reg_1_q,reg_0_q};
assign T_14 = {reg_4_q,reg_3_q};
assign T_15 = {T_14,reg_2_q};
assign T_16 = {T_15,T_13};
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_16x75k_dp.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_16x75k_dp (
address_a,
address_b,
byteena_a,
byteena_b,
clock_a,
clock_b,
data_a,
data_b,
enable_a,
enable_b,
wren_a,
wren_b,
q_a,
q_b);
input [16:0] address_a;
input [16:0] address_b;
input [1:0] byteena_a;
input [1:0] byteena_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input enable_a;
input enable_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 [1:0] byteena_b;
tri1 clock_a;
tri1 enable_a;
tri1 enable_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.byteena_b (byteena_b),
.clock0 (clock_a),
.clock1 (clock_b),
.clocken0 (enable_a),
.clocken1 (enable_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byteena_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_input_b = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 76800,
altsyncram_component.numwords_b = 76800,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 17,
altsyncram_component.widthad_b = 17,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 2,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1228800"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "76800"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "76800"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "2"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 17 0 INPUT NODEFVAL "address_a[16..0]"
// Retrieval info: USED_PORT: address_b 0 0 17 0 INPUT NODEFVAL "address_b[16..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]"
// Retrieval info: USED_PORT: byteena_b 0 0 2 0 INPUT VCC "byteena_b[1..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a"
// Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 17 0 address_a 0 0 17 0
// Retrieval info: CONNECT: @address_b 0 0 17 0 address_b 0 0 17 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
// Retrieval info: CONNECT: @byteena_b 0 0 2 0 byteena_b 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
// Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_dp_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_TB_V
`define SKY130_FD_SC_MS__AND2B_TB_V
/**
* and2b: 2-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_ms__and2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_BEHAVIORAL_PP_V |
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.60
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
module ddr3_model (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_model_parameters.vh"
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_register_slice (
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
parameter DATA_WIDTH = 32;
parameter FORWARD_REGISTERED = 0;
parameter BACKWARD_REGISTERED = 0;
/*
s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
*/
wire [DATA_WIDTH-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [DATA_WIDTH-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid;
reg [DATA_WIDTH-1:0] fwd_data;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready;
reg [DATA_WIDTH-1:0] bwd_data;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (bwd_ready)
bwd_data <= s_axi_data;
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin
assign bwd_valid_s = s_axi_valid;
assign bwd_data_s = s_axi_data;
assign bwd_ready_s = fwd_ready_s;
end endgenerate
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
assign s_axi_ready = bwd_ready_s;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file DAQ_MEM.v when simulating
// the core, DAQ_MEM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module DAQ_MEM(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [13 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(14),
.C_READ_WIDTH_B(7),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(14),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 11
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_11_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Video_Memory.v when simulating
// the core, Video_Memory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Video_Memory(
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [11 : 0] a;
input [15 : 0] d;
input [11 : 0] dpra;
input clk;
input we;
output [15 : 0] spo;
output [15 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(12),
.C_DEFAULT_DATA("0"),
.C_DEPTH(2400),
.C_FAMILY("spartan6"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("Video_Memory.mif"),
.C_MEM_TYPE(2),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(16)
)
inst (
.A(a),
.D(d),
.DPRA(dpra),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPO(dpo),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
module stage
(
inout wire [53:0] MIO,
inout wire PS_SRSTB,
inout wire PS_CLK,
inout wire PS_PORB,
inout wire DDR_Clk,
inout wire DDR_Clk_n,
inout wire DDR_CKE,
inout wire DDR_CS_n,
inout wire DDR_RAS_n,
inout wire DDR_CAS_n,
output wire DDR_WEB,
inout wire [2:0] DDR_BankAddr,
inout wire [14:0] DDR_Addr,
inout wire DDR_ODT,
inout wire DDR_DRSTB,
inout wire [31:0] DDR_DQ,
inout wire [3:0] DDR_DM,
inout wire [3:0] DDR_DQS,
inout wire [3:0] DDR_DQS_n,
inout wire DDR_VRN,
inout wire DDR_VRP,
output wire [7:0] LED
);
wire [3:0] fclk;
wire [3:0] fclkresetn;
wire FCLK0;
BUFG bufg(.I(fclk[0]),.O(FCLK0));
wire ARESETN;
assign ARESETN = fclkresetn[0];
wire [31:0] PS7_ARADDR;
wire [11:0] PS7_ARID;
wire [2:0] PS7_ARPROT;
wire PS7_ARREADY;
wire PS7_ARVALID;
wire [31:0] PS7_AWADDR;
wire [11:0] PS7_AWID;
wire [2:0] PS7_AWPROT;
wire PS7_AWREADY;
wire PS7_AWVALID;
wire [11:0] PS7_BID;
wire PS7_BREADY;
wire [1:0] PS7_BRESP;
wire PS7_BVALID;
wire [31:0] PS7_RDATA;
wire [11:0] PS7_RID;
wire PS7_RLAST;
wire PS7_RREADY;
wire [1:0] PS7_RRESP;
wire PS7_RVALID;
wire [31:0] PS7_WDATA;
wire PS7_WREADY;
wire [3:0] PS7_WSTRB;
wire PS7_WVALID;
wire [31:0] M_AXI_ARADDR;
wire M_AXI_ARREADY;
wire M_AXI_ARVALID;
wire [31:0] M_AXI_AWADDR;
wire M_AXI_AWREADY;
wire M_AXI_AWVALID;
wire M_AXI_BREADY;
wire [1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire [63:0] M_AXI_RDATA;
wire M_AXI_RREADY;
wire [1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
wire [63:0] M_AXI_WDATA;
wire M_AXI_WREADY;
wire [7:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
wire M_AXI_RLAST;
wire M_AXI_WLAST;
wire [3:0] M_AXI_ARLEN;
wire [1:0] M_AXI_ARSIZE;
wire [1:0] M_AXI_ARBURST;
wire [3:0] M_AXI_AWLEN;
wire [1:0] M_AXI_AWSIZE;
wire [1:0] M_AXI_AWBURST;
wire CONFIG_VALID;
wire [31:0] CONFIG_CMD;
wire [31:0] CONFIG_SRC;
wire [31:0] CONFIG_DEST;
wire [31:0] CONFIG_LEN;
wire CONFIG_IRQ;
wire READER_READY;
wire WRITER_READY;
wire CONFIG_READY;
assign CONFIG_READY = READER_READY && WRITER_READY;
Conf #(.ADDR_BASE(32'h70000000)) conf(
.ACLK(FCLK0),
.ARESETN(ARESETN),
.S_AXI_ARADDR(PS7_ARADDR),
.S_AXI_ARID(PS7_ARID),
.S_AXI_ARREADY(PS7_ARREADY),
.S_AXI_ARVALID(PS7_ARVALID),
.S_AXI_AWADDR(PS7_AWADDR),
.S_AXI_AWID(PS7_AWID),
.S_AXI_AWREADY(PS7_AWREADY),
.S_AXI_AWVALID(PS7_AWVALID),
.S_AXI_BID(PS7_BID),
.S_AXI_BREADY(PS7_BREADY),
.S_AXI_BRESP(PS7_BRESP),
.S_AXI_BVALID(PS7_BVALID),
.S_AXI_RDATA(PS7_RDATA),
.S_AXI_RID(PS7_RID),
.S_AXI_RLAST(PS7_RLAST),
.S_AXI_RREADY(PS7_RREADY),
.S_AXI_RRESP(PS7_RRESP),
.S_AXI_RVALID(PS7_RVALID),
.S_AXI_WDATA(PS7_WDATA),
.S_AXI_WREADY(PS7_WREADY),
.S_AXI_WSTRB(PS7_WSTRB),
.S_AXI_WVALID(PS7_WVALID),
.CONFIG_VALID(CONFIG_VALID),
.CONFIG_READY(CONFIG_READY),
.CONFIG_CMD(CONFIG_CMD),
.CONFIG_SRC(CONFIG_SRC),
.CONFIG_DEST(CONFIG_DEST),
.CONFIG_LEN(CONFIG_LEN),
.CONFIG_IRQ(CONFIG_IRQ));
// lengthInput/lengthOutput are in bytes
wire [31:0] lengthInput;
assign lengthInput = {4'b0000,CONFIG_LEN[27:0]};
wire [31:0] lengthOutput;
assign lengthOutput = (CONFIG_LEN[27:0] << 8'd8) >> CONFIG_LEN[31:28];
reg [31:0] clkcnt = 0;
// assign LED = clkcnt[20:13];
assign LED = clkcnt[28:21];
always @(posedge FCLK0) begin
// if(ARESETN == 0)
// LED <= 0;
// else if(CONFIG_VALID)
// LED <= {CONFIG_CMD[1:0],CONFIG_SRC[2:0],CONFIG_DEST[2:0]};
clkcnt <= clkcnt+1;
end
wire [63:0] pipelineInput;
wire pipelineInputValid;
wire [64:0] pipelineOutputPacked;
wire [63:0] pipelineOutput;
assign pipelineOutput = pipelineOutputPacked[63:0];
wire pipelineOutputValid;
assign pipelineOutputValid = pipelineOutputPacked[64];
wire pipelineReady;
wire downstreamReady;
___PIPELINE_TAPS
___PIPELINE_MODULE_NAME pipeline(.CLK(FCLK0),.reset(CONFIG_READY),.ready(pipelineReady),.ready_downstream(downstreamReady),.process_input({pipelineInputValid,pipelineInput}),.process_output(pipelineOutputPacked) ___PIPELINE_TAPINPUT );
// UnderflowShim #(.WAIT_CYCLES(___PIPELINE_WAIT_CYCLES)) OS(.CLK(FCLK0),.RST(CONFIG_READY),.lengthOutput(lengthOutput),.inp(pipelineOutputPacked[63:0]),.inp_valid(pipelineOutputPacked[64]),.out(pipelineOutput),.out_valid(pipelineOutputValid));
DRAMReader reader(
.ACLK(FCLK0),
.ARESETN(ARESETN),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RREADY(M_AXI_RREADY),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.CONFIG_VALID(CONFIG_VALID),
.CONFIG_READY(READER_READY),
.CONFIG_START_ADDR(CONFIG_SRC),
.CONFIG_NBYTES(___PIPELINE_INPUT_BYTES),
.DATA_READY_DOWNSTREAM(pipelineReady),
.DATA_VALID(pipelineInputValid),
.DATA(pipelineInput)
);
DRAMWriter writer(
.ACLK(FCLK0),
.ARESETN(ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.CONFIG_VALID(CONFIG_VALID),
.CONFIG_READY(WRITER_READY),
.CONFIG_START_ADDR(CONFIG_DEST),
.CONFIG_NBYTES(___PIPELINE_OUTPUT_BYTES),
.DATA_READY(downstreamReady),
.DATA_VALID(pipelineOutputValid),
.DATA(pipelineOutput)
);
PS7 ps7_0(
.DMA0DATYPE(), // out std_logic_vector(1 downto 0);
.DMA0DAVALID(), // out std_ulogic;
.DMA0DRREADY(), // out std_ulogic;
.DMA0RSTN(), // out std_ulogic;
.DMA1DATYPE(), // out std_logic_vector(1 downto 0);
.DMA1DAVALID(), // out std_ulogic;
.DMA1DRREADY(), // out std_ulogic;
.DMA1RSTN(), // out std_ulogic;
.DMA2DATYPE(), // out std_logic_vector(1 downto 0);
.DMA2DAVALID(), // out std_ulogic;
.DMA2DRREADY(), // out std_ulogic;
.DMA2RSTN(), // out std_ulogic;
.DMA3DATYPE(), // out std_logic_vector(1 downto 0);
.DMA3DAVALID(), // out std_ulogic;
.DMA3DRREADY(), // out std_ulogic;
.DMA3RSTN(), // out std_ulogic;
.EMIOCAN0PHYTX(), // out std_ulogic;
.EMIOCAN1PHYTX(), // out std_ulogic;
.EMIOENET0GMIITXD(), // out std_logic_vector(7 downto 0);
.EMIOENET0GMIITXEN(), // out std_ulogic;
.EMIOENET0GMIITXER(), // out std_ulogic;
.EMIOENET0MDIOMDC(), // out std_ulogic;
.EMIOENET0MDIOO(), // out std_ulogic;
.EMIOENET0MDIOTN(), // out std_ulogic;
.EMIOENET0PTPDELAYREQRX(), // out std_ulogic;
.EMIOENET0PTPDELAYREQTX(), // out std_ulogic;
.EMIOENET0PTPPDELAYREQRX(), // out std_ulogic;
.EMIOENET0PTPPDELAYREQTX(), // out std_ulogic;
.EMIOENET0PTPPDELAYRESPRX(), // out std_ulogic;
.EMIOENET0PTPPDELAYRESPTX(), // out std_ulogic;
.EMIOENET0PTPSYNCFRAMERX(), // out std_ulogic;
.EMIOENET0PTPSYNCFRAMETX(), // out std_ulogic;
.EMIOENET0SOFRX(), // out std_ulogic;
.EMIOENET0SOFTX(), // out std_ulogic;
.EMIOENET1GMIITXD(), // out std_logic_vector(7 downto 0);
.EMIOENET1GMIITXEN(), // out std_ulogic;
.EMIOENET1GMIITXER(), // out std_ulogic;
.EMIOENET1MDIOMDC(), // out std_ulogic;
.EMIOENET1MDIOO(), // out std_ulogic;
.EMIOENET1MDIOTN(), // out std_ulogic;
.EMIOENET1PTPDELAYREQRX(), // out std_ulogic;
.EMIOENET1PTPDELAYREQTX(), // out std_ulogic;
.EMIOENET1PTPPDELAYREQRX(), // out std_ulogic;
.EMIOENET1PTPPDELAYREQTX(), // out std_ulogic;
.EMIOENET1PTPPDELAYRESPRX(), // out std_ulogic;
.EMIOENET1PTPPDELAYRESPTX(), // out std_ulogic;
.EMIOENET1PTPSYNCFRAMERX(), // out std_ulogic;
.EMIOENET1PTPSYNCFRAMETX(), // out std_ulogic;
.EMIOENET1SOFRX(), // out std_ulogic;
.EMIOENET1SOFTX(), // out std_ulogic;
.EMIOGPIOO(), // out std_logic_vector(63 downto 0);
.EMIOGPIOTN(), // out std_logic_vector(63 downto 0);
.EMIOI2C0SCLO(), // out std_ulogic;
.EMIOI2C0SCLTN(), // out std_ulogic;
.EMIOI2C0SDAO(), // out std_ulogic;
.EMIOI2C0SDATN(), // out std_ulogic;
.EMIOI2C1SCLO(), // out std_ulogic;
.EMIOI2C1SCLTN(), // out std_ulogic;
.EMIOI2C1SDAO(), // out std_ulogic;
.EMIOI2C1SDATN(), // out std_ulogic;
.EMIOPJTAGTDO(), // out std_ulogic;
.EMIOPJTAGTDTN(), // out std_ulogic;
.EMIOSDIO0BUSPOW(), // out std_ulogic;
.EMIOSDIO0BUSVOLT(), // out std_logic_vector(2 downto 0);
.EMIOSDIO0CLK(), // out std_ulogic;
.EMIOSDIO0CMDO(), // out std_ulogic;
.EMIOSDIO0CMDTN(), // out std_ulogic;
.EMIOSDIO0DATAO(), // out std_logic_vector(3 downto 0);
.EMIOSDIO0DATATN(), // out std_logic_vector(3 downto 0);
.EMIOSDIO0LED(), // out std_ulogic;
.EMIOSDIO1BUSPOW(), // out std_ulogic;
.EMIOSDIO1BUSVOLT(), // out std_logic_vector(2 downto 0);
.EMIOSDIO1CLK(), // out std_ulogic;
.EMIOSDIO1CMDO(), // out std_ulogic;
.EMIOSDIO1CMDTN(), // out std_ulogic;
.EMIOSDIO1DATAO(), // out std_logic_vector(3 downto 0);
.EMIOSDIO1DATATN(), // out std_logic_vector(3 downto 0);
.EMIOSDIO1LED(), // out std_ulogic;
.EMIOSPI0MO(), // out std_ulogic;
.EMIOSPI0MOTN(), // out std_ulogic;
.EMIOSPI0SCLKO(), // out std_ulogic;
.EMIOSPI0SCLKTN(), // out std_ulogic;
.EMIOSPI0SO(), // out std_ulogic;
.EMIOSPI0SSNTN(), // out std_ulogic;
.EMIOSPI0SSON(), // out std_logic_vector(2 downto 0);
.EMIOSPI0STN(), // out std_ulogic;
.EMIOSPI1MO(), // out std_ulogic;
.EMIOSPI1MOTN(), // out std_ulogic;
.EMIOSPI1SCLKO(), // out std_ulogic;
.EMIOSPI1SCLKTN(), // out std_ulogic;
.EMIOSPI1SO(), // out std_ulogic;
.EMIOSPI1SSNTN(), // out std_ulogic;
.EMIOSPI1SSON(), // out std_logic_vector(2 downto 0);
.EMIOSPI1STN(), // out std_ulogic;
.EMIOTRACECTL(), // out std_ulogic;
.EMIOTRACEDATA(), // out std_logic_vector(31 downto 0);
.EMIOTTC0WAVEO(), // out std_logic_vector(2 downto 0);
.EMIOTTC1WAVEO(), // out std_logic_vector(2 downto 0);
.EMIOUART0DTRN(), // out std_ulogic;
.EMIOUART0RTSN(), // out std_ulogic;
.EMIOUART0TX(), // out std_ulogic;
.EMIOUART1DTRN(), // out std_ulogic;
.EMIOUART1RTSN(), // out std_ulogic;
.EMIOUART1TX(), // out std_ulogic;
.EMIOUSB0PORTINDCTL(), // out std_logic_vector(1 downto 0);
.EMIOUSB0VBUSPWRSELECT(), // out std_ulogic;
.EMIOUSB1PORTINDCTL(), // out std_logic_vector(1 downto 0);
.EMIOUSB1VBUSPWRSELECT(), // out std_ulogic;
.EMIOWDTRSTO(), // out std_ulogic;
.EVENTEVENTO(), // out std_ulogic;
.EVENTSTANDBYWFE(), // out std_logic_vector(1 downto 0);
.EVENTSTANDBYWFI(), // out std_logic_vector(1 downto 0);
.FCLKCLK(fclk), // out std_logic_vector(3 downto 0);
.FCLKRESETN(fclkresetn), // out std_logic_vector(3 downto 0);
.FTMTF2PTRIGACK(), // out std_logic_vector(3 downto 0);
.FTMTP2FDEBUG(), // out std_logic_vector(31 downto 0);
.FTMTP2FTRIG(), // out std_logic_vector(3 downto 0);
.IRQP2F(), // out std_logic_vector(28 downto 0);
.MAXIGP0ACLK(FCLK0), // in std_ulogic;
.MAXIGP0ARADDR(PS7_ARADDR), // out std_logic_vector(31 downto 0);
.MAXIGP0ARBURST(), // out std_logic_vector(1 downto 0);
.MAXIGP0ARCACHE(), // out std_logic_vector(3 downto 0);
.MAXIGP0ARESETN(), // out std_ulogic;
.MAXIGP0ARID(PS7_ARID), // out std_logic_vector(11 downto 0);
.MAXIGP0ARLEN(), // out std_logic_vector(3 downto 0);
.MAXIGP0ARLOCK(), // out std_logic_vector(1 downto 0);
.MAXIGP0ARPROT(), // out std_logic_vector(2 downto 0);
.MAXIGP0ARQOS(), // out std_logic_vector(3 downto 0);
.MAXIGP0ARREADY(PS7_ARREADY), // in std_ulogic;
.MAXIGP0ARSIZE(), // out std_logic_vector(1 downto 0);
.MAXIGP0ARVALID(PS7_ARVALID), // out std_ulogic;
.MAXIGP0AWADDR(PS7_AWADDR), // out std_logic_vector(31 downto 0);
.MAXIGP0AWBURST(), // out std_logic_vector(1 downto 0);
.MAXIGP0AWCACHE(), // out std_logic_vector(3 downto 0);
.MAXIGP0AWID(PS7_AWID), // out std_logic_vector(11 downto 0);
.MAXIGP0AWLEN(), // out std_logic_vector(3 downto 0);
.MAXIGP0AWLOCK(), // out std_logic_vector(1 downto 0);
.MAXIGP0AWPROT(), // out std_logic_vector(2 downto 0);
.MAXIGP0AWQOS(), // out std_logic_vector(3 downto 0);
.MAXIGP0AWREADY(PS7_AWREADY), // in std_ulogic;
.MAXIGP0AWSIZE(), // out std_logic_vector(1 downto 0);
.MAXIGP0AWVALID(PS7_AWVALID), // out std_ulogic;
.MAXIGP0BID(PS7_BID), // in std_logic_vector(11 downto 0);
.MAXIGP0BREADY(PS7_BREADY), // out std_ulogic;
.MAXIGP0BRESP(PS7_BRESP), // in std_logic_vector(1 downto 0);
.MAXIGP0BVALID(PS7_BVALID), // in std_ulogic;
.MAXIGP0RDATA(PS7_RDATA), // in std_logic_vector(31 downto 0);
.MAXIGP0RID(PS7_RID), // in std_logic_vector(11 downto 0);
.MAXIGP0RLAST(PS7_RLAST), // in std_ulogic;
.MAXIGP0RREADY(PS7_RREADY), // out std_ulogic;
.MAXIGP0RRESP(PS7_RRESP), // in std_logic_vector(1 downto 0);
.MAXIGP0RVALID(PS7_RVALID), // in std_ulogic;
.MAXIGP0WDATA(PS7_WDATA), // out std_logic_vector(31 downto 0);
.MAXIGP0WID(), // out std_logic_vector(11 downto 0);
.MAXIGP0WLAST(), // out std_ulogic;
.MAXIGP0WREADY(PS7_WREADY), // in std_ulogic;
.MAXIGP0WSTRB(PS7_WSTRB), // out std_logic_vector(3 downto 0);
.MAXIGP0WVALID(PS7_WVALID), // out std_ulogic;
.MAXIGP1ARADDR(), // out std_logic_vector(31 downto 0);
.MAXIGP1ARBURST(), // out std_logic_vector(1 downto 0);
.MAXIGP1ARCACHE(), // out std_logic_vector(3 downto 0);
.MAXIGP1ARESETN(), // out std_ulogic;
.MAXIGP1ARID(), // out std_logic_vector(11 downto 0);
.MAXIGP1ARLEN(), // out std_logic_vector(3 downto 0);
.MAXIGP1ARLOCK(), // out std_logic_vector(1 downto 0);
.MAXIGP1ARPROT(), // out std_logic_vector(2 downto 0);
.MAXIGP1ARQOS(), // out std_logic_vector(3 downto 0);
.MAXIGP1ARSIZE(), // out std_logic_vector(1 downto 0);
.MAXIGP1ARVALID(), // out std_ulogic;
.MAXIGP1AWADDR(), // out std_logic_vector(31 downto 0);
.MAXIGP1AWBURST(), // out std_logic_vector(1 downto 0);
.MAXIGP1AWCACHE(), // out std_logic_vector(3 downto 0);
.MAXIGP1AWID(), // out std_logic_vector(11 downto 0);
.MAXIGP1AWLEN(), // out std_logic_vector(3 downto 0);
.MAXIGP1AWLOCK(), // out std_logic_vector(1 downto 0);
.MAXIGP1AWPROT(), // out std_logic_vector(2 downto 0);
.MAXIGP1AWQOS(), // out std_logic_vector(3 downto 0);
.MAXIGP1AWSIZE(), // out std_logic_vector(1 downto 0);
.MAXIGP1AWVALID(), // out std_ulogic;
.MAXIGP1BREADY(), // out std_ulogic;
.MAXIGP1RREADY(), // out std_ulogic;
.MAXIGP1WDATA(), // out std_logic_vector(31 downto 0);
.MAXIGP1WID(), // out std_logic_vector(11 downto 0);
.MAXIGP1WLAST(), // out std_ulogic;
.MAXIGP1WSTRB(), // out std_logic_vector(3 downto 0);
.MAXIGP1WVALID(), // out std_ulogic;
.SAXIGP0ARESETN(), // out std_ulogic;
.SAXIGP0ARREADY(), // out std_ulogic;
.SAXIGP0AWREADY(), // out std_ulogic;
.SAXIGP0BID(), // out std_logic_vector(5 downto 0);
.SAXIGP0BRESP(), // out std_logic_vector(1 downto 0);
.SAXIGP0BVALID(), // out std_ulogic;
.SAXIGP0RDATA(), // out std_logic_vector(31 downto 0);
.SAXIGP0RID(), // out std_logic_vector(5 downto 0);
.SAXIGP0RLAST(), // out std_ulogic;
.SAXIGP0RRESP(), // out std_logic_vector(1 downto 0);
.SAXIGP0RVALID(), // out std_ulogic;
.SAXIGP0WREADY(), // out std_ulogic;
.SAXIGP1ARESETN(), // out std_ulogic;
.SAXIGP1ARREADY(), // out std_ulogic;
.SAXIGP1AWREADY(), // out std_ulogic;
.SAXIGP1BID(), // out std_logic_vector(5 downto 0);
.SAXIGP1BRESP(), // out std_logic_vector(1 downto 0);
.SAXIGP1BVALID(), // out std_ulogic;
.SAXIGP1RDATA(), // out std_logic_vector(31 downto 0);
.SAXIGP1RID(), // out std_logic_vector(5 downto 0);
.SAXIGP1RLAST(), // out std_ulogic;
.SAXIGP1RRESP(), // out std_logic_vector(1 downto 0);
.SAXIGP1RVALID(), // out std_ulogic;
.SAXIGP1WREADY(), // out std_ulogic;
.SAXIHP0ACLK(1'b0), // in std_ulogic;
.SAXIHP0ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP0ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0ARESETN(), // out std_ulogic;
.SAXIHP0ARID(6'b0), // in std_logic_vector(2 downto 0);
.SAXIHP0ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP0ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0ARREADY(), // out std_ulogic;
.SAXIHP0ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0ARVALID(1'b0), // in std_ulogic;
.SAXIHP0AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP0AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0AWID(6'b0), // in std_logic_vector(2 downto 0);
.SAXIHP0AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP0AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP0AWREADY(), // out std_ulogic;
.SAXIHP0AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP0AWVALID(1'b0), // in std_ulogic;
.SAXIHP0BID(), // out std_logic_vector(2 downto 0);
.SAXIHP0BREADY(1'b0), // in std_ulogic;
.SAXIHP0BRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP0BVALID(), // out std_ulogic;
.SAXIHP0RDATA(), // out std_logic_vector(63 downto 0);
.SAXIHP0RID(), // out std_logic_vector(2 downto 0);
.SAXIHP0RLAST(), // out std_ulogic;
.SAXIHP0RREADY(1'b0), // in std_ulogic;
.SAXIHP0RRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP0RVALID(), // out std_ulogic;
.SAXIHP0WDATA(64'b0), // in std_logic_vector(63 downto 0);
.SAXIHP0WID(6'b0), // in std_logic_vector(2 downto 0);
.SAXIHP0WLAST(1'b0), // in std_ulogic;
.SAXIHP0WREADY(), // out std_ulogic;
.SAXIHP0WSTRB(8'b0), // in std_logic_vector(7 downto 0);
.SAXIHP0WVALID(1'b0), // in std_ulogic;
.SAXIACPARUSER(5'b0), // in std_logic_vector(4 downto 0);
.SAXIACPAWUSER(5'b0), // in std_logic_vector(4 downto 0);
.SAXIACPACLK(FCLK0), // in std_ulogic;
.SAXIACPARADDR(M_AXI_ARADDR),
.SAXIACPARBURST(M_AXI_ARBURST), // in std_logic_vector(1 downto 0);
.SAXIACPARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIACPARESETN(), // out std_ulogic;
.SAXIACPARID(3'b0), // in std_logic_vector(5 downto 0);
.SAXIACPARLEN(M_AXI_ARLEN), // in std_logic_vector(3 downto 0);
.SAXIACPARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIACPARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIACPARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIACPARREADY(M_AXI_ARREADY),
.SAXIACPARSIZE(M_AXI_ARSIZE), // in std_logic_vector(1 downto 0);
.SAXIACPARVALID(M_AXI_ARVALID),
.SAXIACPAWADDR(M_AXI_AWADDR),
.SAXIACPAWBURST(M_AXI_AWBURST), // in std_logic_vector(1 downto 0);
.SAXIACPAWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIACPAWID(3'b0), // in std_logic_vector(5 downto 0);
.SAXIACPAWLEN(M_AXI_AWLEN), // in std_logic_vector(3 downto 0);
.SAXIACPAWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIACPAWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIACPAWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIACPAWREADY(M_AXI_AWREADY),
.SAXIACPAWSIZE(M_AXI_AWSIZE), // in std_logic_vector(1 downto 0);
.SAXIACPAWVALID(M_AXI_AWVALID),
.SAXIACPBID(), // out std_logic_vector(5 downto 0);
.SAXIACPBREADY(M_AXI_BREADY),
.SAXIACPBRESP(M_AXI_BRESP),
.SAXIACPBVALID(M_AXI_BVALID),
.SAXIACPRDATA(M_AXI_RDATA),
.SAXIACPRID(), // out std_logic_vector(5 downto 0);
.SAXIACPRLAST(M_AXI_RLAST), // out std_ulogic;
.SAXIACPRREADY(M_AXI_RREADY),
.SAXIACPRRESP(M_AXI_RRESP),
.SAXIACPRVALID(M_AXI_RVALID),
.SAXIACPWDATA(M_AXI_WDATA),
.SAXIACPWID(3'b0), // in std_logic_vector(5 downto 0);
.SAXIACPWLAST(M_AXI_WLAST), // in std_ulogic;
.SAXIACPWREADY(M_AXI_WREADY),
.SAXIACPWSTRB(M_AXI_WSTRB),
.SAXIACPWVALID(M_AXI_WVALID),
.SAXIHP0RDISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP0WRISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP0RACOUNT(), // out std_logic_vector(2 downto 0);
.SAXIHP0RCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP0WACOUNT(), // out std_logic_vector(5 downto 0);
.SAXIHP0WCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP1ARESETN(), // out std_ulogic;
.SAXIHP1ARREADY(), // out std_ulogic;
.SAXIHP1AWREADY(), // out std_ulogic;
.SAXIHP1BID(), // out std_logic_vector(5 downto 0);
.SAXIHP1BRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP1BVALID(), // out std_ulogic;
.SAXIHP1RACOUNT(), // out std_logic_vector(2 downto 0);
.SAXIHP1RCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP1RDATA(), // out std_logic_vector(63 downto 0);
.SAXIHP1RID(), // out std_logic_vector(5 downto 0);
.SAXIHP1RLAST(), // out std_ulogic;
.SAXIHP1RRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP1RVALID(), // out std_ulogic;
.SAXIHP1WACOUNT(), // out std_logic_vector(5 downto 0);
.SAXIHP1WCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP1WREADY(), // out std_ulogic;
.SAXIHP2ARESETN(), // out std_ulogic;
.SAXIHP2ARREADY(), // out std_ulogic;
.SAXIHP2AWREADY(), // out std_ulogic;
.SAXIHP2BID(), // out std_logic_vector(5 downto 0);
.SAXIHP2BRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP2BVALID(), // out std_ulogic;
.SAXIHP2RACOUNT(), // out std_logic_vector(2 downto 0);
.SAXIHP2RCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP2RDATA(), // out std_logic_vector(63 downto 0);
.SAXIHP2RID(), // out std_logic_vector(5 downto 0);
.SAXIHP2RLAST(), // out std_ulogic;
.SAXIHP2RRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP2RVALID(), // out std_ulogic;
.SAXIHP2WACOUNT(), // out std_logic_vector(5 downto 0);
.SAXIHP2WCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP2WREADY(), // out std_ulogic;
.SAXIHP3ARESETN(), // out std_ulogic;
.SAXIHP3ARREADY(), // out std_ulogic;
.SAXIHP3AWREADY(), // out std_ulogic;
.SAXIHP3BID(), // out std_logic_vector(5 downto 0);
.SAXIHP3BRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP3BVALID(), // out std_ulogic;
.SAXIHP3RACOUNT(), // out std_logic_vector(2 downto 0);
.SAXIHP3RCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP3RDATA(), // out std_logic_vector(63 downto 0);
.SAXIHP3RID(), // out std_logic_vector(5 downto 0);
.SAXIHP3RLAST(), // out std_ulogic;
.SAXIHP3RRESP(), // out std_logic_vector(1 downto 0);
.SAXIHP3RVALID(), // out std_ulogic;
.SAXIHP3WACOUNT(), // out std_logic_vector(5 downto 0);
.SAXIHP3WCOUNT(), // out std_logic_vector(7 downto 0);
.SAXIHP3WREADY(), // out std_ulogic;
.DDRA(DDR_Addr), // inout std_logic_vector(14 downto 0);
.DDRBA(DDR_BankAddr), // inout std_logic_vector(2 downto 0);
.DDRCASB(DDR_CAS_n), // inout std_ulogic;
.DDRCKE(DDR_CKE), // inout std_ulogic;
.DDRCKN(DDR_Clk_n), // inout std_ulogic;
.DDRCKP(DDR_Clk), // inout std_ulogic;
.DDRCSB(DDR_CS_n), // inout std_ulogic;
.DDRDM(DDR_DM), // inout std_logic_vector(3 downto 0);
.DDRDQ(DDR_DQ), // inout std_logic_vector(31 downto 0);
.DDRDQSN(DDR_DQS_n), // inout std_logic_vector(3 downto 0);
.DDRDQSP(DDR_DQS), // inout std_logic_vector(3 downto 0);
.DDRDRSTB(DDR_DRSTB), // inout std_ulogic;
.DDRODT(DDR_ODT), // inout std_ulogic;
.DDRRASB(DDR_RAS_n), // inout std_ulogic;
.DDRVRN(DDR_VRN), // inout std_ulogic;
.DDRVRP(DDR_VRP), // inout std_ulogic;
.DDRWEB(DDR_WEB), // inout std_ulogic;
.MIO(MIO), // inout std_logic_vector(53 downto 0);
.PSCLK(PS_CLK), // inout std_ulogic;
.PSPORB(PS_PORB), // inout std_ulogic;
.PSSRSTB(PS_SRSTB), // inout std_ulogic;
.DDRARB(4'b0), // in std_logic_vector(3 downto 0);
.DMA0ACLK(1'b0), // in std_ulogic;
.DMA0DAREADY(1'b0), // in std_ulogic;
.DMA0DRLAST(1'b0), // in std_ulogic;
.DMA0DRTYPE(2'b0), // in std_logic_vector(1 downto 0);
.DMA0DRVALID(1'b0), // in std_ulogic;
.DMA1ACLK(1'b0), // in std_ulogic;
.DMA1DAREADY(1'b0), // in std_ulogic;
.DMA1DRLAST(1'b0), // in std_ulogic;
.DMA1DRTYPE(2'b0), // in std_logic_vector(1 downto 0);
.DMA1DRVALID(1'b0), // in std_ulogic;
.DMA2ACLK(1'b0), // in std_ulogic;
.DMA2DAREADY(1'b0), // in std_ulogic;
.DMA2DRLAST(1'b0), // in std_ulogic;
.DMA2DRTYPE(2'b0), // in std_logic_vector(1 downto 0);
.DMA2DRVALID(1'b0), // in std_ulogic;
.DMA3ACLK(1'b0), // in std_ulogic;
.DMA3DAREADY(1'b0), // in std_ulogic;
.DMA3DRLAST(1'b0), // in std_ulogic;
.DMA3DRTYPE(2'b0), // in std_logic_vector(1 downto 0);
.DMA3DRVALID(1'b0), // in std_ulogic;
.EMIOCAN0PHYRX(1'b0), // in std_ulogic;
.EMIOCAN1PHYRX(1'b0), // in std_ulogic;
.EMIOENET0EXTINTIN(1'b0), // in std_ulogic;
.EMIOENET0GMIICOL(1'b0), // in std_ulogic;
.EMIOENET0GMIICRS(1'b0), // in std_ulogic;
.EMIOENET0GMIIRXCLK(1'b0), // in std_ulogic;
.EMIOENET0GMIIRXD(8'b0), // in std_logic_vector(7 downto 0);
.EMIOENET0GMIIRXDV(1'b0), // in std_ulogic;
.EMIOENET0GMIIRXER(1'b0), // in std_ulogic;
.EMIOENET0GMIITXCLK(1'b0), // in std_ulogic;
.EMIOENET0MDIOI(1'b0), // in std_ulogic;
.EMIOENET1EXTINTIN(1'b0), // in std_ulogic;
.EMIOENET1GMIICOL(1'b0), // in std_ulogic;
.EMIOENET1GMIICRS(1'b0), // in std_ulogic;
.EMIOENET1GMIIRXCLK(1'b0), // in std_ulogic;
.EMIOENET1GMIIRXD(8'b0), // in std_logic_vector(7 downto 0);
.EMIOENET1GMIIRXDV(1'b0), // in std_ulogic;
.EMIOENET1GMIIRXER(1'b0), // in std_ulogic;
.EMIOENET1GMIITXCLK(1'b0), // in std_ulogic;
.EMIOENET1MDIOI(1'b0), // in std_ulogic;
.EMIOGPIOI(64'b0), // in std_logic_vector(63 downto 0);
.EMIOI2C0SCLI(1'b0), // in std_ulogic;
.EMIOI2C0SDAI(1'b0), // in std_ulogic;
.EMIOI2C1SCLI(1'b0), // in std_ulogic;
.EMIOI2C1SDAI(1'b0), // in std_ulogic;
.EMIOPJTAGTCK(1'b0), // in std_ulogic;
.EMIOPJTAGTDI(1'b0), // in std_ulogic;
.EMIOPJTAGTMS(1'b0), // in std_ulogic;
.EMIOSDIO0CDN(1'b0), // in std_ulogic;
.EMIOSDIO0CLKFB(1'b0), // in std_ulogic;
.EMIOSDIO0CMDI(1'b0), // in std_ulogic;
.EMIOSDIO0DATAI(4'b0), // in std_logic_vector(3 downto 0);
.EMIOSDIO0WP(1'b0), // in std_ulogic;
.EMIOSDIO1CDN(1'b0), // in std_ulogic;
.EMIOSDIO1CLKFB(1'b0), // in std_ulogic;
.EMIOSDIO1CMDI(1'b0), // in std_ulogic;
.EMIOSDIO1DATAI(4'b0), // in std_logic_vector(3 downto 0);
.EMIOSDIO1WP(1'b0), // in std_ulogic;
.EMIOSPI0MI(1'b0), // in std_ulogic;
.EMIOSPI0SCLKI(1'b0), // in std_ulogic;
.EMIOSPI0SI(1'b0), // in std_ulogic;
.EMIOSPI0SSIN(1'b0), // in std_ulogic;
.EMIOSPI1MI(1'b0), // in std_ulogic;
.EMIOSPI1SCLKI(1'b0), // in std_ulogic;
.EMIOSPI1SI(1'b0), // in std_ulogic;
.EMIOSPI1SSIN(1'b0), // in std_ulogic;
.EMIOSRAMINTIN(1'b0), // in std_ulogic;
.EMIOTRACECLK(1'b0), // in std_ulogic;
.EMIOTTC0CLKI(3'b0), // in std_logic_vector(2 downto 0);
.EMIOTTC1CLKI(3'b0), // in std_logic_vector(2 downto 0);
.EMIOUART0CTSN(1'b0), // in std_ulogic;
.EMIOUART0DCDN(1'b0), // in std_ulogic;
.EMIOUART0DSRN(1'b0), // in std_ulogic;
.EMIOUART0RIN(1'b0), // in std_ulogic;
.EMIOUART0RX(1'b0), // in std_ulogic;
.EMIOUART1CTSN(1'b0), // in std_ulogic;
.EMIOUART1DCDN(1'b0), // in std_ulogic;
.EMIOUART1DSRN(1'b0), // in std_ulogic;
.EMIOUART1RIN(1'b0), // in std_ulogic;
.EMIOUART1RX(1'b0), // in std_ulogic;
.EMIOUSB0VBUSPWRFAULT(1'b0), // in std_ulogic;
.EMIOUSB1VBUSPWRFAULT(1'b0), // in std_ulogic;
.EMIOWDTCLKI(1'b0), // in std_ulogic;
.EVENTEVENTI(1'b0), // in std_ulogic;
.FCLKCLKTRIGN(4'b0), // in std_logic_vector(3 downto 0);
.FPGAIDLEN(1'b0), // in std_ulogic;
.FTMDTRACEINATID(4'b0), // in std_logic_vector(3 downto 0);
.FTMDTRACEINCLOCK(1'b0), // in std_ulogic;
.FTMDTRACEINDATA(32'b0), // in std_logic_vector(31 downto 0);
.FTMDTRACEINVALID(1'b0), // in std_ulogic;
.FTMTF2PDEBUG(32'b0), // in std_logic_vector(31 downto 0);
.FTMTF2PTRIG(4'b0), // in std_logic_vector(3 downto 0);
.FTMTP2FTRIGACK(4'b0), // in std_logic_vector(3 downto 0);
.IRQF2P({19'b0,CONFIG_IRQ}), // in std_logic_vector(19 downto 0);
.MAXIGP1ACLK(1'b0), // in std_ulogic;
.MAXIGP1ARREADY(1'b0), // in std_ulogic;
.MAXIGP1AWREADY(1'b0), // in std_ulogic;
.MAXIGP1BID(12'b0), // in std_logic_vector(11 downto 0);
.MAXIGP1BRESP(2'b0), // in std_logic_vector(1 downto 0);
.MAXIGP1BVALID(1'b0), // in std_ulogic;
.MAXIGP1RDATA(32'b0), // in std_logic_vector(31 downto 0);
.MAXIGP1RID(12'b0), // in std_logic_vector(11 downto 0);
.MAXIGP1RLAST(1'b0), // in std_ulogic;
.MAXIGP1RRESP(2'b0), // in std_logic_vector(1 downto 0);
.MAXIGP1RVALID(1'b0), // in std_ulogic;
.MAXIGP1WREADY(1'b0), // in std_ulogic;
.SAXIGP0ACLK(1'b0), // in std_ulogic;
.SAXIGP0ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP0ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0ARID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP0ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIGP0ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0ARVALID(1'b0), // in std_ulogic;
.SAXIGP0AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP0AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0AWID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP0AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIGP0AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP0AWVALID(1'b0), // in std_ulogic;
.SAXIGP0BREADY(1'b0), // in std_ulogic;
.SAXIGP0RREADY(1'b0), // in std_ulogic;
.SAXIGP0WDATA(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP0WID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP0WLAST(1'b0), // in std_ulogic;
.SAXIGP0WSTRB(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP0WVALID(1'b0), // in std_ulogic;
.SAXIGP1ACLK(1'b0), // in std_ulogic;
.SAXIGP1ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP1ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1ARID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP1ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIGP1ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1ARVALID(1'b0), // in std_ulogic;
.SAXIGP1AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP1AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1AWID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP1AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIGP1AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIGP1AWVALID(1'b0), // in std_ulogic;
.SAXIGP1BREADY(1'b0), // in std_ulogic;
.SAXIGP1RREADY(1'b0), // in std_ulogic;
.SAXIGP1WDATA(32'b0), // in std_logic_vector(31 downto 0);
.SAXIGP1WID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIGP1WLAST(1'b0), // in std_ulogic;
.SAXIGP1WSTRB(4'b0), // in std_logic_vector(3 downto 0);
.SAXIGP1WVALID(1'b0), // in std_ulogic;
.SAXIHP1ACLK(1'b0), // in std_ulogic;
.SAXIHP1ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP1ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1ARID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP1ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP1ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1ARVALID(1'b0), // in std_ulogic;
.SAXIHP1AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP1AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1AWID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP1AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP1AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP1AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP1AWVALID(1'b0), // in std_ulogic;
.SAXIHP1BREADY(1'b0), // in std_ulogic;
.SAXIHP1RDISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP1RREADY(1'b0), // in std_ulogic;
.SAXIHP1WDATA(64'b0), // in std_logic_vector(63 downto 0);
.SAXIHP1WID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP1WLAST(1'b0), // in std_ulogic;
.SAXIHP1WRISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP1WSTRB(8'b0), // in std_logic_vector(7 downto 0);
.SAXIHP1WVALID(1'b0), // in std_ulogic;
.SAXIHP2ACLK(1'b0), // in std_ulogic;
.SAXIHP2ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP2ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2ARID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP2ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP2ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2ARVALID(1'b0), // in std_ulogic;
.SAXIHP2AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP2AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2AWID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP2AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP2AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP2AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP2AWVALID(1'b0), // in std_ulogic;
.SAXIHP2BREADY(1'b0), // in std_ulogic;
.SAXIHP2RDISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP2RREADY(1'b0), // in std_ulogic;
.SAXIHP2WDATA(64'b0), // in std_logic_vector(63 downto 0);
.SAXIHP2WID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP2WLAST(1'b0), // in std_ulogic;
.SAXIHP2WRISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP2WSTRB(8'b0), // in std_logic_vector(7 downto 0);
.SAXIHP2WVALID(1'b0), // in std_ulogic;
.SAXIHP3ACLK(1'b0), // in std_ulogic;
.SAXIHP3ARADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP3ARBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3ARCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3ARID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP3ARLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3ARLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3ARPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP3ARQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3ARSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3ARVALID(1'b0), // in std_ulogic;
.SAXIHP3AWADDR(32'b0), // in std_logic_vector(31 downto 0);
.SAXIHP3AWBURST(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3AWCACHE(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3AWID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP3AWLEN(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3AWLOCK(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3AWPROT(3'b0), // in std_logic_vector(2 downto 0);
.SAXIHP3AWQOS(4'b0), // in std_logic_vector(3 downto 0);
.SAXIHP3AWSIZE(2'b0), // in std_logic_vector(1 downto 0);
.SAXIHP3AWVALID(1'b0), // in std_ulogic;
.SAXIHP3BREADY(1'b0), // in std_ulogic;
.SAXIHP3RDISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP3RREADY(1'b0), // in std_ulogic;
.SAXIHP3WDATA(64'b0), // in std_logic_vector(63 downto 0);
.SAXIHP3WID(6'b0), // in std_logic_vector(5 downto 0);
.SAXIHP3WLAST(1'b0), // in std_ulogic;
.SAXIHP3WRISSUECAP1EN(1'b0), // in std_ulogic;
.SAXIHP3WSTRB(8'b0), // in std_logic_vector(7 downto 0);
.SAXIHP3WVALID(1'b0) // in std_ulogic;
);
endmodule
|
`timescale 1ns/1ns
module op_usmod
(input c,
input [15:0] a,
input [15:0] b,
output [15:0] q,
input start,
output done);
// register the inputs to help timing
wire [15:0] a_i, b_i;
d1 #(16) a_i_r(.c(c), .d(a), .q(a_i));
d1 #(16) b_i_r(.c(c), .d(b), .q(b_i));
lpm_divide
#(.lpm_widthn(16),
.lpm_widthd(16),
.lpm_nrepresentation("UNSIGNED"),
.lpm_drepresentation("UNSIGNED"),
.lpm_hint("LPM_REMAINDERPOSITIVE=TRUE"),
.lpm_pipeline(8) // not sure what's best here
) div_inst
(.numer(a_i), .denom(b_i), .clock(c), .clken(1'b1), .aclr(1'b0),
.quotient(), .remain(q));
wire [4:0] cnt;
r #(5) cnt_r
(.c(c), .rst(1'b0), .en(|cnt | start), .d(start ? 5'h1 : cnt+1'b1), .q(cnt));
assign done = cnt == 5'd10; // not sure what this should be
endmodule
////////////////////////////////////////////////////////////////////
`ifdef test_div
module div_tb();
reg [31:0] a, b;
wire [31:0] q;
reg start;
wire done;
wire c;
sim_clk #(125) clk_125(.clk(c));
div dut(.*);
initial begin
$dumpfile("div.lxt");
$dumpvars();
start = 1'b0;
a = 32'h3f80_0000; // 1.0
b = 32'h3fcc_b55a; // 1.59928441047
wait(~c);
wait(c);
start <= 1'b1;
wait(~c);
wait(c);
start <= 1'b0;
#10000;
$finish();
end
endmodule
`endif
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module control_status_slave_which_resides_within_sgdma_rx (
// inputs:
atlantic_error,
chain_run,
clk,
command_fifo_empty,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
desc_address_fifo_empty,
descriptor_read_address,
descriptor_read_read,
descriptor_write_busy,
descriptor_write_write,
owned_by_hw,
reset_n,
status_token_fifo_empty,
status_token_fifo_rdreq,
t_eop,
write_go,
// outputs:
csr_irq,
csr_readdata,
descriptor_pointer_lower_reg_out,
descriptor_pointer_upper_reg_out,
park,
pollen_clear_run,
run,
sw_reset
)
;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] descriptor_pointer_lower_reg_out;
output [ 31: 0] descriptor_pointer_upper_reg_out;
output park;
output pollen_clear_run;
output run;
output sw_reset;
input atlantic_error;
input chain_run;
input clk;
input command_fifo_empty;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input desc_address_fifo_empty;
input [ 31: 0] descriptor_read_address;
input descriptor_read_read;
input descriptor_write_busy;
input descriptor_write_write;
input owned_by_hw;
input reset_n;
input status_token_fifo_empty;
input status_token_fifo_rdreq;
input t_eop;
input write_go;
reg busy;
reg can_have_new_chain_complete;
reg chain_completed;
reg chain_completed_int;
wire chain_completed_int_rise;
wire clear_chain_completed;
wire clear_descriptor_completed;
wire clear_eop_encountered;
wire clear_error;
reg clear_interrupt;
wire clear_run;
reg [ 31: 0] control_reg;
wire control_reg_en;
wire csr_control;
reg csr_irq;
reg [ 31: 0] csr_readdata;
wire csr_status;
reg delayed_chain_completed_int;
reg delayed_csr_write;
reg [ 7: 0] delayed_descriptor_counter;
reg delayed_descriptor_write_write;
reg delayed_eop_encountered;
reg delayed_run;
reg descriptor_completed;
reg [ 7: 0] descriptor_counter;
wire [ 31: 0] descriptor_pointer_data;
reg [ 31: 0] descriptor_pointer_lower_reg;
wire descriptor_pointer_lower_reg_en;
wire [ 31: 0] descriptor_pointer_lower_reg_out;
reg [ 31: 0] descriptor_pointer_upper_reg;
wire descriptor_pointer_upper_reg_en;
wire [ 31: 0] descriptor_pointer_upper_reg_out;
reg descriptor_read_read_r;
wire descriptor_read_read_rising;
wire descriptor_write_write_fall;
reg do_restart;
reg do_restart_compare;
reg eop_encountered;
wire eop_encountered_rise;
reg error;
wire [ 3: 0] hw_version;
wire ie_chain_completed;
wire ie_descriptor_completed;
wire ie_eop_encountered;
wire ie_error;
wire ie_global;
wire ie_max_desc_processed;
wire [ 7: 0] max_desc_processed;
wire park;
wire poll_en;
wire pollen_clear_run;
wire run;
wire [ 31: 0] status_reg;
wire stop_dma_error;
wire sw_reset;
reg [ 15: 0] timeout_counter;
wire [ 10: 0] timeout_reg;
wire version_reg;
//csr, which is an e_avalon_slave
//Control Status Register (Readdata)
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
csr_readdata <= 0;
else if (csr_read)
case (csr_address) // synthesis parallel_case
{4'b0000}: begin
csr_readdata <= status_reg;
end // {4'b0000}
{4'b0001}: begin
csr_readdata <= version_reg;
end // {4'b0001}
{4'b0100}: begin
csr_readdata <= control_reg;
end // {4'b0100}
{4'b1000}: begin
csr_readdata <= descriptor_pointer_lower_reg;
end // {4'b1000}
{4'b1100}: begin
csr_readdata <= descriptor_pointer_upper_reg;
end // {4'b1100}
default: begin
csr_readdata <= 32'b0;
end // default
endcase // csr_address
end
//register outs
assign descriptor_pointer_upper_reg_out = descriptor_pointer_upper_reg;
assign descriptor_pointer_lower_reg_out = descriptor_pointer_lower_reg;
//control register bits
assign ie_error = control_reg[0];
assign ie_eop_encountered = control_reg[1];
assign ie_descriptor_completed = control_reg[2];
assign ie_chain_completed = control_reg[3];
assign ie_global = control_reg[4];
assign run = control_reg[5] && (!(stop_dma_error && error) && ((!chain_completed_int ) ||( do_restart && poll_en && chain_completed_int)));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_run <= 0;
else
delayed_run <= run;
end
assign stop_dma_error = control_reg[6];
assign ie_max_desc_processed = control_reg[7];
assign max_desc_processed = control_reg[15 : 8];
assign sw_reset = control_reg[16];
assign park = control_reg[17];
assign poll_en = control_reg[18];
assign timeout_reg = control_reg[30 : 20];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_counter <= 0;
else if ((control_reg[5] && !busy && poll_en )|| do_restart)
timeout_counter <= do_restart ? 0:(timeout_counter + 1'b1);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_restart_compare <= 0;
else
do_restart_compare <= timeout_counter == {timeout_reg,5'b11111};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_restart <= 0;
else
do_restart <= poll_en && do_restart_compare;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clear_interrupt <= 0;
else
clear_interrupt <= control_reg_en ? csr_writedata[31] : 0;
end
//control register
assign control_reg_en = (csr_address == { 4'b0100}) && csr_write && csr_chipselect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_reg_en)
control_reg <= {1'b0, csr_writedata[30 : 0]};
end
//descriptor_pointer_upper_reg
assign descriptor_pointer_upper_reg_en = (csr_address == { 4'b1100}) && csr_write && csr_chipselect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_pointer_upper_reg <= 0;
else if (descriptor_pointer_upper_reg_en)
descriptor_pointer_upper_reg <= csr_writedata;
end
//section to update the descriptor pointer
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_read_r <= 0;
else
descriptor_read_read_r <= descriptor_read_read;
end
assign descriptor_read_read_rising = descriptor_read_read && !descriptor_read_read_r;
assign descriptor_pointer_data = descriptor_read_read_rising ? descriptor_read_address:csr_writedata;
//descriptor_pointer_lower_reg
assign descriptor_pointer_lower_reg_en = ((csr_address == { 4'b1000}) && csr_write && csr_chipselect) || (poll_en && descriptor_read_read_rising);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_pointer_lower_reg <= 0;
else if (descriptor_pointer_lower_reg_en)
descriptor_pointer_lower_reg <= descriptor_pointer_data;
end
//Hardware Version Register
assign hw_version = 4'b0001;
assign version_reg = {24'h000000, hw_version};
//status register
assign status_reg = {27'b0, busy, chain_completed, descriptor_completed, eop_encountered, error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
busy <= 0;
else
busy <= ~command_fifo_empty || ~status_token_fifo_empty || ~desc_address_fifo_empty || chain_run || descriptor_write_busy || delayed_csr_write || owned_by_hw || write_go;
end
//Chain Completed Status Register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_completed <= 0;
else if ((run && ~owned_by_hw && ~busy) || clear_chain_completed || do_restart)
chain_completed <= (clear_chain_completed || do_restart)? 1'b0 : ~delayed_csr_write;
end
//chain_completed_int is the internal chain completed state for SGDMA.
//Will not be affected with clearing of chain_completed Status Register,to prevent SGDMA being restarted when the status bit is cleared
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_completed_int <= 0;
else if ((run && ~owned_by_hw && ~busy) || clear_run || do_restart)
chain_completed_int <= (clear_run || do_restart) ? 1'b0 : ~delayed_csr_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_csr_write <= 0;
else
delayed_csr_write <= csr_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_completed <= 0;
else if (descriptor_write_write_fall || clear_descriptor_completed)
descriptor_completed <= ~clear_descriptor_completed;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
error <= 0;
else if (atlantic_error || clear_error)
error <= ~clear_error;
end
assign csr_status = csr_write && csr_chipselect && (csr_address == 4'b0);
assign clear_chain_completed = csr_writedata[3] && csr_status;
assign clear_descriptor_completed = csr_writedata[2] && csr_status;
assign clear_error = csr_writedata[0] && csr_status;
assign csr_control = csr_write && csr_chipselect && (csr_address == 4'h4);
assign clear_run = !csr_writedata[5] && csr_control;
assign pollen_clear_run = poll_en & clear_run;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_eop_encountered <= 0;
else
delayed_eop_encountered <= eop_encountered;
end
assign eop_encountered_rise = ~delayed_eop_encountered && eop_encountered;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_descriptor_write_write <= 0;
else
delayed_descriptor_write_write <= descriptor_write_write;
end
assign descriptor_write_write_fall = delayed_descriptor_write_write && ~descriptor_write_write;
//eop_encountered register
assign clear_eop_encountered = csr_writedata[1] && csr_status;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_encountered <= 0;
else if (t_eop || clear_eop_encountered)
eop_encountered <= ~clear_eop_encountered;
end
//chain_completed rising edge detector
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_chain_completed_int <= 0;
else
delayed_chain_completed_int <= chain_completed_int;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
can_have_new_chain_complete <= 0;
else if (descriptor_write_write || (~delayed_chain_completed_int && chain_completed_int))
can_have_new_chain_complete <= descriptor_write_write;
end
assign chain_completed_int_rise = ~delayed_chain_completed_int && chain_completed_int && can_have_new_chain_complete;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_counter <= 0;
else if (status_token_fifo_rdreq)
descriptor_counter <= descriptor_counter + 1'b1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_descriptor_counter <= 0;
else
delayed_descriptor_counter <= descriptor_counter;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
csr_irq <= 0;
else
csr_irq <= csr_irq ? ~clear_interrupt : (delayed_run && ie_global && ((ie_error && error) || (ie_eop_encountered && eop_encountered_rise) || (ie_descriptor_completed && descriptor_write_write_fall) || (ie_chain_completed && chain_completed_int_rise) || (ie_max_desc_processed && (descriptor_counter == max_desc_processed) && (delayed_descriptor_counter == max_desc_processed - 1) )));
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo (
// inputs:
clk,
controlbitsfifo_data,
controlbitsfifo_rdreq,
controlbitsfifo_wrreq,
reset,
// outputs:
controlbitsfifo_empty,
controlbitsfifo_full,
controlbitsfifo_q
)
;
output controlbitsfifo_empty;
output controlbitsfifo_full;
output [ 6: 0] controlbitsfifo_q;
input clk;
input [ 6: 0] controlbitsfifo_data;
input controlbitsfifo_rdreq;
input controlbitsfifo_wrreq;
input reset;
wire controlbitsfifo_empty;
wire controlbitsfifo_full;
wire [ 6: 0] controlbitsfifo_q;
scfifo descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo
(
.aclr (reset),
.clock (clk),
.data (controlbitsfifo_data),
.empty (controlbitsfifo_empty),
.full (controlbitsfifo_full),
.q (controlbitsfifo_q),
.rdreq (controlbitsfifo_rdreq),
.wrreq (controlbitsfifo_wrreq)
);
defparam descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.add_ram_output_register = "ON",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.intended_device_family = "STRATIXIV",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_numwords = 2,
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_showahead = "OFF",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_type = "scfifo",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_width = 7,
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_widthu = 1,
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.overflow_checking = "ON",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.underflow_checking = "ON",
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo_controlbitsfifo.use_eab = "OFF";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_read_which_resides_within_sgdma_rx (
// inputs:
clk,
command_fifo_full,
controlbitsfifo_rdreq,
desc_address_fifo_full,
descriptor_pointer_lower_reg_out,
descriptor_pointer_upper_reg_out,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
pollen_clear_run,
reset,
reset_n,
run,
// outputs:
atlantic_channel,
chain_run,
command_fifo_data,
command_fifo_wrreq,
control,
controlbitsfifo_q,
desc_address_fifo_data,
desc_address_fifo_wrreq,
descriptor_read_address,
descriptor_read_read,
generate_eop,
next_desc,
owned_by_hw,
read_fixed_address,
write_fixed_address
)
;
output [ 3: 0] atlantic_channel;
output chain_run;
output [103: 0] command_fifo_data;
output command_fifo_wrreq;
output [ 7: 0] control;
output [ 6: 0] controlbitsfifo_q;
output [ 31: 0] desc_address_fifo_data;
output desc_address_fifo_wrreq;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output generate_eop;
output [ 31: 0] next_desc;
output owned_by_hw;
output read_fixed_address;
output write_fixed_address;
input clk;
input command_fifo_full;
input controlbitsfifo_rdreq;
input desc_address_fifo_full;
input [ 31: 0] descriptor_pointer_lower_reg_out;
input [ 31: 0] descriptor_pointer_upper_reg_out;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input pollen_clear_run;
input reset;
input reset_n;
input run;
wire [ 3: 0] atlantic_channel;
wire [ 15: 0] bytes_to_transfer;
reg chain_run;
wire [103: 0] command_fifo_data;
reg command_fifo_wrreq;
wire command_fifo_wrreq_in;
wire [ 7: 0] control;
wire [ 6: 0] controlbitsfifo_data;
wire controlbitsfifo_empty;
wire controlbitsfifo_full;
wire [ 6: 0] controlbitsfifo_q;
wire controlbitsfifo_wrreq;
reg delayed_desc_reg_en;
reg delayed_run;
reg [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_wrreq;
reg [255: 0] desc_assembler;
reg desc_read_start;
reg [255: 0] desc_reg;
wire desc_reg_en;
reg [ 31: 0] descriptor_read_address;
reg descriptor_read_completed;
wire descriptor_read_completed_in;
reg descriptor_read_read;
wire fifos_not_full;
wire generate_eop;
wire got_one_descriptor;
wire [255: 0] init_descriptor;
wire [ 31: 0] next_desc;
wire owned_by_hw;
wire [255: 0] pollen_clear_run_desc;
reg [ 3: 0] posted_desc_counter;
reg posted_read_queued;
wire [ 31: 0] read_address;
wire [ 7: 0] read_burst;
wire read_fixed_address;
reg [ 3: 0] received_desc_counter;
reg run_rising_edge;
wire run_rising_edge_in;
reg started;
wire started_in;
wire [ 31: 0] write_address;
wire [ 7: 0] write_burst;
wire write_fixed_address;
//descriptor_read, which is an e_avalon_master
//Control assignments
assign command_fifo_wrreq_in = chain_run && fifos_not_full && delayed_desc_reg_en && owned_by_hw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_fifo_wrreq <= 0;
else
command_fifo_wrreq <= command_fifo_wrreq_in;
end
assign desc_address_fifo_wrreq = command_fifo_wrreq;
assign fifos_not_full = ~command_fifo_full && ~desc_address_fifo_full;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_desc_reg_en <= 0;
else
delayed_desc_reg_en <= desc_reg_en;
end
assign read_address = desc_reg[31 : 0];
assign write_address = desc_reg[95 : 64];
assign next_desc = desc_reg[159 : 128];
assign bytes_to_transfer = desc_reg[207 : 192];
assign read_burst = desc_reg[215 : 208];
assign write_burst = desc_reg[223 : 216];
assign control = desc_reg[255 : 248];
assign command_fifo_data = {control, write_burst, read_burst, bytes_to_transfer, write_address, read_address};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_address_fifo_data <= 0;
else if (desc_reg_en)
desc_address_fifo_data <= next_desc;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
received_desc_counter <= 0;
else
received_desc_counter <= (received_desc_counter == 8)? 0 : (descriptor_read_readdatavalid ? (received_desc_counter + 1) : received_desc_counter);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
posted_desc_counter <= 0;
else
posted_desc_counter <= (desc_read_start & owned_by_hw & (posted_desc_counter != 8)) ? 8 : ((|posted_desc_counter & ~descriptor_read_waitrequest & fifos_not_full) ? (posted_desc_counter - 1) : posted_desc_counter);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_read_start <= 0;
else if (~descriptor_read_waitrequest)
desc_read_start <= desc_read_start ? 0 : ((~(desc_reg_en | delayed_desc_reg_en | command_fifo_wrreq | |received_desc_counter)) ? (chain_run & fifos_not_full & ~|posted_desc_counter & ~posted_read_queued) : 0);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_run <= 0;
else
chain_run <= (run && owned_by_hw | (delayed_desc_reg_en | desc_reg_en) | |posted_desc_counter | |received_desc_counter) || run_rising_edge_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_read <= 0;
else if (~descriptor_read_waitrequest)
descriptor_read_read <= |posted_desc_counter & fifos_not_full;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_address <= 0;
else if (~descriptor_read_waitrequest)
descriptor_read_address <= (descriptor_read_read)? (descriptor_read_address + 4) : next_desc;
end
assign descriptor_read_completed_in = started ? (run && ~owned_by_hw && ~|posted_desc_counter) : descriptor_read_completed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
posted_read_queued <= 0;
else
posted_read_queued <= posted_read_queued ? ~(got_one_descriptor) : (descriptor_read_read);
end
//control bits
assign generate_eop = control[0];
assign read_fixed_address = control[1];
assign write_fixed_address = control[2];
assign atlantic_channel = control[6 : 3];
assign owned_by_hw = control[7];
assign got_one_descriptor = received_desc_counter == 8;
//read descriptor
assign desc_reg_en = chain_run && got_one_descriptor;
assign init_descriptor = {1'b1, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
//Clear owned_by_hw bit when run is clear in Descriptor Polling Mode
assign pollen_clear_run_desc = {1'b0, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_reg <= 0;
else if (desc_reg_en || run_rising_edge_in || pollen_clear_run)
desc_reg <= run_rising_edge_in ? init_descriptor : pollen_clear_run ? pollen_clear_run_desc: desc_assembler;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_assembler <= 0;
else if (descriptor_read_readdatavalid)
desc_assembler <= desc_assembler >> 32 | {descriptor_read_readdata, 224'b0};
end
//descriptor_read_completed register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_completed <= 0;
else
descriptor_read_completed <= descriptor_read_completed_in;
end
//started register
assign started_in = (run_rising_edge || run_rising_edge_in) ? 1'b1 : (descriptor_read_completed ? 1'b0 : started);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
started <= 0;
else
started <= started_in;
end
//delayed_run signal for the rising edge detector
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_run <= 0;
else
delayed_run <= run;
end
//Run rising edge detector
assign run_rising_edge_in = run & ~delayed_run;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
run_rising_edge <= 0;
else if (run_rising_edge_in || desc_reg_en)
run_rising_edge <= run_rising_edge_in;
end
//the_descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo, which is an e_instance
descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo the_descriptor_read_which_resides_within_sgdma_rx_control_bits_fifo
(
.clk (clk),
.controlbitsfifo_data (controlbitsfifo_data),
.controlbitsfifo_empty (controlbitsfifo_empty),
.controlbitsfifo_full (controlbitsfifo_full),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.controlbitsfifo_wrreq (controlbitsfifo_wrreq),
.reset (reset)
);
assign controlbitsfifo_data = control[6 : 0];
assign controlbitsfifo_wrreq = command_fifo_wrreq;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_write_which_resides_within_sgdma_rx (
// inputs:
clk,
controlbitsfifo_q,
desc_address_fifo_empty,
desc_address_fifo_q,
descriptor_write_waitrequest,
park,
reset_n,
status_token_fifo_data,
status_token_fifo_empty,
status_token_fifo_q,
// outputs:
atlantic_error,
controlbitsfifo_rdreq,
desc_address_fifo_rdreq,
descriptor_write_address,
descriptor_write_busy,
descriptor_write_write,
descriptor_write_writedata,
status_token_fifo_rdreq,
t_eop
)
;
output atlantic_error;
output controlbitsfifo_rdreq;
output desc_address_fifo_rdreq;
output [ 31: 0] descriptor_write_address;
output descriptor_write_busy;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output status_token_fifo_rdreq;
output t_eop;
input clk;
input [ 6: 0] controlbitsfifo_q;
input desc_address_fifo_empty;
input [ 31: 0] desc_address_fifo_q;
input descriptor_write_waitrequest;
input park;
input reset_n;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_empty;
input [ 23: 0] status_token_fifo_q;
wire atlantic_error;
wire can_write;
wire controlbitsfifo_rdreq;
wire desc_address_fifo_rdreq;
reg [ 31: 0] descriptor_write_address;
wire descriptor_write_busy;
reg descriptor_write_write;
reg descriptor_write_write0;
reg [ 31: 0] descriptor_write_writedata;
wire fifos_not_empty;
wire [ 7: 0] status_reg;
reg status_token_fifo_rdreq;
wire status_token_fifo_rdreq_in;
wire t_eop;
//descriptor_write, which is an e_avalon_master
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_writedata <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_writedata <= {park, controlbitsfifo_q, status_token_fifo_q};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_address <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_address <= desc_address_fifo_q + 28;
end
assign fifos_not_empty = ~status_token_fifo_empty && ~desc_address_fifo_empty;
assign can_write = ~descriptor_write_waitrequest && fifos_not_empty;
//write register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_write0 <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_write0 <= status_token_fifo_rdreq;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_write <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_write <= descriptor_write_write0;
end
//status_token_fifo_rdreq register
assign status_token_fifo_rdreq_in = status_token_fifo_rdreq ? 1'b0 : can_write;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_token_fifo_rdreq <= 0;
else
status_token_fifo_rdreq <= status_token_fifo_rdreq_in;
end
assign desc_address_fifo_rdreq = status_token_fifo_rdreq;
assign descriptor_write_busy = descriptor_write_write0 | descriptor_write_write;
assign status_reg = status_token_fifo_data[23 : 16];
assign t_eop = status_reg[7];
assign atlantic_error = status_reg[6] | status_reg[5] | status_reg[4] | status_reg[3] | status_reg[2] | status_reg[1] | status_reg[0];
assign controlbitsfifo_rdreq = status_token_fifo_rdreq;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_chain (
// inputs:
clk,
command_fifo_empty,
command_fifo_full,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
descriptor_write_waitrequest,
reset,
reset_n,
status_token_fifo_data,
status_token_fifo_empty,
status_token_fifo_q,
write_go,
// outputs:
command_fifo_data,
command_fifo_wrreq,
csr_irq,
csr_readdata,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
descriptor_read_address,
descriptor_read_read,
descriptor_write_address,
descriptor_write_write,
descriptor_write_writedata,
status_token_fifo_rdreq,
sw_reset
)
;
output [103: 0] command_fifo_data;
output command_fifo_wrreq;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] desc_address_fifo_data;
output desc_address_fifo_rdreq;
output desc_address_fifo_wrreq;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output [ 31: 0] descriptor_write_address;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output status_token_fifo_rdreq;
output sw_reset;
input clk;
input command_fifo_empty;
input command_fifo_full;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input desc_address_fifo_empty;
input desc_address_fifo_full;
input [ 31: 0] desc_address_fifo_q;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input descriptor_write_waitrequest;
input reset;
input reset_n;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_empty;
input [ 23: 0] status_token_fifo_q;
input write_go;
wire [ 3: 0] atlantic_channel;
wire atlantic_error;
wire chain_run;
wire [103: 0] command_fifo_data;
wire command_fifo_wrreq;
wire [ 7: 0] control;
wire [ 6: 0] controlbitsfifo_q;
wire controlbitsfifo_rdreq;
wire csr_irq;
wire [ 31: 0] csr_readdata;
wire [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_rdreq;
wire desc_address_fifo_wrreq;
wire [ 31: 0] descriptor_pointer_lower_reg_out;
wire [ 31: 0] descriptor_pointer_upper_reg_out;
wire [ 31: 0] descriptor_read_address;
wire descriptor_read_read;
wire [ 31: 0] descriptor_write_address;
wire descriptor_write_busy;
wire descriptor_write_write;
wire [ 31: 0] descriptor_write_writedata;
wire generate_eop;
wire [ 31: 0] next_desc;
wire owned_by_hw;
wire park;
wire pollen_clear_run;
wire read_fixed_address;
wire run;
wire status_token_fifo_rdreq;
wire sw_reset;
wire t_eop;
wire write_fixed_address;
control_status_slave_which_resides_within_sgdma_rx the_control_status_slave_which_resides_within_sgdma_rx
(
.atlantic_error (atlantic_error),
.chain_run (chain_run),
.clk (clk),
.command_fifo_empty (command_fifo_empty),
.csr_address (csr_address),
.csr_chipselect (csr_chipselect),
.csr_irq (csr_irq),
.csr_read (csr_read),
.csr_readdata (csr_readdata),
.csr_write (csr_write),
.csr_writedata (csr_writedata),
.desc_address_fifo_empty (desc_address_fifo_empty),
.descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
.descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_write_busy (descriptor_write_busy),
.descriptor_write_write (descriptor_write_write),
.owned_by_hw (owned_by_hw),
.park (park),
.pollen_clear_run (pollen_clear_run),
.reset_n (reset_n),
.run (run),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.sw_reset (sw_reset),
.t_eop (t_eop),
.write_go (write_go)
);
descriptor_read_which_resides_within_sgdma_rx the_descriptor_read_which_resides_within_sgdma_rx
(
.atlantic_channel (atlantic_channel),
.chain_run (chain_run),
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_full (command_fifo_full),
.command_fifo_wrreq (command_fifo_wrreq),
.control (control),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
.descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_read_readdata (descriptor_read_readdata),
.descriptor_read_readdatavalid (descriptor_read_readdatavalid),
.descriptor_read_waitrequest (descriptor_read_waitrequest),
.generate_eop (generate_eop),
.next_desc (next_desc),
.owned_by_hw (owned_by_hw),
.pollen_clear_run (pollen_clear_run),
.read_fixed_address (read_fixed_address),
.reset (reset),
.reset_n (reset_n),
.run (run),
.write_fixed_address (write_fixed_address)
);
descriptor_write_which_resides_within_sgdma_rx the_descriptor_write_which_resides_within_sgdma_rx
(
.atlantic_error (atlantic_error),
.clk (clk),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.descriptor_write_address (descriptor_write_address),
.descriptor_write_busy (descriptor_write_busy),
.descriptor_write_waitrequest (descriptor_write_waitrequest),
.descriptor_write_write (descriptor_write_write),
.descriptor_write_writedata (descriptor_write_writedata),
.park (park),
.reset_n (reset_n),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.t_eop (t_eop)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_command_grabber (
// inputs:
clk,
command_fifo_empty,
command_fifo_q,
m_write_waitrequest,
reset_n,
write_go,
// outputs:
command_fifo_rdreq,
generate_eop,
write_command_data,
write_command_valid
)
;
output command_fifo_rdreq;
output generate_eop;
output [ 56: 0] write_command_data;
output write_command_valid;
input clk;
input command_fifo_empty;
input [103: 0] command_fifo_q;
input m_write_waitrequest;
input reset_n;
input write_go;
wire [ 3: 0] atlantic_channel;
wire [ 15: 0] bytes_to_transfer;
wire command_fifo_rdreq;
wire command_fifo_rdreq_in;
reg command_fifo_rdreq_reg;
reg command_valid;
wire [ 7: 0] control;
reg delay1_command_valid;
wire generate_eop;
wire [ 31: 0] read_address;
wire [ 7: 0] read_burst;
wire read_fixed_address;
wire [ 31: 0] write_address;
wire [ 7: 0] write_burst;
reg [ 56: 0] write_command_data;
wire write_command_valid;
wire write_fixed_address;
//Descriptor components
assign read_address = command_fifo_q[31 : 0];
assign write_address = command_fifo_q[63 : 32];
assign bytes_to_transfer = command_fifo_q[79 : 64];
assign read_burst = command_fifo_q[87 : 80];
assign write_burst = command_fifo_q[95 : 88];
assign control = command_fifo_q[103 : 96];
//control bits
assign generate_eop = control[0];
assign read_fixed_address = control[1];
assign write_fixed_address = control[2];
assign atlantic_channel = control[6 : 3];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_command_data <= 0;
else
write_command_data <= {~write_fixed_address, write_burst, bytes_to_transfer, write_address};
end
assign write_command_valid = command_valid;
//command_fifo_rdreq register
assign command_fifo_rdreq_in = (command_fifo_rdreq_reg || command_valid) ? 1'b0 : (~write_go && ~m_write_waitrequest);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_fifo_rdreq_reg <= 0;
else if (~command_fifo_empty)
command_fifo_rdreq_reg <= command_fifo_rdreq_in;
end
assign command_fifo_rdreq = command_fifo_rdreq_reg;
//command_valid register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delay1_command_valid <= 0;
else
delay1_command_valid <= command_fifo_rdreq_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_valid <= 0;
else
command_valid <= delay1_command_valid;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sixteen_bit_byteenable_FSM_which_resides_within_sgdma_rx (
// inputs:
byteenable_in,
clk,
reset_n,
waitrequest_in,
write_in,
// outputs:
byteenable_out,
waitrequest_out
)
;
output [ 1: 0] byteenable_out;
output waitrequest_out;
input [ 1: 0] byteenable_in;
input clk;
input reset_n;
input waitrequest_in;
input write_in;
wire [ 1: 0] byteenable_out;
wire waitrequest_out;
assign byteenable_out = byteenable_in & {2{write_in}};
assign waitrequest_out = waitrequest_in | ((write_in == 1) & (waitrequest_in == 1));
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module thirty_two_bit_byteenable_FSM_which_resides_within_sgdma_rx (
// inputs:
byteenable_in,
clk,
reset_n,
waitrequest_in,
write_in,
// outputs:
byteenable_out,
waitrequest_out
)
;
output [ 3: 0] byteenable_out;
output waitrequest_out;
input [ 3: 0] byteenable_in;
input clk;
input reset_n;
input waitrequest_in;
input write_in;
wire advance_to_next_state;
wire [ 3: 0] byteenable_out;
wire full_lower_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
wire lower_enable;
wire lower_stall;
wire partial_lower_half_transfer;
wire partial_upper_half_transfer;
reg state_bit;
wire transfer_done;
wire two_stage_transfer;
wire upper_enable;
wire upper_stall;
wire waitrequest_out;
assign partial_lower_half_transfer = byteenable_in[1 : 0] != 0;
assign full_lower_half_transfer = byteenable_in[1 : 0] == {2 {1'b1}};
assign partial_upper_half_transfer = byteenable_in[3 : 2] != 0;
assign full_upper_half_transfer = byteenable_in[3 : 2] == {2 {1'b1}};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state_bit <= 0;
else if (transfer_done == 1)
state_bit <= 0;
else if (advance_to_next_state == 1)
state_bit <= 1;
end
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) |
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) |
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) |
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) |
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));
//lower_sixteen_bit_byteenable_FSM, which is an e_instance
sixteen_bit_byteenable_FSM_which_resides_within_sgdma_rx lower_sixteen_bit_byteenable_FSM
(
.byteenable_in (byteenable_in[1 : 0]),
.byteenable_out (byteenable_out[1 : 0]),
.clk (clk),
.reset_n (reset_n),
.waitrequest_in (waitrequest_in),
.waitrequest_out (lower_stall),
.write_in (lower_enable)
);
//upper_sixteen_bit_byteenable_FSM, which is an e_instance
sixteen_bit_byteenable_FSM_which_resides_within_sgdma_rx upper_sixteen_bit_byteenable_FSM
(
.byteenable_in (byteenable_in[3 : 2]),
.byteenable_out (byteenable_out[3 : 2]),
.clk (clk),
.reset_n (reset_n),
.waitrequest_in (waitrequest_in),
.waitrequest_out (upper_stall),
.write_in (upper_enable)
);
assign waitrequest_out = waitrequest_in | ((transfer_done == 0) & (write_in == 1));
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module byteenable_gen_which_resides_within_sgdma_rx (
// inputs:
byteenable_in,
clk,
reset_n,
waitrequest_in,
write_in,
// outputs:
byteenable_out,
waitrequest_out
)
;
output [ 3: 0] byteenable_out;
output waitrequest_out;
input [ 3: 0] byteenable_in;
input clk;
input reset_n;
input waitrequest_in;
input write_in;
wire [ 3: 0] byteenable_out;
wire waitrequest_out;
//the_thirty_two_bit_byteenable_FSM, which is an e_instance
thirty_two_bit_byteenable_FSM_which_resides_within_sgdma_rx the_thirty_two_bit_byteenable_FSM
(
.byteenable_in (byteenable_in),
.byteenable_out (byteenable_out),
.clk (clk),
.reset_n (reset_n),
.waitrequest_in (waitrequest_in),
.waitrequest_out (waitrequest_out),
.write_in (write_in)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_m_write (
// inputs:
clk,
enough_data,
eop_found,
m_write_waitrequest,
reset_n,
sink_stream_data,
sink_stream_empty,
sink_stream_endofpacket,
sink_stream_error,
sink_stream_startofpacket,
sink_stream_valid,
status_token_fifo_full,
write_command_data,
write_command_valid,
// outputs:
m_write_address,
m_write_byteenable,
m_write_write,
m_write_writedata,
sink_stream_ready,
status_token_fifo_data,
status_token_fifo_wrreq,
write_go
)
;
output [ 31: 0] m_write_address;
output [ 3: 0] m_write_byteenable;
output m_write_write;
output [ 31: 0] m_write_writedata;
output sink_stream_ready;
output [ 23: 0] status_token_fifo_data;
output status_token_fifo_wrreq;
output write_go;
input clk;
input enough_data;
input eop_found;
input m_write_waitrequest;
input reset_n;
input [ 31: 0] sink_stream_data;
input [ 1: 0] sink_stream_empty;
input sink_stream_endofpacket;
input [ 5: 0] sink_stream_error;
input sink_stream_startofpacket;
input sink_stream_valid;
input status_token_fifo_full;
input [ 56: 0] write_command_data;
input write_command_valid;
wire [ 15: 0] actual_bytes_transferred;
wire [ 3: 0] all_one;
reg [ 3: 0] burst_counter;
wire burst_counter_decrement;
wire [ 3: 0] burst_counter_next;
reg [ 3: 0] burst_counter_reg;
wire [ 3: 0] burst_size;
reg byteenable_enable;
wire [ 15: 0] bytes_to_transfer;
reg [ 15: 0] counter;
wire [ 15: 0] counter_in;
reg delayed_write_command_valid;
reg delayed_write_go;
wire e_00;
wire e_01;
wire e_02;
wire e_03;
wire e_04;
wire e_05;
wire e_06;
reg eop_found_hold;
reg eop_reg;
wire increment;
wire increment_address;
reg [ 31: 0] m_write_address;
wire [ 3: 0] m_write_byteenable;
wire [ 3: 0] m_write_byteenable_in;
reg [ 3: 0] m_write_byteenable_reg;
wire m_write_waitrequest_out;
reg m_write_write;
reg m_write_write_sig;
wire [ 31: 0] m_write_writedata;
reg [ 31: 0] m_write_writedata_reg;
wire m_writefifo_fill;
wire [ 3: 0] shift0;
wire [ 3: 0] shift1;
wire [ 3: 0] shift2;
wire [ 3: 0] shift3;
wire single_transfer;
wire [ 3: 0] sink_stream_empty_shift;
wire sink_stream_ready;
wire sink_stream_really_valid;
wire [ 31: 0] start_address;
reg [ 7: 0] status_reg;
wire [ 7: 0] status_reg_in;
wire [ 23: 0] status_token_fifo_data;
wire status_token_fifo_wrreq;
wire [ 7: 0] status_word;
wire t_eop;
reg [ 56: 0] write_command_data_reg;
wire write_go;
reg write_go_fall_reg;
wire write_go_fall_reg_in;
reg write_go_reg;
wire write_go_reg_in;
wire write_go_reg_in_teop;
//m_write, which is an e_avalon_master
assign burst_size = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_write <= 0;
else if (~m_write_waitrequest_out)
m_write_write <= write_go_reg & (sink_stream_really_valid | m_write_write_sig);
end
assign m_writefifo_fill = 1;
//command input
assign start_address = write_command_data_reg[31 : 0];
assign bytes_to_transfer = write_command_data_reg[47 : 32];
assign increment_address = write_command_data_reg[56];
//increment or keep constant, the m_write_address depending on the command bit
assign m_write_writedata = m_write_writedata_reg;
assign increment = write_go_reg & sink_stream_really_valid;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_writedata_reg <= 0;
else if (~m_write_waitrequest_out)
m_write_writedata_reg <= sink_stream_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_write_sig <= 0;
else if (m_write_waitrequest_out)
m_write_write_sig <= sink_stream_really_valid & ~m_write_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_address <= 0;
else if (~m_write_waitrequest_out)
m_write_address <= delayed_write_command_valid ? start_address : (increment_address ? (m_write_write ? (m_write_address + 4) : m_write_address) : start_address);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_found_hold <= 0;
else if (write_go_reg)
eop_found_hold <= eop_found_hold ? ~(sink_stream_endofpacket & sink_stream_really_valid) : eop_found;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
burst_counter_reg <= 0;
else if (~m_write_waitrequest_out)
burst_counter_reg <= burst_counter;
end
assign burst_counter_decrement = |burst_counter & write_go_reg & sink_stream_really_valid;
assign burst_counter_next = burst_counter - 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
burst_counter <= 0;
else if (~|burst_counter & ~|burst_counter_reg & write_go_reg)
begin
if (enough_data)
burst_counter <= burst_size;
else if (eop_found_hold)
burst_counter <= m_writefifo_fill;
end
else if (~m_write_waitrequest_out)
if (burst_counter_decrement)
burst_counter <= burst_counter_next;
end
assign shift3 = {3'b0, all_one[0]};
assign shift2 = {2'b0, all_one[1 : 0]};
assign shift1 = {1'b0, all_one[2 : 0]};
assign shift0 = all_one;
assign sink_stream_empty_shift = ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_byteenable_reg <= 0;
else if (~m_write_waitrequest_out)
m_write_byteenable_reg <= ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
end
assign all_one = 4'b1111;
assign m_write_byteenable_in = byteenable_enable ? m_write_byteenable_reg : all_one;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
byteenable_enable <= 0;
else if (~m_write_waitrequest_out)
byteenable_enable <= sink_stream_endofpacket;
end
assign sink_stream_ready = write_go_reg & ~m_write_waitrequest_out & ~eop_reg & (|bytes_to_transfer ? ~(counter >= bytes_to_transfer) : 1);
//sink_stream_ready_sig
//sink_stream_valid is only really valid when we're ready
assign sink_stream_really_valid = sink_stream_valid && sink_stream_ready;
//write_command_data_reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_command_data_reg <= 0;
else if (write_command_valid)
write_command_data_reg <= write_command_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_write_command_valid <= 0;
else
delayed_write_command_valid <= write_command_valid;
end
//8-bits up-counter
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter <= 0;
else if (~m_write_waitrequest_out)
counter <= counter_in;
end
//write_go bit for all of this operation until count is up
assign write_go_reg_in = (delayed_write_command_valid) ? 1'b1 : (counter >= bytes_to_transfer) ? 1'b0 : write_go_reg;
assign write_go_reg_in_teop = eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : 1'b1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_reg <= 0;
else
eop_reg <= eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : sink_stream_endofpacket & sink_stream_really_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_go_reg <= 0;
else if (~m_write_waitrequest_out)
write_go_reg <= (write_go_reg && (bytes_to_transfer == 0)) ? write_go_reg_in_teop : write_go_reg_in;
end
assign write_go = write_go_reg;
assign t_eop = (sink_stream_endofpacket && sink_stream_really_valid) && (bytes_to_transfer == 0);
assign single_transfer = sink_stream_startofpacket & sink_stream_endofpacket;
assign counter_in = (delayed_write_command_valid) ? 16'b0 : (increment ? (counter + 4 - (sink_stream_endofpacket ? sink_stream_empty : 0)) : counter);
//status register
assign status_reg_in = write_go_fall_reg ? 0 : (status_word | status_reg);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_reg <= 0;
else
status_reg <= status_reg_in;
end
//actual_bytes_transferred register
assign actual_bytes_transferred = counter;
//status_token consists of the status signals and actual_bytes_transferred
assign status_token_fifo_data = {status_reg, actual_bytes_transferred};
assign status_word = {t_eop, e_06, e_05, e_04, e_03, e_02, e_01, e_00};
assign e_00 = sink_stream_error[0];
assign e_01 = sink_stream_error[1];
assign e_02 = sink_stream_error[2];
assign e_03 = sink_stream_error[3];
assign e_04 = sink_stream_error[4];
assign e_05 = sink_stream_error[5];
assign e_06 = 1'b0;
//delayed write go register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_write_go <= 0;
else
delayed_write_go <= write_go_reg;
end
//write_go falling edge detector
assign write_go_fall_reg_in = delayed_write_go && ~write_go_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_go_fall_reg <= 0;
else
write_go_fall_reg <= write_go_fall_reg_in;
end
assign status_token_fifo_wrreq = write_go_fall_reg && ~status_token_fifo_full;
byteenable_gen_which_resides_within_sgdma_rx the_byteenable_gen_which_resides_within_sgdma_rx
(
.byteenable_in (m_write_byteenable_in),
.byteenable_out (m_write_byteenable),
.clk (clk),
.reset_n (reset_n),
.waitrequest_in (m_write_waitrequest),
.waitrequest_out (m_write_waitrequest_out),
.write_in (m_write_write)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
)
;
output command_fifo_empty;
output command_fifo_full;
output [103: 0] command_fifo_q;
input clk;
input [103: 0] command_fifo_data;
input command_fifo_rdreq;
input command_fifo_wrreq;
input reset;
wire command_fifo_empty;
wire command_fifo_full;
wire [103: 0] command_fifo_q;
scfifo sgdma_rx_command_fifo_command_fifo
(
.aclr (reset),
.clock (clk),
.data (command_fifo_data),
.empty (command_fifo_empty),
.full (command_fifo_full),
.q (command_fifo_q),
.rdreq (command_fifo_rdreq),
.wrreq (command_fifo_wrreq)
);
defparam sgdma_rx_command_fifo_command_fifo.add_ram_output_register = "ON",
sgdma_rx_command_fifo_command_fifo.intended_device_family = "STRATIXIV",
sgdma_rx_command_fifo_command_fifo.lpm_numwords = 2,
sgdma_rx_command_fifo_command_fifo.lpm_showahead = "OFF",
sgdma_rx_command_fifo_command_fifo.lpm_type = "scfifo",
sgdma_rx_command_fifo_command_fifo.lpm_width = 104,
sgdma_rx_command_fifo_command_fifo.lpm_widthu = 1,
sgdma_rx_command_fifo_command_fifo.overflow_checking = "ON",
sgdma_rx_command_fifo_command_fifo.underflow_checking = "ON",
sgdma_rx_command_fifo_command_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
)
;
output desc_address_fifo_empty;
output desc_address_fifo_full;
output [ 31: 0] desc_address_fifo_q;
input clk;
input [ 31: 0] desc_address_fifo_data;
input desc_address_fifo_rdreq;
input desc_address_fifo_wrreq;
input reset;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [ 31: 0] desc_address_fifo_q;
scfifo sgdma_rx_desc_address_fifo_desc_address_fifo
(
.aclr (reset),
.clock (clk),
.data (desc_address_fifo_data),
.empty (desc_address_fifo_empty),
.full (desc_address_fifo_full),
.q (desc_address_fifo_q),
.rdreq (desc_address_fifo_rdreq),
.wrreq (desc_address_fifo_wrreq)
);
defparam sgdma_rx_desc_address_fifo_desc_address_fifo.add_ram_output_register = "ON",
sgdma_rx_desc_address_fifo_desc_address_fifo.intended_device_family = "STRATIXIV",
sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_width = 32,
sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
sgdma_rx_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
sgdma_rx_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
sgdma_rx_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
)
;
output status_token_fifo_empty;
output status_token_fifo_full;
output [ 23: 0] status_token_fifo_q;
input clk;
input reset;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_rdreq;
input status_token_fifo_wrreq;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [ 23: 0] status_token_fifo_q;
scfifo sgdma_rx_status_token_fifo_status_token_fifo
(
.aclr (reset),
.clock (clk),
.data (status_token_fifo_data),
.empty (status_token_fifo_empty),
.full (status_token_fifo_full),
.q (status_token_fifo_q),
.rdreq (status_token_fifo_rdreq),
.wrreq (status_token_fifo_wrreq)
);
defparam sgdma_rx_status_token_fifo_status_token_fifo.add_ram_output_register = "ON",
sgdma_rx_status_token_fifo_status_token_fifo.intended_device_family = "STRATIXIV",
sgdma_rx_status_token_fifo_status_token_fifo.lpm_numwords = 2,
sgdma_rx_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
sgdma_rx_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
sgdma_rx_status_token_fifo_status_token_fifo.lpm_width = 24,
sgdma_rx_status_token_fifo_status_token_fifo.lpm_widthu = 1,
sgdma_rx_status_token_fifo_status_token_fifo.overflow_checking = "ON",
sgdma_rx_status_token_fifo_status_token_fifo.underflow_checking = "ON",
sgdma_rx_status_token_fifo_status_token_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sgdma_rx (
// inputs:
clk,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
descriptor_write_waitrequest,
in_data,
in_empty,
in_endofpacket,
in_error,
in_startofpacket,
in_valid,
m_write_waitrequest,
system_reset_n,
// outputs:
csr_irq,
csr_readdata,
descriptor_read_address,
descriptor_read_read,
descriptor_write_address,
descriptor_write_write,
descriptor_write_writedata,
in_ready,
m_write_address,
m_write_byteenable,
m_write_write,
m_write_writedata
)
;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output [ 31: 0] descriptor_write_address;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output in_ready;
output [ 31: 0] m_write_address;
output [ 3: 0] m_write_byteenable;
output m_write_write;
output [ 31: 0] m_write_writedata;
input clk;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input descriptor_write_waitrequest;
input [ 31: 0] in_data;
input [ 1: 0] in_empty;
input in_endofpacket;
input [ 5: 0] in_error;
input in_startofpacket;
input in_valid;
input m_write_waitrequest;
input system_reset_n;
wire [103: 0] command_fifo_data;
wire command_fifo_empty;
wire command_fifo_full;
wire [103: 0] command_fifo_q;
wire command_fifo_rdreq;
wire command_fifo_wrreq;
wire csr_irq;
wire [ 31: 0] csr_readdata;
wire [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [ 31: 0] desc_address_fifo_q;
wire desc_address_fifo_rdreq;
wire desc_address_fifo_wrreq;
wire [ 31: 0] descriptor_read_address;
wire descriptor_read_read;
wire [ 31: 0] descriptor_write_address;
wire descriptor_write_write;
wire [ 31: 0] descriptor_write_writedata;
wire generate_eop;
wire in_ready;
wire [ 31: 0] m_write_address;
wire [ 3: 0] m_write_byteenable;
wire m_write_write;
wire [ 31: 0] m_write_writedata;
wire reset;
reg reset_n;
wire [ 31: 0] sink_stream_data;
wire [ 1: 0] sink_stream_empty;
wire sink_stream_endofpacket;
wire [ 5: 0] sink_stream_error;
wire sink_stream_ready;
wire sink_stream_startofpacket;
wire sink_stream_valid;
wire [ 23: 0] status_token_fifo_data;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [ 23: 0] status_token_fifo_q;
wire status_token_fifo_rdreq;
wire status_token_fifo_wrreq;
wire sw_reset;
reg sw_reset_d1;
reg sw_reset_request;
wire [ 56: 0] write_command_data;
wire write_command_valid;
wire write_go;
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
reset_n <= 0;
else
reset_n <= ~(~system_reset_n | sw_reset_request);
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
sw_reset_d1 <= 0;
else if (sw_reset | sw_reset_request)
sw_reset_d1 <= sw_reset & ~sw_reset_request;
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
sw_reset_request <= 0;
else if (sw_reset | sw_reset_request)
sw_reset_request <= sw_reset_d1 & ~sw_reset_request;
end
assign reset = ~reset_n;
sgdma_rx_chain the_sgdma_rx_chain
(
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_empty (command_fifo_empty),
.command_fifo_full (command_fifo_full),
.command_fifo_wrreq (command_fifo_wrreq),
.csr_address (csr_address),
.csr_chipselect (csr_chipselect),
.csr_irq (csr_irq),
.csr_read (csr_read),
.csr_readdata (csr_readdata),
.csr_write (csr_write),
.csr_writedata (csr_writedata),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_read_readdata (descriptor_read_readdata),
.descriptor_read_readdatavalid (descriptor_read_readdatavalid),
.descriptor_read_waitrequest (descriptor_read_waitrequest & descriptor_read_read),
.descriptor_write_address (descriptor_write_address),
.descriptor_write_waitrequest (descriptor_write_waitrequest & descriptor_write_write),
.descriptor_write_write (descriptor_write_write),
.descriptor_write_writedata (descriptor_write_writedata),
.reset (reset),
.reset_n (reset_n),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.sw_reset (sw_reset),
.write_go (write_go)
);
sgdma_rx_command_grabber the_sgdma_rx_command_grabber
(
.clk (clk),
.command_fifo_empty (command_fifo_empty),
.command_fifo_q (command_fifo_q),
.command_fifo_rdreq (command_fifo_rdreq),
.generate_eop (generate_eop),
.m_write_waitrequest (m_write_waitrequest & m_write_write),
.reset_n (reset_n),
.write_command_data (write_command_data),
.write_command_valid (write_command_valid),
.write_go (write_go)
);
sgdma_rx_m_write the_sgdma_rx_m_write
(
.clk (clk),
.enough_data (1'b1),
.eop_found (1'b0),
.m_write_address (m_write_address),
.m_write_byteenable (m_write_byteenable),
.m_write_waitrequest (m_write_waitrequest & m_write_write),
.m_write_write (m_write_write),
.m_write_writedata (m_write_writedata),
.reset_n (reset_n),
.sink_stream_data (sink_stream_data),
.sink_stream_empty (sink_stream_empty),
.sink_stream_endofpacket (sink_stream_endofpacket),
.sink_stream_error (sink_stream_error),
.sink_stream_ready (sink_stream_ready),
.sink_stream_startofpacket (sink_stream_startofpacket),
.sink_stream_valid (sink_stream_valid),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_full (status_token_fifo_full),
.status_token_fifo_wrreq (status_token_fifo_wrreq),
.write_command_data (write_command_data),
.write_command_valid (write_command_valid),
.write_go (write_go)
);
//the_sgdma_rx_command_fifo, which is an e_instance
sgdma_rx_command_fifo the_sgdma_rx_command_fifo
(
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_empty (command_fifo_empty),
.command_fifo_full (command_fifo_full),
.command_fifo_q (command_fifo_q),
.command_fifo_rdreq (command_fifo_rdreq),
.command_fifo_wrreq (command_fifo_wrreq),
.reset (reset)
);
//the_sgdma_rx_desc_address_fifo, which is an e_instance
sgdma_rx_desc_address_fifo the_sgdma_rx_desc_address_fifo
(
.clk (clk),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.reset (reset)
);
//the_sgdma_rx_status_token_fifo, which is an e_instance
sgdma_rx_status_token_fifo the_sgdma_rx_status_token_fifo
(
.clk (clk),
.reset (reset),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_full (status_token_fifo_full),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.status_token_fifo_wrreq (status_token_fifo_wrreq)
);
//descriptor_read, which is an e_avalon_master
//descriptor_write, which is an e_avalon_master
//csr, which is an e_avalon_slave
//m_write, which is an e_avalon_master
assign sink_stream_empty = in_empty;
assign sink_stream_error = sink_stream_valid ? in_error : 0;
//in, which is an e_atlantic_slave
assign sink_stream_endofpacket = in_endofpacket;
assign sink_stream_startofpacket = in_startofpacket;
assign sink_stream_valid = in_valid;
assign in_ready = sink_stream_ready;
assign sink_stream_data = {in_data[7 : 0], in_data[15 : 8], in_data[23 : 16], in_data[31 : 24]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_pad_up.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS2 PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos2_pad_up(oe ,data ,to_core ,pad ,por_l, vddo );
output to_core ;
input oe ;
input data ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire rcvr_data ;
wire por ;
wire pad_up ;
wire net58 ;
wire net59 ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (vss ),
.bsr_up (net58 ),
.bsr_dn_l (net59 ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (vss ),
.bsr_mode (vss ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (vss ),
.bsr_up (vss ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (vss ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
bw_io_cmos2_term_up I18 (
.vddo (vddo ),
.out (pad ) );
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description: AXI Master
*
* Changes:
* 10/2/2016: Initial Commit
*/
`timescale 1 ns/1 ps
`include "axi_defines.v"
`define BIT_STATUS_BUSY 0
`define BIT_STATUS_BAD_COMMAND 4
`define BIT_STATUS_BAD_TXRX_WIDTH 5
`define BIT_BUS_STATUS_RANGE 9:8
module axi_lite_master #(
//Parameters
parameter INVERT_AXI_RESET = 1,
parameter ADDR_WIDTH = 32,
parameter INTERRUPT_WIDTH = 32,
parameter DEFAULT_TIMEOUT = 32'd100000000 //1 Second at 100MHz
)(
//************* User Facing Side *******************************************
//User Facing Interface end
//indicate to the input that we are ready
output [31:0] o_cmd_status,
output reg o_cmd_interrupt,
input i_cmd_en,
output reg o_cmd_error,
output reg o_cmd_ack,
//Modifier flags, these will be used to change the way address are modified when reading/writing
input [ADDR_WIDTH - 1:0] i_cmd_addr,
input i_cmd_wr_rd, //1 = Write, 0 = Read
input [3:0] i_cmd_byte_en,
input [31:0] i_cmd_data,
output reg [31:0] o_cmd_data,
//***************** AXI Bus ************************************************
input clk,
input rst,
//bus write addr path
output [3:0] o_awid, //Write ID
output [ADDR_WIDTH - 1:0] o_awaddr, //Write Addr Path Address
output [2:0] o_awsize, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output reg o_awvalid, //Write Addr Path Address Valid
input i_awready, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] o_wid, //Write ID
output reg [31:0] o_wdata, //Write Data (this size is set with the 32 Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output reg [3:0] o_wstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
output o_wlast, //Write Last transfer in a write burst
output reg o_wvalid, //Data through this bus is valid
input i_wready, //Slave is ready for data
//Write Response Channel
input [3:0] i_bid, //Response ID (this must match awid)
input [1:0] i_bresp, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input i_bvalid, //Write Response is:
// 1 = Available
// 0 = Not Available
output reg o_bready, //WBM Ready
//bus read addr path
output [3:0] o_arid, //Read ID
output [ADDR_WIDTH - 1:0] o_araddr, //Read Addr Path Address
output reg [7:0] o_arlen, //Read Addr Path Burst Length
output [2:0] o_arsize, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output reg o_arvalid, //Read Addr Path Address Valid
input i_arready, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] i_rid, //Write ID
input [31: 0] i_rdata, //Read Data (this size is set with the 32 Parameter)
input [1:0] i_rresp, //Read Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input [3:0] i_rstrobe, //Read Strobe (a 1 in the write is associated with the byte to write)
input i_rlast, //Read Last transfer in a write burst
input i_rvalid, //Data through this bus is valid
output reg o_rready, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//local parameters
//States
localparam IDLE = 4'h0;
localparam WRITE_CMD = 4'h1; //Write Command and Address to Slave
localparam WRITE_DATA = 4'h2; //Write Data to Slave
localparam WRITE_RESP = 4'h3; //Receive Response from device
localparam READ_CMD = 4'h4; //Send Read Command and Address to Slave
localparam READ_DATA = 4'h5; //Receive Read Response from Slave (including data)
localparam READ_RESP = 4'h6;
localparam COMMAND_FINISHED = 4'h7;
localparam SEND_RESPONSE = 4'h8;
localparam SEND_INTERRUPT = 5'h9;
//registes/wires
reg [3:0] state = IDLE;
wire [15:0] w_flags;
wire [31:0] w_data_size;
reg [ADDR_WIDTH - 1:0] r_address;
reg [31:0] r_output_data;
wire [31:0] w_status;
reg [31:0] r_data_count; //Techinically this should go all the way up to DATA_COUNT - 1: 0
reg [31:0] r_interrupts;
wire w_writing_data;
reg [1:0] r_bus_status;
wire w_rst;
reg [INTERRUPT_WIDTH - 1:0] r_prev_int;
reg r_bad_command = 0;
reg r_bad_txrx_width;
reg [31:0] r_nack_timeout;
//Some Features are not supported at this time
assign o_cmd_status[`BIT_STATUS_BUSY] = (state != IDLE);
assign o_cmd_status[3:1] = 0;
assign o_cmd_status[`BIT_STATUS_BAD_COMMAND] = r_bad_command;
assign o_cmd_status[`BIT_STATUS_BAD_TXRX_WIDTH] = r_bad_txrx_width;
assign o_cmd_status[7:6] = 0;
assign o_cmd_status[`BIT_BUS_STATUS_RANGE] = r_bus_status;
assign o_cmd_status[9:8] = 0;
assign o_cmd_status[31:6] = 0;
assign o_awsize = `AXI_BURST_SIZE_32BIT;
assign o_arsize = `AXI_BURST_SIZE_32BIT;
//Submodules
//asynchronous logic
assign w_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign o_awaddr = r_address;
assign o_araddr = r_address;
assign o_wlast = 1'b1;
assign o_arid = 4'h0;
assign o_awid = 4'h0;
assign o_wid = 4'h0;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
//AXI Strobes
o_awvalid <= 0;
o_bready <= 0;
o_arvalid <= 0;
if (w_rst) begin
o_cmd_error <= 0;
r_output_data <= 0;
r_bad_command <= 0;
r_bad_txrx_width <= 0;
r_address <= 0;
r_data_count <= 32'h0;
r_nack_timeout <= DEFAULT_TIMEOUT;
r_prev_int <= 0;
//AXI
//Write Address Path
//Write Data Path
//Read Address Path
o_arlen <= 0;
r_bus_status <= 0;
o_cmd_ack <= 0;
o_cmd_interrupt <= 0;
o_wstrobe <= 0;
o_cmd_data <= 0;
o_wvalid <= 0;
o_rready <= 0;
o_wdata <= 0;
end
else begin
case (state)
IDLE: begin
r_bad_command <= 0;
r_bad_txrx_width <= 0;
o_rready <= 0;
o_wvalid <= 0;
r_address <= 32'h0;
r_data_count <= 32'h0;
o_wdata <= i_cmd_data;
o_wstrobe <= i_cmd_byte_en;
//Strobe in a command
if (i_cmd_en) begin
o_arlen <= 1;
r_bus_status <= 0;
//Something new from host
r_data_count <= 0;
r_address <= i_cmd_addr;
if (i_cmd_wr_rd) begin
//Write Path
state <= WRITE_CMD;
end
else begin
//Read Path
state <= READ_CMD;
end
end
else if (((!r_prev_int) & i_interrupts) > 0) begin
//Something new from interrupts
state <= SEND_INTERRUPT;
r_interrupts <= 0;
end
end
//Write Path
WRITE_CMD: begin
//Wait for the slave to acknowledge my request to write data to the specified address
o_awvalid <= 1;
if (i_awready && o_awvalid) begin
o_awvalid <= 0;
state <= WRITE_DATA;
end
end
WRITE_DATA: begin
o_wvalid <= 1;
if (i_wready && o_wvalid) begin
o_wvalid <= 0;
state <= WRITE_RESP;
end
end
WRITE_RESP: begin
o_bready <= 1;
if (i_bvalid)begin
//Incomming ID matches the one we sent out
r_bus_status <= i_bresp;
if (r_bus_status != 0) begin
o_cmd_error <= 1;
end
state <= COMMAND_FINISHED;
end
end
//Read Path
READ_CMD: begin
o_arvalid <= 1;
if (i_arready && o_arvalid) begin
o_arvalid <= 0;
state <= READ_DATA;
end
end
READ_DATA: begin
o_rready <= 1;
if (i_rvalid && o_rready) begin
o_rready <= 0;
o_cmd_data <= i_rdata;
r_bus_status <= i_rresp;
state <= COMMAND_FINISHED;
end
end
COMMAND_FINISHED: begin
o_cmd_ack <= 1;
if (!i_cmd_en && o_cmd_ack) begin
state <= IDLE;
end
end
SEND_INTERRUPT: begin
end
default: begin
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_SYMBOL_V
`define SKY130_FD_SC_MS__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_SYMBOL_V
|
// This module uses the synthesizable bsg_fsb_node_trace_replay module
// to communicate over bsg_tag. This module instantitates a trace-replay,
// removes the output data to match what bsg_tag is expecting, and
// finally it serializes the trace data down to a single bit.
//
// Each trace should be in the following format:
//
// M = number of masters
// N = clog2( #_of_tag_clients ) )
// D = max( client_1_width, client_2_width, ..., client_n_width )
// L = clog2( D + 1 ) )
//
// |< 4-bits >|< M-bits >|< N-bits >|< 1-bit >|< L-bits >|< D-bits >|
// +----------------+----------+----------+----------------+----------+----------+
// | replay command | masterEn | nodeID | data_not_reset | length | data |
// +----------------+----------+----------+----------------+----------+----------+
//
// Replay Commands
// 0 = 0000 = Wait a cycle
// 1 = 0001 = Send data
// 2 = 0010 = Receive data
// 3 = 0011 = Assert done_o ouput signal
// 4 = 0100 = End test (calls $finish)
// 5 = 0101 = Wait for cycle_counter == 0
// 6 = 0110 = Initialize cycle_counter with a 16 bit number
//
// To reset the bsg_tag_master, we just need to send a bunch of 0's,
// so we can send a trace of all 0's and just wait for many cycles. This
// will continuously send 0's down bsg_tag thus reseting the master.
//
// To reset a client, set the nodeID, data_not_reset=0, and length
// fields correctly, then set the data to all 1's.
//
`include "bsg_defines.v"
module bsg_tag_trace_replay
#( parameter `BSG_INV_PARAM(rom_addr_width_p )
, parameter `BSG_INV_PARAM(rom_data_width_p )
, parameter num_masters_p = 0
, parameter `BSG_INV_PARAM(num_clients_p )
, parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter uptime_p = 0)
( input clk_i
, input reset_i
, input en_i
, output [rom_addr_width_p-1:0] rom_addr_o
, input [rom_data_width_p-1:0] rom_data_i
, input valid_i
, input [max_payload_width_p-1:0] data_i
, output ready_o
, output valid_o
, output [`BSG_MAX(1,num_masters_p)-1:0] en_r_o
, output tag_data_o
, input yumi_i
, output done_o
, output error_o
) ;
`include "bsg_tag.vh"
// The trace ring width is the size of the rom data width
// minus the 4-bits for the trace-replay command.
localparam trace_ring_width_lp = rom_data_width_p - 4;
// The number of bits needed to represent the length of the
// payload inside bsg_tag.
localparam lg_max_payload_width_lp = `BSG_SAFE_CLOG2(max_payload_width_p + 1);
// The number of bits in the header of the tag packet.
`declare_bsg_tag_header_s(num_clients_p, lg_max_payload_width_lp);
localparam bsg_tag_header_width_lp = $bits(bsg_tag_header_s);
// Data signals between trace_replay and parallel_in_serial_out.
logic tr_valid_lo;
logic [trace_ring_width_lp-1:0] tr_data_lo;
logic tr_yumi_li;
// Instantiate the trace replay
bsg_fsb_node_trace_replay #( .ring_width_p(trace_ring_width_lp)
, .rom_addr_width_p(rom_addr_width_p)
, .uptime_p(uptime_p))
trace_replay
(.clk_i (clk_i)
,.reset_i (reset_i)
,.en_i (en_i)
/* input channel */
,.v_i (valid_i)
,.data_i (trace_ring_width_lp ' (data_i))
,.ready_o (ready_o)
/* output channel */
,.v_o (tr_valid_lo)
,.data_o (tr_data_lo)
,.yumi_i (tr_yumi_li)
/* rom connections */
,.rom_addr_o (rom_addr_o)
,.rom_data_i (rom_data_i)
/* signals */
,.done_o (done_o)
,.error_o (error_o)
);
// Reform the data between the trace-replay and the piso
// to properly act like a bsg_tag packet. This includes adding
// a 1-bit to the beginning of the data and a 0-bit to the
// end. Furthermore, swap the header and payload order.
wire [bsg_tag_header_width_lp-1:0] header_n = tr_data_lo[max_payload_width_p+:bsg_tag_header_width_lp];
wire [max_payload_width_p-1:0] payload_n = tr_data_lo[0+:max_payload_width_p];
wire [trace_ring_width_lp + 2 - 1:0] data_n = {1'b0, payload_n, header_n, 1'b1};
wire piso_ready_lo;
assign tr_yumi_li = piso_ready_lo & tr_valid_lo;
// Instantiate the paralle-in serial-out data structure.
bsg_parallel_in_serial_out #( .width_p(1)
, .els_p(trace_ring_width_lp + 2) )
trace_piso
(.clk_i (clk_i)
,.reset_i (reset_i)
/* Data Input Channel (Valid then Yumi) */
,.valid_i (tr_valid_lo)
,.data_i (data_n)
,.ready_and_o (piso_ready_lo)
/* Data Output Channel (Valid then Yumi) */
,.valid_o (valid_o)
,.data_o (tag_data_o)
,.yumi_i (yumi_i)
);
// If there are "no masters" (or at least none required to drive the enables
// for) then we will disconnect en_r_o, otherwise we will instantiate a
// register to capture the enables.
if (num_masters_p == 0)
begin
assign en_r_o = 1'bz;
end
else
begin
bsg_dff_en #( .width_p(num_masters_p) )
en_reg
(.clk_i (clk_i)
,.en_i (tr_valid_lo & piso_ready_lo)
,.data_i (tr_data_lo[(max_payload_width_p+bsg_tag_header_width_lp)+:num_masters_p])
,.data_o (en_r_o)
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_tag_trace_replay)
|
/* Made by brandon for brandon.
* I guarantee absolutely nothing and am not liable for any damages.
*/
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_Nano(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// EPCS //////////
EPCS_ASDO,
EPCS_DATA0,
EPCS_DCLK,
EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0,
GPIO_0_IN,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
GPIO_1,
GPIO_1_IN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// EPCS //////////
output EPCS_ASDO;
input EPCS_DATA0;
output EPCS_DCLK;
output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0;
inout [1:0] GPIO_0_IN;
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
// Stuff about more "natural" wires. ;)
wire [0:3] seconds;
wire [0:3] tens_seconds;
wire [0:3] minutes;
wire [0:3] tens_minutes;
wire [0:3] hours;
wire [0:3] tens_hours;
wire AM;
wire PM;
wire seconds_tick;
// What the wires actually are...
assign GPIO_0_IN[1] = seconds[0];
assign GPIO_0[1:3] = seconds[1:3];
assign GPIO_0[4:7] = tens_seconds[0:3];
assign GPIO_0[8:11] = minutes[0:3];
assign GPIO_0[12:15] = tens_minutes[0:3];
assign GPIO_0[16:19] = hours[0:3];
assign GPIO_0[20:23] = tens_hours[0:3];
assign GPIO_0[24] = AM;
assign GPIO_0[25] = PM;
assign GPIO_0[26] = seconds_tick;
//=======================================================
// Structural coding
//=======================================================
endmodule
|
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