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module sin_rom (
input wire [8:0] inadrs,
output wire [15:0] outsine);
assign outsine = sin_rom(inadrs);
function [15:0] sin_rom;
input [8:0] adrs;
begin
case (adrs)
9'D0 : sin_rom = 0 ;
9'D1 : sin_rom = 201 ;
9'D2 : sin_rom = 402 ;
9'D3 : sin_rom = 604 ;
9'D4 : sin_rom = 805 ;
9'D5 : sin_rom = 1007 ;
9'D6 : sin_rom = 1208 ;
9'D7 : sin_rom = 1410 ;
9'D8 : sin_rom = 1611 ;
9'D9 : sin_rom = 1812 ;
9'D10 : sin_rom = 2014 ;
9'D11 : sin_rom = 2215 ;
9'D12 : sin_rom = 2416 ;
9'D13 : sin_rom = 2618 ;
9'D14 : sin_rom = 2819 ;
9'D15 : sin_rom = 3020 ;
9'D16 : sin_rom = 3221 ;
9'D17 : sin_rom = 3423 ;
9'D18 : sin_rom = 3624 ;
9'D19 : sin_rom = 3825 ;
9'D20 : sin_rom = 4026 ;
9'D21 : sin_rom = 4227 ;
9'D22 : sin_rom = 4428 ;
9'D23 : sin_rom = 4629 ;
9'D24 : sin_rom = 4830 ;
9'D25 : sin_rom = 5031 ;
9'D26 : sin_rom = 5232 ;
9'D27 : sin_rom = 5433 ;
9'D28 : sin_rom = 5633 ;
9'D29 : sin_rom = 5834 ;
9'D30 : sin_rom = 6035 ;
9'D31 : sin_rom = 6235 ;
9'D32 : sin_rom = 6436 ;
9'D33 : sin_rom = 6636 ;
9'D34 : sin_rom = 6837 ;
9'D35 : sin_rom = 7037 ;
9'D36 : sin_rom = 7237 ;
9'D37 : sin_rom = 7437 ;
9'D38 : sin_rom = 7637 ;
9'D39 : sin_rom = 7837 ;
9'D40 : sin_rom = 8037 ;
9'D41 : sin_rom = 8237 ;
9'D42 : sin_rom = 8437 ;
9'D43 : sin_rom = 8637 ;
9'D44 : sin_rom = 8837 ;
9'D45 : sin_rom = 9036 ;
9'D46 : sin_rom = 9236 ;
9'D47 : sin_rom = 9435 ;
9'D48 : sin_rom = 9634 ;
9'D49 : sin_rom = 9834 ;
9'D50 : sin_rom = 10033 ;
9'D51 : sin_rom = 10232 ;
9'D52 : sin_rom = 10431 ;
9'D53 : sin_rom = 10629 ;
9'D54 : sin_rom = 10828 ;
9'D55 : sin_rom = 11027 ;
9'D56 : sin_rom = 11225 ;
9'D57 : sin_rom = 11424 ;
9'D58 : sin_rom = 11622 ;
9'D59 : sin_rom = 11820 ;
9'D60 : sin_rom = 12018 ;
9'D61 : sin_rom = 12216 ;
9'D62 : sin_rom = 12414 ;
9'D63 : sin_rom = 12612 ;
9'D64 : sin_rom = 12810 ;
9'D65 : sin_rom = 13007 ;
9'D66 : sin_rom = 13205 ;
9'D67 : sin_rom = 13402 ;
9'D68 : sin_rom = 13599 ;
9'D69 : sin_rom = 13796 ;
9'D70 : sin_rom = 13993 ;
9'D71 : sin_rom = 14190 ;
9'D72 : sin_rom = 14386 ;
9'D73 : sin_rom = 14583 ;
9'D74 : sin_rom = 14779 ;
9'D75 : sin_rom = 14975 ;
9'D76 : sin_rom = 15171 ;
9'D77 : sin_rom = 15367 ;
9'D78 : sin_rom = 15563 ;
9'D79 : sin_rom = 15759 ;
9'D80 : sin_rom = 15954 ;
9'D81 : sin_rom = 16149 ;
9'D82 : sin_rom = 16344 ;
9'D83 : sin_rom = 16539 ;
9'D84 : sin_rom = 16734 ;
9'D85 : sin_rom = 16929 ;
9'D86 : sin_rom = 17124 ;
9'D87 : sin_rom = 17318 ;
9'D88 : sin_rom = 17512 ;
9'D89 : sin_rom = 17706 ;
9'D90 : sin_rom = 17900 ;
9'D91 : sin_rom = 18094 ;
9'D92 : sin_rom = 18287 ;
9'D93 : sin_rom = 18481 ;
9'D94 : sin_rom = 18674 ;
9'D95 : sin_rom = 18867 ;
9'D96 : sin_rom = 19060 ;
9'D97 : sin_rom = 19252 ;
9'D98 : sin_rom = 19445 ;
9'D99 : sin_rom = 19637 ;
9'D100 : sin_rom = 19829 ;
9'D101 : sin_rom = 20021 ;
9'D102 : sin_rom = 20213 ;
9'D103 : sin_rom = 20404 ;
9'D104 : sin_rom = 20596 ;
9'D105 : sin_rom = 20787 ;
9'D106 : sin_rom = 20978 ;
9'D107 : sin_rom = 21169 ;
9'D108 : sin_rom = 21359 ;
9'D109 : sin_rom = 21550 ;
9'D110 : sin_rom = 21740 ;
9'D111 : sin_rom = 21930 ;
9'D112 : sin_rom = 22119 ;
9'D113 : sin_rom = 22309 ;
9'D114 : sin_rom = 22498 ;
9'D115 : sin_rom = 22687 ;
9'D116 : sin_rom = 22876 ;
9'D117 : sin_rom = 23065 ;
9'D118 : sin_rom = 23253 ;
9'D119 : sin_rom = 23442 ;
9'D120 : sin_rom = 23630 ;
9'D121 : sin_rom = 23817 ;
9'D122 : sin_rom = 24005 ;
9'D123 : sin_rom = 24192 ;
9'D124 : sin_rom = 24379 ;
9'D125 : sin_rom = 24566 ;
9'D126 : sin_rom = 24753 ;
9'D127 : sin_rom = 24939 ;
9'D128 : sin_rom = 25126 ;
9'D129 : sin_rom = 25312 ;
9'D130 : sin_rom = 25497 ;
9'D131 : sin_rom = 25683 ;
9'D132 : sin_rom = 25868 ;
9'D133 : sin_rom = 26053 ;
9'D134 : sin_rom = 26238 ;
9'D135 : sin_rom = 26422 ;
9'D136 : sin_rom = 26606 ;
9'D137 : sin_rom = 26790 ;
9'D138 : sin_rom = 26974 ;
9'D139 : sin_rom = 27157 ;
9'D140 : sin_rom = 27341 ;
9'D141 : sin_rom = 27524 ;
9'D142 : sin_rom = 27706 ;
9'D143 : sin_rom = 27889 ;
9'D144 : sin_rom = 28071 ;
9'D145 : sin_rom = 28253 ;
9'D146 : sin_rom = 28435 ;
9'D147 : sin_rom = 28616 ;
9'D148 : sin_rom = 28797 ;
9'D149 : sin_rom = 28978 ;
9'D150 : sin_rom = 29158 ;
9'D151 : sin_rom = 29339 ;
9'D152 : sin_rom = 29519 ;
9'D153 : sin_rom = 29698 ;
9'D154 : sin_rom = 29878 ;
9'D155 : sin_rom = 30057 ;
9'D156 : sin_rom = 30236 ;
9'D157 : sin_rom = 30414 ;
9'D158 : sin_rom = 30593 ;
9'D159 : sin_rom = 30771 ;
9'D160 : sin_rom = 30948 ;
9'D161 : sin_rom = 31126 ;
9'D162 : sin_rom = 31303 ;
9'D163 : sin_rom = 31480 ;
9'D164 : sin_rom = 31656 ;
9'D165 : sin_rom = 31833 ;
9'D166 : sin_rom = 32009 ;
9'D167 : sin_rom = 32184 ;
9'D168 : sin_rom = 32360 ;
9'D169 : sin_rom = 32535 ;
9'D170 : sin_rom = 32709 ;
9'D171 : sin_rom = 32884 ;
9'D172 : sin_rom = 33058 ;
9'D173 : sin_rom = 33232 ;
9'D174 : sin_rom = 33405 ;
9'D175 : sin_rom = 33578 ;
9'D176 : sin_rom = 33751 ;
9'D177 : sin_rom = 33924 ;
9'D178 : sin_rom = 34096 ;
9'D179 : sin_rom = 34268 ;
9'D180 : sin_rom = 34439 ;
9'D181 : sin_rom = 34611 ;
9'D182 : sin_rom = 34781 ;
9'D183 : sin_rom = 34952 ;
9'D184 : sin_rom = 35122 ;
9'D185 : sin_rom = 35292 ;
9'D186 : sin_rom = 35462 ;
9'D187 : sin_rom = 35631 ;
9'D188 : sin_rom = 35800 ;
9'D189 : sin_rom = 35968 ;
9'D190 : sin_rom = 36137 ;
9'D191 : sin_rom = 36305 ;
9'D192 : sin_rom = 36472 ;
9'D193 : sin_rom = 36639 ;
9'D194 : sin_rom = 36806 ;
9'D195 : sin_rom = 36973 ;
9'D196 : sin_rom = 37139 ;
9'D197 : sin_rom = 37305 ;
9'D198 : sin_rom = 37470 ;
9'D199 : sin_rom = 37635 ;
9'D200 : sin_rom = 37800 ;
9'D201 : sin_rom = 37964 ;
9'D202 : sin_rom = 38128 ;
9'D203 : sin_rom = 38292 ;
9'D204 : sin_rom = 38455 ;
9'D205 : sin_rom = 38618 ;
9'D206 : sin_rom = 38781 ;
9'D207 : sin_rom = 38943 ;
9'D208 : sin_rom = 39105 ;
9'D209 : sin_rom = 39266 ;
9'D210 : sin_rom = 39428 ;
9'D211 : sin_rom = 39588 ;
9'D212 : sin_rom = 39749 ;
9'D213 : sin_rom = 39909 ;
9'D214 : sin_rom = 40068 ;
9'D215 : sin_rom = 40227 ;
9'D216 : sin_rom = 40386 ;
9'D217 : sin_rom = 40545 ;
9'D218 : sin_rom = 40703 ;
9'D219 : sin_rom = 40861 ;
9'D220 : sin_rom = 41018 ;
9'D221 : sin_rom = 41175 ;
9'D222 : sin_rom = 41331 ;
9'D223 : sin_rom = 41487 ;
9'D224 : sin_rom = 41643 ;
9'D225 : sin_rom = 41799 ;
9'D226 : sin_rom = 41954 ;
9'D227 : sin_rom = 42108 ;
9'D228 : sin_rom = 42262 ;
9'D229 : sin_rom = 42416 ;
9'D230 : sin_rom = 42569 ;
9'D231 : sin_rom = 42722 ;
9'D232 : sin_rom = 42875 ;
9'D233 : sin_rom = 43027 ;
9'D234 : sin_rom = 43179 ;
9'D235 : sin_rom = 43330 ;
9'D236 : sin_rom = 43481 ;
9'D237 : sin_rom = 43632 ;
9'D238 : sin_rom = 43782 ;
9'D239 : sin_rom = 43931 ;
9'D240 : sin_rom = 44081 ;
9'D241 : sin_rom = 44230 ;
9'D242 : sin_rom = 44378 ;
9'D243 : sin_rom = 44526 ;
9'D244 : sin_rom = 44674 ;
9'D245 : sin_rom = 44821 ;
9'D246 : sin_rom = 44968 ;
9'D247 : sin_rom = 45114 ;
9'D248 : sin_rom = 45260 ;
9'D249 : sin_rom = 45405 ;
9'D250 : sin_rom = 45550 ;
9'D251 : sin_rom = 45695 ;
9'D252 : sin_rom = 45839 ;
9'D253 : sin_rom = 45983 ;
9'D254 : sin_rom = 46126 ;
9'D255 : sin_rom = 46269 ;
9'D256 : sin_rom = 46412 ;
9'D257 : sin_rom = 46554 ;
9'D258 : sin_rom = 46695 ;
9'D259 : sin_rom = 46836 ;
9'D260 : sin_rom = 46977 ;
9'D261 : sin_rom = 47117 ;
9'D262 : sin_rom = 47257 ;
9'D263 : sin_rom = 47396 ;
9'D264 : sin_rom = 47535 ;
9'D265 : sin_rom = 47674 ;
9'D266 : sin_rom = 47812 ;
9'D267 : sin_rom = 47949 ;
9'D268 : sin_rom = 48086 ;
9'D269 : sin_rom = 48223 ;
9'D270 : sin_rom = 48359 ;
9'D271 : sin_rom = 48495 ;
9'D272 : sin_rom = 48630 ;
9'D273 : sin_rom = 48765 ;
9'D274 : sin_rom = 48899 ;
9'D275 : sin_rom = 49033 ;
9'D276 : sin_rom = 49167 ;
9'D277 : sin_rom = 49300 ;
9'D278 : sin_rom = 49432 ;
9'D279 : sin_rom = 49564 ;
9'D280 : sin_rom = 49696 ;
9'D281 : sin_rom = 49827 ;
9'D282 : sin_rom = 49958 ;
9'D283 : sin_rom = 50088 ;
9'D284 : sin_rom = 50217 ;
9'D285 : sin_rom = 50347 ;
9'D286 : sin_rom = 50475 ;
9'D287 : sin_rom = 50604 ;
9'D288 : sin_rom = 50731 ;
9'D289 : sin_rom = 50859 ;
9'D290 : sin_rom = 50985 ;
9'D291 : sin_rom = 51112 ;
9'D292 : sin_rom = 51238 ;
9'D293 : sin_rom = 51363 ;
9'D294 : sin_rom = 51488 ;
9'D295 : sin_rom = 51612 ;
9'D296 : sin_rom = 51736 ;
9'D297 : sin_rom = 51860 ;
9'D298 : sin_rom = 51982 ;
9'D299 : sin_rom = 52105 ;
9'D300 : sin_rom = 52227 ;
9'D301 : sin_rom = 52348 ;
9'D302 : sin_rom = 52469 ;
9'D303 : sin_rom = 52590 ;
9'D304 : sin_rom = 52710 ;
9'D305 : sin_rom = 52829 ;
9'D306 : sin_rom = 52948 ;
9'D307 : sin_rom = 53067 ;
9'D308 : sin_rom = 53185 ;
9'D309 : sin_rom = 53302 ;
9'D310 : sin_rom = 53419 ;
9'D311 : sin_rom = 53535 ;
9'D312 : sin_rom = 53651 ;
9'D313 : sin_rom = 53767 ;
9'D314 : sin_rom = 53882 ;
9'D315 : sin_rom = 53996 ;
9'D316 : sin_rom = 54110 ;
9'D317 : sin_rom = 54223 ;
9'D318 : sin_rom = 54336 ;
9'D319 : sin_rom = 54449 ;
9'D320 : sin_rom = 54561 ;
9'D321 : sin_rom = 54672 ;
9'D322 : sin_rom = 54783 ;
9'D323 : sin_rom = 54893 ;
9'D324 : sin_rom = 55003 ;
9'D325 : sin_rom = 55112 ;
9'D326 : sin_rom = 55221 ;
9'D327 : sin_rom = 55329 ;
9'D328 : sin_rom = 55437 ;
9'D329 : sin_rom = 55544 ;
9'D330 : sin_rom = 55651 ;
9'D331 : sin_rom = 55757 ;
9'D332 : sin_rom = 55862 ;
9'D333 : sin_rom = 55967 ;
9'D334 : sin_rom = 56072 ;
9'D335 : sin_rom = 56176 ;
9'D336 : sin_rom = 56279 ;
9'D337 : sin_rom = 56382 ;
9'D338 : sin_rom = 56485 ;
9'D339 : sin_rom = 56587 ;
9'D340 : sin_rom = 56688 ;
9'D341 : sin_rom = 56789 ;
9'D342 : sin_rom = 56889 ;
9'D343 : sin_rom = 56989 ;
9'D344 : sin_rom = 57088 ;
9'D345 : sin_rom = 57187 ;
9'D346 : sin_rom = 57285 ;
9'D347 : sin_rom = 57382 ;
9'D348 : sin_rom = 57480 ;
9'D349 : sin_rom = 57576 ;
9'D350 : sin_rom = 57672 ;
9'D351 : sin_rom = 57767 ;
9'D352 : sin_rom = 57862 ;
9'D353 : sin_rom = 57957 ;
9'D354 : sin_rom = 58050 ;
9'D355 : sin_rom = 58144 ;
9'D356 : sin_rom = 58236 ;
9'D357 : sin_rom = 58328 ;
9'D358 : sin_rom = 58420 ;
9'D359 : sin_rom = 58511 ;
9'D360 : sin_rom = 58601 ;
9'D361 : sin_rom = 58691 ;
9'D362 : sin_rom = 58781 ;
9'D363 : sin_rom = 58869 ;
9'D364 : sin_rom = 58958 ;
9'D365 : sin_rom = 59045 ;
9'D366 : sin_rom = 59133 ;
9'D367 : sin_rom = 59219 ;
9'D368 : sin_rom = 59305 ;
9'D369 : sin_rom = 59391 ;
9'D370 : sin_rom = 59475 ;
9'D371 : sin_rom = 59560 ;
9'D372 : sin_rom = 59644 ;
9'D373 : sin_rom = 59727 ;
9'D374 : sin_rom = 59809 ;
9'D375 : sin_rom = 59891 ;
9'D376 : sin_rom = 59973 ;
9'D377 : sin_rom = 60054 ;
9'D378 : sin_rom = 60134 ;
9'D379 : sin_rom = 60214 ;
9'D380 : sin_rom = 60293 ;
9'D381 : sin_rom = 60372 ;
9'D382 : sin_rom = 60450 ;
9'D383 : sin_rom = 60528 ;
9'D384 : sin_rom = 60605 ;
9'D385 : sin_rom = 60681 ;
9'D386 : sin_rom = 60757 ;
9'D387 : sin_rom = 60832 ;
9'D388 : sin_rom = 60907 ;
9'D389 : sin_rom = 60981 ;
9'D390 : sin_rom = 61054 ;
9'D391 : sin_rom = 61127 ;
9'D392 : sin_rom = 61199 ;
9'D393 : sin_rom = 61271 ;
9'D394 : sin_rom = 61342 ;
9'D395 : sin_rom = 61413 ;
9'D396 : sin_rom = 61483 ;
9'D397 : sin_rom = 61553 ;
9'D398 : sin_rom = 61621 ;
9'D399 : sin_rom = 61690 ;
9'D400 : sin_rom = 61757 ;
9'D401 : sin_rom = 61824 ;
9'D402 : sin_rom = 61891 ;
9'D403 : sin_rom = 61957 ;
9'D404 : sin_rom = 62022 ;
9'D405 : sin_rom = 62087 ;
9'D406 : sin_rom = 62151 ;
9'D407 : sin_rom = 62215 ;
9'D408 : sin_rom = 62278 ;
9'D409 : sin_rom = 62340 ;
9'D410 : sin_rom = 62402 ;
9'D411 : sin_rom = 62463 ;
9'D412 : sin_rom = 62524 ;
9'D413 : sin_rom = 62584 ;
9'D414 : sin_rom = 62644 ;
9'D415 : sin_rom = 62703 ;
9'D416 : sin_rom = 62761 ;
9'D417 : sin_rom = 62819 ;
9'D418 : sin_rom = 62876 ;
9'D419 : sin_rom = 62932 ;
9'D420 : sin_rom = 62988 ;
9'D421 : sin_rom = 63043 ;
9'D422 : sin_rom = 63098 ;
9'D423 : sin_rom = 63152 ;
9'D424 : sin_rom = 63206 ;
9'D425 : sin_rom = 63259 ;
9'D426 : sin_rom = 63311 ;
9'D427 : sin_rom = 63363 ;
9'D428 : sin_rom = 63414 ;
9'D429 : sin_rom = 63465 ;
9'D430 : sin_rom = 63514 ;
9'D431 : sin_rom = 63564 ;
9'D432 : sin_rom = 63613 ;
9'D433 : sin_rom = 63661 ;
9'D434 : sin_rom = 63708 ;
9'D435 : sin_rom = 63755 ;
9'D436 : sin_rom = 63802 ;
9'D437 : sin_rom = 63847 ;
9'D438 : sin_rom = 63892 ;
9'D439 : sin_rom = 63937 ;
9'D440 : sin_rom = 63981 ;
9'D441 : sin_rom = 64024 ;
9'D442 : sin_rom = 64067 ;
9'D443 : sin_rom = 64109 ;
9'D444 : sin_rom = 64150 ;
9'D445 : sin_rom = 64191 ;
9'D446 : sin_rom = 64232 ;
9'D447 : sin_rom = 64271 ;
9'D448 : sin_rom = 64310 ;
9'D449 : sin_rom = 64349 ;
9'D450 : sin_rom = 64387 ;
9'D451 : sin_rom = 64424 ;
9'D452 : sin_rom = 64461 ;
9'D453 : sin_rom = 64497 ;
9'D454 : sin_rom = 64532 ;
9'D455 : sin_rom = 64567 ;
9'D456 : sin_rom = 64601 ;
9'D457 : sin_rom = 64635 ;
9'D458 : sin_rom = 64668 ;
9'D459 : sin_rom = 64700 ;
9'D460 : sin_rom = 64732 ;
9'D461 : sin_rom = 64763 ;
9'D462 : sin_rom = 64793 ;
9'D463 : sin_rom = 64823 ;
9'D464 : sin_rom = 64853 ;
9'D465 : sin_rom = 64881 ;
9'D466 : sin_rom = 64909 ;
9'D467 : sin_rom = 64937 ;
9'D468 : sin_rom = 64964 ;
9'D469 : sin_rom = 64990 ;
9'D470 : sin_rom = 65016 ;
9'D471 : sin_rom = 65041 ;
9'D472 : sin_rom = 65065 ;
9'D473 : sin_rom = 65089 ;
9'D474 : sin_rom = 65112 ;
9'D475 : sin_rom = 65135 ;
9'D476 : sin_rom = 65157 ;
9'D477 : sin_rom = 65178 ;
9'D478 : sin_rom = 65199 ;
9'D479 : sin_rom = 65219 ;
9'D480 : sin_rom = 65238 ;
9'D481 : sin_rom = 65257 ;
9'D482 : sin_rom = 65275 ;
9'D483 : sin_rom = 65293 ;
9'D484 : sin_rom = 65310 ;
9'D485 : sin_rom = 65326 ;
9'D486 : sin_rom = 65342 ;
9'D487 : sin_rom = 65357 ;
9'D488 : sin_rom = 65372 ;
9'D489 : sin_rom = 65386 ;
9'D490 : sin_rom = 65399 ;
9'D491 : sin_rom = 65412 ;
9'D492 : sin_rom = 65424 ;
9'D493 : sin_rom = 65435 ;
9'D494 : sin_rom = 65446 ;
9'D495 : sin_rom = 65456 ;
9'D496 : sin_rom = 65466 ;
9'D497 : sin_rom = 65475 ;
9'D498 : sin_rom = 65483 ;
9'D499 : sin_rom = 65491 ;
9'D500 : sin_rom = 65498 ;
9'D501 : sin_rom = 65505 ;
9'D502 : sin_rom = 65510 ;
9'D503 : sin_rom = 65516 ;
9'D504 : sin_rom = 65520 ;
9'D505 : sin_rom = 65524 ;
9'D506 : sin_rom = 65528 ;
9'D507 : sin_rom = 65531 ;
9'D508 : sin_rom = 65533 ;
9'D509 : sin_rom = 65534 ;
9'D510 : sin_rom = 65535 ;
9'D511 : sin_rom = 65535 ;
default : sin_rom = 0 ;
endcase
end
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKINV_PP_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkinv (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_fpbuf_p0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module cpx_fpbuf_p0(/*AUTOARG*/
// Outputs
fp_cpx_req_bufp0_cq,
// Inputs
fp_cpx_req_bufpt_cq_l
);
input [7:0] fp_cpx_req_bufpt_cq_l;
output [7:0] fp_cpx_req_bufp0_cq;
assign fp_cpx_req_bufp0_cq[7:0] = ~fp_cpx_req_bufpt_cq_l[7:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
|
//cont_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module cont_controller (
input rst, //reset
input clk,
input phy_ready,
input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)
input last_prim,
input [31:0] ll_tx_din,
input ll_tx_isk,
output [31:0] cont_tx_dout,
output cont_tx_isk,
input [31:0] rx_din,
input [3:0] rx_isk,
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_err,
output detect_r_ok,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_preq_s,
output detect_preq_p,
output detect_align,
output detect_xrdy_xrdy
);
//Parameters
//Registers/Wires
//CONT detect State Machine
wire hold_cont;
wire holda_cont;
wire pmreq_p_cont;
wire pmreq_s_cont;
wire r_err_cont;
wire r_ip_cont;
wire r_ok_cont;
wire r_rdy_cont;
wire sync_cont;
wire wtrm_cont;
wire x_rdy_cont;
reg cont_detect;
reg [31:0] prev_prim;
reg hold_cont_ready;
reg holda_cont_ready;
reg pmreq_p_cont_ready;
reg pmreq_s_cont_ready;
reg r_err_cont_ready;
reg r_ip_cont_ready;
reg r_ok_cont_ready;
reg r_rdy_cont_ready;
reg sync_cont_ready;
reg wtrm_cont_ready;
reg x_rdy_cont_ready;
//CONT generate state machine
reg [31:0] tx_prev_prim;
reg tx_cont_enable;
reg tx_cont_sent;
reg send_cont;
//Scrambler control
wire scram_en;
wire [31:0] scram_dout;
//Submodules
scrambler scram (
.rst (rst ),
.clk (clk ),
.prim_scrambler (1'b1 ),
.en (scram_en ),
.din (ll_tx_din ),
.dout (scram_dout )
);
//Asynchronous Logic
assign detect_sync = ((rx_isk[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
assign detect_r_rdy = ((rx_isk[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
assign detect_r_ip = ((rx_isk[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
assign detect_r_err = ((rx_isk[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
assign detect_r_ok = ((rx_isk[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
assign detect_x_rdy = ((rx_isk[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
assign detect_sof = (rx_isk[0]) && (rx_din == `PRIM_SOF );
assign detect_eof = (rx_isk[0]) && (rx_din == `PRIM_EOF );
assign detect_wtrm = ((rx_isk[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
assign detect_cont = (rx_isk[0]) && (rx_din == `PRIM_CONT );
assign detect_hold = ((rx_isk[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
assign detect_holda = ((rx_isk[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
assign detect_preq_s = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
assign detect_preq_p = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
assign detect_align = (rx_isk[0]) && (rx_din == `PRIM_ALIGN );
assign detect_xrdy_xrdy = ((((rx_isk[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_isk && (ll_tx_din == `PRIM_X_RDY));
assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_din : //if the prev != curr (exit)
(last_prim) ? ll_tx_din:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? `PRIM_CONT : //need to first send the cont
scram_dout : //send the junk
ll_tx_din; //tx cont is not enabled
assign cont_tx_isk = (!xmit_cont_en) ? ll_tx_isk :
((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_isk ://if the prev != curr (exit)
(last_prim) ?ll_tx_isk:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? 1 : //need to first send the cont
0 : //send the junk
ll_tx_isk; //tx cont is not enabled
assign scram_en = tx_cont_enable;
//Synchronous logic
//Cont detect
always @ (posedge clk) begin
if (rst) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
else begin
if (!detect_align) begin
if (rx_isk) begin
if (rx_din == `PRIM_CONT) begin
cont_detect <= 1;
end
else if (prev_prim == rx_din) begin
case (prev_prim)
`PRIM_SYNC : begin
sync_cont_ready <= 1;
end
`PRIM_R_RDY : begin
r_rdy_cont_ready <= 1;
end
`PRIM_R_IP : begin
r_ip_cont_ready <= 1;
end
`PRIM_R_ERR : begin
r_err_cont_ready <= 1;
end
`PRIM_R_OK : begin
r_ok_cont_ready <= 1;
end
`PRIM_X_RDY : begin
x_rdy_cont_ready <= 1;
end
`PRIM_WTRM : begin
wtrm_cont_ready <= 1;
end
`PRIM_HOLD : begin
if (cont_detect) begin
hold_cont_ready <= 0;
cont_detect <= 0;
end
else begin
hold_cont_ready <= 1;
end
end
`PRIM_HOLDA : begin
if (cont_detect) begin
holda_cont_ready <= 0;
cont_detect <= 0;
end
else begin
holda_cont_ready <= 1;
end
end
`PRIM_PREQ_S : begin
pmreq_s_cont_ready <= 1;
end
`PRIM_PREQ_P : begin
pmreq_p_cont_ready <= 1;
end
`PRIM_ALIGN : begin
end
default: begin
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
endcase
end
//save the previous primative
else begin
prev_prim <= rx_din;
//previous primative doesn't equal current primitive
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
if (!rx_isk[0] && !cont_detect) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
end
end
//Cont Generator
always @ (posedge clk) begin
if (rst || !xmit_cont_en) begin
tx_prev_prim <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
send_cont <= 0;
end
else begin
if (phy_ready) begin
send_cont <= 0;
if (ll_tx_isk) begin
//reset everything because the previous primative is not equal to the current one
if (tx_prev_prim != ll_tx_din) begin
send_cont <= 0;
tx_cont_sent <= 0;
tx_cont_enable <= 0;
end
else begin
//see if we need to send the cont primative
if (tx_cont_enable && send_cont) begin
tx_cont_sent <= 1;
end
//previous primative == current primative
case (tx_prev_prim)
`PRIM_SYNC : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_IP : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_ERR : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_OK : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_X_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_WTRM : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLD : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLDA : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_S : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_P : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
default: begin
send_cont <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
end
endcase
end
end
else begin
//it is not a k value so don't read it
tx_prev_prim <= 0;
end
//k value record the PRIM
tx_prev_prim <= ll_tx_din;
if (last_prim) begin
tx_cont_enable <= 0;
end
end
end
end
endmodule
|
//==============================================================================
// Copyright (C) John-Philip Taylor
// [email protected]
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART_Tx #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Reset,
input Clk,
input [7:0]Data,
input Send,
output reg Busy,
output reg Tx // Tx line on the board D4.
);
//------------------------------------------------------------------------------
reg tSend;
reg [ 7:0]Temp;
reg [N-1:0]Count;
reg [ 2:0]BitCount;
//------------------------------------------------------------------------------
reg [1:0]State;
localparam Idle = 2'b00;
localparam Sending = 2'b01;
localparam StopBit = 2'b11;
localparam Done = 2'b10;
//------------------------------------------------------------------------------
reg tReset;
always @(posedge Clk) begin
tReset <= Reset;
if(tReset) begin
Busy <= 1'b0;
Tx <= 1'b1;
tSend <= 0;
Count <= 0;
BitCount <= 0;
State <= Idle;
//------------------------------------------------------------------------------
end else begin
tSend <= Send;
if(~|Count) begin
case(State)
Idle: begin
if(tSend) begin
Count <= Full;
BitCount <= 3'd7;
{Temp, Tx} <= {Data, 1'b0};
Busy <= 1'b1;
State <= Sending;
end
end
//------------------------------------------------------------------------------
Sending: begin
Count <= Full;
{Temp[6:0], Tx} <= Temp;
if(~|BitCount) State <= StopBit;
BitCount <= BitCount - 1'b1;
end
//------------------------------------------------------------------------------
StopBit: begin
Tx <= 1'b1;
Count <= Full;
State <= Done;
end
//------------------------------------------------------------------------------
Done: begin
if(~tSend) begin
Busy <= 1'b0;
State <= Idle;
end
end
//------------------------------------------------------------------------------
default:;
endcase
end else begin
Count <= Count - 1'b1;
end
end
end
//------------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_BEHAVIORAL_PP_V |
//-------------------------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------------------------------
// Filename : cabac_bae_stage1.v
// Author : chewein
// Created : 2014-09-03
// Description : loop up table for i_range_lut and shift_lut ,
// calculation bin_eq_lps
//-------------------------------------------------------------------------------------------
`include "enc_defines.v"
module cabac_bae_stage1(
state_i ,
bin_i ,
mps_i ,
range_lps_o ,
range_lps_update_lut_o ,
shift_lut_o ,
bin_eq_lps_o
);
//-------------------------------------------------------------------------------------------
//
//-------------------------------------------------------------------------------------------
input [5:0] state_i ;
input bin_i ;
input mps_i ;
output [31:0] range_lps_o ;
output [35:0] range_lps_update_lut_o ;
output [15:0] shift_lut_o ;
output bin_eq_lps_o ;
//-------------------------------------------------------------------------------------------
// loop up table for i_range_lut
//-------------------------------------------------------------------------------------------
reg [31:0] range_lps_r ;
always @* begin
case (state_i)
6'd0: begin range_lps_r = 32'h80_b0_d0_f0 ; end
6'd1: begin range_lps_r = 32'h80_a7_c5_e3 ; end
6'd2: begin range_lps_r = 32'h80_9e_bb_d8 ; end
6'd3: begin range_lps_r = 32'h7b_96_b2_cd ; end
6'd4: begin range_lps_r = 32'h74_8e_a9_c3 ; end
6'd5: begin range_lps_r = 32'h6f_87_a0_b9 ; end
6'd6: begin range_lps_r = 32'h69_80_98_af ; end
6'd7: begin range_lps_r = 32'h64_7a_90_a6 ; end
6'd8: begin range_lps_r = 32'h5f_74_89_9e ; end
6'd9: begin range_lps_r = 32'h5a_6e_82_96 ; end
6'd10: begin range_lps_r = 32'h55_68_7b_8e ; end
6'd11: begin range_lps_r = 32'h51_63_75_87 ; end
6'd12: begin range_lps_r = 32'h4d_5e_6f_80 ; end
6'd13: begin range_lps_r = 32'h49_59_69_7a ; end
6'd14: begin range_lps_r = 32'h45_55_64_74 ; end
6'd15: begin range_lps_r = 32'h42_50_5f_6e ; end
6'd16: begin range_lps_r = 32'h3e_4c_5a_68 ; end
6'd17: begin range_lps_r = 32'h3b_48_56_63 ; end
6'd18: begin range_lps_r = 32'h38_45_51_5e ; end
6'd19: begin range_lps_r = 32'h35_41_4d_59 ; end
6'd20: begin range_lps_r = 32'h33_3e_49_55 ; end
6'd21: begin range_lps_r = 32'h30_3b_45_50 ; end
6'd22: begin range_lps_r = 32'h2e_38_42_4c ; end
6'd23: begin range_lps_r = 32'h2b_35_3f_48 ; end
6'd24: begin range_lps_r = 32'h29_32_3b_45 ; end
6'd25: begin range_lps_r = 32'h27_30_38_41 ; end
6'd26: begin range_lps_r = 32'h25_2d_36_3e ; end
6'd27: begin range_lps_r = 32'h23_2b_33_3b ; end
6'd28: begin range_lps_r = 32'h21_29_30_38 ; end
6'd29: begin range_lps_r = 32'h20_27_2e_35 ; end
6'd30: begin range_lps_r = 32'h1e_25_2b_32 ; end
6'd31: begin range_lps_r = 32'h1d_23_29_30 ; end
6'd32: begin range_lps_r = 32'h1b_21_27_2d ; end
6'd33: begin range_lps_r = 32'h1a_1f_25_2b ; end
6'd34: begin range_lps_r = 32'h18_1e_23_29 ; end
6'd35: begin range_lps_r = 32'h17_1c_21_27 ; end
6'd36: begin range_lps_r = 32'h16_1b_20_25 ; end
6'd37: begin range_lps_r = 32'h15_1a_1e_23 ; end
6'd38: begin range_lps_r = 32'h14_18_1d_21 ; end
6'd39: begin range_lps_r = 32'h13_17_1b_1f ; end
6'd40: begin range_lps_r = 32'h12_16_1a_1e ; end
6'd41: begin range_lps_r = 32'h11_15_19_1c ; end
6'd42: begin range_lps_r = 32'h10_14_17_1b ; end
6'd43: begin range_lps_r = 32'h0f_13_16_19 ; end
6'd44: begin range_lps_r = 32'h0e_12_15_18 ; end
6'd45: begin range_lps_r = 32'h0e_11_14_17 ; end
6'd46: begin range_lps_r = 32'h0d_10_13_16 ; end
6'd47: begin range_lps_r = 32'h0c_0f_12_15 ; end
6'd48: begin range_lps_r = 32'h0c_0e_11_14 ; end
6'd49: begin range_lps_r = 32'h0b_0e_10_13 ; end
6'd50: begin range_lps_r = 32'h0b_0d_0f_12 ; end
6'd51: begin range_lps_r = 32'h0a_0c_0f_11 ; end
6'd52: begin range_lps_r = 32'h0a_0c_0e_10 ; end
6'd53: begin range_lps_r = 32'h09_0b_0d_0f ; end
6'd54: begin range_lps_r = 32'h09_0b_0c_0e ; end
6'd55: begin range_lps_r = 32'h08_0a_0c_0e ; end
6'd56: begin range_lps_r = 32'h08_09_0b_0d ; end
6'd57: begin range_lps_r = 32'h07_09_0b_0c ; end
6'd58: begin range_lps_r = 32'h07_09_0a_0c ; end
6'd59: begin range_lps_r = 32'h07_08_0a_0b ; end
6'd60: begin range_lps_r = 32'h06_08_09_0b ; end
6'd61: begin range_lps_r = 32'h06_07_09_0a ; end
6'd62: begin range_lps_r = 32'h06_07_08_09 ; end
6'd63: begin range_lps_r = 32'h02_02_02_02 ; end
endcase
end
//-------------------------------------------------------------------------------------------
// loop up table for shift_lut_r
//-------------------------------------------------------------------------------------------
reg [15:0] shift_lut_r ;
always @* begin
case (state_i)
6'd0: begin shift_lut_r = 16'h1_1_1_1 ; end // 9_9_9_9
6'd1: begin shift_lut_r = 16'h1_1_1_1 ; end // 9_9_9_9
6'd2: begin shift_lut_r = 16'h1_1_1_1 ; end // 9_9_9_9
6'd3: begin shift_lut_r = 16'h2_1_1_1 ; end
6'd4: begin shift_lut_r = 16'h2_1_1_1 ; end
6'd5: begin shift_lut_r = 16'h2_1_1_1 ; end
6'd6: begin shift_lut_r = 16'h2_1_1_1 ; end
6'd7: begin shift_lut_r = 16'h2_2_1_1 ; end
6'd8: begin shift_lut_r = 16'h2_2_1_1 ; end
6'd9: begin shift_lut_r = 16'h2_2_1_1 ; end
6'd10: begin shift_lut_r = 16'h2_2_2_1 ; end
6'd11: begin shift_lut_r = 16'h2_2_2_1 ; end
6'd12: begin shift_lut_r = 16'h2_2_2_1 ; end
6'd13: begin shift_lut_r = 16'h2_2_2_2 ; end
6'd14: begin shift_lut_r = 16'h2_2_2_2 ; end
6'd15: begin shift_lut_r = 16'h2_2_2_2 ; end
6'd16: begin shift_lut_r = 16'h3_2_2_2 ; end
6'd17: begin shift_lut_r = 16'h3_2_2_2 ; end
6'd18: begin shift_lut_r = 16'h3_2_2_2 ; end
6'd19: begin shift_lut_r = 16'h3_2_2_2 ; end
6'd20: begin shift_lut_r = 16'h3_3_2_2 ; end
6'd21: begin shift_lut_r = 16'h3_3_2_2 ; end
6'd22: begin shift_lut_r = 16'h3_3_2_2 ; end
6'd23: begin shift_lut_r = 16'h3_3_3_2 ; end
6'd24: begin shift_lut_r = 16'h3_3_3_2 ; end
6'd25: begin shift_lut_r = 16'h3_3_3_2 ; end
6'd26: begin shift_lut_r = 16'h3_3_3_3 ; end
6'd27: begin shift_lut_r = 16'h3_3_3_3 ; end
6'd28: begin shift_lut_r = 16'h3_3_3_3 ; end
6'd29: begin shift_lut_r = 16'h3_3_3_3 ; end
6'd30: begin shift_lut_r = 16'h4_3_3_3 ; end
6'd31: begin shift_lut_r = 16'h4_3_3_3 ; end
6'd32: begin shift_lut_r = 16'h4_3_3_3 ; end
6'd33: begin shift_lut_r = 16'h4_4_3_3 ; end
6'd34: begin shift_lut_r = 16'h4_4_3_3 ; end
6'd35: begin shift_lut_r = 16'h4_4_3_3 ; end
6'd36: begin shift_lut_r = 16'h4_4_3_3 ; end
6'd37: begin shift_lut_r = 16'h4_4_4_3 ; end
6'd38: begin shift_lut_r = 16'h4_4_4_3 ; end
6'd39: begin shift_lut_r = 16'h4_4_4_4 ; end
6'd40: begin shift_lut_r = 16'h4_4_4_4 ; end
6'd41: begin shift_lut_r = 16'h4_4_4_4 ; end
6'd42: begin shift_lut_r = 16'h4_4_4_4 ; end
6'd43: begin shift_lut_r = 16'h5_4_4_4 ; end
6'd44: begin shift_lut_r = 16'h5_4_4_4 ; end
6'd45: begin shift_lut_r = 16'h5_4_4_4 ; end
6'd46: begin shift_lut_r = 16'h5_4_4_4 ; end
6'd47: begin shift_lut_r = 16'h5_5_4_4 ; end
6'd48: begin shift_lut_r = 16'h5_5_4_4 ; end
6'd49: begin shift_lut_r = 16'h5_5_4_4 ; end
6'd50: begin shift_lut_r = 16'h5_5_5_4 ; end
6'd51: begin shift_lut_r = 16'h5_5_5_4 ; end
6'd52: begin shift_lut_r = 16'h5_5_5_4 ; end
6'd53: begin shift_lut_r = 16'h5_5_5_5 ; end
6'd54: begin shift_lut_r = 16'h5_5_5_5 ; end
6'd55: begin shift_lut_r = 16'h5_5_5_5 ; end
6'd56: begin shift_lut_r = 16'h5_5_5_5 ; end
6'd57: begin shift_lut_r = 16'h6_5_5_5 ; end
6'd58: begin shift_lut_r = 16'h6_5_5_5 ; end
6'd59: begin shift_lut_r = 16'h6_5_5_5 ; end
6'd60: begin shift_lut_r = 16'h6_5_5_5 ; end
6'd61: begin shift_lut_r = 16'h6_6_5_5 ; end
6'd62: begin shift_lut_r = 16'h6_6_5_5 ; end
6'd63: begin shift_lut_r = 16'h6_6_6_6 ; end
endcase
end
//-------------------------------------------------------------------------------------------
// calculation bin_eq_lps
//-------------------------------------------------------------------------------------------
wire bin_eq_lps_w = bin_i != mps_i ;
//-------------------------------------------------------------------------------------------
// calculation range_lps_lut_o
//-------------------------------------------------------------------------------------------
wire [8:0] range_lps_update_0_w = range_lps_r[ 7:0 ]<<shift_lut_r[ 3:0 ];
wire [8:0] range_lps_update_1_w = range_lps_r[15:8 ]<<shift_lut_r[ 7:4 ];
wire [8:0] range_lps_update_2_w = range_lps_r[23:16]<<shift_lut_r[11:8 ];
wire [8:0] range_lps_update_3_w = range_lps_r[31:24]<<shift_lut_r[15:12];
//-------------------------------------------------------------------------------------------
// output
//-------------------------------------------------------------------------------------------
assign range_lps_o = range_lps_r ;
assign shift_lut_o = shift_lut_r ;
assign bin_eq_lps_o = bin_eq_lps_w ;
assign range_lps_update_lut_o = {range_lps_update_3_w,range_lps_update_2_w,range_lps_update_1_w,range_lps_update_0_w};
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 08 00:47:23 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.v
// Design : system_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_processing_system7_0_0
(SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_WP;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
PULLUP pullup_MIO_0
(.O(MIO[0]));
PULLUP pullup_MIO_9
(.O(MIO[9]));
PULLUP pullup_MIO_10
(.O(MIO[10]));
PULLUP pullup_MIO_11
(.O(MIO[11]));
PULLUP pullup_MIO_12
(.O(MIO[12]));
PULLUP pullup_MIO_13
(.O(MIO[13]));
PULLUP pullup_MIO_14
(.O(MIO[14]));
PULLUP pullup_MIO_15
(.O(MIO[15]));
PULLUP pullup_MIO_46
(.O(MIO[46]));
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
system_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(SDIO0_WP),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module system_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
(* X_CORE_INFO = "vio,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_vio_0_0,vio,{}" *)
(* CORE_GENERATION_INFO = "system_vio_0_0,vio,{x_ipProduct=Vivado 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WIDTH=1,C_PROBE_IN212_WIDTH=1,C_PROBE_IN213_WIDTH=1,C_PROBE_IN214_WIDTH=1,C_PROBE_IN215_WIDTH=1,C_PROBE_IN216_WIDTH=1,C_PROBE_IN217_WIDTH=1,C_PROBE_IN218_WIDTH=1,C_PROBE_IN219_WIDTH=1,C_PROBE_IN220_WIDTH=1,C_PROBE_IN221_WIDTH=1,C_PROBE_IN222_WIDTH=1,C_PROBE_IN223_WIDTH=1,C_PROBE_IN224_WIDTH=1,C_PROBE_IN225_WIDTH=1,C_PROBE_IN226_WIDTH=1,C_PROBE_IN227_WIDTH=1,C_PROBE_IN228_WIDTH=1,C_PROBE_IN229_WIDTH=1,C_PROBE_IN230_WIDTH=1,C_PROBE_IN231_WIDTH=1,C_PROBE_IN232_WIDTH=1,C_PROBE_IN233_WIDTH=1,C_PROBE_IN234_WIDTH=1,C_PROBE_IN235_WIDTH=1,C_PROBE_IN236_WIDTH=1,C_PROBE_IN237_WIDTH=1,C_PROBE_IN238_WIDTH=1,C_PROBE_IN239_WIDTH=1,C_PROBE_IN240_WIDTH=1,C_PROBE_IN241_WIDTH=1,C_PROBE_IN242_WIDTH=1,C_PROBE_IN243_WIDTH=1,C_PROBE_IN244_WIDTH=1,C_PROBE_IN245_WIDTH=1,C_PROBE_IN246_WIDTH=1,C_PROBE_IN247_WIDTH=1,C_PROBE_IN248_WIDTH=1,C_PROBE_IN249_WIDTH=1,C_PROBE_IN250_WIDTH=1,C_PROBE_IN251_WIDTH=1,C_PROBE_IN252_WIDTH=1,C_PROBE_IN253_WIDTH=1,C_PROBE_IN254_WIDTH=1,C_PROBE_IN255_WIDTH=1,C_PROBE_OUT0_WIDTH=1,C_PROBE_OUT1_WIDTH=1,C_PROBE_OUT2_WIDTH=1,C_PROBE_OUT3_WIDTH=1,C_PROBE_OUT4_WIDTH=1,C_PROBE_OUT5_WIDTH=1,C_PROBE_OUT6_WIDTH=1,C_PROBE_OUT7_WIDTH=1,C_PROBE_OUT8_WIDTH=1,C_PROBE_OUT9_WIDTH=1,C_PROBE_OUT10_WIDTH=1,C_PROBE_OUT11_WIDTH=1,C_PROBE_OUT12_WIDTH=1,C_PROBE_OUT13_WIDTH=1,C_PROBE_OUT14_WIDTH=1,C_PROBE_OUT15_WIDTH=1,C_PROBE_OUT16_WIDTH=1,C_PROBE_OUT17_WIDTH=1,C_PROBE_OUT18_WIDTH=1,C_PROBE_OUT19_WIDTH=1,C_PROBE_OUT20_WIDTH=1,C_PROBE_OUT21_WIDTH=1,C_PROBE_OUT22_WIDTH=1,C_PROBE_OUT23_WIDTH=1,C_PROBE_OUT24_WIDTH=1,C_PROBE_OUT25_WIDTH=1,C_PROBE_OUT26_WIDTH=1,C_PROBE_OUT27_WIDTH=1,C_PROBE_OUT28_WIDTH=1,C_PROBE_OUT29_WIDTH=1,C_PROBE_OUT30_WIDTH=1,C_PROBE_OUT31_WIDTH=1,C_PROBE_OUT32_WIDTH=1,C_PROBE_OUT33_WIDTH=1,C_PROBE_OUT34_WIDTH=1,C_PROBE_OUT35_WIDTH=1,C_PROBE_OUT36_WIDTH=1,C_PROBE_OUT37_WIDTH=1,C_PROBE_OUT38_WIDTH=1,C_PROBE_OUT39_WIDTH=1,C_PROBE_OUT40_WIDTH=1,C_PROBE_OUT41_WIDTH=1,C_PROBE_OUT42_WIDTH=1,C_PROBE_OUT43_WIDTH=1,C_PROBE_OUT44_WIDTH=1,C_PROBE_OUT45_WIDTH=1,C_PROBE_OUT46_WIDTH=1,C_PROBE_OUT47_WIDTH=1,C_PROBE_OUT48_WIDTH=1,C_PROBE_OUT49_WIDTH=1,C_PROBE_OUT50_WIDTH=1,C_PROBE_OUT51_WIDTH=1,C_PROBE_OUT52_WIDTH=1,C_PROBE_OUT53_WIDTH=1,C_PROBE_OUT54_WIDTH=1,C_PROBE_OUT55_WIDTH=1,C_PROBE_OUT56_WIDTH=1,C_PROBE_OUT57_WIDTH=1,C_PROBE_OUT58_WIDTH=1,C_PROBE_OUT59_WIDTH=1,C_PROBE_OUT60_WIDTH=1,C_PROBE_OUT61_WIDTH=1,C_PROBE_OUT62_WIDTH=1,C_PROBE_OUT63_WIDTH=1,C_PROBE_OUT64_WIDTH=1,C_PROBE_OUT65_WIDTH=1,C_PROBE_OUT66_WIDTH=1,C_PROBE_OUT67_WIDTH=1,C_PROBE_OUT68_WIDTH=1,C_PROBE_OUT69_WIDTH=1,C_PROBE_OUT70_WIDTH=1,C_PROBE_OUT71_WIDTH=1,C_PROBE_OUT72_WIDTH=1,C_PROBE_OUT73_WIDTH=1,C_PROBE_OUT74_WIDTH=1,C_PROBE_OUT75_WIDTH=1,C_PROBE_OUT76_WIDTH=1,C_PROBE_OUT77_WIDTH=1,C_PROBE_OUT78_WIDTH=1,C_PROBE_OUT79_WIDTH=1,C_PROBE_OUT80_WIDTH=1,C_PROBE_OUT81_WIDTH=1,C_PROBE_OUT82_WIDTH=1,C_PROBE_OUT83_WIDTH=1,C_PROBE_OUT84_WIDTH=1,C_PROBE_OUT85_WIDTH=1,C_PROBE_OUT86_WIDTH=1,C_PROBE_OUT87_WIDTH=1,C_PROBE_OUT88_WIDTH=1,C_PROBE_OUT89_WIDTH=1,C_PROBE_OUT90_WIDTH=1,C_PROBE_OUT91_WIDTH=1,C_PROBE_OUT92_WIDTH=1,C_PROBE_OUT93_WIDTH=1,C_PROBE_OUT94_WIDTH=1,C_PROBE_OUT95_WIDTH=1,C_PROBE_OUT96_WIDTH=1,C_PROBE_OUT97_WIDTH=1,C_PROBE_OUT98_WIDTH=1,C_PROBE_OUT99_WIDTH=1,C_PROBE_OUT100_WIDTH=1,C_PROBE_OUT101_WIDTH=1,C_PROBE_OUT102_WIDTH=1,C_PROBE_OUT103_WIDTH=1,C_PROBE_OUT104_WIDTH=1,C_PROBE_OUT105_WIDTH=1,C_PROBE_OUT106_WIDTH=1,C_PROBE_OUT107_WIDTH=1,C_PROBE_OUT108_WIDTH=1,C_PROBE_OUT109_WIDTH=1,C_PROBE_OUT110_WIDTH=1,C_PROBE_OUT111_WIDTH=1,C_PROBE_OUT112_WIDTH=1,C_PROBE_OUT113_WIDTH=1,C_PROBE_OUT114_WIDTH=1,C_PROBE_OUT115_WIDTH=1,C_PROBE_OUT116_WIDTH=1,C_PROBE_OUT117_WIDTH=1,C_PROBE_OUT118_WIDTH=1,C_PROBE_OUT119_WIDTH=1,C_PROBE_OUT120_WIDTH=1,C_PROBE_OUT121_WIDTH=1,C_PROBE_OUT122_WIDTH=1,C_PROBE_OUT123_WIDTH=1,C_PROBE_OUT124_WIDTH=1,C_PROBE_OUT125_WIDTH=1,C_PROBE_OUT126_WIDTH=1,C_PROBE_OUT127_WIDTH=1,C_PROBE_OUT128_WIDTH=1,C_PROBE_OUT129_WIDTH=1,C_PROBE_OUT130_WIDTH=1,C_PROBE_OUT131_WIDTH=1,C_PROBE_OUT132_WIDTH=1,C_PROBE_OUT133_WIDTH=1,C_PROBE_OUT134_WIDTH=1,C_PROBE_OUT135_WIDTH=1,C_PROBE_OUT136_WIDTH=1,C_PROBE_OUT137_WIDTH=1,C_PROBE_OUT138_WIDTH=1,C_PROBE_OUT139_WIDTH=1,C_PROBE_OUT140_WIDTH=1,C_PROBE_OUT141_WIDTH=1,C_PROBE_OUT142_WIDTH=1,C_PROBE_OUT143_WIDTH=1,C_PROBE_OUT144_WIDTH=1,C_PROBE_OUT145_WIDTH=1,C_PROBE_OUT146_WIDTH=1,C_PROBE_OUT147_WIDTH=1,C_PROBE_OUT148_WIDTH=1,C_PROBE_OUT149_WIDTH=1,C_PROBE_OUT150_WIDTH=1,C_PROBE_OUT151_WIDTH=1,C_PROBE_OUT152_WIDTH=1,C_PROBE_OUT153_WIDTH=1,C_PROBE_OUT154_WIDTH=1,C_PROBE_OUT155_WIDTH=1,C_PROBE_OUT156_WIDTH=1,C_PROBE_OUT157_WIDTH=1,C_PROBE_OUT158_WIDTH=1,C_PROBE_OUT159_WIDTH=1,C_PROBE_OUT160_WIDTH=1,C_PROBE_OUT161_WIDTH=1,C_PROBE_OUT162_WIDTH=1,C_PROBE_OUT163_WIDTH=1,C_PROBE_OUT164_WIDTH=1,C_PROBE_OUT165_WIDTH=1,C_PROBE_OUT166_WIDTH=1,C_PROBE_OUT167_WIDTH=1,C_PROBE_OUT168_WIDTH=1,C_PROBE_OUT169_WIDTH=1,C_PROBE_OUT170_WIDTH=1,C_PROBE_OUT171_WIDTH=1,C_PROBE_OUT172_WIDTH=1,C_PROBE_OUT173_WIDTH=1,C_PROBE_OUT174_WIDTH=1,C_PROBE_OUT175_WIDTH=1,C_PROBE_OUT176_WIDTH=1,C_PROBE_OUT177_WIDTH=1,C_PROBE_OUT178_WIDTH=1,C_PROBE_OUT179_WIDTH=1,C_PROBE_OUT180_WIDTH=1,C_PROBE_OUT181_WIDTH=1,C_PROBE_OUT182_WIDTH=1,C_PROBE_OUT183_WIDTH=1,C_PROBE_OUT184_WIDTH=1,C_PROBE_OUT185_WIDTH=1,C_PROBE_OUT186_WIDTH=1,C_PROBE_OUT187_WIDTH=1,C_PROBE_OUT188_WIDTH=1,C_PROBE_OUT189_WIDTH=1,C_PROBE_OUT190_WIDTH=1,C_PROBE_OUT191_WIDTH=1,C_PROBE_OUT192_WIDTH=1,C_PROBE_OUT193_WIDTH=1,C_PROBE_OUT194_WIDTH=1,C_PROBE_OUT195_WIDTH=1,C_PROBE_OUT196_WIDTH=1,C_PROBE_OUT197_WIDTH=1,C_PROBE_OUT198_WIDTH=1,C_PROBE_OUT199_WIDTH=1,C_PROBE_OUT200_WIDTH=1,C_PROBE_OUT201_WIDTH=1,C_PROBE_OUT202_WIDTH=1,C_PROBE_OUT203_WIDTH=1,C_PROBE_OUT204_WIDTH=1,C_PROBE_OUT205_WIDTH=1,C_PROBE_OUT206_WIDTH=1,C_PROBE_OUT207_WIDTH=1,C_PROBE_OUT208_WIDTH=1,C_PROBE_OUT209_WIDTH=1,C_PROBE_OUT210_WIDTH=1,C_PROBE_OUT211_WIDTH=1,C_PROBE_OUT212_WIDTH=1,C_PROBE_OUT213_WIDTH=1,C_PROBE_OUT214_WIDTH=1,C_PROBE_OUT215_WIDTH=1,C_PROBE_OUT216_WIDTH=1,C_PROBE_OUT217_WIDTH=1,C_PROBE_OUT218_WIDTH=1,C_PROBE_OUT219_WIDTH=1,C_PROBE_OUT220_WIDTH=1,C_PROBE_OUT221_WIDTH=1,C_PROBE_OUT222_WIDTH=1,C_PROBE_OUT223_WIDTH=1,C_PROBE_OUT224_WIDTH=1,C_PROBE_OUT225_WIDTH=1,C_PROBE_OUT226_WIDTH=1,C_PROBE_OUT227_WIDTH=1,C_PROBE_OUT228_WIDTH=1,C_PROBE_OUT229_WIDTH=1,C_PROBE_OUT230_WIDTH=1,C_PROBE_OUT231_WIDTH=1,C_PROBE_OUT232_WIDTH=1,C_PROBE_OUT233_WIDTH=1,C_PROBE_OUT234_WIDTH=1,C_PROBE_OUT235_WIDTH=1,C_PROBE_OUT236_WIDTH=1,C_PROBE_OUT237_WIDTH=1,C_PROBE_OUT238_WIDTH=1,C_PROBE_OUT239_WIDTH=1,C_PROBE_OUT240_WIDTH=1,C_PROBE_OUT241_WIDTH=1,C_PROBE_OUT242_WIDTH=1,C_PROBE_OUT243_WIDTH=1,C_PROBE_OUT244_WIDTH=1,C_PROBE_OUT245_WIDTH=1,C_PROBE_OUT246_WIDTH=1,C_PROBE_OUT247_WIDTH=1,C_PROBE_OUT248_WIDTH=1,C_PROBE_OUT249_WIDTH=1,C_PROBE_OUT250_WIDTH=1,C_PROBE_OUT251_WIDTH=1,C_PROBE_OUT252_WIDTH=1,C_PROBE_OUT253_WIDTH=1,C_PROBE_OUT254_WIDTH=1,C_PROBE_OUT255_WIDTH=1,C_PROBE_OUT0_INIT_VAL=0x0,C_PROBE_OUT1_INIT_VAL=0,C_PROBE_OUT2_INIT_VAL=0,C_PROBE_OUT3_INIT_VAL=0,C_PROBE_OUT4_INIT_VAL=0,C_PROBE_OUT5_INIT_VAL=0,C_PROBE_OUT6_INIT_VAL=0,C_PROBE_OUT7_INIT_VAL=0,C_PROBE_OUT8_INIT_VAL=0,C_PROBE_OUT9_INIT_VAL=0,C_PROBE_OUT10_INIT_VAL=0,C_PROBE_OUT11_INIT_VAL=0,C_PROBE_OUT12_INIT_VAL=0,C_PROBE_OUT13_INIT_VAL=0,C_PROBE_OUT14_INIT_VAL=0,C_PROBE_OUT15_INIT_VAL=0,C_PROBE_OUT16_INIT_VAL=0,C_PROBE_OUT17_INIT_VAL=0,C_PROBE_OUT18_INIT_VAL=0,C_PROBE_OUT19_INIT_VAL=0,C_PROBE_OUT20_INIT_VAL=0,C_PROBE_OUT21_INIT_VAL=0,C_PROBE_OUT22_INIT_VAL=0,C_PROBE_OUT23_INIT_VAL=0,C_PROBE_OUT24_INIT_VAL=0,C_PROBE_OUT25_INIT_VAL=0,C_PROBE_OUT26_INIT_VAL=0,C_PROBE_OUT27_INIT_VAL=0,C_PROBE_OUT28_INIT_VAL=0,C_PROBE_OUT29_INIT_VAL=0,C_PROBE_OUT30_INIT_VAL=0,C_PROBE_OUT31_INIT_VAL=0,C_PROBE_OUT32_INIT_VAL=0,C_PROBE_OUT33_INIT_VAL=0,C_PROBE_OUT34_INIT_VAL=0,C_PROBE_OUT35_INIT_VAL=0,C_PROBE_OUT36_INIT_VAL=0,C_PROBE_OUT37_INIT_VAL=0,C_PROBE_OUT38_INIT_VAL=0,C_PROBE_OUT39_INIT_VAL=0,C_PROBE_OUT40_INIT_VAL=0,C_PROBE_OUT41_INIT_VAL=0,C_PROBE_OUT42_INIT_VAL=0,C_PROBE_OUT43_INIT_VAL=0,C_PROBE_OUT44_INIT_VAL=0,C_PROBE_OUT45_INIT_VAL=0,C_PROBE_OUT46_INIT_VAL=0,C_PROBE_OUT47_INIT_VAL=0,C_PROBE_OUT48_INIT_VAL=0,C_PROBE_OUT49_INIT_VAL=0,C_PROBE_OUT50_INIT_VAL=0,C_PROBE_OUT51_INIT_VAL=0,C_PROBE_OUT52_INIT_VAL=0,C_PROBE_OUT53_INIT_VAL=0,C_PROBE_OUT54_INIT_VAL=0,C_PROBE_OUT55_INIT_VAL=0,C_PROBE_OUT56_INIT_VAL=0,C_PROBE_OUT57_INIT_VAL=0,C_PROBE_OUT58_INIT_VAL=0,C_PROBE_OUT59_INIT_VAL=0,C_PROBE_OUT60_INIT_VAL=0,C_PROBE_OUT61_INIT_VAL=0,C_PROBE_OUT62_INIT_VAL=0,C_PROBE_OUT63_INIT_VAL=0,C_PROBE_OUT64_INIT_VAL=0,C_PROBE_OUT65_INIT_VAL=0,C_PROBE_OUT66_INIT_VAL=0,C_PROBE_OUT67_INIT_VAL=0,C_PROBE_OUT68_INIT_VAL=0,C_PROBE_OUT69_INIT_VAL=0,C_PROBE_OUT70_INIT_VAL=0,C_PROBE_OUT71_INIT_VAL=0,C_PROBE_OUT72_INIT_VAL=0,C_PROBE_OUT73_INIT_VAL=0,C_PROBE_OUT74_INIT_VAL=0,C_PROBE_OUT75_INIT_VAL=0,C_PROBE_OUT76_INIT_VAL=0,C_PROBE_OUT77_INIT_VAL=0,C_PROBE_OUT78_INIT_VAL=0,C_PROBE_OUT79_INIT_VAL=0,C_PROBE_OUT80_INIT_VAL=0,C_PROBE_OUT81_INIT_VAL=0,C_PROBE_OUT82_INIT_VAL=0,C_PROBE_OUT83_INIT_VAL=0,C_PROBE_OUT84_INIT_VAL=0,C_PROBE_OUT85_INIT_VAL=0,C_PROBE_OUT86_INIT_VAL=0,C_PROBE_OUT87_INIT_VAL=0,C_PROBE_OUT88_INIT_VAL=0,C_PROBE_OUT89_INIT_VAL=0,C_PROBE_OUT90_INIT_VAL=0,C_PROBE_OUT91_INIT_VAL=0,C_PROBE_OUT92_INIT_VAL=0,C_PROBE_OUT93_INIT_VAL=0,C_PROBE_OUT94_INIT_VAL=0,C_PROBE_OUT95_INIT_VAL=0,C_PROBE_OUT96_INIT_VAL=0,C_PROBE_OUT97_INIT_VAL=0,C_PROBE_OUT98_INIT_VAL=0,C_PROBE_OUT99_INIT_VAL=0,C_PROBE_OUT100_INIT_VAL=0,C_PROBE_OUT101_INIT_VAL=0,C_PROBE_OUT102_INIT_VAL=0,C_PROBE_OUT103_INIT_VAL=0,C_PROBE_OUT104_INIT_VAL=0,C_PROBE_OUT105_INIT_VAL=0,C_PROBE_OUT106_INIT_VAL=0,C_PROBE_OUT107_INIT_VAL=0,C_PROBE_OUT108_INIT_VAL=0,C_PROBE_OUT109_INIT_VAL=0,C_PROBE_OUT110_INIT_VAL=0,C_PROBE_OUT111_INIT_VAL=0,C_PROBE_OUT112_INIT_VAL=0,C_PROBE_OUT113_INIT_VAL=0,C_PROBE_OUT114_INIT_VAL=0,C_PROBE_OUT115_INIT_VAL=0,C_PROBE_OUT116_INIT_VAL=0,C_PROBE_OUT117_INIT_VAL=0,C_PROBE_OUT118_INIT_VAL=0,C_PROBE_OUT119_INIT_VAL=0,C_PROBE_OUT120_INIT_VAL=0,C_PROBE_OUT121_INIT_VAL=0,C_PROBE_OUT122_INIT_VAL=0,C_PROBE_OUT123_INIT_VAL=0,C_PROBE_OUT124_INIT_VAL=0,C_PROBE_OUT125_INIT_VAL=0,C_PROBE_OUT126_INIT_VAL=0,C_PROBE_OUT127_INIT_VAL=0,C_PROBE_OUT128_INIT_VAL=0,C_PROBE_OUT129_INIT_VAL=0,C_PROBE_OUT130_INIT_VAL=0,C_PROBE_OUT131_INIT_VAL=0,C_PROBE_OUT132_INIT_VAL=0,C_PROBE_OUT133_INIT_VAL=0,C_PROBE_OUT134_INIT_VAL=0,C_PROBE_OUT135_INIT_VAL=0,C_PROBE_OUT136_INIT_VAL=0,C_PROBE_OUT137_INIT_VAL=0,C_PROBE_OUT138_INIT_VAL=0,C_PROBE_OUT139_INIT_VAL=0,C_PROBE_OUT140_INIT_VAL=0,C_PROBE_OUT141_INIT_VAL=0,C_PROBE_OUT142_INIT_VAL=0,C_PROBE_OUT143_INIT_VAL=0,C_PROBE_OUT144_INIT_VAL=0,C_PROBE_OUT145_INIT_VAL=0,C_PROBE_OUT146_INIT_VAL=0,C_PROBE_OUT147_INIT_VAL=0,C_PROBE_OUT148_INIT_VAL=0,C_PROBE_OUT149_INIT_VAL=0,C_PROBE_OUT150_INIT_VAL=0,C_PROBE_OUT151_INIT_VAL=0,C_PROBE_OUT152_INIT_VAL=0,C_PROBE_OUT153_INIT_VAL=0,C_PROBE_OUT154_INIT_VAL=0,C_PROBE_OUT155_INIT_VAL=0,C_PROBE_OUT156_INIT_VAL=0,C_PROBE_OUT157_INIT_VAL=0,C_PROBE_OUT158_INIT_VAL=0,C_PROBE_OUT159_INIT_VAL=0,C_PROBE_OUT160_INIT_VAL=0,C_PROBE_OUT161_INIT_VAL=0,C_PROBE_OUT162_INIT_VAL=0,C_PROBE_OUT163_INIT_VAL=0,C_PROBE_OUT164_INIT_VAL=0,C_PROBE_OUT165_INIT_VAL=0,C_PROBE_OUT166_INIT_VAL=0,C_PROBE_OUT167_INIT_VAL=0,C_PROBE_OUT168_INIT_VAL=0,C_PROBE_OUT169_INIT_VAL=0,C_PROBE_OUT170_INIT_VAL=0,C_PROBE_OUT171_INIT_VAL=0,C_PROBE_OUT172_INIT_VAL=0,C_PROBE_OUT173_INIT_VAL=0,C_PROBE_OUT174_INIT_VAL=0,C_PROBE_OUT175_INIT_VAL=0,C_PROBE_OUT176_INIT_VAL=0,C_PROBE_OUT177_INIT_VAL=0,C_PROBE_OUT178_INIT_VAL=0,C_PROBE_OUT179_INIT_VAL=0,C_PROBE_OUT180_INIT_VAL=0,C_PROBE_OUT181_INIT_VAL=0,C_PROBE_OUT182_INIT_VAL=0,C_PROBE_OUT183_INIT_VAL=0,C_PROBE_OUT184_INIT_VAL=0,C_PROBE_OUT185_INIT_VAL=0,C_PROBE_OUT186_INIT_VAL=0,C_PROBE_OUT187_INIT_VAL=0,C_PROBE_OUT188_INIT_VAL=0,C_PROBE_OUT189_INIT_VAL=0,C_PROBE_OUT190_INIT_VAL=0,C_PROBE_OUT191_INIT_VAL=0,C_PROBE_OUT192_INIT_VAL=0,C_PROBE_OUT193_INIT_VAL=0,C_PROBE_OUT194_INIT_VAL=0,C_PROBE_OUT195_INIT_VAL=0,C_PROBE_OUT196_INIT_VAL=0,C_PROBE_OUT197_INIT_VAL=0,C_PROBE_OUT198_INIT_VAL=0,C_PROBE_OUT199_INIT_VAL=0,C_PROBE_OUT200_INIT_VAL=0,C_PROBE_OUT201_INIT_VAL=0,C_PROBE_OUT202_INIT_VAL=0,C_PROBE_OUT203_INIT_VAL=0,C_PROBE_OUT204_INIT_VAL=0,C_PROBE_OUT205_INIT_VAL=0,C_PROBE_OUT206_INIT_VAL=0,C_PROBE_OUT207_INIT_VAL=0,C_PROBE_OUT208_INIT_VAL=0,C_PROBE_OUT209_INIT_VAL=0,C_PROBE_OUT210_INIT_VAL=0,C_PROBE_OUT211_INIT_VAL=0,C_PROBE_OUT212_INIT_VAL=0,C_PROBE_OUT213_INIT_VAL=0,C_PROBE_OUT214_INIT_VAL=0,C_PROBE_OUT215_INIT_VAL=0,C_PROBE_OUT216_INIT_VAL=0,C_PROBE_OUT217_INIT_VAL=0,C_PROBE_OUT218_INIT_VAL=0,C_PROBE_OUT219_INIT_VAL=0,C_PROBE_OUT220_INIT_VAL=0,C_PROBE_OUT221_INIT_VAL=0,C_PROBE_OUT222_INIT_VAL=0,C_PROBE_OUT223_INIT_VAL=0,C_PROBE_OUT224_INIT_VAL=0,C_PROBE_OUT225_INIT_VAL=0,C_PROBE_OUT226_INIT_VAL=0,C_PROBE_OUT227_INIT_VAL=0,C_PROBE_OUT228_INIT_VAL=0,C_PROBE_OUT229_INIT_VAL=0,C_PROBE_OUT230_INIT_VAL=0,C_PROBE_OUT231_INIT_VAL=0,C_PROBE_OUT232_INIT_VAL=0,C_PROBE_OUT233_INIT_VAL=0,C_PROBE_OUT234_INIT_VAL=0,C_PROBE_OUT235_INIT_VAL=0,C_PROBE_OUT236_INIT_VAL=0,C_PROBE_OUT237_INIT_VAL=0,C_PROBE_OUT238_INIT_VAL=0,C_PROBE_OUT239_INIT_VAL=0,C_PROBE_OUT240_INIT_VAL=0,C_PROBE_OUT241_INIT_VAL=0,C_PROBE_OUT242_INIT_VAL=0,C_PROBE_OUT243_INIT_VAL=0,C_PROBE_OUT244_INIT_VAL=0,C_PROBE_OUT245_INIT_VAL=0,C_PROBE_OUT246_INIT_VAL=0,C_PROBE_OUT247_INIT_VAL=0,C_PROBE_OUT248_INIT_VAL=0,C_PROBE_OUT249_INIT_VAL=0,C_PROBE_OUT250_INIT_VAL=0,C_PROBE_OUT251_INIT_VAL=0,C_PROBE_OUT252_INIT_VAL=0,C_PROBE_OUT253_INIT_VAL=0,C_PROBE_OUT254_INIT_VAL=0,C_PROBE_OUT255_INIT_VAL=0}" *)
module system_vio_0_0 (
clk,
probe_out0
);
input clk;
output [0 : 0] probe_out0;
wire [16:0] sl_oport0;
wire [36:0] sl_iport0;
vio_v3_0_vio #(
.C_XLNX_HW_PROBE_INFO("DEFAULT"),
.C_XDEVICEFAMILY("zynq"),
.C_CORE_TYPE(2),
.C_CORE_INFO1(0),
.C_CORE_INFO2(0),
.C_NUM_PROBE_IN(0),
.C_EN_PROBE_IN_ACTIVITY(0),
.C_NUM_PROBE_OUT(1),
.C_MAJOR_VERSION(2013),
.C_MINOR_VERSION(1),
.C_BUILD_REVISION(0),
.C_CORE_MAJOR_VER(2),
.C_CORE_MINOR_VER(0),
.C_CORE_MINOR_ALPHA_VER(97),
.C_XSDB_SLAVE_TYPE(33),
.C_NEXT_SLAVE(0),
.C_CSE_DRV_VER(1),
.C_USE_TEST_REG(1),
.C_PIPE_IFACE(0),
.C_PROBE_IN0_WIDTH(1),
.C_PROBE_IN1_WIDTH(1),
.C_PROBE_IN2_WIDTH(1),
.C_PROBE_IN3_WIDTH(1),
.C_PROBE_IN4_WIDTH(1),
.C_PROBE_IN5_WIDTH(1),
.C_PROBE_IN6_WIDTH(1),
.C_PROBE_IN7_WIDTH(1),
.C_PROBE_IN8_WIDTH(1),
.C_PROBE_IN9_WIDTH(1),
.C_PROBE_IN10_WIDTH(1),
.C_PROBE_IN11_WIDTH(1),
.C_PROBE_IN12_WIDTH(1),
.C_PROBE_IN13_WIDTH(1),
.C_PROBE_IN14_WIDTH(1),
.C_PROBE_IN15_WIDTH(1),
.C_PROBE_IN16_WIDTH(1),
.C_PROBE_IN17_WIDTH(1),
.C_PROBE_IN18_WIDTH(1),
.C_PROBE_IN19_WIDTH(1),
.C_PROBE_IN20_WIDTH(1),
.C_PROBE_IN21_WIDTH(1),
.C_PROBE_IN22_WIDTH(1),
.C_PROBE_IN23_WIDTH(1),
.C_PROBE_IN24_WIDTH(1),
.C_PROBE_IN25_WIDTH(1),
.C_PROBE_IN26_WIDTH(1),
.C_PROBE_IN27_WIDTH(1),
.C_PROBE_IN28_WIDTH(1),
.C_PROBE_IN29_WIDTH(1),
.C_PROBE_IN30_WIDTH(1),
.C_PROBE_IN31_WIDTH(1),
.C_PROBE_IN32_WIDTH(1),
.C_PROBE_IN33_WIDTH(1),
.C_PROBE_IN34_WIDTH(1),
.C_PROBE_IN35_WIDTH(1),
.C_PROBE_IN36_WIDTH(1),
.C_PROBE_IN37_WIDTH(1),
.C_PROBE_IN38_WIDTH(1),
.C_PROBE_IN39_WIDTH(1),
.C_PROBE_IN40_WIDTH(1),
.C_PROBE_IN41_WIDTH(1),
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.C_PROBE_OUT61_INIT_VAL('h0),
.C_PROBE_OUT62_INIT_VAL('h0),
.C_PROBE_OUT63_INIT_VAL('h0),
.C_PROBE_OUT64_INIT_VAL('h0),
.C_PROBE_OUT65_INIT_VAL('h0),
.C_PROBE_OUT66_INIT_VAL('h0),
.C_PROBE_OUT67_INIT_VAL('h0),
.C_PROBE_OUT68_INIT_VAL('h0),
.C_PROBE_OUT69_INIT_VAL('h0),
.C_PROBE_OUT70_INIT_VAL('h0),
.C_PROBE_OUT71_INIT_VAL('h0),
.C_PROBE_OUT72_INIT_VAL('h0),
.C_PROBE_OUT73_INIT_VAL('h0),
.C_PROBE_OUT74_INIT_VAL('h0),
.C_PROBE_OUT75_INIT_VAL('h0),
.C_PROBE_OUT76_INIT_VAL('h0),
.C_PROBE_OUT77_INIT_VAL('h0),
.C_PROBE_OUT78_INIT_VAL('h0),
.C_PROBE_OUT79_INIT_VAL('h0),
.C_PROBE_OUT80_INIT_VAL('h0),
.C_PROBE_OUT81_INIT_VAL('h0),
.C_PROBE_OUT82_INIT_VAL('h0),
.C_PROBE_OUT83_INIT_VAL('h0),
.C_PROBE_OUT84_INIT_VAL('h0),
.C_PROBE_OUT85_INIT_VAL('h0),
.C_PROBE_OUT86_INIT_VAL('h0),
.C_PROBE_OUT87_INIT_VAL('h0),
.C_PROBE_OUT88_INIT_VAL('h0),
.C_PROBE_OUT89_INIT_VAL('h0),
.C_PROBE_OUT90_INIT_VAL('h0),
.C_PROBE_OUT91_INIT_VAL('h0),
.C_PROBE_OUT92_INIT_VAL('h0),
.C_PROBE_OUT93_INIT_VAL('h0),
.C_PROBE_OUT94_INIT_VAL('h0),
.C_PROBE_OUT95_INIT_VAL('h0),
.C_PROBE_OUT96_INIT_VAL('h0),
.C_PROBE_OUT97_INIT_VAL('h0),
.C_PROBE_OUT98_INIT_VAL('h0),
.C_PROBE_OUT99_INIT_VAL('h0),
.C_PROBE_OUT100_INIT_VAL('h0),
.C_PROBE_OUT101_INIT_VAL('h0),
.C_PROBE_OUT102_INIT_VAL('h0),
.C_PROBE_OUT103_INIT_VAL('h0),
.C_PROBE_OUT104_INIT_VAL('h0),
.C_PROBE_OUT105_INIT_VAL('h0),
.C_PROBE_OUT106_INIT_VAL('h0),
.C_PROBE_OUT107_INIT_VAL('h0),
.C_PROBE_OUT108_INIT_VAL('h0),
.C_PROBE_OUT109_INIT_VAL('h0),
.C_PROBE_OUT110_INIT_VAL('h0),
.C_PROBE_OUT111_INIT_VAL('h0),
.C_PROBE_OUT112_INIT_VAL('h0),
.C_PROBE_OUT113_INIT_VAL('h0),
.C_PROBE_OUT114_INIT_VAL('h0),
.C_PROBE_OUT115_INIT_VAL('h0),
.C_PROBE_OUT116_INIT_VAL('h0),
.C_PROBE_OUT117_INIT_VAL('h0),
.C_PROBE_OUT118_INIT_VAL('h0),
.C_PROBE_OUT119_INIT_VAL('h0),
.C_PROBE_OUT120_INIT_VAL('h0),
.C_PROBE_OUT121_INIT_VAL('h0),
.C_PROBE_OUT122_INIT_VAL('h0),
.C_PROBE_OUT123_INIT_VAL('h0),
.C_PROBE_OUT124_INIT_VAL('h0),
.C_PROBE_OUT125_INIT_VAL('h0),
.C_PROBE_OUT126_INIT_VAL('h0),
.C_PROBE_OUT127_INIT_VAL('h0),
.C_PROBE_OUT128_INIT_VAL('h0),
.C_PROBE_OUT129_INIT_VAL('h0),
.C_PROBE_OUT130_INIT_VAL('h0),
.C_PROBE_OUT131_INIT_VAL('h0),
.C_PROBE_OUT132_INIT_VAL('h0),
.C_PROBE_OUT133_INIT_VAL('h0),
.C_PROBE_OUT134_INIT_VAL('h0),
.C_PROBE_OUT135_INIT_VAL('h0),
.C_PROBE_OUT136_INIT_VAL('h0),
.C_PROBE_OUT137_INIT_VAL('h0),
.C_PROBE_OUT138_INIT_VAL('h0),
.C_PROBE_OUT139_INIT_VAL('h0),
.C_PROBE_OUT140_INIT_VAL('h0),
.C_PROBE_OUT141_INIT_VAL('h0),
.C_PROBE_OUT142_INIT_VAL('h0),
.C_PROBE_OUT143_INIT_VAL('h0),
.C_PROBE_OUT144_INIT_VAL('h0),
.C_PROBE_OUT145_INIT_VAL('h0),
.C_PROBE_OUT146_INIT_VAL('h0),
.C_PROBE_OUT147_INIT_VAL('h0),
.C_PROBE_OUT148_INIT_VAL('h0),
.C_PROBE_OUT149_INIT_VAL('h0),
.C_PROBE_OUT150_INIT_VAL('h0),
.C_PROBE_OUT151_INIT_VAL('h0),
.C_PROBE_OUT152_INIT_VAL('h0),
.C_PROBE_OUT153_INIT_VAL('h0),
.C_PROBE_OUT154_INIT_VAL('h0),
.C_PROBE_OUT155_INIT_VAL('h0),
.C_PROBE_OUT156_INIT_VAL('h0),
.C_PROBE_OUT157_INIT_VAL('h0),
.C_PROBE_OUT158_INIT_VAL('h0),
.C_PROBE_OUT159_INIT_VAL('h0),
.C_PROBE_OUT160_INIT_VAL('h0),
.C_PROBE_OUT161_INIT_VAL('h0),
.C_PROBE_OUT162_INIT_VAL('h0),
.C_PROBE_OUT163_INIT_VAL('h0),
.C_PROBE_OUT164_INIT_VAL('h0),
.C_PROBE_OUT165_INIT_VAL('h0),
.C_PROBE_OUT166_INIT_VAL('h0),
.C_PROBE_OUT167_INIT_VAL('h0),
.C_PROBE_OUT168_INIT_VAL('h0),
.C_PROBE_OUT169_INIT_VAL('h0),
.C_PROBE_OUT170_INIT_VAL('h0),
.C_PROBE_OUT171_INIT_VAL('h0),
.C_PROBE_OUT172_INIT_VAL('h0),
.C_PROBE_OUT173_INIT_VAL('h0),
.C_PROBE_OUT174_INIT_VAL('h0),
.C_PROBE_OUT175_INIT_VAL('h0),
.C_PROBE_OUT176_INIT_VAL('h0),
.C_PROBE_OUT177_INIT_VAL('h0),
.C_PROBE_OUT178_INIT_VAL('h0),
.C_PROBE_OUT179_INIT_VAL('h0),
.C_PROBE_OUT180_INIT_VAL('h0),
.C_PROBE_OUT181_INIT_VAL('h0),
.C_PROBE_OUT182_INIT_VAL('h0),
.C_PROBE_OUT183_INIT_VAL('h0),
.C_PROBE_OUT184_INIT_VAL('h0),
.C_PROBE_OUT185_INIT_VAL('h0),
.C_PROBE_OUT186_INIT_VAL('h0),
.C_PROBE_OUT187_INIT_VAL('h0),
.C_PROBE_OUT188_INIT_VAL('h0),
.C_PROBE_OUT189_INIT_VAL('h0),
.C_PROBE_OUT190_INIT_VAL('h0),
.C_PROBE_OUT191_INIT_VAL('h0),
.C_PROBE_OUT192_INIT_VAL('h0),
.C_PROBE_OUT193_INIT_VAL('h0),
.C_PROBE_OUT194_INIT_VAL('h0),
.C_PROBE_OUT195_INIT_VAL('h0),
.C_PROBE_OUT196_INIT_VAL('h0),
.C_PROBE_OUT197_INIT_VAL('h0),
.C_PROBE_OUT198_INIT_VAL('h0),
.C_PROBE_OUT199_INIT_VAL('h0),
.C_PROBE_OUT200_INIT_VAL('h0),
.C_PROBE_OUT201_INIT_VAL('h0),
.C_PROBE_OUT202_INIT_VAL('h0),
.C_PROBE_OUT203_INIT_VAL('h0),
.C_PROBE_OUT204_INIT_VAL('h0),
.C_PROBE_OUT205_INIT_VAL('h0),
.C_PROBE_OUT206_INIT_VAL('h0),
.C_PROBE_OUT207_INIT_VAL('h0),
.C_PROBE_OUT208_INIT_VAL('h0),
.C_PROBE_OUT209_INIT_VAL('h0),
.C_PROBE_OUT210_INIT_VAL('h0),
.C_PROBE_OUT211_INIT_VAL('h0),
.C_PROBE_OUT212_INIT_VAL('h0),
.C_PROBE_OUT213_INIT_VAL('h0),
.C_PROBE_OUT214_INIT_VAL('h0),
.C_PROBE_OUT215_INIT_VAL('h0),
.C_PROBE_OUT216_INIT_VAL('h0),
.C_PROBE_OUT217_INIT_VAL('h0),
.C_PROBE_OUT218_INIT_VAL('h0),
.C_PROBE_OUT219_INIT_VAL('h0),
.C_PROBE_OUT220_INIT_VAL('h0),
.C_PROBE_OUT221_INIT_VAL('h0),
.C_PROBE_OUT222_INIT_VAL('h0),
.C_PROBE_OUT223_INIT_VAL('h0),
.C_PROBE_OUT224_INIT_VAL('h0),
.C_PROBE_OUT225_INIT_VAL('h0),
.C_PROBE_OUT226_INIT_VAL('h0),
.C_PROBE_OUT227_INIT_VAL('h0),
.C_PROBE_OUT228_INIT_VAL('h0),
.C_PROBE_OUT229_INIT_VAL('h0),
.C_PROBE_OUT230_INIT_VAL('h0),
.C_PROBE_OUT231_INIT_VAL('h0),
.C_PROBE_OUT232_INIT_VAL('h0),
.C_PROBE_OUT233_INIT_VAL('h0),
.C_PROBE_OUT234_INIT_VAL('h0),
.C_PROBE_OUT235_INIT_VAL('h0),
.C_PROBE_OUT236_INIT_VAL('h0),
.C_PROBE_OUT237_INIT_VAL('h0),
.C_PROBE_OUT238_INIT_VAL('h0),
.C_PROBE_OUT239_INIT_VAL('h0),
.C_PROBE_OUT240_INIT_VAL('h0),
.C_PROBE_OUT241_INIT_VAL('h0),
.C_PROBE_OUT242_INIT_VAL('h0),
.C_PROBE_OUT243_INIT_VAL('h0),
.C_PROBE_OUT244_INIT_VAL('h0),
.C_PROBE_OUT245_INIT_VAL('h0),
.C_PROBE_OUT246_INIT_VAL('h0),
.C_PROBE_OUT247_INIT_VAL('h0),
.C_PROBE_OUT248_INIT_VAL('h0),
.C_PROBE_OUT249_INIT_VAL('h0),
.C_PROBE_OUT250_INIT_VAL('h0),
.C_PROBE_OUT251_INIT_VAL('h0),
.C_PROBE_OUT252_INIT_VAL('h0),
.C_PROBE_OUT253_INIT_VAL('h0),
.C_PROBE_OUT254_INIT_VAL('h0),
.C_PROBE_OUT255_INIT_VAL('h0)
) inst (
.clk(clk),
.sl_iport0(sl_iport0),
.sl_oport0(sl_oport0),
.probe_in0(0),
.probe_in1(0),
.probe_in2(0),
.probe_in3(0),
.probe_in4(0),
.probe_in5(0),
.probe_in6(0),
.probe_in7(0),
.probe_in8(0),
.probe_in9(0),
.probe_in10(0),
.probe_in11(0),
.probe_in12(0),
.probe_in13(0),
.probe_in14(0),
.probe_in15(0),
.probe_in16(0),
.probe_in17(0),
.probe_in18(0),
.probe_in19(0),
.probe_in20(0),
.probe_in21(0),
.probe_in22(0),
.probe_in23(0),
.probe_in24(0),
.probe_in25(0),
.probe_in26(0),
.probe_in27(0),
.probe_in28(0),
.probe_in29(0),
.probe_in30(0),
.probe_in31(0),
.probe_in32(0),
.probe_in33(0),
.probe_in34(0),
.probe_in35(0),
.probe_in36(0),
.probe_in37(0),
.probe_in38(0),
.probe_in39(0),
.probe_in40(0),
.probe_in41(0),
.probe_in42(0),
.probe_in43(0),
.probe_in44(0),
.probe_in45(0),
.probe_in46(0),
.probe_in47(0),
.probe_in48(0),
.probe_in49(0),
.probe_in50(0),
.probe_in51(0),
.probe_in52(0),
.probe_in53(0),
.probe_in54(0),
.probe_in55(0),
.probe_in56(0),
.probe_in57(0),
.probe_in58(0),
.probe_in59(0),
.probe_in60(0),
.probe_in61(0),
.probe_in62(0),
.probe_in63(0),
.probe_in64(0),
.probe_in65(0),
.probe_in66(0),
.probe_in67(0),
.probe_in68(0),
.probe_in69(0),
.probe_in70(0),
.probe_in71(0),
.probe_in72(0),
.probe_in73(0),
.probe_in74(0),
.probe_in75(0),
.probe_in76(0),
.probe_in77(0),
.probe_in78(0),
.probe_in79(0),
.probe_in80(0),
.probe_in81(0),
.probe_in82(0),
.probe_in83(0),
.probe_in84(0),
.probe_in85(0),
.probe_in86(0),
.probe_in87(0),
.probe_in88(0),
.probe_in89(0),
.probe_in90(0),
.probe_in91(0),
.probe_in92(0),
.probe_in93(0),
.probe_in94(0),
.probe_in95(0),
.probe_in96(0),
.probe_in97(0),
.probe_in98(0),
.probe_in99(0),
.probe_in100(0),
.probe_in101(0),
.probe_in102(0),
.probe_in103(0),
.probe_in104(0),
.probe_in105(0),
.probe_in106(0),
.probe_in107(0),
.probe_in108(0),
.probe_in109(0),
.probe_in110(0),
.probe_in111(0),
.probe_in112(0),
.probe_in113(0),
.probe_in114(0),
.probe_in115(0),
.probe_in116(0),
.probe_in117(0),
.probe_in118(0),
.probe_in119(0),
.probe_in120(0),
.probe_in121(0),
.probe_in122(0),
.probe_in123(0),
.probe_in124(0),
.probe_in125(0),
.probe_in126(0),
.probe_in127(0),
.probe_in128(0),
.probe_in129(0),
.probe_in130(0),
.probe_in131(0),
.probe_in132(0),
.probe_in133(0),
.probe_in134(0),
.probe_in135(0),
.probe_in136(0),
.probe_in137(0),
.probe_in138(0),
.probe_in139(0),
.probe_in140(0),
.probe_in141(0),
.probe_in142(0),
.probe_in143(0),
.probe_in144(0),
.probe_in145(0),
.probe_in146(0),
.probe_in147(0),
.probe_in148(0),
.probe_in149(0),
.probe_in150(0),
.probe_in151(0),
.probe_in152(0),
.probe_in153(0),
.probe_in154(0),
.probe_in155(0),
.probe_in156(0),
.probe_in157(0),
.probe_in158(0),
.probe_in159(0),
.probe_in160(0),
.probe_in161(0),
.probe_in162(0),
.probe_in163(0),
.probe_in164(0),
.probe_in165(0),
.probe_in166(0),
.probe_in167(0),
.probe_in168(0),
.probe_in169(0),
.probe_in170(0),
.probe_in171(0),
.probe_in172(0),
.probe_in173(0),
.probe_in174(0),
.probe_in175(0),
.probe_in176(0),
.probe_in177(0),
.probe_in178(0),
.probe_in179(0),
.probe_in180(0),
.probe_in181(0),
.probe_in182(0),
.probe_in183(0),
.probe_in184(0),
.probe_in185(0),
.probe_in186(0),
.probe_in187(0),
.probe_in188(0),
.probe_in189(0),
.probe_in190(0),
.probe_in191(0),
.probe_in192(0),
.probe_in193(0),
.probe_in194(0),
.probe_in195(0),
.probe_in196(0),
.probe_in197(0),
.probe_in198(0),
.probe_in199(0),
.probe_in200(0),
.probe_in201(0),
.probe_in202(0),
.probe_in203(0),
.probe_in204(0),
.probe_in205(0),
.probe_in206(0),
.probe_in207(0),
.probe_in208(0),
.probe_in209(0),
.probe_in210(0),
.probe_in211(0),
.probe_in212(0),
.probe_in213(0),
.probe_in214(0),
.probe_in215(0),
.probe_in216(0),
.probe_in217(0),
.probe_in218(0),
.probe_in219(0),
.probe_in220(0),
.probe_in221(0),
.probe_in222(0),
.probe_in223(0),
.probe_in224(0),
.probe_in225(0),
.probe_in226(0),
.probe_in227(0),
.probe_in228(0),
.probe_in229(0),
.probe_in230(0),
.probe_in231(0),
.probe_in232(0),
.probe_in233(0),
.probe_in234(0),
.probe_in235(0),
.probe_in236(0),
.probe_in237(0),
.probe_in238(0),
.probe_in239(0),
.probe_in240(0),
.probe_in241(0),
.probe_in242(0),
.probe_in243(0),
.probe_in244(0),
.probe_in245(0),
.probe_in246(0),
.probe_in247(0),
.probe_in248(0),
.probe_in249(0),
.probe_in250(0),
.probe_in251(0),
.probe_in252(0),
.probe_in253(0),
.probe_in254(0),
.probe_in255(0),
.probe_out0(probe_out0),
.probe_out1(),
.probe_out2(),
.probe_out3(),
.probe_out4(),
.probe_out5(),
.probe_out6(),
.probe_out7(),
.probe_out8(),
.probe_out9(),
.probe_out10(),
.probe_out11(),
.probe_out12(),
.probe_out13(),
.probe_out14(),
.probe_out15(),
.probe_out16(),
.probe_out17(),
.probe_out18(),
.probe_out19(),
.probe_out20(),
.probe_out21(),
.probe_out22(),
.probe_out23(),
.probe_out24(),
.probe_out25(),
.probe_out26(),
.probe_out27(),
.probe_out28(),
.probe_out29(),
.probe_out30(),
.probe_out31(),
.probe_out32(),
.probe_out33(),
.probe_out34(),
.probe_out35(),
.probe_out36(),
.probe_out37(),
.probe_out38(),
.probe_out39(),
.probe_out40(),
.probe_out41(),
.probe_out42(),
.probe_out43(),
.probe_out44(),
.probe_out45(),
.probe_out46(),
.probe_out47(),
.probe_out48(),
.probe_out49(),
.probe_out50(),
.probe_out51(),
.probe_out52(),
.probe_out53(),
.probe_out54(),
.probe_out55(),
.probe_out56(),
.probe_out57(),
.probe_out58(),
.probe_out59(),
.probe_out60(),
.probe_out61(),
.probe_out62(),
.probe_out63(),
.probe_out64(),
.probe_out65(),
.probe_out66(),
.probe_out67(),
.probe_out68(),
.probe_out69(),
.probe_out70(),
.probe_out71(),
.probe_out72(),
.probe_out73(),
.probe_out74(),
.probe_out75(),
.probe_out76(),
.probe_out77(),
.probe_out78(),
.probe_out79(),
.probe_out80(),
.probe_out81(),
.probe_out82(),
.probe_out83(),
.probe_out84(),
.probe_out85(),
.probe_out86(),
.probe_out87(),
.probe_out88(),
.probe_out89(),
.probe_out90(),
.probe_out91(),
.probe_out92(),
.probe_out93(),
.probe_out94(),
.probe_out95(),
.probe_out96(),
.probe_out97(),
.probe_out98(),
.probe_out99(),
.probe_out100(),
.probe_out101(),
.probe_out102(),
.probe_out103(),
.probe_out104(),
.probe_out105(),
.probe_out106(),
.probe_out107(),
.probe_out108(),
.probe_out109(),
.probe_out110(),
.probe_out111(),
.probe_out112(),
.probe_out113(),
.probe_out114(),
.probe_out115(),
.probe_out116(),
.probe_out117(),
.probe_out118(),
.probe_out119(),
.probe_out120(),
.probe_out121(),
.probe_out122(),
.probe_out123(),
.probe_out124(),
.probe_out125(),
.probe_out126(),
.probe_out127(),
.probe_out128(),
.probe_out129(),
.probe_out130(),
.probe_out131(),
.probe_out132(),
.probe_out133(),
.probe_out134(),
.probe_out135(),
.probe_out136(),
.probe_out137(),
.probe_out138(),
.probe_out139(),
.probe_out140(),
.probe_out141(),
.probe_out142(),
.probe_out143(),
.probe_out144(),
.probe_out145(),
.probe_out146(),
.probe_out147(),
.probe_out148(),
.probe_out149(),
.probe_out150(),
.probe_out151(),
.probe_out152(),
.probe_out153(),
.probe_out154(),
.probe_out155(),
.probe_out156(),
.probe_out157(),
.probe_out158(),
.probe_out159(),
.probe_out160(),
.probe_out161(),
.probe_out162(),
.probe_out163(),
.probe_out164(),
.probe_out165(),
.probe_out166(),
.probe_out167(),
.probe_out168(),
.probe_out169(),
.probe_out170(),
.probe_out171(),
.probe_out172(),
.probe_out173(),
.probe_out174(),
.probe_out175(),
.probe_out176(),
.probe_out177(),
.probe_out178(),
.probe_out179(),
.probe_out180(),
.probe_out181(),
.probe_out182(),
.probe_out183(),
.probe_out184(),
.probe_out185(),
.probe_out186(),
.probe_out187(),
.probe_out188(),
.probe_out189(),
.probe_out190(),
.probe_out191(),
.probe_out192(),
.probe_out193(),
.probe_out194(),
.probe_out195(),
.probe_out196(),
.probe_out197(),
.probe_out198(),
.probe_out199(),
.probe_out200(),
.probe_out201(),
.probe_out202(),
.probe_out203(),
.probe_out204(),
.probe_out205(),
.probe_out206(),
.probe_out207(),
.probe_out208(),
.probe_out209(),
.probe_out210(),
.probe_out211(),
.probe_out212(),
.probe_out213(),
.probe_out214(),
.probe_out215(),
.probe_out216(),
.probe_out217(),
.probe_out218(),
.probe_out219(),
.probe_out220(),
.probe_out221(),
.probe_out222(),
.probe_out223(),
.probe_out224(),
.probe_out225(),
.probe_out226(),
.probe_out227(),
.probe_out228(),
.probe_out229(),
.probe_out230(),
.probe_out231(),
.probe_out232(),
.probe_out233(),
.probe_out234(),
.probe_out235(),
.probe_out236(),
.probe_out237(),
.probe_out238(),
.probe_out239(),
.probe_out240(),
.probe_out241(),
.probe_out242(),
.probe_out243(),
.probe_out244(),
.probe_out245(),
.probe_out246(),
.probe_out247(),
.probe_out248(),
.probe_out249(),
.probe_out250(),
.probe_out251(),
.probe_out252(),
.probe_out253(),
.probe_out254(),
.probe_out255()
)/* synthesis syn_noprune=1 */;
endmodule
|
// megafunction wizard: %Altera PLL v13.1%
// GENERATION: XML
// clock_pll.v
// Generated using ACDS version 13.1.1 166 at 2014.03.29.18:33:11
`timescale 1 ps / 1 ps
module clock_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
clock_pll_0002 clock_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="13.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="11.288659" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="49.772727" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : clock_pll.vo
// RELATED_FILES: clock_pll.v, clock_pll_0002.v
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1 ns / 1 ps
`include "xls/uncore_rtl/ice40/uart_transmitter.v"
`ifndef CLOCKS_PER_BAUD
`define CLOCKS_PER_BAUD 2
`endif
module uart_transmitter_two_bytes_test;
reg clk;
reg rst_n;
reg [7:0] tx_byte;
reg tx_byte_valid;
wire tx_byte_done;
wire tx;
integer i, start_time, first_byte_done_time, second_byte_done_time;
// #TicksPerClock waits for a single clock cycle.
localparam TicksPerClock = 2;
// Number of clock cycles that consitutes the time of a single baud.
localparam ClocksPerBaud = `CLOCKS_PER_BAUD;
uart_transmitter #(
.ClocksPerBaud(ClocksPerBaud)
) transmitter(
.clk (clk),
.rst_n (rst_n),
.tx_byte (tx_byte),
.tx_byte_valid (tx_byte_valid),
.tx_byte_done_out(tx_byte_done),
.tx_out (tx)
);
initial begin
#1 clk = 0;
forever #1 clk = !clk;
end
`include "xls/uncore_rtl/ice40/xls_assertions.inc"
// Make sure we finish after some reasonable amount of time.
initial begin
#1024 begin
$display("ERROR: timeout, simulation ran too long");
$finish;
end
end
initial begin
//$dumpfile("/tmp/uart_transmitter_two_bytes_test.vcd");
//$dumpvars(0, clk, rst_n, tx_byte, tx_byte_valid, tx_byte_done, tx,
// transmitter.tx_bitno, transmitter.tx_state,
// transmitter.tx_state_next, transmitter.tx_byte_done_next);
$display("Starting...\n");
$monitor("%t tx: %b tx_byte_done: %b", $time, tx, tx_byte_done);
rst_n <= 0;
tx_byte_valid <= 0;
tx_byte <= 'hff;
// Come out of reset after a few cycles.
#4 rst_n <= 1;
$dumpon;
#TicksPerClock;
for (i = 0; i < 10; i = i + 1) begin
xls_assert(1, tx, "idle");
#1;
end
// Present a byte to transmit after those few cycles of non-reset idle
// activity.
tx_byte <= 'h55;
tx_byte_valid <= 1;
#TicksPerClock tx_byte_valid <= 0;
#0.1 xls_assert(tx_byte_done, 0, "tx_byte_done 'h55 start");
// Wait for the start bit to show up.
wait (tx == 0);
// Note the start time!
start_time = $time;
// Check we wiggle 1-0 four times for the data.
repeat (4) begin
wait (tx == 1);
wait (tx == 0);
end
wait (transmitter.tx_state_next == 'b11); // Going to stop.
$display("About to stop @ %t", $time);
`ifdef PRESENT_BIT_EARLY
$display("Presenting bit early...");
// Present the next byte to transmit for one cycle while the stop bit is
// tranmitting.
#TicksPerClock;
$display("Presenting second byte @ %t", $time);
tx_byte <= 'haa;
tx_byte_valid <= 1;
#TicksPerClock tx_byte_valid <= 0;
`else
$display("Presenting bit late...");
wait (tx == 1); // stop bit
#((ClocksPerBaud-2)*TicksPerClock);
// Present the transfer request on the last cycle.
// Note we already observed one cycle of stop bit above.
tx_byte <= 'haa;
tx_byte_valid <= 1;
#(TicksPerClock+0.3) tx_byte_valid <= 0;
`endif
// Wait for it to say it's processing that second byte.
wait (transmitter.tx_state != 'b11);
first_byte_done_time = $time;
// Check we wiggle 0-1 four times for the data.
repeat (4) begin
wait (tx == 0);
wait (tx == 1);
end
// Wait for that second byte to be done.
wait (tx_byte_done == 1);
// Note when this second byte is done!
second_byte_done_time = $time;
$display("start: %t first_byte_done: %t second_byte_done: %t",
start_time, first_byte_done_time, second_byte_done_time);
xls_assert_int_eq(
10*ClocksPerBaud-1,
(first_byte_done_time-start_time)/2, "first byte cycles");
xls_assert_int_eq(
`ifdef PRESENT_BIT_EARLY
9*ClocksPerBaud,
`else
9*ClocksPerBaud+1,
`endif
(second_byte_done_time-first_byte_done_time)/2,
"second byte cycles");
#256 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_4_V
`define SKY130_FD_SC_LS__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_SYMBOL_V
`define SKY130_FD_SC_HD__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen640
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter CLKDV = 4,
parameter OUTPUT_SIZE =2
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire PULSE_CLK,
input wire PULSE_CLK160,
input wire PULSE_CLK320,
input wire EXT_START,
output wire [OUTPUT_SIZE-1:0] PULSE,
output wire DEBUG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
pulse_gen640_core #(
.ABUSWIDTH(ABUSWIDTH),
.CLKDV(CLKDV),
.OUTPUT_SIZE(OUTPUT_SIZE)
) i_pulse_gen640_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.PULSE_CLK(PULSE_CLK),
.PULSE_CLK160(PULSE_CLK160),
.PULSE_CLK320(PULSE_CLK320),
.EXT_START(EXT_START),
.PULSE(PULSE),
.DEBUG(DEBUG)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: uart6551.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
module glb6551(
RESET_N,
RX_CLK,
RX_CLK_IN,
XTAL_CLK_IN,
PH_2,
DI,
DO,
IRQ,
CS,
RW_N,
RS,
TXDATA_OUT,
RXDATA_IN,
RTS,
CTS,
DCD,
DTR,
DSR
);
input RESET_N;
output RX_CLK;
input RX_CLK_IN;
input XTAL_CLK_IN;
input PH_2;
input [7:0] DI;
output [7:0] DO;
output IRQ;
input [1:0] CS;
input [1:0] RS;
input RW_N;
output TXDATA_OUT;
input RXDATA_IN;
output RTS;
input CTS;
input DCD;
output DTR;
input DSR;
reg [7:0] TX_BUFFER;
reg [7:0] TX_REG;
wire [7:0] RX_BUFFER;
reg [7:0] RX_REG;
wire [7:0] STATUS_REG;
reg [7:0] CTL_REG;
reg [7:0] CMD_REG;
reg OVERRUN;
reg FRAME;
reg PARITY;
wire TX_DONE;
reg TX_DONE0;
reg TX_DONE1;
reg TX_START;
reg TDRE;
reg RDRF;
reg [10:0] TX_CLK_DIV;
wire TX_CLK;
wire RX_CLK;
wire FRAME_BUF;
wire [1:0] WORD_SELECT;
wire RESET_X;
wire STOP;
wire PARITY_ERR;
wire PAR_DIS;
reg [7:0] LOOPBACK;
wire RX_DATA;
wire TX_DATA;
reg RESET_NX;
reg TX_CLK_REG;
reg [1:0] READ_STATE;
wire GOT_DATA;
reg READY0;
reg READY1;
/*
Baud rate divisors
(for toggle of baud clock bit)
1 50 1152
2 75 768
3 110 524 -0.069396
4 135 428 -0.311526
5 150 384
6 300 192
7 600 96
8 1200 48
9 1800 32
A 2400 24
B 3600 16
C 4800 12
D 7200 8
E 9600 6
F 19200 3
*/
always @ (negedge XTAL_CLK_IN or negedge RESET_X)
begin
if(~RESET_X)
begin
TX_CLK_DIV <= 11'h000;
TX_CLK_REG <= 1'b0;
end
else
case (TX_CLK_DIV)
11'h000:
begin
TX_CLK_DIV <= 11'h001;
TX_CLK_REG <= ~TX_CLK_REG;
end
11'h002:
begin
if(CTL_REG[3:0] == 4'hF)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h003;
end
11'h005:
begin
if(CTL_REG[3:0] == 4'hE)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h006;
end
11'h007:
begin
if(CTL_REG[3:0] == 4'hD)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h008;
end
11'h00B:
begin
if(CTL_REG[3:0] == 4'hC)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h00C;
end
11'h00F:
begin
if(CTL_REG[3:0] == 4'hB)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h010;
end
11'h017:
begin
if(CTL_REG[3:0] == 4'hA)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h018;
end
11'h01F:
begin
if(CTL_REG[3:0] == 4'h9)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h020;
end
11'h02F:
begin
if(CTL_REG[3:0] == 4'h8)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h030;
end
11'h05F:
begin
if(CTL_REG[3:0] == 4'h7)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h060;
end
11'h0BF:
begin
if(CTL_REG[3:0] == 4'h6)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h0C0;
end
11'h17F:
begin
if(CTL_REG[3:0] == 4'h5)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h180;
end
11'h1AB:
begin
if(CTL_REG[3:0] == 4'h4)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h1AC;
end
11'h20B:
begin
if(CTL_REG[3:0] == 4'h3)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h20C;
end
11'h2FF:
begin
if(CTL_REG[3:0] == 4'h2)
TX_CLK_DIV <= 11'h000;
else
TX_CLK_DIV <= 11'h300;
end
11'h47F:
begin
TX_CLK_DIV <= 11'h000;
end
default:
begin
TX_CLK_DIV <= TX_CLK_DIV +1'b1;
end
endcase
end
assign TX_CLK = (CTL_REG[3:0] == 4'h0) ? XTAL_CLK_IN:
TX_CLK_REG;
assign RX_CLK = (CTL_REG[4] == 1'b0) ? RX_CLK_IN:
TX_CLK_REG;
assign RESET_X = RESET_NX ? 1'b0:
RESET_N;
always @ (negedge TX_CLK)
begin
LOOPBACK <= {LOOPBACK[6:0], TX_DATA}; //half bit time FIFO
end
assign RX_DATA = (CMD_REG[4:2] == 3'b100) ? LOOPBACK[7]:
RXDATA_IN;
assign TXDATA_OUT = (CMD_REG[4:2] == 3'b100) ? 1'b1:
TX_DATA;
assign STATUS_REG = {!IRQ, DSR, DCD, TDRE, RDRF, OVERRUN, FRAME, PARITY};
assign DO = (RS == 2'b00) ? RX_REG:
(RS == 2'b01) ? STATUS_REG:
(RS == 2'b10) ? CMD_REG:
CTL_REG;
assign IRQ = ({CMD_REG[1:0], RDRF} == 3'b011) ? 1'b0:
({CMD_REG[3:2], CMD_REG[0], TDRE} == 4'b0111) ? 1'b0: 1'b1;
assign RTS = (CMD_REG[3:2] == 2'b00);
assign DTR = ~CMD_REG[0];
assign STOP = (CTL_REG[7] == 1'b0) ? 1'b0: // Stop = 1
({CTL_REG[7:5], CMD_REG[5]} == 4'b1001) ? 1'b0: // Stop >1 but 8bit word and parity
1'b1; // Stop > 1
assign PAR_DIS = ~CMD_REG[5];
assign WORD_SELECT = CTL_REG[6:5];
always @ (negedge PH_2 or negedge RESET_N)
begin
if(!RESET_N)
RESET_NX <= 1'b1;
else
begin
if({RW_N, CS, RS} == 5'b00101) // Software RESET
RESET_NX <= 1'b1;
else
RESET_NX <= 1'b0;
end
end
always @ (negedge PH_2 or negedge RESET_X)
begin
if(!RESET_X)
begin
RDRF <= 1'b0;
READ_STATE <= 2'b00;
TX_BUFFER <= 8'h00;
CTL_REG <= 8'h00;
// Commador data sheet says reset value is 02
// but Apple Super Serial will not work unless it is 00
CMD_REG <= 8'h00;
TDRE <= 1'b1;
TX_START <= 1'b0;
RX_REG <= 8'h00;
OVERRUN <= 1'b0;
FRAME <= 1'b0;
PARITY <= 1'b0;
TX_DONE1 <= 1'b1;
TX_DONE0 <= 1'b1;
READY0 <= 1'b0;
READY1 <= 1'b0;
end
else
begin
TX_DONE1 <= TX_DONE0; // sync TX_DONE with E clock for metastability?
TX_DONE0 <= TX_DONE;
READY1 <= READY0;
READY0 <= GOT_DATA;
case (READ_STATE)
2'b00:
begin
if(READY1) //Stop bit
begin
RDRF <= 1'b1;
READ_STATE <= 2'b01;
RX_REG <= RX_BUFFER;
OVERRUN <= 1'b0;
PARITY <= (PARITY_ERR & !PAR_DIS);
FRAME <= FRAME_BUF;
end
end
2'b01:
begin
if({RW_N, CS, RS} == 5'b10100)
begin
RDRF <= 1'b0;
READ_STATE <= 2'b10;
PARITY <= 1'b0;
OVERRUN <= 1'b0;
FRAME <= 1'b0;
end
else
begin
if(~READY1)
READ_STATE <= 2'b11;
end
end
2'b10:
begin
if(~READY1)
READ_STATE <= 2'b00;
end
2'b11:
begin
if({RW_N, CS, RS} == 5'b10100)
begin
RDRF <= 1'b0;
READ_STATE <= 2'b00;
PARITY <= 1'b0;
OVERRUN <= 1'b0;
FRAME <= 1'b0;
end
else
begin
if(READY1)
begin
RDRF <= 1'b1;
READ_STATE <= 2'b01;
OVERRUN <= 1'b1;
PARITY <= (PARITY_ERR & !PAR_DIS);
FRAME <= FRAME_BUF;
RX_REG <= RX_BUFFER;
end
end
end
endcase
if({RW_N, CS, RS} == 5'b00100) // Write TX data register
TX_REG <= DI;
if({RW_N, CS, RS} == 5'b00110) // Write CMD register
CMD_REG <= DI;
if({RW_N, CS, RS} == 5'b00111) // Write CTL register
CTL_REG <= DI;
if(~TDRE & TX_DONE1 & ~TX_START & ~(CS == 2'b01))
begin
TX_BUFFER <= TX_REG;
TDRE <= 1'b1;
TX_START <= 1'b1;
end
else
begin
if({RW_N, CS, RS} == 5'b00100) // Write TX data register
TDRE <= 1'b0;
if(~TX_DONE1)
TX_START <= 1'b0;
end
end
end
uart51_tx tx(
.RESET_N(RESET_X),
.BAUD_CLK(TX_CLK),
.TX_DATA(TX_DATA),
.TX_START(TX_START),
.TX_DONE(TX_DONE),
.TX_STOP(STOP),
.TX_WORD(WORD_SELECT),
.TX_PAR_DIS(PAR_DIS),
.TX_PARITY(CMD_REG[7:6]),
.CTS(CTS),
.TX_BUFFER(TX_BUFFER)
);
uart51_rx rx(
.RESET_N(RESET_X),
.BAUD_CLK(RX_CLK),
.RX_DATA(RX_DATA),
.RX_BUFFER(RX_BUFFER),
.RX_WORD(WORD_SELECT),
.RX_PAR_DIS(PAR_DIS),
.RX_PARITY(CMD_REG[7:6]),
.PARITY_ERR(PARITY_ERR),
.FRAME(FRAME_BUF),
.READY(GOT_DATA)
);
endmodule
|
`timescale 1ns / 1ps
module multiplier_8bit_tb( );
reg [7:0] x0;
reg [7:0] y0;
wire [15:0] mult_out;
reg status;
multiplier_8bit DUT (
.\a_in[0] (x0[0]), .\a_in[1] (x0[1]), .\a_in[2] (x0[2]), .\a_in[3] (x0[3]), .\a_in[4] (x0[4]), .\a_in[5] (x0[5]), .\a_in[6] (x0[6]), .\a_in[7] (x0[7]), .\b_in[0] (y0[0]), .\b_in[1] (y0[1]), .\b_in[2] (y0[2]), .\b_in[3] (y0[3]), .\b_in[4] (y0[4]), .\b_in[5] (y0[5]), .\b_in[6] (y0[6]), .\b_in[7] (y0[7]), .\prod[0] (mult_out[0]), .\prod[1] (mult_out[1]), .\prod[2] (mult_out[2]), .\prod[3] (mult_out[3]), .\prod[4] (mult_out[4]), .\prod[5] (mult_out[5]), .\prod[6] (mult_out[6]), .\prod[7] (mult_out[7]), .\prod[8] (mult_out[8]), .\prod[9] (mult_out[9]), .\prod[10] (mult_out[10]), .\prod[11] (mult_out[11]), .\prod[12] (mult_out[12]), .\prod[13] (mult_out[13]), .\prod[14] (mult_out[14]), .\prod[15] (mult_out[15]));
initial begin
status = 0;
x0 =0;
y0 =0;
#50 x0 = 25;
#20 y0 = 93;
#10
if(mult_out == 2325)
$display("Valid Output");
else begin
$display("FAIL");
$fatal(2,"Mult output does not match");
status =1;
end
#50 y0 = 87;
#10
if(mult_out == 2175)
$display("Valid Output");
else
begin
$display("FAIL");
$fatal(2,"Mult output does not match");
status =1;
end
end
initial begin
$dumpfile("multiplier_8bit_tb.vcd");
$dumpvars(0,multiplier_8bit_tb);
$sdf_annotate("multiplier_8bit_post_synthesis.sdf", DUT);
$display("\t\ttime,\tx0,\ty0,\tmult_out");
$monitor("%d :\t[%d] X\t[%d] \t= [%d]",$time,x0,y0,mult_out);
if(status == 1'b0)
$display("PASS");
end
initial
#500 $finish;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scbuf_sig_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module scbuf_sig_buf (/*AUTOARG*/
// Outputs
scbuf_scdata_fbdecc_c4, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
scbuf_sctag_ev_uerr_r5, scbuf_sctag_ev_cerr_r5,
// Inputs
scbuf_scdata_fbdecc_c4_pb, scbuf_dram_wr_data_r5_pb,
scbuf_dram_data_vld_r5_pb, scbuf_dram_data_mecc_r5_pb,
scbuf_sctag_ev_uerr_r5_pb, scbuf_sctag_ev_cerr_r5_pb
);
output [623:0] scbuf_scdata_fbdecc_c4;
output [63:0] scbuf_dram_wr_data_r5;
output scbuf_dram_data_vld_r5;
output scbuf_dram_data_mecc_r5;
output scbuf_sctag_ev_uerr_r5;
output scbuf_sctag_ev_cerr_r5;
input [623:0] scbuf_scdata_fbdecc_c4_pb;
input [63:0] scbuf_dram_wr_data_r5_pb;
input scbuf_dram_data_vld_r5_pb;
input scbuf_dram_data_mecc_r5_pb;
input scbuf_sctag_ev_uerr_r5_pb;
input scbuf_sctag_ev_cerr_r5_pb;
assign scbuf_scdata_fbdecc_c4[623:0] = scbuf_scdata_fbdecc_c4_pb[623:0];
assign scbuf_dram_wr_data_r5[63:0] = scbuf_dram_wr_data_r5_pb[63:0];
assign scbuf_dram_data_vld_r5 = scbuf_dram_data_vld_r5_pb;
assign scbuf_dram_data_mecc_r5 = scbuf_dram_data_mecc_r5_pb;
assign scbuf_sctag_ev_uerr_r5 = scbuf_sctag_ev_uerr_r5_pb;
assign scbuf_sctag_ev_cerr_r5 = scbuf_sctag_ev_cerr_r5_pb;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/15/2015
// Summary: The overall top module for Lab 4 Part 2
//////////////////////////////////////////////////////////////////////////////////
module lab4part2overall(NextAddress,Reset,DataIn,Clock,SendWrite,Mode,Locked,Display,Transistors,RAMaddress,Transmitting,tx);
input NextAddress, Reset, Clock, SendWrite, Mode;
input [6:0] DataIn;
output Locked, Transmitting, tx;
output [7:0] Display;
output [3:0] Transistors;
output [5:0] RAMaddress;
wire DebouncedNextAddress;
wire OneshotNextAddress;
wire DebouncedSendWrite;
wire OneshotSendWrite;
wire [6:0] RAMDout;
wire RAMShouldRead;
wire [7:0] Bit3_0out;
wire [7:0] Bit7_4out;
wire ClockOut;
wire [5:0] ModeControllerNumberOfChars;
wire write_to_uart;
wire [5:0] UpdatedRAMAddress;
wire [5:0] SendCharsRAMAddress;
wire tx_buffer_full;
wire tx_buffer_half_full;
wire UARTClock;
parameter baudRate = 20'd38400;
parameter clockFrequency = 30'd70000000;
Clock70MHz Clock70MHzUnit(Clock,ClockOut,Locked);
//module DebouncerWithoutLatch(InputPulse, DebouncedOuput, Reset, CLOCK) ;
DebouncerWithoutLatch NextDebounceUnit(NextAddress,DebouncedNextAddress,Reset,ClockOut);
ClockedOneShot NextOneShot(DebouncedNextAddress,OneshotNextAddress,Reset,ClockOut);
RAM40x7bits RAMUnit(RAMaddress,DataIn,ClockOut,Reset,RAMShouldRead,RAMDout);
HEXto7Segment Bit3_0Unit(RAMDout[3:0],Bit3_0out);
HEXto7Segment Bit7_4Unit({1'b0,RAMDout[6:4]},Bit7_4out);
DebouncerWithoutLatch SendDebounceUnit(SendWrite,DebouncedSendWrite,Reset,ClockOut);
ClockedOneShot SendOneShot(DebouncedSendWrite,OneshotSendWrite,Reset,ClockOut);
SevenSegDriver DisplayUnit(8'b11111111,8'b11111111,Bit7_4out,Bit3_0out,Display,Reset,ClockOut,Transistors);
RAMAddressUpdate UpdateAddress(ClockOut,OneshotNextAddress,Reset,UpdatedRAMAddress);
ModeController ModeUnit(DataIn,SendCharsRAMAddress,UpdatedRAMAddress,Mode,OneshotSendWrite,ModeControllerNumberOfChars,RAMaddress,RAMShouldRead);
SendChars SendCharsUnit(ModeControllerNumberOfChars,ClockOut,Reset,Mode&OneshotSendWrite,tx_buffer_full,UARTClock,SendCharsRAMAddress,Transmitting,write_to_uart);
uart_tx TransmitUnit({1'b0,RAMDout},write_to_uart,1'b0,UARTClock,tx,tx_buffer_full,tx_buffer_half_full,ClockOut);
BaudRateGenerator BaudRateUnit(UARTClock,Reset,ClockOut,baudRate,clockFrequency);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O311A_FUNCTIONAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_FUNCTIONAL_V |
module build_tree (
input wire in,
output [15:0] reg out,
output [3:0] reg out_addr,
output reg out_valid,
output reg done,
input wire CLK,
input wire Reset,
input wire EN
);
// the len = 4
// This means that there is no need for the initial 6 bits
// These 6 bits would normally tell the length of the values
// Our value length is always 4
reg [15:0] code;
reg [3:0] leaf;
reg [4:0] leaf_valid_sh;
reg [4:0] done_acc;
assign out_valid = leaf_valid[0];
always @ (negedge Reset or posedge CLK) begin
if (~Reset) begin
out <= 16'b0;
out_addr <= 4'b0;
out_valid <= 1'b0;
done <= 1'b0;
code <= 16'b0;
leaf; <= 4'b0;
leaf_valid_sh <= 5'b0;
done_acc <= 5'b0;
end
else begin
if (~leaf_valid[4]) begin
// We have not found a leaf
// We are traversing the tree
if(~in) begin
leaf_valid_sh <= 5'b0;
out <= 16'b0;
code <= {code[14:1], 1'b0};
end
else begin
// We have discovered a new leaf
// Now it is time to enter it in
leaf_valid_sh <= 5'b10000;
out <= code;
casex (code)
16'bxxxxxxxxxxxxxxx0 : code <= {00'b0, code[15:01], 1'b1};
16'bxxxxxxxxxxxxxx01 : code <= {01'b0, code[15:02], 1'b1};
16'bxxxxxxxxxxxxx011 : code <= {02'b0, code[15:03], 1'b1};
16'bxxxxxxxxxxxx0111 : code <= {03'b0, code[15:04], 1'b1};
16'bxxxxxxxxxxx01111 : code <= {04'b0, code[15:05], 1'b1};
16'bxxxxxxxxxx011111 : code <= {05'b0, code[15:06], 1'b1};
16'bxxxxxxxxx0111111 : code <= {06'b0, code[15:07], 1'b1};
16'bxxxxxxxx01111111 : code <= {07'b0, code[15:08], 1'b1};
16'bxxxxxxx011111111 : code <= {08'b0, code[15:09], 1'b1};
16'bxxxxxx0111111111 : code <= {09'b0, code[15:10], 1'b1};
16'bxxxxx01111111111 : code <= {10'b0, code[15:11], 1'b1};
16'bxxxx011111111111 : code <= {11'b0, code[15:12], 1'b1};
16'bxxx0111111111111 : code <= {12'b0, code[15:13], 1'b1};
16'bxx01111111111111 : code <= {13'b0, code[15:14], 1'b1};
16'bx011111111111111 : code <= {14'b0, code[15:15], 1'b1};
16'b0111111111111111 : code <= 16'h1;
end
end
else begin
// We have found a leaf
if(~leaf_valid[0]) begin
// Still entering in the leaf
leaf_valid <= {1'b1, leaf_valid[4:1]};
out <= out;
end
else begin
// Finished entering in the leaf
// Go back to tree traversal
done_acc <= done_acc + 1;
end
end
end
end
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : gtx_drp_chanalign_fix_3752_v6.v
// Version : 2.3
//--
//-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module GTX_DRP_CHANALIGN_FIX_3752_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [7:0] daddr,
output reg [3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
localparam DRP_IDLE_FTS = 1;
localparam DRP_IDLE_TS1 = 2;
localparam DRP_RESET = 3;
localparam DRP_WRITE_FTS = 6;
localparam DRP_WRITE_DONE_FTS = 7;
localparam DRP_WRITE_TS1 = 8;
localparam DRP_WRITE_DONE_TS1 = 9;
localparam DRP_COM = 10'b0110111100;
localparam DRP_FTS = 10'b0100111100;
localparam DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if ( ~Reset_n ) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate=drpstate;
next_daddr=daddr;
den=0;
din=0;
dwe=0;
case(drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET : begin
next_drpstate= DRP_WRITE_TS1;
next_daddr=8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFD3C;
else if(daddr==8'h9)
din=16'hC53C;
else if(daddr==8'hA)
din=16'hFDBC;
else if(daddr==8'hB)
din=16'h853C;
next_drpstate=DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_FTS;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=daddr+1'b1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS : begin
if(write_ts1_gated) begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1 : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFC4A;
else if(daddr==8'h9)
din=16'hDC4A; //CHANGE
else if(daddr==8'hA)
din=16'hC04A; //CHANGE
else if(daddr==8'hB)
din=16'h85BC;
next_drpstate=DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1 : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_TS1;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=daddr+1'b1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1 : begin
if(write_fts_gated) begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=8'h8;
end
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H ,
inout PAD_A_ESD_1_H ,
inout PAD_A_NOESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ANALOG_EN ,
input ANALOG_POL ,
input ANALOG_SEL ,
input [2:0] DM ,
input ENABLE_H ,
input ENABLE_INP_H ,
input ENABLE_VDDA_H ,
input ENABLE_VDDIO ,
input ENABLE_VSWITCH_H,
input HLD_H_N ,
input HLD_OVR ,
input HYS_TRIM ,
input [1:0] IB_MODE_SEL ,
input OE_N ,
input [1:0] SLEW_CTL ,
//# {{power|Power}}
input VTRIP_SEL ,
output TIE_HI_ESD ,
input VINREF ,
output TIE_LO_ESD
);
// Voltage supply signals
supply1 VDDIO ;
supply1 VDDIO_Q;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "wasca_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2560,
the_altsyncram.numwords_a = 2560,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
module pixcopy (
input clk,
input rdclk,
input [7:0] data,
input acapture,
output reg write,
output reg [15:0] wrdata,
output reg [9:0] horiz_count
);
reg uphalf;
reg [7:0] upbyte;
reg loaded;
always @(posedge clk)
begin
if (write) begin
write <= 1'b0;
end
if (!acapture) begin
uphalf <= 1'b1;
loaded <= 1'b0;
write <= 1'b0;
horiz_count<= 0;
end else begin
if (rdclk) begin
if (!loaded) begin
if (uphalf) begin
upbyte <= data;
uphalf <= 1'b0;
loaded <= 1'b1;
end else begin
horiz_count <= horiz_count + 1'b1;
wrdata <= {upbyte, data};
uphalf <= 1'b1;
write <= 1'b1;
loaded <= 1'b1;
end
end
end else begin
loaded <= 1'b0;
end
end
end
endmodule
module vline_capture (
input ahref,
input avsync,
output acapture,
output newframe
);
reg [9:0] linecount;
reg [2:0] state;
parameter
ABOVE_SKIP = 3'h0,
HOTLINE = 3'h1,
LINEOMIT = 3'h2;
assign acapture = ((state == HOTLINE) & ahref);
function [2:0] nextstate;
input [2:0] state;
input [9:0] linecount;
begin
case (state)
ABOVE_SKIP:
begin
if (linecount == 10'h0f4) begin
nextstate = HOTLINE;
end else begin
nextstate = state;
end
end
HOTLINE:
nextstate = LINEOMIT;
LINEOMIT:
begin
if (linecount == 10'h00a) begin
nextstate = HOTLINE;
end else begin
nextstate = state;
end
end
default:
nextstate = state;
endcase
end
endfunction
always @(posedge avsync or posedge ahref)
begin
if (avsync) begin
linecount <= 8'h00;
state <= ABOVE_SKIP;
end else begin
linecount <= (state == ABOVE_SKIP || state == LINEOMIT)
? linecount + 10'b1
: 10'h000;
state <= nextstate(state, linecount);
end
end
endmodule
|
//////////////////////////////////////////////////////////////
// //
// This testbench has been generated by the Verilog //
// testbench generator . //
// Copyright (c) 2012 Kanai L. Ghosh //
// Contact [email protected] for support/info.//
// //
// //
//////////////////////////////////////////////////////////////
//
//
// Generated by : sonals on 4/26/12 1:08 PM
//
//
`timescale 1ns / 1ps
module test;
reg [0:72] indata_array;
reg sysClk;
reg reset;
wire bench_TILE0_REFCLK_PAD_N_IN;
wire bench_TILE0_REFCLK_PAD_P_IN;
wire bench_TILE1_REFCLK_PAD_N_IN;
wire bench_TILE1_REFCLK_PAD_P_IN;
wire bench_TILE2_REFCLK_PAD_N_IN;
wire bench_TILE2_REFCLK_PAD_P_IN;
wire bench_TILE3_REFCLK_PAD_N_IN;
wire bench_TILE3_REFCLK_PAD_P_IN;
wire bench_GTPRESET_IN;
wire [7:0] bench_RXN_IN;
wire [7:0] bench_RXP_IN;
wire [7:0] bench_TXN_OUT;
wire [7:0] bench_TXP_OUT;
wire bench_phy_rst_pad_0_o;
wire [7:0] bench_DataOut_pad_0_o;
wire bench_TxValid_pad_0_o;
wire bench_TxReady_pad_0_i;
wire [7:0] bench_DataIn_pad_0_i;
wire bench_RxValid_pad_0_i;
wire bench_RxActive_pad_0_i;
wire bench_RxError_pad_0_i;
wire bench_XcvSelect_pad_0_o;
wire bench_TermSel_pad_0_o;
wire bench_SuspendM_pad_0_o;
wire [1:0] bench_LineState_pad_0_i;
wire [1:0] bench_OpMode_pad_0_o;
wire bench_usb_vbus_pad_0_i;
wire bench_VControl_Load_pad_0_o;
wire [3:0] bench_VControl_pad_0_o;
wire [7:0] bench_VStatus_pad_0_i;
wire bench_phy_rst_pad_1_o;
wire [7:0] bench_DataOut_pad_1_o;
wire bench_TxValid_pad_1_o;
wire bench_TxReady_pad_1_i;
wire [7:0] bench_DataIn_pad_1_i;
wire bench_RxValid_pad_1_i;
wire bench_RxActive_pad_1_i;
wire bench_RxError_pad_1_i;
wire bench_XcvSelect_pad_1_o;
wire bench_TermSel_pad_1_o;
wire bench_SuspendM_pad_1_o;
wire [1:0] bench_LineState_pad_1_i;
wire [1:0] bench_OpMode_pad_1_o;
wire bench_usb_vbus_pad_1_i;
wire bench_VControl_Load_pad_1_o;
wire [3:0] bench_VControl_pad_1_o;
wire [7:0] bench_VStatus_pad_1_i;
wire bench_or1200_clmode;
wire bench_or1200_pic_ints;
wire [3:0] bench_or1200_pm_out;
assign bench_sysClk = sysClk;
assign bench_reset = reset;
assign bench_TILE0_REFCLK_PAD_N_IN = indata_array[0:0];
assign bench_TILE0_REFCLK_PAD_P_IN = indata_array[1:1];
assign bench_TILE1_REFCLK_PAD_N_IN = indata_array[2:2];
assign bench_TILE1_REFCLK_PAD_P_IN = indata_array[3:3];
assign bench_TILE2_REFCLK_PAD_N_IN = indata_array[4:4];
assign bench_TILE2_REFCLK_PAD_P_IN = indata_array[5:5];
assign bench_TILE3_REFCLK_PAD_N_IN = indata_array[6:6];
assign bench_TILE3_REFCLK_PAD_P_IN = indata_array[7:7];
assign bench_GTPRESET_IN = indata_array[8:8];
assign bench_RXN_IN = indata_array[9:16];
assign bench_RXP_IN = indata_array[17:24];
assign bench_TxReady_pad_0_i = indata_array[25:25];
assign bench_DataIn_pad_0_i = indata_array[26:33];
assign bench_RxValid_pad_0_i = indata_array[34:34];
assign bench_RxActive_pad_0_i = indata_array[35:35];
assign bench_RxError_pad_0_i = indata_array[36:36];
assign bench_LineState_pad_0_i = indata_array[37:38];
assign bench_usb_vbus_pad_0_i = indata_array[39:39];
assign bench_VStatus_pad_0_i = indata_array[40:47];
assign bench_TxReady_pad_1_i = indata_array[48:48];
assign bench_DataIn_pad_1_i = indata_array[49:56];
assign bench_RxValid_pad_1_i = indata_array[57:57];
assign bench_RxActive_pad_1_i = indata_array[58:58];
assign bench_RxError_pad_1_i = indata_array[59:59];
assign bench_LineState_pad_1_i = indata_array[60:61];
assign bench_usb_vbus_pad_1_i = indata_array[62:62];
assign bench_VStatus_pad_1_i = indata_array[63:70];
assign bench_or1200_clmode = indata_array[71:71];
assign bench_or1200_pic_ints = indata_array[72:72];
initial
begin
#0 sysClk = 1'b0;
end
always
begin
#5 sysClk = !sysClk;
end
initial
begin
#0 reset = 1'b0;
end
always
begin
#500 reset = !reset;
#5 reset = !reset;
end
always
begin : stim
reg [0:31] r1;
reg [0:31] r2;
reg [0:7] r3;
r1 = $random;
r2 = $random;
r3 = $random;
#5 indata_array = {r1, r2, r3};
end
top inst(
.sysClk(bench_sysClk),
.reset(bench_reset),
.TILE0_REFCLK_PAD_N_IN(bench_TILE0_REFCLK_PAD_N_IN),
.TILE0_REFCLK_PAD_P_IN(bench_TILE0_REFCLK_PAD_P_IN),
.TILE1_REFCLK_PAD_N_IN(bench_TILE1_REFCLK_PAD_N_IN),
.TILE1_REFCLK_PAD_P_IN(bench_TILE1_REFCLK_PAD_P_IN),
.TILE2_REFCLK_PAD_N_IN(bench_TILE2_REFCLK_PAD_N_IN),
.TILE2_REFCLK_PAD_P_IN(bench_TILE2_REFCLK_PAD_P_IN),
.TILE3_REFCLK_PAD_N_IN(bench_TILE3_REFCLK_PAD_N_IN),
.TILE3_REFCLK_PAD_P_IN(bench_TILE3_REFCLK_PAD_P_IN),
.GTPRESET_IN(bench_GTPRESET_IN),
.RXN_IN(bench_RXN_IN),
.RXP_IN(bench_RXP_IN),
.TXN_OUT(bench_TXN_OUT),
.TXP_OUT(bench_TXP_OUT),
.phy_rst_pad_0_o(bench_phy_rst_pad_0_o),
.DataOut_pad_0_o(bench_DataOut_pad_0_o),
.TxValid_pad_0_o(bench_TxValid_pad_0_o),
.TxReady_pad_0_i(bench_TxReady_pad_0_i),
.DataIn_pad_0_i(bench_DataIn_pad_0_i),
.RxValid_pad_0_i(bench_RxValid_pad_0_i),
.RxActive_pad_0_i(bench_RxActive_pad_0_i),
.RxError_pad_0_i(bench_RxError_pad_0_i),
.XcvSelect_pad_0_o(bench_XcvSelect_pad_0_o),
.TermSel_pad_0_o(bench_TermSel_pad_0_o),
.SuspendM_pad_0_o(bench_SuspendM_pad_0_o),
.LineState_pad_0_i(bench_LineState_pad_0_i),
.OpMode_pad_0_o(bench_OpMode_pad_0_o),
.usb_vbus_pad_0_i(bench_usb_vbus_pad_0_i),
.VControl_Load_pad_0_o(bench_VControl_Load_pad_0_o),
.VControl_pad_0_o(bench_VControl_pad_0_o),
.VStatus_pad_0_i(bench_VStatus_pad_0_i),
.phy_rst_pad_1_o(bench_phy_rst_pad_1_o),
.DataOut_pad_1_o(bench_DataOut_pad_1_o),
.TxValid_pad_1_o(bench_TxValid_pad_1_o),
.TxReady_pad_1_i(bench_TxReady_pad_1_i),
.DataIn_pad_1_i(bench_DataIn_pad_1_i),
.RxValid_pad_1_i(bench_RxValid_pad_1_i),
.RxActive_pad_1_i(bench_RxActive_pad_1_i),
.RxError_pad_1_i(bench_RxError_pad_1_i),
.XcvSelect_pad_1_o(bench_XcvSelect_pad_1_o),
.TermSel_pad_1_o(bench_TermSel_pad_1_o),
.SuspendM_pad_1_o(bench_SuspendM_pad_1_o),
.LineState_pad_1_i(bench_LineState_pad_1_i),
.OpMode_pad_1_o(bench_OpMode_pad_1_o),
.usb_vbus_pad_1_i(bench_usb_vbus_pad_1_i),
.VControl_Load_pad_1_o(bench_VControl_Load_pad_1_o),
.VControl_pad_1_o(bench_VControl_pad_1_o),
.VStatus_pad_1_i(bench_VStatus_pad_1_i),
.or1200_clmode(bench_or1200_clmode),
.or1200_pic_ints(bench_or1200_pic_ints),
.or1200_pm_out(bench_or1200_pm_out)
);
initial
begin
// $monitor($time, " reset = %b, sysClk = %b, TILE0_REFCLK_PAD_N_IN = %b , TILE0_REFCLK_PAD_P_IN = %b , TILE1_REFCLK_PAD_N_IN = %b , TILE1_REFCLK_PAD_P_IN = %b , TILE2_REFCLK_PAD_N_IN = %b , TILE2_REFCLK_PAD_P_IN = %b , TILE3_REFCLK_PAD_N_IN = %b , TILE3_REFCLK_PAD_P_IN = %b , GTPRESET_IN = %b , RXN_IN = %b , RXP_IN = %b , TxReady_pad_0_i = %b , DataIn_pad_0_i = %b , RxValid_pad_0_i = %b , RxActive_pad_0_i = %b , RxError_pad_0_i = %b , LineState_pad_0_i = %b , usb_vbus_pad_0_i = %b , VStatus_pad_0_i = %b , TxReady_pad_1_i = %b , DataIn_pad_1_i = %b , RxValid_pad_1_i = %b , RxActive_pad_1_i = %b , RxError_pad_1_i = %b , LineState_pad_1_i = %b , usb_vbus_pad_1_i = %b , VStatus_pad_1_i = %b , or1200_clmode = %b , or1200_pic_ints = %b , TXN_OUT = %b , TXP_OUT = %b , phy_rst_pad_0_o = %b , DataOut_pad_0_o = %b , TxValid_pad_0_o = %b , XcvSelect_pad_0_o = %b , TermSel_pad_0_o = %b , SuspendM_pad_0_o = %b , OpMode_pad_0_o = %b , VControl_Load_pad_0_o = %b , VControl_pad_0_o = %b , phy_rst_pad_1_o = %b , DataOut_pad_1_o = %b , TxValid_pad_1_o = %b , XcvSelect_pad_1_o = %b , TermSel_pad_1_o = %b , SuspendM_pad_1_o = %b , OpMode_pad_1_o = %b , VControl_Load_pad_1_o = %b , VControl_pad_1_o = %b , or1200_pm_out = %b ",
// bench_reset, bench_sysClk, bench_TILE0_REFCLK_PAD_N_IN, bench_TILE0_REFCLK_PAD_P_IN, bench_TILE1_REFCLK_PAD_N_IN, bench_TILE1_REFCLK_PAD_P_IN, bench_TILE2_REFCLK_PAD_N_IN, bench_TILE2_REFCLK_PAD_P_IN, bench_TILE3_REFCLK_PAD_N_IN, bench_TILE3_REFCLK_PAD_P_IN, bench_GTPRESET_IN, bench_RXN_IN, bench_RXP_IN, bench_TxReady_pad_0_i, bench_DataIn_pad_0_i, bench_RxValid_pad_0_i, bench_RxActive_pad_0_i, bench_RxError_pad_0_i, bench_LineState_pad_0_i, bench_usb_vbus_pad_0_i, bench_VStatus_pad_0_i, bench_TxReady_pad_1_i, bench_DataIn_pad_1_i, bench_RxValid_pad_1_i, bench_RxActive_pad_1_i, bench_RxError_pad_1_i, bench_LineState_pad_1_i, bench_usb_vbus_pad_1_i, bench_VStatus_pad_1_i, bench_or1200_clmode, bench_or1200_pic_ints, bench_TXN_OUT, bench_TXP_OUT, bench_phy_rst_pad_0_o, bench_DataOut_pad_0_o, bench_TxValid_pad_0_o, bench_XcvSelect_pad_0_o, bench_TermSel_pad_0_o, bench_SuspendM_pad_0_o, bench_OpMode_pad_0_o, bench_VControl_Load_pad_0_o, bench_VControl_pad_0_o, bench_phy_rst_pad_1_o, bench_DataOut_pad_1_o, bench_TxValid_pad_1_o, bench_XcvSelect_pad_1_o, bench_TermSel_pad_1_o, bench_SuspendM_pad_1_o, bench_OpMode_pad_1_o, bench_VControl_Load_pad_1_o, bench_VControl_pad_1_o, bench_or1200_pm_out);
end
initial
begin
#5000 $display("TEST PASSED");
$finish;
end
endmodule
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 ;
output n2048 , n2049 ;
wire n4100 , n4101 , n4102 , n4103 , n4104 , n4105 , n4106 , n4107 , n4108 ,
n4109 , n4110 , n4111 , n4112 , n4113 , n4114 , n4115 , n4116 , n4117 , n4118 ,
n4119 , n4120 , n4121 , n4122 , n4123 , n4124 , n4125 , n4126 , n4127 , n4128 ,
n4129 , n4130 , n4131 , n4132 , n4133 , n4134 , n4135 , n4136 , n4137 , n4138 ,
n4139 , n4140 , n4141 , n4142 , n4143 , n4144 , n4145 , n4146 , n4147 , n4148 ,
n4149 , n4150 , n4151 , n4152 , n4153 , n4154 , n4155 , n4156 , n4157 , n4158 ,
n4159 , n4160 , n4161 , n4162 , n4163 , n4164 , n4165 , n4166 , n4167 , n4168 ,
n4169 , n4170 , n4171 , n4172 , n4173 , n4174 , n4175 , n4176 , n4177 , n4178 ,
n4179 , n4180 , n4181 , n4182 , n4183 , n4184 , n4185 , n4186 , n4187 , n4188 ,
n4189 , n4190 , n4191 , n4192 , n4193 , n4194 , n4195 , n4196 , n4197 , n4198 ,
n4199 , n4200 , n4201 , n4202 , n4203 , n4204 , n4205 , n4206 , n4207 , n4208 ,
n4209 , n4210 , n4211 , n4212 , n4213 , n4214 , n4215 , n4216 , n4217 , n4218 ,
n4219 , n4220 , n4221 , n4222 , n4223 , n4224 , n4225 , n4226 , n4227 , n4228 ,
n4229 , n4230 , n4231 , n4232 , n4233 , n4234 , n4235 , n4236 , n4237 , n4238 ,
n4239 , n4240 , n4241 , n4242 , n4243 , n4244 , n4245 , n4246 , n4247 , n4248 ,
n4249 , n4250 , n4251 , n4252 , n4253 , n4254 , n4255 , n4256 , n4257 , n4258 ,
n4259 , n4260 , n4261 , n4262 , n4263 , n4264 , n4265 , n4266 , n4267 , n4268 ,
n4269 , n4270 , n4271 , n4272 , n4273 , n4274 , n4275 , n4276 , n4277 , n4278 ,
n4279 , n4280 , n4281 , n4282 , n4283 , n4284 , n4285 , n4286 , n4287 , n4288 ,
n4289 , n4290 , n4291 , n4292 , n4293 , n4294 , n4295 , n4296 , n4297 , n4298 ,
n4299 , n4300 , n4301 , n4302 , n4303 , n4304 , n4305 , n4306 , n4307 , n4308 ,
n4309 , n4310 , n4311 , n4312 , n4313 , n4314 , n4315 , n4316 , n4317 , n4318 ,
n4319 , n4320 , n4321 , n4322 , n4323 , n4324 , n4325 , n4326 , n4327 , n4328 ,
n4329 , n4330 , n4331 , n4332 , n4333 , n4334 , n4335 , n4336 , n4337 , n4338 ,
n4339 , n4340 , n4341 , n4342 , n4343 , n4344 , n4345 , n4346 , n4347 , n4348 ,
n4349 , n4350 , n4351 , n4352 , n4353 , n4354 , n4355 , n4356 , n4357 , n4358 ,
n4359 , n4360 , n4361 , n4362 , n4363 , n4364 , n4365 , n4366 , n4367 , n4368 ,
n4369 , n4370 , n4371 , n4372 , n4373 , n4374 , n4375 , n4376 , n4377 , n4378 ,
n4379 , n4380 , n4381 , n4382 , n4383 , n4384 , n4385 , n4386 , n4387 , n4388 ,
n4389 , n4390 , n4391 , n4392 , n4393 , n4394 , n4395 , n4396 , n4397 , n4398 ,
n4399 , n4400 , n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 ,
n4409 , n4410 , n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 ,
n4419 , n4420 , n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 ,
n4429 , n4430 , n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 ,
n4439 , n4440 , n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 ,
n4449 , n4450 , n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 ,
n4459 , n4460 , n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 ,
n4469 , n4470 , n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 ,
n4479 , n4480 , n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 ,
n4489 , n4490 , n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 ,
n4499 , n4500 , n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 ,
n4509 , n4510 , n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 ,
n4519 , n4520 , n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 ,
n4529 , n4530 , n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 ,
n4539 , n4540 , n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 ,
n4549 , n4550 , n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 ,
n4559 , n4560 , n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 ,
n4569 , n4570 , n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 ,
n4579 , n4580 , n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 ,
n4589 , n4590 , n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 ,
n4599 , n4600 , n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 ,
n4609 , n4610 , n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 ,
n4619 , n4620 , n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 ,
n4629 , n4630 , n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 ,
n4639 , n4640 , n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 ,
n4649 , n4650 , n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 ,
n4659 , n4660 , n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 ,
n4669 , n4670 , n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 ,
n4679 , n4680 , n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 ,
n4689 , n4690 , n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 ,
n4699 , n4700 , n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 ,
n4709 , n4710 , n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 ,
n4719 , n4720 , n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 ,
n4729 , n4730 , n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 ,
n4739 , n4740 , n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 ,
n4749 , n4750 , n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 ,
n4759 , n4760 , n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 ,
n4769 , n4770 , n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 ,
n4779 , n4780 , n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 ,
n4789 , n4790 , n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 ,
n4799 , n4800 , n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 ,
n4809 , n4810 , n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 ,
n4819 , n4820 , n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 ,
n4829 , n4830 , n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 ,
n4839 , n4840 , n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 ,
n4849 , n4850 , n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 ,
n4859 , n4860 , n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 ,
n4869 , n4870 , n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 ,
n4879 , n4880 , n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 ,
n4889 , n4890 , n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 ,
n4899 , n4900 , n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 ,
n4909 , n4910 , n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 ,
n4919 , n4920 , n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 ,
n4929 , n4930 , n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 ,
n4939 , n4940 , n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 ,
n4949 , n4950 , n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 ,
n4959 , n4960 , n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 ,
n4969 , n4970 , n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 ,
n4979 , n4980 , n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 ,
n4989 , n4990 , n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 ,
n4999 , n5000 , n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 ,
n5009 , n5010 , n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 ,
n5019 , n5020 , n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 ,
n5029 , n5030 , n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 ,
n5039 , n5040 , n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 ,
n5049 , n5050 , n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 ,
n5059 , n5060 , n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 ,
n5069 , n5070 , n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 ,
n5079 , n5080 , n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 ,
n5089 , n5090 , n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 ,
n5099 , n5100 , n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 ,
n5109 , n5110 , n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 ,
n5119 , n5120 , n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 ,
n5129 , n5130 , n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 ,
n5139 , n5140 , n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 ,
n5149 , n5150 , n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 ,
n5159 , n5160 , n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 ,
n5169 , n5170 , n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 ,
n5179 , n5180 , n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 ,
n5189 , n5190 , n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 ,
n5199 , n5200 , n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 ,
n5209 , n5210 , n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 ,
n5219 , n5220 , n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 ,
n5229 , n5230 , n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 ,
n5239 , n5240 , n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 ,
n5249 , n5250 , n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 ,
n5259 , n5260 , n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 ,
n5269 , n5270 , n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 ,
n5279 , n5280 , n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 ,
n5289 , n5290 , n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 ,
n5299 , n5300 , n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 ,
n5309 , n5310 , n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 ,
n5319 , n5320 , n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 ,
n5329 , n5330 , n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 ,
n5339 , n5340 , n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 ,
n5349 , n5350 , n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 ,
n5359 , n5360 , n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 ,
n5369 , n5370 , n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 ,
n5379 , n5380 , n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 ,
n5389 , n5390 , n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 ,
n5399 , n5400 , n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 ,
n5409 , n5410 , n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 ,
n5419 , n5420 , n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 ,
n5429 , n5430 , n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 ,
n5439 , n5440 , n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 ,
n5449 , n5450 , n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 ,
n5459 , n5460 , n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 ,
n5469 , n5470 , n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 ,
n5479 , n5480 , n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 ,
n5489 , n5490 , n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 ,
n5499 , n5500 , n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 ,
n5509 , n5510 , n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 ,
n5519 , n5520 , n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 ,
n5529 , n5530 , n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 ,
n5539 , n5540 , n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 ,
n5549 , n5550 , n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 ,
n5559 , n5560 , n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 ,
n5569 , n5570 , n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 ,
n5579 , n5580 , n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 ,
n5589 , n5590 , n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 ,
n5599 , n5600 , n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 ,
n5609 , n5610 , n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 ,
n5619 , n5620 , n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 ,
n5629 , n5630 , n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 ,
n5639 , n5640 , n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 ,
n5649 , n5650 , n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 ,
n5659 , n5660 , n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 ,
n5669 , n5670 , n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 ,
n5679 , n5680 , n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 ,
n5689 , n5690 , n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 ,
n5699 , n5700 , n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 ,
n5709 , n5710 , n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 ,
n5719 , n5720 , n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 ,
n5729 , n5730 , n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 ,
n5739 , n5740 , n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 ,
n5749 , n5750 , n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 ,
n5759 , n5760 , n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 ,
n5769 , n5770 , n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 ,
n5779 , n5780 , n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 ,
n5789 , n5790 , n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 ,
n5799 , n5800 , n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 ,
n5809 , n5810 , n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 ,
n5819 , n5820 , n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 ,
n5829 , n5830 , n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 ,
n5839 , n5840 , n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 ,
n5849 , n5850 , n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 ,
n5859 , n5860 , n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 ,
n5869 , n5870 , n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 ,
n5879 , n5880 , n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 ,
n5889 , n5890 , n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 ,
n5899 , n5900 , n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 ,
n5909 , n5910 , n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 ,
n5919 , n5920 , n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 ,
n5929 , n5930 , n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 ,
n5939 , n5940 , n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 ,
n5949 , n5950 , n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 ,
n5959 , n5960 , n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 ,
n5969 , n5970 , n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 ,
n5979 , n5980 , n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 ,
n5989 , n5990 , n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 ,
n5999 , n6000 , n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 ,
n6009 , n6010 , n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 ,
n6019 , n6020 , n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 ,
n6029 , n6030 , n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 ,
n6039 , n6040 , n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 ,
n6049 , n6050 , n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 ,
n6059 , n6060 , n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 ,
n6069 , n6070 , n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 ,
n6079 , n6080 , n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 ,
n6089 , n6090 , n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 ,
n6099 , n6100 , n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 ,
n6109 , n6110 , n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 ,
n6119 , n6120 , n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 ,
n6129 , n6130 , n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 ,
n6139 , n6140 , n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 ,
n6149 , n6150 , n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 ,
n6159 , n6160 , n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 ,
n6169 , n6170 , n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 ,
n6179 , n6180 , n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 ,
n6189 , n6190 , n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 ,
n6199 , n6200 , n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 ,
n6209 , n6210 , n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 ,
n6219 , n6220 , n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 ,
n6229 , n6230 , n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 ,
n6239 , n6240 , n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 ,
n6249 , n6250 , n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 ,
n6259 , n6260 , n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 ,
n6269 , n6270 , n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 ,
n6279 , n6280 , n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 ,
n6289 , n6290 , n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 ,
n6299 , n6300 , n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 ,
n6309 , n6310 , n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 ,
n6319 , n6320 , n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 ,
n6329 , n6330 , n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 ,
n6339 , n6340 , n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 ,
n6349 , n6350 , n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 ,
n6359 , n6360 , n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 ,
n6369 , n6370 , n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 ,
n6379 , n6380 , n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 ,
n6389 , n6390 , n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 ,
n6399 , n6400 , n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 ,
n6409 , n6410 , n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 ,
n6419 , n6420 , n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 ,
n6429 , n6430 , n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 ,
n6439 , n6440 , n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 ,
n6449 , n6450 , n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 ,
n6459 , n6460 , n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 ,
n6469 , n6470 , n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 ,
n6479 , n6480 , n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 ,
n6489 , n6490 , n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 ,
n6499 , n6500 , n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 ,
n6509 , n6510 , n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 ,
n6519 , n6520 , n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 ,
n6529 , n6530 , n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 ,
n6539 , n6540 , n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 ,
n6549 , n6550 , n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 ,
n6559 , n6560 , n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 ,
n6569 , n6570 , n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 ,
n6579 , n6580 , n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 ,
n6589 , n6590 , n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 ,
n6599 , n6600 , n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 ,
n6609 , n6610 , n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 ,
n6619 , n6620 , n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 ,
n6629 , n6630 , n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 ,
n6639 , n6640 , n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 ,
n6649 , n6650 , n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 ,
n6659 , n6660 , n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 ,
n6669 , n6670 , n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 ,
n6679 , n6680 , n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 ,
n6689 , n6690 , n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 ,
n6699 , n6700 , n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 ,
n6709 , n6710 , n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 ,
n6719 , n6720 , n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 ,
n6729 , n6730 , n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 ,
n6739 , n6740 , n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 ,
n6749 , n6750 , n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 ,
n6759 , n6760 , n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 ,
n6769 , n6770 , n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 ,
n6779 , n6780 , n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 ,
n6789 , n6790 , n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 ,
n6799 , n6800 , n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 ,
n6809 , n6810 , n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 ,
n6819 , n6820 , n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 ,
n6829 , n6830 , n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 ,
n6839 , n6840 , n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 ,
n6849 , n6850 , n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 ,
n6859 , n6860 , n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 ,
n6869 , n6870 , n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 ,
n6879 , n6880 , n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 ,
n6889 , n6890 , n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 ,
n6899 , n6900 , n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 ,
n6909 , n6910 , n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 ,
n6919 , n6920 , n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 ,
n6929 , n6930 , n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 ,
n6939 , n6940 , n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 ,
n6949 , n6950 , n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 ,
n6959 , n6960 , n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 ,
n6969 , n6970 , n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 ,
n6979 , n6980 , n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 ,
n6989 , n6990 , n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 ,
n6999 , n7000 , n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 ,
n7009 , n7010 , n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 ,
n7019 , n7020 , n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 ,
n7029 , n7030 , n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 ,
n7039 , n7040 , n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 ,
n7049 , n7050 , n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 ,
n7059 , n7060 , n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 ,
n7069 , n7070 , n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 ,
n7079 , n7080 , n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 ,
n7089 , n7090 , n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 ,
n7099 , n7100 , n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 ,
n7109 , n7110 , n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 ,
n7119 , n7120 , n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 ,
n7129 , n7130 , n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 ,
n7139 , n7140 , n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 ,
n7149 , n7150 , n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 ,
n7159 , n7160 , n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 ,
n7169 , n7170 , n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 ,
n7179 , n7180 , n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 ,
n7189 , n7190 , n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 ,
n7199 , n7200 , n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 ,
n7209 , n7210 , n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 ,
n7219 , n7220 , n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 ,
n7229 , n7230 , n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 ,
n7239 , n7240 , n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 ,
n7249 , n7250 , n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 ,
n7259 , n7260 , n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 ,
n7269 , n7270 , n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 ,
n7279 , n7280 , n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 ,
n7289 , n7290 , n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 ,
n7299 , n7300 , n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 ,
n7309 , n7310 , n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 ,
n7319 , n7320 , n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 ,
n7329 , n7330 , n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 ,
n7339 , n7340 , n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 ,
n7349 , n7350 , n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 ,
n7359 , n7360 , n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 ,
n7369 , n7370 , n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 ,
n7379 , n7380 , n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 ,
n7389 , n7390 , n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 ,
n7399 , n7400 , n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 ,
n7409 , n7410 , n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 ,
n7419 , n7420 , n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 ,
n7429 , n7430 , n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 ,
n7439 , n7440 , n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 ,
n7449 , n7450 , n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 ,
n7459 , n7460 , n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 ,
n7469 , n7470 , n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 ,
n7479 , n7480 , n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 ,
n7489 , n7490 , n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 ,
n7499 , n7500 , n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 ,
n7509 , n7510 , n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 ,
n7519 , n7520 , n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 ,
n7529 , n7530 , n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 ,
n7539 , n7540 , n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 ,
n7549 , n7550 , n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 ,
n7559 , n7560 , n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 ,
n7569 , n7570 , n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 ,
n7579 , n7580 , n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 ,
n7589 , n7590 , n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 ,
n7599 , n7600 , n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 ,
n7609 , n7610 , n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 ,
n7619 , n7620 , n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 ,
n7629 , n7630 , n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 ,
n7639 , n7640 , n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 ,
n7649 , n7650 , n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 ,
n7659 , n7660 , n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 ,
n7669 , n7670 , n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 ,
n7679 , n7680 , n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 ,
n7689 , n7690 , n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 ,
n7699 , n7700 , n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 ,
n7709 , n7710 , n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 ,
n7719 , n7720 , n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 ,
n7729 , n7730 , n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 ,
n7739 , n7740 , n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 ,
n7749 , n7750 , n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 ,
n7759 , n7760 , n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 ,
n7769 , n7770 , n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 ,
n7779 , n7780 , n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 ,
n7789 , n7790 , n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 ,
n7799 , n7800 , n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 ,
n7809 , n7810 , n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 ,
n7819 , n7820 , n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 ,
n7829 , n7830 , n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 ,
n7839 , n7840 , n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 ,
n7849 , n7850 , n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 ,
n7859 , n7860 , n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 ,
n7869 , n7870 , n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 ,
n7879 , n7880 , n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 ,
n7889 , n7890 , n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 ,
n7899 , n7900 , n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 ,
n7909 , n7910 , n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 ,
n7919 , n7920 , n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 ,
n7929 , n7930 , n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 ,
n7939 , n7940 , n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 ,
n7949 , n7950 , n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 ,
n7959 , n7960 , n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 ,
n7969 , n7970 , n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 ,
n7979 , n7980 , n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 ,
n7989 , n7990 , n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 ,
n7999 , n8000 , n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 ,
n8009 , n8010 , n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 ,
n8019 , n8020 , n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 ,
n8029 , n8030 , n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 ,
n8039 , n8040 , n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 ,
n8049 , n8050 , n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 ,
n8059 , n8060 , n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 ,
n8069 , n8070 , n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 ,
n8079 , n8080 , n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 ,
n8089 , n8090 , n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 ,
n8099 , n8100 , n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 ,
n8109 , n8110 , n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 ,
n8119 , n8120 , n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 ,
n8129 , n8130 , n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 ,
n8139 , n8140 , n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 ,
n8149 , n8150 , n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 ,
n8159 , n8160 , n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 ,
n8169 , n8170 , n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 ,
n8179 , n8180 , n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 ,
n8189 , n8190 , n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 ,
n8199 , n8200 , n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 ,
n8209 , n8210 , n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 ,
n8219 , n8220 , n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 ,
n8229 , n8230 , n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 ,
n8239 , n8240 , n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 ,
n8249 , n8250 , n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 ,
n8259 , n8260 , n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 ,
n8269 , n8270 , n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 ,
n8279 , n8280 , n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 ,
n8289 , n8290 , n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 ,
n8299 , n8300 , n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 ,
n8309 , n8310 , n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 ,
n8319 , n8320 , n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 ,
n8329 , n8330 , n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 ,
n8339 , n8340 , n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 ,
n8349 , n8350 , n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 ,
n8359 , n8360 , n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 ,
n8369 , n8370 , n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 ,
n8379 , n8380 , n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 ,
n8389 , n8390 , n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 ,
n8399 , n8400 , n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 ,
n8409 , n8410 , n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 ,
n8419 , n8420 , n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 ,
n8429 , n8430 , n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 ,
n8439 , n8440 , n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 ,
n8449 , n8450 , n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 ,
n8459 , n8460 , n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 ,
n8469 , n8470 , n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 ,
n8479 , n8480 , n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 ,
n8489 , n8490 , n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 ,
n8499 , n8500 , n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 ,
n8509 , n8510 , n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 ,
n8519 , n8520 , n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 ,
n8529 , n8530 , n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 ,
n8539 , n8540 , n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 ,
n8549 , n8550 , n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 ,
n8559 , n8560 , n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 ,
n8569 , n8570 , n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 ,
n8579 , n8580 , n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 ,
n8589 , n8590 , n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 ,
n8599 , n8600 , n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 ,
n8609 , n8610 , n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 ,
n8619 , n8620 , n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 ,
n8629 , n8630 , n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 ,
n8639 , n8640 , n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 ,
n8649 , n8650 , n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 ,
n8659 , n8660 , n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 ,
n8669 , n8670 , n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 ,
n8679 , n8680 , n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 ,
n8689 , n8690 , n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 ,
n8699 , n8700 , n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 ,
n8709 , n8710 , n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 ,
n8719 , n8720 , n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 ,
n8729 , n8730 , n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 ,
n8739 , n8740 , n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 ,
n8749 , n8750 , n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 ,
n8759 , n8760 , n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 ,
n8769 , n8770 , n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 ,
n8779 , n8780 , n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 ,
n8789 , n8790 , n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 ,
n8799 , n8800 , n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 ,
n8809 , n8810 , n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 ,
n8819 , n8820 , n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 ,
n8829 , n8830 , n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 , n8838 ,
n8839 , n8840 , n8841 , n8842 , n8843 , n8844 , n8845 , n8846 , n8847 , n8848 ,
n8849 , n8850 , n8851 , n8852 , n8853 , n8854 , n8855 , n8856 , n8857 , n8858 ,
n8859 , n8860 , n8861 , n8862 , n8863 , n8864 , n8865 , n8866 , n8867 , n8868 ,
n8869 , n8870 , n8871 , n8872 , n8873 , n8874 , n8875 , n8876 , n8877 , n8878 ,
n8879 , n8880 , n8881 , n8882 , n8883 , n8884 , n8885 , n8886 , n8887 , n8888 ,
n8889 , n8890 , n8891 , n8892 , n8893 , n8894 , n8895 , n8896 , n8897 , n8898 ,
n8899 , n8900 , n8901 , n8902 , n8903 , n8904 , n8905 , n8906 , n8907 , n8908 ,
n8909 , n8910 , n8911 , n8912 , n8913 , n8914 , n8915 , n8916 , n8917 , n8918 ,
n8919 , n8920 , n8921 , n8922 , n8923 , n8924 , n8925 , n8926 , n8927 , n8928 ,
n8929 , n8930 , n8931 , n8932 , n8933 , n8934 , n8935 , n8936 , n8937 , n8938 ,
n8939 , n8940 , n8941 , n8942 , n8943 , n8944 , n8945 , n8946 , n8947 , n8948 ,
n8949 , n8950 , n8951 , n8952 , n8953 , n8954 , n8955 , n8956 , n8957 , n8958 ,
n8959 , n8960 , n8961 , n8962 , n8963 , n8964 , n8965 , n8966 , n8967 , n8968 ,
n8969 , n8970 , n8971 , n8972 , n8973 , n8974 , n8975 , n8976 , n8977 , n8978 ,
n8979 , n8980 , n8981 , n8982 , n8983 , n8984 , n8985 , n8986 , n8987 , n8988 ,
n8989 , n8990 , n8991 , n8992 , n8993 , n8994 , n8995 , n8996 , n8997 , n8998 ,
n8999 , n9000 , n9001 , n9002 , n9003 , n9004 , n9005 , n9006 , n9007 , n9008 ,
n9009 , n9010 , n9011 , n9012 , n9013 , n9014 , n9015 , n9016 , n9017 , n9018 ,
n9019 , n9020 , n9021 , n9022 , n9023 , n9024 , n9025 , n9026 , n9027 , n9028 ,
n9029 , n9030 , n9031 , n9032 , n9033 , n9034 , n9035 , n9036 , n9037 , n9038 ,
n9039 , n9040 , n9041 , n9042 , n9043 , n9044 , n9045 , n9046 , n9047 , n9048 ,
n9049 , n9050 , n9051 , n9052 , n9053 , n9054 , n9055 , n9056 , n9057 , n9058 ,
n9059 , n9060 , n9061 , n9062 , n9063 , n9064 , n9065 , n9066 , n9067 , n9068 ,
n9069 , n9070 , n9071 , n9072 , n9073 , n9074 , n9075 , n9076 , n9077 , n9078 ,
n9079 , n9080 , n9081 , n9082 , n9083 , n9084 , n9085 , n9086 , n9087 , n9088 ,
n9089 , n9090 , n9091 , n9092 , n9093 , n9094 , n9095 , n9096 , n9097 , n9098 ,
n9099 , n9100 , n9101 , n9102 , n9103 , n9104 , n9105 , n9106 , n9107 , n9108 ,
n9109 , n9110 , n9111 , n9112 , n9113 , n9114 , n9115 , n9116 , n9117 , n9118 ,
n9119 , n9120 , n9121 , n9122 , n9123 , n9124 , n9125 , n9126 , n9127 , n9128 ,
n9129 , n9130 , n9131 , n9132 , n9133 , n9134 , n9135 , n9136 , n9137 , n9138 ,
n9139 , n9140 , n9141 , n9142 , n9143 , n9144 , n9145 , n9146 , n9147 , n9148 ,
n9149 , n9150 , n9151 , n9152 , n9153 , n9154 , n9155 , n9156 , n9157 , n9158 ,
n9159 , n9160 , n9161 , n9162 , n9163 , n9164 , n9165 , n9166 , n9167 , n9168 ,
n9169 , n9170 , n9171 , n9172 , n9173 , n9174 , n9175 , n9176 , n9177 , n9178 ,
n9179 , n9180 , n9181 , n9182 , n9183 , n9184 , n9185 , n9186 , n9187 , n9188 ,
n9189 , n9190 , n9191 , n9192 , n9193 , n9194 , n9195 , n9196 , n9197 , n9198 ,
n9199 , n9200 , n9201 , n9202 , n9203 , n9204 , n9205 , n9206 , n9207 , n9208 ,
n9209 , n9210 , n9211 , n9212 , n9213 , n9214 , n9215 , n9216 , n9217 , n9218 ,
n9219 , n9220 , n9221 , n9222 , n9223 , n9224 , n9225 , n9226 , n9227 , n9228 ,
n9229 , n9230 , n9231 , n9232 , n9233 , n9234 , n9235 , n9236 , n9237 , n9238 ,
n9239 , n9240 , n9241 , n9242 , n9243 , n9244 , n9245 , n9246 , n9247 , n9248 ,
n9249 , n9250 , n9251 , n9252 , n9253 , n9254 , n9255 , n9256 , n9257 , n9258 ,
n9259 , n9260 , n9261 , n9262 , n9263 , n9264 , n9265 , n9266 , n9267 , n9268 ,
n9269 , n9270 , n9271 , n9272 , n9273 , n9274 , n9275 , n9276 , n9277 , n9278 ,
n9279 , n9280 , n9281 , n9282 , n9283 , n9284 , n9285 , n9286 , n9287 , n9288 ,
n9289 , n9290 , n9291 , n9292 , n9293 , n9294 , n9295 , n9296 , n9297 , n9298 ,
n9299 , n9300 , n9301 , n9302 , n9303 , n9304 , n9305 , n9306 , n9307 , n9308 ,
n9309 , n9310 , n9311 , n9312 , n9313 , n9314 , n9315 , n9316 , n9317 , n9318 ,
n9319 , n9320 , n9321 , n9322 , n9323 , n9324 , n9325 , n9326 , n9327 , n9328 ,
n9329 , n9330 , n9331 , n9332 , n9333 , n9334 , n9335 , n9336 , n9337 , n9338 ,
n9339 , n9340 , n9341 , n9342 , n9343 , n9344 , n9345 , n9346 , n9347 , n9348 ,
n9349 , n9350 , n9351 , n9352 , n9353 , n9354 , n9355 , n9356 , n9357 , n9358 ,
n9359 , n9360 , n9361 , n9362 , n9363 , n9364 , n9365 , n9366 , n9367 , n9368 ,
n9369 , n9370 , n9371 , n9372 , n9373 , n9374 , n9375 , n9376 , n9377 , n9378 ,
n9379 , n9380 , n9381 , n9382 , n9383 , n9384 , n9385 , n9386 , n9387 , n9388 ,
n9389 , n9390 , n9391 , n9392 , n9393 , n9394 , n9395 , n9396 , n9397 , n9398 ,
n9399 , n9400 , n9401 , n9402 , n9403 , n9404 , n9405 , n9406 , n9407 , n9408 ,
n9409 , n9410 , n9411 , n9412 , n9413 , n9414 , n9415 , n9416 , n9417 , n9418 ,
n9419 , n9420 , n9421 , n9422 , n9423 , n9424 , n9425 , n9426 , n9427 , n9428 ,
n9429 , n9430 , n9431 , n9432 , n9433 , n9434 , n9435 , n9436 , n9437 , n9438 ,
n9439 , n9440 , n9441 , n9442 , n9443 , n9444 , n9445 , n9446 , n9447 , n9448 ,
n9449 , n9450 , n9451 , n9452 , n9453 , n9454 , n9455 , n9456 , n9457 , n9458 ,
n9459 , n9460 , n9461 , n9462 , n9463 , n9464 , n9465 , n9466 , n9467 , n9468 ,
n9469 , n9470 , n9471 , n9472 , n9473 , n9474 , n9475 , n9476 , n9477 , n9478 ,
n9479 , n9480 , n9481 , n9482 , n9483 , n9484 , n9485 , n9486 , n9487 , n9488 ,
n9489 , n9490 , n9491 , n9492 , n9493 , n9494 , n9495 , n9496 , n9497 , n9498 ,
n9499 , n9500 , n9501 , n9502 , n9503 , n9504 , n9505 , n9506 , n9507 , n9508 ,
n9509 , n9510 , n9511 , n9512 , n9513 , n9514 , n9515 , n9516 , n9517 , n9518 ,
n9519 , n9520 , n9521 , n9522 , n9523 , n9524 , n9525 , n9526 , n9527 , n9528 ,
n9529 , n9530 , n9531 , n9532 , n9533 , n9534 , n9535 , n9536 , n9537 , n9538 ,
n9539 , n9540 , n9541 , n9542 , n9543 , n9544 , n9545 , n9546 , n9547 , n9548 ,
n9549 , n9550 , n9551 , n9552 , n9553 , n9554 , n9555 , n9556 , n9557 , n9558 ,
n9559 , n9560 , n9561 , n9562 , n9563 , n9564 , n9565 , n9566 , n9567 , n9568 ,
n9569 , n9570 , n9571 , n9572 , n9573 , n9574 , n9575 , n9576 , n9577 , n9578 ,
n9579 , n9580 , n9581 , n9582 , n9583 , n9584 , n9585 , n9586 , n9587 , n9588 ,
n9589 , n9590 , n9591 , n9592 , n9593 , n9594 , n9595 , n9596 , n9597 , n9598 ,
n9599 , n9600 , n9601 , n9602 , n9603 , n9604 , n9605 , n9606 , n9607 , n9608 ,
n9609 , n9610 , n9611 , n9612 , n9613 , n9614 , n9615 , n9616 , n9617 , n9618 ,
n9619 , n9620 , n9621 , n9622 , n9623 , n9624 , n9625 , n9626 , n9627 , n9628 ,
n9629 , n9630 , n9631 , n9632 , n9633 , n9634 , n9635 , n9636 , n9637 , n9638 ,
n9639 , n9640 , n9641 , n9642 , n9643 , n9644 , n9645 , n9646 , n9647 , n9648 ,
n9649 , n9650 , n9651 , n9652 , n9653 , n9654 , n9655 , n9656 , n9657 , n9658 ,
n9659 , n9660 , n9661 , n9662 , n9663 , n9664 , n9665 , n9666 , n9667 , n9668 ,
n9669 , n9670 , n9671 , n9672 , n9673 , n9674 , n9675 , n9676 , n9677 , n9678 ,
n9679 , n9680 , n9681 , n9682 , n9683 , n9684 , n9685 , n9686 , n9687 , n9688 ,
n9689 , n9690 , n9691 , n9692 , n9693 , n9694 , n9695 , n9696 , n9697 , n9698 ,
n9699 , n9700 , n9701 , n9702 , n9703 , n9704 , n9705 , n9706 , n9707 , n9708 ,
n9709 , n9710 , n9711 , n9712 , n9713 , n9714 , n9715 , n9716 , n9717 , n9718 ,
n9719 , n9720 , n9721 , n9722 , n9723 , n9724 , n9725 , n9726 , n9727 , n9728 ,
n9729 , n9730 , n9731 , n9732 , n9733 , n9734 , n9735 , n9736 , n9737 , n9738 ,
n9739 , n9740 , n9741 , n9742 , n9743 , n9744 , n9745 , n9746 , n9747 , n9748 ,
n9749 , n9750 , n9751 , n9752 , n9753 , n9754 , n9755 , n9756 , n9757 , n9758 ,
n9759 , n9760 , n9761 , n9762 , n9763 , n9764 , n9765 , n9766 , n9767 , n9768 ,
n9769 , n9770 , n9771 , n9772 , n9773 , n9774 , n9775 , n9776 , n9777 , n9778 ,
n9779 , n9780 , n9781 , n9782 , n9783 , n9784 , n9785 , n9786 , n9787 , n9788 ,
n9789 , n9790 , n9791 , n9792 , n9793 , n9794 , n9795 , n9796 , n9797 , n9798 ,
n9799 , n9800 , n9801 , n9802 , n9803 , n9804 , n9805 , n9806 , n9807 , n9808 ,
n9809 , n9810 , n9811 , n9812 , n9813 , n9814 , n9815 , n9816 , n9817 , n9818 ,
n9819 , n9820 , n9821 , n9822 , n9823 , n9824 , n9825 , n9826 , n9827 , n9828 ,
n9829 , n9830 , n9831 , n9832 , n9833 , n9834 , n9835 , n9836 , n9837 , n9838 ,
n9839 , n9840 , n9841 , n9842 , n9843 , n9844 , n9845 , n9846 , n9847 , n9848 ,
n9849 , n9850 , n9851 , n9852 , n9853 , n9854 , n9855 , n9856 , n9857 , n9858 ,
n9859 , n9860 , n9861 , n9862 , n9863 , n9864 , n9865 , n9866 , n9867 , n9868 ,
n9869 , n9870 , n9871 , n9872 , n9873 , n9874 , n9875 , n9876 , n9877 , n9878 ,
n9879 , n9880 , n9881 , n9882 , n9883 , n9884 , n9885 , n9886 , n9887 , n9888 ,
n9889 , n9890 , n9891 , n9892 , n9893 , n9894 , n9895 , n9896 , n9897 , n9898 ,
n9899 , n9900 , n9901 , n9902 , n9903 , n9904 , n9905 , n9906 , n9907 , n9908 ,
n9909 , n9910 , n9911 , n9912 , n9913 , n9914 , n9915 , n9916 , n9917 , n9918 ,
n9919 , n9920 , n9921 , n9922 , n9923 , n9924 , n9925 , n9926 , n9927 , n9928 ,
n9929 , n9930 , n9931 , n9932 , n9933 , n9934 , n9935 , n9936 , n9937 , n9938 ,
n9939 , n9940 , n9941 , n9942 , n9943 , n9944 , n9945 , n9946 , n9947 , n9948 ,
n9949 , n9950 , n9951 , n9952 , n9953 , n9954 , n9955 , n9956 , n9957 , n9958 ,
n9959 , n9960 , n9961 , n9962 , n9963 , n9964 , n9965 , n9966 , n9967 , n9968 ,
n9969 , n9970 , n9971 , n9972 , n9973 , n9974 , n9975 , n9976 , n9977 , n9978 ,
n9979 , n9980 , n9981 , n9982 , n9983 , n9984 , n9985 , n9986 , n9987 , n9988 ,
n9989 , n9990 , n9991 , n9992 , n9993 , n9994 , n9995 , n9996 , n9997 , n9998 ,
n9999 , n10000 , n10001 , n10002 , n10003 , n10004 , n10005 , n10006 , n10007 , n10008 ,
n10009 , n10010 , n10011 , n10012 , n10013 , n10014 , n10015 , n10016 , n10017 , n10018 ,
n10019 , n10020 , n10021 , n10022 , n10023 , n10024 , n10025 , n10026 , n10027 , n10028 ,
n10029 , n10030 , n10031 , n10032 , n10033 , n10034 , n10035 , n10036 , n10037 , n10038 ,
n10039 , n10040 , n10041 , n10042 , n10043 , n10044 , n10045 , n10046 , n10047 , n10048 ,
n10049 , n10050 , n10051 , n10052 , n10053 , n10054 , n10055 , n10056 , n10057 , n10058 ,
n10059 , n10060 , n10061 , n10062 , n10063 , n10064 , n10065 , n10066 , n10067 , n10068 ,
n10069 , n10070 , n10071 , n10072 , n10073 , n10074 , n10075 , n10076 , n10077 , n10078 ,
n10079 , n10080 , n10081 , n10082 , n10083 , n10084 , n10085 , n10086 , n10087 , n10088 ,
n10089 , n10090 , n10091 , n10092 , n10093 , n10094 , n10095 , n10096 , n10097 , n10098 ,
n10099 , n10100 , n10101 , n10102 , n10103 , n10104 , n10105 , n10106 , n10107 , n10108 ,
n10109 , n10110 , n10111 , n10112 , n10113 , n10114 , n10115 , n10116 , n10117 , n10118 ,
n10119 , n10120 , n10121 , n10122 , n10123 , n10124 , n10125 , n10126 , n10127 , n10128 ,
n10129 , n10130 , n10131 , n10132 , n10133 , n10134 , n10135 , n10136 , n10137 , n10138 ,
n10139 , n10140 , n10141 , n10142 , n10143 , n10144 , n10145 , n10146 , n10147 , n10148 ,
n10149 , n10150 , n10151 , n10152 , n10153 , n10154 , n10155 , n10156 , n10157 , n10158 ,
n10159 , n10160 , n10161 , n10162 , n10163 , n10164 , n10165 , n10166 , n10167 , n10168 ,
n10169 , n10170 , n10171 , n10172 , n10173 , n10174 , n10175 , n10176 , n10177 , n10178 ,
n10179 , n10180 , n10181 , n10182 , n10183 , n10184 , n10185 , n10186 , n10187 , n10188 ,
n10189 , n10190 , n10191 , n10192 , n10193 , n10194 , n10195 , n10196 , n10197 , n10198 ,
n10199 , n10200 , n10201 , n10202 , n10203 , n10204 , n10205 , n10206 , n10207 , n10208 ,
n10209 , n10210 , n10211 , n10212 , n10213 , n10214 , n10215 , n10216 , n10217 , n10218 ,
n10219 , n10220 , n10221 , n10222 , n10223 , n10224 , n10225 , n10226 , n10227 , n10228 ,
n10229 , n10230 , n10231 , n10232 , n10233 , n10234 , n10235 , n10236 , n10237 , n10238 ,
n10239 , n10240 , n10241 , n10242 , n10243 , n10244 , n10245 , n10246 , n10247 , n10248 ,
n10249 , n10250 , n10251 , n10252 , n10253 , n10254 , n10255 , n10256 , n10257 , n10258 ,
n10259 , n10260 , n10261 , n10262 , n10263 , n10264 , n10265 , n10266 , n10267 , n10268 ,
n10269 , n10270 , n10271 , n10272 , n10273 , n10274 , n10275 , n10276 , n10277 , n10278 ,
n10279 , n10280 , n10281 , n10282 , n10283 , n10284 , n10285 , n10286 , n10287 , n10288 ,
n10289 , n10290 , n10291 , n10292 , n10293 , n10294 , n10295 , n10296 , n10297 , n10298 ,
n10299 , n10300 , n10301 , n10302 , n10303 , n10304 , n10305 , n10306 , n10307 , n10308 ,
n10309 , n10310 , n10311 , n10312 , n10313 , n10314 , n10315 , n10316 , n10317 , n10318 ,
n10319 , n10320 , n10321 , n10322 , n10323 , n10324 , n10325 , n10326 , n10327 , n10328 ,
n10329 , n10330 , n10331 , n10332 , n10333 , n10334 , n10335 , n10336 , n10337 , n10338 ,
n10339 , n10340 , n10341 , n10342 , n10343 , n10344 , n10345 , n10346 , n10347 , n10348 ,
n10349 , n10350 , n10351 , n10352 , n10353 , n10354 , n10355 , n10356 , n10357 , n10358 ,
n10359 , n10360 , n10361 , n10362 , n10363 , n10364 , n10365 , n10366 , n10367 , n10368 ,
n10369 , n10370 , n10371 , n10372 , n10373 , n10374 , n10375 , n10376 , n10377 , n10378 ,
n10379 , n10380 , n10381 , n10382 , n10383 , n10384 , n10385 , n10386 , n10387 , n10388 ,
n10389 , n10390 , n10391 , n10392 , n10393 , n10394 , n10395 , n10396 , n10397 , n10398 ,
n10399 , n10400 , n10401 , n10402 , n10403 , n10404 , n10405 , n10406 , n10407 , n10408 ,
n10409 , n10410 , n10411 , n10412 , n10413 , n10414 , n10415 , n10416 , n10417 , n10418 ,
n10419 , n10420 , n10421 , n10422 , n10423 , n10424 , n10425 , n10426 , n10427 , n10428 ,
n10429 , n10430 , n10431 , n10432 , n10433 , n10434 , n10435 , n10436 , n10437 , n10438 ,
n10439 , n10440 , n10441 , n10442 , n10443 , n10444 , n10445 , n10446 , n10447 , n10448 ,
n10449 , n10450 , n10451 , n10452 , n10453 , n10454 , n10455 , n10456 , n10457 , n10458 ,
n10459 , n10460 , n10461 , n10462 , n10463 , n10464 , n10465 , n10466 , n10467 , n10468 ,
n10469 , n10470 , n10471 , n10472 , n10473 , n10474 , n10475 , n10476 , n10477 , n10478 ,
n10479 , n10480 , n10481 , n10482 , n10483 , n10484 , n10485 , n10486 , n10487 , n10488 ,
n10489 , n10490 , n10491 , n10492 , n10493 , n10494 , n10495 , n10496 , n10497 , n10498 ,
n10499 , n10500 , n10501 , n10502 , n10503 , n10504 , n10505 , n10506 , n10507 , n10508 ,
n10509 , n10510 , n10511 , n10512 , n10513 , n10514 , n10515 , n10516 , n10517 , n10518 ,
n10519 , n10520 , n10521 , n10522 , n10523 , n10524 , n10525 , n10526 , n10527 , n10528 ,
n10529 , n10530 , n10531 , n10532 , n10533 , n10534 , n10535 , n10536 , n10537 , n10538 ,
n10539 , n10540 , n10541 , n10542 , n10543 , n10544 , n10545 , n10546 , n10547 , n10548 ,
n10549 , n10550 , n10551 , n10552 , n10553 , n10554 , n10555 , n10556 , n10557 , n10558 ,
n10559 , n10560 , n10561 , n10562 , n10563 , n10564 , n10565 , n10566 , n10567 , n10568 ,
n10569 , n10570 , n10571 , n10572 , n10573 , n10574 , n10575 , n10576 , n10577 , n10578 ,
n10579 , n10580 , n10581 , n10582 , n10583 , n10584 , n10585 , n10586 , n10587 , n10588 ,
n10589 , n10590 , n10591 , n10592 , n10593 , n10594 , n10595 , n10596 , n10597 , n10598 ,
n10599 , n10600 , n10601 , n10602 , n10603 , n10604 , n10605 , n10606 , n10607 , n10608 ,
n10609 , n10610 , n10611 , n10612 , n10613 , n10614 , n10615 , n10616 , n10617 , n10618 ,
n10619 , n10620 , n10621 , n10622 , n10623 , n10624 , n10625 , n10626 , n10627 , n10628 ,
n10629 , n10630 , n10631 , n10632 , n10633 , n10634 , n10635 , n10636 , n10637 , n10638 ,
n10639 , n10640 , n10641 , n10642 , n10643 , n10644 , n10645 , n10646 , n10647 , n10648 ,
n10649 , n10650 , n10651 , n10652 , n10653 , n10654 , n10655 , n10656 , n10657 , n10658 ,
n10659 , n10660 , n10661 , n10662 , n10663 , n10664 , n10665 , n10666 , n10667 , n10668 ,
n10669 , n10670 , n10671 , n10672 , n10673 , n10674 , n10675 , n10676 , n10677 , n10678 ,
n10679 , n10680 , n10681 , n10682 , n10683 , n10684 , n10685 , n10686 , n10687 , n10688 ,
n10689 , n10690 , n10691 , n10692 , n10693 , n10694 , n10695 , n10696 , n10697 , n10698 ,
n10699 , n10700 , n10701 , n10702 , n10703 , n10704 , n10705 , n10706 , n10707 , n10708 ,
n10709 , n10710 , n10711 , n10712 , n10713 , n10714 , n10715 , n10716 , n10717 , n10718 ,
n10719 , n10720 , n10721 , n10722 , n10723 , n10724 , n10725 , n10726 , n10727 , n10728 ,
n10729 , n10730 , n10731 , n10732 , n10733 , n10734 , n10735 , n10736 , n10737 , n10738 ,
n10739 , n10740 , n10741 , n10742 , n10743 , n10744 , n10745 , n10746 , n10747 , n10748 ,
n10749 , n10750 , n10751 , n10752 , n10753 , n10754 , n10755 , n10756 , n10757 , n10758 ,
n10759 , n10760 , n10761 , n10762 , n10763 , n10764 , n10765 , n10766 , n10767 , n10768 ,
n10769 , n10770 , n10771 , n10772 , n10773 , n10774 , n10775 , n10776 , n10777 , n10778 ,
n10779 , n10780 , n10781 , n10782 , n10783 , n10784 , n10785 , n10786 , n10787 , n10788 ,
n10789 , n10790 , n10791 , n10792 , n10793 , n10794 , n10795 , n10796 , n10797 , n10798 ,
n10799 , n10800 , n10801 , n10802 , n10803 , n10804 , n10805 , n10806 , n10807 , n10808 ,
n10809 , n10810 , n10811 , n10812 , n10813 , n10814 , n10815 , n10816 , n10817 , n10818 ,
n10819 , n10820 , n10821 , n10822 , n10823 , n10824 , n10825 , n10826 , n10827 , n10828 ,
n10829 , n10830 , n10831 , n10832 , n10833 , n10834 , n10835 , n10836 , n10837 , n10838 ,
n10839 , n10840 , n10841 , n10842 , n10843 , n10844 , n10845 , n10846 , n10847 , n10848 ,
n10849 , n10850 , n10851 , n10852 , n10853 , n10854 , n10855 , n10856 , n10857 , n10858 ,
n10859 , n10860 , n10861 , n10862 , n10863 , n10864 , n10865 , n10866 , n10867 , n10868 ,
n10869 , n10870 , n10871 , n10872 , n10873 , n10874 , n10875 , n10876 , n10877 , n10878 ,
n10879 , n10880 , n10881 , n10882 , n10883 , n10884 , n10885 , n10886 , n10887 , n10888 ,
n10889 , n10890 , n10891 , n10892 , n10893 , n10894 , n10895 , n10896 , n10897 , n10898 ,
n10899 , n10900 , n10901 , n10902 , n10903 , n10904 , n10905 , n10906 , n10907 , n10908 ,
n10909 , n10910 , n10911 , n10912 , n10913 , n10914 , n10915 , n10916 , n10917 , n10918 ,
n10919 , n10920 , n10921 , n10922 , n10923 , n10924 , n10925 , n10926 , n10927 , n10928 ,
n10929 , n10930 , n10931 , n10932 , n10933 , n10934 , n10935 , n10936 , n10937 , n10938 ,
n10939 , n10940 , n10941 , n10942 , n10943 , n10944 , n10945 , n10946 , n10947 , n10948 ,
n10949 , n10950 , n10951 , n10952 , n10953 , n10954 , n10955 , n10956 , n10957 , n10958 ,
n10959 , n10960 , n10961 , n10962 , n10963 , n10964 , n10965 , n10966 , n10967 , n10968 ,
n10969 , n10970 , n10971 , n10972 , n10973 , n10974 , n10975 , n10976 , n10977 , n10978 ,
n10979 , n10980 , n10981 , n10982 , n10983 , n10984 , n10985 , n10986 , n10987 , n10988 ,
n10989 , n10990 , n10991 , n10992 , n10993 , n10994 , n10995 , n10996 , n10997 , n10998 ,
n10999 , n11000 , n11001 , n11002 , n11003 , n11004 , n11005 , n11006 , n11007 , n11008 ,
n11009 , n11010 , n11011 , n11012 , n11013 , n11014 , n11015 , n11016 , n11017 , n11018 ,
n11019 , n11020 , n11021 , n11022 , n11023 , n11024 , n11025 , n11026 , n11027 , n11028 ,
n11029 , n11030 , n11031 , n11032 , n11033 , n11034 , n11035 , n11036 , n11037 , n11038 ,
n11039 , n11040 , n11041 , n11042 , n11043 , n11044 , n11045 , n11046 , n11047 , n11048 ,
n11049 , n11050 , n11051 , n11052 , n11053 , n11054 , n11055 , n11056 , n11057 , n11058 ,
n11059 , n11060 , n11061 , n11062 , n11063 , n11064 , n11065 , n11066 , n11067 , n11068 ,
n11069 , n11070 , n11071 , n11072 , n11073 , n11074 , n11075 , n11076 , n11077 , n11078 ,
n11079 , n11080 , n11081 , n11082 , n11083 , n11084 , n11085 , n11086 , n11087 , n11088 ,
n11089 , n11090 , n11091 , n11092 , n11093 , n11094 , n11095 , n11096 , n11097 , n11098 ,
n11099 , n11100 , n11101 , n11102 , n11103 , n11104 , n11105 , n11106 , n11107 , n11108 ,
n11109 , n11110 , n11111 , n11112 , n11113 , n11114 , n11115 , n11116 , n11117 , n11118 ,
n11119 , n11120 , n11121 , n11122 , n11123 , n11124 , n11125 , n11126 , n11127 , n11128 ,
n11129 , n11130 , n11131 , n11132 , n11133 , n11134 , n11135 , n11136 , n11137 , n11138 ,
n11139 , n11140 , n11141 , n11142 , n11143 , n11144 , n11145 , n11146 , n11147 , n11148 ,
n11149 , n11150 , n11151 , n11152 , n11153 , n11154 , n11155 , n11156 , n11157 , n11158 ,
n11159 , n11160 , n11161 , n11162 , n11163 , n11164 , n11165 , n11166 , n11167 , n11168 ,
n11169 , n11170 , n11171 , n11172 , n11173 , n11174 , n11175 , n11176 , n11177 , n11178 ,
n11179 , n11180 , n11181 , n11182 , n11183 , n11184 , n11185 , n11186 , n11187 , n11188 ,
n11189 , n11190 , n11191 , n11192 , n11193 , n11194 , n11195 , n11196 , n11197 , n11198 ,
n11199 , n11200 , n11201 , n11202 , n11203 , n11204 , n11205 , n11206 , n11207 , n11208 ,
n11209 , n11210 , n11211 , n11212 , n11213 , n11214 , n11215 , n11216 , n11217 , n11218 ,
n11219 , n11220 , n11221 , n11222 , n11223 , n11224 , n11225 , n11226 , n11227 , n11228 ,
n11229 , n11230 , n11231 , n11232 , n11233 , n11234 , n11235 , n11236 , n11237 , n11238 ,
n11239 , n11240 , n11241 , n11242 , n11243 , n11244 , n11245 , n11246 , n11247 , n11248 ,
n11249 , n11250 , n11251 , n11252 , n11253 , n11254 , n11255 , n11256 , n11257 , n11258 ,
n11259 , n11260 , n11261 , n11262 , n11263 , n11264 , n11265 , n11266 , n11267 , n11268 ,
n11269 , n11270 , n11271 , n11272 , n11273 , n11274 , n11275 , n11276 , n11277 , n11278 ,
n11279 , n11280 , n11281 , n11282 , n11283 , n11284 , n11285 , n11286 , n11287 , n11288 ,
n11289 , n11290 , n11291 , n11292 , n11293 , n11294 , n11295 , n11296 , n11297 , n11298 ,
n11299 , n11300 , n11301 , n11302 , n11303 , n11304 , n11305 , n11306 , n11307 , n11308 ,
n11309 , n11310 , n11311 , n11312 , n11313 , n11314 , n11315 , n11316 , n11317 , n11318 ,
n11319 , n11320 , n11321 , n11322 , n11323 , n11324 , n11325 , n11326 , n11327 , n11328 ,
n11329 , n11330 , n11331 , n11332 , n11333 , n11334 , n11335 , n11336 , n11337 , n11338 ,
n11339 , n11340 , n11341 , n11342 , n11343 , n11344 , n11345 , n11346 , n11347 , n11348 ,
n11349 , n11350 , n11351 , n11352 , n11353 , n11354 , n11355 , n11356 , n11357 , n11358 ,
n11359 , n11360 , n11361 , n11362 , n11363 , n11364 , n11365 , n11366 , n11367 , n11368 ,
n11369 , n11370 , n11371 , n11372 , n11373 , n11374 , n11375 , n11376 , n11377 , n11378 ,
n11379 , n11380 , n11381 , n11382 , n11383 , n11384 , n11385 , n11386 , n11387 , n11388 ,
n11389 , n11390 , n11391 , n11392 , n11393 , n11394 , n11395 , n11396 , n11397 , n11398 ,
n11399 , n11400 , n11401 , n11402 , n11403 , n11404 , n11405 , n11406 , n11407 , n11408 ,
n11409 , n11410 , n11411 , n11412 , n11413 , n11414 , n11415 , n11416 , n11417 , n11418 ,
n11419 , n11420 , n11421 , n11422 , n11423 , n11424 , n11425 , n11426 , n11427 , n11428 ,
n11429 , n11430 , n11431 , n11432 , n11433 , n11434 , n11435 , n11436 , n11437 , n11438 ,
n11439 , n11440 , n11441 , n11442 , n11443 , n11444 , n11445 , n11446 , n11447 , n11448 ,
n11449 , n11450 , n11451 , n11452 , n11453 , n11454 , n11455 , n11456 , n11457 , n11458 ,
n11459 , n11460 , n11461 , n11462 , n11463 , n11464 , n11465 , n11466 , n11467 , n11468 ,
n11469 , n11470 , n11471 , n11472 , n11473 , n11474 , n11475 , n11476 , n11477 , n11478 ,
n11479 , n11480 , n11481 , n11482 , n11483 , n11484 , n11485 , n11486 , n11487 , n11488 ,
n11489 , n11490 , n11491 , n11492 , n11493 , n11494 , n11495 , n11496 , n11497 , n11498 ,
n11499 , n11500 , n11501 , n11502 , n11503 , n11504 , n11505 , n11506 , n11507 , n11508 ,
n11509 , n11510 , n11511 , n11512 , n11513 , n11514 , n11515 , n11516 , n11517 , n11518 ,
n11519 , n11520 , n11521 , n11522 , n11523 , n11524 , n11525 , n11526 , n11527 , n11528 ,
n11529 , n11530 , n11531 , n11532 , n11533 , n11534 , n11535 , n11536 , n11537 , n11538 ,
n11539 , n11540 , n11541 , n11542 , n11543 , n11544 , n11545 , n11546 , n11547 , n11548 ,
n11549 , n11550 , n11551 , n11552 , n11553 , n11554 , n11555 , n11556 , n11557 , n11558 ,
n11559 , n11560 , n11561 , n11562 , n11563 , n11564 , n11565 , n11566 , n11567 , n11568 ,
n11569 , n11570 , n11571 , n11572 , n11573 , n11574 , n11575 , n11576 , n11577 , n11578 ,
n11579 , n11580 , n11581 , n11582 , n11583 , n11584 , n11585 , n11586 , n11587 , n11588 ,
n11589 , n11590 , n11591 , n11592 , n11593 , n11594 , n11595 , n11596 , n11597 , n11598 ,
n11599 , n11600 , n11601 , n11602 , n11603 , n11604 , n11605 , n11606 , n11607 , n11608 ,
n11609 , n11610 , n11611 , n11612 , n11613 , n11614 , n11615 , n11616 , n11617 , n11618 ,
n11619 , n11620 , n11621 , n11622 , n11623 , n11624 , n11625 , n11626 , n11627 , n11628 ,
n11629 , n11630 , n11631 , n11632 , n11633 , n11634 , n11635 , n11636 , n11637 , n11638 ,
n11639 , n11640 , n11641 , n11642 , n11643 , n11644 , n11645 , n11646 , n11647 , n11648 ,
n11649 , n11650 , n11651 , n11652 , n11653 , n11654 , n11655 , n11656 , n11657 , n11658 ,
n11659 , n11660 , n11661 , n11662 , n11663 , n11664 , n11665 , n11666 , n11667 , n11668 ,
n11669 , n11670 , n11671 , n11672 , n11673 , n11674 , n11675 , n11676 , n11677 , n11678 ,
n11679 , n11680 , n11681 , n11682 , n11683 , n11684 , n11685 , n11686 , n11687 , n11688 ,
n11689 , n11690 , n11691 , n11692 , n11693 , n11694 , n11695 , n11696 , n11697 , n11698 ,
n11699 , n11700 , n11701 , n11702 , n11703 , n11704 , n11705 , n11706 , n11707 , n11708 ,
n11709 , n11710 , n11711 , n11712 , n11713 , n11714 , n11715 , n11716 , n11717 , n11718 ,
n11719 , n11720 , n11721 , n11722 , n11723 , n11724 , n11725 , n11726 , n11727 , n11728 ,
n11729 , n11730 , n11731 , n11732 , n11733 , n11734 , n11735 , n11736 , n11737 , n11738 ,
n11739 , n11740 , n11741 , n11742 , n11743 , n11744 , n11745 , n11746 , n11747 , n11748 ,
n11749 , n11750 , n11751 , n11752 , n11753 , n11754 , n11755 , n11756 , n11757 , n11758 ,
n11759 , n11760 , n11761 , n11762 , n11763 , n11764 , n11765 , n11766 , n11767 , n11768 ,
n11769 , n11770 , n11771 , n11772 , n11773 , n11774 , n11775 , n11776 , n11777 , n11778 ,
n11779 , n11780 , n11781 , n11782 , n11783 , n11784 , n11785 , n11786 , n11787 , n11788 ,
n11789 , n11790 , n11791 , n11792 , n11793 , n11794 , n11795 , n11796 , n11797 , n11798 ,
n11799 , n11800 , n11801 , n11802 , n11803 , n11804 , n11805 , n11806 , n11807 , n11808 ,
n11809 , n11810 , n11811 , n11812 , n11813 , n11814 , n11815 , n11816 , n11817 , n11818 ,
n11819 , n11820 , n11821 , n11822 , n11823 , n11824 , n11825 , n11826 , n11827 , n11828 ,
n11829 , n11830 , n11831 , n11832 , n11833 , n11834 , n11835 , n11836 , n11837 , n11838 ,
n11839 , n11840 , n11841 , n11842 , n11843 , n11844 , n11845 , n11846 , n11847 , n11848 ,
n11849 , n11850 , n11851 , n11852 , n11853 , n11854 , n11855 , n11856 , n11857 , n11858 ,
n11859 , n11860 , n11861 , n11862 , n11863 , n11864 , n11865 , n11866 , n11867 , n11868 ,
n11869 , n11870 , n11871 , n11872 , n11873 , n11874 , n11875 , n11876 , n11877 , n11878 ,
n11879 , n11880 , n11881 , n11882 , n11883 , n11884 , n11885 , n11886 , n11887 , n11888 ,
n11889 , n11890 , n11891 , n11892 , n11893 , n11894 , n11895 , n11896 , n11897 , n11898 ,
n11899 , n11900 , n11901 , n11902 , n11903 , n11904 , n11905 , n11906 , n11907 , n11908 ,
n11909 , n11910 , n11911 , n11912 , n11913 , n11914 , n11915 , n11916 , n11917 , n11918 ,
n11919 , n11920 , n11921 , n11922 , n11923 , n11924 , n11925 , n11926 , n11927 , n11928 ,
n11929 , n11930 , n11931 , n11932 , n11933 , n11934 , n11935 , n11936 , n11937 , n11938 ,
n11939 , n11940 , n11941 , n11942 , n11943 , n11944 , n11945 , n11946 , n11947 , n11948 ,
n11949 , n11950 , n11951 , n11952 , n11953 , n11954 , n11955 , n11956 , n11957 , n11958 ,
n11959 , n11960 , n11961 , n11962 , n11963 , n11964 , n11965 , n11966 , n11967 , n11968 ,
n11969 , n11970 , n11971 , n11972 , n11973 , n11974 , n11975 , n11976 , n11977 , n11978 ,
n11979 , n11980 , n11981 , n11982 , n11983 , n11984 , n11985 , n11986 , n11987 , n11988 ,
n11989 , n11990 , n11991 , n11992 , n11993 , n11994 , n11995 , n11996 , n11997 , n11998 ,
n11999 , n12000 , n12001 , n12002 , n12003 , n12004 , n12005 , n12006 , n12007 , n12008 ,
n12009 , n12010 , n12011 , n12012 , n12013 , n12014 , n12015 , n12016 , n12017 , n12018 ,
n12019 , n12020 , n12021 , n12022 , n12023 , n12024 , n12025 , n12026 , n12027 , n12028 ,
n12029 , n12030 , n12031 , n12032 , n12033 , n12034 , n12035 , n12036 , n12037 , n12038 ,
n12039 , n12040 , n12041 , n12042 , n12043 , n12044 , n12045 , n12046 , n12047 , n12048 ,
n12049 , n12050 , n12051 , n12052 , n12053 , n12054 , n12055 , n12056 , n12057 , n12058 ,
n12059 , n12060 , n12061 , n12062 , n12063 , n12064 , n12065 , n12066 , n12067 , n12068 ,
n12069 , n12070 , n12071 , n12072 , n12073 , n12074 , n12075 , n12076 , n12077 , n12078 ,
n12079 , n12080 , n12081 , n12082 , n12083 , n12084 , n12085 , n12086 , n12087 , n12088 ,
n12089 , n12090 , n12091 , n12092 , n12093 , n12094 , n12095 , n12096 , n12097 , n12098 ,
n12099 , n12100 , n12101 , n12102 , n12103 , n12104 , n12105 , n12106 , n12107 , n12108 ,
n12109 , n12110 , n12111 , n12112 , n12113 , n12114 , n12115 , n12116 , n12117 , n12118 ,
n12119 , n12120 , n12121 , n12122 , n12123 , n12124 , n12125 , n12126 , n12127 , n12128 ,
n12129 , n12130 , n12131 , n12132 , n12133 , n12134 , n12135 , n12136 , n12137 , n12138 ,
n12139 , n12140 , n12141 , n12142 , n12143 , n12144 , n12145 , n12146 , n12147 , n12148 ,
n12149 , n12150 , n12151 , n12152 , n12153 , n12154 , n12155 , n12156 , n12157 , n12158 ,
n12159 , n12160 , n12161 , n12162 , n12163 , n12164 , n12165 , n12166 , n12167 , n12168 ,
n12169 , n12170 , n12171 , n12172 , n12173 , n12174 , n12175 , n12176 , n12177 , n12178 ,
n12179 , n12180 , n12181 , n12182 , n12183 , n12184 , n12185 , n12186 , n12187 , n12188 ,
n12189 , n12190 , n12191 , n12192 , n12193 , n12194 , n12195 , n12196 , n12197 , n12198 ,
n12199 , n12200 , n12201 , n12202 , n12203 , n12204 , n12205 , n12206 , n12207 , n12208 ,
n12209 , n12210 , n12211 , n12212 , n12213 , n12214 , n12215 , n12216 , n12217 , n12218 ,
n12219 , n12220 , n12221 , n12222 , n12223 , n12224 , n12225 , n12226 , n12227 , n12228 ,
n12229 , n12230 , n12231 , n12232 , n12233 , n12234 , n12235 , n12236 , n12237 , n12238 ,
n12239 , n12240 , n12241 , n12242 , n12243 , n12244 , n12245 , n12246 , n12247 , n12248 ,
n12249 , n12250 , n12251 , n12252 , n12253 , n12254 , n12255 , n12256 , n12257 , n12258 ,
n12259 , n12260 , n12261 , n12262 , n12263 , n12264 , n12265 , n12266 , n12267 , n12268 ,
n12269 , n12270 , n12271 , n12272 , n12273 , n12274 , n12275 , n12276 , n12277 , n12278 ,
n12279 , n12280 , n12281 , n12282 , n12283 , n12284 , n12285 , n12286 , n12287 , n12288 ,
n12289 , n12290 , n12291 , n12292 , n12293 , n12294 , n12295 , n12296 , n12297 , n12298 ,
n12299 , n12300 , n12301 , n12302 , n12303 , n12304 , n12305 , n12306 , n12307 , n12308 ,
n12309 , n12310 , n12311 , n12312 , n12313 , n12314 , n12315 , n12316 , n12317 , n12318 ,
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buf ( n5735 , n585 );
buf ( n5736 , n357 );
buf ( n5737 , n1871 );
buf ( n5738 , n562 );
buf ( n5739 , n1717 );
buf ( n5740 , n983 );
buf ( n5741 , n1059 );
buf ( n5742 , n940 );
buf ( n5743 , n194 );
buf ( n5744 , n929 );
buf ( n5745 , n1995 );
buf ( n5746 , n1359 );
buf ( n5747 , n1182 );
buf ( n5748 , n899 );
buf ( n5749 , n441 );
buf ( n5750 , n705 );
buf ( n5751 , n1987 );
buf ( n5752 , n1837 );
buf ( n5753 , n788 );
buf ( n5754 , n1245 );
buf ( n5755 , n1233 );
buf ( n5756 , n819 );
buf ( n5757 , n887 );
buf ( n5758 , n1341 );
buf ( n5759 , n1292 );
buf ( n5760 , n1062 );
buf ( n5761 , n1099 );
buf ( n5762 , n1081 );
buf ( n5763 , n1917 );
buf ( n5764 , n1502 );
buf ( n5765 , n1102 );
buf ( n5766 , n1177 );
buf ( n5767 , n430 );
buf ( n5768 , n1957 );
buf ( n5769 , n2022 );
buf ( n5770 , n902 );
buf ( n5771 , n1452 );
buf ( n5772 , n352 );
buf ( n5773 , n1204 );
buf ( n5774 , n1786 );
buf ( n5775 , n1492 );
buf ( n5776 , n327 );
buf ( n5777 , n1708 );
buf ( n5778 , n182 );
buf ( n5779 , n1377 );
buf ( n5780 , n1509 );
buf ( n5781 , n1562 );
buf ( n5782 , n848 );
buf ( n5783 , n1125 );
buf ( n5784 , n367 );
buf ( n5785 , n204 );
buf ( n5786 , n1164 );
buf ( n5787 , n218 );
buf ( n5788 , n991 );
buf ( n5789 , n1986 );
buf ( n5790 , n1774 );
buf ( n5791 , n594 );
buf ( n5792 , n446 );
buf ( n5793 , n1981 );
buf ( n5794 , n1258 );
buf ( n5795 , n122 );
buf ( n5796 , n84 );
buf ( n5797 , n700 );
buf ( n5798 , n188 );
buf ( n5799 , n476 );
buf ( n5800 , n935 );
buf ( n5801 , n1903 );
buf ( n5802 , n952 );
buf ( n5803 , n290 );
buf ( n5804 , n120 );
buf ( n5805 , n571 );
buf ( n5806 , n580 );
buf ( n5807 , n1507 );
buf ( n5808 , n433 );
buf ( n5809 , n1353 );
buf ( n5810 , n890 );
buf ( n5811 , n300 );
buf ( n5812 , n111 );
buf ( n5813 , n1642 );
buf ( n5814 , n335 );
buf ( n5815 , n92 );
buf ( n5816 , n232 );
buf ( n5817 , n1351 );
buf ( n5818 , n1067 );
buf ( n5819 , n1880 );
buf ( n5820 , n1192 );
buf ( n5821 , n18 );
buf ( n5822 , n136 );
buf ( n5823 , n123 );
buf ( n5824 , n1422 );
buf ( n5825 , n1217 );
buf ( n5826 , n44 );
buf ( n5827 , n866 );
buf ( n5828 , n1964 );
buf ( n5829 , n296 );
buf ( n5830 , n1922 );
buf ( n5831 , n1510 );
buf ( n5832 , n379 );
buf ( n5833 , n106 );
buf ( n5834 , n295 );
buf ( n5835 , n638 );
buf ( n5836 , n1881 );
buf ( n5837 , n818 );
buf ( n5838 , n1468 );
buf ( n5839 , n363 );
buf ( n5840 , n1118 );
buf ( n5841 , n1660 );
buf ( n5842 , n722 );
buf ( n5843 , n521 );
buf ( n5844 , n1340 );
buf ( n5845 , n1093 );
buf ( n5846 , n2011 );
buf ( n5847 , n1 );
buf ( n5848 , n1825 );
buf ( n5849 , n1891 );
buf ( n5850 , n192 );
buf ( n5851 , n1999 );
buf ( n5852 , n791 );
buf ( n5853 , n764 );
buf ( n5854 , n1701 );
buf ( n5855 , n761 );
buf ( n5856 , n1572 );
buf ( n5857 , n293 );
buf ( n5858 , n1498 );
buf ( n5859 , n119 );
buf ( n5860 , n151 );
buf ( n5861 , n1077 );
buf ( n5862 , n1934 );
buf ( n5863 , n380 );
buf ( n5864 , n581 );
buf ( n5865 , n733 );
buf ( n5866 , n496 );
buf ( n5867 , n966 );
buf ( n5868 , n418 );
buf ( n5869 , n1547 );
buf ( n5870 , n525 );
buf ( n5871 , n258 );
buf ( n5872 , n927 );
buf ( n5873 , n1208 );
buf ( n5874 , n508 );
buf ( n5875 , n1429 );
buf ( n5876 , n1199 );
buf ( n5877 , n797 );
buf ( n5878 , n951 );
buf ( n5879 , n102 );
buf ( n5880 , n134 );
buf ( n5881 , n1958 );
buf ( n5882 , n1057 );
buf ( n5883 , n955 );
buf ( n5884 , n1156 );
buf ( n5885 , n56 );
buf ( n5886 , n1692 );
buf ( n5887 , n822 );
buf ( n5888 , n1352 );
buf ( n5889 , n1464 );
buf ( n5890 , n735 );
buf ( n5891 , n410 );
buf ( n5892 , n1811 );
buf ( n5893 , n980 );
buf ( n5894 , n1714 );
buf ( n5895 , n523 );
buf ( n5896 , n1349 );
buf ( n5897 , n915 );
buf ( n5898 , n692 );
buf ( n5899 , n941 );
buf ( n5900 , n1809 );
buf ( n5901 , n1631 );
buf ( n5902 , n614 );
buf ( n5903 , n1887 );
buf ( n5904 , n1735 );
buf ( n5905 , n1520 );
buf ( n5906 , n483 );
buf ( n5907 , n33 );
buf ( n5908 , n877 );
buf ( n5909 , n1853 );
buf ( n5910 , n882 );
buf ( n5911 , n39 );
buf ( n5912 , n1024 );
buf ( n5913 , n658 );
buf ( n5914 , n244 );
buf ( n5915 , n1326 );
buf ( n5916 , n574 );
buf ( n5917 , n162 );
buf ( n5918 , n417 );
buf ( n5919 , n1682 );
buf ( n5920 , n1760 );
buf ( n5921 , n1961 );
buf ( n5922 , n1609 );
buf ( n5923 , n214 );
buf ( n5924 , n781 );
buf ( n5925 , n542 );
buf ( n5926 , n553 );
buf ( n5927 , n1630 );
buf ( n5928 , n590 );
buf ( n5929 , n1322 );
buf ( n5930 , n835 );
buf ( n5931 , n226 );
buf ( n5932 , n861 );
buf ( n5933 , n495 );
buf ( n5934 , n1013 );
buf ( n5935 , n669 );
buf ( n5936 , n289 );
buf ( n5937 , n1681 );
buf ( n5938 , n216 );
buf ( n5939 , n1415 );
buf ( n5940 , n895 );
buf ( n5941 , n500 );
buf ( n5942 , n1732 );
buf ( n5943 , n839 );
buf ( n5944 , n438 );
buf ( n5945 , n330 );
buf ( n5946 , n1250 );
buf ( n5947 , n1381 );
buf ( n5948 , n1018 );
buf ( n5949 , n233 );
buf ( n5950 , n88 );
buf ( n5951 , n551 );
buf ( n5952 , n832 );
buf ( n5953 , n916 );
buf ( n5954 , n1141 );
buf ( n5955 , n879 );
buf ( n5956 , n1597 );
buf ( n5957 , n1474 );
buf ( n5958 , n117 );
buf ( n5959 , n1396 );
buf ( n5960 , n598 );
buf ( n5961 , n1779 );
buf ( n5962 , n1197 );
buf ( n5963 , n392 );
buf ( n5964 , n844 );
buf ( n5965 , n165 );
buf ( n5966 , n988 );
buf ( n5967 , n1689 );
buf ( n5968 , n1159 );
buf ( n5969 , n1273 );
buf ( n5970 , n945 );
buf ( n5971 , n546 );
buf ( n5972 , n2040 );
buf ( n5973 , n1528 );
buf ( n5974 , n1766 );
buf ( n5975 , n1529 );
buf ( n5976 , n96 );
buf ( n5977 , n1953 );
buf ( n5978 , n1918 );
buf ( n5979 , n572 );
buf ( n5980 , n1295 );
buf ( n5981 , n2004 );
buf ( n5982 , n965 );
buf ( n5983 , n566 );
buf ( n5984 , n1376 );
buf ( n5985 , n1225 );
buf ( n5986 , n1207 );
buf ( n5987 , n664 );
buf ( n5988 , n147 );
buf ( n5989 , n1665 );
buf ( n5990 , n345 );
buf ( n5991 , n943 );
buf ( n5992 , n1757 );
buf ( n5993 , n2032 );
buf ( n5994 , n721 );
buf ( n5995 , n294 );
buf ( n5996 , n183 );
buf ( n5997 , n1932 );
buf ( n5998 , n773 );
buf ( n5999 , n1055 );
buf ( n6000 , n1213 );
buf ( n6001 , n1829 );
buf ( n6002 , n1655 );
buf ( n6003 , n894 );
buf ( n6004 , n1810 );
buf ( n6005 , n1355 );
buf ( n6006 , n337 );
buf ( n6007 , n1945 );
buf ( n6008 , n1924 );
buf ( n6009 , n926 );
buf ( n6010 , n639 );
buf ( n6011 , n1569 );
buf ( n6012 , n653 );
buf ( n6013 , n1656 );
buf ( n6014 , n1382 );
buf ( n6015 , n74 );
buf ( n6016 , n1329 );
buf ( n6017 , n463 );
buf ( n6018 , n2033 );
buf ( n6019 , n582 );
buf ( n6020 , n68 );
buf ( n6021 , n776 );
buf ( n6022 , n1019 );
buf ( n6023 , n2024 );
buf ( n6024 , n1434 );
buf ( n6025 , n259 );
buf ( n6026 , n1738 );
buf ( n6027 , n1318 );
buf ( n6028 , n198 );
buf ( n6029 , n808 );
buf ( n6030 , n699 );
buf ( n6031 , n1497 );
buf ( n6032 , n167 );
buf ( n6033 , n517 );
buf ( n6034 , n982 );
buf ( n6035 , n110 );
buf ( n6036 , n2007 );
buf ( n6037 , n1044 );
buf ( n6038 , n429 );
buf ( n6039 , n576 );
buf ( n6040 , n528 );
buf ( n6041 , n47 );
buf ( n6042 , n1378 );
buf ( n6043 , n235 );
buf ( n6044 , n427 );
buf ( n6045 , n436 );
buf ( n6046 , n828 );
buf ( n6047 , n1798 );
buf ( n6048 , n1747 );
buf ( n6049 , n859 );
buf ( n6050 , n1202 );
buf ( n6051 , n1833 );
buf ( n6052 , n1365 );
buf ( n6053 , n1788 );
buf ( n6054 , n1796 );
buf ( n6055 , n976 );
buf ( n6056 , n1150 );
buf ( n6057 , n306 );
buf ( n6058 , n741 );
buf ( n6059 , n778 );
buf ( n6060 , n1252 );
buf ( n6061 , n1852 );
buf ( n6062 , n93 );
buf ( n6063 , n1229 );
buf ( n6064 , n1080 );
buf ( n6065 , n1142 );
buf ( n6066 , n810 );
buf ( n6067 , n407 );
buf ( n6068 , n593 );
buf ( n6069 , n934 );
buf ( n6070 , n1372 );
buf ( n6071 , n1545 );
buf ( n6072 , n1687 );
buf ( n6073 , n526 );
buf ( n6074 , n1489 );
buf ( n6075 , n1283 );
buf ( n6076 , n1049 );
buf ( n6077 , n14 );
buf ( n6078 , n1036 );
buf ( n6079 , n697 );
buf ( n6080 , n1481 );
buf ( n6081 , n174 );
buf ( n6082 , n591 );
buf ( n6083 , n334 );
buf ( n6084 , n458 );
buf ( n6085 , n1471 );
buf ( n6086 , n184 );
buf ( n6087 , n724 );
buf ( n6088 , n1254 );
buf ( n6089 , n979 );
buf ( n6090 , n1821 );
buf ( n6091 , n936 );
buf ( n6092 , n199 );
buf ( n6093 , n1094 );
buf ( n6094 , n573 );
buf ( n6095 , n1858 );
buf ( n6096 , n1383 );
buf ( n6097 , n305 );
buf ( n6098 , n385 );
buf ( n6099 , n592 );
buf ( n6100 , n749 );
buf ( n6101 , n1845 );
buf ( n6102 , n1823 );
buf ( n6103 , n2001 );
buf ( n6104 , n541 );
buf ( n6105 , n1236 );
buf ( n6106 , n1723 );
buf ( n6107 , n1367 );
buf ( n6108 , n1558 );
buf ( n6109 , n897 );
buf ( n6110 , n1402 );
buf ( n6111 , n1176 );
buf ( n6112 , n996 );
buf ( n6113 , n1712 );
buf ( n6114 , n1278 );
buf ( n6115 , n1488 );
buf ( n6116 , n762 );
buf ( n6117 , n347 );
buf ( n6118 , n1667 );
buf ( n6119 , n1644 );
buf ( n6120 , n1467 );
buf ( n6121 , n1843 );
buf ( n6122 , n1238 );
buf ( n6123 , n502 );
buf ( n6124 , n1873 );
buf ( n6125 , n1157 );
buf ( n6126 , n671 );
buf ( n6127 , n1135 );
buf ( n6128 , n2046 );
buf ( n6129 , n729 );
buf ( n6130 , n1293 );
buf ( n6131 , n1128 );
buf ( n6132 , n1338 );
buf ( n6133 , n961 );
buf ( n6134 , n274 );
buf ( n6135 , n1720 );
buf ( n6136 , n1730 );
buf ( n6137 , n851 );
buf ( n6138 , n8 );
buf ( n6139 , n1039 );
buf ( n6140 , n1041 );
buf ( n6141 , n960 );
buf ( n6142 , n1394 );
buf ( n6143 , n1370 );
buf ( n6144 , n660 );
buf ( n6145 , n642 );
buf ( n6146 , n1698 );
buf ( n6147 , n1111 );
buf ( n6148 , n59 );
buf ( n6149 , n547 );
buf ( n6150 , n5126 );
buf ( n6151 , n5127 );
or ( n6152 , n6150 , n6151 );
buf ( n6153 , n5128 );
or ( n6154 , n6152 , n6153 );
buf ( n6155 , n5129 );
or ( n6156 , n6154 , n6155 );
buf ( n6157 , n5130 );
or ( n6158 , n6156 , n6157 );
buf ( n6159 , n5131 );
or ( n6160 , n6158 , n6159 );
buf ( n6161 , n5132 );
or ( n6162 , n6160 , n6161 );
buf ( n6163 , n5133 );
or ( n6164 , n6162 , n6163 );
buf ( n6165 , n5134 );
or ( n6166 , n6164 , n6165 );
buf ( n6167 , n5135 );
or ( n6168 , n6166 , n6167 );
buf ( n6169 , n5136 );
or ( n6170 , n6168 , n6169 );
buf ( n6171 , n5137 );
or ( n6172 , n6170 , n6171 );
buf ( n6173 , n5138 );
or ( n6174 , n6172 , n6173 );
buf ( n6175 , n5139 );
or ( n6176 , n6174 , n6175 );
buf ( n6177 , n5140 );
or ( n6178 , n6176 , n6177 );
buf ( n6179 , n5141 );
or ( n6180 , n6178 , n6179 );
buf ( n6181 , n5142 );
or ( n6182 , n6180 , n6181 );
buf ( n6183 , n5143 );
or ( n6184 , n6182 , n6183 );
buf ( n6185 , n5144 );
or ( n6186 , n6184 , n6185 );
buf ( n6187 , n5145 );
or ( n6188 , n6186 , n6187 );
buf ( n6189 , n5146 );
or ( n6190 , n6188 , n6189 );
buf ( n6191 , n5147 );
or ( n6192 , n6190 , n6191 );
buf ( n6193 , n5148 );
or ( n6194 , n6192 , n6193 );
buf ( n6195 , n5149 );
or ( n6196 , n6194 , n6195 );
buf ( n6197 , n5150 );
or ( n6198 , n6196 , n6197 );
buf ( n6199 , n5151 );
or ( n6200 , n6198 , n6199 );
buf ( n6201 , n5152 );
or ( n6202 , n6200 , n6201 );
buf ( n6203 , n5153 );
or ( n6204 , n6202 , n6203 );
buf ( n6205 , n5154 );
or ( n6206 , n6204 , n6205 );
buf ( n6207 , n5155 );
or ( n6208 , n6206 , n6207 );
buf ( n6209 , n5156 );
or ( n6210 , n6208 , n6209 );
buf ( n6211 , n5157 );
or ( n6212 , n6210 , n6211 );
buf ( n6213 , n5158 );
or ( n6214 , n6212 , n6213 );
buf ( n6215 , n5159 );
or ( n6216 , n6214 , n6215 );
buf ( n6217 , n5160 );
or ( n6218 , n6216 , n6217 );
buf ( n6219 , n5161 );
or ( n6220 , n6218 , n6219 );
buf ( n6221 , n5162 );
or ( n6222 , n6220 , n6221 );
buf ( n6223 , n5163 );
or ( n6224 , n6222 , n6223 );
buf ( n6225 , n5164 );
or ( n6226 , n6224 , n6225 );
buf ( n6227 , n5165 );
or ( n6228 , n6226 , n6227 );
buf ( n6229 , n5166 );
or ( n6230 , n6228 , n6229 );
buf ( n6231 , n5167 );
or ( n6232 , n6230 , n6231 );
buf ( n6233 , n5168 );
or ( n6234 , n6232 , n6233 );
buf ( n6235 , n5169 );
or ( n6236 , n6234 , n6235 );
buf ( n6237 , n5170 );
or ( n6238 , n6236 , n6237 );
buf ( n6239 , n5171 );
or ( n6240 , n6238 , n6239 );
buf ( n6241 , n5172 );
or ( n6242 , n6240 , n6241 );
buf ( n6243 , n5173 );
or ( n6244 , n6242 , n6243 );
buf ( n6245 , n5174 );
or ( n6246 , n6244 , n6245 );
buf ( n6247 , n5175 );
or ( n6248 , n6246 , n6247 );
buf ( n6249 , n5176 );
or ( n6250 , n6248 , n6249 );
buf ( n6251 , n5177 );
or ( n6252 , n6250 , n6251 );
buf ( n6253 , n5178 );
or ( n6254 , n6252 , n6253 );
buf ( n6255 , n5179 );
or ( n6256 , n6254 , n6255 );
buf ( n6257 , n5180 );
or ( n6258 , n6256 , n6257 );
buf ( n6259 , n5181 );
or ( n6260 , n6258 , n6259 );
buf ( n6261 , n5182 );
or ( n6262 , n6260 , n6261 );
buf ( n6263 , n5183 );
or ( n6264 , n6262 , n6263 );
buf ( n6265 , n5184 );
or ( n6266 , n6264 , n6265 );
buf ( n6267 , n5185 );
or ( n6268 , n6266 , n6267 );
buf ( n6269 , n5186 );
or ( n6270 , n6268 , n6269 );
buf ( n6271 , n5187 );
or ( n6272 , n6270 , n6271 );
buf ( n6273 , n5188 );
or ( n6274 , n6272 , n6273 );
buf ( n6275 , n5189 );
or ( n6276 , n6274 , n6275 );
buf ( n6277 , n5190 );
or ( n6278 , n6276 , n6277 );
buf ( n6279 , n5191 );
or ( n6280 , n6278 , n6279 );
buf ( n6281 , n5192 );
or ( n6282 , n6280 , n6281 );
buf ( n6283 , n5193 );
or ( n6284 , n6282 , n6283 );
buf ( n6285 , n5194 );
or ( n6286 , n6284 , n6285 );
buf ( n6287 , n5195 );
or ( n6288 , n6286 , n6287 );
buf ( n6289 , n5196 );
or ( n6290 , n6288 , n6289 );
buf ( n6291 , n5197 );
or ( n6292 , n6290 , n6291 );
buf ( n6293 , n5198 );
or ( n6294 , n6292 , n6293 );
buf ( n6295 , n5199 );
or ( n6296 , n6294 , n6295 );
buf ( n6297 , n5200 );
or ( n6298 , n6296 , n6297 );
buf ( n6299 , n5201 );
or ( n6300 , n6298 , n6299 );
buf ( n6301 , n5202 );
or ( n6302 , n6300 , n6301 );
buf ( n6303 , n5203 );
or ( n6304 , n6302 , n6303 );
buf ( n6305 , n5204 );
or ( n6306 , n6304 , n6305 );
buf ( n6307 , n5205 );
or ( n6308 , n6306 , n6307 );
buf ( n6309 , n5206 );
or ( n6310 , n6308 , n6309 );
buf ( n6311 , n5207 );
or ( n6312 , n6310 , n6311 );
buf ( n6313 , n5208 );
or ( n6314 , n6312 , n6313 );
buf ( n6315 , n5209 );
or ( n6316 , n6314 , n6315 );
buf ( n6317 , n5210 );
or ( n6318 , n6316 , n6317 );
buf ( n6319 , n5211 );
or ( n6320 , n6318 , n6319 );
buf ( n6321 , n5212 );
or ( n6322 , n6320 , n6321 );
buf ( n6323 , n5213 );
or ( n6324 , n6322 , n6323 );
buf ( n6325 , n5214 );
or ( n6326 , n6324 , n6325 );
buf ( n6327 , n5215 );
or ( n6328 , n6326 , n6327 );
buf ( n6329 , n5216 );
or ( n6330 , n6328 , n6329 );
buf ( n6331 , n5217 );
or ( n6332 , n6330 , n6331 );
buf ( n6333 , n5218 );
or ( n6334 , n6332 , n6333 );
buf ( n6335 , n5219 );
or ( n6336 , n6334 , n6335 );
buf ( n6337 , n5220 );
or ( n6338 , n6336 , n6337 );
buf ( n6339 , n5221 );
or ( n6340 , n6338 , n6339 );
buf ( n6341 , n5222 );
or ( n6342 , n6340 , n6341 );
buf ( n6343 , n5223 );
or ( n6344 , n6342 , n6343 );
buf ( n6345 , n5224 );
or ( n6346 , n6344 , n6345 );
buf ( n6347 , n5225 );
or ( n6348 , n6346 , n6347 );
buf ( n6349 , n5226 );
or ( n6350 , n6348 , n6349 );
buf ( n6351 , n5227 );
or ( n6352 , n6350 , n6351 );
buf ( n6353 , n5228 );
or ( n6354 , n6352 , n6353 );
buf ( n6355 , n5229 );
or ( n6356 , n6354 , n6355 );
buf ( n6357 , n5230 );
or ( n6358 , n6356 , n6357 );
buf ( n6359 , n5231 );
or ( n6360 , n6358 , n6359 );
buf ( n6361 , n5232 );
or ( n6362 , n6360 , n6361 );
buf ( n6363 , n5233 );
or ( n6364 , n6362 , n6363 );
buf ( n6365 , n5234 );
or ( n6366 , n6364 , n6365 );
buf ( n6367 , n5235 );
or ( n6368 , n6366 , n6367 );
buf ( n6369 , n5236 );
or ( n6370 , n6368 , n6369 );
buf ( n6371 , n5237 );
or ( n6372 , n6370 , n6371 );
buf ( n6373 , n5238 );
or ( n6374 , n6372 , n6373 );
buf ( n6375 , n5239 );
or ( n6376 , n6374 , n6375 );
buf ( n6377 , n5240 );
or ( n6378 , n6376 , n6377 );
buf ( n6379 , n5241 );
or ( n6380 , n6378 , n6379 );
buf ( n6381 , n5242 );
or ( n6382 , n6380 , n6381 );
buf ( n6383 , n5243 );
or ( n6384 , n6382 , n6383 );
buf ( n6385 , n5244 );
or ( n6386 , n6384 , n6385 );
buf ( n6387 , n5245 );
or ( n6388 , n6386 , n6387 );
buf ( n6389 , n5246 );
or ( n6390 , n6388 , n6389 );
buf ( n6391 , n5247 );
or ( n6392 , n6390 , n6391 );
buf ( n6393 , n5248 );
or ( n6394 , n6392 , n6393 );
buf ( n6395 , n5249 );
or ( n6396 , n6394 , n6395 );
buf ( n6397 , n5250 );
or ( n6398 , n6396 , n6397 );
buf ( n6399 , n5251 );
or ( n6400 , n6398 , n6399 );
buf ( n6401 , n5252 );
or ( n6402 , n6400 , n6401 );
buf ( n6403 , n5253 );
or ( n6404 , n6402 , n6403 );
buf ( n6405 , n5254 );
or ( n6406 , n6404 , n6405 );
buf ( n6407 , n5255 );
or ( n6408 , n6406 , n6407 );
buf ( n6409 , n5256 );
or ( n6410 , n6408 , n6409 );
buf ( n6411 , n5257 );
or ( n6412 , n6410 , n6411 );
buf ( n6413 , n5258 );
or ( n6414 , n6412 , n6413 );
buf ( n6415 , n5259 );
or ( n6416 , n6414 , n6415 );
buf ( n6417 , n5260 );
or ( n6418 , n6416 , n6417 );
buf ( n6419 , n5261 );
or ( n6420 , n6418 , n6419 );
buf ( n6421 , n5262 );
or ( n6422 , n6420 , n6421 );
buf ( n6423 , n5263 );
or ( n6424 , n6422 , n6423 );
buf ( n6425 , n5264 );
or ( n6426 , n6424 , n6425 );
buf ( n6427 , n5265 );
or ( n6428 , n6426 , n6427 );
buf ( n6429 , n5266 );
or ( n6430 , n6428 , n6429 );
buf ( n6431 , n5267 );
or ( n6432 , n6430 , n6431 );
buf ( n6433 , n5268 );
or ( n6434 , n6432 , n6433 );
buf ( n6435 , n5269 );
or ( n6436 , n6434 , n6435 );
buf ( n6437 , n5270 );
or ( n6438 , n6436 , n6437 );
buf ( n6439 , n5271 );
or ( n6440 , n6438 , n6439 );
buf ( n6441 , n5272 );
or ( n6442 , n6440 , n6441 );
buf ( n6443 , n5273 );
or ( n6444 , n6442 , n6443 );
buf ( n6445 , n5274 );
or ( n6446 , n6444 , n6445 );
buf ( n6447 , n5275 );
or ( n6448 , n6446 , n6447 );
buf ( n6449 , n5276 );
or ( n6450 , n6448 , n6449 );
buf ( n6451 , n5277 );
or ( n6452 , n6450 , n6451 );
buf ( n6453 , n5278 );
or ( n6454 , n6452 , n6453 );
buf ( n6455 , n5279 );
or ( n6456 , n6454 , n6455 );
buf ( n6457 , n5280 );
or ( n6458 , n6456 , n6457 );
buf ( n6459 , n5281 );
or ( n6460 , n6458 , n6459 );
buf ( n6461 , n5282 );
or ( n6462 , n6460 , n6461 );
buf ( n6463 , n5283 );
or ( n6464 , n6462 , n6463 );
buf ( n6465 , n5284 );
or ( n6466 , n6464 , n6465 );
buf ( n6467 , n5285 );
or ( n6468 , n6466 , n6467 );
buf ( n6469 , n5286 );
or ( n6470 , n6468 , n6469 );
buf ( n6471 , n5287 );
or ( n6472 , n6470 , n6471 );
buf ( n6473 , n5288 );
or ( n6474 , n6472 , n6473 );
buf ( n6475 , n5289 );
or ( n6476 , n6474 , n6475 );
buf ( n6477 , n5290 );
or ( n6478 , n6476 , n6477 );
buf ( n6479 , n5291 );
or ( n6480 , n6478 , n6479 );
buf ( n6481 , n5292 );
or ( n6482 , n6480 , n6481 );
buf ( n6483 , n5293 );
or ( n6484 , n6482 , n6483 );
buf ( n6485 , n5294 );
or ( n6486 , n6484 , n6485 );
buf ( n6487 , n5295 );
or ( n6488 , n6486 , n6487 );
buf ( n6489 , n5296 );
or ( n6490 , n6488 , n6489 );
buf ( n6491 , n5297 );
or ( n6492 , n6490 , n6491 );
buf ( n6493 , n5298 );
or ( n6494 , n6492 , n6493 );
buf ( n6495 , n5299 );
or ( n6496 , n6494 , n6495 );
buf ( n6497 , n5300 );
or ( n6498 , n6496 , n6497 );
buf ( n6499 , n5301 );
or ( n6500 , n6498 , n6499 );
buf ( n6501 , n5302 );
or ( n6502 , n6500 , n6501 );
buf ( n6503 , n5303 );
or ( n6504 , n6502 , n6503 );
buf ( n6505 , n5304 );
or ( n6506 , n6504 , n6505 );
buf ( n6507 , n5305 );
or ( n6508 , n6506 , n6507 );
buf ( n6509 , n5306 );
or ( n6510 , n6508 , n6509 );
buf ( n6511 , n5307 );
or ( n6512 , n6510 , n6511 );
buf ( n6513 , n5308 );
or ( n6514 , n6512 , n6513 );
buf ( n6515 , n5309 );
or ( n6516 , n6514 , n6515 );
buf ( n6517 , n5310 );
or ( n6518 , n6516 , n6517 );
buf ( n6519 , n5311 );
or ( n6520 , n6518 , n6519 );
buf ( n6521 , n5312 );
or ( n6522 , n6520 , n6521 );
buf ( n6523 , n5313 );
or ( n6524 , n6522 , n6523 );
buf ( n6525 , n5314 );
or ( n6526 , n6524 , n6525 );
buf ( n6527 , n5315 );
or ( n6528 , n6526 , n6527 );
buf ( n6529 , n5316 );
or ( n6530 , n6528 , n6529 );
buf ( n6531 , n5317 );
or ( n6532 , n6530 , n6531 );
buf ( n6533 , n5318 );
or ( n6534 , n6532 , n6533 );
buf ( n6535 , n5319 );
or ( n6536 , n6534 , n6535 );
buf ( n6537 , n5320 );
or ( n6538 , n6536 , n6537 );
buf ( n6539 , n5321 );
or ( n6540 , n6538 , n6539 );
buf ( n6541 , n5322 );
or ( n6542 , n6540 , n6541 );
buf ( n6543 , n5323 );
or ( n6544 , n6542 , n6543 );
buf ( n6545 , n5324 );
or ( n6546 , n6544 , n6545 );
buf ( n6547 , n5325 );
or ( n6548 , n6546 , n6547 );
buf ( n6549 , n5326 );
or ( n6550 , n6548 , n6549 );
buf ( n6551 , n5327 );
or ( n6552 , n6550 , n6551 );
buf ( n6553 , n5328 );
or ( n6554 , n6552 , n6553 );
buf ( n6555 , n5329 );
or ( n6556 , n6554 , n6555 );
buf ( n6557 , n5330 );
or ( n6558 , n6556 , n6557 );
buf ( n6559 , n5331 );
or ( n6560 , n6558 , n6559 );
buf ( n6561 , n5332 );
or ( n6562 , n6560 , n6561 );
buf ( n6563 , n5333 );
or ( n6564 , n6562 , n6563 );
buf ( n6565 , n5334 );
or ( n6566 , n6564 , n6565 );
buf ( n6567 , n5335 );
or ( n6568 , n6566 , n6567 );
buf ( n6569 , n5336 );
or ( n6570 , n6568 , n6569 );
buf ( n6571 , n5337 );
or ( n6572 , n6570 , n6571 );
buf ( n6573 , n5338 );
or ( n6574 , n6572 , n6573 );
buf ( n6575 , n5339 );
or ( n6576 , n6574 , n6575 );
buf ( n6577 , n5340 );
or ( n6578 , n6576 , n6577 );
buf ( n6579 , n5341 );
or ( n6580 , n6578 , n6579 );
buf ( n6581 , n5342 );
or ( n6582 , n6580 , n6581 );
buf ( n6583 , n5343 );
or ( n6584 , n6582 , n6583 );
buf ( n6585 , n5344 );
or ( n6586 , n6584 , n6585 );
buf ( n6587 , n5345 );
or ( n6588 , n6586 , n6587 );
buf ( n6589 , n5346 );
or ( n6590 , n6588 , n6589 );
buf ( n6591 , n5347 );
or ( n6592 , n6590 , n6591 );
buf ( n6593 , n5348 );
or ( n6594 , n6592 , n6593 );
buf ( n6595 , n5349 );
or ( n6596 , n6594 , n6595 );
buf ( n6597 , n5350 );
or ( n6598 , n6596 , n6597 );
buf ( n6599 , n5351 );
or ( n6600 , n6598 , n6599 );
buf ( n6601 , n5352 );
or ( n6602 , n6600 , n6601 );
buf ( n6603 , n5353 );
or ( n6604 , n6602 , n6603 );
buf ( n6605 , n5354 );
or ( n6606 , n6604 , n6605 );
buf ( n6607 , n5355 );
or ( n6608 , n6606 , n6607 );
buf ( n6609 , n5356 );
or ( n6610 , n6608 , n6609 );
buf ( n6611 , n5357 );
or ( n6612 , n6610 , n6611 );
buf ( n6613 , n5358 );
or ( n6614 , n6612 , n6613 );
buf ( n6615 , n5359 );
or ( n6616 , n6614 , n6615 );
buf ( n6617 , n5360 );
or ( n6618 , n6616 , n6617 );
buf ( n6619 , n5361 );
or ( n6620 , n6618 , n6619 );
buf ( n6621 , n5362 );
or ( n6622 , n6620 , n6621 );
buf ( n6623 , n5363 );
or ( n6624 , n6622 , n6623 );
buf ( n6625 , n5364 );
or ( n6626 , n6624 , n6625 );
buf ( n6627 , n5365 );
or ( n6628 , n6626 , n6627 );
buf ( n6629 , n5366 );
or ( n6630 , n6628 , n6629 );
buf ( n6631 , n5367 );
or ( n6632 , n6630 , n6631 );
buf ( n6633 , n5368 );
or ( n6634 , n6632 , n6633 );
buf ( n6635 , n5369 );
or ( n6636 , n6634 , n6635 );
buf ( n6637 , n5370 );
or ( n6638 , n6636 , n6637 );
buf ( n6639 , n5371 );
or ( n6640 , n6638 , n6639 );
buf ( n6641 , n5372 );
or ( n6642 , n6640 , n6641 );
buf ( n6643 , n5373 );
or ( n6644 , n6642 , n6643 );
buf ( n6645 , n5374 );
or ( n6646 , n6644 , n6645 );
buf ( n6647 , n5375 );
or ( n6648 , n6646 , n6647 );
buf ( n6649 , n5376 );
or ( n6650 , n6648 , n6649 );
buf ( n6651 , n5377 );
or ( n6652 , n6650 , n6651 );
buf ( n6653 , n5378 );
or ( n6654 , n6652 , n6653 );
buf ( n6655 , n5379 );
or ( n6656 , n6654 , n6655 );
buf ( n6657 , n5380 );
or ( n6658 , n6656 , n6657 );
buf ( n6659 , n5381 );
or ( n6660 , n6658 , n6659 );
buf ( n6661 , n5382 );
or ( n6662 , n6660 , n6661 );
buf ( n6663 , n5383 );
or ( n6664 , n6662 , n6663 );
buf ( n6665 , n5384 );
or ( n6666 , n6664 , n6665 );
buf ( n6667 , n5385 );
or ( n6668 , n6666 , n6667 );
buf ( n6669 , n5386 );
or ( n6670 , n6668 , n6669 );
buf ( n6671 , n5387 );
or ( n6672 , n6670 , n6671 );
buf ( n6673 , n5388 );
or ( n6674 , n6672 , n6673 );
buf ( n6675 , n5389 );
or ( n6676 , n6674 , n6675 );
buf ( n6677 , n5390 );
or ( n6678 , n6676 , n6677 );
buf ( n6679 , n5391 );
or ( n6680 , n6678 , n6679 );
buf ( n6681 , n5392 );
or ( n6682 , n6680 , n6681 );
buf ( n6683 , n5393 );
or ( n6684 , n6682 , n6683 );
buf ( n6685 , n5394 );
or ( n6686 , n6684 , n6685 );
buf ( n6687 , n5395 );
or ( n6688 , n6686 , n6687 );
buf ( n6689 , n5396 );
or ( n6690 , n6688 , n6689 );
buf ( n6691 , n5397 );
or ( n6692 , n6690 , n6691 );
buf ( n6693 , n5398 );
or ( n6694 , n6692 , n6693 );
buf ( n6695 , n5399 );
or ( n6696 , n6694 , n6695 );
buf ( n6697 , n5400 );
or ( n6698 , n6696 , n6697 );
buf ( n6699 , n5401 );
or ( n6700 , n6698 , n6699 );
buf ( n6701 , n5402 );
or ( n6702 , n6700 , n6701 );
buf ( n6703 , n5403 );
or ( n6704 , n6702 , n6703 );
buf ( n6705 , n5404 );
or ( n6706 , n6704 , n6705 );
buf ( n6707 , n5405 );
or ( n6708 , n6706 , n6707 );
buf ( n6709 , n5406 );
or ( n6710 , n6708 , n6709 );
buf ( n6711 , n5407 );
or ( n6712 , n6710 , n6711 );
buf ( n6713 , n5408 );
or ( n6714 , n6712 , n6713 );
buf ( n6715 , n5409 );
or ( n6716 , n6714 , n6715 );
buf ( n6717 , n5410 );
or ( n6718 , n6716 , n6717 );
buf ( n6719 , n5411 );
or ( n6720 , n6718 , n6719 );
buf ( n6721 , n5412 );
or ( n6722 , n6720 , n6721 );
buf ( n6723 , n5413 );
or ( n6724 , n6722 , n6723 );
buf ( n6725 , n5414 );
or ( n6726 , n6724 , n6725 );
buf ( n6727 , n5415 );
or ( n6728 , n6726 , n6727 );
buf ( n6729 , n5416 );
or ( n6730 , n6728 , n6729 );
buf ( n6731 , n5417 );
or ( n6732 , n6730 , n6731 );
buf ( n6733 , n5418 );
or ( n6734 , n6732 , n6733 );
buf ( n6735 , n5419 );
or ( n6736 , n6734 , n6735 );
buf ( n6737 , n5420 );
or ( n6738 , n6736 , n6737 );
buf ( n6739 , n5421 );
or ( n6740 , n6738 , n6739 );
buf ( n6741 , n5422 );
or ( n6742 , n6740 , n6741 );
buf ( n6743 , n5423 );
or ( n6744 , n6742 , n6743 );
buf ( n6745 , n5424 );
or ( n6746 , n6744 , n6745 );
buf ( n6747 , n5425 );
or ( n6748 , n6746 , n6747 );
buf ( n6749 , n5426 );
or ( n6750 , n6748 , n6749 );
buf ( n6751 , n5427 );
or ( n6752 , n6750 , n6751 );
buf ( n6753 , n5428 );
or ( n6754 , n6752 , n6753 );
buf ( n6755 , n5429 );
or ( n6756 , n6754 , n6755 );
buf ( n6757 , n5430 );
or ( n6758 , n6756 , n6757 );
buf ( n6759 , n5431 );
or ( n6760 , n6758 , n6759 );
buf ( n6761 , n5432 );
or ( n6762 , n6760 , n6761 );
buf ( n6763 , n5433 );
or ( n6764 , n6762 , n6763 );
buf ( n6765 , n5434 );
or ( n6766 , n6764 , n6765 );
buf ( n6767 , n5435 );
or ( n6768 , n6766 , n6767 );
buf ( n6769 , n5436 );
or ( n6770 , n6768 , n6769 );
buf ( n6771 , n5437 );
or ( n6772 , n6770 , n6771 );
buf ( n6773 , n5438 );
or ( n6774 , n6772 , n6773 );
buf ( n6775 , n5439 );
or ( n6776 , n6774 , n6775 );
buf ( n6777 , n5440 );
or ( n6778 , n6776 , n6777 );
buf ( n6779 , n5441 );
or ( n6780 , n6778 , n6779 );
buf ( n6781 , n5442 );
or ( n6782 , n6780 , n6781 );
buf ( n6783 , n5443 );
or ( n6784 , n6782 , n6783 );
buf ( n6785 , n5444 );
or ( n6786 , n6784 , n6785 );
buf ( n6787 , n5445 );
or ( n6788 , n6786 , n6787 );
buf ( n6789 , n5446 );
or ( n6790 , n6788 , n6789 );
buf ( n6791 , n5447 );
or ( n6792 , n6790 , n6791 );
buf ( n6793 , n5448 );
or ( n6794 , n6792 , n6793 );
buf ( n6795 , n5449 );
or ( n6796 , n6794 , n6795 );
buf ( n6797 , n5450 );
or ( n6798 , n6796 , n6797 );
buf ( n6799 , n5451 );
or ( n6800 , n6798 , n6799 );
buf ( n6801 , n5452 );
or ( n6802 , n6800 , n6801 );
buf ( n6803 , n5453 );
or ( n6804 , n6802 , n6803 );
buf ( n6805 , n5454 );
or ( n6806 , n6804 , n6805 );
buf ( n6807 , n5455 );
or ( n6808 , n6806 , n6807 );
buf ( n6809 , n5456 );
or ( n6810 , n6808 , n6809 );
buf ( n6811 , n5457 );
or ( n6812 , n6810 , n6811 );
buf ( n6813 , n5458 );
or ( n6814 , n6812 , n6813 );
buf ( n6815 , n5459 );
or ( n6816 , n6814 , n6815 );
buf ( n6817 , n5460 );
or ( n6818 , n6816 , n6817 );
buf ( n6819 , n5461 );
or ( n6820 , n6818 , n6819 );
buf ( n6821 , n5462 );
or ( n6822 , n6820 , n6821 );
buf ( n6823 , n5463 );
or ( n6824 , n6822 , n6823 );
buf ( n6825 , n5464 );
or ( n6826 , n6824 , n6825 );
buf ( n6827 , n5465 );
or ( n6828 , n6826 , n6827 );
buf ( n6829 , n5466 );
or ( n6830 , n6828 , n6829 );
buf ( n6831 , n5467 );
or ( n6832 , n6830 , n6831 );
buf ( n6833 , n5468 );
or ( n6834 , n6832 , n6833 );
buf ( n6835 , n5469 );
or ( n6836 , n6834 , n6835 );
buf ( n6837 , n5470 );
or ( n6838 , n6836 , n6837 );
buf ( n6839 , n5471 );
or ( n6840 , n6838 , n6839 );
buf ( n6841 , n5472 );
or ( n6842 , n6840 , n6841 );
buf ( n6843 , n5473 );
or ( n6844 , n6842 , n6843 );
buf ( n6845 , n5474 );
or ( n6846 , n6844 , n6845 );
buf ( n6847 , n5475 );
or ( n6848 , n6846 , n6847 );
buf ( n6849 , n5476 );
or ( n6850 , n6848 , n6849 );
buf ( n6851 , n5477 );
or ( n6852 , n6850 , n6851 );
buf ( n6853 , n5478 );
or ( n6854 , n6852 , n6853 );
buf ( n6855 , n5479 );
or ( n6856 , n6854 , n6855 );
buf ( n6857 , n5480 );
or ( n6858 , n6856 , n6857 );
buf ( n6859 , n5481 );
or ( n6860 , n6858 , n6859 );
buf ( n6861 , n5482 );
or ( n6862 , n6860 , n6861 );
buf ( n6863 , n5483 );
or ( n6864 , n6862 , n6863 );
buf ( n6865 , n5484 );
or ( n6866 , n6864 , n6865 );
buf ( n6867 , n5485 );
or ( n6868 , n6866 , n6867 );
buf ( n6869 , n5486 );
or ( n6870 , n6868 , n6869 );
buf ( n6871 , n5487 );
or ( n6872 , n6870 , n6871 );
buf ( n6873 , n5488 );
or ( n6874 , n6872 , n6873 );
buf ( n6875 , n5489 );
or ( n6876 , n6874 , n6875 );
buf ( n6877 , n5490 );
or ( n6878 , n6876 , n6877 );
buf ( n6879 , n5491 );
or ( n6880 , n6878 , n6879 );
buf ( n6881 , n5492 );
or ( n6882 , n6880 , n6881 );
buf ( n6883 , n5493 );
or ( n6884 , n6882 , n6883 );
buf ( n6885 , n5494 );
or ( n6886 , n6884 , n6885 );
buf ( n6887 , n5495 );
or ( n6888 , n6886 , n6887 );
buf ( n6889 , n5496 );
or ( n6890 , n6888 , n6889 );
buf ( n6891 , n5497 );
or ( n6892 , n6890 , n6891 );
buf ( n6893 , n5498 );
or ( n6894 , n6892 , n6893 );
buf ( n6895 , n5499 );
or ( n6896 , n6894 , n6895 );
buf ( n6897 , n5500 );
or ( n6898 , n6896 , n6897 );
buf ( n6899 , n5501 );
or ( n6900 , n6898 , n6899 );
buf ( n6901 , n5502 );
or ( n6902 , n6900 , n6901 );
buf ( n6903 , n5503 );
or ( n6904 , n6902 , n6903 );
buf ( n6905 , n5504 );
or ( n6906 , n6904 , n6905 );
buf ( n6907 , n5505 );
or ( n6908 , n6906 , n6907 );
buf ( n6909 , n5506 );
or ( n6910 , n6908 , n6909 );
buf ( n6911 , n5507 );
or ( n6912 , n6910 , n6911 );
buf ( n6913 , n5508 );
or ( n6914 , n6912 , n6913 );
buf ( n6915 , n5509 );
or ( n6916 , n6914 , n6915 );
buf ( n6917 , n5510 );
or ( n6918 , n6916 , n6917 );
buf ( n6919 , n5511 );
or ( n6920 , n6918 , n6919 );
buf ( n6921 , n5512 );
or ( n6922 , n6920 , n6921 );
buf ( n6923 , n5513 );
or ( n6924 , n6922 , n6923 );
buf ( n6925 , n5514 );
or ( n6926 , n6924 , n6925 );
buf ( n6927 , n5515 );
or ( n6928 , n6926 , n6927 );
buf ( n6929 , n5516 );
or ( n6930 , n6928 , n6929 );
buf ( n6931 , n5517 );
or ( n6932 , n6930 , n6931 );
buf ( n6933 , n5518 );
or ( n6934 , n6932 , n6933 );
buf ( n6935 , n5519 );
or ( n6936 , n6934 , n6935 );
buf ( n6937 , n5520 );
or ( n6938 , n6936 , n6937 );
buf ( n6939 , n5521 );
or ( n6940 , n6938 , n6939 );
buf ( n6941 , n5522 );
or ( n6942 , n6940 , n6941 );
buf ( n6943 , n5523 );
or ( n6944 , n6942 , n6943 );
buf ( n6945 , n5524 );
or ( n6946 , n6944 , n6945 );
buf ( n6947 , n5525 );
or ( n6948 , n6946 , n6947 );
buf ( n6949 , n5526 );
or ( n6950 , n6948 , n6949 );
buf ( n6951 , n5527 );
or ( n6952 , n6950 , n6951 );
buf ( n6953 , n5528 );
or ( n6954 , n6952 , n6953 );
buf ( n6955 , n5529 );
or ( n6956 , n6954 , n6955 );
buf ( n6957 , n5530 );
or ( n6958 , n6956 , n6957 );
buf ( n6959 , n5531 );
or ( n6960 , n6958 , n6959 );
buf ( n6961 , n5532 );
or ( n6962 , n6960 , n6961 );
buf ( n6963 , n5533 );
or ( n6964 , n6962 , n6963 );
buf ( n6965 , n5534 );
or ( n6966 , n6964 , n6965 );
buf ( n6967 , n5535 );
or ( n6968 , n6966 , n6967 );
buf ( n6969 , n5536 );
or ( n6970 , n6968 , n6969 );
buf ( n6971 , n5537 );
or ( n6972 , n6970 , n6971 );
buf ( n6973 , n5538 );
or ( n6974 , n6972 , n6973 );
buf ( n6975 , n5539 );
or ( n6976 , n6974 , n6975 );
buf ( n6977 , n5540 );
or ( n6978 , n6976 , n6977 );
buf ( n6979 , n5541 );
or ( n6980 , n6978 , n6979 );
buf ( n6981 , n5542 );
or ( n6982 , n6980 , n6981 );
buf ( n6983 , n5543 );
or ( n6984 , n6982 , n6983 );
buf ( n6985 , n5544 );
or ( n6986 , n6984 , n6985 );
buf ( n6987 , n5545 );
or ( n6988 , n6986 , n6987 );
buf ( n6989 , n5546 );
or ( n6990 , n6988 , n6989 );
buf ( n6991 , n5547 );
or ( n6992 , n6990 , n6991 );
buf ( n6993 , n5548 );
or ( n6994 , n6992 , n6993 );
buf ( n6995 , n5549 );
or ( n6996 , n6994 , n6995 );
buf ( n6997 , n5550 );
or ( n6998 , n6996 , n6997 );
buf ( n6999 , n5551 );
or ( n7000 , n6998 , n6999 );
buf ( n7001 , n5552 );
or ( n7002 , n7000 , n7001 );
buf ( n7003 , n5553 );
or ( n7004 , n7002 , n7003 );
buf ( n7005 , n5554 );
or ( n7006 , n7004 , n7005 );
buf ( n7007 , n5555 );
or ( n7008 , n7006 , n7007 );
buf ( n7009 , n5556 );
or ( n7010 , n7008 , n7009 );
buf ( n7011 , n5557 );
or ( n7012 , n7010 , n7011 );
buf ( n7013 , n5558 );
or ( n7014 , n7012 , n7013 );
buf ( n7015 , n5559 );
or ( n7016 , n7014 , n7015 );
buf ( n7017 , n5560 );
or ( n7018 , n7016 , n7017 );
buf ( n7019 , n5561 );
or ( n7020 , n7018 , n7019 );
buf ( n7021 , n5562 );
or ( n7022 , n7020 , n7021 );
buf ( n7023 , n5563 );
or ( n7024 , n7022 , n7023 );
buf ( n7025 , n5564 );
or ( n7026 , n7024 , n7025 );
buf ( n7027 , n5565 );
or ( n7028 , n7026 , n7027 );
buf ( n7029 , n5566 );
or ( n7030 , n7028 , n7029 );
buf ( n7031 , n5567 );
or ( n7032 , n7030 , n7031 );
buf ( n7033 , n5568 );
or ( n7034 , n7032 , n7033 );
buf ( n7035 , n5569 );
or ( n7036 , n7034 , n7035 );
buf ( n7037 , n5570 );
or ( n7038 , n7036 , n7037 );
buf ( n7039 , n5571 );
or ( n7040 , n7038 , n7039 );
buf ( n7041 , n5572 );
or ( n7042 , n7040 , n7041 );
buf ( n7043 , n5573 );
or ( n7044 , n7042 , n7043 );
buf ( n7045 , n5574 );
or ( n7046 , n7044 , n7045 );
buf ( n7047 , n5575 );
or ( n7048 , n7046 , n7047 );
buf ( n7049 , n5576 );
or ( n7050 , n7048 , n7049 );
buf ( n7051 , n5577 );
or ( n7052 , n7050 , n7051 );
buf ( n7053 , n5578 );
or ( n7054 , n7052 , n7053 );
buf ( n7055 , n5579 );
or ( n7056 , n7054 , n7055 );
buf ( n7057 , n5580 );
or ( n7058 , n7056 , n7057 );
buf ( n7059 , n5581 );
or ( n7060 , n7058 , n7059 );
buf ( n7061 , n5582 );
or ( n7062 , n7060 , n7061 );
buf ( n7063 , n5583 );
or ( n7064 , n7062 , n7063 );
buf ( n7065 , n5584 );
or ( n7066 , n7064 , n7065 );
buf ( n7067 , n5585 );
or ( n7068 , n7066 , n7067 );
buf ( n7069 , n5586 );
or ( n7070 , n7068 , n7069 );
buf ( n7071 , n5587 );
or ( n7072 , n7070 , n7071 );
buf ( n7073 , n5588 );
or ( n7074 , n7072 , n7073 );
buf ( n7075 , n5589 );
or ( n7076 , n7074 , n7075 );
buf ( n7077 , n5590 );
or ( n7078 , n7076 , n7077 );
buf ( n7079 , n5591 );
or ( n7080 , n7078 , n7079 );
buf ( n7081 , n5592 );
or ( n7082 , n7080 , n7081 );
buf ( n7083 , n5593 );
or ( n7084 , n7082 , n7083 );
buf ( n7085 , n5594 );
or ( n7086 , n7084 , n7085 );
buf ( n7087 , n5595 );
or ( n7088 , n7086 , n7087 );
buf ( n7089 , n5596 );
or ( n7090 , n7088 , n7089 );
buf ( n7091 , n5597 );
or ( n7092 , n7090 , n7091 );
buf ( n7093 , n5598 );
or ( n7094 , n7092 , n7093 );
buf ( n7095 , n5599 );
or ( n7096 , n7094 , n7095 );
buf ( n7097 , n5600 );
or ( n7098 , n7096 , n7097 );
buf ( n7099 , n5601 );
or ( n7100 , n7098 , n7099 );
buf ( n7101 , n5602 );
or ( n7102 , n7100 , n7101 );
buf ( n7103 , n5603 );
or ( n7104 , n7102 , n7103 );
buf ( n7105 , n5604 );
or ( n7106 , n7104 , n7105 );
buf ( n7107 , n5605 );
or ( n7108 , n7106 , n7107 );
buf ( n7109 , n5606 );
or ( n7110 , n7108 , n7109 );
buf ( n7111 , n5607 );
or ( n7112 , n7110 , n7111 );
buf ( n7113 , n5608 );
or ( n7114 , n7112 , n7113 );
buf ( n7115 , n5609 );
or ( n7116 , n7114 , n7115 );
buf ( n7117 , n5610 );
or ( n7118 , n7116 , n7117 );
buf ( n7119 , n5611 );
or ( n7120 , n7118 , n7119 );
buf ( n7121 , n5612 );
or ( n7122 , n7120 , n7121 );
buf ( n7123 , n5613 );
or ( n7124 , n7122 , n7123 );
buf ( n7125 , n5614 );
or ( n7126 , n7124 , n7125 );
buf ( n7127 , n5615 );
or ( n7128 , n7126 , n7127 );
buf ( n7129 , n5616 );
or ( n7130 , n7128 , n7129 );
buf ( n7131 , n5617 );
or ( n7132 , n7130 , n7131 );
buf ( n7133 , n5618 );
or ( n7134 , n7132 , n7133 );
buf ( n7135 , n5619 );
or ( n7136 , n7134 , n7135 );
buf ( n7137 , n5620 );
or ( n7138 , n7136 , n7137 );
buf ( n7139 , n5621 );
or ( n7140 , n7138 , n7139 );
buf ( n7141 , n5622 );
or ( n7142 , n7140 , n7141 );
buf ( n7143 , n5623 );
or ( n7144 , n7142 , n7143 );
buf ( n7145 , n5624 );
or ( n7146 , n7144 , n7145 );
buf ( n7147 , n5625 );
or ( n7148 , n7146 , n7147 );
buf ( n7149 , n5626 );
or ( n7150 , n7148 , n7149 );
buf ( n7151 , n5627 );
or ( n7152 , n7150 , n7151 );
buf ( n7153 , n5628 );
or ( n7154 , n7152 , n7153 );
buf ( n7155 , n5629 );
or ( n7156 , n7154 , n7155 );
buf ( n7157 , n5630 );
or ( n7158 , n7156 , n7157 );
buf ( n7159 , n5631 );
or ( n7160 , n7158 , n7159 );
buf ( n7161 , n5632 );
or ( n7162 , n7160 , n7161 );
buf ( n7163 , n5633 );
or ( n7164 , n7162 , n7163 );
buf ( n7165 , n5634 );
or ( n7166 , n7164 , n7165 );
buf ( n7167 , n5635 );
or ( n7168 , n7166 , n7167 );
buf ( n7169 , n5636 );
or ( n7170 , n7168 , n7169 );
buf ( n7171 , n5637 );
or ( n7172 , n7170 , n7171 );
buf ( n7173 , n5638 );
or ( n7174 , n7172 , n7173 );
buf ( n7175 , n5639 );
or ( n7176 , n7174 , n7175 );
buf ( n7177 , n5640 );
or ( n7178 , n7176 , n7177 );
buf ( n7179 , n5641 );
or ( n7180 , n7178 , n7179 );
buf ( n7181 , n5642 );
or ( n7182 , n7180 , n7181 );
buf ( n7183 , n5643 );
or ( n7184 , n7182 , n7183 );
buf ( n7185 , n5644 );
or ( n7186 , n7184 , n7185 );
buf ( n7187 , n5645 );
or ( n7188 , n7186 , n7187 );
buf ( n7189 , n5646 );
or ( n7190 , n7188 , n7189 );
buf ( n7191 , n5647 );
or ( n7192 , n7190 , n7191 );
buf ( n7193 , n5648 );
or ( n7194 , n7192 , n7193 );
buf ( n7195 , n5649 );
or ( n7196 , n7194 , n7195 );
buf ( n7197 , n5650 );
or ( n7198 , n7196 , n7197 );
buf ( n7199 , n5651 );
or ( n7200 , n7198 , n7199 );
buf ( n7201 , n5652 );
or ( n7202 , n7200 , n7201 );
buf ( n7203 , n5653 );
or ( n7204 , n7202 , n7203 );
buf ( n7205 , n5654 );
or ( n7206 , n7204 , n7205 );
buf ( n7207 , n5655 );
or ( n7208 , n7206 , n7207 );
buf ( n7209 , n5656 );
or ( n7210 , n7208 , n7209 );
buf ( n7211 , n5657 );
or ( n7212 , n7210 , n7211 );
buf ( n7213 , n5658 );
or ( n7214 , n7212 , n7213 );
buf ( n7215 , n5659 );
or ( n7216 , n7214 , n7215 );
buf ( n7217 , n5660 );
or ( n7218 , n7216 , n7217 );
buf ( n7219 , n5661 );
or ( n7220 , n7218 , n7219 );
buf ( n7221 , n5662 );
or ( n7222 , n7220 , n7221 );
buf ( n7223 , n5663 );
or ( n7224 , n7222 , n7223 );
buf ( n7225 , n5664 );
or ( n7226 , n7224 , n7225 );
buf ( n7227 , n5665 );
or ( n7228 , n7226 , n7227 );
buf ( n7229 , n5666 );
or ( n7230 , n7228 , n7229 );
buf ( n7231 , n5667 );
or ( n7232 , n7230 , n7231 );
buf ( n7233 , n5668 );
or ( n7234 , n7232 , n7233 );
buf ( n7235 , n5669 );
or ( n7236 , n7234 , n7235 );
buf ( n7237 , n5670 );
or ( n7238 , n7236 , n7237 );
buf ( n7239 , n5671 );
or ( n7240 , n7238 , n7239 );
buf ( n7241 , n5672 );
or ( n7242 , n7240 , n7241 );
buf ( n7243 , n5673 );
or ( n7244 , n7242 , n7243 );
buf ( n7245 , n5674 );
or ( n7246 , n7244 , n7245 );
buf ( n7247 , n5675 );
or ( n7248 , n7246 , n7247 );
buf ( n7249 , n5676 );
or ( n7250 , n7248 , n7249 );
buf ( n7251 , n5677 );
or ( n7252 , n7250 , n7251 );
buf ( n7253 , n5678 );
or ( n7254 , n7252 , n7253 );
buf ( n7255 , n5679 );
or ( n7256 , n7254 , n7255 );
buf ( n7257 , n5680 );
or ( n7258 , n7256 , n7257 );
buf ( n7259 , n5681 );
or ( n7260 , n7258 , n7259 );
buf ( n7261 , n5682 );
or ( n7262 , n7260 , n7261 );
buf ( n7263 , n5683 );
or ( n7264 , n7262 , n7263 );
buf ( n7265 , n5684 );
or ( n7266 , n7264 , n7265 );
buf ( n7267 , n5685 );
or ( n7268 , n7266 , n7267 );
buf ( n7269 , n5686 );
or ( n7270 , n7268 , n7269 );
buf ( n7271 , n5687 );
or ( n7272 , n7270 , n7271 );
buf ( n7273 , n5688 );
or ( n7274 , n7272 , n7273 );
buf ( n7275 , n5689 );
or ( n7276 , n7274 , n7275 );
buf ( n7277 , n5690 );
or ( n7278 , n7276 , n7277 );
buf ( n7279 , n5691 );
or ( n7280 , n7278 , n7279 );
buf ( n7281 , n5692 );
or ( n7282 , n7280 , n7281 );
buf ( n7283 , n5693 );
or ( n7284 , n7282 , n7283 );
buf ( n7285 , n5694 );
or ( n7286 , n7284 , n7285 );
buf ( n7287 , n5695 );
or ( n7288 , n7286 , n7287 );
buf ( n7289 , n5696 );
or ( n7290 , n7288 , n7289 );
buf ( n7291 , n5697 );
or ( n7292 , n7290 , n7291 );
buf ( n7293 , n5698 );
or ( n7294 , n7292 , n7293 );
buf ( n7295 , n5699 );
or ( n7296 , n7294 , n7295 );
buf ( n7297 , n5700 );
or ( n7298 , n7296 , n7297 );
buf ( n7299 , n5701 );
or ( n7300 , n7298 , n7299 );
buf ( n7301 , n5702 );
or ( n7302 , n7300 , n7301 );
buf ( n7303 , n5703 );
or ( n7304 , n7302 , n7303 );
buf ( n7305 , n5704 );
or ( n7306 , n7304 , n7305 );
buf ( n7307 , n5705 );
or ( n7308 , n7306 , n7307 );
buf ( n7309 , n5706 );
or ( n7310 , n7308 , n7309 );
buf ( n7311 , n5707 );
or ( n7312 , n7310 , n7311 );
buf ( n7313 , n5708 );
or ( n7314 , n7312 , n7313 );
buf ( n7315 , n5709 );
or ( n7316 , n7314 , n7315 );
buf ( n7317 , n5710 );
or ( n7318 , n7316 , n7317 );
buf ( n7319 , n5711 );
or ( n7320 , n7318 , n7319 );
buf ( n7321 , n5712 );
or ( n7322 , n7320 , n7321 );
buf ( n7323 , n5713 );
or ( n7324 , n7322 , n7323 );
buf ( n7325 , n5714 );
or ( n7326 , n7324 , n7325 );
buf ( n7327 , n5715 );
or ( n7328 , n7326 , n7327 );
buf ( n7329 , n5716 );
or ( n7330 , n7328 , n7329 );
buf ( n7331 , n5717 );
or ( n7332 , n7330 , n7331 );
buf ( n7333 , n5718 );
or ( n7334 , n7332 , n7333 );
buf ( n7335 , n5719 );
or ( n7336 , n7334 , n7335 );
buf ( n7337 , n5720 );
or ( n7338 , n7336 , n7337 );
buf ( n7339 , n5721 );
or ( n7340 , n7338 , n7339 );
buf ( n7341 , n5722 );
or ( n7342 , n7340 , n7341 );
buf ( n7343 , n5723 );
or ( n7344 , n7342 , n7343 );
buf ( n7345 , n5724 );
or ( n7346 , n7344 , n7345 );
buf ( n7347 , n5725 );
or ( n7348 , n7346 , n7347 );
buf ( n7349 , n5726 );
or ( n7350 , n7348 , n7349 );
buf ( n7351 , n5727 );
or ( n7352 , n7350 , n7351 );
buf ( n7353 , n5728 );
or ( n7354 , n7352 , n7353 );
buf ( n7355 , n5729 );
or ( n7356 , n7354 , n7355 );
buf ( n7357 , n5730 );
or ( n7358 , n7356 , n7357 );
buf ( n7359 , n5731 );
or ( n7360 , n7358 , n7359 );
buf ( n7361 , n5732 );
or ( n7362 , n7360 , n7361 );
buf ( n7363 , n5733 );
or ( n7364 , n7362 , n7363 );
buf ( n7365 , n5734 );
or ( n7366 , n7364 , n7365 );
buf ( n7367 , n5735 );
or ( n7368 , n7366 , n7367 );
buf ( n7369 , n5736 );
or ( n7370 , n7368 , n7369 );
buf ( n7371 , n5737 );
or ( n7372 , n7370 , n7371 );
buf ( n7373 , n5738 );
or ( n7374 , n7372 , n7373 );
buf ( n7375 , n5739 );
or ( n7376 , n7374 , n7375 );
buf ( n7377 , n5740 );
or ( n7378 , n7376 , n7377 );
buf ( n7379 , n5741 );
or ( n7380 , n7378 , n7379 );
buf ( n7381 , n5742 );
or ( n7382 , n7380 , n7381 );
buf ( n7383 , n5743 );
or ( n7384 , n7382 , n7383 );
buf ( n7385 , n5744 );
or ( n7386 , n7384 , n7385 );
buf ( n7387 , n5745 );
or ( n7388 , n7386 , n7387 );
buf ( n7389 , n5746 );
or ( n7390 , n7388 , n7389 );
buf ( n7391 , n5747 );
or ( n7392 , n7390 , n7391 );
buf ( n7393 , n5748 );
or ( n7394 , n7392 , n7393 );
buf ( n7395 , n5749 );
or ( n7396 , n7394 , n7395 );
buf ( n7397 , n5750 );
or ( n7398 , n7396 , n7397 );
buf ( n7399 , n5751 );
or ( n7400 , n7398 , n7399 );
buf ( n7401 , n5752 );
or ( n7402 , n7400 , n7401 );
buf ( n7403 , n5753 );
or ( n7404 , n7402 , n7403 );
buf ( n7405 , n5754 );
or ( n7406 , n7404 , n7405 );
buf ( n7407 , n5755 );
or ( n7408 , n7406 , n7407 );
buf ( n7409 , n5756 );
or ( n7410 , n7408 , n7409 );
buf ( n7411 , n5757 );
or ( n7412 , n7410 , n7411 );
buf ( n7413 , n5758 );
or ( n7414 , n7412 , n7413 );
buf ( n7415 , n5759 );
or ( n7416 , n7414 , n7415 );
buf ( n7417 , n5760 );
or ( n7418 , n7416 , n7417 );
buf ( n7419 , n5761 );
or ( n7420 , n7418 , n7419 );
buf ( n7421 , n5762 );
or ( n7422 , n7420 , n7421 );
buf ( n7423 , n5763 );
or ( n7424 , n7422 , n7423 );
buf ( n7425 , n5764 );
or ( n7426 , n7424 , n7425 );
buf ( n7427 , n5765 );
or ( n7428 , n7426 , n7427 );
buf ( n7429 , n5766 );
or ( n7430 , n7428 , n7429 );
buf ( n7431 , n5767 );
or ( n7432 , n7430 , n7431 );
buf ( n7433 , n5768 );
or ( n7434 , n7432 , n7433 );
buf ( n7435 , n5769 );
or ( n7436 , n7434 , n7435 );
buf ( n7437 , n5770 );
or ( n7438 , n7436 , n7437 );
buf ( n7439 , n5771 );
or ( n7440 , n7438 , n7439 );
buf ( n7441 , n5772 );
or ( n7442 , n7440 , n7441 );
buf ( n7443 , n5773 );
or ( n7444 , n7442 , n7443 );
buf ( n7445 , n5774 );
or ( n7446 , n7444 , n7445 );
buf ( n7447 , n5775 );
or ( n7448 , n7446 , n7447 );
buf ( n7449 , n5776 );
or ( n7450 , n7448 , n7449 );
buf ( n7451 , n5777 );
or ( n7452 , n7450 , n7451 );
buf ( n7453 , n5778 );
or ( n7454 , n7452 , n7453 );
buf ( n7455 , n5779 );
or ( n7456 , n7454 , n7455 );
buf ( n7457 , n5780 );
or ( n7458 , n7456 , n7457 );
buf ( n7459 , n5781 );
or ( n7460 , n7458 , n7459 );
buf ( n7461 , n5782 );
or ( n7462 , n7460 , n7461 );
buf ( n7463 , n5783 );
or ( n7464 , n7462 , n7463 );
buf ( n7465 , n5784 );
or ( n7466 , n7464 , n7465 );
buf ( n7467 , n5785 );
or ( n7468 , n7466 , n7467 );
buf ( n7469 , n5786 );
or ( n7470 , n7468 , n7469 );
buf ( n7471 , n5787 );
or ( n7472 , n7470 , n7471 );
buf ( n7473 , n5788 );
or ( n7474 , n7472 , n7473 );
buf ( n7475 , n5789 );
or ( n7476 , n7474 , n7475 );
buf ( n7477 , n5790 );
or ( n7478 , n7476 , n7477 );
buf ( n7479 , n5791 );
or ( n7480 , n7478 , n7479 );
buf ( n7481 , n5792 );
or ( n7482 , n7480 , n7481 );
buf ( n7483 , n5793 );
or ( n7484 , n7482 , n7483 );
buf ( n7485 , n5794 );
or ( n7486 , n7484 , n7485 );
buf ( n7487 , n5795 );
or ( n7488 , n7486 , n7487 );
buf ( n7489 , n5796 );
or ( n7490 , n7488 , n7489 );
buf ( n7491 , n5797 );
or ( n7492 , n7490 , n7491 );
buf ( n7493 , n5798 );
or ( n7494 , n7492 , n7493 );
buf ( n7495 , n5799 );
or ( n7496 , n7494 , n7495 );
buf ( n7497 , n5800 );
or ( n7498 , n7496 , n7497 );
buf ( n7499 , n5801 );
or ( n7500 , n7498 , n7499 );
buf ( n7501 , n5802 );
or ( n7502 , n7500 , n7501 );
buf ( n7503 , n5803 );
or ( n7504 , n7502 , n7503 );
buf ( n7505 , n5804 );
or ( n7506 , n7504 , n7505 );
buf ( n7507 , n5805 );
or ( n7508 , n7506 , n7507 );
buf ( n7509 , n5806 );
or ( n7510 , n7508 , n7509 );
buf ( n7511 , n5807 );
or ( n7512 , n7510 , n7511 );
buf ( n7513 , n5808 );
or ( n7514 , n7512 , n7513 );
buf ( n7515 , n5809 );
or ( n7516 , n7514 , n7515 );
buf ( n7517 , n5810 );
or ( n7518 , n7516 , n7517 );
buf ( n7519 , n5811 );
or ( n7520 , n7518 , n7519 );
buf ( n7521 , n5812 );
or ( n7522 , n7520 , n7521 );
buf ( n7523 , n5813 );
or ( n7524 , n7522 , n7523 );
buf ( n7525 , n5814 );
or ( n7526 , n7524 , n7525 );
buf ( n7527 , n5815 );
or ( n7528 , n7526 , n7527 );
buf ( n7529 , n5816 );
or ( n7530 , n7528 , n7529 );
buf ( n7531 , n5817 );
or ( n7532 , n7530 , n7531 );
buf ( n7533 , n5818 );
or ( n7534 , n7532 , n7533 );
buf ( n7535 , n5819 );
or ( n7536 , n7534 , n7535 );
buf ( n7537 , n5820 );
or ( n7538 , n7536 , n7537 );
buf ( n7539 , n5821 );
or ( n7540 , n7538 , n7539 );
buf ( n7541 , n5822 );
or ( n7542 , n7540 , n7541 );
buf ( n7543 , n5823 );
or ( n7544 , n7542 , n7543 );
buf ( n7545 , n5824 );
or ( n7546 , n7544 , n7545 );
buf ( n7547 , n5825 );
or ( n7548 , n7546 , n7547 );
buf ( n7549 , n5826 );
or ( n7550 , n7548 , n7549 );
buf ( n7551 , n5827 );
or ( n7552 , n7550 , n7551 );
buf ( n7553 , n5828 );
or ( n7554 , n7552 , n7553 );
buf ( n7555 , n5829 );
or ( n7556 , n7554 , n7555 );
buf ( n7557 , n5830 );
or ( n7558 , n7556 , n7557 );
buf ( n7559 , n5831 );
or ( n7560 , n7558 , n7559 );
buf ( n7561 , n5832 );
or ( n7562 , n7560 , n7561 );
buf ( n7563 , n5833 );
or ( n7564 , n7562 , n7563 );
buf ( n7565 , n5834 );
or ( n7566 , n7564 , n7565 );
buf ( n7567 , n5835 );
or ( n7568 , n7566 , n7567 );
buf ( n7569 , n5836 );
or ( n7570 , n7568 , n7569 );
buf ( n7571 , n5837 );
or ( n7572 , n7570 , n7571 );
buf ( n7573 , n5838 );
or ( n7574 , n7572 , n7573 );
buf ( n7575 , n5839 );
or ( n7576 , n7574 , n7575 );
buf ( n7577 , n5840 );
or ( n7578 , n7576 , n7577 );
buf ( n7579 , n5841 );
or ( n7580 , n7578 , n7579 );
buf ( n7581 , n5842 );
or ( n7582 , n7580 , n7581 );
buf ( n7583 , n5843 );
or ( n7584 , n7582 , n7583 );
buf ( n7585 , n5844 );
or ( n7586 , n7584 , n7585 );
buf ( n7587 , n5845 );
or ( n7588 , n7586 , n7587 );
buf ( n7589 , n5846 );
or ( n7590 , n7588 , n7589 );
buf ( n7591 , n5847 );
or ( n7592 , n7590 , n7591 );
buf ( n7593 , n5848 );
or ( n7594 , n7592 , n7593 );
buf ( n7595 , n5849 );
or ( n7596 , n7594 , n7595 );
buf ( n7597 , n5850 );
or ( n7598 , n7596 , n7597 );
buf ( n7599 , n5851 );
or ( n7600 , n7598 , n7599 );
buf ( n7601 , n5852 );
or ( n7602 , n7600 , n7601 );
buf ( n7603 , n5853 );
or ( n7604 , n7602 , n7603 );
buf ( n7605 , n5854 );
or ( n7606 , n7604 , n7605 );
buf ( n7607 , n5855 );
or ( n7608 , n7606 , n7607 );
buf ( n7609 , n5856 );
or ( n7610 , n7608 , n7609 );
buf ( n7611 , n5857 );
or ( n7612 , n7610 , n7611 );
buf ( n7613 , n5858 );
or ( n7614 , n7612 , n7613 );
buf ( n7615 , n5859 );
or ( n7616 , n7614 , n7615 );
buf ( n7617 , n5860 );
or ( n7618 , n7616 , n7617 );
buf ( n7619 , n5861 );
or ( n7620 , n7618 , n7619 );
buf ( n7621 , n5862 );
or ( n7622 , n7620 , n7621 );
buf ( n7623 , n5863 );
or ( n7624 , n7622 , n7623 );
buf ( n7625 , n5864 );
or ( n7626 , n7624 , n7625 );
buf ( n7627 , n5865 );
or ( n7628 , n7626 , n7627 );
buf ( n7629 , n5866 );
or ( n7630 , n7628 , n7629 );
buf ( n7631 , n5867 );
or ( n7632 , n7630 , n7631 );
buf ( n7633 , n5868 );
or ( n7634 , n7632 , n7633 );
buf ( n7635 , n5869 );
or ( n7636 , n7634 , n7635 );
buf ( n7637 , n5870 );
or ( n7638 , n7636 , n7637 );
buf ( n7639 , n5871 );
or ( n7640 , n7638 , n7639 );
buf ( n7641 , n5872 );
or ( n7642 , n7640 , n7641 );
buf ( n7643 , n5873 );
or ( n7644 , n7642 , n7643 );
buf ( n7645 , n5874 );
or ( n7646 , n7644 , n7645 );
buf ( n7647 , n5875 );
or ( n7648 , n7646 , n7647 );
buf ( n7649 , n5876 );
or ( n7650 , n7648 , n7649 );
buf ( n7651 , n5877 );
or ( n7652 , n7650 , n7651 );
buf ( n7653 , n5878 );
or ( n7654 , n7652 , n7653 );
buf ( n7655 , n5879 );
or ( n7656 , n7654 , n7655 );
buf ( n7657 , n5880 );
or ( n7658 , n7656 , n7657 );
buf ( n7659 , n5881 );
or ( n7660 , n7658 , n7659 );
buf ( n7661 , n5882 );
or ( n7662 , n7660 , n7661 );
buf ( n7663 , n5883 );
or ( n7664 , n7662 , n7663 );
buf ( n7665 , n5884 );
or ( n7666 , n7664 , n7665 );
buf ( n7667 , n5885 );
or ( n7668 , n7666 , n7667 );
buf ( n7669 , n5886 );
or ( n7670 , n7668 , n7669 );
buf ( n7671 , n5887 );
or ( n7672 , n7670 , n7671 );
buf ( n7673 , n5888 );
or ( n7674 , n7672 , n7673 );
buf ( n7675 , n5889 );
or ( n7676 , n7674 , n7675 );
buf ( n7677 , n5890 );
or ( n7678 , n7676 , n7677 );
buf ( n7679 , n5891 );
or ( n7680 , n7678 , n7679 );
buf ( n7681 , n5892 );
or ( n7682 , n7680 , n7681 );
buf ( n7683 , n5893 );
or ( n7684 , n7682 , n7683 );
buf ( n7685 , n5894 );
or ( n7686 , n7684 , n7685 );
buf ( n7687 , n5895 );
or ( n7688 , n7686 , n7687 );
buf ( n7689 , n5896 );
or ( n7690 , n7688 , n7689 );
buf ( n7691 , n5897 );
or ( n7692 , n7690 , n7691 );
buf ( n7693 , n5898 );
or ( n7694 , n7692 , n7693 );
buf ( n7695 , n5899 );
or ( n7696 , n7694 , n7695 );
buf ( n7697 , n5900 );
or ( n7698 , n7696 , n7697 );
buf ( n7699 , n5901 );
or ( n7700 , n7698 , n7699 );
buf ( n7701 , n5902 );
or ( n7702 , n7700 , n7701 );
buf ( n7703 , n5903 );
or ( n7704 , n7702 , n7703 );
buf ( n7705 , n5904 );
or ( n7706 , n7704 , n7705 );
buf ( n7707 , n5905 );
or ( n7708 , n7706 , n7707 );
buf ( n7709 , n5906 );
or ( n7710 , n7708 , n7709 );
buf ( n7711 , n5907 );
or ( n7712 , n7710 , n7711 );
buf ( n7713 , n5908 );
or ( n7714 , n7712 , n7713 );
buf ( n7715 , n5909 );
or ( n7716 , n7714 , n7715 );
buf ( n7717 , n5910 );
or ( n7718 , n7716 , n7717 );
buf ( n7719 , n5911 );
or ( n7720 , n7718 , n7719 );
buf ( n7721 , n5912 );
or ( n7722 , n7720 , n7721 );
buf ( n7723 , n5913 );
or ( n7724 , n7722 , n7723 );
buf ( n7725 , n5914 );
or ( n7726 , n7724 , n7725 );
buf ( n7727 , n5915 );
or ( n7728 , n7726 , n7727 );
buf ( n7729 , n5916 );
or ( n7730 , n7728 , n7729 );
buf ( n7731 , n5917 );
or ( n7732 , n7730 , n7731 );
buf ( n7733 , n5918 );
or ( n7734 , n7732 , n7733 );
buf ( n7735 , n5919 );
or ( n7736 , n7734 , n7735 );
buf ( n7737 , n5920 );
or ( n7738 , n7736 , n7737 );
buf ( n7739 , n5921 );
or ( n7740 , n7738 , n7739 );
buf ( n7741 , n5922 );
or ( n7742 , n7740 , n7741 );
buf ( n7743 , n5923 );
or ( n7744 , n7742 , n7743 );
buf ( n7745 , n5924 );
or ( n7746 , n7744 , n7745 );
buf ( n7747 , n5925 );
or ( n7748 , n7746 , n7747 );
buf ( n7749 , n5926 );
or ( n7750 , n7748 , n7749 );
buf ( n7751 , n5927 );
or ( n7752 , n7750 , n7751 );
buf ( n7753 , n5928 );
or ( n7754 , n7752 , n7753 );
buf ( n7755 , n5929 );
or ( n7756 , n7754 , n7755 );
buf ( n7757 , n5930 );
or ( n7758 , n7756 , n7757 );
buf ( n7759 , n5931 );
or ( n7760 , n7758 , n7759 );
buf ( n7761 , n5932 );
or ( n7762 , n7760 , n7761 );
buf ( n7763 , n5933 );
or ( n7764 , n7762 , n7763 );
buf ( n7765 , n5934 );
or ( n7766 , n7764 , n7765 );
buf ( n7767 , n5935 );
or ( n7768 , n7766 , n7767 );
buf ( n7769 , n5936 );
or ( n7770 , n7768 , n7769 );
buf ( n7771 , n5937 );
or ( n7772 , n7770 , n7771 );
buf ( n7773 , n5938 );
or ( n7774 , n7772 , n7773 );
buf ( n7775 , n5939 );
or ( n7776 , n7774 , n7775 );
buf ( n7777 , n5940 );
or ( n7778 , n7776 , n7777 );
buf ( n7779 , n5941 );
or ( n7780 , n7778 , n7779 );
buf ( n7781 , n5942 );
or ( n7782 , n7780 , n7781 );
buf ( n7783 , n5943 );
or ( n7784 , n7782 , n7783 );
buf ( n7785 , n5944 );
or ( n7786 , n7784 , n7785 );
buf ( n7787 , n5945 );
or ( n7788 , n7786 , n7787 );
buf ( n7789 , n5946 );
or ( n7790 , n7788 , n7789 );
buf ( n7791 , n5947 );
or ( n7792 , n7790 , n7791 );
buf ( n7793 , n5948 );
or ( n7794 , n7792 , n7793 );
buf ( n7795 , n5949 );
or ( n7796 , n7794 , n7795 );
buf ( n7797 , n5950 );
or ( n7798 , n7796 , n7797 );
buf ( n7799 , n5951 );
or ( n7800 , n7798 , n7799 );
buf ( n7801 , n5952 );
or ( n7802 , n7800 , n7801 );
buf ( n7803 , n5953 );
or ( n7804 , n7802 , n7803 );
buf ( n7805 , n5954 );
or ( n7806 , n7804 , n7805 );
buf ( n7807 , n5955 );
or ( n7808 , n7806 , n7807 );
buf ( n7809 , n5956 );
or ( n7810 , n7808 , n7809 );
buf ( n7811 , n5957 );
or ( n7812 , n7810 , n7811 );
buf ( n7813 , n5958 );
or ( n7814 , n7812 , n7813 );
buf ( n7815 , n5959 );
or ( n7816 , n7814 , n7815 );
buf ( n7817 , n5960 );
or ( n7818 , n7816 , n7817 );
buf ( n7819 , n5961 );
or ( n7820 , n7818 , n7819 );
buf ( n7821 , n5962 );
or ( n7822 , n7820 , n7821 );
buf ( n7823 , n5963 );
or ( n7824 , n7822 , n7823 );
buf ( n7825 , n5964 );
or ( n7826 , n7824 , n7825 );
buf ( n7827 , n5965 );
or ( n7828 , n7826 , n7827 );
buf ( n7829 , n5966 );
or ( n7830 , n7828 , n7829 );
buf ( n7831 , n5967 );
or ( n7832 , n7830 , n7831 );
buf ( n7833 , n5968 );
or ( n7834 , n7832 , n7833 );
buf ( n7835 , n5969 );
or ( n7836 , n7834 , n7835 );
buf ( n7837 , n5970 );
or ( n7838 , n7836 , n7837 );
buf ( n7839 , n5971 );
or ( n7840 , n7838 , n7839 );
buf ( n7841 , n5972 );
or ( n7842 , n7840 , n7841 );
buf ( n7843 , n5973 );
or ( n7844 , n7842 , n7843 );
buf ( n7845 , n5974 );
or ( n7846 , n7844 , n7845 );
buf ( n7847 , n5975 );
or ( n7848 , n7846 , n7847 );
buf ( n7849 , n5976 );
or ( n7850 , n7848 , n7849 );
buf ( n7851 , n5977 );
or ( n7852 , n7850 , n7851 );
buf ( n7853 , n5978 );
or ( n7854 , n7852 , n7853 );
buf ( n7855 , n5979 );
or ( n7856 , n7854 , n7855 );
buf ( n7857 , n5980 );
or ( n7858 , n7856 , n7857 );
buf ( n7859 , n5981 );
or ( n7860 , n7858 , n7859 );
buf ( n7861 , n5982 );
or ( n7862 , n7860 , n7861 );
buf ( n7863 , n5983 );
or ( n7864 , n7862 , n7863 );
buf ( n7865 , n5984 );
or ( n7866 , n7864 , n7865 );
buf ( n7867 , n5985 );
or ( n7868 , n7866 , n7867 );
buf ( n7869 , n5986 );
or ( n7870 , n7868 , n7869 );
buf ( n7871 , n5987 );
or ( n7872 , n7870 , n7871 );
buf ( n7873 , n5988 );
or ( n7874 , n7872 , n7873 );
buf ( n7875 , n5989 );
or ( n7876 , n7874 , n7875 );
buf ( n7877 , n5990 );
or ( n7878 , n7876 , n7877 );
buf ( n7879 , n5991 );
or ( n7880 , n7878 , n7879 );
buf ( n7881 , n5992 );
or ( n7882 , n7880 , n7881 );
buf ( n7883 , n5993 );
or ( n7884 , n7882 , n7883 );
buf ( n7885 , n5994 );
or ( n7886 , n7884 , n7885 );
buf ( n7887 , n5995 );
or ( n7888 , n7886 , n7887 );
buf ( n7889 , n5996 );
or ( n7890 , n7888 , n7889 );
buf ( n7891 , n5997 );
or ( n7892 , n7890 , n7891 );
buf ( n7893 , n5998 );
or ( n7894 , n7892 , n7893 );
buf ( n7895 , n5999 );
or ( n7896 , n7894 , n7895 );
buf ( n7897 , n6000 );
or ( n7898 , n7896 , n7897 );
buf ( n7899 , n6001 );
or ( n7900 , n7898 , n7899 );
buf ( n7901 , n6002 );
or ( n7902 , n7900 , n7901 );
buf ( n7903 , n6003 );
or ( n7904 , n7902 , n7903 );
buf ( n7905 , n6004 );
or ( n7906 , n7904 , n7905 );
buf ( n7907 , n6005 );
or ( n7908 , n7906 , n7907 );
buf ( n7909 , n6006 );
or ( n7910 , n7908 , n7909 );
buf ( n7911 , n6007 );
or ( n7912 , n7910 , n7911 );
buf ( n7913 , n6008 );
or ( n7914 , n7912 , n7913 );
buf ( n7915 , n6009 );
or ( n7916 , n7914 , n7915 );
buf ( n7917 , n6010 );
or ( n7918 , n7916 , n7917 );
buf ( n7919 , n6011 );
or ( n7920 , n7918 , n7919 );
buf ( n7921 , n6012 );
or ( n7922 , n7920 , n7921 );
buf ( n7923 , n6013 );
or ( n7924 , n7922 , n7923 );
buf ( n7925 , n6014 );
or ( n7926 , n7924 , n7925 );
buf ( n7927 , n6015 );
or ( n7928 , n7926 , n7927 );
buf ( n7929 , n6016 );
or ( n7930 , n7928 , n7929 );
buf ( n7931 , n6017 );
or ( n7932 , n7930 , n7931 );
buf ( n7933 , n6018 );
or ( n7934 , n7932 , n7933 );
buf ( n7935 , n6019 );
or ( n7936 , n7934 , n7935 );
buf ( n7937 , n6020 );
or ( n7938 , n7936 , n7937 );
buf ( n7939 , n6021 );
or ( n7940 , n7938 , n7939 );
buf ( n7941 , n6022 );
or ( n7942 , n7940 , n7941 );
buf ( n7943 , n6023 );
or ( n7944 , n7942 , n7943 );
buf ( n7945 , n6024 );
or ( n7946 , n7944 , n7945 );
buf ( n7947 , n6025 );
or ( n7948 , n7946 , n7947 );
buf ( n7949 , n6026 );
or ( n7950 , n7948 , n7949 );
buf ( n7951 , n6027 );
or ( n7952 , n7950 , n7951 );
buf ( n7953 , n6028 );
or ( n7954 , n7952 , n7953 );
buf ( n7955 , n6029 );
or ( n7956 , n7954 , n7955 );
buf ( n7957 , n6030 );
or ( n7958 , n7956 , n7957 );
buf ( n7959 , n6031 );
or ( n7960 , n7958 , n7959 );
buf ( n7961 , n6032 );
or ( n7962 , n7960 , n7961 );
buf ( n7963 , n6033 );
or ( n7964 , n7962 , n7963 );
buf ( n7965 , n6034 );
or ( n7966 , n7964 , n7965 );
buf ( n7967 , n6035 );
or ( n7968 , n7966 , n7967 );
buf ( n7969 , n6036 );
or ( n7970 , n7968 , n7969 );
buf ( n7971 , n6037 );
or ( n7972 , n7970 , n7971 );
buf ( n7973 , n6038 );
or ( n7974 , n7972 , n7973 );
buf ( n7975 , n6039 );
or ( n7976 , n7974 , n7975 );
buf ( n7977 , n6040 );
or ( n7978 , n7976 , n7977 );
buf ( n7979 , n6041 );
or ( n7980 , n7978 , n7979 );
buf ( n7981 , n6042 );
or ( n7982 , n7980 , n7981 );
buf ( n7983 , n6043 );
or ( n7984 , n7982 , n7983 );
buf ( n7985 , n6044 );
or ( n7986 , n7984 , n7985 );
buf ( n7987 , n6045 );
or ( n7988 , n7986 , n7987 );
buf ( n7989 , n6046 );
or ( n7990 , n7988 , n7989 );
buf ( n7991 , n6047 );
or ( n7992 , n7990 , n7991 );
buf ( n7993 , n6048 );
or ( n7994 , n7992 , n7993 );
buf ( n7995 , n6049 );
or ( n7996 , n7994 , n7995 );
buf ( n7997 , n6050 );
or ( n7998 , n7996 , n7997 );
buf ( n7999 , n6051 );
or ( n8000 , n7998 , n7999 );
buf ( n8001 , n6052 );
or ( n8002 , n8000 , n8001 );
buf ( n8003 , n6053 );
or ( n8004 , n8002 , n8003 );
buf ( n8005 , n6054 );
or ( n8006 , n8004 , n8005 );
buf ( n8007 , n6055 );
or ( n8008 , n8006 , n8007 );
buf ( n8009 , n6056 );
or ( n8010 , n8008 , n8009 );
buf ( n8011 , n6057 );
or ( n8012 , n8010 , n8011 );
buf ( n8013 , n6058 );
or ( n8014 , n8012 , n8013 );
buf ( n8015 , n6059 );
or ( n8016 , n8014 , n8015 );
buf ( n8017 , n6060 );
or ( n8018 , n8016 , n8017 );
buf ( n8019 , n6061 );
or ( n8020 , n8018 , n8019 );
buf ( n8021 , n6062 );
or ( n8022 , n8020 , n8021 );
buf ( n8023 , n6063 );
or ( n8024 , n8022 , n8023 );
buf ( n8025 , n6064 );
or ( n8026 , n8024 , n8025 );
buf ( n8027 , n6065 );
or ( n8028 , n8026 , n8027 );
buf ( n8029 , n6066 );
or ( n8030 , n8028 , n8029 );
buf ( n8031 , n6067 );
or ( n8032 , n8030 , n8031 );
buf ( n8033 , n6068 );
or ( n8034 , n8032 , n8033 );
buf ( n8035 , n6069 );
or ( n8036 , n8034 , n8035 );
buf ( n8037 , n6070 );
or ( n8038 , n8036 , n8037 );
buf ( n8039 , n6071 );
or ( n8040 , n8038 , n8039 );
buf ( n8041 , n6072 );
or ( n8042 , n8040 , n8041 );
buf ( n8043 , n6073 );
or ( n8044 , n8042 , n8043 );
buf ( n8045 , n6074 );
or ( n8046 , n8044 , n8045 );
buf ( n8047 , n6075 );
or ( n8048 , n8046 , n8047 );
buf ( n8049 , n6076 );
or ( n8050 , n8048 , n8049 );
buf ( n8051 , n6077 );
or ( n8052 , n8050 , n8051 );
buf ( n8053 , n6078 );
or ( n8054 , n8052 , n8053 );
buf ( n8055 , n6079 );
or ( n8056 , n8054 , n8055 );
buf ( n8057 , n6080 );
or ( n8058 , n8056 , n8057 );
buf ( n8059 , n6081 );
or ( n8060 , n8058 , n8059 );
buf ( n8061 , n6082 );
or ( n8062 , n8060 , n8061 );
buf ( n8063 , n6083 );
or ( n8064 , n8062 , n8063 );
buf ( n8065 , n6084 );
or ( n8066 , n8064 , n8065 );
buf ( n8067 , n6085 );
or ( n8068 , n8066 , n8067 );
buf ( n8069 , n6086 );
or ( n8070 , n8068 , n8069 );
buf ( n8071 , n6087 );
or ( n8072 , n8070 , n8071 );
buf ( n8073 , n6088 );
or ( n8074 , n8072 , n8073 );
buf ( n8075 , n6089 );
or ( n8076 , n8074 , n8075 );
buf ( n8077 , n6090 );
or ( n8078 , n8076 , n8077 );
buf ( n8079 , n6091 );
or ( n8080 , n8078 , n8079 );
buf ( n8081 , n6092 );
or ( n8082 , n8080 , n8081 );
buf ( n8083 , n6093 );
or ( n8084 , n8082 , n8083 );
buf ( n8085 , n6094 );
or ( n8086 , n8084 , n8085 );
buf ( n8087 , n6095 );
or ( n8088 , n8086 , n8087 );
buf ( n8089 , n6096 );
or ( n8090 , n8088 , n8089 );
buf ( n8091 , n6097 );
or ( n8092 , n8090 , n8091 );
buf ( n8093 , n6098 );
or ( n8094 , n8092 , n8093 );
buf ( n8095 , n6099 );
or ( n8096 , n8094 , n8095 );
buf ( n8097 , n6100 );
or ( n8098 , n8096 , n8097 );
buf ( n8099 , n6101 );
or ( n8100 , n8098 , n8099 );
buf ( n8101 , n6102 );
or ( n8102 , n8100 , n8101 );
buf ( n8103 , n6103 );
or ( n8104 , n8102 , n8103 );
buf ( n8105 , n6104 );
or ( n8106 , n8104 , n8105 );
buf ( n8107 , n6105 );
or ( n8108 , n8106 , n8107 );
buf ( n8109 , n6106 );
or ( n8110 , n8108 , n8109 );
buf ( n8111 , n6107 );
or ( n8112 , n8110 , n8111 );
buf ( n8113 , n6108 );
or ( n8114 , n8112 , n8113 );
buf ( n8115 , n6109 );
or ( n8116 , n8114 , n8115 );
buf ( n8117 , n6110 );
or ( n8118 , n8116 , n8117 );
buf ( n8119 , n6111 );
or ( n8120 , n8118 , n8119 );
buf ( n8121 , n6112 );
or ( n8122 , n8120 , n8121 );
buf ( n8123 , n6113 );
or ( n8124 , n8122 , n8123 );
buf ( n8125 , n6114 );
or ( n8126 , n8124 , n8125 );
buf ( n8127 , n6115 );
or ( n8128 , n8126 , n8127 );
buf ( n8129 , n5092 );
buf ( n8130 , n6116 );
xor ( n8131 , n8129 , n8130 );
or ( n8132 , n8128 , n8131 );
buf ( n8133 , n6117 );
or ( n8134 , n8132 , n8133 );
buf ( n8135 , n5094 );
buf ( n8136 , n6118 );
xor ( n8137 , n8135 , n8136 );
or ( n8138 , n8134 , n8137 );
buf ( n8139 , n6119 );
or ( n8140 , n8138 , n8139 );
buf ( n8141 , n6120 );
or ( n8142 , n8140 , n8141 );
buf ( n8143 , n5097 );
buf ( n8144 , n6121 );
xor ( n8145 , n8143 , n8144 );
or ( n8146 , n8142 , n8145 );
buf ( n8147 , n6122 );
or ( n8148 , n8146 , n8147 );
buf ( n8149 , n5099 );
buf ( n8150 , n6123 );
xor ( n8151 , n8149 , n8150 );
or ( n8152 , n8148 , n8151 );
buf ( n8153 , n5100 );
buf ( n8154 , n6124 );
xor ( n8155 , n8153 , n8154 );
or ( n8156 , n8152 , n8155 );
buf ( n8157 , n6125 );
or ( n8158 , n8156 , n8157 );
buf ( n8159 , n6126 );
or ( n8160 , n8158 , n8159 );
buf ( n8161 , n5103 );
buf ( n8162 , n6127 );
xor ( n8163 , n8161 , n8162 );
or ( n8164 , n8160 , n8163 );
buf ( n8165 , n6128 );
or ( n8166 , n8164 , n8165 );
buf ( n8167 , n6129 );
or ( n8168 , n8166 , n8167 );
buf ( n8169 , n6130 );
or ( n8170 , n8168 , n8169 );
buf ( n8171 , n5107 );
buf ( n8172 , n6131 );
xor ( n8173 , n8171 , n8172 );
or ( n8174 , n8170 , n8173 );
buf ( n8175 , n6132 );
or ( n8176 , n8174 , n8175 );
buf ( n8177 , n6133 );
or ( n8178 , n8176 , n8177 );
buf ( n8179 , n6134 );
or ( n8180 , n8178 , n8179 );
buf ( n8181 , n5111 );
buf ( n8182 , n6135 );
xor ( n8183 , n8181 , n8182 );
or ( n8184 , n8180 , n8183 );
buf ( n8185 , n5112 );
buf ( n8186 , n6136 );
xor ( n8187 , n8185 , n8186 );
or ( n8188 , n8184 , n8187 );
buf ( n8189 , n6137 );
or ( n8190 , n8188 , n8189 );
buf ( n8191 , n5114 );
buf ( n8192 , n6138 );
xor ( n8193 , n8191 , n8192 );
or ( n8194 , n8190 , n8193 );
buf ( n8195 , n6139 );
or ( n8196 , n8194 , n8195 );
buf ( n8197 , n6140 );
or ( n8198 , n8196 , n8197 );
buf ( n8199 , n6141 );
or ( n8200 , n8198 , n8199 );
buf ( n8201 , n5118 );
buf ( n8202 , n6142 );
xor ( n8203 , n8201 , n8202 );
or ( n8204 , n8200 , n8203 );
buf ( n8205 , n5119 );
buf ( n8206 , n6143 );
xor ( n8207 , n8205 , n8206 );
or ( n8208 , n8204 , n8207 );
buf ( n8209 , n6144 );
or ( n8210 , n8208 , n8209 );
buf ( n8211 , n5121 );
buf ( n8212 , n6145 );
xor ( n8213 , n8211 , n8212 );
or ( n8214 , n8210 , n8213 );
buf ( n8215 , n5122 );
buf ( n8216 , n6146 );
xor ( n8217 , n8215 , n8216 );
or ( n8218 , n8214 , n8217 );
buf ( n8219 , n6147 );
or ( n8220 , n8218 , n8219 );
buf ( n8221 , n5124 );
buf ( n8222 , n6148 );
xor ( n8223 , n8221 , n8222 );
or ( n8224 , n8220 , n8223 );
buf ( n8225 , n5125 );
buf ( n8226 , n6149 );
xor ( n8227 , n8225 , n8226 );
or ( n8228 , n8224 , n8227 );
buf ( n8229 , n8228 );
buf ( n8230 , n8229 );
buf ( n8231 , n4102 );
buf ( n8232 , n5126 );
xor ( n8233 , n8231 , n8232 );
buf ( n8234 , n4103 );
buf ( n8235 , n5127 );
xor ( n8236 , n8234 , n8235 );
or ( n8237 , n8233 , n8236 );
buf ( n8238 , n4104 );
buf ( n8239 , n5128 );
xor ( n8240 , n8238 , n8239 );
or ( n8241 , n8237 , n8240 );
buf ( n8242 , n4105 );
buf ( n8243 , n5129 );
xor ( n8244 , n8242 , n8243 );
or ( n8245 , n8241 , n8244 );
buf ( n8246 , n4106 );
buf ( n8247 , n5130 );
xor ( n8248 , n8246 , n8247 );
or ( n8249 , n8245 , n8248 );
buf ( n8250 , n4107 );
buf ( n8251 , n5131 );
xor ( n8252 , n8250 , n8251 );
or ( n8253 , n8249 , n8252 );
buf ( n8254 , n4108 );
buf ( n8255 , n5132 );
xor ( n8256 , n8254 , n8255 );
or ( n8257 , n8253 , n8256 );
buf ( n8258 , n4109 );
buf ( n8259 , n5133 );
xor ( n8260 , n8258 , n8259 );
or ( n8261 , n8257 , n8260 );
buf ( n8262 , n4110 );
buf ( n8263 , n5134 );
xor ( n8264 , n8262 , n8263 );
or ( n8265 , n8261 , n8264 );
buf ( n8266 , n4111 );
buf ( n8267 , n5135 );
xor ( n8268 , n8266 , n8267 );
or ( n8269 , n8265 , n8268 );
buf ( n8270 , n4112 );
buf ( n8271 , n5136 );
xor ( n8272 , n8270 , n8271 );
or ( n8273 , n8269 , n8272 );
buf ( n8274 , n4113 );
buf ( n8275 , n5137 );
xor ( n8276 , n8274 , n8275 );
or ( n8277 , n8273 , n8276 );
buf ( n8278 , n4114 );
buf ( n8279 , n5138 );
xor ( n8280 , n8278 , n8279 );
or ( n8281 , n8277 , n8280 );
buf ( n8282 , n4115 );
buf ( n8283 , n5139 );
xor ( n8284 , n8282 , n8283 );
or ( n8285 , n8281 , n8284 );
buf ( n8286 , n4116 );
buf ( n8287 , n5140 );
xor ( n8288 , n8286 , n8287 );
or ( n8289 , n8285 , n8288 );
buf ( n8290 , n4117 );
buf ( n8291 , n5141 );
xor ( n8292 , n8290 , n8291 );
or ( n8293 , n8289 , n8292 );
buf ( n8294 , n4118 );
buf ( n8295 , n5142 );
xor ( n8296 , n8294 , n8295 );
or ( n8297 , n8293 , n8296 );
buf ( n8298 , n4119 );
buf ( n8299 , n5143 );
xor ( n8300 , n8298 , n8299 );
or ( n8301 , n8297 , n8300 );
buf ( n8302 , n4120 );
buf ( n8303 , n5144 );
xor ( n8304 , n8302 , n8303 );
or ( n8305 , n8301 , n8304 );
buf ( n8306 , n4121 );
buf ( n8307 , n5145 );
xor ( n8308 , n8306 , n8307 );
or ( n8309 , n8305 , n8308 );
buf ( n8310 , n4122 );
buf ( n8311 , n5146 );
xor ( n8312 , n8310 , n8311 );
or ( n8313 , n8309 , n8312 );
buf ( n8314 , n4123 );
buf ( n8315 , n5147 );
xor ( n8316 , n8314 , n8315 );
or ( n8317 , n8313 , n8316 );
buf ( n8318 , n4124 );
buf ( n8319 , n5148 );
xor ( n8320 , n8318 , n8319 );
or ( n8321 , n8317 , n8320 );
buf ( n8322 , n4125 );
buf ( n8323 , n5149 );
xor ( n8324 , n8322 , n8323 );
or ( n8325 , n8321 , n8324 );
buf ( n8326 , n4126 );
buf ( n8327 , n5150 );
xor ( n8328 , n8326 , n8327 );
or ( n8329 , n8325 , n8328 );
buf ( n8330 , n4127 );
buf ( n8331 , n5151 );
xor ( n8332 , n8330 , n8331 );
or ( n8333 , n8329 , n8332 );
buf ( n8334 , n4128 );
buf ( n8335 , n5152 );
xor ( n8336 , n8334 , n8335 );
or ( n8337 , n8333 , n8336 );
buf ( n8338 , n4129 );
buf ( n8339 , n5153 );
xor ( n8340 , n8338 , n8339 );
or ( n8341 , n8337 , n8340 );
buf ( n8342 , n4130 );
buf ( n8343 , n5154 );
xor ( n8344 , n8342 , n8343 );
or ( n8345 , n8341 , n8344 );
buf ( n8346 , n4131 );
buf ( n8347 , n5155 );
xor ( n8348 , n8346 , n8347 );
or ( n8349 , n8345 , n8348 );
buf ( n8350 , n4132 );
buf ( n8351 , n5156 );
xor ( n8352 , n8350 , n8351 );
or ( n8353 , n8349 , n8352 );
buf ( n8354 , n4133 );
buf ( n8355 , n5157 );
xor ( n8356 , n8354 , n8355 );
or ( n8357 , n8353 , n8356 );
buf ( n8358 , n4134 );
buf ( n8359 , n5158 );
xor ( n8360 , n8358 , n8359 );
or ( n8361 , n8357 , n8360 );
buf ( n8362 , n4135 );
buf ( n8363 , n5159 );
xor ( n8364 , n8362 , n8363 );
or ( n8365 , n8361 , n8364 );
buf ( n8366 , n4136 );
buf ( n8367 , n5160 );
xor ( n8368 , n8366 , n8367 );
or ( n8369 , n8365 , n8368 );
buf ( n8370 , n4137 );
buf ( n8371 , n5161 );
xor ( n8372 , n8370 , n8371 );
or ( n8373 , n8369 , n8372 );
buf ( n8374 , n4138 );
buf ( n8375 , n5162 );
xor ( n8376 , n8374 , n8375 );
or ( n8377 , n8373 , n8376 );
buf ( n8378 , n4139 );
buf ( n8379 , n5163 );
xor ( n8380 , n8378 , n8379 );
or ( n8381 , n8377 , n8380 );
buf ( n8382 , n4140 );
buf ( n8383 , n5164 );
xor ( n8384 , n8382 , n8383 );
or ( n8385 , n8381 , n8384 );
buf ( n8386 , n4141 );
buf ( n8387 , n5165 );
xor ( n8388 , n8386 , n8387 );
or ( n8389 , n8385 , n8388 );
buf ( n8390 , n4142 );
buf ( n8391 , n5166 );
xor ( n8392 , n8390 , n8391 );
or ( n8393 , n8389 , n8392 );
buf ( n8394 , n4143 );
buf ( n8395 , n5167 );
xor ( n8396 , n8394 , n8395 );
or ( n8397 , n8393 , n8396 );
buf ( n8398 , n4144 );
buf ( n8399 , n5168 );
xor ( n8400 , n8398 , n8399 );
or ( n8401 , n8397 , n8400 );
buf ( n8402 , n4145 );
buf ( n8403 , n5169 );
xor ( n8404 , n8402 , n8403 );
or ( n8405 , n8401 , n8404 );
buf ( n8406 , n4146 );
buf ( n8407 , n5170 );
xor ( n8408 , n8406 , n8407 );
or ( n8409 , n8405 , n8408 );
buf ( n8410 , n4147 );
buf ( n8411 , n5171 );
xor ( n8412 , n8410 , n8411 );
or ( n8413 , n8409 , n8412 );
buf ( n8414 , n4148 );
buf ( n8415 , n5172 );
xor ( n8416 , n8414 , n8415 );
or ( n8417 , n8413 , n8416 );
buf ( n8418 , n4149 );
buf ( n8419 , n5173 );
xor ( n8420 , n8418 , n8419 );
or ( n8421 , n8417 , n8420 );
buf ( n8422 , n4150 );
buf ( n8423 , n5174 );
xor ( n8424 , n8422 , n8423 );
or ( n8425 , n8421 , n8424 );
buf ( n8426 , n4151 );
buf ( n8427 , n5175 );
xor ( n8428 , n8426 , n8427 );
or ( n8429 , n8425 , n8428 );
buf ( n8430 , n4152 );
buf ( n8431 , n5176 );
xor ( n8432 , n8430 , n8431 );
or ( n8433 , n8429 , n8432 );
buf ( n8434 , n4153 );
buf ( n8435 , n5177 );
xor ( n8436 , n8434 , n8435 );
or ( n8437 , n8433 , n8436 );
buf ( n8438 , n4154 );
buf ( n8439 , n5178 );
xor ( n8440 , n8438 , n8439 );
or ( n8441 , n8437 , n8440 );
buf ( n8442 , n4155 );
buf ( n8443 , n5179 );
xor ( n8444 , n8442 , n8443 );
or ( n8445 , n8441 , n8444 );
buf ( n8446 , n4156 );
buf ( n8447 , n5180 );
xor ( n8448 , n8446 , n8447 );
or ( n8449 , n8445 , n8448 );
buf ( n8450 , n4157 );
buf ( n8451 , n5181 );
xor ( n8452 , n8450 , n8451 );
or ( n8453 , n8449 , n8452 );
buf ( n8454 , n4158 );
buf ( n8455 , n5182 );
xor ( n8456 , n8454 , n8455 );
or ( n8457 , n8453 , n8456 );
buf ( n8458 , n4159 );
buf ( n8459 , n5183 );
xor ( n8460 , n8458 , n8459 );
or ( n8461 , n8457 , n8460 );
buf ( n8462 , n4160 );
buf ( n8463 , n5184 );
xor ( n8464 , n8462 , n8463 );
or ( n8465 , n8461 , n8464 );
buf ( n8466 , n4161 );
buf ( n8467 , n5185 );
xor ( n8468 , n8466 , n8467 );
or ( n8469 , n8465 , n8468 );
buf ( n8470 , n4162 );
buf ( n8471 , n5186 );
xor ( n8472 , n8470 , n8471 );
or ( n8473 , n8469 , n8472 );
buf ( n8474 , n4163 );
buf ( n8475 , n5187 );
xor ( n8476 , n8474 , n8475 );
or ( n8477 , n8473 , n8476 );
buf ( n8478 , n4164 );
buf ( n8479 , n5188 );
xor ( n8480 , n8478 , n8479 );
or ( n8481 , n8477 , n8480 );
buf ( n8482 , n4165 );
buf ( n8483 , n5189 );
xor ( n8484 , n8482 , n8483 );
or ( n8485 , n8481 , n8484 );
buf ( n8486 , n4166 );
buf ( n8487 , n5190 );
xor ( n8488 , n8486 , n8487 );
or ( n8489 , n8485 , n8488 );
buf ( n8490 , n4167 );
buf ( n8491 , n5191 );
xor ( n8492 , n8490 , n8491 );
or ( n8493 , n8489 , n8492 );
buf ( n8494 , n4168 );
buf ( n8495 , n5192 );
xor ( n8496 , n8494 , n8495 );
or ( n8497 , n8493 , n8496 );
buf ( n8498 , n4169 );
buf ( n8499 , n5193 );
xor ( n8500 , n8498 , n8499 );
or ( n8501 , n8497 , n8500 );
buf ( n8502 , n4170 );
buf ( n8503 , n5194 );
xor ( n8504 , n8502 , n8503 );
or ( n8505 , n8501 , n8504 );
buf ( n8506 , n4171 );
buf ( n8507 , n5195 );
xor ( n8508 , n8506 , n8507 );
or ( n8509 , n8505 , n8508 );
buf ( n8510 , n4172 );
buf ( n8511 , n5196 );
xor ( n8512 , n8510 , n8511 );
or ( n8513 , n8509 , n8512 );
buf ( n8514 , n4173 );
buf ( n8515 , n5197 );
xor ( n8516 , n8514 , n8515 );
or ( n8517 , n8513 , n8516 );
buf ( n8518 , n4174 );
buf ( n8519 , n5198 );
xor ( n8520 , n8518 , n8519 );
or ( n8521 , n8517 , n8520 );
buf ( n8522 , n4175 );
buf ( n8523 , n5199 );
xor ( n8524 , n8522 , n8523 );
or ( n8525 , n8521 , n8524 );
buf ( n8526 , n4176 );
buf ( n8527 , n5200 );
xor ( n8528 , n8526 , n8527 );
or ( n8529 , n8525 , n8528 );
buf ( n8530 , n4177 );
buf ( n8531 , n5201 );
xor ( n8532 , n8530 , n8531 );
or ( n8533 , n8529 , n8532 );
buf ( n8534 , n4178 );
buf ( n8535 , n5202 );
xor ( n8536 , n8534 , n8535 );
or ( n8537 , n8533 , n8536 );
buf ( n8538 , n4179 );
buf ( n8539 , n5203 );
xor ( n8540 , n8538 , n8539 );
or ( n8541 , n8537 , n8540 );
buf ( n8542 , n4180 );
buf ( n8543 , n5204 );
xor ( n8544 , n8542 , n8543 );
or ( n8545 , n8541 , n8544 );
buf ( n8546 , n4181 );
buf ( n8547 , n5205 );
xor ( n8548 , n8546 , n8547 );
or ( n8549 , n8545 , n8548 );
buf ( n8550 , n4182 );
buf ( n8551 , n5206 );
xor ( n8552 , n8550 , n8551 );
or ( n8553 , n8549 , n8552 );
buf ( n8554 , n4183 );
buf ( n8555 , n5207 );
xor ( n8556 , n8554 , n8555 );
or ( n8557 , n8553 , n8556 );
buf ( n8558 , n4184 );
buf ( n8559 , n5208 );
xor ( n8560 , n8558 , n8559 );
or ( n8561 , n8557 , n8560 );
buf ( n8562 , n4185 );
buf ( n8563 , n5209 );
xor ( n8564 , n8562 , n8563 );
or ( n8565 , n8561 , n8564 );
buf ( n8566 , n4186 );
buf ( n8567 , n5210 );
xor ( n8568 , n8566 , n8567 );
or ( n8569 , n8565 , n8568 );
buf ( n8570 , n4187 );
buf ( n8571 , n5211 );
xor ( n8572 , n8570 , n8571 );
or ( n8573 , n8569 , n8572 );
buf ( n8574 , n4188 );
buf ( n8575 , n5212 );
xor ( n8576 , n8574 , n8575 );
or ( n8577 , n8573 , n8576 );
buf ( n8578 , n4189 );
buf ( n8579 , n5213 );
xor ( n8580 , n8578 , n8579 );
or ( n8581 , n8577 , n8580 );
buf ( n8582 , n4190 );
buf ( n8583 , n5214 );
xor ( n8584 , n8582 , n8583 );
or ( n8585 , n8581 , n8584 );
buf ( n8586 , n4191 );
buf ( n8587 , n5215 );
xor ( n8588 , n8586 , n8587 );
or ( n8589 , n8585 , n8588 );
buf ( n8590 , n4192 );
buf ( n8591 , n5216 );
xor ( n8592 , n8590 , n8591 );
or ( n8593 , n8589 , n8592 );
buf ( n8594 , n4193 );
buf ( n8595 , n5217 );
xor ( n8596 , n8594 , n8595 );
or ( n8597 , n8593 , n8596 );
buf ( n8598 , n4194 );
buf ( n8599 , n5218 );
xor ( n8600 , n8598 , n8599 );
or ( n8601 , n8597 , n8600 );
buf ( n8602 , n4195 );
buf ( n8603 , n5219 );
xor ( n8604 , n8602 , n8603 );
or ( n8605 , n8601 , n8604 );
buf ( n8606 , n4196 );
buf ( n8607 , n5220 );
xor ( n8608 , n8606 , n8607 );
or ( n8609 , n8605 , n8608 );
buf ( n8610 , n4197 );
buf ( n8611 , n5221 );
xor ( n8612 , n8610 , n8611 );
or ( n8613 , n8609 , n8612 );
buf ( n8614 , n4198 );
buf ( n8615 , n5222 );
xor ( n8616 , n8614 , n8615 );
or ( n8617 , n8613 , n8616 );
buf ( n8618 , n4199 );
buf ( n8619 , n5223 );
xor ( n8620 , n8618 , n8619 );
or ( n8621 , n8617 , n8620 );
buf ( n8622 , n4200 );
buf ( n8623 , n5224 );
xor ( n8624 , n8622 , n8623 );
or ( n8625 , n8621 , n8624 );
buf ( n8626 , n4201 );
buf ( n8627 , n5225 );
xor ( n8628 , n8626 , n8627 );
or ( n8629 , n8625 , n8628 );
buf ( n8630 , n4202 );
buf ( n8631 , n5226 );
xor ( n8632 , n8630 , n8631 );
or ( n8633 , n8629 , n8632 );
buf ( n8634 , n4203 );
buf ( n8635 , n5227 );
xor ( n8636 , n8634 , n8635 );
or ( n8637 , n8633 , n8636 );
buf ( n8638 , n4204 );
buf ( n8639 , n5228 );
xor ( n8640 , n8638 , n8639 );
or ( n8641 , n8637 , n8640 );
buf ( n8642 , n4205 );
buf ( n8643 , n5229 );
xor ( n8644 , n8642 , n8643 );
or ( n8645 , n8641 , n8644 );
buf ( n8646 , n4206 );
buf ( n8647 , n5230 );
xor ( n8648 , n8646 , n8647 );
or ( n8649 , n8645 , n8648 );
buf ( n8650 , n4207 );
buf ( n8651 , n5231 );
xor ( n8652 , n8650 , n8651 );
or ( n8653 , n8649 , n8652 );
buf ( n8654 , n4208 );
buf ( n8655 , n5232 );
xor ( n8656 , n8654 , n8655 );
or ( n8657 , n8653 , n8656 );
buf ( n8658 , n4209 );
buf ( n8659 , n5233 );
xor ( n8660 , n8658 , n8659 );
or ( n8661 , n8657 , n8660 );
buf ( n8662 , n4210 );
buf ( n8663 , n5234 );
xor ( n8664 , n8662 , n8663 );
or ( n8665 , n8661 , n8664 );
buf ( n8666 , n4211 );
buf ( n8667 , n5235 );
xor ( n8668 , n8666 , n8667 );
or ( n8669 , n8665 , n8668 );
buf ( n8670 , n4212 );
buf ( n8671 , n5236 );
xor ( n8672 , n8670 , n8671 );
or ( n8673 , n8669 , n8672 );
buf ( n8674 , n4213 );
buf ( n8675 , n5237 );
xor ( n8676 , n8674 , n8675 );
or ( n8677 , n8673 , n8676 );
buf ( n8678 , n4214 );
buf ( n8679 , n5238 );
xor ( n8680 , n8678 , n8679 );
or ( n8681 , n8677 , n8680 );
buf ( n8682 , n4215 );
buf ( n8683 , n5239 );
xor ( n8684 , n8682 , n8683 );
or ( n8685 , n8681 , n8684 );
buf ( n8686 , n4216 );
buf ( n8687 , n5240 );
xor ( n8688 , n8686 , n8687 );
or ( n8689 , n8685 , n8688 );
buf ( n8690 , n4217 );
buf ( n8691 , n5241 );
xor ( n8692 , n8690 , n8691 );
or ( n8693 , n8689 , n8692 );
buf ( n8694 , n4218 );
buf ( n8695 , n5242 );
xor ( n8696 , n8694 , n8695 );
or ( n8697 , n8693 , n8696 );
buf ( n8698 , n4219 );
buf ( n8699 , n5243 );
xor ( n8700 , n8698 , n8699 );
or ( n8701 , n8697 , n8700 );
buf ( n8702 , n4220 );
buf ( n8703 , n5244 );
xor ( n8704 , n8702 , n8703 );
or ( n8705 , n8701 , n8704 );
buf ( n8706 , n4221 );
buf ( n8707 , n5245 );
xor ( n8708 , n8706 , n8707 );
or ( n8709 , n8705 , n8708 );
buf ( n8710 , n4222 );
buf ( n8711 , n5246 );
xor ( n8712 , n8710 , n8711 );
or ( n8713 , n8709 , n8712 );
buf ( n8714 , n4223 );
buf ( n8715 , n5247 );
xor ( n8716 , n8714 , n8715 );
or ( n8717 , n8713 , n8716 );
buf ( n8718 , n4224 );
buf ( n8719 , n5248 );
xor ( n8720 , n8718 , n8719 );
or ( n8721 , n8717 , n8720 );
buf ( n8722 , n4225 );
buf ( n8723 , n5249 );
xor ( n8724 , n8722 , n8723 );
or ( n8725 , n8721 , n8724 );
buf ( n8726 , n4226 );
buf ( n8727 , n5250 );
xor ( n8728 , n8726 , n8727 );
or ( n8729 , n8725 , n8728 );
buf ( n8730 , n4227 );
buf ( n8731 , n5251 );
xor ( n8732 , n8730 , n8731 );
or ( n8733 , n8729 , n8732 );
buf ( n8734 , n4228 );
buf ( n8735 , n5252 );
xor ( n8736 , n8734 , n8735 );
or ( n8737 , n8733 , n8736 );
buf ( n8738 , n4229 );
buf ( n8739 , n5253 );
xor ( n8740 , n8738 , n8739 );
or ( n8741 , n8737 , n8740 );
buf ( n8742 , n4230 );
buf ( n8743 , n5254 );
xor ( n8744 , n8742 , n8743 );
or ( n8745 , n8741 , n8744 );
buf ( n8746 , n4231 );
buf ( n8747 , n5255 );
xor ( n8748 , n8746 , n8747 );
or ( n8749 , n8745 , n8748 );
buf ( n8750 , n4232 );
buf ( n8751 , n5256 );
xor ( n8752 , n8750 , n8751 );
or ( n8753 , n8749 , n8752 );
buf ( n8754 , n4233 );
buf ( n8755 , n5257 );
xor ( n8756 , n8754 , n8755 );
or ( n8757 , n8753 , n8756 );
buf ( n8758 , n4234 );
buf ( n8759 , n5258 );
xor ( n8760 , n8758 , n8759 );
or ( n8761 , n8757 , n8760 );
buf ( n8762 , n4235 );
buf ( n8763 , n5259 );
xor ( n8764 , n8762 , n8763 );
or ( n8765 , n8761 , n8764 );
buf ( n8766 , n4236 );
buf ( n8767 , n5260 );
xor ( n8768 , n8766 , n8767 );
or ( n8769 , n8765 , n8768 );
buf ( n8770 , n4237 );
buf ( n8771 , n5261 );
xor ( n8772 , n8770 , n8771 );
or ( n8773 , n8769 , n8772 );
buf ( n8774 , n4238 );
buf ( n8775 , n5262 );
xor ( n8776 , n8774 , n8775 );
or ( n8777 , n8773 , n8776 );
buf ( n8778 , n4239 );
buf ( n8779 , n5263 );
xor ( n8780 , n8778 , n8779 );
or ( n8781 , n8777 , n8780 );
buf ( n8782 , n4240 );
buf ( n8783 , n5264 );
xor ( n8784 , n8782 , n8783 );
or ( n8785 , n8781 , n8784 );
buf ( n8786 , n4241 );
buf ( n8787 , n5265 );
xor ( n8788 , n8786 , n8787 );
or ( n8789 , n8785 , n8788 );
buf ( n8790 , n4242 );
buf ( n8791 , n5266 );
xor ( n8792 , n8790 , n8791 );
or ( n8793 , n8789 , n8792 );
buf ( n8794 , n4243 );
buf ( n8795 , n5267 );
xor ( n8796 , n8794 , n8795 );
or ( n8797 , n8793 , n8796 );
buf ( n8798 , n4244 );
buf ( n8799 , n5268 );
xor ( n8800 , n8798 , n8799 );
or ( n8801 , n8797 , n8800 );
buf ( n8802 , n4245 );
buf ( n8803 , n5269 );
xor ( n8804 , n8802 , n8803 );
or ( n8805 , n8801 , n8804 );
buf ( n8806 , n4246 );
buf ( n8807 , n5270 );
xor ( n8808 , n8806 , n8807 );
or ( n8809 , n8805 , n8808 );
buf ( n8810 , n4247 );
buf ( n8811 , n5271 );
xor ( n8812 , n8810 , n8811 );
or ( n8813 , n8809 , n8812 );
buf ( n8814 , n4248 );
buf ( n8815 , n5272 );
xor ( n8816 , n8814 , n8815 );
or ( n8817 , n8813 , n8816 );
buf ( n8818 , n4249 );
buf ( n8819 , n5273 );
xor ( n8820 , n8818 , n8819 );
or ( n8821 , n8817 , n8820 );
buf ( n8822 , n4250 );
buf ( n8823 , n5274 );
xor ( n8824 , n8822 , n8823 );
or ( n8825 , n8821 , n8824 );
buf ( n8826 , n4251 );
buf ( n8827 , n5275 );
xor ( n8828 , n8826 , n8827 );
or ( n8829 , n8825 , n8828 );
buf ( n8830 , n4252 );
buf ( n8831 , n5276 );
xor ( n8832 , n8830 , n8831 );
or ( n8833 , n8829 , n8832 );
buf ( n8834 , n4253 );
buf ( n8835 , n5277 );
xor ( n8836 , n8834 , n8835 );
or ( n8837 , n8833 , n8836 );
buf ( n8838 , n4254 );
buf ( n8839 , n5278 );
xor ( n8840 , n8838 , n8839 );
or ( n8841 , n8837 , n8840 );
buf ( n8842 , n4255 );
buf ( n8843 , n5279 );
xor ( n8844 , n8842 , n8843 );
or ( n8845 , n8841 , n8844 );
buf ( n8846 , n4256 );
buf ( n8847 , n5280 );
xor ( n8848 , n8846 , n8847 );
or ( n8849 , n8845 , n8848 );
buf ( n8850 , n4257 );
buf ( n8851 , n5281 );
xor ( n8852 , n8850 , n8851 );
or ( n8853 , n8849 , n8852 );
buf ( n8854 , n4258 );
buf ( n8855 , n5282 );
xor ( n8856 , n8854 , n8855 );
or ( n8857 , n8853 , n8856 );
buf ( n8858 , n4259 );
buf ( n8859 , n5283 );
xor ( n8860 , n8858 , n8859 );
or ( n8861 , n8857 , n8860 );
buf ( n8862 , n4260 );
buf ( n8863 , n5284 );
xor ( n8864 , n8862 , n8863 );
or ( n8865 , n8861 , n8864 );
buf ( n8866 , n4261 );
buf ( n8867 , n5285 );
xor ( n8868 , n8866 , n8867 );
or ( n8869 , n8865 , n8868 );
buf ( n8870 , n4262 );
buf ( n8871 , n5286 );
xor ( n8872 , n8870 , n8871 );
or ( n8873 , n8869 , n8872 );
buf ( n8874 , n4263 );
buf ( n8875 , n5287 );
xor ( n8876 , n8874 , n8875 );
or ( n8877 , n8873 , n8876 );
buf ( n8878 , n4264 );
buf ( n8879 , n5288 );
xor ( n8880 , n8878 , n8879 );
or ( n8881 , n8877 , n8880 );
buf ( n8882 , n4265 );
buf ( n8883 , n5289 );
xor ( n8884 , n8882 , n8883 );
or ( n8885 , n8881 , n8884 );
buf ( n8886 , n4266 );
buf ( n8887 , n5290 );
xor ( n8888 , n8886 , n8887 );
or ( n8889 , n8885 , n8888 );
buf ( n8890 , n4267 );
buf ( n8891 , n5291 );
xor ( n8892 , n8890 , n8891 );
or ( n8893 , n8889 , n8892 );
buf ( n8894 , n4268 );
buf ( n8895 , n5292 );
xor ( n8896 , n8894 , n8895 );
or ( n8897 , n8893 , n8896 );
buf ( n8898 , n4269 );
buf ( n8899 , n5293 );
xor ( n8900 , n8898 , n8899 );
or ( n8901 , n8897 , n8900 );
buf ( n8902 , n4270 );
buf ( n8903 , n5294 );
xor ( n8904 , n8902 , n8903 );
or ( n8905 , n8901 , n8904 );
buf ( n8906 , n4271 );
buf ( n8907 , n5295 );
xor ( n8908 , n8906 , n8907 );
or ( n8909 , n8905 , n8908 );
buf ( n8910 , n4272 );
buf ( n8911 , n5296 );
xor ( n8912 , n8910 , n8911 );
or ( n8913 , n8909 , n8912 );
buf ( n8914 , n4273 );
buf ( n8915 , n5297 );
xor ( n8916 , n8914 , n8915 );
or ( n8917 , n8913 , n8916 );
buf ( n8918 , n4274 );
buf ( n8919 , n5298 );
xor ( n8920 , n8918 , n8919 );
or ( n8921 , n8917 , n8920 );
buf ( n8922 , n4275 );
buf ( n8923 , n5299 );
xor ( n8924 , n8922 , n8923 );
or ( n8925 , n8921 , n8924 );
buf ( n8926 , n4276 );
buf ( n8927 , n5300 );
xor ( n8928 , n8926 , n8927 );
or ( n8929 , n8925 , n8928 );
buf ( n8930 , n4277 );
buf ( n8931 , n5301 );
xor ( n8932 , n8930 , n8931 );
or ( n8933 , n8929 , n8932 );
buf ( n8934 , n4278 );
buf ( n8935 , n5302 );
xor ( n8936 , n8934 , n8935 );
or ( n8937 , n8933 , n8936 );
buf ( n8938 , n4279 );
buf ( n8939 , n5303 );
xor ( n8940 , n8938 , n8939 );
or ( n8941 , n8937 , n8940 );
buf ( n8942 , n4280 );
buf ( n8943 , n5304 );
xor ( n8944 , n8942 , n8943 );
or ( n8945 , n8941 , n8944 );
buf ( n8946 , n4281 );
buf ( n8947 , n5305 );
xor ( n8948 , n8946 , n8947 );
or ( n8949 , n8945 , n8948 );
buf ( n8950 , n4282 );
buf ( n8951 , n5306 );
xor ( n8952 , n8950 , n8951 );
or ( n8953 , n8949 , n8952 );
buf ( n8954 , n4283 );
buf ( n8955 , n5307 );
xor ( n8956 , n8954 , n8955 );
or ( n8957 , n8953 , n8956 );
buf ( n8958 , n4284 );
buf ( n8959 , n5308 );
xor ( n8960 , n8958 , n8959 );
or ( n8961 , n8957 , n8960 );
buf ( n8962 , n4285 );
buf ( n8963 , n5309 );
xor ( n8964 , n8962 , n8963 );
or ( n8965 , n8961 , n8964 );
buf ( n8966 , n4286 );
buf ( n8967 , n5310 );
xor ( n8968 , n8966 , n8967 );
or ( n8969 , n8965 , n8968 );
buf ( n8970 , n4287 );
buf ( n8971 , n5311 );
xor ( n8972 , n8970 , n8971 );
or ( n8973 , n8969 , n8972 );
buf ( n8974 , n4288 );
buf ( n8975 , n5312 );
xor ( n8976 , n8974 , n8975 );
or ( n8977 , n8973 , n8976 );
buf ( n8978 , n4289 );
buf ( n8979 , n5313 );
xor ( n8980 , n8978 , n8979 );
or ( n8981 , n8977 , n8980 );
buf ( n8982 , n4290 );
buf ( n8983 , n5314 );
xor ( n8984 , n8982 , n8983 );
or ( n8985 , n8981 , n8984 );
buf ( n8986 , n4291 );
buf ( n8987 , n5315 );
xor ( n8988 , n8986 , n8987 );
or ( n8989 , n8985 , n8988 );
buf ( n8990 , n4292 );
buf ( n8991 , n5316 );
xor ( n8992 , n8990 , n8991 );
or ( n8993 , n8989 , n8992 );
buf ( n8994 , n4293 );
buf ( n8995 , n5317 );
xor ( n8996 , n8994 , n8995 );
or ( n8997 , n8993 , n8996 );
buf ( n8998 , n4294 );
buf ( n8999 , n5318 );
xor ( n9000 , n8998 , n8999 );
or ( n9001 , n8997 , n9000 );
buf ( n9002 , n4295 );
buf ( n9003 , n5319 );
xor ( n9004 , n9002 , n9003 );
or ( n9005 , n9001 , n9004 );
buf ( n9006 , n4296 );
buf ( n9007 , n5320 );
xor ( n9008 , n9006 , n9007 );
or ( n9009 , n9005 , n9008 );
buf ( n9010 , n4297 );
buf ( n9011 , n5321 );
xor ( n9012 , n9010 , n9011 );
or ( n9013 , n9009 , n9012 );
buf ( n9014 , n4298 );
buf ( n9015 , n5322 );
xor ( n9016 , n9014 , n9015 );
or ( n9017 , n9013 , n9016 );
buf ( n9018 , n4299 );
buf ( n9019 , n5323 );
xor ( n9020 , n9018 , n9019 );
or ( n9021 , n9017 , n9020 );
buf ( n9022 , n4300 );
buf ( n9023 , n5324 );
xor ( n9024 , n9022 , n9023 );
or ( n9025 , n9021 , n9024 );
buf ( n9026 , n4301 );
buf ( n9027 , n5325 );
xor ( n9028 , n9026 , n9027 );
or ( n9029 , n9025 , n9028 );
buf ( n9030 , n4302 );
buf ( n9031 , n5326 );
xor ( n9032 , n9030 , n9031 );
or ( n9033 , n9029 , n9032 );
buf ( n9034 , n4303 );
buf ( n9035 , n5327 );
xor ( n9036 , n9034 , n9035 );
or ( n9037 , n9033 , n9036 );
buf ( n9038 , n4304 );
buf ( n9039 , n5328 );
xor ( n9040 , n9038 , n9039 );
or ( n9041 , n9037 , n9040 );
buf ( n9042 , n4305 );
buf ( n9043 , n5329 );
xor ( n9044 , n9042 , n9043 );
or ( n9045 , n9041 , n9044 );
buf ( n9046 , n4306 );
buf ( n9047 , n5330 );
xor ( n9048 , n9046 , n9047 );
or ( n9049 , n9045 , n9048 );
buf ( n9050 , n4307 );
buf ( n9051 , n5331 );
xor ( n9052 , n9050 , n9051 );
or ( n9053 , n9049 , n9052 );
buf ( n9054 , n4308 );
buf ( n9055 , n5332 );
xor ( n9056 , n9054 , n9055 );
or ( n9057 , n9053 , n9056 );
buf ( n9058 , n4309 );
buf ( n9059 , n5333 );
xor ( n9060 , n9058 , n9059 );
or ( n9061 , n9057 , n9060 );
buf ( n9062 , n4310 );
buf ( n9063 , n5334 );
xor ( n9064 , n9062 , n9063 );
or ( n9065 , n9061 , n9064 );
buf ( n9066 , n4311 );
buf ( n9067 , n5335 );
xor ( n9068 , n9066 , n9067 );
or ( n9069 , n9065 , n9068 );
buf ( n9070 , n4312 );
buf ( n9071 , n5336 );
xor ( n9072 , n9070 , n9071 );
or ( n9073 , n9069 , n9072 );
buf ( n9074 , n4313 );
buf ( n9075 , n5337 );
xor ( n9076 , n9074 , n9075 );
or ( n9077 , n9073 , n9076 );
buf ( n9078 , n4314 );
buf ( n9079 , n5338 );
xor ( n9080 , n9078 , n9079 );
or ( n9081 , n9077 , n9080 );
buf ( n9082 , n4315 );
buf ( n9083 , n5339 );
xor ( n9084 , n9082 , n9083 );
or ( n9085 , n9081 , n9084 );
buf ( n9086 , n4316 );
buf ( n9087 , n5340 );
xor ( n9088 , n9086 , n9087 );
or ( n9089 , n9085 , n9088 );
buf ( n9090 , n4317 );
buf ( n9091 , n5341 );
xor ( n9092 , n9090 , n9091 );
or ( n9093 , n9089 , n9092 );
buf ( n9094 , n4318 );
buf ( n9095 , n5342 );
xor ( n9096 , n9094 , n9095 );
or ( n9097 , n9093 , n9096 );
buf ( n9098 , n4319 );
buf ( n9099 , n5343 );
xor ( n9100 , n9098 , n9099 );
or ( n9101 , n9097 , n9100 );
buf ( n9102 , n4320 );
buf ( n9103 , n5344 );
xor ( n9104 , n9102 , n9103 );
or ( n9105 , n9101 , n9104 );
buf ( n9106 , n4321 );
buf ( n9107 , n5345 );
xor ( n9108 , n9106 , n9107 );
or ( n9109 , n9105 , n9108 );
buf ( n9110 , n4322 );
buf ( n9111 , n5346 );
xor ( n9112 , n9110 , n9111 );
or ( n9113 , n9109 , n9112 );
buf ( n9114 , n4323 );
buf ( n9115 , n5347 );
xor ( n9116 , n9114 , n9115 );
or ( n9117 , n9113 , n9116 );
buf ( n9118 , n4324 );
buf ( n9119 , n5348 );
xor ( n9120 , n9118 , n9119 );
or ( n9121 , n9117 , n9120 );
buf ( n9122 , n4325 );
buf ( n9123 , n5349 );
xor ( n9124 , n9122 , n9123 );
or ( n9125 , n9121 , n9124 );
buf ( n9126 , n4326 );
buf ( n9127 , n5350 );
xor ( n9128 , n9126 , n9127 );
or ( n9129 , n9125 , n9128 );
buf ( n9130 , n4327 );
buf ( n9131 , n5351 );
xor ( n9132 , n9130 , n9131 );
or ( n9133 , n9129 , n9132 );
buf ( n9134 , n4328 );
buf ( n9135 , n5352 );
xor ( n9136 , n9134 , n9135 );
or ( n9137 , n9133 , n9136 );
buf ( n9138 , n4329 );
buf ( n9139 , n5353 );
xor ( n9140 , n9138 , n9139 );
or ( n9141 , n9137 , n9140 );
buf ( n9142 , n4330 );
buf ( n9143 , n5354 );
xor ( n9144 , n9142 , n9143 );
or ( n9145 , n9141 , n9144 );
buf ( n9146 , n4331 );
buf ( n9147 , n5355 );
xor ( n9148 , n9146 , n9147 );
or ( n9149 , n9145 , n9148 );
buf ( n9150 , n4332 );
buf ( n9151 , n5356 );
xor ( n9152 , n9150 , n9151 );
or ( n9153 , n9149 , n9152 );
buf ( n9154 , n4333 );
buf ( n9155 , n5357 );
xor ( n9156 , n9154 , n9155 );
or ( n9157 , n9153 , n9156 );
buf ( n9158 , n4334 );
buf ( n9159 , n5358 );
xor ( n9160 , n9158 , n9159 );
or ( n9161 , n9157 , n9160 );
buf ( n9162 , n4335 );
buf ( n9163 , n5359 );
xor ( n9164 , n9162 , n9163 );
or ( n9165 , n9161 , n9164 );
buf ( n9166 , n4336 );
buf ( n9167 , n5360 );
xor ( n9168 , n9166 , n9167 );
or ( n9169 , n9165 , n9168 );
buf ( n9170 , n4337 );
buf ( n9171 , n5361 );
xor ( n9172 , n9170 , n9171 );
or ( n9173 , n9169 , n9172 );
buf ( n9174 , n4338 );
buf ( n9175 , n5362 );
xor ( n9176 , n9174 , n9175 );
or ( n9177 , n9173 , n9176 );
buf ( n9178 , n4339 );
buf ( n9179 , n5363 );
xor ( n9180 , n9178 , n9179 );
or ( n9181 , n9177 , n9180 );
buf ( n9182 , n4340 );
buf ( n9183 , n5364 );
xor ( n9184 , n9182 , n9183 );
or ( n9185 , n9181 , n9184 );
buf ( n9186 , n4341 );
buf ( n9187 , n5365 );
xor ( n9188 , n9186 , n9187 );
or ( n9189 , n9185 , n9188 );
buf ( n9190 , n4342 );
buf ( n9191 , n5366 );
xor ( n9192 , n9190 , n9191 );
or ( n9193 , n9189 , n9192 );
buf ( n9194 , n4343 );
buf ( n9195 , n5367 );
xor ( n9196 , n9194 , n9195 );
or ( n9197 , n9193 , n9196 );
buf ( n9198 , n4344 );
buf ( n9199 , n5368 );
xor ( n9200 , n9198 , n9199 );
or ( n9201 , n9197 , n9200 );
buf ( n9202 , n4345 );
buf ( n9203 , n5369 );
xor ( n9204 , n9202 , n9203 );
or ( n9205 , n9201 , n9204 );
buf ( n9206 , n4346 );
buf ( n9207 , n5370 );
xor ( n9208 , n9206 , n9207 );
or ( n9209 , n9205 , n9208 );
buf ( n9210 , n4347 );
buf ( n9211 , n5371 );
xor ( n9212 , n9210 , n9211 );
or ( n9213 , n9209 , n9212 );
buf ( n9214 , n4348 );
buf ( n9215 , n5372 );
xor ( n9216 , n9214 , n9215 );
or ( n9217 , n9213 , n9216 );
buf ( n9218 , n4349 );
buf ( n9219 , n5373 );
xor ( n9220 , n9218 , n9219 );
or ( n9221 , n9217 , n9220 );
buf ( n9222 , n4350 );
buf ( n9223 , n5374 );
xor ( n9224 , n9222 , n9223 );
or ( n9225 , n9221 , n9224 );
buf ( n9226 , n4351 );
buf ( n9227 , n5375 );
xor ( n9228 , n9226 , n9227 );
or ( n9229 , n9225 , n9228 );
buf ( n9230 , n4352 );
buf ( n9231 , n5376 );
xor ( n9232 , n9230 , n9231 );
or ( n9233 , n9229 , n9232 );
buf ( n9234 , n4353 );
buf ( n9235 , n5377 );
xor ( n9236 , n9234 , n9235 );
or ( n9237 , n9233 , n9236 );
buf ( n9238 , n4354 );
buf ( n9239 , n5378 );
xor ( n9240 , n9238 , n9239 );
or ( n9241 , n9237 , n9240 );
buf ( n9242 , n4355 );
buf ( n9243 , n5379 );
xor ( n9244 , n9242 , n9243 );
or ( n9245 , n9241 , n9244 );
buf ( n9246 , n4356 );
buf ( n9247 , n5380 );
xor ( n9248 , n9246 , n9247 );
or ( n9249 , n9245 , n9248 );
buf ( n9250 , n4357 );
buf ( n9251 , n5381 );
xor ( n9252 , n9250 , n9251 );
or ( n9253 , n9249 , n9252 );
buf ( n9254 , n4358 );
buf ( n9255 , n5382 );
xor ( n9256 , n9254 , n9255 );
or ( n9257 , n9253 , n9256 );
buf ( n9258 , n4359 );
buf ( n9259 , n5383 );
xor ( n9260 , n9258 , n9259 );
or ( n9261 , n9257 , n9260 );
buf ( n9262 , n4360 );
buf ( n9263 , n5384 );
xor ( n9264 , n9262 , n9263 );
or ( n9265 , n9261 , n9264 );
buf ( n9266 , n4361 );
buf ( n9267 , n5385 );
xor ( n9268 , n9266 , n9267 );
or ( n9269 , n9265 , n9268 );
buf ( n9270 , n4362 );
buf ( n9271 , n5386 );
xor ( n9272 , n9270 , n9271 );
or ( n9273 , n9269 , n9272 );
buf ( n9274 , n4363 );
buf ( n9275 , n5387 );
xor ( n9276 , n9274 , n9275 );
or ( n9277 , n9273 , n9276 );
buf ( n9278 , n4364 );
buf ( n9279 , n5388 );
xor ( n9280 , n9278 , n9279 );
or ( n9281 , n9277 , n9280 );
buf ( n9282 , n4365 );
buf ( n9283 , n5389 );
xor ( n9284 , n9282 , n9283 );
or ( n9285 , n9281 , n9284 );
buf ( n9286 , n4366 );
buf ( n9287 , n5390 );
xor ( n9288 , n9286 , n9287 );
or ( n9289 , n9285 , n9288 );
buf ( n9290 , n4367 );
buf ( n9291 , n5391 );
xor ( n9292 , n9290 , n9291 );
or ( n9293 , n9289 , n9292 );
buf ( n9294 , n4368 );
buf ( n9295 , n5392 );
xor ( n9296 , n9294 , n9295 );
or ( n9297 , n9293 , n9296 );
buf ( n9298 , n4369 );
buf ( n9299 , n5393 );
xor ( n9300 , n9298 , n9299 );
or ( n9301 , n9297 , n9300 );
buf ( n9302 , n4370 );
buf ( n9303 , n5394 );
xor ( n9304 , n9302 , n9303 );
or ( n9305 , n9301 , n9304 );
buf ( n9306 , n4371 );
buf ( n9307 , n5395 );
xor ( n9308 , n9306 , n9307 );
or ( n9309 , n9305 , n9308 );
buf ( n9310 , n4372 );
buf ( n9311 , n5396 );
xor ( n9312 , n9310 , n9311 );
or ( n9313 , n9309 , n9312 );
buf ( n9314 , n4373 );
buf ( n9315 , n5397 );
xor ( n9316 , n9314 , n9315 );
or ( n9317 , n9313 , n9316 );
buf ( n9318 , n4374 );
buf ( n9319 , n5398 );
xor ( n9320 , n9318 , n9319 );
or ( n9321 , n9317 , n9320 );
buf ( n9322 , n4375 );
buf ( n9323 , n5399 );
xor ( n9324 , n9322 , n9323 );
or ( n9325 , n9321 , n9324 );
buf ( n9326 , n4376 );
buf ( n9327 , n5400 );
xor ( n9328 , n9326 , n9327 );
or ( n9329 , n9325 , n9328 );
buf ( n9330 , n4377 );
buf ( n9331 , n5401 );
xor ( n9332 , n9330 , n9331 );
or ( n9333 , n9329 , n9332 );
buf ( n9334 , n4378 );
buf ( n9335 , n5402 );
xor ( n9336 , n9334 , n9335 );
or ( n9337 , n9333 , n9336 );
buf ( n9338 , n4379 );
buf ( n9339 , n5403 );
xor ( n9340 , n9338 , n9339 );
or ( n9341 , n9337 , n9340 );
buf ( n9342 , n4380 );
buf ( n9343 , n5404 );
xor ( n9344 , n9342 , n9343 );
or ( n9345 , n9341 , n9344 );
buf ( n9346 , n4381 );
buf ( n9347 , n5405 );
xor ( n9348 , n9346 , n9347 );
or ( n9349 , n9345 , n9348 );
buf ( n9350 , n4382 );
buf ( n9351 , n5406 );
xor ( n9352 , n9350 , n9351 );
or ( n9353 , n9349 , n9352 );
buf ( n9354 , n4383 );
buf ( n9355 , n5407 );
xor ( n9356 , n9354 , n9355 );
or ( n9357 , n9353 , n9356 );
buf ( n9358 , n4384 );
buf ( n9359 , n5408 );
xor ( n9360 , n9358 , n9359 );
or ( n9361 , n9357 , n9360 );
buf ( n9362 , n4385 );
buf ( n9363 , n5409 );
xor ( n9364 , n9362 , n9363 );
or ( n9365 , n9361 , n9364 );
buf ( n9366 , n4386 );
buf ( n9367 , n5410 );
xor ( n9368 , n9366 , n9367 );
or ( n9369 , n9365 , n9368 );
buf ( n9370 , n4387 );
buf ( n9371 , n5411 );
xor ( n9372 , n9370 , n9371 );
or ( n9373 , n9369 , n9372 );
buf ( n9374 , n4388 );
buf ( n9375 , n5412 );
xor ( n9376 , n9374 , n9375 );
or ( n9377 , n9373 , n9376 );
buf ( n9378 , n4389 );
buf ( n9379 , n5413 );
xor ( n9380 , n9378 , n9379 );
or ( n9381 , n9377 , n9380 );
buf ( n9382 , n4390 );
buf ( n9383 , n5414 );
xor ( n9384 , n9382 , n9383 );
or ( n9385 , n9381 , n9384 );
buf ( n9386 , n4391 );
buf ( n9387 , n5415 );
xor ( n9388 , n9386 , n9387 );
or ( n9389 , n9385 , n9388 );
buf ( n9390 , n4392 );
buf ( n9391 , n5416 );
xor ( n9392 , n9390 , n9391 );
or ( n9393 , n9389 , n9392 );
buf ( n9394 , n4393 );
buf ( n9395 , n5417 );
xor ( n9396 , n9394 , n9395 );
or ( n9397 , n9393 , n9396 );
buf ( n9398 , n4394 );
buf ( n9399 , n5418 );
xor ( n9400 , n9398 , n9399 );
or ( n9401 , n9397 , n9400 );
buf ( n9402 , n4395 );
buf ( n9403 , n5419 );
xor ( n9404 , n9402 , n9403 );
or ( n9405 , n9401 , n9404 );
buf ( n9406 , n4396 );
buf ( n9407 , n5420 );
xor ( n9408 , n9406 , n9407 );
or ( n9409 , n9405 , n9408 );
buf ( n9410 , n4397 );
buf ( n9411 , n5421 );
xor ( n9412 , n9410 , n9411 );
or ( n9413 , n9409 , n9412 );
buf ( n9414 , n4398 );
buf ( n9415 , n5422 );
xor ( n9416 , n9414 , n9415 );
or ( n9417 , n9413 , n9416 );
buf ( n9418 , n4399 );
buf ( n9419 , n5423 );
xor ( n9420 , n9418 , n9419 );
or ( n9421 , n9417 , n9420 );
buf ( n9422 , n4400 );
buf ( n9423 , n5424 );
xor ( n9424 , n9422 , n9423 );
or ( n9425 , n9421 , n9424 );
buf ( n9426 , n4401 );
buf ( n9427 , n5425 );
xor ( n9428 , n9426 , n9427 );
or ( n9429 , n9425 , n9428 );
buf ( n9430 , n4402 );
buf ( n9431 , n5426 );
xor ( n9432 , n9430 , n9431 );
or ( n9433 , n9429 , n9432 );
buf ( n9434 , n4403 );
buf ( n9435 , n5427 );
xor ( n9436 , n9434 , n9435 );
or ( n9437 , n9433 , n9436 );
buf ( n9438 , n4404 );
buf ( n9439 , n5428 );
xor ( n9440 , n9438 , n9439 );
or ( n9441 , n9437 , n9440 );
buf ( n9442 , n4405 );
buf ( n9443 , n5429 );
xor ( n9444 , n9442 , n9443 );
or ( n9445 , n9441 , n9444 );
buf ( n9446 , n4406 );
buf ( n9447 , n5430 );
xor ( n9448 , n9446 , n9447 );
or ( n9449 , n9445 , n9448 );
buf ( n9450 , n4407 );
buf ( n9451 , n5431 );
xor ( n9452 , n9450 , n9451 );
or ( n9453 , n9449 , n9452 );
buf ( n9454 , n4408 );
buf ( n9455 , n5432 );
xor ( n9456 , n9454 , n9455 );
or ( n9457 , n9453 , n9456 );
buf ( n9458 , n4409 );
buf ( n9459 , n5433 );
xor ( n9460 , n9458 , n9459 );
or ( n9461 , n9457 , n9460 );
buf ( n9462 , n4410 );
buf ( n9463 , n5434 );
xor ( n9464 , n9462 , n9463 );
or ( n9465 , n9461 , n9464 );
buf ( n9466 , n4411 );
buf ( n9467 , n5435 );
xor ( n9468 , n9466 , n9467 );
or ( n9469 , n9465 , n9468 );
buf ( n9470 , n4412 );
buf ( n9471 , n5436 );
xor ( n9472 , n9470 , n9471 );
or ( n9473 , n9469 , n9472 );
buf ( n9474 , n4413 );
buf ( n9475 , n5437 );
xor ( n9476 , n9474 , n9475 );
or ( n9477 , n9473 , n9476 );
buf ( n9478 , n4414 );
buf ( n9479 , n5438 );
xor ( n9480 , n9478 , n9479 );
or ( n9481 , n9477 , n9480 );
buf ( n9482 , n4415 );
buf ( n9483 , n5439 );
xor ( n9484 , n9482 , n9483 );
or ( n9485 , n9481 , n9484 );
buf ( n9486 , n4416 );
buf ( n9487 , n5440 );
xor ( n9488 , n9486 , n9487 );
or ( n9489 , n9485 , n9488 );
buf ( n9490 , n4417 );
buf ( n9491 , n5441 );
xor ( n9492 , n9490 , n9491 );
or ( n9493 , n9489 , n9492 );
buf ( n9494 , n4418 );
buf ( n9495 , n5442 );
xor ( n9496 , n9494 , n9495 );
or ( n9497 , n9493 , n9496 );
buf ( n9498 , n4419 );
buf ( n9499 , n5443 );
xor ( n9500 , n9498 , n9499 );
or ( n9501 , n9497 , n9500 );
buf ( n9502 , n4420 );
buf ( n9503 , n5444 );
xor ( n9504 , n9502 , n9503 );
or ( n9505 , n9501 , n9504 );
buf ( n9506 , n4421 );
buf ( n9507 , n5445 );
xor ( n9508 , n9506 , n9507 );
or ( n9509 , n9505 , n9508 );
buf ( n9510 , n4422 );
buf ( n9511 , n5446 );
xor ( n9512 , n9510 , n9511 );
or ( n9513 , n9509 , n9512 );
buf ( n9514 , n4423 );
buf ( n9515 , n5447 );
xor ( n9516 , n9514 , n9515 );
or ( n9517 , n9513 , n9516 );
buf ( n9518 , n4424 );
buf ( n9519 , n5448 );
xor ( n9520 , n9518 , n9519 );
or ( n9521 , n9517 , n9520 );
buf ( n9522 , n4425 );
buf ( n9523 , n5449 );
xor ( n9524 , n9522 , n9523 );
or ( n9525 , n9521 , n9524 );
buf ( n9526 , n4426 );
buf ( n9527 , n5450 );
xor ( n9528 , n9526 , n9527 );
or ( n9529 , n9525 , n9528 );
buf ( n9530 , n4427 );
buf ( n9531 , n5451 );
xor ( n9532 , n9530 , n9531 );
or ( n9533 , n9529 , n9532 );
buf ( n9534 , n4428 );
buf ( n9535 , n5452 );
xor ( n9536 , n9534 , n9535 );
or ( n9537 , n9533 , n9536 );
buf ( n9538 , n4429 );
buf ( n9539 , n5453 );
xor ( n9540 , n9538 , n9539 );
or ( n9541 , n9537 , n9540 );
buf ( n9542 , n4430 );
buf ( n9543 , n5454 );
xor ( n9544 , n9542 , n9543 );
or ( n9545 , n9541 , n9544 );
buf ( n9546 , n4431 );
buf ( n9547 , n5455 );
xor ( n9548 , n9546 , n9547 );
or ( n9549 , n9545 , n9548 );
buf ( n9550 , n4432 );
buf ( n9551 , n5456 );
xor ( n9552 , n9550 , n9551 );
or ( n9553 , n9549 , n9552 );
buf ( n9554 , n4433 );
buf ( n9555 , n5457 );
xor ( n9556 , n9554 , n9555 );
or ( n9557 , n9553 , n9556 );
buf ( n9558 , n4434 );
buf ( n9559 , n5458 );
xor ( n9560 , n9558 , n9559 );
or ( n9561 , n9557 , n9560 );
buf ( n9562 , n4435 );
buf ( n9563 , n5459 );
xor ( n9564 , n9562 , n9563 );
or ( n9565 , n9561 , n9564 );
buf ( n9566 , n4436 );
buf ( n9567 , n5460 );
xor ( n9568 , n9566 , n9567 );
or ( n9569 , n9565 , n9568 );
buf ( n9570 , n4437 );
buf ( n9571 , n5461 );
xor ( n9572 , n9570 , n9571 );
or ( n9573 , n9569 , n9572 );
buf ( n9574 , n4438 );
buf ( n9575 , n5462 );
xor ( n9576 , n9574 , n9575 );
or ( n9577 , n9573 , n9576 );
buf ( n9578 , n4439 );
buf ( n9579 , n5463 );
xor ( n9580 , n9578 , n9579 );
or ( n9581 , n9577 , n9580 );
buf ( n9582 , n4440 );
buf ( n9583 , n5464 );
xor ( n9584 , n9582 , n9583 );
or ( n9585 , n9581 , n9584 );
buf ( n9586 , n4441 );
buf ( n9587 , n5465 );
xor ( n9588 , n9586 , n9587 );
or ( n9589 , n9585 , n9588 );
buf ( n9590 , n4442 );
buf ( n9591 , n5466 );
xor ( n9592 , n9590 , n9591 );
or ( n9593 , n9589 , n9592 );
buf ( n9594 , n4443 );
buf ( n9595 , n5467 );
xor ( n9596 , n9594 , n9595 );
or ( n9597 , n9593 , n9596 );
buf ( n9598 , n4444 );
buf ( n9599 , n5468 );
xor ( n9600 , n9598 , n9599 );
or ( n9601 , n9597 , n9600 );
buf ( n9602 , n4445 );
buf ( n9603 , n5469 );
xor ( n9604 , n9602 , n9603 );
or ( n9605 , n9601 , n9604 );
buf ( n9606 , n4446 );
buf ( n9607 , n5470 );
xor ( n9608 , n9606 , n9607 );
or ( n9609 , n9605 , n9608 );
buf ( n9610 , n4447 );
buf ( n9611 , n5471 );
xor ( n9612 , n9610 , n9611 );
or ( n9613 , n9609 , n9612 );
buf ( n9614 , n4448 );
buf ( n9615 , n5472 );
xor ( n9616 , n9614 , n9615 );
or ( n9617 , n9613 , n9616 );
buf ( n9618 , n4449 );
buf ( n9619 , n5473 );
xor ( n9620 , n9618 , n9619 );
or ( n9621 , n9617 , n9620 );
buf ( n9622 , n4450 );
buf ( n9623 , n5474 );
xor ( n9624 , n9622 , n9623 );
or ( n9625 , n9621 , n9624 );
buf ( n9626 , n4451 );
buf ( n9627 , n5475 );
xor ( n9628 , n9626 , n9627 );
or ( n9629 , n9625 , n9628 );
buf ( n9630 , n4452 );
buf ( n9631 , n5476 );
xor ( n9632 , n9630 , n9631 );
or ( n9633 , n9629 , n9632 );
buf ( n9634 , n4453 );
buf ( n9635 , n5477 );
xor ( n9636 , n9634 , n9635 );
or ( n9637 , n9633 , n9636 );
buf ( n9638 , n4454 );
buf ( n9639 , n5478 );
xor ( n9640 , n9638 , n9639 );
or ( n9641 , n9637 , n9640 );
buf ( n9642 , n4455 );
buf ( n9643 , n5479 );
xor ( n9644 , n9642 , n9643 );
or ( n9645 , n9641 , n9644 );
buf ( n9646 , n4456 );
buf ( n9647 , n5480 );
xor ( n9648 , n9646 , n9647 );
or ( n9649 , n9645 , n9648 );
buf ( n9650 , n4457 );
buf ( n9651 , n5481 );
xor ( n9652 , n9650 , n9651 );
or ( n9653 , n9649 , n9652 );
buf ( n9654 , n4458 );
buf ( n9655 , n5482 );
xor ( n9656 , n9654 , n9655 );
or ( n9657 , n9653 , n9656 );
buf ( n9658 , n4459 );
buf ( n9659 , n5483 );
xor ( n9660 , n9658 , n9659 );
or ( n9661 , n9657 , n9660 );
buf ( n9662 , n4460 );
buf ( n9663 , n5484 );
xor ( n9664 , n9662 , n9663 );
or ( n9665 , n9661 , n9664 );
buf ( n9666 , n4461 );
buf ( n9667 , n5485 );
xor ( n9668 , n9666 , n9667 );
or ( n9669 , n9665 , n9668 );
buf ( n9670 , n4462 );
buf ( n9671 , n5486 );
xor ( n9672 , n9670 , n9671 );
or ( n9673 , n9669 , n9672 );
buf ( n9674 , n4463 );
buf ( n9675 , n5487 );
xor ( n9676 , n9674 , n9675 );
or ( n9677 , n9673 , n9676 );
buf ( n9678 , n4464 );
buf ( n9679 , n5488 );
xor ( n9680 , n9678 , n9679 );
or ( n9681 , n9677 , n9680 );
buf ( n9682 , n4465 );
buf ( n9683 , n5489 );
xor ( n9684 , n9682 , n9683 );
or ( n9685 , n9681 , n9684 );
buf ( n9686 , n4466 );
buf ( n9687 , n5490 );
xor ( n9688 , n9686 , n9687 );
or ( n9689 , n9685 , n9688 );
buf ( n9690 , n4467 );
buf ( n9691 , n5491 );
xor ( n9692 , n9690 , n9691 );
or ( n9693 , n9689 , n9692 );
buf ( n9694 , n4468 );
buf ( n9695 , n5492 );
xor ( n9696 , n9694 , n9695 );
or ( n9697 , n9693 , n9696 );
buf ( n9698 , n4469 );
buf ( n9699 , n5493 );
xor ( n9700 , n9698 , n9699 );
or ( n9701 , n9697 , n9700 );
buf ( n9702 , n4470 );
buf ( n9703 , n5494 );
xor ( n9704 , n9702 , n9703 );
or ( n9705 , n9701 , n9704 );
buf ( n9706 , n4471 );
buf ( n9707 , n5495 );
xor ( n9708 , n9706 , n9707 );
or ( n9709 , n9705 , n9708 );
buf ( n9710 , n4472 );
buf ( n9711 , n5496 );
xor ( n9712 , n9710 , n9711 );
or ( n9713 , n9709 , n9712 );
buf ( n9714 , n4473 );
buf ( n9715 , n5497 );
xor ( n9716 , n9714 , n9715 );
or ( n9717 , n9713 , n9716 );
buf ( n9718 , n4474 );
buf ( n9719 , n5498 );
xor ( n9720 , n9718 , n9719 );
or ( n9721 , n9717 , n9720 );
buf ( n9722 , n4475 );
buf ( n9723 , n5499 );
xor ( n9724 , n9722 , n9723 );
or ( n9725 , n9721 , n9724 );
buf ( n9726 , n4476 );
buf ( n9727 , n5500 );
xor ( n9728 , n9726 , n9727 );
or ( n9729 , n9725 , n9728 );
buf ( n9730 , n4477 );
buf ( n9731 , n5501 );
xor ( n9732 , n9730 , n9731 );
or ( n9733 , n9729 , n9732 );
buf ( n9734 , n4478 );
buf ( n9735 , n5502 );
xor ( n9736 , n9734 , n9735 );
or ( n9737 , n9733 , n9736 );
buf ( n9738 , n4479 );
buf ( n9739 , n5503 );
xor ( n9740 , n9738 , n9739 );
or ( n9741 , n9737 , n9740 );
buf ( n9742 , n4480 );
buf ( n9743 , n5504 );
xor ( n9744 , n9742 , n9743 );
or ( n9745 , n9741 , n9744 );
buf ( n9746 , n4481 );
buf ( n9747 , n5505 );
xor ( n9748 , n9746 , n9747 );
or ( n9749 , n9745 , n9748 );
buf ( n9750 , n4482 );
buf ( n9751 , n5506 );
xor ( n9752 , n9750 , n9751 );
or ( n9753 , n9749 , n9752 );
buf ( n9754 , n4483 );
buf ( n9755 , n5507 );
xor ( n9756 , n9754 , n9755 );
or ( n9757 , n9753 , n9756 );
buf ( n9758 , n4484 );
buf ( n9759 , n5508 );
xor ( n9760 , n9758 , n9759 );
or ( n9761 , n9757 , n9760 );
buf ( n9762 , n4485 );
buf ( n9763 , n5509 );
xor ( n9764 , n9762 , n9763 );
or ( n9765 , n9761 , n9764 );
buf ( n9766 , n4486 );
buf ( n9767 , n5510 );
xor ( n9768 , n9766 , n9767 );
or ( n9769 , n9765 , n9768 );
buf ( n9770 , n4487 );
buf ( n9771 , n5511 );
xor ( n9772 , n9770 , n9771 );
or ( n9773 , n9769 , n9772 );
buf ( n9774 , n4488 );
buf ( n9775 , n5512 );
xor ( n9776 , n9774 , n9775 );
or ( n9777 , n9773 , n9776 );
buf ( n9778 , n4489 );
buf ( n9779 , n5513 );
xor ( n9780 , n9778 , n9779 );
or ( n9781 , n9777 , n9780 );
buf ( n9782 , n4490 );
buf ( n9783 , n5514 );
xor ( n9784 , n9782 , n9783 );
or ( n9785 , n9781 , n9784 );
buf ( n9786 , n4491 );
buf ( n9787 , n5515 );
xor ( n9788 , n9786 , n9787 );
or ( n9789 , n9785 , n9788 );
buf ( n9790 , n4492 );
buf ( n9791 , n5516 );
xor ( n9792 , n9790 , n9791 );
or ( n9793 , n9789 , n9792 );
buf ( n9794 , n4493 );
buf ( n9795 , n5517 );
xor ( n9796 , n9794 , n9795 );
or ( n9797 , n9793 , n9796 );
buf ( n9798 , n4494 );
buf ( n9799 , n5518 );
xor ( n9800 , n9798 , n9799 );
or ( n9801 , n9797 , n9800 );
buf ( n9802 , n4495 );
buf ( n9803 , n5519 );
xor ( n9804 , n9802 , n9803 );
or ( n9805 , n9801 , n9804 );
buf ( n9806 , n4496 );
buf ( n9807 , n5520 );
xor ( n9808 , n9806 , n9807 );
or ( n9809 , n9805 , n9808 );
buf ( n9810 , n4497 );
buf ( n9811 , n5521 );
xor ( n9812 , n9810 , n9811 );
or ( n9813 , n9809 , n9812 );
buf ( n9814 , n4498 );
buf ( n9815 , n5522 );
xor ( n9816 , n9814 , n9815 );
or ( n9817 , n9813 , n9816 );
buf ( n9818 , n4499 );
buf ( n9819 , n5523 );
xor ( n9820 , n9818 , n9819 );
or ( n9821 , n9817 , n9820 );
buf ( n9822 , n4500 );
buf ( n9823 , n5524 );
xor ( n9824 , n9822 , n9823 );
or ( n9825 , n9821 , n9824 );
buf ( n9826 , n4501 );
buf ( n9827 , n5525 );
xor ( n9828 , n9826 , n9827 );
or ( n9829 , n9825 , n9828 );
buf ( n9830 , n4502 );
buf ( n9831 , n5526 );
xor ( n9832 , n9830 , n9831 );
or ( n9833 , n9829 , n9832 );
buf ( n9834 , n4503 );
buf ( n9835 , n5527 );
xor ( n9836 , n9834 , n9835 );
or ( n9837 , n9833 , n9836 );
buf ( n9838 , n4504 );
buf ( n9839 , n5528 );
xor ( n9840 , n9838 , n9839 );
or ( n9841 , n9837 , n9840 );
buf ( n9842 , n4505 );
buf ( n9843 , n5529 );
xor ( n9844 , n9842 , n9843 );
or ( n9845 , n9841 , n9844 );
buf ( n9846 , n4506 );
buf ( n9847 , n5530 );
xor ( n9848 , n9846 , n9847 );
or ( n9849 , n9845 , n9848 );
buf ( n9850 , n4507 );
buf ( n9851 , n5531 );
xor ( n9852 , n9850 , n9851 );
or ( n9853 , n9849 , n9852 );
buf ( n9854 , n4508 );
buf ( n9855 , n5532 );
xor ( n9856 , n9854 , n9855 );
or ( n9857 , n9853 , n9856 );
buf ( n9858 , n4509 );
buf ( n9859 , n5533 );
xor ( n9860 , n9858 , n9859 );
or ( n9861 , n9857 , n9860 );
buf ( n9862 , n4510 );
buf ( n9863 , n5534 );
xor ( n9864 , n9862 , n9863 );
or ( n9865 , n9861 , n9864 );
buf ( n9866 , n4511 );
buf ( n9867 , n5535 );
xor ( n9868 , n9866 , n9867 );
or ( n9869 , n9865 , n9868 );
buf ( n9870 , n4512 );
buf ( n9871 , n5536 );
xor ( n9872 , n9870 , n9871 );
or ( n9873 , n9869 , n9872 );
buf ( n9874 , n4513 );
buf ( n9875 , n5537 );
xor ( n9876 , n9874 , n9875 );
or ( n9877 , n9873 , n9876 );
buf ( n9878 , n4514 );
buf ( n9879 , n5538 );
xor ( n9880 , n9878 , n9879 );
or ( n9881 , n9877 , n9880 );
buf ( n9882 , n4515 );
buf ( n9883 , n5539 );
xor ( n9884 , n9882 , n9883 );
or ( n9885 , n9881 , n9884 );
buf ( n9886 , n4516 );
buf ( n9887 , n5540 );
xor ( n9888 , n9886 , n9887 );
or ( n9889 , n9885 , n9888 );
buf ( n9890 , n4517 );
buf ( n9891 , n5541 );
xor ( n9892 , n9890 , n9891 );
or ( n9893 , n9889 , n9892 );
buf ( n9894 , n4518 );
buf ( n9895 , n5542 );
xor ( n9896 , n9894 , n9895 );
or ( n9897 , n9893 , n9896 );
buf ( n9898 , n4519 );
buf ( n9899 , n5543 );
xor ( n9900 , n9898 , n9899 );
or ( n9901 , n9897 , n9900 );
buf ( n9902 , n4520 );
buf ( n9903 , n5544 );
xor ( n9904 , n9902 , n9903 );
or ( n9905 , n9901 , n9904 );
buf ( n9906 , n4521 );
buf ( n9907 , n5545 );
xor ( n9908 , n9906 , n9907 );
or ( n9909 , n9905 , n9908 );
buf ( n9910 , n4522 );
buf ( n9911 , n5546 );
xor ( n9912 , n9910 , n9911 );
or ( n9913 , n9909 , n9912 );
buf ( n9914 , n4523 );
buf ( n9915 , n5547 );
xor ( n9916 , n9914 , n9915 );
or ( n9917 , n9913 , n9916 );
buf ( n9918 , n4524 );
buf ( n9919 , n5548 );
xor ( n9920 , n9918 , n9919 );
or ( n9921 , n9917 , n9920 );
buf ( n9922 , n4525 );
buf ( n9923 , n5549 );
xor ( n9924 , n9922 , n9923 );
or ( n9925 , n9921 , n9924 );
buf ( n9926 , n4526 );
buf ( n9927 , n5550 );
xor ( n9928 , n9926 , n9927 );
or ( n9929 , n9925 , n9928 );
buf ( n9930 , n4527 );
buf ( n9931 , n5551 );
xor ( n9932 , n9930 , n9931 );
or ( n9933 , n9929 , n9932 );
buf ( n9934 , n4528 );
buf ( n9935 , n5552 );
xor ( n9936 , n9934 , n9935 );
or ( n9937 , n9933 , n9936 );
buf ( n9938 , n4529 );
buf ( n9939 , n5553 );
xor ( n9940 , n9938 , n9939 );
or ( n9941 , n9937 , n9940 );
buf ( n9942 , n4530 );
buf ( n9943 , n5554 );
xor ( n9944 , n9942 , n9943 );
or ( n9945 , n9941 , n9944 );
buf ( n9946 , n4531 );
buf ( n9947 , n5555 );
xor ( n9948 , n9946 , n9947 );
or ( n9949 , n9945 , n9948 );
buf ( n9950 , n4532 );
buf ( n9951 , n5556 );
xor ( n9952 , n9950 , n9951 );
or ( n9953 , n9949 , n9952 );
buf ( n9954 , n4533 );
buf ( n9955 , n5557 );
xor ( n9956 , n9954 , n9955 );
or ( n9957 , n9953 , n9956 );
buf ( n9958 , n4534 );
buf ( n9959 , n5558 );
xor ( n9960 , n9958 , n9959 );
or ( n9961 , n9957 , n9960 );
buf ( n9962 , n4535 );
buf ( n9963 , n5559 );
xor ( n9964 , n9962 , n9963 );
or ( n9965 , n9961 , n9964 );
buf ( n9966 , n4536 );
buf ( n9967 , n5560 );
xor ( n9968 , n9966 , n9967 );
or ( n9969 , n9965 , n9968 );
buf ( n9970 , n4537 );
buf ( n9971 , n5561 );
xor ( n9972 , n9970 , n9971 );
or ( n9973 , n9969 , n9972 );
buf ( n9974 , n4538 );
buf ( n9975 , n5562 );
xor ( n9976 , n9974 , n9975 );
or ( n9977 , n9973 , n9976 );
buf ( n9978 , n4539 );
buf ( n9979 , n5563 );
xor ( n9980 , n9978 , n9979 );
or ( n9981 , n9977 , n9980 );
buf ( n9982 , n4540 );
buf ( n9983 , n5564 );
xor ( n9984 , n9982 , n9983 );
or ( n9985 , n9981 , n9984 );
buf ( n9986 , n4541 );
buf ( n9987 , n5565 );
xor ( n9988 , n9986 , n9987 );
or ( n9989 , n9985 , n9988 );
buf ( n9990 , n4542 );
buf ( n9991 , n5566 );
xor ( n9992 , n9990 , n9991 );
or ( n9993 , n9989 , n9992 );
buf ( n9994 , n4543 );
buf ( n9995 , n5567 );
xor ( n9996 , n9994 , n9995 );
or ( n9997 , n9993 , n9996 );
buf ( n9998 , n4544 );
buf ( n9999 , n5568 );
xor ( n10000 , n9998 , n9999 );
or ( n10001 , n9997 , n10000 );
buf ( n10002 , n4545 );
buf ( n10003 , n5569 );
xor ( n10004 , n10002 , n10003 );
or ( n10005 , n10001 , n10004 );
buf ( n10006 , n4546 );
buf ( n10007 , n5570 );
xor ( n10008 , n10006 , n10007 );
or ( n10009 , n10005 , n10008 );
buf ( n10010 , n4547 );
buf ( n10011 , n5571 );
xor ( n10012 , n10010 , n10011 );
or ( n10013 , n10009 , n10012 );
buf ( n10014 , n4548 );
buf ( n10015 , n5572 );
xor ( n10016 , n10014 , n10015 );
or ( n10017 , n10013 , n10016 );
buf ( n10018 , n4549 );
buf ( n10019 , n5573 );
xor ( n10020 , n10018 , n10019 );
or ( n10021 , n10017 , n10020 );
buf ( n10022 , n4550 );
buf ( n10023 , n5574 );
xor ( n10024 , n10022 , n10023 );
or ( n10025 , n10021 , n10024 );
buf ( n10026 , n4551 );
buf ( n10027 , n5575 );
xor ( n10028 , n10026 , n10027 );
or ( n10029 , n10025 , n10028 );
buf ( n10030 , n4552 );
buf ( n10031 , n5576 );
xor ( n10032 , n10030 , n10031 );
or ( n10033 , n10029 , n10032 );
buf ( n10034 , n4553 );
buf ( n10035 , n5577 );
xor ( n10036 , n10034 , n10035 );
or ( n10037 , n10033 , n10036 );
buf ( n10038 , n4554 );
buf ( n10039 , n5578 );
xor ( n10040 , n10038 , n10039 );
or ( n10041 , n10037 , n10040 );
buf ( n10042 , n4555 );
buf ( n10043 , n5579 );
xor ( n10044 , n10042 , n10043 );
or ( n10045 , n10041 , n10044 );
buf ( n10046 , n4556 );
buf ( n10047 , n5580 );
xor ( n10048 , n10046 , n10047 );
or ( n10049 , n10045 , n10048 );
buf ( n10050 , n4557 );
buf ( n10051 , n5581 );
xor ( n10052 , n10050 , n10051 );
or ( n10053 , n10049 , n10052 );
buf ( n10054 , n4558 );
buf ( n10055 , n5582 );
xor ( n10056 , n10054 , n10055 );
or ( n10057 , n10053 , n10056 );
buf ( n10058 , n4559 );
buf ( n10059 , n5583 );
xor ( n10060 , n10058 , n10059 );
or ( n10061 , n10057 , n10060 );
buf ( n10062 , n4560 );
buf ( n10063 , n5584 );
xor ( n10064 , n10062 , n10063 );
or ( n10065 , n10061 , n10064 );
buf ( n10066 , n4561 );
buf ( n10067 , n5585 );
xor ( n10068 , n10066 , n10067 );
or ( n10069 , n10065 , n10068 );
buf ( n10070 , n4562 );
buf ( n10071 , n5586 );
xor ( n10072 , n10070 , n10071 );
or ( n10073 , n10069 , n10072 );
buf ( n10074 , n4563 );
buf ( n10075 , n5587 );
xor ( n10076 , n10074 , n10075 );
or ( n10077 , n10073 , n10076 );
buf ( n10078 , n4564 );
buf ( n10079 , n5588 );
xor ( n10080 , n10078 , n10079 );
or ( n10081 , n10077 , n10080 );
buf ( n10082 , n4565 );
buf ( n10083 , n5589 );
xor ( n10084 , n10082 , n10083 );
or ( n10085 , n10081 , n10084 );
buf ( n10086 , n4566 );
buf ( n10087 , n5590 );
xor ( n10088 , n10086 , n10087 );
or ( n10089 , n10085 , n10088 );
buf ( n10090 , n4567 );
buf ( n10091 , n5591 );
xor ( n10092 , n10090 , n10091 );
or ( n10093 , n10089 , n10092 );
buf ( n10094 , n4568 );
buf ( n10095 , n5592 );
xor ( n10096 , n10094 , n10095 );
or ( n10097 , n10093 , n10096 );
buf ( n10098 , n4569 );
buf ( n10099 , n5593 );
xor ( n10100 , n10098 , n10099 );
or ( n10101 , n10097 , n10100 );
buf ( n10102 , n4570 );
buf ( n10103 , n5594 );
xor ( n10104 , n10102 , n10103 );
or ( n10105 , n10101 , n10104 );
buf ( n10106 , n4571 );
buf ( n10107 , n5595 );
xor ( n10108 , n10106 , n10107 );
or ( n10109 , n10105 , n10108 );
buf ( n10110 , n4572 );
buf ( n10111 , n5596 );
xor ( n10112 , n10110 , n10111 );
or ( n10113 , n10109 , n10112 );
buf ( n10114 , n4573 );
buf ( n10115 , n5597 );
xor ( n10116 , n10114 , n10115 );
or ( n10117 , n10113 , n10116 );
buf ( n10118 , n4574 );
buf ( n10119 , n5598 );
xor ( n10120 , n10118 , n10119 );
or ( n10121 , n10117 , n10120 );
buf ( n10122 , n4575 );
buf ( n10123 , n5599 );
xor ( n10124 , n10122 , n10123 );
or ( n10125 , n10121 , n10124 );
buf ( n10126 , n4576 );
buf ( n10127 , n5600 );
xor ( n10128 , n10126 , n10127 );
or ( n10129 , n10125 , n10128 );
buf ( n10130 , n4577 );
buf ( n10131 , n5601 );
xor ( n10132 , n10130 , n10131 );
or ( n10133 , n10129 , n10132 );
buf ( n10134 , n4578 );
buf ( n10135 , n5602 );
xor ( n10136 , n10134 , n10135 );
or ( n10137 , n10133 , n10136 );
buf ( n10138 , n4579 );
buf ( n10139 , n5603 );
xor ( n10140 , n10138 , n10139 );
or ( n10141 , n10137 , n10140 );
buf ( n10142 , n4580 );
buf ( n10143 , n5604 );
xor ( n10144 , n10142 , n10143 );
or ( n10145 , n10141 , n10144 );
buf ( n10146 , n4581 );
buf ( n10147 , n5605 );
xor ( n10148 , n10146 , n10147 );
or ( n10149 , n10145 , n10148 );
buf ( n10150 , n4582 );
buf ( n10151 , n5606 );
xor ( n10152 , n10150 , n10151 );
or ( n10153 , n10149 , n10152 );
buf ( n10154 , n4583 );
buf ( n10155 , n5607 );
xor ( n10156 , n10154 , n10155 );
or ( n10157 , n10153 , n10156 );
buf ( n10158 , n4584 );
buf ( n10159 , n5608 );
xor ( n10160 , n10158 , n10159 );
or ( n10161 , n10157 , n10160 );
buf ( n10162 , n4585 );
buf ( n10163 , n5609 );
xor ( n10164 , n10162 , n10163 );
or ( n10165 , n10161 , n10164 );
buf ( n10166 , n4586 );
buf ( n10167 , n5610 );
xor ( n10168 , n10166 , n10167 );
or ( n10169 , n10165 , n10168 );
buf ( n10170 , n4587 );
buf ( n10171 , n5611 );
xor ( n10172 , n10170 , n10171 );
or ( n10173 , n10169 , n10172 );
buf ( n10174 , n4588 );
buf ( n10175 , n5612 );
xor ( n10176 , n10174 , n10175 );
or ( n10177 , n10173 , n10176 );
buf ( n10178 , n4589 );
buf ( n10179 , n5613 );
xor ( n10180 , n10178 , n10179 );
or ( n10181 , n10177 , n10180 );
buf ( n10182 , n4590 );
buf ( n10183 , n5614 );
xor ( n10184 , n10182 , n10183 );
or ( n10185 , n10181 , n10184 );
buf ( n10186 , n4591 );
buf ( n10187 , n5615 );
xor ( n10188 , n10186 , n10187 );
or ( n10189 , n10185 , n10188 );
buf ( n10190 , n4592 );
buf ( n10191 , n5616 );
xor ( n10192 , n10190 , n10191 );
or ( n10193 , n10189 , n10192 );
buf ( n10194 , n4593 );
buf ( n10195 , n5617 );
xor ( n10196 , n10194 , n10195 );
or ( n10197 , n10193 , n10196 );
buf ( n10198 , n4594 );
buf ( n10199 , n5618 );
xor ( n10200 , n10198 , n10199 );
or ( n10201 , n10197 , n10200 );
buf ( n10202 , n4595 );
buf ( n10203 , n5619 );
xor ( n10204 , n10202 , n10203 );
or ( n10205 , n10201 , n10204 );
buf ( n10206 , n4596 );
buf ( n10207 , n5620 );
xor ( n10208 , n10206 , n10207 );
or ( n10209 , n10205 , n10208 );
buf ( n10210 , n4597 );
buf ( n10211 , n5621 );
xor ( n10212 , n10210 , n10211 );
or ( n10213 , n10209 , n10212 );
buf ( n10214 , n4598 );
buf ( n10215 , n5622 );
xor ( n10216 , n10214 , n10215 );
or ( n10217 , n10213 , n10216 );
buf ( n10218 , n4599 );
buf ( n10219 , n5623 );
xor ( n10220 , n10218 , n10219 );
or ( n10221 , n10217 , n10220 );
buf ( n10222 , n4600 );
buf ( n10223 , n5624 );
xor ( n10224 , n10222 , n10223 );
or ( n10225 , n10221 , n10224 );
buf ( n10226 , n4601 );
buf ( n10227 , n5625 );
xor ( n10228 , n10226 , n10227 );
or ( n10229 , n10225 , n10228 );
buf ( n10230 , n4602 );
buf ( n10231 , n5626 );
xor ( n10232 , n10230 , n10231 );
or ( n10233 , n10229 , n10232 );
buf ( n10234 , n4603 );
buf ( n10235 , n5627 );
xor ( n10236 , n10234 , n10235 );
or ( n10237 , n10233 , n10236 );
buf ( n10238 , n4604 );
buf ( n10239 , n5628 );
xor ( n10240 , n10238 , n10239 );
or ( n10241 , n10237 , n10240 );
buf ( n10242 , n4605 );
buf ( n10243 , n5629 );
xor ( n10244 , n10242 , n10243 );
or ( n10245 , n10241 , n10244 );
buf ( n10246 , n4606 );
buf ( n10247 , n5630 );
xor ( n10248 , n10246 , n10247 );
or ( n10249 , n10245 , n10248 );
buf ( n10250 , n4607 );
buf ( n10251 , n5631 );
xor ( n10252 , n10250 , n10251 );
or ( n10253 , n10249 , n10252 );
buf ( n10254 , n4608 );
buf ( n10255 , n5632 );
xor ( n10256 , n10254 , n10255 );
or ( n10257 , n10253 , n10256 );
buf ( n10258 , n4609 );
buf ( n10259 , n5633 );
xor ( n10260 , n10258 , n10259 );
or ( n10261 , n10257 , n10260 );
buf ( n10262 , n4610 );
buf ( n10263 , n5634 );
xor ( n10264 , n10262 , n10263 );
or ( n10265 , n10261 , n10264 );
buf ( n10266 , n4611 );
buf ( n10267 , n5635 );
xor ( n10268 , n10266 , n10267 );
or ( n10269 , n10265 , n10268 );
buf ( n10270 , n4612 );
buf ( n10271 , n5636 );
xor ( n10272 , n10270 , n10271 );
or ( n10273 , n10269 , n10272 );
buf ( n10274 , n4613 );
buf ( n10275 , n5637 );
xor ( n10276 , n10274 , n10275 );
or ( n10277 , n10273 , n10276 );
buf ( n10278 , n4614 );
buf ( n10279 , n5638 );
xor ( n10280 , n10278 , n10279 );
or ( n10281 , n10277 , n10280 );
buf ( n10282 , n4615 );
buf ( n10283 , n5639 );
xor ( n10284 , n10282 , n10283 );
or ( n10285 , n10281 , n10284 );
buf ( n10286 , n4616 );
buf ( n10287 , n5640 );
xor ( n10288 , n10286 , n10287 );
or ( n10289 , n10285 , n10288 );
buf ( n10290 , n4617 );
buf ( n10291 , n5641 );
xor ( n10292 , n10290 , n10291 );
or ( n10293 , n10289 , n10292 );
buf ( n10294 , n4618 );
buf ( n10295 , n5642 );
xor ( n10296 , n10294 , n10295 );
or ( n10297 , n10293 , n10296 );
buf ( n10298 , n4619 );
buf ( n10299 , n5643 );
xor ( n10300 , n10298 , n10299 );
or ( n10301 , n10297 , n10300 );
buf ( n10302 , n4620 );
buf ( n10303 , n5644 );
xor ( n10304 , n10302 , n10303 );
or ( n10305 , n10301 , n10304 );
buf ( n10306 , n4621 );
buf ( n10307 , n5645 );
xor ( n10308 , n10306 , n10307 );
or ( n10309 , n10305 , n10308 );
buf ( n10310 , n4622 );
buf ( n10311 , n5646 );
xor ( n10312 , n10310 , n10311 );
or ( n10313 , n10309 , n10312 );
buf ( n10314 , n4623 );
buf ( n10315 , n5647 );
xor ( n10316 , n10314 , n10315 );
or ( n10317 , n10313 , n10316 );
buf ( n10318 , n4624 );
buf ( n10319 , n5648 );
xor ( n10320 , n10318 , n10319 );
or ( n10321 , n10317 , n10320 );
buf ( n10322 , n4625 );
buf ( n10323 , n5649 );
xor ( n10324 , n10322 , n10323 );
or ( n10325 , n10321 , n10324 );
buf ( n10326 , n4626 );
buf ( n10327 , n5650 );
xor ( n10328 , n10326 , n10327 );
or ( n10329 , n10325 , n10328 );
buf ( n10330 , n4627 );
buf ( n10331 , n5651 );
xor ( n10332 , n10330 , n10331 );
or ( n10333 , n10329 , n10332 );
buf ( n10334 , n4628 );
buf ( n10335 , n5652 );
xor ( n10336 , n10334 , n10335 );
or ( n10337 , n10333 , n10336 );
buf ( n10338 , n4629 );
buf ( n10339 , n5653 );
xor ( n10340 , n10338 , n10339 );
or ( n10341 , n10337 , n10340 );
buf ( n10342 , n4630 );
buf ( n10343 , n5654 );
xor ( n10344 , n10342 , n10343 );
or ( n10345 , n10341 , n10344 );
buf ( n10346 , n4631 );
buf ( n10347 , n5655 );
xor ( n10348 , n10346 , n10347 );
or ( n10349 , n10345 , n10348 );
buf ( n10350 , n4632 );
buf ( n10351 , n5656 );
xor ( n10352 , n10350 , n10351 );
or ( n10353 , n10349 , n10352 );
buf ( n10354 , n4633 );
buf ( n10355 , n5657 );
xor ( n10356 , n10354 , n10355 );
or ( n10357 , n10353 , n10356 );
buf ( n10358 , n4634 );
buf ( n10359 , n5658 );
xor ( n10360 , n10358 , n10359 );
or ( n10361 , n10357 , n10360 );
buf ( n10362 , n4635 );
buf ( n10363 , n5659 );
xor ( n10364 , n10362 , n10363 );
or ( n10365 , n10361 , n10364 );
buf ( n10366 , n4636 );
buf ( n10367 , n5660 );
xor ( n10368 , n10366 , n10367 );
or ( n10369 , n10365 , n10368 );
buf ( n10370 , n4637 );
buf ( n10371 , n5661 );
xor ( n10372 , n10370 , n10371 );
or ( n10373 , n10369 , n10372 );
buf ( n10374 , n4638 );
buf ( n10375 , n5662 );
xor ( n10376 , n10374 , n10375 );
or ( n10377 , n10373 , n10376 );
buf ( n10378 , n4639 );
buf ( n10379 , n5663 );
xor ( n10380 , n10378 , n10379 );
or ( n10381 , n10377 , n10380 );
buf ( n10382 , n4640 );
buf ( n10383 , n5664 );
xor ( n10384 , n10382 , n10383 );
or ( n10385 , n10381 , n10384 );
buf ( n10386 , n4641 );
buf ( n10387 , n5665 );
xor ( n10388 , n10386 , n10387 );
or ( n10389 , n10385 , n10388 );
buf ( n10390 , n4642 );
buf ( n10391 , n5666 );
xor ( n10392 , n10390 , n10391 );
or ( n10393 , n10389 , n10392 );
buf ( n10394 , n4643 );
buf ( n10395 , n5667 );
xor ( n10396 , n10394 , n10395 );
or ( n10397 , n10393 , n10396 );
buf ( n10398 , n4644 );
buf ( n10399 , n5668 );
xor ( n10400 , n10398 , n10399 );
or ( n10401 , n10397 , n10400 );
buf ( n10402 , n4645 );
buf ( n10403 , n5669 );
xor ( n10404 , n10402 , n10403 );
or ( n10405 , n10401 , n10404 );
buf ( n10406 , n4646 );
buf ( n10407 , n5670 );
xor ( n10408 , n10406 , n10407 );
or ( n10409 , n10405 , n10408 );
buf ( n10410 , n4647 );
buf ( n10411 , n5671 );
xor ( n10412 , n10410 , n10411 );
or ( n10413 , n10409 , n10412 );
buf ( n10414 , n4648 );
buf ( n10415 , n5672 );
xor ( n10416 , n10414 , n10415 );
or ( n10417 , n10413 , n10416 );
buf ( n10418 , n4649 );
buf ( n10419 , n5673 );
xor ( n10420 , n10418 , n10419 );
or ( n10421 , n10417 , n10420 );
buf ( n10422 , n4650 );
buf ( n10423 , n5674 );
xor ( n10424 , n10422 , n10423 );
or ( n10425 , n10421 , n10424 );
buf ( n10426 , n4651 );
buf ( n10427 , n5675 );
xor ( n10428 , n10426 , n10427 );
or ( n10429 , n10425 , n10428 );
buf ( n10430 , n4652 );
buf ( n10431 , n5676 );
xor ( n10432 , n10430 , n10431 );
or ( n10433 , n10429 , n10432 );
buf ( n10434 , n4653 );
buf ( n10435 , n5677 );
xor ( n10436 , n10434 , n10435 );
or ( n10437 , n10433 , n10436 );
buf ( n10438 , n4654 );
buf ( n10439 , n5678 );
xor ( n10440 , n10438 , n10439 );
or ( n10441 , n10437 , n10440 );
buf ( n10442 , n4655 );
buf ( n10443 , n5679 );
xor ( n10444 , n10442 , n10443 );
or ( n10445 , n10441 , n10444 );
buf ( n10446 , n4656 );
buf ( n10447 , n5680 );
xor ( n10448 , n10446 , n10447 );
or ( n10449 , n10445 , n10448 );
buf ( n10450 , n4657 );
buf ( n10451 , n5681 );
xor ( n10452 , n10450 , n10451 );
or ( n10453 , n10449 , n10452 );
buf ( n10454 , n4658 );
buf ( n10455 , n5682 );
xor ( n10456 , n10454 , n10455 );
or ( n10457 , n10453 , n10456 );
buf ( n10458 , n4659 );
buf ( n10459 , n5683 );
xor ( n10460 , n10458 , n10459 );
or ( n10461 , n10457 , n10460 );
buf ( n10462 , n4660 );
buf ( n10463 , n5684 );
xor ( n10464 , n10462 , n10463 );
or ( n10465 , n10461 , n10464 );
buf ( n10466 , n4661 );
buf ( n10467 , n5685 );
xor ( n10468 , n10466 , n10467 );
or ( n10469 , n10465 , n10468 );
buf ( n10470 , n4662 );
buf ( n10471 , n5686 );
xor ( n10472 , n10470 , n10471 );
or ( n10473 , n10469 , n10472 );
buf ( n10474 , n4663 );
buf ( n10475 , n5687 );
xor ( n10476 , n10474 , n10475 );
or ( n10477 , n10473 , n10476 );
buf ( n10478 , n4664 );
buf ( n10479 , n5688 );
xor ( n10480 , n10478 , n10479 );
or ( n10481 , n10477 , n10480 );
buf ( n10482 , n4665 );
buf ( n10483 , n5689 );
xor ( n10484 , n10482 , n10483 );
or ( n10485 , n10481 , n10484 );
buf ( n10486 , n4666 );
buf ( n10487 , n5690 );
xor ( n10488 , n10486 , n10487 );
or ( n10489 , n10485 , n10488 );
buf ( n10490 , n4667 );
buf ( n10491 , n5691 );
xor ( n10492 , n10490 , n10491 );
or ( n10493 , n10489 , n10492 );
buf ( n10494 , n4668 );
buf ( n10495 , n5692 );
xor ( n10496 , n10494 , n10495 );
or ( n10497 , n10493 , n10496 );
buf ( n10498 , n4669 );
buf ( n10499 , n5693 );
xor ( n10500 , n10498 , n10499 );
or ( n10501 , n10497 , n10500 );
buf ( n10502 , n4670 );
buf ( n10503 , n5694 );
xor ( n10504 , n10502 , n10503 );
or ( n10505 , n10501 , n10504 );
buf ( n10506 , n4671 );
buf ( n10507 , n5695 );
xor ( n10508 , n10506 , n10507 );
or ( n10509 , n10505 , n10508 );
buf ( n10510 , n4672 );
buf ( n10511 , n5696 );
xor ( n10512 , n10510 , n10511 );
or ( n10513 , n10509 , n10512 );
buf ( n10514 , n4673 );
buf ( n10515 , n5697 );
xor ( n10516 , n10514 , n10515 );
or ( n10517 , n10513 , n10516 );
buf ( n10518 , n4674 );
buf ( n10519 , n5698 );
xor ( n10520 , n10518 , n10519 );
or ( n10521 , n10517 , n10520 );
buf ( n10522 , n4675 );
buf ( n10523 , n5699 );
xor ( n10524 , n10522 , n10523 );
or ( n10525 , n10521 , n10524 );
buf ( n10526 , n4676 );
buf ( n10527 , n5700 );
xor ( n10528 , n10526 , n10527 );
or ( n10529 , n10525 , n10528 );
buf ( n10530 , n4677 );
buf ( n10531 , n5701 );
xor ( n10532 , n10530 , n10531 );
or ( n10533 , n10529 , n10532 );
buf ( n10534 , n4678 );
buf ( n10535 , n5702 );
xor ( n10536 , n10534 , n10535 );
or ( n10537 , n10533 , n10536 );
buf ( n10538 , n4679 );
buf ( n10539 , n5703 );
xor ( n10540 , n10538 , n10539 );
or ( n10541 , n10537 , n10540 );
buf ( n10542 , n4680 );
buf ( n10543 , n5704 );
xor ( n10544 , n10542 , n10543 );
or ( n10545 , n10541 , n10544 );
buf ( n10546 , n4681 );
buf ( n10547 , n5705 );
xor ( n10548 , n10546 , n10547 );
or ( n10549 , n10545 , n10548 );
buf ( n10550 , n4682 );
buf ( n10551 , n5706 );
xor ( n10552 , n10550 , n10551 );
or ( n10553 , n10549 , n10552 );
buf ( n10554 , n4683 );
buf ( n10555 , n5707 );
xor ( n10556 , n10554 , n10555 );
or ( n10557 , n10553 , n10556 );
buf ( n10558 , n4684 );
buf ( n10559 , n5708 );
xor ( n10560 , n10558 , n10559 );
or ( n10561 , n10557 , n10560 );
buf ( n10562 , n4685 );
buf ( n10563 , n5709 );
xor ( n10564 , n10562 , n10563 );
or ( n10565 , n10561 , n10564 );
buf ( n10566 , n4686 );
buf ( n10567 , n5710 );
xor ( n10568 , n10566 , n10567 );
or ( n10569 , n10565 , n10568 );
buf ( n10570 , n4687 );
buf ( n10571 , n5711 );
xor ( n10572 , n10570 , n10571 );
or ( n10573 , n10569 , n10572 );
buf ( n10574 , n4688 );
buf ( n10575 , n5712 );
xor ( n10576 , n10574 , n10575 );
or ( n10577 , n10573 , n10576 );
buf ( n10578 , n4689 );
buf ( n10579 , n5713 );
xor ( n10580 , n10578 , n10579 );
or ( n10581 , n10577 , n10580 );
buf ( n10582 , n4690 );
buf ( n10583 , n5714 );
xor ( n10584 , n10582 , n10583 );
or ( n10585 , n10581 , n10584 );
buf ( n10586 , n4691 );
buf ( n10587 , n5715 );
xor ( n10588 , n10586 , n10587 );
or ( n10589 , n10585 , n10588 );
buf ( n10590 , n4692 );
buf ( n10591 , n5716 );
xor ( n10592 , n10590 , n10591 );
or ( n10593 , n10589 , n10592 );
buf ( n10594 , n4693 );
buf ( n10595 , n5717 );
xor ( n10596 , n10594 , n10595 );
or ( n10597 , n10593 , n10596 );
buf ( n10598 , n4694 );
buf ( n10599 , n5718 );
xor ( n10600 , n10598 , n10599 );
or ( n10601 , n10597 , n10600 );
buf ( n10602 , n4695 );
buf ( n10603 , n5719 );
xor ( n10604 , n10602 , n10603 );
or ( n10605 , n10601 , n10604 );
buf ( n10606 , n4696 );
buf ( n10607 , n5720 );
xor ( n10608 , n10606 , n10607 );
or ( n10609 , n10605 , n10608 );
buf ( n10610 , n4697 );
buf ( n10611 , n5721 );
xor ( n10612 , n10610 , n10611 );
or ( n10613 , n10609 , n10612 );
buf ( n10614 , n4698 );
buf ( n10615 , n5722 );
xor ( n10616 , n10614 , n10615 );
or ( n10617 , n10613 , n10616 );
buf ( n10618 , n4699 );
buf ( n10619 , n5723 );
xor ( n10620 , n10618 , n10619 );
or ( n10621 , n10617 , n10620 );
buf ( n10622 , n4700 );
buf ( n10623 , n5724 );
xor ( n10624 , n10622 , n10623 );
or ( n10625 , n10621 , n10624 );
buf ( n10626 , n4701 );
buf ( n10627 , n5725 );
xor ( n10628 , n10626 , n10627 );
or ( n10629 , n10625 , n10628 );
buf ( n10630 , n4702 );
buf ( n10631 , n5726 );
xor ( n10632 , n10630 , n10631 );
or ( n10633 , n10629 , n10632 );
buf ( n10634 , n4703 );
buf ( n10635 , n5727 );
xor ( n10636 , n10634 , n10635 );
or ( n10637 , n10633 , n10636 );
buf ( n10638 , n4704 );
buf ( n10639 , n5728 );
xor ( n10640 , n10638 , n10639 );
or ( n10641 , n10637 , n10640 );
buf ( n10642 , n4705 );
buf ( n10643 , n5729 );
xor ( n10644 , n10642 , n10643 );
or ( n10645 , n10641 , n10644 );
buf ( n10646 , n4706 );
buf ( n10647 , n5730 );
xor ( n10648 , n10646 , n10647 );
or ( n10649 , n10645 , n10648 );
buf ( n10650 , n4707 );
buf ( n10651 , n5731 );
xor ( n10652 , n10650 , n10651 );
or ( n10653 , n10649 , n10652 );
buf ( n10654 , n4708 );
buf ( n10655 , n5732 );
xor ( n10656 , n10654 , n10655 );
or ( n10657 , n10653 , n10656 );
buf ( n10658 , n4709 );
buf ( n10659 , n5733 );
xor ( n10660 , n10658 , n10659 );
or ( n10661 , n10657 , n10660 );
buf ( n10662 , n4710 );
buf ( n10663 , n5734 );
xor ( n10664 , n10662 , n10663 );
or ( n10665 , n10661 , n10664 );
buf ( n10666 , n4711 );
buf ( n10667 , n5735 );
xor ( n10668 , n10666 , n10667 );
or ( n10669 , n10665 , n10668 );
buf ( n10670 , n4712 );
buf ( n10671 , n5736 );
xor ( n10672 , n10670 , n10671 );
or ( n10673 , n10669 , n10672 );
buf ( n10674 , n4713 );
buf ( n10675 , n5737 );
xor ( n10676 , n10674 , n10675 );
or ( n10677 , n10673 , n10676 );
buf ( n10678 , n4714 );
buf ( n10679 , n5738 );
xor ( n10680 , n10678 , n10679 );
or ( n10681 , n10677 , n10680 );
buf ( n10682 , n4715 );
buf ( n10683 , n5739 );
xor ( n10684 , n10682 , n10683 );
or ( n10685 , n10681 , n10684 );
buf ( n10686 , n4716 );
buf ( n10687 , n5740 );
xor ( n10688 , n10686 , n10687 );
or ( n10689 , n10685 , n10688 );
buf ( n10690 , n4717 );
buf ( n10691 , n5741 );
xor ( n10692 , n10690 , n10691 );
or ( n10693 , n10689 , n10692 );
buf ( n10694 , n4718 );
buf ( n10695 , n5742 );
xor ( n10696 , n10694 , n10695 );
or ( n10697 , n10693 , n10696 );
buf ( n10698 , n4719 );
buf ( n10699 , n5743 );
xor ( n10700 , n10698 , n10699 );
or ( n10701 , n10697 , n10700 );
buf ( n10702 , n4720 );
buf ( n10703 , n5744 );
xor ( n10704 , n10702 , n10703 );
or ( n10705 , n10701 , n10704 );
buf ( n10706 , n4721 );
buf ( n10707 , n5745 );
xor ( n10708 , n10706 , n10707 );
or ( n10709 , n10705 , n10708 );
buf ( n10710 , n4722 );
buf ( n10711 , n5746 );
xor ( n10712 , n10710 , n10711 );
or ( n10713 , n10709 , n10712 );
buf ( n10714 , n4723 );
buf ( n10715 , n5747 );
xor ( n10716 , n10714 , n10715 );
or ( n10717 , n10713 , n10716 );
buf ( n10718 , n4724 );
buf ( n10719 , n5748 );
xor ( n10720 , n10718 , n10719 );
or ( n10721 , n10717 , n10720 );
buf ( n10722 , n4725 );
buf ( n10723 , n5749 );
xor ( n10724 , n10722 , n10723 );
or ( n10725 , n10721 , n10724 );
buf ( n10726 , n4726 );
buf ( n10727 , n5750 );
xor ( n10728 , n10726 , n10727 );
or ( n10729 , n10725 , n10728 );
buf ( n10730 , n4727 );
buf ( n10731 , n5751 );
xor ( n10732 , n10730 , n10731 );
or ( n10733 , n10729 , n10732 );
buf ( n10734 , n4728 );
buf ( n10735 , n5752 );
xor ( n10736 , n10734 , n10735 );
or ( n10737 , n10733 , n10736 );
buf ( n10738 , n4729 );
buf ( n10739 , n5753 );
xor ( n10740 , n10738 , n10739 );
or ( n10741 , n10737 , n10740 );
buf ( n10742 , n4730 );
buf ( n10743 , n5754 );
xor ( n10744 , n10742 , n10743 );
or ( n10745 , n10741 , n10744 );
buf ( n10746 , n4731 );
buf ( n10747 , n5755 );
xor ( n10748 , n10746 , n10747 );
or ( n10749 , n10745 , n10748 );
buf ( n10750 , n4732 );
buf ( n10751 , n5756 );
xor ( n10752 , n10750 , n10751 );
or ( n10753 , n10749 , n10752 );
buf ( n10754 , n4733 );
buf ( n10755 , n5757 );
xor ( n10756 , n10754 , n10755 );
or ( n10757 , n10753 , n10756 );
buf ( n10758 , n4734 );
buf ( n10759 , n5758 );
xor ( n10760 , n10758 , n10759 );
or ( n10761 , n10757 , n10760 );
buf ( n10762 , n4735 );
buf ( n10763 , n5759 );
xor ( n10764 , n10762 , n10763 );
or ( n10765 , n10761 , n10764 );
buf ( n10766 , n4736 );
buf ( n10767 , n5760 );
xor ( n10768 , n10766 , n10767 );
or ( n10769 , n10765 , n10768 );
buf ( n10770 , n4737 );
buf ( n10771 , n5761 );
xor ( n10772 , n10770 , n10771 );
or ( n10773 , n10769 , n10772 );
buf ( n10774 , n4738 );
buf ( n10775 , n5762 );
xor ( n10776 , n10774 , n10775 );
or ( n10777 , n10773 , n10776 );
buf ( n10778 , n4739 );
buf ( n10779 , n5763 );
xor ( n10780 , n10778 , n10779 );
or ( n10781 , n10777 , n10780 );
buf ( n10782 , n4740 );
buf ( n10783 , n5764 );
xor ( n10784 , n10782 , n10783 );
or ( n10785 , n10781 , n10784 );
buf ( n10786 , n4741 );
buf ( n10787 , n5765 );
xor ( n10788 , n10786 , n10787 );
or ( n10789 , n10785 , n10788 );
buf ( n10790 , n4742 );
buf ( n10791 , n5766 );
xor ( n10792 , n10790 , n10791 );
or ( n10793 , n10789 , n10792 );
buf ( n10794 , n4743 );
buf ( n10795 , n5767 );
xor ( n10796 , n10794 , n10795 );
or ( n10797 , n10793 , n10796 );
buf ( n10798 , n4744 );
buf ( n10799 , n5768 );
xor ( n10800 , n10798 , n10799 );
or ( n10801 , n10797 , n10800 );
buf ( n10802 , n4745 );
buf ( n10803 , n5769 );
xor ( n10804 , n10802 , n10803 );
or ( n10805 , n10801 , n10804 );
buf ( n10806 , n4746 );
buf ( n10807 , n5770 );
xor ( n10808 , n10806 , n10807 );
or ( n10809 , n10805 , n10808 );
buf ( n10810 , n4747 );
buf ( n10811 , n5771 );
xor ( n10812 , n10810 , n10811 );
or ( n10813 , n10809 , n10812 );
buf ( n10814 , n4748 );
buf ( n10815 , n5772 );
xor ( n10816 , n10814 , n10815 );
or ( n10817 , n10813 , n10816 );
buf ( n10818 , n4749 );
buf ( n10819 , n5773 );
xor ( n10820 , n10818 , n10819 );
or ( n10821 , n10817 , n10820 );
buf ( n10822 , n4750 );
buf ( n10823 , n5774 );
xor ( n10824 , n10822 , n10823 );
or ( n10825 , n10821 , n10824 );
buf ( n10826 , n4751 );
buf ( n10827 , n5775 );
xor ( n10828 , n10826 , n10827 );
or ( n10829 , n10825 , n10828 );
buf ( n10830 , n4752 );
buf ( n10831 , n5776 );
xor ( n10832 , n10830 , n10831 );
or ( n10833 , n10829 , n10832 );
buf ( n10834 , n4753 );
buf ( n10835 , n5777 );
xor ( n10836 , n10834 , n10835 );
or ( n10837 , n10833 , n10836 );
buf ( n10838 , n4754 );
buf ( n10839 , n5778 );
xor ( n10840 , n10838 , n10839 );
or ( n10841 , n10837 , n10840 );
buf ( n10842 , n4755 );
buf ( n10843 , n5779 );
xor ( n10844 , n10842 , n10843 );
or ( n10845 , n10841 , n10844 );
buf ( n10846 , n4756 );
buf ( n10847 , n5780 );
xor ( n10848 , n10846 , n10847 );
or ( n10849 , n10845 , n10848 );
buf ( n10850 , n4757 );
buf ( n10851 , n5781 );
xor ( n10852 , n10850 , n10851 );
or ( n10853 , n10849 , n10852 );
buf ( n10854 , n4758 );
buf ( n10855 , n5782 );
xor ( n10856 , n10854 , n10855 );
or ( n10857 , n10853 , n10856 );
buf ( n10858 , n4759 );
buf ( n10859 , n5783 );
xor ( n10860 , n10858 , n10859 );
or ( n10861 , n10857 , n10860 );
buf ( n10862 , n4760 );
buf ( n10863 , n5784 );
xor ( n10864 , n10862 , n10863 );
or ( n10865 , n10861 , n10864 );
buf ( n10866 , n4761 );
buf ( n10867 , n5785 );
xor ( n10868 , n10866 , n10867 );
or ( n10869 , n10865 , n10868 );
buf ( n10870 , n4762 );
buf ( n10871 , n5786 );
xor ( n10872 , n10870 , n10871 );
or ( n10873 , n10869 , n10872 );
buf ( n10874 , n4763 );
buf ( n10875 , n5787 );
xor ( n10876 , n10874 , n10875 );
or ( n10877 , n10873 , n10876 );
buf ( n10878 , n4764 );
buf ( n10879 , n5788 );
xor ( n10880 , n10878 , n10879 );
or ( n10881 , n10877 , n10880 );
buf ( n10882 , n4765 );
buf ( n10883 , n5789 );
xor ( n10884 , n10882 , n10883 );
or ( n10885 , n10881 , n10884 );
buf ( n10886 , n4766 );
buf ( n10887 , n5790 );
xor ( n10888 , n10886 , n10887 );
or ( n10889 , n10885 , n10888 );
buf ( n10890 , n4767 );
buf ( n10891 , n5791 );
xor ( n10892 , n10890 , n10891 );
or ( n10893 , n10889 , n10892 );
buf ( n10894 , n4768 );
buf ( n10895 , n5792 );
xor ( n10896 , n10894 , n10895 );
or ( n10897 , n10893 , n10896 );
buf ( n10898 , n4769 );
buf ( n10899 , n5793 );
xor ( n10900 , n10898 , n10899 );
or ( n10901 , n10897 , n10900 );
buf ( n10902 , n4770 );
buf ( n10903 , n5794 );
xor ( n10904 , n10902 , n10903 );
or ( n10905 , n10901 , n10904 );
buf ( n10906 , n4771 );
buf ( n10907 , n5795 );
xor ( n10908 , n10906 , n10907 );
or ( n10909 , n10905 , n10908 );
buf ( n10910 , n4772 );
buf ( n10911 , n5796 );
xor ( n10912 , n10910 , n10911 );
or ( n10913 , n10909 , n10912 );
buf ( n10914 , n4773 );
buf ( n10915 , n5797 );
xor ( n10916 , n10914 , n10915 );
or ( n10917 , n10913 , n10916 );
buf ( n10918 , n4774 );
buf ( n10919 , n5798 );
xor ( n10920 , n10918 , n10919 );
or ( n10921 , n10917 , n10920 );
buf ( n10922 , n4775 );
buf ( n10923 , n5799 );
xor ( n10924 , n10922 , n10923 );
or ( n10925 , n10921 , n10924 );
buf ( n10926 , n4776 );
buf ( n10927 , n5800 );
xor ( n10928 , n10926 , n10927 );
or ( n10929 , n10925 , n10928 );
buf ( n10930 , n4777 );
buf ( n10931 , n5801 );
xor ( n10932 , n10930 , n10931 );
or ( n10933 , n10929 , n10932 );
buf ( n10934 , n4778 );
buf ( n10935 , n5802 );
xor ( n10936 , n10934 , n10935 );
or ( n10937 , n10933 , n10936 );
buf ( n10938 , n4779 );
buf ( n10939 , n5803 );
xor ( n10940 , n10938 , n10939 );
or ( n10941 , n10937 , n10940 );
buf ( n10942 , n4780 );
buf ( n10943 , n5804 );
xor ( n10944 , n10942 , n10943 );
or ( n10945 , n10941 , n10944 );
buf ( n10946 , n4781 );
buf ( n10947 , n5805 );
xor ( n10948 , n10946 , n10947 );
or ( n10949 , n10945 , n10948 );
buf ( n10950 , n4782 );
buf ( n10951 , n5806 );
xor ( n10952 , n10950 , n10951 );
or ( n10953 , n10949 , n10952 );
buf ( n10954 , n4783 );
buf ( n10955 , n5807 );
xor ( n10956 , n10954 , n10955 );
or ( n10957 , n10953 , n10956 );
buf ( n10958 , n4784 );
buf ( n10959 , n5808 );
xor ( n10960 , n10958 , n10959 );
or ( n10961 , n10957 , n10960 );
buf ( n10962 , n4785 );
buf ( n10963 , n5809 );
xor ( n10964 , n10962 , n10963 );
or ( n10965 , n10961 , n10964 );
buf ( n10966 , n4786 );
buf ( n10967 , n5810 );
xor ( n10968 , n10966 , n10967 );
or ( n10969 , n10965 , n10968 );
buf ( n10970 , n4787 );
buf ( n10971 , n5811 );
xor ( n10972 , n10970 , n10971 );
or ( n10973 , n10969 , n10972 );
buf ( n10974 , n4788 );
buf ( n10975 , n5812 );
xor ( n10976 , n10974 , n10975 );
or ( n10977 , n10973 , n10976 );
buf ( n10978 , n4789 );
buf ( n10979 , n5813 );
xor ( n10980 , n10978 , n10979 );
or ( n10981 , n10977 , n10980 );
buf ( n10982 , n4790 );
buf ( n10983 , n5814 );
xor ( n10984 , n10982 , n10983 );
or ( n10985 , n10981 , n10984 );
buf ( n10986 , n4791 );
buf ( n10987 , n5815 );
xor ( n10988 , n10986 , n10987 );
or ( n10989 , n10985 , n10988 );
buf ( n10990 , n4792 );
buf ( n10991 , n5816 );
xor ( n10992 , n10990 , n10991 );
or ( n10993 , n10989 , n10992 );
buf ( n10994 , n4793 );
buf ( n10995 , n5817 );
xor ( n10996 , n10994 , n10995 );
or ( n10997 , n10993 , n10996 );
buf ( n10998 , n4794 );
buf ( n10999 , n5818 );
xor ( n11000 , n10998 , n10999 );
or ( n11001 , n10997 , n11000 );
buf ( n11002 , n4795 );
buf ( n11003 , n5819 );
xor ( n11004 , n11002 , n11003 );
or ( n11005 , n11001 , n11004 );
buf ( n11006 , n4796 );
buf ( n11007 , n5820 );
xor ( n11008 , n11006 , n11007 );
or ( n11009 , n11005 , n11008 );
buf ( n11010 , n4797 );
buf ( n11011 , n5821 );
xor ( n11012 , n11010 , n11011 );
or ( n11013 , n11009 , n11012 );
buf ( n11014 , n4798 );
buf ( n11015 , n5822 );
xor ( n11016 , n11014 , n11015 );
or ( n11017 , n11013 , n11016 );
buf ( n11018 , n4799 );
buf ( n11019 , n5823 );
xor ( n11020 , n11018 , n11019 );
or ( n11021 , n11017 , n11020 );
buf ( n11022 , n4800 );
buf ( n11023 , n5824 );
xor ( n11024 , n11022 , n11023 );
or ( n11025 , n11021 , n11024 );
buf ( n11026 , n4801 );
buf ( n11027 , n5825 );
xor ( n11028 , n11026 , n11027 );
or ( n11029 , n11025 , n11028 );
buf ( n11030 , n4802 );
buf ( n11031 , n5826 );
xor ( n11032 , n11030 , n11031 );
or ( n11033 , n11029 , n11032 );
buf ( n11034 , n4803 );
buf ( n11035 , n5827 );
xor ( n11036 , n11034 , n11035 );
or ( n11037 , n11033 , n11036 );
buf ( n11038 , n4804 );
buf ( n11039 , n5828 );
xor ( n11040 , n11038 , n11039 );
or ( n11041 , n11037 , n11040 );
buf ( n11042 , n4805 );
buf ( n11043 , n5829 );
xor ( n11044 , n11042 , n11043 );
or ( n11045 , n11041 , n11044 );
buf ( n11046 , n4806 );
buf ( n11047 , n5830 );
xor ( n11048 , n11046 , n11047 );
or ( n11049 , n11045 , n11048 );
buf ( n11050 , n4807 );
buf ( n11051 , n5831 );
xor ( n11052 , n11050 , n11051 );
or ( n11053 , n11049 , n11052 );
buf ( n11054 , n4808 );
buf ( n11055 , n5832 );
xor ( n11056 , n11054 , n11055 );
or ( n11057 , n11053 , n11056 );
buf ( n11058 , n4809 );
buf ( n11059 , n5833 );
xor ( n11060 , n11058 , n11059 );
or ( n11061 , n11057 , n11060 );
buf ( n11062 , n4810 );
buf ( n11063 , n5834 );
xor ( n11064 , n11062 , n11063 );
or ( n11065 , n11061 , n11064 );
buf ( n11066 , n4811 );
buf ( n11067 , n5835 );
xor ( n11068 , n11066 , n11067 );
or ( n11069 , n11065 , n11068 );
buf ( n11070 , n4812 );
buf ( n11071 , n5836 );
xor ( n11072 , n11070 , n11071 );
or ( n11073 , n11069 , n11072 );
buf ( n11074 , n4813 );
buf ( n11075 , n5837 );
xor ( n11076 , n11074 , n11075 );
or ( n11077 , n11073 , n11076 );
buf ( n11078 , n4814 );
buf ( n11079 , n5838 );
xor ( n11080 , n11078 , n11079 );
or ( n11081 , n11077 , n11080 );
buf ( n11082 , n4815 );
buf ( n11083 , n5839 );
xor ( n11084 , n11082 , n11083 );
or ( n11085 , n11081 , n11084 );
buf ( n11086 , n4816 );
buf ( n11087 , n5840 );
xor ( n11088 , n11086 , n11087 );
or ( n11089 , n11085 , n11088 );
buf ( n11090 , n4817 );
buf ( n11091 , n5841 );
xor ( n11092 , n11090 , n11091 );
or ( n11093 , n11089 , n11092 );
buf ( n11094 , n4818 );
buf ( n11095 , n5842 );
xor ( n11096 , n11094 , n11095 );
or ( n11097 , n11093 , n11096 );
buf ( n11098 , n4819 );
buf ( n11099 , n5843 );
xor ( n11100 , n11098 , n11099 );
or ( n11101 , n11097 , n11100 );
buf ( n11102 , n4820 );
buf ( n11103 , n5844 );
xor ( n11104 , n11102 , n11103 );
or ( n11105 , n11101 , n11104 );
buf ( n11106 , n4821 );
buf ( n11107 , n5845 );
xor ( n11108 , n11106 , n11107 );
or ( n11109 , n11105 , n11108 );
buf ( n11110 , n4822 );
buf ( n11111 , n5846 );
xor ( n11112 , n11110 , n11111 );
or ( n11113 , n11109 , n11112 );
buf ( n11114 , n4823 );
buf ( n11115 , n5847 );
xor ( n11116 , n11114 , n11115 );
or ( n11117 , n11113 , n11116 );
buf ( n11118 , n4824 );
buf ( n11119 , n5848 );
xor ( n11120 , n11118 , n11119 );
or ( n11121 , n11117 , n11120 );
buf ( n11122 , n4825 );
buf ( n11123 , n5849 );
xor ( n11124 , n11122 , n11123 );
or ( n11125 , n11121 , n11124 );
buf ( n11126 , n4826 );
buf ( n11127 , n5850 );
xor ( n11128 , n11126 , n11127 );
or ( n11129 , n11125 , n11128 );
buf ( n11130 , n4827 );
buf ( n11131 , n5851 );
xor ( n11132 , n11130 , n11131 );
or ( n11133 , n11129 , n11132 );
buf ( n11134 , n4828 );
buf ( n11135 , n5852 );
xor ( n11136 , n11134 , n11135 );
or ( n11137 , n11133 , n11136 );
buf ( n11138 , n4829 );
buf ( n11139 , n5853 );
xor ( n11140 , n11138 , n11139 );
or ( n11141 , n11137 , n11140 );
buf ( n11142 , n4830 );
buf ( n11143 , n5854 );
xor ( n11144 , n11142 , n11143 );
or ( n11145 , n11141 , n11144 );
buf ( n11146 , n4831 );
buf ( n11147 , n5855 );
xor ( n11148 , n11146 , n11147 );
or ( n11149 , n11145 , n11148 );
buf ( n11150 , n4832 );
buf ( n11151 , n5856 );
xor ( n11152 , n11150 , n11151 );
or ( n11153 , n11149 , n11152 );
buf ( n11154 , n4833 );
buf ( n11155 , n5857 );
xor ( n11156 , n11154 , n11155 );
or ( n11157 , n11153 , n11156 );
buf ( n11158 , n4834 );
buf ( n11159 , n5858 );
xor ( n11160 , n11158 , n11159 );
or ( n11161 , n11157 , n11160 );
buf ( n11162 , n4835 );
buf ( n11163 , n5859 );
xor ( n11164 , n11162 , n11163 );
or ( n11165 , n11161 , n11164 );
buf ( n11166 , n4836 );
buf ( n11167 , n5860 );
xor ( n11168 , n11166 , n11167 );
or ( n11169 , n11165 , n11168 );
buf ( n11170 , n4837 );
buf ( n11171 , n5861 );
xor ( n11172 , n11170 , n11171 );
or ( n11173 , n11169 , n11172 );
buf ( n11174 , n4838 );
buf ( n11175 , n5862 );
xor ( n11176 , n11174 , n11175 );
or ( n11177 , n11173 , n11176 );
buf ( n11178 , n4839 );
buf ( n11179 , n5863 );
xor ( n11180 , n11178 , n11179 );
or ( n11181 , n11177 , n11180 );
buf ( n11182 , n4840 );
buf ( n11183 , n5864 );
xor ( n11184 , n11182 , n11183 );
or ( n11185 , n11181 , n11184 );
buf ( n11186 , n4841 );
buf ( n11187 , n5865 );
xor ( n11188 , n11186 , n11187 );
or ( n11189 , n11185 , n11188 );
buf ( n11190 , n4842 );
buf ( n11191 , n5866 );
xor ( n11192 , n11190 , n11191 );
or ( n11193 , n11189 , n11192 );
buf ( n11194 , n4843 );
buf ( n11195 , n5867 );
xor ( n11196 , n11194 , n11195 );
or ( n11197 , n11193 , n11196 );
buf ( n11198 , n4844 );
buf ( n11199 , n5868 );
xor ( n11200 , n11198 , n11199 );
or ( n11201 , n11197 , n11200 );
buf ( n11202 , n4845 );
buf ( n11203 , n5869 );
xor ( n11204 , n11202 , n11203 );
or ( n11205 , n11201 , n11204 );
buf ( n11206 , n4846 );
buf ( n11207 , n5870 );
xor ( n11208 , n11206 , n11207 );
or ( n11209 , n11205 , n11208 );
buf ( n11210 , n4847 );
buf ( n11211 , n5871 );
xor ( n11212 , n11210 , n11211 );
or ( n11213 , n11209 , n11212 );
buf ( n11214 , n4848 );
buf ( n11215 , n5872 );
xor ( n11216 , n11214 , n11215 );
or ( n11217 , n11213 , n11216 );
buf ( n11218 , n4849 );
buf ( n11219 , n5873 );
xor ( n11220 , n11218 , n11219 );
or ( n11221 , n11217 , n11220 );
buf ( n11222 , n4850 );
buf ( n11223 , n5874 );
xor ( n11224 , n11222 , n11223 );
or ( n11225 , n11221 , n11224 );
buf ( n11226 , n4851 );
buf ( n11227 , n5875 );
xor ( n11228 , n11226 , n11227 );
or ( n11229 , n11225 , n11228 );
buf ( n11230 , n4852 );
buf ( n11231 , n5876 );
xor ( n11232 , n11230 , n11231 );
or ( n11233 , n11229 , n11232 );
buf ( n11234 , n4853 );
buf ( n11235 , n5877 );
xor ( n11236 , n11234 , n11235 );
or ( n11237 , n11233 , n11236 );
buf ( n11238 , n4854 );
buf ( n11239 , n5878 );
xor ( n11240 , n11238 , n11239 );
or ( n11241 , n11237 , n11240 );
buf ( n11242 , n4855 );
buf ( n11243 , n5879 );
xor ( n11244 , n11242 , n11243 );
or ( n11245 , n11241 , n11244 );
buf ( n11246 , n4856 );
buf ( n11247 , n5880 );
xor ( n11248 , n11246 , n11247 );
or ( n11249 , n11245 , n11248 );
buf ( n11250 , n4857 );
buf ( n11251 , n5881 );
xor ( n11252 , n11250 , n11251 );
or ( n11253 , n11249 , n11252 );
buf ( n11254 , n4858 );
buf ( n11255 , n5882 );
xor ( n11256 , n11254 , n11255 );
or ( n11257 , n11253 , n11256 );
buf ( n11258 , n4859 );
buf ( n11259 , n5883 );
xor ( n11260 , n11258 , n11259 );
or ( n11261 , n11257 , n11260 );
buf ( n11262 , n4860 );
buf ( n11263 , n5884 );
xor ( n11264 , n11262 , n11263 );
or ( n11265 , n11261 , n11264 );
buf ( n11266 , n4861 );
buf ( n11267 , n5885 );
xor ( n11268 , n11266 , n11267 );
or ( n11269 , n11265 , n11268 );
buf ( n11270 , n4862 );
buf ( n11271 , n5886 );
xor ( n11272 , n11270 , n11271 );
or ( n11273 , n11269 , n11272 );
buf ( n11274 , n4863 );
buf ( n11275 , n5887 );
xor ( n11276 , n11274 , n11275 );
or ( n11277 , n11273 , n11276 );
buf ( n11278 , n4864 );
buf ( n11279 , n5888 );
xor ( n11280 , n11278 , n11279 );
or ( n11281 , n11277 , n11280 );
buf ( n11282 , n4865 );
buf ( n11283 , n5889 );
xor ( n11284 , n11282 , n11283 );
or ( n11285 , n11281 , n11284 );
buf ( n11286 , n4866 );
buf ( n11287 , n5890 );
xor ( n11288 , n11286 , n11287 );
or ( n11289 , n11285 , n11288 );
buf ( n11290 , n4867 );
buf ( n11291 , n5891 );
xor ( n11292 , n11290 , n11291 );
or ( n11293 , n11289 , n11292 );
buf ( n11294 , n4868 );
buf ( n11295 , n5892 );
xor ( n11296 , n11294 , n11295 );
or ( n11297 , n11293 , n11296 );
buf ( n11298 , n4869 );
buf ( n11299 , n5893 );
xor ( n11300 , n11298 , n11299 );
or ( n11301 , n11297 , n11300 );
buf ( n11302 , n4870 );
buf ( n11303 , n5894 );
xor ( n11304 , n11302 , n11303 );
or ( n11305 , n11301 , n11304 );
buf ( n11306 , n4871 );
buf ( n11307 , n5895 );
xor ( n11308 , n11306 , n11307 );
or ( n11309 , n11305 , n11308 );
buf ( n11310 , n4872 );
buf ( n11311 , n5896 );
xor ( n11312 , n11310 , n11311 );
or ( n11313 , n11309 , n11312 );
buf ( n11314 , n4873 );
buf ( n11315 , n5897 );
xor ( n11316 , n11314 , n11315 );
or ( n11317 , n11313 , n11316 );
buf ( n11318 , n4874 );
buf ( n11319 , n5898 );
xor ( n11320 , n11318 , n11319 );
or ( n11321 , n11317 , n11320 );
buf ( n11322 , n4875 );
buf ( n11323 , n5899 );
xor ( n11324 , n11322 , n11323 );
or ( n11325 , n11321 , n11324 );
buf ( n11326 , n4876 );
buf ( n11327 , n5900 );
xor ( n11328 , n11326 , n11327 );
or ( n11329 , n11325 , n11328 );
buf ( n11330 , n4877 );
buf ( n11331 , n5901 );
xor ( n11332 , n11330 , n11331 );
or ( n11333 , n11329 , n11332 );
buf ( n11334 , n4878 );
buf ( n11335 , n5902 );
xor ( n11336 , n11334 , n11335 );
or ( n11337 , n11333 , n11336 );
buf ( n11338 , n4879 );
buf ( n11339 , n5903 );
xor ( n11340 , n11338 , n11339 );
or ( n11341 , n11337 , n11340 );
buf ( n11342 , n4880 );
buf ( n11343 , n5904 );
xor ( n11344 , n11342 , n11343 );
or ( n11345 , n11341 , n11344 );
buf ( n11346 , n4881 );
buf ( n11347 , n5905 );
xor ( n11348 , n11346 , n11347 );
or ( n11349 , n11345 , n11348 );
buf ( n11350 , n4882 );
buf ( n11351 , n5906 );
xor ( n11352 , n11350 , n11351 );
or ( n11353 , n11349 , n11352 );
buf ( n11354 , n4883 );
buf ( n11355 , n5907 );
xor ( n11356 , n11354 , n11355 );
or ( n11357 , n11353 , n11356 );
buf ( n11358 , n4884 );
buf ( n11359 , n5908 );
xor ( n11360 , n11358 , n11359 );
or ( n11361 , n11357 , n11360 );
buf ( n11362 , n4885 );
buf ( n11363 , n5909 );
xor ( n11364 , n11362 , n11363 );
or ( n11365 , n11361 , n11364 );
buf ( n11366 , n4886 );
buf ( n11367 , n5910 );
xor ( n11368 , n11366 , n11367 );
or ( n11369 , n11365 , n11368 );
buf ( n11370 , n4887 );
buf ( n11371 , n5911 );
xor ( n11372 , n11370 , n11371 );
or ( n11373 , n11369 , n11372 );
buf ( n11374 , n4888 );
buf ( n11375 , n5912 );
xor ( n11376 , n11374 , n11375 );
or ( n11377 , n11373 , n11376 );
buf ( n11378 , n4889 );
buf ( n11379 , n5913 );
xor ( n11380 , n11378 , n11379 );
or ( n11381 , n11377 , n11380 );
buf ( n11382 , n4890 );
buf ( n11383 , n5914 );
xor ( n11384 , n11382 , n11383 );
or ( n11385 , n11381 , n11384 );
buf ( n11386 , n4891 );
buf ( n11387 , n5915 );
xor ( n11388 , n11386 , n11387 );
or ( n11389 , n11385 , n11388 );
buf ( n11390 , n4892 );
buf ( n11391 , n5916 );
xor ( n11392 , n11390 , n11391 );
or ( n11393 , n11389 , n11392 );
buf ( n11394 , n4893 );
buf ( n11395 , n5917 );
xor ( n11396 , n11394 , n11395 );
or ( n11397 , n11393 , n11396 );
buf ( n11398 , n4894 );
buf ( n11399 , n5918 );
xor ( n11400 , n11398 , n11399 );
or ( n11401 , n11397 , n11400 );
buf ( n11402 , n4895 );
buf ( n11403 , n5919 );
xor ( n11404 , n11402 , n11403 );
or ( n11405 , n11401 , n11404 );
buf ( n11406 , n4896 );
buf ( n11407 , n5920 );
xor ( n11408 , n11406 , n11407 );
or ( n11409 , n11405 , n11408 );
buf ( n11410 , n4897 );
buf ( n11411 , n5921 );
xor ( n11412 , n11410 , n11411 );
or ( n11413 , n11409 , n11412 );
buf ( n11414 , n4898 );
buf ( n11415 , n5922 );
xor ( n11416 , n11414 , n11415 );
or ( n11417 , n11413 , n11416 );
buf ( n11418 , n4899 );
buf ( n11419 , n5923 );
xor ( n11420 , n11418 , n11419 );
or ( n11421 , n11417 , n11420 );
buf ( n11422 , n4900 );
buf ( n11423 , n5924 );
xor ( n11424 , n11422 , n11423 );
or ( n11425 , n11421 , n11424 );
buf ( n11426 , n4901 );
buf ( n11427 , n5925 );
xor ( n11428 , n11426 , n11427 );
or ( n11429 , n11425 , n11428 );
buf ( n11430 , n4902 );
buf ( n11431 , n5926 );
xor ( n11432 , n11430 , n11431 );
or ( n11433 , n11429 , n11432 );
buf ( n11434 , n4903 );
buf ( n11435 , n5927 );
xor ( n11436 , n11434 , n11435 );
or ( n11437 , n11433 , n11436 );
buf ( n11438 , n4904 );
buf ( n11439 , n5928 );
xor ( n11440 , n11438 , n11439 );
or ( n11441 , n11437 , n11440 );
buf ( n11442 , n4905 );
buf ( n11443 , n5929 );
xor ( n11444 , n11442 , n11443 );
or ( n11445 , n11441 , n11444 );
buf ( n11446 , n4906 );
buf ( n11447 , n5930 );
xor ( n11448 , n11446 , n11447 );
or ( n11449 , n11445 , n11448 );
buf ( n11450 , n4907 );
buf ( n11451 , n5931 );
xor ( n11452 , n11450 , n11451 );
or ( n11453 , n11449 , n11452 );
buf ( n11454 , n4908 );
buf ( n11455 , n5932 );
xor ( n11456 , n11454 , n11455 );
or ( n11457 , n11453 , n11456 );
buf ( n11458 , n4909 );
buf ( n11459 , n5933 );
xor ( n11460 , n11458 , n11459 );
or ( n11461 , n11457 , n11460 );
buf ( n11462 , n4910 );
buf ( n11463 , n5934 );
xor ( n11464 , n11462 , n11463 );
or ( n11465 , n11461 , n11464 );
buf ( n11466 , n4911 );
buf ( n11467 , n5935 );
xor ( n11468 , n11466 , n11467 );
or ( n11469 , n11465 , n11468 );
buf ( n11470 , n4912 );
buf ( n11471 , n5936 );
xor ( n11472 , n11470 , n11471 );
or ( n11473 , n11469 , n11472 );
buf ( n11474 , n4913 );
buf ( n11475 , n5937 );
xor ( n11476 , n11474 , n11475 );
or ( n11477 , n11473 , n11476 );
buf ( n11478 , n4914 );
buf ( n11479 , n5938 );
xor ( n11480 , n11478 , n11479 );
or ( n11481 , n11477 , n11480 );
buf ( n11482 , n4915 );
buf ( n11483 , n5939 );
xor ( n11484 , n11482 , n11483 );
or ( n11485 , n11481 , n11484 );
buf ( n11486 , n4916 );
buf ( n11487 , n5940 );
xor ( n11488 , n11486 , n11487 );
or ( n11489 , n11485 , n11488 );
buf ( n11490 , n4917 );
buf ( n11491 , n5941 );
xor ( n11492 , n11490 , n11491 );
or ( n11493 , n11489 , n11492 );
buf ( n11494 , n4918 );
buf ( n11495 , n5942 );
xor ( n11496 , n11494 , n11495 );
or ( n11497 , n11493 , n11496 );
buf ( n11498 , n4919 );
buf ( n11499 , n5943 );
xor ( n11500 , n11498 , n11499 );
or ( n11501 , n11497 , n11500 );
buf ( n11502 , n4920 );
buf ( n11503 , n5944 );
xor ( n11504 , n11502 , n11503 );
or ( n11505 , n11501 , n11504 );
buf ( n11506 , n4921 );
buf ( n11507 , n5945 );
xor ( n11508 , n11506 , n11507 );
or ( n11509 , n11505 , n11508 );
buf ( n11510 , n4922 );
buf ( n11511 , n5946 );
xor ( n11512 , n11510 , n11511 );
or ( n11513 , n11509 , n11512 );
buf ( n11514 , n4923 );
buf ( n11515 , n5947 );
xor ( n11516 , n11514 , n11515 );
or ( n11517 , n11513 , n11516 );
buf ( n11518 , n4924 );
buf ( n11519 , n5948 );
xor ( n11520 , n11518 , n11519 );
or ( n11521 , n11517 , n11520 );
buf ( n11522 , n4925 );
buf ( n11523 , n5949 );
xor ( n11524 , n11522 , n11523 );
or ( n11525 , n11521 , n11524 );
buf ( n11526 , n4926 );
buf ( n11527 , n5950 );
xor ( n11528 , n11526 , n11527 );
or ( n11529 , n11525 , n11528 );
buf ( n11530 , n4927 );
buf ( n11531 , n5951 );
xor ( n11532 , n11530 , n11531 );
or ( n11533 , n11529 , n11532 );
buf ( n11534 , n4928 );
buf ( n11535 , n5952 );
xor ( n11536 , n11534 , n11535 );
or ( n11537 , n11533 , n11536 );
buf ( n11538 , n4929 );
buf ( n11539 , n5953 );
xor ( n11540 , n11538 , n11539 );
or ( n11541 , n11537 , n11540 );
buf ( n11542 , n4930 );
buf ( n11543 , n5954 );
xor ( n11544 , n11542 , n11543 );
or ( n11545 , n11541 , n11544 );
buf ( n11546 , n4931 );
buf ( n11547 , n5955 );
xor ( n11548 , n11546 , n11547 );
or ( n11549 , n11545 , n11548 );
buf ( n11550 , n4932 );
buf ( n11551 , n5956 );
xor ( n11552 , n11550 , n11551 );
or ( n11553 , n11549 , n11552 );
buf ( n11554 , n4933 );
buf ( n11555 , n5957 );
xor ( n11556 , n11554 , n11555 );
or ( n11557 , n11553 , n11556 );
buf ( n11558 , n4934 );
buf ( n11559 , n5958 );
xor ( n11560 , n11558 , n11559 );
or ( n11561 , n11557 , n11560 );
buf ( n11562 , n4935 );
buf ( n11563 , n5959 );
xor ( n11564 , n11562 , n11563 );
or ( n11565 , n11561 , n11564 );
buf ( n11566 , n4936 );
buf ( n11567 , n5960 );
xor ( n11568 , n11566 , n11567 );
or ( n11569 , n11565 , n11568 );
buf ( n11570 , n4937 );
buf ( n11571 , n5961 );
xor ( n11572 , n11570 , n11571 );
or ( n11573 , n11569 , n11572 );
buf ( n11574 , n4938 );
buf ( n11575 , n5962 );
xor ( n11576 , n11574 , n11575 );
or ( n11577 , n11573 , n11576 );
buf ( n11578 , n4939 );
buf ( n11579 , n5963 );
xor ( n11580 , n11578 , n11579 );
or ( n11581 , n11577 , n11580 );
buf ( n11582 , n4940 );
buf ( n11583 , n5964 );
xor ( n11584 , n11582 , n11583 );
or ( n11585 , n11581 , n11584 );
buf ( n11586 , n4941 );
buf ( n11587 , n5965 );
xor ( n11588 , n11586 , n11587 );
or ( n11589 , n11585 , n11588 );
buf ( n11590 , n4942 );
buf ( n11591 , n5966 );
xor ( n11592 , n11590 , n11591 );
or ( n11593 , n11589 , n11592 );
buf ( n11594 , n4943 );
buf ( n11595 , n5967 );
xor ( n11596 , n11594 , n11595 );
or ( n11597 , n11593 , n11596 );
buf ( n11598 , n4944 );
buf ( n11599 , n5968 );
xor ( n11600 , n11598 , n11599 );
or ( n11601 , n11597 , n11600 );
buf ( n11602 , n4945 );
buf ( n11603 , n5969 );
xor ( n11604 , n11602 , n11603 );
or ( n11605 , n11601 , n11604 );
buf ( n11606 , n4946 );
buf ( n11607 , n5970 );
xor ( n11608 , n11606 , n11607 );
or ( n11609 , n11605 , n11608 );
buf ( n11610 , n4947 );
buf ( n11611 , n5971 );
xor ( n11612 , n11610 , n11611 );
or ( n11613 , n11609 , n11612 );
buf ( n11614 , n4948 );
buf ( n11615 , n5972 );
xor ( n11616 , n11614 , n11615 );
or ( n11617 , n11613 , n11616 );
buf ( n11618 , n4949 );
buf ( n11619 , n5973 );
xor ( n11620 , n11618 , n11619 );
or ( n11621 , n11617 , n11620 );
buf ( n11622 , n4950 );
buf ( n11623 , n5974 );
xor ( n11624 , n11622 , n11623 );
or ( n11625 , n11621 , n11624 );
buf ( n11626 , n4951 );
buf ( n11627 , n5975 );
xor ( n11628 , n11626 , n11627 );
or ( n11629 , n11625 , n11628 );
buf ( n11630 , n4952 );
buf ( n11631 , n5976 );
xor ( n11632 , n11630 , n11631 );
or ( n11633 , n11629 , n11632 );
buf ( n11634 , n4953 );
buf ( n11635 , n5977 );
xor ( n11636 , n11634 , n11635 );
or ( n11637 , n11633 , n11636 );
buf ( n11638 , n4954 );
buf ( n11639 , n5978 );
xor ( n11640 , n11638 , n11639 );
or ( n11641 , n11637 , n11640 );
buf ( n11642 , n4955 );
buf ( n11643 , n5979 );
xor ( n11644 , n11642 , n11643 );
or ( n11645 , n11641 , n11644 );
buf ( n11646 , n4956 );
buf ( n11647 , n5980 );
xor ( n11648 , n11646 , n11647 );
or ( n11649 , n11645 , n11648 );
buf ( n11650 , n4957 );
buf ( n11651 , n5981 );
xor ( n11652 , n11650 , n11651 );
or ( n11653 , n11649 , n11652 );
buf ( n11654 , n4958 );
buf ( n11655 , n5982 );
xor ( n11656 , n11654 , n11655 );
or ( n11657 , n11653 , n11656 );
buf ( n11658 , n4959 );
buf ( n11659 , n5983 );
xor ( n11660 , n11658 , n11659 );
or ( n11661 , n11657 , n11660 );
buf ( n11662 , n4960 );
buf ( n11663 , n5984 );
xor ( n11664 , n11662 , n11663 );
or ( n11665 , n11661 , n11664 );
buf ( n11666 , n4961 );
buf ( n11667 , n5985 );
xor ( n11668 , n11666 , n11667 );
or ( n11669 , n11665 , n11668 );
buf ( n11670 , n4962 );
buf ( n11671 , n5986 );
xor ( n11672 , n11670 , n11671 );
or ( n11673 , n11669 , n11672 );
buf ( n11674 , n4963 );
buf ( n11675 , n5987 );
xor ( n11676 , n11674 , n11675 );
or ( n11677 , n11673 , n11676 );
buf ( n11678 , n4964 );
buf ( n11679 , n5988 );
xor ( n11680 , n11678 , n11679 );
or ( n11681 , n11677 , n11680 );
buf ( n11682 , n4965 );
buf ( n11683 , n5989 );
xor ( n11684 , n11682 , n11683 );
or ( n11685 , n11681 , n11684 );
buf ( n11686 , n4966 );
buf ( n11687 , n5990 );
xor ( n11688 , n11686 , n11687 );
or ( n11689 , n11685 , n11688 );
buf ( n11690 , n4967 );
buf ( n11691 , n5991 );
xor ( n11692 , n11690 , n11691 );
or ( n11693 , n11689 , n11692 );
buf ( n11694 , n4968 );
buf ( n11695 , n5992 );
xor ( n11696 , n11694 , n11695 );
or ( n11697 , n11693 , n11696 );
buf ( n11698 , n4969 );
buf ( n11699 , n5993 );
xor ( n11700 , n11698 , n11699 );
or ( n11701 , n11697 , n11700 );
buf ( n11702 , n4970 );
buf ( n11703 , n5994 );
xor ( n11704 , n11702 , n11703 );
or ( n11705 , n11701 , n11704 );
buf ( n11706 , n4971 );
buf ( n11707 , n5995 );
xor ( n11708 , n11706 , n11707 );
or ( n11709 , n11705 , n11708 );
buf ( n11710 , n4972 );
buf ( n11711 , n5996 );
xor ( n11712 , n11710 , n11711 );
or ( n11713 , n11709 , n11712 );
buf ( n11714 , n4973 );
buf ( n11715 , n5997 );
xor ( n11716 , n11714 , n11715 );
or ( n11717 , n11713 , n11716 );
buf ( n11718 , n4974 );
buf ( n11719 , n5998 );
xor ( n11720 , n11718 , n11719 );
or ( n11721 , n11717 , n11720 );
buf ( n11722 , n4975 );
buf ( n11723 , n5999 );
xor ( n11724 , n11722 , n11723 );
or ( n11725 , n11721 , n11724 );
buf ( n11726 , n4976 );
buf ( n11727 , n6000 );
xor ( n11728 , n11726 , n11727 );
or ( n11729 , n11725 , n11728 );
buf ( n11730 , n4977 );
buf ( n11731 , n6001 );
xor ( n11732 , n11730 , n11731 );
or ( n11733 , n11729 , n11732 );
buf ( n11734 , n4978 );
buf ( n11735 , n6002 );
xor ( n11736 , n11734 , n11735 );
or ( n11737 , n11733 , n11736 );
buf ( n11738 , n4979 );
buf ( n11739 , n6003 );
xor ( n11740 , n11738 , n11739 );
or ( n11741 , n11737 , n11740 );
buf ( n11742 , n4980 );
buf ( n11743 , n6004 );
xor ( n11744 , n11742 , n11743 );
or ( n11745 , n11741 , n11744 );
buf ( n11746 , n4981 );
buf ( n11747 , n6005 );
xor ( n11748 , n11746 , n11747 );
or ( n11749 , n11745 , n11748 );
buf ( n11750 , n4982 );
buf ( n11751 , n6006 );
xor ( n11752 , n11750 , n11751 );
or ( n11753 , n11749 , n11752 );
buf ( n11754 , n4983 );
buf ( n11755 , n6007 );
xor ( n11756 , n11754 , n11755 );
or ( n11757 , n11753 , n11756 );
buf ( n11758 , n4984 );
buf ( n11759 , n6008 );
xor ( n11760 , n11758 , n11759 );
or ( n11761 , n11757 , n11760 );
buf ( n11762 , n4985 );
buf ( n11763 , n6009 );
xor ( n11764 , n11762 , n11763 );
or ( n11765 , n11761 , n11764 );
buf ( n11766 , n4986 );
buf ( n11767 , n6010 );
xor ( n11768 , n11766 , n11767 );
or ( n11769 , n11765 , n11768 );
buf ( n11770 , n4987 );
buf ( n11771 , n6011 );
xor ( n11772 , n11770 , n11771 );
or ( n11773 , n11769 , n11772 );
buf ( n11774 , n4988 );
buf ( n11775 , n6012 );
xor ( n11776 , n11774 , n11775 );
or ( n11777 , n11773 , n11776 );
buf ( n11778 , n4989 );
buf ( n11779 , n6013 );
xor ( n11780 , n11778 , n11779 );
or ( n11781 , n11777 , n11780 );
buf ( n11782 , n4990 );
buf ( n11783 , n6014 );
xor ( n11784 , n11782 , n11783 );
or ( n11785 , n11781 , n11784 );
buf ( n11786 , n4991 );
buf ( n11787 , n6015 );
xor ( n11788 , n11786 , n11787 );
or ( n11789 , n11785 , n11788 );
buf ( n11790 , n4992 );
buf ( n11791 , n6016 );
xor ( n11792 , n11790 , n11791 );
or ( n11793 , n11789 , n11792 );
buf ( n11794 , n4993 );
buf ( n11795 , n6017 );
xor ( n11796 , n11794 , n11795 );
or ( n11797 , n11793 , n11796 );
buf ( n11798 , n4994 );
buf ( n11799 , n6018 );
xor ( n11800 , n11798 , n11799 );
or ( n11801 , n11797 , n11800 );
buf ( n11802 , n4995 );
buf ( n11803 , n6019 );
xor ( n11804 , n11802 , n11803 );
or ( n11805 , n11801 , n11804 );
buf ( n11806 , n4996 );
buf ( n11807 , n6020 );
xor ( n11808 , n11806 , n11807 );
or ( n11809 , n11805 , n11808 );
buf ( n11810 , n4997 );
buf ( n11811 , n6021 );
xor ( n11812 , n11810 , n11811 );
or ( n11813 , n11809 , n11812 );
buf ( n11814 , n4998 );
buf ( n11815 , n6022 );
xor ( n11816 , n11814 , n11815 );
or ( n11817 , n11813 , n11816 );
buf ( n11818 , n4999 );
buf ( n11819 , n6023 );
xor ( n11820 , n11818 , n11819 );
or ( n11821 , n11817 , n11820 );
buf ( n11822 , n5000 );
buf ( n11823 , n6024 );
xor ( n11824 , n11822 , n11823 );
or ( n11825 , n11821 , n11824 );
buf ( n11826 , n5001 );
buf ( n11827 , n6025 );
xor ( n11828 , n11826 , n11827 );
or ( n11829 , n11825 , n11828 );
buf ( n11830 , n5002 );
buf ( n11831 , n6026 );
xor ( n11832 , n11830 , n11831 );
or ( n11833 , n11829 , n11832 );
buf ( n11834 , n5003 );
buf ( n11835 , n6027 );
xor ( n11836 , n11834 , n11835 );
or ( n11837 , n11833 , n11836 );
buf ( n11838 , n5004 );
buf ( n11839 , n6028 );
xor ( n11840 , n11838 , n11839 );
or ( n11841 , n11837 , n11840 );
buf ( n11842 , n5005 );
buf ( n11843 , n6029 );
xor ( n11844 , n11842 , n11843 );
or ( n11845 , n11841 , n11844 );
buf ( n11846 , n5006 );
buf ( n11847 , n6030 );
xor ( n11848 , n11846 , n11847 );
or ( n11849 , n11845 , n11848 );
buf ( n11850 , n5007 );
buf ( n11851 , n6031 );
xor ( n11852 , n11850 , n11851 );
or ( n11853 , n11849 , n11852 );
buf ( n11854 , n5008 );
buf ( n11855 , n6032 );
xor ( n11856 , n11854 , n11855 );
or ( n11857 , n11853 , n11856 );
buf ( n11858 , n5009 );
buf ( n11859 , n6033 );
xor ( n11860 , n11858 , n11859 );
or ( n11861 , n11857 , n11860 );
buf ( n11862 , n5010 );
buf ( n11863 , n6034 );
xor ( n11864 , n11862 , n11863 );
or ( n11865 , n11861 , n11864 );
buf ( n11866 , n5011 );
buf ( n11867 , n6035 );
xor ( n11868 , n11866 , n11867 );
or ( n11869 , n11865 , n11868 );
buf ( n11870 , n5012 );
buf ( n11871 , n6036 );
xor ( n11872 , n11870 , n11871 );
or ( n11873 , n11869 , n11872 );
buf ( n11874 , n5013 );
buf ( n11875 , n6037 );
xor ( n11876 , n11874 , n11875 );
or ( n11877 , n11873 , n11876 );
buf ( n11878 , n5014 );
buf ( n11879 , n6038 );
xor ( n11880 , n11878 , n11879 );
or ( n11881 , n11877 , n11880 );
buf ( n11882 , n5015 );
buf ( n11883 , n6039 );
xor ( n11884 , n11882 , n11883 );
or ( n11885 , n11881 , n11884 );
buf ( n11886 , n5016 );
buf ( n11887 , n6040 );
xor ( n11888 , n11886 , n11887 );
or ( n11889 , n11885 , n11888 );
buf ( n11890 , n5017 );
buf ( n11891 , n6041 );
xor ( n11892 , n11890 , n11891 );
or ( n11893 , n11889 , n11892 );
buf ( n11894 , n5018 );
buf ( n11895 , n6042 );
xor ( n11896 , n11894 , n11895 );
or ( n11897 , n11893 , n11896 );
buf ( n11898 , n5019 );
buf ( n11899 , n6043 );
xor ( n11900 , n11898 , n11899 );
or ( n11901 , n11897 , n11900 );
buf ( n11902 , n5020 );
buf ( n11903 , n6044 );
xor ( n11904 , n11902 , n11903 );
or ( n11905 , n11901 , n11904 );
buf ( n11906 , n5021 );
buf ( n11907 , n6045 );
xor ( n11908 , n11906 , n11907 );
or ( n11909 , n11905 , n11908 );
buf ( n11910 , n5022 );
buf ( n11911 , n6046 );
xor ( n11912 , n11910 , n11911 );
or ( n11913 , n11909 , n11912 );
buf ( n11914 , n5023 );
buf ( n11915 , n6047 );
xor ( n11916 , n11914 , n11915 );
or ( n11917 , n11913 , n11916 );
buf ( n11918 , n5024 );
buf ( n11919 , n6048 );
xor ( n11920 , n11918 , n11919 );
or ( n11921 , n11917 , n11920 );
buf ( n11922 , n5025 );
buf ( n11923 , n6049 );
xor ( n11924 , n11922 , n11923 );
or ( n11925 , n11921 , n11924 );
buf ( n11926 , n5026 );
buf ( n11927 , n6050 );
xor ( n11928 , n11926 , n11927 );
or ( n11929 , n11925 , n11928 );
buf ( n11930 , n5027 );
buf ( n11931 , n6051 );
xor ( n11932 , n11930 , n11931 );
or ( n11933 , n11929 , n11932 );
buf ( n11934 , n5028 );
buf ( n11935 , n6052 );
xor ( n11936 , n11934 , n11935 );
or ( n11937 , n11933 , n11936 );
buf ( n11938 , n5029 );
buf ( n11939 , n6053 );
xor ( n11940 , n11938 , n11939 );
or ( n11941 , n11937 , n11940 );
buf ( n11942 , n5030 );
buf ( n11943 , n6054 );
xor ( n11944 , n11942 , n11943 );
or ( n11945 , n11941 , n11944 );
buf ( n11946 , n5031 );
buf ( n11947 , n6055 );
xor ( n11948 , n11946 , n11947 );
or ( n11949 , n11945 , n11948 );
buf ( n11950 , n5032 );
buf ( n11951 , n6056 );
xor ( n11952 , n11950 , n11951 );
or ( n11953 , n11949 , n11952 );
buf ( n11954 , n5033 );
buf ( n11955 , n6057 );
xor ( n11956 , n11954 , n11955 );
or ( n11957 , n11953 , n11956 );
buf ( n11958 , n5034 );
buf ( n11959 , n6058 );
xor ( n11960 , n11958 , n11959 );
or ( n11961 , n11957 , n11960 );
buf ( n11962 , n5035 );
buf ( n11963 , n6059 );
xor ( n11964 , n11962 , n11963 );
or ( n11965 , n11961 , n11964 );
buf ( n11966 , n5036 );
buf ( n11967 , n6060 );
xor ( n11968 , n11966 , n11967 );
or ( n11969 , n11965 , n11968 );
buf ( n11970 , n5037 );
buf ( n11971 , n6061 );
xor ( n11972 , n11970 , n11971 );
or ( n11973 , n11969 , n11972 );
buf ( n11974 , n5038 );
buf ( n11975 , n6062 );
xor ( n11976 , n11974 , n11975 );
or ( n11977 , n11973 , n11976 );
buf ( n11978 , n5039 );
buf ( n11979 , n6063 );
xor ( n11980 , n11978 , n11979 );
or ( n11981 , n11977 , n11980 );
buf ( n11982 , n5040 );
buf ( n11983 , n6064 );
xor ( n11984 , n11982 , n11983 );
or ( n11985 , n11981 , n11984 );
buf ( n11986 , n5041 );
buf ( n11987 , n6065 );
xor ( n11988 , n11986 , n11987 );
or ( n11989 , n11985 , n11988 );
buf ( n11990 , n5042 );
buf ( n11991 , n6066 );
xor ( n11992 , n11990 , n11991 );
or ( n11993 , n11989 , n11992 );
buf ( n11994 , n5043 );
buf ( n11995 , n6067 );
xor ( n11996 , n11994 , n11995 );
or ( n11997 , n11993 , n11996 );
buf ( n11998 , n5044 );
buf ( n11999 , n6068 );
xor ( n12000 , n11998 , n11999 );
or ( n12001 , n11997 , n12000 );
buf ( n12002 , n5045 );
buf ( n12003 , n6069 );
xor ( n12004 , n12002 , n12003 );
or ( n12005 , n12001 , n12004 );
buf ( n12006 , n5046 );
buf ( n12007 , n6070 );
xor ( n12008 , n12006 , n12007 );
or ( n12009 , n12005 , n12008 );
buf ( n12010 , n5047 );
buf ( n12011 , n6071 );
xor ( n12012 , n12010 , n12011 );
or ( n12013 , n12009 , n12012 );
buf ( n12014 , n5048 );
buf ( n12015 , n6072 );
xor ( n12016 , n12014 , n12015 );
or ( n12017 , n12013 , n12016 );
buf ( n12018 , n5049 );
buf ( n12019 , n6073 );
xor ( n12020 , n12018 , n12019 );
or ( n12021 , n12017 , n12020 );
buf ( n12022 , n5050 );
buf ( n12023 , n6074 );
xor ( n12024 , n12022 , n12023 );
or ( n12025 , n12021 , n12024 );
buf ( n12026 , n5051 );
buf ( n12027 , n6075 );
xor ( n12028 , n12026 , n12027 );
or ( n12029 , n12025 , n12028 );
buf ( n12030 , n5052 );
buf ( n12031 , n6076 );
xor ( n12032 , n12030 , n12031 );
or ( n12033 , n12029 , n12032 );
buf ( n12034 , n5053 );
buf ( n12035 , n6077 );
xor ( n12036 , n12034 , n12035 );
or ( n12037 , n12033 , n12036 );
buf ( n12038 , n5054 );
buf ( n12039 , n6078 );
xor ( n12040 , n12038 , n12039 );
or ( n12041 , n12037 , n12040 );
buf ( n12042 , n5055 );
buf ( n12043 , n6079 );
xor ( n12044 , n12042 , n12043 );
or ( n12045 , n12041 , n12044 );
buf ( n12046 , n5056 );
buf ( n12047 , n6080 );
xor ( n12048 , n12046 , n12047 );
or ( n12049 , n12045 , n12048 );
buf ( n12050 , n5057 );
buf ( n12051 , n6081 );
xor ( n12052 , n12050 , n12051 );
or ( n12053 , n12049 , n12052 );
buf ( n12054 , n5058 );
buf ( n12055 , n6082 );
xor ( n12056 , n12054 , n12055 );
or ( n12057 , n12053 , n12056 );
buf ( n12058 , n5059 );
buf ( n12059 , n6083 );
xor ( n12060 , n12058 , n12059 );
or ( n12061 , n12057 , n12060 );
buf ( n12062 , n5060 );
buf ( n12063 , n6084 );
xor ( n12064 , n12062 , n12063 );
or ( n12065 , n12061 , n12064 );
buf ( n12066 , n5061 );
buf ( n12067 , n6085 );
xor ( n12068 , n12066 , n12067 );
or ( n12069 , n12065 , n12068 );
buf ( n12070 , n5062 );
buf ( n12071 , n6086 );
xor ( n12072 , n12070 , n12071 );
or ( n12073 , n12069 , n12072 );
buf ( n12074 , n5063 );
buf ( n12075 , n6087 );
xor ( n12076 , n12074 , n12075 );
or ( n12077 , n12073 , n12076 );
buf ( n12078 , n5064 );
buf ( n12079 , n6088 );
xor ( n12080 , n12078 , n12079 );
or ( n12081 , n12077 , n12080 );
buf ( n12082 , n5065 );
buf ( n12083 , n6089 );
xor ( n12084 , n12082 , n12083 );
or ( n12085 , n12081 , n12084 );
buf ( n12086 , n5066 );
buf ( n12087 , n6090 );
xor ( n12088 , n12086 , n12087 );
or ( n12089 , n12085 , n12088 );
buf ( n12090 , n5067 );
buf ( n12091 , n6091 );
xor ( n12092 , n12090 , n12091 );
or ( n12093 , n12089 , n12092 );
buf ( n12094 , n5068 );
buf ( n12095 , n6092 );
xor ( n12096 , n12094 , n12095 );
or ( n12097 , n12093 , n12096 );
buf ( n12098 , n5069 );
buf ( n12099 , n6093 );
xor ( n12100 , n12098 , n12099 );
or ( n12101 , n12097 , n12100 );
buf ( n12102 , n5070 );
buf ( n12103 , n6094 );
xor ( n12104 , n12102 , n12103 );
or ( n12105 , n12101 , n12104 );
buf ( n12106 , n5071 );
buf ( n12107 , n6095 );
xor ( n12108 , n12106 , n12107 );
or ( n12109 , n12105 , n12108 );
buf ( n12110 , n5072 );
buf ( n12111 , n6096 );
xor ( n12112 , n12110 , n12111 );
or ( n12113 , n12109 , n12112 );
buf ( n12114 , n5073 );
buf ( n12115 , n6097 );
xor ( n12116 , n12114 , n12115 );
or ( n12117 , n12113 , n12116 );
buf ( n12118 , n5074 );
buf ( n12119 , n6098 );
xor ( n12120 , n12118 , n12119 );
or ( n12121 , n12117 , n12120 );
buf ( n12122 , n5075 );
buf ( n12123 , n6099 );
xor ( n12124 , n12122 , n12123 );
or ( n12125 , n12121 , n12124 );
buf ( n12126 , n5076 );
buf ( n12127 , n6100 );
xor ( n12128 , n12126 , n12127 );
or ( n12129 , n12125 , n12128 );
buf ( n12130 , n5077 );
buf ( n12131 , n6101 );
xor ( n12132 , n12130 , n12131 );
or ( n12133 , n12129 , n12132 );
buf ( n12134 , n5078 );
buf ( n12135 , n6102 );
xor ( n12136 , n12134 , n12135 );
or ( n12137 , n12133 , n12136 );
buf ( n12138 , n5079 );
buf ( n12139 , n6103 );
xor ( n12140 , n12138 , n12139 );
or ( n12141 , n12137 , n12140 );
buf ( n12142 , n5080 );
buf ( n12143 , n6104 );
xor ( n12144 , n12142 , n12143 );
or ( n12145 , n12141 , n12144 );
buf ( n12146 , n5081 );
buf ( n12147 , n6105 );
xor ( n12148 , n12146 , n12147 );
or ( n12149 , n12145 , n12148 );
buf ( n12150 , n5082 );
buf ( n12151 , n6106 );
xor ( n12152 , n12150 , n12151 );
or ( n12153 , n12149 , n12152 );
buf ( n12154 , n5083 );
buf ( n12155 , n6107 );
xor ( n12156 , n12154 , n12155 );
or ( n12157 , n12153 , n12156 );
buf ( n12158 , n5084 );
buf ( n12159 , n6108 );
xor ( n12160 , n12158 , n12159 );
or ( n12161 , n12157 , n12160 );
buf ( n12162 , n5085 );
buf ( n12163 , n6109 );
xor ( n12164 , n12162 , n12163 );
or ( n12165 , n12161 , n12164 );
buf ( n12166 , n5086 );
buf ( n12167 , n6110 );
xor ( n12168 , n12166 , n12167 );
or ( n12169 , n12165 , n12168 );
buf ( n12170 , n5087 );
buf ( n12171 , n6111 );
xor ( n12172 , n12170 , n12171 );
or ( n12173 , n12169 , n12172 );
buf ( n12174 , n5088 );
buf ( n12175 , n6112 );
xor ( n12176 , n12174 , n12175 );
or ( n12177 , n12173 , n12176 );
buf ( n12178 , n5089 );
buf ( n12179 , n6113 );
xor ( n12180 , n12178 , n12179 );
or ( n12181 , n12177 , n12180 );
buf ( n12182 , n5090 );
buf ( n12183 , n6114 );
xor ( n12184 , n12182 , n12183 );
or ( n12185 , n12181 , n12184 );
buf ( n12186 , n5091 );
buf ( n12187 , n6115 );
xor ( n12188 , n12186 , n12187 );
or ( n12189 , n12185 , n12188 );
buf ( n12190 , n5092 );
buf ( n12191 , n6116 );
xor ( n12192 , n12190 , n12191 );
or ( n12193 , n12189 , n12192 );
buf ( n12194 , n5093 );
buf ( n12195 , n6117 );
xor ( n12196 , n12194 , n12195 );
or ( n12197 , n12193 , n12196 );
buf ( n12198 , n5094 );
buf ( n12199 , n6118 );
xor ( n12200 , n12198 , n12199 );
or ( n12201 , n12197 , n12200 );
buf ( n12202 , n5095 );
buf ( n12203 , n6119 );
xor ( n12204 , n12202 , n12203 );
or ( n12205 , n12201 , n12204 );
buf ( n12206 , n5096 );
buf ( n12207 , n6120 );
xor ( n12208 , n12206 , n12207 );
or ( n12209 , n12205 , n12208 );
buf ( n12210 , n5097 );
buf ( n12211 , n6121 );
xor ( n12212 , n12210 , n12211 );
or ( n12213 , n12209 , n12212 );
buf ( n12214 , n5098 );
buf ( n12215 , n6122 );
xor ( n12216 , n12214 , n12215 );
or ( n12217 , n12213 , n12216 );
buf ( n12218 , n5099 );
buf ( n12219 , n6123 );
xor ( n12220 , n12218 , n12219 );
or ( n12221 , n12217 , n12220 );
buf ( n12222 , n5100 );
buf ( n12223 , n6124 );
xor ( n12224 , n12222 , n12223 );
or ( n12225 , n12221 , n12224 );
buf ( n12226 , n5101 );
buf ( n12227 , n6125 );
xor ( n12228 , n12226 , n12227 );
or ( n12229 , n12225 , n12228 );
buf ( n12230 , n5102 );
buf ( n12231 , n6126 );
xor ( n12232 , n12230 , n12231 );
or ( n12233 , n12229 , n12232 );
buf ( n12234 , n5103 );
buf ( n12235 , n6127 );
xor ( n12236 , n12234 , n12235 );
or ( n12237 , n12233 , n12236 );
buf ( n12238 , n5104 );
buf ( n12239 , n6128 );
xor ( n12240 , n12238 , n12239 );
or ( n12241 , n12237 , n12240 );
buf ( n12242 , n5105 );
buf ( n12243 , n6129 );
xor ( n12244 , n12242 , n12243 );
or ( n12245 , n12241 , n12244 );
buf ( n12246 , n5106 );
buf ( n12247 , n6130 );
xor ( n12248 , n12246 , n12247 );
or ( n12249 , n12245 , n12248 );
buf ( n12250 , n5107 );
buf ( n12251 , n6131 );
xor ( n12252 , n12250 , n12251 );
or ( n12253 , n12249 , n12252 );
buf ( n12254 , n5108 );
buf ( n12255 , n6132 );
xor ( n12256 , n12254 , n12255 );
or ( n12257 , n12253 , n12256 );
buf ( n12258 , n5109 );
not ( n12259 , n12258 );
or ( n12260 , n12257 , n12259 );
buf ( n12261 , n5110 );
buf ( n12262 , n6134 );
xor ( n12263 , n12261 , n12262 );
or ( n12264 , n12260 , n12263 );
buf ( n12265 , n5111 );
not ( n12266 , n12265 );
or ( n12267 , n12264 , n12266 );
buf ( n12268 , n5112 );
not ( n12269 , n12268 );
or ( n12270 , n12267 , n12269 );
buf ( n12271 , n5113 );
buf ( n12272 , n6137 );
xor ( n12273 , n12271 , n12272 );
or ( n12274 , n12270 , n12273 );
buf ( n12275 , n5114 );
buf ( n12276 , n6138 );
xor ( n12277 , n12275 , n12276 );
or ( n12278 , n12274 , n12277 );
buf ( n12279 , n5115 );
buf ( n12280 , n6139 );
xor ( n12281 , n12279 , n12280 );
or ( n12282 , n12278 , n12281 );
buf ( n12283 , n5116 );
not ( n12284 , n12283 );
or ( n12285 , n12282 , n12284 );
buf ( n12286 , n5117 );
not ( n12287 , n12286 );
or ( n12288 , n12285 , n12287 );
buf ( n12289 , n5118 );
buf ( n12290 , n6142 );
xor ( n12291 , n12289 , n12290 );
or ( n12292 , n12288 , n12291 );
buf ( n12293 , n5119 );
not ( n12294 , n12293 );
or ( n12295 , n12292 , n12294 );
buf ( n12296 , n5120 );
not ( n12297 , n12296 );
or ( n12298 , n12295 , n12297 );
buf ( n12299 , n5121 );
not ( n12300 , n12299 );
or ( n12301 , n12298 , n12300 );
buf ( n12302 , n5122 );
not ( n12303 , n12302 );
or ( n12304 , n12301 , n12303 );
buf ( n12305 , n5123 );
buf ( n12306 , n6147 );
xor ( n12307 , n12305 , n12306 );
or ( n12308 , n12304 , n12307 );
buf ( n12309 , n5124 );
buf ( n12310 , n6148 );
xor ( n12311 , n12309 , n12310 );
or ( n12312 , n12308 , n12311 );
buf ( n12313 , n5125 );
buf ( n12314 , n6149 );
xor ( n12315 , n12313 , n12314 );
or ( n12316 , n12312 , n12315 );
not ( n12317 , n12316 );
buf ( n12318 , n12317 );
buf ( n12319 , n12318 );
endmodule
|
// Check that packed arrays of all sorts get elaborated without an error and
// that the resulting type has the right packed width.
package p;
typedef logic [2:0] vector;
endpackage
module test;
typedef bit bit2;
typedef logic [1:0] vector;
bit2 [1:0] b;
vector [2:0] l;
p::vector [3:0] scoped_pa;
typedef enum logic [7:0] {
A
} E;
typedef E [1:0] EP;
typedef EP [2:0] EPP;
E e;
EP ep1;
E [1:0] ep2;
EP [2:0] epp1;
EPP epp2;
EPP [3:0] eppp;
enum logic [7:0] {
B
} [1:0] ep3;
typedef struct packed {
longint x;
} S1;
typedef struct packed {
time t;
integer i;
logic [1:0] x;
bit [3:0] y;
int z;
shortint w;
E e;
EP ep;
S1 s;
} S2;
localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64;
typedef S2 [3:0] SP;
typedef SP [9:0] SPP;
S2 s;
SP sp1;
S2 [3:0] sp2;
SP [9:0] spp1;
SPP spp2;
SPP [1:0] sppp;
struct packed {
S2 s;
} [3:0] sp3;
bit failed = 1'b0;
initial begin
// Packed arrays of basic types
failed |= $bits(b) !== 2;
failed |= $bits(l) !== 2 * 3;
failed |= $bits(scoped_pa) !== 3 * 4;
// Packed arrays of enums
failed |= $bits(e) !== 8;
failed |= $bits(ep1) !== $bits(e) * 2;
failed |= $bits(ep2) !== $bits(ep1);
failed |= $bits(ep3) !== $bits(ep1);
failed |= $bits(epp1) !== $bits(ep1) * 3;
failed |= $bits(epp2) !== $bits(epp1);
failed |= $bits(eppp) !== $bits(epp1) * 4;
// Packed arrays of structs
failed |= $bits(s) !== S_SIZE;
failed |= $bits(sp1) !== $bits(s) * 4;
failed |= $bits(sp2) !== $bits(sp1);
failed |= $bits(sp3) !== $bits(sp1);
failed |= $bits(spp1) !== $bits(sp1) * 10;
failed |= $bits(spp1) !== $bits(spp2);
failed |= $bits(sppp) !== $bits(spp1) * 2;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_channel_1 (
// rst and clocks
ref_clk,
lpm_dfe_n,
cpll_pd,
cpll_rst,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// receive
rx_rst,
rx_p,
rx_n,
rx_sys_clk_sel,
rx_out_clk_sel,
rx_out_clk,
rx_rst_done,
rx_pll_locked,
rx_clk,
rx_charisk,
rx_disperr,
rx_notintable,
rx_data,
rx_comma_align_enb,
rx_ilas_f,
rx_ilas_q,
rx_ilas_a,
rx_ilas_r,
rx_cgs_k,
// transmit
tx_rst,
tx_p,
tx_n,
tx_sys_clk_sel,
tx_out_clk_sel,
tx_out_clk,
tx_rst_done,
tx_pll_locked,
tx_clk,
tx_charisk,
tx_data,
// drp interface
up_clk,
up_drp_sel,
up_drp_addr,
up_drp_wr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_lanesel,
up_drp_rxrate);
// parameters
parameter DRP_ID = 0;
parameter GTH_GTX_N = 0;
parameter CPLL_FBDIV = 2;
parameter RX_OUT_DIV = 1;
parameter TX_OUT_DIV = 1;
parameter RX_CLK25_DIV = 10;
parameter TX_CLK25_DIV = 10;
parameter PMA_RSV = 32'h00018480;
parameter RX_CDR_CFG = 72'h03000023ff20400020;
// rst and clocks
input ref_clk;
input lpm_dfe_n;
input cpll_pd;
input cpll_rst;
input qpll_clk;
input qpll_ref_clk;
input qpll_locked;
// receive
input rx_rst;
input rx_p;
input rx_n;
input [ 1:0] rx_sys_clk_sel;
input [ 2:0] rx_out_clk_sel;
output rx_out_clk;
output rx_rst_done;
output rx_pll_locked;
input rx_clk;
output [ 3:0] rx_charisk;
output [ 3:0] rx_disperr;
output [ 3:0] rx_notintable;
output [31:0] rx_data;
input rx_comma_align_enb;
output [ 3:0] rx_ilas_f;
output [ 3:0] rx_ilas_q;
output [ 3:0] rx_ilas_a;
output [ 3:0] rx_ilas_r;
output [ 3:0] rx_cgs_k;
// transmit
input tx_rst;
output tx_p;
output tx_n;
input [ 1:0] tx_sys_clk_sel;
input [ 2:0] tx_out_clk_sel;
output tx_out_clk;
output tx_rst_done;
output tx_pll_locked;
input tx_clk;
input [ 3:0] tx_charisk;
input [31:0] tx_data;
// drp interface
input up_clk;
input up_drp_sel;
input [11:0] up_drp_addr;
input up_drp_wr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
input [ 7:0] up_drp_lanesel;
output [ 7:0] up_drp_rxrate;
// internal registers
reg [ 3:0] rx_user_ready = 'd0;
reg [ 3:0] tx_user_ready = 'd0;
reg rx_rst_done = 'd0;
reg tx_rst_done = 'd0;
reg up_drp_sel_int = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg up_drp_wr_int = 'd0;
reg [15:0] up_drp_wdata_int = 'd0;
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg [ 7:0] up_drp_rxrate = 'd0;
// internal signals
wire [ 3:0] rx_valid_k_s;
wire [ 2:0] rx_rate_p_s;
wire [ 7:0] rx_rate_s;
wire [ 3:0] rx_charisk_open_s;
wire [ 3:0] rx_disperr_open_s;
wire [ 3:0] rx_notintable_open_s;
wire [31:0] rx_data_open_s;
wire [ 1:0] rx_sys_clk_sel_s;
wire [ 1:0] tx_sys_clk_sel_s;
wire [ 1:0] rx_pll_clk_sel_s;
wire [ 1:0] tx_pll_clk_sel_s;
wire rx_rst_done_s;
wire tx_rst_done_s;
wire cpll_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// cgs & ilas frame characters
assign rx_ilas_f[3] = (rx_data[31:24] == 8'hfc) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_f[2] = (rx_data[23:16] == 8'hfc) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_f[1] = (rx_data[15: 8] == 8'hfc) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_f[0] = (rx_data[ 7: 0] == 8'hfc) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_q[3] = (rx_data[31:24] == 8'h9c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_q[2] = (rx_data[23:16] == 8'h9c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_q[1] = (rx_data[15: 8] == 8'h9c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_q[0] = (rx_data[ 7: 0] == 8'h9c) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_a[3] = (rx_data[31:24] == 8'h7c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_a[2] = (rx_data[23:16] == 8'h7c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_a[1] = (rx_data[15: 8] == 8'h7c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_a[0] = (rx_data[ 7: 0] == 8'h7c) ? rx_valid_k_s[0] : 1'b0;
assign rx_ilas_r[3] = (rx_data[31:24] == 8'h1c) ? rx_valid_k_s[3] : 1'b0;
assign rx_ilas_r[2] = (rx_data[23:16] == 8'h1c) ? rx_valid_k_s[2] : 1'b0;
assign rx_ilas_r[1] = (rx_data[15: 8] == 8'h1c) ? rx_valid_k_s[1] : 1'b0;
assign rx_ilas_r[0] = (rx_data[ 7: 0] == 8'h1c) ? rx_valid_k_s[0] : 1'b0;
assign rx_cgs_k[3] = (rx_data[31:24] == 8'hbc) ? rx_valid_k_s[3] : 1'b0;
assign rx_cgs_k[2] = (rx_data[23:16] == 8'hbc) ? rx_valid_k_s[2] : 1'b0;
assign rx_cgs_k[1] = (rx_data[15: 8] == 8'hbc) ? rx_valid_k_s[1] : 1'b0;
assign rx_cgs_k[0] = (rx_data[ 7: 0] == 8'hbc) ? rx_valid_k_s[0] : 1'b0;
// validate all characters
assign rx_valid_k_s = rx_charisk & (~rx_disperr) & (~rx_notintable);
// rate
assign rx_rate_p_s = 0;
assign rx_rate_s = (rx_rate_p_s == 3'd0) ? RX_OUT_DIV :
(rx_rate_p_s == 3'd1) ? 8'h01 :
(rx_rate_p_s == 3'd2) ? 8'h02 :
(rx_rate_p_s == 3'd3) ? 8'h04 :
(rx_rate_p_s == 3'd4) ? 8'h08 :
(rx_rate_p_s == 3'd5) ? 8'h10 : 8'h00;
// pll locked
assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
generate
if (GTH_GTX_N == 0) begin
assign rx_sys_clk_sel_s = rx_sys_clk_sel;
assign tx_sys_clk_sel_s = tx_sys_clk_sel;
assign rx_pll_clk_sel_s = 2'd0;
assign tx_pll_clk_sel_s = 2'd0;
end
if (GTH_GTX_N == 1) begin
assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
assign rx_pll_clk_sel_s = rx_sys_clk_sel;
assign tx_pll_clk_sel_s = tx_sys_clk_sel;
end
endgenerate
// user ready
always @(posedge up_clk) begin
if ((rx_rst == 1'b1) || (rx_pll_locked == 1'b0)) begin
rx_user_ready <= 4'd0;
end else begin
rx_user_ready <= {rx_user_ready[2:0], 1'b1};
end
end
always @(posedge up_clk) begin
if ((tx_rst == 1'b1) || (tx_pll_locked == 1'b0)) begin
tx_user_ready <= 4'd0;
end else begin
tx_user_ready <= {tx_user_ready[2:0], 1'b1};
end
end
// reset done
always @(posedge rx_clk) begin
rx_rst_done <= rx_rst_done_s;
end
always @(posedge tx_clk) begin
tx_rst_done <= tx_rst_done_s;
end
// drp control
always @(posedge up_clk) begin
if (up_drp_lanesel == DRP_ID) begin
up_drp_sel_int <= up_drp_sel;
up_drp_addr_int <= up_drp_addr;
up_drp_wr_int <= up_drp_wr;
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_rxrate <= rx_rate_s;
end else begin
up_drp_sel_int <= 1'd0;
up_drp_addr_int <= 12'd0;
up_drp_wr_int <= 1'd0;
up_drp_wdata_int <= 16'd0;
up_drp_rdata <= 16'd0;
up_drp_ready <= 1'd0;
up_drp_rxrate <= 8'd0;
end
end
// instantiations
generate
if (GTH_GTX_N == 0) begin
GTXE2_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.SHOW_REALIGN_COMMA ("TRUE"),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (35),
.CLK_COR_MIN_LAT (31),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_LEN (1),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_1_1 (10'b0000000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0000000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (7),
.CHAN_BOND_SEQ_LEN (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
.ES_QUAL_MASK (80'h00000000000000000000),
.ES_SDATA_MASK (80'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
.RX_DATA_WIDTH (40),
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (16'h2070),
.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RX_BIAS_CFG (12'b000000000100),
.DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DEBUG_CFG (12'b000000000000),
.RX_OS_CFG (13'b0000010000000),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
.TST_RSV (32'h00000000),
.RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.UCODEER_CLR (1'b0),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD_ATTR (48'h000000000000),
.RXBUF_ADDR_MODE ("FULL"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RX_BUFFER_CFG (6'b000000),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_THRESH_OVFLW (61),
.RXBUF_THRESH_OVRD ("FALSE"),
.RXBUF_THRESH_UNDFLW (4),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RXCDR_CFG (RX_CDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXISCANRESET_TIME (5'b00001),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (5'b00011),
.RXOOB_CFG (7'b0000110),
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
.RXPRBS_ERR_LOOPBACK (1'b0),
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.TRANS_TIME_RATE (8'h0E),
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
.TXPH_CFG (16'h0780),
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
.TX_DATA_WIDTH (40),
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_DRIVE_MODE ("DIRECT"),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
.TXGEARBOX_EN ("FALSE"),
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (5'b00001),
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.RXOUT_DIV (RX_OUT_DIV),
.TXOUT_DIV (TX_OUT_DIV),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.RXDFELPMRESET_TIME (7'b0001111),
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
.RX_CLKMUX_PD (1'b1),
.TX_CLKMUX_PD (1'b1),
.RX_INT_DATAWIDTH (1),
.TX_INT_DATAWIDTH (1),
.TX_QPI_STATUS_EN (1'b0),
.RX_DFE_KL_CFG2 (32'h3010D90C),
.RX_DFE_XYD_CFG (13'b0001100010000),
.TX_PREDRIVER_MODE (1'b0))
i_gtxe2_channel (
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (cpll_pd),
.CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpll_rst),
.GTRSVD (16'b0000000000000000),
.PCSRSVDIN (16'b0000000000000000),
.PCSRSVDIN2 (5'b00000),
.PMARSVDIN (5'b00000),
.PMARSVDIN2 (5'b00000),
.TSTIN (20'b11111111111111111111),
.TSTOUT (),
.CLKRSVD (4'b0000),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (ref_clk),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.DRPADDR (up_drp_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata_int),
.DRPDO (up_drp_rdata_s),
.DRPEN (up_drp_sel_int),
.DRPRDY (up_drp_ready_s),
.DRPWE (up_drp_wr_int),
.GTREFCLKMONITOR (),
.QPLLCLK (qpll_clk),
.QPLLREFCLK (qpll_ref_clk),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.DMONITOROUT (),
.TX8B10BEN (1'd1),
.LOOPBACK (3'd0),
.PHYSTATUS (),
.RXRATE (rx_rate_p_s),
.RXVALID (),
.RXPD (2'b00),
.TXPD (2'b00),
.SETERRSTATUS (1'd0),
.EYESCANRESET (1'd0),
.RXUSERRDY (rx_user_ready[3]),
.EYESCANDATAERROR (),
.EYESCANMODE (1'd0),
.EYESCANTRIGGER (1'd0),
.RXCDRFREQRESET (1'd0),
.RXCDRHOLD (1'd0),
.RXCDRLOCK (),
.RXCDROVRDEN (1'd0),
.RXCDRRESET (1'd0),
.RXCDRRESETRSV (1'd0),
.RXCLKCORCNT (),
.RX8B10BEN (1'd1),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.RXDATA ({rx_data_open_s, rx_data}),
.RXPRBSERR (),
.RXPRBSSEL (3'd0),
.RXPRBSCNTRESET (1'd0),
.RXDFEXYDEN (1'd0),
.RXDFEXYDHOLD (1'd0),
.RXDFEXYDOVRDEN (1'd0),
.RXDISPERR ({rx_disperr_open_s, rx_disperr}),
.RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
.GTXRXP (rx_p),
.GTXRXN (rx_n),
.RXBUFRESET (1'd0),
.RXBUFSTATUS (),
.RXDDIEN (1'd0),
.RXDLYBYPASS (1'd1),
.RXDLYEN (1'd0),
.RXDLYOVRDEN (1'd0),
.RXDLYSRESET (1'd0),
.RXDLYSRESETDONE (),
.RXPHALIGN (1'd0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (1'd0),
.RXPHDLYPD (1'd0),
.RXPHDLYRESET (1'd0),
.RXPHMONITOR (),
.RXPHOVRDEN (1'd0),
.RXPHSLIPMONITOR (),
.RXSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCOMMADET (),
.RXCOMMADETEN (1'd1),
.RXMCOMMAALIGNEN (rx_comma_align_enb),
.RXPCOMMAALIGNEN (rx_comma_align_enb),
.RXCHANBONDSEQ (),
.RXCHBONDEN (1'd0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'd1),
.RXCHBONDO (),
.RXCHBONDSLAVE (1'd0),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXDFEAGCHOLD (1'd0),
.RXDFEAGCOVRDEN (1'd0),
.RXDFECM1EN (1'd0),
.RXDFELFHOLD (1'd0),
.RXDFELFOVRDEN (1'd1),
.RXDFELPMRESET (1'd0),
.RXDFETAP2HOLD (1'd0),
.RXDFETAP2OVRDEN (1'd0),
.RXDFETAP3HOLD (1'd0),
.RXDFETAP3OVRDEN (1'd0),
.RXDFETAP4HOLD (1'd0),
.RXDFETAP4OVRDEN (1'd0),
.RXDFETAP5HOLD (1'd0),
.RXDFETAP5OVRDEN (1'd0),
.RXDFEUTHOLD (1'd0),
.RXDFEUTOVRDEN (1'd0),
.RXDFEVPHOLD (1'd0),
.RXDFEVPOVRDEN (1'd0),
.RXDFEVSEN (1'd0),
.RXLPMLFKLOVRDEN (1'd0),
.RXMONITOROUT (),
.RXMONITORSEL (2'd0),
.RXOSHOLD (1'd0),
.RXOSOVRDEN (1'd0),
.RXLPMHFHOLD (1'd0),
.RXLPMHFOVRDEN (1'd0),
.RXLPMLFHOLD (1'd0),
.RXRATEDONE (),
.RXOUTCLK (rx_out_clk),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (rx_out_clk_sel),
.RXDATAVALID (),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
.RXGEARBOXSLIP (1'd0),
.GTRXRESET (rx_rst),
.RXOOBRESET (1'd0),
.RXPCSRESET (1'd0),
.RXPMARESET (1'd0),
.RXLPMEN (lpm_dfe_n),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCOMINITDET (),
.RXELECIDLE (),
.RXELECIDLEMODE (2'b10),
.RXPOLARITY (1'd0),
.RXSLIDE (1'd0),
.RXCHARISCOMMA (),
.RXCHARISK ({rx_charisk_open_s, rx_charisk}),
.RXCHBONDI (5'd0),
.RXRESETDONE (rx_rst_done_s),
.RXQPIEN (1'd0),
.RXQPISENN (),
.RXQPISENP (),
.TXPHDLYTSTCLK (1'd0),
.TXPOSTCURSOR (5'd0),
.TXPOSTCURSORINV (1'd0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'd0),
.TXQPIBIASEN (1'd0),
.TXQPISTRONGPDOWN (1'd0),
.TXQPIWEAKPUP (1'd0),
.CFGRESET (1'd0),
.GTTXRESET (tx_rst),
.PCSRSVDOUT (),
.TXUSERRDY (tx_user_ready[3]),
.GTRESETSEL (1'd0),
.RESETOVRD (1'd0),
.TXCHARDISPMODE (8'd0),
.TXCHARDISPVAL (8'd0),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk),
.TXELECIDLE (1'd0),
.TXMARGIN (3'd0),
.TXRATE (3'd0),
.TXSWING (1'd0),
.TXPRBSFORCEERR (1'd0),
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
.TXDLYOVRDEN (1'd0),
.TXDLYSRESET (1'd0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (1'd0),
.TXPHALIGN (1'd0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (1'd0),
.TXPHDLYPD (1'd0),
.TXPHDLYRESET (1'd0),
.TXPHINIT (1'd0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'd0),
.TXBUFSTATUS (),
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (1'd0),
.TXDIFFCTRL (4'b1000),
.TXDIFFPD (1'd0),
.TXINHIBIT (1'd0),
.TXMAINCURSOR (7'b0000000),
.TXPISOPD (1'd0),
.TXDATA ({32'd0, tx_data}),
.GTXTXP (tx_p),
.GTXTXN (tx_n),
.TXOUTCLK (tx_out_clk),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (tx_out_clk_sel),
.TXRATEDONE (),
.TXCHARISK ({4'd0, tx_charisk}),
.TXGEARBOXREADY (),
.TXHEADER (3'd0),
.TXSEQUENCE (7'd0),
.TXSTARTSEQ (1'd0),
.TXPCSRESET (1'd0),
.TXPMARESET (1'd0),
.TXRESETDONE (tx_rst_done_s),
.TXCOMFINISH (),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
.TXCOMWAKE (1'd0),
.TXPDELECIDLEMODE (1'd0),
.TXPOLARITY (1'd0),
.TXDETECTRX (1'd0),
.TX8B10BBYPASS (8'd0),
.TXPRBSSEL (3'd0),
.TXQPISENP (),
.TXQPISENN ());
end
if (GTH_GTX_N == 1) begin
GTHE3_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
.ADAPT_CFG0 (16'b1111100000000000),
.ADAPT_CFG1 (16'b0000000000000000),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_TXPROGDIVRESET (1'b0),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CDR_SWAP_MODE_EN (1'b0),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (16'b0110011111111010),
.CPLL_CFG1 (16'b1010010010010100),
.CPLL_CFG2 (16'b1111000000000111),
.CPLL_CFG3 (6'b000000),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (5),
.CPLL_INIT_CFG0 (16'b0000000000011110),
.CPLL_INIT_CFG1 (8'b00000000),
.CPLL_LOCK_CFG (16'b0000000111101000),
.CPLL_REFCLK_DIV (1),
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DFE_D_X_REL_POS (1'b0),
.DFE_VCM_COMP_EN (1'b0),
.DMONITOR_CFG0 (10'b0000000000),
.DMONITOR_CFG1 (8'b00000000),
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'b000000000000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER0 (16'b0000000000000000),
.ES_QUALIFIER1 (16'b0000000000000000),
.ES_QUALIFIER2 (16'b0000000000000000),
.ES_QUALIFIER3 (16'b0000000000000000),
.ES_QUALIFIER4 (16'b0000000000000000),
.ES_QUAL_MASK0 (16'b0000000000000000),
.ES_QUAL_MASK1 (16'b0000000000000000),
.ES_QUAL_MASK2 (16'b0000000000000000),
.ES_QUAL_MASK3 (16'b0000000000000000),
.ES_QUAL_MASK4 (16'b0000000000000000),
.ES_SDATA_MASK0 (16'b0000000000000000),
.ES_SDATA_MASK1 (16'b0000000000000000),
.ES_SDATA_MASK2 (16'b0000000000000000),
.ES_SDATA_MASK3 (16'b0000000000000000),
.ES_SDATA_MASK4 (16'b0000000000000000),
.EVODD_PHI_CFG (11'b00000000000),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (5'b00000),
.GM_BIAS_SELECT (1'b0),
.LOCAL_MASTER (1'b1),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
.PCIE_BUFG_DIV_CTRL (16'b0011010100001001),
.PCIE_RXPCS_CFG_GEN3 (16'b0000001010100100),
.PCIE_RXPMA_CFG (16'b0000000000001010),
.PCIE_TXPCS_CFG_GEN3 (16'b0010010010100000),
.PCIE_TXPMA_CFG (16'b0000000000001010),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PCS_RSVD1 (3'b000),
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PLL_SEL_MODE_GEN12 (2'b11),
.PLL_SEL_MODE_GEN3 (2'b11),
.PMA_RSV1 (16'b0001000000000000),
.PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b0),
.RESET_POWERSAVE_DISABLE (1'b0),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("FALSE"),
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (16'b0000000000000000),
.RXCDR_CFG0_GEN3 (16'b0000000000000000),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (16'b0000011101100110),
.RXCDR_CFG2_GEN3 (16'b0000011101100110),
.RXCDR_CFG3 (16'b0000000000000000),
.RXCDR_CFG3_GEN3 (16'b0000000000000000),
.RXCDR_CFG4 (16'b0000000000000000),
.RXCDR_CFG4_GEN3 (16'b0000000000000000),
.RXCDR_CFG5 (16'b0000000000000000),
.RXCDR_CFG5_GEN3 (16'b0000000000000000),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG0 (16'b0100010010000000),
.RXCDR_LOCK_CFG1 (16'b0101111111111111),
.RXCDR_LOCK_CFG2 (16'b0111011111000011),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCFOK_CFG0 (16'b0100000000000000),
.RXCFOK_CFG1 (16'b0000000001100101),
.RXCFOK_CFG2 (16'b0000000000101110),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDFELPM_KL_CFG0 (16'b0000000000000000),
.RXDFELPM_KL_CFG1 (16'b0000000000000010),
.RXDFELPM_KL_CFG2 (16'b0000000000000000),
.RXDFE_CFG0 (16'b0000101000000000),
.RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'b0000000000000000),
.RXDFE_GC_CFG1 (16'b0111100001100000),
.RXDFE_GC_CFG2 (16'b0000000000000000),
.RXDFE_H2_CFG0 (16'b0000000000000000),
.RXDFE_H2_CFG1 (16'b0000000000000000),
.RXDFE_H3_CFG0 (16'b0100000000000000),
.RXDFE_H3_CFG1 (16'b0000000000000000),
.RXDFE_H4_CFG0 (16'b0010000000000000),
.RXDFE_H4_CFG1 (16'b0000000000000011),
.RXDFE_H5_CFG0 (16'b0010000000000000),
.RXDFE_H5_CFG1 (16'b0000000000000011),
.RXDFE_H6_CFG0 (16'b0010000000000000),
.RXDFE_H6_CFG1 (16'b0000000000000000),
.RXDFE_H7_CFG0 (16'b0010000000000000),
.RXDFE_H7_CFG1 (16'b0000000000000000),
.RXDFE_H8_CFG0 (16'b0010000000000000),
.RXDFE_H8_CFG1 (16'b0000000000000000),
.RXDFE_H9_CFG0 (16'b0010000000000000),
.RXDFE_H9_CFG1 (16'b0000000000000000),
.RXDFE_HA_CFG0 (16'b0010000000000000),
.RXDFE_HA_CFG1 (16'b0000000000000000),
.RXDFE_HB_CFG0 (16'b0010000000000000),
.RXDFE_HB_CFG1 (16'b0000000000000000),
.RXDFE_HC_CFG0 (16'b0000000000000000),
.RXDFE_HC_CFG1 (16'b0000000000000000),
.RXDFE_HD_CFG0 (16'b0000000000000000),
.RXDFE_HD_CFG1 (16'b0000000000000000),
.RXDFE_HE_CFG0 (16'b0000000000000000),
.RXDFE_HE_CFG1 (16'b0000000000000000),
.RXDFE_HF_CFG0 (16'b0000000000000000),
.RXDFE_HF_CFG1 (16'b0000000000000000),
.RXDFE_OS_CFG0 (16'b1000000000000000),
.RXDFE_OS_CFG1 (16'b0000000000000000),
.RXDFE_UT_CFG0 (16'b1000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_VP_CFG0 (16'b1010101000000000),
.RXDFE_VP_CFG1 (16'b0000000000110011),
.RXDLY_CFG (16'b0000000000011111),
.RXDLY_LCFG (16'b0000000000110000),
.RXELECIDLE_CFG ("Sigcfg_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (4),
.RXGEARBOX_EN ("FALSE"),
.RXISCANRESET_TIME (5'b00001),
.RXLPM_CFG (16'b0000000000000000),
.RXLPM_GC_CFG (16'b0000000000000000),
.RXLPM_KH_CFG0 (16'b0000000000000000),
.RXLPM_KH_CFG1 (16'b0000000000000010),
.RXLPM_OS_CFG0 (16'b1000000000000000),
.RXLPM_OS_CFG1 (16'b0000000000000010),
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
.RXPHBEACON_CFG (16'b0000000000000000),
.RXPHDLY_CFG (16'b0010000000100000),
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b0110011000100010),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_CFG0 (2'b00),
.RXPI_CFG1 (2'b00),
.RXPI_CFG2 (2'b00),
.RXPI_CFG3 (2'b00),
.RXPI_CFG4 (1'b0),
.RXPI_CFG5 (1'b1),
.RXPI_CFG6 (3'b000),
.RXPI_LPM (1'b0),
.RXPI_VREFSEL (1'b0),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
.RX_BIAS_CFG0 (16'b0000101010110100),
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (4'b1010),
.RX_CTLE3_LPF (8'b00000001),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DFELPM_CFG0 (4'b0110),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG0 (2'b10),
.RX_DFE_AGC_CFG1 (3'b100),
.RX_DFE_KL_LPM_KH_CFG0 (2'b01),
.RX_DFE_KL_LPM_KH_CFG1 (3'b100),
.RX_DFE_KL_LPM_KL_CFG0 (2'b01),
.RX_DFE_KL_LPM_KL_CFG1 (3'b100),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_HI_LR (1'b1),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
.RX_INT_DATAWIDTH (1),
.RX_PMA_POWER_SAVE (1'b0),
.RX_PROGDIV_CFG (20.0),
.RX_SAMPLE_PERIOD (3'b101),
.RX_SIG_VALID_DLY (11),
.RX_SUM_DFETAPREP_EN (1'b0),
.RX_SUM_IREF_TUNE (4'b0000),
.RX_SUM_RES_CTRL (2'b00),
.RX_SUM_VCMTUNE (4'b0000),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b000),
.RX_TUNE_AFE_OS (2'b10),
.RX_WIDEMODE_CDR (1'b1),
.RX_XCLK_SEL ("RXDES"),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL (1'b0),
.SIM_VERSION (2),
.TAPDLY_SET_TX (2'b00),
.TEMPERATUR_PAR (4'b0010),
.TERM_RCAL_CFG (15'b100001000010000),
.TERM_RCAL_OVRD (3'b000),
.TRANS_TIME_RATE (8'b00001110),
.TST_RSV0 (8'b00000000),
.TST_RSV1 (8'b00000000),
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'b0000000000001001),
.TXDLY_LCFG (16'b0000000001010000),
.TXDRVBIAS_N (4'b1010),
.TXDRVBIAS_P (4'b1010),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
.TXPHDLY_CFG0 (16'b0010000000100000),
.TXPHDLY_CFG1 (16'b0000000011010101),
.TXPH_CFG (16'b0000100110000000),
.TXPH_MONITOR_SEL (5'b00000),
.TXPI_CFG0 (2'b00),
.TXPI_CFG1 (2'b00),
.TXPI_CFG2 (2'b00),
.TXPI_CFG3 (1'b0),
.TXPI_CFG4 (1'b1),
.TXPI_CFG5 (3'b000),
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_LPM (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'b00000000),
.TXPI_SYNFREQ_PPM (3'b000),
.TXPI_VREFSEL (1'b0),
.TXPMARESET_TIME (5'b00011),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (40),
.TX_DCD_CFG (6'b000010),
.TX_DCD_EN (1'b0),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_EML_PHI_TUNE (1'b0),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
.TX_INT_DATAWIDTH (1),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1001111),
.TX_MARGIN_FULL_1 (7'b1001110),
.TX_MARGIN_FULL_2 (7'b1001100),
.TX_MARGIN_FULL_3 (7'b1001010),
.TX_MARGIN_FULL_4 (7'b1001000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000101),
.TX_MARGIN_LOW_2 (7'b1000011),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_MODE_SEL (3'b000),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PROGCLK_SEL ("PREPI"),
.TX_PROGDIV_CFG (20.0),
.TX_QPI_STATUS_EN (1'b0),
.TX_RXDETECT_CFG (14'b00000000110010),
.TX_RXDETECT_REF (3'b100),
.TX_SAMPLE_PERIOD (3'b101),
.TX_SARC_LPBK_ENB (1'b0),
.TX_XCLK_SEL ("TXOUT"),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.WB_MODE (2'b00))
i_gthe3_channel (
.CFGRESET (1'd0),
.CLKRSVD0 (1'd0),
.CLKRSVD1 (1'd0),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (cpll_pd),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpll_rst),
.DMONFIFORESET (1'd0),
.DMONITORCLK (1'd0),
.DRPADDR (up_drp_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata_int),
.DRPEN (up_drp_sel_int),
.DRPWE (up_drp_wr_int),
.EVODDPHICALDONE (1'd0),
.EVODDPHICALSTART (1'd0),
.EVODDPHIDRDEN (1'd0),
.EVODDPHIDWREN (1'd0),
.EVODDPHIXRDEN (1'd0),
.EVODDPHIXWREN (1'd0),
.EYESCANMODE (1'd0),
.EYESCANRESET (1'd0),
.EYESCANTRIGGER (1'd0),
.GTGREFCLK (1'd0),
.GTHRXN (rx_n),
.GTHRXP (rx_p),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (ref_clk),
.GTREFCLK1 (1'd0),
.GTRESETSEL (1'd0),
.GTRSVD (15'd0),
.GTRXRESET (rx_rst),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.GTTXRESET (tx_rst),
.LOOPBACK (3'd0),
.LPBKRXTXSEREN (1'd0),
.LPBKTXRXSEREN (1'd0),
.PCIEEQRXEQADAPTDONE (1'd0),
.PCIERSTIDLE (1'd0),
.PCIERSTTXSYNCSTART (1'd0),
.PCIEUSERRATEDONE (1'd0),
.PCSRSVDIN (16'd0),
.PCSRSVDIN2 (5'd0),
.PMARSVDIN (5'd0),
.QPLL0CLK (qpll_clk),
.QPLL0REFCLK (qpll_ref_clk),
.QPLL1CLK (1'd0),
.QPLL1REFCLK (1'd0),
.RESETOVRD (1'd0),
.RSTCLKENTX (1'd0),
.RXBUFRESET (1'd0),
.RXCDRFREQRESET (1'd0),
.RXCDRHOLD (1'd0),
.RXCDROVRDEN (1'd0),
.RXCDRRESET (1'd0),
.RXCDRRESETRSV (1'd0),
.RXCHBONDEN (1'd0),
.RXCHBONDI (5'd0),
.RXCHBONDLEVEL (2'd0),
.RXCHBONDMASTER (1'd0),
.RXCHBONDSLAVE (1'd0),
.RXCOMMADETEN (1'd1),
.RXDFEAGCCTRL (2'b01),
.RXDFEAGCHOLD (1'd0),
.RXDFEAGCOVRDEN (1'd0),
.RXDFELFHOLD (1'd0),
.RXDFELFOVRDEN (1'd0),
.RXDFELPMRESET (1'd0),
.RXDFETAP10HOLD (1'd0),
.RXDFETAP10OVRDEN (1'd0),
.RXDFETAP11HOLD (1'd0),
.RXDFETAP11OVRDEN (1'd0),
.RXDFETAP12HOLD (1'd0),
.RXDFETAP12OVRDEN (1'd0),
.RXDFETAP13HOLD (1'd0),
.RXDFETAP13OVRDEN (1'd0),
.RXDFETAP14HOLD (1'd0),
.RXDFETAP14OVRDEN (1'd0),
.RXDFETAP15HOLD (1'd0),
.RXDFETAP15OVRDEN (1'd0),
.RXDFETAP2HOLD (1'd0),
.RXDFETAP2OVRDEN (1'd0),
.RXDFETAP3HOLD (1'd0),
.RXDFETAP3OVRDEN (1'd0),
.RXDFETAP4HOLD (1'd0),
.RXDFETAP4OVRDEN (1'd0),
.RXDFETAP5HOLD (1'd0),
.RXDFETAP5OVRDEN (1'd0),
.RXDFETAP6HOLD (1'd0),
.RXDFETAP6OVRDEN (1'd0),
.RXDFETAP7HOLD (1'd0),
.RXDFETAP7OVRDEN (1'd0),
.RXDFETAP8HOLD (1'd0),
.RXDFETAP8OVRDEN (1'd0),
.RXDFETAP9HOLD (1'd0),
.RXDFETAP9OVRDEN (1'd0),
.RXDFEUTHOLD (1'd0),
.RXDFEUTOVRDEN (1'd0),
.RXDFEVPHOLD (1'd0),
.RXDFEVPOVRDEN (1'd0),
.RXDFEVSEN (1'd0),
.RXDFEXYDEN (1'd1),
.RXDLYBYPASS (1'd1),
.RXDLYEN (1'd0),
.RXDLYOVRDEN (1'd0),
.RXDLYSRESET (1'd0),
.RXELECIDLEMODE (2'b11),
.RXGEARBOXSLIP (1'd0),
.RXLATCLK (1'd0),
.RXLPMEN (lpm_dfe_n),
.RXLPMGCHOLD (1'd0),
.RXLPMGCOVRDEN (1'd0),
.RXLPMHFHOLD (1'd0),
.RXLPMHFOVRDEN (1'd0),
.RXLPMLFHOLD (1'd0),
.RXLPMLFKLOVRDEN (1'd0),
.RXLPMOSHOLD (1'd0),
.RXLPMOSOVRDEN (1'd0),
.RXMCOMMAALIGNEN (rx_comma_align_enb),
.RXMONITORSEL (2'd0),
.RXOOBRESET (1'd0),
.RXOSCALRESET (1'd0),
.RXOSHOLD (1'd0),
.RXOSINTCFG (4'b1101),
.RXOSINTEN (1'd1),
.RXOSINTHOLD (1'd0),
.RXOSINTOVRDEN (1'd0),
.RXOSINTSTROBE (1'd0),
.RXOSINTTESTOVRDEN (1'd0),
.RXOSOVRDEN (1'd0),
.RXOUTCLKSEL (rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_comma_align_enb),
.RXPCSRESET (1'd0),
.RXPD (2'd0),
.RXPHALIGN (1'd0),
.RXPHALIGNEN (1'd0),
.RXPHDLYPD (1'd1),
.RXPHDLYRESET (1'd0),
.RXPHOVRDEN (1'd0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'd0),
.RXPOLARITY (1'd0),
.RXPRBSCNTRESET (1'd0),
.RXPRBSSEL (4'd0),
.RXPROGDIVRESET (1'd0),
.RXQPIEN (1'd0),
.RXRATE (rx_rate_p_s),
.RXRATEMODE (1'd0),
.RXSLIDE (1'd0),
.RXSLIPOUTCLK (1'd0),
.RXSLIPPMA (1'd0),
.RXSYNCALLIN (1'd0),
.RXSYNCIN (1'd0),
.RXSYNCMODE (1'd0),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (rx_user_ready[3]),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.RX8B10BEN (1'd1),
.SIGVALIDCLK (1'd0),
.TSTIN (20'd0),
.TXBUFDIFFCTRL (3'd0),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
.TXCOMWAKE (1'd0),
.TXCTRL0 (16'd0),
.TXCTRL1 (16'd0),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA ({32'd0, tx_data}),
.TXDATAEXTENDRSVD (8'd0),
.TXDEEMPH (1'd0),
.TXDETECTRX (1'd0),
.TXDIFFCTRL (4'b1100),
.TXDIFFPD (1'd0),
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
.TXDLYOVRDEN (1'd0),
.TXDLYSRESET (1'd0),
.TXDLYUPDOWN (1'd0),
.TXELECIDLE (1'd0),
.TXHEADER (6'd0),
.TXINHIBIT (1'd0),
.TXLATCLK (1'd0),
.TXMAINCURSOR (7'b1000000),
.TXMARGIN (3'd0),
.TXOUTCLKSEL (tx_out_clk_sel),
.TXPCSRESET (1'd0),
.TXPD (2'd0),
.TXPDELECIDLEMODE (1'd0),
.TXPHALIGN (1'd0),
.TXPHALIGNEN (1'd0),
.TXPHDLYPD (1'd1),
.TXPHDLYRESET (1'd0),
.TXPHDLYTSTCLK (1'd0),
.TXPHINIT (1'd0),
.TXPHOVRDEN (1'd0),
.TXPIPPMEN (1'd0),
.TXPIPPMOVRDEN (1'd0),
.TXPIPPMPD (1'd0),
.TXPIPPMSEL (1'd0),
.TXPIPPMSTEPSIZE (5'd0),
.TXPISOPD (1'd0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'd0),
.TXPOLARITY (1'd0),
.TXPOSTCURSOR (5'd0),
.TXPOSTCURSORINV (1'd0),
.TXPRBSFORCEERR (1'd0),
.TXPRBSSEL (4'd0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'd0),
.TXPROGDIVRESET (tx_rst),
.TXQPIBIASEN (1'd0),
.TXQPISTRONGPDOWN (1'd0),
.TXQPIWEAKPUP (1'd0),
.TXRATE (3'd0),
.TXRATEMODE (1'd0),
.TXSEQUENCE (7'd0),
.TXSWING (1'd0),
.TXSYNCALLIN (1'd0),
.TXSYNCIN (1'd0),
.TXSYNCMODE (1'd0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (tx_user_ready[3]),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk),
.TX8B10BBYPASS (8'd0),
.TX8B10BEN (1'd1),
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLREFCLKLOST (),
.DMONITOROUT (),
.DRPDO (up_drp_rdata_s),
.DRPRDY (up_drp_ready_s),
.EYESCANDATAERROR (),
.GTHTXN (tx_n),
.GTHTXP (tx_p),
.GTPOWERGOOD (),
.GTREFCLKMONITOR (),
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
.PCIEUSERRATESTART (),
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
.RESETEXCEPTION (),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRLOCK (),
.RXCDRPHDONE (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCHBONDO (),
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
.RXCTRL2 (),
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA ({rx_data_open_s, rx_data}),
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADER (),
.RXHEADERVALID (),
.RXMONITOROUT (),
.RXOSINTDONE (),
.RXOSINTSTARTED (),
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
.RXOUTCLK (rx_out_clk),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXPHALIGNDONE (),
.RXPHALIGNERR (),
.RXPMARESETDONE (),
.RXPRBSERR (),
.RXPRBSLOCKED (),
.RXPRGDIVRESETDONE (),
.RXQPISENN (),
.RXQPISENP (),
.RXRATEDONE (),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLKRDY (),
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
.RXSYNCDONE (),
.RXSYNCOUT (),
.RXVALID (),
.TXBUFSTATUS (),
.TXCOMFINISH (),
.TXDLYSRESETDONE (),
.TXOUTCLK (tx_out_clk),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXPMARESETDONE (),
.TXPRGDIVRESETDONE (),
.TXQPISENN (),
.TXQPISENP (),
.TXRATEDONE (),
.TXRESETDONE (tx_rst_done_s),
.TXSYNCDONE (),
.TXSYNCOUT ());
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_int_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE
|
`timescale 1ns / 1ps
//__________________________________________________uart_tx
`define RDY 2'b11
`define LOAD_BIT 2'b01
`define SEND_BIT 2'b00
`define STOP 2'b10
//__________Test Bench
`define BIT_TMR_MAX 10'd869 // test bench <-- 115200 : tb #1738
//`define BIT_TMR_MAX 4'd10417//14'b10100010110000 // 14'd1023
//______________________________________________________________________
// `define BIT_INDEX_MAX 4'd10
module uart_tx(
input clk,
input rst,
input send,
input [7:0] data_tx,
output done,
output txd
);
reg [9:0] bitTmr;
//wire bitDone;
reg [3:0] bitIndex;
wire txBit;
//reg [9:0] txdata_tx;
reg [1:0] txState;
assign done = (txState == `STOP) ? 1'b1 : 1'b0;
assign txd = (txState == `SEND_BIT) ? txBit : 1'b1;
//{1'b1,data_tx[7:0],1'b0}
assign txBit =( (bitIndex == 0) ? 1'b0 :
( (bitIndex == 1) ? data_tx[0] :
( (bitIndex == 2) ? data_tx[1] :
( (bitIndex == 3) ? data_tx[2] :
( (bitIndex == 4) ? data_tx[3] :
( (bitIndex == 5) ? data_tx[4] :
( (bitIndex == 6) ? data_tx[5] :
( (bitIndex == 7) ? data_tx[6] :
( (bitIndex == 8) ? data_tx[7] :
1'b1
)
)
)
)
)
)
)
)
);
always@(posedge clk) begin
if(rst)
txState<= `RDY;
else
case(txState)
`RDY :
begin
bitIndex <= 0;
bitTmr <= 0;
if(send == 1'b1)
txState<=`SEND_BIT;
else
txState<=`RDY;
end
`SEND_BIT :
begin
if (bitTmr == `BIT_TMR_MAX-1)
begin
bitTmr <=0;
if (bitIndex == 4'd10-1)
begin
txState<=`STOP;
end
else
begin
bitIndex <= bitIndex + 1'b1;
txState<=`SEND_BIT;
end
end
else
begin
bitTmr <= bitTmr + 1'b1;
txState <= `SEND_BIT;
end
end
`STOP :
begin
if(send == 1'b1)
txState<=txState;
else //if(send == 1'b0)
txState<=`RDY;
end
default :
txState <= `RDY;
endcase
end
/*
always@(posedge clk) begin
if(rst)
bitTmr <= 0;
else
if(txState[0] == 1) // if(txState == `RDY)
bitTmr <= 0;
else
if(bitDone)
bitTmr <= 0;
else
bitTmr <= bitTmr +1 ;
end
assign bitDone = (bitTmr == `BIT_TMR_MAX) ? 1 : 0;
always@(posedge clk) begin
if(rst)
bitIndex <= 0;
else
if(txState[1] == 1) // if(txState == `RDY)
bitIndex <= 0;
else
if(txState == `LOAD_BIT)
bitIndex <= bitIndex +1 ;
else
bitIndex <= bitIndex;
end
*/
/*
always@(posedge clk) begin
if(rst)
txdata_tx <= 0;
else
if(txState[1] == 0) // if(send == 1'b1)
txdata_tx <= {1'b1,data_tx,1'b0} ;
else
txdata_tx <= 10'b1_1111_1111_1;
end
always@(posedge clk) begin
if(rst)
txBit <= 1'b1;
else
if(txState[1] == 1) // if(txState == `RDY)
txBit <= 1'b1 ;
else //if(txState == `LOAD_BIT)
txBit <= txdata_tx[bitIndex];
end
assign txd = rst ? 1 : txBit;
*/
//assign ready = (txState == `RDY) ? 1'b1 : 1'b0;
endmodule
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "DeepGATE_include.v"
module convLayerControl #(
parameter SIZE = 16'd125, //number of processing units in this tile
parameter LOOP = 16'd100, //nodes calculated per processing unit
parameter PRV_SIZE = 16'd10, //number of processing units in previous tile
parameter PRV_LOOP = 16'd10, //number of loops in previous tile
parameter FILTER_X = 16'd10,
parameter FILTER_Y = 16'd10,
parameter STRIDE = 16'd1
)(
input clk,
input rstIn,
input dataAvailable,
input ramFull,
output reg enable = 0,
output reg transfer = 0,
output reg tileIdle = 0,
output reg rstNodes = 0,
output reg dataRead = 0,
output reg [15:0] iterationCnt = 0
);
localparam READY = 4'b0001,
PROCESS = 4'b0010,
TRANSFER = 4'b0100,
WAIT = 4'b1000;
reg [3:0] CURRENT_STATE = READY;
reg ramWait = 0;
reg [$clog2(LOOP):0] loopCnt = 0;
/*
Control FSM for each tile.
In state READY the tile waits for data from the previous tile to become
available. In PROCESS, the tile computes the output of each node using
successive add-multiply ops. These outputs are passed through a combinational
approximation of the sigmoid function in one cycle and then TRANSFERred
to RAM. The PROCESS/TRANSFER cycle repeats a LOOP number of times, after
which the state machine enters the WAIT state, where the module idles until
the following tile compute its outputs based on the data in the aforementioned
RAM.
*/
always@(posedge clk) begin
if(rstIn) begin
enable <= 0;
transfer <= 0;
iterationCnt <= 0;
loopCnt <= 0;
tileIdle <= 0;
ramWait <= 0;
rstNodes <= 1;
CURRENT_STATE <= READY;
end
else begin
rstNodes <= 0;
case(CURRENT_STATE)
READY: begin
tileIdle <= 1;
if(dataAvailable) begin
tileIdle <= 0;
dataRead <= 1;
CURRENT_STATE <= PROCESS;
end
end
PROCESS: begin
iterationCnt <= iterationCnt + 1'd1;
if(iterationCnt == PRV_SIZE*PRV_LOOP - 1)
dataRead <= 0;
if(iterationCnt < PRV_SIZE*PRV_LOOP)
enable <= 1;
else begin
enable <= 0;
iterationCnt <= 0;
loopCnt <= loopCnt + 1'b1;
transfer <= 1;
CURRENT_STATE <= TRANSFER;
end
end
TRANSFER: begin
iterationCnt <= iterationCnt + 1'b1;
if(iterationCnt == SIZE - 1'b1) begin
iterationCnt <= 0;
transfer <= 0;
rstNodes <= 1;
if(loopCnt < LOOP) begin
dataRead <= 1;
CURRENT_STATE <= PROCESS;
end
else begin
CURRENT_STATE <= WAIT;
loopCnt <= 0;
end
end
end
WAIT: begin
ramWait <= 1;
if(!ramFull && ramWait) begin
ramWait <= 0;
tileIdle <= 1;
CURRENT_STATE <= READY;
end
end
endcase
end
end
endmodule |
`default_nettype wire
module damy_memory_16entry_512bit(
input iCLOCK,
input [63:0] iBYTE_ENA,
//Write
input iWR_ENA,
input [3:0] iWR_ADDR,
input [511:0] iWR_DATA,
//Read
input [3:0] iRD_ADDR,
output [511:0] oRD_DATA
);
reg [511:0] b_mem[0:15];
always@(posedge iCLOCK)begin
if(iWR_ENA)begin
b_mem[iWR_ADDR] <= func_byteena_o(iBYTE_ENA, b_mem[iWR_ADDR], iWR_DATA);
end
end
function [511:0] func_byteena_o;
input [63:0] func_byteena;
input [511:0] func_current_data;
input [511:0] func_new_data;
reg [511:0] func_local_data;
begin
func_local_data[7:0] = (func_byteena[0])? func_new_data[7:0] : func_current_data[7:0];
func_local_data[15:8] = (func_byteena[1])? func_new_data[15:8] : func_current_data[15:8];
func_local_data[23:16] = (func_byteena[2])? func_new_data[23:16] : func_current_data[23:16];
func_local_data[31:24] = (func_byteena[3])? func_new_data[31:24] : func_current_data[31:24];
func_local_data[39:32] = (func_byteena[4])? func_new_data[39:32] : func_current_data[39:32];
func_local_data[47:40] = (func_byteena[5])? func_new_data[47:40] : func_current_data[47:40];
func_local_data[55:48] = (func_byteena[6])? func_new_data[55:48] : func_current_data[55:48];
func_local_data[63:56] = (func_byteena[7])? func_new_data[63:56] : func_current_data[63:56];
func_local_data[71:64] = (func_byteena[8])? func_new_data[71:64] : func_current_data[71:64];
func_local_data[79:72] = (func_byteena[9])? func_new_data[79:72] : func_current_data[79:72];
func_local_data[87:80] = (func_byteena[10])? func_new_data[87:80] : func_current_data[87:80];
func_local_data[95:88] = (func_byteena[11])? func_new_data[95:88] : func_current_data[95:88];
func_local_data[103:96] = (func_byteena[12])? func_new_data[103:96] : func_current_data[103:96];
func_local_data[111:104] = (func_byteena[13])? func_new_data[111:104] : func_current_data[111:104];
func_local_data[119:112] = (func_byteena[14])? func_new_data[119:112] : func_current_data[119:112];
func_local_data[127:120] = (func_byteena[15])? func_new_data[127:120] : func_current_data[127:120];
func_local_data[135:128] = (func_byteena[16])? func_new_data[135:128] : func_current_data[135:128];
func_local_data[143:136] = (func_byteena[17])? func_new_data[143:136] : func_current_data[143:136];
func_local_data[151:144] = (func_byteena[18])? func_new_data[151:144] : func_current_data[151:144];
func_local_data[159:152] = (func_byteena[19])? func_new_data[159:152] : func_current_data[159:152];
func_local_data[167:160] = (func_byteena[20])? func_new_data[167:160] : func_current_data[167:160];
func_local_data[175:168] = (func_byteena[21])? func_new_data[175:168] : func_current_data[175:168];
func_local_data[183:176] = (func_byteena[22])? func_new_data[183:176] : func_current_data[183:176];
func_local_data[191:184] = (func_byteena[23])? func_new_data[191:184] : func_current_data[191:184];
func_local_data[199:192] = (func_byteena[24])? func_new_data[199:192] : func_current_data[199:192];
func_local_data[207:200] = (func_byteena[25])? func_new_data[207:200] : func_current_data[207:200];
func_local_data[215:208] = (func_byteena[26])? func_new_data[215:208] : func_current_data[215:208];
func_local_data[223:216] = (func_byteena[27])? func_new_data[223:216] : func_current_data[223:216];
func_local_data[231:224] = (func_byteena[28])? func_new_data[231:224] : func_current_data[231:224];
func_local_data[239:232] = (func_byteena[29])? func_new_data[239:232] : func_current_data[239:232];
func_local_data[247:240] = (func_byteena[30])? func_new_data[247:240] : func_current_data[247:240];
func_local_data[255:248] = (func_byteena[31])? func_new_data[255:248] : func_current_data[255:248];
func_local_data[263:256] = (func_byteena[32])? func_new_data[263:256] : func_current_data[263:256];
func_local_data[271:264] = (func_byteena[33])? func_new_data[271:264] : func_current_data[271:264];
func_local_data[279:272] = (func_byteena[34])? func_new_data[279:272] : func_current_data[279:272];
func_local_data[287:280] = (func_byteena[35])? func_new_data[287:280] : func_current_data[287:280];
func_local_data[295:288] = (func_byteena[36])? func_new_data[295:288] : func_current_data[295:288];
func_local_data[303:296] = (func_byteena[37])? func_new_data[303:296] : func_current_data[303:296];
func_local_data[311:304] = (func_byteena[38])? func_new_data[311:304] : func_current_data[311:304];
func_local_data[319:312] = (func_byteena[39])? func_new_data[319:312] : func_current_data[319:312];
func_local_data[327:320] = (func_byteena[40])? func_new_data[327:320] : func_current_data[327:320];
func_local_data[335:328] = (func_byteena[41])? func_new_data[335:328] : func_current_data[335:328];
func_local_data[343:336] = (func_byteena[42])? func_new_data[343:336] : func_current_data[343:336];
func_local_data[351:344] = (func_byteena[43])? func_new_data[351:344] : func_current_data[351:344];
func_local_data[359:352] = (func_byteena[44])? func_new_data[359:352] : func_current_data[359:352];
func_local_data[367:360] = (func_byteena[45])? func_new_data[367:360] : func_current_data[367:360];
func_local_data[375:368] = (func_byteena[46])? func_new_data[375:368] : func_current_data[375:368];
func_local_data[383:376] = (func_byteena[47])? func_new_data[383:376] : func_current_data[383:376];
func_local_data[391:384] = (func_byteena[48])? func_new_data[391:384] : func_current_data[391:384];
func_local_data[399:392] = (func_byteena[49])? func_new_data[399:392] : func_current_data[399:392];
func_local_data[407:400] = (func_byteena[50])? func_new_data[407:400] : func_current_data[407:400];
func_local_data[415:408] = (func_byteena[51])? func_new_data[415:408] : func_current_data[415:408];
func_local_data[423:416] = (func_byteena[52])? func_new_data[423:416] : func_current_data[423:416];
func_local_data[431:424] = (func_byteena[53])? func_new_data[431:424] : func_current_data[431:424];
func_local_data[439:432] = (func_byteena[54])? func_new_data[439:432] : func_current_data[439:432];
func_local_data[447:440] = (func_byteena[55])? func_new_data[447:440] : func_current_data[447:440];
func_local_data[455:448] = (func_byteena[56])? func_new_data[455:448] : func_current_data[455:448];
func_local_data[463:456] = (func_byteena[57])? func_new_data[463:456] : func_current_data[463:456];
func_local_data[471:464] = (func_byteena[58])? func_new_data[471:464] : func_current_data[471:464];
func_local_data[479:472] = (func_byteena[59])? func_new_data[479:472] : func_current_data[479:472];
func_local_data[487:480] = (func_byteena[60])? func_new_data[487:480] : func_current_data[487:480];
func_local_data[495:488] = (func_byteena[61])? func_new_data[495:488] : func_current_data[495:488];
func_local_data[503:496] = (func_byteena[62])? func_new_data[503:496] : func_current_data[503:496];
func_local_data[511:504] = (func_byteena[63])? func_new_data[511:504] : func_current_data[511:504];
func_byteena_o = func_local_data;
end
endfunction
assign oRD_DATA = b_mem[iRD_ADDR];
endmodule
`default_nettype none |
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (
IO_CLK,
IO_RST_N,
LED
);
input IO_CLK;
input IO_RST_N;
output [3:0] LED;
parameter signed [31:0] MEM_SIZE = 65536;
parameter [31:0] MEM_START = 32'h00000000;
parameter [31:0] MEM_MASK = (MEM_SIZE - 1);
wire clk_sys;
wire rst_sys_n;
wire instr_req;
reg instr_gnt;
wire instr_rvalid;
wire [31:0] instr_addr;
wire [31:0] instr_rdata;
wire data_req;
reg data_gnt;
reg data_rvalid;
wire data_we;
wire [3:0] data_be;
wire [31:0] data_addr;
wire [31:0] data_wdata;
wire [31:0] data_rdata;
reg [31:0] mem_addr;
reg mem_req;
reg mem_write;
reg [3:0] mem_be;
reg [31:0] mem_wdata;
wire mem_rvalid;
wire [31:0] mem_rdata;
ibex_core #(
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000)
) u_core(
.clk_i(clk_sys),
.rst_ni(rst_sys_n),
.test_en_i('b0),
.hart_id_i(32'b0),
.boot_addr_i(32'h00000000),
.instr_req_o(instr_req),
.instr_gnt_i(instr_gnt),
.instr_rvalid_i(instr_rvalid),
.instr_addr_o(instr_addr),
.instr_rdata_i(instr_rdata),
.instr_err_i('b0),
.data_req_o(data_req),
.data_gnt_i(data_gnt),
.data_rvalid_i(data_rvalid),
.data_we_o(data_we),
.data_be_o(data_be),
.data_addr_o(data_addr),
.data_wdata_o(data_wdata),
.data_rdata_i(data_rdata),
.data_err_i('b0),
.irq_software_i(1'b0),
.irq_timer_i(1'b0),
.irq_external_i(1'b0),
.irq_fast_i(15'b0),
.irq_nm_i(1'b0),
.debug_req_i('b0),
.fetch_enable_i('b1),
.core_sleep_o()
);
always @(*) begin
mem_req = 1'b0;
mem_addr = 32'b0;
mem_write = 1'b0;
mem_be = 4'b0;
mem_wdata = 32'b0;
if (instr_req) begin
mem_req = ((instr_addr & ~MEM_MASK) == MEM_START);
mem_addr = instr_addr;
end
else if (data_req) begin
mem_req = ((data_addr & ~MEM_MASK) == MEM_START);
mem_write = data_we;
mem_be = data_be;
mem_addr = data_addr;
mem_wdata = data_wdata;
end
end
ram_1p #(.Depth((MEM_SIZE / 4))) u_ram(
.clk_i(clk_sys),
.rst_ni(rst_sys_n),
.req_i(mem_req),
.we_i(mem_write),
.be_i(mem_be),
.addr_i(mem_addr),
.wdata_i(mem_wdata),
.rvalid_o(mem_rvalid),
.rdata_o(mem_rdata)
);
assign instr_rdata = mem_rdata;
assign data_rdata = mem_rdata;
assign instr_rvalid = mem_rvalid;
always @(posedge clk_sys or negedge rst_sys_n)
if (!rst_sys_n) begin
instr_gnt <= 'b0;
data_gnt <= 'b0;
data_rvalid <= 'b0;
end
else begin
instr_gnt <= (instr_req && mem_req);
data_gnt <= ((~instr_req && data_req) && mem_req);
data_rvalid <= ((~instr_req && data_req) && mem_req);
end
reg [3:0] leds;
always @(posedge clk_sys or negedge rst_sys_n)
if (!rst_sys_n)
leds <= 4'b0;
else if (((mem_req && data_req) && data_we)) begin : sv2v_autoblock_1
reg signed [31:0] i;
for (i = 0; (i < 4); i = (i + 1))
if ((data_be[i] == 1'b1))
leds <= data_wdata[(i * 8)+:4];
end
assign LED = leds;
clkgen_xil7series clkgen(
.IO_CLK(IO_CLK),
.IO_RST_N(IO_RST_N),
.clk_sys(clk_sys),
.rst_sys_n(rst_sys_n)
);
endmodule
|
`timescale 1ns/1ps
//wb_uart.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000003
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_uart
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x03
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:8
*/
`include "uart_defines.v"
//Control Flag Defines
`define CONTROL_RESET 0
`define CONTROL_FC_CTS_RTS 1
`define CONTROL_FC_DTS_DSR 2
`define CONTROL_READ_INTERRUPT 3
`define CONTROL_WRITE_INTERRUPT 4
//Status
`define STATUS_TRANSMIT_OVERFLOW 0
`define STATUS_READ_OVERFLOW 1
`define STATUS_READ_UNDERFLOW 2
`define STATUS_READ_INTERRUPT 3
`define STATUS_WRITE_INTERRUPT 4
//`define BAUDRATE 115200
//`define DIVISOR 8
//`define DEFAULT_CLOCK_DIVISOR (`CLOCK_RATE / (`BAUDRATE * `DIVISOR))
`define INTERRUPT_SLEEP_TIMEOUT (100)
module wb_uart (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//UART Phy
output o_tx,
input i_rx,
input i_rts,
output o_cts,
input i_dtr,
output o_dsr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Registers/Wires
reg [31:0] control;
reg [31:0] status;
wire [31:0] prescaler;
reg [31:0] clock_div;
reg set_clock_div;
wire [31:0] default_clock_div;
reg write_strobe;
reg [7:0] write_data;
wire write_full;
wire [31:0] write_available;
reg [15:0] write_count;
reg [1:0] dw_countdown;
wire [31:0] write_size;
reg [1:0] read_delay;
reg read_strobe;
wire [7:0] read_data;
wire read_empty;
wire [31:0] read_count;
wire [31:0] read_size;
//Status
wire read_overflow;
wire write_overflow;
//write data
reg write_en;
reg read_en;
reg [1:0] local_read_count;
//User Request to red this much data
reg [31:0] user_read_count;
wire reading;
wire writing;
reg [31:0] interrupt_sleep;
wire interrupt_ready;
//Submodules
uart_controller uc (
.clk (clk ),
.rst (rst ),
//Physical Lines
.rx (i_rx ),
.tx (o_tx ),
.cts (o_cts ),
.rts (i_rts ),
//Control/Status
.control_reset (control[`CONTROL_RESET] ),
.cts_rts_flowcontrol (control[`CONTROL_FC_CTS_RTS] ),
.read_overflow (read_overflow ),
.prescaler (prescaler ),
.set_clock_div (set_clock_div ),
.clock_div (clock_div ),
.default_clock_div (default_clock_div ),
//Data In
.write_strobe (write_strobe ),
.write_data (write_data ),
.write_full (write_full ),
.write_available (write_available ),
.write_size (write_size ),
//Data Out
.read_strobe (read_strobe ),
.read_data (read_data ),
.read_empty (read_empty ),
.read_count (read_count ),
.read_size (read_size )
);
//Asynchronous Logic
integer i;
assign reading = ((i_wbs_cyc && !i_wbs_we && (read_count > 0) && (i_wbs_adr == `UART_REG_READ)) || read_en);
assign writing = (i_wbs_cyc && i_wbs_we && ((write_count > 0) || (i_wbs_adr == `UART_REG_WRITE)));
/*
assign interrupt_ready = (!o_wbs_ack && !i_wbs_cyc && !write_en && !read_en) &&
(user_read_count == 0) &&
((control[`CONTROL_READ_INTERRUPT] && !read_empty) ||
(control[`CONTROL_WRITE_INTERRUPT] && !write_full));
*/
assign interrupt_ready = (user_read_count == 0) &&
((control[`CONTROL_READ_INTERRUPT] && !read_empty) ||
(control[`CONTROL_WRITE_INTERRUPT] && !write_full));
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
control <= 8'h0;
write_strobe <= 0;
read_strobe <= 0;
read_delay <= 0;
user_read_count <= 0;
local_read_count <= 0;
//write
write_en <= 0;
read_en <= 0;
write_count <= 0;
dw_countdown <= 0;
write_data <= 0;
//status
status <= 0;
set_clock_div <= 0;
clock_div <= 0;
o_wbs_int <= 0;
interrupt_sleep <= `INTERRUPT_SLEEP_TIMEOUT;
end
else begin
write_strobe <= 0;
set_clock_div <= 0;
read_strobe <= 0;
control[`CONTROL_RESET] <= 0;
//Status (Change Strobes from the UART controller to flags for the user)
if (write_overflow) begin
status[`STATUS_TRANSMIT_OVERFLOW] <= 1;
end
if (read_overflow) begin
status[`STATUS_READ_OVERFLOW] <= 1;
end
if (!read_empty) begin
//Tell the user there is data for them to read
status[`STATUS_READ_INTERRUPT] <= 1;
end
if (!write_full) begin
//Tell the user there is room available
status[`STATUS_WRITE_INTERRUPT] <= 1;
end
//Control
if (!interrupt_ready) begin
o_wbs_int <= 0;
end
//Get rid of spurious toggling of interrupts
if (o_wbs_int) begin
interrupt_sleep <= 0;
end
else if (interrupt_ready && !o_wbs_int) begin
if (interrupt_sleep < `INTERRUPT_SLEEP_TIMEOUT) begin
interrupt_sleep <= interrupt_sleep + 1;
end
else begin
o_wbs_int <= 1;
end
end
if (i_wbs_cyc == 0) begin
//at the end of a cycle disable the special case of writing to the UART FIFO
write_en <= 0;
read_en <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//Continuation of a read
if (write_en) begin
if (!o_wbs_ack) begin
$display ("WBM: Writing a byte write_count == %d, dw_countdown == %d", write_count, dw_countdown);
if (write_count > 0) begin
case (dw_countdown)
0: begin
write_data <= i_wbs_dat[7:0];
end
1: begin
write_data <= i_wbs_dat[15:8];
end
2: begin
write_data <= i_wbs_dat[23:16];
end
3: begin
write_data <= i_wbs_dat[31:24];
end
endcase
write_strobe <= 1;
if (dw_countdown == 0) begin
o_wbs_ack <= 1;
//I KNOW this code is redundant but it is more readible
dw_countdown <= 3;
end
else begin
dw_countdown <= dw_countdown - 1;
end
if (write_count <= 1) begin
o_wbs_ack <= 1;
write_en <= 0;
//Consumed all data from the user
end
else begin
write_count <= write_count - 1;
end
end
else begin
o_wbs_ack <= 1;
end
end
end
//not a continuation of a write
else begin
if (!o_wbs_ack) begin
case (i_wbs_adr)
`UART_REG_CONTROL: begin
control <= i_wbs_dat[31:0];
o_wbs_ack <= 1;
end
`UART_REG_STATUS: begin
//USER CANNOT WRITE ANYTHING TO STATUS
o_wbs_ack <= 1;
end
`UART_REG_PRESCALER: begin
//USER CANNOT WRITE ANYTHING TO PRESCALER
o_wbs_ack <= 1;
end
`UART_REG_CLOCK_DIV: begin
//the host will have to calculate out the baudrate
clock_div <= i_wbs_dat[31:0];
set_clock_div <= 1;
$display("WBM: user wrote %h", i_wbs_dat);
o_wbs_ack <= 1;
end
`UART_REG_WRITE_COUNT: begin
//USER CANNOT WRITE ANYTHING TO WRITE COUNT
o_wbs_ack <= 1;
end
`UART_REG_WRITE: begin
if (!o_wbs_ack) begin
$display ("WBM: Starting a write cycle");
//this is where the start of a UART write will begin, subsequent burst reads after this will be written to a output FIFO
//I need a flag that will inidicate that the user will be writting to the buffer
//write register
write_en <= 1;
dw_countdown <= 1;
if (i_wbs_dat[31:16] == 0) begin
write_count <= 0;
write_en <= 0;
end
else begin
write_count <= i_wbs_dat[31:16];
end
end
end
`UART_REG_READ_COUNT: begin
//USER CANNOT WRITE ANYTHING TO READ COUNT
user_read_count <= i_wbs_dat;
o_wbs_ack <= 1;
end
`UART_REG_READ: begin
//USER CANNOT WRITE ANYTHING TO THE READ
o_wbs_ack <= 1;
end
default: begin
o_wbs_ack <= 1;
end
endcase
end
end
end
else begin
if (read_en) begin
if (o_wbs_ack == 0) begin
if (read_delay > 0) begin
read_delay <= read_delay - 1;
end
else begin
$display ("WB_UART (%g): Reading a byte user_read_count == %d, local_read_count == %d", $time, user_read_count, local_read_count);
$display ("WB_UART: Data: 0x%h \"%s\"", read_data, read_data);
//I can't use a normal shift register because the first value won't be at the end if the user
//specifies anything below a multiple of 4
case (local_read_count)
0: begin
//$display ("WB_UART (%g): putting read data into the top byte", $time);
o_wbs_dat[31:24] <= read_data;
o_wbs_dat[23:0] <= 0;
read_strobe <= 1;
read_delay <= 2;
end
1: begin
o_wbs_dat[23:16] <= read_data;
read_strobe <= 1;
read_delay <= 2;
end
2: begin
o_wbs_dat[15:8] <= read_data;
read_strobe <= 1;
read_delay <= 2;
end
3: begin
o_wbs_dat[7:0] <= read_data;
read_strobe <= 1;
read_delay <= 2;
end
endcase
if (local_read_count == 3) begin
$display ("WB_UART (%g): Sending an Ack for a 32 bit data packet to the host", $time);
o_wbs_ack <= 1;
end
if (user_read_count == 0) begin
$display ("WB_UART (%g): Finished reading all the user's data", $time);
o_wbs_ack <= 1;
read_en <= 0;
end
else begin
local_read_count <= local_read_count + 1;
user_read_count <= user_read_count - 1;
end
if (read_count == 0) begin
local_read_count <= 0;
$display ("WB_UART (%g): Read FIFO is empty", $time);
o_wbs_ack <= 1;
end
end
end
end
else begin
//read request
if (!o_wbs_ack) begin
case (i_wbs_adr)
`UART_REG_CONTROL: begin
o_wbs_dat <= control;
o_wbs_ack <= 1;
end
`UART_REG_STATUS: begin
//reset all status flags on a READ
o_wbs_dat <= status;
status[`STATUS_TRANSMIT_OVERFLOW] <= 0;
status[`STATUS_READ_OVERFLOW] <= 0;
status[`STATUS_READ_UNDERFLOW] <= 0;
status[`STATUS_READ_INTERRUPT] <= 0;
status[`STATUS_WRITE_INTERRUPT] <= 0;
o_wbs_ack <= 1;
end
`UART_REG_PRESCALER: begin
o_wbs_dat <= prescaler;
o_wbs_ack <= 1;
end
`UART_REG_CLOCK_DIV: begin
if (clock_div == 0) begin
o_wbs_dat <= default_clock_div;
end
else begin
o_wbs_dat <= clock_div;
end
o_wbs_ack <= 1;
end
`UART_REG_WRITE_COUNT: begin
o_wbs_dat <= write_available;
o_wbs_ack <= 1;
end
`UART_REG_WRITE: begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 1;
end
`UART_REG_READ_COUNT: begin
o_wbs_dat <= read_count;
o_wbs_ack <= 1;
end
`UART_REG_READ: begin
$display ("WB_UART: User requested data");
if (read_count > 0) begin
read_en <= 1;
read_strobe <= 0;
//reset the 8-bit -> 32-bit converter counter
local_read_count <= 0;
o_wbs_dat <= 0;
o_wbs_dat[31:24] <= read_data;
o_wbs_dat[23:0] <= 0;
if (user_read_count > 1) begin
read_delay <= 2;
//user has specified an amount of data to read
local_read_count <= 0;
//decrement the user_read_count because we are requesting a byte right now
if (user_read_count >= 2) begin
user_read_count <= user_read_count - 1;
end
end
else begin
read_delay <= 2;
local_read_count <= 0;
user_read_count <= 0;
end
end
else begin
//no data just return 0
o_wbs_dat <= 32'h00000000;
status[`STATUS_READ_UNDERFLOW] <= 1;
end
end
default: begin
o_wbs_dat <= 32'h00000000;
end
endcase
end
end
end
if (!reading && !writing) begin
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
//-------------------------------------------------------------------------------
//--tb_FinalProject.v---------------------------------------------------------
//--By Kyle Williams, 11/20/2012-------------------------------------------------
//--PROJECT DESCRIPTION----------------------------------------------------------
//----------------Define Modules to be used--------------------------------------
`include "ClockGenerator.v"
`include "Ram.v"
`include "TestInitRam.v"
`include "Encryption.v"
`include "Decryption.v"
module tb_FinalProject
#(
parameter BYTE = 8,
parameter ADDR_WIDTH = BYTE,
parameter WORD = 4*BYTE,//4 ascii letters
parameter DATA_WIDTH = WORD,
parameter MEM_DEPTH = 256
//256 * 32 bytes = 8 kilobyte ram
);
wire clk;
wire rst;
wire[DATA_WIDTH-1:0] key;
wor wr_enaA;
wor wr_enaB;
wor[ADDR_WIDTH-1:0] addrA;
wor[ADDR_WIDTH-1:0] addrB;
wor[DATA_WIDTH-1:0] ram_inA;
wor[DATA_WIDTH-1:0] ram_inB;
wor[DATA_WIDTH-1:0] ram_outA;
wor[DATA_WIDTH-1:0] ram_outB;
wire finished;
reg enableEncryption;
wire encryptionFinished;
reg enableDecryption;
wire decryptionFinished;
wire stage1;
wire stage2;
wire stage3;
assign stage1 = finished;
assign stage2 = encryptionFinished;
assign stage3 = decryptionFinished;
always@(*)
begin
if(encryptionFinished)begin
enableEncryption <= 1'b0;
end else if(stage1)begin
enableEncryption <= 1'b1;
end
if(decryptionFinished)begin
enableDecryption <= 1'b0;
end else if(stage2)begin
enableDecryption <= 1'b1;
end
end
ClockGenerator cG(.clock(clk),
.reset(rst));
Ram #(.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MEM_DEPTH(MEM_DEPTH))
memory(.clk(clk),
.addrA(addrA),
.wr_enaA(wr_enaA),
.ram_inA(ram_inA),
.ram_outA(ram_outA),
.addrB(addrB),
.wr_enaB(wr_enaB),
.ram_inB(ram_inB),
.ram_outB(ram_outB));
TestInitRam #(.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MEM_DEPTH(MEM_DEPTH))
testMemory(.clk(clk),
.rst(rst),
.key(key),
.finished(stage1),
.addrA(addrA),
.addrB(addrB),
.wr_enaA(wr_enaA),
.wr_enaB(wr_enaB),
.data_outA(ram_inA),
.data_outB(ram_inB));
Encryption #(.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MEM_DEPTH(MEM_DEPTH))
AES (.clk(clk),
.rst(rst),
.key(key),
.ena(enableEncryption),
.finished(encryptionFinished),
.data_in(ram_outA),
.memIn_addr(addrA),
.mem_wr_ena(wr_enaB),
.memOut_addr(addrB),
.data_out(ram_inB));
Decryption #(.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MEM_DEPTH(MEM_DEPTH))
DES (.clk(clk),
.rst(rst),
.key(key),
.ena(enableDecryption),
.finished(decryptionFinished),
.data_in(ram_outA),
.memIn_addr(addrA),
.mem_wr_ena(wr_enaB),
.memOut_addr(addrB),
.data_out(ram_inB));
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_TB_V
`define SKY130_FD_SC_HD__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_hd__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_TB_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr;
reg r_reset_n;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n=1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
last_test_expr <= test_expr;
// check second clock afer reset
if (r_reset_n && (last_test_expr != test_expr)) begin
temp_expr = {1'b0,test_expr} - {1'b0,last_test_expr};
// 2's complement result
if (temp_expr[width-1:0] != value) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is increased by a value other than specified");
end
end
end
else begin
r_reset_n <= 0;
`ifdef OVL_INIT_REG
last_test_expr <= {width{1'b0}};
temp_expr = {(width+1){1'b0}};
`endif
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if(`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
(** * RecordSub: Subtyping with Records *)
(** In this chapter, we combine two significant extensions of the pure
STLC -- records (from chapter [Records]) and subtyping (from
chapter [Sub]) -- and explore their interactions. Most of the
concepts have already been discussed in those chapters, so the
presentation here is somewhat terse. We just comment where things
are nonstandard. *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Strings.String.
From PLF Require Import Maps.
From PLF Require Import Smallstep.
Module RecordSub.
(* ################################################################# *)
(** * Core Definitions *)
(* ----------------------------------------------------------------- *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| Ty_Top : ty
| Ty_Base : string -> ty
| Ty_Arrow : ty -> ty -> ty
(* record types *)
| Ty_RNil : ty
| Ty_RCons : string -> ty -> ty -> ty.
Inductive tm : Type :=
(* proper terms *)
| tm_var : string -> tm
| tm_app : tm -> tm -> tm
| tm_abs : string -> ty -> tm -> tm
| tm_rproj : tm -> string -> tm
(* record terms *)
| tm_rnil : tm
| tm_rcons : string -> tm -> tm -> tm.
Declare Custom Entry stlc.
Declare Custom Entry stlc_ty.
Notation "<{ e }>" := e (e custom stlc at level 99).
Notation "<{{ e }}>" := e (e custom stlc_ty at level 99).
Notation "( x )" := x (in custom stlc, x at level 99).
Notation "( x )" := x (in custom stlc_ty, x at level 99).
Notation "x" := x (in custom stlc at level 0, x constr at level 0).
Notation "x" := x (in custom stlc_ty at level 0, x constr at level 0).
Notation "S -> T" := (Ty_Arrow S T) (in custom stlc_ty at level 50, right associativity).
Notation "x y" := (tm_app x y) (in custom stlc at level 1, left associativity).
Notation "\ x : t , y" :=
(tm_abs x t y) (in custom stlc at level 90, x at level 99,
t custom stlc_ty at level 99,
y custom stlc at level 99,
left associativity).
Coercion tm_var : string >-> tm.
Notation "{ x }" := x (in custom stlc at level 1, x constr).
Notation "'Base' x" := (Ty_Base x) (in custom stlc_ty at level 0).
Notation " l ':' t1 '::' t2" := (Ty_RCons l t1 t2) (in custom stlc_ty at level 3, right associativity).
Notation " l := e1 '::' e2" := (tm_rcons l e1 e2) (in custom stlc at level 3, right associativity).
Notation "'nil'" := (Ty_RNil) (in custom stlc_ty).
Notation "'nil'" := (tm_rnil) (in custom stlc).
Notation "o --> l" := (tm_rproj o l) (in custom stlc at level 0).
Notation "'Top'" := (Ty_Top) (in custom stlc_ty at level 0).
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** The syntax of terms and types is a bit too loose, in the sense
that it admits things like a record type whose final "tail" is
[Top] or some arrow type rather than [Nil]. To avoid such cases,
it is useful to assume that all the record types and terms that we
see will obey some simple well-formedness conditions.
[An interesting technical question is whether the basic properties
of the system -- progress and preservation -- remain true if we
drop these conditions. I believe they do, and I would encourage
motivated readers to try to check this by dropping the conditions
from the definitions of typing and subtyping and adjusting the
proofs in the rest of the chapter accordingly. This is not a
trivial exercise (or I'd have done it!), but it should not involve
changing the basic structure of the proofs. If someone does do
it, please let me know. --BCP 5/16.] *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty <{{ nil }}>
| RTcons : forall i T1 T2,
record_ty <{{ i : T1 :: T2 }}>.
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm <{ nil }>
| rtcons : forall i t1 t2,
record_tm <{ i := t1 :: t2 }>.
Inductive well_formed_ty : ty -> Prop :=
| wfTop :
well_formed_ty <{{ Top }}>
| wfBase : forall (i : string),
well_formed_ty <{{ Base i }}>
| wfArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty <{{ T1 -> T2 }}>
| wfRNil :
well_formed_ty <{{ nil }}>
| wfRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty <{{ i : T1 :: T2 }}>.
Hint Constructors record_ty record_tm well_formed_ty : core.
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** Substitution and reduction are as before. *)
Reserved Notation "'[' x ':=' s ']' t" (in custom stlc at level 20, x constr).
Fixpoint subst (x : string) (s : tm) (t : tm) : tm :=
match t with
| tm_var y =>
if eqb_string x y then s else t
| <{\y:T, t1}> =>
if eqb_string x y then t else <{\y:T, [x:=s] t1}>
| <{t1 t2}> =>
<{([x:=s] t1) ([x:=s] t2)}>
| <{ t1 --> i }> =>
<{ ( [x := s] t1) --> i }>
| <{ nil }> =>
<{ nil }>
| <{ i := t1 :: tr }> =>
<{ i := [x := s] t1 :: ( [x := s] tr) }>
end
where "'[' x ':=' s ']' t" := (subst x s t) (in custom stlc).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T2 t1,
value <{ \ x : T2, t1 }>
| v_rnil : value <{ nil }>
| v_rcons : forall i v1 vr,
value v1 ->
value vr ->
value <{ i := v1 :: vr }>.
Hint Constructors value : core.
Fixpoint Tlookup (i:string) (Tr:ty) : option ty :=
match Tr with
| <{{ i' : T :: Tr' }}> =>
if eqb_string i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:string) (tr:tm) : option tm :=
match tr with
| <{ i' := t :: tr' }> =>
if eqb_string i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t '-->' t'" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T2 t1 v2,
value v2 ->
<{(\x:T2, t1) v2}> --> <{ [x:=v2]t1 }>
| ST_App1 : forall t1 t1' t2,
t1 --> t1' ->
<{t1 t2}> --> <{t1' t2}>
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
<{v1 t2}> --> <{v1 t2'}>
| ST_Proj1 : forall t1 t1' i,
t1 --> t1' ->
<{ t1 --> i }> --> <{ t1' --> i }>
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
<{ tr --> i }> --> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 --> t1' ->
<{ i := t1 :: tr2 }> --> <{ i := t1' :: tr2 }>
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 --> tr2' ->
<{ i := v1 :: tr2 }> --> <{ i := v1 :: tr2' }>
where "t '-->' t'" := (step t t').
Hint Constructors step : core.
(* ################################################################# *)
(** * Subtyping *)
(** Now we come to the interesting part, where the features we've
added start to interact. We begin by defining the subtyping
relation and developing some of its important technical
properties. *)
(* ================================================================= *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we sketched
in the discussion of record subtyping in chapter [Sub], but we
need to add well-formedness side conditions to some of the rules.
Also, we replace the "n-ary" width, depth, and permutation
subtyping rules by binary rules that deal with just the first
field. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
well_formed_ty S ->
S <: <{{ Top }}>
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
<{{ S1 -> S2 }}> <: <{{ T1 -> T2 }}>
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty <{{ i : T1 :: T2 }}> ->
<{{ i : T1 :: T2 }}> <: <{{ nil }}>
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
S1 <: T1 ->
Sr2 <: Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
<{{ i : S1 :: Sr2 }}> <: <{{ i : T1 :: Tr2 }}>
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty <{{ i1 : T1 :: i2 : T2 :: Tr3 }}> ->
i1 <> i2 ->
<{{ i1 : T1 :: i2 : T2 :: Tr3 }}>
<: <{{ i2 : T2 :: i1 : T1 :: Tr3 }}>
where "T '<:' U" := (subtype T U).
Hint Constructors subtype : core.
(* ================================================================= *)
(** ** Examples *)
Module Examples.
Open Scope string_scope.
Notation x := "x".
Notation y := "y".
Notation z := "z".
Notation j := "j".
Notation k := "k".
Notation i := "i".
Notation A := <{{ Base "A" }}>.
Notation B := <{{ Base "B" }}>.
Notation C := <{{ Base "C" }}>.
Definition TRcd_j :=
<{{ j : (B -> B) :: nil }}>. (* {j:B->B} *)
Definition TRcd_kj :=
<{{ k : (A -> A) :: TRcd_j }}>. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
<{{ C -> TRcd_kj }}> <: <{{ C -> nil }}>.
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get full
benefit, make sure you also understand how to prove them on
paper! *)
(** **** Exercise: 2 stars, standard (subtyping_example_1) *)
Example subtyping_example_1 :
TRcd_kj <: TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
unfold TRcd_kj.
unfold TRcd_j.
eapply S_Trans.
apply S_RcdPerm; auto. easy.
apply S_RcdDepth; auto.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (subtyping_example_2) *)
Example subtyping_example_2 :
<{{ Top -> TRcd_kj }}> <:
<{{ (C -> C) -> TRcd_j }}>.
Proof with eauto.
apply S_Arrow.
auto.
apply subtyping_example_1.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (subtyping_example_3) *)
Example subtyping_example_3 :
<{{ nil -> (j : A :: nil) }}> <:
<{{ (k : B :: nil) -> nil }}>.
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
auto.
Qed.
(** **** Exercise: 2 stars, standard (subtyping_example_4) *)
Example subtyping_example_4 :
<{{ x : A :: y : B :: z : C :: nil }}> <:
<{{ z : C :: y : B :: x : A :: nil }}>.
Proof with eauto.
eapply S_Trans.
apply S_RcdPerm... easy.
eapply S_Trans.
apply S_RcdDepth.
apply S_Refl. auto.
apply S_RcdPerm. auto. easy.
auto.
auto.
eapply S_RcdPerm... easy.
Qed.
(** [] *)
End Examples.
(* ================================================================= *)
(** ** Properties of Subtyping *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** To get started proving things about subtyping, we need a couple of
technical lemmas that intuitively (1) allow us to extract the
well-formedness assumptions embedded in subtyping derivations
and (2) record the fact that fields of well-formed record types
are themselves well-formed types. *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
induction Hsub;
intros; try (destruct IHHsub1; destruct IHHsub2)...
- (* S_RcdPerm *)
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
induction T; intros; try solve_by_invert.
- (* RCons *)
inversion H. subst. unfold Tlookup in H0.
destruct (eqb_string i s)... inversion H0; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
(** The record matching lemmas get a little more complicated in the
presence of subtyping, for two reasons. First, record types no
longer necessarily describe the exact structure of the
corresponding terms. And second, reasoning by induction on typing
derivations becomes harder in general, because typing is no longer
syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
induction Hsub; intros Ti Hget;
try solve_by_invert.
- (* S_Refl *)
exists Ti...
- (* S_Trans *)
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
- (* S_RcdDepth *)
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (eqb_string i k)...
+ (* i = k -- we're looking up the first field *)
inversion Hget. subst. exists S1...
- (* S_RcdPerm *)
exists Ti. split.
+ (* lookup *)
unfold Tlookup. unfold Tlookup in Hget.
destruct (eqb_stringP i i1)...
* (* i = i1 -- we're looking up the first field *)
destruct (eqb_stringP i i2)...
(* i = i2 -- contradictory *)
destruct H0.
subst...
+ (* subtype *)
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars, standard (rcd_types_match_informal)
Write a careful informal proof of the [rcd_types_match]
lemma. *)
(*
We want to prove that if a record type S is the subtype of record type
T, then every field in T has a subtype as the field in S.
We prove this by induction on the fact that [S <: T]. Most of the
cases are trivial to prove, we will focus on those recursive cases.
- In case where S <: U <: T for some U, By hypothesis, T include a
field i of type Ti, by the two IHs, U includes a field i of type Ui
and thus S includes field i of type Si.
Also by the IHs, Ui <: Ti and Si <: Ui, thus Si <: Ti.
- In case where S and T both have an extra field k, the field's type
satisfies Sk <: Tk and the rest of the fields Sr <: Tr.
We do a case analysis on k = i:
+ when k = i, then we already have this field (Sk) and have Sk <: Tk.
+ when k <> i, by IH, there is some i in Sr that satisfies the conditions.
- In case where S and T both have two permuted fields i1 and i2 of the same
type T1 and T2. By IH, T has field i of type Ti. We will find the same Ti
in S.
We do a case analysis on i:
+ when i = i1, then Ti = T1. Because S have {i1 : T1}, therefore S contains i2.
+ when i = i2, then Ti = T2. Because S have {i2 : T2}, therefore S contains i2.
+ when i <> i1 and i <> i2, then {i:Ti} must be found in Tr.
because S also contains Tr, thus S can also find field i of type Ti.
In all cases, the type we found Ti is always a subtype of Ti by Sub_Refl.
Qed.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_rcd_types_match_informal : option (nat*string) := None.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, standard, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
U <: <{{ V1 -> V2 }}> ->
exists U1 U2,
(U= <{{ U1 -> U2 }}> ) /\ (V1 <: U1) /\ (U2 <: V2).
Proof with eauto.
intros U V1 V2 Hs.
remember <{{ V1 -> V2 }}> as V.
generalize dependent V2. generalize dependent V1.
induction Hs; intros; try solve_by_invert; subst.
- inversion H; subst.
exists V1. exists V2. eauto.
- edestruct IHHs2... destruct H. destruct H. destruct H0. subst.
edestruct IHHs1... destruct H. destruct H. destruct H2. subst.
clear IHHs2. clear IHHs1.
exists x1. exists x2. split...
- inversion HeqV; subst. eauto.
Qed.
(** [] *)
(* ################################################################# *)
(** * Typing *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40,
t custom stlc at level 99, T custom stlc_ty at level 0).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma (x : string) T,
Gamma x = Some T ->
well_formed_ty T ->
Gamma |- x \in T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
(x |-> T11; Gamma) |- t12 \in T12 ->
Gamma |- (\ x : T11, t12) \in (T11 -> T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (T1 -> T2) ->
Gamma |- t2 \in T1 ->
Gamma |- t1 t2 \in T2
| T_Proj : forall Gamma i t T Ti,
Gamma |- t \in T ->
Tlookup i T = Some Ti ->
Gamma |- t --> i \in Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
subtype S T ->
Gamma |- t \in T
(* Rules for record terms *)
| T_RNil : forall Gamma,
Gamma |- nil \in nil
| T_RCons : forall Gamma i t T tr Tr,
Gamma |- t \in T ->
Gamma |- tr \in Tr ->
record_ty Tr ->
record_tm tr ->
Gamma |- i := t :: tr \in (i : T :: Tr)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type : core.
(* ================================================================= *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star, standard (typing_example_0) *)
Definition trcd_kj :=
<{ k := (\z : A, z) :: j := (\z : B, z) :: nil }>.
Example typing_example_0 :
empty |- trcd_kj \in TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
unfold trcd_kj.
unfold TRcd_kj.
eapply T_Sub.
apply T_RCons; auto.
apply T_Abs; auto.
apply T_Var; auto. unfold update. rewrite t_update_eq. reflexivity.
apply T_RCons; auto.
apply T_Abs; auto.
apply T_Var; auto. unfold update. rewrite t_update_eq. reflexivity.
apply S_RcdDepth; unfold TRcd_j; auto.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (typing_example_1) *)
Example typing_example_1 :
empty |- (\x : TRcd_j, x --> j) trcd_kj \in (B -> B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j)
{k=(\z:A.z), j=(\z:B.z)}
: B->B *)
Proof with eauto.
unfold TRcd_j.
unfold trcd_kj.
econstructor.
constructor; auto.
econstructor.
constructor.
unfold update; rewrite t_update_eq. auto. auto. auto.
eapply T_Sub. constructor; auto.
apply T_Abs; auto; apply T_Var; auto; unfold update; rewrite t_update_eq; auto.
constructor; auto.
apply T_Abs; auto; apply T_Var; auto; unfold update; rewrite t_update_eq; auto.
eapply S_Trans.
eapply S_RcdPerm; auto. easy.
apply S_RcdDepth; auto.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (typing_example_2) *)
Example typing_example_2 :
empty |- (\ z : (C -> C) -> TRcd_j, (z (\ x : C, x) ) --> j )
( \z : (C -> C), trcd_kj ) \in (B -> B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
unfold TRcd_j.
unfold trcd_kj.
econstructor.
constructor. auto.
econstructor.
econstructor.
apply T_Var. constructor. auto.
apply T_Abs; auto; apply T_Var; auto; unfold update; rewrite t_update_eq; auto.
constructor.
constructor.
auto.
eapply T_Sub.
repeat constructor.
eapply S_Trans.
eapply S_RcdPerm; auto. easy.
apply S_RcdDepth; auto.
Qed.
(** [] *)
End Examples2.
(* ================================================================= *)
(** ** Properties of Typing *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
induction Htyp...
- (* T_App *)
inversion IHHtyp1...
- (* T_Proj *)
eapply wf_rcd_lookup...
- (* T_Sub *)
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr --> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
empty |- v \in T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ empty |- vi \in Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. generalize dependent Ti.
induction Htyp; intros; subst; try solve_by_invert.
- (* T_Sub *)
apply (rcd_types_match S) in H0...
destruct H0 as [Si [HgetSi Hsub]].
eapply IHHtyp in HgetSi...
destruct HgetSi as [vi [Hget Htyvi]]...
- (* T_RCons *)
simpl in H0. simpl. simpl in H1.
destruct (eqb_string i i0).
+ (* i is first *)
injection H1 as H1. subst. exists t...
+ (* i in tail *)
eapply IHHtyp2 in H1...
inversion Hval... Qed.
(* ----------------------------------------------------------------- *)
(** *** Progress *)
(** **** Exercise: 3 stars, standard (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
Gamma |- s \in (T1 -> T2) ->
value s ->
exists x S1 s2,
s = <{ \ x : S1, s2 }>.
Proof with eauto.
intros.
generalize dependent H0.
remember <{{T1 -> T2}}> as V.
generalize dependent HeqV.
generalize dependent T1.
generalize dependent T2.
induction H; intros T1' T2' HeqV; intros; subst; eauto;
try solve_by_invert.
apply sub_inversion_arrow in H0.
destruct H0. destruct H0. destruct H0. destruct H2.
eauto.
Qed.
(** [] *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t --> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists <{ [x:=t2] t12 }>...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists <{ t1 t2' }> ...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists <{ t1' t2 }>...
- (* T_Proj *)
right. destruct IHHt...
+ (* rcd is value *)
destruct (lookup_field_in_value t T i Ti)
as [t' [Hget Ht']]...
+ (* rcd_steps *)
destruct H0 as [t' Hstp]. exists <{ t' --> i }>...
- (* T_RCons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. destruct H2 as [tr' Hstp].
exists <{ i := t :: tr' }>...
+ (* head steps *)
right. destruct H1 as [t' Hstp].
exists <{ i := t' :: tr}>... Qed.
(** _Theorem_ : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t --> t'] for some term [t'].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the given typing derivation.
- The cases where the last step in the typing derivation is
[T_Abs] or [T_RNil] are immediate because abstractions and
[{}] are always values. The case for [T_Var] is vacuous
because variables cannot be typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that [t =
t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 :
T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps.
- Suppose [t1 --> t1'] for some term [t1']. Then [t1 t2 -->
t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 --> t2'] for some term [t2']. Then [t1 t2 -->
t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By Lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for
some [x], [S1], and [s2]. But then [(\x:S1.s2) t2 -->
[x:=t2]s2] by [ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
are a term [tr], a type [Tr], and a label [i] such that [t =
tr.i], [empty |- tr : Tr], and [Tlookup i Tr = Some T].
By the IH, either [tr] is a value or it steps. If [tr -->
tr'] for some term [tr'], then [tr.i --> tr'.i] by rule
[ST_Proj1].
If [tr] is a value, then Lemma [lookup_field_in_value] yields
that there is a term [ti] such that [tlookup i tr = Some ti].
It follows that [tr.i --> ti] by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then
there exist some terms [t1] [tr], types [T1 Tr] and a label
[t] such that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_ty
tr], [record_tm Tr], [empty |- t1 : T1] and [empty |- tr :
Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 --> t1'] for some term [t1']. Then [{i=t1, tr}
--> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr --> tr'] for some term [tr']. Then [{i=t1,
tr} --> {i=t1, tr'}] by rule [ST_Rcd_Tail], since [t1] is
a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemma *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
Gamma |- \ x : S1, t2 \in T ->
(exists S2, <{{ S1 -> S2 }}> <: T
/\ (x |-> S1; Gamma) |- t2 \in S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember <{ \ x : S1, t2 }> as t.
induction H;
inversion Heqt; subst; intros; try solve_by_invert.
- (* T_Abs *)
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
empty |- \x : S1, s2 \in (T1 -> T2) ->
T1 <: S1
/\ (x |-> S1) |- s2 \in T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ================================================================= *)
(** ** Weakening *)
(** The weakening lemma is proved as in pure STLC. *)
Lemma weakening : forall Gamma Gamma' t T,
inclusion Gamma Gamma' ->
Gamma |- t \in T ->
Gamma' |- t \in T.
Proof.
intros Gamma Gamma' t T H Ht.
generalize dependent Gamma'.
induction Ht; eauto using inclusion_update.
Qed.
Lemma weakening_empty : forall Gamma t T,
empty |- t \in T ->
Gamma |- t \in T.
Proof.
intros Gamma t T.
eapply weakening.
discriminate.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
(x |-> U ; Gamma) |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
Proof.
intros Gamma x U t v T Ht Hv.
remember (x |-> U; Gamma) as Gamma'.
generalize dependent Gamma.
induction Ht; intros Gamma' G; simpl; eauto.
- (* T_Var *)
rename x0 into y.
destruct (eqb_stringP x y) as [Hxy|Hxy]; subst.
+ (* x = y *)
rewrite update_eq in H.
injection H as H. subst.
apply weakening_empty. assumption.
+ (* x<>y *)
apply T_Var; [|assumption].
rewrite update_neq in H; assumption.
- (* T_Abs *)
rename x0 into y. subst.
destruct (eqb_stringP x y) as [Hxy|Hxy]; apply T_Abs; try assumption.
+ (* x=y *)
subst. rewrite update_shadow in Ht. assumption.
+ (* x <> y *)
subst. apply IHHt.
rewrite update_permute; auto.
- (* rcons *) (* <=== only new case compared to pure STLC *)
apply T_RCons; eauto.
inversion H0; subst; simpl; auto.
Qed.
Theorem preservation : forall t t' T,
empty |- t \in T ->
t --> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT. generalize dependent t'.
remember empty as Gamma.
induction HT;
intros t' HE; subst;
try solve [inversion HE; subst; eauto].
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T0...
- (* T_Proj *)
inversion HE; subst...
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
- (* T_RCons *)
inversion HE; subst...
eauto using step_preserves_record_tm. Qed.
(** _Theorem_: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t --> t'], then [empty |- t' : T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and [{}] don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr --> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr --> i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = i:=t1 :: tr}], [T = i:T1 :: Tr], [record_ty tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
End RecordSub.
(* 2020-09-09 21:08 *)
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jun 27 05:23:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.5 2006/07/04 09:54:10 wig Exp $
// $Date: 2006/07/04 09:54:10 $
// $Log: ent_ba.v,v $
// Revision 1.5 2006/07/04 09:54:10 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Require Export Coq.Classes.RelationClasses.
Generalizable All Variables.
Local Obligation Tactic := simpl_relation.
Local Notation "'λ' x .. y , t" := (fun x => .. (fun y => t) ..)
(at level 200, x binder, y binder, right associativity).
Local Notation "'Π' x .. y , P" := (forall x, .. (forall y, P) ..)
(at level 200, x binder, y binder, right associativity) : type_scope.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Class Proper {A} (R : relation A) (m : A) : Prop :=
proper_prf : R m m.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Prop)
(R' : forall (x : A) (y : B), C x -> D y -> Prop) :
(forall x : A, C x) -> (forall x : B, D x) -> Prop :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful {A B : Type}
(R : relation A) (R' : relation B) : relation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Arguments Scope Proper [type_scope signature_scope].
Arguments Scope respectful [type_scope type_scope signature_scope signature_scope].
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (inverse (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Export ProperNotations.
Open Local Scope signature_scope.
(** Dependent pointwise lifting of a relation on the range. *)
Definition forall_relation {A : Type} {B : A -> Type} (sig : Π a : A, relation (B a)) : relation (Π x : A, B x) :=
λ f g, Π a : A, sig a (f a) (g a).
Arguments Scope forall_relation [type_scope type_scope signature_scope].
(** Non-dependent pointwise lifting *)
Definition pointwise_relation (A : Type) {B : Type} (R : relation B) : relation (A -> B) :=
Eval compute in forall_relation (B:=λ _, B) (λ _, R).
Lemma pointwise_pointwise A B (R : relation B) :
relation_equivalence (pointwise_relation A R) (@eq A ==> R).
Proof. intros. split. simpl_relation. firstorder. Qed.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
(** Subrelations induce a morphism on the identity. *)
Instance subrelation_id_proper `(subrelation A R₁ R₂) : Proper (R₁ ==> R₂) id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A R₂ R₁, subr : subrelation B S₁ S₂) :
subrelation (R₁ ==> S₁) (R₂ ==> S₂).
Proof. simpl_relation. apply subr. apply H. apply subl. apply H0. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl A R : @subrelation A R R.
Proof. simpl_relation. Qed.
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
(** [Proper] is itself a covariant morphism for [subrelation]. *)
Lemma subrelation_proper `(mor : Proper A R₁ m, unc : Unconvertible (relation A) R₁ R₂,
sub : subrelation A R₁ R₂) : Proper R₂ m.
Proof.
intros. apply sub. apply mor.
Qed.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
Instance proper_subrelation_proper :
Proper (subrelation ++> eq ==> impl) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_inverse_impl_subrelation : subrelation iff (inverse impl) | 2.
Proof. firstorder. Qed.
Instance pointwise_subrelation {A} `(sub : subrelation B R R') :
subrelation (pointwise_relation A R) (pointwise_relation A R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. apply H. Qed.
(** For dependent function types. *)
Lemma forall_subrelation A (B : A -> Type) (R S : forall x : A, relation (B x)) :
(forall a, subrelation (R a) (S a)) -> subrelation (forall_relation R) (forall_relation S).
Proof. reduce. apply H. apply H0. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric A R `(Symmetric A R) : subrelation (inverse R) R.
Proof. reduce. red in H0. symmetry. assumption. Qed.
Hint Extern 4 (subrelation (inverse _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
(** The complement of a relation conserves its proper elements. *)
Program Instance complement_proper
`(mR : Proper (A -> A -> Prop) (RA ==> RA ==> iff) R) :
Proper (RA ==> RA ==> iff) (complement R).
Next Obligation.
Proof.
unfold complement.
pose (mR x y H x0 y0 H0).
intuition.
Qed.
(** The [inverse] too, actually the [flip] instance is a bit more general. *)
Program Instance flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f).
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive relation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Program Instance trans_contra_co_morphism
`(Transitive A R) : Proper (R --> R ++> impl) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Program Instance trans_contra_inv_impl_morphism
`(Transitive A R) : Proper (R --> inverse impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Program Instance trans_co_impl_morphism
`(Transitive A R) : Proper (R ++> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Program Instance trans_sym_co_inv_impl_morphism
`(PER A R) : Proper (R ++> inverse impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Program Instance trans_sym_contra_impl_morphism
`(PER A R) : Proper (R --> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Program Instance per_partial_app_morphism
`(PER A R) : Proper (R ==> iff) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive relation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof
to get an [R y z] goal. *)
Program Instance trans_co_eq_inv_impl_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> inverse impl) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive relation gives rise to an equivariant morphism. *)
Program Instance PER_morphism `(PER A R) : Proper (R ==> R ==> iff) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_inverse `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Program Instance compose_proper A B C R₀ R₁ R₂ :
Proper ((R₁ ==> R₂) ==> (R₀ ==> R₁) ==> (R₀ ==> R₂)) (@compose A B C).
Next Obligation.
Proof.
simpl_relation.
unfold compose. apply H. apply H0. apply H1.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Instance reflexive_eq_dom_reflexive (A : Type) `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_relation. Qed.
(** [respectful] is a morphism for relation equivalence. *)
Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence) (@respectful A B).
Proof.
reduce.
unfold respectful, relation_equivalence, predicate_equivalence in * ; simpl in *.
split ; intros.
rewrite <- H0.
apply H1.
rewrite H.
assumption.
rewrite H0.
apply H1.
rewrite <- H.
assumption.
Qed.
(** Every element in the carrier of a reflexive relation is a morphism for this relation.
We use a proxy class for this case which is used internally to discharge reflexivity constraints.
The [Reflexive] instance will almost always be used, but it won't apply in general to any kind of
[Proper (A -> B) _ _] goal, making proof-search much slower. A cleaner solution would be to be able
to set different priorities in different hint bases and select a particular hint database for
resolution of a type class constraint.*)
Class ProperProxy {A} (R : relation A) (m : A) : Prop :=
proper_proxy : R m m.
Lemma eq_proper_proxy A (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy `(Proper A R x) : ProperProxy R x.
Proof. firstorder. Qed.
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) => not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_relation. Qed.
Class Params {A : Type} (of : A) (arity : nat).
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ; [do_partial_apps H m'|clear H]
| _ => idtac
end
in
let rec do_partial H ar m :=
match ar with
| 0 => do_partial_apps H m
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let on_morphism m :=
let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
do_partial H v' m
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ _ : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism
| _ =>
on_morphism (m x) ||
(class_apply @Reflexive_partial_app_morphism ;
[ pose Build_PartialApplication | idtac ])
end
end.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic : typeclass_instances.
Lemma inverse_respectful : forall (A : Type) (R : relation A) (B : Type) (R' : relation B),
relation_equivalence (inverse (R ==> R')) (inverse R ==> inverse R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Special-purpose class to do normalization of signatures w.r.t. inverse. *)
Class Normalizes (A : Type) (m : relation A) (m' : relation A) : Prop :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [inverse] everywhere and reduce using [subrelation]
afterwards. *)
Lemma inverse_atom A R : Normalizes A R (inverse (inverse R)).
Proof.
firstorder.
Qed.
Lemma inverse_arrow `(NA : Normalizes A R (inverse R'''), NB : Normalizes B R' (inverse R'')) :
Normalizes (A -> B) (R ==> R') (inverse (R''' ==> R'')%signature).
Proof. unfold Normalizes in *. intros.
rewrite NA, NB. firstorder.
Qed.
Ltac inverse :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @inverse_arrow
| _ => class_apply @inverse_atom
end.
Hint Extern 1 (Normalizes _ _ _) => inverse : typeclass_instances.
(** Treating inverse: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma inverse1 `(subrelation A R' R) : subrelation (inverse (inverse R')) R.
Proof. firstorder. Qed.
Lemma inverse2 `(subrelation A R R') : subrelation R (inverse (inverse R')).
Proof. firstorder. Qed.
Hint Extern 1 (subrelation (flip _) _) => class_apply @inverse1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @inverse2 : typeclass_instances.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_relation. Qed.
(* Hint Extern 3 (subrelation eq ?R) => not_evar R ; class_apply eq_subrelation : typeclass_instances. *)
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_inverse_proper `(mor : Proper A R m) : Proper (inverse R) m := mor.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_inverse_proper : typeclass_instances.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iff) (@Proper A).
Proof.
simpl_relation.
reduce in H.
split ; red ; intros.
setoid_rewrite <- H.
apply H0.
setoid_rewrite H.
apply H0.
Qed.
Lemma proper_normalizes_proper `(Normalizes A R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0.
setoid_rewrite H.
assumption.
Qed.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] => let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 6 (@Proper _ _ _) => proper_normalization : typeclass_instances.
(** Every reflexive relation gives rise to a morphism, only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A)
: Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq A (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive : typeclass_instances.
(** When the relation on the domain is symmetric, we can
inverse the relation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>inverse R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>inverse R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the relation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary relation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Instance PartialOrder_proper `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iff) R.
Proof.
intros.
apply proper_sym_impl_iff_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
generalize (partial_order_equivalence x x'); compute; intuition.
transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
intros x (_,Hx). apply Hx, Equivalence_Reflexive.
intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
apply PreOrder_Transitive with y; assumption.
intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
intros x. right. reflexivity.
intros x y z [Hxy|Hxy] [Hyz|Hyz].
left. transitivity y; auto.
left. rewrite <- Hyz; auto.
left. rewrite Hxy; auto.
right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
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* All rights reserved. *
* *
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* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
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* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module nios_system_clocks (
// Inputs
CLOCK_50,
CLOCK_27,
reset,
// Bidirectional
// Outputs
SDRAM_CLK,
VGA_CLK,
AUD_CLK,
sys_clk,
sys_reset_n
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input CLOCK_27;
input reset;
// Bidirectionals
// Outputs
output SDRAM_CLK;
output VGA_CLK;
output AUD_CLK;
output sys_clk;
output sys_reset_n;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
localparam AUD_CLK_MULT = 14;
localparam AUD_CLK_DIV = 31;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 2: 0] sys_mem_clks;
wire [ 2: 0] audio_clks;
wire clk_locked;
wire audio_clk_locked;
wire video_in_clk;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
assign video_in_clk = audio_clks[0];
assign AUD_CLK = audio_clks[1];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
// Inputs
.inclk ({1'b0, CLOCK_50}),
// Outputs
.clk (sys_mem_clks),
.locked (clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
altpll DE_Clock_Generator_Audio (
// Inputs
.inclk ({1'b0, CLOCK_27}),
// Outputs
.clk (audio_clks),
.locked (audio_clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_Audio.clk0_divide_by = 1,
DE_Clock_Generator_Audio.clk0_duty_cycle = 50,
DE_Clock_Generator_Audio.clk0_multiply_by = 1,
DE_Clock_Generator_Audio.clk0_phase_shift = "0",
DE_Clock_Generator_Audio.clk1_divide_by = AUD_CLK_DIV,
DE_Clock_Generator_Audio.clk1_duty_cycle = 50,
DE_Clock_Generator_Audio.clk1_multiply_by = AUD_CLK_MULT,
DE_Clock_Generator_Audio.clk1_phase_shift = "0",
DE_Clock_Generator_Audio.clk2_divide_by = 1,
DE_Clock_Generator_Audio.clk2_duty_cycle = 50,
DE_Clock_Generator_Audio.clk2_multiply_by = 1,
DE_Clock_Generator_Audio.clk2_phase_shift = "0",
DE_Clock_Generator_Audio.compensate_clock = "CLK0",
DE_Clock_Generator_Audio.gate_lock_signal = "NO",
DE_Clock_Generator_Audio.inclk0_input_frequency = 37037,
DE_Clock_Generator_Audio.intended_device_family = "Cyclone II",
DE_Clock_Generator_Audio.invalid_lock_multiplier = 5,
DE_Clock_Generator_Audio.lpm_type = "altpll",
DE_Clock_Generator_Audio.operation_mode = "NORMAL",
DE_Clock_Generator_Audio.pll_type = "FAST",
DE_Clock_Generator_Audio.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_areset = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_inclk0 = "PORT_USED",
DE_Clock_Generator_Audio.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_locked = "PORT_USED",
DE_Clock_Generator_Audio.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk0 = "PORT_USED",
DE_Clock_Generator_Audio.port_clk1 = "PORT_USED",
DE_Clock_Generator_Audio.port_clk2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.valid_lock_multiplier = 1;
endmodule
|
`include "../src/registers.v"
`include "../src/reg_interface.v"
`include "../src/clock.v"
`include "../src/registroDesplazable.v"
`include "../src/startStop.v"
`include "../src/i2cSlave.v"
module test_registros;
wire clk;
reg reset, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data;
reg [7:0] ir_ri0_in_data, ir_ri0_address, ir_ri1_in_data, ir_ri1_address, ir_ri2_in_data, ir_ri2_address;
reg SCL,SDA;
clock c(clk);
REG_INTERFACE reg_interface(ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data, ir_ri0_address, ir_ri1_address, ir_ri2_address, ir_ri0_in_data, ir_ri1_in_data, ir_ri2_in_data, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb, reset, clk);
///I2C
/// creacion del i2c, concetar lo que es requerido
wire pull_Down;
wire [2:0] cuenta;
wire [8:0] estado;
wire read_write;
//
i2cSlave i2c_Slave(reset,SCL,SDA,pull_Down,ir_ri2_address,ir_ri2_enb,read_write,ow_ri2_out_data,ir_ri2_in_data,estado,cuenta);
initial
begin
$dumpfile("test_registros.vcd");
$dumpvars;
reset=1;
#`PERIODO reset=0;
ir_ri0_enb=1;
ir_ri1_enb=1;
ir_ri0_address=8'h10; //direccion de alert parte alta y baja
ir_ri1_address=8'h11; //
ir_ri0_in_data=8'h00;
ir_ri1_in_data=8'h04; //escribimos la alerta de mensaje recibido
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Poner las transiciones requeridas para la lectura del alert
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
//SDA=0;
#3
SDA=0;
#2
SDA=1;#4
SDA=1;#4
SDA=0;#4
SDA=0;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=0;#4 //dir slave
SDA=1;#4//ACK
SDA=0;#4
SDA=0;#4
SDA=0;#4
SDA=0;#4
SDA=0;#4
SDA=1;#4
SDA=0;#4
SDA=1;#4 //50 la dir de registro
SDA=1;#4//ACK
///
SDA=1;#2
SDA=0;#2//repeated start
///
SDA=1;#4
SDA=1;#4
SDA=0;#4
SDA=0;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4 //dir slave
SDA=1;#4 //ACK tercero
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4
SDA=1;#4 //liberar linea para recibir byte
SDA=1;#4 //NACK
SDA=0;#2
SDA=1;#9
#`PERIODO $finish;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_c
//
// Generated
// by: wig
// on: Tue Jul 4 05:34:51 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../configuration.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_c.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_c.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_c
//
// No user `defines in this module
// Generated include statements
`include "include.h" // some include test
`define some_var somevalue
`include "include2.h"
module ent_c
//
// Generated Module inst_c
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_14;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ca
ent_ca inst_ca (
.sig_14(sig_14) // Create connection for inst_c
);
// End of Generated Instance Port Map for inst_ca
// Generated Instance Port Map for inst_cb
ent_cb inst_cb (
.sig_14(sig_14) // Create connection for inst_c
);
// End of Generated Instance Port Map for inst_cb
endmodule
//
// End of Generated Module rtl of ent_c
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file is used for simulation in chaining DMA design example
//*
//* This file is the top level of the testbench
//*/
module pcie_hip_s4gx_gen2_x4_128_chaining_testbench
;
parameter PIPE_MODE_SIM = 1'b1;
parameter TEST_LEVEL = 1;
parameter NUM_CONNECTED_LANES = 8;
parameter FAST_COUNTERS = 1'b1;
wire bfm_log_common_dummy_out;
wire bfm_req_intf_common_dummy_out;
wire bfm_shmem_common_dummy_out;
wire [ 7: 0] connected_bits;
wire [ 3: 0] connected_lanes;
wire dummy_out;
wire ep_clk250_out;
wire ep_clk500_out;
wire ep_clk_out;
wire ep_core_clk_out;
wire [ 4: 0] ep_ltssm;
wire ep_pclk_in;
wire ep_pld_clk;
wire [ 1: 0] gnd_powerdown4_ext;
wire [ 1: 0] gnd_powerdown5_ext;
wire [ 1: 0] gnd_powerdown6_ext;
wire [ 1: 0] gnd_powerdown7_ext;
wire gnd_rp_rx_in4;
wire gnd_rp_rx_in5;
wire gnd_rp_rx_in6;
wire gnd_rp_rx_in7;
wire gnd_rxpolarity4_ext;
wire gnd_rxpolarity5_ext;
wire gnd_rxpolarity6_ext;
wire gnd_rxpolarity7_ext;
wire gnd_txcompl4_ext;
wire gnd_txcompl5_ext;
wire gnd_txcompl6_ext;
wire gnd_txcompl7_ext;
wire [ 7: 0] gnd_txdata4_ext;
wire [ 7: 0] gnd_txdata5_ext;
wire [ 7: 0] gnd_txdata6_ext;
wire [ 7: 0] gnd_txdata7_ext;
wire gnd_txdatak4_ext;
wire gnd_txdatak5_ext;
wire gnd_txdatak6_ext;
wire gnd_txdatak7_ext;
wire gnd_txdetectrx4_ext;
wire gnd_txdetectrx5_ext;
wire gnd_txdetectrx6_ext;
wire gnd_txdetectrx7_ext;
wire gnd_txelecidle4_ext;
wire gnd_txelecidle5_ext;
wire gnd_txelecidle6_ext;
wire gnd_txelecidle7_ext;
wire [ 3: 0] lane_width_code;
wire local_rstn;
wire ltssm_dummy_out;
wire open_phystatus4_ext;
wire open_phystatus5_ext;
wire open_phystatus6_ext;
wire open_phystatus7_ext;
wire open_rp_tx_out4;
wire open_rp_tx_out5;
wire open_rp_tx_out6;
wire open_rp_tx_out7;
wire [ 7: 0] open_rxdata4_ext;
wire [ 7: 0] open_rxdata5_ext;
wire [ 7: 0] open_rxdata6_ext;
wire [ 7: 0] open_rxdata7_ext;
wire open_rxdatak4_ext;
wire open_rxdatak5_ext;
wire open_rxdatak6_ext;
wire open_rxdatak7_ext;
wire open_rxelecidle4_ext;
wire open_rxelecidle5_ext;
wire open_rxelecidle6_ext;
wire open_rxelecidle7_ext;
wire [ 2: 0] open_rxstatus4_ext;
wire [ 2: 0] open_rxstatus5_ext;
wire [ 2: 0] open_rxstatus6_ext;
wire [ 2: 0] open_rxstatus7_ext;
wire open_rxvalid4_ext;
wire open_rxvalid5_ext;
wire open_rxvalid6_ext;
wire open_rxvalid7_ext;
wire pcie_rstn;
wire [ 3: 0] phy_sel_code;
wire phystatus0_ext;
wire phystatus1_ext;
wire phystatus2_ext;
wire phystatus3_ext;
wire pipe_mode;
wire pipe_mode_sig2;
wire [ 1: 0] powerdown0_ext;
wire [ 1: 0] powerdown1_ext;
wire [ 1: 0] powerdown2_ext;
wire [ 1: 0] powerdown3_ext;
wire rate_ext;
wire [ 3: 0] ref_clk_sel_code;
wire refclk;
wire [ 4: 0] rp_ltssm;
wire rp_pclk;
wire rp_phystatus0_ext;
wire rp_phystatus1_ext;
wire rp_phystatus2_ext;
wire rp_phystatus3_ext;
wire rp_phystatus4_ext;
wire rp_phystatus5_ext;
wire rp_phystatus6_ext;
wire rp_phystatus7_ext;
wire [ 1: 0] rp_powerdown0_ext;
wire [ 1: 0] rp_powerdown1_ext;
wire [ 1: 0] rp_powerdown2_ext;
wire [ 1: 0] rp_powerdown3_ext;
wire [ 1: 0] rp_powerdown4_ext;
wire [ 1: 0] rp_powerdown5_ext;
wire [ 1: 0] rp_powerdown6_ext;
wire [ 1: 0] rp_powerdown7_ext;
wire rp_rate;
wire rp_rstn;
wire rp_rx_in0;
wire rp_rx_in1;
wire rp_rx_in2;
wire rp_rx_in3;
wire [ 7: 0] rp_rxdata0_ext;
wire [ 7: 0] rp_rxdata1_ext;
wire [ 7: 0] rp_rxdata2_ext;
wire [ 7: 0] rp_rxdata3_ext;
wire [ 7: 0] rp_rxdata4_ext;
wire [ 7: 0] rp_rxdata5_ext;
wire [ 7: 0] rp_rxdata6_ext;
wire [ 7: 0] rp_rxdata7_ext;
wire rp_rxdatak0_ext;
wire rp_rxdatak1_ext;
wire rp_rxdatak2_ext;
wire rp_rxdatak3_ext;
wire rp_rxdatak4_ext;
wire rp_rxdatak5_ext;
wire rp_rxdatak6_ext;
wire rp_rxdatak7_ext;
wire rp_rxelecidle0_ext;
wire rp_rxelecidle1_ext;
wire rp_rxelecidle2_ext;
wire rp_rxelecidle3_ext;
wire rp_rxelecidle4_ext;
wire rp_rxelecidle5_ext;
wire rp_rxelecidle6_ext;
wire rp_rxelecidle7_ext;
wire rp_rxpolarity0_ext;
wire rp_rxpolarity1_ext;
wire rp_rxpolarity2_ext;
wire rp_rxpolarity3_ext;
wire rp_rxpolarity4_ext;
wire rp_rxpolarity5_ext;
wire rp_rxpolarity6_ext;
wire rp_rxpolarity7_ext;
wire [ 2: 0] rp_rxstatus0_ext;
wire [ 2: 0] rp_rxstatus1_ext;
wire [ 2: 0] rp_rxstatus2_ext;
wire [ 2: 0] rp_rxstatus3_ext;
wire [ 2: 0] rp_rxstatus4_ext;
wire [ 2: 0] rp_rxstatus5_ext;
wire [ 2: 0] rp_rxstatus6_ext;
wire [ 2: 0] rp_rxstatus7_ext;
wire rp_rxvalid0_ext;
wire rp_rxvalid1_ext;
wire rp_rxvalid2_ext;
wire rp_rxvalid3_ext;
wire rp_rxvalid4_ext;
wire rp_rxvalid5_ext;
wire rp_rxvalid6_ext;
wire rp_rxvalid7_ext;
wire [ 31: 0] rp_test_in;
wire [511: 0] rp_test_out;
wire rp_tx_out0;
wire rp_tx_out1;
wire rp_tx_out2;
wire rp_tx_out3;
wire rp_txcompl0_ext;
wire rp_txcompl1_ext;
wire rp_txcompl2_ext;
wire rp_txcompl3_ext;
wire rp_txcompl4_ext;
wire rp_txcompl5_ext;
wire rp_txcompl6_ext;
wire rp_txcompl7_ext;
wire [ 7: 0] rp_txdata0_ext;
wire [ 7: 0] rp_txdata1_ext;
wire [ 7: 0] rp_txdata2_ext;
wire [ 7: 0] rp_txdata3_ext;
wire [ 7: 0] rp_txdata4_ext;
wire [ 7: 0] rp_txdata5_ext;
wire [ 7: 0] rp_txdata6_ext;
wire [ 7: 0] rp_txdata7_ext;
wire rp_txdatak0_ext;
wire rp_txdatak1_ext;
wire rp_txdatak2_ext;
wire rp_txdatak3_ext;
wire rp_txdatak4_ext;
wire rp_txdatak5_ext;
wire rp_txdatak6_ext;
wire rp_txdatak7_ext;
wire rp_txdetectrx0_ext;
wire rp_txdetectrx1_ext;
wire rp_txdetectrx2_ext;
wire rp_txdetectrx3_ext;
wire rp_txdetectrx4_ext;
wire rp_txdetectrx5_ext;
wire rp_txdetectrx6_ext;
wire rp_txdetectrx7_ext;
wire rp_txelecidle0_ext;
wire rp_txelecidle1_ext;
wire rp_txelecidle2_ext;
wire rp_txelecidle3_ext;
wire rp_txelecidle4_ext;
wire rp_txelecidle5_ext;
wire rp_txelecidle6_ext;
wire rp_txelecidle7_ext;
wire rx_in0;
wire rx_in1;
wire rx_in2;
wire rx_in3;
wire [ 7: 0] rxdata0_ext;
wire [ 7: 0] rxdata1_ext;
wire [ 7: 0] rxdata2_ext;
wire [ 7: 0] rxdata3_ext;
wire rxdatak0_ext;
wire rxdatak1_ext;
wire rxdatak2_ext;
wire rxdatak3_ext;
wire rxelecidle0_ext;
wire rxelecidle1_ext;
wire rxelecidle2_ext;
wire rxelecidle3_ext;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire [ 2: 0] rxstatus0_ext;
wire [ 2: 0] rxstatus1_ext;
wire [ 2: 0] rxstatus2_ext;
wire [ 2: 0] rxstatus3_ext;
wire rxvalid0_ext;
wire rxvalid1_ext;
wire rxvalid2_ext;
wire rxvalid3_ext;
wire [ 5: 0] swdn_out;
wire [ 39: 0] test_in;
wire [ 8: 0] test_out;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx0_ext;
wire txdetectrx1_ext;
wire txdetectrx2_ext;
wire txdetectrx3_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign gnd_rp_rx_in4 = 1;
assign gnd_rp_rx_in5 = 1;
assign gnd_rp_rx_in6 = 1;
assign gnd_rp_rx_in7 = 1;
assign ep_ltssm = test_out[4 : 0];
assign rp_ltssm = rp_test_out[324 : 320];
assign gnd_txdata4_ext = 0;
assign gnd_txdatak4_ext = 0;
assign gnd_txdetectrx4_ext = 0;
assign gnd_txelecidle4_ext = 0;
assign gnd_rxpolarity4_ext = 0;
assign gnd_txcompl4_ext = 0;
assign gnd_powerdown4_ext = 0;
assign gnd_txdata5_ext = 0;
assign gnd_txdatak5_ext = 0;
assign gnd_txdetectrx5_ext = 0;
assign gnd_txelecidle5_ext = 0;
assign gnd_rxpolarity5_ext = 0;
assign gnd_txcompl5_ext = 0;
assign gnd_powerdown5_ext = 0;
assign gnd_txdata6_ext = 0;
assign gnd_txdatak6_ext = 0;
assign gnd_txdetectrx6_ext = 0;
assign gnd_txelecidle6_ext = 0;
assign gnd_rxpolarity6_ext = 0;
assign gnd_txcompl6_ext = 0;
assign gnd_powerdown6_ext = 0;
assign gnd_txdata7_ext = 0;
assign gnd_txdatak7_ext = 0;
assign gnd_txdetectrx7_ext = 0;
assign gnd_txelecidle7_ext = 0;
assign gnd_rxpolarity7_ext = 0;
assign gnd_txcompl7_ext = 0;
assign gnd_powerdown7_ext = 0;
assign txdetectrx1_ext = txdetectrx0_ext;
assign powerdown1_ext = powerdown0_ext;
assign txdetectrx2_ext = txdetectrx0_ext;
assign powerdown2_ext = powerdown0_ext;
assign txdetectrx3_ext = txdetectrx0_ext;
assign powerdown3_ext = powerdown0_ext;
assign ep_pld_clk = ep_core_clk_out;
assign ep_clk_out = ep_pclk_in;
assign ep_pclk_in = (rate_ext == 1) ? ep_clk500_out : ep_clk250_out;
assign rp_pclk = (rp_rate == 1) ? ep_clk500_out : ep_clk250_out;
assign rx_in0 = (connected_bits[0] == 1'b1) ? rp_tx_out0 : 1;
assign rp_rx_in0 = tx_out0;
assign rx_in1 = (connected_bits[1] == 1'b1) ? rp_tx_out1 : 1;
assign rp_rx_in1 = tx_out1;
assign rx_in2 = (connected_bits[2] == 1'b1) ? rp_tx_out2 : 1;
assign rp_rx_in2 = tx_out2;
assign rx_in3 = (connected_bits[3] == 1'b1) ? rp_tx_out3 : 1;
assign rp_rx_in3 = tx_out3;
assign local_rstn = 1;
assign test_in[2 : 1] = 0;
assign test_in[8 : 4] = 0;
assign test_in[9] = 1;
assign test_in[39 : 10] = 0;
//Bit 3: Work around simulation Reciever Detect issue for Stratix IV GX
assign test_in[3] = ~pipe_mode;
//Bit 0: Speed up the simulation but making counters faster than normal
assign test_in[0] = FAST_COUNTERS;
//Compute number of lanes to hookup
assign connected_lanes = NUM_CONNECTED_LANES;
assign connected_bits = connected_lanes[3] ? 8'hFF : connected_lanes[2] ? 8'h0F : connected_lanes[1] ? 8'h03 : 8'h01;
assign rp_test_in[31 : 8] = 0;
assign rp_test_in[6] = 0;
assign rp_test_in[4] = 0;
assign rp_test_in[2 : 1] = 0;
//Bit 0: Speed up the simulation but making counters faster than normal
assign rp_test_in[0] = 1;
//Bit 3: Forces all lanes to detect the receiver
//For Stratix GX we must force but can use Rx Detect for
//the generic PIPE interface
assign rp_test_in[3] = ~pipe_mode;
//Bit 5: Disable polling.compliance
assign rp_test_in[5] = 1;
//Bit 7: Disable any entrance to low power link states (for Stratix GX)
//For Stratix GX we must disable but can use Low Power for
//the generic PIPE interface
assign rp_test_in[7] = ~pipe_mode;
//When the phy is Stratix GX we can allow the pipe_mode to be disabled
//otherwise we need to force pipe_mode on
assign pipe_mode_sig2 = PIPE_MODE_SIM;
assign pipe_mode = ((phy_sel_code == 4'h0) || (phy_sel_code == 4'h2) || (phy_sel_code == 4'h6) || (phy_sel_code == 4'h7)) ? pipe_mode_sig2 : 1'b1;
altpcietb_bfm_rp_top_x8_pipen1b rp
(
.clk250_in (ep_clk250_out),
.clk500_in (ep_clk500_out),
.local_rstn (local_rstn),
.pcie_rstn (rp_rstn),
.phystatus0_ext (rp_phystatus0_ext),
.phystatus1_ext (rp_phystatus1_ext),
.phystatus2_ext (rp_phystatus2_ext),
.phystatus3_ext (rp_phystatus3_ext),
.phystatus4_ext (rp_phystatus4_ext),
.phystatus5_ext (rp_phystatus5_ext),
.phystatus6_ext (rp_phystatus6_ext),
.phystatus7_ext (rp_phystatus7_ext),
.pipe_mode (pipe_mode),
.powerdown0_ext (rp_powerdown0_ext),
.powerdown1_ext (rp_powerdown1_ext),
.powerdown2_ext (rp_powerdown2_ext),
.powerdown3_ext (rp_powerdown3_ext),
.powerdown4_ext (rp_powerdown4_ext),
.powerdown5_ext (rp_powerdown5_ext),
.powerdown6_ext (rp_powerdown6_ext),
.powerdown7_ext (rp_powerdown7_ext),
.rate_ext (rp_rate),
.rx_in0 (rp_rx_in0),
.rx_in1 (rp_rx_in1),
.rx_in2 (rp_rx_in2),
.rx_in3 (rp_rx_in3),
.rx_in4 (gnd_rp_rx_in4),
.rx_in5 (gnd_rp_rx_in5),
.rx_in6 (gnd_rp_rx_in6),
.rx_in7 (gnd_rp_rx_in7),
.rxdata0_ext (rp_rxdata0_ext),
.rxdata1_ext (rp_rxdata1_ext),
.rxdata2_ext (rp_rxdata2_ext),
.rxdata3_ext (rp_rxdata3_ext),
.rxdata4_ext (rp_rxdata4_ext),
.rxdata5_ext (rp_rxdata5_ext),
.rxdata6_ext (rp_rxdata6_ext),
.rxdata7_ext (rp_rxdata7_ext),
.rxdatak0_ext (rp_rxdatak0_ext),
.rxdatak1_ext (rp_rxdatak1_ext),
.rxdatak2_ext (rp_rxdatak2_ext),
.rxdatak3_ext (rp_rxdatak3_ext),
.rxdatak4_ext (rp_rxdatak4_ext),
.rxdatak5_ext (rp_rxdatak5_ext),
.rxdatak6_ext (rp_rxdatak6_ext),
.rxdatak7_ext (rp_rxdatak7_ext),
.rxelecidle0_ext (rp_rxelecidle0_ext),
.rxelecidle1_ext (rp_rxelecidle1_ext),
.rxelecidle2_ext (rp_rxelecidle2_ext),
.rxelecidle3_ext (rp_rxelecidle3_ext),
.rxelecidle4_ext (rp_rxelecidle4_ext),
.rxelecidle5_ext (rp_rxelecidle5_ext),
.rxelecidle6_ext (rp_rxelecidle6_ext),
.rxelecidle7_ext (rp_rxelecidle7_ext),
.rxpolarity0_ext (rp_rxpolarity0_ext),
.rxpolarity1_ext (rp_rxpolarity1_ext),
.rxpolarity2_ext (rp_rxpolarity2_ext),
.rxpolarity3_ext (rp_rxpolarity3_ext),
.rxpolarity4_ext (rp_rxpolarity4_ext),
.rxpolarity5_ext (rp_rxpolarity5_ext),
.rxpolarity6_ext (rp_rxpolarity6_ext),
.rxpolarity7_ext (rp_rxpolarity7_ext),
.rxstatus0_ext (rp_rxstatus0_ext),
.rxstatus1_ext (rp_rxstatus1_ext),
.rxstatus2_ext (rp_rxstatus2_ext),
.rxstatus3_ext (rp_rxstatus3_ext),
.rxstatus4_ext (rp_rxstatus4_ext),
.rxstatus5_ext (rp_rxstatus5_ext),
.rxstatus6_ext (rp_rxstatus6_ext),
.rxstatus7_ext (rp_rxstatus7_ext),
.rxvalid0_ext (rp_rxvalid0_ext),
.rxvalid1_ext (rp_rxvalid1_ext),
.rxvalid2_ext (rp_rxvalid2_ext),
.rxvalid3_ext (rp_rxvalid3_ext),
.rxvalid4_ext (rp_rxvalid4_ext),
.rxvalid5_ext (rp_rxvalid5_ext),
.rxvalid6_ext (rp_rxvalid6_ext),
.rxvalid7_ext (rp_rxvalid7_ext),
.swdn_out (swdn_out),
.test_in (rp_test_in),
.test_out (rp_test_out),
.tx_out0 (rp_tx_out0),
.tx_out1 (rp_tx_out1),
.tx_out2 (rp_tx_out2),
.tx_out3 (rp_tx_out3),
.tx_out4 (open_rp_tx_out4),
.tx_out5 (open_rp_tx_out5),
.tx_out6 (open_rp_tx_out6),
.tx_out7 (open_rp_tx_out7),
.txcompl0_ext (rp_txcompl0_ext),
.txcompl1_ext (rp_txcompl1_ext),
.txcompl2_ext (rp_txcompl2_ext),
.txcompl3_ext (rp_txcompl3_ext),
.txcompl4_ext (rp_txcompl4_ext),
.txcompl5_ext (rp_txcompl5_ext),
.txcompl6_ext (rp_txcompl6_ext),
.txcompl7_ext (rp_txcompl7_ext),
.txdata0_ext (rp_txdata0_ext),
.txdata1_ext (rp_txdata1_ext),
.txdata2_ext (rp_txdata2_ext),
.txdata3_ext (rp_txdata3_ext),
.txdata4_ext (rp_txdata4_ext),
.txdata5_ext (rp_txdata5_ext),
.txdata6_ext (rp_txdata6_ext),
.txdata7_ext (rp_txdata7_ext),
.txdatak0_ext (rp_txdatak0_ext),
.txdatak1_ext (rp_txdatak1_ext),
.txdatak2_ext (rp_txdatak2_ext),
.txdatak3_ext (rp_txdatak3_ext),
.txdatak4_ext (rp_txdatak4_ext),
.txdatak5_ext (rp_txdatak5_ext),
.txdatak6_ext (rp_txdatak6_ext),
.txdatak7_ext (rp_txdatak7_ext),
.txdetectrx0_ext (rp_txdetectrx0_ext),
.txdetectrx1_ext (rp_txdetectrx1_ext),
.txdetectrx2_ext (rp_txdetectrx2_ext),
.txdetectrx3_ext (rp_txdetectrx3_ext),
.txdetectrx4_ext (rp_txdetectrx4_ext),
.txdetectrx5_ext (rp_txdetectrx5_ext),
.txdetectrx6_ext (rp_txdetectrx6_ext),
.txdetectrx7_ext (rp_txdetectrx7_ext),
.txelecidle0_ext (rp_txelecidle0_ext),
.txelecidle1_ext (rp_txelecidle1_ext),
.txelecidle2_ext (rp_txelecidle2_ext),
.txelecidle3_ext (rp_txelecidle3_ext),
.txelecidle4_ext (rp_txelecidle4_ext),
.txelecidle5_ext (rp_txelecidle5_ext),
.txelecidle6_ext (rp_txelecidle6_ext),
.txelecidle7_ext (rp_txelecidle7_ext)
);
altpcietb_bfm_driver_chaining drvr
(
.INTA (swdn_out[0]),
.INTB (swdn_out[1]),
.INTC (swdn_out[2]),
.INTD (swdn_out[3]),
.clk_in (rp_pclk),
.dummy_out (dummy_out),
.rstn (pcie_rstn)
);
defparam drvr.TEST_LEVEL = 1;
altpcietb_ltssm_mon ltssm_mon
(
.dummy_out (ltssm_dummy_out),
.ep_ltssm (ep_ltssm),
.rp_clk (rp_pclk),
.rp_ltssm (rp_ltssm),
.rstn (pcie_rstn)
);
pcie_hip_s4gx_gen2_x4_128_example_chaining_pipen1b ep
(
.clk250_out (ep_clk250_out),
.clk500_out (ep_clk500_out),
.core_clk_out (ep_core_clk_out),
.free_100MHz (refclk),
.lane_width_code (lane_width_code),
.local_rstn (local_rstn),
.pcie_rstn (pcie_rstn),
.pclk_in (ep_pclk_in),
.phy_sel_code (phy_sel_code),
.phystatus_ext (phystatus0_ext),
.pipe_mode (pipe_mode),
.pld_clk (ep_pld_clk),
.powerdown_ext (powerdown0_ext),
.rate_ext (rate_ext),
.ref_clk_sel_code (ref_clk_sel_code),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.test_in (test_in),
.test_out_icm (test_out),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx0_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
altpcietb_bfm_log_common bfm_log_common
(
.dummy_out (bfm_log_common_dummy_out)
);
altpcietb_bfm_req_intf_common bfm_req_intf_common
(
.dummy_out (bfm_req_intf_common_dummy_out)
);
altpcietb_bfm_shmem_common bfm_shmem_common
(
.dummy_out (bfm_shmem_common_dummy_out)
);
altpcietb_pipe_phy lane0
(
.A_lane_conn (connected_bits[0]),
.A_phystatus (phystatus0_ext),
.A_powerdown (powerdown0_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata0_ext),
.A_rxdatak (rxdatak0_ext),
.A_rxelecidle (rxelecidle0_ext),
.A_rxpolarity (rxpolarity0_ext),
.A_rxstatus (rxstatus0_ext),
.A_rxvalid (rxvalid0_ext),
.A_txcompl (txcompl0_ext),
.A_txdata (txdata0_ext),
.A_txdatak (txdatak0_ext),
.A_txdetectrx (txdetectrx0_ext),
.A_txelecidle (txelecidle0_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus0_ext),
.B_powerdown (rp_powerdown0_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata0_ext),
.B_rxdatak (rp_rxdatak0_ext),
.B_rxelecidle (rp_rxelecidle0_ext),
.B_rxpolarity (rp_rxpolarity0_ext),
.B_rxstatus (rp_rxstatus0_ext),
.B_rxvalid (rp_rxvalid0_ext),
.B_txcompl (rp_txcompl0_ext),
.B_txdata (rp_txdata0_ext),
.B_txdatak (rp_txdatak0_ext),
.B_txdetectrx (rp_txdetectrx0_ext),
.B_txelecidle (rp_txelecidle0_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane0.APIPE_WIDTH = 8,
lane0.BPIPE_WIDTH = 8,
lane0.LANE_NUM = 0;
altpcietb_pipe_phy lane1
(
.A_lane_conn (connected_bits[1]),
.A_phystatus (phystatus1_ext),
.A_powerdown (powerdown1_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata1_ext),
.A_rxdatak (rxdatak1_ext),
.A_rxelecidle (rxelecidle1_ext),
.A_rxpolarity (rxpolarity1_ext),
.A_rxstatus (rxstatus1_ext),
.A_rxvalid (rxvalid1_ext),
.A_txcompl (txcompl1_ext),
.A_txdata (txdata1_ext),
.A_txdatak (txdatak1_ext),
.A_txdetectrx (txdetectrx1_ext),
.A_txelecidle (txelecidle1_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus1_ext),
.B_powerdown (rp_powerdown1_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata1_ext),
.B_rxdatak (rp_rxdatak1_ext),
.B_rxelecidle (rp_rxelecidle1_ext),
.B_rxpolarity (rp_rxpolarity1_ext),
.B_rxstatus (rp_rxstatus1_ext),
.B_rxvalid (rp_rxvalid1_ext),
.B_txcompl (rp_txcompl1_ext),
.B_txdata (rp_txdata1_ext),
.B_txdatak (rp_txdatak1_ext),
.B_txdetectrx (rp_txdetectrx1_ext),
.B_txelecidle (rp_txelecidle1_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane1.APIPE_WIDTH = 8,
lane1.BPIPE_WIDTH = 8,
lane1.LANE_NUM = 1;
altpcietb_pipe_phy lane2
(
.A_lane_conn (connected_bits[2]),
.A_phystatus (phystatus2_ext),
.A_powerdown (powerdown2_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata2_ext),
.A_rxdatak (rxdatak2_ext),
.A_rxelecidle (rxelecidle2_ext),
.A_rxpolarity (rxpolarity2_ext),
.A_rxstatus (rxstatus2_ext),
.A_rxvalid (rxvalid2_ext),
.A_txcompl (txcompl2_ext),
.A_txdata (txdata2_ext),
.A_txdatak (txdatak2_ext),
.A_txdetectrx (txdetectrx2_ext),
.A_txelecidle (txelecidle2_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus2_ext),
.B_powerdown (rp_powerdown2_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata2_ext),
.B_rxdatak (rp_rxdatak2_ext),
.B_rxelecidle (rp_rxelecidle2_ext),
.B_rxpolarity (rp_rxpolarity2_ext),
.B_rxstatus (rp_rxstatus2_ext),
.B_rxvalid (rp_rxvalid2_ext),
.B_txcompl (rp_txcompl2_ext),
.B_txdata (rp_txdata2_ext),
.B_txdatak (rp_txdatak2_ext),
.B_txdetectrx (rp_txdetectrx2_ext),
.B_txelecidle (rp_txelecidle2_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane2.APIPE_WIDTH = 8,
lane2.BPIPE_WIDTH = 8,
lane2.LANE_NUM = 2;
altpcietb_pipe_phy lane3
(
.A_lane_conn (connected_bits[3]),
.A_phystatus (phystatus3_ext),
.A_powerdown (powerdown3_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata3_ext),
.A_rxdatak (rxdatak3_ext),
.A_rxelecidle (rxelecidle3_ext),
.A_rxpolarity (rxpolarity3_ext),
.A_rxstatus (rxstatus3_ext),
.A_rxvalid (rxvalid3_ext),
.A_txcompl (txcompl3_ext),
.A_txdata (txdata3_ext),
.A_txdatak (txdatak3_ext),
.A_txdetectrx (txdetectrx3_ext),
.A_txelecidle (txelecidle3_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus3_ext),
.B_powerdown (rp_powerdown3_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata3_ext),
.B_rxdatak (rp_rxdatak3_ext),
.B_rxelecidle (rp_rxelecidle3_ext),
.B_rxpolarity (rp_rxpolarity3_ext),
.B_rxstatus (rp_rxstatus3_ext),
.B_rxvalid (rp_rxvalid3_ext),
.B_txcompl (rp_txcompl3_ext),
.B_txdata (rp_txdata3_ext),
.B_txdatak (rp_txdatak3_ext),
.B_txdetectrx (rp_txdetectrx3_ext),
.B_txelecidle (rp_txelecidle3_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane3.APIPE_WIDTH = 8,
lane3.BPIPE_WIDTH = 8,
lane3.LANE_NUM = 3;
altpcietb_pipe_phy lane4
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus4_ext),
.A_powerdown (gnd_powerdown4_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata4_ext),
.A_rxdatak (open_rxdatak4_ext),
.A_rxelecidle (open_rxelecidle4_ext),
.A_rxpolarity (gnd_rxpolarity4_ext),
.A_rxstatus (open_rxstatus4_ext),
.A_rxvalid (open_rxvalid4_ext),
.A_txcompl (gnd_txcompl4_ext),
.A_txdata (gnd_txdata4_ext),
.A_txdatak (gnd_txdatak4_ext),
.A_txdetectrx (gnd_txdetectrx4_ext),
.A_txelecidle (gnd_txelecidle4_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus4_ext),
.B_powerdown (rp_powerdown4_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata4_ext),
.B_rxdatak (rp_rxdatak4_ext),
.B_rxelecidle (rp_rxelecidle4_ext),
.B_rxpolarity (rp_rxpolarity4_ext),
.B_rxstatus (rp_rxstatus4_ext),
.B_rxvalid (rp_rxvalid4_ext),
.B_txcompl (rp_txcompl4_ext),
.B_txdata (rp_txdata4_ext),
.B_txdatak (rp_txdatak4_ext),
.B_txdetectrx (rp_txdetectrx4_ext),
.B_txelecidle (rp_txelecidle4_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane4.APIPE_WIDTH = 8,
lane4.BPIPE_WIDTH = 8,
lane4.LANE_NUM = 4;
altpcietb_pipe_phy lane5
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus5_ext),
.A_powerdown (gnd_powerdown5_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata5_ext),
.A_rxdatak (open_rxdatak5_ext),
.A_rxelecidle (open_rxelecidle5_ext),
.A_rxpolarity (gnd_rxpolarity5_ext),
.A_rxstatus (open_rxstatus5_ext),
.A_rxvalid (open_rxvalid5_ext),
.A_txcompl (gnd_txcompl5_ext),
.A_txdata (gnd_txdata5_ext),
.A_txdatak (gnd_txdatak5_ext),
.A_txdetectrx (gnd_txdetectrx5_ext),
.A_txelecidle (gnd_txelecidle5_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus5_ext),
.B_powerdown (rp_powerdown5_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata5_ext),
.B_rxdatak (rp_rxdatak5_ext),
.B_rxelecidle (rp_rxelecidle5_ext),
.B_rxpolarity (rp_rxpolarity5_ext),
.B_rxstatus (rp_rxstatus5_ext),
.B_rxvalid (rp_rxvalid5_ext),
.B_txcompl (rp_txcompl5_ext),
.B_txdata (rp_txdata5_ext),
.B_txdatak (rp_txdatak5_ext),
.B_txdetectrx (rp_txdetectrx5_ext),
.B_txelecidle (rp_txelecidle5_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane5.APIPE_WIDTH = 8,
lane5.BPIPE_WIDTH = 8,
lane5.LANE_NUM = 5;
altpcietb_pipe_phy lane6
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus6_ext),
.A_powerdown (gnd_powerdown6_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata6_ext),
.A_rxdatak (open_rxdatak6_ext),
.A_rxelecidle (open_rxelecidle6_ext),
.A_rxpolarity (gnd_rxpolarity6_ext),
.A_rxstatus (open_rxstatus6_ext),
.A_rxvalid (open_rxvalid6_ext),
.A_txcompl (gnd_txcompl6_ext),
.A_txdata (gnd_txdata6_ext),
.A_txdatak (gnd_txdatak6_ext),
.A_txdetectrx (gnd_txdetectrx6_ext),
.A_txelecidle (gnd_txelecidle6_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus6_ext),
.B_powerdown (rp_powerdown6_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata6_ext),
.B_rxdatak (rp_rxdatak6_ext),
.B_rxelecidle (rp_rxelecidle6_ext),
.B_rxpolarity (rp_rxpolarity6_ext),
.B_rxstatus (rp_rxstatus6_ext),
.B_rxvalid (rp_rxvalid6_ext),
.B_txcompl (rp_txcompl6_ext),
.B_txdata (rp_txdata6_ext),
.B_txdatak (rp_txdatak6_ext),
.B_txdetectrx (rp_txdetectrx6_ext),
.B_txelecidle (rp_txelecidle6_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane6.APIPE_WIDTH = 8,
lane6.BPIPE_WIDTH = 8,
lane6.LANE_NUM = 6;
altpcietb_pipe_phy lane7
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus7_ext),
.A_powerdown (gnd_powerdown7_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata7_ext),
.A_rxdatak (open_rxdatak7_ext),
.A_rxelecidle (open_rxelecidle7_ext),
.A_rxpolarity (gnd_rxpolarity7_ext),
.A_rxstatus (open_rxstatus7_ext),
.A_rxvalid (open_rxvalid7_ext),
.A_txcompl (gnd_txcompl7_ext),
.A_txdata (gnd_txdata7_ext),
.A_txdatak (gnd_txdatak7_ext),
.A_txdetectrx (gnd_txdetectrx7_ext),
.A_txelecidle (gnd_txelecidle7_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus7_ext),
.B_powerdown (rp_powerdown7_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata7_ext),
.B_rxdatak (rp_rxdatak7_ext),
.B_rxelecidle (rp_rxelecidle7_ext),
.B_rxpolarity (rp_rxpolarity7_ext),
.B_rxstatus (rp_rxstatus7_ext),
.B_rxvalid (rp_rxvalid7_ext),
.B_txcompl (rp_txcompl7_ext),
.B_txdata (rp_txdata7_ext),
.B_txdatak (rp_txdatak7_ext),
.B_txdetectrx (rp_txdetectrx7_ext),
.B_txelecidle (rp_txelecidle7_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane7.APIPE_WIDTH = 8,
lane7.BPIPE_WIDTH = 8,
lane7.LANE_NUM = 7;
altpcietb_rst_clk rst_clk_gen
(
.ep_core_clk_out (ep_core_clk_out),
.pcie_rstn (pcie_rstn),
.ref_clk_out (refclk),
.ref_clk_sel_code (ref_clk_sel_code),
.rp_rstn (rp_rstn)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:39:56 02/27/2014
// Design Name:
// Module Name: seven_seg_dev
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_seg (
clk,
clr,
disp_num,
Scanning,
SW,
AN,
SEGMENT
);
input wire clk, clr;
input wire [ 1: 0] Scanning;
input wire [ 1: 0] SW;
input wire [31: 0] disp_num;
output reg [ 3: 0] AN;
output wire [ 7: 0] SEGMENT;
reg [ 3: 0] digit = 4'h0;
reg [ 7: 0] temp_seg = 8'h0,
digit_seg = 8'h0;
wire [15: 0] disp_current;
assign SEGMENT = SW[0] ? digit_seg : temp_seg; // 0: Pic mode, 1: Text mode
assign disp_current = SW[1] ? disp_num[31:16] : disp_num[15:0]; // 0: Low, 1: High
// 7-Seg docode
always @(posedge clk)begin
case (digit)
4'h0: digit_seg = 8'b10000001;
4'h1: digit_seg = 8'b11001111;
4'h2: digit_seg = 8'b10010010;
4'h3: digit_seg = 8'b10000110;
4'h4: digit_seg = 8'b11001100;
4'h5: digit_seg = 8'b10100100;
4'h6: digit_seg = 8'b10100000;
4'h7: digit_seg = 8'b10001111;
4'h8: digit_seg = 8'b10000000;
4'h9: digit_seg = 8'b10000100;
4'hA: digit_seg = 8'b10001000;
4'hB: digit_seg = 8'b11100000;
4'hC: digit_seg = 8'b10110001;
4'hD: digit_seg = 8'b11000010;
4'hE: digit_seg = 8'b10110000;
4'hF: digit_seg = 8'b10111000;
default: digit_seg = 8'b00000000;
endcase
end
always @(posedge clk)begin
case (Scanning) // temp_seg for Pic mode
0: begin // disp_num[ 7: 0]
digit = disp_current[ 3: 0]; // TextMode: D[ 3: 0] or D[19:16]
temp_seg = { disp_num[24], disp_num[ 0], disp_num[ 4], disp_num[16],
disp_num[25], disp_num[17], disp_num[ 5], disp_num[12]};
AN = 4'b1110;
end
1: begin // disp_num[15:8]
digit = disp_current[ 7: 4]; // TextMode: D[ 7: 4] or D[23:20]
temp_seg = { disp_num[26], disp_num[ 1], disp_num[ 6], disp_num[18],
disp_num[27], disp_num[19], disp_num[ 7], disp_num[13]};
AN = 4'b1101;
end
2: begin // disp_num[23:16]
digit = disp_current[11: 8]; // TextMode: D[11: 8] or D[27:24]
temp_seg = { disp_num[28], disp_num[ 2], disp_num[ 8], disp_num[20],
disp_num[29], disp_num[21], disp_num[ 9], disp_num[14]};
AN = 4'b1011;
end
3: begin // disp_num[31:24]
digit = disp_current[15:12]; // TextMode: D[15:2] or D[31:28]
temp_seg = { disp_num[30], disp_num[ 3], disp_num[10], disp_num[22],
disp_num[31], disp_num[23], disp_num[11], disp_num[15]};
AN = 4'b0111;
end
endcase
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_padder;
// Inputs
reg clk;
reg reset;
reg [63:0] in;
reg in_ready;
reg is_last;
reg [2:0] byte_num;
reg f_ack;
// Outputs
wire buffer_full;
wire [575:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
padder uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready),
.f_ack(f_ack)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
f_ack = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// pad an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
if (buffer_full !== 0) error;
in_ready = 1;
is_last = 1;
#(`P);
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check({8'h1, 560'h0, 8'h80});
f_ack = 1; #(`P); f_ack = 0;
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should be 0
end
// pad an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
if (out_ready !== 1) error;
check({9{64'h1234567890ABCDEF}});
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 64'h999; // should not eat this
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
f_ack = 1; #(`P); f_ack = 0;
if (out_ready !== 0) error;
// feed next (576-16) bit
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF; #(`P);
end
byte_num = 6;
is_last = 1;
in = 64'h1234567890ABCDEF; #(`P);
if (out_ready !== 1) error;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
is_last = 0;
// eat these bits
f_ack = 1; #(`P); f_ack = 0;
// should not provide any more bits, if user provides nothing
in_ready = 0;
is_last = 0;
for (i=0; i<10; i=i+1)
begin
if (out_ready === 1) error;
#(`P);
end
in_ready = 0;
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [575:0] wish;
begin
if (out !== wish)
begin
$display("out:%h wish:%h", out, wish);
error;
end
end
endtask
endmodule
`undef P
|
`default_nettype none
`define WIDTH 16
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [`WIDTH-1:0] dout,
input wire [`WIDTH-1:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn);
reg [4:0] dsp, dspN; // data stack pointer
reg [`WIDTH-1:0] st0, st0N; // top of data stack
reg dstkW; // data stack write
reg [12:0] pc /* verilator public_flat */, pcN; // program counter
wire [12:0] pc_plus_1 = pc + 13'd1;
reg rstkW; // return stack write
wire [`WIDTH-1:0] rstkD; // return stack write value
reg reboot = 1;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(19)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
// stack2 #(.DEPTH(24)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
// stack2 #(.DEPTH(24)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
always @*
begin
// Compute the new value of st0
casez ({pc[12], insn[15:8]})
9'b1_???_?????: st0N = insn; // literal
9'b0_1??_?????: st0N = { {(`WIDTH - 15){1'b0}}, insn[14:0] }; // literal
9'b0_000_?????: st0N = st0; // jump
9'b0_010_?????: st0N = st0; // call
9'b0_001_?????: st0N = st1; // conditional jump
9'b0_011_?0000: st0N = st0; // ALU operations...
9'b0_011_?0001: st0N = st1;
9'b0_011_?0010: st0N = st0 + st1;
9'b0_011_?0011: st0N = st0 & st1;
9'b0_011_?0100: st0N = st0 | st1;
9'b0_011_?0101: st0N = st0 ^ st1;
9'b0_011_?0110: st0N = ~st0;
9'b0_011_?0111: st0N = {`WIDTH{(st1 == st0)}};
9'b0_011_?1000: st0N = {`WIDTH{($signed(st1) < $signed(st0))}};
9'b0_011_?1001: st0N = {st0[`WIDTH - 1], st0[`WIDTH - 1:1]};
9'b0_011_?1010: st0N = {st0[`WIDTH - 2:0], 1'b0};
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = io_din;
9'b0_011_?1101: st0N = io_din;
9'b0_011_?1110: st0N = {{(`WIDTH - 5){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(st1 < st0)}};
default: st0N = {`WIDTH{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire is_alu = !pc[12] & (insn[15:13] == 3'b011);
assign mem_wr = !reboot & is_alu & func_write;
assign dout = st1;
assign io_wr = !reboot & is_alu & func_iow;
assign io_rd = !reboot & is_alu & func_ior;
assign rstkD = (insn[13] == 1'b0) ? {{(`WIDTH - 14){1'b0}}, pc_plus_1, 1'b0} : st0;
always @*
begin
casez ({pc[12], insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({pc[12], insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
casez ({reboot, pc[12], insn[15:13], insn[7], |st0})
7'b1_0_???_?_?: pcN = 0;
7'b0_0_000_?_?,
7'b0_0_010_?_?,
7'b0_0_001_?_0: pcN = insn[12:0];
7'b0_1_???_?_?,
7'b0_0_011_1_?: pcN = rst0[13:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
reboot <= 1'b1;
{ pc, dsp, st0} <= 0;
end else begin
reboot <= 0;
{ pc, dsp, st0} <= { pcN, dspN, st0N };
end
end
endmodule
|
`timescale 1ns/1ns
module test_mips (/*port details*/);
reg clk,rst,clk_i;
integer i;
wire [31:2] PrAddr;
wire [3:0] PrBe;
wire [31:0] PrWD;
wire [31:0] PrRD;
wire [7:2] HWInt;
wire [31:0] Dev1_RD;
wire [31:0] Dev2_RD;
wire Dev1_Irq,Dev2_Irq;
wire [3:2] DevAddr;
wire [31:0] DevWd;
wire Dev1_WE,Dev2_WE;
mips _mips(clk,rst,PrAddr,PrBe,PrRD,PrWD,HWInt);
bridge _bridge(PrAddr,PrBe,PrWD,PrRD,HWInt,DevAddr,Dev1_WE,Dev1_RD,Dev1_Irq,Dev2_WE,Dev2_RD,Dev2_Irq,DevWd);
coco_timer _coco_timer1(clk_i,rst,DevAddr,Dev1_WE,DevWd,Dev1_RD,Dev1_Irq);
coco_timer _coco_timer2(clk_i,rst,DevAddr,Dev2_WE,DevWd,Dev2_RD,Dev2_Irq);
always #5 clk=~clk;
always #5 clk_i=~clk_i;
initial begin
clk=1;
clk_i=1;
rst=1;
#3 rst=0;
end
initial begin
#10000 $finish;
end
initial begin
/*$monitor("%t IF(%x) ID(%x) EX(%x) MEM(%x) WB(%x)",$time,
_mips.instr,_mips.instrD,_mips.instrE,_mips.instrM,_mips.instrW);*/
#9999
for (i=0; i!=2048; i=i+8) begin
$display("%x %x %x %x %x %x %x %x",
_mips._dm._dm[i],
_mips._dm._dm[i+1],
_mips._dm._dm[i+2],
_mips._dm._dm[i+3],
_mips._dm._dm[i+4],
_mips._dm._dm[i+5],
_mips._dm._dm[i+6],
_mips._dm._dm[i+7]);
end
end
initial begin
$dumpfile("test.lxt");
$dumpvars(0,test_mips);
end
endmodule // test_mips
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Tue Mar 8 16:35:05 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_BEHAVIORAL_V |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_1024_134.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_1024_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output rdempty;
output [10:0] rdusedw;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire sub_wire1;
wire [10:0] sub_wire2;
wire [10:0] sub_wire3;
wire [133:0] q = sub_wire0[133:0];
wire rdempty = sub_wire1;
wire [10:0] rdusedw = sub_wire2[10:0];
wire [10:0] wrusedw = sub_wire3[10:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL "rdusedw[10..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_1024_134_bb.v FALSE
|
//
// Written by Synplify
// Product Version "H-2013.03-SP1-1 "
// Program "Synplify Premier", Mapper "map201303sp1_1rc, Build 007R"
// Thu Feb 5 14:25:36 2015
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/std.vhd "
// file 2 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/snps_haps_pkg.vhd "
// file 3 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/std1164.vhd "
// file 4 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/numeric.vhd "
// file 5 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/umr_capim.vhd "
// file 6 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/arith.vhd "
// file 7 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vhd/unsigned.vhd "
// file 8 "\/home/david/projects/faultify_github/faultify/hardware/testcases/FIR/src/fir.vhd "
// file 9 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/xilinx/unisim.v "
// file 10 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/umr_capim.v "
// file 11 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/scemi_objects.v "
// file 12 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/scemi_pipes.svh "
// file 13 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/hypermods.v "
// file 14 "\/home/david/projects/faultify_github/faultify/hardware/testcases/FIR/fpga_syn/rev_1/syntmp/multadd.v "
// file 15 "\/home/david/projects/faultify_github/faultify/hardware/testcases/FIR/fpga_syn/rev_1/syntmp/unisim.v "
`timescale 100 ps/100 ps
module fir (
x_in,
clk,
y
)
;
/* Synopsys
.origName=fir
.langParams="N"
N=16
*/
input [7:0] x_in ;
input clk ;
output [7:0] y ;
wire clk ;
wire [7:0] x_0;
wire [15:4] un1_x_1;
wire [15:5] un1_x_2;
wire [15:4] un1_x_3;
wire [7:0] x_4;
wire [15:2] un1_x_4;
wire [14:0] un84_sop_0_0_0_0_5;
wire [7:0] x_7;
wire [7:0] x_8;
wire [0:0] x_9;
wire [7:0] x_12;
wire [7:0] x_13;
wire [9:0] un84_sop_0_0_0_0_0;
wire [9:0] un84_sop_0_0_0_0_1;
wire [15:4] un1_x_14_0_0;
wire [15:5] un1_x_13_0_0;
wire [15:4] un1_x_12_0_0;
wire [14:7] un1_x_11_0_0;
wire [14:0] un84_sop_0_0_0_10_0;
wire [15:8] un1_x_10_0_0;
wire [15:5] un1_x_9_0;
wire [15:4] un1_x_8_0;
wire [15:2] un1_x_7_0;
wire [15:1] un1_x_6_0;
wire [14:0] un84_sop_0_0_0_5_0;
wire [47:11] P_uc;
wire [29:0] ACOUT;
wire [3:0] CARRYOUT;
wire [47:0] PCOUT;
wire [47:11] P_uc_0;
wire [29:0] ACOUT_0;
wire [3:0] CARRYOUT_0;
wire [47:0] PCOUT_0;
wire [47:11] P_uc_1;
wire [29:0] ACOUT_1;
wire [17:0] BCOUT_1;
wire [3:0] CARRYOUT_1;
wire [47:0] PCOUT_1;
wire [47:12] P_uc_2;
wire [29:0] ACOUT_2;
wire [3:0] CARRYOUT_2;
wire [47:0] PCOUT_2;
wire [47:12] P_uc_3;
wire [29:0] ACOUT_3;
wire [3:0] CARRYOUT_3;
wire [47:0] PCOUT_3;
wire [47:12] P_uc_4;
wire [29:0] ACOUT_4;
wire [3:0] CARRYOUT_4;
wire [47:0] PCOUT_4;
wire [47:12] P_uc_5;
wire [29:0] ACOUT_5;
wire [3:0] CARRYOUT_5;
wire [47:0] PCOUT_5;
wire [47:12] P_uc_6;
wire [29:0] ACOUT_6;
wire [3:0] CARRYOUT_6;
wire [47:0] PCOUT_6;
wire [47:14] P_uc_7;
wire [29:0] ACOUT_7;
wire [3:0] CARRYOUT_7;
wire [47:0] PCOUT_7;
wire [47:14] P_uc_8;
wire [29:0] ACOUT_8;
wire [3:0] CARRYOUT_8;
wire [47:0] PCOUT_8;
wire [47:15] P_uc_9;
wire [29:0] ACOUT_9;
wire [17:0] BCOUT_9;
wire [3:0] CARRYOUT_9;
wire [47:0] PCOUT_9;
wire [7:0] x_10_0;
wire [7:7] x_10_1;
wire [7:7] x_10_2;
wire [7:7] x_10_3;
wire [7:7] x_10_4;
wire [7:7] x_10_5;
wire [7:7] x_10_6;
wire [7:7] x_10_7;
wire [7:7] x_10_8;
wire [7:7] x_10_9;
wire [7:7] x_10_10;
wire [7:0] x_9_0;
wire [7:7] x_9_1;
wire [7:7] x_9_2;
wire [7:7] x_9_3;
wire [7:7] x_9_4;
wire [7:7] x_9_5;
wire [7:7] x_9_6;
wire [7:7] x_9_7;
wire [7:7] x_9_8;
wire [7:7] x_9_9;
wire [7:7] x_9_10;
wire [7:0] x_6_0;
wire [7:7] x_6_1;
wire [7:7] x_6_2;
wire [7:7] x_6_3;
wire [7:7] x_6_4;
wire [7:7] x_6_5;
wire [7:7] x_6_6;
wire [7:7] x_6_7;
wire [7:7] x_6_8;
wire [7:7] x_6_9;
wire [7:7] x_6_10;
wire [7:0] x_5_0;
wire [7:7] x_5_1;
wire [7:7] x_5_2;
wire [7:7] x_5_3;
wire [7:7] x_5_4;
wire [7:7] x_5_5;
wire [7:7] x_5_6;
wire [7:7] x_5_7;
wire [7:7] x_5_8;
wire [7:7] x_5_9;
wire [7:7] x_5_10;
wire [7:0] x_4_0;
wire [7:7] x_4_1;
wire [7:7] x_4_2;
wire [7:7] x_4_3;
wire [7:7] x_4_4;
wire [7:7] x_4_5;
wire [7:7] x_4_6;
wire [7:7] x_4_7;
wire [7:7] x_4_8;
wire [7:7] x_4_9;
wire [7:7] x_4_10;
wire [7:0] x_3_0;
wire [7:7] x_3_1;
wire [7:7] x_3_2;
wire [7:7] x_3_3;
wire [7:7] x_3_4;
wire [7:7] x_3_5;
wire [7:7] x_3_6;
wire [7:7] x_3_7;
wire [7:7] x_3_8;
wire [7:7] x_3_9;
wire [7:7] x_3_10;
wire [7:0] x_2_0;
wire [7:7] x_2_1;
wire [7:7] x_2_2;
wire [7:7] x_2_3;
wire [7:7] x_2_4;
wire [7:7] x_2_5;
wire [7:7] x_2_6;
wire [7:7] x_2_7;
wire [7:7] x_2_8;
wire [7:7] x_2_9;
wire [7:7] x_2_10;
wire [7:0] x_1_0;
wire [7:7] x_1_1;
wire [7:7] x_1_2;
wire [7:7] x_1_3;
wire [7:7] x_1_4;
wire [7:7] x_1_5;
wire [7:7] x_1_6;
wire [7:7] x_1_7;
wire [7:7] x_1_8;
wire [7:7] x_1_9;
wire [7:7] x_1_10;
wire [7:0] x_0_0;
wire [7:7] x_0_1;
wire [7:7] x_0_2;
wire [7:7] x_0_3;
wire [7:7] x_0_4;
wire [7:7] x_0_5;
wire [7:7] x_0_6;
wire [7:7] x_0_7;
wire [7:7] x_0_8;
wire [7:7] x_0_9;
wire [7:7] x_0_10;
wire [14:3] un84_sop_0_0_0_1_6_8;
wire [14:0] un84_sop_1_7;
wire [14:0] un84_sop_0_0_0_0_11_7;
wire [14:0] un84_sop_1_4;
wire [10:2] un1_x_10_4;
wire [14:0] un84_sop_0_0_0_1_6_4;
wire [14:0] un84_sop_0_0_0_0_11_6;
wire [14:0] un84_sop_0_0_0_0_8;
wire [14:0] un84_sop_0_0_0_1_6_6;
wire [14:0] un84_sop_1_6;
wire [14:7] un1_x_15_0_0_0;
wire [14:7] un1_x_11_0_0_0;
wire [14:7] un1_x_16_0_0_0;
wire [0:0] x_12_6_tmp_d_array_0;
wire [0:0] x_12_5_tmp_d_array_0;
wire [0:0] x_12_4_tmp_d_array_0;
wire [0:0] x_12_3_tmp_d_array_0;
wire [0:0] x_12_2_tmp_d_array_0;
wire [0:0] x_12_1_tmp_d_array_0;
wire [0:0] x_12_0_tmp_d_array_0;
wire [0:0] x_12_tmp_d_array_0;
wire [0:0] x_7_6_tmp_d_array_0;
wire [0:0] x_7_5_tmp_d_array_0;
wire [0:0] x_7_4_tmp_d_array_0;
wire [0:0] x_7_3_tmp_d_array_0;
wire [0:0] x_7_2_tmp_d_array_0;
wire [0:0] x_7_1_tmp_d_array_0;
wire [0:0] x_7_0_tmp_d_array_0;
wire [0:0] x_7_tmp_d_array_0;
wire [0:0] x_4_6_tmp_d_array_0;
wire [0:0] x_4_5_tmp_d_array_0;
wire [0:0] x_4_4_tmp_d_array_0;
wire [0:0] x_4_3_tmp_d_array_0;
wire [0:0] x_4_2_tmp_d_array_0;
wire [0:0] x_4_1_tmp_d_array_0;
wire [0:0] x_4_0_tmp_d_array_0;
wire [0:0] x_4_tmp_d_array_0;
wire [4:4] un1_x_14_0_0_0;
wire [5:5] un1_x_9_0_0;
wire [4:4] un1_x_3_0;
wire VCC ;
wire GND ;
wire un84_sop_1_s_7 ;
wire un84_sop_1_s_8 ;
wire un84_sop_1_s_9 ;
wire un84_sop_1_s_10 ;
wire un84_sop_1_s_11 ;
wire un84_sop_1_s_12 ;
wire un84_sop_1_s_13 ;
wire un84_sop_1_s_14 ;
wire un1_x_10_s_2_sf ;
wire un1_x_10_axb_3 ;
wire CARRYCASCOUT ;
wire OVERFLOW ;
wire MULTSIGNOUT ;
wire PATTERNBDETECT ;
wire PATTERNDETECT ;
wire UNDERFLOW ;
wire CARRYCASCOUT_0 ;
wire OVERFLOW_0 ;
wire MULTSIGNOUT_0 ;
wire PATTERNBDETECT_0 ;
wire PATTERNDETECT_0 ;
wire UNDERFLOW_0 ;
wire CARRYCASCOUT_1 ;
wire OVERFLOW_1 ;
wire MULTSIGNOUT_1 ;
wire PATTERNBDETECT_1 ;
wire PATTERNDETECT_1 ;
wire UNDERFLOW_1 ;
wire CARRYCASCOUT_2 ;
wire OVERFLOW_2 ;
wire MULTSIGNOUT_2 ;
wire PATTERNBDETECT_2 ;
wire PATTERNDETECT_2 ;
wire UNDERFLOW_2 ;
wire CARRYCASCOUT_3 ;
wire OVERFLOW_3 ;
wire MULTSIGNOUT_3 ;
wire PATTERNBDETECT_3 ;
wire PATTERNDETECT_3 ;
wire UNDERFLOW_3 ;
wire CARRYCASCOUT_4 ;
wire OVERFLOW_4 ;
wire MULTSIGNOUT_4 ;
wire PATTERNBDETECT_4 ;
wire PATTERNDETECT_4 ;
wire UNDERFLOW_4 ;
wire CARRYCASCOUT_5 ;
wire OVERFLOW_5 ;
wire MULTSIGNOUT_5 ;
wire PATTERNBDETECT_5 ;
wire PATTERNDETECT_5 ;
wire UNDERFLOW_5 ;
wire CARRYCASCOUT_6 ;
wire OVERFLOW_6 ;
wire MULTSIGNOUT_6 ;
wire PATTERNBDETECT_6 ;
wire PATTERNDETECT_6 ;
wire UNDERFLOW_6 ;
wire CARRYCASCOUT_7 ;
wire OVERFLOW_7 ;
wire MULTSIGNOUT_7 ;
wire PATTERNBDETECT_7 ;
wire PATTERNDETECT_7 ;
wire UNDERFLOW_7 ;
wire CARRYCASCOUT_8 ;
wire OVERFLOW_8 ;
wire MULTSIGNOUT_8 ;
wire PATTERNBDETECT_8 ;
wire PATTERNDETECT_8 ;
wire UNDERFLOW_8 ;
wire CARRYCASCOUT_9 ;
wire OVERFLOW_9 ;
wire MULTSIGNOUT_9 ;
wire PATTERNBDETECT_9 ;
wire PATTERNDETECT_9 ;
wire UNDERFLOW_9 ;
wire un84_sop_1_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_1_6_0_o5_2 ;
wire un84_sop_1_6_0_o5_3 ;
wire un84_sop_1_6_0_o5_4 ;
wire un84_sop_1_6_0_o5_5 ;
wire un84_sop_1_6_0_o5_6 ;
wire un84_sop_1_6_0_o5_7 ;
wire un84_sop_1_6_0_o5_8 ;
wire un84_sop_1_6_0_o5_9 ;
wire un84_sop_1_6_0_o5_10 ;
wire un84_sop_1_6_0_o5_11 ;
wire un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5 ;
wire un84_sop_0_0_0_1_6_8_o5_3 ;
wire un84_sop_0_0_0_1_6_8_o5_4 ;
wire un84_sop_0_0_0_1_6_8_o5_5 ;
wire un84_sop_0_0_0_1_6_8_o5_6 ;
wire un84_sop_0_0_0_1_6_8_o5_7 ;
wire un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_6_6_0_o5_2 ;
wire un84_sop_0_0_0_6_6_0_o5_3 ;
wire un84_sop_0_0_0_6_6_0_o5_4 ;
wire un84_sop_0_0_0_6_6_0_o5_5 ;
wire un84_sop_0_0_0_6_6_0_o5_6 ;
wire un84_sop_0_0_0_6_6_0_o5_7 ;
wire un84_sop_0_0_0_6_6_0_o5_8 ;
wire un84_sop_0_0_0_6_6_0_o5_9 ;
wire un84_sop_0_0_0_6_6_0_o5_10 ;
wire un84_sop_0_0_0_6_6_0_o5_11 ;
wire un84_sop_0_0_0_6_6_0_o5_12 ;
wire un84_sop_0_0_0_11_0_o5_2 ;
wire un84_sop_0_0_0_11_0_o5_3 ;
wire un84_sop_0_0_0_11_0_o5_4 ;
wire un84_sop_0_0_0_11_0_o5_5 ;
wire un84_sop_0_0_0_11_0_o5_6 ;
wire un84_sop_0_0_0_11_0_o5_7 ;
wire un84_sop_0_0_0_11_0_o5_8 ;
wire un84_sop_0_0_0_11_0_o5_9 ;
wire un84_sop_0_0_0_11_0_o5_10 ;
wire un84_sop_0_0_0_11_0_o5_11 ;
wire un84_sop_0_0_0_11_0_o5_12 ;
wire un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_11_6_0_o5_2 ;
wire un84_sop_0_0_0_11_6_0_o5_3 ;
wire un84_sop_0_0_0_11_6_0_o5_4 ;
wire un84_sop_0_0_0_11_6_0_o5_5 ;
wire un84_sop_0_0_0_11_6_0_o5_6 ;
wire un84_sop_0_0_0_11_6_0_o5_7 ;
wire un84_sop_0_0_0_11_6_0_o5_8 ;
wire un84_sop_0_0_0_11_6_0_o5_9 ;
wire un84_sop_0_0_0_11_6_0_o5_10 ;
wire un84_sop_0_0_0_11_6_0_o5_11 ;
wire un84_sop_0_0_0_11_6_0_cry_0 ;
wire un84_sop_0_0_0_11_6_0_axb_1 ;
wire un84_sop_0_0_0_11_6_0_cry_1 ;
wire un84_sop_0_0_0_11_6_0_axb_2 ;
wire un84_sop_0_0_0_11_6_0_cry_2 ;
wire un84_sop_0_0_0_11_6_0_axb_3 ;
wire un84_sop_0_0_0_11_6_0_cry_3 ;
wire un84_sop_0_0_0_11_6_0_axb_4 ;
wire un84_sop_0_0_0_11_6_0_cry_4 ;
wire un84_sop_0_0_0_11_6_0_axb_5 ;
wire un84_sop_0_0_0_11_6_0_cry_5 ;
wire un84_sop_0_0_0_11_6_0_axb_6 ;
wire un84_sop_0_0_0_11_6_0_cry_6 ;
wire un84_sop_0_0_0_11_6_0_axb_7 ;
wire un84_sop_0_0_0_11_6_0_cry_7 ;
wire un84_sop_0_0_0_11_6_0_axb_8 ;
wire un84_sop_0_0_0_11_6_0_cry_8 ;
wire un84_sop_0_0_0_11_6_0_axb_9 ;
wire un84_sop_0_0_0_11_6_0_cry_9 ;
wire un84_sop_0_0_0_11_6_0_axb_10 ;
wire un84_sop_0_0_0_11_6_0_cry_10 ;
wire un84_sop_0_0_0_11_6_0_axb_11 ;
wire un84_sop_0_0_0_11_6_0_cry_11 ;
wire un84_sop_0_0_0_11_6_0_axb_12 ;
wire un84_sop_0_0_0_11_6_0_cry_12 ;
wire un84_sop_0_0_0_11_6_0_axb_13 ;
wire un84_sop_0_0_0_11_0_axb_0 ;
wire un84_sop_0_0_0_11_0_cry_0 ;
wire un84_sop_0_0_0_11_0_axb_1 ;
wire un84_sop_0_0_0_11_0_cry_1 ;
wire un84_sop_0_0_0_11_0_cry_2_RNO ;
wire un84_sop_0_0_0_11_0_axb_2 ;
wire un84_sop_0_0_0_11_0_cry_2 ;
wire un84_sop_0_0_0_11_0_axb_3 ;
wire un84_sop_0_0_0_11_0_cry_3 ;
wire un84_sop_0_0_0_11_0_axb_4 ;
wire un84_sop_0_0_0_11_0_cry_4 ;
wire un84_sop_0_0_0_11_0_axb_5 ;
wire un84_sop_0_0_0_11_0_cry_5 ;
wire un84_sop_0_0_0_11_0_axb_6 ;
wire un84_sop_0_0_0_11_0_cry_6 ;
wire un84_sop_0_0_0_11_0_axb_7 ;
wire un84_sop_0_0_0_11_0_cry_7 ;
wire un84_sop_0_0_0_11_0_axb_8 ;
wire un84_sop_0_0_0_11_0_cry_8 ;
wire un84_sop_0_0_0_11_0_axb_9 ;
wire un84_sop_0_0_0_11_0_cry_9 ;
wire un84_sop_0_0_0_11_0_axb_10 ;
wire un84_sop_0_0_0_11_0_cry_10 ;
wire un84_sop_0_0_0_11_0_axb_11 ;
wire un84_sop_0_0_0_11_0_cry_11 ;
wire un84_sop_0_0_0_11_0_axb_12 ;
wire un84_sop_0_0_0_11_0_cry_12 ;
wire un84_sop_0_0_0_11_0_axb_13 ;
wire un84_sop_0_0_0_11_0_cry_13 ;
wire un84_sop_0_0_0_11_0_axb_14 ;
wire un84_sop_0_0_0_6_6_0_cry_0 ;
wire un84_sop_0_0_0_6_6_0_axb_1 ;
wire un84_sop_0_0_0_6_6_0_cry_1 ;
wire un84_sop_0_0_0_6_6_0_axb_2 ;
wire un84_sop_0_0_0_6_6_0_cry_2 ;
wire un84_sop_0_0_0_6_6_0_axb_3 ;
wire un84_sop_0_0_0_6_6_0_cry_3 ;
wire un84_sop_0_0_0_6_6_0_axb_4 ;
wire un84_sop_0_0_0_6_6_0_cry_4 ;
wire un84_sop_0_0_0_6_6_0_axb_5 ;
wire un84_sop_0_0_0_6_6_0_cry_5 ;
wire un84_sop_0_0_0_6_6_0_axb_6 ;
wire un84_sop_0_0_0_6_6_0_cry_6 ;
wire un84_sop_0_0_0_6_6_0_axb_7 ;
wire un84_sop_0_0_0_6_6_0_cry_7 ;
wire un84_sop_0_0_0_6_6_0_axb_8 ;
wire un84_sop_0_0_0_6_6_0_cry_8 ;
wire un84_sop_0_0_0_6_6_0_axb_9 ;
wire un84_sop_0_0_0_6_6_0_cry_9 ;
wire un84_sop_0_0_0_6_6_0_axb_10 ;
wire un84_sop_0_0_0_6_6_0_cry_10 ;
wire un84_sop_0_0_0_6_6_0_axb_11 ;
wire un84_sop_0_0_0_6_6_0_cry_11 ;
wire un84_sop_0_0_0_6_6_0_axb_12 ;
wire un84_sop_0_0_0_6_6_0_cry_12 ;
wire un84_sop_0_0_0_6_6_0_axb_13 ;
wire un84_sop_0_0_0_6_6_0_cry_13 ;
wire un84_sop_0_0_0_6_6_0_axb_14 ;
wire un84_sop_0_0_0_1_6_8_cry_0 ;
wire un84_sop_0_0_0_1_6_8_axb_1 ;
wire un84_sop_0_0_0_1_6_8_cry_1 ;
wire un84_sop_0_0_0_1_6_8_axb_2 ;
wire un84_sop_0_0_0_1_6_8_cry_2 ;
wire un84_sop_0_0_0_1_6_8_axb_3 ;
wire un84_sop_0_0_0_1_6_8_cry_3 ;
wire un84_sop_0_0_0_1_6_8_axb_4 ;
wire un84_sop_0_0_0_1_6_8_cry_4 ;
wire un84_sop_0_0_0_1_6_8_axb_5 ;
wire un84_sop_0_0_0_1_6_8_cry_5 ;
wire un84_sop_0_0_0_1_6_8_axb_6 ;
wire un84_sop_0_0_0_1_6_8_cry_6 ;
wire un84_sop_0_0_0_1_6_8_axb_7 ;
wire un84_sop_0_0_0_1_6_8_cry_7 ;
wire un84_sop_0_0_0_1_6_8_axb_8 ;
wire un84_sop_0_0_0_1_6_8_cry_8 ;
wire un84_sop_0_0_0_1_6_8_axb_9 ;
wire un84_sop_0_0_0_1_6_8_cry_9 ;
wire un84_sop_0_0_0_1_6_8_axb_10 ;
wire un84_sop_0_0_0_1_6_8_cry_10 ;
wire un84_sop_0_0_0_1_6_8_axb_11 ;
wire un84_sop_1_6_0_cry_0 ;
wire un84_sop_1_6_0_axb_1 ;
wire un84_sop_1_6_0_cry_1 ;
wire un84_sop_1_6_0_axb_2 ;
wire un84_sop_1_6_0_cry_2 ;
wire un84_sop_1_6_0_axb_3 ;
wire un84_sop_1_6_0_cry_3 ;
wire un84_sop_1_6_0_axb_4 ;
wire un84_sop_1_6_0_cry_4 ;
wire un84_sop_1_6_0_axb_5 ;
wire un84_sop_1_6_0_cry_5 ;
wire un84_sop_1_6_0_axb_6 ;
wire un84_sop_1_6_0_cry_6 ;
wire un84_sop_1_6_0_axb_7 ;
wire un84_sop_1_6_0_cry_7 ;
wire un84_sop_1_6_0_axb_8 ;
wire un84_sop_1_6_0_cry_8 ;
wire un84_sop_1_6_0_axb_9 ;
wire un84_sop_1_6_0_cry_9 ;
wire un84_sop_1_6_0_axb_10 ;
wire un84_sop_1_6_0_cry_10 ;
wire un84_sop_1_6_0_axb_11 ;
wire un84_sop_1_6_0_cry_11 ;
wire un84_sop_1_6_0_axb_12 ;
wire un84_sop_1_6_0_cry_12 ;
wire un84_sop_1_6_0_axb_13 ;
wire un1_x_10_cry_3 ;
wire un1_x_10_axb_4 ;
wire un1_x_10_cry_4 ;
wire un1_x_10_axb_5 ;
wire un1_x_10_cry_5 ;
wire un1_x_10_axb_6 ;
wire un1_x_10_cry_6 ;
wire un1_x_10_axb_7 ;
wire un1_x_10_cry_7 ;
wire un1_x_10_axb_8 ;
wire un1_x_10_cry_8 ;
wire un1_x_10_axb_9 ;
wire un1_x_10_cry_9 ;
wire un1_x_10_axb_10 ;
wire un1_x_10_cry_10 ;
wire un1_x_10_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_0 ;
wire un84_sop_0_0_0_1_6_4_axb_1 ;
wire un84_sop_0_0_0_1_6_4_cry_1 ;
wire un84_sop_0_0_0_1_6_4_axb_2 ;
wire un84_sop_0_0_0_1_6_4_cry_2 ;
wire un84_sop_0_0_0_1_6_4_axb_3 ;
wire un84_sop_0_0_0_1_6_4_cry_3 ;
wire un84_sop_0_0_0_1_6_4_axb_4 ;
wire un84_sop_0_0_0_1_6_4_cry_4 ;
wire un84_sop_0_0_0_1_6_4_axb_5 ;
wire un84_sop_0_0_0_1_6_4_cry_5 ;
wire un84_sop_0_0_0_1_6_4_axb_6 ;
wire un84_sop_0_0_0_1_6_4_cry_6 ;
wire un84_sop_0_0_0_1_6_4_axb_7 ;
wire un84_sop_0_0_0_1_6_4_cry_7 ;
wire un84_sop_0_0_0_1_6_4_axb_8 ;
wire un84_sop_0_0_0_1_6_4_cry_8 ;
wire un84_sop_0_0_0_1_6_4_axb_9 ;
wire un84_sop_0_0_0_1_6_4_cry_9 ;
wire un84_sop_0_0_0_1_6_4_axb_10 ;
wire un84_sop_0_0_0_1_6_4_cry_10 ;
wire un84_sop_0_0_0_1_6_4_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_11 ;
wire un84_sop_0_0_0_1_6_4_axb_12 ;
wire un84_sop_0_0_0_1_6_4_cry_12 ;
wire un84_sop_0_0_0_1_6_4_axb_13 ;
wire un84_sop_0_0_0_1_6_4_cry_13 ;
wire un84_sop_0_0_0_1_6_4_axb_14 ;
wire un84_sop_0_0_0_1_6_cry_0 ;
wire un84_sop_0_0_0_1_6_axb_1 ;
wire un84_sop_0_0_0_1_6_cry_1 ;
wire un84_sop_0_0_0_1_6_axb_2 ;
wire un84_sop_0_0_0_1_6_cry_2 ;
wire un84_sop_0_0_0_1_6_axb_3 ;
wire un84_sop_0_0_0_1_6_cry_3 ;
wire un84_sop_0_0_0_1_6_axb_4 ;
wire un84_sop_0_0_0_1_6_cry_4 ;
wire un84_sop_0_0_0_1_6_axb_5 ;
wire un84_sop_0_0_0_1_6_cry_5 ;
wire un84_sop_0_0_0_1_6_axb_6 ;
wire un84_sop_0_0_0_1_6_cry_6 ;
wire un84_sop_0_0_0_1_6_axb_7 ;
wire un84_sop_0_0_0_1_6_cry_7 ;
wire un84_sop_0_0_0_1_6_axb_8 ;
wire un84_sop_0_0_0_1_6_cry_8 ;
wire un84_sop_0_0_0_1_6_axb_9 ;
wire un84_sop_0_0_0_1_6_cry_9 ;
wire un84_sop_0_0_0_1_6_axb_10 ;
wire un84_sop_0_0_0_1_6_cry_10 ;
wire un84_sop_0_0_0_1_6_axb_11 ;
wire un84_sop_0_0_0_1_6_cry_11 ;
wire un84_sop_0_0_0_1_6_axb_12 ;
wire un84_sop_0_0_0_1_6_cry_12 ;
wire un84_sop_0_0_0_1_6_axb_13 ;
wire un84_sop_0_0_0_1_6_cry_13 ;
wire un84_sop_0_0_0_1_6_axb_14 ;
wire un1_x_0_0_c4 ;
wire un1_x_10_5_c5 ;
wire un84_sop_1_7_cry_0 ;
wire un84_sop_1_7_axb_1 ;
wire un84_sop_1_7_cry_1 ;
wire un84_sop_1_7_axb_2 ;
wire un84_sop_1_7_cry_2 ;
wire un84_sop_1_7_axb_3 ;
wire un84_sop_1_7_cry_3 ;
wire un84_sop_1_7_axb_4 ;
wire un84_sop_1_7_cry_4 ;
wire un84_sop_1_7_axb_5 ;
wire un84_sop_1_7_cry_5 ;
wire un84_sop_1_7_axb_6 ;
wire un84_sop_1_7_cry_6 ;
wire un84_sop_1_7_axb_7 ;
wire un84_sop_1_7_cry_7 ;
wire un84_sop_1_7_axb_8 ;
wire un84_sop_1_7_cry_8 ;
wire un84_sop_1_7_axb_9 ;
wire un84_sop_1_7_cry_9 ;
wire un84_sop_1_7_axb_10 ;
wire un84_sop_1_7_cry_10 ;
wire un84_sop_1_7_axb_11 ;
wire un84_sop_1_7_cry_11 ;
wire un84_sop_1_7_axb_12 ;
wire un84_sop_1_7_cry_12 ;
wire un84_sop_1_7_axb_13 ;
wire un84_sop_1_7_cry_13 ;
wire un84_sop_1_7_axb_14 ;
wire un84_sop_0_0_0_0_11_7_cry_0 ;
wire un84_sop_0_0_0_0_11_7_axb_1 ;
wire un84_sop_0_0_0_0_11_7_cry_1 ;
wire un84_sop_0_0_0_0_11_7_axb_2 ;
wire un84_sop_0_0_0_0_11_7_cry_2 ;
wire un84_sop_0_0_0_0_11_7_axb_3 ;
wire un84_sop_0_0_0_0_11_7_cry_3 ;
wire un84_sop_0_0_0_0_11_7_axb_4 ;
wire un84_sop_0_0_0_0_11_7_cry_4 ;
wire un84_sop_0_0_0_0_11_7_axb_5 ;
wire un84_sop_0_0_0_0_11_7_cry_5 ;
wire un84_sop_0_0_0_0_11_7_axb_6 ;
wire un84_sop_0_0_0_0_11_7_cry_6 ;
wire un84_sop_0_0_0_0_11_7_axb_7 ;
wire un84_sop_0_0_0_0_11_7_cry_7 ;
wire un84_sop_0_0_0_0_11_7_axb_8 ;
wire un84_sop_0_0_0_0_11_7_cry_8 ;
wire un84_sop_0_0_0_0_11_7_axb_9 ;
wire un84_sop_0_0_0_0_11_7_cry_9 ;
wire un84_sop_0_0_0_0_11_7_axb_10 ;
wire un84_sop_1_4_cry_0 ;
wire un84_sop_1_4_axb_1 ;
wire un84_sop_1_4_cry_1 ;
wire un84_sop_1_4_axb_2 ;
wire un84_sop_1_4_cry_2 ;
wire un84_sop_1_4_axb_3 ;
wire un84_sop_1_4_cry_3 ;
wire un84_sop_1_4_axb_4 ;
wire un84_sop_1_4_cry_4 ;
wire un84_sop_1_4_axb_5 ;
wire un84_sop_1_4_cry_5 ;
wire un84_sop_1_4_axb_6 ;
wire un84_sop_1_4_cry_6 ;
wire un84_sop_1_4_axb_7 ;
wire un84_sop_1_4_cry_7 ;
wire un84_sop_1_4_axb_8 ;
wire un84_sop_1_4_cry_8 ;
wire un84_sop_1_4_axb_9 ;
wire un84_sop_1_4_cry_9 ;
wire un84_sop_1_4_axb_10 ;
wire un84_sop_1_4_cry_10 ;
wire un84_sop_1_4_axb_11 ;
wire un84_sop_1_4_cry_11 ;
wire un84_sop_1_4_axb_12 ;
wire un84_sop_1_4_cry_12 ;
wire un84_sop_1_4_axb_13 ;
wire un84_sop_1_4_cry_13 ;
wire un84_sop_1_4_axb_14 ;
wire un84_sop_1_axb_0 ;
wire un84_sop_1_cry_0 ;
wire un84_sop_1_axb_1 ;
wire un84_sop_1_cry_1 ;
wire un84_sop_1_axb_2 ;
wire un84_sop_1_cry_2 ;
wire un84_sop_1_axb_3 ;
wire un84_sop_1_cry_3 ;
wire un84_sop_1_axb_4 ;
wire un84_sop_1_cry_4 ;
wire un84_sop_1_axb_5 ;
wire un84_sop_1_cry_5 ;
wire un84_sop_1_axb_6 ;
wire un84_sop_1_cry_6 ;
wire un84_sop_1_axb_7 ;
wire un84_sop_1_cry_7 ;
wire un84_sop_1_axb_8 ;
wire un84_sop_1_cry_8 ;
wire un84_sop_1_axb_9 ;
wire un84_sop_1_cry_9 ;
wire un84_sop_1_axb_10 ;
wire un84_sop_1_cry_10 ;
wire un84_sop_1_axb_11 ;
wire un84_sop_1_cry_11 ;
wire un84_sop_1_axb_12 ;
wire un84_sop_1_cry_12 ;
wire un84_sop_1_axb_13 ;
wire un84_sop_1_cry_13 ;
wire un84_sop_1_axb_14 ;
wire un1_x_10_4_cry_1 ;
wire un1_x_10_4_axb_2 ;
wire un1_x_10_4_cry_2 ;
wire un1_x_10_4_axb_3 ;
wire un1_x_10_4_cry_3 ;
wire un1_x_10_4_axb_4 ;
wire un1_x_10_4_cry_4 ;
wire un1_x_10_4_axb_5 ;
wire un1_x_10_4_cry_5 ;
wire un1_x_10_4_axb_6 ;
wire un1_x_10_4_cry_6 ;
wire un1_x_10_4_axb_7 ;
wire un1_x_10_4_cry_7 ;
wire un1_x_15_0_axb_0 ;
wire un1_x_15_0_cry_0 ;
wire un1_x_15_0_axb_1 ;
wire un1_x_15_0_cry_1 ;
wire un1_x_15_0_axb_2 ;
wire un1_x_15_0_cry_2 ;
wire un1_x_15_0_axb_3 ;
wire un1_x_15_0_cry_3 ;
wire un1_x_15_0_axb_4 ;
wire un1_x_15_0_cry_4 ;
wire un1_x_15_0_axb_5 ;
wire un1_x_15_0_cry_5 ;
wire un1_x_15_0_axb_6 ;
wire un1_x_15_0_cry_6 ;
wire un1_x_15_0_axb_7 ;
wire un1_x_15_0_cry_7 ;
wire un1_x_15_0_axb_8 ;
wire un1_x_11_0_axb_0 ;
wire un1_x_11_0_cry_0 ;
wire un1_x_11_0_axb_1 ;
wire un1_x_11_0_cry_1 ;
wire un1_x_11_0_axb_2 ;
wire un1_x_11_0_cry_2 ;
wire un1_x_11_0_axb_3 ;
wire un1_x_11_0_cry_3 ;
wire un1_x_11_0_axb_4 ;
wire un1_x_11_0_cry_4 ;
wire un1_x_11_0_axb_5 ;
wire un1_x_11_0_cry_5 ;
wire un1_x_11_0_axb_6 ;
wire un1_x_11_0_cry_6 ;
wire un1_x_11_0_axb_7 ;
wire un1_x_11_0_cry_7 ;
wire un1_x_11_0_axb_8 ;
wire un1_x_16_0_axb_0 ;
wire un1_x_16_0_cry_0 ;
wire un1_x_16_0_axb_1 ;
wire un1_x_16_0_cry_1 ;
wire un1_x_16_0_axb_2 ;
wire un1_x_16_0_cry_2 ;
wire un1_x_16_0_axb_3 ;
wire un1_x_16_0_cry_3 ;
wire un1_x_16_0_axb_4 ;
wire un1_x_16_0_cry_4 ;
wire un1_x_16_0_axb_5 ;
wire un1_x_16_0_cry_5 ;
wire un1_x_16_0_axb_6 ;
wire un1_x_16_0_cry_6 ;
wire un1_x_16_0_axb_7 ;
wire un1_x_16_0_cry_7 ;
wire un1_x_16_0_axb_8 ;
wire un84_sop_0_0_0_1_cry_0 ;
wire un84_sop_0_0_0_1_axb_1 ;
wire un84_sop_0_0_0_1_cry_1 ;
wire un84_sop_0_0_0_1_axb_2 ;
wire un84_sop_0_0_0_1_cry_2 ;
wire un84_sop_0_0_0_1_axb_3 ;
wire un84_sop_0_0_0_1_cry_3 ;
wire un84_sop_0_0_0_1_axb_4 ;
wire un84_sop_0_0_0_1_cry_4 ;
wire un84_sop_0_0_0_1_axb_5 ;
wire un84_sop_0_0_0_1_cry_5 ;
wire un84_sop_0_0_0_1_axb_6 ;
wire un84_sop_0_0_0_1_cry_6 ;
wire un84_sop_0_0_0_1_axb_7 ;
wire un84_sop_0_0_0_1_cry_7 ;
wire un84_sop_0_0_0_1_axb_8 ;
wire un84_sop_0_0_0_1_cry_8 ;
wire un84_sop_0_0_0_1_axb_9 ;
wire un1_x_10_4_cry_1_sf ;
wire un84_sop_0_0_0_0_11_7_axb_0_ci ;
wire un84_sop_0_0_0_11_0_cry_0_cy ;
wire un84_sop_0_0_0_11_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_6_0_cry_0_cy ;
wire un84_sop_1_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_0_axb_0_0 ;
wire un84_sop_0_0_0_6_0_axb_0_1 ;
wire un84_sop_1_6_0_axb_0_0 ;
wire un1_x_10_4_s_8_false ;
wire x_4_x_4_1Q_Q31 ;
wire x_4_0_x_4_1Q_Q31 ;
wire x_4_1_x_4_1Q_Q31 ;
wire x_4_2_x_4_1Q_Q31 ;
wire x_4_3_x_4_1Q_Q31 ;
wire x_4_4_x_4_1Q_Q31 ;
wire x_4_5_x_4_1Q_Q31 ;
wire x_4_6_x_4_1Q_Q31 ;
wire x_7_x_7_1Q_Q31 ;
wire x_7_0_x_7_1Q_Q31 ;
wire x_7_1_x_7_1Q_Q31 ;
wire x_7_2_x_7_1Q_Q31 ;
wire x_7_3_x_7_1Q_Q31 ;
wire x_7_4_x_7_1Q_Q31 ;
wire x_7_5_x_7_1Q_Q31 ;
wire x_7_6_x_7_1Q_Q31 ;
wire x_12_x_4_1Q_Q31 ;
wire x_12_0_x_4_1Q_Q31 ;
wire x_12_1_x_4_1Q_Q31 ;
wire x_12_2_x_4_1Q_Q31 ;
wire x_12_3_x_4_1Q_Q31 ;
wire x_12_4_x_4_1Q_Q31 ;
wire x_12_5_x_4_1Q_Q31 ;
wire x_12_6_x_7_1Q_Q31 ;
GND GND_cZ (
.G(GND)
);
VCC VCC_cZ (
.P(VCC)
);
// @8:21
SRLC32E x_12_6_x_7_1Q (
.Q(x_12_6_tmp_d_array_0[0]),
.Q31(x_12_6_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_9[0]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_5_x_4_1Q (
.Q(x_12_5_tmp_d_array_0[0]),
.Q31(x_12_5_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[1]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_4_x_4_1Q (
.Q(x_12_4_tmp_d_array_0[0]),
.Q31(x_12_4_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[2]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_3_x_4_1Q (
.Q(x_12_3_tmp_d_array_0[0]),
.Q31(x_12_3_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[3]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_2_x_4_1Q (
.Q(x_12_2_tmp_d_array_0[0]),
.Q31(x_12_2_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[4]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_1_x_4_1Q (
.Q(x_12_1_tmp_d_array_0[0]),
.Q31(x_12_1_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[5]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_0_x_4_1Q (
.Q(x_12_0_tmp_d_array_0[0]),
.Q31(x_12_0_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[6]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_12_x_4_1Q (
.Q(x_12_tmp_d_array_0[0]),
.Q31(x_12_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_8[7]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_6_x_7_1Q (
.Q(x_7_6_tmp_d_array_0[0]),
.Q31(x_7_6_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[0]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_5_x_7_1Q (
.Q(x_7_5_tmp_d_array_0[0]),
.Q31(x_7_5_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[1]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_4_x_7_1Q (
.Q(x_7_4_tmp_d_array_0[0]),
.Q31(x_7_4_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[2]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_3_x_7_1Q (
.Q(x_7_3_tmp_d_array_0[0]),
.Q31(x_7_3_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[3]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_2_x_7_1Q (
.Q(x_7_2_tmp_d_array_0[0]),
.Q31(x_7_2_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[4]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_1_x_7_1Q (
.Q(x_7_1_tmp_d_array_0[0]),
.Q31(x_7_1_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[5]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_0_x_7_1Q (
.Q(x_7_0_tmp_d_array_0[0]),
.Q31(x_7_0_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[6]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_7_x_7_1Q (
.Q(x_7_tmp_d_array_0[0]),
.Q31(x_7_x_7_1Q_Q31),
.A({GND, GND, GND, GND, VCC}),
.D(x_4[7]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_6_x_4_1Q (
.Q(x_4_6_tmp_d_array_0[0]),
.Q31(x_4_6_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[0]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_5_x_4_1Q (
.Q(x_4_5_tmp_d_array_0[0]),
.Q31(x_4_5_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[1]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_4_x_4_1Q (
.Q(x_4_4_tmp_d_array_0[0]),
.Q31(x_4_4_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[2]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_3_x_4_1Q (
.Q(x_4_3_tmp_d_array_0[0]),
.Q31(x_4_3_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[3]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_2_x_4_1Q (
.Q(x_4_2_tmp_d_array_0[0]),
.Q31(x_4_2_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[4]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_1_x_4_1Q (
.Q(x_4_1_tmp_d_array_0[0]),
.Q31(x_4_1_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[5]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_0_x_4_1Q (
.Q(x_4_0_tmp_d_array_0[0]),
.Q31(x_4_0_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[6]),
.CLK(clk),
.CE(VCC)
);
// @8:21
SRLC32E x_4_x_4_1Q (
.Q(x_4_tmp_d_array_0[0]),
.Q31(x_4_x_4_1Q_Q31),
.A({GND, GND, GND, VCC, GND}),
.D(x_0[7]),
.CLK(clk),
.CE(VCC)
);
// @8:30
LUT1 un1_x_10_4_s_8_false_cZ (
.I0(GND),
.O(un1_x_10_4_s_8_false)
);
defparam un1_x_10_4_s_8_false_cZ.INIT=2'h0;
LUT3 un84_sop_1_6_0_s_0_lut (
.I0(un1_x_1[4]),
.I1(un1_x_2[5]),
.I2(un1_x_3[4]),
.O(un84_sop_1_6[0])
);
defparam un84_sop_1_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_11_6_0_s_0_lut (
.I0(un1_x_12_0_0[4]),
.I1(un1_x_13_0_0[5]),
.I2(un1_x_14_0_0[4]),
.O(un84_sop_0_0_0_0_11_6[0])
);
defparam un84_sop_0_0_0_11_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_6_6_0_s_0_lut (
.I0(un1_x_7_0[2]),
.I1(un1_x_8_0[4]),
.I2(un1_x_9_0[5]),
.O(un84_sop_0_0_0_1_6_6[0])
);
defparam un84_sop_0_0_0_6_6_0_s_0_lut.INIT=8'h96;
// @8:30
LUT2 un84_sop_0_0_0_6_0_axb_0_0_cZ (
.I0(un1_x_12_0_0[4]),
.I1(un1_x_13_0_0[5]),
.O(un84_sop_0_0_0_6_0_axb_0_0)
);
defparam un84_sop_0_0_0_6_0_axb_0_0_cZ.INIT=4'h6;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_axb_12_cZ (
.I0(un1_x_12_0_0[15]),
.I1(un1_x_13_0_0[15]),
.I2(un1_x_14_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_axb_12)
);
defparam un84_sop_0_0_0_11_6_0_axb_12_cZ.INIT=8'h7E;
// @8:30
LUT2 un84_sop_0_0_0_6_0_axb_0_1_cZ (
.I0(un1_x_7_0[2]),
.I1(un1_x_8_0[4]),
.O(un84_sop_0_0_0_6_0_axb_0_1)
);
defparam un84_sop_0_0_0_6_0_axb_0_1_cZ.INIT=4'h6;
// @8:30
LUT4 un84_sop_0_0_0_6_6_0_axb_12_cZ (
.I0(un1_x_7_0[13]),
.I1(un1_x_7_0[14]),
.I2(un1_x_8_0[15]),
.I3(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_axb_12)
);
defparam un84_sop_0_0_0_6_6_0_axb_12_cZ.INIT=16'h399C;
// @8:30
LUT4 un84_sop_0_0_0_6_6_0_axb_13_cZ (
.I0(un1_x_7_0[14]),
.I1(un1_x_7_0[15]),
.I2(un1_x_8_0[15]),
.I3(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_axb_13)
);
defparam un84_sop_0_0_0_6_6_0_axb_13_cZ.INIT=16'h399C;
// @8:30
LUT2 un84_sop_0_0_0_1_6_8_axb_0 (
.I0(un84_sop_0_0_0_10_0[3]),
.I1(x_4[0]),
.O(un84_sop_0_0_0_1_6_8[3])
);
defparam un84_sop_0_0_0_1_6_8_axb_0.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_8_axb_1_cZ (
.I0(un84_sop_0_0_0_10_0[4]),
.I1(x_4[1]),
.O(un84_sop_0_0_0_1_6_8_axb_1)
);
defparam un84_sop_0_0_0_1_6_8_axb_1_cZ.INIT=4'h6;
// @8:30
LUT4 un84_sop_0_0_0_1_6_8_axb_9_cZ (
.I0(un84_sop_0_0_0_10_0[11]),
.I1(un84_sop_0_0_0_10_0[12]),
.I2(x_4[6]),
.I3(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_axb_9)
);
defparam un84_sop_0_0_0_1_6_8_axb_9_cZ.INIT=16'h366C;
// @8:30
LUT2 un84_sop_0_0_0_1_6_8_axb_10_cZ (
.I0(un84_sop_0_0_0_10_0[13]),
.I1(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_axb_10)
);
defparam un84_sop_0_0_0_1_6_8_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_6_0_axb_0_0_cZ (
.I0(un1_x_1[4]),
.I1(un1_x_2[5]),
.O(un84_sop_1_6_0_axb_0_0)
);
defparam un84_sop_1_6_0_axb_0_0_cZ.INIT=4'h6;
// @8:30
LUT3 un84_sop_1_6_0_axb_12_cZ (
.I0(un1_x_1[15]),
.I1(un1_x_2[15]),
.I2(un1_x_3[15]),
.O(un84_sop_1_6_0_axb_12)
);
defparam un84_sop_1_6_0_axb_12_cZ.INIT=8'h7E;
// @8:30
LUT3 un1_x_10_axb_4_cZ (
.I0(un1_x_10_4[4]),
.I1(x_8[0]),
.I2(x_8[1]),
.O(un1_x_10_axb_4)
);
defparam un1_x_10_axb_4_cZ.INIT=8'h96;
// @8:30
LUT4 un1_x_10_axb_5_cZ (
.I0(un1_x_10_4[5]),
.I1(x_8[0]),
.I2(x_8[1]),
.I3(x_8[2]),
.O(un1_x_10_axb_5)
);
defparam un1_x_10_axb_5_cZ.INIT=16'hA956;
// @8:30
LUT3 un1_x_10_axb_8_cZ (
.I0(un1_x_10_4[8]),
.I1(un1_x_10_5_c5),
.I2(x_8[5]),
.O(un1_x_10_axb_8)
);
defparam un1_x_10_axb_8_cZ.INIT=8'h69;
// @8:30
LUT4 un1_x_10_axb_9_cZ (
.I0(un1_x_10_5_c5),
.I1(x_8[5]),
.I2(x_8[6]),
.I3(x_8[7]),
.O(un1_x_10_axb_9)
);
defparam un1_x_10_axb_9_cZ.INIT=16'hD22D;
// @8:30
LUT3 un1_x_10_axb_10_cZ (
.I0(un1_x_10_5_c5),
.I1(x_8[5]),
.I2(x_8[6]),
.O(un1_x_10_axb_10)
);
defparam un1_x_10_axb_10_cZ.INIT=8'hFD;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_0 (
.I0(un1_x_6_0[1]),
.I1(un84_sop_0_0_0_10_0[0]),
.O(un84_sop_0_0_0_1_6_4[0])
);
defparam un84_sop_0_0_0_1_6_4_axb_0.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_1_cZ (
.I0(un1_x_6_0[2]),
.I1(un84_sop_0_0_0_10_0[1]),
.O(un84_sop_0_0_0_1_6_4_axb_1)
);
defparam un84_sop_0_0_0_1_6_4_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_2_cZ (
.I0(un1_x_6_0[3]),
.I1(un84_sop_0_0_0_10_0[2]),
.O(un84_sop_0_0_0_1_6_4_axb_2)
);
defparam un84_sop_0_0_0_1_6_4_axb_2_cZ.INIT=4'h6;
// @8:30
LUT3 un84_sop_0_0_0_1_6_4_axb_3_cZ (
.I0(un1_x_6_0[4]),
.I1(un84_sop_0_0_0_10_0[3]),
.I2(x_4[0]),
.O(un84_sop_0_0_0_1_6_4_axb_3)
);
defparam un84_sop_0_0_0_1_6_4_axb_3_cZ.INIT=8'h96;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_4_cZ (
.I0(un1_x_6_0[5]),
.I1(un84_sop_0_0_0_1_6_8[4]),
.O(un84_sop_0_0_0_1_6_4_axb_4)
);
defparam un84_sop_0_0_0_1_6_4_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_5_cZ (
.I0(un1_x_6_0[6]),
.I1(un84_sop_0_0_0_1_6_8[5]),
.O(un84_sop_0_0_0_1_6_4_axb_5)
);
defparam un84_sop_0_0_0_1_6_4_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_6_cZ (
.I0(un1_x_6_0[7]),
.I1(un84_sop_0_0_0_1_6_8[6]),
.O(un84_sop_0_0_0_1_6_4_axb_6)
);
defparam un84_sop_0_0_0_1_6_4_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_7_cZ (
.I0(un1_x_6_0[8]),
.I1(un84_sop_0_0_0_1_6_8[7]),
.O(un84_sop_0_0_0_1_6_4_axb_7)
);
defparam un84_sop_0_0_0_1_6_4_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_8_cZ (
.I0(un1_x_6_0[9]),
.I1(un84_sop_0_0_0_1_6_8[8]),
.O(un84_sop_0_0_0_1_6_4_axb_8)
);
defparam un84_sop_0_0_0_1_6_4_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_9_cZ (
.I0(un1_x_6_0[10]),
.I1(un84_sop_0_0_0_1_6_8[9]),
.O(un84_sop_0_0_0_1_6_4_axb_9)
);
defparam un84_sop_0_0_0_1_6_4_axb_9_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_10_cZ (
.I0(un1_x_6_0[11]),
.I1(un84_sop_0_0_0_1_6_8[10]),
.O(un84_sop_0_0_0_1_6_4_axb_10)
);
defparam un84_sop_0_0_0_1_6_4_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_11_cZ (
.I0(un1_x_6_0[12]),
.I1(un84_sop_0_0_0_1_6_8[11]),
.O(un84_sop_0_0_0_1_6_4_axb_11)
);
defparam un84_sop_0_0_0_1_6_4_axb_11_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_12_cZ (
.I0(un1_x_6_0[13]),
.I1(un84_sop_0_0_0_1_6_8[12]),
.O(un84_sop_0_0_0_1_6_4_axb_12)
);
defparam un84_sop_0_0_0_1_6_4_axb_12_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_13_cZ (
.I0(un1_x_6_0[14]),
.I1(un84_sop_0_0_0_1_6_8[13]),
.O(un84_sop_0_0_0_1_6_4_axb_13)
);
defparam un84_sop_0_0_0_1_6_4_axb_13_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_1_cZ (
.I0(un1_x_4[3]),
.I1(un84_sop_0_0_0_0_5[1]),
.O(un84_sop_1_7_axb_1)
);
defparam un84_sop_1_7_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_2_cZ (
.I0(un1_x_4[4]),
.I1(un84_sop_0_0_0_0_5[2]),
.O(un84_sop_1_7_axb_2)
);
defparam un84_sop_1_7_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_3_cZ (
.I0(un1_x_4[5]),
.I1(un84_sop_0_0_0_0_5[3]),
.O(un84_sop_1_7_axb_3)
);
defparam un84_sop_1_7_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_4_cZ (
.I0(un1_x_4[6]),
.I1(un84_sop_0_0_0_0_5[4]),
.O(un84_sop_1_7_axb_4)
);
defparam un84_sop_1_7_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_5_cZ (
.I0(un1_x_4[7]),
.I1(un84_sop_0_0_0_0_5[5]),
.O(un84_sop_1_7_axb_5)
);
defparam un84_sop_1_7_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_6_cZ (
.I0(un1_x_4[8]),
.I1(un84_sop_0_0_0_0_5[6]),
.O(un84_sop_1_7_axb_6)
);
defparam un84_sop_1_7_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_7_cZ (
.I0(un1_x_4[9]),
.I1(un84_sop_0_0_0_0_5[7]),
.O(un84_sop_1_7_axb_7)
);
defparam un84_sop_1_7_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_8_cZ (
.I0(un1_x_4[10]),
.I1(un84_sop_0_0_0_0_5[8]),
.O(un84_sop_1_7_axb_8)
);
defparam un84_sop_1_7_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_9_cZ (
.I0(un1_x_4[11]),
.I1(un84_sop_0_0_0_0_5[9]),
.O(un84_sop_1_7_axb_9)
);
defparam un84_sop_1_7_axb_9_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_10_cZ (
.I0(un1_x_4[12]),
.I1(un84_sop_0_0_0_0_5[10]),
.O(un84_sop_1_7_axb_10)
);
defparam un84_sop_1_7_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_11_cZ (
.I0(un1_x_4[13]),
.I1(un84_sop_0_0_0_0_5[11]),
.O(un84_sop_1_7_axb_11)
);
defparam un84_sop_1_7_axb_11_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_12_cZ (
.I0(un1_x_4[14]),
.I1(un84_sop_0_0_0_0_5[12]),
.O(un84_sop_1_7_axb_12)
);
defparam un84_sop_1_7_axb_12_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_13_cZ (
.I0(un1_x_4[15]),
.I1(un84_sop_0_0_0_0_5[13]),
.O(un84_sop_1_7_axb_13)
);
defparam un84_sop_1_7_axb_13_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_0 (
.I0(un84_sop_0_0_0_0_0[0]),
.I1(x_9[0]),
.O(un84_sop_0_0_0_0_11_7[0])
);
defparam un84_sop_0_0_0_0_11_7_axb_0.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_1_cZ (
.I0(un1_x_11_0_0[7]),
.I1(un84_sop_0_0_0_0_0[1]),
.O(un84_sop_0_0_0_0_11_7_axb_1)
);
defparam un84_sop_0_0_0_0_11_7_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_2_cZ (
.I0(un1_x_11_0_0[8]),
.I1(un84_sop_0_0_0_0_0[2]),
.O(un84_sop_0_0_0_0_11_7_axb_2)
);
defparam un84_sop_0_0_0_0_11_7_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_3_cZ (
.I0(un1_x_11_0_0[9]),
.I1(un84_sop_0_0_0_0_0[3]),
.O(un84_sop_0_0_0_0_11_7_axb_3)
);
defparam un84_sop_0_0_0_0_11_7_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_4_cZ (
.I0(un1_x_11_0_0[10]),
.I1(un84_sop_0_0_0_0_0[4]),
.O(un84_sop_0_0_0_0_11_7_axb_4)
);
defparam un84_sop_0_0_0_0_11_7_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_5_cZ (
.I0(un1_x_11_0_0[11]),
.I1(un84_sop_0_0_0_0_0[5]),
.O(un84_sop_0_0_0_0_11_7_axb_5)
);
defparam un84_sop_0_0_0_0_11_7_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_6_cZ (
.I0(un1_x_11_0_0[12]),
.I1(un84_sop_0_0_0_0_0[6]),
.O(un84_sop_0_0_0_0_11_7_axb_6)
);
defparam un84_sop_0_0_0_0_11_7_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_7_cZ (
.I0(un1_x_11_0_0[13]),
.I1(un84_sop_0_0_0_0_0[7]),
.O(un84_sop_0_0_0_0_11_7_axb_7)
);
defparam un84_sop_0_0_0_0_11_7_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_8_cZ (
.I0(un1_x_11_0_0[14]),
.I1(un84_sop_0_0_0_0_0[8]),
.O(un84_sop_0_0_0_0_11_7_axb_8)
);
defparam un84_sop_0_0_0_0_11_7_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_9_cZ (
.I0(un1_x_11_0_0[14]),
.I1(un84_sop_0_0_0_0_0[9]),
.O(un84_sop_0_0_0_0_11_7_axb_9)
);
defparam un84_sop_0_0_0_0_11_7_axb_9_cZ.INIT=4'h6;
LUT3 un84_sop_1_4_cry_0_RNO (
.I0(un1_x_4[2]),
.I1(un84_sop_0_0_0_0_5[0]),
.I2(x_0[0]),
.O(un84_sop_1_4[0])
);
defparam un84_sop_1_4_cry_0_RNO.INIT=8'h96;
// @8:30
LUT3 un84_sop_1_4_axb_1_cZ (
.I0(un84_sop_1_7[1]),
.I1(x_0[0]),
.I2(x_0[1]),
.O(un84_sop_1_4_axb_1)
);
defparam un84_sop_1_4_axb_1_cZ.INIT=8'h96;
// @8:30
LUT4 un84_sop_1_4_axb_2_cZ (
.I0(un84_sop_1_7[2]),
.I1(x_0[0]),
.I2(x_0[1]),
.I3(x_0[2]),
.O(un84_sop_1_4_axb_2)
);
defparam un84_sop_1_4_axb_2_cZ.INIT=16'hA956;
// @8:30
LUT4 un84_sop_1_4_axb_5_cZ (
.I0(un1_x_0_0_c4),
.I1(un84_sop_1_7[5]),
.I2(x_0[4]),
.I3(x_0[5]),
.O(un84_sop_1_4_axb_5)
);
defparam un84_sop_1_4_axb_5_cZ.INIT=16'hC639;
// @8:30
LUT4 un84_sop_1_axb_0_cZ (
.I0(un1_x_4[2]),
.I1(un84_sop_0_0_0_0_5[0]),
.I2(un84_sop_1_6[0]),
.I3(x_0[0]),
.O(un84_sop_1_axb_0)
);
defparam un84_sop_1_axb_0_cZ.INIT=16'h6996;
// @8:30
LUT2 un84_sop_1_axb_1_cZ (
.I0(un84_sop_1_4[1]),
.I1(un84_sop_1_6[1]),
.O(un84_sop_1_axb_1)
);
defparam un84_sop_1_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_axb_2_cZ (
.I0(un84_sop_1_4[2]),
.I1(un84_sop_1_6[2]),
.O(un84_sop_1_axb_2)
);
defparam un84_sop_1_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_axb_3_cZ (
.I0(un84_sop_1_4[3]),
.I1(un84_sop_1_6[3]),
.O(un84_sop_1_axb_3)
);
defparam un84_sop_1_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_axb_4_cZ (
.I0(un84_sop_1_4[4]),
.I1(un84_sop_1_6[4]),
.O(un84_sop_1_axb_4)
);
defparam un84_sop_1_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_axb_5_cZ (
.I0(un84_sop_1_4[5]),
.I1(un84_sop_1_6[5]),
.O(un84_sop_1_axb_5)
);
defparam un84_sop_1_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_axb_6_cZ (
.I0(un84_sop_1_4[6]),
.I1(un84_sop_1_6[6]),
.O(un84_sop_1_axb_6)
);
defparam un84_sop_1_axb_6_cZ.INIT=4'h6;
LUT2 un1_x_10_4_cry_1_RNO (
.I0(x_8[0]),
.I1(x_8[1]),
.O(un1_x_10_4_cry_1_sf)
);
defparam un1_x_10_4_cry_1_RNO.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_2_cZ (
.I0(x_8[1]),
.I1(x_8[2]),
.O(un1_x_10_4_axb_2)
);
defparam un1_x_10_4_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_3_cZ (
.I0(x_8[2]),
.I1(x_8[3]),
.O(un1_x_10_4_axb_3)
);
defparam un1_x_10_4_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_4_cZ (
.I0(x_8[3]),
.I1(x_8[4]),
.O(un1_x_10_4_axb_4)
);
defparam un1_x_10_4_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_5_cZ (
.I0(x_8[4]),
.I1(x_8[5]),
.O(un1_x_10_4_axb_5)
);
defparam un1_x_10_4_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_6_cZ (
.I0(x_8[5]),
.I1(x_8[6]),
.O(un1_x_10_4_axb_6)
);
defparam un1_x_10_4_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_4_axb_7_cZ (
.I0(x_8[6]),
.I1(x_8[7]),
.O(un1_x_10_4_axb_7)
);
defparam un1_x_10_4_axb_7_cZ.INIT=4'h6;
// @8:30
LUT1 un1_x_15_0_axb_0_cZ (
.I0(x_12[0]),
.O(un1_x_15_0_axb_0)
);
defparam un1_x_15_0_axb_0_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_1_cZ (
.I0(x_12[1]),
.O(un1_x_15_0_axb_1)
);
defparam un1_x_15_0_axb_1_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_2_cZ (
.I0(x_12[2]),
.O(un1_x_15_0_axb_2)
);
defparam un1_x_15_0_axb_2_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_3_cZ (
.I0(x_12[3]),
.O(un1_x_15_0_axb_3)
);
defparam un1_x_15_0_axb_3_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_4_cZ (
.I0(x_12[4]),
.O(un1_x_15_0_axb_4)
);
defparam un1_x_15_0_axb_4_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_5_cZ (
.I0(x_12[5]),
.O(un1_x_15_0_axb_5)
);
defparam un1_x_15_0_axb_5_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_6_cZ (
.I0(x_12[6]),
.O(un1_x_15_0_axb_6)
);
defparam un1_x_15_0_axb_6_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_7_cZ (
.I0(x_12[7]),
.O(un1_x_15_0_axb_7)
);
defparam un1_x_15_0_axb_7_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_11_0_axb_0_cZ (
.I0(x_8[0]),
.O(un1_x_11_0_axb_0)
);
defparam un1_x_11_0_axb_0_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_0_cZ (
.I0(x_13[0]),
.O(un1_x_16_0_axb_0)
);
defparam un1_x_16_0_axb_0_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_1_cZ (
.I0(x_13[1]),
.O(un1_x_16_0_axb_1)
);
defparam un1_x_16_0_axb_1_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_2_cZ (
.I0(x_13[2]),
.O(un1_x_16_0_axb_2)
);
defparam un1_x_16_0_axb_2_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_3_cZ (
.I0(x_13[3]),
.O(un1_x_16_0_axb_3)
);
defparam un1_x_16_0_axb_3_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_4_cZ (
.I0(x_13[4]),
.O(un1_x_16_0_axb_4)
);
defparam un1_x_16_0_axb_4_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_5_cZ (
.I0(x_13[5]),
.O(un1_x_16_0_axb_5)
);
defparam un1_x_16_0_axb_5_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_6_cZ (
.I0(x_13[6]),
.O(un1_x_16_0_axb_6)
);
defparam un1_x_16_0_axb_6_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_16_0_axb_7_cZ (
.I0(x_13[7]),
.O(un1_x_16_0_axb_7)
);
defparam un1_x_16_0_axb_7_cZ.INIT=2'h1;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_0_ci_cZ (
.I0(un84_sop_0_0_0_0_0[0]),
.I1(x_9[0]),
.O(un84_sop_0_0_0_0_11_7_axb_0_ci)
);
defparam un84_sop_0_0_0_0_11_7_axb_0_ci_cZ.INIT=4'h6;
// @8:30
LUT1 un84_sop_0_0_0_11_6_0_cry_0_thru (
.I0(un1_x_14_0_0[4]),
.O(un1_x_14_0_0_0[4])
);
defparam un84_sop_0_0_0_11_6_0_cry_0_thru.INIT=2'h2;
// @8:30
LUT1 un84_sop_0_0_0_6_6_0_cry_0_thru (
.I0(un1_x_9_0[5]),
.O(un1_x_9_0_0[5])
);
defparam un84_sop_0_0_0_6_6_0_cry_0_thru.INIT=2'h2;
// @8:30
LUT1 un84_sop_1_6_0_cry_0_thru (
.I0(un1_x_3[4]),
.O(un1_x_3_0[4])
);
defparam un84_sop_1_6_0_cry_0_thru.INIT=2'h2;
// @8:21
FD \x_0_Z[0] (
.Q(x_0[0]),
.D(x_in[0]),
.C(clk)
);
// @8:21
FD \x_0_Z[1] (
.Q(x_0[1]),
.D(x_in[1]),
.C(clk)
);
// @8:21
FD \x_0_Z[2] (
.Q(x_0[2]),
.D(x_in[2]),
.C(clk)
);
// @8:21
FD \x_0_Z[3] (
.Q(x_0[3]),
.D(x_in[3]),
.C(clk)
);
// @8:21
FD \x_0_Z[4] (
.Q(x_0[4]),
.D(x_in[4]),
.C(clk)
);
// @8:21
FD \x_0_Z[5] (
.Q(x_0[5]),
.D(x_in[5]),
.C(clk)
);
// @8:21
FD \x_0_Z[6] (
.Q(x_0[6]),
.D(x_in[6]),
.C(clk)
);
// @8:21
FD \x_0_Z[7] (
.Q(x_0[7]),
.D(x_in[7]),
.C(clk)
);
// @8:21
FD \y_Z[7] (
.Q(y[7]),
.D(un84_sop_1_s_14),
.C(clk)
);
// @8:21
FD \y_Z[0] (
.Q(y[0]),
.D(un84_sop_1_s_7),
.C(clk)
);
// @8:21
FD \y_Z[1] (
.Q(y[1]),
.D(un84_sop_1_s_8),
.C(clk)
);
// @8:21
FD \y_Z[2] (
.Q(y[2]),
.D(un84_sop_1_s_9),
.C(clk)
);
// @8:21
FD \y_Z[3] (
.Q(y[3]),
.D(un84_sop_1_s_10),
.C(clk)
);
// @8:21
FD \y_Z[4] (
.Q(y[4]),
.D(un84_sop_1_s_11),
.C(clk)
);
// @8:21
FD \y_Z[5] (
.Q(y[5]),
.D(un84_sop_1_s_12),
.C(clk)
);
// @8:21
FD \y_Z[6] (
.Q(y[6]),
.D(un84_sop_1_s_13),
.C(clk)
);
// @8:21
FD \x_8_Z[7] (
.Q(x_8[7]),
.D(x_7[7]),
.C(clk)
);
// @8:21
FD \x_8_Z[6] (
.Q(x_8[6]),
.D(x_7[6]),
.C(clk)
);
// @8:21
FD \x_8_Z[5] (
.Q(x_8[5]),
.D(x_7[5]),
.C(clk)
);
// @8:21
FD \x_8_Z[4] (
.Q(x_8[4]),
.D(x_7[4]),
.C(clk)
);
// @8:21
FD \x_8_Z[3] (
.Q(x_8[3]),
.D(x_7[3]),
.C(clk)
);
// @8:21
FD \x_8_Z[2] (
.Q(x_8[2]),
.D(x_7[2]),
.C(clk)
);
// @8:21
FD \x_8_Z[1] (
.Q(x_8[1]),
.D(x_7[1]),
.C(clk)
);
// @8:21
FD \x_8_Z[0] (
.Q(x_8[0]),
.D(x_7[0]),
.C(clk)
);
// @8:21
FD \x_9_Z[0] (
.Q(x_9[0]),
.D(x_8[0]),
.C(clk)
);
// @8:21
FD \x_13_Z[7] (
.Q(x_13[7]),
.D(x_12[7]),
.C(clk)
);
// @8:21
FD \x_13_Z[6] (
.Q(x_13[6]),
.D(x_12[6]),
.C(clk)
);
// @8:21
FD \x_13_Z[5] (
.Q(x_13[5]),
.D(x_12[5]),
.C(clk)
);
// @8:21
FD \x_13_Z[4] (
.Q(x_13[4]),
.D(x_12[4]),
.C(clk)
);
// @8:21
FD \x_13_Z[3] (
.Q(x_13[3]),
.D(x_12[3]),
.C(clk)
);
// @8:21
FD \x_13_Z[2] (
.Q(x_13[2]),
.D(x_12[2]),
.C(clk)
);
// @8:21
FD \x_13_Z[1] (
.Q(x_13[1]),
.D(x_12[1]),
.C(clk)
);
// @8:21
FD \x_13_Z[0] (
.Q(x_13[0]),
.D(x_12[0]),
.C(clk)
);
FD x_14_pipe_0_Z (
.Q(un84_sop_0_0_0_0_0[0]),
.D(un84_sop_0_0_0_0_1[0]),
.C(clk)
);
FD x_14_pipe_9_Z (
.Q(un84_sop_0_0_0_0_0[1]),
.D(un84_sop_0_0_0_0_1[1]),
.C(clk)
);
FD x_14_pipe_10_Z (
.Q(un84_sop_0_0_0_0_0[2]),
.D(un84_sop_0_0_0_0_1[2]),
.C(clk)
);
FD x_14_pipe_11_Z (
.Q(un84_sop_0_0_0_0_0[3]),
.D(un84_sop_0_0_0_0_1[3]),
.C(clk)
);
FD x_14_pipe_12_Z (
.Q(un84_sop_0_0_0_0_0[4]),
.D(un84_sop_0_0_0_0_1[4]),
.C(clk)
);
FD x_14_pipe_13_Z (
.Q(un84_sop_0_0_0_0_0[5]),
.D(un84_sop_0_0_0_0_1[5]),
.C(clk)
);
FD x_14_pipe_14_Z (
.Q(un84_sop_0_0_0_0_0[6]),
.D(un84_sop_0_0_0_0_1[6]),
.C(clk)
);
FD x_14_pipe_15_Z (
.Q(un84_sop_0_0_0_0_0[7]),
.D(un84_sop_0_0_0_0_1[7]),
.C(clk)
);
FD x_14_pipe_16_Z (
.Q(un84_sop_0_0_0_0_0[8]),
.D(un84_sop_0_0_0_0_1[8]),
.C(clk)
);
FD x_14_pipe_17_Z (
.Q(un84_sop_0_0_0_0_0[9]),
.D(un84_sop_0_0_0_0_1[9]),
.C(clk)
);
FD x_9_pipe_1_Z (
.Q(un1_x_11_0_0[7]),
.D(un1_x_11_0_0_0[7]),
.C(clk)
);
FD x_9_pipe_2_Z (
.Q(un1_x_11_0_0[8]),
.D(un1_x_11_0_0_0[8]),
.C(clk)
);
FD x_9_pipe_3_Z (
.Q(un1_x_11_0_0[9]),
.D(un1_x_11_0_0_0[9]),
.C(clk)
);
FD x_9_pipe_4_Z (
.Q(un1_x_11_0_0[10]),
.D(un1_x_11_0_0_0[10]),
.C(clk)
);
FD x_9_pipe_5_Z (
.Q(un1_x_11_0_0[11]),
.D(un1_x_11_0_0_0[11]),
.C(clk)
);
FD x_9_pipe_6_Z (
.Q(un1_x_11_0_0[12]),
.D(un1_x_11_0_0_0[12]),
.C(clk)
);
FD x_9_pipe_7_Z (
.Q(un1_x_11_0_0[13]),
.D(un1_x_11_0_0_0[13]),
.C(clk)
);
FD x_9_pipe_8_Z (
.Q(un1_x_11_0_0[14]),
.D(un1_x_11_0_0_0[14]),
.C(clk)
);
FD x_15_pipe_0_0_15_Z (
.Q(un84_sop_0_0_0_10_0[0]),
.D(un84_sop_0_0_0_0_8[0]),
.C(clk)
);
FD x_15_pipe_0_0_16_Z (
.Q(un84_sop_0_0_0_10_0[1]),
.D(un84_sop_0_0_0_0_8[1]),
.C(clk)
);
FD x_15_pipe_0_0_17_Z (
.Q(un84_sop_0_0_0_10_0[2]),
.D(un84_sop_0_0_0_0_8[2]),
.C(clk)
);
FD x_15_pipe_0_0_18_Z (
.Q(un84_sop_0_0_0_10_0[3]),
.D(un84_sop_0_0_0_0_8[3]),
.C(clk)
);
FD x_15_pipe_0_0_19_Z (
.Q(un84_sop_0_0_0_10_0[4]),
.D(un84_sop_0_0_0_0_8[4]),
.C(clk)
);
FD x_15_pipe_0_0_20_Z (
.Q(un84_sop_0_0_0_10_0[5]),
.D(un84_sop_0_0_0_0_8[5]),
.C(clk)
);
FD x_15_pipe_0_0_21_Z (
.Q(un84_sop_0_0_0_10_0[6]),
.D(un84_sop_0_0_0_0_8[6]),
.C(clk)
);
FD x_15_pipe_0_0_22_Z (
.Q(un84_sop_0_0_0_10_0[7]),
.D(un84_sop_0_0_0_0_8[7]),
.C(clk)
);
FD x_15_pipe_0_0_23_Z (
.Q(un84_sop_0_0_0_10_0[8]),
.D(un84_sop_0_0_0_0_8[8]),
.C(clk)
);
FD x_15_pipe_0_0_24_Z (
.Q(un84_sop_0_0_0_10_0[9]),
.D(un84_sop_0_0_0_0_8[9]),
.C(clk)
);
FD x_15_pipe_0_0_25_Z (
.Q(un84_sop_0_0_0_10_0[10]),
.D(un84_sop_0_0_0_0_8[10]),
.C(clk)
);
FD x_15_pipe_0_0_26_Z (
.Q(un84_sop_0_0_0_10_0[11]),
.D(un84_sop_0_0_0_0_8[11]),
.C(clk)
);
FD x_15_pipe_0_0_27_Z (
.Q(un84_sop_0_0_0_10_0[12]),
.D(un84_sop_0_0_0_0_8[12]),
.C(clk)
);
FD x_15_pipe_0_0_28_Z (
.Q(un84_sop_0_0_0_10_0[13]),
.D(un84_sop_0_0_0_0_8[13]),
.C(clk)
);
FD x_15_pipe_0_0_29_Z (
.Q(un84_sop_0_0_0_10_0[14]),
.D(un84_sop_0_0_0_0_8[14]),
.C(clk)
);
FD x_16_pipe_0_0_0_Z (
.Q(un84_sop_0_0_0_0_5[0]),
.D(un84_sop_0_0_0_5_0[0]),
.C(clk)
);
FD x_16_pipe_0_0_1_Z (
.Q(un84_sop_0_0_0_0_5[1]),
.D(un84_sop_0_0_0_5_0[1]),
.C(clk)
);
FD x_16_pipe_0_0_2_Z (
.Q(un84_sop_0_0_0_0_5[2]),
.D(un84_sop_0_0_0_5_0[2]),
.C(clk)
);
FD x_16_pipe_0_0_3_Z (
.Q(un84_sop_0_0_0_0_5[3]),
.D(un84_sop_0_0_0_5_0[3]),
.C(clk)
);
FD x_16_pipe_0_0_4_Z (
.Q(un84_sop_0_0_0_0_5[4]),
.D(un84_sop_0_0_0_5_0[4]),
.C(clk)
);
FD x_16_pipe_0_0_5_Z (
.Q(un84_sop_0_0_0_0_5[5]),
.D(un84_sop_0_0_0_5_0[5]),
.C(clk)
);
FD x_16_pipe_0_0_6_Z (
.Q(un84_sop_0_0_0_0_5[6]),
.D(un84_sop_0_0_0_5_0[6]),
.C(clk)
);
FD x_16_pipe_0_0_7_Z (
.Q(un84_sop_0_0_0_0_5[7]),
.D(un84_sop_0_0_0_5_0[7]),
.C(clk)
);
FD x_16_pipe_0_0_8_Z (
.Q(un84_sop_0_0_0_0_5[8]),
.D(un84_sop_0_0_0_5_0[8]),
.C(clk)
);
FD x_16_pipe_0_0_9_Z (
.Q(un84_sop_0_0_0_0_5[9]),
.D(un84_sop_0_0_0_5_0[9]),
.C(clk)
);
FD x_16_pipe_0_0_10_Z (
.Q(un84_sop_0_0_0_0_5[10]),
.D(un84_sop_0_0_0_5_0[10]),
.C(clk)
);
FD x_16_pipe_0_0_11_Z (
.Q(un84_sop_0_0_0_0_5[11]),
.D(un84_sop_0_0_0_5_0[11]),
.C(clk)
);
FD x_16_pipe_0_0_12_Z (
.Q(un84_sop_0_0_0_0_5[12]),
.D(un84_sop_0_0_0_5_0[12]),
.C(clk)
);
FD x_16_pipe_0_0_13_Z (
.Q(un84_sop_0_0_0_0_5[13]),
.D(un84_sop_0_0_0_5_0[13]),
.C(clk)
);
FD x_16_pipe_0_0_14_Z (
.Q(un84_sop_0_0_0_0_5[14]),
.D(un84_sop_0_0_0_5_0[14]),
.C(clk)
);
// @8:21
FD \x_4_DOUT_Z[0] (
.Q(x_4[7]),
.D(x_4_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_0_DOUT_Z[0] (
.Q(x_4[6]),
.D(x_4_0_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_1_DOUT_Z[0] (
.Q(x_4[5]),
.D(x_4_1_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_2_DOUT_Z[0] (
.Q(x_4[4]),
.D(x_4_2_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_3_DOUT_Z[0] (
.Q(x_4[3]),
.D(x_4_3_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_4_DOUT_Z[0] (
.Q(x_4[2]),
.D(x_4_4_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_5_DOUT_Z[0] (
.Q(x_4[1]),
.D(x_4_5_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_4_6_DOUT_Z[0] (
.Q(x_4[0]),
.D(x_4_6_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_DOUT_Z[0] (
.Q(x_7[7]),
.D(x_7_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_0_DOUT_Z[0] (
.Q(x_7[6]),
.D(x_7_0_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_1_DOUT_Z[0] (
.Q(x_7[5]),
.D(x_7_1_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_2_DOUT_Z[0] (
.Q(x_7[4]),
.D(x_7_2_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_3_DOUT_Z[0] (
.Q(x_7[3]),
.D(x_7_3_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_4_DOUT_Z[0] (
.Q(x_7[2]),
.D(x_7_4_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_5_DOUT_Z[0] (
.Q(x_7[1]),
.D(x_7_5_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_7_6_DOUT_Z[0] (
.Q(x_7[0]),
.D(x_7_6_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_DOUT_Z[0] (
.Q(x_12[7]),
.D(x_12_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_0_DOUT_Z[0] (
.Q(x_12[6]),
.D(x_12_0_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_1_DOUT_Z[0] (
.Q(x_12[5]),
.D(x_12_1_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_2_DOUT_Z[0] (
.Q(x_12[4]),
.D(x_12_2_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_3_DOUT_Z[0] (
.Q(x_12[3]),
.D(x_12_3_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_4_DOUT_Z[0] (
.Q(x_12[2]),
.D(x_12_4_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_5_DOUT_Z[0] (
.Q(x_12[1]),
.D(x_12_5_tmp_d_array_0[0]),
.C(clk)
);
// @8:21
FD \x_12_6_DOUT_Z[0] (
.Q(x_12[0]),
.D(x_12_6_tmp_d_array_0[0]),
.C(clk)
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_3_0[4]),
.LO(un84_sop_1_6_0_cry_0_cy)
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_9_0_0[5]),
.LO(un84_sop_0_0_0_6_6_0_cry_0_cy)
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_14_0_0_0[4]),
.LO(un84_sop_0_0_0_11_6_0_cry_0_cy)
);
LUT3 un84_sop_0_0_0_11_0_cry_2_RNO_cZ (
.I0(x_8[1]),
.I1(x_8[0]),
.I2(un84_sop_0_0_0_0_11_7[1]),
.O(un84_sop_0_0_0_11_0_cry_2_RNO)
);
defparam un84_sop_0_0_0_11_0_cry_2_RNO_cZ.INIT=8'h60;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_8_cZ (
.I0(un1_x_12_0_0[11]),
.I1(un1_x_12_0_0[12]),
.I2(un1_x_13_0_0[12]),
.I3(un1_x_13_0_0[13]),
.I4(un1_x_14_0_0[11]),
.I5(un1_x_14_0_0[12]),
.O(un84_sop_0_0_0_11_6_0_axb_8)
);
defparam un84_sop_0_0_0_11_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_3_cZ (
.I0(un1_x_12_0_0[6]),
.I1(un1_x_12_0_0[7]),
.I2(un1_x_13_0_0[7]),
.I3(un1_x_13_0_0[8]),
.I4(un1_x_14_0_0[6]),
.I5(un1_x_14_0_0[7]),
.O(un84_sop_0_0_0_11_6_0_axb_3)
);
defparam un84_sop_0_0_0_11_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_4_cZ (
.I0(un1_x_12_0_0[7]),
.I1(un1_x_12_0_0[8]),
.I2(un1_x_13_0_0[8]),
.I3(un1_x_13_0_0[9]),
.I4(un1_x_14_0_0[7]),
.I5(un1_x_14_0_0[8]),
.O(un84_sop_0_0_0_11_6_0_axb_4)
);
defparam un84_sop_0_0_0_11_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_9_cZ (
.I0(un1_x_12_0_0[12]),
.I1(un1_x_12_0_0[13]),
.I2(un1_x_13_0_0[13]),
.I3(un1_x_13_0_0[14]),
.I4(un1_x_14_0_0[12]),
.I5(un1_x_14_0_0[13]),
.O(un84_sop_0_0_0_11_6_0_axb_9)
);
defparam un84_sop_0_0_0_11_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT5 un84_sop_0_0_0_11_6_0_axb_11_cZ (
.I0(un1_x_12_0_0[14]),
.I1(un1_x_14_0_0[14]),
.I2(un1_x_12_0_0[15]),
.I3(un1_x_14_0_0[15]),
.I4(un1_x_13_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_axb_11)
);
defparam un84_sop_0_0_0_11_6_0_axb_11_cZ.INIT=32'h1EE18778;
// @8:30
LUT6 un84_sop_1_6_0_axb_4_cZ (
.I0(un1_x_1[7]),
.I1(un1_x_1[8]),
.I2(un1_x_2[8]),
.I3(un1_x_2[9]),
.I4(un1_x_3[7]),
.I5(un1_x_3[8]),
.O(un84_sop_1_6_0_axb_4)
);
defparam un84_sop_1_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_10_cZ (
.I0(un1_x_12_0_0[13]),
.I1(un1_x_12_0_0[14]),
.I2(un1_x_13_0_0[14]),
.I3(un1_x_14_0_0[13]),
.I4(un1_x_14_0_0[14]),
.I5(un1_x_13_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_axb_10)
);
defparam un84_sop_0_0_0_11_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_2_cZ (
.I0(un1_x_12_0_0[5]),
.I1(un1_x_12_0_0[6]),
.I2(un1_x_13_0_0[6]),
.I3(un1_x_13_0_0[7]),
.I4(un1_x_14_0_0[5]),
.I5(un1_x_14_0_0[6]),
.O(un84_sop_0_0_0_11_6_0_axb_2)
);
defparam un84_sop_0_0_0_11_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_5_cZ (
.I0(un84_sop_0_0_0_0_11_7[4]),
.I1(un84_sop_0_0_0_0_11_7[5]),
.I2(un84_sop_0_0_0_0_11_6[4]),
.I3(un84_sop_0_0_0_0_11_6[5]),
.I4(un1_x_10_0_0[8]),
.I5(un1_x_10_0_0[9]),
.LO(un84_sop_0_0_0_11_0_axb_5)
);
defparam un84_sop_0_0_0_11_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_6_cZ (
.I0(un84_sop_0_0_0_0_11_7[5]),
.I1(un84_sop_0_0_0_0_11_7[6]),
.I2(un84_sop_0_0_0_0_11_6[5]),
.I3(un84_sop_0_0_0_0_11_6[6]),
.I4(un1_x_10_0_0[9]),
.I5(un1_x_10_0_0[10]),
.LO(un84_sop_0_0_0_11_0_axb_6)
);
defparam un84_sop_0_0_0_11_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_6_cZ (
.I0(un1_x_12_0_0[9]),
.I1(un1_x_12_0_0[10]),
.I2(un1_x_13_0_0[10]),
.I3(un1_x_13_0_0[11]),
.I4(un1_x_14_0_0[9]),
.I5(un1_x_14_0_0[10]),
.O(un84_sop_0_0_0_11_6_0_axb_6)
);
defparam un84_sop_0_0_0_11_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_7_cZ (
.I0(un1_x_12_0_0[10]),
.I1(un1_x_12_0_0[11]),
.I2(un1_x_13_0_0[11]),
.I3(un1_x_13_0_0[12]),
.I4(un1_x_14_0_0[10]),
.I5(un1_x_14_0_0[11]),
.O(un84_sop_0_0_0_11_6_0_axb_7)
);
defparam un84_sop_0_0_0_11_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_10_cZ (
.I0(un84_sop_0_0_0_0_11_7[9]),
.I1(un84_sop_0_0_0_0_11_7[14]),
.I2(un84_sop_0_0_0_0_11_6[9]),
.I3(un84_sop_0_0_0_0_11_6[10]),
.I4(un1_x_10_0_0[13]),
.I5(un1_x_10_0_0[14]),
.LO(un84_sop_0_0_0_11_0_axb_10)
);
defparam un84_sop_0_0_0_11_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT4_L un84_sop_0_0_0_11_0_axb_12_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[11]),
.I2(un84_sop_0_0_0_0_11_6[12]),
.I3(un1_x_10_0_0[15]),
.LO(un84_sop_0_0_0_11_0_axb_12)
);
defparam un84_sop_0_0_0_11_0_axb_12_cZ.INIT=16'h4BD2;
// @8:30
LUT4_L un84_sop_0_0_0_11_0_axb_13_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[14]),
.I2(un84_sop_0_0_0_0_11_6[12]),
.I3(un1_x_10_0_0[15]),
.LO(un84_sop_0_0_0_11_0_axb_13)
);
defparam un84_sop_0_0_0_11_0_axb_13_cZ.INIT=16'h63C6;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_axb_13_cZ (
.I0(un1_x_12_0_0[15]),
.I1(un1_x_14_0_0[15]),
.I2(un1_x_13_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_axb_13)
);
defparam un84_sop_0_0_0_11_6_0_axb_13_cZ.INIT=8'h7E;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_3_cZ (
.I0(un84_sop_0_0_0_0_11_7[2]),
.I1(un84_sop_0_0_0_0_11_7[3]),
.I2(un84_sop_0_0_0_0_11_6[2]),
.I3(un1_x_10_s_2_sf),
.I4(un1_x_10_axb_3),
.I5(un84_sop_0_0_0_0_11_6[3]),
.LO(un84_sop_0_0_0_11_0_axb_3)
);
defparam un84_sop_0_0_0_11_0_axb_3_cZ.INIT=64'h366CC993C993366C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_4_cZ (
.I0(un84_sop_0_0_0_0_11_7[3]),
.I1(un84_sop_0_0_0_0_11_7[4]),
.I2(un1_x_10_axb_3),
.I3(un84_sop_0_0_0_0_11_6[3]),
.I4(un84_sop_0_0_0_0_11_6[4]),
.I5(un1_x_10_0_0[8]),
.LO(un84_sop_0_0_0_11_0_axb_4)
);
defparam un84_sop_0_0_0_11_0_axb_4_cZ.INIT=64'h366CC993C993366C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_5_cZ (
.I0(un1_x_7_0[6]),
.I1(un1_x_7_0[7]),
.I2(un1_x_8_0[8]),
.I3(un1_x_8_0[9]),
.I4(un1_x_9_0[9]),
.I5(un1_x_9_0[10]),
.O(un84_sop_0_0_0_6_6_0_axb_5)
);
defparam un84_sop_0_0_0_6_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_6_cZ (
.I0(un1_x_7_0[7]),
.I1(un1_x_7_0[8]),
.I2(un1_x_8_0[9]),
.I3(un1_x_8_0[10]),
.I4(un1_x_9_0[10]),
.I5(un1_x_9_0[11]),
.O(un84_sop_0_0_0_6_6_0_axb_6)
);
defparam un84_sop_0_0_0_6_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_10_cZ (
.I0(un1_x_7_0[11]),
.I1(un1_x_7_0[12]),
.I2(un1_x_8_0[13]),
.I3(un1_x_8_0[14]),
.I4(un1_x_9_0[14]),
.I5(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_axb_10)
);
defparam un84_sop_0_0_0_6_6_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT5 un84_sop_0_0_0_6_6_0_axb_11_cZ (
.I0(un1_x_7_0[12]),
.I1(un1_x_7_0[13]),
.I2(un1_x_8_0[14]),
.I3(un1_x_8_0[15]),
.I4(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_axb_11)
);
defparam un84_sop_0_0_0_6_6_0_axb_11_cZ.INIT=32'h36C9936C;
// @8:30
LUT6 un84_sop_0_0_0_1_6_8_axb_3_cZ (
.I0(un84_sop_0_0_0_10_0[5]),
.I1(un84_sop_0_0_0_10_0[6]),
.I2(x_4[1]),
.I3(x_4[0]),
.I4(x_4[2]),
.I5(x_4[3]),
.O(un84_sop_0_0_0_1_6_8_axb_3)
);
defparam un84_sop_0_0_0_1_6_8_axb_3_cZ.INIT=64'h3C6969C3C396963C;
// @8:30
LUT6 un84_sop_0_0_0_1_6_8_axb_4_cZ (
.I0(un84_sop_0_0_0_10_0[6]),
.I1(un84_sop_0_0_0_10_0[7]),
.I2(x_4[1]),
.I3(x_4[2]),
.I4(x_4[3]),
.I5(x_4[4]),
.O(un84_sop_0_0_0_1_6_8_axb_4)
);
defparam un84_sop_0_0_0_1_6_8_axb_4_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_1_6_8_axb_5_cZ (
.I0(un84_sop_0_0_0_10_0[7]),
.I1(un84_sop_0_0_0_10_0[8]),
.I2(x_4[2]),
.I3(x_4[3]),
.I4(x_4[4]),
.I5(x_4[5]),
.O(un84_sop_0_0_0_1_6_8_axb_5)
);
defparam un84_sop_0_0_0_1_6_8_axb_5_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_1_6_8_axb_6_cZ (
.I0(un84_sop_0_0_0_10_0[8]),
.I1(un84_sop_0_0_0_10_0[9]),
.I2(x_4[6]),
.I3(x_4[3]),
.I4(x_4[4]),
.I5(x_4[5]),
.O(un84_sop_0_0_0_1_6_8_axb_6)
);
defparam un84_sop_0_0_0_1_6_8_axb_6_cZ.INIT=64'h3C69C39669C3963C;
// @8:30
LUT6 un84_sop_0_0_0_1_6_8_axb_7_cZ (
.I0(un84_sop_0_0_0_10_0[9]),
.I1(un84_sop_0_0_0_10_0[10]),
.I2(x_4[6]),
.I3(x_4[4]),
.I4(x_4[5]),
.I5(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_axb_7)
);
defparam un84_sop_0_0_0_1_6_8_axb_7_cZ.INIT=64'h366CC993C993366C;
// @8:30
LUT5 un84_sop_0_0_0_1_6_8_axb_8_cZ (
.I0(un84_sop_0_0_0_10_0[11]),
.I1(un84_sop_0_0_0_10_0[10]),
.I2(x_4[6]),
.I3(x_4[5]),
.I4(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_axb_8)
);
defparam un84_sop_0_0_0_1_6_8_axb_8_cZ.INIT=32'h5A69965A;
// @8:30
LUT6 un84_sop_0_0_0_11_6_0_axb_5_cZ (
.I0(un1_x_12_0_0[8]),
.I1(un1_x_12_0_0[9]),
.I2(un1_x_13_0_0[9]),
.I3(un1_x_13_0_0[10]),
.I4(un1_x_14_0_0[8]),
.I5(un1_x_14_0_0[9]),
.O(un84_sop_0_0_0_11_6_0_axb_5)
);
defparam un84_sop_0_0_0_11_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_2_cZ (
.I0(un1_x_1[5]),
.I1(un1_x_1[6]),
.I2(un1_x_2[6]),
.I3(un1_x_2[7]),
.I4(un1_x_3[5]),
.I5(un1_x_3[6]),
.O(un84_sop_1_6_0_axb_2)
);
defparam un84_sop_1_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_3_cZ (
.I0(un1_x_1[6]),
.I1(un1_x_1[7]),
.I2(un1_x_2[7]),
.I3(un1_x_2[8]),
.I4(un1_x_3[6]),
.I5(un1_x_3[7]),
.O(un84_sop_1_6_0_axb_3)
);
defparam un84_sop_1_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_5_cZ (
.I0(un1_x_1[8]),
.I1(un1_x_1[9]),
.I2(un1_x_2[9]),
.I3(un1_x_2[10]),
.I4(un1_x_3[8]),
.I5(un1_x_3[9]),
.O(un84_sop_1_6_0_axb_5)
);
defparam un84_sop_1_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_6_cZ (
.I0(un1_x_1[9]),
.I1(un1_x_1[10]),
.I2(un1_x_2[10]),
.I3(un1_x_2[11]),
.I4(un1_x_3[9]),
.I5(un1_x_3[10]),
.O(un84_sop_1_6_0_axb_6)
);
defparam un84_sop_1_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_7_cZ (
.I0(un1_x_1[10]),
.I1(un1_x_1[11]),
.I2(un1_x_2[11]),
.I3(un1_x_2[12]),
.I4(un1_x_3[10]),
.I5(un1_x_3[11]),
.O(un84_sop_1_6_0_axb_7)
);
defparam un84_sop_1_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_8_cZ (
.I0(un1_x_1[11]),
.I1(un1_x_1[12]),
.I2(un1_x_2[12]),
.I3(un1_x_2[13]),
.I4(un1_x_3[11]),
.I5(un1_x_3[12]),
.O(un84_sop_1_6_0_axb_8)
);
defparam un84_sop_1_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_9_cZ (
.I0(un1_x_1[12]),
.I1(un1_x_1[13]),
.I2(un1_x_2[13]),
.I3(un1_x_2[14]),
.I4(un1_x_3[12]),
.I5(un1_x_3[13]),
.O(un84_sop_1_6_0_axb_9)
);
defparam un84_sop_1_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_1_6_0_axb_10_cZ (
.I0(un1_x_1[13]),
.I1(un1_x_1[14]),
.I2(un1_x_2[14]),
.I3(un1_x_3[13]),
.I4(un1_x_3[14]),
.I5(un1_x_2[15]),
.O(un84_sop_1_6_0_axb_10)
);
defparam un84_sop_1_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
// @8:30
LUT5 un84_sop_1_6_0_axb_11_cZ (
.I0(un1_x_1[14]),
.I1(un1_x_3[14]),
.I2(un1_x_1[15]),
.I3(un1_x_3[15]),
.I4(un1_x_2[15]),
.O(un84_sop_1_6_0_axb_11)
);
defparam un84_sop_1_6_0_axb_11_cZ.INIT=32'h1EE18778;
// @8:30
LUT3 un84_sop_1_6_0_axb_13_cZ (
.I0(un1_x_1[15]),
.I1(un1_x_3[15]),
.I2(un1_x_2[15]),
.O(un84_sop_1_6_0_axb_13)
);
defparam un84_sop_1_6_0_axb_13_cZ.INIT=8'h7E;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_7_cZ (
.I0(un84_sop_0_0_0_0_11_7[6]),
.I1(un84_sop_0_0_0_0_11_7[7]),
.I2(un84_sop_0_0_0_0_11_6[6]),
.I3(un84_sop_0_0_0_0_11_6[7]),
.I4(un1_x_10_0_0[10]),
.I5(un1_x_10_0_0[11]),
.LO(un84_sop_0_0_0_11_0_axb_7)
);
defparam un84_sop_0_0_0_11_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_8_cZ (
.I0(un84_sop_0_0_0_0_11_7[7]),
.I1(un84_sop_0_0_0_0_11_7[8]),
.I2(un84_sop_0_0_0_0_11_6[7]),
.I3(un84_sop_0_0_0_0_11_6[8]),
.I4(un1_x_10_0_0[11]),
.I5(un1_x_10_0_0[12]),
.LO(un84_sop_0_0_0_11_0_axb_8)
);
defparam un84_sop_0_0_0_11_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6_L un84_sop_0_0_0_11_0_axb_9_cZ (
.I0(un84_sop_0_0_0_0_11_7[8]),
.I1(un84_sop_0_0_0_0_11_7[9]),
.I2(un84_sop_0_0_0_0_11_6[8]),
.I3(un84_sop_0_0_0_0_11_6[9]),
.I4(un1_x_10_0_0[12]),
.I5(un1_x_10_0_0[13]),
.LO(un84_sop_0_0_0_11_0_axb_9)
);
defparam un84_sop_0_0_0_11_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT4_L un84_sop_0_0_0_11_0_axb_1_cZ (
.I0(x_8[1]),
.I1(x_8[0]),
.I2(un84_sop_0_0_0_0_11_7[1]),
.I3(un84_sop_0_0_0_0_11_6[1]),
.LO(un84_sop_0_0_0_11_0_axb_1)
);
defparam un84_sop_0_0_0_11_0_axb_1_cZ.INIT=16'h6996;
// @8:30
LUT5_L un84_sop_0_0_0_11_0_axb_11_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[10]),
.I2(un84_sop_0_0_0_0_11_6[11]),
.I3(un1_x_10_0_0[14]),
.I4(un1_x_10_0_0[15]),
.LO(un84_sop_0_0_0_11_0_axb_11)
);
defparam un84_sop_0_0_0_11_0_axb_11_cZ.INIT=32'h4B2DB4D2;
// @8:30
LUT3 un84_sop_0_0_0_1_6_axb_0 (
.I0(un84_sop_0_0_0_10_0[0]),
.I1(un1_x_6_0[1]),
.I2(un84_sop_0_0_0_1_6_6[0]),
.O(un84_sop_0_0_0_5_0[0])
);
defparam un84_sop_0_0_0_1_6_axb_0.INIT=8'h96;
// @8:30
LUT6 un84_sop_1_4_axb_4_cZ (
.I0(x_0[3]),
.I1(x_0[2]),
.I2(x_0[1]),
.I3(x_0[0]),
.I4(x_0[4]),
.I5(un84_sop_1_7[4]),
.O(un84_sop_1_4_axb_4)
);
defparam un84_sop_1_4_axb_4_cZ.INIT=64'hFFFE00010001FFFE;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_2_cZ (
.I0(un1_x_7_0[3]),
.I1(un1_x_7_0[4]),
.I2(un1_x_8_0[5]),
.I3(un1_x_8_0[6]),
.I4(un1_x_9_0[6]),
.I5(un1_x_9_0[7]),
.O(un84_sop_0_0_0_6_6_0_axb_2)
);
defparam un84_sop_0_0_0_6_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_3_cZ (
.I0(un1_x_7_0[4]),
.I1(un1_x_7_0[5]),
.I2(un1_x_8_0[6]),
.I3(un1_x_8_0[7]),
.I4(un1_x_9_0[7]),
.I5(un1_x_9_0[8]),
.O(un84_sop_0_0_0_6_6_0_axb_3)
);
defparam un84_sop_0_0_0_6_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_4_cZ (
.I0(un1_x_7_0[5]),
.I1(un1_x_7_0[6]),
.I2(un1_x_8_0[7]),
.I3(un1_x_8_0[8]),
.I4(un1_x_9_0[8]),
.I5(un1_x_9_0[9]),
.O(un84_sop_0_0_0_6_6_0_axb_4)
);
defparam un84_sop_0_0_0_6_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_6_0_s_2_RNIGK751 (
.I0(x_8[1]),
.I1(x_8[0]),
.I2(un84_sop_0_0_0_0_11_7[1]),
.I3(un84_sop_0_0_0_0_11_7[2]),
.I4(un84_sop_0_0_0_0_11_6[2]),
.I5(un1_x_10_s_2_sf),
.LO(un84_sop_0_0_0_11_0_axb_2)
);
defparam un84_sop_0_0_0_11_6_0_s_2_RNIGK751.INIT=64'h9F60609F609F9F60;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_7_cZ (
.I0(un1_x_7_0[8]),
.I1(un1_x_7_0[9]),
.I2(un1_x_8_0[10]),
.I3(un1_x_8_0[11]),
.I4(un1_x_9_0[11]),
.I5(un1_x_9_0[12]),
.O(un84_sop_0_0_0_6_6_0_axb_7)
);
defparam un84_sop_0_0_0_6_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_8_cZ (
.I0(un1_x_7_0[9]),
.I1(un1_x_7_0[10]),
.I2(un1_x_8_0[11]),
.I3(un1_x_8_0[12]),
.I4(un1_x_9_0[12]),
.I5(un1_x_9_0[13]),
.O(un84_sop_0_0_0_6_6_0_axb_8)
);
defparam un84_sop_0_0_0_6_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT6 un84_sop_0_0_0_6_6_0_axb_9_cZ (
.I0(un1_x_7_0[10]),
.I1(un1_x_7_0[11]),
.I2(un1_x_8_0[12]),
.I3(un1_x_8_0[13]),
.I4(un1_x_9_0[13]),
.I5(un1_x_9_0[14]),
.O(un84_sop_0_0_0_6_6_0_axb_9)
);
defparam un84_sop_0_0_0_6_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
// @8:30
LUT4 un1_x_10_axb_11_cZ (
.I0(x_8[6]),
.I1(x_8[7]),
.I2(x_8[5]),
.I3(un1_x_10_5_c5),
.O(un1_x_10_axb_11)
);
defparam un1_x_10_axb_11_cZ.INIT=16'hFEFF;
// @8:30
LUT3_L un84_sop_0_0_0_11_0_axb_14_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[14]),
.I2(un1_x_10_0_0[15]),
.LO(un84_sop_0_0_0_11_0_axb_14)
);
defparam un84_sop_0_0_0_11_0_axb_14_cZ.INIT=8'h7E;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_axb_14_cZ (
.I0(un1_x_7_0[15]),
.I1(un1_x_8_0[15]),
.I2(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_axb_14)
);
defparam un84_sop_0_0_0_6_6_0_axb_14_cZ.INIT=8'h7E;
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(un84_sop_0_0_0_0_11_7_axb_0_ci),
.LO(un84_sop_0_0_0_11_0_cry_0_cy)
);
LUT1 un1_x_10_4_s_2_RNI13H1 (
.I0(un1_x_10_4[2]),
.O(un1_x_10_s_2_sf)
);
defparam un1_x_10_4_s_2_RNI13H1.INIT=2'h2;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_9_cZ (
.I0(un1_x_16_0_0_0[14]),
.I1(un1_x_15_0_0_0[14]),
.LO(un84_sop_0_0_0_1_axb_9)
);
defparam un84_sop_0_0_0_1_axb_9_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_8_cZ (
.I0(un1_x_16_0_0_0[14]),
.I1(un1_x_15_0_0_0[14]),
.LO(un84_sop_0_0_0_1_axb_8)
);
defparam un84_sop_0_0_0_1_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_7_cZ (
.I0(un1_x_16_0_0_0[13]),
.I1(un1_x_15_0_0_0[13]),
.LO(un84_sop_0_0_0_1_axb_7)
);
defparam un84_sop_0_0_0_1_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_6_cZ (
.I0(un1_x_16_0_0_0[12]),
.I1(un1_x_15_0_0_0[12]),
.LO(un84_sop_0_0_0_1_axb_6)
);
defparam un84_sop_0_0_0_1_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_5_cZ (
.I0(un1_x_16_0_0_0[11]),
.I1(un1_x_15_0_0_0[11]),
.LO(un84_sop_0_0_0_1_axb_5)
);
defparam un84_sop_0_0_0_1_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_4_cZ (
.I0(un1_x_16_0_0_0[10]),
.I1(un1_x_15_0_0_0[10]),
.LO(un84_sop_0_0_0_1_axb_4)
);
defparam un84_sop_0_0_0_1_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_3_cZ (
.I0(un1_x_16_0_0_0[9]),
.I1(un1_x_15_0_0_0[9]),
.LO(un84_sop_0_0_0_1_axb_3)
);
defparam un84_sop_0_0_0_1_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_2_cZ (
.I0(un1_x_16_0_0_0[8]),
.I1(un1_x_15_0_0_0[8]),
.LO(un84_sop_0_0_0_1_axb_2)
);
defparam un84_sop_0_0_0_1_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_axb_1_cZ (
.I0(un1_x_16_0_0_0[7]),
.I1(un1_x_15_0_0_0[7]),
.LO(un84_sop_0_0_0_1_axb_1)
);
defparam un84_sop_0_0_0_1_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_axb_0 (
.I0(x_12[0]),
.I1(x_13[0]),
.O(un84_sop_0_0_0_0_1[0])
);
defparam un84_sop_0_0_0_1_axb_0.INIT=4'h6;
// @8:30
LUT1 un1_x_16_0_axb_8_cZ (
.I0(x_13[7]),
.O(un1_x_16_0_axb_8)
);
defparam un1_x_16_0_axb_8_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_8_cZ (
.I0(x_8[7]),
.LO(un1_x_11_0_axb_8)
);
defparam un1_x_11_0_axb_8_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_7_cZ (
.I0(x_8[7]),
.LO(un1_x_11_0_axb_7)
);
defparam un1_x_11_0_axb_7_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_6_cZ (
.I0(x_8[6]),
.LO(un1_x_11_0_axb_6)
);
defparam un1_x_11_0_axb_6_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_5_cZ (
.I0(x_8[5]),
.LO(un1_x_11_0_axb_5)
);
defparam un1_x_11_0_axb_5_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_4_cZ (
.I0(x_8[4]),
.LO(un1_x_11_0_axb_4)
);
defparam un1_x_11_0_axb_4_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_3_cZ (
.I0(x_8[3]),
.LO(un1_x_11_0_axb_3)
);
defparam un1_x_11_0_axb_3_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_2_cZ (
.I0(x_8[2]),
.LO(un1_x_11_0_axb_2)
);
defparam un1_x_11_0_axb_2_cZ.INIT=2'h1;
// @8:30
LUT1_L un1_x_11_0_axb_1_cZ (
.I0(x_8[1]),
.LO(un1_x_11_0_axb_1)
);
defparam un1_x_11_0_axb_1_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_15_0_axb_8_cZ (
.I0(x_12[7]),
.O(un1_x_15_0_axb_8)
);
defparam un1_x_15_0_axb_8_cZ.INIT=2'h1;
// @8:30
LUT1 un1_x_10_4_axb_10 (
.I0(x_8[7]),
.O(un1_x_10_4[10])
);
defparam un1_x_10_4_axb_10.INIT=2'h2;
// @8:30
LUT1 un1_x_10_4_axb_9 (
.I0(x_8[7]),
.O(un1_x_10_4[9])
);
defparam un1_x_10_4_axb_9.INIT=2'h2;
// @8:30
LUT2_L un84_sop_1_axb_14_cZ (
.I0(un84_sop_1_6[14]),
.I1(un84_sop_1_4[14]),
.LO(un84_sop_1_axb_14)
);
defparam un84_sop_1_axb_14_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_13_cZ (
.I0(un84_sop_1_6[14]),
.I1(un84_sop_1_4[13]),
.LO(un84_sop_1_axb_13)
);
defparam un84_sop_1_axb_13_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_12_cZ (
.I0(un84_sop_1_6[12]),
.I1(un84_sop_1_4[12]),
.LO(un84_sop_1_axb_12)
);
defparam un84_sop_1_axb_12_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_11_cZ (
.I0(un84_sop_1_6[11]),
.I1(un84_sop_1_4[11]),
.LO(un84_sop_1_axb_11)
);
defparam un84_sop_1_axb_11_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_10_cZ (
.I0(un84_sop_1_6[10]),
.I1(un84_sop_1_4[10]),
.LO(un84_sop_1_axb_10)
);
defparam un84_sop_1_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_9_cZ (
.I0(un84_sop_1_6[9]),
.I1(un84_sop_1_4[9]),
.LO(un84_sop_1_axb_9)
);
defparam un84_sop_1_axb_9_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_8_cZ (
.I0(un84_sop_1_6[8]),
.I1(un84_sop_1_4[8]),
.LO(un84_sop_1_axb_8)
);
defparam un84_sop_1_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_1_axb_7_cZ (
.I0(un84_sop_1_6[7]),
.I1(un84_sop_1_4[7]),
.LO(un84_sop_1_axb_7)
);
defparam un84_sop_1_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_0_11_7_axb_10_cZ (
.I0(un1_x_11_0_0[14]),
.I1(un84_sop_0_0_0_0_0[9]),
.O(un84_sop_0_0_0_0_11_7_axb_10)
);
defparam un84_sop_0_0_0_0_11_7_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_1_7_axb_14_cZ (
.I0(un84_sop_0_0_0_0_5[14]),
.I1(un1_x_4[15]),
.O(un84_sop_1_7_axb_14)
);
defparam un84_sop_1_7_axb_14_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_14_cZ (
.I0(un84_sop_0_0_0_1_6_6[14]),
.I1(un84_sop_0_0_0_1_6_4[14]),
.LO(un84_sop_0_0_0_1_6_axb_14)
);
defparam un84_sop_0_0_0_1_6_axb_14_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_13_cZ (
.I0(un84_sop_0_0_0_1_6_6[13]),
.I1(un84_sop_0_0_0_1_6_4[13]),
.LO(un84_sop_0_0_0_1_6_axb_13)
);
defparam un84_sop_0_0_0_1_6_axb_13_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_12_cZ (
.I0(un84_sop_0_0_0_1_6_6[12]),
.I1(un84_sop_0_0_0_1_6_4[12]),
.LO(un84_sop_0_0_0_1_6_axb_12)
);
defparam un84_sop_0_0_0_1_6_axb_12_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_11_cZ (
.I0(un84_sop_0_0_0_1_6_6[11]),
.I1(un84_sop_0_0_0_1_6_4[11]),
.LO(un84_sop_0_0_0_1_6_axb_11)
);
defparam un84_sop_0_0_0_1_6_axb_11_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_10_cZ (
.I0(un84_sop_0_0_0_1_6_6[10]),
.I1(un84_sop_0_0_0_1_6_4[10]),
.LO(un84_sop_0_0_0_1_6_axb_10)
);
defparam un84_sop_0_0_0_1_6_axb_10_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_9_cZ (
.I0(un84_sop_0_0_0_1_6_6[9]),
.I1(un84_sop_0_0_0_1_6_4[9]),
.LO(un84_sop_0_0_0_1_6_axb_9)
);
defparam un84_sop_0_0_0_1_6_axb_9_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_8_cZ (
.I0(un84_sop_0_0_0_1_6_6[8]),
.I1(un84_sop_0_0_0_1_6_4[8]),
.LO(un84_sop_0_0_0_1_6_axb_8)
);
defparam un84_sop_0_0_0_1_6_axb_8_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_7_cZ (
.I0(un84_sop_0_0_0_1_6_6[7]),
.I1(un84_sop_0_0_0_1_6_4[7]),
.LO(un84_sop_0_0_0_1_6_axb_7)
);
defparam un84_sop_0_0_0_1_6_axb_7_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_6_cZ (
.I0(un84_sop_0_0_0_1_6_6[6]),
.I1(un84_sop_0_0_0_1_6_4[6]),
.LO(un84_sop_0_0_0_1_6_axb_6)
);
defparam un84_sop_0_0_0_1_6_axb_6_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_5_cZ (
.I0(un84_sop_0_0_0_1_6_6[5]),
.I1(un84_sop_0_0_0_1_6_4[5]),
.LO(un84_sop_0_0_0_1_6_axb_5)
);
defparam un84_sop_0_0_0_1_6_axb_5_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_4_cZ (
.I0(un84_sop_0_0_0_1_6_6[4]),
.I1(un84_sop_0_0_0_1_6_4[4]),
.LO(un84_sop_0_0_0_1_6_axb_4)
);
defparam un84_sop_0_0_0_1_6_axb_4_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_3_cZ (
.I0(un84_sop_0_0_0_1_6_4[3]),
.I1(un84_sop_0_0_0_1_6_6[3]),
.LO(un84_sop_0_0_0_1_6_axb_3)
);
defparam un84_sop_0_0_0_1_6_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_2_cZ (
.I0(un84_sop_0_0_0_1_6_4[2]),
.I1(un84_sop_0_0_0_1_6_6[2]),
.LO(un84_sop_0_0_0_1_6_axb_2)
);
defparam un84_sop_0_0_0_1_6_axb_2_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_1_6_axb_1_cZ (
.I0(un84_sop_0_0_0_1_6_4[1]),
.I1(un84_sop_0_0_0_1_6_6[1]),
.LO(un84_sop_0_0_0_1_6_axb_1)
);
defparam un84_sop_0_0_0_1_6_axb_1_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_4_axb_14_cZ (
.I0(un1_x_6_0[15]),
.I1(un84_sop_0_0_0_1_6_8[14]),
.O(un84_sop_0_0_0_1_6_4_axb_14)
);
defparam un84_sop_0_0_0_1_6_4_axb_14_cZ.INIT=4'h6;
// @8:30
LUT2 un1_x_10_axb_3_cZ (
.I0(x_8[0]),
.I1(un1_x_10_4[3]),
.O(un1_x_10_axb_3)
);
defparam un1_x_10_axb_3_cZ.INIT=4'h6;
// @8:30
LUT2 un84_sop_0_0_0_1_6_8_axb_11_cZ (
.I0(un84_sop_0_0_0_10_0[14]),
.I1(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_axb_11)
);
defparam un84_sop_0_0_0_1_6_8_axb_11_cZ.INIT=4'h6;
// @8:30
LUT2_L un84_sop_0_0_0_11_0_axb_0_cZ (
.I0(x_8[0]),
.I1(un84_sop_0_0_0_0_11_6[0]),
.LO(un84_sop_0_0_0_11_0_axb_0)
);
defparam un84_sop_0_0_0_11_0_axb_0_cZ.INIT=4'h6;
// @8:30
LUT4 un1_x_0_0_ac0_5 (
.I0(x_0[3]),
.I1(x_0[2]),
.I2(x_0[1]),
.I3(x_0[0]),
.O(un1_x_0_0_c4)
);
defparam un1_x_0_0_ac0_5.INIT=16'h0001;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_11_cZ (
.I0(un1_x_12_0_0[15]),
.I1(un1_x_14_0_0[15]),
.I2(un1_x_13_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_o5_11)
);
defparam un84_sop_0_0_0_11_6_0_o5_11_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_10_cZ (
.I0(un1_x_12_0_0[14]),
.I1(un1_x_14_0_0[14]),
.I2(un1_x_13_0_0[15]),
.O(un84_sop_0_0_0_11_6_0_o5_10)
);
defparam un84_sop_0_0_0_11_6_0_o5_10_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_9_cZ (
.I0(un1_x_12_0_0[13]),
.I1(un1_x_13_0_0[14]),
.I2(un1_x_14_0_0[13]),
.O(un84_sop_0_0_0_11_6_0_o5_9)
);
defparam un84_sop_0_0_0_11_6_0_o5_9_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_8_cZ (
.I0(un1_x_12_0_0[12]),
.I1(un1_x_13_0_0[13]),
.I2(un1_x_14_0_0[12]),
.O(un84_sop_0_0_0_11_6_0_o5_8)
);
defparam un84_sop_0_0_0_11_6_0_o5_8_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_7_cZ (
.I0(un1_x_12_0_0[11]),
.I1(un1_x_13_0_0[12]),
.I2(un1_x_14_0_0[11]),
.O(un84_sop_0_0_0_11_6_0_o5_7)
);
defparam un84_sop_0_0_0_11_6_0_o5_7_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_6_cZ (
.I0(un1_x_12_0_0[10]),
.I1(un1_x_13_0_0[11]),
.I2(un1_x_14_0_0[10]),
.O(un84_sop_0_0_0_11_6_0_o5_6)
);
defparam un84_sop_0_0_0_11_6_0_o5_6_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_5_cZ (
.I0(un1_x_12_0_0[9]),
.I1(un1_x_13_0_0[10]),
.I2(un1_x_14_0_0[9]),
.O(un84_sop_0_0_0_11_6_0_o5_5)
);
defparam un84_sop_0_0_0_11_6_0_o5_5_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_4_cZ (
.I0(un1_x_12_0_0[8]),
.I1(un1_x_13_0_0[9]),
.I2(un1_x_14_0_0[8]),
.O(un84_sop_0_0_0_11_6_0_o5_4)
);
defparam un84_sop_0_0_0_11_6_0_o5_4_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_3_cZ (
.I0(un1_x_12_0_0[7]),
.I1(un1_x_13_0_0[8]),
.I2(un1_x_14_0_0[7]),
.O(un84_sop_0_0_0_11_6_0_o5_3)
);
defparam un84_sop_0_0_0_11_6_0_o5_3_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_o5_2_cZ (
.I0(un1_x_12_0_0[6]),
.I1(un1_x_13_0_0[7]),
.I2(un1_x_14_0_0[6]),
.O(un84_sop_0_0_0_11_6_0_o5_2)
);
defparam un84_sop_0_0_0_11_6_0_o5_2_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_12_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[12]),
.I2(un1_x_10_0_0[15]),
.O(un84_sop_0_0_0_11_0_o5_12)
);
defparam un84_sop_0_0_0_11_0_o5_12_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_11_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[11]),
.I2(un1_x_10_0_0[15]),
.O(un84_sop_0_0_0_11_0_o5_11)
);
defparam un84_sop_0_0_0_11_0_o5_11_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_10_cZ (
.I0(un84_sop_0_0_0_0_11_7[14]),
.I1(un84_sop_0_0_0_0_11_6[10]),
.I2(un1_x_10_0_0[14]),
.O(un84_sop_0_0_0_11_0_o5_10)
);
defparam un84_sop_0_0_0_11_0_o5_10_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_9_cZ (
.I0(un84_sop_0_0_0_0_11_7[9]),
.I1(un84_sop_0_0_0_0_11_6[9]),
.I2(un1_x_10_0_0[13]),
.O(un84_sop_0_0_0_11_0_o5_9)
);
defparam un84_sop_0_0_0_11_0_o5_9_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_8_cZ (
.I0(un84_sop_0_0_0_0_11_7[8]),
.I1(un84_sop_0_0_0_0_11_6[8]),
.I2(un1_x_10_0_0[12]),
.O(un84_sop_0_0_0_11_0_o5_8)
);
defparam un84_sop_0_0_0_11_0_o5_8_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_7_cZ (
.I0(un84_sop_0_0_0_0_11_7[7]),
.I1(un84_sop_0_0_0_0_11_6[7]),
.I2(un1_x_10_0_0[11]),
.O(un84_sop_0_0_0_11_0_o5_7)
);
defparam un84_sop_0_0_0_11_0_o5_7_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_6_cZ (
.I0(un84_sop_0_0_0_0_11_7[6]),
.I1(un84_sop_0_0_0_0_11_6[6]),
.I2(un1_x_10_0_0[10]),
.O(un84_sop_0_0_0_11_0_o5_6)
);
defparam un84_sop_0_0_0_11_0_o5_6_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_5_cZ (
.I0(un84_sop_0_0_0_0_11_7[5]),
.I1(un84_sop_0_0_0_0_11_6[5]),
.I2(un1_x_10_0_0[9]),
.O(un84_sop_0_0_0_11_0_o5_5)
);
defparam un84_sop_0_0_0_11_0_o5_5_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_4_cZ (
.I0(un84_sop_0_0_0_0_11_7[4]),
.I1(un84_sop_0_0_0_0_11_6[4]),
.I2(un1_x_10_0_0[8]),
.O(un84_sop_0_0_0_11_0_o5_4)
);
defparam un84_sop_0_0_0_11_0_o5_4_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_3_cZ (
.I0(un84_sop_0_0_0_0_11_7[3]),
.I1(un1_x_10_axb_3),
.I2(un84_sop_0_0_0_0_11_6[3]),
.O(un84_sop_0_0_0_11_0_o5_3)
);
defparam un84_sop_0_0_0_11_0_o5_3_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_11_0_o5_2_cZ (
.I0(un84_sop_0_0_0_0_11_7[2]),
.I1(un84_sop_0_0_0_0_11_6[2]),
.I2(un1_x_10_s_2_sf),
.O(un84_sop_0_0_0_11_0_o5_2)
);
defparam un84_sop_0_0_0_11_0_o5_2_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_12_cZ (
.I0(un1_x_7_0[14]),
.I1(un1_x_8_0[15]),
.I2(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_o5_12)
);
defparam un84_sop_0_0_0_6_6_0_o5_12_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_11_cZ (
.I0(un1_x_7_0[13]),
.I1(un1_x_8_0[15]),
.I2(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_o5_11)
);
defparam un84_sop_0_0_0_6_6_0_o5_11_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_10_cZ (
.I0(un1_x_7_0[12]),
.I1(un1_x_8_0[14]),
.I2(un1_x_9_0[15]),
.O(un84_sop_0_0_0_6_6_0_o5_10)
);
defparam un84_sop_0_0_0_6_6_0_o5_10_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_9_cZ (
.I0(un1_x_7_0[11]),
.I1(un1_x_8_0[13]),
.I2(un1_x_9_0[14]),
.O(un84_sop_0_0_0_6_6_0_o5_9)
);
defparam un84_sop_0_0_0_6_6_0_o5_9_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_8_cZ (
.I0(un1_x_7_0[10]),
.I1(un1_x_8_0[12]),
.I2(un1_x_9_0[13]),
.O(un84_sop_0_0_0_6_6_0_o5_8)
);
defparam un84_sop_0_0_0_6_6_0_o5_8_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_7_cZ (
.I0(un1_x_7_0[9]),
.I1(un1_x_8_0[11]),
.I2(un1_x_9_0[12]),
.O(un84_sop_0_0_0_6_6_0_o5_7)
);
defparam un84_sop_0_0_0_6_6_0_o5_7_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_6_cZ (
.I0(un1_x_7_0[8]),
.I1(un1_x_8_0[10]),
.I2(un1_x_9_0[11]),
.O(un84_sop_0_0_0_6_6_0_o5_6)
);
defparam un84_sop_0_0_0_6_6_0_o5_6_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_5_cZ (
.I0(un1_x_7_0[7]),
.I1(un1_x_8_0[9]),
.I2(un1_x_9_0[10]),
.O(un84_sop_0_0_0_6_6_0_o5_5)
);
defparam un84_sop_0_0_0_6_6_0_o5_5_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_4_cZ (
.I0(un1_x_7_0[6]),
.I1(un1_x_8_0[8]),
.I2(un1_x_9_0[9]),
.O(un84_sop_0_0_0_6_6_0_o5_4)
);
defparam un84_sop_0_0_0_6_6_0_o5_4_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_3_cZ (
.I0(un1_x_7_0[5]),
.I1(un1_x_8_0[7]),
.I2(un1_x_9_0[8]),
.O(un84_sop_0_0_0_6_6_0_o5_3)
);
defparam un84_sop_0_0_0_6_6_0_o5_3_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_o5_2_cZ (
.I0(un1_x_7_0[4]),
.I1(un1_x_8_0[6]),
.I2(un1_x_9_0[7]),
.O(un84_sop_0_0_0_6_6_0_o5_2)
);
defparam un84_sop_0_0_0_6_6_0_o5_2_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_o5_7_cZ (
.I0(un84_sop_0_0_0_10_0[10]),
.I1(x_4[5]),
.I2(x_4[7]),
.O(un84_sop_0_0_0_1_6_8_o5_7)
);
defparam un84_sop_0_0_0_1_6_8_o5_7_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_o5_6_cZ (
.I0(un84_sop_0_0_0_10_0[9]),
.I1(x_4[6]),
.I2(x_4[4]),
.O(un84_sop_0_0_0_1_6_8_o5_6)
);
defparam un84_sop_0_0_0_1_6_8_o5_6_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_o5_5_cZ (
.I0(un84_sop_0_0_0_10_0[8]),
.I1(x_4[3]),
.I2(x_4[5]),
.O(un84_sop_0_0_0_1_6_8_o5_5)
);
defparam un84_sop_0_0_0_1_6_8_o5_5_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_o5_4_cZ (
.I0(un84_sop_0_0_0_10_0[7]),
.I1(x_4[2]),
.I2(x_4[4]),
.O(un84_sop_0_0_0_1_6_8_o5_4)
);
defparam un84_sop_0_0_0_1_6_8_o5_4_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_o5_3_cZ (
.I0(un84_sop_0_0_0_10_0[6]),
.I1(x_4[1]),
.I2(x_4[3]),
.O(un84_sop_0_0_0_1_6_8_o5_3)
);
defparam un84_sop_0_0_0_1_6_8_o5_3_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_11_cZ (
.I0(un1_x_1[15]),
.I1(un1_x_3[15]),
.I2(un1_x_2[15]),
.O(un84_sop_1_6_0_o5_11)
);
defparam un84_sop_1_6_0_o5_11_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_10_cZ (
.I0(un1_x_1[14]),
.I1(un1_x_3[14]),
.I2(un1_x_2[15]),
.O(un84_sop_1_6_0_o5_10)
);
defparam un84_sop_1_6_0_o5_10_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_9_cZ (
.I0(un1_x_1[13]),
.I1(un1_x_2[14]),
.I2(un1_x_3[13]),
.O(un84_sop_1_6_0_o5_9)
);
defparam un84_sop_1_6_0_o5_9_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_8_cZ (
.I0(un1_x_1[12]),
.I1(un1_x_2[13]),
.I2(un1_x_3[12]),
.O(un84_sop_1_6_0_o5_8)
);
defparam un84_sop_1_6_0_o5_8_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_7_cZ (
.I0(un1_x_1[11]),
.I1(un1_x_2[12]),
.I2(un1_x_3[11]),
.O(un84_sop_1_6_0_o5_7)
);
defparam un84_sop_1_6_0_o5_7_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_6_cZ (
.I0(un1_x_1[10]),
.I1(un1_x_2[11]),
.I2(un1_x_3[10]),
.O(un84_sop_1_6_0_o5_6)
);
defparam un84_sop_1_6_0_o5_6_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_5_cZ (
.I0(un1_x_1[9]),
.I1(un1_x_2[10]),
.I2(un1_x_3[9]),
.O(un84_sop_1_6_0_o5_5)
);
defparam un84_sop_1_6_0_o5_5_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_4_cZ (
.I0(un1_x_1[8]),
.I1(un1_x_2[9]),
.I2(un1_x_3[8]),
.O(un84_sop_1_6_0_o5_4)
);
defparam un84_sop_1_6_0_o5_4_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_3_cZ (
.I0(un1_x_1[7]),
.I1(un1_x_2[8]),
.I2(un1_x_3[7]),
.O(un84_sop_1_6_0_o5_3)
);
defparam un84_sop_1_6_0_o5_3_cZ.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_o5_2_cZ (
.I0(un1_x_1[6]),
.I1(un1_x_2[7]),
.I2(un1_x_3[6]),
.O(un84_sop_1_6_0_o5_2)
);
defparam un84_sop_1_6_0_o5_2_cZ.INIT=8'hE8;
// @8:30
LUT5 un84_sop_1_4_axb_3_cZ (
.I0(x_0[3]),
.I1(x_0[2]),
.I2(x_0[1]),
.I3(x_0[0]),
.I4(un84_sop_1_7[3]),
.O(un84_sop_1_4_axb_3)
);
defparam un84_sop_1_4_axb_3_cZ.INIT=32'hAAA95556;
// @8:30
LUT5 un1_x_10_5_ac0_7 (
.I0(x_8[4]),
.I1(x_8[3]),
.I2(x_8[2]),
.I3(x_8[1]),
.I4(x_8[0]),
.O(un1_x_10_5_c5)
);
defparam un1_x_10_5_ac0_7.INIT=32'h00000001;
// @8:30
LUT5 un1_x_10_axb_6_cZ (
.I0(x_8[3]),
.I1(x_8[2]),
.I2(x_8[1]),
.I3(x_8[0]),
.I4(un1_x_10_4[6]),
.O(un1_x_10_axb_6)
);
defparam un1_x_10_axb_6_cZ.INIT=32'hAAA95556;
// @8:30
LUT6 un1_x_10_axb_7_cZ (
.I0(x_8[4]),
.I1(x_8[3]),
.I2(x_8[2]),
.I3(x_8[1]),
.I4(x_8[0]),
.I5(un1_x_10_4[7]),
.O(un1_x_10_axb_7)
);
defparam un1_x_10_axb_7_cZ.INIT=64'hAAAAAAA955555556;
// @8:30
LUT5 un84_sop_1_4_axb_6_cZ (
.I0(x_0[6]),
.I1(x_0[5]),
.I2(x_0[4]),
.I3(un1_x_0_0_c4),
.I4(un84_sop_1_7[6]),
.O(un84_sop_1_4_axb_6)
);
defparam un84_sop_1_4_axb_6_cZ.INIT=32'hA9AA5655;
// @8:30
LUT6 un84_sop_1_4_axb_7_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[7]),
.O(un84_sop_1_4_axb_7)
);
defparam un84_sop_1_4_axb_7_cZ.INIT=64'hAAA9AAAA55565555;
// @8:30
LUT6 un84_sop_1_4_axb_14_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[14]),
.O(un84_sop_1_4_axb_14)
);
defparam un84_sop_1_4_axb_14_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_13_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[13]),
.O(un84_sop_1_4_axb_13)
);
defparam un84_sop_1_4_axb_13_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_12_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[12]),
.O(un84_sop_1_4_axb_12)
);
defparam un84_sop_1_4_axb_12_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_11_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[11]),
.O(un84_sop_1_4_axb_11)
);
defparam un84_sop_1_4_axb_11_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_10_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[10]),
.O(un84_sop_1_4_axb_10)
);
defparam un84_sop_1_4_axb_10_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_9_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[9]),
.O(un84_sop_1_4_axb_9)
);
defparam un84_sop_1_4_axb_9_cZ.INIT=64'hAAABAAAA55545555;
// @8:30
LUT6 un84_sop_1_4_axb_8_cZ (
.I0(x_0[7]),
.I1(x_0[6]),
.I2(x_0[5]),
.I3(x_0[4]),
.I4(un1_x_0_0_c4),
.I5(un84_sop_1_7[8]),
.O(un84_sop_1_4_axb_8)
);
defparam un84_sop_1_4_axb_8_cZ.INIT=64'hAAABAAAA55545555;
LUT2 x_16_pipe_0_0_0_RNI0KBH (
.I0(un84_sop_0_0_0_0_5[0]),
.I1(un1_x_4[2]),
.O(un84_sop_1_7[0])
);
defparam x_16_pipe_0_0_0_RNI0KBH.INIT=4'h6;
// @8:30
XORCY un84_sop_0_0_0_1_s_9 (
.LI(un84_sop_0_0_0_1_axb_9),
.CI(un84_sop_0_0_0_1_cry_8),
.O(un84_sop_0_0_0_0_1[9])
);
// @8:30
XORCY un84_sop_0_0_0_1_s_8 (
.LI(un84_sop_0_0_0_1_axb_8),
.CI(un84_sop_0_0_0_1_cry_7),
.O(un84_sop_0_0_0_0_1[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_8_cZ (
.DI(un1_x_15_0_0_0[14]),
.CI(un84_sop_0_0_0_1_cry_7),
.S(un84_sop_0_0_0_1_axb_8),
.LO(un84_sop_0_0_0_1_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_7 (
.LI(un84_sop_0_0_0_1_axb_7),
.CI(un84_sop_0_0_0_1_cry_6),
.O(un84_sop_0_0_0_0_1[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_7_cZ (
.DI(un1_x_15_0_0_0[13]),
.CI(un84_sop_0_0_0_1_cry_6),
.S(un84_sop_0_0_0_1_axb_7),
.LO(un84_sop_0_0_0_1_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_6 (
.LI(un84_sop_0_0_0_1_axb_6),
.CI(un84_sop_0_0_0_1_cry_5),
.O(un84_sop_0_0_0_0_1[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_6_cZ (
.DI(un1_x_15_0_0_0[12]),
.CI(un84_sop_0_0_0_1_cry_5),
.S(un84_sop_0_0_0_1_axb_6),
.LO(un84_sop_0_0_0_1_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_5 (
.LI(un84_sop_0_0_0_1_axb_5),
.CI(un84_sop_0_0_0_1_cry_4),
.O(un84_sop_0_0_0_0_1[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_5_cZ (
.DI(un1_x_15_0_0_0[11]),
.CI(un84_sop_0_0_0_1_cry_4),
.S(un84_sop_0_0_0_1_axb_5),
.LO(un84_sop_0_0_0_1_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_4 (
.LI(un84_sop_0_0_0_1_axb_4),
.CI(un84_sop_0_0_0_1_cry_3),
.O(un84_sop_0_0_0_0_1[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_4_cZ (
.DI(un1_x_15_0_0_0[10]),
.CI(un84_sop_0_0_0_1_cry_3),
.S(un84_sop_0_0_0_1_axb_4),
.LO(un84_sop_0_0_0_1_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_3 (
.LI(un84_sop_0_0_0_1_axb_3),
.CI(un84_sop_0_0_0_1_cry_2),
.O(un84_sop_0_0_0_0_1[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_3_cZ (
.DI(un1_x_15_0_0_0[9]),
.CI(un84_sop_0_0_0_1_cry_2),
.S(un84_sop_0_0_0_1_axb_3),
.LO(un84_sop_0_0_0_1_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_2 (
.LI(un84_sop_0_0_0_1_axb_2),
.CI(un84_sop_0_0_0_1_cry_1),
.O(un84_sop_0_0_0_0_1[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_2_cZ (
.DI(un1_x_15_0_0_0[8]),
.CI(un84_sop_0_0_0_1_cry_1),
.S(un84_sop_0_0_0_1_axb_2),
.LO(un84_sop_0_0_0_1_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_1_s_1 (
.LI(un84_sop_0_0_0_1_axb_1),
.CI(un84_sop_0_0_0_1_cry_0),
.O(un84_sop_0_0_0_0_1[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_1_cZ (
.DI(un1_x_15_0_0_0[7]),
.CI(un84_sop_0_0_0_1_cry_0),
.S(un84_sop_0_0_0_1_axb_1),
.LO(un84_sop_0_0_0_1_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_cry_0_cZ (
.DI(x_13[0]),
.CI(GND),
.S(un84_sop_0_0_0_0_1[0]),
.LO(un84_sop_0_0_0_1_cry_0)
);
// @8:30
XORCY un1_x_16_0_s_8 (
.LI(un1_x_16_0_axb_8),
.CI(un1_x_16_0_cry_7),
.O(un1_x_16_0_0_0[14])
);
// @8:30
XORCY un1_x_16_0_s_7 (
.LI(un1_x_16_0_axb_7),
.CI(un1_x_16_0_cry_6),
.O(un1_x_16_0_0_0[13])
);
// @8:30
MUXCY_L un1_x_16_0_cry_7_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_6),
.S(un1_x_16_0_axb_7),
.LO(un1_x_16_0_cry_7)
);
// @8:30
XORCY un1_x_16_0_s_6 (
.LI(un1_x_16_0_axb_6),
.CI(un1_x_16_0_cry_5),
.O(un1_x_16_0_0_0[12])
);
// @8:30
MUXCY_L un1_x_16_0_cry_6_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_5),
.S(un1_x_16_0_axb_6),
.LO(un1_x_16_0_cry_6)
);
// @8:30
XORCY un1_x_16_0_s_5 (
.LI(un1_x_16_0_axb_5),
.CI(un1_x_16_0_cry_4),
.O(un1_x_16_0_0_0[11])
);
// @8:30
MUXCY_L un1_x_16_0_cry_5_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_4),
.S(un1_x_16_0_axb_5),
.LO(un1_x_16_0_cry_5)
);
// @8:30
XORCY un1_x_16_0_s_4 (
.LI(un1_x_16_0_axb_4),
.CI(un1_x_16_0_cry_3),
.O(un1_x_16_0_0_0[10])
);
// @8:30
MUXCY_L un1_x_16_0_cry_4_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_3),
.S(un1_x_16_0_axb_4),
.LO(un1_x_16_0_cry_4)
);
// @8:30
XORCY un1_x_16_0_s_3 (
.LI(un1_x_16_0_axb_3),
.CI(un1_x_16_0_cry_2),
.O(un1_x_16_0_0_0[9])
);
// @8:30
MUXCY_L un1_x_16_0_cry_3_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_2),
.S(un1_x_16_0_axb_3),
.LO(un1_x_16_0_cry_3)
);
// @8:30
XORCY un1_x_16_0_s_2 (
.LI(un1_x_16_0_axb_2),
.CI(un1_x_16_0_cry_1),
.O(un1_x_16_0_0_0[8])
);
// @8:30
MUXCY_L un1_x_16_0_cry_2_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_1),
.S(un1_x_16_0_axb_2),
.LO(un1_x_16_0_cry_2)
);
// @8:30
XORCY un1_x_16_0_s_1 (
.LI(un1_x_16_0_axb_1),
.CI(un1_x_16_0_cry_0),
.O(un1_x_16_0_0_0[7])
);
// @8:30
MUXCY_L un1_x_16_0_cry_1_cZ (
.DI(GND),
.CI(un1_x_16_0_cry_0),
.S(un1_x_16_0_axb_1),
.LO(un1_x_16_0_cry_1)
);
// @8:30
MUXCY_L un1_x_16_0_cry_0_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_16_0_axb_0),
.LO(un1_x_16_0_cry_0)
);
// @8:30
XORCY un1_x_11_0_s_8 (
.LI(un1_x_11_0_axb_8),
.CI(un1_x_11_0_cry_7),
.O(un1_x_11_0_0_0[14])
);
// @8:30
XORCY un1_x_11_0_s_7 (
.LI(un1_x_11_0_axb_7),
.CI(un1_x_11_0_cry_6),
.O(un1_x_11_0_0_0[13])
);
// @8:30
MUXCY_L un1_x_11_0_cry_7_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_6),
.S(un1_x_11_0_axb_7),
.LO(un1_x_11_0_cry_7)
);
// @8:30
XORCY un1_x_11_0_s_6 (
.LI(un1_x_11_0_axb_6),
.CI(un1_x_11_0_cry_5),
.O(un1_x_11_0_0_0[12])
);
// @8:30
MUXCY_L un1_x_11_0_cry_6_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_5),
.S(un1_x_11_0_axb_6),
.LO(un1_x_11_0_cry_6)
);
// @8:30
XORCY un1_x_11_0_s_5 (
.LI(un1_x_11_0_axb_5),
.CI(un1_x_11_0_cry_4),
.O(un1_x_11_0_0_0[11])
);
// @8:30
MUXCY_L un1_x_11_0_cry_5_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_4),
.S(un1_x_11_0_axb_5),
.LO(un1_x_11_0_cry_5)
);
// @8:30
XORCY un1_x_11_0_s_4 (
.LI(un1_x_11_0_axb_4),
.CI(un1_x_11_0_cry_3),
.O(un1_x_11_0_0_0[10])
);
// @8:30
MUXCY_L un1_x_11_0_cry_4_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_3),
.S(un1_x_11_0_axb_4),
.LO(un1_x_11_0_cry_4)
);
// @8:30
XORCY un1_x_11_0_s_3 (
.LI(un1_x_11_0_axb_3),
.CI(un1_x_11_0_cry_2),
.O(un1_x_11_0_0_0[9])
);
// @8:30
MUXCY_L un1_x_11_0_cry_3_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_2),
.S(un1_x_11_0_axb_3),
.LO(un1_x_11_0_cry_3)
);
// @8:30
XORCY un1_x_11_0_s_2 (
.LI(un1_x_11_0_axb_2),
.CI(un1_x_11_0_cry_1),
.O(un1_x_11_0_0_0[8])
);
// @8:30
MUXCY_L un1_x_11_0_cry_2_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_1),
.S(un1_x_11_0_axb_2),
.LO(un1_x_11_0_cry_2)
);
// @8:30
XORCY un1_x_11_0_s_1 (
.LI(un1_x_11_0_axb_1),
.CI(un1_x_11_0_cry_0),
.O(un1_x_11_0_0_0[7])
);
// @8:30
MUXCY_L un1_x_11_0_cry_1_cZ (
.DI(GND),
.CI(un1_x_11_0_cry_0),
.S(un1_x_11_0_axb_1),
.LO(un1_x_11_0_cry_1)
);
// @8:30
MUXCY_L un1_x_11_0_cry_0_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_11_0_axb_0),
.LO(un1_x_11_0_cry_0)
);
// @8:30
XORCY un1_x_15_0_s_8 (
.LI(un1_x_15_0_axb_8),
.CI(un1_x_15_0_cry_7),
.O(un1_x_15_0_0_0[14])
);
// @8:30
XORCY un1_x_15_0_s_7 (
.LI(un1_x_15_0_axb_7),
.CI(un1_x_15_0_cry_6),
.O(un1_x_15_0_0_0[13])
);
// @8:30
MUXCY_L un1_x_15_0_cry_7_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_6),
.S(un1_x_15_0_axb_7),
.LO(un1_x_15_0_cry_7)
);
// @8:30
XORCY un1_x_15_0_s_6 (
.LI(un1_x_15_0_axb_6),
.CI(un1_x_15_0_cry_5),
.O(un1_x_15_0_0_0[12])
);
// @8:30
MUXCY_L un1_x_15_0_cry_6_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_5),
.S(un1_x_15_0_axb_6),
.LO(un1_x_15_0_cry_6)
);
// @8:30
XORCY un1_x_15_0_s_5 (
.LI(un1_x_15_0_axb_5),
.CI(un1_x_15_0_cry_4),
.O(un1_x_15_0_0_0[11])
);
// @8:30
MUXCY_L un1_x_15_0_cry_5_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_4),
.S(un1_x_15_0_axb_5),
.LO(un1_x_15_0_cry_5)
);
// @8:30
XORCY un1_x_15_0_s_4 (
.LI(un1_x_15_0_axb_4),
.CI(un1_x_15_0_cry_3),
.O(un1_x_15_0_0_0[10])
);
// @8:30
MUXCY_L un1_x_15_0_cry_4_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_3),
.S(un1_x_15_0_axb_4),
.LO(un1_x_15_0_cry_4)
);
// @8:30
XORCY un1_x_15_0_s_3 (
.LI(un1_x_15_0_axb_3),
.CI(un1_x_15_0_cry_2),
.O(un1_x_15_0_0_0[9])
);
// @8:30
MUXCY_L un1_x_15_0_cry_3_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_2),
.S(un1_x_15_0_axb_3),
.LO(un1_x_15_0_cry_3)
);
// @8:30
XORCY un1_x_15_0_s_2 (
.LI(un1_x_15_0_axb_2),
.CI(un1_x_15_0_cry_1),
.O(un1_x_15_0_0_0[8])
);
// @8:30
MUXCY_L un1_x_15_0_cry_2_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_1),
.S(un1_x_15_0_axb_2),
.LO(un1_x_15_0_cry_2)
);
// @8:30
XORCY un1_x_15_0_s_1 (
.LI(un1_x_15_0_axb_1),
.CI(un1_x_15_0_cry_0),
.O(un1_x_15_0_0_0[7])
);
// @8:30
MUXCY_L un1_x_15_0_cry_1_cZ (
.DI(GND),
.CI(un1_x_15_0_cry_0),
.S(un1_x_15_0_axb_1),
.LO(un1_x_15_0_cry_1)
);
// @8:30
MUXCY_L un1_x_15_0_cry_0_cZ (
.DI(GND),
.CI(VCC),
.S(un1_x_15_0_axb_0),
.LO(un1_x_15_0_cry_0)
);
// @8:30
XORCY un1_x_10_4_s_8 (
.LI(un1_x_10_4_s_8_false),
.CI(un1_x_10_4_cry_7),
.O(un1_x_10_4[8])
);
// @8:30
XORCY un1_x_10_4_s_7 (
.LI(un1_x_10_4_axb_7),
.CI(un1_x_10_4_cry_6),
.O(un1_x_10_4[7])
);
// @8:30
MUXCY_L un1_x_10_4_cry_7_cZ (
.DI(x_8[6]),
.CI(un1_x_10_4_cry_6),
.S(un1_x_10_4_axb_7),
.LO(un1_x_10_4_cry_7)
);
// @8:30
XORCY un1_x_10_4_s_6 (
.LI(un1_x_10_4_axb_6),
.CI(un1_x_10_4_cry_5),
.O(un1_x_10_4[6])
);
// @8:30
MUXCY_L un1_x_10_4_cry_6_cZ (
.DI(x_8[5]),
.CI(un1_x_10_4_cry_5),
.S(un1_x_10_4_axb_6),
.LO(un1_x_10_4_cry_6)
);
// @8:30
XORCY un1_x_10_4_s_5 (
.LI(un1_x_10_4_axb_5),
.CI(un1_x_10_4_cry_4),
.O(un1_x_10_4[5])
);
// @8:30
MUXCY_L un1_x_10_4_cry_5_cZ (
.DI(x_8[4]),
.CI(un1_x_10_4_cry_4),
.S(un1_x_10_4_axb_5),
.LO(un1_x_10_4_cry_5)
);
// @8:30
XORCY un1_x_10_4_s_4 (
.LI(un1_x_10_4_axb_4),
.CI(un1_x_10_4_cry_3),
.O(un1_x_10_4[4])
);
// @8:30
MUXCY_L un1_x_10_4_cry_4_cZ (
.DI(x_8[3]),
.CI(un1_x_10_4_cry_3),
.S(un1_x_10_4_axb_4),
.LO(un1_x_10_4_cry_4)
);
// @8:30
XORCY un1_x_10_4_s_3 (
.LI(un1_x_10_4_axb_3),
.CI(un1_x_10_4_cry_2),
.O(un1_x_10_4[3])
);
// @8:30
MUXCY_L un1_x_10_4_cry_3_cZ (
.DI(x_8[2]),
.CI(un1_x_10_4_cry_2),
.S(un1_x_10_4_axb_3),
.LO(un1_x_10_4_cry_3)
);
// @8:30
XORCY un1_x_10_4_s_2 (
.LI(un1_x_10_4_axb_2),
.CI(un1_x_10_4_cry_1),
.O(un1_x_10_4[2])
);
// @8:30
MUXCY_L un1_x_10_4_cry_2_cZ (
.DI(x_8[1]),
.CI(un1_x_10_4_cry_1),
.S(un1_x_10_4_axb_2),
.LO(un1_x_10_4_cry_2)
);
// @8:30
MUXCY_L un1_x_10_4_cry_1_cZ (
.DI(x_8[0]),
.CI(GND),
.S(un1_x_10_4_cry_1_sf),
.LO(un1_x_10_4_cry_1)
);
// @8:30
XORCY un84_sop_1_s_14_cZ (
.LI(un84_sop_1_axb_14),
.CI(un84_sop_1_cry_13),
.O(un84_sop_1_s_14)
);
// @8:30
XORCY un84_sop_1_s_13_cZ (
.LI(un84_sop_1_axb_13),
.CI(un84_sop_1_cry_12),
.O(un84_sop_1_s_13)
);
// @8:30
MUXCY_L un84_sop_1_cry_13_cZ (
.DI(un84_sop_1_4[13]),
.CI(un84_sop_1_cry_12),
.S(un84_sop_1_axb_13),
.LO(un84_sop_1_cry_13)
);
// @8:30
XORCY un84_sop_1_s_12_cZ (
.LI(un84_sop_1_axb_12),
.CI(un84_sop_1_cry_11),
.O(un84_sop_1_s_12)
);
// @8:30
MUXCY_L un84_sop_1_cry_12_cZ (
.DI(un84_sop_1_4[12]),
.CI(un84_sop_1_cry_11),
.S(un84_sop_1_axb_12),
.LO(un84_sop_1_cry_12)
);
// @8:30
XORCY un84_sop_1_s_11_cZ (
.LI(un84_sop_1_axb_11),
.CI(un84_sop_1_cry_10),
.O(un84_sop_1_s_11)
);
// @8:30
MUXCY_L un84_sop_1_cry_11_cZ (
.DI(un84_sop_1_4[11]),
.CI(un84_sop_1_cry_10),
.S(un84_sop_1_axb_11),
.LO(un84_sop_1_cry_11)
);
// @8:30
XORCY un84_sop_1_s_10_cZ (
.LI(un84_sop_1_axb_10),
.CI(un84_sop_1_cry_9),
.O(un84_sop_1_s_10)
);
// @8:30
MUXCY_L un84_sop_1_cry_10_cZ (
.DI(un84_sop_1_4[10]),
.CI(un84_sop_1_cry_9),
.S(un84_sop_1_axb_10),
.LO(un84_sop_1_cry_10)
);
// @8:30
XORCY un84_sop_1_s_9_cZ (
.LI(un84_sop_1_axb_9),
.CI(un84_sop_1_cry_8),
.O(un84_sop_1_s_9)
);
// @8:30
MUXCY_L un84_sop_1_cry_9_cZ (
.DI(un84_sop_1_4[9]),
.CI(un84_sop_1_cry_8),
.S(un84_sop_1_axb_9),
.LO(un84_sop_1_cry_9)
);
// @8:30
XORCY un84_sop_1_s_8_cZ (
.LI(un84_sop_1_axb_8),
.CI(un84_sop_1_cry_7),
.O(un84_sop_1_s_8)
);
// @8:30
MUXCY_L un84_sop_1_cry_8_cZ (
.DI(un84_sop_1_4[8]),
.CI(un84_sop_1_cry_7),
.S(un84_sop_1_axb_8),
.LO(un84_sop_1_cry_8)
);
// @8:30
XORCY un84_sop_1_s_7_cZ (
.LI(un84_sop_1_axb_7),
.CI(un84_sop_1_cry_6),
.O(un84_sop_1_s_7)
);
// @8:30
MUXCY_L un84_sop_1_cry_7_cZ (
.DI(un84_sop_1_4[7]),
.CI(un84_sop_1_cry_6),
.S(un84_sop_1_axb_7),
.LO(un84_sop_1_cry_7)
);
// @8:30
MUXCY_L un84_sop_1_cry_6_cZ (
.DI(un84_sop_1_4[6]),
.CI(un84_sop_1_cry_5),
.S(un84_sop_1_axb_6),
.LO(un84_sop_1_cry_6)
);
// @8:30
MUXCY_L un84_sop_1_cry_5_cZ (
.DI(un84_sop_1_4[5]),
.CI(un84_sop_1_cry_4),
.S(un84_sop_1_axb_5),
.LO(un84_sop_1_cry_5)
);
// @8:30
MUXCY_L un84_sop_1_cry_4_cZ (
.DI(un84_sop_1_4[4]),
.CI(un84_sop_1_cry_3),
.S(un84_sop_1_axb_4),
.LO(un84_sop_1_cry_4)
);
// @8:30
MUXCY_L un84_sop_1_cry_3_cZ (
.DI(un84_sop_1_4[3]),
.CI(un84_sop_1_cry_2),
.S(un84_sop_1_axb_3),
.LO(un84_sop_1_cry_3)
);
// @8:30
MUXCY_L un84_sop_1_cry_2_cZ (
.DI(un84_sop_1_4[2]),
.CI(un84_sop_1_cry_1),
.S(un84_sop_1_axb_2),
.LO(un84_sop_1_cry_2)
);
// @8:30
MUXCY_L un84_sop_1_cry_1_cZ (
.DI(un84_sop_1_4[1]),
.CI(un84_sop_1_cry_0),
.S(un84_sop_1_axb_1),
.LO(un84_sop_1_cry_1)
);
// @8:30
MUXCY_L un84_sop_1_cry_0_cZ (
.DI(un84_sop_1_6[0]),
.CI(GND),
.S(un84_sop_1_axb_0),
.LO(un84_sop_1_cry_0)
);
// @8:30
XORCY un84_sop_1_4_s_14 (
.LI(un84_sop_1_4_axb_14),
.CI(un84_sop_1_4_cry_13),
.O(un84_sop_1_4[14])
);
// @8:30
XORCY un84_sop_1_4_s_13 (
.LI(un84_sop_1_4_axb_13),
.CI(un84_sop_1_4_cry_12),
.O(un84_sop_1_4[13])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_13_cZ (
.DI(un84_sop_1_7[13]),
.CI(un84_sop_1_4_cry_12),
.S(un84_sop_1_4_axb_13),
.LO(un84_sop_1_4_cry_13)
);
// @8:30
XORCY un84_sop_1_4_s_12 (
.LI(un84_sop_1_4_axb_12),
.CI(un84_sop_1_4_cry_11),
.O(un84_sop_1_4[12])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_12_cZ (
.DI(un84_sop_1_7[12]),
.CI(un84_sop_1_4_cry_11),
.S(un84_sop_1_4_axb_12),
.LO(un84_sop_1_4_cry_12)
);
// @8:30
XORCY un84_sop_1_4_s_11 (
.LI(un84_sop_1_4_axb_11),
.CI(un84_sop_1_4_cry_10),
.O(un84_sop_1_4[11])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_11_cZ (
.DI(un84_sop_1_7[11]),
.CI(un84_sop_1_4_cry_10),
.S(un84_sop_1_4_axb_11),
.LO(un84_sop_1_4_cry_11)
);
// @8:30
XORCY un84_sop_1_4_s_10 (
.LI(un84_sop_1_4_axb_10),
.CI(un84_sop_1_4_cry_9),
.O(un84_sop_1_4[10])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_10_cZ (
.DI(un84_sop_1_7[10]),
.CI(un84_sop_1_4_cry_9),
.S(un84_sop_1_4_axb_10),
.LO(un84_sop_1_4_cry_10)
);
// @8:30
XORCY un84_sop_1_4_s_9 (
.LI(un84_sop_1_4_axb_9),
.CI(un84_sop_1_4_cry_8),
.O(un84_sop_1_4[9])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_9_cZ (
.DI(un84_sop_1_7[9]),
.CI(un84_sop_1_4_cry_8),
.S(un84_sop_1_4_axb_9),
.LO(un84_sop_1_4_cry_9)
);
// @8:30
XORCY un84_sop_1_4_s_8 (
.LI(un84_sop_1_4_axb_8),
.CI(un84_sop_1_4_cry_7),
.O(un84_sop_1_4[8])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_8_cZ (
.DI(un84_sop_1_7[8]),
.CI(un84_sop_1_4_cry_7),
.S(un84_sop_1_4_axb_8),
.LO(un84_sop_1_4_cry_8)
);
// @8:30
XORCY un84_sop_1_4_s_7 (
.LI(un84_sop_1_4_axb_7),
.CI(un84_sop_1_4_cry_6),
.O(un84_sop_1_4[7])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_7_cZ (
.DI(un84_sop_1_7[7]),
.CI(un84_sop_1_4_cry_6),
.S(un84_sop_1_4_axb_7),
.LO(un84_sop_1_4_cry_7)
);
// @8:30
XORCY un84_sop_1_4_s_6 (
.LI(un84_sop_1_4_axb_6),
.CI(un84_sop_1_4_cry_5),
.O(un84_sop_1_4[6])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_6_cZ (
.DI(un84_sop_1_7[6]),
.CI(un84_sop_1_4_cry_5),
.S(un84_sop_1_4_axb_6),
.LO(un84_sop_1_4_cry_6)
);
// @8:30
XORCY un84_sop_1_4_s_5 (
.LI(un84_sop_1_4_axb_5),
.CI(un84_sop_1_4_cry_4),
.O(un84_sop_1_4[5])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_5_cZ (
.DI(un84_sop_1_7[5]),
.CI(un84_sop_1_4_cry_4),
.S(un84_sop_1_4_axb_5),
.LO(un84_sop_1_4_cry_5)
);
// @8:30
XORCY un84_sop_1_4_s_4 (
.LI(un84_sop_1_4_axb_4),
.CI(un84_sop_1_4_cry_3),
.O(un84_sop_1_4[4])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_4_cZ (
.DI(un84_sop_1_7[4]),
.CI(un84_sop_1_4_cry_3),
.S(un84_sop_1_4_axb_4),
.LO(un84_sop_1_4_cry_4)
);
// @8:30
XORCY un84_sop_1_4_s_3 (
.LI(un84_sop_1_4_axb_3),
.CI(un84_sop_1_4_cry_2),
.O(un84_sop_1_4[3])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_3_cZ (
.DI(un84_sop_1_7[3]),
.CI(un84_sop_1_4_cry_2),
.S(un84_sop_1_4_axb_3),
.LO(un84_sop_1_4_cry_3)
);
// @8:30
XORCY un84_sop_1_4_s_2 (
.LI(un84_sop_1_4_axb_2),
.CI(un84_sop_1_4_cry_1),
.O(un84_sop_1_4[2])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_2_cZ (
.DI(un84_sop_1_7[2]),
.CI(un84_sop_1_4_cry_1),
.S(un84_sop_1_4_axb_2),
.LO(un84_sop_1_4_cry_2)
);
// @8:30
XORCY un84_sop_1_4_s_1 (
.LI(un84_sop_1_4_axb_1),
.CI(un84_sop_1_4_cry_0),
.O(un84_sop_1_4[1])
);
// @8:30
MUXCY_L un84_sop_1_4_cry_1_cZ (
.DI(un84_sop_1_7[1]),
.CI(un84_sop_1_4_cry_0),
.S(un84_sop_1_4_axb_1),
.LO(un84_sop_1_4_cry_1)
);
// @8:30
MUXCY_L un84_sop_1_4_cry_0_cZ (
.DI(un84_sop_1_7[0]),
.CI(GND),
.S(un84_sop_1_4[0]),
.LO(un84_sop_1_4_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_10 (
.LI(un84_sop_0_0_0_0_11_7_axb_10),
.CI(un84_sop_0_0_0_0_11_7_cry_9),
.O(un84_sop_0_0_0_0_11_7[14])
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_9 (
.LI(un84_sop_0_0_0_0_11_7_axb_9),
.CI(un84_sop_0_0_0_0_11_7_cry_8),
.O(un84_sop_0_0_0_0_11_7[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_9_cZ (
.DI(un84_sop_0_0_0_0_0[9]),
.CI(un84_sop_0_0_0_0_11_7_cry_8),
.S(un84_sop_0_0_0_0_11_7_axb_9),
.LO(un84_sop_0_0_0_0_11_7_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_8 (
.LI(un84_sop_0_0_0_0_11_7_axb_8),
.CI(un84_sop_0_0_0_0_11_7_cry_7),
.O(un84_sop_0_0_0_0_11_7[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_8_cZ (
.DI(un84_sop_0_0_0_0_0[8]),
.CI(un84_sop_0_0_0_0_11_7_cry_7),
.S(un84_sop_0_0_0_0_11_7_axb_8),
.LO(un84_sop_0_0_0_0_11_7_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_7 (
.LI(un84_sop_0_0_0_0_11_7_axb_7),
.CI(un84_sop_0_0_0_0_11_7_cry_6),
.O(un84_sop_0_0_0_0_11_7[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_7_cZ (
.DI(un84_sop_0_0_0_0_0[7]),
.CI(un84_sop_0_0_0_0_11_7_cry_6),
.S(un84_sop_0_0_0_0_11_7_axb_7),
.LO(un84_sop_0_0_0_0_11_7_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_6 (
.LI(un84_sop_0_0_0_0_11_7_axb_6),
.CI(un84_sop_0_0_0_0_11_7_cry_5),
.O(un84_sop_0_0_0_0_11_7[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_6_cZ (
.DI(un84_sop_0_0_0_0_0[6]),
.CI(un84_sop_0_0_0_0_11_7_cry_5),
.S(un84_sop_0_0_0_0_11_7_axb_6),
.LO(un84_sop_0_0_0_0_11_7_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_5 (
.LI(un84_sop_0_0_0_0_11_7_axb_5),
.CI(un84_sop_0_0_0_0_11_7_cry_4),
.O(un84_sop_0_0_0_0_11_7[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_5_cZ (
.DI(un84_sop_0_0_0_0_0[5]),
.CI(un84_sop_0_0_0_0_11_7_cry_4),
.S(un84_sop_0_0_0_0_11_7_axb_5),
.LO(un84_sop_0_0_0_0_11_7_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_4 (
.LI(un84_sop_0_0_0_0_11_7_axb_4),
.CI(un84_sop_0_0_0_0_11_7_cry_3),
.O(un84_sop_0_0_0_0_11_7[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_4_cZ (
.DI(un84_sop_0_0_0_0_0[4]),
.CI(un84_sop_0_0_0_0_11_7_cry_3),
.S(un84_sop_0_0_0_0_11_7_axb_4),
.LO(un84_sop_0_0_0_0_11_7_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_3 (
.LI(un84_sop_0_0_0_0_11_7_axb_3),
.CI(un84_sop_0_0_0_0_11_7_cry_2),
.O(un84_sop_0_0_0_0_11_7[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_3_cZ (
.DI(un84_sop_0_0_0_0_0[3]),
.CI(un84_sop_0_0_0_0_11_7_cry_2),
.S(un84_sop_0_0_0_0_11_7_axb_3),
.LO(un84_sop_0_0_0_0_11_7_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_2 (
.LI(un84_sop_0_0_0_0_11_7_axb_2),
.CI(un84_sop_0_0_0_0_11_7_cry_1),
.O(un84_sop_0_0_0_0_11_7[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_2_cZ (
.DI(un84_sop_0_0_0_0_0[2]),
.CI(un84_sop_0_0_0_0_11_7_cry_1),
.S(un84_sop_0_0_0_0_11_7_axb_2),
.LO(un84_sop_0_0_0_0_11_7_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_0_11_7_s_1 (
.LI(un84_sop_0_0_0_0_11_7_axb_1),
.CI(un84_sop_0_0_0_0_11_7_cry_0),
.O(un84_sop_0_0_0_0_11_7[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_1_cZ (
.DI(un84_sop_0_0_0_0_0[1]),
.CI(un84_sop_0_0_0_0_11_7_cry_0),
.S(un84_sop_0_0_0_0_11_7_axb_1),
.LO(un84_sop_0_0_0_0_11_7_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_0_11_7_cry_0_cZ (
.DI(un84_sop_0_0_0_0_0[0]),
.CI(GND),
.S(un84_sop_0_0_0_0_11_7[0]),
.LO(un84_sop_0_0_0_0_11_7_cry_0)
);
// @8:30
XORCY un84_sop_1_7_s_14 (
.LI(un84_sop_1_7_axb_14),
.CI(un84_sop_1_7_cry_13),
.O(un84_sop_1_7[14])
);
// @8:30
XORCY un84_sop_1_7_s_13 (
.LI(un84_sop_1_7_axb_13),
.CI(un84_sop_1_7_cry_12),
.O(un84_sop_1_7[13])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_13_cZ (
.DI(un84_sop_0_0_0_0_5[13]),
.CI(un84_sop_1_7_cry_12),
.S(un84_sop_1_7_axb_13),
.LO(un84_sop_1_7_cry_13)
);
// @8:30
XORCY un84_sop_1_7_s_12 (
.LI(un84_sop_1_7_axb_12),
.CI(un84_sop_1_7_cry_11),
.O(un84_sop_1_7[12])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_12_cZ (
.DI(un84_sop_0_0_0_0_5[12]),
.CI(un84_sop_1_7_cry_11),
.S(un84_sop_1_7_axb_12),
.LO(un84_sop_1_7_cry_12)
);
// @8:30
XORCY un84_sop_1_7_s_11 (
.LI(un84_sop_1_7_axb_11),
.CI(un84_sop_1_7_cry_10),
.O(un84_sop_1_7[11])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_11_cZ (
.DI(un84_sop_0_0_0_0_5[11]),
.CI(un84_sop_1_7_cry_10),
.S(un84_sop_1_7_axb_11),
.LO(un84_sop_1_7_cry_11)
);
// @8:30
XORCY un84_sop_1_7_s_10 (
.LI(un84_sop_1_7_axb_10),
.CI(un84_sop_1_7_cry_9),
.O(un84_sop_1_7[10])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_10_cZ (
.DI(un84_sop_0_0_0_0_5[10]),
.CI(un84_sop_1_7_cry_9),
.S(un84_sop_1_7_axb_10),
.LO(un84_sop_1_7_cry_10)
);
// @8:30
XORCY un84_sop_1_7_s_9 (
.LI(un84_sop_1_7_axb_9),
.CI(un84_sop_1_7_cry_8),
.O(un84_sop_1_7[9])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_9_cZ (
.DI(un84_sop_0_0_0_0_5[9]),
.CI(un84_sop_1_7_cry_8),
.S(un84_sop_1_7_axb_9),
.LO(un84_sop_1_7_cry_9)
);
// @8:30
XORCY un84_sop_1_7_s_8 (
.LI(un84_sop_1_7_axb_8),
.CI(un84_sop_1_7_cry_7),
.O(un84_sop_1_7[8])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_8_cZ (
.DI(un84_sop_0_0_0_0_5[8]),
.CI(un84_sop_1_7_cry_7),
.S(un84_sop_1_7_axb_8),
.LO(un84_sop_1_7_cry_8)
);
// @8:30
XORCY un84_sop_1_7_s_7 (
.LI(un84_sop_1_7_axb_7),
.CI(un84_sop_1_7_cry_6),
.O(un84_sop_1_7[7])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_7_cZ (
.DI(un84_sop_0_0_0_0_5[7]),
.CI(un84_sop_1_7_cry_6),
.S(un84_sop_1_7_axb_7),
.LO(un84_sop_1_7_cry_7)
);
// @8:30
XORCY un84_sop_1_7_s_6 (
.LI(un84_sop_1_7_axb_6),
.CI(un84_sop_1_7_cry_5),
.O(un84_sop_1_7[6])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_6_cZ (
.DI(un84_sop_0_0_0_0_5[6]),
.CI(un84_sop_1_7_cry_5),
.S(un84_sop_1_7_axb_6),
.LO(un84_sop_1_7_cry_6)
);
// @8:30
XORCY un84_sop_1_7_s_5 (
.LI(un84_sop_1_7_axb_5),
.CI(un84_sop_1_7_cry_4),
.O(un84_sop_1_7[5])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_5_cZ (
.DI(un84_sop_0_0_0_0_5[5]),
.CI(un84_sop_1_7_cry_4),
.S(un84_sop_1_7_axb_5),
.LO(un84_sop_1_7_cry_5)
);
// @8:30
XORCY un84_sop_1_7_s_4 (
.LI(un84_sop_1_7_axb_4),
.CI(un84_sop_1_7_cry_3),
.O(un84_sop_1_7[4])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_4_cZ (
.DI(un84_sop_0_0_0_0_5[4]),
.CI(un84_sop_1_7_cry_3),
.S(un84_sop_1_7_axb_4),
.LO(un84_sop_1_7_cry_4)
);
// @8:30
XORCY un84_sop_1_7_s_3 (
.LI(un84_sop_1_7_axb_3),
.CI(un84_sop_1_7_cry_2),
.O(un84_sop_1_7[3])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_3_cZ (
.DI(un84_sop_0_0_0_0_5[3]),
.CI(un84_sop_1_7_cry_2),
.S(un84_sop_1_7_axb_3),
.LO(un84_sop_1_7_cry_3)
);
// @8:30
XORCY un84_sop_1_7_s_2 (
.LI(un84_sop_1_7_axb_2),
.CI(un84_sop_1_7_cry_1),
.O(un84_sop_1_7[2])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_2_cZ (
.DI(un84_sop_0_0_0_0_5[2]),
.CI(un84_sop_1_7_cry_1),
.S(un84_sop_1_7_axb_2),
.LO(un84_sop_1_7_cry_2)
);
// @8:30
XORCY un84_sop_1_7_s_1 (
.LI(un84_sop_1_7_axb_1),
.CI(un84_sop_1_7_cry_0),
.O(un84_sop_1_7[1])
);
// @8:30
MUXCY_L un84_sop_1_7_cry_1_cZ (
.DI(un84_sop_0_0_0_0_5[1]),
.CI(un84_sop_1_7_cry_0),
.S(un84_sop_1_7_axb_1),
.LO(un84_sop_1_7_cry_1)
);
// @8:30
MUXCY_L un84_sop_1_7_cry_0_cZ (
.DI(un84_sop_0_0_0_0_5[0]),
.CI(GND),
.S(un84_sop_1_7[0]),
.LO(un84_sop_1_7_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_14 (
.LI(un84_sop_0_0_0_1_6_axb_14),
.CI(un84_sop_0_0_0_1_6_cry_13),
.O(un84_sop_0_0_0_5_0[14])
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_13 (
.LI(un84_sop_0_0_0_1_6_axb_13),
.CI(un84_sop_0_0_0_1_6_cry_12),
.O(un84_sop_0_0_0_5_0[13])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_13_cZ (
.DI(un84_sop_0_0_0_1_6_4[13]),
.CI(un84_sop_0_0_0_1_6_cry_12),
.S(un84_sop_0_0_0_1_6_axb_13),
.LO(un84_sop_0_0_0_1_6_cry_13)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_12 (
.LI(un84_sop_0_0_0_1_6_axb_12),
.CI(un84_sop_0_0_0_1_6_cry_11),
.O(un84_sop_0_0_0_5_0[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_12_cZ (
.DI(un84_sop_0_0_0_1_6_4[12]),
.CI(un84_sop_0_0_0_1_6_cry_11),
.S(un84_sop_0_0_0_1_6_axb_12),
.LO(un84_sop_0_0_0_1_6_cry_12)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_11 (
.LI(un84_sop_0_0_0_1_6_axb_11),
.CI(un84_sop_0_0_0_1_6_cry_10),
.O(un84_sop_0_0_0_5_0[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_11_cZ (
.DI(un84_sop_0_0_0_1_6_4[11]),
.CI(un84_sop_0_0_0_1_6_cry_10),
.S(un84_sop_0_0_0_1_6_axb_11),
.LO(un84_sop_0_0_0_1_6_cry_11)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_10 (
.LI(un84_sop_0_0_0_1_6_axb_10),
.CI(un84_sop_0_0_0_1_6_cry_9),
.O(un84_sop_0_0_0_5_0[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_10_cZ (
.DI(un84_sop_0_0_0_1_6_4[10]),
.CI(un84_sop_0_0_0_1_6_cry_9),
.S(un84_sop_0_0_0_1_6_axb_10),
.LO(un84_sop_0_0_0_1_6_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_9 (
.LI(un84_sop_0_0_0_1_6_axb_9),
.CI(un84_sop_0_0_0_1_6_cry_8),
.O(un84_sop_0_0_0_5_0[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_9_cZ (
.DI(un84_sop_0_0_0_1_6_4[9]),
.CI(un84_sop_0_0_0_1_6_cry_8),
.S(un84_sop_0_0_0_1_6_axb_9),
.LO(un84_sop_0_0_0_1_6_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_8 (
.LI(un84_sop_0_0_0_1_6_axb_8),
.CI(un84_sop_0_0_0_1_6_cry_7),
.O(un84_sop_0_0_0_5_0[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_8_cZ (
.DI(un84_sop_0_0_0_1_6_4[8]),
.CI(un84_sop_0_0_0_1_6_cry_7),
.S(un84_sop_0_0_0_1_6_axb_8),
.LO(un84_sop_0_0_0_1_6_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_7 (
.LI(un84_sop_0_0_0_1_6_axb_7),
.CI(un84_sop_0_0_0_1_6_cry_6),
.O(un84_sop_0_0_0_5_0[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_7_cZ (
.DI(un84_sop_0_0_0_1_6_4[7]),
.CI(un84_sop_0_0_0_1_6_cry_6),
.S(un84_sop_0_0_0_1_6_axb_7),
.LO(un84_sop_0_0_0_1_6_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_6 (
.LI(un84_sop_0_0_0_1_6_axb_6),
.CI(un84_sop_0_0_0_1_6_cry_5),
.O(un84_sop_0_0_0_5_0[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_6_cZ (
.DI(un84_sop_0_0_0_1_6_4[6]),
.CI(un84_sop_0_0_0_1_6_cry_5),
.S(un84_sop_0_0_0_1_6_axb_6),
.LO(un84_sop_0_0_0_1_6_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_5 (
.LI(un84_sop_0_0_0_1_6_axb_5),
.CI(un84_sop_0_0_0_1_6_cry_4),
.O(un84_sop_0_0_0_5_0[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_5_cZ (
.DI(un84_sop_0_0_0_1_6_4[5]),
.CI(un84_sop_0_0_0_1_6_cry_4),
.S(un84_sop_0_0_0_1_6_axb_5),
.LO(un84_sop_0_0_0_1_6_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_4 (
.LI(un84_sop_0_0_0_1_6_axb_4),
.CI(un84_sop_0_0_0_1_6_cry_3),
.O(un84_sop_0_0_0_5_0[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_4_cZ (
.DI(un84_sop_0_0_0_1_6_4[4]),
.CI(un84_sop_0_0_0_1_6_cry_3),
.S(un84_sop_0_0_0_1_6_axb_4),
.LO(un84_sop_0_0_0_1_6_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_3 (
.LI(un84_sop_0_0_0_1_6_axb_3),
.CI(un84_sop_0_0_0_1_6_cry_2),
.O(un84_sop_0_0_0_5_0[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_3_cZ (
.DI(un84_sop_0_0_0_1_6_4[3]),
.CI(un84_sop_0_0_0_1_6_cry_2),
.S(un84_sop_0_0_0_1_6_axb_3),
.LO(un84_sop_0_0_0_1_6_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_2 (
.LI(un84_sop_0_0_0_1_6_axb_2),
.CI(un84_sop_0_0_0_1_6_cry_1),
.O(un84_sop_0_0_0_5_0[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_2_cZ (
.DI(un84_sop_0_0_0_1_6_4[2]),
.CI(un84_sop_0_0_0_1_6_cry_1),
.S(un84_sop_0_0_0_1_6_axb_2),
.LO(un84_sop_0_0_0_1_6_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_s_1 (
.LI(un84_sop_0_0_0_1_6_axb_1),
.CI(un84_sop_0_0_0_1_6_cry_0),
.O(un84_sop_0_0_0_5_0[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_1_cZ (
.DI(un84_sop_0_0_0_1_6_4[1]),
.CI(un84_sop_0_0_0_1_6_cry_0),
.S(un84_sop_0_0_0_1_6_axb_1),
.LO(un84_sop_0_0_0_1_6_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_cry_0_cZ (
.DI(un84_sop_0_0_0_1_6_6[0]),
.CI(GND),
.S(un84_sop_0_0_0_5_0[0]),
.LO(un84_sop_0_0_0_1_6_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_14 (
.LI(un84_sop_0_0_0_1_6_4_axb_14),
.CI(un84_sop_0_0_0_1_6_4_cry_13),
.O(un84_sop_0_0_0_1_6_4[14])
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_13 (
.LI(un84_sop_0_0_0_1_6_4_axb_13),
.CI(un84_sop_0_0_0_1_6_4_cry_12),
.O(un84_sop_0_0_0_1_6_4[13])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_13_cZ (
.DI(un84_sop_0_0_0_1_6_8[13]),
.CI(un84_sop_0_0_0_1_6_4_cry_12),
.S(un84_sop_0_0_0_1_6_4_axb_13),
.LO(un84_sop_0_0_0_1_6_4_cry_13)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_12 (
.LI(un84_sop_0_0_0_1_6_4_axb_12),
.CI(un84_sop_0_0_0_1_6_4_cry_11),
.O(un84_sop_0_0_0_1_6_4[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_12_cZ (
.DI(un84_sop_0_0_0_1_6_8[12]),
.CI(un84_sop_0_0_0_1_6_4_cry_11),
.S(un84_sop_0_0_0_1_6_4_axb_12),
.LO(un84_sop_0_0_0_1_6_4_cry_12)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_11 (
.LI(un84_sop_0_0_0_1_6_4_axb_11),
.CI(un84_sop_0_0_0_1_6_4_cry_10),
.O(un84_sop_0_0_0_1_6_4[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_11_cZ (
.DI(un84_sop_0_0_0_1_6_8[11]),
.CI(un84_sop_0_0_0_1_6_4_cry_10),
.S(un84_sop_0_0_0_1_6_4_axb_11),
.LO(un84_sop_0_0_0_1_6_4_cry_11)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_10 (
.LI(un84_sop_0_0_0_1_6_4_axb_10),
.CI(un84_sop_0_0_0_1_6_4_cry_9),
.O(un84_sop_0_0_0_1_6_4[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_10_cZ (
.DI(un84_sop_0_0_0_1_6_8[10]),
.CI(un84_sop_0_0_0_1_6_4_cry_9),
.S(un84_sop_0_0_0_1_6_4_axb_10),
.LO(un84_sop_0_0_0_1_6_4_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_9 (
.LI(un84_sop_0_0_0_1_6_4_axb_9),
.CI(un84_sop_0_0_0_1_6_4_cry_8),
.O(un84_sop_0_0_0_1_6_4[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_9_cZ (
.DI(un84_sop_0_0_0_1_6_8[9]),
.CI(un84_sop_0_0_0_1_6_4_cry_8),
.S(un84_sop_0_0_0_1_6_4_axb_9),
.LO(un84_sop_0_0_0_1_6_4_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_8 (
.LI(un84_sop_0_0_0_1_6_4_axb_8),
.CI(un84_sop_0_0_0_1_6_4_cry_7),
.O(un84_sop_0_0_0_1_6_4[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_8_cZ (
.DI(un84_sop_0_0_0_1_6_8[8]),
.CI(un84_sop_0_0_0_1_6_4_cry_7),
.S(un84_sop_0_0_0_1_6_4_axb_8),
.LO(un84_sop_0_0_0_1_6_4_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_7 (
.LI(un84_sop_0_0_0_1_6_4_axb_7),
.CI(un84_sop_0_0_0_1_6_4_cry_6),
.O(un84_sop_0_0_0_1_6_4[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_7_cZ (
.DI(un84_sop_0_0_0_1_6_8[7]),
.CI(un84_sop_0_0_0_1_6_4_cry_6),
.S(un84_sop_0_0_0_1_6_4_axb_7),
.LO(un84_sop_0_0_0_1_6_4_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_6 (
.LI(un84_sop_0_0_0_1_6_4_axb_6),
.CI(un84_sop_0_0_0_1_6_4_cry_5),
.O(un84_sop_0_0_0_1_6_4[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_6_cZ (
.DI(un84_sop_0_0_0_1_6_8[6]),
.CI(un84_sop_0_0_0_1_6_4_cry_5),
.S(un84_sop_0_0_0_1_6_4_axb_6),
.LO(un84_sop_0_0_0_1_6_4_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_5 (
.LI(un84_sop_0_0_0_1_6_4_axb_5),
.CI(un84_sop_0_0_0_1_6_4_cry_4),
.O(un84_sop_0_0_0_1_6_4[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_5_cZ (
.DI(un84_sop_0_0_0_1_6_8[5]),
.CI(un84_sop_0_0_0_1_6_4_cry_4),
.S(un84_sop_0_0_0_1_6_4_axb_5),
.LO(un84_sop_0_0_0_1_6_4_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_4 (
.LI(un84_sop_0_0_0_1_6_4_axb_4),
.CI(un84_sop_0_0_0_1_6_4_cry_3),
.O(un84_sop_0_0_0_1_6_4[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_4_cZ (
.DI(un84_sop_0_0_0_1_6_8[4]),
.CI(un84_sop_0_0_0_1_6_4_cry_3),
.S(un84_sop_0_0_0_1_6_4_axb_4),
.LO(un84_sop_0_0_0_1_6_4_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_3 (
.LI(un84_sop_0_0_0_1_6_4_axb_3),
.CI(un84_sop_0_0_0_1_6_4_cry_2),
.O(un84_sop_0_0_0_1_6_4[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_3_cZ (
.DI(un1_x_6_0[4]),
.CI(un84_sop_0_0_0_1_6_4_cry_2),
.S(un84_sop_0_0_0_1_6_4_axb_3),
.LO(un84_sop_0_0_0_1_6_4_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_2 (
.LI(un84_sop_0_0_0_1_6_4_axb_2),
.CI(un84_sop_0_0_0_1_6_4_cry_1),
.O(un84_sop_0_0_0_1_6_4[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_2_cZ (
.DI(un1_x_6_0[3]),
.CI(un84_sop_0_0_0_1_6_4_cry_1),
.S(un84_sop_0_0_0_1_6_4_axb_2),
.LO(un84_sop_0_0_0_1_6_4_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_4_s_1 (
.LI(un84_sop_0_0_0_1_6_4_axb_1),
.CI(un84_sop_0_0_0_1_6_4_cry_0),
.O(un84_sop_0_0_0_1_6_4[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_1_cZ (
.DI(un1_x_6_0[2]),
.CI(un84_sop_0_0_0_1_6_4_cry_0),
.S(un84_sop_0_0_0_1_6_4_axb_1),
.LO(un84_sop_0_0_0_1_6_4_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_4_cry_0_cZ (
.DI(un1_x_6_0[1]),
.CI(GND),
.S(un84_sop_0_0_0_1_6_4[0]),
.LO(un84_sop_0_0_0_1_6_4_cry_0)
);
// @8:30
XORCY un1_x_10_s_11 (
.LI(un1_x_10_axb_11),
.CI(un1_x_10_cry_10),
.O(un1_x_10_0_0[15])
);
// @8:30
XORCY un1_x_10_s_10 (
.LI(un1_x_10_axb_10),
.CI(un1_x_10_cry_9),
.O(un1_x_10_0_0[14])
);
// @8:30
MUXCY_L un1_x_10_cry_10_cZ (
.DI(un1_x_10_4[10]),
.CI(un1_x_10_cry_9),
.S(un1_x_10_axb_10),
.LO(un1_x_10_cry_10)
);
// @8:30
XORCY un1_x_10_s_9 (
.LI(un1_x_10_axb_9),
.CI(un1_x_10_cry_8),
.O(un1_x_10_0_0[13])
);
// @8:30
MUXCY_L un1_x_10_cry_9_cZ (
.DI(un1_x_10_4[9]),
.CI(un1_x_10_cry_8),
.S(un1_x_10_axb_9),
.LO(un1_x_10_cry_9)
);
// @8:30
XORCY un1_x_10_s_8 (
.LI(un1_x_10_axb_8),
.CI(un1_x_10_cry_7),
.O(un1_x_10_0_0[12])
);
// @8:30
MUXCY_L un1_x_10_cry_8_cZ (
.DI(un1_x_10_4[8]),
.CI(un1_x_10_cry_7),
.S(un1_x_10_axb_8),
.LO(un1_x_10_cry_8)
);
// @8:30
XORCY un1_x_10_s_7 (
.LI(un1_x_10_axb_7),
.CI(un1_x_10_cry_6),
.O(un1_x_10_0_0[11])
);
// @8:30
MUXCY_L un1_x_10_cry_7_cZ (
.DI(un1_x_10_4[7]),
.CI(un1_x_10_cry_6),
.S(un1_x_10_axb_7),
.LO(un1_x_10_cry_7)
);
// @8:30
XORCY un1_x_10_s_6 (
.LI(un1_x_10_axb_6),
.CI(un1_x_10_cry_5),
.O(un1_x_10_0_0[10])
);
// @8:30
MUXCY_L un1_x_10_cry_6_cZ (
.DI(un1_x_10_4[6]),
.CI(un1_x_10_cry_5),
.S(un1_x_10_axb_6),
.LO(un1_x_10_cry_6)
);
// @8:30
XORCY un1_x_10_s_5 (
.LI(un1_x_10_axb_5),
.CI(un1_x_10_cry_4),
.O(un1_x_10_0_0[9])
);
// @8:30
MUXCY_L un1_x_10_cry_5_cZ (
.DI(un1_x_10_4[5]),
.CI(un1_x_10_cry_4),
.S(un1_x_10_axb_5),
.LO(un1_x_10_cry_5)
);
// @8:30
XORCY un1_x_10_s_4 (
.LI(un1_x_10_axb_4),
.CI(un1_x_10_cry_3),
.O(un1_x_10_0_0[8])
);
// @8:30
MUXCY_L un1_x_10_cry_4_cZ (
.DI(un1_x_10_4[4]),
.CI(un1_x_10_cry_3),
.S(un1_x_10_axb_4),
.LO(un1_x_10_cry_4)
);
// @8:30
MUXCY_L un1_x_10_cry_3_cZ (
.DI(un1_x_10_4[3]),
.CI(GND),
.S(un1_x_10_axb_3),
.LO(un1_x_10_cry_3)
);
// @8:30
XORCY un84_sop_1_6_0_s_13 (
.LI(un84_sop_1_6_0_axb_13),
.CI(un84_sop_1_6_0_cry_12),
.O(un84_sop_1_6[14])
);
// @8:30
XORCY un84_sop_1_6_0_s_12 (
.LI(un84_sop_1_6_0_axb_12),
.CI(un84_sop_1_6_0_cry_11),
.O(un84_sop_1_6[12])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_12_cZ (
.DI(un84_sop_1_6_0_o5_11),
.CI(un84_sop_1_6_0_cry_11),
.S(un84_sop_1_6_0_axb_12),
.LO(un84_sop_1_6_0_cry_12)
);
// @8:30
XORCY un84_sop_1_6_0_s_11 (
.LI(un84_sop_1_6_0_axb_11),
.CI(un84_sop_1_6_0_cry_10),
.O(un84_sop_1_6[11])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_11_cZ (
.DI(un84_sop_1_6_0_o5_10),
.CI(un84_sop_1_6_0_cry_10),
.S(un84_sop_1_6_0_axb_11),
.LO(un84_sop_1_6_0_cry_11)
);
// @8:30
XORCY un84_sop_1_6_0_s_10 (
.LI(un84_sop_1_6_0_axb_10),
.CI(un84_sop_1_6_0_cry_9),
.O(un84_sop_1_6[10])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_10_cZ (
.DI(un84_sop_1_6_0_o5_9),
.CI(un84_sop_1_6_0_cry_9),
.S(un84_sop_1_6_0_axb_10),
.LO(un84_sop_1_6_0_cry_10)
);
// @8:30
XORCY un84_sop_1_6_0_s_9 (
.LI(un84_sop_1_6_0_axb_9),
.CI(un84_sop_1_6_0_cry_8),
.O(un84_sop_1_6[9])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_9_cZ (
.DI(un84_sop_1_6_0_o5_8),
.CI(un84_sop_1_6_0_cry_8),
.S(un84_sop_1_6_0_axb_9),
.LO(un84_sop_1_6_0_cry_9)
);
// @8:30
XORCY un84_sop_1_6_0_s_8 (
.LI(un84_sop_1_6_0_axb_8),
.CI(un84_sop_1_6_0_cry_7),
.O(un84_sop_1_6[8])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_8_cZ (
.DI(un84_sop_1_6_0_o5_7),
.CI(un84_sop_1_6_0_cry_7),
.S(un84_sop_1_6_0_axb_8),
.LO(un84_sop_1_6_0_cry_8)
);
// @8:30
XORCY un84_sop_1_6_0_s_7 (
.LI(un84_sop_1_6_0_axb_7),
.CI(un84_sop_1_6_0_cry_6),
.O(un84_sop_1_6[7])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_7_cZ (
.DI(un84_sop_1_6_0_o5_6),
.CI(un84_sop_1_6_0_cry_6),
.S(un84_sop_1_6_0_axb_7),
.LO(un84_sop_1_6_0_cry_7)
);
// @8:30
XORCY un84_sop_1_6_0_s_6 (
.LI(un84_sop_1_6_0_axb_6),
.CI(un84_sop_1_6_0_cry_5),
.O(un84_sop_1_6[6])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_6_cZ (
.DI(un84_sop_1_6_0_o5_5),
.CI(un84_sop_1_6_0_cry_5),
.S(un84_sop_1_6_0_axb_6),
.LO(un84_sop_1_6_0_cry_6)
);
// @8:30
XORCY un84_sop_1_6_0_s_5 (
.LI(un84_sop_1_6_0_axb_5),
.CI(un84_sop_1_6_0_cry_4),
.O(un84_sop_1_6[5])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_5_cZ (
.DI(un84_sop_1_6_0_o5_4),
.CI(un84_sop_1_6_0_cry_4),
.S(un84_sop_1_6_0_axb_5),
.LO(un84_sop_1_6_0_cry_5)
);
// @8:30
XORCY un84_sop_1_6_0_s_4 (
.LI(un84_sop_1_6_0_axb_4),
.CI(un84_sop_1_6_0_cry_3),
.O(un84_sop_1_6[4])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_4_cZ (
.DI(un84_sop_1_6_0_o5_3),
.CI(un84_sop_1_6_0_cry_3),
.S(un84_sop_1_6_0_axb_4),
.LO(un84_sop_1_6_0_cry_4)
);
// @8:30
XORCY un84_sop_1_6_0_s_3 (
.LI(un84_sop_1_6_0_axb_3),
.CI(un84_sop_1_6_0_cry_2),
.O(un84_sop_1_6[3])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_3_cZ (
.DI(un84_sop_1_6_0_o5_2),
.CI(un84_sop_1_6_0_cry_2),
.S(un84_sop_1_6_0_axb_3),
.LO(un84_sop_1_6_0_cry_3)
);
// @8:30
XORCY un84_sop_1_6_0_s_2 (
.LI(un84_sop_1_6_0_axb_2),
.CI(un84_sop_1_6_0_cry_1),
.O(un84_sop_1_6[2])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_2_cZ (
.DI(un84_sop_1_6_0_axb_1_lut6_2_O5),
.CI(un84_sop_1_6_0_cry_1),
.S(un84_sop_1_6_0_axb_2),
.LO(un84_sop_1_6_0_cry_2)
);
// @8:30
XORCY un84_sop_1_6_0_s_1 (
.LI(un84_sop_1_6_0_axb_1),
.CI(un84_sop_1_6_0_cry_0),
.O(un84_sop_1_6[1])
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_1_cZ (
.DI(GND),
.CI(un84_sop_1_6_0_cry_0),
.S(un84_sop_1_6_0_axb_1),
.LO(un84_sop_1_6_0_cry_1)
);
// @8:30
MUXCY_L un84_sop_1_6_0_cry_0_cZ (
.DI(un1_x_2[5]),
.CI(un84_sop_1_6_0_cry_0_cy),
.S(un84_sop_1_6_0_axb_0_0),
.LO(un84_sop_1_6_0_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_11 (
.LI(un84_sop_0_0_0_1_6_8_axb_11),
.CI(un84_sop_0_0_0_1_6_8_cry_10),
.O(un84_sop_0_0_0_1_6_8[14])
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_10 (
.LI(un84_sop_0_0_0_1_6_8_axb_10),
.CI(un84_sop_0_0_0_1_6_8_cry_9),
.O(un84_sop_0_0_0_1_6_8[13])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_10_cZ (
.DI(un84_sop_0_0_0_10_0[13]),
.CI(un84_sop_0_0_0_1_6_8_cry_9),
.S(un84_sop_0_0_0_1_6_8_axb_10),
.LO(un84_sop_0_0_0_1_6_8_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_9 (
.LI(un84_sop_0_0_0_1_6_8_axb_9),
.CI(un84_sop_0_0_0_1_6_8_cry_8),
.O(un84_sop_0_0_0_1_6_8[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_9_cZ (
.DI(un84_sop_0_0_0_10_0[12]),
.CI(un84_sop_0_0_0_1_6_8_cry_8),
.S(un84_sop_0_0_0_1_6_8_axb_9),
.LO(un84_sop_0_0_0_1_6_8_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_8 (
.LI(un84_sop_0_0_0_1_6_8_axb_8),
.CI(un84_sop_0_0_0_1_6_8_cry_7),
.O(un84_sop_0_0_0_1_6_8[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_8_cZ (
.DI(un84_sop_0_0_0_1_6_8_o5_7),
.CI(un84_sop_0_0_0_1_6_8_cry_7),
.S(un84_sop_0_0_0_1_6_8_axb_8),
.LO(un84_sop_0_0_0_1_6_8_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_7 (
.LI(un84_sop_0_0_0_1_6_8_axb_7),
.CI(un84_sop_0_0_0_1_6_8_cry_6),
.O(un84_sop_0_0_0_1_6_8[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_7_cZ (
.DI(un84_sop_0_0_0_1_6_8_o5_6),
.CI(un84_sop_0_0_0_1_6_8_cry_6),
.S(un84_sop_0_0_0_1_6_8_axb_7),
.LO(un84_sop_0_0_0_1_6_8_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_6 (
.LI(un84_sop_0_0_0_1_6_8_axb_6),
.CI(un84_sop_0_0_0_1_6_8_cry_5),
.O(un84_sop_0_0_0_1_6_8[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_6_cZ (
.DI(un84_sop_0_0_0_1_6_8_o5_5),
.CI(un84_sop_0_0_0_1_6_8_cry_5),
.S(un84_sop_0_0_0_1_6_8_axb_6),
.LO(un84_sop_0_0_0_1_6_8_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_5 (
.LI(un84_sop_0_0_0_1_6_8_axb_5),
.CI(un84_sop_0_0_0_1_6_8_cry_4),
.O(un84_sop_0_0_0_1_6_8[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_5_cZ (
.DI(un84_sop_0_0_0_1_6_8_o5_4),
.CI(un84_sop_0_0_0_1_6_8_cry_4),
.S(un84_sop_0_0_0_1_6_8_axb_5),
.LO(un84_sop_0_0_0_1_6_8_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_4 (
.LI(un84_sop_0_0_0_1_6_8_axb_4),
.CI(un84_sop_0_0_0_1_6_8_cry_3),
.O(un84_sop_0_0_0_1_6_8[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_4_cZ (
.DI(un84_sop_0_0_0_1_6_8_o5_3),
.CI(un84_sop_0_0_0_1_6_8_cry_3),
.S(un84_sop_0_0_0_1_6_8_axb_4),
.LO(un84_sop_0_0_0_1_6_8_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_3 (
.LI(un84_sop_0_0_0_1_6_8_axb_3),
.CI(un84_sop_0_0_0_1_6_8_cry_2),
.O(un84_sop_0_0_0_1_6_8[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_3_cZ (
.DI(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5),
.CI(un84_sop_0_0_0_1_6_8_cry_2),
.S(un84_sop_0_0_0_1_6_8_axb_3),
.LO(un84_sop_0_0_0_1_6_8_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_2 (
.LI(un84_sop_0_0_0_1_6_8_axb_2),
.CI(un84_sop_0_0_0_1_6_8_cry_1),
.O(un84_sop_0_0_0_1_6_8[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_2_cZ (
.DI(GND),
.CI(un84_sop_0_0_0_1_6_8_cry_1),
.S(un84_sop_0_0_0_1_6_8_axb_2),
.LO(un84_sop_0_0_0_1_6_8_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_1_6_8_s_1 (
.LI(un84_sop_0_0_0_1_6_8_axb_1),
.CI(un84_sop_0_0_0_1_6_8_cry_0),
.O(un84_sop_0_0_0_1_6_8[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_1_cZ (
.DI(un84_sop_0_0_0_10_0[4]),
.CI(un84_sop_0_0_0_1_6_8_cry_0),
.S(un84_sop_0_0_0_1_6_8_axb_1),
.LO(un84_sop_0_0_0_1_6_8_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_1_6_8_cry_0_cZ (
.DI(un84_sop_0_0_0_10_0[3]),
.CI(GND),
.S(un84_sop_0_0_0_1_6_8[3]),
.LO(un84_sop_0_0_0_1_6_8_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_14 (
.LI(un84_sop_0_0_0_6_6_0_axb_14),
.CI(un84_sop_0_0_0_6_6_0_cry_13),
.O(un84_sop_0_0_0_1_6_6[14])
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_13 (
.LI(un84_sop_0_0_0_6_6_0_axb_13),
.CI(un84_sop_0_0_0_6_6_0_cry_12),
.O(un84_sop_0_0_0_1_6_6[13])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_13_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_12),
.CI(un84_sop_0_0_0_6_6_0_cry_12),
.S(un84_sop_0_0_0_6_6_0_axb_13),
.LO(un84_sop_0_0_0_6_6_0_cry_13)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_12 (
.LI(un84_sop_0_0_0_6_6_0_axb_12),
.CI(un84_sop_0_0_0_6_6_0_cry_11),
.O(un84_sop_0_0_0_1_6_6[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_12_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_11),
.CI(un84_sop_0_0_0_6_6_0_cry_11),
.S(un84_sop_0_0_0_6_6_0_axb_12),
.LO(un84_sop_0_0_0_6_6_0_cry_12)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_11 (
.LI(un84_sop_0_0_0_6_6_0_axb_11),
.CI(un84_sop_0_0_0_6_6_0_cry_10),
.O(un84_sop_0_0_0_1_6_6[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_11_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_10),
.CI(un84_sop_0_0_0_6_6_0_cry_10),
.S(un84_sop_0_0_0_6_6_0_axb_11),
.LO(un84_sop_0_0_0_6_6_0_cry_11)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_10 (
.LI(un84_sop_0_0_0_6_6_0_axb_10),
.CI(un84_sop_0_0_0_6_6_0_cry_9),
.O(un84_sop_0_0_0_1_6_6[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_10_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_9),
.CI(un84_sop_0_0_0_6_6_0_cry_9),
.S(un84_sop_0_0_0_6_6_0_axb_10),
.LO(un84_sop_0_0_0_6_6_0_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_9 (
.LI(un84_sop_0_0_0_6_6_0_axb_9),
.CI(un84_sop_0_0_0_6_6_0_cry_8),
.O(un84_sop_0_0_0_1_6_6[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_9_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_8),
.CI(un84_sop_0_0_0_6_6_0_cry_8),
.S(un84_sop_0_0_0_6_6_0_axb_9),
.LO(un84_sop_0_0_0_6_6_0_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_8 (
.LI(un84_sop_0_0_0_6_6_0_axb_8),
.CI(un84_sop_0_0_0_6_6_0_cry_7),
.O(un84_sop_0_0_0_1_6_6[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_8_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_7),
.CI(un84_sop_0_0_0_6_6_0_cry_7),
.S(un84_sop_0_0_0_6_6_0_axb_8),
.LO(un84_sop_0_0_0_6_6_0_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_7 (
.LI(un84_sop_0_0_0_6_6_0_axb_7),
.CI(un84_sop_0_0_0_6_6_0_cry_6),
.O(un84_sop_0_0_0_1_6_6[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_7_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_6),
.CI(un84_sop_0_0_0_6_6_0_cry_6),
.S(un84_sop_0_0_0_6_6_0_axb_7),
.LO(un84_sop_0_0_0_6_6_0_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_6 (
.LI(un84_sop_0_0_0_6_6_0_axb_6),
.CI(un84_sop_0_0_0_6_6_0_cry_5),
.O(un84_sop_0_0_0_1_6_6[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_6_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_5),
.CI(un84_sop_0_0_0_6_6_0_cry_5),
.S(un84_sop_0_0_0_6_6_0_axb_6),
.LO(un84_sop_0_0_0_6_6_0_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_5 (
.LI(un84_sop_0_0_0_6_6_0_axb_5),
.CI(un84_sop_0_0_0_6_6_0_cry_4),
.O(un84_sop_0_0_0_1_6_6[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_5_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_4),
.CI(un84_sop_0_0_0_6_6_0_cry_4),
.S(un84_sop_0_0_0_6_6_0_axb_5),
.LO(un84_sop_0_0_0_6_6_0_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_4 (
.LI(un84_sop_0_0_0_6_6_0_axb_4),
.CI(un84_sop_0_0_0_6_6_0_cry_3),
.O(un84_sop_0_0_0_1_6_6[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_4_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_3),
.CI(un84_sop_0_0_0_6_6_0_cry_3),
.S(un84_sop_0_0_0_6_6_0_axb_4),
.LO(un84_sop_0_0_0_6_6_0_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_3 (
.LI(un84_sop_0_0_0_6_6_0_axb_3),
.CI(un84_sop_0_0_0_6_6_0_cry_2),
.O(un84_sop_0_0_0_1_6_6[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_3_cZ (
.DI(un84_sop_0_0_0_6_6_0_o5_2),
.CI(un84_sop_0_0_0_6_6_0_cry_2),
.S(un84_sop_0_0_0_6_6_0_axb_3),
.LO(un84_sop_0_0_0_6_6_0_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_2 (
.LI(un84_sop_0_0_0_6_6_0_axb_2),
.CI(un84_sop_0_0_0_6_6_0_cry_1),
.O(un84_sop_0_0_0_1_6_6[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_2_cZ (
.DI(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5),
.CI(un84_sop_0_0_0_6_6_0_cry_1),
.S(un84_sop_0_0_0_6_6_0_axb_2),
.LO(un84_sop_0_0_0_6_6_0_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_6_6_0_s_1 (
.LI(un84_sop_0_0_0_6_6_0_axb_1),
.CI(un84_sop_0_0_0_6_6_0_cry_0),
.O(un84_sop_0_0_0_1_6_6[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_1_cZ (
.DI(GND),
.CI(un84_sop_0_0_0_6_6_0_cry_0),
.S(un84_sop_0_0_0_6_6_0_axb_1),
.LO(un84_sop_0_0_0_6_6_0_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cZ (
.DI(un1_x_8_0[4]),
.CI(un84_sop_0_0_0_6_6_0_cry_0_cy),
.S(un84_sop_0_0_0_6_0_axb_0_1),
.LO(un84_sop_0_0_0_6_6_0_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_14 (
.LI(un84_sop_0_0_0_11_0_axb_14),
.CI(un84_sop_0_0_0_11_0_cry_13),
.O(un84_sop_0_0_0_0_8[14])
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_13 (
.LI(un84_sop_0_0_0_11_0_axb_13),
.CI(un84_sop_0_0_0_11_0_cry_12),
.O(un84_sop_0_0_0_0_8[13])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_13_cZ (
.DI(un84_sop_0_0_0_11_0_o5_12),
.CI(un84_sop_0_0_0_11_0_cry_12),
.S(un84_sop_0_0_0_11_0_axb_13),
.LO(un84_sop_0_0_0_11_0_cry_13)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_12 (
.LI(un84_sop_0_0_0_11_0_axb_12),
.CI(un84_sop_0_0_0_11_0_cry_11),
.O(un84_sop_0_0_0_0_8[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_12_cZ (
.DI(un84_sop_0_0_0_11_0_o5_11),
.CI(un84_sop_0_0_0_11_0_cry_11),
.S(un84_sop_0_0_0_11_0_axb_12),
.LO(un84_sop_0_0_0_11_0_cry_12)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_11 (
.LI(un84_sop_0_0_0_11_0_axb_11),
.CI(un84_sop_0_0_0_11_0_cry_10),
.O(un84_sop_0_0_0_0_8[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_11_cZ (
.DI(un84_sop_0_0_0_11_0_o5_10),
.CI(un84_sop_0_0_0_11_0_cry_10),
.S(un84_sop_0_0_0_11_0_axb_11),
.LO(un84_sop_0_0_0_11_0_cry_11)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_10 (
.LI(un84_sop_0_0_0_11_0_axb_10),
.CI(un84_sop_0_0_0_11_0_cry_9),
.O(un84_sop_0_0_0_0_8[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_10_cZ (
.DI(un84_sop_0_0_0_11_0_o5_9),
.CI(un84_sop_0_0_0_11_0_cry_9),
.S(un84_sop_0_0_0_11_0_axb_10),
.LO(un84_sop_0_0_0_11_0_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_9 (
.LI(un84_sop_0_0_0_11_0_axb_9),
.CI(un84_sop_0_0_0_11_0_cry_8),
.O(un84_sop_0_0_0_0_8[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_9_cZ (
.DI(un84_sop_0_0_0_11_0_o5_8),
.CI(un84_sop_0_0_0_11_0_cry_8),
.S(un84_sop_0_0_0_11_0_axb_9),
.LO(un84_sop_0_0_0_11_0_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_8 (
.LI(un84_sop_0_0_0_11_0_axb_8),
.CI(un84_sop_0_0_0_11_0_cry_7),
.O(un84_sop_0_0_0_0_8[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_8_cZ (
.DI(un84_sop_0_0_0_11_0_o5_7),
.CI(un84_sop_0_0_0_11_0_cry_7),
.S(un84_sop_0_0_0_11_0_axb_8),
.LO(un84_sop_0_0_0_11_0_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_7 (
.LI(un84_sop_0_0_0_11_0_axb_7),
.CI(un84_sop_0_0_0_11_0_cry_6),
.O(un84_sop_0_0_0_0_8[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_7_cZ (
.DI(un84_sop_0_0_0_11_0_o5_6),
.CI(un84_sop_0_0_0_11_0_cry_6),
.S(un84_sop_0_0_0_11_0_axb_7),
.LO(un84_sop_0_0_0_11_0_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_6 (
.LI(un84_sop_0_0_0_11_0_axb_6),
.CI(un84_sop_0_0_0_11_0_cry_5),
.O(un84_sop_0_0_0_0_8[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_6_cZ (
.DI(un84_sop_0_0_0_11_0_o5_5),
.CI(un84_sop_0_0_0_11_0_cry_5),
.S(un84_sop_0_0_0_11_0_axb_6),
.LO(un84_sop_0_0_0_11_0_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_5 (
.LI(un84_sop_0_0_0_11_0_axb_5),
.CI(un84_sop_0_0_0_11_0_cry_4),
.O(un84_sop_0_0_0_0_8[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_5_cZ (
.DI(un84_sop_0_0_0_11_0_o5_4),
.CI(un84_sop_0_0_0_11_0_cry_4),
.S(un84_sop_0_0_0_11_0_axb_5),
.LO(un84_sop_0_0_0_11_0_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_4 (
.LI(un84_sop_0_0_0_11_0_axb_4),
.CI(un84_sop_0_0_0_11_0_cry_3),
.O(un84_sop_0_0_0_0_8[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_4_cZ (
.DI(un84_sop_0_0_0_11_0_o5_3),
.CI(un84_sop_0_0_0_11_0_cry_3),
.S(un84_sop_0_0_0_11_0_axb_4),
.LO(un84_sop_0_0_0_11_0_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_3 (
.LI(un84_sop_0_0_0_11_0_axb_3),
.CI(un84_sop_0_0_0_11_0_cry_2),
.O(un84_sop_0_0_0_0_8[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_3_cZ (
.DI(un84_sop_0_0_0_11_0_o5_2),
.CI(un84_sop_0_0_0_11_0_cry_2),
.S(un84_sop_0_0_0_11_0_axb_3),
.LO(un84_sop_0_0_0_11_0_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_2 (
.LI(un84_sop_0_0_0_11_0_axb_2),
.CI(un84_sop_0_0_0_11_0_cry_1),
.O(un84_sop_0_0_0_0_8[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_2_cZ (
.DI(un84_sop_0_0_0_11_0_cry_2_RNO),
.CI(un84_sop_0_0_0_11_0_cry_1),
.S(un84_sop_0_0_0_11_0_axb_2),
.LO(un84_sop_0_0_0_11_0_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_1 (
.LI(un84_sop_0_0_0_11_0_axb_1),
.CI(un84_sop_0_0_0_11_0_cry_0),
.O(un84_sop_0_0_0_0_8[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_1_cZ (
.DI(un84_sop_0_0_0_0_11_6[1]),
.CI(un84_sop_0_0_0_11_0_cry_0),
.S(un84_sop_0_0_0_11_0_axb_1),
.LO(un84_sop_0_0_0_11_0_cry_1)
);
// @8:30
XORCY un84_sop_0_0_0_11_0_s_0 (
.LI(un84_sop_0_0_0_11_0_axb_0),
.CI(un84_sop_0_0_0_11_0_cry_0_cy),
.O(un84_sop_0_0_0_0_8[0])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cZ (
.DI(un84_sop_0_0_0_0_11_6[0]),
.CI(un84_sop_0_0_0_11_0_cry_0_cy),
.S(un84_sop_0_0_0_11_0_axb_0),
.LO(un84_sop_0_0_0_11_0_cry_0)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_13 (
.LI(un84_sop_0_0_0_11_6_0_axb_13),
.CI(un84_sop_0_0_0_11_6_0_cry_12),
.O(un84_sop_0_0_0_0_11_6[14])
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_12 (
.LI(un84_sop_0_0_0_11_6_0_axb_12),
.CI(un84_sop_0_0_0_11_6_0_cry_11),
.O(un84_sop_0_0_0_0_11_6[12])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_12_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_11),
.CI(un84_sop_0_0_0_11_6_0_cry_11),
.S(un84_sop_0_0_0_11_6_0_axb_12),
.LO(un84_sop_0_0_0_11_6_0_cry_12)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_11 (
.LI(un84_sop_0_0_0_11_6_0_axb_11),
.CI(un84_sop_0_0_0_11_6_0_cry_10),
.O(un84_sop_0_0_0_0_11_6[11])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_11_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_10),
.CI(un84_sop_0_0_0_11_6_0_cry_10),
.S(un84_sop_0_0_0_11_6_0_axb_11),
.LO(un84_sop_0_0_0_11_6_0_cry_11)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_10 (
.LI(un84_sop_0_0_0_11_6_0_axb_10),
.CI(un84_sop_0_0_0_11_6_0_cry_9),
.O(un84_sop_0_0_0_0_11_6[10])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_10_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_9),
.CI(un84_sop_0_0_0_11_6_0_cry_9),
.S(un84_sop_0_0_0_11_6_0_axb_10),
.LO(un84_sop_0_0_0_11_6_0_cry_10)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_9 (
.LI(un84_sop_0_0_0_11_6_0_axb_9),
.CI(un84_sop_0_0_0_11_6_0_cry_8),
.O(un84_sop_0_0_0_0_11_6[9])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_9_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_8),
.CI(un84_sop_0_0_0_11_6_0_cry_8),
.S(un84_sop_0_0_0_11_6_0_axb_9),
.LO(un84_sop_0_0_0_11_6_0_cry_9)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_8 (
.LI(un84_sop_0_0_0_11_6_0_axb_8),
.CI(un84_sop_0_0_0_11_6_0_cry_7),
.O(un84_sop_0_0_0_0_11_6[8])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_8_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_7),
.CI(un84_sop_0_0_0_11_6_0_cry_7),
.S(un84_sop_0_0_0_11_6_0_axb_8),
.LO(un84_sop_0_0_0_11_6_0_cry_8)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_7 (
.LI(un84_sop_0_0_0_11_6_0_axb_7),
.CI(un84_sop_0_0_0_11_6_0_cry_6),
.O(un84_sop_0_0_0_0_11_6[7])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_7_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_6),
.CI(un84_sop_0_0_0_11_6_0_cry_6),
.S(un84_sop_0_0_0_11_6_0_axb_7),
.LO(un84_sop_0_0_0_11_6_0_cry_7)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_6 (
.LI(un84_sop_0_0_0_11_6_0_axb_6),
.CI(un84_sop_0_0_0_11_6_0_cry_5),
.O(un84_sop_0_0_0_0_11_6[6])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_6_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_5),
.CI(un84_sop_0_0_0_11_6_0_cry_5),
.S(un84_sop_0_0_0_11_6_0_axb_6),
.LO(un84_sop_0_0_0_11_6_0_cry_6)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_5 (
.LI(un84_sop_0_0_0_11_6_0_axb_5),
.CI(un84_sop_0_0_0_11_6_0_cry_4),
.O(un84_sop_0_0_0_0_11_6[5])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_5_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_4),
.CI(un84_sop_0_0_0_11_6_0_cry_4),
.S(un84_sop_0_0_0_11_6_0_axb_5),
.LO(un84_sop_0_0_0_11_6_0_cry_5)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_4 (
.LI(un84_sop_0_0_0_11_6_0_axb_4),
.CI(un84_sop_0_0_0_11_6_0_cry_3),
.O(un84_sop_0_0_0_0_11_6[4])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_4_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_3),
.CI(un84_sop_0_0_0_11_6_0_cry_3),
.S(un84_sop_0_0_0_11_6_0_axb_4),
.LO(un84_sop_0_0_0_11_6_0_cry_4)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_3 (
.LI(un84_sop_0_0_0_11_6_0_axb_3),
.CI(un84_sop_0_0_0_11_6_0_cry_2),
.O(un84_sop_0_0_0_0_11_6[3])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_3_cZ (
.DI(un84_sop_0_0_0_11_6_0_o5_2),
.CI(un84_sop_0_0_0_11_6_0_cry_2),
.S(un84_sop_0_0_0_11_6_0_axb_3),
.LO(un84_sop_0_0_0_11_6_0_cry_3)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_2 (
.LI(un84_sop_0_0_0_11_6_0_axb_2),
.CI(un84_sop_0_0_0_11_6_0_cry_1),
.O(un84_sop_0_0_0_0_11_6[2])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_2_cZ (
.DI(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5),
.CI(un84_sop_0_0_0_11_6_0_cry_1),
.S(un84_sop_0_0_0_11_6_0_axb_2),
.LO(un84_sop_0_0_0_11_6_0_cry_2)
);
// @8:30
XORCY un84_sop_0_0_0_11_6_0_s_1 (
.LI(un84_sop_0_0_0_11_6_0_axb_1),
.CI(un84_sop_0_0_0_11_6_0_cry_0),
.O(un84_sop_0_0_0_0_11_6[1])
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_1_cZ (
.DI(GND),
.CI(un84_sop_0_0_0_11_6_0_cry_0),
.S(un84_sop_0_0_0_11_6_0_axb_1),
.LO(un84_sop_0_0_0_11_6_0_cry_1)
);
// @8:30
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cZ (
.DI(un1_x_13_0_0[5]),
.CI(un84_sop_0_0_0_11_6_0_cry_0_cy),
.S(un84_sop_0_0_0_6_0_axb_0_0),
.LO(un84_sop_0_0_0_11_6_0_cry_0)
);
// @8:30
DSP48E1 \un1_x_1[15:4] (
.ACOUT(ACOUT[29:0]),
.BCOUT({x_0_10[7], x_0_9[7], x_0_8[7], x_0_7[7], x_0_6[7], x_0_5[7], x_0_4[7], x_0_3[7], x_0_2[7], x_0_1[7], x_0_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT),
.CARRYOUT(CARRYOUT[3:0]),
.MULTSIGNOUT(MULTSIGNOUT),
.OVERFLOW(OVERFLOW),
.P({P_uc[47:12], un1_x_1[15:4]}),
.PATTERNBDETECT(PATTERNBDETECT),
.PATTERNDETECT(PATTERNDETECT),
.PCOUT(PCOUT[47:0]),
.UNDERFLOW(UNDERFLOW),
.A({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, GND, VCC, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7], x_in[7:0]}),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_1[15:4] .ACASCREG=0;
defparam \un1_x_1[15:4] .ADREG=0;
defparam \un1_x_1[15:4] .ALUMODEREG=0;
defparam \un1_x_1[15:4] .AREG=0;
defparam \un1_x_1[15:4] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_1[15:4] .A_INPUT="DIRECT";
defparam \un1_x_1[15:4] .BCASCREG=1;
defparam \un1_x_1[15:4] .BREG=1;
defparam \un1_x_1[15:4] .B_INPUT="DIRECT";
defparam \un1_x_1[15:4] .CARRYINREG=0;
defparam \un1_x_1[15:4] .CARRYINSELREG=0;
defparam \un1_x_1[15:4] .CREG=1;
defparam \un1_x_1[15:4] .DREG=0;
defparam \un1_x_1[15:4] .INMODEREG=0;
defparam \un1_x_1[15:4] .MREG=0;
defparam \un1_x_1[15:4] .OPMODEREG=0;
defparam \un1_x_1[15:4] .PREG=1;
defparam \un1_x_1[15:4] .USE_DPORT="FALSE";
defparam \un1_x_1[15:4] .USE_MULT="MULTIPLY";
defparam \un1_x_1[15:4] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_12[15:4] (
.ACOUT(ACOUT_0[29:0]),
.BCOUT({x_9_10[7], x_9_9[7], x_9_8[7], x_9_7[7], x_9_6[7], x_9_5[7], x_9_4[7], x_9_3[7], x_9_2[7], x_9_1[7], x_9_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_0),
.CARRYOUT(CARRYOUT_0[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_0),
.OVERFLOW(OVERFLOW_0),
.P({P_uc_0[47:12], un1_x_12_0_0[15:4]}),
.PATTERNBDETECT(PATTERNBDETECT_0),
.PATTERNDETECT(PATTERNDETECT_0),
.PCOUT(PCOUT_0[47:0]),
.UNDERFLOW(UNDERFLOW_0),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, VCC, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7], x_7[7:0]}),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(VCC),
.CEA2(VCC),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(VCC),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_12[15:4] .ACASCREG=2;
defparam \un1_x_12[15:4] .ADREG=0;
defparam \un1_x_12[15:4] .ALUMODEREG=0;
defparam \un1_x_12[15:4] .AREG=2;
defparam \un1_x_12[15:4] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_12[15:4] .A_INPUT="DIRECT";
defparam \un1_x_12[15:4] .BCASCREG=2;
defparam \un1_x_12[15:4] .BREG=2;
defparam \un1_x_12[15:4] .B_INPUT="DIRECT";
defparam \un1_x_12[15:4] .CARRYINREG=0;
defparam \un1_x_12[15:4] .CARRYINSELREG=0;
defparam \un1_x_12[15:4] .CREG=1;
defparam \un1_x_12[15:4] .DREG=0;
defparam \un1_x_12[15:4] .INMODEREG=0;
defparam \un1_x_12[15:4] .MREG=0;
defparam \un1_x_12[15:4] .OPMODEREG=0;
defparam \un1_x_12[15:4] .PREG=1;
defparam \un1_x_12[15:4] .USE_DPORT="FALSE";
defparam \un1_x_12[15:4] .USE_MULT="MULTIPLY";
defparam \un1_x_12[15:4] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_14[15:4] (
.ACOUT(ACOUT_1[29:0]),
.BCOUT(BCOUT_1[17:0]),
.CARRYCASCOUT(CARRYCASCOUT_1),
.CARRYOUT(CARRYOUT_1[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_1),
.OVERFLOW(OVERFLOW_1),
.P({P_uc_1[47:12], un1_x_14_0_0[15:4]}),
.PATTERNBDETECT(PATTERNBDETECT_1),
.PATTERNDETECT(PATTERNDETECT_1),
.PCOUT(PCOUT_1[47:0]),
.UNDERFLOW(UNDERFLOW_1),
.A({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, GND, VCC, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_10_10[7], x_10_9[7], x_10_8[7], x_10_7[7], x_10_6[7], x_10_5[7], x_10_4[7], x_10_3[7], x_10_2[7], x_10_1[7], x_10_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_14[15:4] .ACASCREG=0;
defparam \un1_x_14[15:4] .ADREG=0;
defparam \un1_x_14[15:4] .ALUMODEREG=0;
defparam \un1_x_14[15:4] .AREG=0;
defparam \un1_x_14[15:4] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_14[15:4] .A_INPUT="DIRECT";
defparam \un1_x_14[15:4] .BCASCREG=1;
defparam \un1_x_14[15:4] .BREG=1;
defparam \un1_x_14[15:4] .B_INPUT="CASCADE";
defparam \un1_x_14[15:4] .CARRYINREG=0;
defparam \un1_x_14[15:4] .CARRYINSELREG=0;
defparam \un1_x_14[15:4] .CREG=1;
defparam \un1_x_14[15:4] .DREG=0;
defparam \un1_x_14[15:4] .INMODEREG=0;
defparam \un1_x_14[15:4] .MREG=0;
defparam \un1_x_14[15:4] .OPMODEREG=0;
defparam \un1_x_14[15:4] .PREG=1;
defparam \un1_x_14[15:4] .USE_DPORT="FALSE";
defparam \un1_x_14[15:4] .USE_MULT="MULTIPLY";
defparam \un1_x_14[15:4] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_3[15:4] (
.ACOUT(ACOUT_2[29:0]),
.BCOUT({x_2_10[7], x_2_9[7], x_2_8[7], x_2_7[7], x_2_6[7], x_2_5[7], x_2_4[7], x_2_3[7], x_2_2[7], x_2_1[7], x_2_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_2),
.CARRYOUT(CARRYOUT_2[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_2),
.OVERFLOW(OVERFLOW_2),
.P({P_uc_2[47:12], un1_x_3[15:4]}),
.PATTERNBDETECT(PATTERNBDETECT_2),
.PATTERNDETECT(PATTERNDETECT_2),
.PCOUT(PCOUT_2[47:0]),
.UNDERFLOW(UNDERFLOW_2),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, VCC, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_1_10[7], x_1_9[7], x_1_8[7], x_1_7[7], x_1_6[7], x_1_5[7], x_1_4[7], x_1_3[7], x_1_2[7], x_1_1[7], x_1_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_3[15:4] .ACASCREG=0;
defparam \un1_x_3[15:4] .ADREG=0;
defparam \un1_x_3[15:4] .ALUMODEREG=0;
defparam \un1_x_3[15:4] .AREG=0;
defparam \un1_x_3[15:4] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_3[15:4] .A_INPUT="DIRECT";
defparam \un1_x_3[15:4] .BCASCREG=1;
defparam \un1_x_3[15:4] .BREG=1;
defparam \un1_x_3[15:4] .B_INPUT="CASCADE";
defparam \un1_x_3[15:4] .CARRYINREG=0;
defparam \un1_x_3[15:4] .CARRYINSELREG=0;
defparam \un1_x_3[15:4] .CREG=1;
defparam \un1_x_3[15:4] .DREG=0;
defparam \un1_x_3[15:4] .INMODEREG=0;
defparam \un1_x_3[15:4] .MREG=0;
defparam \un1_x_3[15:4] .OPMODEREG=0;
defparam \un1_x_3[15:4] .PREG=1;
defparam \un1_x_3[15:4] .USE_DPORT="FALSE";
defparam \un1_x_3[15:4] .USE_MULT="MULTIPLY";
defparam \un1_x_3[15:4] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_8[15:4] (
.ACOUT(ACOUT_3[29:0]),
.BCOUT({x_6_10[7], x_6_9[7], x_6_8[7], x_6_7[7], x_6_6[7], x_6_5[7], x_6_4[7], x_6_3[7], x_6_2[7], x_6_1[7], x_6_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_3),
.CARRYOUT(CARRYOUT_3[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_3),
.OVERFLOW(OVERFLOW_3),
.P({P_uc_3[47:12], un1_x_8_0[15:4]}),
.PATTERNBDETECT(PATTERNBDETECT_3),
.PATTERNDETECT(PATTERNDETECT_3),
.PCOUT(PCOUT_3[47:0]),
.UNDERFLOW(UNDERFLOW_3),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, VCC, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_5_10[7], x_5_9[7], x_5_8[7], x_5_7[7], x_5_6[7], x_5_5[7], x_5_4[7], x_5_3[7], x_5_2[7], x_5_1[7], x_5_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_8[15:4] .ACASCREG=0;
defparam \un1_x_8[15:4] .ADREG=0;
defparam \un1_x_8[15:4] .ALUMODEREG=0;
defparam \un1_x_8[15:4] .AREG=0;
defparam \un1_x_8[15:4] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_8[15:4] .A_INPUT="DIRECT";
defparam \un1_x_8[15:4] .BCASCREG=1;
defparam \un1_x_8[15:4] .BREG=1;
defparam \un1_x_8[15:4] .B_INPUT="CASCADE";
defparam \un1_x_8[15:4] .CARRYINREG=0;
defparam \un1_x_8[15:4] .CARRYINSELREG=0;
defparam \un1_x_8[15:4] .CREG=1;
defparam \un1_x_8[15:4] .DREG=0;
defparam \un1_x_8[15:4] .INMODEREG=0;
defparam \un1_x_8[15:4] .MREG=0;
defparam \un1_x_8[15:4] .OPMODEREG=0;
defparam \un1_x_8[15:4] .PREG=1;
defparam \un1_x_8[15:4] .USE_DPORT="FALSE";
defparam \un1_x_8[15:4] .USE_MULT="MULTIPLY";
defparam \un1_x_8[15:4] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_6[15:1] (
.ACOUT(ACOUT_4[29:0]),
.BCOUT({x_4_10[7], x_4_9[7], x_4_8[7], x_4_7[7], x_4_6[7], x_4_5[7], x_4_4[7], x_4_3[7], x_4_2[7], x_4_1[7], x_4_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_4),
.CARRYOUT(CARRYOUT_4[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_4),
.OVERFLOW(OVERFLOW_4),
.P({P_uc_4[47:15], un1_x_6_0[15:1]}),
.PATTERNBDETECT(PATTERNBDETECT_4),
.PATTERNDETECT(PATTERNDETECT_4),
.PCOUT(PCOUT_4[47:0]),
.UNDERFLOW(UNDERFLOW_4),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, GND, VCC, GND, GND, GND}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_3_10[7], x_3_9[7], x_3_8[7], x_3_7[7], x_3_6[7], x_3_5[7], x_3_4[7], x_3_3[7], x_3_2[7], x_3_1[7], x_3_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_6[15:1] .ACASCREG=0;
defparam \un1_x_6[15:1] .ADREG=0;
defparam \un1_x_6[15:1] .ALUMODEREG=0;
defparam \un1_x_6[15:1] .AREG=0;
defparam \un1_x_6[15:1] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_6[15:1] .A_INPUT="DIRECT";
defparam \un1_x_6[15:1] .BCASCREG=1;
defparam \un1_x_6[15:1] .BREG=1;
defparam \un1_x_6[15:1] .B_INPUT="CASCADE";
defparam \un1_x_6[15:1] .CARRYINREG=0;
defparam \un1_x_6[15:1] .CARRYINSELREG=0;
defparam \un1_x_6[15:1] .CREG=1;
defparam \un1_x_6[15:1] .DREG=0;
defparam \un1_x_6[15:1] .INMODEREG=0;
defparam \un1_x_6[15:1] .MREG=0;
defparam \un1_x_6[15:1] .OPMODEREG=0;
defparam \un1_x_6[15:1] .PREG=1;
defparam \un1_x_6[15:1] .USE_DPORT="FALSE";
defparam \un1_x_6[15:1] .USE_MULT="MULTIPLY";
defparam \un1_x_6[15:1] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_4[15:2] (
.ACOUT(ACOUT_5[29:0]),
.BCOUT({x_3_10[7], x_3_9[7], x_3_8[7], x_3_7[7], x_3_6[7], x_3_5[7], x_3_4[7], x_3_3[7], x_3_2[7], x_3_1[7], x_3_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_5),
.CARRYOUT(CARRYOUT_5[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_5),
.OVERFLOW(OVERFLOW_5),
.P({P_uc_5[47:15], P_uc_4[14], un1_x_4[15:2]}),
.PATTERNBDETECT(PATTERNBDETECT_5),
.PATTERNDETECT(PATTERNDETECT_5),
.PCOUT(PCOUT_5[47:0]),
.UNDERFLOW(UNDERFLOW_5),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, VCC, GND, GND, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_2_10[7], x_2_9[7], x_2_8[7], x_2_7[7], x_2_6[7], x_2_5[7], x_2_4[7], x_2_3[7], x_2_2[7], x_2_1[7], x_2_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_4[15:2] .ACASCREG=0;
defparam \un1_x_4[15:2] .ADREG=0;
defparam \un1_x_4[15:2] .ALUMODEREG=0;
defparam \un1_x_4[15:2] .AREG=0;
defparam \un1_x_4[15:2] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_4[15:2] .A_INPUT="DIRECT";
defparam \un1_x_4[15:2] .BCASCREG=1;
defparam \un1_x_4[15:2] .BREG=1;
defparam \un1_x_4[15:2] .B_INPUT="CASCADE";
defparam \un1_x_4[15:2] .CARRYINREG=0;
defparam \un1_x_4[15:2] .CARRYINSELREG=0;
defparam \un1_x_4[15:2] .CREG=1;
defparam \un1_x_4[15:2] .DREG=0;
defparam \un1_x_4[15:2] .INMODEREG=0;
defparam \un1_x_4[15:2] .MREG=0;
defparam \un1_x_4[15:2] .OPMODEREG=0;
defparam \un1_x_4[15:2] .PREG=1;
defparam \un1_x_4[15:2] .USE_DPORT="FALSE";
defparam \un1_x_4[15:2] .USE_MULT="MULTIPLY";
defparam \un1_x_4[15:2] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_7[15:2] (
.ACOUT(ACOUT_6[29:0]),
.BCOUT({x_5_10[7], x_5_9[7], x_5_8[7], x_5_7[7], x_5_6[7], x_5_5[7], x_5_4[7], x_5_3[7], x_5_2[7], x_5_1[7], x_5_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_6),
.CARRYOUT(CARRYOUT_6[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_6),
.OVERFLOW(OVERFLOW_6),
.P({P_uc_6[47:15], P_uc_5[14], un1_x_7_0[15:2]}),
.PATTERNBDETECT(PATTERNBDETECT_6),
.PATTERNDETECT(PATTERNDETECT_6),
.PCOUT(PCOUT_6[47:0]),
.UNDERFLOW(UNDERFLOW_6),
.A({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, VCC, VCC, GND, GND, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_4_10[7], x_4_9[7], x_4_8[7], x_4_7[7], x_4_6[7], x_4_5[7], x_4_4[7], x_4_3[7], x_4_2[7], x_4_1[7], x_4_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_7[15:2] .ACASCREG=0;
defparam \un1_x_7[15:2] .ADREG=0;
defparam \un1_x_7[15:2] .ALUMODEREG=0;
defparam \un1_x_7[15:2] .AREG=0;
defparam \un1_x_7[15:2] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_7[15:2] .A_INPUT="DIRECT";
defparam \un1_x_7[15:2] .BCASCREG=1;
defparam \un1_x_7[15:2] .BREG=1;
defparam \un1_x_7[15:2] .B_INPUT="CASCADE";
defparam \un1_x_7[15:2] .CARRYINREG=0;
defparam \un1_x_7[15:2] .CARRYINSELREG=0;
defparam \un1_x_7[15:2] .CREG=1;
defparam \un1_x_7[15:2] .DREG=0;
defparam \un1_x_7[15:2] .INMODEREG=0;
defparam \un1_x_7[15:2] .MREG=0;
defparam \un1_x_7[15:2] .OPMODEREG=0;
defparam \un1_x_7[15:2] .PREG=1;
defparam \un1_x_7[15:2] .USE_DPORT="FALSE";
defparam \un1_x_7[15:2] .USE_MULT="MULTIPLY";
defparam \un1_x_7[15:2] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_13[15:5] (
.ACOUT(ACOUT_7[29:0]),
.BCOUT({x_10_10[7], x_10_9[7], x_10_8[7], x_10_7[7], x_10_6[7], x_10_5[7], x_10_4[7], x_10_3[7], x_10_2[7], x_10_1[7], x_10_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_7),
.CARRYOUT(CARRYOUT_7[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_7),
.OVERFLOW(OVERFLOW_7),
.P({P_uc_7[47:15], P_uc_6[14], P_uc_4[13:12], P_uc[11], un1_x_13_0_0[15:5]}),
.PATTERNBDETECT(PATTERNBDETECT_7),
.PATTERNDETECT(PATTERNDETECT_7),
.PCOUT(PCOUT_7[47:0]),
.UNDERFLOW(UNDERFLOW_7),
.A({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, GND, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_9_10[7], x_9_9[7], x_9_8[7], x_9_7[7], x_9_6[7], x_9_5[7], x_9_4[7], x_9_3[7], x_9_2[7], x_9_1[7], x_9_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_13[15:5] .ACASCREG=0;
defparam \un1_x_13[15:5] .ADREG=0;
defparam \un1_x_13[15:5] .ALUMODEREG=0;
defparam \un1_x_13[15:5] .AREG=0;
defparam \un1_x_13[15:5] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_13[15:5] .A_INPUT="DIRECT";
defparam \un1_x_13[15:5] .BCASCREG=1;
defparam \un1_x_13[15:5] .BREG=1;
defparam \un1_x_13[15:5] .B_INPUT="CASCADE";
defparam \un1_x_13[15:5] .CARRYINREG=0;
defparam \un1_x_13[15:5] .CARRYINSELREG=0;
defparam \un1_x_13[15:5] .CREG=1;
defparam \un1_x_13[15:5] .DREG=0;
defparam \un1_x_13[15:5] .INMODEREG=0;
defparam \un1_x_13[15:5] .MREG=0;
defparam \un1_x_13[15:5] .OPMODEREG=0;
defparam \un1_x_13[15:5] .PREG=1;
defparam \un1_x_13[15:5] .USE_DPORT="FALSE";
defparam \un1_x_13[15:5] .USE_MULT="MULTIPLY";
defparam \un1_x_13[15:5] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_2[15:5] (
.ACOUT(ACOUT_8[29:0]),
.BCOUT({x_1_10[7], x_1_9[7], x_1_8[7], x_1_7[7], x_1_6[7], x_1_5[7], x_1_4[7], x_1_3[7], x_1_2[7], x_1_1[7], x_1_0[7:0]}),
.CARRYCASCOUT(CARRYCASCOUT_8),
.CARRYOUT(CARRYOUT_8[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_8),
.OVERFLOW(OVERFLOW_8),
.P({P_uc_8[47:15], P_uc_7[14], P_uc_5[13:12], P_uc_0[11], un1_x_2[15:5]}),
.PATTERNBDETECT(PATTERNBDETECT_8),
.PATTERNDETECT(PATTERNDETECT_8),
.PCOUT(PCOUT_8[47:0]),
.UNDERFLOW(UNDERFLOW_8),
.A({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, GND, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_0_10[7], x_0_9[7], x_0_8[7], x_0_7[7], x_0_6[7], x_0_5[7], x_0_4[7], x_0_3[7], x_0_2[7], x_0_1[7], x_0_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_2[15:5] .ACASCREG=0;
defparam \un1_x_2[15:5] .ADREG=0;
defparam \un1_x_2[15:5] .ALUMODEREG=0;
defparam \un1_x_2[15:5] .AREG=0;
defparam \un1_x_2[15:5] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_2[15:5] .A_INPUT="DIRECT";
defparam \un1_x_2[15:5] .BCASCREG=1;
defparam \un1_x_2[15:5] .BREG=1;
defparam \un1_x_2[15:5] .B_INPUT="CASCADE";
defparam \un1_x_2[15:5] .CARRYINREG=0;
defparam \un1_x_2[15:5] .CARRYINSELREG=0;
defparam \un1_x_2[15:5] .CREG=1;
defparam \un1_x_2[15:5] .DREG=0;
defparam \un1_x_2[15:5] .INMODEREG=0;
defparam \un1_x_2[15:5] .MREG=0;
defparam \un1_x_2[15:5] .OPMODEREG=0;
defparam \un1_x_2[15:5] .PREG=1;
defparam \un1_x_2[15:5] .USE_DPORT="FALSE";
defparam \un1_x_2[15:5] .USE_MULT="MULTIPLY";
defparam \un1_x_2[15:5] .USE_SIMD="ONE48";
// @8:30
DSP48E1 \un1_x_9[15:5] (
.ACOUT(ACOUT_9[29:0]),
.BCOUT(BCOUT_9[17:0]),
.CARRYCASCOUT(CARRYCASCOUT_9),
.CARRYOUT(CARRYOUT_9[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_9),
.OVERFLOW(OVERFLOW_9),
.P({P_uc_9[47:15], P_uc_8[14], P_uc_6[13:12], P_uc_1[11], un1_x_9_0[15:5]}),
.PATTERNBDETECT(PATTERNBDETECT_9),
.PATTERNDETECT(PATTERNDETECT_9),
.PCOUT(PCOUT_9[47:0]),
.UNDERFLOW(UNDERFLOW_9),
.A({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, GND, VCC}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.BCIN({x_6_10[7], x_6_9[7], x_6_8[7], x_6_7[7], x_6_6[7], x_6_5[7], x_6_4[7], x_6_3[7], x_6_2[7], x_6_1[7], x_6_0[7:0]}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(VCC),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(GND),
.CEM(GND),
.CEP(VCC),
.CLK(clk),
.D({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.INMODE({GND, GND, GND, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un1_x_9[15:5] .ACASCREG=0;
defparam \un1_x_9[15:5] .ADREG=0;
defparam \un1_x_9[15:5] .ALUMODEREG=0;
defparam \un1_x_9[15:5] .AREG=0;
defparam \un1_x_9[15:5] .AUTORESET_PATDET="NO_RESET";
defparam \un1_x_9[15:5] .A_INPUT="DIRECT";
defparam \un1_x_9[15:5] .BCASCREG=1;
defparam \un1_x_9[15:5] .BREG=1;
defparam \un1_x_9[15:5] .B_INPUT="CASCADE";
defparam \un1_x_9[15:5] .CARRYINREG=0;
defparam \un1_x_9[15:5] .CARRYINSELREG=0;
defparam \un1_x_9[15:5] .CREG=1;
defparam \un1_x_9[15:5] .DREG=0;
defparam \un1_x_9[15:5] .INMODEREG=0;
defparam \un1_x_9[15:5] .MREG=0;
defparam \un1_x_9[15:5] .OPMODEREG=0;
defparam \un1_x_9[15:5] .PREG=1;
defparam \un1_x_9[15:5] .USE_DPORT="FALSE";
defparam \un1_x_9[15:5] .USE_MULT="MULTIPLY";
defparam \un1_x_9[15:5] .USE_SIMD="ONE48";
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6 (
.I0(un1_x_12_0_0[5]),
.I1(un1_x_13_0_0[6]),
.I2(un1_x_14_0_0[5]),
.O(un84_sop_0_0_0_11_6_0_axb_1)
);
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6.INIT=8'h96;
// @8:30
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5 (
.I0(un1_x_12_0_0[5]),
.I1(un1_x_13_0_0[6]),
.I2(un1_x_14_0_0[5]),
.O(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5)
);
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6 (
.I0(un1_x_7_0[3]),
.I1(un1_x_8_0[5]),
.I2(un1_x_9_0[6]),
.O(un84_sop_0_0_0_6_6_0_axb_1)
);
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6.INIT=8'h96;
// @8:30
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5 (
.I0(un1_x_7_0[3]),
.I1(un1_x_8_0[5]),
.I2(un1_x_9_0[6]),
.O(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5)
);
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6 (
.I0(un84_sop_0_0_0_10_0[5]),
.I1(x_4[0]),
.I2(x_4[2]),
.O(un84_sop_0_0_0_1_6_8_axb_2)
);
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6.INIT=8'h96;
// @8:30
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5 (
.I0(un84_sop_0_0_0_10_0[5]),
.I1(x_4[0]),
.I2(x_4[2]),
.O(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5)
);
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5.INIT=8'hE8;
// @8:30
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o6 (
.I0(un1_x_1[5]),
.I1(un1_x_2[6]),
.I2(un1_x_3[5]),
.O(un84_sop_1_6_0_axb_1)
);
defparam un84_sop_1_6_0_axb_1_lut6_2_o6.INIT=8'h96;
// @8:30
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o5 (
.I0(un1_x_1[5]),
.I1(un1_x_2[6]),
.I2(un1_x_3[5]),
.O(un84_sop_1_6_0_axb_1_lut6_2_O5)
);
defparam un84_sop_1_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
endmodule /* fir */
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG
`define TEST_PROG "firmware.hex"
`include "top.v"
module top_test;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #8 uart_clk = !uart_clk; //For sim. UART TX clock gets divided by 4
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_in_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU input control logic.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_in_ctl (
pcx_fpio_data_rdy_px2,
pcx_fpio_data_px2,
fp_op_in,
fp_op_in_7in,
a1stg_step,
m1stg_step,
d1stg_step,
add_pipe_active,
mul_pipe_active,
div_pipe_active,
sehold,
arst_l,
grst_l,
rclk,
fp_data_rdy,
fadd_clken_l,
fmul_clken_l,
fdiv_clken_l,
inq_we,
inq_wraddr,
inq_read_en,
inq_rdaddr,
inq_bp,
inq_bp_inv,
inq_fwrd,
inq_fwrd_inv,
inq_add,
inq_mul,
inq_div,
se,
si,
so
);
input pcx_fpio_data_rdy_px2; // FPU request ready from PCX
input [123:118] pcx_fpio_data_px2; // FPU request data from PCX
input [3:2] fp_op_in; // request opcode
input fp_op_in_7in; // request opcode
input a1stg_step; // add pipe load
input m1stg_step; // multiply pipe load
input d1stg_step; // divide pipe load
input add_pipe_active; // add pipe is executing a valid instr
input mul_pipe_active; // mul pipe is executing a valid instr
input div_pipe_active; // div pipe is executing a valid instr
input sehold; // hold sram output MUX (for inq_data[155:0] in fpu_in_dp) for macrotest
input arst_l; // global asynchronous reset- asserted low
input grst_l; // global synchronous reset- asserted low
input rclk; // global clock
output fp_data_rdy;
output fadd_clken_l; // add pipe clk enable - asserted low
output fmul_clken_l; // multiply pipe clk enable - asserted low
output fdiv_clken_l; // divide pipe clk enable - asserted low
output inq_we; // input Q write enable
output [3:0] inq_wraddr; // input Q write address
output inq_read_en; // input Q read enable
output [3:0] inq_rdaddr; // input Q read address
output inq_bp; // bypass the input Q SRAM
output inq_bp_inv; // don't bypass the input Q SRAM
output inq_fwrd; // input Q is empty
output inq_fwrd_inv; // input Q is not empty
output inq_add; // add pipe request
output inq_mul; // multiply pipe request
output inq_div; // divide pipe request
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire fp_data_rdy;
wire fp_vld_in;
wire [4:0] fp_type_in;
wire fadd_clken_l;
wire fmul_clken_l;
wire fdiv_clken_l;
wire fp_op_in_7;
wire fp_op_in_7_inv;
wire inq_we;
wire inq_read_en;
wire [3:0] inq_wrptr_plus1;
wire inq_wrptr_step;
wire [3:0] inq_wrptr;
wire [3:0] inq_div_wrptr_plus1;
wire inq_div_wrptr_step;
wire [3:0] inq_div_wrptr;
wire [3:0] inq_wraddr;
wire [3:0] inq_wraddr_del;
wire inq_re;
wire [3:0] inq_rdptr_plus1;
wire [3:0] inq_rdptr_in;
wire [3:0] inq_rdptr;
wire inq_div_re;
wire [3:0] inq_div_rdptr_plus1;
wire [3:0] inq_div_rdptr_in;
wire [3:0] inq_div_rdptr;
wire inq_div_rd_in;
wire inq_div_rd;
wire [3:0] inq_rdaddr;
wire [3:0] inq_rdaddr_del;
wire inq_bp;
wire inq_bp_inv;
wire inq_empty;
wire inq_div_empty;
wire inq_fwrd;
wire inq_fwrd_inv;
wire fp_add_in;
wire fp_mul_in;
wire fp_div_in;
wire [7:0] inq_rdptr_dec_in;
wire [7:0] inq_rdptr_dec;
wire [7:0] inq_div_rdptr_dec_in;
wire [7:0] inq_div_rdptr_dec;
wire [15:0] inq_rdaddr_del_dec_in;
wire [15:0] inq_rdaddr_del_dec;
wire inq_pipe0_we;
wire inq_pipe1_we;
wire inq_pipe2_we;
wire inq_pipe3_we;
wire inq_pipe4_we;
wire inq_pipe5_we;
wire inq_pipe6_we;
wire inq_pipe7_we;
wire inq_pipe8_we;
wire inq_pipe9_we;
wire inq_pipe10_we;
wire inq_pipe11_we;
wire inq_pipe12_we;
wire inq_pipe13_we;
wire inq_pipe14_we;
wire inq_pipe15_we;
wire [2:0] inq_pipe0;
wire [2:0] inq_pipe1;
wire [2:0] inq_pipe2;
wire [2:0] inq_pipe3;
wire [2:0] inq_pipe4;
wire [2:0] inq_pipe5;
wire [2:0] inq_pipe6;
wire [2:0] inq_pipe7;
wire [2:0] inq_pipe8;
wire [2:0] inq_pipe9;
wire [2:0] inq_pipe10;
wire [2:0] inq_pipe11;
wire [2:0] inq_pipe12;
wire [2:0] inq_pipe13;
wire [2:0] inq_pipe14;
wire [2:0] inq_pipe15;
wire [2:0] inq_pipe;
wire inq_div;
wire inq_diva;
wire inq_diva_dly;
wire d1stg_step_dly;
wire inq_mul;
wire inq_mula;
wire inq_add;
wire inq_adda;
wire valid_packet;
wire valid_packet_dly;
wire tag_sel;
wire sehold_inv;
dffrl_async #(1) dffrl_in_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (in_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!in_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Capture request and input control information.
//
///////////////////////////////////////////////////////////////////////////////
dffr_s #(1) i_fp_data_rdy (
.din (pcx_fpio_data_rdy_px2),
.rst (reset),
.clk (rclk),
.q (fp_data_rdy),
.se (se),
.si (),
.so ()
);
dff_s #(1) i_fp_vld_in (
.din (pcx_fpio_data_px2[123]),
.clk (rclk),
.q (fp_vld_in),
.se (se),
.si (),
.so ()
);
dff_s #(5) i_fp_type_in (
.din (pcx_fpio_data_px2[122:118]),
.clk (rclk),
.q (fp_type_in[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- extract the two operands.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_op_in_7= fp_op_in_7in;
assign fp_op_in_7_inv= (!fp_op_in_7);
///////////////////////////////////////////////////////////////////////////////
//
// Input queue control logic
// - write enables
// - write pointers
// - read enables
// - read pointers
// - write address
// - read address
//
///////////////////////////////////////////////////////////////////////////////
assign inq_we= fp_data_rdy && fp_vld_in
&& (((fp_type_in[4:0]==5'h0a) && fp_op_in_7)
|| ((fp_type_in[4:0]==5'h0b) && fp_op_in_7_inv));
assign inq_wrptr_plus1[3:0]= inq_wrptr[3:0] + 4'h1;
assign inq_wrptr_step= inq_we && (!fp_div_in);
dffre_s #(4) i_inq_wrptr (
.din (inq_wrptr_plus1[3:0]),
.en (inq_wrptr_step),
.rst (reset),
.clk (rclk),
.q (inq_wrptr[3:0]),
.se (se),
.si (),
.so ()
);
assign inq_div_wrptr_plus1[3:0]= inq_div_wrptr[3:0] + 4'h1;
assign inq_div_wrptr_step= inq_we && fp_div_in;
dffre_s #(4) i_inq_div_wrptr (
.din (inq_div_wrptr_plus1[3:0]),
.en (inq_div_wrptr_step),
.rst (reset),
.clk (rclk),
.q (inq_div_wrptr[3:0]),
.se (se),
.si (),
.so ()
);
assign inq_wraddr[3:0]= {fp_div_in,
(({3{fp_div_in}}
& inq_div_wrptr[2:0])
| ({3{(!fp_div_in)}}
& inq_wrptr[2:0]))};
dff_s #(4) i_inq_wraddr_del (
.din (inq_wraddr[3:0]),
.clk (rclk),
.q (inq_wraddr_del[3:0]),
.se (se),
.si (),
.so ()
);
assign inq_read_en = ~inq_empty | ~inq_div_empty;
assign inq_re= (inq_adda && a1stg_step)
|| (inq_mula && m1stg_step);
assign inq_rdptr_plus1[3:0]= inq_rdptr[3:0] + 4'h1;
assign inq_rdptr_in[3:0]= ({4{(inq_re && (!reset))}}
& inq_rdptr_plus1[3:0])
| ({4{((!inq_re) && (!reset))}}
& inq_rdptr[3:0]);
dff_s #(4) i_inq_rdptr (
.din (inq_rdptr_in[3:0]),
.clk (rclk),
.q (inq_rdptr[3:0]),
.se (se),
.si (),
.so ()
);
assign inq_div_re= (inq_diva && d1stg_step);
assign inq_div_rdptr_plus1[3:0]= inq_div_rdptr[3:0] + 4'h1;
assign inq_div_rdptr_in[3:0]= ({4{(inq_div_re && (!reset))}}
& inq_div_rdptr_plus1[3:0])
| ({4{((!inq_div_re) && (!reset))}}
& inq_div_rdptr[3:0]);
dff_s #(4) i_inq_div_rdptr (
.din (inq_div_rdptr_in[3:0]),
.clk (rclk),
.q (inq_div_rdptr[3:0]),
.se (se),
.si (),
.so ()
);
assign inq_div_rd_in= (!inq_div_empty) && d1stg_step && (!inq_diva);
dff_s #(1) i_inq_div_rd (
.din (inq_div_rd_in),
.clk (rclk),
.q (inq_div_rd),
.se (se),
.si (),
.so ()
);
assign inq_rdaddr[3:0]= {inq_div_rd_in,
(({3{inq_div_rd_in}}
& (inq_div_rdptr[2:0] & {3{(!reset)}}))
| ({3{(!inq_div_rd_in)}}
& inq_rdptr_in[2:0]))};
dff_s #(4) i_inq_rdaddr_del (
.din (inq_rdaddr[3:0]),
.clk (rclk),
.q (inq_rdaddr_del[3:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Input queue empty and bypass signals.
//
///////////////////////////////////////////////////////////////////////////////
// Power management update
assign valid_packet = fp_data_rdy && fp_vld_in &&
((fp_type_in[4:0]==5'h0a) || (fp_type_in[4:0]==5'h0b));
dffre_s #(1) i_valid_packet_dly (
.din (valid_packet),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (valid_packet_dly),
.se (se),
.si (),
.so ()
);
// Never bypass/forward invalid packets to the execution pipes
// assign inq_bp= (inq_wraddr_del[3:0]==inq_rdaddr_del[3:0]);
// 11/11/03: macrotest (AND with sehold_inv)
assign sehold_inv = ~sehold;
assign inq_bp= (inq_wraddr_del[3:0]==inq_rdaddr_del[3:0]) && valid_packet_dly && sehold_inv;
assign inq_bp_inv= (!inq_bp);
assign inq_empty= (inq_wrptr[3:0]==inq_rdptr[3:0]);
assign inq_div_empty= (inq_div_wrptr[3:0]==inq_div_rdptr[3:0]);
// Power management update
// Never bypass/forward invalid packets to the execution pipes
// assign inq_fwrd= (inq_empty && (!inq_div_rd))
// || (inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
// && d1stg_step);
// 11/11/03: macrotest change (AND with sehold_inv)
assign inq_fwrd= ((inq_empty && (!inq_div_rd))
|| (inq_div_empty && fp_div_in
&& d1stg_step)) && valid_packet && sehold_inv;
assign inq_fwrd_inv= (!inq_fwrd);
///////////////////////////////////////////////////////////////////////////////
//
// FPU pipe selection flags.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_add_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:1]==4'h5)
&& ((fp_op_in_7 && (!fp_type_in[0]))
|| (fp_op_in_7_inv && (!fp_op_in[3]) && fp_type_in[0]));
assign fp_mul_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:0]==5'h0b)
&& fp_op_in_7_inv && (fp_op_in[3:2]==2'b10);
assign fp_div_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:0]==5'h0b)
&& fp_op_in_7_inv && (fp_op_in[3:2]==2'b11);
assign inq_rdptr_dec_in[7:0]= ({8{reset}}
& 8'h01)
| ({8{(inq_re && (!reset))}}
& {inq_rdptr_dec[6:0], inq_rdptr_dec[7]})
| ({8{((!inq_re) && (!reset))}}
& inq_rdptr_dec[7:0]);
dff_s #(8) i_inq_rdptr_dec (
.din (inq_rdptr_dec_in[7:0]),
.clk (rclk),
.q (inq_rdptr_dec[7:0]),
.se (se),
.si (),
.so ()
);
assign inq_div_rdptr_dec_in[7:0]= ({8{reset}}
& 8'h01)
| ({8{(inq_div_re && (!reset))}}
& {inq_div_rdptr_dec[6:0], inq_div_rdptr_dec[7]})
| ({8{((!inq_div_re) && (!reset))}}
& inq_div_rdptr_dec[7:0]);
dff_s #(8) i_inq_div_rdptr_dec (
.din (inq_div_rdptr_dec_in[7:0]),
.clk (rclk),
.q (inq_div_rdptr_dec[7:0]),
.se (se),
.si (),
.so ()
);
assign inq_rdaddr_del_dec_in[15:0]= ({16{((!inq_div_empty) && d1stg_step
&& (!inq_diva))}}
& {(inq_div_rdptr_dec[7:1] & {7{(!reset)}}),
(inq_div_rdptr_dec[0] || reset), 8'b0})
| ({16{(!((!inq_div_empty) && d1stg_step && (!inq_diva)))}}
& {8'b0, inq_rdptr_dec_in[7:0]});
dff_s #16 i_inq_rdaddr_del_dec (
.din (inq_rdaddr_del_dec_in[15:0]),
.clk (rclk),
.q (inq_rdaddr_del_dec[15:0]),
.se (se),
.si (),
.so ()
);
assign inq_pipe0_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h0);
assign inq_pipe1_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h1);
assign inq_pipe2_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h2);
assign inq_pipe3_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h3);
assign inq_pipe4_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h4);
assign inq_pipe5_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h5);
assign inq_pipe6_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h6);
assign inq_pipe7_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h7);
assign inq_pipe8_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h0);
assign inq_pipe9_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h1);
assign inq_pipe10_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h2);
assign inq_pipe11_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h3);
assign inq_pipe12_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h4);
assign inq_pipe13_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h5);
assign inq_pipe14_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h6);
assign inq_pipe15_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h7);
dffre_s #(3) i_inq_pipe0 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe0_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe0[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe1 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe1_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe1[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe2 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe2_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe2[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe3 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe3_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe3[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe4 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe4_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe4[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe5 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe5_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe5[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe6 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe6_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe6[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe7 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe7_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe7[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe8 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe8_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe8[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe9 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe9_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe9[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe10 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe10_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe10[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe11 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe11_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe11[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe12 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe12_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe12[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe13 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe13_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe13[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe14 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe14_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe14[2:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(3) i_inq_pipe15 (
.din ({fp_div_in, fp_mul_in, fp_add_in}),
.en (inq_pipe15_we),
.rst (reset),
.clk (rclk),
.q (inq_pipe15[2:0]),
.se (se),
.si (),
.so ()
);
// Power management update
// 3-bit fifo pipe tags (div,mul,add) are not cleared after use.
// Now that inq_fwrd is qualified by valid_packet, inq_fwrd can't be
// used for inq_pipe[2:0] selection.
assign tag_sel = (inq_empty && (!inq_div_rd))
|| (inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
&& d1stg_step);
assign inq_pipe[2:0]= ({3{tag_sel}}
// Austin update
// performance change: allow div to bypass FIFO (2 cyc latency reduction)
& {(inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
&& d1stg_step
&& d1stg_step_dly && (!inq_diva_dly)),
fp_mul_in,
fp_add_in})
| ({3{(!tag_sel)}}
& (({3{inq_rdaddr_del_dec[0]}}
& inq_pipe0[2:0])
| ({3{inq_rdaddr_del_dec[1]}}
& inq_pipe1[2:0])
| ({3{inq_rdaddr_del_dec[2]}}
& inq_pipe2[2:0])
| ({3{inq_rdaddr_del_dec[3]}}
& inq_pipe3[2:0])
| ({3{inq_rdaddr_del_dec[4]}}
& inq_pipe4[2:0])
| ({3{inq_rdaddr_del_dec[5]}}
& inq_pipe5[2:0])
| ({3{inq_rdaddr_del_dec[6]}}
& inq_pipe6[2:0])
| ({3{inq_rdaddr_del_dec[7]}}
& inq_pipe7[2:0])
| ({3{inq_rdaddr_del_dec[8]}}
& inq_pipe8[2:0])
| ({3{inq_rdaddr_del_dec[9]}}
& inq_pipe9[2:0])
| ({3{inq_rdaddr_del_dec[10]}}
& inq_pipe10[2:0])
| ({3{inq_rdaddr_del_dec[11]}}
& inq_pipe11[2:0])
| ({3{inq_rdaddr_del_dec[12]}}
& inq_pipe12[2:0])
| ({3{inq_rdaddr_del_dec[13]}}
& inq_pipe13[2:0])
| ({3{inq_rdaddr_del_dec[14]}}
& inq_pipe14[2:0])
| ({3{inq_rdaddr_del_dec[15]}}
& inq_pipe15[2:0])));
assign inq_div= inq_pipe[2];
assign inq_diva= inq_pipe[2];
assign inq_mul= inq_pipe[1];
assign inq_mula= inq_pipe[1];
assign inq_add= inq_pipe[0];
assign inq_adda= inq_pipe[0];
// Power management update
// Gate the clocks on a per pipe basis (add, mul, div independently)
// when a given pipe is not in use
dffre_s #(1) i_inq_adda_dly (
.din (inq_adda),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (inq_adda_dly),
.se (se),
.si (),
.so ()
);
dffre_s #(1) i_inq_mula_dly (
.din (inq_mula),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (inq_mula_dly),
.se (se),
.si (),
.so ()
);
dffre_s #(1) i_inq_diva_dly (
.din (inq_diva),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (inq_diva_dly),
.se (se),
.si (),
.so ()
);
dffre_s #(1) i_d1stg_step_dly (
.din (d1stg_step),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (d1stg_step_dly),
.se (se),
.si (),
.so ()
);
assign fadd_clken_l = !(add_pipe_active || inq_adda || inq_adda_dly || reset);
assign fmul_clken_l = !(mul_pipe_active || inq_mula || inq_mula_dly || reset);
assign fdiv_clken_l = !(div_pipe_active || inq_diva || inq_diva_dly || reset);
endmodule
|
/*
* Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters
* to contol the single interface.
*/
module xilinx_ddr2
(
// Inputs
input [31:0] wbm0_adr_i,
input [1:0] wbm0_bte_i,
input [2:0] wbm0_cti_i,
input wbm0_cyc_i,
input [31:0] wbm0_dat_i,
input [3:0] wbm0_sel_i,
input wbm0_stb_i,
input wbm0_we_i,
// Outputs
output wbm0_ack_o,
output wbm0_err_o,
output wbm0_rty_o,
output [31:0] wbm0_dat_o,
// Inputs
input [31:0] wbm1_adr_i,
input [1:0] wbm1_bte_i,
input [2:0] wbm1_cti_i,
input wbm1_cyc_i,
input [31:0] wbm1_dat_i,
input [3:0] wbm1_sel_i,
input wbm1_stb_i,
input wbm1_we_i,
// Outputs
output wbm1_ack_o,
output wbm1_err_o,
output wbm1_rty_o,
output [31:0] wbm1_dat_o,
// Inputs
input [31:0] wbm2_adr_i,
input [1:0] wbm2_bte_i,
input [2:0] wbm2_cti_i,
input wbm2_cyc_i,
input [31:0] wbm2_dat_i,
input [3:0] wbm2_sel_i,
input wbm2_stb_i,
input wbm2_we_i,
// Outputs
output wbm2_ack_o,
output wbm2_err_o,
output wbm2_rty_o,
output [31:0] wbm2_dat_o,
input wb_clk,
input wb_rst,
output [12:0] ddr2_a,
output [1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [1:0] ddr2_cs_n,
output [1:0] ddr2_odt,
output [1:0] ddr2_cke,
output [7:0] ddr2_dm,
inout [63:0] ddr2_dq,
inout [7:0] ddr2_dqs,
inout [7:0] ddr2_dqs_n,
output [1:0] ddr2_ck,
output [1:0] ddr2_ck_n,
input ddr2_if_clk,
input clk200,
input ddr2_if_rst
);
// Internal wires to actual RAM
wire [31:0] wbs_ram_adr_i;
wire [1:0] wbs_ram_bte_i;
wire [2:0] wbs_ram_cti_i;
wire wbs_ram_cyc_i;
wire [31:0] wbs_ram_dat_i;
wire [3:0] wbs_ram_sel_i;
wire wbs_ram_stb_i;
wire wbs_ram_we_i;
wire wbs_ram_ack_o;
wire [31:0] wbs_ram_dat_o;
reg [2:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
// Wires allowing selection of new input
assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
// Master select logic
always @(posedge wb_clk)
if (wb_rst)
input_select <= 0;
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
| (input_select[2] & !wbm2_cyc_i))
input_select <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
input_select <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
input_select <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
input_select <= 3'b100;
always @(posedge wb_clk)
if (wb_rst)
last_selected <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
last_selected <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
last_selected <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
last_selected <= 3'b100;
// Mux input signals to RAM (default to wbm0)
assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
(input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
(input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
(input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
(input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
(input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
(input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
(input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
(input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbm0_dat_o = wbs_ram_dat_o;
assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
assign wbm0_err_o = 0;
assign wbm0_rty_o = 0;
assign wbm1_dat_o = wbs_ram_dat_o;
assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
assign wbm1_err_o = 0;
assign wbm1_rty_o = 0;
assign wbm2_dat_o = wbs_ram_dat_o;
assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
assign wbm2_err_o = 0;
assign wbm2_rty_o = 0;
xilinx_ddr2_if xilinx_ddr2_if0
(
.wb_dat_o (wbs_ram_dat_o),
.wb_ack_o (wbs_ram_ack_o),
.wb_adr_i (wbs_ram_adr_i[31:0]),
.wb_stb_i (wbs_ram_stb_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_we_i (wbs_ram_we_i),
.wb_sel_i (wbs_ram_sel_i[3:0]),
.wb_dat_i (wbs_ram_dat_i[31:0]),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ddr2_ba[1:0]),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm[7:0]),
.ddr2_ck (ddr2_ck[1:0]),
.ddr2_ck_n (ddr2_ck_n[1:0]),
.ddr2_dq (ddr2_dq[63:0]),
.ddr2_dqs (ddr2_dqs[7:0]),
.ddr2_dqs_n (ddr2_dqs_n[7:0]),
.ddr2_if_clk (ddr2_if_clk),
.idly_clk_200 (clk200),
.ddr2_if_rst (ddr2_if_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst));
endmodule
|
//==================================================================================================
// Filename : musb_alu.v
// Created On : 2014-09-23 20:09:00
// Last Modified : 2015-05-24 21:00:31
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : The Execution unit.
// Performs the following operations:
// - Arithmetic
// - Logical
// - Shift
// - Comparison
//==================================================================================================
`include "musb_defines.v"
module musb_alu#(
parameter ENABLE_HW_MULT = 1, // Implement the multiplier
parameter ENABLE_HW_DIV = 1, // Implement the divider
parameter ENABLE_HW_CLO_Z = 1 // Implement the CLO/CLZ
)(
input clk, // clock
input rst, // reset
input [31:0] ex_alu_port_a, // Operand
input [31:0] ex_alu_port_b, // Operand
input [4:0] ex_alu_operation, // ALU operation
input ex_stall, // stall the execution stage
input ex_flush, // flush the execution stage
output ex_request_stall, // Executing a Div/Mult instruction
output reg [31:0] ex_alu_result, // Result
output ex_b_is_zero, // for MOVN and MOVZ
output reg exc_overflow // Overflow
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [63:0] hilo; // hold the result from MULT instruction
reg div_active; // 1 if the divider is currently active.
reg hilo_access; // check access
reg [5:0] clo_result;
reg [5:0] clz_result;
///-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [31:0] A; // Port A (unsigned)
wire [31:0] B; // Port B (unsigned)
wire signed [31:0] As; // Port A (signed)
wire signed [61:0] Bs; // Port B (signed)
wire signed [31:0] add_sub_result; // A+B or A - B
wire [4:0] operation; // Operation
wire [63:0] multx_result; // Multiplication result
wire [31:0] hi; // HILO[63:32]
wire [31:0] lo; // HILO[31:0]
wire [31:0] shift_result; // Shift result
wire [31:0] quotient; // Division
wire [31:0] remainder; // Division
wire op_divs; // Signed division
wire op_divu; // Unsigned division
wire div_stall; // Stall
wire enable_ex; // Enable operations
wire op_mults; // Signed multiplication
wire op_multu; // Unsigned multiplication
wire mult_active; // Mult operation active inside the pipeline
wire mult_ready; // Mult result ready
wire mult_stall;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign A = ex_alu_port_a; // unsigned
assign B = ex_alu_port_b; // unsigned
assign As = $signed(ex_alu_port_a); // signed
assign Bs = $signed(ex_alu_port_b); // signed
assign operation = ex_alu_operation; // only to avoid renaming (e_e)
assign ex_b_is_zero = (B == 32'b0);
assign add_sub_result = ((operation == `ALU_OP_ADD) | (operation == `ALU_OP_ADDU)) ? (A + B) : (A - B);
assign hi = hilo[63:32];
assign lo = hilo[31:0];
// enable mult/div if no stall or flush.
assign enable_ex = ~(ex_stall | ex_flush);
// Do nothing if B == 0. A single pulse. Ignore if EX is stalled (MEM, exception or data dependency)
assign op_divs = (B != 32'd0) & (div_active == 1'b0) & (operation == `ALU_OP_DIV) & enable_ex;
assign op_divu = (B != 32'd0) & (div_active == 1'b0) & (operation == `ALU_OP_DIVU) & enable_ex;
// A single pulse. Ignore if EX is stalled (MEM, exception or data dependency)
assign op_mults = (mult_active == 1'b0) & (operation == `ALU_OP_MULS) & enable_ex;
assign op_multu = (mult_active == 1'b0) & (operation == `ALU_OP_MULU) & enable_ex;
// request stall if (divx or div active) or (multx | mult active)
assign ex_request_stall = ((op_divu | op_divs) | div_stall) | ((op_multu | op_mults) | (mult_active ^ mult_ready));
assign mult_stall = ex_stall;
//--------------------------------------------------------------------------
// the BIG multiplexer
//--------------------------------------------------------------------------
always @(*) begin
case(operation)
`ALU_OP_ADD : ex_alu_result <= add_sub_result;
`ALU_OP_ADDU : ex_alu_result <= add_sub_result;
`ALU_OP_SUB : ex_alu_result <= add_sub_result;
`ALU_OP_SUBU : ex_alu_result <= add_sub_result;
`ALU_OP_AND : ex_alu_result <= A & B;
`ALU_OP_CLO : ex_alu_result <= {26'b0, clo_result};
`ALU_OP_CLZ : ex_alu_result <= {26'b0, clz_result};
`ALU_OP_NOR : ex_alu_result <= ~(A | B);
`ALU_OP_OR : ex_alu_result <= A | B;
`ALU_OP_SLL : ex_alu_result <= shift_result;
`ALU_OP_SRA : ex_alu_result <= shift_result;
`ALU_OP_SRL : ex_alu_result <= shift_result;
`ALU_OP_XOR : ex_alu_result <= A ^ B;
`ALU_OP_MFHI : ex_alu_result <= hi;
`ALU_OP_MFLO : ex_alu_result <= lo;
`ALU_OP_SLT : ex_alu_result <= As < Bs;
`ALU_OP_SLTU : ex_alu_result <= A < B;
`ALU_OP_A : ex_alu_result <= A;
`ALU_OP_B : ex_alu_result <= B;
default : ex_alu_result <= 32'bx; // I don't BLOODY CARE.
endcase
end
//--------------------------------------------------------------------------
// Detect Overflow
//--------------------------------------------------------------------------
always @(*) begin
case (operation)
`ALU_OP_ADD : exc_overflow <= ((A[31] ~^ B[31]) & (A[31] ^ add_sub_result[31]));
`ALU_OP_SUB : exc_overflow <= ((A[31] ^ B[31]) & (A[31] ^ add_sub_result[31]));
default : exc_overflow <= 1'b0;
endcase
end
//--------------------------------------------------------------------------
// Write to HILO register
// Div has priority over mult
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
hilo <= 64'h00000000_00000000;
end
else if ((div_stall == 1'b0) & (div_active == 1'b1)) begin
hilo <= {remainder, quotient};
end
else if(enable_ex) begin
case (operation)
`ALU_OP_MULS : hilo <= multx_result;
`ALU_OP_MULU : hilo <= multx_result;
`ALU_OP_MADD : hilo <= hilo + multx_result;
`ALU_OP_MADDU : hilo <= hilo + multx_result;
`ALU_OP_MSUB : hilo <= hilo - multx_result;
`ALU_OP_MSUBU : hilo <= hilo - multx_result;
`ALU_OP_MTHI : hilo <= {A, lo};
`ALU_OP_MTLO : hilo <= {hi, A};
default : hilo <= hilo;
endcase
end
end
//--------------------------------------------------------------------------
// determinate if the div unit is currently active
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
div_active <= 1'b0;
end
else begin
case(div_active)
1'd0 : div_active <= (op_divs || op_divu) ? 1'b1 : 1'b0;
1'd1 : div_active <= (~div_stall) ? 1'b0 : 1'b1;
endcase
end
end
//--------------------------------------------------------------------------
// Detect access to HILO register
//--------------------------------------------------------------------------
always @(*) begin
case (operation)
`ALU_OP_DIV : hilo_access <= 1'b1;
`ALU_OP_DIVU : hilo_access <= 1'b1;
`ALU_OP_MULS : hilo_access <= 1'b1;
`ALU_OP_MULU : hilo_access <= 1'b1;
`ALU_OP_MADD : hilo_access <= 1'b1;
`ALU_OP_MADDU : hilo_access <= 1'b1;
`ALU_OP_MSUB : hilo_access <= 1'b1;
`ALU_OP_MSUBU : hilo_access <= 1'b1;
`ALU_OP_MTHI : hilo_access <= 1'b1;
`ALU_OP_MTLO : hilo_access <= 1'b1;
`ALU_OP_MFHI : hilo_access <= 1'b1;
`ALU_OP_MFLO : hilo_access <= 1'b1;
default : hilo_access <= 1'b0;
endcase
end
//--------------------------------------------------------------------------
// Count Leading Ones/Zeros
//--------------------------------------------------------------------------
generate
// Hardware CLO_CLZ
if (ENABLE_HW_CLO_Z) begin
//--------------------------------------------------------------------------
// Count Leading Ones
//--------------------------------------------------------------------------
always @(A) begin
casex (A)
32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd0;
32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd1;
32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd2;
32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd3;
32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd4;
32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd5;
32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd6;
32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd7;
32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd8;
32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd9;
32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd10;
32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd11;
32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd12;
32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd13;
32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd14;
32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : clo_result <= 6'd15;
32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : clo_result <= 6'd16;
32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : clo_result <= 6'd17;
32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : clo_result <= 6'd18;
32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : clo_result <= 6'd19;
32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : clo_result <= 6'd20;
32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : clo_result <= 6'd21;
32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : clo_result <= 6'd22;
32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : clo_result <= 6'd23;
32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : clo_result <= 6'd24;
32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : clo_result <= 6'd25;
32'b1111_1111_1111_1111_1111_1111_110x_xxxx : clo_result <= 6'd26;
32'b1111_1111_1111_1111_1111_1111_1110_xxxx : clo_result <= 6'd27;
32'b1111_1111_1111_1111_1111_1111_1111_0xxx : clo_result <= 6'd28;
32'b1111_1111_1111_1111_1111_1111_1111_10xx : clo_result <= 6'd29;
32'b1111_1111_1111_1111_1111_1111_1111_110x : clo_result <= 6'd30;
32'b1111_1111_1111_1111_1111_1111_1111_1110 : clo_result <= 6'd31;
32'b1111_1111_1111_1111_1111_1111_1111_1111 : clo_result <= 6'd32;
default : clo_result <= 6'd0;
endcase
end
//--------------------------------------------------------------------------
// Count Leading Zeros
//--------------------------------------------------------------------------
always @(A) begin
casex (A)
32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd0;
32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd1;
32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd2;
32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd3;
32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd4;
32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd5;
32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd6;
32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd7;
32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd8;
32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd9;
32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd10;
32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd11;
32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd12;
32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd13;
32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd14;
32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : clz_result <= 6'd15;
32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : clz_result <= 6'd16;
32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : clz_result <= 6'd17;
32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : clz_result <= 6'd18;
32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : clz_result <= 6'd19;
32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : clz_result <= 6'd20;
32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : clz_result <= 6'd21;
32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : clz_result <= 6'd22;
32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : clz_result <= 6'd23;
32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : clz_result <= 6'd24;
32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : clz_result <= 6'd25;
32'b0000_0000_0000_0000_0000_0000_001x_xxxx : clz_result <= 6'd26;
32'b0000_0000_0000_0000_0000_0000_0001_xxxx : clz_result <= 6'd27;
32'b0000_0000_0000_0000_0000_0000_0000_1xxx : clz_result <= 6'd28;
32'b0000_0000_0000_0000_0000_0000_0000_01xx : clz_result <= 6'd29;
32'b0000_0000_0000_0000_0000_0000_0000_001x : clz_result <= 6'd30;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : clz_result <= 6'd31;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : clz_result <= 6'd32;
default : clz_result <= 6'd0;
endcase
end
end
// Disable
else begin
always @(A) begin
clo_result <= 6'd0;
clz_result <= 6'b0;
end
end
endgenerate
//--------------------------------------------------------------------------
// Shifter: instantiation
//--------------------------------------------------------------------------
musb_shifter shifter(
.input_data ( B ),
.shamnt ( A[4:0] ),
.direction ( operation == `ALU_OP_SLL ),
.sign_extend ( operation == `ALU_OP_SRA ),
.shift_result ( shift_result[31:0] )
);
//--------------------------------------------------------------------------
// 32 x 32 bits multiplier: instantiation
//--------------------------------------------------------------------------
generate
// Hardware multiplier
if (ENABLE_HW_MULT) begin
musb_multiplier mult(
.clk ( clk ),
.rst ( rst ),
.input_a ( A[31:0] ),
.input_b ( B[31:0] ),
.signed_operation ( operation == `ALU_OP_MULS ),
.enable_op ( op_mults | op_multu ),
.stall ( mult_stall ),
.flush ( ex_flush ),
.mult_result ( multx_result[63:0] ),
.active ( mult_active ),
.ready ( mult_ready )
);
end
// No hardware multiplier
else begin
assign multx_result = 64'b0; // disabled
assign mult_active = 1'b0; // disabled
assign mult_ready = 1'b0; // disabled
end
endgenerate
//--------------------------------------------------------------------------
// instantiate the divider unit
//--------------------------------------------------------------------------
generate
// Hardware divider
if (ENABLE_HW_DIV) begin
musb_div Divider(
.clk ( clk ),
.rst ( rst ),
.op_divs ( op_divs ),
.op_divu ( op_divu ),
.dividend ( A[31:0] ),
.divisor ( B[31:0] ),
.quotient ( quotient[31:0] ),
.remainder ( remainder[31:0] ),
.stall ( div_stall )
);
end
// No hardware divider
else begin
assign quotient = 32'b0; // disabled
assign remainder = 32'b0; // disabled
assign div_stall = 1'b0; // disabled
end
endgenerate
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
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// (individually and collectively, "Critical
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=2,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ([email protected])
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: mem_ctrl.v (tranlate from mem_ctrl.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ([email protected])
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from mem_ctrl.vhd
// 2004/10/27 yfchen 1.2 minor coding style change
// 2004/10/29 yfchen 1.3 fix mem_byte_sel bug when read
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Memory Controller
// AUTHOR: Steve Rhoads ([email protected])
// DATE CREATED: 1/31/01
// FILENAME: mem_ctrl.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Memory controller for the Plasma CPU.
// Supports Big or Little Endian mode.
// Four cycles for a write unless a(31)='1' then two cycles.
// This entity could implement interfaces to:
// Data cache
// Address cache
// Memory management unit (MMU)
// DRAM controller
//-------------------------------------------------------------------
`include "yf32_define.v"
module mem_ctrl (clk, reset, pause_in, nullify_op, address_pc, opcode_out,
address_data, mem_source, data_write, data_read, pause_out,
mem_address, mem_data_w, mem_data_r, mem_byte_sel, mem_write);
parameter ACCURATE_TIMING = 1'b0;
parameter STATE_FETCH = 2'b00;
parameter STATE_ADDR = 2'b01;
parameter STATE_WRITE = 2'b10;
parameter STATE_PAUSE = 2'b11;
input clk;
input reset;
input pause_in;
input nullify_op;
input [31:0] address_pc;
input [31:0] address_data;
input [ 3:0] mem_source;
input [31:0] data_write;
input [31:0] mem_data_r;
output [31:0] opcode_out;
output [31:0] data_read;
output pause_out;
output [31:0] mem_address;
output [31:0] mem_data_w;
output [ 3:0] mem_byte_sel;
output mem_write;
wire [ 1:0] little_endian = `mem_byte_ordering;
reg [31:0] opcode_out;
reg [31:0] data_read;
reg pause_out;
reg [31:0] mem_address;
reg [31:0] mem_data_w;
reg [ 3:0] mem_byte_sel;
reg mem_write;
reg [31:0] opcode_reg;
reg [31:0] next_opcode_reg;
reg [ 1:0] mem_state_reg;
//ACCURATE_TIMING notes:
//The VHDL compiler's timing calculation isn't able to realize that
//memory reads take two clock cycles. It notices that reg_bank:reg_dest
//is dependent on mem_ctrl:mem_data_r which is dependent on
//mem_ctrl:mem_address which is dependent on alu:c_alu. However,
//this dependency is only true for memory read or write cycles
//which are multiple clock cycles. Enabling ACCURATE_TIMING
//creates an additional 32-bit register that does nothing other
//than letting the VHDL compiler accurately predict the maximum
//clock speed.
reg [31:0] address_reg;
reg write_reg;
reg [ 3:0] byte_sel_reg;
reg [ 1:0] mem_state_next_sig;
reg [31:0] opcode_next_sig;
reg write_next_sig;
reg [ 3:0] byte_sel_next_sig;
reg [31:0] data;
reg [31:0] opcode_next;
reg [ 3:0] byte_sel_next;
reg [ 3:0] byte_sel;
reg write_next;
reg write_line;
reg [ 1:0] mem_state_next;
reg pause;
reg [31:0] address;
reg [ 1:0] bits;
reg [31:0] mem_data_w_v;
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_state_reg <= STATE_FETCH ;
opcode_reg <= `ZERO ;
next_opcode_reg <= `ZERO ;
end else begin
mem_state_reg <= mem_state_next_sig ;
opcode_reg <= opcode_next_sig ;
if (mem_state_reg == STATE_FETCH)
next_opcode_reg <= mem_data_r ;
end
end
`ifdef ACCURATE_TIMING
always @(posedge clk or posedge reset)
begin
if (reset) begin
address_reg <= 0;
write_reg <= 0;
byte_sel_reg <= 0;
else begin
address_reg <= address_data ;
write_reg <= write_next_sig ;
byte_sel_reg <= byte_sel_next_sig ;
end
end
`else
always @(address_data or write_next_sig or byte_sel_next_sig)
begin
address_reg = address_data ;
write_reg = write_next_sig ;
byte_sel_reg = byte_sel_next_sig ;
end
`endif
always @(reset or pause_in or nullify_op or address_pc or address_data or
mem_source or data_write or mem_data_r or opcode_reg or
next_opcode_reg or mem_state_reg or address_reg or write_reg or
byte_sel_reg or little_endian)
begin
byte_sel_next = 4'b0000;
write_next = 1'b0;
pause = 1'b0;
mem_state_next = mem_state_reg;
data = `ZERO;
mem_data_w_v = `ZERO;
case (mem_source) // synopsys parallel_case
`mem_read32 :
begin
data = mem_data_r;
byte_sel_next = 4'b1111; // yfchen modified
end
`mem_read16, `mem_read16s :
begin
if (address_reg[1] == little_endian[1]) begin
data[15:0] = mem_data_r[31:16];
byte_sel_next = 4'b1100; // yfchen modified
end else begin
data[15:0] = mem_data_r[15:0];
byte_sel_next = 4'b0011; // yfchen modified
end
if (mem_source == `mem_read16 | ~data[15]) begin
data[31:16] = 16'h0000; //`ZERO[31:16];
end else begin
data[31:16] = 16'hFFFF; //`ONES[31:16];
end
end
`mem_read8, `mem_read8s :
begin
bits = address_reg[1:0] ^ little_endian;
case (bits) // synopsys parallel_case
2'b00 : data[7:0] = mem_data_r[31:24];
2'b01 : data[7:0] = mem_data_r[23:16];
2'b10 : data[7:0] = mem_data_r[15: 8];
default: data[7:0] = mem_data_r[ 7: 0];
endcase
if (mem_source == `mem_read8 | ~data[7]) begin
data[31:8] = 24'h000000; //`ZERO[31:8];
end else begin
data[31:8] = 24'hffffff; //`ONES[31:8];
end
case (bits) // yfchen modified
2'b00 : byte_sel_next = 4'b1000;
2'b01 : byte_sel_next = 4'b0100;
2'b10 : byte_sel_next = 4'b0010;
default : byte_sel_next = 4'b0001;
endcase
end
`mem_write32 :
begin
write_next = 1'b1;
mem_data_w_v = data_write;
byte_sel_next = 4'b1111;
end
`mem_write16 :
begin
write_next = 1'b1;
mem_data_w_v = {data_write[15:0], data_write[15:0]};
if (address_data[1] == little_endian[1]) begin
byte_sel_next = 4'b1100;
end else begin
byte_sel_next = 4'b0011;
end
end
`mem_write8 :
begin
write_next = 1'b1;
mem_data_w_v = {data_write[7:0], data_write[7:0],
data_write[7:0], data_write[7:0]};
bits = address_data[1:0] ^ little_endian;
case (bits)
2'b00 : byte_sel_next = 4'b1000;
2'b01 : byte_sel_next = 4'b0100;
2'b10 : byte_sel_next = 4'b0010;
default : byte_sel_next = 4'b0001;
endcase
end
default :
begin
end
endcase
byte_sel_next_sig <= byte_sel_next ;
write_next_sig <= write_next ;
opcode_next = opcode_reg;
case (mem_state_reg) // synopsys parallel_case
//State Machine
STATE_FETCH :
begin
address = address_pc;
write_line = 1'b0;
byte_sel = 4'b0000;
// mem_state_next = STATE_ADDR;
// opcode_next = mem_data_r;
if (mem_source == `mem_fetch) begin
//opcode fetch
mem_state_next = STATE_FETCH;
if (~pause_in)
opcode_next = mem_data_r;
end else begin
//memory read or write
pause = 1'b1;
if (~pause_in)
mem_state_next = STATE_ADDR;
end
end
STATE_ADDR :
begin
//address lines pre-hold
address = address_reg;
write_line = write_reg;
if (write_reg & address_reg[31])
begin
pause = 1'b1;
byte_sel = 4'b0000;
if (pause_in == 1'b0) begin
mem_state_next = STATE_WRITE; //4 cycle access
end
end else begin
byte_sel = byte_sel_reg;
if (~pause_in) begin
opcode_next = next_opcode_reg;
mem_state_next = STATE_FETCH; //2 cycle access
end
end
end
STATE_WRITE :
begin
pause = 1'b1;
address = address_reg;
write_line = write_reg;
byte_sel = byte_sel_reg;
if (~pause_in) begin
mem_state_next = STATE_PAUSE;
end
end
default :
begin
//STATE_PAUSE address lines post-hold
address = address_reg;
write_line = write_reg;
byte_sel = 4'b0000;
if (~pause_in) begin
opcode_next = next_opcode_reg;
mem_state_next = STATE_FETCH;
end
end
endcase
if (nullify_op & ~pause_in)
opcode_next = `ZERO; //NOP after beql
mem_state_next_sig <= mem_state_next;
opcode_next_sig <= opcode_next;
if (reset) write_line = 1'b0;
opcode_out <= opcode_reg;
data_read <= data;
pause_out <= pause;
mem_byte_sel <= byte_sel;
mem_address <= address;
mem_write <= write_line;
mem_data_w <= mem_data_w_v ;
//`ifdef mem_dat_w_TRISTATE
// if (~write_line)
// mem_data_w <= `HIGH_Z ; //ZERO;
//`endif
end //data_proc
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Clk_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:13 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module Clk_ctrl(
Reset ,
Clk_125M ,
//host interface,
Speed ,
//Phy interface ,
Gtx_clk ,
Rx_clk ,
Tx_clk ,
//interface clk ,
MAC_tx_clk ,
MAC_rx_clk ,
MAC_tx_clk_div ,
MAC_rx_clk_div
);
input Reset ;
input Clk_125M ;
//host interface
input [2:0] Speed ;
//Phy interface
output Gtx_clk ;//used only in GMII mode
input Rx_clk ;
input Tx_clk ;//used only in MII mode
//interface clk signals
output MAC_tx_clk ;
output MAC_rx_clk ;
output MAC_tx_clk_div ;
output MAC_rx_clk_div ;
//******************************************************************************
//internal signals
//******************************************************************************
wire Rx_clk_div2 ;
wire Tx_clk_div2 ;
//******************************************************************************
//
//******************************************************************************
assign Gtx_clk =Clk_125M ;
assign MAC_rx_clk =Rx_clk ;
CLK_DIV2 U_0_CLK_DIV2(
.Reset (Reset ),
.IN (Rx_clk ),
.OUT (Rx_clk_div2 )
);
CLK_DIV2 U_1_CLK_DIV2(
.Reset (Reset ),
.IN (Tx_clk ),
.OUT (Tx_clk_div2 )
);
CLK_SWITCH U_0_CLK_SWITCH(
.IN_0 (Rx_clk_div2 ),
.IN_1 (Rx_clk ),
.SW (Speed[2] ),
.OUT (MAC_rx_clk_div )
);
CLK_SWITCH U_1_CLK_SWITCH(
.IN_0 (Tx_clk ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk )
);
CLK_SWITCH U_2_CLK_SWITCH(
.IN_0 (Tx_clk_div2 ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk_div )
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_BEHAVIORAL_PP_V |
// fpgaTop_vc707.v - the top-level Verilog for the Xilinx VC707 board
// Copyright (c) 2012 Atomic Rules LLC - ALL RIGHTS RESERVED
//
module fpgaTop (
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire sys0_rst, // sys0 Reset (active high)
//input wire sys1_clkp, // sys1 Clock +
//input wire sys1_clkn, // sys1 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [3:0] pci_exp_txp, // PCIe lanes...
output wire [3:0] pci_exp_txn,
input wire [3:0] pci_exp_rxp,
input wire [3:0] pci_exp_rxn,
//input wire ppsExtIn, // PPS in
//output wire ppsOut, // PPS out
//
input wire [ 7:0] usr_sw, // dip-switches
output wire [ 7:0] led, // leds
output wire [ 3:0] lcd_db, // LCD databus
output wire lcd_e, // LCD enable
output wire lcd_rs, // LCD register-select
output wire lcd_rw, // LCD read-not-write
output wire [15:0] debug // debug
//output wire [7:0] gmii_txd, // Alaska GMII...
//output wire gmii_tx_en,
//output wire gmii_tx_er,
//input wire [7:0] gmii_rxd,
//input wire gmii_rx_dv,
//input wire gmii_rx_er,
//output wire gmii_tx_clk,
//input wire gmii_rx_clk,
//output wire [23:0] flash_addr,
//inout wire [15:0] flash_io_dq,
//input wire flash_wait,
//output wire flash_we_n,
//output wire flash_oe_n,
//output wire flash_ce_n
//inout wire [63:0] ddr3_dq, // DDR3 DRAM...
//output wire [12:0] ddr3_addr,
//output wire [2:0] ddr3_ba,
//output wire ddr3_ras_n,
//output wire ddr3_cas_n,
//output wire ddr3_we_n,
//output wire ddr3_reset_n,
//output wire [0:0] ddr3_cs_n,
//output wire [0:0] ddr3_odt,
//output wire [0:0] ddr3_cke,
//output wire [7:0] ddr3_dm,
//inout wire [7:0] ddr3_dqs_p,
//inout wire [7:0] ddr3_dqs_n,
//output wire [0:0] ddr3_ck_p,
//output wire [0:0] ddr3_ck_n
//output wire flp_com_sclk, // FMC150 in LPC Slot...
//output wire flp_com_sdc2m,
//input wire flp_cdc_sdm2c,
//input wire flp_mon_sdm2c,
//input wire flp_adc_sdm2c,
//input wire flp_dac_sdm2c,
//output wire flp_cdc_sen_n,
//output wire flp_mon_sen_n,
//output wire flp_adc_sen_n,
//output wire flp_dac_sen_n,
//output wire flp_cdc_rstn,
//output wire flp_cdc_pdn,
//output wire flp_mon_rstn,
//output wire flp_mon_intn,
//output wire flp_adc_rstn
);
// Instance and connect mkFTop...
mkFTop_kc705 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.sys0_rstn (!sys0_rst), // Invert to make active-low
//.sys1_clkp (sys1_clkp),
//.sys1_clkn (sys1_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.lcd_db (lcd_db),
.lcd_e (lcd_e),
.lcd_rs (lcd_rs),
.lcd_rw (lcd_rw),
//.gps_ppsSyncIn_x (ppsExtIn),
//.gps_ppsSyncOut (ppsOut),
.usr_sw_i (usr_sw),
.debug (debug)
//.gmii_txd (gmii_txd),
//.gmii_tx_en (gmii_tx_en),
//.gmii_tx_er (gmii_tx_er),
//.gmii_rxd_i (gmii_rxd),
//.gmii_rx_dv_i (gmii_rx_dv),
//.gmii_rx_er_i (gmii_rx_er),
//.gmii_tx_clk (gmii_tx_clk),
//.gmii_rx_clk (gmii_rx_clk),
//.flash_addr (flash_addr),
//.flash_io_dq (flash_io_dq),
//.flash_fwait_i (flash_wait),
//.flash_we_n (flash_we_n),
//.flash_oe_n (flash_oe_n),
//.flash_ce_n (flash_ce_n)
//.dram_io_dq (ddr3_dq),
//.dram_addr (ddr3_addr),
//.dram_ba (ddr3_ba),
//.dram_ras_n (ddr3_ras_n),
//.dram_cas_n (ddr3_cas_n),
//.dram_we_n (ddr3_we_n),
//.dram_reset_n (ddr3_reset_n),
//.dram_cs_n (ddr3_cs_n),
//.dram_odt (ddr3_odt),
//.dram_cke (ddr3_cke),
//.dram_dm (ddr3_dm),
//.dram_io_dqs_p (ddr3_dqs_p),
//.dram_io_dqs_n (ddr3_dqs_n),
//.dram_ck_p (ddr3_ck_p),
//.dram_ck_n (ddr3_ck_n)
//.flp_com_sclk (flp_com_sclk),
//.flp_com_sdc2m (flp_com_sdc2m),
//.flp_cdc_sdm2c (flp_cdc_sdm2c),
//.flp_mon_sdm2c (flp_mon_sdm2c),
//.flp_adc_sdm2c (flp_adc_sdm2c),
//.flp_dac_sdm2c (flp_dac_sdm2c),
//.flp_cdc_sen_n (flp_cdc_sen_n),
//.flp_mon_sen_n (flp_mon_sen_n),
//.flp_adc_sen_n (flp_adc_sen_n),
//.flp_dac_sen_n (flp_dac_sen_n),
//.flp_cdc_rstn (flp_cdc_rstn),
//.flp_cdc_pdn (flp_cdc_pdn),
//.flp_mon_rstn (flp_mon_rstn),
//.flp_mon_intn (flp_mon_intn),
//.flp_adc_rstn (flp_adc_rstn)
);
endmodule
|
/******************************************************************************
* File Name : jhash_core.v
* Version : 0.1
* Date : 2008 08 29
* Description: jash core module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module jhash_core(/*AUTOARG*/
// Outputs
stream_ack, hash_out, hash_done, m_endn,
// Inputs
clk, rst, ce, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left
);
input clk, rst, ce;
input [31:0] stream_data0,
stream_data1,
stream_data2;
input stream_valid;
input stream_done;
input [1:0] stream_left;
output stream_ack;
output [31:0] hash_out;
output hash_done;
output m_endn;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg hash_done;
reg stream_ack;
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] OA; // From mix of mix.v
wire [31:0] OB; // From mix of mix.v
wire [31:0] OC; // From mix of mix.v
// End of automatics
parameter [1:0]
S_IDLE = 2'b00,
S_LOAD = 2'b01,
S_RUN = 2'b10,
S_DONE = 2'b11;
reg [1:0]
state, state_n;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [2:0] round;
reg round_rst, round_inc;
always @(posedge clk)
if (round_rst)
round <= #1 3'b000;
else if (round_inc)
round <= #1 round + 1'b1;
reg [31:0] a, a_n,
b, b_n,
c, c_n;
reg [4:0] shift, shift_n;
reg final_r, final_n;
mix mix (/*AUTOINST*/
// Outputs
.OA (OA[31:0]),
.OB (OB[31:0]),
.OC (OC[31:0]),
// Inputs
.a (a[31:0]),
.b (b[31:0]),
.c (c[31:0]),
.clk (clk),
.shift (shift[4:0]));
always @(posedge clk)
begin
a <= #1 a_n;
b <= #1 b_n;
c <= #1 c_n;
shift <= #1 shift_n;
final_r<=#1 final_n;
end
always @(/*AS*/OA or OB or OC or a or b or c or final_r
or round or shift or state or stream_data0
or stream_data1 or stream_data2 or stream_done
or stream_left or stream_valid)
begin
a_n = a;
b_n = b;
c_n = c;
state_n = state;
stream_ack = 1'b0;
shift_n = shift;
round_inc = 1'b0;
round_rst = 1'b0;
final_n = final_r;
case (state)
S_IDLE: begin
a_n = 32'h0;
b_n = 32'h0;
c_n = 32'h0;
final_n = 1'b0;
if (stream_valid) begin
state_n = S_LOAD;
end
end
S_LOAD: if (stream_done && 1'b0) begin
/* a -= c; a ^= rot(c, 4); c += b; */
round_rst = 1'b1;
shift_n = 4;
state_n = S_RUN;
final_n = 1'b1;
case (stream_left)
2'b00: state_n = S_DONE;
2'b01: begin
a_n = a + stream_data0;
end
2'b10: begin
a_n = a + stream_data0;
b_n = b + stream_data1;
end
2'b11: begin
a_n = a + stream_data0;
b_n = b + stream_data1;
c_n = c + stream_data2;
end
endcase // case(stream_left)
end else // if (stream_done)
if (stream_valid) begin
/* a -= c; a ^= rot(c, 4); c += b; */
a_n = a + stream_data0;
b_n = b + stream_data1;
c_n = c + stream_data2;
state_n = S_RUN;
shift_n = 4;
stream_ack = 1'b1;
round_rst = 1'b1;
end
S_RUN: begin
a_n = OB;
b_n = OC;
c_n = OA;
round_inc = 1'b1;
case (round)
3'b000: /* b -= a; b ^= rot(a, 6); a += c; */
shift_n = 6;
3'b001: /* c -= b; c ^= rot(b, 8); b += a; */
shift_n = 8;
3'b010: /* a -= c; a ^= rot(c,16); c += b; */
shift_n = 16;
3'b011: /* b -= a; b ^= rot(a,19); a += c */
shift_n = 19;
3'b100: /* c -= b; c ^= rot(b, 4); b += a; */
shift_n = 4;
3'b101: begin
if (/*final_r*/stream_done)
state_n = S_DONE;
else
state_n = S_LOAD;
end
endcase // case(round)
end // case: S_RUN
S_DONE: ;
endcase // case(state)
end // always @ (...
always @(posedge clk)
hash_done <= #1 state == S_DONE;
assign m_endn = ce ? ~hash_done : 1'bz;
assign hash_out = ce ? c : 32'hz;
endmodule // jhash_core |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_74x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_74x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [73:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [73:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [73:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [73:0] q = sub_wire3[73:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 240,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 74,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "74"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "74"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "74"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 74 0 INPUT NODEFVAL data[73..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 74 0 OUTPUT NODEFVAL q[73..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 74 0 data 0 0 74 0
// Retrieval info: CONNECT: q 0 0 74 0 @q 0 0 74 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_74x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
/**
* udp_dlatch$PSa_pp$sN: Positive level sensitive D-type -latch with
* active low
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PSa_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_ASYNC ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER_REG
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
|
/*
* Titor - System - PS/2 controller wrapper
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_WRAPPER_PS2
`else
`define INC_WRAPPER_PS2
`timescale 1 ns / 100 ps
module PS2MemoryWrapper(
dout,
din,
address,
size,
read_write,
enable,
interrupt,
ps2_clock,
ps2_data,
reset,
clk
);
`include "definition/Definition.v"
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg interrupt;
inout ps2_clock;
inout ps2_data;
wire [BYTE-1:0] rx_data;
input reset;
input clk;
reg [WORD-1:0] key_normal;
wire rx_done;
// Memory interface
always @(posedge clk) begin
if(reset) begin
dout <= 0;
end
else if((address==0) && (enable==ENABLE) && (read_write==READ)) begin
dout <= key_normal;
end
end
// Local definitions
localparam UNSPECIAL = 0;
localparam SPECIAL = 224;
localparam EXTRA = 255;
localparam BREAK = 240;
// Key disambiguation
reg ignore;
reg [WORD-1:0] specialc;
reg breakc;
// Key translation
reg [WORD-1:0] try_normalized;
reg try_interrupt;
reg try_ignore;
always @(posedge clk) begin
if(reset) begin
ignore <= 0;
specialc <= UNSPECIAL;
breakc <= 0;
end
else begin
if(!rx_done) begin
ignore <= ignore;
specialc <= specialc;
breakc <= breakc;
end
else begin
case(rx_data)
SPECIAL: begin
ignore <= ignore;
specialc <= SPECIAL;
breakc <= 0;
end
EXTRA: begin
ignore <= ignore;
specialc <= EXTRA;
breakc <= 0;
end
BREAK: begin
ignore <= ignore;
specialc <= specialc;
breakc <= 1;
end
default: begin
ignore <= try_ignore;
specialc <= UNSPECIAL;
breakc <= 0;
end
endcase
end
end
end
// In the lookup table determine the normalized key
always @(*) begin
if(!rx_done) begin
try_normalized <= 0;
try_interrupt <= 0;
try_ignore <= 0;
end
else begin
`include "meta-include/Scan-Code.meta.v"
end
end
// Combine all the information and send an interrupt if necessary
always @(posedge clk) begin
if(reset) begin
interrupt <= 0;
key_normal <= 0;
end
else if(try_interrupt) begin
interrupt <= !ignore;
key_normal <= (breakc<<(WORD-1)) | try_normalized;
end
else begin
interrupt <= 0;
key_normal <= key_normal;
end
end
PS2 hardware(
.ps2_clock(ps2_clock),
.ps2_data(ps2_data),
.rx_data(rx_data),
.rx_done(rx_done),
.reset(reset),
.clk(clk)
);
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hd__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_FUNCTIONAL_PP_V |
// File clk.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module clk(
reset,
preset,
qreset,
sysclk,
dsysclk,
esysclk,
ival
);
input reset, preset, qreset, sysclk, dsysclk, esysclk;
input [31:0] ival;
wire reset;
wire preset;
wire qreset;
wire sysclk;
wire dsysclk;
wire esysclk;
wire [31:0] ival;
reg [10 + 3:0] foo;
reg [2:0] baz;
reg [4:7 - 1] egg;
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
foo <= {(((10 + 3))-((0))+1){1'b1}};
end else begin
foo <= ival[31:31 - ((10 + 3))];
end
end
always @(negedge preset or negedge dsysclk) begin
if((preset != 1'b 1)) begin
baz <= {3{1'b0}};
end else begin
baz <= ival[2:0];
end
end
always @(negedge qreset or negedge esysclk) begin
if((qreset != 1'b 1)) begin
egg <= {(((7 - 1))-((4))+1){1'b0}};
end else begin
egg <= ival[6:4];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V |
module testbench();
parameter els_p = 16;
parameter width_p = 32;
parameter lg_els_lp = `BSG_SAFE_CLOG2(els_p);
parameter num_test_p = 100000;
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) cg0 (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(8)
) rg0 (
.clk_i(clk)
,.async_reset_o(reset)
);
logic fifo_alloc_v_lo;
logic [lg_els_lp-1:0] fifo_alloc_id_lo;
logic fifo_alloc_yumi_li;
logic write_v_li;
logic [lg_els_lp-1:0] write_id_li;
logic [width_p-1:0] write_data_li;
logic fifo_deq_v_lo;
logic [width_p-1:0] fifo_deq_data_lo;
logic fifo_deq_yumi_li;
logic empty_lo;
bsg_fifo_reorder #(
.width_p(width_p)
,.els_p(els_p)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.fifo_alloc_v_o(fifo_alloc_v_lo)
,.fifo_alloc_id_o(fifo_alloc_id_lo)
,.fifo_alloc_yumi_i(fifo_alloc_yumi_li)
,.write_v_i(write_v_li)
,.write_id_i(write_id_li)
,.write_data_i(write_data_li)
,.fifo_deq_v_o(fifo_deq_v_lo)
,.fifo_deq_data_o(fifo_deq_data_lo)
,.fifo_deq_yumi_i(fifo_deq_yumi_li)
,.empty_o(empty_lo)
);
logic [els_p-1:0] node_v_li;
logic [width_p-1:0] node_data_li;
logic [els_p-1:0] node_yumi_lo;
logic [els_p-1:0] node_v_lo;
logic [els_p-1:0][width_p-1:0] node_data_lo;
logic [els_p-1:0] node_yumi_li;
for (genvar i = 0; i < els_p; i++) begin
remote_node #(
.width_p(width_p)
,.max_delay_p(32-(i/2)) // unequal random delay
,.id_p(i)
) node0 (
.clk_i(clk)
,.reset_i(reset)
,.v_i(node_v_li[i])
,.data_i(node_data_li)
,.yumi_o(node_yumi_lo[i])
,.v_o(node_v_lo[i])
,.data_o(node_data_lo[i])
,.yumi_i(node_yumi_li[i])
);
end
// sender
integer sent_r;
wire send_done = (sent_r == num_test_p);
bsg_decode_with_v #(
.num_out_p(els_p)
) demux0 (
.i(fifo_alloc_id_lo)
,.v_i(fifo_alloc_v_lo & ~send_done)
,.o(node_v_li)
);
wire send = fifo_alloc_v_lo & node_yumi_lo[fifo_alloc_id_lo] & ~send_done;
assign fifo_alloc_yumi_li = send;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= 0;
end
else begin
if (send) sent_r <= sent_r + 1;
end
end
assign node_data_li = (width_p)'(sent_r);
// recv
logic rr_v_lo;
logic rr_yumi_li;
bsg_round_robin_n_to_1 #(
.width_p(width_p)
,.num_in_p(els_p)
,.strict_p(0)
) rr0 (
.clk_i(clk)
,.reset_i(reset)
,.data_i(node_data_lo)
,.v_i(node_v_lo)
,.yumi_o(node_yumi_li)
,.v_o(rr_v_lo)
,.data_o(write_data_li)
,.tag_o(write_id_li)
,.yumi_i(rr_yumi_li)
);
//assign rr_yumi_li = rr_v_lo;
//assign write_v_li = rr_v_lo;
integer recv_delay_r;
always_ff @ (posedge clk) begin
if (reset) begin
recv_delay_r <= 0;
end
else begin
if (rr_v_lo) begin
if (recv_delay_r == 0)
recv_delay_r <= $urandom_range(8,0);
else
recv_delay_r <= recv_delay_r - 1;
end
end
end
assign rr_yumi_li = rr_v_lo & (recv_delay_r == 0);
assign write_v_li = rr_v_lo & (recv_delay_r == 0);
// checker
integer check_delay_r;
always_ff @ (posedge clk) begin
if (reset) begin
check_delay_r <= 0;
end
else begin
if (fifo_deq_v_lo) begin
if (check_delay_r == 0) begin
check_delay_r <= $urandom_range(8,0);
end
else begin
check_delay_r <= check_delay_r - 1;
end
end
end
end
assign fifo_deq_yumi_li = fifo_deq_v_lo & (check_delay_r == 0);
integer check_count_r;
always_ff @ (posedge clk) begin
if (reset) begin
check_count_r <= 0 ;
end
else begin
if (fifo_deq_yumi_li) begin
check_count_r <= check_count_r + 1;
$display("data out: %d", fifo_deq_data_lo);
assert(check_count_r == fifo_deq_data_lo) else $fatal("fail");
end
end
end
initial begin
wait((check_count_r == num_test_p) & (sent_r == num_test_p));
#100000;
assert(empty_lo) else $fatal("[BSG_FAIL] FIFO is not empty.");
$finish();
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_2_V
`define SKY130_FD_SC_MS__AND4_2_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:48:21 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
`timescale 1ns / 1ps
module selector_mode_tb();
reg [31:0]clk;
reg start, power, mode_ch;
reg [1:0]washing_machine_running;
wire push;
wire [2:0]sel_value;
parameter TIME = 1000;
selector_mode #(0,5) MODE_SEL (.clk(clk),
.switch_power(power),
.switch_en(start),
.sig_change(mode_ch),
.push(push),
.washing_machine_running(washing_machine_running),
.sel_value(sel_value)
);
initial begin
power = 0;
clk[25] = 0;
clk[0] = 0;
start = 0;
mode_ch = 0;
washing_machine_running = 0;
#TIME $finish;
end
always begin
#10 clk[25] = ~clk[25];
end
always begin
#1 clk[0] = ~clk[0];
end
always begin
// #5 start = 0;
#20 power = 1;
#10 mode_ch = 1;
#10 mode_ch = 0;
#10 mode_ch = 1;
#10 mode_ch = 0;
#10 mode_ch = 1;
#10 mode_ch = 0;
#10 mode_ch = 1;
// #100 start = 1; washing_machine_running = 1;
#100 start = 0; washing_machine_running = 2;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__MUX2_FUNCTIONAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__mux2 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_20_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (u_mux_20_out_X , A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_20_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_BLACKBOX_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb16to1 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_BLACKBOX_V
|
module autoconstant_gooch
(/*AUTOARG*/
// Outputs
out1, out2, out3,
// Inputs
in1, in2, in3
);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
output [3:0] out1;
reg [3:0] out1;
output [3:0] out2;
reg [3:0] out2;
output [3:0] out3;
reg [3:0] out3;
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out1 = in2;
end
4'b0010 : begin
out1 = in2 + in3;
end
4'b0100 : begin
out1 = in2 - in3;
end
4'b1000 : begin
out1 = in2;
end
default : begin
out1 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out2 = in2;
end
4'b0010 : begin
out2 = in2 + in3;
end
4'b0100 : begin
out2 = in2 - in3;
end
4'b1000 : begin
out2 = in2;
end
default : begin
out2 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
/* AUTO_CONSTANT( temp )*/
/* AxxxUTO_CONSTANT temp */
out3 = in1 + in2;
temp2 = temp;
// ERROR here - above constant definition is not
// correct - no braces - and so parser keeps looking
// for the first variable it finds between a pair of
// braces - in this case, in2. This in2 is now a
// "constant" and is removed from all sensitivity lists.
// ( in2 )
case (in1)
4'b0001 : begin
out3 = in2;
end
4'b0010 : begin
out3 = in2 + in3;
end
4'b0100 : begin
out3 = in2 - in3;
end
4'b1000 : begin
out3 = in2;
end
default : begin
out3 = {4{1'b0}};
end
endcase
end
endmodule
|
`default_nettype none
module flag_rename_management #(
parameter ENTRY_ID = 4'h0
)(
//System
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iREMOVE_VALID,
//Commit Vector
input wire [63:0] iCOMMIT_VECTOR,
//Regist
input wire iREGIST_0_VALID,
input wire [3:0] iREGIST_0_FLAGAS_REGNAME,
input wire [5:0] iREGIST_0_COMMIT_TAG,
input wire iREGIST_1_VALID,
input wire [3:0] iREGIST_1_FLAGAS_REGNAME,
input wire [5:0] iREGIST_1_COMMIT_TAG,
//EXEND
//input wire iEXEND_BRANCH_VALID,
//input wire [5:0] iEXEND_BRANCH_COMMIT_TAG,
//Common Data Bus CDB(CH1)
input wire iALU1_VALID,
input wire [5:0] iALU1_COMMIT_TAG,
input wire [4:0] iALU1_FLAGS,
//Common Data Bus CDB(CH2)
input wire iALU2_VALID,
input wire [5:0] iALU2_COMMIT_TAG,
input wire [4:0] iALU2_FLAGS,
//Free List Valid
input wire iFREELIST_REGIST_VALID,
//INFO
output wire oINFO_FREELIST_REQ,
output wire oINFO_FLAGS_VALID,
output wire [4:0] oINFO_FLAGS
);
reg [2:0] b_state;
reg b_reset;
reg b_freelist_req;
reg b_flag_valid;
reg [5:0] b_commit_tag;
reg [4:0] b_flags;
wire [5:0] w_commit_wait_check_vector;
assign w_commit_wait_check_vector = b_commit_tag+6'h1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= 3'h0;
b_reset <= 1'b0;
b_freelist_req <= 1'b0;
b_flag_valid <= 1'b0;
b_commit_tag <= 6'h00;
b_flags <= 5'h00;
end
else if((iREMOVE_VALID && b_state != 3'h3) || b_reset)begin
b_state <= 3'h0;
b_reset <= 1'b0;
b_freelist_req <= 1'b0;
b_flag_valid <= 1'b0;
b_commit_tag <= 6'h00;
b_flags <= 5'h00;
end
else begin
case(b_state)
3'h0 : //Free List Regist Wait
begin
if(iFREELIST_REGIST_VALID)begin
b_state <= 3'h1;
b_freelist_req <= 1'b0;
end
else begin
b_freelist_req <= 1'b1;
b_flag_valid <= 1'b0;
end
end
3'h1 : //Entry Regist Wait
begin
if(iREGIST_0_VALID && ENTRY_ID == iREGIST_0_FLAGAS_REGNAME)begin
b_state <= 3'h2;
b_commit_tag <= iREGIST_0_COMMIT_TAG;
end
else if(iREGIST_1_VALID && ENTRY_ID == iREGIST_1_FLAGAS_REGNAME)begin
b_state <= 3'h2;
b_commit_tag <= iREGIST_1_COMMIT_TAG;
end
end
3'h2 : //Get Flag Wait
begin
//CMP Exeenc Wait
if(iALU1_VALID && b_commit_tag == iALU1_COMMIT_TAG)begin
//Commit Check
b_state <= 3'h3;
b_flags <= iALU1_FLAGS;
b_flag_valid <= 1'b1;
end
else if(iALU2_VALID && b_commit_tag == iALU2_COMMIT_TAG)begin
b_state <= 3'h3;
b_flags <= iALU2_FLAGS;
b_flag_valid <= 1'b1;
end
end
3'h3: //Commit Wait
begin
if(iCOMMIT_VECTOR[w_commit_wait_check_vector])begin
b_flag_valid <= 1'b0;
b_reset <= 1'b1;
end
end
endcase
end
end //always
assign oINFO_FREELIST_REQ = b_freelist_req;
assign oINFO_FLAGS_VALID = b_flag_valid;//(b_state == 3'h2 || b_state == 3'h3)? 1'b1 : 1'b0;
assign oINFO_FLAGS = b_flags;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_BEHAVIORAL_V |
// arWCIS2A4LM.v - Bridge module from WCI-Slave to AXI4-Lite Master
// Copyright (c) 2010 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// 2010-09-12 Module declaration in Verilog
// 2010-09-14 20b, 1MB Address Window on both sides of bridge
// 2011-01-15 Switch to 32b 4GB address
module arWCI2A4LM (
input bridge_Clk,
input bridge_Reset_n,
input [2:0] wciS0_MCmd, // WCI Slave...
input [0:0] wciS0_MAddrSpace, // MAddrSpace[0]: 0=Control ; 1=Configuration
input [3:0] wciS0_MByteEn,
input [31:0] wciS0_MAddr, // 32b 4GB Address Space
input [31:0] wciS0_MData,
output [1:0] wciS0_SResp,
output [31:0] wciS0_SData,
output [0:0] wciS0_SThreadBusy,
output [0:0] wciS0_SFlag,
input [0:0] wciS0_MFlag,
output axiM0_AWVALID, // AXI4-Lite Write-Address channel...
input axiM0_AWREADY,
output [31:0] axiM0_AWADDR, // 32b 4GB Address Space
output [2:0] axiM0_AWPROT,
output axiM0_WVALID, // AXI4-Lite Write-Data channel...
input axiM0_WREADY,
output [31:0] axiM0_WDATA,
output [3:0] axiM0_WSTRB,
input axiM0_BVALID, // AXI4-Lite Write-Response channel...
output axiM0_BREADY,
input [1:0] axiM0_BRESP,
output axiM0_ARVALID, // AXI4-Lite Read-Address channel...
input axiM0_ARREADY,
output [31:0] axiM0_ARADDR, // 32b 4GB Address Space
output [2:0] axiM0_ARPROT, // ARPROT[2]: 0=Data/Configuration ; 1=Instruction/Control
input axiM0_RVALID, // AXI4-Lite Read-Data channel...
output axiM0_RREADY,
input [31:0] axiM0_RDATA,
input [1:0] axiM0_RRESP
);
wire[34:0] axiM0_wrAddr_data = {axiM0_AWPROT, axiM0_AWADDR};
wire[35:0] axiM0_wrData_data = {axiM0_WSTRB, axiM0_WDATA};
wire[1:0] axiM0_wrResp_data_value = {axiM0_BRESP};
wire[34:0] axiM0_rdAddr_data = {axiM0_ARPROT, axiM0_ARADDR};
wire[33:0] axiM0_rdResp_data_value = {axiM0_RRESP, axiM0_RDATA};
// Instance the BSV module...
mkWCI2A4LM bridge(
.wciS0_Clk (bridge_Clk),
.wciS0_MReset_n (bridge_Reset_n),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MAddrSpace (wciS0_AddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MData (wciS0_MData),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wciS0_MFlag (wciS0_MFlag),
.axiM0_wrAddr_data (axiM0_wrAddr_data),
.axiM0_wrAddr_valid (axiM0_AWVALID),
.axiM0_wrAddr_ready_value (axiM0_AWREADY),
.axiM0_wrData_data (axiM0_wrData_data),
.axiM0_wrData_valid (axiM0_WVALID),
.axiM0_wrData_ready_value (axiM0_WREADY),
.axiM0_wrResp_data_value (axiM0_wrResp_data_value),
.axiM0_wrResp_valid_value (axiM0_BVALID),
.axiM0_wrResp_ready (axiM0_BREADY),
.axiM0_rdAddr_data (axiM0_rdAddr_data),
.axiM0_rdAddr_valid (axiM0_ARVALID),
.axiM0_rdAddr_ready_value (axiM0_ARREADY),
.axiM0_rdResp_data_value (axiM0_rdResp_data_value),
.axiM0_rdResp_valid_value (axiM0_RVALID),
.axiM0_rdResp_ready (axiM0_RREADY)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, GATE, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V |
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
*)
(**
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;;
{{ Q }}
c2
{{ R }}
*)
(**
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
*)
(**
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
*)
(**
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
*)
(**
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;;
Y ::= X - Y;;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ X <= Y }} ->>
{{ Y = X + (Y - X) }}
Z ::= Y - X
{{ Y = X + Z }}
ELSE
{{ X > Y }} ->>
{{ X + Z = X + Z }}
Y ::= X + Z
{{ Y = X + Z }}
FI
{{ Y = X + Z }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;;
Y ::= 0;;
WHILE n <= X DO
X ::= X - n;;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;;
(3) {{ n * 0 + X = m }}
Y ::= 0;;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to
show that [n = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;;
WHILE X <> 0 DO
X ::= X - 1;;
Y ::= Y + 1
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(*
{{ X = m }} ->>
{{ X + 0 = m }}
Y ::= 0;;
{{ X + Y = m }}
WHILE X <> 0 DO
{{ X + Y = m /\ X <> 0 }} ->>
{{ (X - 1) + (Y + 1) = m }}
X ::= X - 1;;
{{ X + (Y + 1) = m }}
Y ::= Y + 1
{{ X + Y = m }}
END
{{ X + Y = m /\ X = 0 }} ->>
{{ Y = m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(*
{{ X = m /\ Z = n }} ->>
{{ X + Z = m + n }}
WHILE X <> 0 DO
{{ X + Z = m + n /\ X <> 0 }} ->>
{{ (X - 1) + (Z + 1) = m + n}}
Z ::= Z + 1;;
{{ (X - 1) + Z = m + n }}
X ::= X - 1
{{ X + Z = m + n}}
END
{{ X + Z = m + n /\ X = 0 }} ->>
{{ Z = m + n }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
intros.
remember (fun st => parity (st X) = parity m) as I.
eapply hoare_consequence_post.
eapply hoare_consequence_pre with I.
eapply hoare_while.
eapply hoare_consequence_pre.
eapply hoare_asgn.
unfold assert_implies, assn_sub, bassn, beval, update; rewrite HeqI; intros; simpl.
inversion H; subst.
rewrite <- H0.
apply parity_ge_2.
apply ble_nat_true.
apply H1.
unfold assert_implies, assn_sub, bassn, beval, update; rewrite HeqI; intros; simpl.
auto.
unfold assert_implies, assn_sub, bassn, beval, update; rewrite HeqI; intros; simpl.
inversion H; subst.
rewrite <- H0.
symmetry.
apply parity_lt_2.
apply ble_nat_false.
apply not_true_is_false.
apply H1.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;;
Z ::= 0;;
WHILE Y <> X DO
Z ::= Z + X;;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;;
{{ 0 = m*m /\ X = m }}
Z ::= 0;;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }}
Y ::= 1 ;;
WHILE X <> 0
DO
Y ::= Y * X ;;
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ 1 * X! = m! }}
Y ::= 1;;
{{ Y * X! = m! }}
WHILE X <> 0
DO {{ Y * X! = m! /\ X <> 0 }} ->>
{{ Y * X * (X - 1)! = m! }}
Y ::= Y * X;;
{{ Y * (X - 1)! = m! }}
X ::= X - 1
{{ Y * X! = m! }}
END
{{ Y * X! = m! /\ X = 0 }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ 0 + min a b = min a b }}
X ::= a;;
{{ 0 + min X b = min a b }}
Y ::= b;;
{{ 0 + min X Y = min a b }}
Z ::= 0;;
{{ Z + min X Y = min a b }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ Z + min X Y = min a b /\ X <> 0 /\ Y <> 0 }} ->>
{{ Z + 1 + min (X - 1) (Y - 1) = min a b }}
X := X - 1;;
{{ Z + 1 + min X (Y - 1) = min a b }}
Y := Y - 1;;
{{ Z + 1 + min X Y = min a b }}
Z := Z + 1
{{ Z + min X Y = min a b }}
END
{{ Z + min X Y = min a b /\ (X = 0 \/ Y = 0) }} ->>
{{ Z = min a b }}
*)
(** [] *)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;;
Y ::= 0;;
Z ::= c;;
WHILE X <> a DO
X ::= X + 1;;
Z ::= Z + 1
END;;
WHILE Y <> b DO
Y ::= Y + 1;;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ c = 0 + 0 + c }}
X ::= 0;;
{{ c = X + 0 + c }}
Y ::= 0;;
{{ c = X + Y + c }}
Z ::= c;;
{{ Z = X + Y + c }}
WHILE X <> a DO
{{ Z = X + Y + c /\ X <> a }} ->>
{{ Z + 1 = (X + 1) + Y + c }}
X ::= X + 1;;
{{ Z + 1 = X + Y + c }}
Z ::= Z + 1
{{ Z = X + Y + c }}
END;;
{{ Z = X + Y + c /\ X = a }} ->>
{{ Z = a + Y + c }}
WHILE Y <> b DO
{{ Z = a + Y + c /\ Y <> b }} ->>
{{ Z + 1 = a + (Y + 1) + c }}
Y ::= Y + 1;;
{{ Z + 1 = a + Y + c }}
Z ::= Z + 1
{{ Z = a + Y + c }}
END
{{ Z = a + Y + c /\ Y = b }} ->>
{{ Z = a + b + c }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;;
Y ::= 1;;
Z ::= 1;;
WHILE X <> m DO
Z ::= 2 * Z;;
Y ::= Y + Z;;
X ::= X + 1
END
Write a decorated program for this. *)
(*
{{ True }} ->>
{{ 1 = 2 ^ (0 + 1) - 1 /\ 1 = 2 ^ 0 }}
X ::= 0;;
{{ 1 = 2 ^ (X + 1) - 1 /\ 1 = 2 ^ X }}
Y ::= 1;;
{{ Y = 2 ^ (X + 1) - 1 /\ 1 = 2 ^ X }}
Z ::= 1;;
{{ Y = 2 ^ (X + 1) - 1 /\ Z = 2 ^ X }}
WHILE X <> m DO
{{ Y = 2 ^ (X + 1) - 1 /\ Z = 2 ^ X /\ X <> m }} ->>
{{ Y + 2 * Z = 2 ^ (X + 1 + 1) - 1 /\ 2 * Z = 2 ^ (X + 1) }}
Z ::= 2 * Z;;
{{ Y + Z = 2 ^ (X + 1 + 1) - 1 /\ Z = 2 ^ (X + 1) }}
Y ::= Y + Z;;
{{ Y = 2 ^ (X + 1 + 1) - 1 /\ Z = 2 ^ (X + 1) }}
X ::= X + 1
{{ Y = 2 ^ (X + 1) - 1 /\ Z = 2 ^ X }}
END
{{ Y = 2 ^ (X + 1) - 1 /\ Z = 2 ^ X /\ X = m }} ->>
{{ Y = 2 ^ (m + 1) - 1 }}
*)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ X = 5 }} SKIP {{ X = 5 }}
2) {{ Y + Z = 5 }} X ::= Y + Z {{ X = 5 }}
3) {{ True }} X ::= Y {{ X = Y }}
4) {{ (X = 0 /\ Z = 4) \/ (X <> 0 /\ W = 3) }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ False }}
X ::= 5
{{ X = 0 }}
6) {{ True }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
unfold is_wp, hoare_triple; split; intros; simpl.
Case "left".
inversion H; subst.
unfold update; simpl.
omega.
Case "right".
unfold assert_implies; intros.
assert ((X ::= APlus (AId Y) (ANum 1)) / st || update st X (st Y + 1)).
apply E_Ass.
reflexivity.
apply H in H1.
rewrite update_eq in H1.
omega.
apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
unfold is_wp, hoare_triple, assn_sub; split; intros; simpl.
Case "left".
inversion H; subst.
apply H0.
Case "right".
unfold assert_implies; intros.
assert ((X ::= a) / st || update st X (aeval st a)).
apply E_Ass.
reflexivity.
apply H in H1; assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
unfold hoare_triple, assert_implies, havoc_pre; intros.
assert ((HAVOC X) / st || update st X x).
apply E_Havoc.
apply H in H1; assumption.
Qed.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => st X + 0 = m }}
Y ::= ANum 0
{{ fun st => st X + st Y = m }} ;;
WHILE BNot (BEq (AId X) (ANum 0)) DO
{{ fun st => st X + st Y = m /\ st X <> 0 }} ->>
{{ fun st => (st X - 1) + (st Y + 1) = m }}
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st X + (st Y + 1) = m }} ;;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st X + st Y = m }}
END
{{ fun st => st X + st Y = m /\ st X = 0 }} ->>
{{ fun st => st Y = m }}
) % dcom.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof.
intros.
verify.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program [factorial_dec] that implements the factorial function and
prove it correct as [factorial_dec_correct]. *)
Example factorial_dec (m : nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => 1 * real_fact (st X) = real_fact m }}
Y ::= ANum 1
{{ fun st => st Y * real_fact (st X) = real_fact m }} ;;
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Y * real_fact (st X) = real_fact m /\ st X <> 0 }} ->>
{{ fun st => st Y * st X * real_fact (st X - 1) = real_fact m }}
Y ::= AMult (AId Y) (AId X)
{{ fun st => st Y * real_fact (st X - 1) = real_fact m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Y * real_fact (st X) = real_fact m }}
END
{{ fun st => st Y * real_fact (st X) = real_fact m /\ st X = 0 }} ->>
{{ fun st => st Y = real_fact m }}
) % dcom.
Theorem factorial_dec_correct : forall m, dec_correct (factorial_dec m).
Proof.
intros.
verify.
assert (st X * real_fact (st X - 1) = real_fact (st X)).
destruct (st X).
apply ex_falso_quodlibet.
apply H0.
reflexivity.
simpl.
rewrite <- minus_n_O.
reflexivity.
rewrite <- mult_assoc.
rewrite H1.
apply H.
rewrite mult_1_r in H.
apply H.
Qed.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_mac_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.ptp_ts(rx_ptp_ts),
.rx_start_packet(rx_start_packet),
.rx_error_count(rx_error_count),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_mac_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_mac_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B ;
input SLEEP;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire nor_teb_SLEEP;
wire zgnd ;
wire zpwr ;
// Name Output Other arguments
nor nor0 (nor_teb_SLEEP, TE_B, SLEEP );
bufif1 bufif10 (zgnd , A, VPWR );
bufif0 bufif00 (zpwr , zgnd, VGND );
bufif1 bufif11 (Z , zpwr, nor_teb_SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V |
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
WBM reader arbiter
Loosely based on the arbiter_dbus.v (LGPL) in orpsocv2 by Julius Baxter, [email protected]
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
// 3 Masters, one slave
module gfx_wbm_read_arbiter
(
master_busy_o,
// Interface against the wbm read module
read_request_o,
addr_o,
sel_o,
dat_i,
ack_i,
// Interface against masters (clip)
m0_read_request_i,
m0_addr_i,
m0_sel_i,
m0_dat_o,
m0_ack_o,
// Interface against masters (fragment processor)
m1_read_request_i,
m1_addr_i,
m1_sel_i,
m1_dat_o,
m1_ack_o,
// Interface against masters (blender)
m2_read_request_i,
m2_addr_i,
m2_sel_i,
m2_dat_o,
m2_ack_o
);
output master_busy_o;
// Interface against the wbm read module
output read_request_o;
output [31:2] addr_o;
output [3:0] sel_o;
input [31:0] dat_i;
input ack_i;
// Interface against masters (clip)
input m0_read_request_i;
input [31:2] m0_addr_i;
input [3:0] m0_sel_i;
output [31:0] m0_dat_o;
output m0_ack_o;
// Interface against masters (fragment processor)
input m1_read_request_i;
input [31:2] m1_addr_i;
input [3:0] m1_sel_i;
output [31:0] m1_dat_o;
output m1_ack_o;
// Interface against masters (blender)
input m2_read_request_i;
input [31:2] m2_addr_i;
input [3:0] m2_sel_i;
output [31:0] m2_dat_o;
output m2_ack_o;
// Master ins -> |MUX> -> these wires
wire rreq_w;
wire [31:2] addr_w;
wire [3:0] sel_w;
// Slave ins -> |MUX> -> these wires
wire [31:0] dat_w;
wire ack_w;
// Master select (MUX controls)
wire [2:0] master_sel;
assign master_busy_o = m0_read_request_i | m1_read_request_i | m2_read_request_i;
// priority to wbm1, the blender master
assign master_sel[0] = m0_read_request_i & !m1_read_request_i & !m2_read_request_i;
assign master_sel[1] = m1_read_request_i & !m2_read_request_i;
assign master_sel[2] = m2_read_request_i;
// Master input mux, priority to blender master
assign m0_dat_o = dat_i;
assign m0_ack_o = ack_i & master_sel[0];
assign m1_dat_o = dat_i;
assign m1_ack_o = ack_i & master_sel[1];
assign m2_dat_o = dat_i;
assign m2_ack_o = ack_i & master_sel[2];
assign read_request_o = master_sel[2] |
master_sel[1] |
master_sel[0];
assign addr_o = master_sel[2] ? m2_addr_i :
master_sel[1] ? m1_addr_i :
m0_addr_i;
assign sel_o = master_sel[2] ? m2_sel_i :
master_sel[1] ? m1_sel_i :
m0_sel_i;
endmodule // gfx_wbm_read_arbiter
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
parameter PORT_MODE = "BI_MODE";
parameter DATA_MODE = 4'b0010;
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// For small devices, choose one only.
// For large device, choose "DGEN_ALL"
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter DM_WIDTH = 2;
// # of DM (data mask)
parameter DQ_WIDTH = 16;
// # of DQ (data)
parameter DQS_WIDTH = 2;
parameter DQS_CNT_WIDTH = 1;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999;
// Input Clock Period
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333;
// memory tCK paramter.
// # = Clock Period in pS.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR2";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam ECC_TEST = "OFF" ;
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
reg clk_ref_i;
wire ddr2_reset_n;
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_addr_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
reg [ROW_WIDTH-1:0] ddr2_addr_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr2_odt_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr2_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_p_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_addr_sdram <= #(TPROP_PCB_CTRL) ddr2_addr_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
end
always @( * )
ddr2_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
assign ddr2_cs_n_sdram = ddr2_cs_n_sdram_tmp;
always @( * )
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
always @( * )
ddr2_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
assign ddr2_odt_sdram = ddr2_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq_0
(
.A (ddr2_dq_fpga[0]),
.B (ddr2_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr2_dqs_p_fpga[dqswd]),
.B (ddr2_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
.PORT_MODE (PORT_MODE),
.DATA_MODE (DATA_MODE),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC_TEST (ECC_TEST),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BURST_MODE (BURST_MODE),
.TCQ (TCQ),
.DEBUG_PORT (DEBUG_PORT)
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
.ddr2_dqs_p (ddr2_dqs_p_fpga),
.ddr2_addr (ddr2_addr_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_ck_p (ddr2_ck_p_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_odt (ddr2_odt_fpga),
.sys_clk_i (sys_clk_i),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
if(DQ_WIDTH/16) begin: mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq (ddr2_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr2_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs ({ddr2_dm_sdram[DM_WIDTH-1],ddr2_dm_sdram[DM_WIDTH-1]}),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq ({ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr2_dqs_p_sdram[DQS_WIDTH-1],
ddr2_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH-1],
ddr2_dqs_n_sdram[DQS_WIDTH-1]}),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
// This is the test-bench for the single-cycle datapath supporting instructions
// add, sub, slt, and, or, lw, sw, beq. When sequential logic components are
// sent an asynchronous reset signal (clear), their content is set to the
// following values:
//
// * The initial value of register PC is 0x400000.
//
// * The initial value of all registers are 0, except for the following
// registers:
//
// $1 = 1
// $2 = 2
// #3 = 0x10010000 (base address of data segment)
//
// * The data memory is initialized with the following words:
//
// [0x10010000] = 100
// [0x10010004] = 200
//
// * The instruction memory has been initialized to contain the following
// program:
//
// main:
// add $3, $1, $2 # $3 = 1 + 2 = 3
// sub $3, $1, $2 # $3 = 1 - 2 = -1
// and $3, $1, $2 # $3 = 1 & 2 = 0
// or $3, $1, $2 # $3 = 1 | 2 = 3
// slt $3, $1, $2 # $3 = 1 < 2 = 1 (true)
// slt $3, $2, $1 # $3 = 2 < 1 = 0 (false)
// beq $10, $zero, main # Doesn't jump, $10 is 0x10010000
// lw $3, 0($10) # $3 = Mem[0x10010000] = 100
// lw $3, 4($10) # $3 = Mem[0x10010004] = 200
// sw $3, 8($10) # Mem[0x10010008] = 200
// beq $zero, $zero, main # Jumps to main
//
module Main;
// The datapath
reg clock;
reg clear;
Datapath datapath(clock, clear);
// Initial pulse for 'clear'
initial begin
clear = 1;
#5 clear = 0;
end
// Clock signal
initial begin
clock = 1;
forever #5 clock = ~clock;
end
// Run for 11 cycles
initial begin
#40 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/11/29 22:40:09
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_adder(
input clk,
input button,
output [1:0] C,
output [3:0] Q
);
reg [3:0]Q;
reg [1:0]C;
reg before;
wire D;
wire [3:0]inD;
wire [3:0]tempQ;
wire [1:0]tempC;
always@(posedge clk)
begin
if(~before&button)
C[1:0]<=tempC[1:0];
else
Q[3:0]<=tempQ[3:0];
before<=button;
end
assign inD[0]=~(Q[0]|Q[1]|Q[2]);
assign inD[1]=~(Q[3])|(Q[3]&~Q[2]&~Q[1]&Q[0]);
assign inD[2]=~(Q[3])|(Q[3]&Q[2]&~Q[1]&~Q[0]);
assign inD[3]=(Q[0]^Q[3])|(~Q[0]&~Q[1]&~Q[2]&~Q[3]);
assign D=(inD[0]&~C[0]&~C[1])|(inD[1]&C[0]&~C[1])|(inD[2]&~C[0]&C[1])|(inD[3]&C[0]&C[1]);
assign tempQ[0]=D;
assign tempQ[1]=Q[0];
assign tempQ[2]=Q[1];
assign tempQ[3]=Q[2];
assign tempC[0]=~C[0];
assign tempC[1]=C[0]^C[1];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:13:45 02/02/2016
// Design Name: pipeline
// Module Name: D:/workspace-ISE/Pipeline/pipeline_tb.v
// Project Name: Pipeline
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pipeline
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pipeline_tb;
// Inputs
reg clk;
reg reset;
reg ena;
integer ciclo;
//HZ
//wire [1:0] test_ForwardAE;
//wire [1:0] test_ForwardBE;
//wire test_stallF;
//wire test_stallD;
//wire test_flushE;
//wire [4:0] test_instruction_25_21_ID;
//wire [4:0] test_instruction_20_16_ID;
//wire test_wb_MemtoReg_IDEX;
//IF (salidas)
////Datos
wire [31:0] test_pc_incrementado_PC;
wire [31:0] test_instruction_IF;
/*
//IF-ID (salidas)
////Datos
wire [31:0] test_pc_incrementado_IF_ID;
wire [31:0] test_instruction_IF_ID;
//ID (salidas)
////Datos
wire [31:0] test_data1_ID;
wire [31:0] test_data2_ID;
////Control
wire test_wb_RegWrite_ID;
wire test_wb_MemtoReg_ID;
//////MEM
wire test_m_Jump_ID;
wire test_m_Branch_ID;
wire test_m_MemRead_ID;
wire test_m_MemWrite_ID;
//////EX
wire test_ex_RegDst_ID;
wire [5:0] test_ex_ALUOp_ID;
wire test_ex_ALUSrc_ID;
////Datos
wire [31:0] test_sign_extend_ID;
//ID-EX
////Control signals
wire test_wb_RegWrite_ID_EX_out;
wire test_wb_MemtoReg_ID_EX_out;
wire test_m_Jump_ID_EX_out;
wire test_m_Branch_ID_EX_out;
wire test_m_MemRead_ID_EX_out;
wire test_m_MemWrite_ID_EX_out;
wire test_ex_RegDst_ID_EX_out;
wire [5:0] test_ex_ALUOp_ID_EX_out;
wire test_ex_ALUSrc_ID_EX_out;
////Data signals
wire [31:0] test_pc_incrementado_ID_EX_out;
wire [31:0] test_data1_ID_EX_out;
wire [31:0] test_data2_ID_EX_out;
wire [31:0] test_sign_extended_ID_EX_out;
wire [4:0] test_inst_15_11_ID_EX_out;
wire [4:0] test_inst_20_16_ID_EX_out;
wire [4:0] test_inst_25_21_ID_EX_out;
//EX
////Data signals
wire [31:0] test_alu_result_EX;
//EX-MEM
////Data signals
wire [31:0] test_alu_result_EX_MEM;
////Control
wire [5:0] test_opcode_EX_MEM;
wire test_wb_MemtoReg_EXMEM;
//MEM-WB
////Data signals
wire [31:0] test_mem_data_MEM_WB;
wire [4:0] test_reg_dest_addr_MEM_WB;
////Control
wire test_memToReg_MEM_WB;
//WB
////Data signals
wire [31:0] test_mux_wb_data_WB;
//Registros
wire [31:0] test_reg_16;
wire [31:0] test_reg_17;
wire [31:0] test_reg_18;
wire [31:0] test_reg_19;
wire [31:0] test_reg_20;
*/
// Instantiate the Unit Under Test (UUT)
pipeline uut (
.clk(clk),
.reset(reset),
.ena(ena),
//IF (salidas)
////Datos
.test_pc_incrementado_PC(test_pc_incrementado_PC),
.test_instruction_IF(test_instruction_IF)
//IF-ID (salidas)
////Datos
//.test_pc_incrementado_IF_ID(test_pc_incrementado_IF_ID),
//.test_instruction_IF_ID(test_instruction_IF_ID),
/*
//ID (salidas)
////Datos
.test_data1_ID(test_data1_ID),
.test_data2_ID(test_data2_ID),
.test_instruction_20_16_ID(test_instruction_20_16_ID),
.test_instruction_25_21_ID(test_instruction_25_21_ID),
////Control
.test_wb_RegWrite_ID(test_wb_RegWrite_ID),
.test_wb_MemtoReg_ID(test_wb_MemtoReg_ID),
//////MEM
.test_m_Jump_ID(test_m_Jump_ID),
.test_m_Branch_ID(test_m_Branch_ID),
.test_m_MemRead_ID(test_m_MemRead_ID),
.test_m_MemWrite_ID(test_m_MemWrite_ID),
//////EX
.test_ex_RegDst_ID(test_ex_RegDst_ID),
.test_ex_ALUOp_ID(test_ex_ALUOp_ID),
.test_ex_ALUSrc_ID(test_ex_ALUSrc_ID),
////Datos
.test_sign_extend_ID(test_sign_extend_ID),
//ID-EX
////Control signals
.test_wb_RegWrite_ID_EX_out(test_wb_RegWrite_ID_EX_out),
.test_wb_MemtoReg_ID_EX_out(test_wb_MemtoReg_ID_EX_out),
.test_m_Jump_ID_EX_out(test_m_Jump_ID_EX_out),
.test_m_Branch_ID_EX_out(test_m_Branch_ID_EX_out),
.test_m_MemRead_ID_EX_out(test_m_MemRead_ID_EX_out),
.test_m_MemWrite_ID_EX_out(test_m_MemWrite_ID_EX_out),
.test_ex_RegDst_ID_EX_out(test_ex_RegDst_ID_EX_out),
.test_ex_ALUOp_ID_EX_out(test_ex_ALUOp_ID_EX_out),
.test_ex_ALUSrc_ID_EX_out(test_ex_ALUSrc_ID_EX_out),
////Data signals
.test_pc_incrementado_ID_EX_out(test_pc_incrementado_ID_EX_out),
.test_data1_ID_EX_out(test_data1_ID_EX_out),
.test_data2_ID_EX_out(test_data2_ID_EX_out),
.test_sign_extended_ID_EX_out(test_sign_extended_ID_EX_out),
.test_inst_15_11_ID_EX_out(test_inst_15_11_ID_EX_out),
.test_inst_20_16_ID_EX_out(test_inst_20_16_ID_EX_out),
.test_inst_25_21_ID_EX_out(test_inst_25_21_ID_EX_out),
///////For hazards
.test_ForwardAE(test_ForwardAE),
.test_ForwardBE(test_ForwardBE),
.test_stallF(test_stallF),
.test_stallD(test_stallD),
.test_flushE(test_flushE),
.test_wb_MemtoReg_IDEX(test_wb_MemtoReg_IDEX),
//EX
////Data signals
.test_alu_result_EX(test_alu_result_EX),
//EX-MEM
////Data signals
.test_alu_result_EX_MEM(test_alu_result_EX_MEM),
////Control
.test_opcode_EX_MEM(test_opcode_EX_MEM),
.test_wb_MemtoReg_EXMEM(test_wb_MemtoReg_EXMEM),
//MEM-WB
////Data signals
.test_mem_data_MEM_WB(test_mem_data_MEM_WB),
.test_reg_dest_addr_MEM_WB(test_reg_dest_addr_MEM_WB),
////Control signals
.test_memToReg_MEM_WB(test_memToReg_MEM_WB),
//WB
.test_mux_wb_data_WB(test_mux_wb_data_WB),
//Registros
.reg_16(test_reg_16),
.reg_17(test_reg_17),
.reg_18(test_reg_18),
.reg_19(test_reg_19),
.reg_20(test_reg_20)
*/
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
ciclo = 0;
ena = 1'b0;
// Wait 100 ns for global reset to finish
#2;
begin
reset = 1'b0;
//ena = 1'b0;
end
#1000
ena = 1'b1;
// Add stimulus here
end
always
begin
#1
clk=~clk;
#1
clk=~clk;
ciclo = ciclo + 1;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:user:debug_counter:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_debug_counter_0_0 (
CLK,
led
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
output wire [3 : 0] led;
debug_counter inst (
.CLK(CLK),
.led(led)
);
endmodule
|
Require Import Verdi.Verdi.
Require Import Verdi.HandlerMonad.
Require Import Verdi.NameOverlay.
Require Import Verdi.LabeledNet.
Require Import Verdi.TotalMapSimulations.
Require Import Verdi.PartialMapSimulations.
Require Import Verdi.TotalMapExecutionSimulations.
Require Import Verdi.PartialMapExecutionSimulations.
Require Import NameAdjacency.
Require Import TreeAux.
Require Import FailureRecorderStaticLabeledCorrect.
Require Import TreeStaticLabeled.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import InfSeqExt.exteq.
Require Import InfSeqExt.map.
Require Import Sumbool.
Require Import Orders.
Require Import MSetFacts.
Require Import MSetProperties.
Require Import FMapInterface.
Require Import Sorting.Permutation.
Require Import mathcomp.ssreflect.ssreflect.
Require Import mathcomp.ssreflect.ssrbool.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Set Implicit Arguments.
Module TreeCorrect (Import NT : NameType)
(NOT : NameOrderedType NT) (NSet : MSetInterface.S with Module E := NOT)
(NOTC : NameOrderedTypeCompat NT) (NMap : FMapInterface.S with Module E := NOTC)
(Import RNT : RootNameType NT)
(Import ANT : AdjacentNameType NT) (Import A : Adjacency NT NOT NSet ANT)
(Import TA : TAux NT NOT NSet NOTC NMap).
Module NSetFacts := Facts NSet.
Module NSetProps := Properties NSet.
Module NSetOrdProps := OrdProperties NSet.
Require Import FMapFacts.
Module NMapFacts := Facts NMap.
Module FRC := FailureRecorderCorrect NT NOT NSet ANT A.
Module FR := FRC.FR.
Module TR := Tree NT NOT NSet NOTC NMap RNT ANT A TA.
Import TR.
Instance Tree_FailureRecorder_base_params_pt_map : BaseParamsPartialMap Tree_BaseParams FR.FailureRecorder_BaseParams :=
{
pt_map_data := fun d => FR.mkData d.(adjacent) ;
pt_map_input := fun _ => None ;
pt_map_output := fun _ => None
}.
Instance Tree_FailureRecorder_name_tot_map : MultiParamsNameTotalMap Tree_MultiParams FR.FailureRecorder_MultiParams :=
{
tot_map_name := id ;
tot_map_name_inv := id ;
}.
Instance Tree_FailureRecorder_name_tot_map_bijective : MultiParamsNameTotalMapBijective Tree_FailureRecorder_name_tot_map :=
{
tot_map_name_inv_inverse := fun _ => Logic.eq_refl ;
tot_map_name_inverse_inv := fun _ => Logic.eq_refl
}.
Instance Tree_FailureRecorder_multi_params_pt_map : MultiParamsMsgPartialMap Tree_MultiParams FR.FailureRecorder_MultiParams :=
{
pt_map_msg := fun m => match m with Fail => Some FR.Fail | _ => None end ;
}.
Instance Tree_FailureRecorder_multi_params_pt_map_congruency : MultiParamsPartialMapCongruency Tree_FailureRecorder_base_params_pt_map Tree_FailureRecorder_name_tot_map Tree_FailureRecorder_multi_params_pt_map :=
{
pt_init_handlers_eq := _ ;
pt_net_handlers_some := _ ;
pt_net_handlers_none := _ ;
pt_input_handlers_some := _ ;
pt_input_handlers_none := _
}.
Proof.
- by move => n; rewrite /= /InitData /=; break_if.
- move => me src mg st mg' H_eq.
rewrite /pt_mapped_net_handlers.
repeat break_let.
case H_n: net_handlers => [[out st'] ps].
rewrite /net_handlers /= /runGenHandler_ignore /= /unlabeled_net_handlers /lb_net_handlers /= /runGenHandler /id in Heqp H_n.
repeat break_let.
repeat tuple_inversion.
destruct st'.
by net_handler_cases; FR.net_handler_cases; simpl in *; congruence.
- move => me src mg st out st' ps H_eq H_eq'.
rewrite /= /runGenHandler_ignore /unlabeled_net_handlers /= /runGenHandler /= in H_eq'.
repeat break_let.
repeat tuple_inversion.
destruct st'.
by net_handler_cases; simpl in *; congruence.
- move => me inp st inp' H_eq.
rewrite /pt_mapped_input_handlers.
repeat break_let.
case H_i: input_handlers => [[out st'] ps].
rewrite /= /runGenHandler_ignore /= /unlabeled_input_handlers /lb_input_handlers /= /runGenHandler in Heqp H_i.
repeat break_let.
repeat tuple_inversion.
by io_handler_cases.
- move => me inp st out st' ps H_eq H_eq'.
rewrite /= /runGenHandler_ignore /= /unlabeled_input_handlers /lb_input_handlers /= /runGenHandler in H_eq'.
repeat break_let.
repeat tuple_inversion.
destruct st'.
io_handler_cases; simpl in *; try congruence.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: NSet.elements => //=.
move => n l IH.
rewrite /flip /= /level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg).
by rewrite filterMap_app /= IH.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: NSet.elements => //=.
move => n l IH.
rewrite /flip /= /level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg).
by rewrite filterMap_app /= IH.
Qed.
Instance Tree_FailureRecorder_fail_msg_params_pt_map_congruency : FailMsgParamsPartialMapCongruency Tree_FailMsgParams FR.FailureRecorder_FailMsgParams Tree_FailureRecorder_multi_params_pt_map :=
{
pt_fail_msg_fst_snd := Logic.eq_refl
}.
Instance Tree_FailureRecorder_name_overlay_params_tot_map_congruency : NameOverlayParamsTotalMapCongruency Tree_NameOverlayParams FR.FailureRecorder_NameOverlayParams Tree_FailureRecorder_name_tot_map :=
{
tot_adjacent_to_fst_snd := fun _ _ => conj (fun H => H) (fun H => H)
}.
Theorem Tree_Failed_pt_mapped_simulation_star_1 :
forall net failed tr,
@step_ordered_failure_star _ _ _ Tree_FailMsgParams step_ordered_failure_init (failed, net) tr ->
@step_ordered_failure_star _ _ _ FR.FailureRecorder_FailMsgParams step_ordered_failure_init (failed, pt_map_onet net) (filterMap pt_map_trace_ev tr).
Proof.
move => onet failed tr H_st.
apply step_ordered_failure_pt_mapped_simulation_star_1 in H_st.
by rewrite map_id in H_st.
Qed.
Instance Tree_FailureRecorder_label_tot_map : LabeledMultiParamsLabelTotalMap Tree_LabeledMultiParams FR.FailureRecorder_LabeledMultiParams :=
{
tot_map_label := fun lb =>
match lb with
| Tau => FR.Tau
| RecvFail dst src => FR.RecvFail dst src
| RecvLevel _ _ => FR.Tau
| DeliverBroadcastTrue _ => FR.Tau
| DeliverBroadcastFalse _ => FR.Tau
| DeliverLevelRequest _ => FR.Tau
end
}.
Instance Tree_FailureRecorder_labeled_partial_map_congruency : LabeledMultiParamsPartialMapCongruency Tree_FailureRecorder_base_params_pt_map Tree_FailureRecorder_name_tot_map Tree_FailureRecorder_multi_params_pt_map Tree_FailureRecorder_label_tot_map :=
{
pt_lb_label_silent_fst_snd := Logic.eq_refl ;
pt_lb_net_handlers_some := _ ;
pt_lb_net_handlers_none := _ ;
pt_lb_input_handlers_some := _ ;
pt_lb_input_handlers_none := _
}.
Proof.
- move => me src m st m' out st' ps lb H_m H_eq.
rewrite /lb_net_handlers /= /runGenHandler /= /id /= in H_eq.
rewrite /tot_mapped_lb_net_handlers_label /= /runGenHandler /=.
case H_n: NetHandler => [[[lb' out'] st''] ps'].
by net_handler_cases; FR.net_handler_cases; simpl in *; congruence.
- move => me src m st H_eq.
rewrite /tot_mapped_lb_net_handlers_label /= /runGenHandler /=.
case H_n: NetHandler => [[[lb out] st'] ps].
by net_handler_cases.
- move => me inp st inp' out st' ps lb H_i H_eq.
rewrite /tot_mapped_lb_input_handlers_label /= /runGenHandler /=.
case H_inp: IOHandler => [[[lb' out'] st''] ps'].
by io_handler_cases.
- move => me inp st H_eq.
rewrite /tot_mapped_lb_input_handlers_label /= /runGenHandler /=.
case H_inp: IOHandler => [[[lb' out'] st''] ps'].
by io_handler_cases.
Qed.
Lemma Tree_node_not_adjacent_self :
forall net failed tr n,
step_ordered_failure_star step_ordered_failure_init (failed, net) tr ->
~ In n failed ->
~ NSet.In n (onwState net n).(adjacent).
Proof.
move => onet failed tr n H_st H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact: FRC.Failure_node_not_adjacent_self H_st' H_in_f.
Qed.
Lemma Tree_not_failed_no_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In Fail (onet.(onwPackets) n n').
Proof.
move => onet failed tr H_st n n' H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_not_failed_no_fail H_st' n n' H_in_f.
move => H_in.
case: H_inv'.
rewrite /= /id /=.
move: H_in.
exact: in_msg_filterMap_pt_map_msg.
Qed.
Lemma Tree_in_adj_adjacent_to :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
adjacent_to n' n.
Proof.
move => net failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact (FRC.Failure_in_adj_adjacent_to H_st' n H_in_f H_ins).
Qed.
Lemma Tree_pt_map_msg_injective :
forall m0 m1 m2 : msg,
pt_map_msg m0 = Some m2 -> pt_map_msg m1 = Some m2 -> m0 = m1.
Proof.
by case => [|lvo]; case => [|lvo'] H_eq.
Qed.
Lemma Tree_in_adj_or_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
~ In n' failed \/ (In n' failed /\ In Fail (onet.(onwPackets) n' n)).
Proof.
move => net failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_in_adj_or_incoming_fail H_st' _ H_in_f H_ins.
case: H_inv' => H_inv'; first by left.
right.
move: H_inv' => [H_in_f' H_inv'].
split => //.
move: H_inv'.
apply: in_filterMap_pt_map_msg_in_msg; last exact: pt_fail_msg_fst_snd.
exact: Tree_pt_map_msg_injective.
Qed.
Lemma Tree_le_one_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
count_occ Msg_eq_dec (onet.(onwPackets) n' n) Fail <= 1.
Proof.
move => onet failed tr H_st n n' H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_le_one_fail H_st' _ n' H_in_f.
rewrite /= /id /= in H_inv'.
move: H_inv'.
set c1 := count_occ _ _ _.
set c2 := count_occ _ _ _.
suff H_suff: c1 = c2 by rewrite -H_suff.
rewrite /c1 /c2 {c1 c2}.
apply: count_occ_filterMap_pt_map_msg_eq => //.
exact: Tree_pt_map_msg_injective.
Qed.
Lemma Tree_adjacent_to_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In n' failed ->
adjacent_to n' n ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_in_f' H_adj.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact: (FRC.Failure_adjacent_to_in_adj H_st' H_in_f H_in_f' H_adj).
Qed.
Lemma Tree_in_queue_fail_then_adjacent :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
In Fail (onet.(onwPackets) n' n) ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_in_queue_fail_then_adjacent H_st' _ n' H_in_f.
apply: H_inv'.
rewrite /= /id /=.
move: H_ins.
exact: in_msg_filterMap_pt_map_msg.
Qed.
Lemma Tree_first_fail_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
head (onet.(onwPackets) n' n) = Some Fail ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_eq.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_first_fail_in_adj H_st' _ n' H_in_f.
apply: H_inv'.
rewrite /= /id /=.
move: H_eq.
exact: hd_error_filterMap_pt_map_msg.
Qed.
Lemma Tree_adjacent_failed_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
In n' failed ->
In Fail (onet.(onwPackets) n' n).
Proof.
move => onet failed tr H_st n n' H_in_f H_adj H_in_f'.
have H_or := Tree_in_adj_or_incoming_fail H_st _ H_in_f H_adj.
case: H_or => H_or //.
by move: H_or => [H_in H_in'].
Qed.
(* bfs_net_ok_root_levels_empty *)
Lemma Tree_root_levels_empty :
forall net failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, net) tr ->
forall n, ~ In n failed ->
root n ->
(net.(onwState) n).(levels) = NMap.empty lv.
Proof.
move => onet failed tr H.
have H_eq_f: failed = fst (failed, onet) by [].
have H_eq_o: onet = snd (failed, onet) by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in *.
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => H_init {failed}.
rewrite H_init /=.
move => n H_in H_r.
rewrite /InitData /=.
by break_if.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases => //= ; simpl in *;
update_destruct_max_simplify; repeat find_rewrite; auto.
- find_apply_lem_hyp input_handlers_IOHandler; break_exists.
io_handler_cases => //=; simpl in *;
update_destruct_max_simplify; repeat find_rewrite; auto.
- intros. simpl in *.
eauto.
Qed.
Definition head_message_enables_label m src dst l :=
forall net failed,
~ In dst failed ->
head (net.(onwPackets) src dst) = Some m ->
lb_step_ex lb_step_ordered_failure l (failed, net).
Lemma Fail_enables_RecvFail :
forall src dst, head_message_enables_label Fail src dst (RecvFail dst src).
Proof.
move => src dst.
rewrite /head_message_enables_label.
move => net failed H_f H_eq.
case H_eq_p: (onwPackets net src dst) => [|m ms]; first by find_rewrite.
find_rewrite.
simpl in *.
find_injection.
rewrite /enabled.
case H_hnd: (@lb_net_handlers _ Tree_LabeledMultiParams dst src Fail (onwState net dst)) => [[[lb' out] d'] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
by net_handler_cases => //;
exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Level_enables_RecvLevel :
forall src dst lvo, head_message_enables_label (Level lvo) src dst (RecvLevel dst src).
Proof.
move => src dst lvo.
rewrite /head_message_enables_label.
move => net failed H_f H_eq.
case H_eq_p: (onwPackets net src dst) => [|m ms]; first by find_rewrite.
find_rewrite.
simpl in *.
find_injection.
rewrite /enabled.
case H_hnd: (@lb_net_handlers _ Tree_LabeledMultiParams dst src (Level lvo) (onwState net dst)) => [[[lb' out] d'] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
net_handler_cases => //; find_injection.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst (onwState net dst) |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Tree_lb_step_ordered_failure_RecvFail_enabled :
forall net net' net'' failed failed' failed'' tr tr' dst src l,
l <> RecvFail dst src ->
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
lb_step_ordered_failure (failed, net) (RecvFail dst src) (failed'', net'') tr' ->
lb_step_ex lb_step_ordered_failure (RecvFail dst src) (failed', net').
Proof.
move => net net' net'' failed failed' failed'' tr tr' dst src l H_neq H_st H_st'.
destruct l => //.
- invcs H_st => //.
* by net_handler_cases.
* by io_handler_cases.
* invcs H_st' => //; last by io_handler_cases.
have H_hd: head (onwPackets net' src dst) = Some Fail by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
io_handler_cases => //=.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
io_handler_cases => //=.
by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
by io_handler_cases => //=; find_rewrite.
exact: Fail_enables_RecvFail.
Qed.
Lemma Tree_lb_step_ordered_failure_RecvLevel_enabled :
forall net net' net'' failed failed' failed'' tr tr' dst src l,
l <> RecvLevel dst src ->
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
lb_step_ordered_failure (failed, net) (RecvLevel dst src) (failed'', net'') tr' ->
lb_step_ex lb_step_ordered_failure (RecvLevel dst src) (failed', net').
Proof.
move => net net' net'' failed failed' failed'' tr tr' dst src l H_neq H_st H_st'.
destruct l => //.
- invcs H_st => //.
* by net_handler_cases.
* by io_handler_cases.
* invcs H_st' => //; last by io_handler_cases.
have H_hd: exists lvo, head (onwPackets net' src dst) = Some (Level lvo) by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
io_handler_cases => //=.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
io_handler_cases => //=.
by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
by io_handler_cases => //=; find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
Qed.
Lemma Tree_RecvFail_enabled_weak_until_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst, enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
weak_until (now (enabled lb_step_ordered_failure (RecvFail dst src)))
(now (occurred (RecvFail dst src)))
s.
Proof.
cofix c.
case => /=.
case; case => failed net l tr s H_exec src dst.
case (Label_eq_dec l (RecvFail dst src)) => H_eq H_en.
- find_rewrite.
exact: W0.
- apply: W_tl; first by [].
apply: c; first by find_apply_lem_hyp lb_step_execution_invar.
unfold enabled in *.
unfold lb_step_ex in H_en.
break_exists.
destruct s as [e s].
inversion H_exec; subst_max.
inversion H5; subst.
destruct e, evt_a.
destruct e', evt_a.
destruct x.
simpl in *.
by apply: Tree_lb_step_ordered_failure_RecvFail_enabled; eauto.
Qed.
Lemma Tree_RecvLevel_enabled_weak_until_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst, enabled lb_step_ordered_failure (RecvLevel dst src) (hd s) ->
weak_until (now (enabled lb_step_ordered_failure (RecvLevel dst src)))
(now (occurred (RecvLevel dst src)))
s.
Proof.
cofix c.
case => /=.
case; case => failed net l tr s H_exec src dst.
case (Label_eq_dec l (RecvLevel dst src)) => H_eq H_en.
- find_rewrite.
exact: W0.
- apply: W_tl; first by [].
apply: c; first by find_apply_lem_hyp lb_step_execution_invar.
unfold enabled in *.
unfold lb_step_ex in H_en.
break_exists.
destruct s as [e s].
inversion H_exec; subst_max.
inversion H5; subst.
destruct e, evt_a.
destruct e', evt_a.
destruct x.
simpl in *.
by apply: Tree_lb_step_ordered_failure_RecvLevel_enabled; eauto.
Qed.
Lemma Tree_RecvFail_eventually_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
eventually (now (occurred (RecvFail dst src))) s.
Proof.
move => s H_exec H_fair src dst H_en.
have H_wu := Tree_RecvFail_enabled_weak_until_occurred H_exec H_en.
apply weak_until_until_or_always in H_wu.
case: H_wu; first exact: until_eventually.
move => H_al.
apply always_continuously in H_al.
apply H_fair in H_al => //.
destruct s as [x s].
by apply always_now in H_al.
Qed.
Lemma Tree_RecvLevel_eventually_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, enabled lb_step_ordered_failure (RecvLevel dst src) (hd s) ->
eventually (now (occurred (RecvLevel dst src))) s.
Proof.
move => s H_exec H_fair src dst H_en.
have H_wu := Tree_RecvLevel_enabled_weak_until_occurred H_exec H_en.
apply weak_until_until_or_always in H_wu.
case: H_wu; first exact: until_eventually.
move => H_al.
apply always_continuously in H_al.
apply H_fair in H_al => //.
destruct s as [x s].
by apply always_now in H_al.
Qed.
Lemma Tree_lb_step_ordered_failure_not_in_failed :
forall net net' failed failed' lb tr h,
~ In h failed ->
lb_step_ordered_failure (failed, net) lb (failed', net') tr ->
~ In h failed'.
Proof.
move => net net' failed failed' lb tr h H_in_f H_step.
by invcs H_step.
Qed.
Lemma Tree_not_in_failed_always :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall h, ~ In h (fst (hd s).(evt_a)) ->
always (now (fun e => ~ In h (fst e.(evt_a)))) s.
Proof.
cofix c.
move => s H_exec.
inversion H_exec => /=.
move => h H_in_f.
apply: Always; first by [].
rewrite /=.
apply: c; first by [].
rewrite /=.
destruct e, e', evt_a, evt_a0.
simpl in *.
by eapply Tree_lb_step_ordered_failure_not_in_failed; eauto.
Qed.
Lemma Tree_lb_step_ordered_failure_Fail_head_add_msg_end :
forall net net' failed failed' tr l,
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
forall dst src ms, l <> RecvFail dst src ->
onwPackets net src dst = Fail :: ms ->
exists ms' : list Msg, onwPackets net' src dst = Fail :: ms ++ ms'.
Proof.
move => net net' failed failed' tr l H_st dst src ms H_neq H_eq.
invcs H_st => //=.
- net_handler_cases => //=.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
- io_handler_cases => //=.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (Some 0)].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (level (adjacent (onwState net src)) (levels (onwState net src)))].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H0.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
Qed.
Lemma Tree_lb_step_ordered_failure_Level_head_add_msg_end :
forall net net' failed failed' tr l,
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
forall dst src lvo ms, l <> RecvLevel dst src ->
onwPackets net src dst = Level lvo :: ms ->
exists ms' : list Msg, onwPackets net' src dst = Level lvo :: ms ++ ms'.
Proof.
move => net net' failed failed' tr l H_st dst src lvo ms H_neq H_eq.
invcs H_st => //=.
- net_handler_cases => //=.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
- io_handler_cases => //=.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (Some 0)].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (level (adjacent (onwState net src)) (levels (onwState net src)))].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H0.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
Qed.
Lemma Tree_Fail_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall ms, onwPackets (snd (evt_a (hd s))) src dst = Fail :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fair src dst H_f ms H_eq.
have H_hd: head (onwPackets (snd (evt_a (hd s))) src dst) = Some Fail by find_rewrite.
have H_en := Fail_enables_RecvFail _ _ _ _ H_f H_hd.
have H_ev: eventually (now (occurred (RecvFail dst src))) s.
apply (@Tree_RecvFail_eventually_occurred _ H_exec H_fair src dst).
rewrite /enabled.
by destruct evt_a.
have H_ex: exists ms', onwPackets (snd (evt_a (hd s))) src dst = Fail :: ms ++ ms' by exists []; rewrite app_nil_r.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
have H_wu := @Tree_RecvFail_enabled_weak_until_occurred _ H_exec src dst.
move: H_wu.
set le := enabled _ _ _.
have H_le: le by rewrite /le /enabled; destruct evt_a.
move => H_wu.
concludes.
move {H_eq H_f H_hd H_en H_le le}.
elim: H_ev H_exec H_fair H_ex H_al H_wu.
* case; case; case => /= failed net l tr.
case; case; case => /= failed' net' l' tr'.
case; case; case => /= failed'' net'' l'' tr'' s0 H_occ H_exec H_fair H_ex H_al H_wu.
apply: E_next.
apply: E0.
rewrite /=.
rewrite /occurred /= in H_occ.
subst_max.
inversion H_exec; subst_max.
break_exists_name ms'.
exists ms'.
simpl in *.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
* case; case => failed net l tr.
case; case; case => failed' net' l' tr'.
case; case; case => failed'' net'' l'' tr'' s0 H_ev IH H_exec H_fair H_ex H_al H_wu.
simpl in *.
break_exists_name ms'.
case (Label_eq_dec l (RecvFail dst src)) => H_eq.
+ subst_max.
apply E_next.
apply E0.
inversion H_exec; subst_max.
simpl in *.
exists ms'.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ apply E_next.
apply IH.
-- by find_apply_lem_hyp lb_step_execution_invar.
-- by find_apply_lem_hyp weak_fairness_invar.
-- inversion H_exec; subst_max.
simpl in *.
have H_add := Tree_lb_step_ordered_failure_Fail_head_add_msg_end H2 H_eq H_ex.
break_exists.
rewrite app_assoc_reverse in H.
by exists (ms' ++ x).
-- by find_apply_lem_hyp always_invar.
-- find_apply_lem_hyp weak_until_Cons.
simpl in *.
rewrite /occurred in H_wu.
break_or_hyp; simpl in *; last by intuition.
by rewrite H in H_eq.
Qed.
Lemma Tree_Level_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall lvo ms, onwPackets (snd (evt_a (hd s))) src dst = Level lvo :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fair src dst H_f lvo ms H_eq.
have H_hd: head (onwPackets (snd (evt_a (hd s))) src dst) = Some (Level lvo) by find_rewrite.
have H_en := Level_enables_RecvLevel _ _ _ _ H_f H_hd.
have H_ev: eventually (now (occurred (RecvLevel dst src))) s.
apply (@Tree_RecvLevel_eventually_occurred _ H_exec H_fair src dst).
rewrite /enabled.
by destruct evt_a.
have H_ex: exists ms', onwPackets (snd (evt_a (hd s))) src dst = Level lvo :: ms ++ ms' by exists []; rewrite app_nil_r.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
have H_wu := @Tree_RecvLevel_enabled_weak_until_occurred _ H_exec src dst.
move: H_wu.
set le := enabled _ _ _.
have H_le: le by rewrite /le /enabled; destruct evt_a.
move => H_wu.
concludes.
move {H_eq H_f H_hd H_en H_le le}.
elim: H_ev H_exec H_fair H_ex H_al H_wu.
* case; case; case => /= failed net l tr.
case; case; case => /= failed' net' l' tr'.
case; case; case => /= failed'' net'' l'' tr'' s0 H_occ H_exec H_fair H_ex H_al H_wu.
apply: E_next.
apply: E0.
rewrite /=.
rewrite /occurred /= in H_occ.
subst_max.
inversion H_exec; subst_max.
break_exists_name ms'.
exists ms'.
simpl in *.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
* case; case => failed net l tr.
case; case; case => failed' net' l' tr'.
case; case; case => failed'' net'' l'' tr'' s0 H_ev IH H_exec H_fair H_ex H_al H_wu.
simpl in *.
break_exists_name ms'.
case (Label_eq_dec l (RecvLevel dst src)) => H_eq.
+ subst_max.
apply E_next.
apply E0.
inversion H_exec; subst_max.
simpl in *.
exists ms'.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ apply E_next.
apply IH.
-- by find_apply_lem_hyp lb_step_execution_invar.
-- by find_apply_lem_hyp weak_fairness_invar.
-- inversion H_exec; subst_max.
simpl in *.
have H_add := Tree_lb_step_ordered_failure_Level_head_add_msg_end H2 H_eq H_ex.
break_exists.
rewrite app_assoc_reverse in H.
by exists (ms' ++ x).
-- by find_apply_lem_hyp always_invar.
-- find_apply_lem_hyp weak_until_Cons.
simpl in *.
rewrite /occurred in H_wu.
break_or_hyp; simpl in *; last by intuition.
by rewrite H in H_eq.
Qed.
Lemma Tree_msg_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall m ms, onwPackets (snd (evt_a (hd s))) src dst = m :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fai src dst H_in.
case.
- move => ms H_eq.
by apply: Tree_Fail_eventually_remove_head; eauto.
- move => ms H_eq.
by apply: Tree_Level_eventually_remove_head; eauto.
Qed.
Lemma Tree_msg_in_eventually_first :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall m, In m (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (fun e => head (onwPackets (snd (evt_a e)) src dst) = Some m)) s.
Proof.
move => s H_exec H_fair src dst H_f m H_in.
find_apply_lem_hyp in_split.
break_exists_name l1.
break_exists_name l2.
elim: l1 s H_exec H_fair l2 H_in H_f => /=.
- case; case; case => failed net lb tr s H_exec H_fair l2.
rewrite /= => H_eq H_f.
apply: E0.
by rewrite /= H_eq.
- move => m' l /= IH.
case; case; case => /= failed net lb tr s.
set s' := Cons _ _.
move => H_exec H_fair l2 H_eq H_f.
have H_ev := Tree_msg_eventually_remove_head H_exec H_fair _ _ H_f H_eq.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
simpl in *.
elim: H_ev H_exec H_fair H_al.
* case; case; case => /= failed' net' lb' tr' s0 H_eq' H_exec H_fair H_al.
break_exists.
rewrite app_assoc_reverse -app_comm_cons in H.
apply always_now in H_al.
by apply: IH => //=; eauto.
* case; case => /= failed' net' lb' tr' s0 H_ev IH' H_exec H_fair H_al.
apply: E_next.
apply IH'.
+ by find_apply_lem_hyp lb_step_execution_invar.
+ by find_apply_lem_hyp weak_fairness_invar.
+ by find_apply_lem_hyp always_invar.
Qed.
Lemma Tree_Fail_in_eventually_enabled :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
In Fail (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (enabled lb_step_ordered_failure (RecvFail dst src))) s.
Proof.
move => s H_exec H_fair src dst H_f H_in.
have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H_f _ H_in.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
move: H_al H_ev.
apply: eventually_monotonic.
- move => e s0 H_al.
by find_apply_lem_hyp always_invar.
- case; case; case => failed net l tr s' H_eq.
rewrite /enabled.
simpl in *.
apply: Fail_enables_RecvFail => //.
by find_apply_lem_hyp always_now.
Qed.
Lemma Tree_Level_in_eventually_enabled :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall lvo, In (Level lvo) (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (enabled lb_step_ordered_failure (RecvLevel dst src))) s.
Proof.
move => s H_exec H_fair src dst H_f lvo H_in.
have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H_f _ H_in.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
move: H_al H_ev.
apply: eventually_monotonic.
- move => e s0 H_al.
by find_apply_lem_hyp always_invar.
- case; case; case => failed net l tr s' H_eq.
rewrite /enabled.
simpl in *.
apply: Level_enables_RecvLevel => //.
by find_apply_lem_hyp always_now.
Qed.
Lemma Tree_FailureRecorder_lb_step_execution_pt_map : forall s,
lb_step_execution lb_step_ordered_failure s ->
lb_step_execution lb_step_ordered_failure (map pt_map_onet_event s).
Proof.
apply: lb_step_execution_lb_step_ordered_failure_pt_map_onet_infseq.
exact: FR.Label_eq_dec.
Qed.
Lemma Tree_FailureRecorder_pt_map_onet_hd_step_ordered_failure_star_always :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
always (now (event_step_star step_ordered_failure step_ordered_failure_init)) (map pt_map_onet_event s).
Proof.
apply: pt_map_onet_hd_step_ordered_failure_star_always.
exact: FR.Label_eq_dec.
Qed.
Lemma Tree_lb_step_ordered_failure_enabled_weak_fairness_pt_map_onet_eventually :
forall l, tot_map_label l <> FR.Tau ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
enabled lb_step_ordered_failure (tot_map_label l) (pt_map_onet_event (hd s)) ->
eventually (now (enabled lb_step_ordered_failure l)) s.
Proof.
case => //= dst src H_neq {H_neq}.
case => [[[failed net] l]] tr s H_exec H_fair H_en.
rewrite /enabled /lb_step_ex /= map_id in H_en.
break_exists.
destruct x as [failed' net'].
invcs H => //.
unfold id in *.
rewrite /runGenHandler /= in H7.
FR.net_handler_cases.
find_injection.
simpl in *.
move {H6}.
have H_in: In Fail (onwPackets net from to).
apply: in_filterMap_pt_map_msg_in_msg.
- by case => //; case.
- by eexists.
- by rewrite H4; left.
exact: Tree_Fail_in_eventually_enabled.
Qed.
Lemma Tree_pt_map_onet_tot_map_label_event_state_strong_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
strong_fairness lb_step_ordered_failure label_silent s ->
strong_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof.
apply: pt_map_onet_tot_map_label_event_strong_fairness.
- case; first by exists Tau.
move => dst src.
by exists (RecvFail dst src).
- move => l H_neq s H_exec H_fair.
find_apply_lem_hyp strong_fairness_weak.
exact: Tree_lb_step_ordered_failure_enabled_weak_fairness_pt_map_onet_eventually.
Qed.
Lemma Tree_has_fail_not_in_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
In Fail (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually ((now (fun e => head (onwPackets (snd (evt_a e)) src dst) = Some Fail)) /\_
(always (now (fun e => ~ In Fail (List.tl (onwPackets (snd (evt_a e)) src dst)))))) s.
Proof.
Admitted.
Lemma Tree_pt_map_onet_always_enabled_continuously :
forall l : label,
tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
always (now (enabled lb_step_ordered_failure (tot_map_label l))) (map pt_map_onet_event s) ->
continuously (now (enabled lb_step_ordered_failure l)) s.
Proof.
case => //= src dst H_neq.
case; case; case => /= failed net l tr s H_exec H_fair H_al.
find_rewrite_lem map_Cons.
find_apply_lem_hyp always_Cons.
break_and.
rewrite /= /enabled /lb_step_ex /= map_id /id in H.
break_exists_name a.
break_exists_name tr'.
destruct a as [failed' net'].
invcs H; last by FR.io_handler_cases.
unfold id in *.
FR.net_handler_cases => //.
simpl in *.
find_injection.
move: H5.
set ptm := filterMap _ _.
move => H_eq_pt.
have H_in_pt: In FR.Fail ptm by find_rewrite; left.
have H_in: In Fail (onwPackets net from to).
move: H_in_pt.
apply: in_filterMap_pt_map_msg_in_msg => //.
by case => //=; case.
unfold ptm in *.
move {ptm H_in_pt}.
have H_ev := Tree_has_fail_not_in_fail H_exec H_fair _ _ H6 H_in.
elim: H_ev H0 H_exec; clearall => //=.
- by admit.
- by admit.
(* have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H6 _ H_in.
have H_al := Tree_not_in_failed_always H_exec to H6.
simpl in *.
find_apply_lem_hyp always_invar.
move {H_fair H7 H_in H6}. *)
Admitted.
Lemma Tree_pt_map_onet_tot_map_label_event_state_weak_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
weak_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof.
move => s H_star H_exec H_fair.
apply: pt_map_onet_tot_map_label_event_state_weak_fairness => //.
- case; first by exists Tau.
move => dst src.
by exists (RecvFail dst src).
- exact: Tree_pt_map_onet_always_enabled_continuously.
Qed.
Lemma Tree_lb_step_ordered_failure_continuously_no_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall src dst,
~ In dst (fst (hd s).(evt_a)) ->
continuously (now (fun e => ~ In Fail ((snd e.(evt_a)).(onwPackets) src dst))) s.
Proof.
move => s H_exec H_fair src dst H_in_f.
have H_exec_map := Tree_FailureRecorder_lb_step_execution_pt_map H_exec.
have H_w := Tree_pt_map_onet_tot_map_label_event_state_weak_fairness H_exec H_fair.
have H_map := FRC.Failure_lb_step_ordered_failure_continuously_no_fail H_exec_map H_w src dst.
move: H_map.
set ind := ~ In _ _.
move => H_map.
have H_ind: ind.
move => H_ind.
case: H_in_f.
destruct s as [e s].
simpl in *.
by rewrite map_id in H_ind.
concludes.
move: H_map.
apply continuously_map_conv.
- exact: extensional_now.
- exact: extensional_now.
- case => /= e s0.
rewrite /id /=.
move => H_in H_in'.
case: H_in.
move: H_in'.
exact: in_msg_filterMap_pt_map_msg.
Qed.
Lemma Tree_lb_step_ordered_failure_continuously_adj_not_failed :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
forall n n',
~ In n (fst (hd s).(evt_a)) ->
continuously (now (fun e =>
NSet.In n' ((snd e.(evt_a)).(onwState) n).(adjacent) ->
~ In n' (fst e.(evt_a)) /\ adjacent_to n' n)) s.
Proof.
move => s H_star H_exec H_fair src dst H_in_f.
have H_exec_map := Tree_FailureRecorder_lb_step_execution_pt_map H_exec.
have H_w := Tree_pt_map_onet_tot_map_label_event_state_weak_fairness H_exec H_fair.
have H_map := FRC.Failure_lb_step_ordered_failure_continuously_adj_not_failed _ H_exec_map H_w src dst.
move: H_map.
set ind := ~ In _ _.
set eex := event_step_star _ _ _.
move => H_map.
have H_ind: ind.
move => H_ind.
case: H_in_f.
destruct s as [e s].
simpl in *.
by rewrite map_id in H_ind.
have H_eex: eex.
rewrite /eex.
destruct s as [e s].
exact: pt_map_onet_hd_step_ordered_failure_star.
concludes.
concludes.
move: H_map.
apply continuously_map_conv.
- exact: extensional_now.
- exact: extensional_now.
- case => /= e s0.
rewrite /id map_id /=.
move => H_in H_in'.
by concludes.
Qed.
Inductive root_path_length (failed : list name) : name -> nat -> Prop :=
| root_path_length_self : forall n,
~ In n failed ->
root n ->
root_path_length failed n 0
| root_path_length_proxy : forall n n' k,
root_path_length failed n k ->
~ In n' failed ->
adjacent_to n n' ->
root_path_length failed n' (S k).
Definition min_root_path_length (failed : list name) (n : name) (k : nat) : Prop :=
root_path_length failed n k /\ (forall k', root_path_length failed n k' -> k <= k').
Lemma root_path_length_exists_root :
forall failed n k,
root_path_length failed n k ->
exists r, ~ In r failed /\ root r.
Proof.
move => failed n k.
elim => //.
move => r H_in H_eq.
by exists r.
Qed.
Lemma root_path_length_not_failed :
forall failed n k,
root_path_length failed n k ->
~ In n failed.
Proof. by move => failed n k; case. Qed.
Lemma min_root_path_length_not_adjacent_plus_2 :
forall failed n k n' k',
min_root_path_length failed n k ->
min_root_path_length failed n' k' ->
k' >= S (S k) ->
~ adjacent_to n n'.
Proof.
move => failed n k n' k' H_min H_min' H_ge H_adj.
unfold min_root_path_length in *.
repeat break_and.
have H_r: root_path_length failed n' (S k).
apply: root_path_length_proxy; eauto.
by apply: root_path_length_not_failed; eauto.
have H_r' := H0 _ H_r.
by omega.
Qed.
End TreeCorrect.
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// WISHBONE Interface Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_wb_if.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_wb_if.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_wb_if(clk, rst,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
adr, dout, rf_din, i3_din, i4_din, i6_din,
rf_we, rf_re, o3_we, o4_we, o6_we, o7_we, o8_we, o9_we,
i3_re, i4_re, i6_re
);
input clk,rst;
// WISHBONE Interface
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// Internal Interface
output [3:0] adr;
output [31:0] dout;
input [31:0] rf_din, i3_din, i4_din, i6_din;
output rf_we;
output rf_re;
output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
output i3_re, i4_re, i6_re;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] wb_data_o;
reg [31:0] dout;
reg wb_ack_o;
reg rf_we;
reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
reg i3_re, i4_re, i6_re;
reg we1, we2;
wire we;
reg re2, re1;
wire re;
////////////////////////////////////////////////////////////////////
//
// Modules
//
assign adr = wb_addr_i[5:2];
assign wb_err_o = 1'b0;
always @(posedge clk)
dout <= #1 wb_data_i;
always @(posedge clk)
case(wb_addr_i[6:2]) // synopsys parallel_case full_case
5'he: wb_data_o <= #1 i3_din;
5'hf: wb_data_o <= #1 i4_din;
5'h10: wb_data_o <= #1 i6_din;
default: wb_data_o <= #1 rf_din;
endcase
always @(posedge clk)
re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ;
assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i;
assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i;
always @(posedge clk)
wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
always @(posedge clk)
rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
always @(posedge clk)
o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
always @(posedge clk)
o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
always @(posedge clk)
o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
always @(posedge clk)
o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
always @(posedge clk)
o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
always @(posedge clk)
i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
always @(posedge clk)
i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
always @(posedge clk)
i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
endmodule
|
`timescale 1ns / 1ns
module udp_rxq
(input clk,
input [7:0] rxd, input rxdv, input rxlast,
output [7:0] qrxd, output qrxdv, output qrxlast);
// this module accepts the off-the-wire UDP payload and buffers it until
// we can determine if this was a valid UDP payload or not. (i.e., if the
// ethernet FCS matched, and if the IP and UDP headers were sane)
//////////////////////////////////////////////////////////////////
// input section
// we're getting one word per 4 clocks.
wire [3:0] rxdv_shift;
wire rxdv_d4 = rxdv_shift[3];
r #(4) rxdv_shift_r
(.c(clk), .d({rxdv_shift[2:0], rxdv}), .rst(1'b0), .en(1'b1), .q(rxdv_shift));
wire rxdv_end = ~rxdv & rxdv_d4;
wire [31:0] rxd_shift;
wire [7:0] rxd_d4 = rxd_shift[31:24];
r #(32) rxd_shift_r
(.c(clk), .rst(1'b0), .en(1'b1), .d({rxd_shift[23:0], rxd}), .q(rxd_shift));
wire rxlast_d1, rxlast_d2, rxlast_d3, rxlast_d4;
r rxlast_d1_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast), .q(rxlast_d1));
r rxlast_d2_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d1), .q(rxlast_d2));
r rxlast_d3_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d2), .q(rxlast_d3));
r rxlast_d4_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d3), .q(rxlast_d4));
wire [10:0] dfifo_usedw;
wire dfifo_empty;
wire dfifo_rdreq;
wire [8:0] dfifo_q;
scfifo #(.lpm_width(9),
.lpm_numwords(2048),
.lpm_widthu(11),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo // data fifo
(.clock(clk),
.wrreq(rxdv_d4), .data({rxdv_end, rxd_d4}),
.rdreq(dfifo_rdreq), .q(dfifo_q),
.empty(dfifo_empty),
.usedw(dfifo_usedw),
.aclr(1'b0), .sclr(1'b0));
assign qrxd = dfifo_q[7:0];
// shift through 22 samples of rxlast in case we see any that are high
// which indicates that (after potentially up to 22 octets on short packets)
// the FCS and length fields all checked out OK
// (of course this could be short-circuited for long packets; revisit this
// design if that ever matters).
localparam RXLAST_SHIFT_LEN = 26;
wire [RXLAST_SHIFT_LEN-1:0] rxlast_shift;
r #(RXLAST_SHIFT_LEN) rxlast_shift_r
(.c(clk), .en(1'b1), .rst(1'b0),
.d({rxlast_shift[RXLAST_SHIFT_LEN-2:0], rxlast_d4}), .q(rxlast_shift));
wire [RXLAST_SHIFT_LEN-1:0] rxdv_end_shift;
r #(RXLAST_SHIFT_LEN) rxdv_end_shift_r
(.c(clk), .en(1'b1), .rst(1'b0),
.d({rxdv_end_shift[RXLAST_SHIFT_LEN-2:0], rxdv_end}),
.q(rxdv_end_shift));
wire vfifo_wrreq = rxdv_end_shift[RXLAST_SHIFT_LEN-1];
wire found_rxlast = |rxlast_shift;
wire vfifo_q;
wire vfifo_rdreq, vfifo_empty;
wire [4:0] vfifo_usedw;
scfifo #(.lpm_width(1),
.lpm_numwords(32),
.lpm_widthu(5),
.lpm_showahead("ON"),
.intended_device_family("CYCLONE V")) vfifo // valid fifo
(.clock(clk),
.wrreq(vfifo_wrreq), .rdreq(vfifo_rdreq),
.empty(vfifo_empty), .usedw(vfifo_usedw),
.data(found_rxlast), .q(vfifo_q),
.aclr(1'b0), .sclr(1'b0));
//////////////////////////////////////////////////////////////////
// output section
wire pkt_draining, pkt_draining_en;
r pkt_draining_r(.c(clk), .rst(1'b0), .en(1'b1),
.d(pkt_draining_en), .q(pkt_draining));
assign pkt_draining_en = pkt_draining ?
~dfifo_q[8] : // stop when you hit a prior rxdv_end
~vfifo_empty;
assign qrxdv = pkt_draining & vfifo_q; // mask qrxdv on its rxlast flag
assign qrxlast = pkt_draining & dfifo_q[8] & vfifo_q;
assign dfifo_rdreq = pkt_draining;
assign vfifo_rdreq = pkt_draining & dfifo_q[8];
endmodule
|
/*
* File: reg_sprs.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Description:
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b£©ÊµÏÖSPRs£º
Status Register(MSR)£º
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Öжϴ¦ÀíÏà¹ØSPRsÔÚexceptÄ£¿éʵÏÖ£¬°üÀ¨EPC, BADADDR, EVEC, CAUSE, K0ºÍK1µÈ
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Original ppc405 register sets excluding GPRs including:
a. MSR
b. CSRs:
b.1) Interrupts and Exceptions (implemented at except module)
EPC, BADADDR, EVEC, CAUSE - Privileged
b.2) Timer Facilities at timer units
CYCLES, TIME
b.3) Performance Counters
INSTRET
* Task
* [TBD]SPRsµØÖ·ÒëÂëͳһÔÚ±¾Ä£¿éʵÏÖ£¿È»ºóËͳöweºÍdata_wr£¬»òrdeºÍ½ÓÊÕdata_rd
* µØÖ·À´×Ôex_inst£¬×¢ÒâÁ¬½Ó¹ØϵÔÚ¶¥²ãÄ£¿éÁ¬½ÓʱʵÏÖ£¬ÀýÈçSPRsµØÖ·µÄÖû»
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* 1£¬SPRs·ÃÎÊÖ¸ÁÊǵ¥ÖÜÆÚÖ´ÐÐÍê³É£¬½øÈëEXE½×¶Î£¬¾Í»áÕý³£wb£¬²»»á²úÉúwb_freezeµÄÇé¿ö
* 2£¬[TBD]SPRs·ÃÎÊÖ¸Áî¿ÉÄܲúÉúÖжϣ·Çsupervisorִ̬ÐÐprevilleged²Ù×÷£¨·ÃÎÊsupervisorµÄSPRs£©µÈ£¬ÐèÒª¸ù¾ÝflushpipeÈ¡Ïûд»Ø£¿
* [TBD]msr¸üÐÂÖµÊÇ·ñÐèÒªËÍÖÁexceptÄ£¿é
* [TBD]SPRs²¼Ï߻᲻»á´øÀ´ÎÊÌ⣹ý¶àioÁ¬½Ó£¬Ìæ´ú·½°¸£ºÁ½´ÎÒëÂ룬ÀýÈçÔÚexceptÄ£¿éÔÙ¶Ôspr_addrÒëÂë
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_sprs(
// Clk & Rst
clk, rst,
reg_uops, reg_addr, dat_i, spr_wb_dat,
msr,
msr_except, msr_expwe,
sig_svm_check,
epc, badaddr, evec, cause,
epc_we, badaddr_we, evec_we, cause_we,
csr_time, csr_cycle, csr_count, csr_compare,
csr_time_we, csr_cycle_we, csr_count_we, csr_compare_we,
dsurx, dsutx, dsuctrl, dsusta,
dsurx_we, dsutx_we, dsuctrl_we, dsusta_we,
spr_dat_wr_o
);
parameter width = `OPERAND_WIDTH;
//
// I/O Ports
//
input clk;
input rst;
//
// Pipeline interface
//
input [`REGOP_WIDTH-1:0] reg_uops;
input [`SPR_ADDR_WIDTH-1:0] reg_addr;
input [width-1:0] dat_i;
output [width-1:0] spr_wb_dat; // write-back data for mfspr-class instructions
//
// Interface with Exception Unit: expception request, SPRs access
//
output sig_svm_check;
input msr_expwe;
input [width-1:0] msr_except;
output [width-1:0] msr;
output dear_we;
output esr_we;
output srr0_we;
output srr1_we;
output srr2_we;
output srr3_we;
output evpr_we;
output mcsr_we;
input [width-1:0] dear;
input [width-1:0] esr;
input [width-1:0] srr0;
input [width-1:0] srr1;
input [width-1:0] srr2;
input [width-1:0] srr3;
input [width-1:0] evpr;
input [width-1:0] mcsr;
//
// timer
//
input [width-1:0] tbl, tbu, pit, tsr, tcr;
output tbl_we, tbu_we, pit_we, tsr_we, tcr_we;
//
// interface with dsu
//
input [7:0] dsurx, dsutx, dsuctrl, dsusta;
output dsurx_we, dsutx_we, dsuctrl_we, dsusta_we;
//
// To/from SPRs at core-out building blocks
//
output [width-1:0] spr_dat_wr_o;
//
// Internal regs & wires
//
reg [width-1:0] msr;
wire [width-1:0] pvr;
reg write_spr;
reg read_spr;
reg [width-1:0] spr_wb_dat;
wire [`REGOP_WIDTH-1:0] reg_uops;
wire [`SPR_ADDR_WIDTH-1:0] spr_addr;
wire pvr_sel;
wire [width-1:0] spr_dat_i;
wire [width-1:0] msr_new;
//
wire [7:0] dsurx, dsutx, dsuctrl, dsusta;
//
wire [width-1:0] tbl, tbu, pit, tsr, tcr;
//
// Generate sprs opcode
//
assign spr_addr = reg_addr;
assign spr_dat_i = dat_i; // write data to SPRs, send out by DSS or mtspr-class instructions
assign spr_dat_wr_o = dat_i; // bypass the write data to other SPRs, from GPRs via operandmux
//
// supervisor model check
// svm instructions£ºmfmsr/mtmsr, rfi/rfci, wrtee/wrteei, mfdcr/mtdcr
// msb of spr_addr must be 1'b0 under mfspr/mtspr case
// rfi/rfci is check at except module
assign sig_svm_check = msr[`pippo_MSR_PR_BITS] &
(((reg_uops == `REGOP_MTMSR) | (reg_uops == `REGOP_MFMSR)) |
(spr_addr[9] & (reg_uops == `REGOP_MFSPR) | (reg_uops == `REGOP_MFSPR)));
//
// MSR
//
// Note: 1, MSR of pippo only implemented: [PR][ME][CE][EE]
// 2, other unimplemented fields are keep to 1'b0;
// 3, reserved field operate as 405
assign msr_we = msr_expwe | (!sig_svm_check & (reg_uops == `REGOP_MTMSR) | (reg_uops == `REGOP_WRTEE));
// [TBV] msr_new logic's coding style: mux should be inferred, not priority decoder
assign msr_new[`pippo_MSR_PR_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_PR_BITS]:
msr[`pippo_MSR_PR_BITS];
assign msr_new[`pippo_MSR_ME_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_ME_BITS]:
msr[`pippo_MSR_ME_BITS];
assign msr_new[`pippo_MSR_CE_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_CE_BITS]:
msr[`pippo_MSR_CE_BITS];
// wrtee/wrteei
assign msr_new[`pippo_MSR_EE_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_EE_BITS]:
(reg_uops == `REGOP_WRTEE)? spr_dat_i[`pippo_MSR_EE_BITS]:
msr[`pippo_MSR_EE_BITS];
always @(posedge clk or posedge rst)
if (rst)
msr <= #1 `pippo_MSR_RESET;
else if (msr_expwe)
msr <= #1 msr_except;
else if (msr_we)
msr <= #1 msr_new;
//
// GP CSR
//
reg [width-1:0] uarch0, uarch1, uarch2, uarch3, uarch4, uarch5, uarch6, uarch7;
reg [width-1:0] uarch8, uarch9, uarch10, uarch11, uarch12, uarch13, uarch14, uarch15;
// SPRG0, SPRG1, SPRG2, SPRG3 - Privileged
assign uarch0_sel = (spr_addr == `pippo_CSR_UARCH0);
assign uarch1_sel = (spr_addr == `pippo_CSR_UARCH1);
assign uarch2_sel = (spr_addr == `pippo_CSR_UARCH2);
assign uarch3_sel = (spr_addr == `pippo_CSR_UARCH3);
assign uarch4_sel = (spr_addr == `pippo_CSR_UARCH4);
assign uarch5_sel = (spr_addr == `pippo_CSR_UARCH5);
assign uarch6_sel = (spr_addr == `pippo_CSR_UARCH6);
assign uarch7_sel = (spr_addr == `pippo_CSR_UARCH7);
assign uarch8_sel = (spr_addr == `pippo_CSR_UARCH8);
assign uarch9_sel = (spr_addr == `pippo_CSR_UARCH9);
assign uarch10_sel = (spr_addr == `pippo_CSR_UARCH10);
assign uarch11_sel = (spr_addr == `pippo_CSR_UARCH11);
assign uarch12_sel = (spr_addr == `pippo_CSR_UARCH12);
assign uarch13_sel = (spr_addr == `pippo_CSR_UARCH13);
assign uarch14_sel = (spr_addr == `pippo_CSR_UARCH14);
assign uarch15_sel = (spr_addr == `pippo_CSR_UARCH15);
assign uarch0_we = write_spr & uarch0_sel;
assign uarch1_we = write_spr & uarch1_sel;
assign uarch2_we = write_spr & uarch2_sel;
assign uarch3_we = write_spr & uarch3_sel;
assign uarch4_we = write_spr & uarch4_sel;
assign uarch5_we = write_spr & uarch5_sel;
assign uarch6_we = write_spr & uarch6_sel;
assign uarch7_we = write_spr & uarch7_sel;
assign uarch8_we = write_spr & uarch8_sel;
assign uarch9_we = write_spr & uarch9_sel;
assign uarch10_we = write_spr & uarch10_sel;
assign uarch11_we = write_spr & uarch11_sel;
assign uarch12_we = write_spr & uarch12_sel;
assign uarch13_we = write_spr & uarch13_sel;
assign uarch14_we = write_spr & uarch14_sel;
assign uarch15_we = write_spr & uarch15_sel;
always @(posedge clk or posedge rst) begin
if (rst)
uarch0 <= #1 `pippo_CSR_UARCH0_RESET;
else if (uarch0_we)
uarch0 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch1 <= #1 `pippo_CSR_UARCH1_RESET;
else if (uarch1_we)
uarch1 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch2 <= #1 `pippo_CSR_UARCH2_RESET;
else if (uarch2_we)
uarch2 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch3 <= #1 `pippo_CSR_UARCH3_RESET;
else if (uarch3_we)
uarch3 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch4 <= #1 `pippo_CSR_UARCH4_RESET;
else if (uarch4_we)
uarch4 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch5 <= #1 `pippo_CSR_UARCH5_RESET;
else if (uarch5_we)
uarch5 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch6 <= #1 `pippo_CSR_UARCH6_RESET;
else if (uarch6_we)
uarch6 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch7 <= #1 `pippo_CSR_UARCH7_RESET;
else if (uarch7_we)
uarch7 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch8 <= #1 `pippo_CSR_UARCH8_RESET;
else if (uarch8_we)
uarch8 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch9 <= #1 `pippo_CSR_UARCH9_RESET;
else if (uarch9_we)
uarch9 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch10 <= #1 `pippo_CSR_UARCH10_RESET;
else if (uarch10_we)
uarch10 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch11 <= #1 `pippo_CSR_UARCH11_RESET;
else if (uarch11_we)
uarch11 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch12 <= #1 `pippo_CSR_UARCH12_RESET;
else if (uarch12_we)
uarch12 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch13 <= #1 `pippo_CSR_UARCH13_RESET;
else if (uarch13_we)
uarch13 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch14 <= #1 `pippo_CSR_UARCH14_RESET;
else if (uarch14_we)
uarch14 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
uarch15 <= #1 `pippo_CSR_UARCH15_RESET;
else if (uarch15_we)
uarch15 <= #1 spr_dat_i;
end
//
// PVR: Read Only
// Implemented as combinational logic only
// [TBD] coding style, to check
assign pvr_sel = (spr_addr == `pippo_SPR_PVR);
assign pvr[`pippo_SPR_PVR_OWN_BITS] = `pippo_SPR_PVR_OWN;
assign pvr[`pippo_SPR_PVR_PCF_BITS] = `pippo_SPR_PVR_PCF;
assign pvr[`pippo_SPR_PVR_CAS_BITS] = `pippo_SPR_PVR_CAS;
assign pvr[`pippo_SPR_PVR_PCV_BITS] = `pippo_SPR_PVR_PCV;
assign pvr[`pippo_SPR_PVR_AID_BITS] = `pippo_SPR_PVR_AID;
//
// Exception SPRs Interface
//
assign dear_sel = (spr_addr == `pippo_SPR_DEAR);
assign esr_sel = (spr_addr == `pippo_SPR_ESR);
assign evpr_sel = (spr_addr == `pippo_SPR_EVPR);
assign mcsr_sel = (spr_addr == `pippo_SPR_MCSR);
assign srr0_sel = (spr_addr == `pippo_SPR_SRR0);
assign srr1_sel = (spr_addr == `pippo_SPR_SRR1);
assign srr2_sel = (spr_addr == `pippo_SPR_SRR2);
assign srr3_sel = (spr_addr == `pippo_SPR_SRR3);
assign dear_we = (write_spr && dear_sel);
assign esr_we = (write_spr && esr_sel);
assign evpr_we = (write_spr && evpr_sel);
assign mcsr_we = (write_spr && mcsr_sel);
assign srr0_we = (write_spr && srr0_sel);
assign srr1_we = (write_spr && srr1_sel);
assign srr2_we = (write_spr && srr2_sel);
assign srr3_we = (write_spr && srr3_sel);
//
// timer interface
//
assign tbl_selu = (spr_addr == `pippo_SPR_TBLU);
assign tbu_selu = (spr_addr == `pippo_SPR_TBUU);
assign tbl_sel = (spr_addr == `pippo_SPR_TBL);
assign tbl_we = (write_spr && tbl_sel);
assign tbu_sel = (spr_addr == `pippo_SPR_TBU);
assign tbu_we = (write_spr && tbu_sel);
assign pit_sel = (spr_addr == `pippo_SPR_PIT);
assign pit_we = (write_spr && pit_sel);
assign tsr_sel = (spr_addr == `pippo_SPR_TSR);
assign tsr_we = (write_spr && tsr_sel);
assign tcr_sel = (spr_addr == `pippo_SPR_TCR);
assign tcr_we = (write_spr && tcr_sel);
//
// DSU interface
//
assign dsurx_sel = (spr_addr == `pippo_SPR_DSURX);
assign dsurx_we = (write_spr && dsurx_sel);
assign dsutx_sel = (spr_addr == `pippo_SPR_DSUTX);
assign dsutx_we = (write_spr && dsutx_sel);
assign dsuctrl_sel = (spr_addr == `pippo_SPR_DSUCTRL);
assign dsuctrl_we = (write_spr && dsuctrl_sel);
assign dsusta_sel = (spr_addr == `pippo_SPR_DSUSTA);
assign dsusta_we = (write_spr && dsusta_sel);
//
// MTSPR/MFSPR interface
//
always @(reg_uops or spr_addr or msr or pvr or
dear or esr or evpr or mcsr or srr0 or srr1 or srr2 or srr3 or
usprg0 or sprg0 or sprg1 or sprg2 or sprg3 or sprg4 or sprg5 or
sprg6 or sprg7 or dsurx or dsutx or dsuctrl or dsusta or
tbl or tbu or pit or tsr or tcr or
dear_sel or esr_sel or evpr_sel or mcsr_sel or srr0_sel or srr1_sel or
srr2_sel or srr3_sel or pvr_sel or
usprg0_sel or sprg0_sel or sprg1_sel or sprg2_sel or sprg3_sel or
sprg4_sel or sprg5_sel or sprg6_sel or sprg7_sel or
sprg4_selu or sprg5_selu or sprg6_selu or sprg7_selu or
tbl_sel or tbl_selu or tbu_sel or tbu_selu or pit_sel or tsr_sel or tcr_sel or
dsurx_sel or dsutx_sel or dsuctrl_sel or dsusta_sel) begin
write_spr = 1'b0;
read_spr = 1'b0;
spr_wb_dat = 64'b0;
case (reg_uops) // synopsys parallel_case
`REGOP_MFMSR : begin
write_spr = 1'b0;
read_spr = 1'b1;
spr_wb_dat = msr;
end
`REGOP_MFSPR : begin
write_spr = 1'b0;
read_spr = 1'b1;
casex (1) // synopsys parallel_case
pvr_sel:
spr_wb_dat = pvr;
usprg0_sel:
spr_wb_dat = usprg0;
sprg0_sel:
spr_wb_dat = sprg0;
sprg1_sel:
spr_wb_dat = sprg1;
sprg2_sel:
spr_wb_dat = sprg2;
sprg3_sel:
spr_wb_dat = sprg3;
sprg4_sel, sprg4_selu:
spr_wb_dat = sprg4;
sprg5_sel, sprg5_selu:
spr_wb_dat = sprg5;
sprg6_sel, sprg6_selu:
spr_wb_dat = sprg6;
sprg7_sel, sprg7_sel:
spr_wb_dat = sprg7;
dear_sel:
spr_wb_dat = dear;
esr_sel:
spr_wb_dat = esr;
evpr_sel:
spr_wb_dat = evpr;
mcsr_sel:
spr_wb_dat = mcsr;
srr0_sel:
spr_wb_dat = srr0;
srr1_sel:
spr_wb_dat = srr1;
srr2_sel:
spr_wb_dat = srr2;
srr3_sel:
spr_wb_dat = srr3;
tbl_sel, tbl_selu:
spr_wb_dat = tbl;
tbu_sel, tbu_selu:
spr_wb_dat = tbu;
pit_sel:
spr_wb_dat = pit;
tsr_sel:
spr_wb_dat = tsr;
tcr_sel:
spr_wb_dat = tcr;
dsurx_sel:
spr_wb_dat = {56'd0, dsurx};
dsutx_sel:
spr_wb_dat = {56'd0, dsutx};
dsuctrl_sel:
spr_wb_dat = {56'd0, dsuctrl};
dsusta_sel:
spr_wb_dat = {56'd0, dsusta};
default:
spr_wb_dat = 64'd0; // how to deal with CCR0/CCR1 access, to support legacy binary
endcase
end
`REGOP_MTSPR : begin
write_spr = 1'b1;
read_spr = 1'b0;
spr_wb_dat = 64'b0;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
spr_wb_dat = 64'b0;
end
endcase
end
endmodule
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