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// testbench_8.v
////////////////////////////////////////////////////////////////////////////////
// CPU testbench using the suggested program of lab 8
////////////////////////////////////////////////////////////////////////////////
// Dimitrios Paraschas ([email protected])
////////////////////////////////////////////////////////////////////////////////
// inf.uth.gr
// ce232 Computer Organization and Design
////////////////////////////////////////////////////////////////////////////////
// lab 8
// implementation of a subset of MIPS instructions executing CPU
////////////////////////////////////////////////////////////////////////////////
`include "constants.h"
`timescale 1ns/1ps
module cpu_tb;
// unchangeable parameters
// http://www.edaboard.com/thread194570.html
localparam N_REGISTERS = 32;
localparam IMS = 32;
localparam DMS = 32;
reg clock, reset; // clock and reset signals
integer i;
// CPU (clock, reset);
// module with multiple parameters
// http://www.asic-world.com/verilog/para_modules1.html
CPU #(.INSTR_MEM_SIZE(IMS), .DATA_MEM_SIZE(DMS)) CPU_0 (clock, reset);
always begin
#5;
clock = ~clock;
end
initial begin
// specify a VCD dump file and variables
// http://verilog.renerta.com/source/vrg00056.htm
$dumpfile("dumpfile_8.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
// clock and reset signals
clock = 1;
reset = 0;
// load the program to the instruction memory
//$readmemh("program_8.mhex", CPU_0.InstructionMemory_0.data);
$readmemb("program_8.mbin", CPU_0.InstructionMemory_0.data);
// TODO
// zero waiting time is preferred
//#0;
#5;
reset = 1;
// initialize the registers
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#55;
#30;
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 2) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 4) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 8) &&
(CPU_0.Registers_0.data[9] == 1) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 13) &&
(CPU_0.Registers_0.data[14] == 14) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 12) &&
(CPU_0.Registers_0.data[19] == 19) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 29) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31) &&
(CPU_0.DataMemory_0.data[16] == 12) &&
// NOTE
// the program counter would be 20 just after the program
// execution in a sinlge cycle CPU.
(CPU_0.ProgramCounter_0.pc == 32)) begin
$display("\n");
$display("program 8 completed successfully");
$display("\n");
end // if
else begin
$display("\n");
$display("program 8 failed");
$display("\n");
end // else
$finish;
end // initial
endmodule
|
module sram_router(clk, rst, Data_in_N, Data_in_S, Data_in_W, Data_in_E, Data_in_ready_N, Data_in_ready_S, Data_in_ready_W,
Data_in_ready_E, Data_out_N, Data_out_S, Data_out_W, Data_out_E,
Data_out_ready_N, Data_out_ready_S, Data_out_ready_W, Data_out_ready_E,
Data_in_valid_N, Data_in_valid_E, Data_in_valid_S, Data_in_valid_W,
Data_out_valid_N, Data_out_valid_S, Data_out_valid_W, Data_out_valid_E,
noc_locationx, noc_locationy);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
input [WIDTH-1:0] Data_in_N;
input [WIDTH-1:0] Data_in_E;
input [WIDTH-1:0] Data_in_S;
input [WIDTH-1:0] Data_in_W;
//input [WIDTH-1:0] Data_in_L;
input Data_in_ready_N;
input Data_in_ready_E;
input Data_in_ready_S;
input Data_in_ready_W;
//input Data_in_ready_L;
input Data_in_valid_N;
input Data_in_valid_E;
input Data_in_valid_S;
input Data_in_valid_W;
input [1:0] noc_locationx;
input [1:0] noc_locationy;
output [WIDTH-1:0] Data_out_N;
output [WIDTH-1:0] Data_out_E;
output [WIDTH-1:0] Data_out_S;
output [WIDTH-1:0] Data_out_W;
//output [WIDTH-1:0] Data_out_L;
output Data_out_ready_N;
output Data_out_ready_E;
output Data_out_ready_S;
output Data_out_ready_W;
//output Data_out_ready_L;
output Data_out_valid_N;
output Data_out_valid_E;
output Data_out_valid_S;
output Data_out_valid_W;
wire sram_out_en;
wire [4:0] Data_in_valid;
assign Data_in_valid[4] = sram_out_en;
assign Data_in_valid[3] = Data_in_valid_W;
assign Data_in_valid[2] = Data_in_valid_S;
assign Data_in_valid[1] = Data_in_valid_E;
assign Data_in_valid[0] = Data_in_valid_N;
wire [WIDTH-1:0] Data_router2sram;
wire [WIDTH-1:0] Data_sram2router;
wire Ready_router2sram;
wire Ready_sram2router;
wire [5*WIDTH-1:0] Data_out;
assign Data_out_N = Data_out[WIDTH-1:0];
assign Data_out_E = Data_out[2*WIDTH-1:WIDTH];
assign Data_out_S = Data_out[3*WIDTH-1:2*WIDTH];
assign Data_out_W = Data_out[4*WIDTH-1:3*WIDTH];
assign Data_router2sram = Data_out[5*WIDTH-1:4*WIDTH];
wire [4:0] Data_out_ready;
assign Data_out_ready[0] = Data_out_ready_N;
assign Data_out_ready[1] = Data_out_ready_E;
assign Data_out_ready[2] = Data_out_ready_S;
assign Data_out_ready[3] = Data_out_ready_W;
assign Data_out_ready[4] = Ready_router2sram;
wire [4:0] Data_out_valid;
assign Data_out_valid_N = Data_out_valid[0];
assign Data_out_valid_E = Data_out_valid[1] ;
assign Data_out_valid_S = Data_out_valid[2] ;
assign Data_out_valid_W = Data_out_valid[3] ;
wire [5*WIDTH-1:0] Data_in;
assign Data_in[WIDTH-1:0] = Data_in_N;
assign Data_in[2*WIDTH-1:WIDTH] = Data_in_E;
assign Data_in[3*WIDTH-1:2*WIDTH] = Data_in_S;
assign Data_in[4*WIDTH-1:3*WIDTH] = Data_in_W;
assign Data_in[5*WIDTH-1:4*WIDTH] = Data_sram2router;
/*reg [5*WIDTH-1:0] Data_in;
always@*
begin
Data_in[WIDTH-1:0] = Data_in_N;
Data_in[2*WIDTH-1:WIDTH] = Data_in_S;
Data_in[3*WIDTH-1:2*WIDTH] = Data_in_W;
Data_in[4*WIDTH-1:3*WIDTH] = Data_in_E;
Data_in[5*WIDTH-1:4*WIDTH] = Data_sram2router;
end */
//Connect to 'bustorouter_ready' of router
wire [4:0] Data_in_ready;
assign Data_in_ready[0] = Data_in_ready_N;
assign Data_in_ready[1] = Data_in_ready_E;
assign Data_in_ready[2] = Data_in_ready_S;
assign Data_in_ready[3] = Data_in_ready_W;
//assign Data_in_ready[4] = Ready_sram2router;
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
assign Data_in_ready[4] = !Data_in_valid_E;
//assign Data_in_ready[4] = 0;
//wire routertobus_valid;
wire sram_read_en;
assign sram_read_en = Data_out_valid[4];
router router0(
.clk(clk),
.reset_b(rst),
.bustorouter_data(Data_in),
.bustorouter_ready(Data_in_ready),
.bustorouter_valid(Data_in_valid),
.X(noc_locationx),
.Y(noc_locationy),
.routertobus_data(Data_out),
.routertobus_ready(),
.routertobus_valid(Data_out_valid)
);
sram sram0(
.clk(clk),
.rst(rst),
.address(Data_router2sram),
.data(Data_sram2router),
.read_en(sram_read_en),
.out_en(sram_out_en)
// Data_router2sram
// Ready_router2sram
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
VPWR,
VGND,
Q ,
Q_N ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
reg notifier ;
wire buf_Q ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ------------------------------------------------------------------
// ALL RIGHTS RESERVED
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user’s design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Project: superkdf9_simple
// File: superkdf9_simple.v
// Date: 星期三, 10 四月 2013 18:45:44 CST
// Version: 2.1
// Targeted Family: All
//
// =======================================================================
`include "system_conf.v"
`include "mm_defines.vh"
module arbiter2
#(
parameter MAX_DAT_WIDTH = 32,
parameter WBS_DAT_WIDTH = 32,
parameter WBM0_DAT_WIDTH = 32,
parameter WBM1_DAT_WIDTH = 32
)(
// Multiple Master Port0
WBM0_ADR_O,
WBM0_DAT_O,
WBM0_DAT_I,
WBM0_SEL_O,
WBM0_WE_O,
WBM0_ACK_I,
WBM0_ERR_I,
WBM0_RTY_I,
WBM0_CTI_O,
WBM0_BTE_O,
WBM0_LOCK_O,
WBM0_CYC_O,
WBM0_STB_O,
// Multiple Master Port1
WBM1_ADR_O,
WBM1_DAT_O,
WBM1_DAT_I,
WBM1_SEL_O,
WBM1_WE_O,
WBM1_ACK_I,
WBM1_ERR_I,
WBM1_RTY_I,
WBM1_CTI_O,
WBM1_BTE_O,
WBM1_LOCK_O,
WBM1_CYC_O,
WBM1_STB_O,
// Single Slave Port
WBS_ADR_I,
WBS_DAT_I,
WBS_DAT_O,
WBS_SEL_I,
WBS_WE_I,
WBS_ACK_O,
WBS_ERR_O,
WBS_RTY_O,
WBS_CTI_I,
WBS_BTE_I,
WBS_LOCK_I,
WBS_CYC_I,
WBS_STB_I,
clk,
reset
);
input clk, reset;
input [31:0]WBM0_ADR_O;
input [WBM0_DAT_WIDTH-1:0] WBM0_DAT_O;
output [WBM0_DAT_WIDTH-1:0] WBM0_DAT_I;
input [WBM0_DAT_WIDTH/8-1:0] WBM0_SEL_O;
input WBM0_WE_O;
output WBM0_ACK_I;
output WBM0_ERR_I;
output WBM0_RTY_I;
input [2:0]WBM0_CTI_O;
input [1:0]WBM0_BTE_O;
input WBM0_LOCK_O;
input WBM0_CYC_O;
input WBM0_STB_O;
input [31:0]WBM1_ADR_O;
input [WBM1_DAT_WIDTH-1:0] WBM1_DAT_O;
output [WBM1_DAT_WIDTH-1:0] WBM1_DAT_I;
input [WBM1_DAT_WIDTH/8-1:0] WBM1_SEL_O;
input WBM1_WE_O;
output WBM1_ACK_I;
output WBM1_ERR_I;
output WBM1_RTY_I;
input [2:0]WBM1_CTI_O;
input [1:0]WBM1_BTE_O;
input WBM1_LOCK_O;
input WBM1_CYC_O;
input WBM1_STB_O;
output [31:0]WBS_ADR_I;
output [WBS_DAT_WIDTH-1:0] WBS_DAT_I;
input [WBS_DAT_WIDTH-1:0] WBS_DAT_O;
output [WBS_DAT_WIDTH/8-1:0] WBS_SEL_I;
output WBS_WE_I;
input WBS_ACK_O;
input WBS_ERR_O;
input WBS_RTY_O;
output [2:0]WBS_CTI_I;
output [1:0]WBS_BTE_I;
output WBS_LOCK_I;
output WBS_CYC_I;
output WBS_STB_I;
wire [MAX_DAT_WIDTH-1:0] WBM0_DAT_I_INT;
wire [MAX_DAT_WIDTH-1:0] WBM0_DAT_O_INT;
wire [MAX_DAT_WIDTH/8-1:0] WBM0_SEL_O_INT;
wire [MAX_DAT_WIDTH-1:0] WBM1_DAT_I_INT;
wire [MAX_DAT_WIDTH-1:0] WBM1_DAT_O_INT;
wire [MAX_DAT_WIDTH/8-1:0] WBM1_SEL_O_INT;
wire [MAX_DAT_WIDTH-1:0] WBS_DAT_O_INT;
wire [MAX_DAT_WIDTH-1:0] WBS_DAT_I_INT;
wire [MAX_DAT_WIDTH/8-1:0] WBS_SEL_I_INT;
generate
if ((WBS_DAT_WIDTH == 8) && ((WBM0_DAT_WIDTH == 32) || (WBM1_DAT_WIDTH == 32))) begin
assign WBS_DAT_I = ((WBS_ADR_I[1:0] == 2'b00)
? WBS_DAT_I_INT[31:24]
: ((WBS_ADR_I[1:0] == 2'b01)
? WBS_DAT_I_INT[23:16]
: ((WBS_ADR_I[1:0] == 2'b10)
? WBS_DAT_I_INT[15:8]
: WBS_DAT_I_INT[7:0]
)));
assign WBS_SEL_I = ((WBS_ADR_I[1:0] == 2'b00)
? WBS_SEL_I_INT[3]
: ((WBS_ADR_I[1:0] == 2'b01)
? WBS_SEL_I_INT[2]
: ((WBS_ADR_I[1:0] == 2'b10)
? WBS_SEL_I_INT[1]
: WBS_SEL_I_INT[0]
)));
assign WBS_DAT_O_INT = {4{WBS_DAT_O}};
end
else begin
assign WBS_DAT_I = WBS_DAT_I_INT;
assign WBS_SEL_I = WBS_SEL_I_INT;
assign WBS_DAT_O_INT = WBS_DAT_O;
end
endgenerate
generate
if ((WBS_DAT_WIDTH == 32) && (WBM0_DAT_WIDTH == 8)) begin
assign WBM0_DAT_I = ((WBM0_ADR_O[1:0] == 2'b00)
? WBM0_DAT_I_INT[31:24]
: ((WBM0_ADR_O[1:0] == 2'b01)
? WBM0_DAT_I_INT[23:16]
: ((WBM0_ADR_O[1:0] == 2'b10)
? WBM0_DAT_I_INT[15:8]
: WBM0_DAT_I_INT[7:0]
)));
assign WBM0_DAT_O_INT = {4{WBM0_DAT_O}};
assign WBM0_SEL_O_INT = ((WBM0_ADR_O[1:0] == 2'b00)
? {WBM0_SEL_O, 3'b000}
: ((WBM0_ADR_O[1:0] == 2'b01)
? {1'b0, WBM0_SEL_O, 2'b00}
: ((WBM0_ADR_O[1:0] == 2'b10)
? {2'b00, WBM0_SEL_O, 1'b0}
: {3'b000, WBM0_SEL_O}
)));
end
else if ((WBS_DAT_WIDTH == 8) && (MAX_DAT_WIDTH == 32)) begin
assign WBM0_DAT_I = WBM0_DAT_I_INT;
assign WBM0_SEL_O_INT = {4{WBM0_SEL_O}};
assign WBM0_DAT_O_INT = {4{WBM0_DAT_O}};
end
else begin
assign WBM0_DAT_I = WBM0_DAT_I_INT;
assign WBM0_SEL_O_INT = WBM0_SEL_O;
assign WBM0_DAT_O_INT = WBM0_DAT_O;
end
endgenerate
generate
if ((WBS_DAT_WIDTH == 32) && (WBM1_DAT_WIDTH == 8)) begin
assign WBM1_DAT_I = ((WBM1_ADR_O[1:0] == 2'b00)
? WBM1_DAT_I_INT[31:24]
: ((WBM1_ADR_O[1:0] == 2'b01)
? WBM1_DAT_I_INT[23:16]
: ((WBM1_ADR_O[1:0] == 2'b10)
? WBM1_DAT_I_INT[15:8]
: WBM1_DAT_I_INT[7:0]
)));
assign WBM1_DAT_O_INT = {4{WBM1_DAT_O}};
assign WBM1_SEL_O_INT = ((WBM1_ADR_O[1:0] == 2'b00)
? {WBM1_SEL_O, 3'b000}
: ((WBM1_ADR_O[1:0] == 2'b01)
? {1'b0, WBM1_SEL_O, 2'b00}
: ((WBM1_ADR_O[1:0] == 2'b10)
? {2'b00, WBM1_SEL_O, 1'b0}
: {3'b000, WBM1_SEL_O}
)));
end
else if ((WBS_DAT_WIDTH == 8) && (MAX_DAT_WIDTH == 32)) begin
assign WBM1_DAT_I = WBM1_DAT_I_INT;
assign WBM1_SEL_O_INT = {4{WBM1_SEL_O}};
assign WBM1_DAT_O_INT = {4{WBM1_DAT_O}};
end
else begin
assign WBM1_DAT_I = WBM1_DAT_I_INT;
assign WBM1_SEL_O_INT = WBM1_SEL_O;
assign WBM1_DAT_O_INT = WBM1_DAT_O;
end
endgenerate
reg [2-1:0] selected; // which master is selected.
reg locked;
always @(posedge clk or posedge reset)
begin
if (reset) begin
selected <= #1 0;
locked <= #1 0;
end
else begin
if (selected == 0) begin
if (WBM0_STB_O) begin
selected <= #1 2'd1;
locked <= #1 WBM0_LOCK_O;
end
else if (WBM1_STB_O) begin
selected <= #1 2'd2;
locked <= #1 WBM1_LOCK_O;
end
end
else if (selected == 2'd1) begin
if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM0_CTI_O == 3'b000) || (WBM0_CTI_O == 3'b111) || locked) && !WBM0_LOCK_O) begin
selected <= #1 0;
locked <= #1 0;
end
end
else if (selected == 2'd2) begin
if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM1_CTI_O == 3'b000) || (WBM1_CTI_O == 3'b111) || locked) && !WBM1_LOCK_O) begin
selected <= #1 0;
locked <= #1 0;
end
end
end
end
assign WBS_ADR_I =
(selected == 2'd1 ? WBM0_ADR_O :
(selected == 2'd2 ? WBM1_ADR_O :
0));
assign WBS_DAT_I_INT =
(selected == 2'd1 ? WBM0_DAT_O_INT :
(selected == 2'd2 ? WBM1_DAT_O_INT :
0));
assign WBS_SEL_I_INT =
(selected == 2'd1 ? WBM0_SEL_O_INT :
(selected == 2'd2 ? WBM1_SEL_O_INT :
0));
assign WBS_WE_I =
(selected == 2'd1 ? WBM0_WE_O :
(selected == 2'd2 ? WBM1_WE_O :
0));
assign WBS_CTI_I =
(selected == 2'd1 ? WBM0_CTI_O :
(selected == 2'd2 ? WBM1_CTI_O :
0));
assign WBS_BTE_I =
(selected == 2'd1 ? WBM0_BTE_O :
(selected == 2'd2 ? WBM1_BTE_O :
0));
assign WBS_LOCK_I =
(selected == 2'd1 ? WBM0_LOCK_O :
(selected == 2'd2 ? WBM1_LOCK_O :
0));
assign WBS_CYC_I =
(selected == 2'd1 ? WBM0_CYC_O :
(selected == 2'd2 ? WBM1_CYC_O :
0));
assign WBS_STB_I =
(selected == 2'd1 ? WBM0_STB_O :
(selected == 2'd2 ? WBM1_STB_O :
0));
assign WBM0_DAT_I_INT = WBS_DAT_O_INT;
assign WBM0_ACK_I = (selected == 2'd1 ? WBS_ACK_O : 0);
assign WBM0_ERR_I = (selected == 2'd1 ? WBS_ERR_O : 0);
assign WBM0_RTY_I = (selected == 2'd1 ? WBS_RTY_O : 0);
assign WBM1_DAT_I_INT = WBS_DAT_O_INT;
assign WBM1_ACK_I = (selected == 2'd2 ? WBS_ACK_O : 0);
assign WBM1_ERR_I = (selected == 2'd2 ? WBS_ERR_O : 0);
assign WBM1_RTY_I = (selected == 2'd2 ? WBS_RTY_O : 0);
endmodule
`include "../components/lm32_top/lm32_functions.v" // for clogb2_v1
`include "../components/lm32_top/lm32_include.v" // for {IROM,DRAM}_ADDR_WIDTH
`include "../components/lm32_top/lm32_include_all.v"
`include "../components/uart_core/uart_core.v"
`include "../components/spi/wb_spi.v"
`include "../components/gpio/gpio.v"
`include "../components/gpio/tpio.v"
`include "../components/sha/sha.v"
`include "../components/sha/dbl_sha.v"
`include "../components/sha/sha_core.v"
`include "../components/alink/tx_timer.v"
`include "../components/alink/txc.v"
`include "../components/alink/alink_slave.v"
`include "../components/alink/alink_define.v"
`include "../components/alink/rxc.v"
`include "../components/alink/tx_phy.v"
`include "../components/alink/rx_phy.v"
`include "../components/alink/alink.v"
`include "../components/twi/twi_define.v"
`include "../components/twi/twi.v"
`include "../components/twi/shift.v"
`include "../components/twi/twi_core.v"
`ifdef UART_PRO_EN
`include "../components/uart_pro/async_receiver.v"
`include "../components/uart_pro/async_transmitter.v"
`include "../components/uart_pro/uart_pro_define.v"
`include "../components/uart_pro/uart_pro.v"
`include "../components/uart_pro/uart_txc.v"
`endif
`define AVALON_CARD
//module superkdf9_simple (
module mm (
ex_clk_i
, ex_clk_o
, uartSIN
, uartSOUT
, INT
, uartSIN_led
, uartSOUT_led
, NONCE_led
, uartRXRDY_N
, uartTXRDY_N
, uartRESET_N
, hubRESET_N
, spiMISO_MASTER
, spiMOSI_MASTER
, spiSS_N_MASTER
, spiSCLK_MASTER
, gpioPIO_IN
, gpioPIO_OUT
, uart_debugSIN
, uart_debugSOUT
, TX_P
, TX_N
, RX_P
, RX_N
, PWM
, TWI_SCL
, TWI_SDA
, SFT_SHCP
, SFT_DS
, SFT_STCP
, SFT_MR_N
, SFT_OE_N
, FAN_IN0
, FAN_IN1
`ifdef AVALON_CARD
, RSTN_CHIP
`endif
);
output PWM ;
input ex_clk_i;
`ifdef AVALON_CARD
output [3:0] ex_clk_o ;
`else
output ex_clk_o ;
`endif
wire clk_i , reset_n, clk25m_on;
`ifdef AVALON_CARD
wire [3:0] ex_clk_o_w;
clkgen clk (.clkin(ex_clk_i), .clk25m_on(clk25m_on), .clkout(clk_i), .clk25m(ex_clk_o), .locked(reset_n));
`else
clkgen clk (.clkin(ex_clk_i), .clk25m_on(clk25m_on), .clkout(clk_i), .clk25m(ex_clk_o), .locked(reset_n));
`endif
`ifdef AVALON_CARD
output [3:0] RSTN_CHIP;
assign RSTN_CHIP = {gpioPIO_OUT[1],gpioPIO_OUT[1],gpioPIO_OUT[1],gpioPIO_OUT[1]};
`endif
wire WATCH_DOG ;
wire [31:0] irom_q_rd, irom_q_wr;
wire [31:0] dram_q_rd, dram_q_wr /* unused */;
wire irom_clk_rd, irom_clk_wr;
wire irom_rst_rd, irom_rst_wr;
wire [31:0] irom_d_rd /* unused */, irom_d_wr;
wire [32-2-1:0] irom_addr_rd, irom_addr_wr;
wire irom_en_rd, irom_en_wr;
wire irom_write_rd, irom_write_wr;
wire dram_clk_rd, dram_clk_wr;
wire dram_rst_rd, dram_rst_wr;
wire [31:0] dram_d_rd /* unused */, dram_d_wr;
wire [32-2-1:0] dram_addr_rd, dram_addr_wr;
wire dram_en_rd, dram_en_wr;
wire dram_write_rd, dram_write_wr;
genvar i;
wire [31:0] zwire = 32'hZZZZZZZZ;
wire [31:0] zerowire = 32'h00000000;
wire [31:0] SHAREDBUS_ADR_I;
wire [31:0] SHAREDBUS_DAT_I;
wire [31:0] SHAREDBUS_DAT_O;
wire [3:0] SHAREDBUS_SEL_I;
wire SHAREDBUS_WE_I;
wire SHAREDBUS_ACK_O;
wire SHAREDBUS_ERR_O;
wire SHAREDBUS_RTY_O;
wire [2:0] SHAREDBUS_CTI_I;
wire [1:0] SHAREDBUS_BTE_I;
wire SHAREDBUS_LOCK_I;
wire SHAREDBUS_CYC_I;
wire SHAREDBUS_STB_I;
wire SHAREDBUS_en;
wire [31:0] superkdf9I_ADR_O;
wire [31:0] superkdf9I_DAT_O;
wire [31:0] superkdf9I_DAT_I;
wire [3:0] superkdf9I_SEL_O;
wire superkdf9I_WE_O;
wire superkdf9I_ACK_I;
wire superkdf9I_ERR_I;
wire superkdf9I_RTY_I;
wire [2:0] superkdf9I_CTI_O;
wire [1:0] superkdf9I_BTE_O;
wire superkdf9I_LOCK_O;
wire superkdf9I_CYC_O;
wire superkdf9I_STB_O;
wire [31:0] superkdf9D_ADR_O;
wire [31:0] superkdf9D_DAT_O;
wire [31:0] superkdf9D_DAT_I;
wire [3:0] superkdf9D_SEL_O;
wire superkdf9D_WE_O;
wire superkdf9D_ACK_I;
wire superkdf9D_ERR_I;
wire superkdf9D_RTY_I;
wire [2:0] superkdf9D_CTI_O;
wire [1:0] superkdf9D_BTE_O;
wire superkdf9D_LOCK_O;
wire superkdf9D_CYC_O;
wire superkdf9D_STB_O;
wire [31:0] superkdf9DEBUG_DAT_O;
wire superkdf9DEBUG_ACK_O;
wire superkdf9DEBUG_ERR_O;
wire superkdf9DEBUG_RTY_O;
wire superkdf9DEBUG_en;
wire [31:0] superkdf9interrupt_n;
wire [7:0] uartUART_DAT_O;
wire uartUART_ACK_O;
wire uartUART_ERR_O;
wire uartUART_RTY_O;
wire uartUART_en;
wire uartINTR;
input uartSIN;
inout uartSOUT;
output INT;
output uartRESET_N;
output hubRESET_N;
output uartRXRDY_N;
output uartTXRDY_N;
output uartSIN_led;
output uartSOUT_led;
assign uartSIN_led = ~uartSIN ;
assign uartSOUT_led= ~uartSOUT_w;
wire [31:0] spiSPI_DAT_O;
wire spiSPI_ACK_O;
wire spiSPI_ERR_O;
wire spiSPI_RTY_O;
wire spiSPI_en;
wire spiSPI_INT_O;
input spiMISO_MASTER;
output spiMOSI_MASTER;
output [1-1:0] spiSS_N_MASTER;
output spiSCLK_MASTER;
wire [31:0] gpioGPIO_DAT_O;
wire gpioGPIO_ACK_O;
wire gpioGPIO_ERR_O;
wire gpioGPIO_RTY_O;
wire gpioGPIO_en;
wire gpioIRQ_O;
input [7:0] gpioPIO_IN;
output [3:0] gpioPIO_OUT;
wire [7:0] uart_debugUART_DAT_O;
wire uart_debugUART_ACK_O;
wire uart_debugUART_ERR_O;
wire uart_debugUART_RTY_O;
wire uart_debugUART_en;
wire uart_debugINTR;
input uart_debugSIN;
output uart_debugSOUT;
//alink
output [`PHY_NUM-1:0] TX_P ;
output [`PHY_NUM-1:0] TX_N ;
input [`PHY_NUM-1:0] RX_P ;
input [`PHY_NUM-1:0] RX_N ;
output [4:0] NONCE_led ;
wire [4:0] ALINK_led ;
reg [4:0] NONCE_led_r0 ;
reg [4:0] NONCE_led_r1 ;
reg [4:0] NONCE_led_r2 ;
always @ (posedge clk_i)begin
NONCE_led_r0[0] <= RX_P[0] & RX_N[0];
NONCE_led_r0[1] <= RX_P[1] & RX_N[1];
NONCE_led_r0[2] <= RX_P[2] & RX_N[2];
NONCE_led_r0[3] <= RX_P[3] & RX_N[3];
NONCE_led_r0[4] <= RX_P[4] & RX_N[4];
NONCE_led_r1[0] <= NONCE_led_r0[0];
NONCE_led_r1[1] <= NONCE_led_r0[1];
NONCE_led_r1[2] <= NONCE_led_r0[2];
NONCE_led_r1[3] <= NONCE_led_r0[3];
NONCE_led_r1[4] <= NONCE_led_r0[4];
NONCE_led_r2[0] <= (~NONCE_led_r0[0] && NONCE_led_r1[0]) ? ~NONCE_led_r2[0] : NONCE_led_r2[0];
NONCE_led_r2[1] <= (~NONCE_led_r0[1] && NONCE_led_r1[1]) ? ~NONCE_led_r2[1] : NONCE_led_r2[1];
NONCE_led_r2[2] <= (~NONCE_led_r0[2] && NONCE_led_r1[2]) ? ~NONCE_led_r2[2] : NONCE_led_r2[2];
NONCE_led_r2[3] <= (~NONCE_led_r0[3] && NONCE_led_r1[3]) ? ~NONCE_led_r2[3] : NONCE_led_r2[3];
NONCE_led_r2[4] <= (~NONCE_led_r0[4] && NONCE_led_r1[4]) ? ~NONCE_led_r2[4] : NONCE_led_r2[4];
end
assign NONCE_led[0] = NONCE_led_r2[0] ;
assign NONCE_led[1] = NONCE_led_r2[1] ;
assign NONCE_led[2] = NONCE_led_r2[2] ;
assign NONCE_led[3] = NONCE_led_r2[3] ;
assign NONCE_led[4] = NONCE_led_r2[4] ;
//sha core
wire [31:0] shaSHA_DAT_O;
wire shaSHA_ACK_O;
wire shaSHA_ERR_O;
wire shaSHA_RTY_O;
wire shaSHA_en;
//alink core
wire [31:0] alinkALINK_DAT_O;
wire alinkALINK_ACK_O;
wire alinkALINK_ERR_O;
wire alinkALINK_RTY_O;
wire alinkALINK_en;
//twi core
inout TWI_SCL ;
inout TWI_SDA ;
wire [31:0] twiTWI_DAT_O;
wire twiTWI_ACK_O;
wire twiTWI_ERR_O;
wire twiTWI_RTY_O;
wire twiTWI_en;
wire TWI_SCL_O ;
wire TWI_SDA_OEN ;
output SFT_SHCP ;
output SFT_DS ;
output SFT_STCP ;
output SFT_MR_N ;
output SFT_OE_N ;
input FAN_IN0 ;
input FAN_IN1 ;
// Enable the FT232 and HUB
assign uartRESET_N = 1'b1;
assign hubRESET_N = 1'b1;
wire TIME0_INT ;
wire TIME1_INT ;
reg [2:0] counter;
wire sys_reset = !counter[2] || WATCH_DOG ;
always @(posedge clk_i or negedge reset_n)
if (reset_n == 1'b0)
counter <= #1 3'b000;
else
if (counter[2] == 1'b0)
counter <= #1 counter + 1'b1;
wire one_zero = 1'b0;
wire[1:0] two_zero = 2'b00;
wire[2:0] three_zero = 3'b000;
wire[3:0] four_zero = 4'b0000;
wire[31:0] thirtytwo_zero = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
arbiter2
#(
.MAX_DAT_WIDTH ( 32 )
,.WBS_DAT_WIDTH ( 32 )
,.WBM0_DAT_WIDTH ( 32 )
,.WBM1_DAT_WIDTH ( 32 )
)
arbiter (
.WBM0_ADR_O(superkdf9I_ADR_O),
.WBM0_DAT_O(superkdf9I_DAT_O[31:0]),
.WBM0_DAT_I(superkdf9I_DAT_I),
.WBM0_SEL_O(superkdf9I_SEL_O[3:0]),
.WBM0_WE_O(superkdf9I_WE_O),
.WBM0_ACK_I(superkdf9I_ACK_I),
.WBM0_ERR_I(superkdf9I_ERR_I),
.WBM0_RTY_I(superkdf9I_RTY_I),
.WBM0_CTI_O(superkdf9I_CTI_O),
.WBM0_BTE_O(superkdf9I_BTE_O),
.WBM0_LOCK_O(superkdf9I_LOCK_O),
.WBM0_CYC_O(superkdf9I_CYC_O),
.WBM0_STB_O(superkdf9I_STB_O),
.WBM1_ADR_O(superkdf9D_ADR_O),
.WBM1_DAT_O(superkdf9D_DAT_O[31:0]),
.WBM1_DAT_I(superkdf9D_DAT_I),
.WBM1_SEL_O(superkdf9D_SEL_O[3:0]),
.WBM1_WE_O(superkdf9D_WE_O),
.WBM1_ACK_I(superkdf9D_ACK_I),
.WBM1_ERR_I(superkdf9D_ERR_I),
.WBM1_RTY_I(superkdf9D_RTY_I),
.WBM1_CTI_O(superkdf9D_CTI_O),
.WBM1_BTE_O(superkdf9D_BTE_O),
.WBM1_LOCK_O(superkdf9D_LOCK_O),
.WBM1_CYC_O(superkdf9D_CYC_O),
.WBM1_STB_O(superkdf9D_STB_O),
.WBS_ADR_I(SHAREDBUS_ADR_I[31:0]),
.WBS_DAT_I(SHAREDBUS_DAT_I[31:0]),
.WBS_DAT_O(SHAREDBUS_DAT_O[31:0]),
.WBS_SEL_I(SHAREDBUS_SEL_I[3:0]),
.WBS_WE_I(SHAREDBUS_WE_I),
.WBS_ACK_O(SHAREDBUS_ACK_O),
.WBS_ERR_O(SHAREDBUS_ERR_O),
.WBS_RTY_O(SHAREDBUS_RTY_O),
.WBS_CTI_I(SHAREDBUS_CTI_I),
.WBS_BTE_I(SHAREDBUS_BTE_I),
.WBS_LOCK_I(SHAREDBUS_LOCK_I),
.WBS_CYC_I(SHAREDBUS_CYC_I),
.WBS_STB_I(SHAREDBUS_STB_I),
.clk (clk_i),
.reset (sys_reset));
assign SHAREDBUS_DAT_O =
uartUART_en ? {4{uartUART_DAT_O[7:0]}} :
spiSPI_en ? spiSPI_DAT_O :
gpioGPIO_en ? gpioGPIO_DAT_O :
uart_debugUART_en ? {4{uart_debugUART_DAT_O[7:0]}} :
shaSHA_en ? shaSHA_DAT_O :
alinkALINK_en ? alinkALINK_DAT_O :
twiTWI_en ? twiTWI_DAT_O :
0;
assign SHAREDBUS_ERR_O = SHAREDBUS_CYC_I & !(
(!uartUART_ERR_O & uartUART_en) |
(!spiSPI_ERR_O & spiSPI_en) |
(!gpioGPIO_ERR_O & gpioGPIO_en) |
(!uart_debugUART_ERR_O & uart_debugUART_en) |
(!shaSHA_ERR_O & shaSHA_en ) |
(!alinkALINK_ERR_O & alinkALINK_en ) |
(!twiTWI_ERR_O & twiTWI_en ) |
0);
assign SHAREDBUS_ACK_O =
uartUART_en ? uartUART_ACK_O :
spiSPI_en ? spiSPI_ACK_O :
gpioGPIO_en ? gpioGPIO_ACK_O :
uart_debugUART_en ? uart_debugUART_ACK_O :
shaSHA_en ? shaSHA_ACK_O :
alinkALINK_en ? alinkALINK_ACK_O :
twiTWI_en ? twiTWI_ACK_O :
0;
assign SHAREDBUS_RTY_O =
uartUART_en ? uartUART_RTY_O :
spiSPI_en ? spiSPI_RTY_O :
gpioGPIO_en ? gpioGPIO_RTY_O :
uart_debugUART_en ? uart_debugUART_RTY_O :
shaSHA_en ? shaSHA_RTY_O :
alinkALINK_en ? alinkALINK_RTY_O :
twiTWI_en ? twiTWI_RTY_O :
0;
wire [31:0] superkdf9DEBUG_DAT_I;
assign superkdf9DEBUG_DAT_I = 0;
wire [3:0] superkdf9DEBUG_SEL_I;
assign superkdf9DEBUG_SEL_I = 0;
assign superkdf9DEBUG_en = 0;
lm32_top
superkdf9(
.I_ADR_O(superkdf9I_ADR_O),
.I_DAT_O(superkdf9I_DAT_O),
.I_DAT_I(superkdf9I_DAT_I),
.I_SEL_O(superkdf9I_SEL_O),
.I_WE_O(superkdf9I_WE_O),
.I_ACK_I(superkdf9I_ACK_I),
.I_ERR_I(superkdf9I_ERR_I),
.I_RTY_I(superkdf9I_RTY_I),
.I_CTI_O(superkdf9I_CTI_O),
.I_BTE_O(superkdf9I_BTE_O),
.I_LOCK_O(superkdf9I_LOCK_O),
.I_CYC_O(superkdf9I_CYC_O),
.I_STB_O(superkdf9I_STB_O),
.D_ADR_O(superkdf9D_ADR_O),
.D_DAT_O(superkdf9D_DAT_O),
.D_DAT_I(superkdf9D_DAT_I),
.D_SEL_O(superkdf9D_SEL_O),
.D_WE_O(superkdf9D_WE_O),
.D_ACK_I(superkdf9D_ACK_I),
.D_ERR_I(superkdf9D_ERR_I),
.D_RTY_I(superkdf9D_RTY_I),
.D_CTI_O(superkdf9D_CTI_O),
.D_BTE_O(superkdf9D_BTE_O),
.D_LOCK_O(superkdf9D_LOCK_O),
.D_CYC_O(superkdf9D_CYC_O),
.D_STB_O(superkdf9D_STB_O),
.DEBUG_ADR_I(SHAREDBUS_ADR_I[31:0]),
.DEBUG_DAT_I(superkdf9DEBUG_DAT_I[31:0]),
.DEBUG_DAT_O(superkdf9DEBUG_DAT_O[31:0]),
.DEBUG_SEL_I(superkdf9DEBUG_SEL_I[3:0]),
.DEBUG_WE_I(SHAREDBUS_WE_I),
.DEBUG_ACK_O(superkdf9DEBUG_ACK_O),
.DEBUG_ERR_O(superkdf9DEBUG_ERR_O),
.DEBUG_RTY_O(superkdf9DEBUG_RTY_O),
.DEBUG_CTI_I(SHAREDBUS_CTI_I),
.DEBUG_BTE_I(SHAREDBUS_BTE_I),
.DEBUG_LOCK_I(SHAREDBUS_LOCK_I),
.DEBUG_CYC_I(SHAREDBUS_CYC_I & superkdf9DEBUG_en),
.DEBUG_STB_I(SHAREDBUS_STB_I & superkdf9DEBUG_en),
.interrupt_n(superkdf9interrupt_n),
.clk_i (clk_i), .rst_i (sys_reset),
// the exposed IROM
.irom_clk_rd(irom_clk_rd),
.irom_clk_wr(irom_clk_wr),
.irom_rst_rd(irom_rst_rd),
.irom_rst_wr(irom_rst_wr),
.irom_d_rd(irom_d_rd) /* unused */,
.irom_d_wr(irom_d_wr),
.irom_q_rd(irom_q_rd),
.irom_q_wr(irom_q_wr),
.irom_addr_rd(irom_addr_rd[`IROM_ADDR_WIDTH-1:0]),
.irom_addr_wr(irom_addr_wr[`IROM_ADDR_WIDTH-1:0]),
.irom_en_rd(irom_en_rd),
.irom_en_wr(irom_en_wr),
.irom_write_rd(irom_write_rd),
.irom_write_wr(irom_write_wr),
// the exposed DRAM
.dram_clk_rd(dram_clk_rd),
.dram_clk_wr(dram_clk_wr),
.dram_rst_rd(dram_rst_rd),
.dram_rst_wr(dram_rst_wr),
.dram_d_rd(dram_d_rd) /* unused */,
.dram_d_wr(dram_d_wr),
.dram_q_rd(dram_q_rd),
.dram_q_wr(dram_q_wr) /* unused */,
.dram_addr_rd(dram_addr_rd[`DRAM_ADDR_WIDTH-1:0]),
.dram_addr_wr(dram_addr_wr[`DRAM_ADDR_WIDTH-1:0]),
.dram_en_rd(dram_en_rd),
.dram_en_wr(dram_en_wr),
.dram_write_rd(dram_write_rd),
.dram_write_wr(dram_write_wr)
);
// VIO/ILA and ICON {{{
wire [35:0] icon_ctrl_0, icon_ctrl_1;
wire [255:0] trig0 = {
8'ha ,//[15:8]
irom_addr_rd[29:0] ,
irom_q_rd[31:0] ,
superkdf9interrupt_n[7:0]
} ;
icon icon_test(.CONTROL0(icon_ctrl_0));
ila ila_test(.CONTROL(icon_ctrl_0), .CLK(clk_i), .TRIG0(trig0)
);
//vio vio_test(.CONTROL(icon_ctrl_1), .ASYNC_OUT(intr_i));
// }}}
// IROM {{{
bram #(
.size(1+`CFG_IROM_LIMIT - `CFG_IROM_BASE_ADDRESS),
.name("irom")
) irom (
.ClockA(irom_clk_rd),
.ClockB(irom_clk_wr),
.ResetA(irom_rst_rd),
.ResetB(irom_rst_wr),
.AddressA(irom_addr_rd),
.AddressB(irom_addr_wr),
.DataInA(irom_d_rd), /* unused */
.DataInB(irom_d_wr),
.DataOutA(irom_q_rd),
.DataOutB(irom_q_wr), /* unused */
.ClockEnA(irom_en_rd),
.ClockEnB(irom_en_wr),
.WriteA(irom_write_rd),
.WriteB(irom_write_wr)
);
// }}}
// DRAM {{{
bram #(
.size(1+`CFG_DRAM_LIMIT - `CFG_DRAM_BASE_ADDRESS),
.name("irom")
) dram (
.ClockA(dram_clk_rd),
.ClockB(dram_clk_wr),
.ResetA(dram_rst_rd),
.ResetB(dram_rst_wr),
.AddressA(dram_addr_rd),
.AddressB(dram_addr_wr),
.DataInA(dram_d_rd), /* unused */
.DataInB(dram_d_wr),
.DataOutA(dram_q_rd),
.DataOutB(dram_q_wr),
.ClockEnA(dram_en_rd),
.ClockEnB(dram_en_wr),
.WriteA(dram_write_rd),
.WriteB(dram_write_wr)
);
// }}}
wire [7:0] uartUART_DAT_I;
assign uartUART_DAT_I = ((
SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_DAT_I[31:24] : ((
SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_DAT_I[23:16] : ((
SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_DAT_I[15:8] : SHAREDBUS_DAT_I[7:0])));
wire uartUART_SEL_I;
assign uartUART_SEL_I = ((
SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_SEL_I[3] : ((
SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_SEL_I[2] : ((
SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_SEL_I[1] : SHAREDBUS_SEL_I[0])));
assign uartUART_en = (SHAREDBUS_ADR_I[31:4] == 28'b1000000000000000000000010000);
wire uartSOUT_w ;
assign uartSOUT = uartSOUT_w ? 1'bz : 1'b0;
`ifndef UART_PRO_EN
uart_core
#(
.UART_WB_DAT_WIDTH(8),
.UART_WB_ADR_WIDTH(4),
.CLK_IN_MHZ(`MM_CLK_IN_MHZ),
.BAUD_RATE(115200),
.STDOUT_SIM(0),
.STDOUT_SIMFAST(0),
.LCR_DATA_BITS(8),
.LCR_STOP_BITS(1),
.LCR_PARITY_ENABLE(0),
.LCR_PARITY_ODD(0),
.LCR_PARITY_STICK(0),
.LCR_SET_BREAK(0),
.FIFO(1))
uart(
.UART_ADR_I(SHAREDBUS_ADR_I[3:0]),
.UART_DAT_I(uartUART_DAT_I[7:0]),
.UART_DAT_O(uartUART_DAT_O[7:0]),
.UART_SEL_I(uartUART_SEL_I),
.UART_WE_I(SHAREDBUS_WE_I),
.UART_ACK_O(uartUART_ACK_O),
.UART_ERR_O(uartUART_ERR_O),
.UART_RTY_O(uartUART_RTY_O),
.UART_CTI_I(SHAREDBUS_CTI_I),
.UART_BTE_I(SHAREDBUS_BTE_I),
.UART_LOCK_I(SHAREDBUS_LOCK_I),
.UART_CYC_I(SHAREDBUS_CYC_I & uartUART_en),
.UART_STB_I(SHAREDBUS_STB_I & uartUART_en),
.SIN(uartSIN),
.SOUT(uartSOUT_w),
.RXRDY_N(uartRXRDY_N),
.TXRDY_N(uartTXRDY_N),
.INTR(uartINTR),
.CLK(clk_i), .RESET(sys_reset));
`else
uart_pro U_uart_pro(
// system clock and reset
/*input */.CLK_I (clk_i ) ,
/*input */.RST_I (sys_reset ) ,
// wishbone interface signals
/*input */.PRO_CYC_I (SHAREDBUS_CYC_I & uartUART_en) ,//NC
/*input */.PRO_STB_I (SHAREDBUS_STB_I & uartUART_en) ,
/*input */.PRO_WE_I (SHAREDBUS_WE_I ) ,
/*input */.PRO_LOCK_I (SHAREDBUS_LOCK_I ) ,//NC
/*input [2:0] */.PRO_CTI_I (SHAREDBUS_CTI_I ) ,//NC
/*input [1:0] */.PRO_BTE_I (SHAREDBUS_BTE_I ) ,//NC
/*input [5:0] */.PRO_ADR_I (SHAREDBUS_ADR_I[3:0] ) ,
/*input [31:0] */.PRO_DAT_I (uartUART_DAT_I[7:0] ) ,
/*input [3:0] */.PRO_SEL_I (uartUART_SEL_I ) ,
/*output reg */.PRO_ACK_O (uartUART_ACK_O ) ,
/*output */.PRO_ERR_O (uartUART_ERR_O ) ,//const 0
/*output */.PRO_RTY_O (uartUART_RTY_O ) ,//const 0
/*output [31:0] */.PRO_DAT_O (uartUART_DAT_O[7:0] ) ,
//Uart Pro interface
/*input */.PRO_RX (uartSIN ) ,
/*output */.PRO_TX (uartSOUT_w ) ,
/*output */.PRO_INT (uartINTR )
);
`endif
wire [31:0] spiSPI_DAT_I;
assign spiSPI_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] spiSPI_SEL_I;
assign spiSPI_SEL_I = SHAREDBUS_SEL_I;
assign spiSPI_en = (SHAREDBUS_ADR_I[31:8] == 24'b100000000000000000000000);
`ifdef SPI_EN
spi
#(
.MASTER(1),
.SLAVE_NUMBER(32'h1),
.CLOCK_SEL(0),
.CLKCNT_WIDTH(6),
.INTERVAL_LENGTH(2),
.DATA_LENGTH(8),
.SHIFT_DIRECTION(0),
.CLOCK_PHASE(0),
.CLOCK_POLARITY(0))
spi(
.SPI_ADR_I(SHAREDBUS_ADR_I[31:0]),
.SPI_DAT_I(spiSPI_DAT_I[31:0]),
.SPI_DAT_O(spiSPI_DAT_O[31:0]),
.SPI_SEL_I(spiSPI_SEL_I[3:0]),
.SPI_WE_I(SHAREDBUS_WE_I),
.SPI_ACK_O(spiSPI_ACK_O),
.SPI_ERR_O(spiSPI_ERR_O),
.SPI_RTY_O(spiSPI_RTY_O),
.SPI_CTI_I(SHAREDBUS_CTI_I),
.SPI_BTE_I(SHAREDBUS_BTE_I),
.SPI_LOCK_I(SHAREDBUS_LOCK_I),
.SPI_CYC_I(SHAREDBUS_CYC_I & spiSPI_en),
.SPI_STB_I(SHAREDBUS_STB_I & spiSPI_en),
.MISO_MASTER(spiMISO_MASTER),
.MOSI_MASTER(spiMOSI_MASTER),
.SS_N_MASTER(spiSS_N_MASTER),
.SCLK_MASTER(spiSCLK_MASTER),
.SPI_INT_O(spiSPI_INT_O),
.CLK_I(clk_i), .RST_I(sys_reset));
`else
assign spiSPI_DAT_O = 'b0;
assign spiSPI_ACK_O = 'b0;
assign spiSPI_ERR_O = 'b0;
assign spiSPI_RTY_O = 'b0;
assign spiMOSI_MASTER= 'b0;
assign spiSS_N_MASTER= 'b0;
assign spiSCLK_MASTER= 'b0;
assign spiSPI_INT_O = 'b0;
`endif
wire [31:0] gpioGPIO_DAT_I;
assign gpioGPIO_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] gpioGPIO_SEL_I;
assign gpioGPIO_SEL_I = SHAREDBUS_SEL_I;
assign gpioGPIO_en = (SHAREDBUS_ADR_I[31:4] == 28'b1000000000000000000000100000);
`ifdef GPIO_EN
gpio
#(
.GPIO_WB_DAT_WIDTH(32),
.GPIO_WB_ADR_WIDTH(4),
.OUTPUT_PORTS_ONLY(0),
.INPUT_PORTS_ONLY(0),
.TRISTATE_PORTS(0),
.BOTH_INPUT_AND_OUTPUT(1),
.DATA_WIDTH(32'h1),
.INPUT_WIDTH(32'h20),
.OUTPUT_WIDTH(32'h20),
.IRQ_MODE(1),
.LEVEL(0),
.EDGE(1),
.EITHER_EDGE_IRQ(1),
.POSE_EDGE_IRQ(0),
.NEGE_EDGE_IRQ(0))
gpio(
.GPIO_ADR_I(SHAREDBUS_ADR_I[3:0]),
.GPIO_DAT_I(gpioGPIO_DAT_I[31:0]),
.GPIO_DAT_O(gpioGPIO_DAT_O[31:0]),
.GPIO_SEL_I(gpioGPIO_SEL_I[3:0]),
.GPIO_WE_I(SHAREDBUS_WE_I),
.GPIO_ACK_O(gpioGPIO_ACK_O),
.GPIO_ERR_O(gpioGPIO_ERR_O),
.GPIO_RTY_O(gpioGPIO_RTY_O),
.GPIO_CTI_I(SHAREDBUS_CTI_I),
.GPIO_BTE_I(SHAREDBUS_BTE_I),
.GPIO_LOCK_I(SHAREDBUS_LOCK_I),
.GPIO_CYC_I(SHAREDBUS_CYC_I & gpioGPIO_en),
.GPIO_STB_I(SHAREDBUS_STB_I & gpioGPIO_en),
.PIO_BOTH_IN(gpioPIO_BOTH_IN),
.PIO_BOTH_OUT(gpioPIO_BOTH_OUT),
.IRQ_O(gpioIRQ_O),
.CLK_I(clk_i), .RST_I(sys_reset));
`else
assign gpioGPIO_DAT_O = 'b0;
assign gpioGPIO_ACK_O = 'b0;
assign gpioGPIO_ERR_O = 'b0;
assign gpioGPIO_RTY_O = 'b0;
assign gpioIRQ_O = 'b0;
`endif
wire [7:0] uart_debugUART_DAT_I;
assign uart_debugUART_DAT_I = ((
SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_DAT_I[31:24] : ((
SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_DAT_I[23:16] : ((
SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_DAT_I[15:8] : SHAREDBUS_DAT_I[7:0])));
wire uart_debugUART_SEL_I;
assign uart_debugUART_SEL_I = ((
SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_SEL_I[3] : ((
SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_SEL_I[2] : ((
SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_SEL_I[1] : SHAREDBUS_SEL_I[0])));
assign uart_debugUART_en = (SHAREDBUS_ADR_I[31:4] == 28'b1000000000000000000000110000);
uart_core
#(
.UART_WB_DAT_WIDTH(8),
.UART_WB_ADR_WIDTH(4),
.CLK_IN_MHZ(`MM_CLK_IN_MHZ),
.BAUD_RATE(115200),
.STDOUT_SIM(0),
.STDOUT_SIMFAST(0),
.LCR_DATA_BITS(8),
.LCR_STOP_BITS(1),
.LCR_PARITY_ENABLE(0),
.LCR_PARITY_ODD(0),
.LCR_PARITY_STICK(0),
.LCR_SET_BREAK(0),
.FIFO(1))
uart_debug(
.UART_ADR_I(SHAREDBUS_ADR_I[3:0]),
.UART_DAT_I(uart_debugUART_DAT_I[7:0]),
.UART_DAT_O(uart_debugUART_DAT_O[7:0]),
.UART_SEL_I(uart_debugUART_SEL_I),
.UART_WE_I(SHAREDBUS_WE_I),
.UART_ACK_O(uart_debugUART_ACK_O),
.UART_ERR_O(uart_debugUART_ERR_O),
.UART_RTY_O(uart_debugUART_RTY_O),
.UART_CTI_I(SHAREDBUS_CTI_I),
.UART_BTE_I(SHAREDBUS_BTE_I),
.UART_LOCK_I(SHAREDBUS_LOCK_I),
.UART_CYC_I(SHAREDBUS_CYC_I & uart_debugUART_en),
.UART_STB_I(SHAREDBUS_STB_I & uart_debugUART_en),
.SIN(uart_debugSIN),
.SOUT(uart_debugSOUT),
.INTR(uart_debugINTR),
.CLK(clk_i), .RESET(sys_reset));
assign shaSHA_en = (SHAREDBUS_ADR_I[31:5] == 28'b100000000000000000000100000);
sha sha256(
// system clock and reset
/*input */ .CLK_I (clk_i),
/*input */ .RST_I (sys_reset),
// wishbone interface signals
/*input */ .SHA_CYC_I (SHAREDBUS_CYC_I & shaSHA_en ) ,//NC
/*input */ .SHA_STB_I (SHAREDBUS_STB_I & shaSHA_en ) ,
/*input */ .SHA_WE_I (SHAREDBUS_WE_I ) ,
/*input */ .SHA_LOCK_I(SHAREDBUS_LOCK_I ) ,//NC
/*input [2:0] */ .SHA_CTI_I (SHAREDBUS_CTI_I ) ,//NC
/*input [1:0] */ .SHA_BTE_I (SHAREDBUS_BTE_I ) ,//NC
/*input [4:0] */ .SHA_ADR_I (SHAREDBUS_ADR_I[4:0] ) ,
/*input [31:0] */ .SHA_DAT_I (SHAREDBUS_DAT_I[31:0] ) ,
/*input [3:0] */ .SHA_SEL_I (SHAREDBUS_SEL_I ) ,
/*output reg */ .SHA_ACK_O (shaSHA_ACK_O ) ,
/*output */ .SHA_ERR_O (shaSHA_ERR_O ) ,//const 0
/*output */ .SHA_RTY_O (shaSHA_RTY_O ) ,//const 0
/*output [31:0]*/ .SHA_DAT_O (shaSHA_DAT_O )
);
assign alinkALINK_en = (SHAREDBUS_ADR_I[31:6] == 26'b10000000000000000000010100);
alink alink(
// system clock and reset
/*input */ .CLK_I (clk_i) ,
/*input */ .RST_I (sys_reset) ,
// wishbone interface signals
/*input */ .ALINK_CYC_I (SHAREDBUS_CYC_I & alinkALINK_en ) ,//NC
/*input */ .ALINK_STB_I (SHAREDBUS_STB_I & alinkALINK_en ) ,
/*input */ .ALINK_WE_I (SHAREDBUS_WE_I ) ,
/*input */ .ALINK_LOCK_I(SHAREDBUS_LOCK_I ) ,//NC
/*input [2:0] */ .ALINK_CTI_I (SHAREDBUS_CTI_I ) ,//NC
/*input [1:0] */ .ALINK_BTE_I (SHAREDBUS_BTE_I ) ,//NC
/*input [5:0] */ .ALINK_ADR_I (SHAREDBUS_ADR_I[5:0] ) ,
/*input [31:0] */ .ALINK_DAT_I (SHAREDBUS_DAT_I[31:0] ) ,
/*input [3:0] */ .ALINK_SEL_I (SHAREDBUS_SEL_I ) ,
/*output */ .ALINK_ACK_O (alinkALINK_ACK_O ) ,
/*output */ .ALINK_ERR_O (alinkALINK_ERR_O ) ,//const 0
/*output */ .ALINK_RTY_O (alinkALINK_RTY_O ) ,//const 0
/*output [31:0] */ .ALINK_DAT_O (alinkALINK_DAT_O ) ,
//TX.PHY
/*output [31:0] */ .TX_P (TX_P ) ,
/*output [31:0] */ .TX_N (TX_N ) ,
//RX.PHY
/*input [31:0] */ .RX_P (RX_P ) ,
/*input [31:0] */ .RX_N (RX_N ) ,
/*output [4:0] */ .ALINK_led (ALINK_led )
);
assign twiTWI_en = (SHAREDBUS_ADR_I[31:6] == 26'b10000000000000000000011000);
assign TWI_SCL = TWI_SCL_O == 1'b0 ? 1'b0 : 1'bz ;//p85
assign TWI_SDA = TWI_SDA_OEN == 1'b0 ? 1'b0 : 1'bz ;//p8
twi u_twi(
// system clock and reset
/*input */ .CLK_I (clk_i ) ,
/*input */ .RST_I (sys_reset ) ,
// wishbone interface signals
/*input */ .TWI_CYC_I (SHAREDBUS_CYC_I & twiTWI_en ) ,//NC
/*input */ .TWI_STB_I (SHAREDBUS_STB_I & twiTWI_en ) ,
/*input */ .TWI_WE_I (SHAREDBUS_WE_I ) ,
/*input */ .TWI_LOCK_I (SHAREDBUS_LOCK_I ) ,//NC
/*input [2:0] */ .TWI_CTI_I (SHAREDBUS_CTI_I ) ,//NC
/*input [1:0] */ .TWI_BTE_I (SHAREDBUS_BTE_I ) ,//NC
/*input [5:0] */ .TWI_ADR_I (SHAREDBUS_ADR_I[5:0] ) ,
/*input [31:0] */ .TWI_DAT_I (SHAREDBUS_DAT_I[31:0] ) ,
/*input [3:0] */ .TWI_SEL_I (SHAREDBUS_SEL_I ) ,
/*output reg */ .TWI_ACK_O (twiTWI_ACK_O ) ,
/*output */ .TWI_ERR_O (twiTWI_ERR_O ) ,//const 0
/*output */ .TWI_RTY_O (twiTWI_RTY_O ) ,//const 0
/*output [31:0] */ .TWI_DAT_O (twiTWI_DAT_O ) ,
/*output */ .TWI_SCL_O (TWI_SCL_O ) ,
/*input */ .TWI_SDA_I (TWI_SDA ) ,
/*output */ .TWI_SDA_OEN (TWI_SDA_OEN ) ,
/*output */ .PWM (PWM ) ,
/*output */ .WATCH_DOG (WATCH_DOG ) ,
/*output */ .SFT_SHCP (SFT_SHCP ) ,
/*output */ .SFT_DS (SFT_DS ) ,
/*output */ .SFT_STCP (SFT_STCP ) ,
/*output */ .SFT_MR_N (SFT_MR_N ) ,
/*output */ .SFT_OE_N (SFT_OE_N ) ,
/*input */ .FAN_IN0 (FAN_IN0 ) ,
/*input */ .FAN_IN1 (FAN_IN1 ) ,
/*output */ .TIME0_INT (TIME0_INT ) ,
/*output */ .TIME1_INT (TIME1_INT ) ,
/*output */ .GPIO_OUT (gpioPIO_OUT ) ,
/*input [7:0] */ .GPIO_IN (gpioPIO_IN ) ,
/*output */ .clk25m_on (clk25m_on )
) ;
assign superkdf9interrupt_n[3] = !uartINTR ;
assign superkdf9interrupt_n[1] = !spiSPI_INT_O ;
assign superkdf9interrupt_n[0] = !gpioIRQ_O ;
assign superkdf9interrupt_n[4] = !uart_debugINTR ;
assign superkdf9interrupt_n[2] = 1;
assign superkdf9interrupt_n[5] = !TIME0_INT;
assign superkdf9interrupt_n[6] = !TIME1_INT;
assign superkdf9interrupt_n[7] = 1;
assign superkdf9interrupt_n[8] = 1;
assign superkdf9interrupt_n[9] = 1;
assign superkdf9interrupt_n[10] = 1;
assign superkdf9interrupt_n[11] = 1;
assign superkdf9interrupt_n[12] = 1;
assign superkdf9interrupt_n[13] = 1;
assign superkdf9interrupt_n[14] = 1;
assign superkdf9interrupt_n[15] = 1;
assign superkdf9interrupt_n[16] = 1;
assign superkdf9interrupt_n[17] = 1;
assign superkdf9interrupt_n[18] = 1;
assign superkdf9interrupt_n[19] = 1;
assign superkdf9interrupt_n[20] = 1;
assign superkdf9interrupt_n[21] = 1;
assign superkdf9interrupt_n[22] = 1;
assign superkdf9interrupt_n[23] = 1;
assign superkdf9interrupt_n[24] = 1;
assign superkdf9interrupt_n[25] = 1;
assign superkdf9interrupt_n[26] = 1;
assign superkdf9interrupt_n[27] = 1;
assign superkdf9interrupt_n[28] = 1;
assign superkdf9interrupt_n[29] = 1;
assign superkdf9interrupt_n[30] = 1;
assign superkdf9interrupt_n[31] = 1;
assign INT = ~(&superkdf9interrupt_n) ;
endmodule
|
(** * MoreStlc: More on the Simply Typed Lambda-Calculus *)
Require Export Stlc.
(* ###################################################################### *)
(** * Simple Extensions to STLC *)
(** The simply typed lambda-calculus has enough structure to make its
theoretical properties interesting, but it is not much of a
programming language. In this chapter, we begin to close the gap
with real-world languages by introducing a number of familiar
features that have straightforward treatments at the level of
typing. *)
(** ** Numbers *)
(** Adding types, constants, and primitive operations for numbers is
easy -- just a matter of combining the [Types] and [Stlc]
chapters. *)
(** ** [let]-bindings *)
(** When writing a complex expression, it is often useful to give
names to some of its subexpressions: this avoids repetition and
often increases readability. Most languages provide one or more
ways of doing this. In OCaml (and Coq), for example, we can write
[let x=t1 in t2] to mean ``evaluate the expression [t1] and bind
the name [x] to the resulting value while evaluating [t2].''
Our [let]-binder follows OCaml's in choosing a call-by-value
evaluation order, where the [let]-bound term must be fully
evaluated before evaluation of the [let]-body can begin. The
typing rule [T_Let] tells us that the type of a [let] can be
calculated by calculating the type of the [let]-bound term,
extending the context with a binding with this type, and in this
enriched context calculating the type of the body, which is then
the type of the whole [let] expression.
At this point in the course, it's probably easier simply to look
at the rules defining this new feature as to wade through a lot of
english text conveying the same information. Here they are: *)
(** Syntax:
<<
t ::= Terms
| ... (other terms same as before)
| let x=t in t let-binding
>>
*)
(**
Reduction:
t1 ==> t1'
---------------------------------- (ST_Let1)
let x=t1 in t2 ==> let x=t1' in t2
---------------------------- (ST_LetValue)
let x=v1 in t2 ==> [x:=v1]t2
Typing:
Gamma |- t1 : T1 Gamma , x:T1 |- t2 : T2
-------------------------------------------- (T_Let)
Gamma |- let x=t1 in t2 : T2
*)
(** ** Pairs *)
(** Our functional programming examples in Coq have made
frequent use of _pairs_ of values. The type of such pairs is
called a _product type_.
The formalization of pairs is almost too simple to be worth
discussing. However, let's look briefly at the various parts of
the definition to emphasize the common pattern. *)
(** In Coq, the primitive way of extracting the components of a pair
is _pattern matching_. An alternative style is to take [fst] and
[snd] -- the first- and second-projection operators -- as
primitives. Just for fun, let's do our products this way. For
example, here's how we'd write a function that takes a pair of
numbers and returns the pair of their sum and difference:
<<
\x:Nat*Nat.
let sum = x.fst + x.snd in
let diff = x.fst - x.snd in
(sum,diff)
>>
*)
(** Adding pairs to the simply typed lambda-calculus, then, involves
adding two new forms of term -- pairing, written [(t1,t2)], and
projection, written [t.fst] for the first projection from [t] and
[t.snd] for the second projection -- plus one new type constructor,
[T1*T2], called the _product_ of [T1] and [T2]. *)
(** Syntax:
<<
t ::= Terms
| ...
| (t,t) pair
| t.fst first projection
| t.snd second projection
v ::= Values
| ...
| (v,v) pair value
T ::= Types
| ...
| T * T product type
>>
*)
(** For evaluation, we need several new rules specifying how pairs and
projection behave.
t1 ==> t1'
-------------------- (ST_Pair1)
(t1,t2) ==> (t1',t2)
t2 ==> t2'
-------------------- (ST_Pair2)
(v1,t2) ==> (v1,t2')
t1 ==> t1'
------------------ (ST_Fst1)
t1.fst ==> t1'.fst
------------------ (ST_FstPair)
(v1,v2).fst ==> v1
t1 ==> t1'
------------------ (ST_Snd1)
t1.snd ==> t1'.snd
------------------ (ST_SndPair)
(v1,v2).snd ==> v2
*)
(**
Rules [ST_FstPair] and [ST_SndPair] specify that, when a fully
evaluated pair meets a first or second projection, the result is
the appropriate component. The congruence rules [ST_Fst1] and
[ST_Snd1] allow reduction to proceed under projections, when the
term being projected from has not yet been fully evaluated.
[ST_Pair1] and [ST_Pair2] evaluate the parts of pairs: first the
left part, and then -- when a value appears on the left -- the right
part. The ordering arising from the use of the metavariables [v]
and [t] in these rules enforces a left-to-right evaluation
strategy for pairs. (Note the implicit convention that
metavariables like [v] and [v1] can only denote values.) We've
also added a clause to the definition of values, above, specifying
that [(v1,v2)] is a value. The fact that the components of a pair
value must themselves be values ensures that a pair passed as an
argument to a function will be fully evaluated before the function
body starts executing. *)
(** The typing rules for pairs and projections are straightforward.
Gamma |- t1 : T1 Gamma |- t2 : T2
--------------------------------------- (T_Pair)
Gamma |- (t1,t2) : T1*T2
Gamma |- t1 : T11*T12
--------------------- (T_Fst)
Gamma |- t1.fst : T11
Gamma |- t1 : T11*T12
--------------------- (T_Snd)
Gamma |- t1.snd : T12
*)
(** The rule [T_Pair] says that [(t1,t2)] has type [T1*T2] if [t1] has
type [T1] and [t2] has type [T2]. Conversely, the rules [T_Fst]
and [T_Snd] tell us that, if [t1] has a product type
[T11*T12] (i.e., if it will evaluate to a pair), then the types of
the projections from this pair are [T11] and [T12]. *)
(** ** Unit *)
(** Another handy base type, found especially in languages in
the ML family, is the singleton type [Unit]. *)
(** It has a single element -- the term constant [unit] (with a small
[u]) -- and a typing rule making [unit] an element of [Unit]. We
also add [unit] to the set of possible result values of
computations -- indeed, [unit] is the _only_ possible result of
evaluating an expression of type [Unit]. *)
(** Syntax:
<<
t ::= Terms
| ...
| unit unit value
v ::= Values
| ...
| unit unit
T ::= Types
| ...
| Unit Unit type
>>
Typing:
-------------------- (T_Unit)
Gamma |- unit : Unit
*)
(** It may seem a little strange to bother defining a type that
has just one element -- after all, wouldn't every computation
living in such a type be trivial?
This is a fair question, and indeed in the STLC the [Unit] type is
not especially critical (though we'll see two uses for it below).
Where [Unit] really comes in handy is in richer languages with
various sorts of _side effects_ -- e.g., assignment statements
that mutate variables or pointers, exceptions and other sorts of
nonlocal control structures, etc. In such languages, it is
convenient to have a type for the (trivial) result of an
expression that is evaluated only for its effect. *)
(** ** Sums *)
(** Many programs need to deal with values that can take two distinct
forms. For example, we might identify employees in an accounting
application using using _either_ their name _or_ their id number.
A search function might return _either_ a matching value _or_ an
error code.
These are specific examples of a binary _sum type_,
which describes a set of values drawn from exactly two given types, e.g.
<<
Nat + Bool
>>
*)
(** We create elements of these types by _tagging_ elements of
the component types. For example, if [n] is a [Nat] then [inl n]
is an element of [Nat+Bool]; similarly, if [b] is a [Bool] then
[inr b] is a [Nat+Bool]. The names of the tags [inl] and [inr]
arise from thinking of them as functions
<<
inl : Nat -> Nat + Bool
inr : Bool -> Nat + Bool
>>
that "inject" elements of [Nat] or [Bool] into the left and right
components of the sum type [Nat+Bool]. (But note that we don't
actually treat them as functions in the way we formalize them:
[inl] and [inr] are keywords, and [inl t] and [inr t] are primitive
syntactic forms, not function applications. This allows us to give
them their own special typing rules.) *)
(** In general, the elements of a type [T1 + T2] consist of the
elements of [T1] tagged with the token [inl], plus the elements of
[T2] tagged with [inr]. *)
(** One important usage of sums is signaling errors:
<<
div : Nat -> Nat -> (Nat + Unit) =
div =
\x:Nat. \y:Nat.
if iszero y then
inr unit
else
inl ...
>>
The type [Nat + Unit] above is in fact isomorphic to [option nat]
in Coq, and we've already seen how to signal errors with options. *)
(** To _use_ elements of sum types, we introduce a [case]
construct (a very simplified form of Coq's [match]) to destruct
them. For example, the following procedure converts a [Nat+Bool]
into a [Nat]: *)
(**
<<
getNat =
\x:Nat+Bool.
case x of
inl n => n
| inr b => if b then 1 else 0
>>
*)
(** More formally... *)
(** Syntax:
<<
t ::= Terms
| ...
| inl T t tagging (left)
| inr T t tagging (right)
| case t of case
inl x => t
| inr x => t
v ::= Values
| ...
| inl T v tagged value (left)
| inr T v tagged value (right)
T ::= Types
| ...
| T + T sum type
>>
*)
(** Evaluation:
t1 ==> t1'
---------------------- (ST_Inl)
inl T t1 ==> inl T t1'
t1 ==> t1'
---------------------- (ST_Inr)
inr T t1 ==> inr T t1'
t0 ==> t0'
------------------------------------------- (ST_Case)
case t0 of inl x1 => t1 | inr x2 => t2 ==>
case t0' of inl x1 => t1 | inr x2 => t2
---------------------------------------------- (ST_CaseInl)
case (inl T v0) of inl x1 => t1 | inr x2 => t2
==> [x1:=v0]t1
---------------------------------------------- (ST_CaseInr)
case (inr T v0) of inl x1 => t1 | inr x2 => t2
==> [x2:=v0]t2
*)
(** Typing:
Gamma |- t1 : T1
---------------------------- (T_Inl)
Gamma |- inl T2 t1 : T1 + T2
Gamma |- t1 : T2
---------------------------- (T_Inr)
Gamma |- inr T1 t1 : T1 + T2
Gamma |- t0 : T1+T2
Gamma , x1:T1 |- t1 : T
Gamma , x2:T2 |- t2 : T
--------------------------------------------------- (T_Case)
Gamma |- case t0 of inl x1 => t1 | inr x2 => t2 : T
We use the type annotation in [inl] and [inr] to make the typing
simpler, similarly to what we did for functions. *)
(** Without this extra
information, the typing rule [T_Inl], for example, would have to
say that, once we have shown that [t1] is an element of type [T1],
we can derive that [inl t1] is an element of [T1 + T2] for _any_
type T2. For example, we could derive both [inl 5 : Nat + Nat]
and [inl 5 : Nat + Bool] (and infinitely many other types).
This failure of uniqueness of types would mean that we cannot
build a typechecking algorithm simply by "reading the rules from
bottom to top" as we could for all the other features seen so far.
There are various ways to deal with this difficulty. One simple
one -- which we've adopted here -- forces the programmer to
explicitly annotate the "other side" of a sum type when performing
an injection. This is rather heavyweight for programmers (and so
real languages adopt other solutions), but it is easy to
understand and formalize. *)
(** ** Lists *)
(** The typing features we have seen can be classified into _base
types_ like [Bool], and _type constructors_ like [->] and [*] that
build new types from old ones. Another useful type constructor is
[List]. For every type [T], the type [List T] describes
finite-length lists whose elements are drawn from [T].
In principle, we could encode lists using pairs, sums and
_recursive_ types. But giving semantics to recursive types is
non-trivial. Instead, we'll just discuss the special case of lists
directly.
Below we give the syntax, semantics, and typing rules for lists.
Except for the fact that explicit type annotations are mandatory
on [nil] and cannot appear on [cons], these lists are essentially
identical to those we built in Coq. We use [lcase] to destruct
lists, to avoid dealing with questions like "what is the [head] of
the empty list?" *)
(** For example, here is a function that calculates the sum of
the first two elements of a list of numbers:
<<
\x:List Nat.
lcase x of nil -> 0
| a::x' -> lcase x' of nil -> a
| b::x'' -> a+b
>>
*)
(**
Syntax:
<<
t ::= Terms
| ...
| nil T
| cons t t
| lcase t of nil -> t | x::x -> t
v ::= Values
| ...
| nil T nil value
| cons v v cons value
T ::= Types
| ...
| List T list of Ts
>>
*)
(** Reduction:
t1 ==> t1'
-------------------------- (ST_Cons1)
cons t1 t2 ==> cons t1' t2
t2 ==> t2'
-------------------------- (ST_Cons2)
cons v1 t2 ==> cons v1 t2'
t1 ==> t1'
---------------------------------------- (ST_Lcase1)
(lcase t1 of nil -> t2 | xh::xt -> t3) ==>
(lcase t1' of nil -> t2 | xh::xt -> t3)
----------------------------------------- (ST_LcaseNil)
(lcase nil T of nil -> t2 | xh::xt -> t3)
==> t2
----------------------------------------------- (ST_LcaseCons)
(lcase (cons vh vt) of nil -> t2 | xh::xt -> t3)
==> [xh:=vh,xt:=vt]t3
*)
(** Typing:
----------------------- (T_Nil)
Gamma |- nil T : List T
Gamma |- t1 : T Gamma |- t2 : List T
----------------------------------------- (T_Cons)
Gamma |- cons t1 t2: List T
Gamma |- t1 : List T1
Gamma |- t2 : T
Gamma , h:T1, t:List T1 |- t3 : T
------------------------------------------------- (T_Lcase)
Gamma |- (lcase t1 of nil -> t2 | h::t -> t3) : T
*)
(** ** General Recursion *)
(** Another facility found in most programming languages (including
Coq) is the ability to define recursive functions. For example,
we might like to be able to define the factorial function like
this:
<<
fact = \x:Nat.
if x=0 then 1 else x * (fact (pred x)))
>>
But this would require quite a bit of work to formalize: we'd have
to introduce a notion of "function definitions" and carry around an
"environment" of such definitions in the definition of the [step]
relation. *)
(** Here is another way that is straightforward to formalize: instead
of writing recursive definitions where the right-hand side can
contain the identifier being defined, we can define a _fixed-point
operator_ that performs the "unfolding" of the recursive definition
in the right-hand side lazily during reduction.
<<
fact =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 1 else x * (f (pred x)))
>>
*)
(** The intuition is that the higher-order function [f] passed
to [fix] is a _generator_ for the [fact] function: if [f] is
applied to a function that approximates the desired behavior of
[fact] up to some number [n] (that is, a function that returns
correct results on inputs less than or equal to [n]), then it
returns a better approximation to [fact] -- a function that returns
correct results for inputs up to [n+1]. Applying [fix] to this
generator returns its _fixed point_ -- a function that gives the
desired behavior for all inputs [n].
(The term "fixed point" has exactly the same sense as in ordinary
mathematics, where a fixed point of a function [f] is an input [x]
such that [f(x) = x]. Here, a fixed point of a function [F] of
type (say) [(Nat->Nat)->(Nat->Nat)] is a function [f] such that [F
f] is behaviorally equivalent to [f].) *)
(** Syntax:
<<
t ::= Terms
| ...
| fix t fixed-point operator
>>
Reduction:
t1 ==> t1'
------------------ (ST_Fix1)
fix t1 ==> fix t1'
F = \xf:T1.t2
----------------------- (ST_FixAbs)
fix F ==> [xf:=fix F]t2
Typing:
Gamma |- t1 : T1->T1
-------------------- (T_Fix)
Gamma |- fix t1 : T1
*)
(** Let's see how [ST_FixAbs] works by reducing [fact 3 = fix F 3],
where [F = (\f. \x. if x=0 then 1 else x * (f (pred x)))] (we are
omitting type annotations for brevity here).
<<
fix F 3
>>
[==>] [ST_FixAbs]
<<
(\x. if x=0 then 1 else x * (fix F (pred x))) 3
>>
[==>] [ST_AppAbs]
<<
if 3=0 then 1 else 3 * (fix F (pred 3))
>>
[==>] [ST_If0_Nonzero]
<<
3 * (fix F (pred 3))
>>
[==>] [ST_FixAbs + ST_Mult2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 3))
>>
[==>] [ST_PredNat + ST_Mult2 + ST_App2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 2)
>>
[==>] [ST_AppAbs + ST_Mult2]
<<
3 * (if 2=0 then 1 else 2 * (fix F (pred 2)))
>>
[==>] [ST_If0_Nonzero + ST_Mult2]
<<
3 * (2 * (fix F (pred 2)))
>>
[==>] [ST_FixAbs + 2 x ST_Mult2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 2)))
>>
[==>] [ST_PredNat + 2 x ST_Mult2 + ST_App2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 1))
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
3 * (2 * (if 1=0 then 1 else 1 * (fix F (pred 1))))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
3 * (2 * (1 * (fix F (pred 1))))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)))
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
3 * (2 * (1 * 1))
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
3 * (2 * 1)
>>
[==>] [ST_MultNats + ST_Mult2]
<<
3 * 2
>>
[==>] [ST_MultNats]
<<
6
>>
*)
(** **** Exercise: 1 star, optional (halve_fix) *)
(** Translate this informal recursive definition into one using [fix]:
<<
halve =
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (halve (pred (pred x))))
>>
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional (fact_steps) *)
(** Write down the sequence of steps that the term [fact 1] goes
through to reduce to a normal form (assuming the usual reduction
rules for arithmetic operations).
(* FILL IN HERE *)
[]
*)
(** The ability to form the fixed point of a function of type [T->T]
for any [T] has some surprising consequences. In particular, it
implies that _every_ type is inhabited by some term. To see this,
observe that, for every type [T], we can define the term
fix (\x:T.x)
By [T_Fix] and [T_Abs], this term has type [T]. By [ST_FixAbs]
it reduces to itself, over and over again. Thus it is an
_undefined element_ of [T].
More usefully, here's an example using [fix] to define a
two-argument recursive function:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
And finally, here is an example where [fix] is used to define a
_pair_ of recursive functions (illustrating the fact that the type
[T1] in the rule [T_Fix] need not be a function type):
<<
evenodd =
fix
(\eo: (Nat->Bool * Nat->Bool).
let e = \n:Nat. if n=0 then true else eo.snd (pred n) in
let o = \n:Nat. if n=0 then false else eo.fst (pred n) in
(e,o))
even = evenodd.fst
odd = evenodd.snd
>>
*)
(* ###################################################################### *)
(** ** Records *)
(** As a final example of a basic extension of the STLC, let's
look briefly at how to define _records_ and their types.
Intuitively, records can be obtained from pairs by two kinds of
generalization: they are n-ary products (rather than just binary)
and their fields are accessed by _label_ (rather than position).
Conceptually, this extension is a straightforward generalization
of pairs and product types, but notationally it becomes a little
heavier; for this reason, we postpone its formal treatment to a
separate chapter ([Records]). *)
(** Records are not included in the extended exercise below, but
they will be useful to motivate the [Sub] chapter. *)
(** Syntax:
<<
t ::= Terms
| ...
| {i1=t1, ..., in=tn} record
| t.i projection
v ::= Values
| ...
| {i1=v1, ..., in=vn} record value
T ::= Types
| ...
| {i1:T1, ..., in:Tn} record type
>>
Intuitively, the generalization is pretty obvious. But it's worth
noticing that what we've actually written is rather informal: in
particular, we've written "[...]" in several places to mean "any
number of these," and we've omitted explicit mention of the usual
side-condition that the labels of a record should not contain
repetitions. *)
(** It is possible to devise informal notations that are
more precise, but these tend to be quite heavy and to obscure the
main points of the definitions. So we'll leave these a bit loose
here (they are informal anyway, after all) and do the work of
tightening things up elsewhere (in chapter [Records]). *)
(**
Reduction:
ti ==> ti'
------------------------------------ (ST_Rcd)
{i1=v1, ..., im=vm, in=ti, ...}
==> {i1=v1, ..., im=vm, in=ti', ...}
t1 ==> t1'
-------------- (ST_Proj1)
t1.i ==> t1'.i
------------------------- (ST_ProjRcd)
{..., i=vi, ...}.i ==> vi
Again, these rules are a bit informal. For example, the first rule
is intended to be read "if [ti] is the leftmost field that is not a
value and if [ti] steps to [ti'], then the whole record steps..."
In the last rule, the intention is that there should only be one
field called i, and that all the other fields must contain values. *)
(**
Typing:
Gamma |- t1 : T1 ... Gamma |- tn : Tn
-------------------------------------------------- (T_Rcd)
Gamma |- {i1=t1, ..., in=tn} : {i1:T1, ..., in:Tn}
Gamma |- t : {..., i:Ti, ...}
----------------------------- (T_Proj)
Gamma |- t.i : Ti
*)
(* ###################################################################### *)
(** *** Encoding Records (Optional) *)
(** There are several ways to make the above definitions precise.
- We can directly formalize the syntactic forms and inference
rules, staying as close as possible to the form we've given
them above. This is conceptually straightforward, and it's
probably what we'd want to do if we were building a real
compiler -- in particular, it will allow us to print error
messages in the form that programmers will find easy to
understand. But the formal versions of the rules will not be
pretty at all!
- We could look for a smoother way of presenting records -- for
example, a binary presentation with one constructor for the
empty record and another constructor for adding a single field
to an existing record, instead of a single monolithic
constructor that builds a whole record at once. This is the
right way to go if we are primarily interested in studying the
metatheory of the calculi with records, since it leads to
clean and elegant definitions and proofs. Chapter [Records]
shows how this can be done.
- Alternatively, if we like, we can avoid formalizing records
altogether, by stipulating that record notations are just
informal shorthands for more complex expressions involving
pairs and product types. We sketch this approach here.
First, observe that we can encode arbitrary-size tuples using
nested pairs and the [unit] value. To avoid overloading the pair
notation [(t1,t2)], we'll use curly braces without labels to write
down tuples, so [{}] is the empty tuple, [{5}] is a singleton
tuple, [{5,6}] is a 2-tuple (morally the same as a pair),
[{5,6,7}] is a triple, etc.
<<
{} ----> unit
{t1, t2, ..., tn} ----> (t1, trest)
where {t2, ..., tn} ----> trest
>>
Similarly, we can encode tuple types using nested product types:
<<
{} ----> Unit
{T1, T2, ..., Tn} ----> T1 * TRest
where {T2, ..., Tn} ----> TRest
>>
The operation of projecting a field from a tuple can be encoded
using a sequence of second projections followed by a first projection:
<<
t.0 ----> t.fst
t.(n+1) ----> (t.snd).n
>>
Next, suppose that there is some total ordering on record labels,
so that we can associate each label with a unique natural number.
This number is called the _position_ of the label. For example,
we might assign positions like this:
<<
LABEL POSITION
a 0
b 1
c 2
... ...
foo 1004
... ...
bar 10562
... ...
>>
We use these positions to encode record values as tuples (i.e., as
nested pairs) by sorting the fields according to their positions.
For example:
<<
{a=5, b=6} ----> {5,6}
{a=5, c=7} ----> {5,unit,7}
{c=7, a=5} ----> {5,unit,7}
{c=5, b=3} ----> {unit,3,5}
{f=8,c=5,a=7} ----> {7,unit,5,unit,unit,8}
{f=8,c=5} ----> {unit,unit,5,unit,unit,8}
>>
Note that each field appears in the position associated with its
label, that the size of the tuple is determined by the label with
the highest position, and that we fill in unused positions with
[unit].
We do exactly the same thing with record types:
<<
{a:Nat, b:Nat} ----> {Nat,Nat}
{c:Nat, a:Nat} ----> {Nat,Unit,Nat}
{f:Nat,c:Nat} ----> {Unit,Unit,Nat,Unit,Unit,Nat}
>>
Finally, record projection is encoded as a tuple projection from
the appropriate position:
<<
t.l ----> t.(position of l)
>>
It is not hard to check that all the typing rules for the original
"direct" presentation of records are validated by this
encoding. (The reduction rules are "almost validated" -- not
quite, because the encoding reorders fields.) *)
(** Of course, this encoding will not be very efficient if we
happen to use a record with label [bar]! But things are not
actually as bad as they might seem: for example, if we assume that
our compiler can see the whole program at the same time, we can
_choose_ the numbering of labels so that we assign small positions
to the most frequently used labels. Indeed, there are industrial
compilers that essentially do this! *)
(** *** Variants (Optional Reading) *)
(** Just as products can be generalized to records, sums can be
generalized to n-ary labeled types called _variants_. Instead of
[T1+T2], we can write something like [<l1:T1,l2:T2,...ln:Tn>]
where [l1],[l2],... are field labels which are used both to build
instances and as case arm labels.
These n-ary variants give us almost enough mechanism to build
arbitrary inductive data types like lists and trees from
scratch -- the only thing missing is a way to allow _recursion_ in
type definitions. We won't cover this here, but detailed
treatments can be found in many textbooks -- e.g., Types and
Programming Languages. *)
(* ###################################################################### *)
(** * Exercise: Formalizing the Extensions *)
(** **** Exercise: 4 stars, optional (STLC_extensions) *)
(** In this problem you will formalize a couple of the extensions
described above. We've provided the necessary additions to the
syntax of terms and types, and we've included a few examples that
you can test your definitions with to make sure they are working
as expected. You'll fill in the rest of the definitions and
extend all the proofs accordingly.
To get you started, we've provided implementations for:
- numbers
- pairs and units
- sums
- lists
You need to complete the implementations for:
- let (which involves binding)
- [fix]
A good strategy is to work on the extensions one at a time, in
multiple passes, rather than trying to work through the file from
start to finish in a single pass. For each definition or proof,
begin by reading carefully through the parts that are provided for
you, referring to the text in the [Stlc] chapter for high-level
intuitions and the embedded comments for detailed mechanics.
*)
Module STLCExtended.
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty
| TUnit : ty
| TProd : ty -> ty -> ty
| TSum : ty -> ty -> ty
| TList : ty -> ty.
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* numbers *)
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* units *)
| tunit : tm
(* let *)
| tlet : id -> tm -> tm -> tm
(* i.e., [let x = t1 in t2] *)
(* sums *)
| tinl : ty -> tm -> tm
| tinr : ty -> tm -> tm
| tcase : tm -> id -> tm -> id -> tm -> tm
(* i.e., [case t0 of inl x1 => t1 | inr x2 => t2] *)
(* lists *)
| tnil : ty -> tm
| tcons : tm -> tm -> tm
| tlcase : tm -> tm -> id -> id -> tm -> tm
(* i.e., [lcase t1 of | nil -> t2 | x::y -> t3] *)
(* fix *)
| tfix : tm -> tm.
(** Note that, for brevity, we've omitted booleans and instead
provided a single [if0] form combining a zero test and a
conditional. That is, instead of writing
<<
if x = 0 then ... else ...
>>
we'll write this:
<<
if0 x then ... else ...
>>
*)
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tpair t1 t2 =>
tpair (subst x s t1) (subst x s t2)
| tfst t1 =>
tfst (subst x s t1)
| tsnd t1 =>
tsnd (subst x s t1)
| tunit => tunit
(* FILL IN HERE *)
| tinl T t1 =>
tinl T (subst x s t1)
| tinr T t1 =>
tinr T (subst x s t1)
| tcase t0 y1 t1 y2 t2 =>
tcase (subst x s t0)
y1 (if eq_id_dec x y1 then t1 else (subst x s t1))
y2 (if eq_id_dec x y2 then t2 else (subst x s t2))
| tnil T =>
tnil T
| tcons t1 t2 =>
tcons (subst x s t1) (subst x s t2)
| tlcase t1 t2 y1 y2 t3 =>
tlcase (subst x s t1) (subst x s t2) y1 y2
(if eq_id_dec x y1 then
t3
else if eq_id_dec x y2 then t3
else (subst x s t3))
(* FILL IN HERE *)
| _ => t (* ... and delete this line *)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
(** Next we define the values of our language. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
(* Numbers are values: *)
| v_nat : forall n1,
value (tnat n1)
(* A pair is a value if both components are: *)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
(* A unit is always a value *)
| v_unit : value tunit
(* A tagged value is a value: *)
| v_inl : forall v T,
value v ->
value (tinl T v)
| v_inr : forall v T,
value v ->
value (tinr T v)
(* A list is a value iff its head and tail are values: *)
| v_lnil : forall T, value (tnil T)
| v_lcons : forall v1 vl,
value v1 ->
value vl ->
value (tcons v1 vl)
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* nats *)
| ST_Succ1 : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_SuccNat : forall n1,
(tsucc (tnat n1)) ==> (tnat (S n1))
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_PredNat : forall n1,
(tpred (tnat n1)) ==> (tnat (pred n1))
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tmult v1 t2) ==> (tmult v1 t2')
| ST_MultNats : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (mult n1 n2))
| ST_If01 : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_If0Zero : forall t2 t3,
(tif0 (tnat 0) t2 t3) ==> t2
| ST_If0Nonzero : forall n t2 t3,
(tif0 (tnat (S n)) t2 t3) ==> t3
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst1 : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd1 : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* let *)
(* FILL IN HERE *)
(* sums *)
| ST_Inl : forall t1 t1' T,
t1 ==> t1' ->
(tinl T t1) ==> (tinl T t1')
| ST_Inr : forall t1 t1' T,
t1 ==> t1' ->
(tinr T t1) ==> (tinr T t1')
| ST_Case : forall t0 t0' x1 t1 x2 t2,
t0 ==> t0' ->
(tcase t0 x1 t1 x2 t2) ==> (tcase t0' x1 t1 x2 t2)
| ST_CaseInl : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinl T v0) x1 t1 x2 t2) ==> [x1:=v0]t1
| ST_CaseInr : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinr T v0) x1 t1 x2 t2) ==> [x2:=v0]t2
(* lists *)
| ST_Cons1 : forall t1 t1' t2,
t1 ==> t1' ->
(tcons t1 t2) ==> (tcons t1' t2)
| ST_Cons2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tcons v1 t2) ==> (tcons v1 t2')
| ST_Lcase1 : forall t1 t1' t2 x1 x2 t3,
t1 ==> t1' ->
(tlcase t1 t2 x1 x2 t3) ==> (tlcase t1' t2 x1 x2 t3)
| ST_LcaseNil : forall T t2 x1 x2 t3,
(tlcase (tnil T) t2 x1 x2 t3) ==> t2
| ST_LcaseCons : forall v1 vl t2 x1 x2 t3,
value v1 ->
value vl ->
(tlcase (tcons v1 vl) t2 x1 x2 t3) ==> (subst x2 vl (subst x1 v1 t3))
(* fix *)
(* FILL IN HERE *)
where "t1 '==>' t2" := (step t1 t2).
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
(** Next we define the typing rules. These are nearly direct
transcriptions of the inference rules shown above. *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
(* nats *)
| T_Nat : forall Gamma n1,
Gamma |- (tnat n1) \in TNat
| T_Succ : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tsucc t1) \in TNat
| T_Pred : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tpred t1) \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma t1 t2 t3 T1,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- (tif0 t1 t2 t3) \in T1
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in T2 ->
Gamma |- (tpair t1 t2) \in (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tfst t) \in T1
| T_Snd : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tsnd t) \in T2
(* unit *)
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* let *)
(* FILL IN HERE *)
(* sums *)
| T_Inl : forall Gamma t1 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- (tinl T2 t1) \in (TSum T1 T2)
| T_Inr : forall Gamma t2 T1 T2,
Gamma |- t2 \in T2 ->
Gamma |- (tinr T1 t2) \in (TSum T1 T2)
| T_Case : forall Gamma t0 x1 T1 t1 x2 T2 t2 T,
Gamma |- t0 \in (TSum T1 T2) ->
(extend Gamma x1 T1) |- t1 \in T ->
(extend Gamma x2 T2) |- t2 \in T ->
Gamma |- (tcase t0 x1 t1 x2 t2) \in T
(* lists *)
| T_Nil : forall Gamma T,
Gamma |- (tnil T) \in (TList T)
| T_Cons : forall Gamma t1 t2 T1,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in (TList T1) ->
Gamma |- (tcons t1 t2) \in (TList T1)
| T_Lcase : forall Gamma t1 T1 t2 x1 x2 t3 T2,
Gamma |- t1 \in (TList T1) ->
Gamma |- t2 \in T2 ->
(extend (extend Gamma x2 (TList T1)) x1 T1) |- t3 \in T2 ->
Gamma |- (tlcase t1 t2 x1 x2 t3) \in T2
(* fix *)
(* FILL IN HERE *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ###################################################################### *)
(** ** Examples *)
(** This section presents formalized versions of the examples from
above (plus several more). The ones at the beginning focus on
specific features; you can use these to make sure your definition
of a given feature is reasonable before moving on to extending the
proofs later in the file with the cases relating to this feature.
The later examples require all the features together, so you'll
need to come back to these when you've got all the definitions
filled in. *)
Module Examples.
(** *** Preliminaries *)
(** First, let's define a few variable names: *)
Notation a := (Id 0).
Notation f := (Id 1).
Notation g := (Id 2).
Notation l := (Id 3).
Notation k := (Id 6).
Notation i1 := (Id 7).
Notation i2 := (Id 8).
Notation x := (Id 9).
Notation y := (Id 10).
Notation processSum := (Id 11).
Notation n := (Id 12).
Notation eq := (Id 13).
Notation m := (Id 14).
Notation evenodd := (Id 15).
Notation even := (Id 16).
Notation odd := (Id 17).
Notation eo := (Id 18).
(** Next, a bit of Coq hackery to automate searching for typing
derivations. You don't need to understand this bit in detail --
just have a look over it so that you'll know what to look for if
you ever find yourself needing to make custom extensions to
[auto].
The following [Hint] declarations say that, whenever [auto]
arrives at a goal of the form [(Gamma |- (tapp e1 e1) \in T)], it
should consider [eapply T_App], leaving an existential variable
for the middle type T1, and similar for [lcase]. That variable
will then be filled in during the search for type derivations for
[e1] and [e2]. We also include a hint to "try harder" when
solving equality goals; this is useful to automate uses of
[T_Var] (which includes an equality as a precondition). *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
(* You'll want to uncomment the following line once
you've defined the [T_Lcase] constructor for the typing
relation: *)
(*
Hint Extern 2 (has_type _ (tlcase _ _ _ _ _) _) =>
eapply T_Lcase; auto.
*)
Hint Extern 2 (_ = _) => compute; reflexivity.
(** *** Numbers *)
Module Numtest.
(* if0 (pred (succ (pred (2 * 0))) then 5 else 6 *)
Definition test :=
tif0
(tpred
(tsucc
(tpred
(tmult
(tnat 2)
(tnat 0)))))
(tnat 5)
(tnat 6).
(** Remove the comment braces once you've implemented enough of the
definitions that you think this should work. *)
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof.
unfold test.
(* This typing derivation is quite deep, so we need to increase the
max search depth of [auto] from the default 5 to 10. *)
auto 10.
Qed.
Example numtest_reduces :
test ==>* tnat 5.
Proof.
unfold test. normalize.
Qed.
*)
End Numtest.
(** *** Products *)
Module Prodtest.
(* ((5,6),7).fst.snd *)
Definition test :=
tsnd
(tfst
(tpair
(tpair
(tnat 5)
(tnat 6))
(tnat 7))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End Prodtest.
(** *** [let] *)
Module LetTest.
(* let x = pred 6 in succ x *)
Definition test :=
tlet
x
(tpred (tnat 6))
(tsucc (tvar x)).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End LetTest.
(** *** Sums *)
Module Sumtest1.
(* case (inl Nat 5) of
inl x => x
| inr y => y *)
Definition test :=
tcase (tinl TNat (tnat 5))
x (tvar x)
y (tvar y).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tnat 5).
Proof. unfold test. normalize. Qed.
*)
End Sumtest1.
Module Sumtest2.
(* let processSum =
\x:Nat+Nat.
case x of
inl n => n
inr n => if0 n then 1 else 0 in
(processSum (inl Nat 5), processSum (inr Nat 5)) *)
Definition test :=
tlet
processSum
(tabs x (TSum TNat TNat)
(tcase (tvar x)
n (tvar n)
n (tif0 (tvar n) (tnat 1) (tnat 0))))
(tpair
(tapp (tvar processSum) (tinl TNat (tnat 5)))
(tapp (tvar processSum) (tinr TNat (tnat 5)))).
(*
Example typechecks :
(@empty ty) |- test \in (TProd TNat TNat).
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tpair (tnat 5) (tnat 0)).
Proof. unfold test. normalize. Qed.
*)
End Sumtest2.
(** *** Lists *)
Module ListTest.
(* let l = cons 5 (cons 6 (nil Nat)) in
lcase l of
nil => 0
| x::y => x*x *)
Definition test :=
tlet l
(tcons (tnat 5) (tcons (tnat 6) (tnil TNat)))
(tlcase (tvar l)
(tnat 0)
x y (tmult (tvar x) (tvar x))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 20. Qed.
Example reduces :
test ==>* (tnat 25).
Proof. unfold test. normalize. Qed.
*)
End ListTest.
(** *** [fix] *)
Module FixTest1.
(* fact := fix
(\f:nat->nat.
\a:nat.
if a=0 then 1 else a * (f (pred a))) *)
Definition fact :=
tfix
(tabs f (TArrow TNat TNat)
(tabs a TNat
(tif0
(tvar a)
(tnat 1)
(tmult
(tvar a)
(tapp (tvar f) (tpred (tvar a))))))).
(** (Warning: you may be able to typecheck [fact] but still have some
rules wrong!) *)
(*
Example fact_typechecks :
(@empty ty) |- fact \in (TArrow TNat TNat).
Proof. unfold fact. auto 10.
Qed.
*)
(*
Example fact_example:
(tapp fact (tnat 4)) ==>* (tnat 24).
Proof. unfold fact. normalize. Qed.
*)
End FixTest1.
Module FixTest2.
(* map :=
\g:nat->nat.
fix
(\f:[nat]->[nat].
\l:[nat].
case l of
| [] -> []
| x::l -> (g x)::(f l)) *)
Definition map :=
tabs g (TArrow TNat TNat)
(tfix
(tabs f (TArrow (TList TNat) (TList TNat))
(tabs l (TList TNat)
(tlcase (tvar l)
(tnil TNat)
a l (tcons (tapp (tvar g) (tvar a))
(tapp (tvar f) (tvar l))))))).
(*
(* Make sure you've uncommented the last [Hint Extern] above... *)
Example map_typechecks :
empty |- map \in
(TArrow (TArrow TNat TNat)
(TArrow (TList TNat)
(TList TNat))).
Proof. unfold map. auto 10. Qed.
Example map_example :
tapp (tapp map (tabs a TNat (tsucc (tvar a))))
(tcons (tnat 1) (tcons (tnat 2) (tnil TNat)))
==>* (tcons (tnat 2) (tcons (tnat 3) (tnil TNat))).
Proof. unfold map. normalize. Qed.
*)
End FixTest2.
Module FixTest3.
(* equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if0 m then (if0 n then 1 else 0)
else if0 n then 0
else eq (pred m) (pred n)) *)
Definition equal :=
tfix
(tabs eq (TArrow TNat (TArrow TNat TNat))
(tabs m TNat
(tabs n TNat
(tif0 (tvar m)
(tif0 (tvar n) (tnat 1) (tnat 0))
(tif0 (tvar n)
(tnat 0)
(tapp (tapp (tvar eq)
(tpred (tvar m)))
(tpred (tvar n)))))))).
(*
Example equal_typechecks :
(@empty ty) |- equal \in (TArrow TNat (TArrow TNat TNat)).
Proof. unfold equal. auto 10.
Qed.
*)
(*
Example equal_example1:
(tapp (tapp equal (tnat 4)) (tnat 4)) ==>* (tnat 1).
Proof. unfold equal. normalize. Qed.
*)
(*
Example equal_example2:
(tapp (tapp equal (tnat 4)) (tnat 5)) ==>* (tnat 0).
Proof. unfold equal. normalize. Qed.
*)
End FixTest3.
Module FixTest4.
(* let evenodd =
fix
(\eo: (Nat->Nat * Nat->Nat).
let e = \n:Nat. if0 n then 1 else eo.snd (pred n) in
let o = \n:Nat. if0 n then 0 else eo.fst (pred n) in
(e,o)) in
let even = evenodd.fst in
let odd = evenodd.snd in
(even 3, even 4)
*)
Definition eotest :=
tlet evenodd
(tfix
(tabs eo (TProd (TArrow TNat TNat) (TArrow TNat TNat))
(tpair
(tabs n TNat
(tif0 (tvar n)
(tnat 1)
(tapp (tsnd (tvar eo)) (tpred (tvar n)))))
(tabs n TNat
(tif0 (tvar n)
(tnat 0)
(tapp (tfst (tvar eo)) (tpred (tvar n))))))))
(tlet even (tfst (tvar evenodd))
(tlet odd (tsnd (tvar evenodd))
(tpair
(tapp (tvar even) (tnat 3))
(tapp (tvar even) (tnat 4))))).
(*
Example eotest_typechecks :
(@empty ty) |- eotest \in (TProd TNat TNat).
Proof. unfold eotest. eauto 30.
Qed.
*)
(*
Example eotest_example1:
eotest ==>* (tpair (tnat 0) (tnat 1)).
Proof. unfold eotest. normalize. Qed.
*)
End FixTest4.
End Examples.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** The proofs of progress and preservation for this system are
essentially the same (though of course somewhat longer) as for the
pure simply typed lambda-calculus. *)
(* ###################################################################### *)
(** *** Progress *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
(* Theorem: Suppose empty |- t : T. Then either
1. t is a value, or
2. t ==> t' for some t'.
Proof: By induction on the given typing derivation. *)
intros t T Ht.
remember (@empty ty) as Gamma.
generalize dependent HeqGamma.
induction Ht; intros HeqGamma; subst.
- (* T_Var *)
(* The final rule in the given typing derivation cannot be [T_Var],
since it can never be the case that [empty |- x : T] (since the
context is empty). *)
inversion H.
- (* T_Abs *)
(* If the [T_Abs] rule was the last used, then [t = tabs x T11 t12],
which is a value. *)
left...
- (* T_App *)
(* If the last rule applied was T_App, then [t = t1 t2], and we know
from the form of the rule that
[empty |- t1 : T1 -> T2]
[empty |- t2 : T1]
By the induction hypothesis, each of t1 and t2 either is a value
or can take a step. *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
(* If both [t1] and [t2] are values, then we know that
[t1 = tabs x T11 t12], since abstractions are the only values
that can have an arrow type. But
[(tabs x T11 t12) t2 ==> [x:=t2]t12] by [ST_AppAbs]. *)
inversion H; subst; try (solve by inversion).
exists (subst x t2 t12)...
* (* t2 steps *)
(* If [t1] is a value and [t2 ==> t2'], then [t1 t2 ==> t1 t2']
by [ST_App2]. *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
(* Finally, If [t1 ==> t1'], then [t1 t2 ==> t1' t2] by [ST_App1]. *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_Nat *)
left...
- (* T_Succ *)
right.
destruct IHHt...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
exists (tnat (S n1))...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tsucc t1')...
- (* T_Pred *)
right.
destruct IHHt...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
exists (tnat (pred n1))...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tpred t1')...
- (* T_Mult *)
right.
destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is a value *)
inversion H; subst; try solve by inversion.
inversion H0; subst; try solve by inversion.
exists (tnat (mult n1 n0))...
* (* t2 steps *)
inversion H0 as [t2' Hstp].
exists (tmult t1 t2')...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tmult t1' t2)...
- (* T_If0 *)
right.
destruct IHHt1...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
destruct n1 as [|n1'].
* (* n1=0 *)
exists t2...
* (* n1<>0 *)
exists t3...
+ (* t1 steps *)
inversion H as [t1' H0].
exists (tif0 t1' t2 t3)...
- (* T_Pair *)
destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 steps *)
right. inversion H0 as [t2' Hstp].
exists (tpair t1 t2')...
+ (* t1 steps *)
right. inversion H as [t1' Hstp].
exists (tpair t1' t2)...
- (* T_Fst *)
right.
destruct IHHt...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
exists v1...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tfst t1')...
- (* T_Snd *)
right.
destruct IHHt...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
exists v2...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tsnd t1')...
- (* T_Unit *)
left...
(* let *)
(* FILL IN HERE *)
- (* T_Inl *)
destruct IHHt...
+ (* t1 steps *)
right. inversion H as [t1' Hstp]...
(* exists (tinl _ t1')... *)
- (* T_Inr *)
destruct IHHt...
+ (* t1 steps *)
right. inversion H as [t1' Hstp]...
(* exists (tinr _ t1')... *)
- (* T_Case *)
right.
destruct IHHt1...
+ (* t0 is a value *)
inversion H; subst; try solve by inversion.
* (* t0 is inl *)
exists ([x1:=v]t1)...
* (* t0 is inr *)
exists ([x2:=v]t2)...
+ (* t0 steps *)
inversion H as [t0' Hstp].
exists (tcase t0' x1 t1 x2 t2)...
- (* T_Nil *)
left...
- (* T_Cons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. inversion H0 as [t2' Hstp].
exists (tcons t1 t2')...
+ (* head steps *)
right. inversion H as [t1' Hstp].
exists (tcons t1' t2)...
- (* T_Lcase *)
right.
destruct IHHt1...
+ (* t1 is a value *)
inversion H; subst; try solve by inversion.
* (* t1=tnil *)
exists t2...
* (* t1=tcons v1 vl *)
exists ([x2:=vl]([x1:=v1]t3))...
+ (* t1 steps *)
inversion H as [t1' Hstp].
exists (tlcase t1' t2 x1 x2 t3)...
(* fix *)
(* FILL IN HERE *)
Qed.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* nats *)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* let *)
(* FILL IN HERE *)
(* sums *)
| afi_inl : forall x t T,
appears_free_in x t ->
appears_free_in x (tinl T t)
| afi_inr : forall x t T,
appears_free_in x t ->
appears_free_in x (tinr T t)
| afi_case0 : forall x t0 x1 t1 x2 t2,
appears_free_in x t0 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case1 : forall x t0 x1 t1 x2 t2,
x1 <> x ->
appears_free_in x t1 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case2 : forall x t0 x1 t1 x2 t2,
x2 <> x ->
appears_free_in x t2 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
(* lists *)
| afi_cons1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tcons t1 t2)
| afi_cons2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tcons t1 t2)
| afi_lcase1 : forall x t1 t2 y1 y2 t3,
appears_free_in x t1 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase2 : forall x t1 t2 y1 y2 t3,
appears_free_in x t2 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase3 : forall x t1 t2 y1 y2 t3,
y1 <> x ->
y2 <> x ->
appears_free_in x t3 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
(* fix *)
(* FILL IN HERE *)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
- (* T_Mult *)
apply T_Mult...
- (* T_If0 *)
apply T_If0...
- (* T_Pair *)
apply T_Pair...
(* let *)
(* FILL IN HERE *)
- (* T_Case *)
eapply T_Case...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x2 y)...
- (* T_Cons *)
apply T_Cons...
- (* T_Lcase *)
eapply T_Lcase... apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
destruct (eq_id_dec x2 y)...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; inversion Hafi; subst...
- (* T_Abs *)
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* let *)
(* FILL IN HERE *)
(* T_Case *)
- (* left *)
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
- (* right *)
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
- (* T_Lcase *)
clear Htyp1 IHHtyp1 Htyp2 IHHtyp2.
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx... rewrite neq_id in Hctx...
Qed.
(* ###################################################################### *)
(** *** Substitution *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- [x:=v]t : S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
induction t;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
- (* tvar *)
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
- (* tabs *)
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 : S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
+ (* x<>y *)
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* let *)
(* FILL IN HERE *)
- (* tcase *)
rename i into x1. rename i0 into x2.
eapply T_Case...
+ (* left arm *)
destruct (eq_id_dec x x1).
* (* x = x1 *)
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
* (* x <> x1 *)
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
subst. rewrite neq_id...
+ (* right arm *)
destruct (eq_id_dec x x2).
* (* x = x2 *)
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
* (* x <> x2 *)
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
subst. rewrite neq_id...
- (* tlcase *)
rename i into y1. rename i0 into y2.
eapply T_Lcase...
destruct (eq_id_dec x y1).
+ (* x=y1 *)
simpl.
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
+ (* x<>y1 *)
destruct (eq_id_dec x y2).
* (* x=y2 *)
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y2 z)...
* (* x<>y2 *)
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
subst. rewrite neq_id...
destruct (eq_id_dec y2 z)...
subst. rewrite neq_id...
Qed.
(* ###################################################################### *)
(** *** Preservation *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
+ (* ST_AppAbs *)
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
- (* T_Fst *)
inversion HT...
- (* T_Snd *)
inversion HT...
(* let *)
(* FILL IN HERE *)
(* T_Case *)
- (* ST_CaseInl *)
inversion HT1; subst.
eapply substitution_preserves_typing...
- (* ST_CaseInr *)
inversion HT1; subst.
eapply substitution_preserves_typing...
- (* T_Lcase *)
+ (* ST_LcaseCons *)
inversion HT1; subst.
apply substitution_preserves_typing with (TList T1)...
apply substitution_preserves_typing with T1...
(* fix *)
(* FILL IN HERE *)
Qed.
(** [] *)
End STLCExtended.
(* $Date$ *)
|
Require Import Coq.Lists.List.
Require Import Coq.Numbers.Natural.Peano.NPeano.
Require Import Coq.omega.Omega Coq.Lists.SetoidList.
Require Export Coq.Setoids.Setoid Coq.Classes.RelationClasses
Coq.Program.Program Coq.Classes.Morphisms.
Require Export Fiat.Common.Coq__8_4__8_5__Compat.
Global Set Implicit Arguments.
Global Generalizable All Variables.
Global Coercion is_true : bool >-> Sortclass.
Coercion bool_of_sumbool {A B} (x : {A} + {B}) : bool := if x then true else false.
Coercion bool_of_sum {A B} (b : sum A B) : bool := if b then true else false.
Lemma bool_of_sum_distr_match {A B C D} (x : sum A B) (c : A -> C) (d : B -> D)
: bool_of_sum (match x with inl k => inl (c k) | inr k => inr (d k) end) = bool_of_sum x.
Proof.
destruct x; reflexivity.
Qed.
(** Test if a tactic succeeds, but always roll-back the results *)
Tactic Notation "test" tactic3(tac) :=
try (first [ tac | fail 2 tac "does not succeed" ]; fail 0 tac "succeeds"; [](* test for [t] solved all goals *)).
(** [not tac] is equivalent to [fail tac "succeeds"] if [tac] succeeds, and is equivalent to [idtac] if [tac] fails *)
Tactic Notation "not" tactic3(tac) := try ((test tac); fail 1 tac "succeeds").
(** Runs [abstract] after clearing the environment, solving the goal
with the tactic associated with [cls <goal type>]. In 8.5, we
could pass a tactic instead. *)
Tactic Notation "clear" "abstract" constr(cls) :=
let G := match goal with |- ?G => constr:(G) end in
let pf := constr:(_ : cls G) in
let pf' := (eval cbv beta in pf) in
repeat match goal with
| [ H : _ |- _ ] => clear H; test (abstract (exact pf'))
end;
[ abstract (exact pf') ].
(** fail if [x] is a function application, a dependent product ([fun _
=> _]), or a sigma type ([forall _, _]) *)
Ltac atomic x :=
idtac;
match x with
| _ => is_evar x; fail 1 x "is not atomic (evar)"
| ?f _ => fail 1 x "is not atomic (application)"
| (fun _ => _) => fail 1 x "is not atomic (fun)"
| forall _, _ => fail 1 x "is not atomic (forall)"
| let x := _ in _ => fail 1 x "is not atomic (let in)"
| match _ with _ => _ end => fail 1 x "is not atomic (match)"
| _ => is_fix x; fail 1 x "is not atomic (fix)"
| context[?E] => (* catch-all *) (not constr_eq E x); fail 1 x "is not atomic (has subterm" E ")"
| _ => idtac
end.
(* [pose proof defn], but only if no hypothesis of the same type exists.
most useful for proofs of a proposition *)
Tactic Notation "unique" "pose" "proof" constr(defn) :=
let T := type of defn in
match goal with
| [ H : T |- _ ] => fail 1
| _ => pose proof defn
end.
(** [pose defn], but only if that hypothesis doesn't exist *)
Tactic Notation "unique" "pose" constr(defn) :=
match goal with
| [ H := defn |- _ ] => fail 1
| _ => pose defn
end.
(** check's if the given hypothesis has a body, i.e., if [clearbody]
could ever succeed. We can't just do [test_tac (clearbody H)],
because maybe the correctness of the proof depends on the body of
H *)
Tactic Notation "has" "body" hyp(H) :=
test (let H' := fresh in pose H as H'; unfold H in H').
Tactic Notation "etransitivity_rev" open_constr(v)
:= match goal with
| [ |- ?R ?LHS ?RHS ]
=> refine ((fun q p => @transitivity _ R _ LHS v RHS p q) _ _)
end.
Tactic Notation "etansitivity_rev" := etransitivity_rev _.
(** find the head of the given expression *)
Ltac head expr :=
match expr with
| ?f _ => head f
| _ => expr
end.
Ltac head_hnf expr := let expr' := eval hnf in expr in head expr'.
(** call [tac H], but first [simpl]ify [H].
This tactic leaves behind the simplified hypothesis. *)
Ltac simpl_do tac H :=
let H' := fresh in pose H as H'; simpl; simpl in H'; tac H'.
(** clear the left-over hypothesis after [simpl_do]ing it *)
Ltac simpl_do_clear tac H := simpl_do ltac:(fun H => tac H; try clear H) H.
Ltac simpl_rewrite term := simpl_do_clear ltac:(fun H => rewrite H) term.
Ltac simpl_rewrite_rev term := simpl_do_clear ltac:(fun H => rewrite <- H) term.
Tactic Notation "simpl" "rewrite" open_constr(term) := simpl_rewrite term.
Tactic Notation "simpl" "rewrite" "->" open_constr(term) := simpl_rewrite term.
Tactic Notation "simpl" "rewrite" "<-" open_constr(term) := simpl_rewrite_rev term.
Ltac do_with_hyp tac :=
match goal with
| [ H : _ |- _ ] => tac H
end.
Ltac rewrite_hyp' := do_with_hyp ltac:(fun H => rewrite H).
Ltac rewrite_hyp := repeat rewrite_hyp'.
Ltac rewrite_rev_hyp' := do_with_hyp ltac:(fun H => rewrite <- H).
Ltac rewrite_rev_hyp := repeat rewrite_rev_hyp'.
Ltac apply_hyp' := do_with_hyp ltac:(fun H => apply H).
Ltac apply_hyp := repeat apply_hyp'.
Ltac eapply_hyp' := do_with_hyp ltac:(fun H => eapply H).
Ltac eapply_hyp := repeat eapply_hyp'.
(** solve simple setiod goals that can be solved by [transitivity] *)
Ltac simpl_transitivity :=
try solve [ match goal with
| [ _ : ?Rel ?a ?b, _ : ?Rel ?b ?c |- ?Rel ?a ?c ] => transitivity b; assumption
end ].
(** given a [matcher] that succeeds on some hypotheses and fails on
others, destruct any matching hypotheses, and then execute [tac]
after each [destruct].
The [tac] part exists so that you can, e.g., [simpl in *], to
speed things up. *)
Ltac do_one_match_then matcher do_tac tac :=
idtac;
match goal with
| [ H : ?T |- _ ]
=> matcher T; do_tac H;
try match type of H with
| T => clear H
end;
tac
end.
Ltac do_all_matches_then matcher do_tac tac :=
repeat do_one_match_then matcher do_tac tac.
Ltac destruct_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => destruct H) tac.
Ltac destruct_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => destruct H) tac.
Ltac inversion_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac inversion_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac destruct_all_matches matcher :=
destruct_all_matches_then matcher ltac:( simpl in * ).
Ltac destruct_one_match matcher := destruct_one_match_then matcher ltac:( simpl in * ).
Ltac destruct_all_matches' matcher := destruct_all_matches_then matcher idtac.
Ltac inversion_all_matches matcher := inversion_all_matches_then matcher ltac:( simpl in * ).
Ltac inversion_one_match matcher := inversion_one_match_then matcher ltac:( simpl in * ).
Ltac inversion_all_matches' matcher := inversion_all_matches_then matcher idtac.
(* matches anything whose type has a [T] in it *)
Ltac destruct_type_matcher T HT :=
match HT with
| context[T] => idtac
end.
Ltac destruct_type T := destruct_all_matches ltac:(destruct_type_matcher T).
Ltac destruct_type' T := destruct_all_matches' ltac:(destruct_type_matcher T).
Ltac destruct_head_matcher T HT :=
match head HT with
| T => idtac
end.
Ltac destruct_head T := destruct_all_matches ltac:(destruct_head_matcher T).
Ltac destruct_one_head T := destruct_one_match ltac:(destruct_head_matcher T).
Ltac destruct_head' T := destruct_all_matches' ltac:(destruct_head_matcher T).
Ltac inversion_head T := inversion_all_matches ltac:(destruct_head_matcher T).
Ltac inversion_one_head T := inversion_one_match ltac:(destruct_head_matcher T).
Ltac inversion_head' T := inversion_all_matches' ltac:(destruct_head_matcher T).
Ltac head_hnf_matcher T HT :=
match head_hnf HT with
| T => idtac
end.
Ltac destruct_head_hnf T := destruct_all_matches ltac:(head_hnf_matcher T).
Ltac destruct_one_head_hnf T := destruct_one_match ltac:(head_hnf_matcher T).
Ltac destruct_head_hnf' T := destruct_all_matches' ltac:(head_hnf_matcher T).
Ltac inversion_head_hnf T := inversion_all_matches ltac:(head_hnf_matcher T).
Ltac inversion_one_head_hnf T := inversion_one_match ltac:(head_hnf_matcher T).
Ltac inversion_head_hnf' T := inversion_all_matches' ltac:(head_hnf_matcher T).
Ltac destruct_sig_matcher HT :=
match eval hnf in HT with
| ex _ => idtac
| ex2 _ _ => idtac
| sig _ => idtac
| sig2 _ _ => idtac
| sigT _ => idtac
| sigT2 _ _ => idtac
| and _ _ => idtac
| prod _ _ => idtac
end.
Ltac destruct_sig := destruct_all_matches destruct_sig_matcher.
Ltac destruct_sig' := destruct_all_matches' destruct_sig_matcher.
Ltac destruct_all_hypotheses := destruct_all_matches ltac:(fun HT =>
destruct_sig_matcher HT || destruct_sig_matcher HT
).
(** if progress can be made by [exists _], but it doesn't matter what
fills in the [_], assume that something exists, and leave the two
goals of finding a member of the apropriate type, and proving that
all members of the appropriate type prove the goal *)
Ltac destruct_exists' T := cut T; try (let H := fresh in intro H; exists H).
Ltac destruct_exists := destruct_head_hnf @sigT;
match goal with
(* | [ |- @sig ?T _ ] => destruct_exists' T*)
| [ |- @sigT ?T _ ] => destruct_exists' T
(* | [ |- @sig2 ?T _ _ ] => destruct_exists' T*)
| [ |- @sigT2 ?T _ _ ] => destruct_exists' T
end.
(** if the goal can be solved by repeated specialization of some
hypothesis with other [specialized] hypotheses, solve the goal by
brute force *)
Ltac specialized_assumption tac := tac;
match goal with
| [ x : ?T, H : forall _ : ?T, _ |- _ ] => specialize (H x); specialized_assumption tac
| _ => assumption
end.
(** for each hypothesis of type [H : forall _ : ?T, _], if there is
exactly one hypothesis of type [H' : T], do [specialize (H H')]. *)
Ltac specialize_uniquely :=
repeat match goal with
| [ x : ?T, y : ?T, H : _ |- _ ] => test (specialize (H x)); fail 1
| [ x : ?T, H : _ |- _ ] => specialize (H x)
end.
(** specialize all hypotheses of type [forall _ : ?T, _] with
appropriately typed hypotheses *)
Ltac specialize_all_ways_forall :=
repeat match goal with
| [ x : ?T, H : forall _ : ?T, _ |- _ ] => unique pose proof (H x)
end.
(** try to specialize all hypotheses with all other hypotheses. This
includes [specialize (H x)] where [H x] requires a coercion from
the type of [H] to Funclass. *)
Ltac specialize_all_ways :=
repeat match goal with
| [ x : ?T, H : _ |- _ ] => unique pose proof (H x)
end.
(** try to specialize all non-dependent hypotheses using [tac] *)
Ltac specialize_by' tac :=
idtac;
match goal with
| [ H : ?A -> ?B |- _ ] => let H' := fresh in assert (H' : A) by tac; specialize (H H'); clear H'
end.
Ltac specialize_by tac := repeat specialize_by' tac.
Ltac apply_in_hyp lem :=
match goal with
| [ H : _ |- _ ] => apply lem in H
end.
Ltac apply_in_hyp_no_match lem :=
match goal with
| [ H : _ |- _ ] => apply lem in H;
match type of H with
| appcontext[match _ with _ => _ end] => fail 1
| _ => idtac
end
end.
Ltac apply_in_hyp_no_cbv_match lem :=
match goal with
| [ H : _ |- _ ]
=> apply lem in H;
cbv beta iota in H;
match type of H with
| appcontext[match _ with _ => _ end] => fail 1
| _ => idtac
end
end.
(* Coq's build in tactics don't work so well with things like [iff]
so split them up into multiple hypotheses *)
Ltac split_in_context_by ident funl funr tac :=
repeat match goal with
| [ H : context p [ident] |- _ ] =>
let H0 := context p[funl] in let H0' := eval simpl in H0 in assert H0' by (tac H);
let H1 := context p[funr] in let H1' := eval simpl in H1 in assert H1' by (tac H);
clear H
end.
Ltac split_in_context ident funl funr :=
split_in_context_by ident funl funr ltac:(fun H => apply H).
Ltac split_iff := split_in_context iff (fun a b : Prop => a -> b) (fun a b : Prop => b -> a).
Ltac split_and' :=
repeat match goal with
| [ H : ?a /\ ?b |- _ ] => let H0 := fresh in let H1 := fresh in
assert (H0 := fst H); assert (H1 := snd H); clear H
end.
Ltac split_and := split_and'; split_in_context and (fun a b : Type => a) (fun a b : Type => b).
Ltac destruct_sum_in_match' :=
match goal with
| [ H : appcontext[match ?E with inl _ => _ | inr _ => _ end] |- _ ]
=> destruct E
| [ |- appcontext[match ?E with inl _ => _ | inr _ => _ end] ]
=> destruct E
end.
Ltac destruct_sum_in_match := repeat destruct_sum_in_match'.
Ltac destruct_ex :=
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end.
Ltac setoid_rewrite_hyp' := do_with_hyp ltac:(fun H => setoid_rewrite H).
Ltac setoid_rewrite_hyp := repeat setoid_rewrite_hyp'.
Ltac setoid_rewrite_rev_hyp' := do_with_hyp ltac:(fun H => setoid_rewrite <- H).
Ltac setoid_rewrite_rev_hyp := repeat setoid_rewrite_rev_hyp'.
Hint Extern 0 => solve [apply reflexivity] : typeclass_instances.
Ltac set_evars :=
repeat match goal with
| [ |- appcontext[?E] ] => is_evar E; let H := fresh in set (H := E)
end.
Tactic Notation "eunify" open_constr(A) open_constr(B) := unify A B.
Instance pointwise_refl A B (eqB : relation B) `{Reflexive _ eqB} : Reflexive (pointwise_relation A eqB).
Proof.
compute in *; auto.
Defined.
Instance pointwise_sym A B (eqB : relation B) `{Symmetric _ eqB} : Symmetric (pointwise_relation A eqB).
Proof.
compute in *; auto.
Defined.
Instance pointwise_transitive A B (eqB : relation B) `{Transitive _ eqB} : Transitive (pointwise_relation A eqB).
Proof.
compute in *; eauto.
Defined.
Lemma Some_ne_None {T} {x : T} : Some x <> None.
Proof.
congruence.
Qed.
Lemma None_ne_Some {T} {x : T} : None <> Some x.
Proof.
congruence.
Qed.
(* We define a wrapper for [if then else] in order for it to play
nicely with setoid_rewriting. *)
Definition If_Then_Else {A}
(c : bool)
(t e : A) :=
if c then t else e.
Notation "'If' c 'Then' t 'Else' e" :=
(If_Then_Else c t e)
(at level 70).
Definition If_Opt_Then_Else {A B}
(c : option A)
(t : A -> B)
(e : B) :=
match c with
| Some a => t a
| None => e
end.
Notation "'Ifopt' c 'as' c' 'Then' t 'Else' e" :=
(If_Opt_Then_Else c (fun c' => t) e)
(at level 70).
Global Instance If_Then_Else_fun_Proper {T} {R : relation T} {A B C D RA RB RC RD}
{bv tv fv}
{H0 : Proper (RA ==> RB ==> RC ==> RD ==> eq) bv}
{H1 : Proper (RA ==> RB ==> RC ==> RD ==> R) tv}
{H2 : Proper (RA ==> RB ==> RC ==> RD ==> R) fv}
: Proper (RA ==> RB ==> RC ==> RD ==> R) (fun (a : A) (b : B) (c : C) (d : D) => If bv a b c d Then tv a b c d Else fv a b c d).
Proof.
intros ?? Ha ?? Hb ?? Hc ?? Hd.
specialize (H0 _ _ Ha _ _ Hb _ _ Hc _ _ Hd).
rewrite H0; clear H0.
edestruct bv; simpl;
unfold Proper, impl, flip, respectful in *; eauto with nocore.
Qed.
Ltac find_if_inside :=
match goal with
| [ |- context[if ?X then _ else _] ] => destruct X
| [ |- context[If_Then_Else ?X _ _] ] => destruct X
| [ H : context[if ?X then _ else _] |- _ ]=> destruct X
| [ H : context[If_Then_Else ?X _ _] |- _ ]=> destruct X
end.
Ltac substs :=
repeat match goal with
| [ H : ?x = ?y |- _ ]
=> first [ subst x | subst y ]
end.
Ltac substss :=
repeat match goal with
| [ H : ?x = _ ,
H0 : ?x = _ |- _ ]
=> rewrite H in H0
end.
Ltac injections :=
repeat match goal with
| [ H : _ = _ |- _ ]
=> injection H; intros; subst; clear H
end.
Ltac inversion_by rule :=
progress repeat first [ progress destruct_ex
| progress split_and
| apply_in_hyp_no_cbv_match rule ].
Class can_transform_sigma A B := do_transform_sigma : A -> B.
Instance can_transform_sigT_base {A} {P : A -> Type}
: can_transform_sigma (sigT P) (sigT P) | 0
:= fun x => x.
Instance can_transform_sig_base {A} {P : A -> Prop}
: can_transform_sigma (sig P) (sig P) | 0
:= fun x => x.
Instance can_transform_sigT {A B B' C'}
`{forall x : A, can_transform_sigma (B x) (@sigT (B' x) (C' x))}
: can_transform_sigma (forall x : A, B x)
(@sigT (forall x, B' x) (fun b => forall x, C' x (b x))) | 0
:= fun f => existT
(fun b => forall x : A, C' x (b x))
(fun x => projT1 (do_transform_sigma (f x)))
(fun x => projT2 (do_transform_sigma (f x))).
Instance can_transform_sig {A B B' C'}
`{forall x : A, can_transform_sigma (B x) (@sig (B' x) (C' x))}
: can_transform_sigma (forall x : A, B x)
(@sig (forall x, B' x) (fun b => forall x, C' x (b x))) | 0
:= fun f => exist
(fun b => forall x : A, C' x (b x))
(fun x => proj1_sig (do_transform_sigma (f x)))
(fun x => proj2_sig (do_transform_sigma (f x))).
Ltac split_sig' :=
match goal with
| [ H : _ |- _ ]
=> let H' := fresh in
pose proof (@do_transform_sigma _ _ _ H) as H';
clear H;
destruct H'
end.
Ltac split_sig :=
repeat split_sig'.
Ltac clearbodies :=
repeat match goal with
| [ H := _ |- _ ] => clearbody H
end.
Ltac subst_body :=
repeat match goal with
| [ H := _ |- _ ] => subst H
end.
(** TODO: Maybe we should replace uses of this with [case_eq], which the stdlib defined for us? *)
Ltac caseEq x := generalize (refl_equal x); pattern x at -1; case x; intros.
Class ReflexiveT A (R : A -> A -> Type) :=
reflexivityT : forall x, R x x.
Class TransitiveT A (R : A -> A -> Type) :=
transitivityT : forall x y z, R x y -> R y z -> R x z.
Class PreOrderT A (R : A -> A -> Type) :=
{ PreOrderT_ReflexiveT :> ReflexiveT R;
PreOrderT_TransitiveT :> TransitiveT R }.
Definition respectful_heteroT A B C D
(R : A -> B -> Type)
(R' : forall (x : A) (y : B), C x -> D y -> Type)
(f : forall x, C x) (g : forall x, D x)
:= forall x y, R x y -> R' x y (f x) (g y).
(* Lifting forall and pointwise relations to multiple arguments. *)
Definition forall_relation2 {A : Type} {B : A -> Type} {C : forall a, B a -> Type} R :=
forall_relation (fun a => (@forall_relation (B a) (C a) (R a))).
Definition pointwise_relation2 {A B C : Type} (R : relation C) :=
pointwise_relation A (@pointwise_relation B C R).
Definition forall_relation3 {A : Type} {B : A -> Type}
{C : forall a, B a -> Type} {D : forall a b, C a b -> Type} R :=
forall_relation (fun a => (@forall_relation2 (B a) (C a) (D a) (R a))).
Definition pointwise_relation3 {A B C D : Type} (R : relation D) :=
pointwise_relation A (@pointwise_relation2 B C D R).
Definition forall_relation4 {A : Type} {B : A -> Type}
{C : forall a, B a -> Type} {D : forall a b, C a b -> Type}
{E : forall a b c, D a b c -> Type} R :=
forall_relation (fun a => (@forall_relation3 (B a) (C a) (D a) (E a) (R a))).
Definition pointwise_relation4 {A B C D E : Type} (R : relation E) :=
pointwise_relation A (@pointwise_relation3 B C D E R).
Ltac higher_order_1_reflexivity' :=
let a := match goal with |- ?R ?a (?f ?x) => constr:(a) end in
let f := match goal with |- ?R ?a (?f ?x) => constr:(f) end in
let x := match goal with |- ?R ?a (?f ?x) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac sym_higher_order_1_reflexivity' :=
let a := match goal with |- ?R (?f ?x) ?a => constr:(a) end in
let f := match goal with |- ?R (?f ?x) ?a => constr:(f) end in
let x := match goal with |- ?R (?f ?x) ?a => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
(* refine is an antisymmetric relation, so we can try to apply
symmetric versions of higher_order_1_reflexivity. *)
Ltac higher_order_1_reflexivity :=
solve [ higher_order_1_reflexivity'
| sym_higher_order_1_reflexivity' ].
Ltac higher_order_1_f_reflexivity :=
let a := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(a) end in
let f := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(f) end in
let x := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
(* This applies reflexivity after refining a method. *)
Ltac higher_order_2_reflexivity' :=
let x := match goal with |- ?R ?x (?f ?a ?b) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac sym_higher_order_2_reflexivity' :=
let x := match goal with |- ?R (?f ?a ?b) ?x => constr:(x) end in
let f := match goal with |- ?R (?f ?a ?b) ?x => constr:(f) end in
let a := match goal with |- ?R (?f ?a ?b) ?x => constr:(a) end in
let b := match goal with |- ?R (?f ?a ?b) ?x => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_2_reflexivity :=
solve [ higher_order_2_reflexivity'
| sym_higher_order_2_reflexivity' ].
Ltac higher_order_2_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_3_reflexivity :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_3_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_4_reflexivity :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(c) end in
let d := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_4_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(c) end in
let d := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_reflexivity :=
match goal with
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => higher_order_4_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => higher_order_3_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a ?b)) => higher_order_2_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a)) => higher_order_1_f_reflexivity
| |- ?R ?x (?f ?a ?b ?c ?d) => higher_order_4_reflexivity
| |- ?R ?x (?f ?a ?b ?c) => higher_order_3_reflexivity
| |- ?R ?x (?f ?a ?b) => higher_order_2_reflexivity
| |- ?R ?x (?f ?a) => higher_order_1_reflexivity
| |- _ => reflexivity
end.
Ltac pre_higher_order_reflexivity_single_evar :=
idtac;
match goal with
| [ |- ?L = ?R ] => has_evar R; not has_evar L; symmetry
| [ |- ?L = ?R ] => has_evar L; not has_evar R
| [ |- ?L = ?R ] => fail 1 "Goal has evars on both sides of the equality" L "=" R
| [ |- ?G ] => fail 1 "Goal is not an equality" G
end.
Ltac higher_order_reflexivity_single_evar_step :=
clear;
match goal with
| [ |- ?f ?x = ?R ] => is_var x; revert x
| [ |- ?f ?x = ?R ]
=> not has_evar x;
let R' := (eval pattern x in R) in
change (f x = R' x)
end;
(lazymatch goal with
| [ |- forall x, ?f x = @?R x ]
=> refine (fun x => f_equal (fun F => F x) (_ : f = R))
| [ |- ?f ?x = ?R ?x ]
=> refine (f_equal (fun F => F x) (_ : f = R))
end);
clear.
Ltac higher_order_reflexivity_single_evar :=
pre_higher_order_reflexivity_single_evar;
repeat (reflexivity || higher_order_reflexivity_single_evar_step).
Ltac higher_order_1_reflexivityT' :=
let a := match goal with |- ?R ?a (?f ?x) => constr:(a) end in
let f := match goal with |- ?R ?a (?f ?x) => constr:(f) end in
let x := match goal with |- ?R ?a (?f ?x) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac sym_higher_order_1_reflexivityT' :=
let a := match goal with |- ?R (?f ?x) ?a => constr:(a) end in
let f := match goal with |- ?R (?f ?x) ?a => constr:(f) end in
let x := match goal with |- ?R (?f ?x) ?a => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
(* refine is an antisymmetric relation, so we can try to apply
symmetric versions of higher_order_1_reflexivityT. *)
Ltac higher_order_1_reflexivityT :=
solve [ higher_order_1_reflexivityT'
| sym_higher_order_1_reflexivityT' ].
Ltac higher_order_1_f_reflexivityT :=
let a := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(a) end in
let f := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(f) end in
let x := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
(* This applies reflexivityT after refining a method. *)
Ltac higher_order_2_reflexivityT' :=
let x := match goal with |- ?R ?x (?f ?a ?b) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac sym_higher_order_2_reflexivityT' :=
let x := match goal with |- ?R (?f ?a ?b) ?x => constr:(x) end in
let f := match goal with |- ?R (?f ?a ?b) ?x => constr:(f) end in
let a := match goal with |- ?R (?f ?a ?b) ?x => constr:(a) end in
let b := match goal with |- ?R (?f ?a ?b) ?x => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_2_reflexivityT :=
solve [ higher_order_2_reflexivityT'
| sym_higher_order_2_reflexivityT' ].
Ltac higher_order_2_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_3_reflexivityT :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_3_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_4_reflexivityT :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(c) end in
let d := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_4_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(c) end in
let d := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_0_f_reflexivityT :=
match goal with
|- ?R (?g ?a) (?g' ?x) =>
unify a x; solve [apply reflexivityT]
end.
Ltac higher_order_reflexivityT :=
match goal with
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => higher_order_4_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => higher_order_3_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a ?b)) => higher_order_2_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a)) => higher_order_1_f_reflexivityT
| |- ?R (?g ?a) (?g' ?x) => higher_order_0_f_reflexivityT
| |- ?R ?x (?f ?a ?b ?c ?d) => higher_order_4_reflexivityT
| |- ?R ?x (?f ?a ?b ?c) => higher_order_3_reflexivityT
| |- ?R ?x (?f ?a ?b) => higher_order_2_reflexivityT
| |- ?R ?x (?f ?a) => higher_order_1_reflexivityT
| |- _ => reflexivityT
end.
Global Arguments f_equal {A B} f {x y} _ .
Lemma fst_fold_right {A B A'} (f : B -> A -> A) (g : B -> A * A' -> A') a a' ls
: fst (fold_right (fun b aa' => (f b (fst aa'), g b aa')) (a, a') ls)
= fold_right f a ls.
Proof.
induction ls; simpl; trivial.
rewrite IHls; reflexivity.
Qed.
Lemma if_app {A} (ls1 ls1' ls2 : list A) (b : bool)
: (if b then ls1 else ls1') ++ ls2 = if b then (ls1 ++ ls2) else (ls1' ++ ls2).
Proof.
destruct b; reflexivity.
Qed.
Definition pull_if_dep {A B} (P : forall b : bool, A b -> B b) (a : A true) (a' : A false)
(b : bool)
: P b (if b as b return A b then a else a') =
if b as b return B b then P _ a else P _ a'
:= match b with true => eq_refl | false => eq_refl end.
Definition pull_if {A B} (P : A -> B) (a a' : A) (b : bool)
: P (if b then a else a') = if b then P a else P a'
:= pull_if_dep (fun _ => P) a a' b.
(** From [email protected] on coq-club *)
Ltac simplify_hyp' H :=
let T := type of H in
let X := (match eval hnf in T with ?X -> _ => constr:(X) end) in
let H' := fresh in
assert (H' : X) by (tauto || congruence);
specialize (H H');
clear H'.
Ltac simplify_hyps :=
repeat match goal with
| [ H : ?X -> _ |- _ ] => simplify_hyp' H
| [ H : ~?X |- _ ] => simplify_hyp' H
end.
Local Ltac bool_eq_t :=
destruct_head_hnf bool; simpl;
repeat (split || intro || destruct_head iff || congruence);
repeat match goal with
| [ H : ?x = ?x -> _ |- _ ] => specialize (H eq_refl)
| [ H : ?x <> ?x |- _ ] => specialize (H eq_refl)
| [ H : False |- _ ] => destruct H
| _ => progress simplify_hyps
| [ H : ?x = ?y |- _ ] => solve [ inversion H ]
| [ H : false = true -> _ |- _ ] => clear H
end.
Lemma bool_true_iff_beq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> b2 = b3) <-> (b0 = (if b1
then if b3
then b2
else negb b2
else if b3
then negb b2
else b2)).
Proof. bool_eq_t. Qed.
Lemma bool_true_iff_bneq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> b2 <> b3) <-> (b0 = (if b1
then if b3
then negb b2
else b2
else if b3
then b2
else negb b2)).
Proof. bool_eq_t. Qed.
Lemma bool_true_iff_bnneq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> ~b2 <> b3) <-> (b0 = (if b1
then if b3
then b2
else negb b2
else if b3
then negb b2
else b2)).
Proof. bool_eq_t. Qed.
Lemma dn_eqb (x y : bool) : ~~(x = y) -> x = y.
Proof.
destruct x, y; try congruence;
intro H; exfalso; apply H; congruence.
Qed.
Lemma neq_to_eq_negb (x y : bool) : x <> y -> x = negb y.
Proof.
destruct x, y; try congruence; try tauto.
Qed.
Lemma InA_In {A} R (ls : list A) x `{Reflexive _ R}
: List.In x ls -> InA R x ls.
Proof.
revert x.
induction ls; simpl; try tauto.
intros ? [?|?]; subst; [ left | right ]; auto.
Qed.
Lemma InA_In_eq {A} (ls : list A) x
: InA eq x ls <-> List.In x ls.
Proof.
split; [ | eapply InA_In; exact _ ].
revert x.
induction ls; simpl.
{ intros ? H. inversion H. }
{ intros ? H.
inversion H; subst;
first [ left; reflexivity
| right; eauto ]. }
Qed.
Lemma NoDupA_NoDup {A} R (ls : list A) `{Reflexive _ R}
: NoDupA R ls -> NoDup ls.
Proof.
intro H'.
induction H'; constructor; auto.
intro H''; apply (@InA_In _ R) in H''; intuition.
Qed.
Lemma push_if_existT {A} (P : A -> Type) (b : bool) (x y : sigT P)
: (if b then x else y)
= existT P
(if b then (projT1 x) else (projT1 y))
(if b as b return P (if b then (projT1 x) else (projT1 y))
then projT2 x
else projT2 y).
Proof.
destruct b, x, y; reflexivity.
Defined.
(** TODO: Find a better place for these *)
Lemma fold_right_projT1 {A B X} (P : A -> Type) (init : A * B) (ls : list X) (f : X -> A -> A) (g : X -> A -> B -> B) pf pf'
: List.fold_right (fun (x : X) (acc : A * B) =>
(f x (fst acc), g x (fst acc) (snd acc)))
init
ls
= let fr := List.fold_right (fun (x : X) (acc : sigT P * B) =>
(existT P (f x (projT1 (fst acc))) (pf' x acc),
g x (projT1 (fst acc)) (snd acc)))
(existT P (fst init) pf, snd init)
ls in
(projT1 (fst fr), snd fr).
Proof.
revert init pf.
induction ls; simpl; intros [? ?]; trivial; simpl.
intro.
simpl in *.
erewrite IHls; simpl.
reflexivity.
Qed.
Lemma fold_right_projT1' {A X} (P : A -> Type) (init : A) (ls : list X) (f : X -> A -> A) pf pf'
: List.fold_right f init ls
= projT1 (List.fold_right (fun (x : X) (acc : sigT P) =>
existT P (f x (projT1 acc)) (pf' x acc))
(existT P init pf)
ls).
Proof.
revert init pf.
induction ls; simpl; intros; trivial; simpl.
simpl in *.
erewrite IHls; simpl.
reflexivity.
Qed.
Fixpoint combine_sig_helper {T} {P : T -> Prop} (ls : list T) : (forall x, In x ls -> P x) -> list (sig P).
Proof.
refine match ls with
| nil => fun _ => nil
| x::xs => fun H => (exist _ x _)::@combine_sig_helper _ _ xs _
end;
clear combine_sig_helper; simpl in *;
intros;
apply H;
first [ left; reflexivity
| right; assumption ].
Defined.
Lemma Forall_forall1_transparent_helper_1 {A P} {x : A} {xs : list A} {l : list A}
(H : Forall P l) (H' : x::xs = l)
: P x.
Proof.
subst; inversion H; repeat subst; assumption.
Defined.
Lemma Forall_forall1_transparent_helper_2 {A P} {x : A} {xs : list A} {l : list A}
(H : Forall P l) (H' : x::xs = l)
: Forall P xs.
Proof.
subst; inversion H; repeat subst; assumption.
Defined.
Fixpoint Forall_forall1_transparent {A} (P : A -> Prop) (l : list A) {struct l}
: Forall P l -> forall x, In x l -> P x
:= match l as l return Forall P l -> forall x, In x l -> P x with
| nil => fun _ _ f => match f : False with end
| x::xs => fun H x' H' =>
match H' with
| or_introl H'' => eq_rect x
P
(Forall_forall1_transparent_helper_1 H eq_refl)
_
H''
| or_intror H'' => @Forall_forall1_transparent A P xs (Forall_forall1_transparent_helper_2 H eq_refl) _ H''
end
end.
Definition combine_sig {T P ls} (H : List.Forall P ls) : list (@sig T P)
:= combine_sig_helper ls (@Forall_forall1_transparent T P ls H).
Arguments Forall_forall1_transparent_helper_1 : simpl never.
Arguments Forall_forall1_transparent_helper_2 : simpl never.
Lemma In_combine_sig {T P ls H x} (H' : In x ls)
: In (exist P x (@Forall_forall1_transparent T P ls H _ H')) (combine_sig H).
Proof.
unfold combine_sig.
induction ls; simpl in *; trivial.
destruct_head or; subst;
try first [ left; reflexivity ].
right.
revert H.
match goal with
| [ |- context[@eq_refl ?A ?a] ] => generalize (@eq_refl A a)
end.
set (als := a::ls) in *.
change als with (a::ls) at 1.
clearbody als.
intros e H.
destruct H; [ exfalso; solve [ inversion e ] | ].
apply IHls.
Defined.
Fixpoint flatten1 {T} (ls : list (list T)) : list T
:= match ls with
| nil => nil
| x::xs => (x ++ flatten1 xs)%list
end.
Lemma flatten1_length_ne_0 {T} (ls : list (list T)) (H0 : Datatypes.length ls <> 0)
(H1 : Datatypes.length (hd nil ls) <> 0)
: Datatypes.length (flatten1 ls) <> 0.
Proof.
destruct ls as [| [|] ]; simpl in *; auto.
Qed.
Local Hint Constructors List.Forall.
Lemma Forall_app {T} P (ls1 ls2 : list T)
: List.Forall P ls1 /\ List.Forall P ls2 <-> List.Forall P (ls1 ++ ls2).
Proof.
split.
{ intros [H1 H2].
induction H1; simpl; auto. }
{ intro H; split; induction ls1; simpl in *; auto.
{ inversion_clear H; auto. }
{ inversion_clear H; auto. } }
Qed.
Lemma Forall_flatten1 {T ls P}
: List.Forall P (@flatten1 T ls) <-> List.Forall (List.Forall P) ls.
Proof.
induction ls; simpl.
{ repeat first [ esplit | intro | constructor ]. }
{ etransitivity; [ symmetry; apply Forall_app | ].
split_iff.
split.
{ intros [? ?]; auto. }
{ intro H'; inversion_clear H'; split; auto. } }
Qed.
Lemma Forall_map {A B} {f : A -> B} {ls P}
: List.Forall P (map f ls) <-> List.Forall (P ∘ f) ls.
Proof.
induction ls; simpl.
{ repeat first [ esplit | intro | constructor ]. }
{ split_iff.
split;
intro H'; inversion_clear H'; auto. }
Qed.
Lemma fold_right_map {A B C} (f : A -> B) g c ls
: @fold_right C B g
c
(map f ls)
= fold_right (g ∘ f) c ls.
Proof.
induction ls; unfold compose; simpl; f_equal; auto.
Qed.
Lemma fold_right_orb_true ls
: fold_right orb true ls = true.
Proof.
induction ls; destruct_head_hnf bool; simpl in *; trivial.
Qed.
Lemma fold_right_orb b ls
: fold_right orb b ls = true
<-> fold_right or (b = true) (map (fun x => x = true) ls).
Proof.
induction ls; simpl; intros; try reflexivity.
rewrite <- IHls; clear.
repeat match goal with
| _ => assumption
| _ => split
| _ => intro
| _ => progress subst
| _ => progress simpl in *
| _ => progress destruct_head or
| _ => progress destruct_head bool
| _ => left; reflexivity
| _ => right; assumption
end.
Qed.
Local Hint Constructors Exists.
Local Ltac fold_right_orb_map_sig_t :=
repeat match goal with
| _ => split
| _ => intro
| _ => progress simpl in *
| _ => progress subst
| _ => progress destruct_head sumbool
| _ => progress destruct_head sig
| _ => progress destruct_head and
| _ => progress destruct_head or
| [ H : _ = true |- _ ] => rewrite H
| [ H : (_ || _)%bool = true |- _ ] => apply Bool.orb_true_elim in H
| [ H : ?a, H' : ?a -> ?b |- _ ] => specialize (H' H)
| [ H : ?a, H' : @sig ?a ?P -> ?b |- _ ] => specialize (fun b' => H' (exist P H b'))
| [ H' : _ /\ _ -> _ |- _ ] => specialize (fun a b => H' (conj a b))
| [ |- (?a || true)%bool = true ] => destruct a; reflexivity
| _ => solve [ eauto ]
| _ => congruence
end.
Lemma fold_right_orb_map_sig1 {T} f (ls : list T)
: fold_right orb false (map f ls) = true
-> sig (fun x => In x ls /\ f x = true).
Proof.
induction ls; fold_right_orb_map_sig_t.
Qed.
Lemma fold_right_orb_map_sig2 {T} f (ls : list T)
: sig (fun x => In x ls /\ f x = true)
-> fold_right orb false (map f ls) = true.
Proof.
induction ls; fold_right_orb_map_sig_t.
Qed.
Lemma fold_right_orb_map {T} f (ls : list T)
: fold_right orb false (map f ls) = true
<-> List.Exists (fun x => f x = true) ls.
Proof.
induction ls;
repeat match goal with
| _ => split
| _ => intro
| _ => progress simpl in *
| [ H : Exists _ [] |- _ ] => solve [ inversion H ]
| [ H : Exists _ (_::_) |- _ ] => inversion_clear H
| _ => progress split_iff
| _ => progress destruct_head sumbool
| [ H : (_ || _)%bool = true |- _ ] => apply Bool.orb_true_elim in H
| [ H : ?a, H' : ?a -> ?b |- _ ] => specialize (H' H)
| [ H : _ = true |- _ ] => rewrite H
| [ |- (?a || true)%bool = _ ] => destruct a; reflexivity
| _ => solve [ eauto ]
| _ => congruence
end.
Qed.
Lemma fold_right_map_andb_andb {T} x y f g (ls : list T)
: fold_right andb x (map f ls) = true /\ fold_right andb y (map g ls) = true
<-> fold_right andb (andb x y) (map (fun k => andb (f k) (g k)) ls) = true.
Proof.
induction ls; simpl; intros; destruct_head_hnf bool; try tauto;
rewrite !Bool.andb_true_iff;
try tauto.
Qed.
Lemma fold_right_map_andb_orb {T} x y f g (ls : list T)
: fold_right andb x (map f ls) = true /\ fold_right orb y (map g ls) = true
-> fold_right orb (andb x y) (map (fun k => andb (f k) (g k)) ls) = true.
Proof.
induction ls; simpl; intros; destruct_head_hnf bool; try tauto;
repeat match goal with
| [ H : _ |- _ ] => progress rewrite ?Bool.orb_true_iff, ?Bool.andb_true_iff in H
| _ => progress rewrite ?Bool.orb_true_iff, ?Bool.andb_true_iff
end;
try tauto.
Qed.
Lemma fold_right_map_and_and {T} x y f g (ls : list T)
: fold_right and x (map f ls) /\ fold_right and y (map g ls)
<-> fold_right and (x /\ y) (map (fun k => f k /\ g k) ls).
Proof.
revert x y.
induction ls; simpl; intros; try reflexivity.
rewrite <- IHls; clear.
tauto.
Qed.
Lemma fold_right_map_and_or {T} x y f g (ls : list T)
: fold_right and x (map f ls) /\ fold_right or y (map g ls)
-> fold_right or (x /\ y) (map (fun k => f k /\ g k) ls).
Proof.
revert x y.
induction ls; simpl; intros; try assumption.
intuition.
Qed.
Functional Scheme fold_right_rect := Induction for fold_right Sort Type.
Lemma fold_right_andb_map_impl {T} x y f g (ls : list T)
(H0 : x = true -> y = true)
(H1 : forall k, f k = true -> g k = true)
: (fold_right andb x (map f ls) = true -> fold_right andb y (map g ls) = true).
Proof.
induction ls; simpl; intros; try tauto.
rewrite IHls; simpl;
repeat match goal with
| [ H : _ = true |- _ ] => apply Bool.andb_true_iff in H
| [ |- _ = true ] => apply Bool.andb_true_iff
| _ => progress destruct_head and
| _ => split
| _ => auto
end.
Qed.
Lemma fold_right_andb_map_in_iff {A P} {ls : list A}
: fold_right andb true (map P ls) = true
<-> (forall x, List.In x ls -> P x = true).
Proof.
induction ls; simpl;
[
| rewrite Bool.andb_true_iff, IHls; clear IHls ];
intuition (subst; eauto).
Qed.
Lemma fold_right_andb_map_in {A P} {ls : list A} (H : fold_right andb true (map P ls) = true)
: forall x, List.In x ls -> P x = true.
Proof.
rewrite fold_right_andb_map_in_iff in H; assumption.
Qed.
Lemma if_ext {T} (b : bool) (f1 f2 : b = true -> T true) (g1 g2 : b = false -> T false)
(ext_f : forall H, f1 H = f2 H)
(ext_g : forall H, g1 H = g2 H)
: (if b as b' return (b = b' -> T b') then f1 else g1) eq_refl
= (if b as b' return (b = b' -> T b') then f2 else g2) eq_refl.
Proof.
destruct b; trivial.
Defined.
Class constr_eq_helper {T0 T1} (a : T0) (b : T1) := mkconstr_eq : True.
Hint Extern 0 (constr_eq_helper ?a ?b) => constr_eq a b; exact I : typeclass_instances.
(** return the first hypothesis with head [h] *)
Ltac hyp_with_head h
:= match goal with
| [ H : ?T |- _ ] => let h' := head T in
let test := constr:(_ : constr_eq_helper h' h) in
constr:(H)
end.
Ltac hyp_with_head_hnf h
:= match goal with
| [ H : ?T |- _ ] => let h' := head_hnf T in
let test := constr:(_ : constr_eq_helper h' h) in
constr:(H)
end.
Lemma or_False {A} (H : A \/ False) : A.
Proof.
destruct H as [ a | [] ].
exact a.
Qed.
Lemma False_or {A} (H : False \/ A) : A.
Proof.
destruct H as [ [] | a ].
exact a.
Qed.
Lemma path_prod {A B} {x y : A * B}
(H : x = y)
: fst x = fst y /\ snd x = snd y.
Proof.
destruct H; split; reflexivity.
Defined.
Definition path_prod' {A B} {x x' : A} {y y' : B}
(H : (x, y) = (x', y'))
: x = x' /\ y = y'
:= path_prod H.
Lemma lt_irrefl' {n m} (H : n = m) : ~n < m.
Proof.
subst; apply Lt.lt_irrefl.
Qed.
Lemma or_not_l {A B} (H : A \/ B) (H' : ~A) : B.
Proof.
destruct H; intuition.
Qed.
Lemma or_not_r {A B} (H : A \/ B) (H' : ~B) : A.
Proof.
destruct H; intuition.
Qed.
Ltac instantiate_evar :=
instantiate;
match goal with
| [ H : appcontext[?E] |- _ ]
=> is_evar E;
match goal with
| [ H' : _ |- _ ] => unify E H'
end
| [ |- appcontext[?E] ]
=> is_evar E;
match goal with
| [ H' : _ |- _ ] => unify E H'
end
end;
instantiate.
Ltac instantiate_evars :=
repeat instantiate_evar.
Ltac find_eassumption :=
match goal with
| [ H : ?T |- ?T' ] => constr:(H : T')
end.
Ltac pre_eassumption := idtac; let x := find_eassumption in idtac.
Definition functor_sum {A A' B B'} (f : A -> A') (g : B -> B') (x : sum A B) : sum A' B' :=
match x with
| inl a => inl (f a)
| inr b => inr (g b)
end.
Lemma impl_sum_match_match_option {A B ret s s' n r}
{x : option A}
(f : match x with
| Some x' => s x'
| None => n
end -> ret)
(g : s' r -> ret)
: match
match x return A + B with
| Some x' => inl x'
| None => inr r
end
with
| inl x' => s x'
| inr x' => s' x'
end -> ret.
Proof.
destruct x; assumption.
Defined.
Lemma impl_match_option {A ret s n}
{x : option A}
(f : forall x', x = Some x' -> s x' -> ret)
(g : x = None -> n -> ret)
: match x with
| Some x' => s x'
| None => n
end -> ret.
Proof.
destruct x; eauto.
Defined.
Definition option_bind {A} {B} (f : A -> option B) (x : option A)
: option B
:= match x with
| None => None
| Some a => f a
end.
Fixpoint ForallT {T} (P : T -> Type) (ls : list T) : Type
:= match ls return Type with
| nil => True
| x::xs => (P x * ForallT P xs)%type
end.
Fixpoint Forall_tails {T} (P : list T -> Type) (ls : list T) : Type
:= match ls with
| nil => P nil
| x::xs => (P (x::xs) * Forall_tails P xs)%type
end.
Fixpoint Forall_tailsP {T} (P : list T -> Prop) (ls : list T) : Prop
:= match ls with
| nil => P nil
| x::xs => (P (x::xs) /\ Forall_tailsP P xs)%type
end.
Fixpoint ForallT_all {T} {P : T -> Type} (p : forall t, P t) {ls}
: ForallT P ls
:= match ls with
| nil => I
| x::xs => (p _, @ForallT_all T P p xs)
end.
Fixpoint Forall_tails_all {T} {P : list T -> Type} (p : forall t, P t) {ls}
: Forall_tails P ls
:= match ls with
| nil => p _
| x::xs => (p _, @Forall_tails_all T P p xs)
end.
Fixpoint ForallT_impl {T} (P P' : T -> Type) (ls : list T) {struct ls}
: ForallT (fun x => P x -> P' x) ls
-> ForallT P ls
-> ForallT P' ls
:= match ls return ForallT (fun x => P x -> P' x) ls
-> ForallT P ls
-> ForallT P' ls
with
| nil => fun _ _ => I
| x::xs => fun H H' => (fst H (fst H'), @ForallT_impl T P P' xs (snd H) (snd H'))
end.
Fixpoint Forall_tails_impl {T} (P P' : list T -> Type) (ls : list T) {struct ls}
: Forall_tails (fun x => P x -> P' x) ls
-> Forall_tails P ls
-> Forall_tails P' ls
:= match ls return Forall_tails (fun x => P x -> P' x) ls
-> Forall_tails P ls
-> Forall_tails P' ls
with
| nil => fun H H' => H H'
| x::xs => fun H H' => (fst H (fst H'), @Forall_tails_impl T P P' xs (snd H) (snd H'))
end.
Ltac free_in x y :=
idtac;
match y with
| appcontext[x] => fail 1 x "appears in" y
| _ => idtac
end.
Ltac setoid_subst'' R x :=
atomic x;
match goal with
| [ H : R x ?y |- _ ]
=> free_in x y;
rewrite ?H;
repeat setoid_rewrite H;
repeat match goal with
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; rewrite H in H'
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; setoid_rewrite H in H'
end;
clear H;
clear x
| [ H : R ?y x |- _ ]
=> free_in x y;
rewrite <- ?H;
repeat setoid_rewrite <- H;
repeat match goal with
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; rewrite <- H in H'
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; setoid_rewrite <- H in H'
end;
clear H;
clear x
end.
Ltac setoid_subst' x :=
atomic x;
match goal with
| [ H : ?R x _ |- _ ] => setoid_subst'' R x
| [ H : ?R _ x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel' R :=
idtac;
match goal with
| [ H : R ?x _ |- _ ] => setoid_subst'' R x
| [ H : R _ ?x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel R := repeat setoid_subst_rel' R.
Ltac setoid_subst_all :=
repeat match goal with
| [ H : ?R ?x ?y |- _ ] => atomic x; setoid_subst'' R x
| [ H : ?R ?x ?y |- _ ] => atomic y; setoid_subst'' R y
end.
Tactic Notation "setoid_subst" ident(x) := setoid_subst' x.
Tactic Notation "setoid_subst" := setoid_subst_all.
Lemma sub_plus {x y z} (H0 : z <= y) (H1 : y <= x)
: x - (y - z) = (x - y) + z.
Proof. omega. Qed.
Lemma fold_right_and_iff {A ls}
: fold_right and A ls <-> (fold_right and True ls /\ A).
Proof.
induction ls; simpl; tauto.
Qed.
Definition impl0_0 {A} : A -> A := fun x => x.
Definition impl0_1 {A B C} : (B -> C) -> ((A -> B) -> (A -> C)). Proof. auto. Defined.
Definition impl1_1 {A B C} : (B -> A) -> ((A -> C) -> (B -> C)). Proof. auto. Defined.
Definition impl1_2 {A A' B C C'} : ((A -> C) -> (A' -> C')) -> ((A -> B -> C) -> (A' -> B -> C')). Proof. eauto. Defined.
Lemma if_aggregate {A} (b1 b2 : bool) (x y : A)
: (if b1 then x else if b2 then x else y) = (if (b1 || b2)%bool then x else y).
Proof.
destruct b1, b2; reflexivity.
Qed.
Lemma if_aggregate2 {A} (b1 b2 b3 : bool) (x y z : A) (H : b1 = false -> b2 = true -> b3 = true -> False)
: (if b1 then x else if b2 then y else if b3 then x else z) = (if (b1 || b3)%bool then x else if b2 then y else z).
Proof.
case_eq b1; case_eq b2; case_eq b3; try reflexivity; simpl; intros; exfalso; subst; eauto.
Qed.
Lemma if_aggregate3 {A} (b1 b2 b3 b4 : bool) (x y z w : A) (H : b1 = false -> (b2 || b3)%bool = true -> b4 = true -> False)
: (if b1 then x else if b2 then y else if b3 then z else if b4 then x else w) = (if (b1 || b4)%bool then x else if b2 then y else if b3 then z else w).
Proof.
case_eq b1; case_eq b2; case_eq b3; case_eq b4; try reflexivity; simpl; intros; exfalso; subst; eauto.
Qed.
Ltac eassumption' :=
eassumption
|| match goal with
| [ H : _ |- _ ] => exact H
end.
Ltac progress_subgoal top tac finish_fn cont :=
top; (* Decompose goal *)
(* idtac "Decomposing Goal"; For debugging *)
(tac; try (cont ()) (* Process goal further with tac and recurse. *)
|| (try (cont ())) (* Just recurse *)
|| finish_fn) (* Finish up if unable to progress after recursing *).
(* ltac is call-by-value, so wrap the cont in a function *)
(* local definition in a_u_s *)
Ltac cont_fn top tac'' finish_fn x :=
apply_under_subgoal top tac'' finish_fn with
(* mutually recursive with progress_subgoal *)
(* calls top on each subgoal generated, which may generate more subgoals *)
(* fails when top fails in progress_subgoals *)
apply_under_subgoal top tac'' finish_fn :=
progress_subgoal top tac'' finish_fn ltac:(cont_fn top tac'' finish_fn).
Ltac doAny srewrite_fn drills_fn finish_fn :=
let repeat_srewrite_fn := repeat srewrite_fn in
try repeat_srewrite_fn;
try apply_under_subgoal drills_fn ltac:(repeat_srewrite_fn) finish_fn;
finish_fn.
Ltac set_refine_evar :=
match goal with
| |- ?R _ (?H _ _ _ _ _) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _ _ _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _ _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H ) =>
let H' := fresh in set (H' := H) in *
end.
Ltac subst_refine_evar :=
match goal with
| |- ?R _ (?H _ _ _ _ _) => subst H
| |- ?R _ (?H _ _ _ _ ) => subst H
| |- ?R _ (?H _ _ _ ) => subst H
| |- ?R _ (?H _ _) => subst H
| |- ?R _ (?H _ ) => subst H
| |- ?R _ (?H ) => subst H
| _ => idtac
end.
(** Change hypotheses of the form [(exists x : A, B x) -> T] into hypotheses of the form [forall (x : A), B x -> T] *)
Class flatten_exC {T} (x : T) {retT} := make_flatten_exC : retT.
Ltac flatten_ex_helper H rec_tac rec_tac_progress :=
let T := type of H in
match eval cbv beta in T with
| forall x : @ex ?A ?B, @?C x => let ret := constr:(fun (a : A) (y : B a) => H (@ex_intro A B a y)) in
rec_tac_progress ret
| forall x : and ?A ?B, @?C x => let ret := constr:(fun (a : A) (b : B) => H (@conj A B a b)) in
rec_tac_progress ret
| forall x : ?A, @?P x => let ret := constr:(fun (x : A) => _ : flatten_exC (H x)) in
let ret := (eval cbv beta delta [flatten_exC] in ret) in
let retT := type of ret in
let retT := (eval cbv beta delta [flatten_exC] in retT) in
let ret := constr:(ret : retT) in
rec_tac ret
end.
Ltac flatten_ex H :=
match H with
| _ => flatten_ex_helper H ltac:(fun x => constr:(x)) flatten_ex
| _ => H
end.
Ltac progress_flatten_ex H :=
flatten_ex_helper H progress_flatten_ex flatten_ex.
Hint Extern 0 (flatten_exC ?H) => let ret := progress_flatten_ex H in exact ret : typeclass_instances.
Ltac flatten_all_ex :=
repeat match goal with
| [ H : context[ex _ -> _] |- _ ]
=> let H' := fresh in
rename H into H';
let term := flatten_ex H' in
pose proof term as H;
cbv beta in H;
clear H'
end.
Fixpoint apply_n {A} (n : nat) (f : A -> A) (a : A) : A :=
match n with
| 0 => a
| S n' => apply_n n' f (f a)
end.
Lemma apply_n_commute {A} n (f : A -> A) v
: apply_n n f (f v) = f (apply_n n f v).
Proof.
revert v; induction n; simpl; trivial.
Qed.
(** Transparent versions of [proj1], [proj2] *)
Definition proj1' : forall {A B}, A /\ B -> A.
Proof. intros ?? [? ?]; assumption. Defined.
Definition proj2' : forall {A B}, A /\ B -> B.
Proof. intros ?? [? ?]; assumption. Defined.
Definition injective_projections'
: forall {A B} {p1 p2 : A * B},
fst p1 = fst p2 -> snd p1 = snd p2 -> p1 = p2.
Proof.
intros; destruct p1, p2; simpl in *; subst; reflexivity.
Defined.
Global Arguments injective_projections' {_ _ _ _} !_ !_.
Module opt.
Definition fst {A B} := Eval compute in @fst A B.
Definition snd {A B} := Eval compute in @snd A B.
End opt.
(** Work around broken [intros []] in trunk (https://coq.inria.fr/bugs/show_bug.cgi?id=4470) *)
Definition intros_destruct_dummy := True.
Ltac intros_destruct :=
assert intros_destruct_dummy by constructor;
let H := fresh in
intro H; destruct H;
repeat match goal with
| [ H' : ?T |- _ ] => first [ constr_eq T intros_destruct_dummy;
fail 2
| revert H' ]
end;
match goal with
| [ H : intros_destruct_dummy |- _ ] => clear H
end.
(** Work around bug 4494, https://coq.inria.fr/bugs/show_bug.cgi?id=4494 (replace is slow and broken under binders *)
Ltac replace_with_at_by x y set_tac tac :=
let H := fresh in
let x' := fresh in
set_tac x' x;
assert (H : y = x') by (subst x'; tac);
clearbody x'; induction H.
Ltac replace_with_at x y set_tac :=
let H := fresh in
let x' := fresh in
set_tac x' x;
cut (y = x');
[ intro H; induction H
| subst x' ].
Tactic Notation "replace" constr(x) "with" constr(y) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) ).
Tactic Notation "replace" constr(x) "with" constr(y) "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H at n ) tac.
Ltac replace_with_vm_compute c :=
let c' := (eval vm_compute in c) in
(* we'd like to just do: *)
(* replace c with c' by (clear; abstract (vm_compute; reflexivity)) *)
(* but [set] is too slow in 8.4, so we write our own version (see https://coq.inria.fr/bugs/show_bug.cgi?id=3280#c13 *)
let set_tac := (fun x' x
=> pose x as x';
change x with x') in
replace_with_at_by c c' set_tac ltac:(clear; vm_cast_no_check (eq_refl c')).
Ltac replace_with_vm_compute_in c H :=
let c' := (eval vm_compute in c) in
(* By constrast [set ... in ...] seems faster than [change .. with ... in ...] in 8.4?! *)
replace c with c' in H by (clear; vm_cast_no_check (eq_refl c')).
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:21:26 03/31/2016
// Design Name: Top
// Module Name: C:/Users/Ranolazine/Desktop/board_eelab_final_back/lab5_v1/test.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg CLOCK;
reg RESET;
reg [2:0] SW;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK(CLOCK),
.RESET(RESET),
.SW(SW),
.LED(LED)
);
always #15 CLOCK = ~CLOCK;
initial begin
// Initialize Inputs
CLOCK = 0;
RESET = 1;
SW = 0;
// Wait 100 ns for global reset to finish
#100;
RESET = 0 ;
// Add stimulus here
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_c3fe_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_c3fe_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:38:31 06/05/2007
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
sysClk,
reset,
TILE0_REFCLK_PAD_N_IN, TILE0_REFCLK_PAD_P_IN, TILE1_REFCLK_PAD_N_IN, TILE1_REFCLK_PAD_P_IN,
TILE2_REFCLK_PAD_N_IN, TILE2_REFCLK_PAD_P_IN, TILE3_REFCLK_PAD_N_IN, TILE3_REFCLK_PAD_P_IN,
GTPRESET_IN,
RXN_IN, RXP_IN, TXN_OUT, TXP_OUT,
phy_rst_pad_0_o,
DataOut_pad_0_o, TxValid_pad_0_o, TxReady_pad_0_i,
RxValid_pad_0_i, RxActive_pad_0_i, RxError_pad_0_i,
DataIn_pad_0_i, XcvSelect_pad_0_o, TermSel_pad_0_o,
SuspendM_pad_0_o, LineState_pad_0_i,
OpMode_pad_0_o, usb_vbus_pad_0_i,
VControl_Load_pad_0_o, VControl_pad_0_o, VStatus_pad_0_i,
phy_rst_pad_1_o,
DataOut_pad_1_o, TxValid_pad_1_o, TxReady_pad_1_i,
RxValid_pad_1_i, RxActive_pad_1_i, RxError_pad_1_i,
DataIn_pad_1_i, XcvSelect_pad_1_o, TermSel_pad_1_o,
SuspendM_pad_1_o, LineState_pad_1_i,
OpMode_pad_1_o, usb_vbus_pad_1_i,
VControl_Load_pad_1_o, VControl_pad_1_o, VStatus_pad_1_i,
or1200_clmode, or1200_pic_ints, or1200_pm_out
);
// clock and reset pads
input sysClk;
input reset;
// GTP pads
input TILE0_REFCLK_PAD_N_IN;
input TILE0_REFCLK_PAD_P_IN;
input TILE1_REFCLK_PAD_N_IN;
input TILE1_REFCLK_PAD_P_IN;
input TILE2_REFCLK_PAD_N_IN;
input TILE2_REFCLK_PAD_P_IN;
input TILE3_REFCLK_PAD_N_IN;
input TILE3_REFCLK_PAD_P_IN;
input GTPRESET_IN;
input [7:0] RXN_IN;
input [7:0] RXP_IN;
output [7:0] TXN_OUT;
output [7:0] TXP_OUT;
// USB 0 UTMI pads
output phy_rst_pad_0_o;
output [7:0] DataOut_pad_0_o;
output TxValid_pad_0_o;
input TxReady_pad_0_i;
input [7:0] DataIn_pad_0_i;
input RxValid_pad_0_i;
input RxActive_pad_0_i;
input RxError_pad_0_i;
output XcvSelect_pad_0_o;
output TermSel_pad_0_o;
output SuspendM_pad_0_o;
input [1:0] LineState_pad_0_i;
output [1:0] OpMode_pad_0_o;
input usb_vbus_pad_0_i;
output VControl_Load_pad_0_o;
output [3:0] VControl_pad_0_o;
input [7:0] VStatus_pad_0_i;
// USB 1 UTMI pads
output phy_rst_pad_1_o;
output [7:0] DataOut_pad_1_o;
output TxValid_pad_1_o;
input TxReady_pad_1_i;
input [7:0] DataIn_pad_1_i;
input RxValid_pad_1_i;
input RxActive_pad_1_i;
input RxError_pad_1_i;
output XcvSelect_pad_1_o;
output TermSel_pad_1_o;
output SuspendM_pad_1_o;
input [1:0] LineState_pad_1_i;
output [1:0] OpMode_pad_1_o;
input usb_vbus_pad_1_i;
output VControl_Load_pad_1_o;
output [3:0] VControl_pad_1_o;
input [7:0] VStatus_pad_1_i;
//or1200 pads
input or1200_clmode, or1200_pic_ints;
output [3:0] or1200_pm_out;
// wishbone master 0 signals
wire m0_stb_i;
wire [31:0] m0_data_o;
wire [31:0] m0_data_i;
wire m0_ack_o;
wire m0_err_o;
wire m0_rty_o;
wire [31:0] m0_addr_i;
wire m0_we_i;
wire m0_cyc_i;
wire [3:0] m0_sel_i;
// wishbone master 1 signals
wire m1_stb_i;
wire [31:0] m1_data_o;
wire [31:0] m1_data_i;
wire m1_ack_o;
wire m1_err_o;
wire m1_rty_o;
wire [31:0] m1_addr_i;
wire m1_we_i;
wire m1_cyc_i;
wire [3:0] m1_sel_i;
// wishbone slave 0 signals
wire s0_stb_o;
wire [31:0] s0_data_o;
wire [31:0] s0_data_i;
wire s0_ack_i;
wire s0_err_i;
wire s0_rty_i;
wire [31:0] s0_addr_o;
wire s0_we_o;
wire s0_cyc_o;
wire [15:0] s0_sel_o;
// wishbone slave 1 signals
wire s1_stb_o;
wire [31:0] s1_data_o;
wire [31:0] s1_data_i;
wire s1_ack_i;
wire s1_err_i;
wire s1_rty_i;
wire [31:0] s1_addr_o;
wire s1_we_o;
wire s1_cyc_o;
wire [15:0] s1_sel_o;
// wishbone slave 2 signals
wire s2_stb_o;
wire [31:0] s2_data_o;
wire [31:0] s2_data_i;
wire s2_ack_i;
wire s2_err_i;
wire s2_rty_i;
wire [31:0] s2_addr_o;
wire s2_we_o;
wire s2_cyc_o;
wire [3:0] s2_sel_o;
// wishbone slave 3 signals
wire s3_stb_o;
wire [31:0] s3_data_o;
wire [31:0] s3_data_i;
wire s3_ack_i;
wire s3_err_i;
wire s3_rty_i;
wire [31:0] s3_addr_o;
wire s3_we_o;
wire s3_cyc_o;
wire [3:0] s3_sel_o;
//wisbone slave 4 signals
wire [31:0] s4_data_o;
wire [31:0] s4_data_i;
wire [31:0] s4_addr_o;
wire [3:0] s4_sel_o;
//usb wb signals
wire [31:0] wb_data_0;
wire [31:0] wb_data_1;
//register golbal inputs
reg reset_reg;
always @(posedge wbClk)
reset_reg <= reset;
// register usb_1 inputs
reg usb_vbus_pad_1_i_reg;
reg [3:0] VControl_pad_1_o;
wire [3:0] VControl_pad_1_o_temp;
reg [1:0] OpMode_pad_1_o;
wire [1:0] OpMode_pad_1_o_temp;
reg phy_rst_pad_1_o;
wire phy_rst_pad_1_o_temp;
reg SuspendM_pad_1_o;
wire SuspendM_pad_1_o_temp;
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (sysClk_int),
.I (sysClk));
// Take system clock and create internal clocks
clock_generator clkgen
(// Clock in ports
.sysClk (sysClk_int), // IN
// Clock out ports
.cpuClk_o (cpuClk), // OUT 50MHz
.wbClk_o (wbClk), // OUT 50MHz
.usbClk_o (usbClk), // OUT 100MHz
.phyClk0_o (phyClk0), // OUT 100MHz
.phyClk1_o (phyClk1), // OUT 100MHz
.fftClk_o (fftClk), // OUT 100MHz
// Status and control signals
.RESET (reset)); // IN
always @(posedge usbClk)
begin
usb_vbus_pad_1_i_reg <= usb_vbus_pad_1_i;
VControl_pad_1_o <= VControl_pad_1_o_temp;
OpMode_pad_1_o <= OpMode_pad_1_o_temp;
SuspendM_pad_1_o <= SuspendM_pad_1_o_temp;
phy_rst_pad_1_o <= phy_rst_pad_1_o_temp;
end
// register usb_0 inputs
reg usb_vbus_pad_0_i_reg;
reg [3:0] VControl_pad_0_o;
wire [3:0] VControl_pad_0_o_temp;
reg [1:0] OpMode_pad_0_o;
wire [1:0] OpMode_pad_0_o_temp;
reg phy_rst_pad_0_o;
wire phy_rst_pad_0_o_temp;
reg SuspendM_pad_0_o;
wire SuspendM_pad_0_o_temp;
always @(posedge usbClk)
begin
usb_vbus_pad_0_i_reg <= usb_vbus_pad_0_i;
VControl_pad_0_o <= VControl_pad_0_o_temp;
OpMode_pad_0_o <= OpMode_pad_0_o_temp;
SuspendM_pad_0_o <= SuspendM_pad_0_o_temp;
phy_rst_pad_0_o <= phy_rst_pad_0_o_temp;
end
// MGT Engine - wishbone slave 2
mgtTop mgtEngine (
.Q0_CLK0_GTREFCLK_PAD_N_IN(TILE0_REFCLK_PAD_N_IN),
.Q0_CLK0_GTREFCLK_PAD_P_IN(TILE0_REFCLK_PAD_P_IN),
.Q0_CLK1_GTREFCLK_PAD_N_IN(TILE1_REFCLK_PAD_N_IN),
.Q0_CLK1_GTREFCLK_PAD_P_IN(TILE1_REFCLK_PAD_P_IN),
.Q1_CLK0_GTREFCLK_PAD_N_IN(TILE2_REFCLK_PAD_N_IN),
.Q1_CLK0_GTREFCLK_PAD_P_IN(TILE2_REFCLK_PAD_P_IN),
.Q1_CLK1_GTREFCLK_PAD_N_IN(TILE3_REFCLK_PAD_N_IN),
.Q1_CLK1_GTREFCLK_PAD_P_IN(TILE3_REFCLK_PAD_P_IN),
.SYSCLK_IN(sysClk_int),
.GTTXRESET_IN(GTPRESET_IN),
.GTRXRESET_IN(GTPRESET_IN),
.TRACK_DATA_OUT(TRACK_DATA_OUT),
.RXN_IN(RXN_IN),
.RXP_IN(RXP_IN),
.TXN_OUT(TXN_OUT),
.TXP_OUT(TXP_OUT),
.wb_clk(wbClk), .wb_reset(reset_reg), .wb_stb_i(s2_stb_o), .wb_dat_o(s2_data_i), .wb_dat_i(s2_data_o), .wb_ack_o(s2_ack_i),
.wb_adr_i(s2_addr_o),.wb_we_i(s2_we_o), .wb_cyc_i(s2_cyc_o), .wb_sel_i(s2_sel_o), .wb_err_o(s2_err_i), .wb_rty_o(s2_rty_i)
);
// FFT engine -wishbone slave 3
fftTop fftEngine (
.wb_clk(wbClk), .clk(fftClk), .reset(reset_reg),
.wb_stb_i(s3_stb_o), .wb_dat_o(s3_data_i), .wb_dat_i(s3_data_o), .wb_ack_o(s3_ack_i),
.wb_adr_i(s3_addr_o), .wb_we_i(s3_we_o), .wb_cyc_i(s3_cyc_o), .wb_sel_i(s3_sel_o), .wb_err_o(s3_err_i), .wb_rty_o(s3_rty_i)
);
// open risc processor - wishbone master 0
or1200_top cpuEngine (
.wb_clk(wbClk), .clk_i(cpuClk), .rst_i(reset_reg), .pic_ints_i(or1200_pic_ints), .clmode_i(or1200_clmode),
.iwb_clk_i(wbClk), .iwb_rst_i(reset), .iwb_ack_i(m0_ack_o), .iwb_err_i(m0_err_o), .iwb_rty_i(m0_rty_o),
.iwb_dat_i(m0_data_o), .iwb_cyc_o(m0_cyc_i), .iwb_adr_o(m0_addr_i), .iwb_stb_o(m0_stb_i), .iwb_we_o(m0_we_i),
.iwb_sel_o(m0_sel_i), .iwb_dat_o(m0_data_i), // .iwb_cab_o(),
.dwb_clk_i(wbClk), .dwb_rst_i(reset_reg), .dwb_ack_i(m1_ack_o), .dwb_err_i(m1_err_o), .dwb_rty_i(m1_rty_o),
.dwb_dat_i(m1_data_o), .dwb_cyc_o(m1_cyc_i), .dwb_adr_o(m1_addr_i), .dwb_stb_o(m1_stb_i), .dwb_we_o(m1_we_i),
.dwb_sel_o(m1_sel_i), .dwb_dat_o(m1_data_i), // .dwb_cab_o(),
.dbg_stall_i(m0_rty_o), .dbg_ewt_i(m0_rty_o), .dbg_is_o(s4_err_i), .dbg_bp_o(s4_rty_i), .dbg_stb_i(s3_ack_i),
.dbg_we_i(m0_rty_o), .dbg_adr_i(s4_addr_o), .dbg_dat_i(s4_data_o), .dbg_dat_o(s4_data_i), .dbg_ack_o(s4_ack_i),
.pm_cpustall_i(m0_stb_i), .pm_clksd_o(or1200_pm_out)//, .pm_dc_gate_o(), .pm_ic_gate_o(), .pm_dmmu_gate_o(), .pm_immu_gate_o(),
//.pm_tt_gate_o()
//, .pm_cpu_gate_o(), .pm_wakeup_o(), .pm_lvolt_o()
);
wire rectify_reset;
assign rectify_reset = reset_reg;
// Wishbone Arbiter
//wb_conmax_top
wb_conmax_top #( 32, // Data Bus width
32, // Address Bus width
4'hf, // Register File Address
2'h1, // Number of priorities for Slave 0
2'h1 // Number of priorities for Slave 1
// Priorities for Slave 2 through 15 will default to 2\u2019h2
) wbArbEngine (
//code modification for a third part synthesis tool
// .clk_i(wbClk), .rst_i(reset_reg),
.clk_i(wbClk), .rst_i(rectify_reset),
// master 0 - or1200 instruction bus
.m0_data_i(m0_data_i), .m0_data_o(m0_data_o), .m0_addr_i(m0_addr_i), .m0_sel_i(m0_sel_i), .m0_we_i(m0_we_i), .m0_cyc_i(m0_cyc_i),
.m0_stb_i(m0_stb_i), .m0_ack_o(m0_ack_o), .m0_err_o(m0_err_o), .m0_rty_o(m0_rty_o),
// master 1 - or1200 data bus
.m1_data_i(m1_data_i), .m1_data_o(m1_data_o), .m1_addr_i(m1_addr_i), .m1_sel_i(m1_sel_i), .m1_we_i(m1_we_i), .m1_cyc_i(m1_cyc_i),
.m1_stb_i(m1_stb_i), .m1_ack_o(m1_ack_o), .m1_err_o(m1_err_o), .m1_rty_o(m1_rty_o),
// slave 0 - usb core 0
.s0_data_i(s0_data_i), .s0_data_o(s0_data_o), .s0_addr_o(s0_addr_o), .s0_sel_o(s0_sel_o), .s0_we_o(s0_we_o), .s0_cyc_o(s0_cyc_o),
.s0_stb_o(s0_stb_o), .s0_ack_i(s0_ack_i), .s0_err_i(s0_err_i), .s0_rty_i(s0_rty_i),
// slave 1 - usb core 1
.s1_data_i(s1_data_i), .s1_data_o(s1_data_o), .s1_addr_o(s1_addr_o), .s1_sel_o(s1_sel_o), .s1_we_o(s1_we_o), .s1_cyc_o(s1_cyc_o),
.s1_stb_o(s1_stb_o), .s1_ack_i(s1_ack_i), .s1_err_i(s1_err_i), .s1_rty_i(s1_rty_i),
// slave 2 - mgt engine
.s2_data_i(s2_data_i), .s2_data_o(s2_data_o), .s2_addr_o(s2_addr_o), .s2_sel_o(s2_sel_o), .s2_we_o(s2_we_o), .s2_cyc_o(s2_cyc_o),
.s2_stb_o(s2_stb_o), .s2_ack_i(s2_ack_i), .s2_err_i(s2_err_i), .s2_rty_i(s2_rty_i),
// slave 3 - fft engine
.s3_data_i(s3_data_i), .s3_data_o(s3_data_o), .s3_addr_o(s3_addr_o), .s3_sel_o(s3_sel_o), .s3_we_o(s3_we_o), .s3_cyc_o(s3_cyc_o),
// .s3_stb_o(s3_stb_o), .s3_ack_i(s3_ack_i), .s3_err_i(s3_err_i), .s3_rty_i(s3_rty_i),
.s3_stb_o(s3_stb_o), .s3_ack_i(s3_ack_i), .s3_err_i(s3_err_i), .s3_rty_i(s3_rty_i)
// master 2 - unused
// .m2_data_i(1'b0), .m2_data_o(), .m2_addr_i(1'b0), .m2_sel_i(1'b0), .m2_we_i(1'b0), .m2_cyc_i(1'b0),
// .m2_stb_i(1'b0), .m2_ack_o(), .m2_err_o(), .m2_rty_o(),
// master 3 - unused
// .m3_data_i(1'b0), .m3_data_o(), .m3_addr_i(1'b0), .m3_sel_i(1'b0), .m3_we_i(1'b0), .m3_cyc_i(1'b0),
// .m3_stb_i(1'b0), .m3_ack_o(), .m3_err_o(), .m3_rty_o(),
// master 4 - unused
// .m4_data_i(1'b0), .m4_data_o(), .m4_addr_i(1'b0), .m4_sel_i(1'b0), .m4_we_i(1'b0), .m4_cyc_i(1'b0),
// .m4_stb_i(1'b0), .m4_ack_o(), .m4_err_o(), .m4_rty_o(),
// master 5 - unused
// .m5_data_i(1'b0), .m5_data_o(), .m5_addr_i(1'b0), .m5_sel_i(1'b0), .m5_we_i(1'b0), .m5_cyc_i(1'b0),
// .m5_stb_i(1'b0), .m5_ack_o(), .m5_err_o(), .m5_rty_o(),
// master 6 - unused
// .m6_data_i(1'b0), .m6_data_o(), .m6_addr_i(1'b0), .m6_sel_i(1'b0), .m6_we_i(1'b0), .m6_cyc_i(1'b0),
// .m6_stb_i(1'b0), .m6_ack_o(), .m6_err_o(), .m6_rty_o(),
// master 7 - unused
// .m7_data_i(1'b0), .m7_data_o(), .m7_addr_i(1'b0), .m7_sel_i(1'b0), .m7_we_i(1'b0), .m7_cyc_i(1'b0),
// .m7_stb_i(1'b0), .m7_ack_o(), .m7_err_o(), .m7_rty_o(),
//slave 4 - cpu debug data
, .s4_data_i(s4_data_i), .s4_data_o(s4_data_o), .s4_addr_o(s4_addr_o), .s4_sel_o(), .s4_we_o(), .s4_cyc_o(),
.s4_stb_o(), .s4_ack_i(s4_ack_i), .s4_err_i(s4_err_i), .s4_rty_i(s4_rty_i)
// slave 5 - unused
// .s5_data_i(1'b0), .s5_data_o(), .s5_addr_o(), .s5_sel_o(), .s5_we_o(), .s5_cyc_o(),
// .s5_stb_o(), .s5_ack_i(1'b0), .s5_err_i(1'b0), .s5_rty_i(1'b0),
// slave 6 - unused
// .s6_data_i(1'b0), .s6_data_o(), .s6_addr_o(), .s6_sel_o(), .s6_we_o(), .s6_cyc_o(),
// .s6_stb_o(), .s6_ack_i(1'b0), .s6_err_i(1'b0), .s6_rty_i(1'b0),
// slave 7 - unused
// .s7_data_i(1'b0), .s7_data_o(), .s7_addr_o(), .s7_sel_o(), .s7_we_o(), .s7_cyc_o(),
// .s7_stb_o(), .s7_ack_i(1'b0), .s7_err_i(1'b0), .s7_rty_i(1'b0),
// slave 8 - unused
// .s8_data_i(1'b0), .s8_data_o(), .s8_addr_o(), .s8_sel_o(), .s8_we_o(), .s8_cyc_o(),
// .s8_stb_o(), .s8_ack_i(1'b0), .s8_err_i(1'b0), .s8_rty_i(1'b0),
// slave 9 - unused
// .s9_data_i(1'b0), .s9_data_o(), .s9_addr_o(), .s9_sel_o(), .s9_we_o(), .s9_cyc_o(),
// .s9_stb_o(), .s9_ack_i(1'b0), .s9_err_i(1'b0), .s9_rty_i(1'b0),
// slave 10 - unused
// .s10_data_i(1'b0), .s10_data_o(), .s10_addr_o(), .s10_sel_o(), .s10_we_o(), .s10_cyc_o(),
// .s10_stb_o(), .s10_ack_i(1'b0), .s10_err_i(1'b0), .s10_rty_i(1'b0),
// slave 11 - unused
// .s11_data_i(1'b0), .s11_data_o(), .s11_addr_o(), .s11_sel_o(), .s11_we_o(), .s11_cyc_o(),
// .s11_stb_o(), .s11_ack_i(1'b0), .s11_err_i(1'b0), .s11_rty_i(1'b0),
// slave 12 - unused
// .s12_data_i(1'b0), .s12_data_o(), .s12_addr_o(), .s12_sel_o(), .s12_we_o(), .s12_cyc_o(),
// .s12_stb_o(), .s12_ack_i(1'b0), .s12_err_i(1'b0), .s12_rty_i(1'b0),
// slave 13 - unused
// .s13_data_i(1'b0), .s13_data_o(), .s13_addr_o(), .s13_sel_o(), .s13_we_o(), .s13_cyc_o(),
// .s13_stb_o(), .s13_ack_i(1'b0), .s13_err_i(1'b0), .s13_rty_i(1'b0),
// slave 14 - unused
// .s14_data_i(1'b0), .s14_data_o(), .s14_addr_o(), .s14_sel_o(), .s14_we_o(), .s14_cyc_o(),
// .s14_stb_o(), .s14_ack_i(1'b0), .s14_err_i(1'b0), .s14_rty_i(1'b0),
// slave 15 - unused
// .s15_data_i(1'b0), .s15_data_o(), .s15_addr_o(), .s15_sel_o(), .s15_we_o(), .s15_cyc_o(),
// .s15_stb_o(), .s15_ack_i(1'b0), .s15_err_i(1'b0), .s15_rty_i(1'b0)
);
// USB 2.0 core - wishbone slave 0
usbf_top usbEngine0 (
.wb_clk(wbClk), .clk_i(usbClk), .rst_i(reset_reg), .wb_addr_i(s0_addr_o), .wb_data_i(s0_data_o), .wb_data_o(s0_data_i),
.wb_ack_o(s0_ack_i), .wb_we_i(s0_we_o), .wb_stb_i(s0_stb_o), .wb_cyc_i(s0_cyc_o),
.inta_o(s0_rty_i), .dma_ack_i(s0_sel_o), .susp_o(s0_err_i), .resume_req_i(s0_rty_i),
// UTMI Interface
.phy_clk_pad_i(phyClk0), .phy_rst_pad_o(phy_rst_pad_0_o_temp),
.DataOut_pad_o(DataOut_pad_0_o), .TxValid_pad_o(TxValid_pad_0_o), .TxReady_pad_i(TxReady_pad_0_i),
.RxValid_pad_i(RxValid_pad_0_i), .RxActive_pad_i(RxActive_pad_0_i), .RxError_pad_i(RxError_pad_0_i),
.DataIn_pad_i(DataIn_pad_0_i), .XcvSelect_pad_o(XcvSelect_pad_0_o), .TermSel_pad_o(TermSel_pad_0_o),
.SuspendM_pad_o(SuspendM_pad_0_o_temp), .LineState_pad_i(LineState_pad_0_i),
.OpMode_pad_o(OpMode_pad_0_o_temp), .usb_vbus_pad_i(usb_vbus_pad_0_i),
.VControl_Load_pad_o(VControl_Load_pad_0_o), .VControl_pad_o(VControl_pad_0_o_temp), .VStatus_pad_i(VStatus_pad_0_i)
);
// USB 2.0 core - wishbone slave 1
usbf_top usbEngine1 (
.wb_clk(wbClk), .clk_i(usbClk), .rst_i(reset_reg), .wb_addr_i(s1_addr_o), .wb_data_i(s1_data_o), .wb_data_o(s1_data_i),
.wb_ack_o(s1_ack_i), .wb_we_i(s1_we_o), .wb_stb_i(s1_stb_o), .wb_cyc_i(s1_cyc_o),
.inta_o(s1_rty_i), .dma_ack_i(s1_sel_o), .susp_o(s1_err_i), .resume_req_i(s1_rty_i),
// UTMI Interface
.phy_clk_pad_i(phyClk1), .phy_rst_pad_o(phy_rst_pad_1_o_temp),
.DataOut_pad_o(DataOut_pad_1_o), .TxValid_pad_o(TxValid_pad_1_o), .TxReady_pad_i(TxReady_pad_1_i),
.RxValid_pad_i(RxValid_pad_1_i), .RxActive_pad_i(RxActive_pad_1_i), .RxError_pad_i(RxError_pad_1_i),
.DataIn_pad_i(DataIn_pad_1_i), .XcvSelect_pad_o(XcvSelect_pad_1_o), .TermSel_pad_o(TermSel_pad_1_o),
.SuspendM_pad_o(SuspendM_pad_1_o_temp), .LineState_pad_i(LineState_pad_1_i),
.OpMode_pad_o(OpMode_pad_1_o_temp), .usb_vbus_pad_i(usb_vbus_pad_1_i),
.VControl_Load_pad_o(VControl_Load_pad_1_o), .VControl_pad_o(VControl_pad_1_o_temp), .VStatus_pad_i(VStatus_pad_1_i)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_4_V
`define SKY130_FD_SC_MS__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_4_V
|
/*************************************************************************
* *
* Copyright (C) 2016,2017 Alves, Fredy. *
* All rights reserved. Email: [email protected] *
* *
* This design is free software; you can redistribute it and/or *
* modify it under the terms of EITHER: *
* (1) The GNU Lesser General Public License as published by the Free *
* Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. The text of the GNU Lesser *
* General Public License is included with this design in the *
* file LICENSE. *
* *
* This design is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the files *
* LICENSE.TXT and LICENSE-BSD.TXT for more details. *
* *
*************************************************************************/
//`define DEBUG 2
//`define DEBUGOUT 3
//`define DEBUGIN 4
module afu_user #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512)
(
input clk,
input reset_n,
// Read Request
output [ADDR_LMT-1:0] rd_req_addr,
output [MDATA-1:0] rd_req_mdata,
output rd_req_en,
input rd_req_almostfull,
// Read Response
input rd_rsp_valid,
input [MDATA-1:0] rd_rsp_mdata,
input [CACHE_WIDTH-1:0] rd_rsp_data,
// Write Request
output [ADDR_LMT-1:0] wr_req_addr,
output [MDATA-1:0] wr_req_mdata,
output [CACHE_WIDTH-1:0] wr_req_data,
output reg wr_req_en,
input wr_req_almostfull,
// Write Response
input wr_rsp0_valid,
input [MDATA-1:0] wr_rsp0_mdata,
input wr_rsp1_valid,
input [MDATA-1:0] wr_rsp1_mdata,
// Start input signal
input start,
// Done output signal
output reg done,
// Control info from software
input [511:0] afu_context
);
reg execcounter_clr;
reg data_buf_we;
wire [CACHE_WIDTH-1:0] floatsReg;
reg [2:0] counter_aux = 0;
// --- Address counter
reg addr_cnt_inc;
reg addr_cnt_clr;
reg addr_cnt_start;
reg [31:0] addr_cnt;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt <= 0;
else
if(addr_cnt_inc)
addr_cnt <= addr_cnt + 1;
else if(addr_cnt_clr)
addr_cnt <= 'd0;
else if (addr_cnt_start)
addr_cnt <= 'd1;
end
// --- Address counter continuous
reg addr_cnt_continuous_inc;
reg addr_cnt_continuous_clr;
reg [31:0] addr_cnt_continuous;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt_continuous <= 0;
else
if(addr_cnt_continuous_inc)
addr_cnt_continuous <= addr_cnt_continuous + 1;
else if(addr_cnt_continuous_clr)
addr_cnt_continuous <= 'd0;
end
assign wr_req_mdata = addr_cnt;
// --- Address counter out
reg addr_cnt_out_inc;
reg addr_cnt_out_sub;
reg addr_cnt_out_clr;
reg [31:0] addr_cnt_out;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt_out <= 0;
else
if(addr_cnt_out_inc)
addr_cnt_out <= addr_cnt_out + 1;
else if(addr_cnt_out_clr)
addr_cnt_out <= 'd0;
else if(addr_cnt_out_sub)
addr_cnt_out <= addr_cnt_out - 1;
end
// --- Address counter out
reg addr_cnt_out_ram_inc;
reg addr_cnt_out_ram_sub;
reg addr_cnt_out_ram_clr;
reg [31:0] addr_cnt_out_ram;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt_out_ram <= 0;
else
if(addr_cnt_out_ram_inc)
addr_cnt_out_ram <= addr_cnt_out_ram + 1;
else if(addr_cnt_out_ram_clr)
addr_cnt_out_ram <= 'd0;
else if(addr_cnt_out_ram_sub)
addr_cnt_out_ram <= addr_cnt_out_ram - 1;
end
// --- Rd and Wr Addr
assign wr_req_addr = addr_cnt_out;
// --- Data buffer (keep read data here)
reg [CACHE_WIDTH-1:0] data_buf;
always @ (posedge clk) begin
if(!reset_n) data_buf <= 0;
else
if(data_buf_we)
data_buf <= rd_rsp_data;
end
// --- Num cache lines to copy (from AFU context)
wire [31:0] num_clines;
assign num_clines = 32'd2;
// --- Num cache lines to copy (from AFU context)
wire [31:0] num_outlines;
assign num_outlines = 32'd1;
/* Sudoku stuff */
localparam DIM_S = 3;
localparam DIM = (DIM_S*DIM_S);
localparam DIM_Q = (DIM*DIM);
reg [(96*DIM)-1:0] r_game;
wire [(16*DIM)-1:0] w_cacheline_cells;
wire [(DIM*DIM_Q)-1:0] w_outGrid, w_outGrid2, w_outGrid3,w_outGrid4,w_outGrid5,w_outGrid6,w_outGrid7,w_outGrid8 ;
reg t_start;
wire w_done_aux1, w_done_aux2, w_done_aux3, w_done_aux4, w_done_aux5, w_done_aux6, w_done_aux7, w_done_aux8, w_done_aux9, w_done_aux10, w_done_aux11, w_done_aux12, w_done_aux13, w_done_aux14, w_done_aux15, w_done_aux16;
assign w_done = w_done_aux1 && w_done_aux2 && w_done_aux3 && w_done_aux4 && w_done_aux5 && w_done_aux6 && w_done_aux7 && w_done_aux8 && w_done_aux9 && w_done_aux10 && w_done_aux11 && w_done_aux12 && w_done_aux13 && w_done_aux14 && w_done_aux15 && w_done_aux16;
assign wr_req_data = (addr_cnt==0)?w_outGrid:(addr_cnt==1)?w_outGrid2:(addr_cnt==2)?w_outGrid3:(addr_cnt==3)?w_outGrid4:(addr_cnt==4)?w_outGrid5:(addr_cnt==5)?w_outGrid6:(addr_cnt==6)?w_outGrid7:(addr_cnt==7)?w_outGrid8:512'b01000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100;
reg mem_we;
wire [511:0] wmem_out;
wire start_fsm;
inputs_mem2 mem_inputs (
.clk(clk),
.reset_n(reset_n),
.rd_req_addr(rd_req_addr),
.rd_req_mdata(rd_req_mdata),
.rd_req_en(rd_req_en),
.rd_req_almostfull(rd_req_almostfull),
.rd_rsp_valid(rd_rsp_valid),
.rd_rsp_mdata(rd_rsp_mdata),
.rd_rsp_data(rd_rsp_data),
.mem_out(floatsReg),
.addr_mem_out(addr_cnt_continuous),
.done(start_fsm)
);
wire [511:0] out_Mem1;
wire [511:0] out_Mem2;
wire [511:0] out_Mem3;
wire [511:0] out_Mem4;
wire [511:0] out_Mem5;
wire [511:0] out_Mem6;
wire [511:0] out_Mem7;
wire [511:0] out_Mem8;
wire [511:0] out_Mem9;
wire [511:0] out_Mem10;
wire [511:0] out_Mem11;
wire [511:0] out_Mem12;
wire [511:0] out_Mem13;
wire [511:0] out_Mem14;
wire [511:0] out_Mem15;
wire [511:0] out_Mem16;
wire [511:0] out_Mem17;
wire [511:0] out_Mem18;
wire [511:0] out_Mem19;
wire [511:0] out_Mem20;
wire [511:0] out_Mem21;
wire [511:0] out_Mem22;
wire [511:0] out_Mem23;
wire [511:0] out_Mem24;
wire [511:0] out_Mem25;
wire [511:0] out_Mem26;
wire [511:0] out_Mem27;
wire [511:0] out_Mem28;
wire [511:0] out_Mem29;
wire [511:0] out_Mem30;
wire [511:0] out_Mem31;
wire [511:0] out_Mem32;
ram_rw_512x128_700 rammem1 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[15:0]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem1));
ram_rw_512x128_700 rammem2 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[31:16]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem2));
ram_rw_512x128_700 rammem3 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[47:32]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem3));
ram_rw_512x128_700 rammem4 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[63:48]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem4));
ram_rw_512x128_700 rammem5 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[79:64]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem5));
ram_rw_512x128_700 rammem6 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[95:80]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem6));
ram_rw_512x128_700 rammem7 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[111:96]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem7));
ram_rw_512x128_700 rammem8 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[127:112]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem8));
ram_rw_512x128_700 rammem9 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[143:128]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem9));
ram_rw_512x128_700 rammem10 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[159:144]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem10));
ram_rw_512x128_700 rammem11 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[175:160]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem11));
ram_rw_512x128_700 rammem12 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[191:176]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem12));
ram_rw_512x128_700 rammem13 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[207:192]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem13));
ram_rw_512x128_700 rammem14 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[223:208]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem14));
ram_rw_512x128_700 rammem15 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[239:224]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem15));
ram_rw_512x128_700 rammem16 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[255:240]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem16));
ram_rw_512x128_700 rammem17 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[271:256]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem17));
ram_rw_512x128_700 rammem18 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[287:272]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem18));
ram_rw_512x128_700 rammem19 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[303:288]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem19));
ram_rw_512x128_700 rammem20 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[319:304]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem20));
ram_rw_512x128_700 rammem21 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[335:320]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem21));
ram_rw_512x128_700 rammem22 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[351:336]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem22));
ram_rw_512x128_700 rammem23 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[367:352]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem23));
ram_rw_512x128_700 rammem24 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[383:368]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem24));
ram_rw_512x128_700 rammem25 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[399:384]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem25));
ram_rw_512x128_700 rammem26 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[415:400]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem26));
ram_rw_512x128_700 rammem27 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[431:416]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem27));
ram_rw_512x128_700 rammem28 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[447:432]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem28));
ram_rw_512x128_700 rammem29 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[463:448]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem29));
ram_rw_512x128_700 rammem30 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[479:464]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem30));
ram_rw_512x128_700 rammem31 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[495:480]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem31));
ram_rw_512x128_700 rammem32 (
.clock(clk),
.data(floatsReg),
.rdaddress(floatsReg[511:496]),
.wraddress(addr_cnt_continuous),
.wren(mem_we),
.q(out_Mem32));
wire [31:0] IDLE_AUX1, IDLE_AUX2, IDLE_AUX3, IDLE_AUX4, IDLE_AUX5, IDLE_AUX6, IDLE_AUX7, IDLE_AUX8, IDLE_AUX9, IDLE_AUX10, IDLE_AUX11, IDLE_AUX12,IDLE_AUX13,IDLE_AUX14,IDLE_AUX15,IDLE_AUX16;
reg [31:0] r_cnt,n_cnt,l_cnt,l_cnt2,l_cnt3;
assign w_outGrid[255:224] = 32'b00111111110110011001100110011010; //1.7
assign w_outGrid[511:480] = l_cnt;
assign w_outGrid2[255:224] = 32'b01000000001011001100110011001101; //2.7
assign w_outGrid2[511:480] = l_cnt2;
assign w_outGrid3[255:224] = 32'b01000000011011001100110011001101; //3.7
assign w_outGrid3[511:480] = l_cnt3;
assign w_outGrid4[255:224] = 32'b01000000100101100110011001100110; //4.7
assign w_outGrid4[511:480] = addr_cnt_continuous;
assign w_outGrid5[255:224] = 32'b01000000101101100110011001100110; //5.7
assign w_outGrid5[511:480] = floatsReg[495:480];
assign w_outGrid6[255:224] = 32'b01000000110101100110011001100110; //6.7
assign w_outGrid6[511:480] = out_Mem31[31:0];
assign w_outGrid7[255:224] = 32'b01000000111101100110011001100110; //7.7
assign w_outGrid7[511:480] = floatsReg[511:496];
assign w_outGrid8[255:224] = 32'b01000001000010110011001100110011; //8.7
assign w_outGrid8[511:480] = out_Mem32[31:0];
dCollideSpheres collisionHandler1 (
.x1(out_Mem1[31:0]),
.y1(out_Mem1[63:32]),
.z1(out_Mem1[95:64]),
.r1(out_Mem1[127:96]),
.x2(out_Mem2[31:0]),
.y2(out_Mem2[63:32]),
.z2(out_Mem2[95:64]),
.r2(out_Mem2[127:96]),
.cx(w_outGrid[31:0]),
.cy(w_outGrid[63:32]),
.cz(w_outGrid[95:64]),
.normalx(w_outGrid[127:96]),
.normaly(w_outGrid[159:128]),
.normalz(w_outGrid[191:160]),
.depth(w_outGrid[223:192]),
.ret(IDLE_AUX1),
.done(w_done_aux1),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler2 (
.x1(out_Mem3[31:0]),
.y1(out_Mem3[63:32]),
.z1(out_Mem3[95:64]),
.r1(out_Mem3[127:96]),
.x2(out_Mem4[31:0]),
.y2(out_Mem4[63:32]),
.z2(out_Mem4[95:64]),
.r2(out_Mem4[127:96]),
.cx(w_outGrid[287:256]),
.cy(w_outGrid[319:288]),
.cz(w_outGrid[351:320]),
.normalx(w_outGrid[383:352]),
.normaly(w_outGrid[415:384]),
.normalz(w_outGrid[447:416]),
.depth(w_outGrid[479:448]),
.ret(IDLE_AUX2),
.done(w_done_aux2),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler3 (
.x1(out_Mem5[31:0]),
.y1(out_Mem5[63:32]),
.z1(out_Mem5[95:64]),
.r1(out_Mem5[127:96]),
.x2(out_Mem6[31:0]),
.y2(out_Mem6[63:32]),
.z2(out_Mem6[95:64]),
.r2(out_Mem6[127:96]),
.cx(w_outGrid2[31:0]),
.cy(w_outGrid2[63:32]),
.cz(w_outGrid2[95:64]),
.normalx(w_outGrid2[127:96]),
.normaly(w_outGrid2[159:128]),
.normalz(w_outGrid2[191:160]),
.depth(w_outGrid2[223:192]),
.ret(IDLE_AUX3),
.done(w_done_aux3),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler4 (
.x1(out_Mem7[31:0]),
.y1(out_Mem7[63:32]),
.z1(out_Mem7[95:64]),
.r1(out_Mem7[127:96]),
.x2(out_Mem8[31:0]),
.y2(out_Mem8[63:32]),
.z2(out_Mem8[95:64]),
.r2(out_Mem8[127:96]),
.cx(w_outGrid2[287:256]),
.cy(w_outGrid2[319:288]),
.cz(w_outGrid2[351:320]),
.normalx(w_outGrid2[383:352]),
.normaly(w_outGrid2[415:384]),
.normalz(w_outGrid2[447:416]),
.depth(w_outGrid2[479:448]),
.ret(IDLE_AUX4),
.done(w_done_aux4),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler5 (
.x1(out_Mem9[31:0]),
.y1(out_Mem9[63:32]),
.z1(out_Mem9[95:64]),
.r1(out_Mem9[127:96]),
.x2(out_Mem10[31:0]),
.y2(out_Mem10[63:32]),
.z2(out_Mem10[95:64]),
.r2(out_Mem10[127:96]),
.cx(w_outGrid3[31:0]),
.cy(w_outGrid3[63:32]),
.cz(w_outGrid3[95:64]),
.normalx(w_outGrid3[127:96]),
.normaly(w_outGrid3[159:128]),
.normalz(w_outGrid3[191:160]),
.depth(w_outGrid3[223:192]),
.ret(IDLE_AUX5),
.done(w_done_aux5),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler6 (
.x1(out_Mem11[31:0]),
.y1(out_Mem11[63:32]),
.z1(out_Mem11[95:64]),
.r1(out_Mem11[127:96]),
.x2(out_Mem12[31:0]),
.y2(out_Mem12[63:32]),
.z2(out_Mem12[95:64]),
.r2(out_Mem12[127:96]),
.cx(w_outGrid3[287:256]),
.cy(w_outGrid3[319:288]),
.cz(w_outGrid3[351:320]),
.normalx(w_outGrid3[383:352]),
.normaly(w_outGrid3[415:384]),
.normalz(w_outGrid3[447:416]),
.depth(w_outGrid3[479:448]),
.ret(IDLE_AUX6),
.done(w_done_aux6),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler7 (
.x1(out_Mem13[31:0]),
.y1(out_Mem13[63:32]),
.z1(out_Mem13[95:64]),
.r1(out_Mem13[127:96]),
.x2(out_Mem14[31:0]),
.y2(out_Mem14[63:32]),
.z2(out_Mem14[95:64]),
.r2(out_Mem14[127:96]),
.cx(w_outGrid4[31:0]),
.cy(w_outGrid4[63:32]),
.cz(w_outGrid4[95:64]),
.normalx(w_outGrid4[127:96]),
.normaly(w_outGrid4[159:128]),
.normalz(w_outGrid4[191:160]),
.depth(w_outGrid4[223:192]),
.ret(IDLE_AUX7),
.done(w_done_aux7),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler8 (
.x1(out_Mem15[31:0]),
.y1(out_Mem15[63:32]),
.z1(out_Mem15[95:64]),
.r1(out_Mem15[127:96]),
.x2(out_Mem16[31:0]),
.y2(out_Mem16[63:32]),
.z2(out_Mem16[95:64]),
.r2(out_Mem16[127:96]),
.cx(w_outGrid4[287:256]),
.cy(w_outGrid4[319:288]),
.cz(w_outGrid4[351:320]),
.normalx(w_outGrid4[383:352]),
.normaly(w_outGrid4[415:384]),
.normalz(w_outGrid4[447:416]),
.depth(w_outGrid4[479:448]),
.ret(IDLE_AUX8),
.done(w_done_aux8),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler9 (
.x1(out_Mem17[31:0]),
.y1(out_Mem17[63:32]),
.z1(out_Mem17[95:64]),
.r1(out_Mem17[127:96]),
.x2(out_Mem18[31:0]),
.y2(out_Mem18[63:32]),
.z2(out_Mem18[95:64]),
.r2(out_Mem18[127:96]),
.cx(w_outGrid5[31:0]),
.cy(w_outGrid5[63:32]),
.cz(w_outGrid5[95:64]),
.normalx(w_outGrid5[127:96]),
.normaly(w_outGrid5[159:128]),
.normalz(w_outGrid5[191:160]),
.depth(w_outGrid5[223:192]),
.ret(IDLE_AUX9),
.done(w_done_aux9),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler10 (
.x1(out_Mem19[31:0]),
.y1(out_Mem19[63:32]),
.z1(out_Mem19[95:64]),
.r1(out_Mem19[127:96]),
.x2(out_Mem20[31:0]),
.y2(out_Mem20[63:32]),
.z2(out_Mem20[95:64]),
.r2(out_Mem20[127:96]),
.cx(w_outGrid5[287:256]),
.cy(w_outGrid5[319:288]),
.cz(w_outGrid5[351:320]),
.normalx(w_outGrid5[383:352]),
.normaly(w_outGrid5[415:384]),
.normalz(w_outGrid5[447:416]),
.depth(w_outGrid5[479:448]),
.ret(IDLE_AUX10),
.done(w_done_aux10),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler11 (
.x1(out_Mem21[31:0]),
.y1(out_Mem21[63:32]),
.z1(out_Mem21[95:64]),
.r1(out_Mem21[127:96]),
.x2(out_Mem22[31:0]),
.y2(out_Mem22[63:32]),
.z2(out_Mem22[95:64]),
.r2(out_Mem22[127:96]),
.cx(w_outGrid6[31:0]),
.cy(w_outGrid6[63:32]),
.cz(w_outGrid6[95:64]),
.normalx(w_outGrid6[127:96]),
.normaly(w_outGrid6[159:128]),
.normalz(w_outGrid6[191:160]),
.depth(w_outGrid6[223:192]),
.ret(IDLE_AUX11),
.done(w_done_aux11),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler12 (
.x1(out_Mem23[31:0]),
.y1(out_Mem23[63:32]),
.z1(out_Mem23[95:64]),
.r1(out_Mem23[127:96]),
.x2(out_Mem24[31:0]),
.y2(out_Mem24[63:32]),
.z2(out_Mem24[95:64]),
.r2(out_Mem24[127:96]),
.cx(w_outGrid6[287:256]),
.cy(w_outGrid6[319:288]),
.cz(w_outGrid6[351:320]),
.normalx(w_outGrid6[383:352]),
.normaly(w_outGrid6[415:384]),
.normalz(w_outGrid6[447:416]),
.depth(w_outGrid6[479:448]),
.ret(IDLE_AUX12),
.done(w_done_aux12),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler13 (
.x1(out_Mem25[31:0]),
.y1(out_Mem25[63:32]),
.z1(out_Mem25[95:64]),
.r1(out_Mem25[127:96]),
.x2(out_Mem26[31:0]),
.y2(out_Mem26[63:32]),
.z2(out_Mem26[95:64]),
.r2(out_Mem26[127:96]),
.cx(w_outGrid7[31:0]),
.cy(w_outGrid7[63:32]),
.cz(w_outGrid7[95:64]),
.normalx(w_outGrid7[127:96]),
.normaly(w_outGrid7[159:128]),
.normalz(w_outGrid7[191:160]),
.depth(w_outGrid7[223:192]),
.ret(IDLE_AUX13),
.done(w_done_aux13),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler14 (
.x1(out_Mem27[31:0]),
.y1(out_Mem27[63:32]),
.z1(out_Mem27[95:64]),
.r1(out_Mem27[127:96]),
.x2(out_Mem28[31:0]),
.y2(out_Mem28[63:32]),
.z2(out_Mem28[95:64]),
.r2(out_Mem28[127:96]),
.cx(w_outGrid7[287:256]),
.cy(w_outGrid7[319:288]),
.cz(w_outGrid7[351:320]),
.normalx(w_outGrid7[383:352]),
.normaly(w_outGrid7[415:384]),
.normalz(w_outGrid7[447:416]),
.depth(w_outGrid7[479:448]),
.ret(IDLE_AUX14),
.done(w_done_aux14),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler15 (
.x1(out_Mem29[31:0]),
.y1(out_Mem29[63:32]),
.z1(out_Mem29[95:64]),
.r1(out_Mem29[127:96]),
.x2(out_Mem30[31:0]),
.y2(out_Mem30[63:32]),
.z2(out_Mem30[95:64]),
.r2(out_Mem30[127:96]),
.cx(w_outGrid8[31:0]),
.cy(w_outGrid8[63:32]),
.cz(w_outGrid8[95:64]),
.normalx(w_outGrid8[127:96]),
.normaly(w_outGrid8[159:128]),
.normalz(w_outGrid8[191:160]),
.depth(w_outGrid8[223:192]),
.ret(IDLE_AUX15),
.done(w_done_aux15),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
dCollideSpheres collisionHandler16 (
.x1(out_Mem31[31:0]),
.y1(out_Mem31[63:32]),
.z1(out_Mem31[95:64]),
.r1(out_Mem31[127:96]),
.x2(out_Mem32[31:0]),
.y2(out_Mem32[63:32]),
.z2(out_Mem32[95:64]),
.r2(out_Mem32[127:96]),
.cx(w_outGrid8[287:256]),
.cy(w_outGrid8[319:288]),
.cz(w_outGrid8[351:320]),
.normalx(w_outGrid8[383:352]),
.normaly(w_outGrid8[415:384]),
.normalz(w_outGrid8[447:416]),
.depth(w_outGrid8[479:448]),
.ret(IDLE_AUX16),
.done(w_done_aux16),
.g1(32'd1),
.g2(32'd1),
.clk(clk),
.rst(!t_start)
);
localparam [4:0]
FSM_IDLE = 4'd0,
FSM_RD_REQ = 4'd1,
FSM_RD_RSP = 4'd2,
FSM_WR_REQ = 4'd3,
FSM_RUN_COLLISIONS = 4'd4,
FSM_WAIT_COLLISIONS = 4'd5,
FSM_WR_RSP = 4'd6,
FSM_RD_REQ2 = 4'd7,
FSM_RD_RSP2 = 4'd8,
ENDSTATE = 4'd9,
FSM_RD_REQ3 = 4'd10,
FSM_RD_RSP3 = 4'd11,
FSM_AUX1 = 4'd12,
DONESTATE = 4'd13;
reg [4:0] fsm_cs, fsm_ns;
always @ (posedge clk)
begin
if(!reset_n) fsm_cs <= FSM_IDLE;
else fsm_cs <= fsm_ns;
end
always@(posedge clk) r_cnt <= (!reset_n) ? 'd0 : n_cnt;
always @ *
begin
fsm_ns = fsm_cs;
addr_cnt_inc = 1'b0;
addr_cnt_clr = 1'b0;
addr_cnt_start = 1'b0;
addr_cnt_continuous_inc = 1'b0;
addr_cnt_continuous_clr = 1'b0;
addr_cnt_out_inc = 1'b0;
addr_cnt_out_sub = 1'b0;
addr_cnt_out_clr = 1'b0;
data_buf_we = 1'b0;
wr_req_en = 1'b0;
done = 1'b0;
t_start = 1'b0;
n_cnt = r_cnt;
addr_cnt_out_ram_inc = 1'b0;
addr_cnt_out_ram_sub = 1'b0;
addr_cnt_out_ram_clr = 1'b0;
mem_we = 1'b0;
case(fsm_cs)
FSM_IDLE:
begin
fsm_ns = FSM_RD_REQ;
n_cnt = 'd0;
l_cnt = 'd0;
l_cnt2 = 'd0;
l_cnt3 = 'd0;
end
FSM_RD_REQ:
begin
// If there's no more data to copy
if(start_fsm)
begin
fsm_ns = FSM_RD_REQ2;
addr_cnt_start = 1'b1;
l_cnt <= floatsReg[95:64];
l_cnt2 <= floatsReg[127:96];
l_cnt3 <= floatsReg[159:128];
$display("wwwb l_cnt_afu: %d", l_cnt);
$display("wwwb l_cnt2_afu: %d", l_cnt2);
addr_cnt_continuous_inc = 1'b1;
end
end
FSM_RD_REQ2:
begin
if(addr_cnt_continuous > l_cnt)
begin
fsm_ns = FSM_RD_REQ3;
addr_cnt_clr = 1'b1;
end
else
begin
fsm_ns = FSM_RD_RSP2;
end
end
FSM_RD_RSP2:
begin
mem_we = 1'b1;
addr_cnt_inc = 1'b1;
addr_cnt_continuous_inc = 1'b1;
fsm_ns = FSM_RD_REQ2;
end
FSM_RD_REQ3:
begin
if(addr_cnt >= 1)
begin
fsm_ns = FSM_RUN_COLLISIONS;
addr_cnt_clr = 1'b1;
end
else
begin
fsm_ns = FSM_RD_RSP3;
end
end
FSM_RD_RSP3:
begin
addr_cnt_inc = 1'b1;
addr_cnt_continuous_inc = 1'b1;
fsm_ns = FSM_RD_REQ3;
end
FSM_RUN_COLLISIONS:
begin
$display("wwwa These are the mem addresses %b",floatsReg);
$display("wwwa This is the address continuous %d",addr_cnt_continuous);
t_start = 1'b1;
fsm_ns = FSM_WAIT_COLLISIONS;
end
FSM_WAIT_COLLISIONS:
begin
if(w_done)
begin
fsm_ns = FSM_WR_REQ;
addr_cnt_clr = 1'b1;
end
end
FSM_WR_REQ:
begin
if(addr_cnt >= 8)
begin
fsm_ns = DONESTATE;
addr_cnt_clr = 1'b1;
end
else if(!wr_req_almostfull)
begin
wr_req_en = 1'b1; // issue wr_req
fsm_ns = FSM_WR_RSP;
//$display("\n\n\n\n\noutinfo wout 1: %d", floatsReg[31:0]);
//$display("outinfo wout 2: %d", floatsReg[63:32]);
//$display("outinfo address out: %d", addr_cnt_out);
//$display("outData1: %b", w_outGrid);
//$display("outData2: %b", w_outGrid2);
end
end
FSM_WR_RSP:
begin
addr_cnt_out_inc = 1'b1;
fsm_ns = FSM_WR_REQ;
addr_cnt_inc = 1'b1;
end
DONESTATE:
begin
if(addr_cnt_continuous >= l_cnt2)
begin
fsm_ns = ENDSTATE;
addr_cnt_clr = 1'b1;
addr_cnt_continuous_clr = 1'b1;
addr_cnt_out_ram_clr = 1'b1;
end else
begin
addr_cnt_clr = 1'b1;
fsm_ns = FSM_RD_REQ3;
end
end
ENDSTATE:
begin
done = 1'b1;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_12_V
`define SKY130_FD_SC_HD__DECAP_12_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_12 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_12_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 09:37:07 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input srst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "0" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(srst),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din[35:0]),
.dout(dout[35:0]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din[63:36]),
.dout(dout[63:36]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({dout[34:27],dout[25:18],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({dout[35],dout[26],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,dout[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,dout[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,dout[6:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_fb_i_reg,
v1_reg,
wr_en,
comp1,
out,
rd_en,
ram_empty_fb_i_reg);
output ram_full_fb_i_reg;
input [4:0]v1_reg;
input wr_en;
input comp1;
input out;
input rd_en;
input ram_empty_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire out;
wire ram_empty_fb_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT6 #(
.INIT(64'hFFC0FFC05500FFC0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(out),
.I4(rd_en),
.I5(ram_empty_fb_i_reg),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_18 ;
wire \gntv_or_sync_fifo.gl0.wr_n_19 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_20 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire [4:0]\grss.rsts/c2/v1_reg ;
wire [9:0]p_0_out;
wire [9:0]p_11_out;
wire p_2_out;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire srst;
wire tmp_ram_rd_en;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out),
.Q(rd_pntr_plus1),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_18 ),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_19 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_20 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.Q(p_11_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[9] (p_0_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_18 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_19 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_20 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.rd_en(rd_en),
.srst(srst),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_11_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
WEA,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input srst;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
srst,
E,
clk);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input srst;
input [0:0]E;
input clk;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire clk;
wire \gc0.count[9]_i_2_n_0 ;
wire [9:0]plusOp;
wire srst;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.Q(Q[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp[8]),
.Q(Q[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(E),
.D(plusOp[9]),
.Q(Q[9]),
.R(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
Q,
tmp_ram_rd_en,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
srst,
clk,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [9:0]Q;
output tmp_ram_rd_en;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input srst;
input clk;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [9:0]Q;
wire clk;
wire empty;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire \grss.rsts_n_2 ;
wire out;
wire ram_full_fb_i_reg;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.E(\grss.rsts_n_2 ),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\grss.rsts_n_2 ),
.Q(Q),
.clk(clk),
.srst(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
E,
tmp_ram_rd_en,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
srst,
clk,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
output tmp_ram_rd_en;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input srst;
input clk;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]E;
wire c1_n_0;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(srst),
.I1(ram_empty_fb_i),
.I2(rd_en),
.O(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 c1
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 c2
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDSE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.Q(ram_empty_fb_i),
.S(srst));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDSE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.Q(ram_empty_i),
.S(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(v1_reg_0,
Q,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
srst,
E,
clk);
output [4:0]v1_reg_0;
output [9:0]Q;
output [4:0]v1_reg;
output [4:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input srst;
input [0:0]E;
input clk;
wire [0:0]E;
wire [9:0]Q;
wire clk;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count[9]_i_2_n_0 ;
wire [9:0]p_12_out;
wire [9:0]plusOp__0;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire srst;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(p_12_out[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.I2(p_12_out[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(p_12_out[1]),
.I1(p_12_out[0]),
.I2(p_12_out[2]),
.I3(p_12_out[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(p_12_out[2]),
.I1(p_12_out[0]),
.I2(p_12_out[1]),
.I3(p_12_out[3]),
.I4(p_12_out[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(p_12_out[3]),
.I1(p_12_out[1]),
.I2(p_12_out[0]),
.I3(p_12_out[2]),
.I4(p_12_out[4]),
.I5(p_12_out[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[9]_i_2_n_0 ),
.I1(p_12_out[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[7]_i_1
(.I0(\gcc0.gc0.count[9]_i_2_n_0 ),
.I1(p_12_out[6]),
.I2(p_12_out[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[8]_i_1
(.I0(p_12_out[6]),
.I1(\gcc0.gc0.count[9]_i_2_n_0 ),
.I2(p_12_out[7]),
.I3(p_12_out[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[9]_i_1
(.I0(p_12_out[7]),
.I1(\gcc0.gc0.count[9]_i_2_n_0 ),
.I2(p_12_out[6]),
.I3(p_12_out[8]),
.I4(p_12_out[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gcc0.gc0.count[9]_i_2
(.I0(p_12_out[5]),
.I1(p_12_out[3]),
.I2(p_12_out[1]),
.I3(p_12_out[0]),
.I4(p_12_out[2]),
.I5(p_12_out[4]),
.O(\gcc0.gc0.count[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(p_12_out[0]),
.Q(Q[0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(p_12_out[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(p_12_out[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(p_12_out[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(p_12_out[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(p_12_out[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(p_12_out[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(p_12_out[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(p_12_out[8]),
.Q(Q[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.D(p_12_out[9]),
.Q(Q[9]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.Q(p_12_out[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp__0[1]),
.Q(p_12_out[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp__0[2]),
.Q(p_12_out[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp__0[3]),
.Q(p_12_out[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp__0[4]),
.Q(p_12_out[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp__0[5]),
.Q(p_12_out[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp__0[6]),
.Q(p_12_out[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp__0[7]),
.Q(p_12_out[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp__0[8]),
.Q(p_12_out[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(E),
.D(plusOp__0[9]),
.Q(p_12_out[9]),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(Q[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(Q[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(Q[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(Q[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(Q[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(ram_empty_i_reg_3));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
WEA,
Q,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
srst,
clk,
wr_en,
rd_en,
ram_empty_fb_i_reg,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] );
output out;
output full;
output [0:0]WEA;
output [9:0]Q;
output [4:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input srst;
input clk;
input wr_en;
input rd_en;
input ram_empty_fb_i_reg;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
wire [9:0]Q;
wire [0:0]WEA;
wire [4:0]\c0/v1_reg ;
wire [4:0]\c1/v1_reg ;
wire clk;
wire full;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire rd_en;
wire srst;
wire [4:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(WEA),
.clk(clk),
.full(full),
.out(out),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.rd_en(rd_en),
.srst(srst),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.E(WEA),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gc0.count_reg[9] (\gc0.count_reg[9] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
E,
v1_reg,
v1_reg_0,
srst,
clk,
wr_en,
rd_en,
ram_empty_fb_i_reg);
output out;
output full;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input srst;
input clk;
input wr_en;
input rd_en;
input ram_empty_fb_i_reg;
wire [0:0]E;
wire c0_n_0;
wire clk;
wire comp1;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire ram_empty_fb_i_reg;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire rd_en;
wire srst;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_full_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c0_n_0),
.Q(ram_full_fb_i),
.R(srst));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(c0_n_0),
.Q(ram_full_i),
.R(srst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//% @file sdm_adc_data_aurora_recv_tb.v
//% @brief test bench of sdm_adc_data_aurora_recv_tb.
//% @author Yuan Mei
//%
`timescale 1ns / 1ps
module sdm_adc_data_aurora_recv_tb
#(
parameter NCH_ADC = 20,
parameter ADC_CYC = 20,
parameter NCH_SDM = 19,
parameter SDM_CYC = 4
)
();
reg reset;
reg clk;
wire [511:0] dout;
wire dout_valid;
reg user_clk;
reg [63:0] axi_rx_tdata;
reg axi_rx_tvalid;
wire fifo_full;
sdm_adc_data_aurora_recv
#(
.NCH_ADC(NCH_ADC),
.ADC_CYC(ADC_CYC),
.NCH_SDM(NCH_SDM),
.SDM_CYC(SDM_CYC)
)
sdm_adc_data_aurora_recv_tb_inst
(
.RESET(reset),
.CLK(clk),
.USER_CLK(user_clk),
.M_AXI_RX_TDATA(axi_rx_tdata),
.M_AXI_RX_TVALID(axi_rx_tvalid),
.DOUT(dout),
.DOUT_VALID(dout_valid),
.FIFO_FULL(fifo_full)
);
//initial begin
//$dumpfile("fifo_over_ufc.vcd");
//$dumpvars(0, fifo_over_ufc);
//end
initial begin
clk = 0;
reset = 0;
#16 reset = 1;
#36 reset = 0;
end
always #5 clk = ~clk;
initial begin
user_clk = 0;
end
always #2.5 user_clk = ~user_clk;
reg [4:0] cnt, cnt1;
always @ (posedge user_clk or posedge reset) begin
if (reset) begin
cnt <= 4;
cnt1 <= 0;
axi_rx_tdata <= 64'h0123456789abcdef;
axi_rx_tvalid <= 0;
end
else begin
cnt1 <= cnt1 + 1;
if (axi_rx_tvalid) begin
cnt <= cnt + 1;
axi_rx_tdata <= axi_rx_tdata + 1;
axi_rx_tdata[63] <= 1'b0;
if (cnt == 8) begin
axi_rx_tdata[63] <= 1'b1;
cnt <= 0;
end
end
axi_rx_tvalid <= 1;
if (cnt1 == 0) begin
axi_rx_tvalid <= 0;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
// Title : 8-bit Client-to-LocalLink Transmitter FIFO
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : tx_client_fifo_8.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is a transmit-side LocalLink FIFO implementation for
// the example design of the Virtex-6 Embedded Tri-Mode Ethernet
// MAC Wrapper core.
//
// The transmit FIFO is created from a Block RAM of size 4096
// words of 8-bits per word.
//
// Valid frame data received from LocalLink interface is written
// into the Block RAM on the write clock. The FIFO will store
// frames upto 4kbytes in length. If larger frames are written
// to the FIFO the LocalLink interface will accept the rest of the
// frame, but that frame will be dropped by the FIFO and
// the overflow signal will be asserted.
//
// The FIFO is designed to work with a minimum frame length of 14
// bytes.
//
// When there is at least one complete frame in the FIFO,
// the MAC transmitter client interface will be driven to
// request frame transmission by placing the first byte of
// the frame onto tx_data[15:0] and by asserting
// tx_data_valid. The MAC will later respond by asserting
// tx_ack. At this point the remaining frame data is read
// out of the FIFO in a continuous burst. Data is read out
// of the FIFO on the rd_clk.
//
// The FIFO has been designed to operate with different clocks
// on the write and read sides. The write clock (LocalLink clock)
// can be an equal or faster frequency than the read clock
// (client clock). The minimum write clock frequency is the read
// clock frequency divided by 2.5.
//
// The FIFO memory size can be increased by expanding the rd_addr
// and wr_addr signal widths, to address further BRAMs.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module tx_client_fifo_8 (
// MAC Interface
rd_clk,
rd_sreset,
rd_enable,
tx_data,
tx_data_valid,
tx_ack,
tx_collision,
tx_retransmit,
overflow,
// LocalLink Interface
wr_clk,
wr_sreset,
wr_data,
wr_sof_n,
wr_eof_n,
wr_src_rdy_n,
wr_dst_rdy_n,
wr_fifo_status
);
//---------------------------------------------------------------------------
// Define interface signals
//---------------------------------------------------------------------------
// MAC Interface
input rd_clk;
input rd_sreset;
input rd_enable;
output [7:0] tx_data;
output tx_data_valid;
input tx_ack;
input tx_collision;
input tx_retransmit;
output overflow;
// LocalLink Interface
input wr_clk;
input wr_sreset;
input [7:0] wr_data;
input wr_sof_n;
input wr_eof_n;
input wr_src_rdy_n;
output wr_dst_rdy_n;
output [3:0] wr_fifo_status;
// If FULL_DUPLEX_ONLY is 1 then all the half duplex logic in the FIFO is removed.
// The default for the fifo is to include the half duplex functionality
parameter FULL_DUPLEX_ONLY = 0;
reg [7:0] tx_data;
reg tx_data_valid;
reg [3:0] wr_fifo_status;
//---------------------------------------------------------------------------
// Define internal signals
//---------------------------------------------------------------------------
wire GND;
wire VCC;
wire [31:0] GND_BUS;
// Encode rd_state_machine states
parameter IDLE_s = 4'b0000; parameter QUEUE1_s = 4'b0001;
parameter QUEUE2_s = 4'b0010; parameter QUEUE3_s = 4'b0011;
parameter QUEUE_ACK_s = 4'b0100; parameter WAIT_ACK_s = 4'b0101;
parameter FRAME_s = 4'b0110; parameter DROP_s = 4'b0111;
parameter RETRANSMIT_s = 4'b1000;
reg [3:0] rd_state;
reg [3:0] rd_nxt_state;
// Encode wr_state_machine states
parameter WAIT_s = 2'b00; parameter DATA_s = 2'b01;
parameter EOF_s = 2'b10; parameter OVFLOW_s = 2'b11;
reg [1:0] wr_state;
reg [1:0] wr_nxt_state;
reg [7:0] wr_data_bram;
reg [7:0] wr_data_pipe[0:1];
reg wr_sof_pipe[0:1];
reg wr_eof_pipe[0:1];
reg wr_accept_pipe[0:1];
reg wr_accept_bram;
reg [0:0] wr_eof_bram;
reg [11:0] wr_addr;
wire wr_addr_inc;
wire wr_start_addr_load;
wire wr_addr_reload;
reg [11:0] wr_start_addr;
reg wr_fifo_full;
wire wr_en;
reg wr_ovflow_dst_rdy;
wire wr_dst_rdy_int_n;
reg frame_in_fifo;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg frame_in_fifo_sync;
wire rd_eof_bram;
reg rd_eof;
reg rd_eof_reg;
reg [11:0] rd_addr;
wire rd_addr_inc;
wire rd_addr_reload;
wire [7:0] rd_data_bram;
reg [7:0] rd_data_pipe;
wire rd_en;
wire rd_en_bram;
wire [31:0] dob_bram;
wire [3:0] dopb_bram;
reg rd_tran_frame_tog;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg wr_tran_frame_tog;
reg wr_tran_frame_sync;
reg wr_tran_frame_delay;
reg rd_retran_frame_tog;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg wr_retran_frame_tog;
reg wr_retran_frame_sync;
reg wr_retran_frame_delay;
wire wr_store_frame;
wire wr_eof_state;
reg wr_eof_state_reg;
reg wr_transmit_frame;
reg wr_retransmit_frame;
reg [8:0] wr_frames;
reg wr_frame_in_fifo;
reg [3:0] rd_16_count;
wire rd_txfer_en;
reg [11:0] rd_addr_txfer;
reg rd_txfer_tog;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg wr_txfer_tog;
reg wr_txfer_tog_sync;
reg wr_txfer_tog_delay;
wire wr_txfer_en;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg [11:0] wr_rd_addr;
reg [11:0] wr_addr_diff;
reg rd_drop_frame;
reg rd_retransmit;
reg [11:0] rd_start_addr;
wire rd_start_addr_load;
wire rd_start_addr_reload;
reg [11:0] rd_dec_addr;
wire rd_transmit_frame;
wire rd_retransmit_frame;
reg rd_col_window_expire;
reg rd_col_window_pipe[0:1];
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg wr_col_window_pipe[0:1];
wire wr_fifo_overflow;
reg [9:0] rd_slot_timer;
reg wr_col_window_expire;
wire rd_idle_state;
reg rd_enable_delay;
reg rd_enable_delay2;
assign GND = 1'b0;
assign VCC = 1'b1;
assign GND_BUS = 32'b0;
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1) begin
rd_enable_delay <= 1'b0;
rd_enable_delay2 <= 1'b0;
end
else begin
rd_enable_delay <= rd_enable;
rd_enable_delay2 <= rd_enable_delay;
end
end
//---------------------------------------------------------------------------
// Write state machine and control
//---------------------------------------------------------------------------
// Write state machine
// states are WAIT, DATA, EOF, OVFLOW
// clock through next state of sm
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_state <= WAIT_s;
else
wr_state <= wr_nxt_state;
end
// decode next state, combinitorial
// should never be able to overflow whilst not in the data state.
always @(wr_state or wr_sof_pipe[1] or wr_eof_pipe[0] or wr_eof_pipe[1] or wr_eof_bram[0] or wr_fifo_overflow)
begin
case (wr_state)
WAIT_s : begin
if (wr_sof_pipe[1] == 1'b1)
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end
DATA_s : begin
// wait for the end of frame to be detected
if (wr_fifo_overflow == 1'b1 && wr_eof_pipe[0] == 1'b0 && wr_eof_pipe[1] == 1'b0)
wr_nxt_state <= OVFLOW_s;
else if (wr_eof_pipe[1] == 1'b1)
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end
EOF_s : begin
// if the start of frame is already in the pipe, a back to back frame
// transmission has occured. move straight back to frame state
if (wr_sof_pipe[1] == 1'b1)
wr_nxt_state <= DATA_s;
else if (wr_eof_bram[0] == 1'b1)
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end
OVFLOW_s : begin
// wait until the end of frame is reached before clearing the overflow
if (wr_eof_bram[0] == 1'b1)
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end
default : begin
wr_nxt_state <= WAIT_s;
end
endcase
end
// decode output signals.
assign wr_en = (wr_state == OVFLOW_s) ? 1'b0 : wr_accept_bram;
assign wr_addr_inc = wr_en;
assign wr_addr_reload = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0;
assign wr_start_addr_load = (wr_state == EOF_s && wr_nxt_state == WAIT_s) ? 1'b1 :
(wr_state == EOF_s && wr_nxt_state == DATA_s) ? 1'b1 : 1'b0;
// pause the LocalLink flow when the fifo is full.
assign wr_dst_rdy_int_n = (wr_state == OVFLOW_s) ? wr_ovflow_dst_rdy : wr_fifo_full;
assign wr_dst_rdy_n = wr_dst_rdy_int_n;
// when in overflow and have captured ovflow eof send dst rdy high again.
assign overflow = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0;
// when in overflow and have captured ovflow eof send dst rdy high again.
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_ovflow_dst_rdy <= 1'b0;
else
begin
if (wr_fifo_overflow == 1'b1 && wr_state == DATA_s)
wr_ovflow_dst_rdy <= 1'b0;
else if (wr_eof_n == 1'b0 && wr_src_rdy_n == 1'b0)
wr_ovflow_dst_rdy <= 1'b1;
end
end
// eof signals for use in overflow logic
assign wr_eof_state = (wr_state == EOF_s) ? 1'b1 : 1'b0;
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_eof_state_reg <= 1'b0;
else
wr_eof_state_reg <= wr_eof_state;
end
//---------------------------------------------------------------------------
// Read state machine and control
//---------------------------------------------------------------------------
// clock through the read state machine
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_state <= IDLE_s;
else if (rd_enable == 1'b1)
rd_state <= rd_nxt_state;
end
// Full duplex only state machine
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_sm
// decode the next state
always @(rd_state or frame_in_fifo or rd_eof or tx_ack)
begin
case (rd_state)
IDLE_s : begin
// if there is a frame in the fifo start to queue the new frame
// to the output
if (frame_in_fifo == 1'b1)
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end
QUEUE1_s : begin
rd_nxt_state <= QUEUE2_s;
end
QUEUE2_s : begin
rd_nxt_state <= QUEUE3_s;
end
QUEUE3_s : begin
rd_nxt_state <= QUEUE_ACK_s;
end
QUEUE_ACK_s : begin
rd_nxt_state <= WAIT_ACK_s;
end
WAIT_ACK_s : begin
// the output pipe line is fully loaded, so wait for ack from mac
// before moving on
if (tx_ack == 1'b1)
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end
FRAME_s : begin
// when the end of frame has been reached wait another frame in
// the fifo
if (rd_eof == 1'b1)
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end
default : begin
rd_nxt_state <= IDLE_s;
end
endcase
end
end // gen_fd_sm
endgenerate
// Full and Half Duplex State Machine
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_sm
// decode the next state
// should never receive a rd_drop_frame pulse outside of the Frame state
always @(rd_state or frame_in_fifo or rd_eof_reg or tx_ack or rd_drop_frame or rd_retransmit)
begin
case (rd_state)
IDLE_s : begin
// if a retransmit request is detected go to retransmit state
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
// if there is a frame in the fifo then queue the new frame to
// the output
else if (frame_in_fifo == 1'b1)
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end
QUEUE1_s : begin
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE2_s;
end
QUEUE2_s : begin
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE3_s;
end
QUEUE3_s : begin
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE_ACK_s;
end
QUEUE_ACK_s : begin
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= WAIT_ACK_s;
end
WAIT_ACK_s : begin
// the output pipeline is now fully loaded so wait for ack from
// mac before moving on.
if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
else if (tx_ack == 1'b1)
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end
FRAME_s : begin
// if a collision only request, then must drop the rest of the
// current frame, move to drop state
if (rd_drop_frame == 1'b1)
rd_nxt_state <= DROP_s;
else if (rd_retransmit == 1'b1)
rd_nxt_state <= RETRANSMIT_s;
// continue transmitting frame until the end of the frame is
// detected, then wait for a new frame to be sent.
else if (rd_eof_reg == 1'b1)
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end
DROP_s : begin
// wait until rest of frame has been cleared.
if (rd_eof_reg == 1'b1)
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end
RETRANSMIT_s : begin
// reload the data pipe from the start of the frame
rd_nxt_state <= QUEUE1_s;
end
default : begin
rd_nxt_state <= IDLE_s;
end
endcase
end
end // gen_hd_sm
endgenerate
// Decode output signals
// decode output data
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
begin
if (rd_nxt_state == FRAME_s)
tx_data <= rd_data_pipe;
else
begin
case (rd_state)
QUEUE_ACK_s :
tx_data <= rd_data_pipe;
WAIT_ACK_s :
tx_data <= tx_data;
FRAME_s :
tx_data <= rd_data_pipe;
default :
tx_data <= 8'b0;
endcase
end
end
end
// decode output data valid
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
begin
if (rd_nxt_state == FRAME_s)
tx_data_valid <= ~(tx_collision && ~(tx_retransmit));
else
begin
case (rd_state)
QUEUE_ACK_s :
tx_data_valid <= 1'b1;
WAIT_ACK_s :
tx_data_valid <= 1'b1;
FRAME_s :
tx_data_valid <= ~(rd_nxt_state == DROP_s);
default :
tx_data_valid <= 1'b0;
endcase
end
end
end
// decode full duplex only control signals
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_decode
assign rd_en = (rd_state == IDLE_s) ? 1'b0 :
(rd_nxt_state == FRAME_s) ? 1'b1 :
(rd_state == WAIT_ACK_s) ? 1'b0 : 1'b1;
assign rd_addr_inc = rd_en;
assign rd_addr_reload = (rd_state == FRAME_s && rd_nxt_state == IDLE_s) ? 1'b1 : 1'b0;
// Transmit frame pulse is only 1 clock enabled pulse long.
// Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
assign rd_transmit_frame = (rd_state == WAIT_ACK_s && rd_nxt_state == FRAME_s) ? 1'b1 : 1'b0;
// unused for full duplex only
assign rd_start_addr_reload = 1'b0;
assign rd_start_addr_load = 1'b0;
assign rd_retransmit_frame = 1'b0;
end // gen_fd_decode
endgenerate
// decode half duplex control signals
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_decode
assign rd_en = (rd_state == IDLE_s) ? 1'b0 :
(rd_nxt_state == DROP_s && rd_eof == 1'b1) ? 1'b0 :
(rd_nxt_state == FRAME_s) ? 1'b1 :
(rd_state == RETRANSMIT_s) ? 1'b0 :
(rd_state == WAIT_ACK_s) ? 1'b0 : 1'b1;
assign rd_addr_inc = rd_en;
assign rd_addr_reload = (rd_state == FRAME_s && rd_nxt_state == IDLE_s) ? 1'b1 :
(rd_state == DROP_s && rd_nxt_state == IDLE_s) ? 1'b1 : 1'b0;
assign rd_start_addr_reload = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0;
assign rd_start_addr_load = (rd_state == WAIT_ACK_s && rd_nxt_state == FRAME_s) ? 1'b1 :
(rd_col_window_expire == 1'b1) ? 1'b1 : 1'b0;
// Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
assign rd_transmit_frame = (rd_state == WAIT_ACK_s && rd_nxt_state == FRAME_s) ? 1'b1 : 1'b0;
// Retransmit frame pulse must never be more frequent than 16 clocks to allow toggle to cross clock domain
assign rd_retransmit_frame = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0;
end // gen_hd_decode
endgenerate
//---------------------------------------------------------------------------
// Frame Count
// We need to maintain a count of frames in the fifo, so that we know when a
// frame is available for transmission. The counter must be held on the
// write clock domain as this is the faster clock.
//---------------------------------------------------------------------------
// A frame has been written to the fifo
assign wr_store_frame = (wr_state == EOF_s && wr_nxt_state != EOF_s) ? 1'b1 : 1'b0;
// generate a toggle to indicate when a frame has been transmitted from the fifo
always @(posedge rd_clk)
begin // process
if (rd_sreset == 1'b1)
rd_tran_frame_tog <= 1'b0;
else if (rd_enable == 1'b1)
if (rd_transmit_frame == 1'b1) // assumes EOF_s is valid for one clock
rd_tran_frame_tog <= !rd_tran_frame_tog;
end
// move the read transmit frame signal onto the write clock domain
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
begin
wr_tran_frame_tog <= 1'b0;
wr_tran_frame_sync <= 1'b0;
wr_tran_frame_delay <= 1'b0;
wr_transmit_frame <= 1'b0;
end
else
begin
wr_tran_frame_tog <= rd_tran_frame_tog;
wr_tran_frame_sync <= wr_tran_frame_tog;
wr_tran_frame_delay <= wr_tran_frame_sync;
// edge detector
if ((wr_tran_frame_delay ^ wr_tran_frame_sync) == 1'b1)
wr_transmit_frame <= 1'b1;
else
wr_transmit_frame <= 1'b0;
end
end
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_count
// count the number of frames in the fifo. the counter is incremented when a
// frame is stored and decremented when a frame is transmitted. Need to keep
// the counter on the write clock as this is the fastest clock.
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_frames <= 9'b0;
else
if ((wr_store_frame & !wr_transmit_frame) == 1'b1)
wr_frames <= wr_frames + 9'b1;
else if ((!wr_store_frame & wr_transmit_frame) == 1'b1)
wr_frames <= wr_frames - 9'b1;
end
end // gen_fd_count
endgenerate
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_count
// generate a toggle to indicate when a frame has been transmitted from the fifo
always @(posedge rd_clk)
begin // process
if (rd_sreset == 1'b1)
rd_retran_frame_tog <= 1'b0;
else if (rd_enable == 1'b1)
if (rd_retransmit_frame == 1'b1) // assumes EOF_s is valid for one clock
rd_retran_frame_tog <= !rd_retran_frame_tog;
end
// move the read transmit frame signal onto the write clock domain
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
begin
wr_retran_frame_tog <= 1'b0;
wr_retran_frame_sync <= 1'b0;
wr_retran_frame_delay <= 1'b0;
wr_retransmit_frame <= 1'b0;
end
else
begin
wr_retran_frame_tog <= rd_retran_frame_tog;
wr_retran_frame_sync <= wr_retran_frame_tog;
wr_retran_frame_delay <= wr_retran_frame_sync;
// edge detector
if ((wr_retran_frame_delay ^ wr_retran_frame_sync) == 1'b1)
wr_retransmit_frame <= 1'b1;
else
wr_retransmit_frame <= 1'b0;
end
end
// count the number of frames in the fifo. the counter is incremented when a
// frame is stored or retransmitted and decremented when a frame is transmitted. Need to keep
// the counter on the write clock as this is the fastest clock.
// Assumes transmit and retransmit cannot happen at same time
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_frames <= 9'b0;
else
if ((wr_store_frame & wr_retransmit_frame) == 1'b1)
wr_frames <= wr_frames + 9'd2;
else if (((wr_store_frame | wr_retransmit_frame) & !wr_transmit_frame) == 1'b1)
wr_frames <= wr_frames + 9'b1;
else if (wr_transmit_frame == 1'b1 & !wr_store_frame)
wr_frames <= wr_frames - 9'b1;
end
end // gen_hd_count
endgenerate
// generate a frame in fifo signal for use in control logic
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_frame_in_fifo <= 1'b0;
else
if (wr_frames != 9'b0)
wr_frame_in_fifo <= 1'b1;
else
wr_frame_in_fifo <= 1'b0;
end
// register back onto read domain for use in the read logic
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
begin
frame_in_fifo_sync <= 1'b0;
frame_in_fifo <= 1'b0;
end
else if (rd_enable == 1'b1)
begin
frame_in_fifo_sync <= wr_frame_in_fifo;
frame_in_fifo <= frame_in_fifo_sync;
end
end
//---------------------------------------------------------------------------
// Address counters
//---------------------------------------------------------------------------
// Address counters
// write address is incremented when write enable signal has been asserted
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_addr <= 12'b0;
else if (wr_addr_reload == 1'b1)
wr_addr <= wr_start_addr;
else if (wr_addr_inc == 1'b1)
wr_addr <= wr_addr + 12'b1;
end
// store the start address incase the address must be reset
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_start_addr <= 12'b0;
else if (wr_start_addr_load == 1'b1)
wr_start_addr <= wr_addr + 12'b1;
end
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_addr
// read address is incremented when read enable signal has been asserted
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_addr <= 12'b0;
else if (rd_enable == 1'b1)
if (rd_addr_reload == 1'b1)
rd_addr <= rd_dec_addr;
else if (rd_addr_inc == 1'b1)
rd_addr <= rd_addr + 12'b1;
end
// do not need to keep a start address, but the address is needed to
// calculate fifo occupancy.
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_start_addr <= 12'b0;
else if (rd_enable == 1'b1)
rd_start_addr <= rd_addr;
end
end // gen_fd_addr
endgenerate
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_addr
// read address is incremented when read enable signal has been asserted
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_addr <= 12'b0;
else if (rd_enable == 1'b1)
if (rd_addr_reload == 1'b1)
rd_addr <= rd_dec_addr;
else if (rd_start_addr_reload == 1'b1)
rd_addr <= rd_start_addr;
else if (rd_addr_inc == 1'b1)
rd_addr <= rd_addr + 12'b1;
end
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_start_addr <= 12'b0;
else if (rd_enable == 1'b1)
if (rd_start_addr_load == 1'b1)
rd_start_addr <= rd_addr - 12'd4;
end
// Collision window expires after MAC has been transmitting for required slot
// time. This is 512 clock cycles at 1G. Also if the end of frame has fully
// been transmitted by the mac then a collision cannot occur. This collision
// expire signal goes high at 768 cycles from the start of the frame.
// Inefficient for short frames, however should be enough to prevent fifo
// locking up.
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_col_window_expire <= 1'b0;
else if (rd_enable == 1'b1)
if (rd_transmit_frame == 1'b1)
rd_col_window_expire <= 1'b0;
else if (rd_slot_timer[9:8] == 2'b11)
rd_col_window_expire <= 1'b1;
end
assign rd_idle_state = (rd_state == IDLE_s) ? 1'b1 : 1'b0;
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
begin
rd_col_window_pipe[0] <= rd_col_window_expire & rd_idle_state;
if (rd_txfer_en == 1'b1)
rd_col_window_pipe[1] <= rd_col_window_pipe[0];
end
end
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1) // will not count until after first
// frame is sent.
rd_slot_timer <= 10'b0;
else if (rd_enable == 1'b1)
if (rd_transmit_frame == 1'b1) // reset counter
rd_slot_timer <= 10'b0;
// do not allow counter to role over.
// only count when frame is being transmitted.
else if (rd_slot_timer != 10'b1111111111)
rd_slot_timer <= rd_slot_timer + 10'b1;
end
end // gen_hd_addr
endgenerate
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_dec_addr <= 12'b0;
else if (rd_enable == 1'b1)
if (rd_addr_inc == 1'b1)
rd_dec_addr <= rd_addr - 12'b1;
end
//---------------------------------------------------------------------------
// Data pipelines
//---------------------------------------------------------------------------
// register input signals to fifo
// no reset to allow srl16 target
always @(posedge wr_clk)
begin
wr_data_pipe[0] <= wr_data;
if (wr_accept_pipe[0] == 1'b1)
wr_data_pipe[1] <= wr_data_pipe[0];
if (wr_accept_pipe[1] == 1'b1)
wr_data_bram <= wr_data_pipe[1];
end
// no reset to allow srl16 target
always @(posedge wr_clk)
begin
wr_sof_pipe[0] <= !wr_sof_n;
if (wr_accept_pipe[0] == 1'b1)
wr_sof_pipe[1] <= wr_sof_pipe[0];
end
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
begin
wr_accept_pipe[0] <= 1'b0;
wr_accept_pipe[1] <= 1'b0;
wr_accept_bram <= 1'b0;
end
else
begin
wr_accept_pipe[0] <= !wr_src_rdy_n & !wr_dst_rdy_int_n;
wr_accept_pipe[1] <= wr_accept_pipe[0];
wr_accept_bram <= wr_accept_pipe[1];
end
end
always @(posedge wr_clk)
begin
wr_eof_pipe[0] <= !wr_eof_n;
if (wr_accept_pipe[0] == 1'b1)
wr_eof_pipe[1] <= wr_eof_pipe[0];
if (wr_accept_pipe[1] == 1'b1)
wr_eof_bram[0] <= wr_eof_pipe[1];
end
// register data output
// no reset to allow srl16 target
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
if (rd_en == 1'b1)
rd_data_pipe <= rd_data_bram;
end
// register data output
// no reset to allow srl16 target
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
if (rd_en == 1'b1)
begin
rd_eof <= rd_eof_bram;
rd_eof_reg <= rd_eof | rd_eof_bram;
end
end
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_input
// register the collision and retransmit signals
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
rd_drop_frame <= tx_collision & !tx_retransmit;
end
always @(posedge rd_clk)
begin
if (rd_enable == 1'b1)
rd_retransmit <= tx_collision & tx_retransmit;
end
end // gen_hd_input
endgenerate
//---------------------------------------------------------------------------
// FIFO full functionality
//---------------------------------------------------------------------------
// when full duplex full functionality is difference between read and write addresses.
// when in half duplex is difference between read start and write addresses.
// Cannot use gray code this time as the read address and read start addresses jump by more than 1
// generate an enable pulse for the read side every 16 read clocks. This provides for the worst case
// situation where wr clk is 20Mhz and rd clk is 125 Mhz.
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_16_count <= 4'b0;
else if (rd_enable == 1'b1)
rd_16_count <= rd_16_count + 4'b1;
end
assign rd_txfer_en = (rd_16_count == 4'b1111) ? 1'b1 : 1'b0;
// register the start address on the enable pulse
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_addr_txfer <= 12'b0;
else if (rd_enable == 1'b1)
begin
if (rd_txfer_en == 1'b1)
rd_addr_txfer <= rd_start_addr;
end
end
// generate a toggle to indicate that the address has been loaded.
always @(posedge rd_clk)
begin
if (rd_sreset == 1'b1)
rd_txfer_tog <= 1'b0;
else if (rd_enable == 1'b1)
begin
if (rd_txfer_en == 1'b1)
rd_txfer_tog <= !rd_txfer_tog;
end
end
// pass the toggle to the write side
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
begin
wr_txfer_tog <= 1'b0;
wr_txfer_tog_sync <= 1'b0;
wr_txfer_tog_delay <= 1'b0;
end
else
begin
wr_txfer_tog <= rd_txfer_tog;
wr_txfer_tog_sync <= wr_txfer_tog;
wr_txfer_tog_delay <= wr_txfer_tog_sync;
end
end
// generate an enable pulse from the toggle, the address should have
// been steady on the wr clock input for at least one clock
assign wr_txfer_en = wr_txfer_tog_delay ^ wr_txfer_tog_sync;
// capture the address on the write clock when the enable pulse is high.
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_rd_addr <= 12'b0;
else if (wr_txfer_en == 1'b1)
wr_rd_addr <= rd_addr_txfer;
end
// Obtain the difference between write and read pointers
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_addr_diff <= 12'b0;
else
wr_addr_diff <= wr_rd_addr - wr_addr;
end
// Detect when the FIFO is full
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_fifo_full <= 1'b0;
else
// The FIFO is considered to be full if the write address
// pointer is within 1 to 3 of the read address pointer.
if (wr_addr_diff[11:4] == 8'b0 && wr_addr_diff[3:2] != 2'b0)
wr_fifo_full <= 1'b1;
else
wr_fifo_full <= 1'b0;
end
// memory overflow occurs when the fifo is full and there are no frames
// available in the fifo for transmission. If the collision window has
// expired and there are no frames in the fifo and the fifo is full, then the
// fifo is in an overflow state. we must accept the rest of the incoming
// frame in overflow condition.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_ovflow
// in full duplex mode, the fifo memory can only overflow if the fifo goes
// full but there is no frame available to be retranmsitted
// do not allow to go high when the frame count is being updated, ie wr_store_frame is asserted.
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0
&& wr_eof_state == 1'b0 && wr_eof_state_reg == 1'b0) ? 1'b1 : 1'b0;
end // gen_fd_ovflow
endgenerate
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_ovflow
// register wr col window to give address counter sufficient time to update.
// do not allow to go high when the frame count is being updated, ie wr_store_frame is asserted.
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0
&& wr_eof_state == 1'b0 && wr_eof_state_reg == 1'b0
&& wr_col_window_expire == 1'b1) ? 1'b1 : 1'b0;
// register rd_col_window signal
// this signal is long, and will remain high until overflow functionality
// has finished, so save just to register the once.
always @(posedge wr_clk)
begin // process
if (wr_sreset == 1'b1)
begin
wr_col_window_pipe[0] <= 1'b0;
wr_col_window_pipe[1] <= 1'b0;
wr_col_window_expire <= 1'b0;
end
else
begin
if (wr_txfer_en == 1'b1)
wr_col_window_pipe[0] <= rd_col_window_pipe[1];
wr_col_window_pipe[1] <= wr_col_window_pipe[0];
wr_col_window_expire <= wr_col_window_pipe[1];
end
end
end // gen_hd_ovflow
endgenerate
//--------------------------------------------------------------------
// Create FIFO Status Signals in the Write Domain
//--------------------------------------------------------------------
// The FIFO status signal is four bits which represents the occupancy
// of the FIFO in 16'ths. To generate this signal we therefore only
// need to compare the 4 most significant bits of the write address
// pointer with the 4 most significant bits of the read address
// pointer.
// The 4 most significant bits of the write pointer minus the 4 msb of
// the read pointer gives us our FIFO status.
always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_fifo_status <= 4'b0;
else
if (wr_addr_diff == 12'b0)
wr_fifo_status <= 4'b0;
else
begin
wr_fifo_status[3] <= !wr_addr_diff[11];
wr_fifo_status[2] <= !wr_addr_diff[10];
wr_fifo_status[1] <= !wr_addr_diff[9];
wr_fifo_status[0] <= !wr_addr_diff[8];
end
end
//---------------------------------------------------------------------------
// Memory
//---------------------------------------------------------------------------
assign rd_en_bram = rd_en & rd_enable_delay2;
RAMB36E1 #(
.DOB_REG (1),
.READ_WIDTH_A (9),
.READ_WIDTH_B (9),
.RSTREG_PRIORITY_B ("RSTREG"),
.SIM_COLLISION_CHECK ("ALL"),
.SRVAL_B (36'h0),
.WRITE_MODE_A ("WRITE_FIRST"),
.WRITE_MODE_B ("WRITE_FIRST"),
.WRITE_WIDTH_A (9),
.WRITE_WIDTH_B (9)
)
ramgen (
.ENARDEN (VCC),
.CLKARDCLK (wr_clk),
.RSTRAMARSTRAM (wr_sreset),
.RSTREGARSTREG (GND),
.CASCADEINA (GND),
.REGCEAREGCE (GND),
.ENBWREN (rd_en_bram),
.CLKBWRCLK (rd_clk),
.RSTRAMB (rd_sreset),
.RSTREGB (rd_sreset),
.CASCADEINB (GND),
.REGCEB (rd_en_bram),
.INJECTDBITERR (GND),
.INJECTSBITERR (GND),
.ADDRARDADDR ({GND, wr_addr, GND_BUS[2:0]}),
.ADDRBWRADDR ({GND, rd_addr, GND_BUS[2:0]}),
.DIADI ({GND_BUS[23:0], wr_data_bram}),
.DIBDI (GND_BUS),
.DIPADIP ({GND_BUS[2:0], wr_eof_bram[0]}),
.DIPBDIP (GND_BUS[3:0]),
.WEA ({GND_BUS[2:0], wr_en}),
.WEBWE (GND_BUS[7:0]),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DOADO (),
.DOBDO (dob_bram),
.DOPADOP (),
.DOPBDOP (dopb_bram),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.DBITERR ()
);
assign rd_data_bram = dob_bram[7:0];
assign rd_eof_bram = dopb_bram[0];
endmodule
|
`default_nettype none
module gci_std_display_hub_interface(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//HUB(Reqest/Write)
input wire iHUB_REQ,
output wire oHUB_BUSY,
input wire iHUB_RW,
input wire [31:0] iHUB_ADDR,
input wire [31:0] iHUB_DATA,
//HUB(Read)
output wire oHUB_VALID,
input wire iHUB_BUSY,
output wire oHUB_DATA,
//Register(Request/Write)
output wire oREG_ENA,
output wire oREG_RW,
output wire [3:0] oREG_ADDR,
output wire [31:0] oREG_DATA,
//Register(Read)
input wire iREG_VALID,
output wire oREG_BUSY,
input wire [31:0] iREG_DATA,
//Command(Request/Write)
output wire oCOMM_VALID,
output wire oCOMM_SEQ,
input wire iCOMM_BUSY,
output wire oCOMM_RW,
output wire [31:0] oCOMM_ADDR,
output wire [31:0] oCOMM_DATA,
//Command(Read)
input wire iCOMM_VALID,
output wire oCOMM_BUSY,
input wire [31:0] iCOMM_ADDR,
input wire [23:0] iCOMM_DATA
);
//Register / Command -> Hub
assign oHUB_BUSY =
assign oHUB_VALID =
assign oHUB_DATA =
//Hub -> Register
assign oREG_ENA = register_ctrl_condition;
assign oREG_RW = iHUB_RW;
assign oREG_ADDR = iHUB_ADDR;
assign oREG_DATA = iHUB_DATA;
assign oREG_BUSY =
//Hub -> Command
assign oCOMM_VALID = display_ctrl_condition || sequence_ctrl_condition;
assign oCOMM_SEQ = sequence_ctrl_condition;
assign oCOMM_RW = iHUB_RW;
assign oCOMM_ADDR = iHUB_ADDR;
assign oCOMM_DATA = iHUB_DATA;
assign oCOMM_BUSY =
wire register_busy_condition =
wire display_busy_condition =
wire sequence_busy_condition =
wire register_ctrl_condition = iHUB_ADDR <= 32'hF && (iHUB_ADDR == 32'h4)? !iHUB_RW : 1'b1;
wire display_ctrl_condition = iHUB_ADDR > 32'hF;
wire sequence_ctrl_condition = (iHUB_ADDR == 32'h4) && iHUB_RW;
localparam P_L_MAIN_STT_WRITE = 1'b0;
localparam P_L_MAIN_STT_READ_WAIT = 1'b1;
reg b_main_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_WRITE;
end
else if(iRESET_SYNC)begin
b_main_state <= P_L_MAIN_STT_WRITE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_WRITE:
begin
if(!iHUB_RW)begin
b_main_state <= P_L_MAIN_STT_READ_WAIT;
end
end
P_L_MAIN_STT_READ_WAIT:
begin
if(!iHUB_BUSY && ())begin
b_main_state <= P_L_MAIN_STT_WRITE;
end
end
endcase
end
end
assign oIF_WR_BUSY = (iIF_WR_RW)? ??? :
endmodule
`default_nettype wire
|
//======================================================================
//
// aes_key_mem.v
// -------------
// The AES key memory including round key generator.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module aes_key_mem(
input wire clk,
input wire reset_n,
input wire [255 : 0] key,
input wire keylen,
input wire init,
input wire [3 : 0] round,
output wire [127 : 0] round_key,
output wire ready,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES_128_NUM_ROUNDS = 10;
localparam AES_256_NUM_ROUNDS = 14;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_GENERATE = 3'h2;
localparam CTRL_DONE = 3'h3;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [127 : 0] key_mem [0 : 14];
reg [127 : 0] key_mem_new;
reg key_mem_we;
reg [127 : 0] prev_key0_reg;
reg [127 : 0] prev_key0_new;
reg prev_key0_we;
reg [127 : 0] prev_key1_reg;
reg [127 : 0] prev_key1_new;
reg prev_key1_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_rst;
reg round_ctr_inc;
reg round_ctr_we;
reg [2 : 0] key_mem_ctrl_reg;
reg [2 : 0] key_mem_ctrl_new;
reg key_mem_ctrl_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [7 : 0] rcon_reg;
reg [7 : 0] rcon_new;
reg rcon_we;
reg rcon_set;
reg rcon_next;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
reg round_key_update;
reg [127 : 0] tmp_round_key;
//----------------------------------------------------------------
// Concurrent assignments for ports.
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
assign sboxw = tmp_sboxw;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
key_mem [i] <= 128'h0;
ready_reg <= 1'b0;
rcon_reg <= 8'h0;
round_ctr_reg <= 4'h0;
prev_key0_reg <= 128'h0;
prev_key1_reg <= 128'h0;
key_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ready_we)
ready_reg <= ready_new;
if (rcon_we)
rcon_reg <= rcon_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (key_mem_we)
key_mem[round_ctr_reg] <= key_mem_new;
if (prev_key0_we)
prev_key0_reg <= prev_key0_new;
if (prev_key1_we)
prev_key1_reg <= prev_key1_new;
if (key_mem_ctrl_we)
key_mem_ctrl_reg <= key_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// key_mem_read
//
// Combinational read port for the key memory.
//----------------------------------------------------------------
always @*
begin : key_mem_read
tmp_round_key = key_mem[round];
end // key_mem_read
//----------------------------------------------------------------
// round_key_gen
//
// The round key generator logic for AES-128 and AES-256.
//----------------------------------------------------------------
always @*
begin: round_key_gen
reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
reg [31 : 0] k0, k1, k2, k3;
reg [31 : 0] rconw, rotstw, tw, trw;
// Default assignments.
key_mem_new = 128'h0;
key_mem_we = 1'b0;
prev_key0_new = 128'h0;
prev_key0_we = 1'b0;
prev_key1_new = 128'h0;
prev_key1_we = 1'b0;
k0 = 32'h0;
k1 = 32'h0;
k2 = 32'h0;
k3 = 32'h0;
rcon_set = 1'b1;
rcon_next = 1'b0;
// Extract words and calculate intermediate values.
// Perform rotation of sbox word etc.
w0 = prev_key0_reg[127 : 096];
w1 = prev_key0_reg[095 : 064];
w2 = prev_key0_reg[063 : 032];
w3 = prev_key0_reg[031 : 000];
w4 = prev_key1_reg[127 : 096];
w5 = prev_key1_reg[095 : 064];
w6 = prev_key1_reg[063 : 032];
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
tmp_sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;
// Generate the specific round keys.
if (round_key_update)
begin
rcon_set = 1'b0;
key_mem_we = 1'b1;
case (keylen)
AES_128_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key1_new = key[255 : 128];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
k0 = w4 ^ trw;
k1 = w5 ^ w4 ^ trw;
k2 = w6 ^ w5 ^ w4 ^ trw;
k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
end
AES_256_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key0_new = key[255 : 128];
prev_key0_we = 1'b1;
end
else if (round_ctr_reg == 1)
begin
key_mem_new = key[127 : 0];
prev_key1_new = key[127 : 0];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
if (round_ctr_reg[0] == 0)
begin
k0 = w0 ^ trw;
k1 = w1 ^ w0 ^ trw;
k2 = w2 ^ w1 ^ w0 ^ trw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
end
else
begin
k0 = w0 ^ tw;
k1 = w1 ^ w0 ^ tw;
k2 = w2 ^ w1 ^ w0 ^ tw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
rcon_next = 1'b1;
end
// Store the generated round keys.
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
prev_key0_new = prev_key1_reg;
prev_key0_we = 1'b1;
end
end
default:
begin
end
endcase // case (keylen)
end
end // round_key_gen
//----------------------------------------------------------------
// rcon_logic
//
// Caclulates the rcon value for the different key expansion
// iterations.
//----------------------------------------------------------------
always @*
begin : rcon_logic
reg [7 : 0] tmp_rcon;
rcon_new = 8'h00;
rcon_we = 1'b0;
tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
if (rcon_set)
begin
rcon_new = 8'h8d;
rcon_we = 1'b1;
end
if (rcon_next)
begin
rcon_new = tmp_rcon[7 : 0];
rcon_we = 1'b1;
end
end
//----------------------------------------------------------------
// round_ctr
//
// The round counter logic with increase and reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// key_mem_ctrl
//
//
// The FSM that controls the round key generation.
//----------------------------------------------------------------
always @*
begin: key_mem_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
ready_new = 1'b0;
ready_we = 1'b0;
round_key_update = 1'b0;
round_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b0;
if (keylen == AES_128_BIT_KEY)
num_rounds = AES_128_NUM_ROUNDS;
else
num_rounds = AES_256_NUM_ROUNDS;
case(key_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'b0;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_INIT;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_rst = 1'b1;
key_mem_ctrl_new = CTRL_GENERATE;
key_mem_ctrl_we = 1'b1;
end
CTRL_GENERATE:
begin
round_ctr_inc = 1'b1;
round_key_update = 1'b1;
if (round_ctr_reg == num_rounds)
begin
key_mem_ctrl_new = CTRL_DONE;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_DONE:
begin
ready_new = 1'b1;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b1;
end
default:
begin
end
endcase // case (key_mem_ctrl_reg)
end // key_mem_ctrl
endmodule // aes_key_mem
//======================================================================
// EOF aes_key_mem.v
//======================================================================
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file wfifo.v when simulating
// the core, wfifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module wfifo(
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_empty
);
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [15 : 0] din;
input wr_en;
input rd_en;
output [15 : 0] dout;
output full;
output empty;
output prog_empty;
// synthesis translate_off
FIFO_GENERATOR_V8_2 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(0),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(32),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(64),
.C_PROG_EMPTY_TYPE(2),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.WR_CLK(wr_clk),
.WR_RST(wr_rst),
.RD_CLK(rd_clk),
.RD_RST(rd_rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_EMPTY(prog_empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FILL_DIODE_PP_BLACKBOX_V
/**
* fill_diode: Fill diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_PP_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Wed Apr 13 17:20:49 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_sim_netlist.v
// Design : FiFo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "FiFo,fifo_generator_v13_0_1,{}" *) (* core_generation_info = "FiFo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module FiFo
(clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [7:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [7:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [5:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [5:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [5:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "6" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "8" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "0" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "2" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "2" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "2" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "62" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "61" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "6" *)
(* C_RD_DEPTH = "64" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "6" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "6" *)
(* C_WR_DEPTH = "64" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "6" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
FiFo_fifo_generator_v13_0_1 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[5:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[5:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[5:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module FiFo_blk_mem_gen_generic_cstr
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module FiFo_blk_mem_gen_prim_width
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module FiFo_blk_mem_gen_prim_wrapper
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9 ;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,1'b0,\gc0.count_d1_reg[5] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,Q,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[3:2],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[1:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:6],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[5:4]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5 ,dout[3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13 ,dout[1:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21 ,dout[7:6],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29 ,dout[5:4]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(E),
.ENBWREN(ram_full_fb_i_reg),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module FiFo_blk_mem_gen_top
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *)
module FiFo_blk_mem_gen_v8_3_1
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module FiFo_blk_mem_gen_v8_3_1_synth
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module FiFo_fifo_generator_ramfifo
(dout,
empty,
full,
clk,
din,
wr_en,
rd_en);
output [7:0]dout;
output empty;
output full;
input clk;
input [7:0]din;
input wr_en;
input rd_en;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire \gwss.wsts/ram_full_comb ;
wire [5:0]p_0_out;
wire [5:0]p_10_out;
wire [5:0]p_11_out;
wire p_16_out;
wire p_1_out;
wire p_2_out;
wire ram_rd_en_i;
wire rd_en;
wire [5:0]rd_pntr_plus1;
wire wr_en;
FiFo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_0_out),
.E(ram_rd_en_i),
.Q(p_11_out),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[5] (rd_pntr_plus1),
.\gc0.count_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_3 ),
.\gcc0.gc0.count_d1_reg[5] (p_10_out),
.p_1_out(p_1_out),
.p_2_out(p_2_out),
.ram_full_comb(\gwss.wsts/ram_full_comb ),
.rd_en(rd_en),
.wr_en(wr_en));
FiFo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.E(p_16_out),
.Q(p_10_out),
.clk(clk),
.full(full),
.\gc0.count_reg[5] (rd_pntr_plus1),
.\gcc0.gc0.count_d1_reg[5] (p_11_out),
.p_1_out(p_1_out),
.p_2_out(p_2_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.ram_full_comb(\gwss.wsts/ram_full_comb ),
.rd_en(rd_en),
.wr_en(wr_en));
FiFo_memory \gntv_or_sync_fifo.mem
(.E(ram_rd_en_i),
.Q(p_10_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (p_0_out),
.ram_full_fb_i_reg(p_16_out));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module FiFo_fifo_generator_top
(dout,
empty,
full,
clk,
din,
wr_en,
rd_en);
output [7:0]dout;
output empty;
output full;
input clk;
input [7:0]din;
input wr_en;
input rd_en;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire wr_en;
FiFo_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "6" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "8" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "2" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "2" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "2" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "62" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "61" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "6" *)
(* C_RD_DEPTH = "64" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "6" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "0" *)
(* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "6" *) (* C_WR_DEPTH = "64" *)
(* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "6" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *)
(* ORIG_REF_NAME = "fifo_generator_v13_0_1" *)
module FiFo_fifo_generator_v13_0_1
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [7:0]din;
input wr_en;
input rd_en;
input [5:0]prog_empty_thresh;
input [5:0]prog_empty_thresh_assert;
input [5:0]prog_empty_thresh_negate;
input [5:0]prog_full_thresh;
input [5:0]prog_full_thresh_assert;
input [5:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [7:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [5:0]data_count;
output [5:0]rd_data_count;
output [5:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [5:0]prog_empty_thresh;
wire [5:0]prog_empty_thresh_assert;
wire [5:0]prog_empty_thresh_negate;
wire [5:0]prog_full_thresh;
wire [5:0]prog_full_thresh_assert;
wire [5:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
FiFo_fifo_generator_v13_0_1_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_0_1_synth" *)
module FiFo_fifo_generator_v13_0_1_synth
(dout,
empty,
full,
wr_en,
clk,
din,
s_aclk,
rd_en,
s_aresetn);
output [7:0]dout;
output empty;
output full;
input wr_en;
input clk;
input [7:0]din;
input s_aclk;
input rd_en;
input s_aresetn;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire s_aclk;
wire s_aresetn;
wire wr_en;
FiFo_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.wr_en(wr_en));
FiFo_reset_blk_ramfifo \reset_gen_cc.rstblk_cc
(.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "memory" *)
module FiFo_memory
(dout,
clk,
E,
ram_full_fb_i_reg,
\gc0.count_d1_reg[5] ,
Q,
din);
output [7:0]dout;
input clk;
input [0:0]E;
input [0:0]ram_full_fb_i_reg;
input [5:0]\gc0.count_d1_reg[5] ;
input [5:0]Q;
input [7:0]din;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]ram_full_fb_i_reg;
FiFo_blk_mem_gen_v8_3_1 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module FiFo_rd_bin_cntr
(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
ram_empty_fb_i_reg,
ram_full_comb,
\gc0.count_d1_reg[5]_0 ,
Q,
p_1_out,
wr_en,
p_2_out,
\gc0.count_reg[0]_0 ,
rd_en,
\gcc0.gc0.count_d1_reg[5] ,
E,
clk);
output [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output ram_empty_fb_i_reg;
output ram_full_comb;
output [5:0]\gc0.count_d1_reg[5]_0 ;
input [5:0]Q;
input p_1_out;
input wr_en;
input p_2_out;
input \gc0.count_reg[0]_0 ;
input rd_en;
input [5:0]\gcc0.gc0.count_d1_reg[5] ;
input [0:0]E;
input clk;
wire [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [5:0]\gc0.count_d1_reg[5]_0 ;
wire \gc0.count_reg[0]_0 ;
wire [5:0]\gcc0.gc0.count_d1_reg[5] ;
wire p_1_out;
wire p_2_out;
wire [5:0]plusOp;
wire ram_empty_fb_i_reg;
wire ram_full_comb;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_3_n_0;
wire ram_full_i_i_4_n_0;
wire ram_full_i_i_5_n_0;
wire ram_full_i_i_6_n_0;
wire ram_full_i_i_7_n_0;
wire rd_en;
wire wr_en;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [0]),
.I1(\gc0.count_d1_reg[5]_0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [0]),
.I1(\gc0.count_d1_reg[5]_0 [1]),
.I2(\gc0.count_d1_reg[5]_0 [2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[3]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [3]),
.I1(\gc0.count_d1_reg[5]_0 [0]),
.I2(\gc0.count_d1_reg[5]_0 [1]),
.I3(\gc0.count_d1_reg[5]_0 [2]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [4]),
.I1(\gc0.count_d1_reg[5]_0 [2]),
.I2(\gc0.count_d1_reg[5]_0 [1]),
.I3(\gc0.count_d1_reg[5]_0 [0]),
.I4(\gc0.count_d1_reg[5]_0 [3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(\gc0.count_d1_reg[5]_0 [5]),
.I1(\gc0.count_d1_reg[5]_0 [3]),
.I2(\gc0.count_d1_reg[5]_0 [0]),
.I3(\gc0.count_d1_reg[5]_0 [1]),
.I4(\gc0.count_d1_reg[5]_0 [2]),
.I5(\gc0.count_d1_reg[5]_0 [4]),
.O(plusOp[5]));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(\gc0.count_d1_reg[5]_0 [5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.Q(\gc0.count_d1_reg[5]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp[1]),
.Q(\gc0.count_d1_reg[5]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp[2]),
.Q(\gc0.count_d1_reg[5]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp[3]),
.Q(\gc0.count_d1_reg[5]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp[4]),
.Q(\gc0.count_d1_reg[5]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp[5]),
.Q(\gc0.count_d1_reg[5]_0 [5]),
.R(1'b0));
LUT5 #(
.INIT(32'h4F444F4F))
ram_empty_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(p_2_out),
.I2(\gc0.count_reg[0]_0 ),
.I3(p_1_out),
.I4(wr_en),
.O(ram_empty_fb_i_reg));
LUT5 #(
.INIT(32'h4F444F4F))
ram_full_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(p_1_out),
.I2(ram_full_i_i_3_n_0),
.I3(p_2_out),
.I4(rd_en),
.O(ram_full_comb));
LUT6 #(
.INIT(64'h0000000000009009))
ram_full_i_i_2
(.I0(\gcc0.gc0.count_d1_reg[5] [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.I2(\gcc0.gc0.count_d1_reg[5] [5]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I4(ram_full_i_i_4_n_0),
.I5(ram_full_i_i_5_n_0),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h0000BFFB0000FFFF))
ram_full_i_i_3
(.I0(ram_full_i_i_6_n_0),
.I1(ram_full_i_i_7_n_0),
.I2(Q[0]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.I4(p_1_out),
.I5(wr_en),
.O(ram_full_i_i_3_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.I1(\gcc0.gc0.count_d1_reg[5] [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.I3(\gcc0.gc0.count_d1_reg[5] [0]),
.O(ram_full_i_i_4_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I1(\gcc0.gc0.count_d1_reg[5] [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I3(\gcc0.gc0.count_d1_reg[5] [2]),
.O(ram_full_i_i_5_n_0));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
ram_full_i_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I1(Q[5]),
.I2(Q[2]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I4(Q[1]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.O(ram_full_i_i_6_n_0));
LUT4 #(
.INIT(16'h9009))
ram_full_i_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I1(Q[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.I3(Q[4]),
.O(ram_full_i_i_7_n_0));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module FiFo_rd_logic
(p_2_out,
empty,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
ram_full_comb,
E,
\gc0.count_d1_reg[5] ,
clk,
Q,
p_1_out,
wr_en,
\gc0.count_reg[0] ,
rd_en,
\gcc0.gc0.count_d1_reg[5] );
output p_2_out;
output empty;
output [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output ram_full_comb;
output [0:0]E;
output [5:0]\gc0.count_d1_reg[5] ;
input clk;
input [5:0]Q;
input p_1_out;
input wr_en;
input \gc0.count_reg[0] ;
input rd_en;
input [5:0]\gcc0.gc0.count_d1_reg[5] ;
wire [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire empty;
wire [5:0]\gc0.count_d1_reg[5] ;
wire \gc0.count_reg[0] ;
wire [5:0]\gcc0.gc0.count_d1_reg[5] ;
wire p_1_out;
wire p_2_out;
wire ram_full_comb;
wire rd_en;
wire rpntr_n_6;
wire wr_en;
FiFo_rd_status_flags_ss \grss.rsts
(.E(E),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[5] (p_2_out),
.ram_empty_fb_i_reg_0(rpntr_n_6),
.rd_en(rd_en));
FiFo_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(E),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[5]_0 (\gc0.count_d1_reg[5] ),
.\gc0.count_reg[0]_0 (\gc0.count_reg[0] ),
.\gcc0.gc0.count_d1_reg[5] (\gcc0.gc0.count_d1_reg[5] ),
.p_1_out(p_1_out),
.p_2_out(p_2_out),
.ram_empty_fb_i_reg(rpntr_n_6),
.ram_full_comb(ram_full_comb),
.rd_en(rd_en),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_ss" *)
module FiFo_rd_status_flags_ss
(\gc0.count_d1_reg[5] ,
empty,
E,
ram_empty_fb_i_reg_0,
clk,
rd_en);
output \gc0.count_d1_reg[5] ;
output empty;
output [0:0]E;
input ram_empty_fb_i_reg_0;
input clk;
input rd_en;
wire [0:0]E;
wire clk;
wire empty;
wire \gc0.count_d1_reg[5] ;
wire ram_empty_fb_i_reg_0;
wire rd_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1
(.I0(rd_en),
.I1(\gc0.count_d1_reg[5] ),
.O(E));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.Q(\gc0.count_d1_reg[5] ),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.Q(empty),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module FiFo_reset_blk_ramfifo
(s_aclk,
s_aresetn);
input s_aclk;
input s_aresetn;
wire inverted_reset;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(inverted_reset),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(inverted_reset),
.Q(rst_d3));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(inverted_reset));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module FiFo_wr_bin_cntr
(ram_empty_fb_i_reg,
Q,
\gcc0.gc0.count_d1_reg[5]_0 ,
\gc0.count_reg[5] ,
rd_en,
p_2_out,
E,
clk);
output ram_empty_fb_i_reg;
output [5:0]Q;
output [5:0]\gcc0.gc0.count_d1_reg[5]_0 ;
input [5:0]\gc0.count_reg[5] ;
input rd_en;
input p_2_out;
input [0:0]E;
input clk;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire [5:0]\gc0.count_reg[5] ;
wire [5:0]\gcc0.gc0.count_d1_reg[5]_0 ;
wire p_2_out;
wire [5:0]plusOp__0;
wire ram_empty_fb_i_reg;
wire ram_empty_i_i_3_n_0;
wire ram_empty_i_i_4_n_0;
wire rd_en;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.I1(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.I1(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.I2(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h6AAA))
\gcc0.gc0.count[3]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [3]),
.I1(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.I2(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.I3(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gcc0.gc0.count[4]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [4]),
.I1(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.I2(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.I3(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.I4(\gcc0.gc0.count_d1_reg[5]_0 [3]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gcc0.gc0.count[5]_i_1
(.I0(\gcc0.gc0.count_d1_reg[5]_0 [5]),
.I1(\gcc0.gc0.count_d1_reg[5]_0 [3]),
.I2(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.I3(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.I4(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.I5(\gcc0.gc0.count_d1_reg[5]_0 [4]),
.O(plusOp__0[5]));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [3]),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [4]),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(\gcc0.gc0.count_d1_reg[5]_0 [5]),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp__0[1]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp__0[2]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp__0[3]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp__0[4]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp__0[5]),
.Q(\gcc0.gc0.count_d1_reg[5]_0 [5]),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFF7DFF))
ram_empty_i_i_2
(.I0(ram_empty_i_i_3_n_0),
.I1(\gc0.count_reg[5] [0]),
.I2(Q[0]),
.I3(rd_en),
.I4(ram_empty_i_i_4_n_0),
.I5(p_2_out),
.O(ram_empty_fb_i_reg));
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3
(.I0(Q[5]),
.I1(\gc0.count_reg[5] [5]),
.I2(Q[4]),
.I3(\gc0.count_reg[5] [4]),
.O(ram_empty_i_i_3_n_0));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
ram_empty_i_i_4
(.I0(Q[3]),
.I1(\gc0.count_reg[5] [3]),
.I2(\gc0.count_reg[5] [2]),
.I3(Q[2]),
.I4(\gc0.count_reg[5] [1]),
.I5(Q[1]),
.O(ram_empty_i_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module FiFo_wr_logic
(p_1_out,
full,
E,
ram_empty_fb_i_reg,
Q,
\gcc0.gc0.count_d1_reg[5] ,
ram_full_comb,
clk,
wr_en,
\gc0.count_reg[5] ,
rd_en,
p_2_out);
output p_1_out;
output full;
output [0:0]E;
output ram_empty_fb_i_reg;
output [5:0]Q;
output [5:0]\gcc0.gc0.count_d1_reg[5] ;
input ram_full_comb;
input clk;
input wr_en;
input [5:0]\gc0.count_reg[5] ;
input rd_en;
input p_2_out;
wire [0:0]E;
wire [5:0]Q;
wire clk;
wire full;
wire [5:0]\gc0.count_reg[5] ;
wire [5:0]\gcc0.gc0.count_d1_reg[5] ;
wire p_1_out;
wire p_2_out;
wire ram_empty_fb_i_reg;
wire ram_full_comb;
wire rd_en;
wire wr_en;
FiFo_wr_status_flags_ss \gwss.wsts
(.E(E),
.clk(clk),
.full(full),
.p_1_out(p_1_out),
.ram_full_comb(ram_full_comb),
.wr_en(wr_en));
FiFo_wr_bin_cntr wpntr
(.E(E),
.Q(Q),
.clk(clk),
.\gc0.count_reg[5] (\gc0.count_reg[5] ),
.\gcc0.gc0.count_d1_reg[5]_0 (\gcc0.gc0.count_d1_reg[5] ),
.p_2_out(p_2_out),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.rd_en(rd_en));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_ss" *)
module FiFo_wr_status_flags_ss
(p_1_out,
full,
E,
ram_full_comb,
clk,
wr_en);
output p_1_out;
output full;
output [0:0]E;
input ram_full_comb;
input clk;
input wr_en;
wire [0:0]E;
wire clk;
wire full;
wire p_1_out;
wire ram_full_comb;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.Q(p_1_out),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.Q(full),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_dbg_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Top level Module: jbi_dbg_ctl
// Where Instantiated: jbi_dbg
// Description: Debug Port Queue Control logic
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_dbg_ctl(/*AUTOARG*/
// Outputs
dbg_req_transparent, dbg_req_arbitrate, dbg_req_priority, dbg_data,
dbgq_hi_raddr, dbgq_hi_waddr, dbgq_hi_csn_wr, dbgq_hi_csn_rd,
dbgq_hi_wdata, dbgq_lo_raddr, dbgq_lo_waddr, dbgq_lo_csn_wr,
dbgq_lo_csn_rd, dbgq_lo_wdata,
// Inputs
clk, rst_l, dbg_rst_l, iob_jbi_dbg_hi_vld, iob_jbi_dbg_hi_data,
iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, csr_jbi_debug_arb_max_wait,
csr_jbi_debug_arb_hi_water, csr_jbi_debug_arb_lo_water,
csr_jbi_debug_arb_data_arb, csr_jbi_debug_arb_tstamp_wrap,
csr_jbi_debug_arb_alternate, csr_jbi_debug_arb_alternate_set_l,
mout_dbg_pop, dbgq_hi_rdata, dbgq_lo_rdata
); //Enter the name of tne module
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
input clk;
input rst_l;
input dbg_rst_l;
// IOB Interface
input iob_jbi_dbg_hi_vld;
input [47:0] iob_jbi_dbg_hi_data;
input iob_jbi_dbg_lo_vld;
input [47:0] iob_jbi_dbg_lo_data;
// CSR Interface
input [`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0] csr_jbi_debug_arb_max_wait;
input [`JBI_CSR_DBG_HI_WATER_WIDTH-1:0] csr_jbi_debug_arb_hi_water;
input [`JBI_CSR_DBG_LO_WATER_WIDTH-1:0] csr_jbi_debug_arb_lo_water;
input csr_jbi_debug_arb_data_arb;
input [`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] csr_jbi_debug_arb_tstamp_wrap;
input csr_jbi_debug_arb_alternate;
input csr_jbi_debug_arb_alternate_set_l;
// Memory Out (mout) Interface
input mout_dbg_pop;
output dbg_req_transparent;
output dbg_req_arbitrate;
output dbg_req_priority;
output [127:0] dbg_data;
// DBGQ Interface
input [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_rdata;
input [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_rdata;
output [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_raddr;
output [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_waddr;
output dbgq_hi_csn_wr;
output dbgq_hi_csn_rd;
output [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_wdata;
output [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_raddr;
output [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_waddr;
output dbgq_lo_csn_wr;
output dbgq_lo_csn_rd;
output [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_wdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire dbg_req_transparent;
wire dbg_req_arbitrate;
wire dbg_req_priority;
wire [127:0] dbg_data;
wire [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_raddr;
wire [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_hi_waddr;
wire dbgq_hi_csn_wr;
wire dbgq_hi_csn_rd;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_hi_wdata;
wire [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_raddr;
wire [`JBI_DBGQ_ADDR_WIDTH-1:0] dbgq_lo_waddr;
wire dbgq_lo_csn_wr;
wire dbgq_lo_csn_rd;
wire [`JBI_DBGQ_WIDTH-1:0] dbgq_lo_wdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] tstamp_lo;
wire [`JBI_DBG_TSTAMP_WIDTH-`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] tstamp_hi;
wire alternate_hi;
wire dbgq_drain;
wire [9:0] max_wait_cnt;
reg [`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] next_tstamp_lo;
reg [`JBI_DBG_TSTAMP_WIDTH-`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] next_tstamp_hi;
reg next_alternate_hi;
wire next_dbgq_drain;
wire [9:0] next_max_wait_cnt;
wire max_wait_cnt_rst_l;
wire max_wait_cnt_en;
wire dbgq_drain_rst_l;
wire alternate_hi_set_l;
wire exceed_max_wait;
wire dbgq_hi_empty;
wire dbgq_lo_empty;
wire dbgq_hi_full;
wire dbgq_lo_full;
wire [63:0] dbg_hi_data;
wire [63:0] dbg_lo_data;
wire dbgq_hi_push;
wire dbgq_lo_push;
wire dbgq_hi_overflow;
wire dbgq_lo_overflow;
wire dbgq_hi_prev_overflow;
wire dbgq_lo_prev_overflow;
wire [`JBI_DBGQ_ADDR_WIDTH:0] dbgq_hi_level;
wire [`JBI_DBGQ_ADDR_WIDTH:0] dbgq_lo_level;
wire dbgq_empty;
wire dbgq_exceed_lo_water;
wire dbgq_exceed_hi_water;
wire iob_jbi_dbg_hi_vld_ff;
wire [47:0] iob_jbi_dbg_hi_data_ff;
wire iob_jbi_dbg_lo_vld_ff;
wire [47:0] iob_jbi_dbg_lo_data_ff;
wire [`JBI_DBG_TSTAMP_WIDTH-1:0] tstamp;
//
// Code start here
//
//*******************************************************************************
// Basic Queue Control Block Instanstiations
//*******************************************************************************
/* jbi_dbg_ctl_qctl AUTO_TEMPLATE (
.\(.*\) (dbgq_hi_\1),
.clk (clk),
.rst_l (rst_l),
.pop (mout_dbg_pop),
); */
jbi_dbg_ctl_qctl u_hi_qctl (/*AUTOINST*/
// Outputs
.prev_overflow(dbgq_hi_prev_overflow), // Templated
.empty (dbgq_hi_empty), // Templated
.full (dbgq_hi_full), // Templated
.level (dbgq_hi_level), // Templated
.waddr (dbgq_hi_waddr), // Templated
.raddr (dbgq_hi_raddr), // Templated
// Inputs
.clk (clk), // Templated
.rst_l (rst_l), // Templated
.pop (mout_dbg_pop), // Templated
.push (dbgq_hi_push), // Templated
.overflow (dbgq_hi_overflow)); // Templated
/* jbi_dbg_ctl_qctl AUTO_TEMPLATE (
.\(.*\) (dbgq_lo_\1),
.clk (clk),
.rst_l (rst_l),
.pop (mout_dbg_pop),
); */
jbi_dbg_ctl_qctl u_lo_qctl (/*AUTOINST*/
// Outputs
.prev_overflow(dbgq_lo_prev_overflow), // Templated
.empty (dbgq_lo_empty), // Templated
.full (dbgq_lo_full), // Templated
.level (dbgq_lo_level), // Templated
.waddr (dbgq_lo_waddr), // Templated
.raddr (dbgq_lo_raddr), // Templated
// Inputs
.clk (clk), // Templated
.rst_l (rst_l), // Templated
.pop (mout_dbg_pop), // Templated
.push (dbgq_lo_push), // Templated
.overflow (dbgq_lo_overflow)); // Templated
//*******************************************************************************
// Timestamp
//*******************************************************************************
always @ ( /*AUTOSENSE*/csr_jbi_debug_arb_tstamp_wrap or tstamp_hi
or tstamp_lo) begin
if (tstamp_lo == csr_jbi_debug_arb_tstamp_wrap) begin
next_tstamp_lo = {`JBI_CSR_DBG_TSWRAP_WIDTH{1'b0}};
next_tstamp_hi = tstamp_hi + 1'b1;
end
else begin
next_tstamp_lo = tstamp_lo + 1'b1;
next_tstamp_hi = tstamp_hi;
end
end
assign tstamp = {tstamp_hi, tstamp_lo};
//*******************************************************************************
// Push Data into DBGQ
//*******************************************************************************
//-----------------------
// Alternate Mode
// - assume simultaneous hi_vld & lo_vld assertion in alternate mode
//-----------------------
assign alternate_hi_set_l = rst_l & csr_jbi_debug_arb_alternate_set_l;
always @ ( /*AUTOSENSE*/alternate_hi or csr_jbi_debug_arb_alternate
or iob_jbi_dbg_hi_vld_ff) begin
if (csr_jbi_debug_arb_alternate & iob_jbi_dbg_hi_vld_ff)
next_alternate_hi = ~alternate_hi;
else
next_alternate_hi = alternate_hi;
end
//-----------------------
// Hi Queue
//-----------------------
// Drop data if dbgq is full
assign dbgq_hi_push = iob_jbi_dbg_hi_vld_ff
& (~csr_jbi_debug_arb_alternate | alternate_hi)
& ~dbgq_hi_full;
assign dbgq_hi_csn_wr = ~dbgq_hi_push;
assign dbgq_hi_csn_rd = (dbgq_hi_waddr == dbgq_hi_raddr) & ~dbgq_hi_full;
assign dbgq_hi_overflow = iob_jbi_dbg_hi_vld_ff
& (~csr_jbi_debug_arb_alternate | alternate_hi)
& dbgq_hi_full;
assign dbgq_hi_wdata[`JBI_DBGQ_D_HI:`JBI_DBGQ_D_LO] = iob_jbi_dbg_hi_data_ff[47:0];
assign dbgq_hi_wdata[`JBI_DBGQ_TSTMP_HI:`JBI_DBGQ_TSTMP_LO] = tstamp;
assign dbgq_hi_wdata[`JBI_DBGQ_DR] = dbgq_hi_prev_overflow;
//-----------------------
// Lo Queue
//-----------------------
// Drop data if dbgq is full
assign dbgq_lo_push = iob_jbi_dbg_lo_vld_ff
& (~csr_jbi_debug_arb_alternate | ~alternate_hi)
& ~dbgq_lo_full;
assign dbgq_lo_csn_wr = ~dbgq_lo_push;
assign dbgq_lo_csn_rd = (dbgq_lo_waddr == dbgq_lo_raddr) & ~dbgq_lo_full;
assign dbgq_lo_overflow = iob_jbi_dbg_lo_vld_ff
& (~csr_jbi_debug_arb_alternate | ~alternate_hi)
& dbgq_lo_full;
assign dbgq_lo_wdata[`JBI_DBGQ_D_HI:`JBI_DBGQ_D_LO] = iob_jbi_dbg_lo_data_ff[47:0];
assign dbgq_lo_wdata[`JBI_DBGQ_TSTMP_HI:`JBI_DBGQ_TSTMP_LO] = tstamp;
assign dbgq_lo_wdata[`JBI_DBGQ_DR] = dbgq_lo_prev_overflow;
//*******************************************************************************
// Pop DBGQ
//*******************************************************************************
assign dbgq_empty = dbgq_hi_empty & dbgq_lo_empty;
assign dbgq_exceed_lo_water = dbgq_hi_level > {1'b0, csr_jbi_debug_arb_lo_water}
| dbgq_lo_level > {1'b0, csr_jbi_debug_arb_lo_water};
assign dbgq_exceed_hi_water = dbgq_hi_level > {1'b0, csr_jbi_debug_arb_hi_water}
| dbgq_lo_level > {1'b0, csr_jbi_debug_arb_hi_water};
// Max Wait Count
assign max_wait_cnt_rst_l = rst_l & ~dbgq_drain;
assign max_wait_cnt_en = ~dbgq_drain & ~dbgq_empty;
assign next_max_wait_cnt[9:0] = max_wait_cnt[9:0] + 1'b1;
assign exceed_max_wait = max_wait_cnt == csr_jbi_debug_arb_max_wait[9:0];
// When exceed max wait, drain entire queue before waiting again
assign dbgq_drain_rst_l = rst_l & ~(dbgq_drain & dbgq_empty);
assign next_dbgq_drain = dbgq_drain | exceed_max_wait;
// dbg_req_* are 1-hot
assign dbg_req_transparent = ~dbgq_empty
& ~dbgq_drain
& ( ~csr_jbi_debug_arb_data_arb
| ~dbgq_exceed_lo_water);
assign dbg_req_arbitrate = ~dbgq_empty
& csr_jbi_debug_arb_data_arb
& dbgq_exceed_lo_water
& ~dbgq_exceed_hi_water
& ~dbgq_drain;
assign dbg_req_priority = ~dbgq_empty
& ( (csr_jbi_debug_arb_data_arb & dbgq_exceed_hi_water)
| dbgq_drain);
// Format Data
assign dbg_hi_data = { {4{1'b0}},
dbgq_hi_rdata[`JBI_DBGQ_DR],
~dbgq_hi_empty,
dbgq_hi_rdata[`JBI_DBGQ_TSTMP_HI:`JBI_DBGQ_TSTMP_LO],
dbgq_hi_rdata[`JBI_DBGQ_D_HI:`JBI_DBGQ_D_LO] };
assign dbg_lo_data = { {4{1'b0}},
dbgq_lo_rdata[`JBI_DBGQ_DR],
~dbgq_lo_empty,
dbgq_lo_rdata[`JBI_DBGQ_TSTMP_HI:`JBI_DBGQ_TSTMP_LO],
dbgq_lo_rdata[`JBI_DBGQ_D_HI:`JBI_DBGQ_D_LO] };
assign dbg_data = { (dbg_hi_data & {64{~dbgq_hi_empty}}), // drive zeros if queue is empty
(dbg_lo_data & {64{~dbgq_lo_empty}}) };
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(48) u_dff_iob_jbi_dbg_hi_data_ff
(.din(iob_jbi_dbg_hi_data),
.clk(clk),
.q(iob_jbi_dbg_hi_data_ff)
);
dff_ns #(48) u_dff_iob_jbi_dbg_lo_data_ff
(.din(iob_jbi_dbg_lo_data),
.clk(clk),
.q(iob_jbi_dbg_lo_data_ff)
);
//*******************************************************************************
// DFFR Instantiations
//*******************************************************************************
dffrl_ns #(1) u_dffrl_dbgq_drain
(.din(next_dbgq_drain),
.clk(clk),
.rst_l(dbgq_drain_rst_l),
.q(dbgq_drain)
);
dffrl_ns #(1) u_dffrl_iob_jbi_dbg_hi_vld_ff
(.din(iob_jbi_dbg_hi_vld),
.clk(clk),
.rst_l(rst_l),
.q(iob_jbi_dbg_hi_vld_ff)
);
dffrl_ns #(1) u_dffrl_iob_jbi_dbg_lo_vld_ff
(.din(iob_jbi_dbg_lo_vld),
.clk(clk),
.rst_l(rst_l),
.q(iob_jbi_dbg_lo_vld_ff)
);
dffrl_ns #(`JBI_CSR_DBG_TSWRAP_WIDTH) u_dffrl_tstamp_lo
(.din(next_tstamp_lo),
.clk(clk),
.rst_l(dbg_rst_l),
.q(tstamp_lo)
);
dffrl_ns #(`JBI_DBG_TSTAMP_WIDTH-`JBI_CSR_DBG_TSWRAP_WIDTH) u_dffrl_tstamp_hi
(.din(next_tstamp_hi),
.clk(clk),
.rst_l(dbg_rst_l),
.q(tstamp_hi)
);
//*******************************************************************************
// DFFSL Instantiations
//*******************************************************************************
dffsl_ns #(1) u_dffrl_alternate_hi
(.din(next_alternate_hi),
.clk(clk),
.set_l(alternate_hi_set_l),
.q(alternate_hi)
);
//*******************************************************************************
// DFFRLE Instantiations
//*******************************************************************************
dffrle_ns #(10) u_dffrle_max_wait_cnt
(.din(next_max_wait_cnt),
.clk(clk),
.en(max_wait_cnt_en),
.rst_l(max_wait_cnt_rst_l),
.q(max_wait_cnt)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
always @ ( /*AUTOSENSE*/csr_jbi_debug_arb_alternate
or iob_jbi_dbg_hi_vld_ff or iob_jbi_dbg_lo_vld_ff) begin
@clk;
if (csr_jbi_debug_arb_alternate
& (iob_jbi_dbg_hi_vld_ff ^ iob_jbi_dbg_lo_vld_ff))
$dispmon ("jbi_dbg_ctl", 49, "%d %m: ERROR - DEBUG ALTERNATE MODE ON and iob_jbi_dbg_hi_vld!=iob_jbi_dbg_lo_vld",
$time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Sim only
module logger(
input CLK_6MB,
input nBNKB,
input SHADOW,
input COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2
);
wire [6:0] LOG_VIDEO_R;
wire [6:0] LOG_VIDEO_G;
wire [6:0] LOG_VIDEO_B;
reg [5:0] MARQUEE;
reg [7:0] LED1;
reg [7:0] LED2;
integer sim_line;
integer sim_frame;
integer i;
integer f_video;
integer f_cab_io;
integer f_ram;
initial
begin
sim_line = 0;
sim_frame = 0;
f_video = $fopen("log_video.txt", "w");
f_cab_io = $fopen("log_cab_io.txt", "w");
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
#500000000 // Run for 500ms
// Save backup RAM contents
f_ram = $fopen("raminit_sram_l.txt", "w");
for (i = 0; i < 32768; i = i + 1)
$fwrite (f_ram, "%x\n", neogeo.SRAM.SRAML.RAMDATA[i]);
$fclose(f_ram);
f_ram = $fopen("raminit_sram_u.txt", "w");
for (i = 0; i < 32768; i = i + 1)
$fwrite (f_ram, "%x\n", neogeo.SRAM.SRAMU.RAMDATA[i]);
$fclose(f_ram);
// Save memory card contents
f_ram = $fopen("raminit_memcard.txt", "w");
for (i = 0; i < 2048; i = i + 1)
$fwrite (f_ram, "%x\n", testbench_1.MC.RAMDATA[i]);
$fclose(f_ram);
$fclose(f_video);
$fclose(f_cab_io);
$stop;
end
// Simulates MV-ELA board
always @(negedge neogeo.LED_LATCH[0])
MARQUEE <= neogeo.LED_DATA[5:0];
// Simulates MV-LED boards
always @(negedge neogeo.LED_LATCH[1])
LED1 <= neogeo.LED_DATA;
always @(negedge neogeo.LED_LATCH[2])
LED2 <= neogeo.LED_DATA;
assign LOG_VIDEO_R = nBNKB ? {~SHADOW, neogeo.PC[11:8], neogeo.PC[14], neogeo.PC[15]} : 7'b0000000;
assign LOG_VIDEO_G = nBNKB ? {~SHADOW, neogeo.PC[7:4], neogeo.PC[13], neogeo.PC[15]} : 7'b0000000;
assign LOG_VIDEO_B = nBNKB ? {~SHADOW, neogeo.PC[3:0], neogeo.PC[12], neogeo.PC[15]} : 7'b0000000;
always @(posedge CLK_6MB)
begin
// Write each pixel
// 0RRRRRRR 0GGGGGGG 0BBBBBBB
$fwrite(f_video, "%06X ", {1'b0, LOG_VIDEO_R, 1'b0, LOG_VIDEO_G, 1'b0, LOG_VIDEO_B});
if (neogeo.LSPC2.VS.PIXELC == 9'h0F0)
begin
$fwrite(f_video, "YYYYYY ");
// $display("Line %d rendered", sim_line);
if (neogeo.LSPC2.VS.RASTERC == 9'd263)
begin
sim_line = 0;
$display("Frame %d rendered", sim_frame);
// Write cab I/O data each frame
// 000000MM MMMMCCKK LLLLLLLL llllllll
$fwrite(f_cab_io, "%08X ", {MARQUEE, COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2, LED2, LED1});
sim_frame = sim_frame + 1;
end
else
sim_line = sim_line + 1;
end
end
endmodule
|
`timescale 1ns / 1ps
module tb_fmrv32im_core;
reg sim_end;
reg RST_N;
reg CLK;
reg [31:0] INTERRUPT;
// Write Address Channel
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
// Write Data Channel
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
// Write Response Channel
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
// Read Address Channel
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
// Read Data Channel
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
// --------------------------------------------------
// AXI4 Interface(Master)
// --------------------------------------------------
// Master Write Address
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
// Master Write Data
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
// Master Write Response
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
// Master Read Address
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
// Master Read Data
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
INTERRUPT = 0;
#100;
@(posedge CLK);
RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_core.dbus_wdata;
end
end
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
fmrv32im_core
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
// ------------------------------------------------------------
// Master Write Address
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
// Master Write Data
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
// Master Write Response
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
// Master Read Address
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
// Master Read Data
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
// ------------------------------------------------------------
// Write Address Channel
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
// Write Data Channel
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
// Write Response Channel
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
// Read Address Channel
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
// Read Data Channel
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
tb_axi_slave_model u_axi_slave
(
// Reset, Clock
.ARESETN ( RST_N ),
.ACLK ( CLK ),
// Master Write Address
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
// Master Write Data
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
// Master Write Response
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
// Master Read Address
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
// .M_AXI_ARLOCK(),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
// Master Read Data
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
tb_axil_slave_model u_axil_slave
(
// Reset, Clock
.ARESETN ( RST_N ),
.ACLK ( CLK ),
// Master Write Address
.M_AXI_AWADDR ( IM_AXI_AWADDR ),
.M_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.M_AXI_AWPROT ( IM_AXI_AWPROT ),
.M_AXI_AWVALID ( IM_AXI_AWVALID ),
.M_AXI_AWREADY ( IM_AXI_AWREADY ),
// Master Write Data
.M_AXI_WDATA ( IM_AXI_WDATA ),
.M_AXI_WSTRB ( IM_AXI_WSTRB ),
.M_AXI_WVALID ( IM_AXI_WVALID ),
.M_AXI_WREADY ( IM_AXI_WREADY ),
// Master Write Response
.M_AXI_BRESP ( IM_AXI_BRESP ),
.M_AXI_BVALID ( IM_AXI_BVALID ),
.M_AXI_BREADY ( IM_AXI_BREADY ),
// Master Read Address
.M_AXI_ARADDR ( IM_AXI_ARADDR ),
.M_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.M_AXI_ARPROT ( IM_AXI_ARPROT ),
.M_AXI_ARVALID ( IM_AXI_ARVALID ),
.M_AXI_ARREADY ( IM_AXI_ARREADY ),
// Master Read Data
.M_AXI_RDATA ( IM_AXI_RDATA ),
.M_AXI_RRESP ( IM_AXI_RRESP ),
.M_AXI_RVALID ( IM_AXI_RVALID ),
.M_AXI_RREADY ( IM_AXI_RREADY )
);
endmodule // tb_fmrv32im_core
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Implements a 16-bit instruction decoder. The 16-bit instruction set is --
// -- not logically organized so as to save on encoding and thus the code --
// -- seem a bit complex. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_thumb_decoder_main (
// Clock and reset.
input wire i_clk,
input wire i_reset,
// Code stall.
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_stall_from_issue,
input wire i_stall_from_decode,
input wire i_clear_from_decode,
// Predictor status.
input wire [1:0] i_taken,
// Input from I-cache.
// Instruction and valid qualifier.
input wire [31:0] i_instruction,
input wire i_instruction_valid,
// Interrupts. Active high level sensitive signals.
input wire i_irq,
input wire i_fiq,
// Aborts.
input wire i_iabort,
output reg o_iabort,
// Ensure compressed mode is active (T bit).
input wire i_cpsr_ff_t,
// Program counter.
input wire [31:0] i_pc_ff,
input wire [31:0] i_pc_plus_8_ff,
//
// Outputs to the ARM decoder.
//
// Instruction, valid, undefined by this decoder and force 32-bit
// align signals (requires memory to keep lower 2 bits as 00).
output reg [34:0] o_instruction,
output reg o_instruction_valid,
output reg o_und,
output reg o_force32_align,
// PCs.
output reg [31:0] o_pc_ff,
output reg [31:0] o_pc_plus_8_ff,
// Interrupt status output.
output reg o_irq,
output reg o_fiq,
// Taken
output reg [1:0] o_taken_ff
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
wire [34:0] instruction_nxt;
wire instruction_valid_nxt;
wire und_nxt;
wire force32_nxt;
wire irq_nxt;
wire fiq_nxt;
reg [1:0] taken_nxt;
zap_thumb_decoder u_zap_thumb_decoder (
.i_instruction(i_instruction),
.i_instruction_valid(i_instruction_valid),
.i_irq(i_irq),
.i_fiq(i_fiq),
.i_offset(o_instruction[11:0]),
.i_cpsr_ff_t(i_cpsr_ff_t),
.o_instruction(instruction_nxt),
.o_instruction_valid(instruction_valid_nxt),
.o_und(und_nxt),
.o_force32_align(force32_nxt),
.o_irq(irq_nxt),
.o_fiq(fiq_nxt)
);
always @ (posedge i_clk)
begin
if ( i_reset )
begin
reset;
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_clear_from_writeback )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_data_stall )
begin
end
else if ( i_clear_from_alu )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_stall_from_shifter ) begin end
else if ( i_stall_from_issue ) begin end
else if ( i_stall_from_decode ) begin end
else if ( i_clear_from_decode )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else // BUG FIX.
begin
o_iabort <= i_iabort;
o_instruction_valid <= instruction_valid_nxt;
o_instruction <= instruction_nxt;
o_und <= und_nxt;
o_force32_align <= force32_nxt;
o_pc_ff <= i_pc_ff;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_irq <= irq_nxt;
o_fiq <= fiq_nxt;
o_taken_ff <= i_taken;
end
end
task reset;
begin
o_iabort <= 0;
o_instruction_valid <= 0;
o_instruction <= 0;
o_und <= 0;
o_force32_align <= 0;
o_pc_ff <= 0;
o_pc_plus_8_ff <= 0;
o_irq <= 0;
o_fiq <= 0;
o_taken_ff <= 0;
end
endtask
// Helpful for debug.
zap_decompile u_zap_decompile (
.i_instruction ({1'd0, o_instruction}),
.i_dav (o_instruction_valid),
.o_decompile ()
);
endmodule // zap_thumb_decoder_main
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_cud_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_cud_rom.dat", ram0);
$readmemh("./Loop_loop_height_cud_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_cud(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_cud_rom Loop_loop_height_cud_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_FUNCTIONAL_V |
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: disk02.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module disk02 (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: PRIVATE: MIFfilename STRING "disk_02.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "disk_02.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**************************************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/**************************************************************************************************/
`default_nettype none
`include "define.v"
/***** Sorter Cell *****/
/**************************************************************************************************/
module SCELL(input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [`SORTW-1:0] din1,
input wire [`SORTW-1:0] din2,
input wire full,
output wire [`SORTW-1:0] dout,
output wire enq);
wire cmp1 = (din1 < din2);
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign enq = (!full && valid1 && valid2);
assign deq1 = (enq && cmp1);
assign deq2 = (enq && !cmp1);
assign dout = mux(din2, din1, cmp1);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire [`SORTW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den; // (!im_full && den);
wire im_deq = (req && !im_emp);
always @(posedge CLK) im_req <= (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`SORTW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [3:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[31:0], dot[31:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==15)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==14)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {32'b0, dot_t[`DRAMW-1:32]};
2'b11: dot_t <= {32'b0, dot[`DRAMW-1:32]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`SORTW-1:0] din, // data in
output wire [`SORTW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORTW-1:0] mux32;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
/*****************************************/
wire [`SORTW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`SORTW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux32(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 1;
if (ecnt==1 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`SORTW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`SORTW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`SORTW-1:0] d00, d01, d02, d03;
assign {d00, d01, d02, d03} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [31:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [31:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [31:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [31:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [31:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [31:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [31:0] F07_din, F07_dot; wire [1:0] F07_cnt;
INBUF IN04(CLK, RST, full[0], F04_full, F04_enq, d00, F04_din, enq[0], phase, irst);
INBUF IN05(CLK, RST, full[1], F05_full, F05_enq, d01, F05_din, enq[1], phase, irst);
INBUF IN06(CLK, RST, full[2], F06_full, F06_enq, d02, F06_din, enq[2], phase, irst);
INBUF IN07(CLK, RST, full[3], F07_full, F07_enq, d03, F07_din, enq[3], phase, irst);
MRE2 #(1,32) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1,32) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1,32) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1,32) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1,32) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1,32) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1,32) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
SCELL S01(!F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL S02(!F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL S03(!F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`SORTW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [3:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:32]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 15);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire [`SRTP_WAY:0] DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg [`SRTP_WAY:0] DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg [`SRTP_WAY:0] DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg [`SRTP_WAY:0] pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester A for data
reg [`SRTP_WAY:0] pcB; // pipeline regester A for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester A for data
reg [`SRTP_WAY:0] pcC; // pipeline regester A for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester A for data
reg [`SRTP_WAY:0] pcD; // pipeline regester A for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester A for data
reg [`SRTP_WAY:0] pcE; // pipeline regester A for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester A for data
reg [`SRTP_WAY:0] pcF; // pipeline regester A for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester A for data
reg [`SRTP_WAY:0] pcG; // pipeline regester A for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester A for data
reg [`SRTP_WAY:0] pcH; // pipeline regester A for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester A for data
reg [`SRTP_WAY:0] pcI; // pipeline regester A for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/***** dummy logic *****/
/**************************************************************************************************/
module CORE_W(input wire CLK, // clock
input wire RST_in, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy_in, // DRAM busy
input wire [1:0] d_mode_in, // DRAM mode
input wire din_bit, // DRAM data out
input wire din_en_in, // DRAM data out enable
output reg [3:0] data_out, // DRAM data in
input wire d_w_in, // DRAM write flag
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output wire ERROR); //
reg RST; always @(posedge CLK) RST <= RST_in;
wire initdone_w; always @(posedge CLK) initdone <= initdone_w;
wire sortdone_w; always @(posedge CLK) sortdone <= sortdone_w;
reg d_busy; always @(posedge CLK) d_busy <= d_busy_in;
reg [1:0] d_mode; always @(posedge CLK) d_mode <= d_mode_in;
reg [`DRAMW-1:0] din; always @(posedge CLK) din <= (RST) ? 0 : {din[`DRAMW-2:0], din_bit};
reg din_en; always @(posedge CLK) din_en <= din_en_in;
wire [1:0] d_req_w; always @(posedge CLK) d_req <= d_req_w;
wire dout_en;
wire [`DRAMW-1:0] dout;
reg [`DRAMW-1:0] dout_r;
always @(posedge CLK) dout_r <= dout;
reg d_w; always @(posedge CLK) d_w <= d_w_in;
always @(posedge CLK) data_out <= {^dout_r[127:0], ^dout_r[128+127:128],
^dout_r[256+127:256], ^dout_r[384+127:384]};
wire [31:0] d_initadr_w, d_blocks_w;
always @(posedge CLK) d_initadr <= d_initadr_w;
always @(posedge CLK) d_blocks <= d_blocks_w;
CORE core(CLK, RST, initdone_w, sortdone_w,
d_busy, dout, d_w, din, din_en, d_req_w, d_initadr_w, d_blocks_w, ERROR);
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output reg ERROR); // Sorting value ERROR ?
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [256-1:0] mux256;
input [256-1:0] a;
input [256-1:0] b;
input sel;
begin
case (sel)
1'b0: mux256 = a;
1'b1: mux256 = b;
endcase
end
endfunction
function [255:0] mux2in256;
input [255:0] a;
input [255:0] b;
input [1:0] sel;
begin
case (sel)
2'b01: mux2in256 = a;
2'b10: mux2in256 = b;
endcase
end
endfunction
/**********************************************************************************************/
reg idone_a;
reg idone_b;
wire [`DRAMW-1:0] OB_dot0;
wire [`DRAMW-1:0] OB_dot1;
wire OB_req_a;
wire OB_req_b;
wire OB_full0;
wire OB_full1;
wire [`PHASE_W] l_phase = `LAST_PHASE;
reg [`DRAMW-1:0] dout_t;
reg [`DRAMW-1:0] dout_tta, dout_ttb;
reg [`DRAMW-1:0] dout_t0_a;
reg [`DRAMW-1:0] dout_t0_b;
reg doen_t;
reg doen_tta, doen_ttb;
reg doen_t0_a;
reg doen_t0_b;
reg [`SORT_WAY-1:0] req_tt0_a, req_tt1_a;
reg [`SORT_WAY-1:0] req_tt0_b, req_tt1_b;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg req_gga, req_ggb;
reg req_ga, req_gb;
reg [`SORT_WAY-1:0] req_a, req_b;
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [31:0] elem; // sorted elements in a phase
reg [31:0] elem_a;
reg [31:0] elem_b;
reg [`PHASE_W] phase; //
reg [`PHASE_W] phase_a;
reg [`PHASE_W] phase_b;
reg last_phase;
reg pchange_a;
reg pchange_b;
reg iter_done_a;
reg iter_done_b;
reg [31:0] ecnt; // sorted elements in an iteration
reg [31:0] ecnt_a;
reg [31:0] ecnt_b;
reg irst_a;
reg irst_b;
reg frst_a;
reg frst_b;
reg pexe_done_a;
reg pexe_done_b;
reg pexe_done_a_p;
reg pexe_done_b_p;
reg RSTa;
always @(posedge CLK) RSTa <= RST_IN;
reg RSTb;
always @(posedge CLK) RSTb <= RST_IN;
/**********************************************************************************************/
wire [`SORTW-1:0] d00_0, d01_0, d02_0, d03_0;
wire [`SORTW-1:0] d00_1, d01_1, d02_1, d03_1;
wire ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a;
wire ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b;
wire F01_emp0;
wire F01_emp1;
wire F01_deq0 = !F01_emp0 && !OB_full0;
wire F01_deq1 = !F01_emp1 && !OB_full1;
wire [`SORTW-1:0] F01_dot0;
wire [`SORTW-1:0] F01_dot1;
wire [`SORTW*`SORT_WAY-1:0] s_din0 = {d00_0, d01_0, d02_0, d03_0};
wire [`SORTW*`SORT_WAY-1:0] s_din1 = {d00_1, d01_1, d02_1, d03_1};
wire [`SORT_WAY-1:0] enq0;
wire [`SORT_WAY-1:0] enq1;
wire [`SORT_WAY-1:0] s_ful0;
wire [`SORT_WAY-1:0] s_ful1;
wire [`DRAMW-1:0] stnet_dout;
wire [`SRTP_WAY:0] stnet_douten;
SORTINGNETWORK sortingnetwork(CLK,
RSTa,
{req_tb, req_ta, doen_t},
dout_t,
stnet_dout,
stnet_douten);
INMOD2 im00_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[0], s_ful0[0], d00_0, enq0[0], ib00_req_a);
INMOD2 im01_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[1], s_ful0[1], d01_0, enq0[1], ib01_req_a);
INMOD2 im02_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[2], s_ful0[2], d02_0, enq0[2], ib02_req_a);
INMOD2 im03_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[3], s_ful0[3], d03_0, enq0[3], ib03_req_a);
INMOD2 im00_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[0], s_ful1[0], d00_1, enq1[0], ib00_req_b);
INMOD2 im01_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[1], s_ful1[1], d01_1, enq1[1], ib01_req_b);
INMOD2 im02_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[2], s_ful1[2], d02_1, enq1[2], ib02_req_b);
INMOD2 im03_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[3], s_ful1[3], d03_1, enq1[3], ib03_req_b);
STREE stree0(CLK, RSTa, irst_a, frst_a, phase_a, s_din0, enq0, s_ful0, F01_deq0, F01_dot0, F01_emp0);
STREE stree1(CLK, RSTb, irst_b, frst_b, phase_b, s_din1, enq1, s_ful1, F01_deq1, F01_dot1, F01_emp1);
reg OB_deq_ta;
reg OB_deq_tb;
wire [1:0] OB_dot_sel ={OB_deq_tb, OB_deq_ta};
wire OB_deq0 = idone_a && d_w && OB_deq_ta;
wire OB_deq1 = idone_b && d_w && OB_deq_tb;
OTMOD ob0(CLK, RSTa, F01_deq0, F01_dot0, OB_deq0, OB_dot0, OB_full0, OB_req_a);
OTMOD ob1(CLK, RSTb, F01_deq1, F01_dot1, OB_deq1, OB_dot1, OB_full1, OB_req_b);
/********************************** Error Check ***********************************************/
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
reg [`SORTW-1:0] check_cnt;
always @(posedge CLK) begin
if (RSTa) begin check_cnt<=1; ERROR<=0; end
if (last_phase && F01_deq0) begin
if (check_cnt != F01_dot0) begin
ERROR <= 1;
$write("Error in core.v: %d %d\n", F01_dot0, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt <= check_cnt + 1;
end
end
end else if (`INITTYPE != "xorshift") begin
always @(posedge CLK) begin
ERROR <= 1;
// for simulation
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.v\n");
$finish();
end
end
endgenerate
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [31:0] w_addr_a; //
reg [31:0] w_addr_b; //
reg [2:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b;
reg c_a, c_b, c_c, c_d;
reg c_a_a, c_b_a, c_c_a, c_d_a;
reg c_a_b, c_b_b, c_c_b, c_d_b;
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b) begin
if (RSTa) {initdone, state} <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) {req_a, req_b} <= 0;
if (RSTa) {req_ga, req_gb} <= 0;
if (RSTa) {req_gga, req_ggb} <= 0;
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, l_phase[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
{cnt_a, cnt_b, cnt_c, cnt_d} <= 0;
{c_a, c_b, c_c, c_d} <= 0;
if ((RSTa || pchange_a) && !pexe_done_a_p) begin
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a} <= 0;
OB_deq_ta <= 0;
end
if ((RSTa || pchange_b) && !pexe_done_b_p) begin
w_addr_b <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b} <= 0;
OB_deq_tb <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= (`SORT_ELM>>4); // 16word/block for VC707, 2word/b for Tokuden
d_initadr <= 0; //
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
initdone <= 1;
OB_deq_ta <= 0;
OB_deq_tb <= 0;
case (last_phase)
1'b0: begin
if (ib00_req_a && !c_a_a) begin req_a <= 4'h1; req_gga <= 1; end //
else if (ib01_req_a && !c_b_a) begin req_a <= 4'h2; req_gga <= 1; end //
else if (ib02_req_a && !c_c_a) begin req_a <= 4'h4; req_gga <= 1; end //
else if (ib03_req_a && !c_d_a) begin req_a <= 4'h8; req_gga <= 1; end //
if (ib00_req_b && !c_a_b) begin req_b <= 4'h1; req_ggb <= 1; end //
else if (ib01_req_b && !c_b_b) begin req_b <= 4'h2; req_ggb <= 1; end //
else if (ib02_req_b && !c_c_b) begin req_b <= 4'h4; req_ggb <= 1; end //
else if (ib03_req_b && !c_d_b) begin req_b <= 4'h8; req_ggb <= 1; end //
state <= 2;
end
1'b1: begin
if (ib00_req_a && !c_a) begin req<=4'h1; state<=3; end //
else if (ib01_req_a && !c_b) begin req<=4'h2; state<=3; end //
else if (ib02_req_a && !c_c) begin req<=4'h4; state<=3; end //
else if (ib03_req_a && !c_d) begin req<=4'h8; state<=3; end //
else if (OB_req_a) begin OB_deq_ta <= 1; state<=4; end // WRITE
end
endcase
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (req_gga) begin req_ga <= 1; req_b <= 0; state <= 3; end
else if (req_ggb) begin req_gb <= 1; req_a <= 0; state <= 3; end
else if (OB_req_a) begin OB_deq_ta <= 1; state <= 4; end // WRITE
else if (OB_req_b) begin OB_deq_tb <= 1; state <= 5; end // WRITE
else state <= 1;
{req_gga, req_ggb} <= 0;
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin
d_req <= 0;
state <= 1;
{req_ga, req_gb} <= 0;
end else if (!d_busy) begin
case (last_phase)
1'b0: begin
req_ta <= req_a;
case ({req_gb, req_ga})
2'b01: begin
case (req_a)
4'h1: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= radr_a_a+(`D_RS);
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= radr_b_a+(`D_RS);
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= radr_c_a+(`D_RS);
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= radr_d_a+(`D_RS);
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
end
endcase
end
2'b10: begin
case (req_b)
4'h1: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= radr_a_b+(`D_RS);
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= radr_b_b+(`D_RS);
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= radr_c_b+(`D_RS);
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= radr_d_b+(`D_RS);
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
end
endcase
end
endcase
end
1'b1: begin
req_ta <= req;
case (req)
4'h1: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), l_phase[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), l_phase[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), l_phase[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), l_phase[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
endcase
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_tb <= req_b;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
case (last_phase)
1'b0: begin
d_initadr <= w_addr_a;
w_addr_a <= w_addr_a + (`D_WS);
end
1'b1: begin
d_initadr <= w_addr;
w_addr <= w_addr + (`D_WS);
end
endcase
end
end
////////////////////////////////////////////////////////////////////////////////////////
5: begin ///// WRITE data to DRAM
if(d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
d_initadr <= w_addr_b;
w_addr_b <= w_addr_b + (`D_WS);
end
end
endcase
end
end
/***** WRITE : feed the initial data to be stored to DRAM *****/
/**********************************************************************************************/
reg RST_INI; // reset signal for value initialization module
always @(posedge CLK) RST_INI <= RSTa;
reg [`SORTW-1:0] i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i,i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a;
generate
if (`INITTYPE == "xorshift") begin
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST_INI, d_w, r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST_INI, d_w, r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST_INI, d_w, r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST_INI, d_w, r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST_INI, d_w, r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST_INI, d_w, r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST_INI, d_w, r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST_INI, d_w, r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST_INI, d_w, r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST_INI, d_w, r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST_INI, d_w, r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST_INI, d_w, r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST_INI, d_w, r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST_INI, d_w, r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST_INI, d_w, r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST_INI, d_w, r15);
always @(posedge CLK) begin
i_a <= r00;
i_b <= r01;
i_c <= r02;
i_d <= r03;
i_e <= r04;
i_f <= r05;
i_g <= r06;
i_h <= r07;
i_i <= r08;
i_j <= r09;
i_k <= r10;
i_l <= r11;
i_m <= r12;
i_n <= r13;
i_o <= r14;
i_p <= r15;
end
end else if (`INITTYPE == "reverse") begin
always @(posedge CLK) begin
if (RST_INI) begin
i_a <= `SORT_ELM+16;
i_b <= `SORT_ELM+16-1;
i_c <= `SORT_ELM+16-2;
i_d <= `SORT_ELM+16-3;
i_e <= `SORT_ELM+16-4;
i_f <= `SORT_ELM+16-5;
i_g <= `SORT_ELM+16-6;
i_h <= `SORT_ELM+16-7;
i_i <= `SORT_ELM+16-8;
i_j <= `SORT_ELM+16-9;
i_k <= `SORT_ELM+16-10;
i_l <= `SORT_ELM+16-11;
i_m <= `SORT_ELM+16-12;
i_n <= `SORT_ELM+16-13;
i_o <= `SORT_ELM+16-14;
i_p <= `SORT_ELM+16-15;
end else begin
if (d_w) begin
i_a <= i_a-16;
i_b <= i_b-16;
i_c <= i_c-16;
i_d <= i_d-16;
i_e <= i_e-16;
i_f <= i_f-16;
i_g <= i_g-16;
i_h <= i_h-16;
i_i <= i_i-16;
i_j <= i_j-16;
i_k <= i_k-16;
i_l <= i_l-16;
i_m <= i_m-16;
i_n <= i_n-16;
i_o <= i_o-16;
i_p <= i_p-16;
end
end
end
end else if (`INITTYPE == "sorted") begin
reg ocen;
always @(posedge CLK) begin
if (RST_INI) begin
ocen <= 0;
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
i_e <= 5;
i_f <= 6;
i_g <= 7;
i_h <= 8;
i_i <= 9;
i_j <= 10;
i_k <= 11;
i_l <= 12;
i_m <= 13;
i_n <= 14;
i_o <= 15;
i_p <= 16;
end else begin
if (d_w) begin
ocen <= 1;
i_a <= mux32(i_a, i_a+16, ocen);
i_b <= mux32(i_b, i_b+16, ocen);
i_c <= mux32(i_c, i_c+16, ocen);
i_d <= mux32(i_d, i_d+16, ocen);
i_e <= mux32(i_e, i_e+16, ocen);
i_f <= mux32(i_f, i_f+16, ocen);
i_g <= mux32(i_g, i_g+16, ocen);
i_h <= mux32(i_h, i_h+16, ocen);
i_i <= mux32(i_i, i_i+16, ocen);
i_j <= mux32(i_j, i_j+16, ocen);
i_k <= mux32(i_k, i_k+16, ocen);
i_l <= mux32(i_l, i_l+16, ocen);
i_m <= mux32(i_m, i_m+16, ocen);
i_n <= mux32(i_n, i_n+16, ocen);
i_o <= mux32(i_o, i_o+16, ocen);
i_p <= mux32(i_p, i_p+16, ocen);
end
end
end
end
endgenerate
always @(posedge CLK) idone_a <= initdone;
always @(posedge CLK) idone_b <= initdone;
assign d_din[255: 0] = mux256({i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a},
mux2in256(OB_dot0[255:0], OB_dot1[255:0], OB_dot_sel),
idone_a);
assign d_din[511:256] = mux256({i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i},
mux2in256(OB_dot0[511:256], OB_dot1[511:256], OB_dot_sel),
idone_b);
/**********************************************************************************************/
always @(posedge CLK) begin
dout_t <= d_dout;
doen_t <= d_douten;
// Stage 0
////////////////////////////////////
dout_tta <= stnet_dout;
dout_ttb <= stnet_dout;
doen_tta <= stnet_douten[0];
doen_ttb <= stnet_douten[0];
req_tt0_a <= stnet_douten[`SORT_WAY:1];
req_tt0_b <= stnet_douten[`SORT_WAY*2:`SORT_WAY+1];
// Stage 1
////////////////////////////////////
dout_t0_a <= dout_tta;
dout_t0_b <= dout_tta;
doen_t0_a <= doen_tta;
doen_t0_b <= doen_tta;
req_tt1_a <= req_tt0_a;
req_tt1_b <= req_tt0_b;
end
// for last_phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
last_phase <= 0;
end else begin
if (pexe_done_a && pexe_done_b) last_phase <= 1;
end
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase <= `LAST_PHASE;
end else begin
if (elem==`SORT_ELM) phase <= phase+1;
end
end
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
// for pexe_done
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a <= 0;
end else begin
if (phase_a==`LAST_PHASE) pexe_done_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b <= 0;
end else begin
if (phase_b==`LAST_PHASE) pexe_done_b <= 1;
end
end
// for pexe_done_p
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a_p <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) pexe_done_a_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b_p <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) pexe_done_b_p <= 1;
end
end
// for elem
// ########################################################################### // not deleted
always @(posedge CLK) begin
if (RSTa) begin
elem <= 0;
elem_a <= 0;
end else begin
case (last_phase)
1'b0: begin
case ({OB_deq0, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= elem_a + 16;
endcase
end
1'b1: begin
case ({OB_deq0, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({OB_deq1, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= elem_b + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==2);
always @(posedge CLK) iter_done_b <= (ecnt_b==2);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= mux1(((ecnt_a==2) || pchange_a), (ecnt==2), last_phase);
always @(posedge CLK) irst_b <= (ecnt_b==2) || pchange_b;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= mux1((RSTa || (ecnt_a==2) || (elem_a==`SRTP_ELM)), (ecnt==2), last_phase);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==2) || (elem_b==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq0 && last_phase) ecnt <= ecnt - 1;
end
end
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq0 && !pexe_done_a) ecnt_a <= ecnt_a - 1;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq1 && !pexe_done_b) ecnt_b <= ecnt_b - 1;
end
end
// for sortdone
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
sortdone <= 0;
end else begin
if (phase==(`LAST_PHASE+1)) sortdone <= 1;
end
end
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_spigpioport_2(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
reg T_271;
reg [31:0] GEN_0;
reg T_272;
reg [31:0] GEN_1;
reg T_273;
reg [31:0] GEN_2;
wire T_274;
reg T_278;
reg [31:0] GEN_3;
reg T_279;
reg [31:0] GEN_4;
reg T_280;
reg [31:0] GEN_5;
wire T_281;
reg T_285;
reg [31:0] GEN_6;
reg T_286;
reg [31:0] GEN_7;
reg T_287;
reg [31:0] GEN_8;
wire T_288;
reg T_292;
reg [31:0] GEN_9;
reg T_293;
reg [31:0] GEN_10;
reg T_294;
reg [31:0] GEN_11;
assign io_spi_dq_0_i = T_273;
assign io_spi_dq_1_i = T_280;
assign io_spi_dq_2_i = T_287;
assign io_spi_dq_3_i = T_294;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h1;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h1;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_274;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h1;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_281;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h1;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_288;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h1;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h1;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_274 = ~ io_spi_dq_1_oe;
assign T_281 = ~ io_spi_dq_2_oe;
assign T_288 = ~ io_spi_dq_3_oe;
always @(posedge clock or posedge reset) begin
if(reset) begin
T_271 <= 1'b0;
T_272 <= 1'b0;
T_273 <= 1'b0;
T_278 <= 1'b0;
T_279 <= 1'b0;
T_280 <= 1'b0;
T_285 <= 1'b0;
T_286 <= 1'b0;
T_287 <= 1'b0;
T_292 <= 1'b0;
T_293 <= 1'b0;
T_294 <= 1'b0;
end
else begin
T_271 <= io_pins_dq_0_i_ival;
T_272 <= T_271;
T_273 <= T_272;
T_278 <= io_pins_dq_1_i_ival;
T_279 <= T_278;
T_280 <= T_279;
T_285 <= io_pins_dq_2_i_ival;
T_286 <= T_285;
T_287 <= T_286;
T_292 <= io_pins_dq_3_i_ival;
T_293 <= T_292;
T_294 <= T_293;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
|
// MBT 5-22-16
//
// Given a bit vector, return a one-hot bit vector
// that has the latest/earliest bit selected.
//
// Can combine with bsg_encode_one_hot
// to get typical priority encoder.
//
`include "bsg_defines.v"
module bsg_priority_encode_one_hot_out #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(lo_to_hi_p )
)
(input [width_p-1:0] i
, output [width_p-1:0] o
, output v_o
);
logic [width_p-1:0] scan_lo;
if (width_p == 1)
begin: w1
assign o = i;
assign v_o = i;
end
else
begin: nw1
bsg_scan #(.width_p(width_p)
,.or_p (1)
,.lo_to_hi_p(lo_to_hi_p)
) scan (.i (i)
,.o(scan_lo)
);
// edge detect
if (lo_to_hi_p)
begin : fi1
assign o = scan_lo & { (~scan_lo[width_p-2:0]), 1'b1 };
assign v_o = scan_lo[width_p-1];
end
else
begin : fi1
assign o = scan_lo & { 1'b1, (~scan_lo[width_p-1:1]) };
assign v_o = scan_lo[0];
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_priority_encode_one_hot_out)
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_scbufrep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_scbufrep(/*AUTOARG*/
// Outputs
sctag_scbuf_stdecc_c3, so,
// Inputs
rep_store_data_c2, rclk, si, se
);
output [77:0] sctag_scbuf_stdecc_c3;
output so;
input [77:0] rep_store_data_c2;
input rclk;
input si, se;
dff_s #(78) ff_stdata_c3
(.q (sctag_scbuf_stdecc_c3[77:0]),
.din (rep_store_data_c2[77:0]),
.clk (rclk),
.se (se), .si (), .so ()
) ;
endmodule
|
// $Revision: $ $Date: $
//-----------------------------------------------------------------------------
// (c) Copyright 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------
/*
Module Description:
This module is the output data synchronizer for AXI4 Streaming
output bridge.
The module takes stream coupler FIFO level and output flags (eol, sof),
and compares the flags with the state of control signals from the
Video Timing Generator (VTG). The timing from the Stream Coupler acts as the
master, and the VTG acts as the slave. This module outputs a clock_enable to
halt the VTG when required.
The algorithm for locking is this:
1) VTG reaches start of frame (sof). The FIFO sof is not present,
so the VTG state machines wait for FIFO first pixel. During this
period, the FIFO is continuously read, but is not allowed to underflow.
Therefore the FIFO is basically always empty, and data passes
directly from the input to the output.
2) FIFO sof occurs. VTG state machines start, the FIFO is reset,
and the initialize flag is set.
3) When the initialize flag is set, reading of the FIFO is held off
until a minimum FIFO level is met. This is the hysteresis level, and
insures that slight variances in read vs write timing will not cause
an underflow.
4) Since reading of the FIFO has been delayed, the VTG will reach
the end-of-line (eol) first. The state machines of the TG are held
until the FIFO eol is received. At this point, the TG is in sync
with the output of the FIFO.
During the initialization field, There may be some more pauses in
reading the FIFO depending on the exact timing of the reads, writes
and updating of the level. Whenever this occurs, the TG state
machines will pause at eol until the FIFO output catches up.
5) At the next sof, the TG will be synchronized with the FIFO
output, so the initialize flag will be cleared.
The input and output are synchronized to the sof level with a
small FIFO delay cushion to absorb small timing variations.
The FIFO will be read at the TG rate. It has a small cushion due
to the hysteresis level so it will not underflow or overflow.
------------------------------------------------------------------------------
*/
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module v_axi4s_vid_out_v3_0_out_sync #(
parameter RAM_ADDR_BITS = 10, // default depth = 1024
parameter HYSTERESIS_LEVEL = 16,
parameter VTG_MASTER_SLAVE = 0 //timing mode, 1= VTG master,0= VTG is slave
)
(
input wire video_out_clk, // video clock - Pos.
input wire rst , // video reset
input wire vid_ce, // video clock enable
// FIFO Interface
input wire fifo_sof, // start of frame from FIFO
input wire fifo_eol, // end of line from FIFO
input wire fifo_fid, // field ID from FIFO
input wire [RAM_ADDR_BITS -1:0] fifo_level, // FIFO Level
input wire empty, // FIFO empty flag
input wire rd_error , // FIFO read error flag
input wire wr_error, // FIFO write error flag
output reg read_en, // FIFO read enable control
output reg fifo_rst, // FIFO reset(synced at FIFO)
// VTG Interface
input wire vsync,
input wire hsync,
input wire field_id,
input wire act_vid,
output reg clock_en,
// Locked flag
output reg locked
);
// Wire and register declarations
reg [4:0] state;
reg [4:0] next_state;
reg initialize;
// inferred AXIS signals from VTG timing signals
wire vtg_de; // inferred DE from VTG
reg vtg_sof_2; // inferred Start of Frame from VTG w/2 clk ltncy
reg vtg_eol_2; // inferred End of Line from VTG w/2 clk ltncy
// input, output, and delay registers-- Pass through - no resets reuired
reg de_1; // DE input register |
reg field_id_1; // field_id input register
reg vsync_1; // vsync input register
reg de_2; // DE output register
reg vsync_2; // vsync delay register
reg vert_bp; // SR, reset by DE rising
reg fifo_eol_1; // eol input register
reg fifo_eol_2; // eol delay register
reg fifo_sof_1; // sof input register
reg fifo_sof_2; // sof delay register
reg fifo_fid_1; // Field ID sample register
wire de_rising;
reg de_rising_1;
wire de_falling;
wire vsync_falling;
reg read_ok; // allow FIFO reads
reg force_read; // force FIFO reads
wire hysteresis_timeout;
wire half_full;
reg fifo_eol_2_rising;
reg [RAM_ADDR_BITS -1:0] hyster_count; // Hysteresis counter
reg count_reset; // Hysteresis counter reset
wire vid_data_invalid; // vid data output is invalid
reg pre_clock_en; // state machine output to halt VTC gen.
// Logic Section
assign vtg_de = act_vid;
assign vid_data_invalid = rd_error;
// edge detectors
assign de_rising = de_1 && !de_2;
assign de_falling = !vtg_de && de_1; // falling is 1 state earlier for eol
assign vsync_falling = !vsync_1 && vsync_2;
assign hysteresis_timeout = hyster_count >= HYSTERESIS_LEVEL;
assign hysteresis_met = fifo_level >= HYSTERESIS_LEVEL;
assign half_full = fifo_level[RAM_ADDR_BITS-1];
// input, output, and delay registers
always @ (posedge video_out_clk) begin
if (vid_ce) begin
de_1 <= vtg_de;
vsync_1 <= vsync;
field_id_1 <= field_id;
if (read_en) begin
fifo_sof_1 <= fifo_sof;
fifo_sof_2 <= fifo_sof_1 && !fifo_fid_1;
fifo_eol_1 <= fifo_eol;
fifo_eol_2 <= fifo_eol_1;
fifo_fid_1 <= fifo_fid;
end
fifo_eol_2_rising <= read_en && fifo_eol_1 && !fifo_eol_2;
de_2 <= de_1;
vsync_2 <= vsync_1;
vtg_eol_2 <= de_falling;
vtg_sof_2 <= de_rising && vert_bp && !field_id_1;
de_rising_1 <= de_rising;
end
end
// Vertical back porch SR register
always @ (posedge video_out_clk) begin
if (vid_ce) begin
if (vsync_falling) // falling edge of vsync
vert_bp <= 1;
else if (de_rising) // rising edge of data enable
vert_bp <= 0;
end
end
// FIFO read enable logic
always @ (posedge video_out_clk) begin
if (rst) begin
read_en <= 0;
end
else begin
if (vid_ce) begin
if ((read_ok && vtg_de) // normal read
||(vid_data_invalid && fifo_level > 3) // bubble swallowing
||(force_read) // state machine force read
)
read_en <= 1;
else
read_en <= 0;
end
end
end
// Clock Enable Logic. This accounts for the video clock enable
// for the Video Timimg Controller (generator). Clock enables are
// used for SD-SDI and 3G-SDI timing standards. The clock_en timing
// is delayed one clock from vid_ce. This is OK because all of
// the timing paths involved are sinble-cycle paths.
always @ (posedge video_out_clk) begin
clock_en <= pre_clock_en && vid_ce;
end
// Hysteresis counter
always @ (posedge video_out_clk) begin
if (vid_ce) begin
if (count_reset)
hyster_count <= 0;
else
hyster_count <= hyster_count + 1;
end
end
// next state logic
always @ * begin
if (VTG_MASTER_SLAVE == 0) begin //Slave mode
if(rst)
next_state = 0;
else
case (state)
0:
if (vtg_sof_2)
next_state = 1;
else
next_state = 0;
1:
if (fifo_sof_2)
next_state = 2;
else
next_state = 1;
2:
if (hysteresis_timeout)
next_state = 3;
else
next_state = 2;
3:
if (vtg_sof_2 && !fifo_sof_2)
next_state = 0;
else if (vsync_falling)
next_state = 8;
else if (fifo_eol_2_rising & !vtg_eol_2 ) // FIFO leads
next_state = 4;
else if (vtg_eol_2 & !fifo_eol_2_rising ) // VTG leads
next_state = 9;
else
next_state = 3;
4:
if (vtg_sof_2 && fifo_sof_2)
next_state = 8;
else if (vtg_sof_2)
next_state = 0;
else if (de_rising_1)
next_state = 5;
else
next_state = 4;
5:
if (vtg_sof_2)
next_state = 0;
else
next_state = 3;
6:
if ((vtg_sof_2 && !fifo_sof_2)
|| (vtg_eol_2 && !fifo_eol_2_rising))
next_state = 0;
else
next_state = 6;
8:
if ((vtg_sof_2 && !fifo_sof_2)
|| (vtg_eol_2 && !fifo_eol_2_rising))
next_state = 0;
else if (vtg_sof_2 && fifo_sof_2)
next_state = 6;
else
next_state = 8;
9:
if (vtg_sof_2 && fifo_sof_2)
next_state = 8;
else if (vtg_sof_2)
next_state = 0;
else if (fifo_eol_2_rising)
next_state = 10;
else
next_state = 9;
10:
if (vtg_sof_2 && !fifo_sof_2)
next_state = 0;
else
next_state = 3;
default:
next_state = 0;
endcase
end
else begin // Master Mode
if(rst)
next_state = 20;
else
case (state)
20:
next_state = 27;
21:
if (vtg_sof_2)
next_state = 23;
else
next_state = 21;
23:
if (vtg_sof_2 && !fifo_sof_2)
next_state = 20;
else if (vsync_falling)
next_state = 28;
else if (fifo_eol_2_rising & !vtg_eol_2 ) // FIFO leads
next_state = 24;
else if (vtg_eol_2 & !fifo_eol_2_rising ) // VTG leads
next_state = 30;
else
next_state = 23;
24:
if (vtg_sof_2 && fifo_sof_2)
next_state = 28;
else if (vtg_sof_2)
next_state = 20;
else if (de_rising_1)
next_state = 25;
else
next_state = 24;
25:
if (vtg_sof_2)
next_state = 20;
else
next_state = 23;
26:
if ((vtg_sof_2 && !fifo_sof_2)
|| (vtg_eol_2 && !fifo_eol_2_rising))
next_state = 20;
else
next_state = 26;
27:
if (fifo_sof_2)
next_state = 21;
else
next_state = 27;
28:
if ((vtg_sof_2 && !fifo_sof_2)
|| (vtg_eol_2 && !fifo_eol_2_rising))
next_state = 20;
else if (vtg_sof_2 && fifo_sof_2)
next_state = 26;
else
next_state = 28;
29:
if (vtg_sof_2 && fifo_sof_2)
next_state = 28;
else if (vtg_sof_2)
next_state = 20;
else if (fifo_eol_2_rising)
next_state = 23;
else
next_state = 29;
30:
if (vtg_sof_2 && !fifo_sof_2)
next_state = 20;
else
next_state = 29;
default:
next_state = 20;
endcase
end
end
// Control Logic
always @ (posedge video_out_clk) begin
if (vid_ce) begin
read_ok <= 1; // default values
force_read <= 0;
pre_clock_en <= 1;
fifo_rst <= 0;
initialize <= 0;
locked <= 0;
count_reset <= 1;
case (next_state)
// Free run uses defaults
0: begin
fifo_rst <= 1;
end
1: begin
pre_clock_en <= 0;
force_read <= 1;
initialize <= 1;
end
2: begin
pre_clock_en <= 0;
initialize <= 1;
count_reset <= 0;
end
3: begin
initialize <= 1;
end
4: begin
initialize <= 1;
end
5: begin
initialize <= 1;
read_ok <= 0;
end
6: begin
locked <= 1;
end
8: begin
initialize <= 1;
end
9: begin
initialize <= 1;
end
10: begin
initialize <= 1;
pre_clock_en <= 0;
end
20: begin
fifo_rst <= 1;
end
21: begin
read_ok <= 0;
initialize <= 1;
end
23: begin
initialize <= 1;
end
24: begin
initialize <= 1;
end
25: begin
initialize <= 1;
read_ok <= 0;
end
26: begin
locked <= 1;
end
27: begin
force_read <= 1;
end
28: begin
initialize <= 1;
end
29: begin
initialize <= 1;
end
30: begin
initialize <= 1;
force_read <= 1;
end
default:
locked <= 0;
endcase
end
end
// state register
always @ (posedge video_out_clk)
if (vid_ce) begin
state <= next_state;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : clk generation logic
// File : crt_clk_gen.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module generates dot clock, pixel clock (serializer
// shift clock) and character clock.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_clk_gen
(
input t_crt_clk,
input line_cmp,
input pix_pan,
input h_reset_n,
input h_io_16, // 16 bit access = 1, 8 bit = 0
input h_io_wr, // IO write cycle
input [15:0] h_addr, // Host address
input [7:0] c_ext_index, // Extended mode Index
input m_sr01_b4, // Shift and load 32
input m_sr01_b2, // Shift and load 16
input m_sr01_b0, /* 8 by 9 dot clock.
* 1 - 1/8; 0 - 1/9
* 1 - dclk is divided by 8
* 0 - dclk is divided by 9 */
input a_ar10_b0, // Graphics mode bit
input a_ar10_b6, // Pixel double clock select
input a_ar13_b3, // Pixel panning control bits 3-0
input a_ar13_b2,
input a_ar13_b1,
input a_ar13_b0,
input cr14_b5, // count by four
input cr17_b3, // count by two
input c_ahde_1, // advance horiz display enable
input c_ahde_1_u, // advance horiz display enable
input h_hclk, // Host clock
input ade, // advance display enable
input screen_off,
input pel_pan_en,
input dclk_en, // dot clock
input [15:0] h_io_dbus, // data bus
output [7:0] reg_misc,
output c_9dot, // 9-dot character clock
output misc_b0, // Address select bit. 0- 3bx, 1- 3dx
output misc_b6, // Horizontal sync. polarity
output misc_b7, // Vertical sync. polarity
output c_mis_3c2_b5, // Odd/Even page select
output clk_sel_ctl, // These 4 bits select the clock source
output cclk_en, // character clock
output final_sh_ld,
output final_crt_rd,
output c_misc_b1,
output pre_load
);
reg [4:0] cntr_op_ff; // Character counter FF's.
reg detect_s3_s7_s8_ff;
reg [1:0] sync1;
reg [1:0] sync2;
reg [1:0] sync4;
reg [1:0] sync5;
reg [1:0] sync6;
reg [1:0] sync7;
reg [1:0] sync8;
reg [1:0] sync9;
reg [1:0] sync10;
reg [1:0] sync11;
reg [1:0] sync12;
reg shift_ld_del;
reg detect_del;
reg [1:0] sh_cnt;
reg [1:0] cr_cnt;
reg cr_1_of_4_dly1;
reg cr_1_of_4_dly2;
wire sh_1_of_4; // generation of shift load signals
wire sh_1_0f_2;
wire int_shift_ld;
wire mid_shift_ld;
wire cr_1_of_4; // generation of crt read signals
wire cr_1_0f_2;
wire int_crt_rd;
wire mid_crt_rd;
wire [3:0] pp_mux_ctl; // pixel panning mux control
wire shift_ld;
wire crt_rd;
wire cntr_rst_n;
wire clk_ctl; // control signal of a mux
wire detect_3; // Set when cntr_op_ff = 5'b000_11
wire cntr_din_3;
wire cntr_din_0;
wire cntr_din_1;
wire state_8; // 000_11
wire state_7; // 0001
wire state_3;
wire detect_s7_s8;
wire detect_s3_s7_s8;
wire state_8i; // 000_11
wire state_7i; // 0001
wire state_3i;
wire detect_s7_s8i;
wire detect_s3_s7_s8i;
wire mode_13_ctl;
wire sh_ld_32 = m_sr01_b4;
wire sh_ld_16 = m_sr01_b2;
wire cnt_by_4 = cr14_b5;
wire cnt_by_2 = cr17_b3;
wire by_8_or_9 = m_sr01_b0; // if by_8_or_9 = 1 then 1/8 else 1/9
wire by_4 = 1'b0; // if by_4 = 1 then 1/4
wire mode_13_ctl_syn_cclk;
wire a_ar13_b3_syn_cclk;
wire a_ar13_b2_syn_cclk;
wire a_ar13_b1_syn_cclk;
wire a_ar13_b0_syn_cclk;
wire sh_ld_32_syn_cclk;
wire sh_ld_16_syn_cclk;
wire cnt_by_4_syn_cclk;
wire cnt_by_2_syn_cclk;
wire by_8_or_9_syn_cclk;
wire by_4_syn_cclk;
wire [3:0] int_pp_mux_ctl;
reg [6:0] store_misc;
assign reg_misc = store_misc;
// Instantiating the registers
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
store_misc <= 7'h0;
end else if (h_io_wr) begin
case (h_addr)
16'h03c2: store_misc <= {h_io_dbus[7:5], h_io_dbus[3:0]};
default: store_misc <= store_misc; // stop linter
endcase // case(h_addr)
end
// Synchronizing control register bits w.r.t cclk
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) begin
sync1 <= 2'b0;
sync2 <= 2'b0;
sync4 <= 2'b0;
sync5 <= 2'b0;
sync6 <= 2'b0;
sync7 <= 2'b0;
sync8 <= 2'b0;
sync9 <= 2'b0;
sync10 <= 2'b0;
sync11 <= 2'b0;
sync12 <= 2'b0;
end else if (cclk_en) begin
sync1 <= {sync1[0], sh_ld_32};
sync2 <= {sync2[0], sh_ld_16};
sync4 <= {sync4[0], cnt_by_4};
sync5 <= {sync5[0], cnt_by_2};
sync6 <= {sync6[0], by_8_or_9};
sync7 <= {sync7[0], by_4};
sync8 <= {sync8[0], a_ar13_b0};
sync9 <= {sync9[0], a_ar13_b1};
sync10 <= {sync10[0], a_ar13_b2};
sync11 <= {sync11[0], a_ar13_b3};
sync12 <= {sync12[0], mode_13_ctl};
end
assign sh_ld_32_syn_cclk = sync1[1];
assign sh_ld_16_syn_cclk = sync2[1];
assign cnt_by_4_syn_cclk = sync4[1];
assign cnt_by_2_syn_cclk = sync5[1];
assign by_8_or_9_syn_cclk = sync6[1];
assign by_4_syn_cclk = sync7[1];
assign a_ar13_b0_syn_cclk = sync8[1];
assign a_ar13_b1_syn_cclk = sync9[1];
assign a_ar13_b2_syn_cclk = sync10[1];
assign a_ar13_b3_syn_cclk = sync11[1];
assign mode_13_ctl_syn_cclk = sync12[1];
assign c_misc_b1 = reg_misc[1];
assign misc_b0 = reg_misc[0];
assign misc_b6 = reg_misc[6];
assign misc_b7 = reg_misc[7];
assign c_mis_3c2_b5 = reg_misc[5];
// Generating external clock selection control signals
assign clk_ctl = (reg_misc[3:2] == 2'b11);
assign clk_sel_ctl = clk_ctl ? 1'b0 : reg_misc[2];
// Generating character clock using Gray counter( Johnson counter )
assign detect_3 = (cntr_op_ff == 5'b000_11);
assign cntr_din_3 = by_8_or_9_syn_cclk ? (~cntr_op_ff[0]) : cntr_op_ff[4];
// if by_8_or_9 is true then cntr_din_0 = cntr_op_ff[1] otherwise
// cntr_din_0 = cntr_op_ff[1] if detect_3 is false. If detect_3 is true
// and by_8_or_9 is false then cntr_din_0 = 0;
// Using this logic we are detecting 000_11 and then forcing the
// counter to 000_00;
assign cntr_din_0 = by_8_or_9_syn_cclk ? cntr_op_ff[1] :
(cntr_op_ff[1] & (~detect_3));
// If by_4 is true then cntr_din_1 = ~cntr_op_ff[0] otherwise
// cntr_din_1 = cntr_op_ff[2]. This logic is to generate 4 dot
// character clock
assign cntr_din_1 = by_4_syn_cclk ? ~cntr_op_ff[0] : cntr_op_ff[2];
always @(posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n)
cntr_op_ff <= 5'b0;
else if (dclk_en) begin
cntr_op_ff[4] <= (~cntr_op_ff[0]);
cntr_op_ff[3] <= cntr_din_3;
cntr_op_ff[2] <= cntr_op_ff[3];
cntr_op_ff[1] <= cntr_din_1;
cntr_op_ff[0] <= cntr_din_0;
end
// Detecting state_7 in case of 8_dot and state_8 in case of 9_dot.
// Detecting state_3 in case of 4_dot
// This set of states are for being used synchronously
assign state_7i = dclk_en & (~cntr_op_ff[3])&(~cntr_din_1)&(cntr_din_0);
assign state_8i = dclk_en & (~cntr_din_3)&(~cntr_op_ff[3])&(cntr_din_1);
assign state_3i = dclk_en & (~cntr_din_1 & cntr_din_0);
assign detect_s7_s8i = by_8_or_9_syn_cclk ? state_7i : state_8i;
assign detect_s3_s7_s8i = by_4_syn_cclk ? state_3i : detect_s7_s8i;
assign state_7 = (~cntr_op_ff[2])&(~cntr_op_ff[1])&(cntr_op_ff[0]);
assign state_8 = (~cntr_op_ff[3])&(~cntr_op_ff[2])&(cntr_op_ff[1]);
assign state_3 = (~cntr_op_ff[1] & cntr_op_ff[0]);
assign detect_s7_s8 = by_8_or_9_syn_cclk ? state_7 : state_8;
assign detect_s3_s7_s8 = by_4_syn_cclk ? state_3 : detect_s7_s8;
always@( posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n)
detect_s3_s7_s8_ff <= 1'b0;
else if (dclk_en)
detect_s3_s7_s8_ff <= (detect_s3_s7_s8 & ade & (~screen_off));
assign cclk_en = cntr_op_ff[0] & ~cntr_din_0 & dclk_en;
assign shift_ld = detect_s3_s7_s8 & (~screen_off);
assign crt_rd = detect_s3_s7_s8_ff;
// Generate a registered version for edge detection
always @(posedge t_crt_clk) begin
shift_ld_del <= detect_s3_s7_s8i & ~screen_off;
detect_del <= detect_s3_s7_s8 & ade & ~screen_off;
end
// Instantiating a 2-bit up counters for countby2/4 & shift16/32.
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) sh_cnt <= 2'b0;
else if (~c_ahde_1) sh_cnt <= 2'b0;
else if (shift_ld_del &
~(detect_s3_s7_s8i & ~screen_off)) sh_cnt <= sh_cnt + 1;
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) cr_cnt <= 2'b0;
else if (~c_ahde_1) cr_cnt <= 2'b0;
else if (detect_del &
~(detect_s3_s7_s8 & ade & ~screen_off)) cr_cnt <= cr_cnt + 1;
assign cntr_rst_n = h_reset_n & c_ahde_1;
// if sh_ld_32 is true generate 1 out of 4.
// if sh_ld_16 is true generate 1 out of 2.
assign sh_1_of_4 = (~sh_cnt[1]) & (sh_cnt[0]); // detect 01
assign sh_1_0f_2 = sh_cnt[0]; // detect 11 or 01
assign int_shift_ld = sh_ld_32_syn_cclk ? sh_1_of_4 : sh_1_0f_2;
assign mid_shift_ld = (sh_ld_16_syn_cclk | sh_ld_32_syn_cclk) ? (int_shift_ld & shift_ld) : shift_ld;
// if cnt_by_4 is true generate 1 out of 4.
// if cnt_by_2 is true generate 1 out of 2.
assign cr_1_of_4 = (~cr_cnt[1]) & (cr_cnt[0]); // detect 01
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) begin
cr_1_of_4_dly1 <= 1'b0;
cr_1_of_4_dly2 <= 1'b0;
end else if (~c_ahde_1_u) begin
cr_1_of_4_dly1 <= 1'b0;
cr_1_of_4_dly2 <= 1'b0;
end else if (detect_del &
~(detect_s3_s7_s8 & ade & ~screen_off)) begin
cr_1_of_4_dly1 <= cr_1_of_4;
cr_1_of_4_dly2 <= cr_1_of_4_dly1;
end
assign cr_1_0f_2 = cr_cnt[0]; // detect 11 or 01
assign int_crt_rd = cnt_by_4_syn_cclk ? cr_1_of_4_dly2 : cr_1_0f_2;
assign mid_crt_rd = ( cnt_by_4_syn_cclk | cnt_by_2_syn_cclk ) ? (int_crt_rd & crt_rd) : crt_rd;
// Mode 13 is true if a_ar10_b0 & a_ar10_b6 are true
assign mode_13_ctl = a_ar10_b0 & a_ar10_b6;
// Realizing the pixel panning
assign int_pp_mux_ctl = { a_ar13_b3_syn_cclk, a_ar13_b2_syn_cclk,
a_ar13_b1_syn_cclk,
( a_ar13_b0_syn_cclk & (~mode_13_ctl_syn_cclk) ) };
assign pp_mux_ctl[3:0] = ~(line_cmp & pix_pan) ? int_pp_mux_ctl[3:0] : 4'b0;
pixel_panning SH_LD_PP
(
.din (mid_shift_ld),
.clk (t_crt_clk),
.clk_en (dclk_en),
.pp_ctl (pp_mux_ctl),
.mode_13_ctl (mode_13_ctl_syn_cclk),
.r_n (h_reset_n),
.by_4_syn_cclk (by_4_syn_cclk),
.dout (final_sh_ld),
.dout_1 (pre_load)
);
pixel_panning CRT_RD_PP
(
.din (mid_crt_rd),
.clk (t_crt_clk),
.clk_en (dclk_en),
.pp_ctl (pp_mux_ctl),
.mode_13_ctl (mode_13_ctl_syn_cclk),
.r_n (h_reset_n),
.by_4_syn_cclk (by_4_syn_cclk),
.dout (final_crt_rd),
.dout_1 ()
);
assign c_9dot = (~by_8_or_9_syn_cclk);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_SYMBOL_V
`define SKY130_FD_SC_HS__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_SYMBOL_V
`define SKY130_FD_SC_HDLL__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_SYMBOL_V
|
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-28 17:48:22
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch2 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
`ifdef SINGLE
CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 uut (
`endif
`ifdef DOUBLE
CORDIC_Arch2_W64_EW11_SW55_SWR55_EWR6 uut (
`endif
.clk(clk),
.rst(rst),
.beg_fsm_cordic(beg_fsm_cordic),
.ack_cordic(ack_cordic),
.operation(operation),
.data_in(data_in),
.shift_region_flag(shift_region_flag),
.r_mode(r_mode),
.ready_cordic(ready_cordic),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.data_output(data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
`ifndef RMODE00
r_mode = 2'b00;
`endif
`ifdef RMODE01
r_mode = 2'b01;
`endif
`ifdef RMODE10
r_mode = 2'b10;
`endif
`ifdef RMODE11
r_mode = 2'b11;
`endif
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
module nh_lcd_command (
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output reg [7:0] o_cmd_data,
input i_enable,
input i_cmd_parameter,
output reg o_cmd_finished,
//Physical Signals
output o_cmd_mode,
output reg o_write,
output reg o_read,
output reg [7:0] o_data_out,
input [7:0] i_data_in,
output reg o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam FINISHED = 4'h1;
//Registers/Wires
reg [3:0] state;
//Submodules
//Asynchronous Logic
assign o_cmd_mode = i_cmd_parameter;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_data_out_en <= 0;
o_data_out <= 0;
o_cmd_finished <= 0;
o_cmd_data <= 0;
o_write <= 0;
o_read <= 0;
end
else begin
//Strobes
o_cmd_finished <= 0;
//State Machine
case (state)
IDLE: begin
o_write <= 0;
o_read <= 0;
o_data_out_en <= 0;
if (i_cmd_write_stb) begin
//Change the bus to an output
o_data_out_en <= 1;
//Put the data on the bus
o_data_out <= i_cmd_data;
o_write <= 1;
state <= FINISHED;
end
else if (i_cmd_read_stb) begin
//Change the bus to an input
o_data_out_en <= 0;
o_read <= 1;
state <= FINISHED;
end
end
FINISHED: begin
o_write <= 0;
o_read <= 0;
if (!o_data_out_en) begin
//XXX: The appliction note doesn't describe how to explicitly read
//and the protocol is different from the 8080 MCU interface
o_cmd_data <= i_data_in;
end
o_cmd_finished <= 1;
state <= IDLE;
end
endcase
end
end
endmodule
|
Close Scope nat_scope.
Require Import ZArith.
Open Scope Z_scope.
Opaque Z.gt.
Opaque Z.lt.
Opaque Z.add.
Opaque Z.sub.
Opaque Z.ge.
Opaque Z.le.
(** Basic concepts **)
Parameter object : Type.
(** Categories **)
Definition S:= Prop.
Definition ADV := (object -> Prop) -> (object -> Prop).
(*Definition VeridicalAdvStrong := { adv : (object -> Prop) -> (object -> Prop) &
forall (x : object) (v : object -> Prop) (f : (object -> Prop) -> (object -> Prop)), f (adv v) x -> f v x}. (**) FIXME: probably too strong; consider eg. the case where f is "not". This would probably be OK for co-variant f's though. *)
Definition AdV := ADV.
Definition Adv := ADV.
Definition VeridicalAdv :=
{ adv : (object -> Prop) -> (object -> Prop)
& prod (forall (x : object) (v : object -> Prop), (adv v) x -> v x)
(forall (v w : object -> Prop), (forall x, v x -> w x) -> forall (x : object), adv v x -> adv w x)
}.
Definition WkVeridical : VeridicalAdv -> Adv
:= fun adv => projT1 adv.
Coercion WkVeridical : VeridicalAdv >-> Adv.
(* Theorem WkADV : VeridicalAdvStrong -> VeridicalAdv. cbv. intro adv. destruct adv as [adv cov]. exists adv. intros. apply cov with (f := fun p => p). exact H. Qed. *)
(* Coercion WkADV : VeridicalAdvStrong >-> VeridicalAdv. *)
Parameter CAdv : Set.
Parameter IAdv : Set.
Parameter IDet : Set.
Parameter IP : Set.
Parameter IQuant : Set.
Parameter PConj : Set.
Definition QCl := Prop.
Definition QS := Prop.
Definition Subj := Prop -> Prop -> Prop.
Definition CN:= object->Prop.
Definition VP := object -> Prop. (* subject *)
Definition SC := VP.
Definition V := object -> Prop.
Definition V2S := object -> S -> object -> Prop.
Definition V2V := object -> VP -> object -> Prop.
Definition V3 := object -> object -> object -> Prop. (* indirect object, direct object, subject *)
Definition V2 := object->object->Prop. (* Object first, subject second. *)
Definition VV := VP -> object -> Prop.
Definition VPS := VP.
Parameter VQ : Set.
Definition VS := S -> VP.
Parameter RP : Set.
Definition A := (object -> Prop) -> (object -> Prop).
Definition A2 := object -> A.
Definition IntersectiveA := object -> Prop.
Definition wkIntersectiveA
: IntersectiveA -> A
:= fun a cn (x:object) => a x /\ cn x.
Coercion wkIntersectiveA : IntersectiveA >-> A.
Inductive SubsectiveA : Type :=
mkSubsective : forall (measure : object -> Z) (threshold : (object -> Prop) -> Z), SubsectiveA.
Add Printing Let SubsectiveA.
Definition apSubsectiveA
: SubsectiveA -> A
:= fun a => let (measure, threshold) := a in
fun cn x => threshold cn <= measure x /\ cn x.
Definition getSubsectiveA := apSubsectiveA.
Coercion apSubsectiveA : SubsectiveA >-> A.
Inductive ExtensionalSubsectiveA : Type :=
mkExtensionalSubsective :
forall
(measure : object -> Z)
(threshold : (object -> Prop) -> Z),
(let a := fun cn x => (threshold cn <= measure x)
in (forall (p q:object -> Prop), (forall x, p x -> q x) -> (forall x, q x -> p x) -> forall x, a p x -> a q x))
-> ExtensionalSubsectiveA.
Add Printing Let ExtensionalSubsectiveA.
Definition apExtensionalSubsectiveA
: ExtensionalSubsectiveA -> SubsectiveA
:= fun a => let (measure,threshold,_) := a in
mkSubsective measure threshold.
Coercion apExtensionalSubsectiveA : ExtensionalSubsectiveA >-> SubsectiveA.
Inductive PrivativeA : Type :=
mkPrivativeA : ((object -> Prop) -> (object -> Prop)) -> PrivativeA.
Add Printing Let PrivativeA.
Definition wkPrivativeA : PrivativeA -> A
:= fun aa cn (x:object) => let (a) := aa in a cn x /\ not (cn x).
Coercion wkPrivativeA : PrivativeA >-> A.
Definition NonCommitalA := A.
Definition AP:= A.
Definition N:= object->Prop.
Definition N2 := object -> object -> Prop.
Inductive Num : Type :=
singular : Num |
plural : Num |
unknownNum : Num |
moreThan : Num -> Num |
cardinal : Z -> Num.
Definition Card := Num.
Definition AdN : Type := Num -> Num.
Parameter LOTS_OF : Z.
Parameter MANY : Z.
Parameter A_FEW : Z.
Parameter SOME : Z. (* the plural number *)
Parameter SEVERAL : Z.
Definition Numeral := Z.
Definition NP0 := VP ->Prop.
Definition NP1 := (object -> Prop) ->Prop.
Definition Quant := Num -> CN -> NP0.
Definition Det := prod Num Quant.
Inductive Prep : Type :=
mkPrep : forall (prep : NP1 -> (object -> Prop) -> (object -> Prop)),
(forall (prepArg : NP1) (v : object -> Prop) (subject : object), prep prepArg v subject -> v subject) -> (* veridical *)
(forall (prepArg : NP1) (v w : object -> Prop), (forall x, v x -> w x) -> forall (subject : object), prep prepArg v subject -> prep prepArg w subject) -> Prep. (* covariant in verb *)
Add Printing Let Prep.
Inductive NP : Type :=
mkNP : Num -> Quant -> CN -> NP.
Definition npClass (np:NP) := let (_,_,cn) := np in cn.
Definition apNP : NP -> NP0.
cbv. intro np. destruct np as [num quant cn]. apply quant. exact num. exact cn. Defined.
Definition VPSlash:=object -> VP.
Definition Pron := NP.
Inductive PN : Type := mkPN : forall (x:object) (cn : CN), cn x -> PN.
Definition Cl:=Prop.
Definition Pol:= Prop->Prop. (* Polarity *)
Definition Temp:= Prop -> Prop. (* temporal information *)
Definition Phr:= Prop.
Definition Ord:=A.
Definition Comp := VP. (* complement of copula*)
Definition Predet := NP -> NP.
Definition AdA := A -> A.
Definition ClSlash := VP. (* the parameter is the direct object of the verb *)
Definition RCl := VP. (* relative clause *)
Definition RS := RCl.
(** Constructors **)
(* Adv *)
(* Parameter AdAdv : AdA -> Adv -> Adv . *)
(* Parameter ComparAdvAdj : CAdv -> A -> NP -> Adv . *)
(* Parameter ComparAdvAdjS : CAdv -> A -> S -> Adv . *)
(* Parameter ConjAdv : Conj -> ListAdv -> Adv . *)
Parameter PositAdvAdj : A -> Adv .
(* Definition VeridicalAdv := { adv : (object -> Prop) -> (object -> Prop) & forall (x : object) (v : object -> Prop), (adv v) x -> v x}. *)
Definition SubjS : Subj -> S -> Adv := fun subj s vp x => subj s (vp x).
(* Card *)
Definition AdNum : AdN -> Card -> Card := fun f => f.
(* Parameter NumDigits : Digits -> Card . *)
Definition NumNumeral : Numeral -> Card := fun x => cardinal x.
(* Parameter digits2numeral : Card -> Card . *)
Parameter half_a_Card : Card .
(* Num *)
Definition NumSg:= singular.
Definition NumPl:= plural.
Definition NumCard : Card -> Num := fun x => x.
(* CN *)
Definition UseN: N->CN := fun n:N=>n.
Definition AdjCN: AP->CN->CN:= fun a o x => a o x.
Definition RelCN: CN->RS->CN:= fun cn rs x => cn x /\ rs x. (* GF FIXME: Relative clauses should apply to NPs. See 013, 027, 044. *)
Definition AdvCN : CN -> Adv -> CN := fun cn adv => adv cn.
(* Parameter PartNP : CN -> NP -> CN . *)
Parameter SentCN : CN -> SC -> CN .
Parameter elliptic_CN : CN .
(* Parameter ApposCN : CN -> NP -> CN . *)
(* Parameter ConjCN : Conj -> ListCN -> CN . *)
(* Parameter PossNP : CN -> NP -> CN . *)
(* Parameter UseN2 : N2 -> CN . *)
(* SC *)
Parameter EmbedPresPart : VP -> SC .
(* Parameter EmbedQS : QS -> SC . *)
Definition EmbedVP : VP -> SC := fun vp => vp.
(* NP *)
Definition DetCN: Det->CN->NP:= fun det cn=> mkNP (fst det) (snd det) cn.
Definition AdvNP : NP -> Adv -> NP
:= fun np adv => let (num,q,cn) := np in mkNP num (fun cn' k => q cn' (adv k)) cn. (* CHECK *)
(* Parameter ConjNP : Conj -> ListNP -> NP . *)
Definition PPartNP : NP -> V2 -> NP (* Word of warning: in FraCas partitives always behave like intersection, which is probably not true in general *)
:= fun np v2 => let (num,q,cn) := np in
mkNP num q (fun x => cn x /\ exists subject, v2 x subject).
(* Parameter RelNP : NP -> RS -> NP . *)
Definition RelNPa : NP -> RS -> NP
:= fun np rs => let (num,q,cn) := np
in mkNP num q (fun x => cn x /\ rs x).
(* Parameter SelfNP : NP -> NP . *)
Definition UsePron : Pron -> NP := fun pron => pron.
(* AP *)
Definition PositA: A -> A := fun x:A=>x.
(* In GF this is PositA : A -> AP; however this type does the conversion from the adjectival subclass to generic adjectives, which is wrong *)
Definition AdAP:AdA->AP->AP:= fun ad a => ad a.
Parameter AdvAP0 : AP -> Adv -> object -> Prop . (* We want to ignore the class here *)
Definition AdvAP : AP -> Adv -> AP
:= fun adj adv cn x => AdvAP0 adj adv x.
Definition ComparA : SubsectiveA -> NP -> AP
:= fun a np cn x => let (measure,_thres) := a in
apNP np (fun y => (1 <= measure x - measure y)).
(* Remark: most of the time, the comparatives are used in a copula, and in that case the category comes from the NP. *)
(* x is faster than y *)
Definition compareGradableMore : SubsectiveA -> (object->Prop) -> object -> object -> Prop :=
fun a cn x y => let (measure,_) := a in 1 <= measure x - measure y.
Definition compareGradableEqual : SubsectiveA -> (object -> Prop) -> object -> object -> Prop :=
fun a cn x y => let (measure,_) := a in measure x = measure y.
Definition ComplA2 : A2 -> NP -> AP := fun a2 np cn x => apNP np (fun y => a2 y cn x).
Parameter PartVP : VP -> AP .
Definition SentAP : AP -> SC -> AP
:= fun ap clause cn x => ap (fun y => clause y /\ cn y) x.
Parameter UseComparA : A -> AP.
Definition UseComparA_prefix : A -> AP := fun adj cn x => adj cn x.
(* Parameter UseA2 : A2 -> AP . *)
(* Parameter ConjAP : Conj -> ListAP -> AP . *)
(* Parameter ReflA2 : A2 -> AP . *)
(* Parameter AdjOrd : Ord -> AP . *)
(* Parameter CAdvAP : CAdv -> AP -> NP -> AP . *)
(* Quant *)
Parameter environment : (object -> Prop) -> object.
Parameter OF : object -> object -> Prop.
Parameter CARD: CN -> Z.
Parameter MOSTPART: Z -> Z.
Definition CARD_MOST := fun x => MOSTPART (CARD x).
Parameter MOST_ineq : forall x, MOSTPART x <= x.
Parameter CARD_monotonous : forall a b:CN, (forall x, a x -> b x) -> CARD a <= CARD b.
Parameter le_trans : forall x y z, x <= y -> y <= z -> x <= z.
Lemma most_card_mono1 : forall a b:CN, (forall x, a x -> b x) -> MOSTPART (CARD a) <= CARD b.
intros. cbv. apply le_trans with (y := CARD a). apply MOST_ineq. apply CARD_monotonous. assumption.
Qed.
(**Definition DefArt:Quant:= fun P:CN=> fun Q:object->Prop=>exists x, P x/\ Q x.**)
(* JP: "exists!" fails to identify that we refer to a thing outside the current NP ??? *)
Parameter PossPron : Pron -> Quant .
Definition no_Quant : Quant:= fun num P Q=> forall x, not (P x -> Q x) .
(* Parameter that_Quant : Quant . *)
Parameter the_other_Q : Quant .
Parameter this_Quant : Quant .
(* Det *)
Definition DetQuant: Quant -> Num -> Det:= fun (q:Quant) (n : Num) => (n,q).
Definition DetQuantOrd: Quant->Num->Ord->Det:= fun q n o =>(n,q). (* Ignoring the ord for now *)
(* Parameter ConjDet : Conj -> ListDet -> Det . *)
(* VPSlash *)
Definition SlashV2a: V2->VPSlash:= fun v dobj s => v dobj s.
(* Parameter AdVVPSlash : AdV -> VPSlash -> VPSlash . *)
(* Parameter AdvVPSlash : VPSlash -> Adv -> VPSlash . *)
(* Parameter SlashV2A : V2A -> AP -> VPSlash . *)
(* Parameter SlashV2Q : V2Q -> QS -> VPSlash . *)
(* Parameter SlashV2VNP : V2V -> NP -> VPSlash -> VPSlash . *)
(* Parameter VPSlashPrep : VP -> Prep -> VPSlash . *)
Definition Slash2V3 : V3 -> NP -> VPSlash
:= fun v np indirectObject subject => apNP np (fun directObject => v indirectObject directObject subject).
Definition Slash3V3 : V3 -> NP -> VPSlash
:= fun v np directObject subject => apNP np (fun indirectObject => v indirectObject directObject subject).
Definition SlashV2S : V2S -> S -> VPSlash
:= fun v2s s directObject subject => v2s directObject s subject.
Definition SlashV2V : V2V -> VP -> VPSlash
:= fun v2v vp directObject subject => v2v directObject vp subject.
Definition SlashVV : VV -> VPSlash -> VPSlash
:= fun vv v2 directObject subject => vv (fun x => v2 directObject x) subject.
(* AdV *)
(* QCl *)
(* Parameter ExistIP : IP -> QCl . *)
(* Parameter ExistIPAdv : IP -> Adv -> QCl . *)
Definition QuestCl : Cl -> QCl := fun c => c.
Parameter QuestIAdv : IAdv -> Cl -> QCl .
(* Parameter QuestIComp : IComp -> NP -> QCl . *)
(* Parameter QuestQVP : IP -> QVP -> QCl . *)
(* Parameter QuestSlash : IP -> ClSlash -> QCl . *)
Parameter QuestVP : IP -> VP -> QCl .
(* IQuant *)
Parameter which_IQuant : IQuant .
(* IDet *)
Parameter IdetQuant : IQuant -> Num -> IDet .
Parameter how8many_IDet : IDet .
(* IP *)
(* Parameter AdvIP : IP -> Adv -> IP . *)
Parameter IdetCN : IDet -> CN -> IP .
(* Parameter IdetIP : IDet -> IP . *)
(* IAdv *)
(* Parameter AdvIAdv : IAdv -> Adv -> IAdv . *)
(* Parameter ConjIAdv : Conj -> ListIAdv -> IAdv . *)
(* Parameter PrepIP : Prep -> IP -> IAdv . *)
(* VP *)
Definition ComplSlash: VPSlash->NP->VP:=fun v2 dobject subject=> apNP dobject(fun o => v2 o subject).
Definition UseComp: Comp -> VP (* be ... *)
:= fun p => p.
Definition ComplVV: VV -> VP -> VP
:= fun vv vp x => vv vp x.
Definition AdVVP : AdV -> VP -> VP
:= fun adV vp x => adV (fun y => vp y) x.
(* can inherit the class of x, because the new VP applies to x anyway *)
Definition AdvVP : VP -> Adv -> VP:= fun vp adV x => adV (fun y => vp y) x.
(* Parameter ComplBareVS : VS -> S -> VP . *)
Parameter ComplVQ : VQ -> QS -> VP .
Definition ComplVS : VS -> S -> VP
:= fun vs s => vs s.
Definition ComplVSa : VS -> S -> VP := ComplVS. (* FIXME: what is the difference from ComplVS? *)
(* Parameter ExtAdvVP : VP -> Adv -> VP . *)
Parameter PassV2 : V2 -> VP .
Parameter PassV2s : V2 -> VP .
Parameter PassVPSlash : VPSlash -> VP .
(* Parameter ProgrVP : VP -> VP . *)
Parameter ProgrVPa : VP -> VP .
Definition ReflVP : VPSlash -> VP
:= fun v2 subject => v2 subject subject.
(* Parameter SelfAdVVP : VP -> VP . *)
(* Parameter SelfAdvVP : VP -> VP . *)
(* Parameter UseCopula : VP . *)
Definition UseV : V -> VP
:= fun v x => v x.
Parameter elliptic_VP : VP .
(* Comp -- complement of copula*)
Definition CompCN: CN -> Comp (* be a thing given by the CN *)
:= fun cn x => cn x.
Definition CompNP: NP -> Comp (* be the thing given by the NP *)
:= fun np o => apNP np (fun o' => o = o').
(* Definition CompAP: AP -> Comp (* have property given by the AP *) *)
(* := fun ap x => ap xClass x. *)
Definition CompAdv : Adv -> Comp := fun adv x => adv (fun _ => True) x.
(* In the above we ignore the class, because test cases 027 and 044 seem to suggest that adverbs do not depend on the class of the object that they are applied to. This makes intuitive sense as adverbs to not expect a noun class, but rather a VP. (Actually, we could propagate the class and make use of it if it were not for relative clauses being applied to common nouns instead of NPs. See RelCN above.) *)
(* Temp *)
Definition Past : Temp := fun p => p .
Definition Present : Temp := fun p => p .
Definition Conditional : Temp := fun p => p.
Definition Future : Temp := fun p => p.
Definition FuturePerfect : Temp := fun p => p.
Definition PastPerfect : Temp := fun p => p.
Definition PresentPerfect : Temp := fun p => p.
(* fun TTAnt : Tense -> Ant -> Temp ; *)
(* Cl *)
Definition PredVP: NP->VP->Cl:= fun np vp=> apNP np vp.
Definition ExistNP: NP->Cl:= fun n=>apNP n (fun x => True).
Parameter IMPERSONAL : object.
Definition ImpersCl : VP -> Cl := fun vp => vp IMPERSONAL.
Parameter SoDoI : NP -> Cl .
Parameter elliptic_Cl : Cl .
(* Parameter CleftAdv : Adv -> S -> Cl . *)
(* Parameter CleftNP : NP -> RS -> Cl . *)
(* Parameter ExistNPAdv : NP -> Adv -> Cl . *)
(* Parameter GenericCl : VP -> Cl . *)
(* Parameter PredSCVP : SC -> VP -> Cl . *)
(* Parameter active2passive : Cl -> Cl . *)
(* ClSlash *)
(* Parameter AdvSlash : ClSlash -> Adv -> ClSlash . *)
(* Parameter SlashPrep : Cl -> Prep -> ClSlash . *)
(* Parameter SlashVS : NP -> VS -> SSlash -> ClSlash . *)
Definition SlashVP : NP -> VPSlash -> ClSlash
:= fun np vp dobject => apNP np (fun subject => vp dobject subject).
(* RCl *)
Definition RelVP: RP->VP->RCl:= fun relativePronounIgnored => fun p => p.
Parameter EmptyRelSlash : ClSlash -> RCl .
(* Parameter RelCl : Cl -> RCl . *)
Definition RelSlash : RP -> ClSlash -> RCl := fun rpIgnored cl => cl. (* TODO: Check *)
Definition StrandRelSlash : RP -> ClSlash -> RCl := fun rp cl => cl.
(* RS *)
Definition UseRCl: Temp->Pol->RCl->RS:=fun t p r x => p (r x).
(* RP *)
(* Parameter FunRP : Prep -> NP -> RP -> RP . *)
Parameter IdRP : RP .
Parameter that_RP : RP .
(* Pol *)
Definition PPos:Pol:= fun p=>p.
Definition UncNeg : Pol := fun p => not p.
Definition PNeg : Pol := UncNeg.
(* VPS *)
(* Parameter ConjVPS : Conj -> ListVPS -> VPS . *)
(* Parameter MkVPS : Temp -> Pol -> VP -> VPS . *)
(* Parameter RelS : S -> RS -> S . *)
(* Parameter SSubjS : S -> Subj -> S -> S . *)
(* PConj *)
(* Parameter NoPConj : PConj . *)
(* Parameter PConjConj : Conj -> PConj . *)
(* Phr *)
Definition Sentence: S->Phr:= fun sentence=> sentence.
Parameter Adverbial : Adv -> Phr .
Parameter Nounphrase : NP -> Phr .
Parameter PAdverbial : PConj -> Adv -> Phr .
Parameter PNounphrase : PConj -> NP -> Phr .
(* Parameter PQuestion : PConj -> QS -> Phr . *)
Parameter PSentence : PConj -> S -> Phr .
(* Parameter PhrUtt : PConj -> Utt -> Voc -> Phr . *)
Parameter Question : QS -> Phr .
(* Ord *)
Definition OrdSuperl: A->Ord:= fun a=>a.
(* Parameter OrdDigits : Digits -> Ord . *)
Parameter OrdNumeral : Numeral -> Ord .
(* Parameter OrdNumeralSuperl : Numeral -> A -> Ord . *)
(* N2 *)
(* Parameter ComplN3 : N3 -> NP -> N2 . *)
(* Parameter Use2N3 : N3 -> N2 . *)
(* Parameter Use3N3 : N3 -> N2 . *)
(** Lexicon **)
Parameter person_N : N .
Parameter whatPl_IP : IP .
Parameter whatSg_IP : IP .
Parameter whoPl_IP : IP .
Parameter whoSg_IP : IP .
Parameter how8much_IAdv : IAdv .
Parameter how_IAdv : IAdv .
Parameter when_IAdv : IAdv .
Parameter where_IAdv : IAdv .
Parameter why_IAdv : IAdv .
(* VQ *)
Parameter know_VQ : VQ .
Parameter come_cheap_VP : VP .
Parameter and_PConj : PConj .
Parameter but_PConj : PConj .
Parameter otherwise_PConj : PConj .
Parameter that_is_PConj : PConj .
Parameter then_PConj : PConj .
Parameter therefore_PConj : PConj .
Definition all_AdV : AdV := fun vp x => vp x . (* Adds no info *)
Parameter already_AdV : AdV .
Parameter also_AdV : AdV .
Parameter always_AdV : AdV .
Parameter currently_AdV : AdV .
Parameter ever_AdV : AdV .
Parameter never_AdV : AdV .
Parameter now_AdV : AdV .
Parameter still_AdV : AdV .
(*Definition a_few_Det : Det := (cardinal A_FEW, fun (num:Num) (cn : CN) (vp : VP) => (exists x, cn x /\ vp x)).*)
(* Definition a_lot_of_Det : Det:= (singular, fun num cn vp => (exists x, cn x /\ LOTS_OF cn x /\ vp cn x)) . (* Because this is used for "a lot of" is a mass; it's still singular. *) *)
Parameter another_Det : Det .
Parameter anyPl_Det : Det .
Parameter either_Det : Det .
Set Implicit Arguments.
(* AdA *)
Parameter almost_AdA : AdA .
Parameter quite_Adv : AdA .
Parameter really_AdA : AdA .
Parameter so_AdA : AdA .
Parameter too_AdA : AdA .
Parameter very_AdA : AdA .
(* Subj *)
Parameter after_Subj : Subj .
Parameter although_Subj : Subj .
Parameter because_Subj : Subj .
Parameter before_Subj : Subj .
Definition if_Subj : Subj := fun p q => p -> q.
Parameter since_Subj : Subj .
Parameter than_Subj : Subj .
Parameter that_Subj : Subj .
Parameter until_Subj : Subj .
Parameter when_Subj : Subj .
Parameter while_Subj : Subj .
(* Prep *)
Parameter above_Prep : Prep .
Parameter after_Prep : Prep .
Parameter at_Prep : Prep .
Parameter before_Prep : Prep .
Parameter behind_Prep : Prep .
Parameter between_Prep : Prep .
Parameter by8agent_Prep : Prep .
Parameter by8means_Prep : Prep .
Parameter during_Prep : Prep .
Parameter except_Prep : Prep .
Parameter for_Prep : Prep .
Parameter from_Prep : Prep .
Parameter in8front_Prep : Prep .
Parameter in_Prep : Prep .
Parameter on_Prep : Prep .
Parameter out_of_Prep : Prep .
Parameter outside_Prep : Prep .
Parameter part_Prep : Prep .
Parameter possess_Prep : Prep .
Parameter than_Prep : Prep .
Parameter through_Prep : Prep .
Parameter to_Prep : Prep .
Parameter under_Prep : Prep .
Parameter with_Prep : Prep .
Parameter within_Prep : Prep .
Parameter without_Prep : Prep .
(* CAdv *)
Parameter as_CAdv : CAdv .
Parameter less_CAdv : CAdv .
Parameter more_CAdv : CAdv .
Parameter allow_V2V : V2V .
Parameter bring_V2V : V2V .
Parameter elliptic_V2V : V2V .
Parameter see_V2V : V2V .
Parameter take_V2V : V2V .
Parameter suggest_to_V2S : V2S .
Parameter believe_VS : VS .
Parameter claim_VS : VS .
Parameter discover_VS : VS .
Parameter know_VS : VS .
Parameter say_VS : VS .
Parameter less_than_AdN : AdN .
Definition more_than_AdN : AdN := moreThan .
Parameter IMPRESSED_BY : object -> object -> Prop.
Definition impressed_by_A2 : A2 :=
fun impressee class impressor => class impressee /\ IMPRESSED_BY impressee impressor.
Parameter can8know_VV : VV .
Parameter can_VV : VV .
Parameter finish_VV : VV .
Parameter manage_VV : VV .
Parameter must_VV : VV .
Parameter need_VV : VV .
Parameter shall_VV : VV .
Parameter start_VV : VV .
Parameter try_VV : VV .
Parameter use_VV : VV .
Parameter want_VV : VV .
Parameter chairman_N2 : N2.
Definition chairman_N : N := fun o => exists institution, chairman_N2 institution o.
Parameter group_N2 : N2 .
Parameter inhabitant_N2 : N2 .
Parameter nobel_prize_N2 : N2 .
Parameter resident_in_N2 : N2 .
Parameter resident_on_N2 : N2 .
Parameter N_10 : Numeral .
Parameter N_100 : Numeral .
Parameter N_13 : Numeral .
Parameter N_14 : Numeral .
Parameter N_15 : Numeral .
Parameter N_150 : Numeral .
Parameter N_2 : Numeral .
Definition N_2500 : Numeral := 2500.
Definition N_3000 : Numeral := 3000.
Definition N_4 : Numeral := 4.
Definition N_500 : Numeral := 500.
Definition N_5500 : Numeral := 5500.
Parameter N_8 : Numeral .
Parameter N_99 : Numeral .
Parameter N_eight : Numeral .
Definition N_eleven : Numeral := 11 .
Parameter N_five : Numeral .
Parameter N_fortyfive : Numeral .
Parameter N_four : Numeral .
Definition N_one : Numeral := 1.
Definition N_six : Numeral := 6.
Definition N_sixteen : Numeral := 16.
Definition N_ten : Numeral := 10.
Definition N_three : Numeral := 3.
Definition N_twenty : Numeral := 20.
Definition N_two : Numeral := 2.
(* Parameter digits2num : Digits -> Numeral . *)
(* Parameter num : Sub1000000 -> Numeral . *)
Parameter beat_V : V .
Parameter come_in_V : V .
Parameter continue_V : V .
Parameter crash_V : V .
Parameter elliptic_V : V .
Parameter exist_V : V .
Parameter expand_V : V .
Parameter gamble_V : V .
Parameter go8travel_V : V .
Parameter go8walk_V : V .
Parameter graduate_V : V .
Parameter increase_V : V .
Parameter leave_V : V .
Parameter live_V : V .
Parameter meet_V : V .
Parameter start_V : V .
Parameter stop_V : V .
Parameter swim_V : V .
Parameter travel_V : V .
Parameter work_V : V .
Parameter award_V3 : V3 .
Parameter contribute_to_V3 : V3 .
Parameter deliver_V3 : V3 .
Parameter obtain_from_V3 : V3 .
Parameter put_in_V3 : V3 .
Parameter rent_from_V3 : V3 .
Parameter tell_about_V3 : V3 .
Parameter anywhere_Adv : Adv .
Parameter at_8_am_Adv : Adv .
Parameter at_a_quarter_past_five_Adv : Adv .
Parameter at_five_oclock_Adv : Adv .
Parameter at_four_oclock_Adv : Adv .
Parameter at_home_Adv : VeridicalAdv .
Parameter at_least_four_times : Adv .
Parameter at_some_time_Adv : Adv .
Parameter at_the_same_time_Adv : Adv .
Parameter by_11_am_Adv : Adv .
Parameter ever_since_Adv : Adv .
Parameter every_month_Adv : Adv .
Parameter every_week_Adv : Adv .
Parameter everywhere_Adv : Adv .
Parameter for_8_years_Adv : Adv .
Parameter for_a_total_of_15_years_or_more_Adv : Adv .
Parameter for_a_year_Adv : Adv .
Parameter for_an_hour_Adv : Adv .
Parameter for_exactly_a_year_Adv : Adv .
Parameter for_more_than_10_years_Adv : Adv .
Parameter for_more_than_two_years_Adv : Adv .
Parameter for_three_days_Adv : Adv .
Parameter for_two_hours_Adv : Adv .
Parameter for_two_years_Adv : VeridicalAdv .
Parameter friday_13th_Adv : Adv .
Parameter from_1988_to_1992_Adv : Adv .
Parameter here7from_Adv : Adv .
Parameter here7to_Adv : Adv .
Parameter here_Adv : Adv .
Parameter in_1990_Adv : VeridicalAdv .
Parameter in_1991_Adv : VeridicalAdv .
Parameter in_1992_Adv : VeridicalAdv .
Parameter in_1993_Adv : VeridicalAdv .
Parameter in_1994_Adv : VeridicalAdv .
Parameter in_a_few_weeks_Adv : Adv .
Parameter in_a_months_time_Adv : Adv .
Parameter in_july_1994_Adv : Adv .
Parameter in_march_1993_Adv : Adv .
Parameter in_march_Adv : Adv .
Parameter in_one_hour_Adv : Adv .
Parameter in_the_coming_year_Adv : Adv .
Parameter in_the_past_Adv : Adv .
Parameter in_two_hours_Adv : Adv .
Parameter last_week_Adv : Adv .
Parameter late_Adv : Adv .
Parameter long_Adv : Adv .
Parameter on_friday_Adv : Adv .
Parameter on_july_4th_1994_Adv : Adv .
Parameter on_july_8th_1994_Adv : Adv .
Parameter on_monday_Adv : VeridicalAdv .
Parameter on_the_5th_of_may_1995_Adv : Adv .
Parameter on_the_7th_of_may_1995_Adv : Adv .
Parameter on_thursday_Adv : VeridicalAdv .
Parameter on_time_Adv : VeridicalAdv .
Parameter on_tuesday_Adv : Adv .
Parameter on_wednesday_Adv : Adv .
Parameter over_Adv : Adv .
Parameter part_time_Adv : Adv .
Parameter saturday_july_14th_Adv : Adv .
Parameter since_1992_Adv : Adv .
Parameter somewhere_Adv : Adv .
Parameter the_15th_of_may_1995_Adv : Adv .
Parameter there7from_Adv : Adv .
Parameter there7to_Adv : Adv .
Parameter there_Adv : Adv .
Parameter together_Adv : Adv .
Parameter too_Adv : Adv .
Parameter twice_Adv : Adv .
Parameter two_years_from_now_Adv : Adv .
Parameter year_1996_Adv : Adv .
Parameter yesterday_Adv : Adv .
Parameter alan_PN : PN .
Parameter anderson_PN : PN .
Parameter apcom_PN : PN .
Parameter berlin_PN : PN .
Parameter bill_PN : PN .
Parameter birmingham_PN : PN .
Parameter bt_PN : PN .
Parameter bug_32985_PN : PN .
Parameter cambridge_PN : PN .
Parameter carl_PN : PN .
Parameter europe_PN : PN .
Parameter fido_PN : PN .
Parameter florence_PN : PN .
Parameter frank_PN : PN .
Parameter gfi_PN : PN .
Parameter helen_PN : PN .
Parameter icm_PN : PN .
Parameter itel_PN : PN .
Parameter john_PN : PN .
Parameter katmandu_PN : PN .
Parameter luxembourg_PN : PN .
Parameter MARY : object.
Parameter MARY_PERSON : person_N MARY.
Definition mary_PN : PN := mkPN MARY person_N MARY_PERSON .
Parameter mfi_PN : PN .
Parameter mtalk_PN : PN .
Parameter paris_PN : PN .
Parameter pavarotti_PN : PN .
Parameter peter_PN : PN .
Parameter portugal_PN : PN .
Parameter r95103_PN : PN .
Parameter scandinavia_PN : PN .
Parameter southern_europe_PN : PN .
Parameter sue_PN : PN .
Parameter sweden_PN : PN .
Parameter the_cia_PN : PN .
Parameter the_m25_PN : PN .
Parameter ambitious_A : A .
Parameter ancient_A : A .
Parameter asleep_A : A .
Parameter blue_A : A .
Parameter british_A : IntersectiveA .
Parameter broke_A : A .
Parameter canadian_A : A .
Parameter clever_A : SubsectiveA .
Parameter competent_A : SubsectiveA .
Parameter crucial_A : A .
Parameter dedicated_A : IntersectiveA .
Parameter different_A : A .
Parameter employed_A : A .
Parameter excellent_A : SubsectiveA .
Parameter false_A : PrivativeA.
Parameter fast_A : SubsectiveA .
Parameter fat_A : ExtensionalSubsectiveA .
Parameter female_A : IntersectiveA .
Parameter neutral_A : IntersectiveA .
Parameter former_A : PrivativeA .
Parameter fourlegged_A : IntersectiveA .
Parameter free_A : A .
Parameter furious_A : A .
Parameter genuine_A : IntersectiveA .
Parameter german_A : IntersectiveA .
Parameter great_A : SubsectiveA .
Parameter important_A : A .
Parameter indispensable_A : SubsectiveA .
Parameter interesting_A : IntersectiveA .
Parameter irish_A : IntersectiveA .
Parameter italian_A : IntersectiveA .
Parameter known_A : A .
Parameter large_A : SubsectiveA .
Parameter leading_A : SubsectiveA .
Parameter legal_A : A .
Parameter likely_A : SubsectiveA .
Parameter major_A : SubsectiveA .
Parameter male_A : IntersectiveA .
Parameter many_A : IntersectiveA .
Parameter missing_A : A .
Parameter modest_A : IntersectiveA .
Parameter national_A : SubsectiveA .
Parameter new_A : A .
Parameter north_american_A : IntersectiveA .
Parameter noted_A : A .
Definition own_A : A := fun cn b => True.
(* Ok, because at the moment "own" occurs only immediately after "his" (a possesive). It does not make syntactic sense otherwise.
Still it'd be nice to improve this --- in the GF syntax. *)
Parameter poor8bad_A : A .
Parameter poor8penniless_A : A .
Parameter portuguese_A : IntersectiveA .
Parameter present8attending_A : A .
Parameter present8current_A : A .
Parameter previous_A : A .
Parameter red_A : A .
Parameter resident_A : A .
Parameter scandinavian_A : SubsectiveA .
Parameter serious_A : A .
Parameter slow_A : SubsectiveA .
Parameter small_A : SubsectiveA .
Parameter successful_A : SubsectiveA .
Parameter swedish_A : IntersectiveA .
Parameter true_A : IntersectiveA.
Parameter unemployed_A : A .
Parameter western_A : A .
Parameter accountant_N : N .
Parameter agenda_N : N .
Parameter animal_N : N .
Parameter apcom_contract_N : N .
Parameter apcom_manager_N : N .
Parameter auditor_N : N .
Parameter authority_N : N .
Parameter board_meeting_N : N .
Parameter boss_N : N .
Parameter business_N : N .
Parameter businessman_N : N .
Parameter car_N : N .
Parameter case_N : N .
Parameter chain_N : N .
Parameter charity_N : N .
Parameter clause_N : N .
Parameter client_N : N .
Parameter colleague_N : N .
Parameter commissioner_N : N .
Parameter committee_N : N .
Parameter committee_member_N : N .
Parameter company_N : N .
Parameter company_car_N : N .
Parameter company_director_N : N .
Parameter computer_N : N .
Parameter concert_N : N .
Parameter conference_N : N .
Parameter continent_N : N .
Parameter contract_N : N .
Parameter copy_N : N .
Parameter country_N : N .
Parameter cover_page_N : N .
Parameter customer_N : N .
Parameter day_N : N .
Parameter delegate_N : N .
Parameter demonstration_N : N .
Parameter department_N : N .
Parameter desk_N : N .
Parameter diamond_N : N .
Parameter editor_N : N .
Parameter elephant_N : N .
Parameter european_N : N .
Parameter executive_N : N .
Parameter factory_N : N .
Parameter fee_N : N .
Parameter file_N : N .
Parameter greek_N : N .
Parameter hard_disk_N : N .
Parameter heart_N : N .
Parameter hour_N : N .
Parameter house_N : N .
Parameter individual_N : N .
Parameter invoice_N : N .
Parameter irishman_N : N .
Parameter italian_N : N .
Parameter itel_computer_N : N .
Definition itelxz_N : N := computer_N. (* hack for sec. 6 to fix comparison class *)
Definition itelzx_N : N := computer_N.
Definition itelzy_N : N := computer_N.
Parameter item_N : N .
Parameter job_N : N .
Parameter labour_mp_N : N .
Parameter laptop_computer_N : N .
Parameter law_lecturer_N : N .
Parameter lawyer_N : N .
Parameter line_N : N .
Parameter literature_N : N .
Parameter lobby_N : N .
Parameter loss_N : N .
Parameter machine_N : N .
Parameter mammal_N : N .
Parameter man_N : N .
Parameter meeting_N : N .
Parameter member_N : N .
Parameter member_state_N : N .
Parameter memoir_N : N .
Parameter mips_N : N .
Parameter moment_N : N .
Parameter mortgage_interest_N : N .
Parameter mouse_N : N .
Parameter newspaper_N : N .
Definition nobel_prize_N : N := fun o => exists x, nobel_prize_N2 o x.
Parameter note_N : N .
Parameter novel_N : N .
Parameter office_building_N : N .
Parameter one_N : N .
Parameter order_N : N .
Parameter paper_N : N .
Parameter payrise_N : N .
Definition pc6082_N : N := computer_N.
Parameter performance_N : N .
Parameter philosopher_N : N .
Parameter phone_N : N .
Parameter politician_N : N .
Parameter popular_music_N : N .
Parameter program_N : N .
Parameter progress_report_N : N .
Parameter project_proposal_N : N .
Parameter proposal_N : N .
Parameter report_N : N .
Parameter representative_N : N .
Parameter resident_N : N .
Parameter result_N : N .
Parameter right_N : N .
Parameter sales_department_N : N .
Parameter scandinavian_N : N .
Parameter secretary_N : N .
Parameter service_contract_N : N .
Parameter shore_N : N .
Parameter software_fault_N : N .
Parameter species_N : N .
Parameter station_N : N .
Parameter stockmarket_trader_N : N .
Parameter story_N : N .
Parameter student_N : N .
Parameter survey_N : N .
Parameter swede_N : N .
Parameter system_N : N .
Parameter system_failure_N : N .
Parameter taxi_N : N .
Parameter temper_N : N .
Parameter tenor_N : N .
Parameter time_N : N .
Parameter today_N : N .
Parameter traffic_N : N .
Parameter train_N : N .
Parameter university_graduate_N : N .
Parameter university_student_N : N .
Parameter week_N : N .
Parameter wife_N : N .
Parameter woman_N : N .
Parameter workstation_N : N .
Parameter world_N : N .
Parameter year_N : N .
Parameter MICKEY : object.
Parameter MICKEY_ANIM : animal_N MICKEY.
Definition mickey_PN := mkPN MICKEY animal_N MICKEY_ANIM .
Parameter DUMBO : object.
Parameter DUMBO_ANIM : animal_N DUMBO.
Definition dumbo_PN := mkPN DUMBO animal_N DUMBO_ANIM .
Parameter jones : object.
Parameter jones_PERSON : person_N jones.
Definition jones_PN := mkPN jones person_N jones_PERSON.
Parameter SMITH : object.
Parameter SMITH_PERSON : person_N SMITH.
Definition smith_PN := mkPN SMITH person_N SMITH_PERSON.
Parameter KIM : object.
Parameter KIM_PERSON : person_N KIM.
Definition kim_PN := mkPN KIM person_N KIM_PERSON.
Parameter accept_V2 : V2 .
Parameter answer_V2 : V2 .
Parameter appoint_V2 : V2 .
Parameter arrive_in_V2 : V2 .
Parameter attend_V2 : V2 .
Parameter become_V2 : V2 .
Parameter blame1_V2 : V2 .
Parameter blame2_V2 : V2 .
Parameter build_V2 : V2 .
Parameter buy_V2 : V2 .
Parameter catch_V2 : V2 .
Parameter chair_V2 : V2 .
Parameter cost_V2 : V2 .
Parameter cross_out_V2 : V2 .
Parameter deliver_V2 : V2 .
Parameter destroy_V2 : V2 .
Parameter develop_V2 : V2 .
Parameter discover_V2 : V2 .
Parameter dupe_V2 : V2 .
Parameter find_V2 : V2 .
Parameter finish_V2 : V2 .
Parameter found_V2 : V2 .
Parameter get_V2 : V2 .
Parameter hate_V2 : V2 .
Parameter have_V2 : V2 .
Parameter hurt_V2 : V2 .
Parameter last_V2 : V2 .
Parameter leave_V2 : V2 .
Parameter like_V2 : V2 .
Parameter lose_V2 : V2 .
Parameter maintain_V2 : V2 .
Parameter make8become_V2 : V2 .
Parameter make8do_V2 : V2 .
Parameter need_V2 : V2 .
Parameter open_V2 : V2 .
Definition own_V2 := have_V2 . (* This is because posessives are implemented with "have", and they sometimes imply ownership. See 134.*)
Parameter pay_V2 : V2 .
Parameter publish_V2 : V2 .
Parameter read_V2 : V2 .
Parameter read_out_V2 : V2 .
Parameter remove_V2 : V2 .
Parameter represent_V2 : V2 .
Parameter revise_V2 : V2 .
Parameter run_V2 : V2 .
Parameter sell_V2 : V2 .
Parameter send_V2 : V2 .
Parameter sign_V2 : V2 .
Parameter sing_V2 : V2 .
Parameter speak_to_V2 : V2 .
Parameter spend_V2 : V2 .
Parameter take_V2 : V2 .
Parameter take_part_in_V2 : V2 .
Parameter update_V2 : V2 .
Parameter use_V2 : V2 .
Parameter vote_for_V2 : V2 .
Parameter win_V2 : V2 .
Parameter win_V2from : object -> V2 .
Parameter work_in_V2 : V2 .
Parameter write_V2 : V2 .
Parameter write_to_V2 : V2 .
(** Knowledge **)
Parameter wantCovariant_K : forall p q:VP, forall s, (q s -> p s) -> want_VV q s -> want_VV p s.
Parameter sayCovariant_K : forall p q:S, forall s, (p -> q) -> say_VS p s -> say_VS q s.
Parameter claimCovariant_K : forall p q:S, forall s, (p -> q) -> claim_VS p s -> claim_VS q s.
Parameter person_K: forall x:object, chairman_N(x)-> person_N(x).
Parameter committee_member_person_K : forall x, committee_member_N x -> person_N x.
Parameter Not_stop_means_continue_K : forall x, stop_V x /\ continue_V x -> False.
Parameter small_and_large_disjoint_K : forall cn o, getSubsectiveA small_A cn o /\ getSubsectiveA large_A cn o -> False.
(* New combinators *)
Definition EXISTS := fun (p : object -> Prop) (q : object -> Prop) => exists x, p x /\ q x.
Definition FORALL := fun (p : object -> Prop) (q : object -> Prop) => forall x, p x -> q x.
Parameter THE : (object -> Prop) -> object.
Parameter THE_sat_exact : forall (q:object -> Prop), q (THE q).
Lemma THE_sat : forall (p:object -> Prop) (q:object -> Prop), (forall x, q x -> p x) -> p (THE q).
intros.
apply H.
apply THE_sat_exact.
Qed.
Definition deliver_V2to := deliver_V3.
Definition Not := not.
Definition PN2object : PN -> object.
cbv.
intros.
destruct X.
exact x.
Defined.
Opaque PN2object.
Definition PN2Class : PN -> (object -> Prop).
cbv.
intro x.
destruct x.
exact cn.
Defined.
Opaque PN2Class.
Parameter assumedNP : object.
Definition appA : A -> (object -> Prop) -> (object -> Prop)
:= fun a cn x => a cn x.
Definition appAdv : Adv -> (object -> Prop) -> (object -> Prop)
:= fun a cn x => a cn x.
Definition appoint_V2by : V3
:= fun x y _ => appoint_V2 x y.
Definition _BE_ : VP := fun x => True.
Parameter _BE_on : object -> VP.
Parameter _BE_in : object -> VP.
Parameter _BE_from : object -> VP.
Parameter _BE_at : object -> VP.
Parameter go8walk_Vto: object -> object -> Prop.
Parameter several: (object -> Prop) -> (object -> Prop) -> Prop.
Parameter have_V2for : object -> object -> object -> Prop.
Parameter take_V2to : object -> object -> object -> Prop.
Parameter take_V2at : object -> object -> object -> Prop.
Definition cover_page_Npossess
:= fun x: object => fun y : object => cover_page_N y /\ have_V2 y x.
Parameter go8travel_Vtoby8means : object -> object -> object -> Prop.
Parameter go8travel_Vby8means : object -> object -> Prop.
Parameter go8travel_Vtoby8meansto : object -> object -> object -> object -> Prop.
Parameter go8travel_Vby8meansto : object -> object -> object -> Prop.
Parameter go8travel_Vto : object -> object -> Prop.
Parameter knowVQ : VS.
Parameter WHY: Prop -> Prop.
Definition speak_to_V2to : object -> object -> object -> Prop
:= fun to _ subj => speak_to_V2 to subj.
Parameter work_Vadv : Adv -> object -> Prop.
Parameter find_V2before : object -> object -> object -> Prop.
Parameter go8walk_Vadv : Adv -> object -> Prop.
Parameter suggest_to_V2Sto : object -> V2S.
Parameter have_V2in : object -> V2.
Parameter travel_Vwithin : object -> V.
Parameter get_V2in : object -> V2.
Definition committee_member_Nfrom origin x :=
_BE_from origin x /\ committee_member_N x.
Parameter live_Vin : object -> V.
Parameter RESIDENT_IN : object -> object -> Prop.
Definition resident_Ain : object -> A :=
fun location pred x => RESIDENT_IN location x /\ pred x.
Parameter resident_Aoutside : object -> A.
Parameter spend_V2part : object -> V2.
Parameter item_Non : object -> N.
Parameter vote_for_V2at : object -> V2.
Parameter blame1_V2for : object -> V2.
Definition blame2_V2on : object -> V2
:= fun x y z => blame1_V2for y x z.
Parameter client_Nat : object -> N.
Definition stock_market_trader_N := stockmarket_trader_N. (* spelling *)
Parameter swim_Vto : object -> V.
Parameter run_V2in : object -> V2.
Parameter chain_Npart : object -> N.
Parameter own_V2in : object -> V2.
Definition QQ := CN -> VP -> Prop.
Definition FEWQ := fun cn => fun vp => (CARD (fun x => cn x /\ vp x) <= A_FEW).
Definition AFEWQ := fun cn => fun vp => A_FEW <= (CARD (fun x => cn x /\ vp x) ) /\ exists x, cn x /\ vp x.
Definition EQUAL : object -> object -> Prop := fun x y => x = y.
Definition MOSTQ := fun cn => fun vp => CARD_MOST cn <= CARD (fun x => cn x /\ vp x) /\ exists x, cn x /\ vp x.
Definition MANYQ := fun cn => fun vp => (MANY <= CARD (fun x => cn x /\ vp x)) /\ exists x, cn x /\ vp x.
Definition LOTSQ := fun cn => fun vp => (LOTS_OF <= CARD (fun x => cn x /\ vp x)) /\ exists x, cn x /\ vp x.
Definition SEVERALQ := fun cn => fun vp => (SEVERAL <= CARD (fun x => cn x /\ vp x)) /\ exists x, cn x /\ vp x.
Definition ATLEAST:= fun n : Z => fun cn=> fun vp=> exists x, cn x /\ vp x /\ (n <= CARD (fun x => cn x /\ vp x)).
Definition ATMOST:= fun n : Z => fun cn=> fun vp=> CARD (fun x => cn x /\ vp x) <= n.
Definition EXEXACT := fun n : Z => fun cn=> fun vp=> exists x, cn x /\ vp x /\ (CARD (fun x => cn x /\ vp x) = n).
Definition EXACT := fun n : Z => fun cn=> fun vp=> (CARD (fun x => cn x /\ vp x) = n).
Definition report_Nfromon := fun source location report => report_N report /\
send_V2 report source /\ _BE_on location report.
Definition award_and_be_awarded_V2 : V2 := fun x => fun y => award_V3 y x y .
Definition going_to_VV : VV := fun v => v. (* FIXME: Ignoring tense *)
Definition do_VV : VV := fun v => v.
Definition NOT:= not.
Lemma le_mono : forall n, forall (p q : CN), (forall x, p x -> q x) -> n <= CARD p -> n <= CARD q.
intros.
apply le_trans with (y := CARD p).
assumption.
apply CARD_monotonous.
assumption.
Qed.
Lemma le_mono' : forall n, forall (p q : CN), (forall x, q x -> p x) -> CARD p <= n -> CARD q <= n.
intros.
apply le_trans with (y := CARD p).
apply CARD_monotonous.
assumption.
assumption.
Qed.
Parameter CARD_exists : forall P:(object -> Prop), 1 <= CARD P -> exists x, P x.
Definition before_PREP
: object -> VP -> object -> Prop
:= fun arg vp subj => before_Subj (vp arg) (vp subj).
Definition le_mono_right := le_mono.
Definition le_mono_left := le_mono'.
Parameter usedToBeCov_K : forall (p q : VP), (forall x, p x -> q x) -> forall x , use_VV p x -> use_VV q x.
Parameter getInK : forall newsPaper result x, get_V2in newsPaper result x -> get_V2 result x.
(* Analysis: In "get published", published should not be intersectional. *)
Parameter client_people_K : forall x, client_N x -> person_N x.
Parameter exactEqual : forall x y (p : object -> Prop), p x -> p y -> CARD (fun x => p x) = 1 -> x = y.
Definition person_Nat : object -> CN :=
fun location person => person_N person /\ _BE_at location person.
Parameter slow_and_fast_disjoint_K : forall cn o, getSubsectiveA slow_A cn o /\ getSubsectiveA fast_A cn o -> False.
Definition opposite_adjectives : SubsectiveA -> SubsectiveA -> Prop
:= fun a1 a2 =>
forall cn o, let (mSmall,threshSmall) := a1 in
let (mLarge,threshLarge) := a2 in
( (mSmall o = - mLarge o)
/\ (1 <= threshLarge cn + threshSmall cn)).
Parameter fast_and_slow_opposite_K : opposite_adjectives slow_A fast_A.
Parameter small_and_large_opposite_K : opposite_adjectives small_A large_A.
|
`include "config.inc"
module gammaconv(
input clock,
input [4:0] gamma_config,
input in_wren,
input [`RAM_WIDTH-1:0] in_wraddr,
input [7:0] in_red,
input [7:0] in_green,
input [7:0] in_blue,
input in_starttrigger,
output reg wren,
output reg [`RAM_WIDTH-1:0] wraddr,
output reg [23:0] wrdata,
output reg starttrigger
);
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
gamma r(
.clock(clock),
.gamma_config(gamma_config),
.in(in_red),
.out(red)
);
gamma g(
.clock(clock),
.gamma_config(gamma_config),
.in(in_green),
.out(green)
);
gamma b(
.clock(clock),
.gamma_config(gamma_config),
.in(in_blue),
.out(blue)
);
reg wren_q;
reg [`RAM_WIDTH-1:0] wraddr_q;
reg starttrigger_q;
always @(posedge clock) begin
{ wren, wren_q } <= { wren_q, in_wren };
{ wraddr, wraddr_q } <= { wraddr_q, in_wraddr };
{ starttrigger, starttrigger_q } <= { starttrigger_q, in_starttrigger };
wrdata <= { red, green, blue };
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module bios_loader (
input wire clk,
input wire rst,
output reg [27:0] address,
output reg [3:0] byteenable,
output reg write,
output reg [31:0] writedata,
output reg read,
input wire [31:0] readdata,
input wire waitrequest
);
parameter PIO_OUTPUT_ADDR = 32'h00008860;
parameter DRIVER_SD_ADDR = 32'h00000000;
parameter BIOS_SECTOR = 72;
parameter BIOS_SIZE = (64*1024);
parameter BIOS_ADDR = 32'hF0000 | 32'h8000000;
parameter VBIOS_SECTOR = 8;
parameter VBIOS_SIZE = (32*1024);
parameter VBIOS_ADDR = 32'hC0000 | 32'h8000000;
parameter CTRL_READ = 2;
reg [31:0] state;
always @(posedge clk) begin
if(rst) state <= 1;
else if(state != 0 && (!(waitrequest && write))) state <= state + 1;
end
always @(posedge clk) begin
if(rst) begin
write <= 0;
read <= 0;
writedata <= 0;
address <= 0;
byteenable <= 4'b0000;
end else if(!(waitrequest && write))begin
case(state)
20000000: begin
// set pio_output to 1 (set ao486_reset to low)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h1;
write <= 1;
end
20001000: begin
// load bios
// bios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= BIOS_ADDR;
end
20002000: begin
// load bios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= BIOS_SECTOR;
end
20003000: begin
// load bios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= BIOS_SIZE / 512;
end
20004000: begin
// load bios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
40004000: begin
// load vbios
// vbios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= VBIOS_ADDR;
end
40005000: begin
// load vbios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= VBIOS_SECTOR;
end
40006000: begin
// load vbios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= VBIOS_SIZE / 512;
end
40007000: begin
// load vbios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
60007000: begin
// set pio_output to 0 (set ao486_reset to high)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h0;
write <= 1;
end
default: begin
write <= 0;
writedata <= 0;
address <= 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_SYMBOL_V
`define SKY130_FD_SC_HVL__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_SYMBOL_V
|
Require Export Metalib.Metatheory.
Require Export Ch5.
(*************************************************************************)
(** * Preservation 6.2 *)
(*************************************************************************)
(** *** Exercise
Complete the proof of preservation. In this proof, we proceed by
induction on the given typing derivation. The induction
hypothesis has already been appropriately generalized by the given
proof fragment.
Proof sketch: By induction on the typing derivation for [e].
- [typing_var] case: Variables don't step.
- [typing_op] case: By case analysis on how [e] steps.
- [typing_let] case: The
[eval_let_red] case is interesting, since it follows by the
substitution lemma. The others follow directly from the
induction hypotheses.
*)
(* HINTS:
- Use [auto] and [eauto], especially with [;], to solve
"uninteresting" subgoals.
- Use [inversion] to perform case analyses and to rule out
impossible cases.
- In the [eval_let_red] subcase of the [typing_let] case:
-- Use [inversion] on a typing judgement to obtain a
hypothesis about when the body of the abstraction is
well-typed.
-- Use [subst_intro] to rewrite the [open] operation into an
[open] followed by a [subst]. You'll need to pick a
fresh variable first.
*)
Lemma preservation : forall (E : env) e e' T,
typing E e T ->
eval e e' ->
typing E e' T.
Proof.
intros E e e' T H.
generalize dependent e'.
induction H; intros e' J.
(* EXERCISE *) Admitted.
(*************************************************************************)
(** * Progress *)
(*************************************************************************)
(** *** Exercise
Complete the proof of the progress lemma. The induction
hypothesis has already been appropriately generalized by the given
proof fragment.
Proof sketch: By induction on the typing derivation for [e].
- [typing_var] case: Can't happen; the empty environment doesn't
bind anything.
- [typing_let] case: Always reduces.
- [typing_op] case: always reduces. The result follows
from an exhaustive case analysis on whether the two components
of the operation step or are values and the fact that a
value must be a nat.
*)
(* HINTS:
- Use [auto] and [eauto], especially with [;], to solve
"uninteresting" subgoals.
- Use [inversion] to rule out impossible cases.
- The lemma [typing_to_lc] will be useful for reasoning
about local closure.
- In the [typing_op] case:
-- Use [destruct] to perform a case analysis on the
conclusions of the induction hypotheses.
-- Use [inversion] on a [value] judgement to determine that
the value must be an abstraction.
*)
Lemma progress : forall e T,
typing nil e T ->
value e \/ exists e', eval e e'.
Proof.
intros e T H.
(* It will be useful to have a "non-destructed" form of the given
typing derivation, since [induction] takes apart the derivation
it is called on. *)
assert (typing nil e T); auto.
(* [remember nil as E] fails here because [nil] takes an implicit
argument that Coq is unable to infer. By prefixing [nil] with
[@], we can supply the argument to nil explicitly. *)
remember (@nil (atom * typ)) as E.
induction H; subst.
(* FILL IN HERE (and delete "Admitted") *) Admitted.
(*************************************************************************)
(** * Canonical Forms *)
(*************************************************************************)
(** Exercise: The above proof implicitly reasons about the canonical forms
of values. State and prove the canonical forms lemma for this language.
(Lemma 6.3). *)
(*************************************************************************)
(** * Run-time errors *)
(*************************************************************************)
(** Challenge Exercise:
Add a division operator and an error term (of any type) to this
language, as described in Section 6.3. You'll want to start a new
file from scratch, starting with the definitions from Section 4.
*)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_range (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 1;
parameter max = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_RANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_range_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_range_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_range_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_range
`endif
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel (Channel-level) Flow-Control
* ============================================
*
* Supports
* - credit flow-control
* - stop/go style flow-control
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to '1' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module LAG_pl_fc_out (flits_valid,
channel_cntrl_in,
pl_status, // pl_status[pl]=1 if blocked (fifo is full)
// only when using credit-based flow control
pl_empty, // pl_empty[pl]=1 if PL fifo is empty (credits=init_credits)
pl_credits,
clk, rst_n);
`include "LAG_functions.v"
parameter num_pls = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input [num_pls-1:0] flits_valid;
input chan_cntrl_t channel_cntrl_in;
output pl_t pl_status;
output [num_pls-1:0] pl_empty;
output [num_pls-1:0][counter_bits-1:0] pl_credits;
input clk, rst_n;
logic [num_pls-1:0][counter_bits-1:0] counter;
logic [num_pls-1:0] inc, dec;
// buffer credit and flit pl id.'s so we can move counter in credit counter optimization
logic [num_pls-1:0] last_flits_valid;
pl_t last_credits;
logic [num_pls-1:0][counter_bits-1:0] counter_current;
logic [num_pls-1:0] pl_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_pls-1:0] current_state, next_state;
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credits <= channel_cntrl_in.credits;
last_flits_valid <= flits_valid;
// $display ("empty=%b", pl_empty);
end
assign pl_credits = counter_current;
for (i=0; i<num_pls; i++) begin:perpl1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
pl_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flits_valid[i]) &&
!(channel_cntrl_in.credits[i])) begin
pl_status[i] <= 1'b1;
pl_empty[i] <= 1'b0;
end else begin
pl_status[i] <= 1'b0;
pl_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i] = last_credits[i];
assign dec[i] = last_flits_valid[i];
end
end else begin
assign pl_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_pls; i++) begin:perpl
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for PL i?
assign inc[i]= channel_cntrl_in.credits[i];
// flit sent, one less credit
assign dec[i] = flits_valid[i];
// if counter==0, PL is blocked
assign pl_status[i]=(counter[i]==0);
// if counter==init_credits, PL buffer is empty
assign pl_empty[i]=(counter[i]==init_credits);
end // block: perpl
end
endgenerate
endmodule
|
module brainfuck
#( parameter AWIDTH = 12, DWIDTH = 16, PWIDTH = 12)
// AWIDTH: Data address bits
// DWIDTH: Data bits
// PWIDTH: Program counter bits
(
input clk, rst, // clk and async reset
input s_rst, // clocked reset
output [PWIDTH-1:0] pc,
output op_r_req,
input [31:0] op,
input op_den, // ignored for now assuming SRAM
output reg [AWIDTH-1:0] dp_adr,
output reg [DWIDTH-1:0] data_out,
output reg data_w_req,
output reg data_w_sel,
input data_w_wait, // ignored for now assuming SRAM
input [DWIDTH-1:0] data_in,
output reg data_r_req,
output reg data_r_sel,
input data_den // this does not stall operation. if 0, input is invalid
);
// opecode
// brainfuck operation code
// 8'h2B: +
// 8'h2C: ,
// 8'h2D: -
// 8'h2E: .
// 8'h3C: <
// 8'h3E: >
// 8'h5B: [
// 8'h5D: ]
localparam OP_PLUS = 8'h2B, OP_DIN = 8'h2c, OP_MINUS = 8'h2D, OP_DOUT = 8'h2E;
localparam OP_LEFT = 8'h3C, OP_RIGHT = 8'h3E, OP_LOOP_ST = 8'h5B, OP_LOOP_END = 8'h5D, OP_HLT = 8'h00;
localparam CMD_NOP = 3'b000;
localparam CMD_PLUS = 3'b010;
localparam CMD_RIGHT = 3'b001;
localparam CMD_DIN = 3'b011;
localparam CMD_DOUT = 3'b100;
localparam CMD_LST = 3'b101;
localparam CMD_LEND = 3'b110;
localparam CMD_HLT = 3'b111;
// Initialization
localparam MEM_MAX = {AWIDTH{1'b1}};
localparam INIT_WAIT = 4;
reg [AWIDTH-1:0] init_cnt;
reg [AWIDTH-1:0] mem_cnt;
// high level state machine
localparam INIT = 4'b0000, MEMI = 4'b0001, PREFETCH = 4'b0010, OPR = 4'b0100, HLT = 4'b1000;
reg [4:0] cur_state;
reg [4:0] nxt_state;
reg hlt_en;
// pipeline operation
wire [2:0] cmd_0st; // Fetch, address change, get operation (op), change dp_adr,
reg [2:0] cmd_1st; // Execute dp_adr change take effect, , dat change
reg [2:0] cmd_2nd; // MEM data memory read/write
wire [3:0] val_0st;
reg [3:0] val_1st;
reg [DWIDTH-1:0] dat; // copy of *dp
wire [DWIDTH-1:0] dat_new;
wire [DWIDTH-1:0] dat_tgt; // target of execution
reg [PWIDTH+1:0] pc_reg;
wire [2:0] pc_inc;
wire [PWIDTH+1:0] pc_cur;
wire [PWIDTH+1:0] pc_nxt;
wire [PWIDTH+1:0] pc_prefetch;
wire pc_dly;
reg pc_mov; // move o the next ']'
// stack for loop
localparam SDEPTH = 6;
reg [PWIDTH+1:0] stack[(1<<SDEPTH)-1:0];
reg [SDEPTH-1:0] sp;
integer i;
reg [SDEPTH-1:0] jmp_cnt; // count the number of [ and ] for forward jump
// data
wire [DWIDTH-1:0] dat_fwd; // data forward from memory read block
reg data_r_sel_z; // is the current data from memory (0) or from input (1)?
// fetch and decode
wire [31:0] op_le; // convert to little endian
wire op_r_req_cur;
// reg [PWIDTH+1:0] pc_z;
wire [1:0] index;
wire [63:0] op64; // history of up to 8 commands
wire [31:0] op32; // current 4 commands
wire [7:0] ops[3:0]; // current 4 commands in 8 bit form
wire [5:0] opc[3:0]; // decoded 4 opecodes (2bit val + 3bit cmd)
wire [2:0] cmd[3:0]; // decoded 4 commands // upper 3 bits of opecode
wire [2:0] cmd0; // the first meaningful command (skip nop)
wire [3:0] val0[3:0]; // +1 for + and >, -1 for - and <, 0 for the rest. Bits extended for later calc
wire [3:0] val[3:0]; // val0 masked by executed command (only +- seriese or <> series are executed at once)
wire [3:0] vals; // sum of val[]
reg [31:0] op_z;
wire val0_plus_en, val1_plus_en, val2_plus_en, val3_plus_en;
wire val0_right_en, val1_right_en, val2_right_en, val3_right_en;
wire cmd0_nop, cmd1_nop, cmd2_nop, cmd3_nop;
// init_cnt
always @(posedge clk or posedge rst) begin
if (rst) begin
init_cnt <= 0;
end
else if (s_rst) begin
init_cnt <= 0;
end
else if (init_cnt<INIT_WAIT) begin
init_cnt <= init_cnt + 12'b1;
end
end
// memory clear
always @(posedge clk or posedge rst) begin
if (rst) begin
mem_cnt <= 0;
end
else if (s_rst) begin
mem_cnt <= 0;
end
else if (cur_state==MEMI) begin
mem_cnt <= mem_cnt + 12'b1;
end
end // always @ (posedge clk or posedge rst)
// state machine
always @(posedge clk or posedge rst) begin
if (rst)
cur_state <= INIT;
else if (s_rst)
cur_state <= INIT;
else
cur_state <= nxt_state;
end
// state machine next state
always @(cur_state or s_rst or init_cnt or mem_cnt or pc_dly or cmd0 or dat_new or hlt_en) begin
if (s_rst)
nxt_state <= INIT;
else begin
case (cur_state)
INIT:
if (init_cnt == INIT_WAIT)
nxt_state <= MEMI;
else
nxt_state <= INIT;
MEMI:
if (mem_cnt == MEM_MAX)
nxt_state <= PREFETCH;
else
nxt_state <= MEMI;
PREFETCH:
nxt_state <= OPR;
OPR:
if (pc_dly==0 & cmd0==CMD_LEND & dat_new!=0) // jump
nxt_state <= PREFETCH;
else if (hlt_en)
nxt_state <= HLT;
else
nxt_state <= OPR;
default: nxt_state <= HLT; // HALT
endcase // case (cur_state)
end // else: !if(s_rst)
end // always @ (cur_state or s_rst or init_cnt or mem_cnt or hlt_en)
//
// pipeline processing
//
//
// Decoder
//
// PC change
// pc points to the program counter of the 1st stage of pipeline
always @(posedge clk or posedge rst) begin
if (rst)
pc_reg <= 0;
else if (s_rst)
pc_reg <= 0;
else if (cur_state == OPR)
pc_reg <= pc_nxt;
// in prefetch, pc_reg is not updated
end // always @ (posedge clk or posedge rst)
assign pc_cur = pc_reg;
assign pc_nxt = (cur_state!=OPR) ? pc_reg :
(pc_dly) ? pc_reg :
(cmd0 == CMD_LEND & dat_new!=0) ? stack[sp-1] : pc_reg + pc_inc;
assign pc_prefetch = pc_nxt + 14'h4;
assign pc = (nxt_state==PREFETCH) ? pc_nxt[PWIDTH+1:2] : pc_prefetch[PWIDTH+1:2];
// assign op_le = {op[7:0], op[15:8], op[23:16], op[31:24]};
assign op_le = op;
assign op64 = {op_le, op_z};
assign op32 = (index==2'b00) ? op64[31: 0] :
(index==2'b01) ? op64[39: 8] :
(index==2'b10) ? op64[47:16] : op64[55:24];
assign ops[0] = op32[ 7: 0];
assign ops[1] = op32[15: 8];
assign ops[2] = op32[23:16];
assign ops[3] = op32[31:24];
assign index = pc_cur[1:0]; // sub pointer
always @(posedge clk or posedge rst) begin
if (rst)
op_z <= {4{8'h20}};
else if (s_rst)
op_z <= {4{8'h20}};
else if (op_r_req)
op_z <= op_le;
end
function [4:0] decode;
input [7:0] opcode;
decode = (opcode == OP_PLUS ) ? {2'b01, CMD_PLUS} :
(opcode == OP_MINUS ) ? {2'b11, CMD_PLUS} :
(opcode == OP_RIGHT ) ? {2'b01, CMD_RIGHT} :
(opcode == OP_LEFT ) ? {2'b11, CMD_RIGHT} :
(opcode == OP_DIN ) ? {2'b00, CMD_DIN} :
(opcode == OP_DOUT ) ? {2'b00, CMD_DOUT} :
(opcode == OP_LOOP_ST ) ? {2'b00, CMD_LST} :
(opcode == OP_LOOP_END) ? {2'b00, CMD_LEND} :
(opcode == OP_HLT ) ? {2'b11, CMD_HLT} : {2'b00, CMD_NOP};
endfunction // decode
assign opc[0] = decode(ops[0]);
assign opc[1] = decode(ops[1]);
assign opc[2] = decode(ops[2]);
assign opc[3] = decode(ops[3]);
assign cmd[0] = opc[0][2:0];
assign cmd[1] = opc[1][2:0];
assign cmd[2] = opc[2][2:0];
assign cmd[3] = opc[3][2:0];
assign val0[0] = {{2{opc[0][4]}}, opc[0][4:3]};
assign val0[1] = {{2{opc[1][4]}}, opc[1][4:3]};
assign val0[2] = {{2{opc[2][4]}}, opc[2][4:3]};
assign val0[3] = {{2{opc[3][4]}}, opc[3][4:3]};
assign val0_plus_en = (cmd[0]==CMD_PLUS);
assign val1_plus_en = (cmd[1]==CMD_PLUS) & (val0_plus_en);
assign val2_plus_en = (cmd[2]==CMD_PLUS) & (val1_plus_en);
assign val3_plus_en = (cmd[3]==CMD_PLUS) & (val2_plus_en);
assign val0_right_en = (cmd[0]==CMD_RIGHT);
assign val1_right_en = (cmd[1]==CMD_RIGHT) & (val0_right_en);
assign val2_right_en = (cmd[2]==CMD_RIGHT) & (val1_right_en);
assign val3_right_en = (cmd[3]==CMD_RIGHT) & (val2_right_en);
assign val[0] = (val0_plus_en | val0_right_en) ? val0[0] : 4'b0000;
assign val[1] = (val1_plus_en | val1_right_en) ? val0[1] : 4'b0000;
assign val[2] = (val2_plus_en | val2_right_en) ? val0[2] : 4'b0000;
assign val[3] = (val3_plus_en | val3_right_en) ? val0[3] : 4'b0000;
assign vals = val[0] + val[1] + val[2] + val[3];
assign cmd0_nop = (cmd[0]==CMD_NOP);
assign cmd1_nop = (cmd[1]==CMD_NOP) & (cmd0_nop);
assign cmd2_nop = (cmd[2]==CMD_NOP) & (cmd1_nop);
assign cmd3_nop = (cmd[3]==CMD_NOP) & (cmd2_nop);
assign pc_inc = (val3_plus_en | val3_right_en | cmd3_nop) ? 3'h4 :
(val2_plus_en | val2_right_en | cmd2_nop) ? 3'h3 :
(val1_plus_en | val1_right_en | cmd1_nop) ? 3'h2 : 3'h1;
// find the first command
assign cmd0 = cmd[0];
assign cmd_0st = (cur_state!=OPR | pc_dly | pc_mov) ? CMD_NOP : cmd0; // insert nop (8'h20) when delaying or moving to next ']'
assign val_0st = vals;
// delay by one clock if the previous operation is reading from memory
assign pc_dly = ((cmd0==CMD_LEND | cmd0==CMD_LST) & (cmd_1st==CMD_RIGHT | cmd_1st==CMD_RIGHT | cmd_1st==CMD_DIN));
assign op_r_req_cur = (nxt_state==PREFETCH) ? 1'b1 :
(cur_state==PREFETCH) ? 1'b1 :
(cur_state==OPR & pc_reg[PWIDTH+1:2] != pc_nxt[PWIDTH+1:2]) ? 1'b1 : 1'b0;
assign op_r_req = op_r_req_cur;
always @(posedge clk or posedge rst) begin
if (rst)
hlt_en <= 0;
else if (s_rst)
hlt_en <= 0;
else if (cur_state==OPR & op==8'h00) // regard 00 as halt operation
hlt_en <= 1;
end
// Stack for loop
always @(posedge clk or posedge rst) begin
if (rst) begin
sp <= 6'h0;
for(i=0; i<64; i=i+1) begin
stack[i] <= 6'h0;
end
end
else if (s_rst)
sp <= 6'h0;
else begin
if (cmd_0st==CMD_LST & dat_new!=0) begin
stack[sp] <= pc_nxt;
sp <= sp + 6'h1;
end
else if (cmd_0st==CMD_LEND & dat_new==0) begin
sp <= sp - 6'h1;
end
end
end // always @ (posedge clk or posedge rst)
// jmp to next [
always @(posedge clk or posedge rst) begin
if (rst)
pc_mov <= 0;
else if (s_rst | cur_state!=OPR)
pc_mov <= 0;
else begin
if (cmd_0st==CMD_LST & dat_new==0)
pc_mov <= 1;
else if (cmd0==CMD_LEND & jmp_cnt==0) // this has to be op
pc_mov <= 0;
end
end // always @ (posedge clk or posedge rst)
// count ther number of [(+1) and ](-1)
always @(posedge clk or posedge rst) begin
if (rst)
jmp_cnt <= 0;
else if (s_rst | cur_state!=OPR)
jmp_cnt <= 0;
else begin
if (!pc_mov)
jmp_cnt <= 0;
else if (cmd0==CMD_LST[2:0])
jmp_cnt <= jmp_cnt + 6'h1;
else if (cmd0==CMD_LEND[2:0] & jmp_cnt!=0)
jmp_cnt <= jmp_cnt - 6'h1;
end
end // always @ (posedge clk or posedge rst)
// opecode
always @(posedge clk or posedge rst) begin
if (rst) begin
cmd_1st <= 0;
val_1st <= 0;
end
else if (s_rst | cur_state!=OPR) begin
cmd_1st <= 0;
val_1st <= 0;
end
else begin
cmd_1st <= cmd_0st;
val_1st <= val_0st;
end
end // always @ (posedge clk or posedge rst)
//
// Exec
//
// dp_adr
always @(posedge clk or posedge rst) begin
if (rst)
dp_adr <= 0;
else if (s_rst)
dp_adr <= 0;
else if (cur_state==MEMI)
dp_adr <= mem_cnt;
else if (cur_state==OPR) begin
if (cmd_0st==CMD_RIGHT)
dp_adr <= dp_adr + {{8{val_0st[3]}}, val_0st[3:0]};
end
end // always @ (posedge clk or posedge rst)
// generate read/write
always @(posedge clk or posedge rst) begin
if (rst) begin
data_w_req <= 0;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end
else if (s_rst) begin
data_w_req <= 0;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end
else if (cur_state==MEMI) begin
data_w_req <= 1;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end
else if (cur_state==OPR) begin
case (cmd_0st)
CMD_RIGHT: begin
data_w_req <= 0;
data_w_sel <= 0;
data_r_req <= 1;
data_r_sel <= 0;
end
CMD_PLUS: begin
data_w_req <= 1;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end
CMD_DIN: begin
data_w_req <= 1;
data_w_sel <= 0;
data_r_req <= 1;
data_r_sel <= 1;
end
CMD_DOUT: begin
data_w_req <= 1;
data_w_sel <= 1;
data_r_req <= 0;
data_r_sel <= 0;
end
default: begin
data_w_req <= 0;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end
endcase // case (cmd_0st)
end // else: !if(s_rst | cur_state!=OPR)
else begin
data_w_req <= 0;
data_w_sel <= 0;
data_r_req <= 0;
data_r_sel <= 0;
end // else: !if(cur_state==OPR)
end // always @ (posedge clk or posedge rst)
// dat (internal data cache) update
always @(posedge clk or posedge rst) begin
if (rst)
dat <= 0;
else if (s_rst)
dat <= 0;
else
dat <= dat_new;
end
assign dat_tgt = (cmd_2nd==CMD_RIGHT | cmd_2nd==CMD_RIGHT | cmd_2nd==CMD_DIN) ? dat_fwd : dat;
assign dat_new = (cmd_1st==CMD_PLUS) ? dat_tgt+{{12{val_1st[3]}}, val_1st[3:0]} : dat_tgt;
// output
always @(dat_new) begin
data_out <= dat_new;
end
//
// MEM Block
//
// memory read and write take effect
// read data is forwarded to dat_tgt
// opecode
always @(posedge clk or posedge rst) begin
if (rst)
cmd_2nd <= 0;
else if (s_rst | cur_state!=OPR)
cmd_2nd <= 0;
else
cmd_2nd <= cmd_1st;
end // always @ (posedge clk or posedge rst)
// if the previous operation is <, >, or , use the input as the target of operation
assign dat_fwd = (!data_r_sel_z & !data_den) ? 16'h0 : data_in; // if data_den==0 and data is from outside (not memory), replace it with zero
always @(posedge clk or posedge rst) begin
if (rst)
data_r_sel_z <= 0;
else if (s_rst)
data_r_sel_z <= 0;
else
data_r_sel_z <= data_r_sel;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_8_V
`define SKY130_FD_SC_HDLL__A21O_8_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_8 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_8 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_8_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: STARTUP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module STARTUP (
address,
clock,
q);
input [8:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "./startup/startup.rif"
`else
altsyncram_component.init_file = "./startup/startup.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./startup/startup.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./startup/startup.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_SYMBOL_V
`define SKY130_FD_SC_HS__DLRTP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_SYMBOL_V
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module ip_arp
#(parameter NUM_QUEUES = 8,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ARP_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to ip_arp
input [31:0] next_hop_ip,
input [NUM_QUEUES-1:0] lpm_output_port,
input lpm_vld,
input lpm_hit,
// --- interface to process block
output [47:0] next_hop_mac,
output [NUM_QUEUES-1:0] output_port,
output arp_mac_vld,
output arp_lookup_hit,
output lpm_lookup_hit,
input rd_arp_result,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read
input arp_rd_req, // request a read
output [47:0] arp_rd_mac, // data read from the LUT at rd_addr
output [31:0] arp_rd_ip, // ip to match in the CAM
output arp_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] arp_wr_addr,
input arp_wr_req,
input [47:0] arp_wr_mac,
input [31:0] arp_wr_ip, // data to match in the CAM
output arp_wr_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//--------------------- Internal Parameter-------------------------
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [47:0] next_hop_mac_result;
wire empty;
reg [NUM_QUEUES-1:0] output_port_latched;
reg lpm_hit_latched;
//------------------------- Modules-------------------------------
// 1 cycle read latency, 2 cycles write latency
/*
bram_cam_unencoded_32x32 arp_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
// wire cam_busy_signal_reg;
cam arp_cam
(
.reset(reset),
.wr_clk(clk),
.wr_en(cam_we),
.wr_key(cam_din),
.wr_index(cam_wr_addr),
.wr_erase_n(1'b1),
.rd_clk(clk),
.rd_en(lpm_vld),
.rd_key(cam_cmp_din),
.one_hot_addr(cam_match_addr),
.match_addr(),
.match(cam_match),
.multi_match(),
.index_reg(),
.cam_full(),
.multi_index()
);
//assign cam_busy = cam_busy_signal_reg;
//assign cam_busy = 1'b0;
localparam
IDLE_STATE_CAM = 2'b00,
FIRST_STATE_CAM = 2'b01,
SECOND_STATE_CAM = 2'b10;
reg [1:0] state_cam,state_cam_nxt;
reg cam_busy_signal_reg,cam_busy_signal_reg_next;
always @(posedge clk) begin
if (reset) begin
state_cam <= IDLE_STATE_CAM;
cam_busy_signal_reg <= 1'b0;
end
else begin
state_cam <= state_cam_nxt;
cam_busy_signal_reg <= cam_busy_signal_reg_next;
end // else
end
always @(*) begin
cam_busy_signal_reg_next = cam_busy_signal_reg;
state_cam_nxt = state_cam;
case (state_cam)
IDLE_STATE_CAM: begin
if (cam_we) begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = FIRST_STATE_CAM;
end
else
cam_busy_signal_reg_next = 1'b0;
end
FIRST_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = SECOND_STATE_CAM;
end
SECOND_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b0;
state_cam_nxt = IDLE_STATE_CAM;
end
endcase // case(state)
end
assign cam_busy = cam_busy_signal_reg;
unencoded_cam_lut_sm
#(.CMP_WIDTH(32), // IPv4 addr width
.DATA_WIDTH(48),
.LUT_DEPTH(LUT_DEPTH)
) cam_lut_sm
(// --- Interface for lookups
.lookup_req (lpm_vld),
.lookup_cmp_data (next_hop_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lookup_ack),
.lookup_hit (lookup_hit),
.lookup_data (next_hop_mac_result),
// --- Interface to registers
// --- Read port
.rd_addr (arp_rd_addr), // address in table to read
.rd_req (arp_rd_req), // request a read
.rd_data (arp_rd_mac), // data found for the entry
.rd_cmp_data (arp_rd_ip), // matching data for the entry
.rd_cmp_dmask (), // don't cares entry
.rd_ack (arp_rd_ack), // pulses high
// --- Write port
.wr_addr (arp_wr_addr),
.wr_req (arp_wr_req),
.wr_data (arp_wr_mac), // data found for the entry
.wr_cmp_data (arp_wr_ip), // matching data for the entry
.wr_cmp_dmask (32'h0), // don't cares for the entry
.wr_ack (arp_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
fallthrough_small_fifo #(.WIDTH(50+NUM_QUEUES), .MAX_DEPTH_BITS (2))
arp_fifo
(.din ({next_hop_mac_result, output_port_latched, lookup_hit, lpm_hit_latched}), // Data in
.wr_en (lookup_ack), // Write enable
.rd_en (rd_arp_result), // Read the next word
.dout ({next_hop_mac, output_port, arp_lookup_hit, lpm_lookup_hit}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic --------------------------------
assign arp_mac_vld = !empty;
always @(posedge clk) begin
if(reset) begin
output_port_latched <= 0;
lpm_hit_latched <= 0;
end
else if(lpm_vld) begin
output_port_latched <= lpm_output_port;
lpm_hit_latched <= lpm_hit;
end
end
endmodule // ip_arp
|
reg reset;
reg tx_clock;
reg rx_clock;
reg carrier_sense;
reg collision;
wire tx_enable;
wire [7:0] tx_data;
wire rx_data_valid;
wire [7:0] rx_data;
wire rx_error;
reg expected_tx_enable;
mac_loopback U_mac_loopback(
.reset(reset),
.tx_clock(tx_clock),
.rx_clock(rx_clock),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data),
.rx_data_valid(rx_data_valid),
.rx_data(rx_data),
.rx_error(rx_error)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
util (
.data_in(1'b0),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock()
);
utilities #(.OUT_WIDTH (8),
.IN_WIDTH (8))
data_in (
.data_in(),
.data_in_enable(),
.data_out(rx_data),
.data_out_enable(rx_data_valid),
.clock(rx_clock)
);
utilities #(.OUT_WIDTH (8),
.IN_WIDTH (8))
data_out (
.data_in(tx_data),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(tx_clock)
);
monitor #(.WIDTH(1))
tx_enable_monitor(
.data(tx_enable),
.expected(expected_tx_enable),
.clock(tx_clock));
initial
begin
rx_clock = 0;
tx_clock = 0;
reset = 1;
collision = 0;
carrier_sense = 0;
expected_tx_enable = 0;
end
always
#5 rx_clock = ~rx_clock;
always
#5
tx_clock = ~tx_clock;
|
// Data RAM
module data_mem
(
input wire clk,
input wire[31:0] addr_dmem_ram_i,
input wire[31:0] wr_data_dmem_ram_i,
input wire[0:3] wr_strb_dmem_ram_i,
input wire wr_en_dmem_ram_i,
output wire[31:0] read_data_dmem_ram_o
);
parameter data_seg_begin = 32'h0,
data_seg_size = 32'h1FFF;
// Byte Addressable mem
reg [31:0] dmem [0:data_seg_size];
wire[31:0] read_data;
wire[31:0] wr_strb = {wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],
wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],
wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],
wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],
wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],
wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],
wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],
wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0]};
assign read_data_dmem_ram_o = read_data;
always @(posedge clk)
if (wr_en_dmem_ram_i)
dmem[((addr_dmem_ram_i - data_seg_begin)&(~32'h3))>>2] <= ((wr_data_dmem_ram_i & wr_strb) | (~wr_strb & read_data));
assign read_data = dmem[((addr_dmem_ram_i - data_seg_begin)&(~32'h3))>>2];
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:32:45 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 64 reg
// wsiM0_MByteEn O 8 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wmemiM0_MCmd O 3 reg
// wmemiM0_MReqLast O 1 reg
// wmemiM0_MAddr O 36 reg
// wmemiM0_MBurstLength O 12 reg
// wmemiM0_MDataValid O 1 reg
// wmemiM0_MDataLast O 1 reg
// wmemiM0_MData O 128 reg
// wmemiM0_MDataByteEn O 16 reg
// wmemiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 64
// wsiS0_MByteEn I 8
// wsiS0_MReqInfo I 8
// wmemiM0_SResp I 2
// wmemiM0_SData I 128
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wmemiM0_SRespLast I 1
// wmemiM0_SCmdAccept I 1
// wmemiM0_SDataAccept I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDelayWorker8B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n);
parameter [31 : 0] dlyCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [63 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [7 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [63 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [7 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// signals for module outputs
wire [127 : 0] wmemiM0_MData;
wire [63 : 0] wsiM0_MData;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wciS0_SData;
wire [15 : 0] wmemiM0_MDataByteEn;
wire [11 : 0] wmemiM0_MBurstLength, wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MByteEn, wsiM0_MReqInfo;
wire [2 : 0] wmemiM0_MCmd, wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [145 : 0] wmemi_dhF_x_wire$wget;
wire [130 : 0] wmemi_wmemiResponse$wget;
wire [127 : 0] wmemi_Em_sData_w$wget;
wire [96 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [63 : 0] mesgWF_wDataIn$wget,
mesgWF_wDataOut$wget,
wsi_Es_mData_w$wget;
wire [51 : 0] wmemi_reqF_x_wire$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] wci_wci_Es_mAddr_w$wget, wci_wci_Es_mData_w$wget;
wire [24 : 0] dlyWordsStored_acc_v1$wget, dlyWordsStored_acc_v2$wget;
wire [15 : 0] dlyReadyToWrite_acc_v1$wget, dlyReadyToWrite_acc_v2$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] dlyReadCredit_acc_v1$wget,
dlyReadCredit_acc_v2$wget,
wsi_Es_mByteEn_w$wget,
wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget,
wci_wslv_wEdge$wget,
wsi_Es_mCmd_w$wget;
wire [1 : 0] wmemi_Em_sResp_w$wget;
wire dlyReadCredit_acc_v1$whas,
dlyReadCredit_acc_v2$whas,
dlyReadyToWrite_acc_v1$whas,
dlyReadyToWrite_acc_v2$whas,
dlyWordsStored_acc_v1$whas,
dlyWordsStored_acc_v2$whas,
mesgWF_pwDequeue$whas,
mesgWF_pwEnqueue$whas,
mesgWF_wDataIn$whas,
mesgWF_wDataOut$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wmemi_Em_sData_w$whas,
wmemi_Em_sRespLast_w$whas,
wmemi_Em_sResp_w$whas,
wmemi_dhF_dequeueing$whas,
wmemi_dhF_enqueueing$whas,
wmemi_dhF_x_wire$whas,
wmemi_operateD_1$wget,
wmemi_operateD_1$whas,
wmemi_peerIsReady_1$wget,
wmemi_peerIsReady_1$whas,
wmemi_reqF_dequeueing$whas,
wmemi_reqF_enqueueing$whas,
wmemi_reqF_x_wire$whas,
wmemi_sCmdAccept_w$wget,
wmemi_sCmdAccept_w$whas,
wmemi_sDataAccept_w$wget,
wmemi_sDataAccept_w$whas,
wmemi_wmemiResponse$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register bytesRead
reg [31 : 0] bytesRead;
wire [31 : 0] bytesRead$D_IN;
wire bytesRead$EN;
// register bytesThisMessage
reg [23 : 0] bytesThisMessage;
wire [23 : 0] bytesThisMessage$D_IN;
wire bytesThisMessage$EN;
// register bytesWritten
reg [31 : 0] bytesWritten;
wire [31 : 0] bytesWritten$D_IN;
wire bytesWritten$EN;
// register cyclesPassed
reg [31 : 0] cyclesPassed;
wire [31 : 0] cyclesPassed$D_IN;
wire cyclesPassed$EN;
// register dlyCtrl
reg [31 : 0] dlyCtrl;
wire [31 : 0] dlyCtrl$D_IN;
wire dlyCtrl$EN;
// register dlyHoldoffBytes
reg [31 : 0] dlyHoldoffBytes;
wire [31 : 0] dlyHoldoffBytes$D_IN;
wire dlyHoldoffBytes$EN;
// register dlyHoldoffCycles
reg [31 : 0] dlyHoldoffCycles;
wire [31 : 0] dlyHoldoffCycles$D_IN;
wire dlyHoldoffCycles$EN;
// register dlyRAG
reg [22 : 0] dlyRAG;
wire [22 : 0] dlyRAG$D_IN;
wire dlyRAG$EN;
// register dlyRdOpOther
reg [31 : 0] dlyRdOpOther;
wire [31 : 0] dlyRdOpOther$D_IN;
wire dlyRdOpOther$EN;
// register dlyRdOpZero
reg [31 : 0] dlyRdOpZero;
wire [31 : 0] dlyRdOpZero$D_IN;
wire dlyRdOpZero$EN;
// register dlyReadCredit_value
reg [7 : 0] dlyReadCredit_value;
wire [7 : 0] dlyReadCredit_value$D_IN;
wire dlyReadCredit_value$EN;
// register dlyReadyToWrite_value
reg [15 : 0] dlyReadyToWrite_value;
wire [15 : 0] dlyReadyToWrite_value$D_IN;
wire dlyReadyToWrite_value$EN;
// register dlyWAG
reg [22 : 0] dlyWAG;
wire [22 : 0] dlyWAG$D_IN;
wire dlyWAG$EN;
// register dlyWordsStored_value
reg [24 : 0] dlyWordsStored_value;
wire [24 : 0] dlyWordsStored_value$D_IN;
wire dlyWordsStored_value$EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar$D_IN;
wire mesgLengthSoFar$EN;
// register mesgRdCount
reg [31 : 0] mesgRdCount;
wire [31 : 0] mesgRdCount$D_IN;
wire mesgRdCount$EN;
// register mesgWF_rCache
reg [77 : 0] mesgWF_rCache;
wire [77 : 0] mesgWF_rCache$D_IN;
wire mesgWF_rCache$EN;
// register mesgWF_rRdPtr
reg [12 : 0] mesgWF_rRdPtr;
wire [12 : 0] mesgWF_rRdPtr$D_IN;
wire mesgWF_rRdPtr$EN;
// register mesgWF_rWrPtr
reg [12 : 0] mesgWF_rWrPtr;
wire [12 : 0] mesgWF_rWrPtr$D_IN;
wire mesgWF_rWrPtr$EN;
// register mesgWtCount
reg [31 : 0] mesgWtCount;
wire [31 : 0] mesgWtCount$D_IN;
wire mesgWtCount$EN;
// register rdSerAddr
reg [31 : 0] rdSerAddr;
wire [31 : 0] rdSerAddr$D_IN;
wire rdSerAddr$EN;
// register rdSerEmpty
reg rdSerEmpty;
wire rdSerEmpty$D_IN, rdSerEmpty$EN;
// register rdSerMeta
reg [31 : 0] rdSerMeta;
wire [31 : 0] rdSerMeta$D_IN;
wire rdSerMeta$EN;
// register rdSerPos
reg [1 : 0] rdSerPos;
wire [1 : 0] rdSerPos$D_IN;
wire rdSerPos$EN;
// register rdSerStage
reg [31 : 0] rdSerStage;
wire [31 : 0] rdSerStage$D_IN;
wire rdSerStage$EN;
// register rdSerStage_1
reg [31 : 0] rdSerStage_1;
wire [31 : 0] rdSerStage_1$D_IN;
wire rdSerStage_1$EN;
// register rdSerStage_2
reg [31 : 0] rdSerStage_2;
wire [31 : 0] rdSerStage_2$D_IN;
wire rdSerStage_2$EN;
// register rdSerStage_3
reg [31 : 0] rdSerStage_3;
wire [31 : 0] rdSerStage_3$D_IN;
wire rdSerStage_3$EN;
// register rdSerUnroll
reg [15 : 0] rdSerUnroll;
wire [15 : 0] rdSerUnroll$D_IN;
wire rdSerUnroll$EN;
// register rdSyncWord
reg rdSyncWord;
reg rdSyncWord$D_IN;
wire rdSyncWord$EN;
// register readMeta
reg [31 : 0] readMeta;
wire [31 : 0] readMeta$D_IN;
wire readMeta$EN;
// register tog50
reg tog50;
wire tog50$D_IN, tog50$EN;
// register unrollCnt
reg [15 : 0] unrollCnt;
wire [15 : 0] unrollCnt$D_IN;
wire unrollCnt$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wmemiRdReq
reg [31 : 0] wmemiRdReq;
wire [31 : 0] wmemiRdReq$D_IN;
wire wmemiRdReq$EN;
// register wmemiRdResp1
reg [31 : 0] wmemiRdResp1;
wire [31 : 0] wmemiRdResp1$D_IN;
wire wmemiRdResp1$EN;
// register wmemiRdResp2
reg [31 : 0] wmemiRdResp2;
wire [31 : 0] wmemiRdResp2$D_IN;
wire wmemiRdResp2$EN;
// register wmemiWrReq
reg [31 : 0] wmemiWrReq;
wire [31 : 0] wmemiWrReq$D_IN;
wire wmemiWrReq$EN;
// register wmemi_busyWithMessage
reg wmemi_busyWithMessage;
wire wmemi_busyWithMessage$D_IN, wmemi_busyWithMessage$EN;
// register wmemi_dhF_c_r
reg [1 : 0] wmemi_dhF_c_r;
wire [1 : 0] wmemi_dhF_c_r$D_IN;
wire wmemi_dhF_c_r$EN;
// register wmemi_dhF_q_0
reg [145 : 0] wmemi_dhF_q_0;
reg [145 : 0] wmemi_dhF_q_0$D_IN;
wire wmemi_dhF_q_0$EN;
// register wmemi_dhF_q_1
reg [145 : 0] wmemi_dhF_q_1;
reg [145 : 0] wmemi_dhF_q_1$D_IN;
wire wmemi_dhF_q_1$EN;
// register wmemi_errorSticky
reg wmemi_errorSticky;
wire wmemi_errorSticky$D_IN, wmemi_errorSticky$EN;
// register wmemi_isReset_isInReset
reg wmemi_isReset_isInReset;
wire wmemi_isReset_isInReset$D_IN, wmemi_isReset_isInReset$EN;
// register wmemi_operateD
reg wmemi_operateD;
wire wmemi_operateD$D_IN, wmemi_operateD$EN;
// register wmemi_peerIsReady
reg wmemi_peerIsReady;
wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN;
// register wmemi_reqF_c_r
reg [1 : 0] wmemi_reqF_c_r;
wire [1 : 0] wmemi_reqF_c_r$D_IN;
wire wmemi_reqF_c_r$EN;
// register wmemi_reqF_q_0
reg [51 : 0] wmemi_reqF_q_0;
reg [51 : 0] wmemi_reqF_q_0$D_IN;
wire wmemi_reqF_q_0$EN;
// register wmemi_reqF_q_1
reg [51 : 0] wmemi_reqF_q_1;
reg [51 : 0] wmemi_reqF_q_1$D_IN;
wire wmemi_reqF_q_1$EN;
// register wmemi_statusR
reg [7 : 0] wmemi_statusR;
wire [7 : 0] wmemi_statusR$D_IN;
wire wmemi_statusR$EN;
// register wmemi_trafficSticky
reg wmemi_trafficSticky;
wire wmemi_trafficSticky$D_IN, wmemi_trafficSticky$EN;
// register wrtSerAddr
reg [31 : 0] wrtSerAddr;
wire [31 : 0] wrtSerAddr$D_IN;
wire wrtSerAddr$EN;
// register wrtSerPos
reg [1 : 0] wrtSerPos;
wire [1 : 0] wrtSerPos$D_IN;
wire wrtSerPos$EN;
// register wrtSerStage
reg [31 : 0] wrtSerStage;
wire [31 : 0] wrtSerStage$D_IN;
wire wrtSerStage$EN;
// register wrtSerStage_1
reg [31 : 0] wrtSerStage_1;
wire [31 : 0] wrtSerStage_1$D_IN;
wire wrtSerStage_1$EN;
// register wrtSerStage_2
reg [31 : 0] wrtSerStage_2;
wire [31 : 0] wrtSerStage_2$D_IN;
wire wrtSerStage_2$EN;
// register wrtSerStage_3
reg [31 : 0] wrtSerStage_3;
wire [31 : 0] wrtSerStage_3$D_IN;
wire wrtSerStage_3$EN;
// register wrtSerUnroll
reg [15 : 0] wrtSerUnroll;
wire [15 : 0] wrtSerUnroll$D_IN;
wire wrtSerUnroll$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [96 : 0] wsiM_reqFifo_q_0;
reg [96 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [96 : 0] wsiM_reqFifo_q_1;
reg [96 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule mesgRF
wire [63 : 0] mesgRF$D_IN, mesgRF$D_OUT;
wire mesgRF$CLR, mesgRF$DEQ, mesgRF$EMPTY_N, mesgRF$ENQ, mesgRF$FULL_N;
// ports of submodule mesgWF_memory
wire [63 : 0] mesgWF_memory$DIA, mesgWF_memory$DIB, mesgWF_memory$DOB;
wire [11 : 0] mesgWF_memory$ADDRA, mesgWF_memory$ADDRB;
wire mesgWF_memory$ENA,
mesgWF_memory$ENB,
mesgWF_memory$WEA,
mesgWF_memory$WEB;
// ports of submodule metaRF
wire [31 : 0] metaRF$D_IN, metaRF$D_OUT;
wire metaRF$CLR, metaRF$DEQ, metaRF$EMPTY_N, metaRF$ENQ, metaRF$FULL_N;
// ports of submodule metaWF
wire [31 : 0] metaWF$D_IN, metaWF$D_OUT;
wire metaWF$CLR, metaWF$DEQ, metaWF$EMPTY_N, metaWF$ENQ, metaWF$FULL_N;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// ports of submodule wide16Fa
wire [127 : 0] wide16Fa$D_IN, wide16Fa$D_OUT;
wire wide16Fa$CLR,
wide16Fa$DEQ,
wide16Fa$EMPTY_N,
wide16Fa$ENQ,
wide16Fa$FULL_N;
// ports of submodule wide16Fb
wire [127 : 0] wide16Fb$D_IN, wide16Fb$D_OUT;
wire wide16Fb$CLR,
wide16Fb$DEQ,
wide16Fb$EMPTY_N,
wide16Fb$ENQ,
wide16Fb$FULL_N;
// ports of submodule wide16Fc
wire [127 : 0] wide16Fc$D_IN, wide16Fc$D_OUT;
wire wide16Fc$CLR,
wide16Fc$DEQ,
wide16Fc$EMPTY_N,
wide16Fc$ENQ,
wide16Fc$FULL_N;
// ports of submodule wmemi_respF
wire [130 : 0] wmemi_respF$D_IN, wmemi_respF$D_OUT;
wire wmemi_respF$CLR,
wmemi_respF$DEQ,
wmemi_respF$EMPTY_N,
wmemi_respF$ENQ,
wmemi_respF$FULL_N;
// ports of submodule wsiS_reqFifo
wire [96 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_delay_read_req,
WILL_FIRE_RL_delay_read_req,
WILL_FIRE_RL_delay_write_req,
WILL_FIRE_RL_rdSer_begin,
WILL_FIRE_RL_rdSer_body,
WILL_FIRE_RL_rdSer_sync,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wmemi_dhF_both,
WILL_FIRE_RL_wmemi_dhF_decCtr,
WILL_FIRE_RL_wmemi_dhF_incCtr,
WILL_FIRE_RL_wmemi_reqF_both,
WILL_FIRE_RL_wmemi_reqF_decCtr,
WILL_FIRE_RL_wmemi_reqF_incCtr,
WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmwt_mesg_ingress,
WILL_FIRE_RL_wrtSer_begin,
WILL_FIRE_RL_wrtSer_body,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsipass_doMessagePush;
// inputs to muxes for submodule ports
reg [127 : 0] MUX_wide16Fa$enq_1__VAL_1, MUX_wide16Fa$enq_1__VAL_2;
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [145 : 0] MUX_wmemi_dhF_q_0$write_1__VAL_1,
MUX_wmemi_dhF_q_0$write_1__VAL_2,
MUX_wmemi_dhF_q_1$write_1__VAL_1;
wire [96 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [51 : 0] MUX_wmemi_reqF_q_0$write_1__VAL_1,
MUX_wmemi_reqF_q_0$write_1__VAL_2,
MUX_wmemi_reqF_q_1$write_1__VAL_1,
MUX_wmemi_reqF_x_wire$wset_1__VAL_1,
MUX_wmemi_reqF_x_wire$wset_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
wire [31 : 0] MUX_mesgRdCount$write_1__VAL_1,
MUX_mesgWtCount$write_1__VAL_1;
wire [24 : 0] MUX_dlyWordsStored_value$write_1__VAL_2;
wire [22 : 0] MUX_dlyRAG$write_1__VAL_1, MUX_dlyWAG$write_1__VAL_1;
wire [15 : 0] MUX_dlyReadyToWrite_value$write_1__VAL_2,
MUX_rdSerUnroll$write_1__VAL_2,
MUX_unrollCnt$write_1__VAL_1,
MUX_unrollCnt$write_1__VAL_2,
MUX_wrtSerUnroll$write_1__VAL_1;
wire [7 : 0] MUX_dlyReadCredit_value$write_1__VAL_2;
wire [1 : 0] MUX_rdSerPos$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2,
MUX_wmemi_dhF_c_r$write_1__VAL_1,
MUX_wmemi_dhF_c_r$write_1__VAL_2,
MUX_wmemi_reqF_c_r$write_1__VAL_1,
MUX_wmemi_reqF_c_r$write_1__VAL_2,
MUX_wrtSerPos$write_1__VAL_1,
MUX_wrtSerPos$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_mesgRdCount$write_1__SEL_1,
MUX_mesgWtCount$write_1__SEL_1,
MUX_rdSerEmpty$write_1__PSEL_1,
MUX_rdSerEmpty$write_1__SEL_1,
MUX_rdSyncWord$write_1__VAL_1,
MUX_rdSyncWord$write_1__VAL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wide16Fa$enq_1__SEL_1,
MUX_wmemi_dhF_q_0$write_1__SEL_2,
MUX_wmemi_dhF_q_1$write_1__SEL_2,
MUX_wmemi_reqF_q_0$write_1__SEL_2,
MUX_wmemi_reqF_q_1$write_1__SEL_2,
MUX_wrtSerStage$write_1__SEL_1,
MUX_wrtSerStage_1$write_1__SEL_1,
MUX_wrtSerStage_2$write_1__SEL_1,
MUX_wrtSerStage_3$write_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h24065, v__h3739, v__h3914, v__h4058;
reg [31 : 0] g_data__h23399, v__h21048;
reg CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2,
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1;
wire [127 : 0] IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d558,
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528,
x__h19290,
x__h19317,
x__h19946,
x__h19970;
wire [63 : 0] x__h16006, x__h19813;
wire [35 : 0] addr__h20380, addr__h20732;
wire [31 : 0] delayStatus__h23019,
rdat__h23426,
rdat__h23432,
rdat__h23438,
rdat__h23444,
rdat__h23568,
rdat__h23582,
rdat__h23590,
rdat__h23596,
rdat__h23610,
rdat__h23618,
rdat__h23624,
rdat__h23630,
rdat__h23636,
rdat__h23642,
rdat__h23653,
rdat__h23664,
rdat__h23675,
rdat__h23696,
rdat__h23751,
rdat__h23760,
rdat__h23769,
rdat__h23778;
wire [26 : 0] x__h20438, x__h20777;
wire [23 : 0] btm__h18537, x__h23448;
wire [13 : 0] mesgLengthSoFar_73_PLUS_1___d911;
wire [12 : 0] x__h16107;
wire [11 : 0] x_burstLength__h22925;
wire [7 : 0] x_byteEn__h22926;
wire [1 : 0] wrtSerPos_90_PLUS_1___d910;
wire IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543,
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532,
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462,
NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506,
bytesWritten_86_ULT_dlyHoldoffBytes_66___d992,
cyclesPassed_56_ULT_dlyHoldoffCycles_69___d990,
dlyWordsStored_value_17_SLE_0_65_OR_bytesWritt_ETC___d573,
dlyWordsStored_value_17_SLE_0___d991,
dlyWordsStored_value_17_SLT_8388608___d575,
mesgRF_i_notFull__72_AND_NOT_rdSerEmpty_22_23__ETC___d673,
metaRF_i_notFull__21_AND_NOT_rdSerEmpty_22_23__ETC___d632,
wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d593;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[96:94] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[93] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[92] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[91:80] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[79:16] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[15:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = wmemi_reqF_q_0[51:49] ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = wmemi_reqF_q_0[48] ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = wmemi_reqF_q_0[47:12] ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = wmemi_reqF_q_0[11:0] ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = wmemi_dhF_q_0[145] ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = wmemi_dhF_q_0[144] ;
// value method wmemiM0_mData
assign wmemiM0_MData = wmemi_dhF_q_0[143:16] ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = wmemi_dhF_q_0[15:0] ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = !wmemi_isReset_isInReset && wmemi_operateD ;
// submodule mesgRF
SizedFIFO #(.p1width(32'd64),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) mesgRF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(mesgRF$D_IN),
.ENQ(mesgRF$ENQ),
.DEQ(mesgRF$DEQ),
.CLR(mesgRF$CLR),
.D_OUT(mesgRF$D_OUT),
.FULL_N(mesgRF$FULL_N),
.EMPTY_N(mesgRF$EMPTY_N));
// submodule mesgWF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd64),
.MEMSIZE(13'd4096)) mesgWF_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(mesgWF_memory$ADDRA),
.ADDRB(mesgWF_memory$ADDRB),
.DIA(mesgWF_memory$DIA),
.DIB(mesgWF_memory$DIB),
.WEA(mesgWF_memory$WEA),
.WEB(mesgWF_memory$WEB),
.ENA(mesgWF_memory$ENA),
.ENB(mesgWF_memory$ENB),
.DOA(),
.DOB(mesgWF_memory$DOB));
// submodule metaRF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaRF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaRF$D_IN),
.ENQ(metaRF$ENQ),
.DEQ(metaRF$DEQ),
.CLR(metaRF$CLR),
.D_OUT(metaRF$D_OUT),
.FULL_N(metaRF$FULL_N),
.EMPTY_N(metaRF$EMPTY_N));
// submodule metaWF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaWF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaWF$D_IN),
.ENQ(metaWF$ENQ),
.DEQ(metaWF$DEQ),
.CLR(metaWF$CLR),
.D_OUT(metaWF$D_OUT),
.FULL_N(metaWF$FULL_N),
.EMPTY_N(metaWF$EMPTY_N));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// submodule wide16Fa
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fa(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fa$D_IN),
.ENQ(wide16Fa$ENQ),
.DEQ(wide16Fa$DEQ),
.CLR(wide16Fa$CLR),
.D_OUT(wide16Fa$D_OUT),
.FULL_N(wide16Fa$FULL_N),
.EMPTY_N(wide16Fa$EMPTY_N));
// submodule wide16Fb
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fb(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fb$D_IN),
.ENQ(wide16Fb$ENQ),
.DEQ(wide16Fb$DEQ),
.CLR(wide16Fb$CLR),
.D_OUT(wide16Fb$D_OUT),
.FULL_N(wide16Fb$FULL_N),
.EMPTY_N(wide16Fb$EMPTY_N));
// submodule wide16Fc
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fc(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fc$D_IN),
.ENQ(wide16Fc$ENQ),
.DEQ(wide16Fc$DEQ),
.CLR(wide16Fc$CLR),
.D_OUT(wide16Fc$D_OUT),
.FULL_N(wide16Fc$FULL_N),
.EMPTY_N(wide16Fc$EMPTY_N));
// submodule wmemi_respF
FIFO2 #(.width(32'd131), .guarded(32'd1)) wmemi_respF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmemi_respF$D_IN),
.ENQ(wmemi_respF$ENQ),
.DEQ(wmemi_respF$DEQ),
.CLR(wmemi_respF$CLR),
.D_OUT(wmemi_respF$D_OUT),
.FULL_N(wmemi_respF$FULL_N),
.EMPTY_N(wmemi_respF$EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd97),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_rdSer_sync
assign WILL_FIRE_RL_rdSer_sync =
wci_wslv_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 && rdSyncWord ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_wsipass_doMessagePush
assign WILL_FIRE_RL_wsipass_doMessagePush =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h0 ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wrtSer_begin
assign WILL_FIRE_RL_wrtSer_begin =
metaWF$EMPTY_N &&
NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll == 16'd0 ;
// rule RL_delay_write_req
assign WILL_FIRE_RL_delay_write_req =
wmemi_reqF_c_r != 2'd2 && wmemi_dhF_c_r != 2'd2 &&
wmemi_operateD &&
wmemi_peerIsReady &&
wide16Fa$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
dlyWordsStored_value_17_SLE_0_65_OR_bytesWritt_ETC___d573 &&
dlyWordsStored_value_17_SLT_8388608___d575 ;
// rule RL_delay_read_req
assign CAN_FIRE_RL_delay_read_req =
wmemi_reqF_c_r != 2'd2 && wmemi_operateD && wmemi_peerIsReady &&
wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d593 &&
(dlyReadCredit_value ^ 8'h80) > 8'd128 &&
wsiM_reqFifo_c_r != 2'd2 ;
assign WILL_FIRE_RL_delay_read_req =
CAN_FIRE_RL_delay_read_req && !WILL_FIRE_RL_delay_write_req ;
// rule RL_wmwt_mesg_ingress
assign WILL_FIRE_RL_wmwt_mesg_ingress =
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462 &&
wsiS_reqFifo$EMPTY_N &&
(!wsiS_reqFifo$D_OUT[93] || metaWF$FULL_N) &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
// rule RL_rdSer_begin
assign WILL_FIRE_RL_rdSer_begin =
metaRF_i_notFull__21_AND_NOT_rdSerEmpty_22_23__ETC___d632 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll == 16'd0 &&
!rdSyncWord ;
// rule RL_rdSer_body
assign WILL_FIRE_RL_rdSer_body =
mesgRF_i_notFull__72_AND_NOT_rdSerEmpty_22_23__ETC___d673 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll != 16'd0 &&
!rdSyncWord ;
// rule RL_wmrd_mesgBegin
assign WILL_FIRE_RL_wmrd_mesgBegin =
metaRF$EMPTY_N && wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
unrollCnt == 16'd0 ;
// rule RL_wmrd_mesgBodyResponse
assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
wsiM_reqFifo_c_r != 2'd2 && mesgRF$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
unrollCnt != 16'd0 ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
// rule RL_wmemi_reqF_incCtr
assign WILL_FIRE_RL_wmemi_reqF_incCtr =
((wmemi_reqF_c_r == 2'd0) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd1 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_enqueueing$whas &&
!wmemi_reqF_dequeueing$whas ;
// rule RL_wmemi_reqF_decCtr
assign WILL_FIRE_RL_wmemi_reqF_decCtr =
wmemi_reqF_dequeueing$whas && !wmemi_reqF_enqueueing$whas ;
// rule RL_wmemi_reqF_both
assign WILL_FIRE_RL_wmemi_reqF_both =
((wmemi_reqF_c_r == 2'd1) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd2 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_dequeueing$whas &&
wmemi_reqF_enqueueing$whas ;
// rule RL_wmemi_dhF_incCtr
assign WILL_FIRE_RL_wmemi_dhF_incCtr =
((wmemi_dhF_c_r == 2'd0) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd1 || WILL_FIRE_RL_delay_write_req) &&
WILL_FIRE_RL_delay_write_req &&
!wmemi_dhF_dequeueing$whas ;
// rule RL_wmemi_dhF_decCtr
assign WILL_FIRE_RL_wmemi_dhF_decCtr =
wmemi_dhF_dequeueing$whas && !WILL_FIRE_RL_delay_write_req ;
// rule RL_wmemi_dhF_both
assign WILL_FIRE_RL_wmemi_dhF_both =
((wmemi_dhF_c_r == 2'd1) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd2 || WILL_FIRE_RL_delay_write_req) &&
wmemi_dhF_dequeueing$whas &&
WILL_FIRE_RL_delay_write_req ;
// rule RL_wrtSer_body
assign WILL_FIRE_RL_wrtSer_body =
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532 &&
IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll != 16'd0 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[96:94] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq || wsiS_reqFifo_r_deq$whas ;
// inputs to muxes for submodule ports
assign MUX_mesgRdCount$write_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
assign MUX_mesgWtCount$write_1__SEL_1 =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[93] ;
assign MUX_rdSerEmpty$write_1__PSEL_1 =
WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin ;
assign MUX_rdSerEmpty$write_1__SEL_1 =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_wide16Fa$enq_1__SEL_1 =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ;
assign MUX_wmemi_dhF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ;
assign MUX_wmemi_dhF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ;
assign MUX_wmemi_reqF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ;
assign MUX_wmemi_reqF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ;
assign MUX_wrtSerStage$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ;
assign MUX_wrtSerStage_1$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ;
assign MUX_wrtSerStage_2$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ;
assign MUX_wrtSerStage_3$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_dlyRAG$write_1__VAL_1 = dlyRAG + 23'd1 ;
assign MUX_dlyReadCredit_value$write_1__VAL_2 =
dlyReadCredit_value +
(WILL_FIRE_RL_delay_read_req ? 8'd255 : 8'd0) +
(dlyReadCredit_acc_v2$whas ? 8'd1 : 8'd0) ;
assign MUX_dlyReadyToWrite_value$write_1__VAL_2 =
dlyReadyToWrite_value +
(dlyReadyToWrite_acc_v1$whas ? 16'd1 : 16'd0) +
(WILL_FIRE_RL_delay_write_req ? 16'd65535 : 16'd0) ;
assign MUX_dlyWAG$write_1__VAL_1 = dlyWAG + 23'd1 ;
assign MUX_dlyWordsStored_value$write_1__VAL_2 =
dlyWordsStored_value +
(WILL_FIRE_RL_delay_write_req ? 25'd1 : 25'd0) +
(WILL_FIRE_RL_delay_read_req ? 25'd33554431 : 25'd0) ;
assign MUX_mesgRdCount$write_1__VAL_1 = mesgRdCount + 32'd1 ;
assign MUX_mesgWtCount$write_1__VAL_1 = mesgWtCount + 32'd1 ;
assign MUX_rdSerPos$write_1__VAL_1 = rdSerPos + 2'd1 ;
assign MUX_rdSerUnroll$write_1__VAL_2 = rdSerUnroll - 16'd1 ;
assign MUX_rdSyncWord$write_1__VAL_1 =
rdSerPos != 2'd3 && v__h21048[23:0] == 24'd0 ;
assign MUX_rdSyncWord$write_1__VAL_2 =
rdSerPos != 2'd3 && rdSerUnroll == 16'd1 ;
assign MUX_unrollCnt$write_1__VAL_1 =
(metaRF$D_OUT[23:0] == 24'd0) ? 16'd1 : metaRF$D_OUT[18:3] ;
assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h23399 } ;
always@(wrtSerPos or
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528 or
x__h19290 or x__h19317)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_1 = x__h19290;
2'd1: MUX_wide16Fa$enq_1__VAL_1 = x__h19317;
default: MUX_wide16Fa$enq_1__VAL_1 =
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528;
endcase
end
always@(wrtSerPos or
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d558 or
x__h19946 or x__h19970)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_2 = x__h19946;
2'd1: MUX_wide16Fa$enq_1__VAL_2 = x__h19970;
default: MUX_wide16Fa$enq_1__VAL_2 =
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d558;
endcase
end
assign MUX_wmemi_dhF_c_r$write_1__VAL_1 = wmemi_dhF_c_r + 2'd1 ;
assign MUX_wmemi_dhF_c_r$write_1__VAL_2 = wmemi_dhF_c_r - 2'd1 ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_1 =
(wmemi_dhF_c_r == 2'd1) ?
MUX_wmemi_dhF_q_0$write_1__VAL_2 :
wmemi_dhF_q_1 ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_2 =
{ 2'd3, wide16Fa$D_OUT, 16'd65535 } ;
assign MUX_wmemi_dhF_q_1$write_1__VAL_1 =
(wmemi_dhF_c_r == 2'd2) ?
MUX_wmemi_dhF_q_0$write_1__VAL_2 :
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_1 = wmemi_reqF_c_r + 2'd1 ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_2 = wmemi_reqF_c_r - 2'd1 ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_1 =
(wmemi_reqF_c_r == 2'd1) ?
MUX_wmemi_reqF_q_0$write_1__VAL_2 :
wmemi_reqF_q_1 ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_2 =
WILL_FIRE_RL_delay_write_req ?
MUX_wmemi_reqF_x_wire$wset_1__VAL_1 :
MUX_wmemi_reqF_x_wire$wset_1__VAL_2 ;
assign MUX_wmemi_reqF_q_1$write_1__VAL_1 =
(wmemi_reqF_c_r == 2'd2) ?
MUX_wmemi_reqF_q_0$write_1__VAL_2 :
52'h0AAAAAAAAAAAA ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_1 = { 4'd3, addr__h20380, 12'd1 } ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_2 = { 4'd5, addr__h20732, 12'd1 } ;
assign MUX_wrtSerPos$write_1__VAL_1 =
(metaWF$D_OUT[23:0] == 24'd0) ?
2'd0 :
wrtSerPos_90_PLUS_1___d910 ;
assign MUX_wrtSerPos$write_1__VAL_2 =
(wrtSerUnroll == 16'd1) ? 2'd0 : wrtSerPos_90_PLUS_1___d910 ;
assign MUX_wrtSerUnroll$write_1__VAL_1 = wrtSerUnroll - 16'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
WILL_FIRE_RL_wmrd_mesgBodyResponse ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
97'h00000AAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unrollCnt == 16'd1,
1'd1,
x_burstLength__h22925,
mesgRF$D_OUT,
x_byteEn__h22926,
readMeta[31:24] } ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ;
assign wci_wslv_respF_x_wire$whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'b0 ;
assign wci_wslv_sFlagReg_1$whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wmemi_reqF_x_wire$wget = MUX_wmemi_reqF_q_0$write_1__VAL_2 ;
assign wmemi_reqF_x_wire$whas =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_delay_read_req ;
assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_2 ;
assign wmemi_dhF_x_wire$whas = WILL_FIRE_RL_delay_write_req ;
assign wmemi_wmemiResponse$wget =
{ wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ;
assign wmemi_wmemiResponse$whas = 1'd1 ;
assign wmemi_sCmdAccept_w$wget = 1'd1 ;
assign wmemi_sCmdAccept_w$whas = wmemiM0_SCmdAccept ;
assign wmemi_sDataAccept_w$wget = 1'd1 ;
assign wmemi_sDataAccept_w$whas = wmemiM0_SDataAccept ;
assign wmemi_operateD_1$wget = 1'd1 ;
assign wmemi_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wmemi_peerIsReady_1$wget = 1'b0 ;
assign wmemi_peerIsReady_1$whas = 1'b0 ;
assign mesgWF_wDataIn$wget = wsiS_reqFifo$D_OUT[79:16] ;
assign mesgWF_wDataIn$whas = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign mesgWF_wDataOut$wget =
(mesgWF_rCache[77] && mesgWF_rCache[76:64] == mesgWF_rRdPtr) ?
mesgWF_rCache[63:0] :
mesgWF_memory$DOB ;
assign mesgWF_wDataOut$whas = 1'd1 ;
assign dlyWordsStored_acc_v1$wget = 25'd1 ;
assign dlyWordsStored_acc_v1$whas = WILL_FIRE_RL_delay_write_req ;
assign dlyWordsStored_acc_v2$wget = 25'd33554431 ;
assign dlyWordsStored_acc_v2$whas = WILL_FIRE_RL_delay_read_req ;
assign dlyReadCredit_acc_v1$wget = 8'd255 ;
assign dlyReadCredit_acc_v1$whas = WILL_FIRE_RL_delay_read_req ;
assign dlyReadCredit_acc_v2$wget = 8'd1 ;
assign dlyReadCredit_acc_v2$whas =
wide16Fc$FULL_N && wide16Fb$EMPTY_N && wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign dlyReadyToWrite_acc_v1$wget = 16'd1 ;
assign dlyReadyToWrite_acc_v1$whas =
WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ;
assign dlyReadyToWrite_acc_v2$wget = 16'd65535 ;
assign dlyReadyToWrite_acc_v2$whas = WILL_FIRE_RL_delay_write_req ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wmemi_Em_sResp_w$wget = wmemiM0_SResp ;
assign wmemi_Em_sResp_w$whas = 1'd1 ;
assign wmemi_Em_sData_w$wget = wmemiM0_SData ;
assign wmemi_Em_sData_w$whas = 1'd1 ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_wmrd_mesgBodyResponse ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wmemi_reqF_enqueueing$whas =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_delay_write_req ;
assign wmemi_reqF_dequeueing$whas =
wmemiM0_SCmdAccept && wmemi_reqF_c_r != 2'd0 ;
assign wmemi_dhF_enqueueing$whas = WILL_FIRE_RL_delay_write_req ;
assign wmemi_dhF_dequeueing$whas =
wmemiM0_SDataAccept && wmemi_dhF_c_r != 2'd0 ;
assign mesgWF_pwDequeue$whas = WILL_FIRE_RL_wrtSer_body ;
assign mesgWF_pwEnqueue$whas = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wmemi_Em_sRespLast_w$whas = wmemiM0_SRespLast ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register bytesRead
assign bytesRead$D_IN = bytesRead + 32'd8 ;
assign bytesRead$EN =
MUX_rdSerEmpty$write_1__PSEL_1 && bytesRead != 32'hFFFFFFFF ;
// register bytesThisMessage
assign bytesThisMessage$D_IN = btm__h18537 ;
assign bytesThisMessage$EN = MUX_mesgWtCount$write_1__SEL_1 ;
// register bytesWritten
assign bytesWritten$D_IN = bytesWritten + 32'd8 ;
assign bytesWritten$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && bytesWritten < 32'hFFFFFFF7 ;
// register cyclesPassed
assign cyclesPassed$D_IN = cyclesPassed + 32'd1 ;
assign cyclesPassed$EN = wsiS_statusR[0] && cyclesPassed != 32'hFFFFFFFF ;
// register dlyCtrl
assign dlyCtrl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:32] == 32'h0 ;
// register dlyHoldoffBytes
assign dlyHoldoffBytes$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyHoldoffBytes$EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF$D_OUT[63:32] == 32'h00000004 ;
// register dlyHoldoffCycles
assign dlyHoldoffCycles$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyHoldoffCycles$EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF$D_OUT[63:32] == 32'h00000008 ;
// register dlyRAG
assign dlyRAG$D_IN =
WILL_FIRE_RL_delay_read_req ? MUX_dlyRAG$write_1__VAL_1 : 23'd0 ;
assign dlyRAG$EN =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyRdOpOther
assign dlyRdOpOther$D_IN = dlyRdOpOther + 32'd1 ;
assign dlyRdOpOther$EN =
WILL_FIRE_RL_rdSer_begin && v__h21048[31:24] != 8'd0 ;
// register dlyRdOpZero
assign dlyRdOpZero$D_IN = dlyRdOpZero + 32'd1 ;
assign dlyRdOpZero$EN =
WILL_FIRE_RL_rdSer_begin && v__h21048[31:24] == 8'd0 ;
// register dlyReadCredit_value
assign dlyReadCredit_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
8'd12 :
MUX_dlyReadCredit_value$write_1__VAL_2 ;
assign dlyReadCredit_value$EN = 1'b1 ;
// register dlyReadyToWrite_value
assign dlyReadyToWrite_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
16'd0 :
MUX_dlyReadyToWrite_value$write_1__VAL_2 ;
assign dlyReadyToWrite_value$EN = 1'b1 ;
// register dlyWAG
assign dlyWAG$D_IN =
WILL_FIRE_RL_delay_write_req ?
MUX_dlyWAG$write_1__VAL_1 :
23'd0 ;
assign dlyWAG$EN =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyWordsStored_value
assign dlyWordsStored_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
25'd0 :
MUX_dlyWordsStored_value$write_1__VAL_2 ;
assign dlyWordsStored_value$EN = 1'b1 ;
// register mesgLengthSoFar
assign mesgLengthSoFar$D_IN =
wsiS_reqFifo$D_OUT[93] ?
14'd0 :
mesgLengthSoFar_73_PLUS_1___d911 ;
assign mesgLengthSoFar$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgRdCount
assign mesgRdCount$D_IN =
MUX_mesgRdCount$write_1__SEL_1 ?
MUX_mesgRdCount$write_1__VAL_1 :
32'd0 ;
assign mesgRdCount$EN =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgWF_rCache
assign mesgWF_rCache$D_IN = { 1'd1, mesgWF_rWrPtr, x__h16006 } ;
assign mesgWF_rCache$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgWF_rRdPtr
assign mesgWF_rRdPtr$D_IN = x__h16107 ;
assign mesgWF_rRdPtr$EN = WILL_FIRE_RL_wrtSer_body ;
// register mesgWF_rWrPtr
assign mesgWF_rWrPtr$D_IN = mesgWF_rWrPtr + 13'd1 ;
assign mesgWF_rWrPtr$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgWtCount
assign mesgWtCount$D_IN =
MUX_mesgWtCount$write_1__SEL_1 ?
MUX_mesgWtCount$write_1__VAL_1 :
32'd0 ;
assign mesgWtCount$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[93] ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register rdSerAddr
assign rdSerAddr$D_IN = 32'h0 ;
assign rdSerAddr$EN = 1'b0 ;
// register rdSerEmpty
assign rdSerEmpty$D_IN = !MUX_rdSerEmpty$write_1__SEL_1 ;
assign rdSerEmpty$EN =
(WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin) &&
(rdSerEmpty || rdSerPos == 2'd0) ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerMeta
assign rdSerMeta$D_IN = v__h21048 ;
assign rdSerMeta$EN = WILL_FIRE_RL_rdSer_begin ;
// register rdSerPos
assign rdSerPos$D_IN =
MUX_rdSerEmpty$write_1__PSEL_1 ?
MUX_rdSerPos$write_1__VAL_1 :
2'd0 ;
assign rdSerPos$EN =
WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerStage
assign rdSerStage$D_IN = wide16Fc$D_OUT[31:0] ;
assign rdSerStage$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_1
assign rdSerStage_1$D_IN = wide16Fc$D_OUT[63:32] ;
assign rdSerStage_1$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_2
assign rdSerStage_2$D_IN = wide16Fc$D_OUT[95:64] ;
assign rdSerStage_2$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_3
assign rdSerStage_3$D_IN = wide16Fc$D_OUT[127:96] ;
assign rdSerStage_3$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerUnroll
assign rdSerUnroll$D_IN =
WILL_FIRE_RL_rdSer_begin ?
v__h21048[18:3] :
MUX_rdSerUnroll$write_1__VAL_2 ;
assign rdSerUnroll$EN =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ;
// register rdSyncWord
always@(WILL_FIRE_RL_rdSer_begin or
MUX_rdSyncWord$write_1__VAL_1 or
WILL_FIRE_RL_rdSer_body or
MUX_rdSyncWord$write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rdSer_begin:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_1;
WILL_FIRE_RL_rdSer_body:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_2;
WILL_FIRE_RL_rdSer_sync: rdSyncWord$D_IN = 1'd0;
default: rdSyncWord$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign rdSyncWord$EN =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ||
WILL_FIRE_RL_rdSer_sync ;
// register readMeta
assign readMeta$D_IN = metaRF$D_OUT ;
assign readMeta$EN = WILL_FIRE_RL_wmrd_mesgBegin ;
// register tog50
assign tog50$D_IN = !tog50 ;
assign tog50$EN = wci_wslv_cState == 3'd2 ;
// register unrollCnt
assign unrollCnt$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
!MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
MUX_wci_wslv_respF_q_0$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
MUX_wci_wslv_respF_q_0$write_1__SEL_2:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_1 or
MUX_wci_wslv_respF_q_1$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1;
MUX_wci_wslv_respF_q_1$write_1__SEL_2:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = 1'b0 ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wmemiRdReq
assign wmemiRdReq$D_IN = wmemiRdReq + 32'd1 ;
assign wmemiRdReq$EN = WILL_FIRE_RL_delay_read_req ;
// register wmemiRdResp1
assign wmemiRdResp1$D_IN = wmemiRdResp1 + 32'd1 ;
assign wmemiRdResp1$EN =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
// register wmemiRdResp2
assign wmemiRdResp2$D_IN = wmemiRdResp2 + 32'd1 ;
assign wmemiRdResp2$EN = dlyReadCredit_acc_v2$whas ;
// register wmemiWrReq
assign wmemiWrReq$D_IN = wmemiWrReq + 32'd1 ;
assign wmemiWrReq$EN = WILL_FIRE_RL_delay_write_req ;
// register wmemi_busyWithMessage
assign wmemi_busyWithMessage$D_IN = 1'b0 ;
assign wmemi_busyWithMessage$EN = 1'b0 ;
// register wmemi_dhF_c_r
assign wmemi_dhF_c_r$D_IN =
WILL_FIRE_RL_wmemi_dhF_incCtr ?
MUX_wmemi_dhF_c_r$write_1__VAL_1 :
MUX_wmemi_dhF_c_r$write_1__VAL_2 ;
assign wmemi_dhF_c_r$EN =
WILL_FIRE_RL_wmemi_dhF_incCtr || WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_0
always@(WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_0$write_1__VAL_1 or
MUX_wmemi_dhF_q_0$write_1__SEL_2 or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
MUX_wmemi_dhF_q_0$write_1__SEL_2:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0$D_IN = wmemi_dhF_q_1;
default: wmemi_dhF_q_0$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_0$EN =
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_1
always@(WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_1$write_1__VAL_1 or
MUX_wmemi_dhF_q_1$write_1__SEL_2 or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_1;
MUX_wmemi_dhF_q_1$write_1__SEL_2:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr:
wmemi_dhF_q_1$D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: wmemi_dhF_q_1$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_1$EN =
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_errorSticky
assign wmemi_errorSticky$D_IN = 1'b0 ;
assign wmemi_errorSticky$EN = 1'b0 ;
// register wmemi_isReset_isInReset
assign wmemi_isReset_isInReset$D_IN = 1'd0 ;
assign wmemi_isReset_isInReset$EN = wmemi_isReset_isInReset ;
// register wmemi_operateD
assign wmemi_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wmemi_operateD$EN = 1'd1 ;
// register wmemi_peerIsReady
assign wmemi_peerIsReady$D_IN = 1'b1 ;
assign wmemi_peerIsReady$EN = 1'd1 ;
// register wmemi_reqF_c_r
assign wmemi_reqF_c_r$D_IN =
WILL_FIRE_RL_wmemi_reqF_incCtr ?
MUX_wmemi_reqF_c_r$write_1__VAL_1 :
MUX_wmemi_reqF_c_r$write_1__VAL_2 ;
assign wmemi_reqF_c_r$EN =
WILL_FIRE_RL_wmemi_reqF_incCtr ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_reqF_q_0
always@(WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_0$write_1__VAL_1 or
MUX_wmemi_reqF_q_0$write_1__SEL_2 or
MUX_wmemi_reqF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_1;
MUX_wmemi_reqF_q_0$write_1__SEL_2:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_0$D_IN = wmemi_reqF_q_1;
default: wmemi_reqF_q_0$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_0$EN =
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_reqF_q_1
always@(WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_1$write_1__VAL_1 or
MUX_wmemi_reqF_q_1$write_1__SEL_2 or
MUX_wmemi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_1$write_1__VAL_1;
MUX_wmemi_reqF_q_1$write_1__SEL_2:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1$D_IN = 52'h0AAAAAAAAAAAA;
default: wmemi_reqF_q_1$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_1$EN =
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_statusR
assign wmemi_statusR$D_IN =
{ wmemi_isReset_isInReset,
!wmemi_peerIsReady,
!wmemi_operateD,
wmemi_errorSticky,
3'd0,
wmemi_trafficSticky } ;
assign wmemi_statusR$EN = 1'd1 ;
// register wmemi_trafficSticky
assign wmemi_trafficSticky$D_IN = 1'd1 ;
assign wmemi_trafficSticky$EN = wmemiM0_SCmdAccept ;
// register wrtSerAddr
assign wrtSerAddr$D_IN = 32'h0 ;
assign wrtSerAddr$EN = 1'b0 ;
// register wrtSerPos
assign wrtSerPos$D_IN =
WILL_FIRE_RL_wrtSer_begin ?
MUX_wrtSerPos$write_1__VAL_1 :
MUX_wrtSerPos$write_1__VAL_2 ;
assign wrtSerPos$EN =
WILL_FIRE_RL_wrtSer_begin || WILL_FIRE_RL_wrtSer_body ;
// register wrtSerStage
assign wrtSerStage$D_IN =
MUX_wrtSerStage$write_1__SEL_1 ? x__h19813[31:0] : metaWF$D_OUT ;
assign wrtSerStage$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd0 ;
// register wrtSerStage_1
assign wrtSerStage_1$D_IN =
MUX_wrtSerStage_1$write_1__SEL_1 ?
x__h19813[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_1$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd1 ;
// register wrtSerStage_2
assign wrtSerStage_2$D_IN =
MUX_wrtSerStage_2$write_1__SEL_1 ?
x__h19813[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_2$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd2 ;
// register wrtSerStage_3
assign wrtSerStage_3$D_IN =
MUX_wrtSerStage_3$write_1__SEL_1 ?
x__h19813[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_3$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd3 ;
// register wrtSerUnroll
assign wrtSerUnroll$D_IN =
WILL_FIRE_RL_wrtSer_body ?
MUX_wrtSerUnroll$write_1__VAL_1 :
metaWF$D_OUT[18:3] ;
assign wrtSerUnroll$EN = dlyReadyToWrite_acc_v1$whas ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[93]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[93] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[93] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[93]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'b0 ;
assign wsiS_errorSticky$EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[93] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[93] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[93] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq$whas ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[93] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule mesgRF
assign mesgRF$D_IN = { 32'd0, v__h21048 } ;
assign mesgRF$ENQ = WILL_FIRE_RL_rdSer_body ;
assign mesgRF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ;
assign mesgRF$CLR = 1'b0 ;
// submodule mesgWF_memory
assign mesgWF_memory$ADDRA = mesgWF_rWrPtr[11:0] ;
assign mesgWF_memory$ADDRB =
WILL_FIRE_RL_wrtSer_body ?
x__h16107[11:0] :
mesgWF_rRdPtr[11:0] ;
assign mesgWF_memory$DIA = x__h16006 ;
assign mesgWF_memory$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign mesgWF_memory$WEA = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign mesgWF_memory$WEB = 1'd0 ;
assign mesgWF_memory$ENA = 1'd1 ;
assign mesgWF_memory$ENB = 1'd1 ;
// submodule metaRF
assign metaRF$D_IN = v__h21048 ;
assign metaRF$ENQ = WILL_FIRE_RL_rdSer_begin ;
assign metaRF$DEQ = WILL_FIRE_RL_wmrd_mesgBegin ;
assign metaRF$CLR = 1'b0 ;
// submodule metaWF
assign metaWF$D_IN = { wsiS_reqFifo$D_OUT[7:0], btm__h18537 } ;
assign metaWF$ENQ = MUX_mesgWtCount$write_1__SEL_1 ;
assign metaWF$DEQ = WILL_FIRE_RL_wrtSer_begin ;
assign metaWF$CLR = 1'b0 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// submodule wide16Fa
assign wide16Fa$D_IN =
MUX_wide16Fa$enq_1__SEL_1 ?
MUX_wide16Fa$enq_1__VAL_1 :
MUX_wide16Fa$enq_1__VAL_2 ;
assign wide16Fa$ENQ =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ||
WILL_FIRE_RL_wrtSer_body &&
(wrtSerPos == 2'd3 || wrtSerUnroll == 16'd1) ;
assign wide16Fa$DEQ = WILL_FIRE_RL_delay_write_req ;
assign wide16Fa$CLR = 1'b0 ;
// submodule wide16Fb
assign wide16Fb$D_IN = wmemi_respF$D_OUT[127:0] ;
assign wide16Fb$ENQ =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign wide16Fb$DEQ = dlyReadCredit_acc_v2$whas ;
assign wide16Fb$CLR = 1'b0 ;
// submodule wide16Fc
assign wide16Fc$D_IN = wide16Fb$D_OUT ;
assign wide16Fc$ENQ = dlyReadCredit_acc_v2$whas ;
assign wide16Fc$DEQ =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign wide16Fc$CLR = 1'b0 ;
// submodule wmemi_respF
assign wmemi_respF$D_IN = wmemi_wmemiResponse$wget ;
assign wmemi_respF$ENQ =
wmemi_respF$FULL_N && wmemi_operateD && wmemi_peerIsReady &&
wmemi_wmemiResponse$wget[130:129] != 2'd0 ;
assign wmemi_respF$DEQ =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign wmemi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543 =
CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2 &&
(wrtSerPos != 2'd3 && wrtSerUnroll != 16'd1 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1) ;
assign IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d558 =
{ (wrtSerPos == 2'd2) ? 32'h0 : x__h19813[31:0],
(wrtSerPos == 2'd2) ? x__h19813[31:0] : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528 =
{ (wrtSerPos == 2'd2) ? 32'h0 : metaWF$D_OUT,
(wrtSerPos == 2'd2) ? metaWF$D_OUT : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532 =
mesgWF_rRdPtr != mesgWF_rWrPtr ;
assign NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462 =
mesgWF_rRdPtr + 13'd2048 != mesgWF_rWrPtr ;
assign NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506 =
wrtSerPos != 2'd3 && metaWF$D_OUT[23:0] != 24'd0 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 ;
assign addr__h20380 = { 9'd0, x__h20438 } ;
assign addr__h20732 = { 9'd0, x__h20777 } ;
assign btm__h18537 =
{ wsiS_reqFifo$D_OUT[92] ?
{ 9'd0, wsiS_reqFifo$D_OUT[91:80] } :
{ 7'd0, mesgLengthSoFar_73_PLUS_1___d911 },
3'd0 } ;
assign bytesWritten_86_ULT_dlyHoldoffBytes_66___d992 =
bytesWritten < dlyHoldoffBytes ;
assign cyclesPassed_56_ULT_dlyHoldoffCycles_69___d990 =
cyclesPassed < dlyHoldoffCycles ;
assign delayStatus__h23019 =
{ 14'h0,
!dlyWordsStored_value_17_SLE_0___d991 &&
!bytesWritten_86_ULT_dlyHoldoffBytes_66___d992 &&
!cyclesPassed_56_ULT_dlyHoldoffCycles_69___d990,
dlyWordsStored_value_17_SLE_0_65_OR_bytesWritt_ETC___d573,
dlyWordsStored_value_17_SLT_8388608___d575,
wsiM_reqFifo_c_r != 2'd2,
metaWF$FULL_N,
metaWF$EMPTY_N,
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462,
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532,
metaRF$FULL_N,
metaRF$EMPTY_N,
mesgRF$FULL_N,
mesgRF$EMPTY_N,
wide16Fa$FULL_N,
wide16Fa$EMPTY_N,
wide16Fb$FULL_N,
wide16Fb$EMPTY_N,
wide16Fc$FULL_N,
wide16Fc$EMPTY_N } ;
assign dlyWordsStored_value_17_SLE_0_65_OR_bytesWritt_ETC___d573 =
dlyWordsStored_value_17_SLE_0___d991 ||
bytesWritten_86_ULT_dlyHoldoffBytes_66___d992 ||
cyclesPassed_56_ULT_dlyHoldoffCycles_69___d990 ||
wsiM_reqFifo_c_r == 2'd2 ||
tog50 ;
assign dlyWordsStored_value_17_SLE_0___d991 =
(dlyWordsStored_value ^ 25'h1000000) <= 25'd16777216 ;
assign dlyWordsStored_value_17_SLT_8388608___d575 =
(dlyWordsStored_value ^ 25'h1000000) < 25'd25165824 ;
assign mesgLengthSoFar_73_PLUS_1___d911 = mesgLengthSoFar + 14'd1 ;
assign mesgRF_i_notFull__72_AND_NOT_rdSerEmpty_22_23__ETC___d673 =
mesgRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign metaRF_i_notFull__21_AND_NOT_rdSerEmpty_22_23__ETC___d632 =
metaRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign rdat__h23426 = hasDebugLogic ? mesgWtCount : 32'd0 ;
assign rdat__h23432 = hasDebugLogic ? mesgRdCount : 32'd0 ;
assign rdat__h23438 = hasDebugLogic ? bytesWritten : 32'd0 ;
assign rdat__h23444 = hasDebugLogic ? { 8'd0, x__h23448 } : 32'd0 ;
assign rdat__h23568 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h23582 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h23590 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h23596 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h23610 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h23618 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h23624 = hasDebugLogic ? wmemiWrReq : 32'd0 ;
assign rdat__h23630 = hasDebugLogic ? wmemiRdReq : 32'd0 ;
assign rdat__h23636 = hasDebugLogic ? wmemiRdResp1 : 32'd0 ;
assign rdat__h23642 =
hasDebugLogic ?
{ {7{dlyWordsStored_value[24]}}, dlyWordsStored_value } :
32'd0 ;
assign rdat__h23653 =
hasDebugLogic ?
{ {24{dlyReadCredit_value[7]}}, dlyReadCredit_value } :
32'd0 ;
assign rdat__h23664 = hasDebugLogic ? { 9'd0, dlyWAG } : 32'd0 ;
assign rdat__h23675 = hasDebugLogic ? { 9'd0, dlyRAG } : 32'd0 ;
assign rdat__h23696 = hasDebugLogic ? wmemiRdResp2 : 32'd0 ;
assign rdat__h23751 =
{ {16{dlyReadyToWrite_value[15]}}, dlyReadyToWrite_value } ;
assign rdat__h23760 = { 16'd0, wrtSerUnroll } ;
assign rdat__h23769 = { 8'd0, bytesThisMessage } ;
assign rdat__h23778 = { 18'd0, mesgLengthSoFar } ;
assign wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d593 =
wci_wslv_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 &&
!dlyWordsStored_value_17_SLE_0___d991 &&
!bytesWritten_86_ULT_dlyHoldoffBytes_66___d992 &&
!cyclesPassed_56_ULT_dlyHoldoffCycles_69___d990 ;
assign wrtSerPos_90_PLUS_1___d910 = wrtSerPos + 2'd1 ;
assign x__h16006 =
WILL_FIRE_RL_wmwt_mesg_ingress ?
wsiS_reqFifo$D_OUT[79:16] :
64'd0 ;
assign x__h16107 = mesgWF_rRdPtr + 13'd1 ;
assign x__h19290 = { 96'd0, metaWF$D_OUT } ;
assign x__h19317 = { 64'd0, metaWF$D_OUT, wrtSerStage } ;
assign x__h19813 = mesgWF_wDataOut$wget ;
assign x__h19946 = { 96'd0, x__h19813[31:0] } ;
assign x__h19970 = { 64'd0, x__h19813[31:0], wrtSerStage } ;
assign x__h20438 = { dlyWAG, 4'h0 } ;
assign x__h20777 = { dlyRAG, 4'h0 } ;
assign x__h23448 = { wmemi_statusR, wsiS_statusR, wsiM_statusR } ;
assign x_burstLength__h22925 =
(readMeta[23:0] == 24'd0) ? 12'd1 : readMeta[14:3] ;
assign x_byteEn__h22926 = (readMeta[23:0] == 24'd0) ? 8'd0 : 8'd255 ;
always@(rdSerPos or
rdSerStage_3 or wide16Fc$D_OUT or rdSerStage_1 or rdSerStage_2)
begin
case (rdSerPos)
2'd0: v__h21048 = wide16Fc$D_OUT[31:0];
2'd1: v__h21048 = rdSerStage_1;
2'd2: v__h21048 = rdSerStage_2;
2'd3: v__h21048 = rdSerStage_3;
endcase
end
always@(wrtSerPos or wide16Fa$FULL_N)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 =
wide16Fa$FULL_N;
2'd3:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 =
wrtSerPos != 2'd3 || wide16Fa$FULL_N;
endcase
end
always@(wrtSerPos)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2, 2'd3: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2 = 1'd1;
endcase
end
always@(wci_wslv_reqF$D_OUT or
dlyCtrl or
dlyHoldoffBytes or
dlyHoldoffCycles or
rdat__h23426 or
rdat__h23432 or
rdat__h23438 or
rdat__h23444 or
rdat__h23568 or
rdat__h23582 or
rdat__h23590 or
rdat__h23596 or
rdat__h23610 or
rdat__h23618 or
rdat__h23624 or
rdat__h23630 or
rdat__h23636 or
rdat__h23642 or
rdat__h23653 or
rdat__h23664 or
rdat__h23675 or
dlyRdOpZero or
dlyRdOpOther or
rdat__h23696 or
delayStatus__h23019 or
rdat__h23751 or rdat__h23760 or rdat__h23769 or rdat__h23778)
begin
case (wci_wslv_reqF$D_OUT[63:32])
32'h0: g_data__h23399 = dlyCtrl;
32'h00000004: g_data__h23399 = dlyHoldoffBytes;
32'h00000008: g_data__h23399 = dlyHoldoffCycles;
32'h0000000C: g_data__h23399 = rdat__h23426;
32'h00000010: g_data__h23399 = rdat__h23432;
32'h00000014: g_data__h23399 = rdat__h23438;
32'h00000018: g_data__h23399 = rdat__h23444;
32'h0000001C: g_data__h23399 = 32'd0;
32'h00000020: g_data__h23399 = rdat__h23568;
32'h00000024: g_data__h23399 = rdat__h23582;
32'h00000028: g_data__h23399 = rdat__h23590;
32'h0000002C: g_data__h23399 = rdat__h23596;
32'h00000030: g_data__h23399 = rdat__h23610;
32'h00000034: g_data__h23399 = rdat__h23618;
32'h00000038: g_data__h23399 = rdat__h23624;
32'h0000003C: g_data__h23399 = rdat__h23630;
32'h00000040: g_data__h23399 = rdat__h23636;
32'h00000044: g_data__h23399 = rdat__h23642;
32'h00000048: g_data__h23399 = rdat__h23653;
32'h0000004C: g_data__h23399 = rdat__h23664;
32'h00000050: g_data__h23399 = rdat__h23675;
32'h00000058: g_data__h23399 = dlyRdOpZero;
32'h0000005C: g_data__h23399 = dlyRdOpOther;
32'h00000060: g_data__h23399 = rdat__h23696;
32'h00000064: g_data__h23399 = delayStatus__h23019;
32'h00000068: g_data__h23399 = rdat__h23751;
32'h0000006C: g_data__h23399 = rdat__h23760;
32'h00000070: g_data__h23399 = rdat__h23769;
32'h00000074: g_data__h23399 = rdat__h23778;
default: g_data__h23399 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
bytesRead <= `BSV_ASSIGNMENT_DELAY 32'd0;
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY 24'd0;
bytesWritten <= `BSV_ASSIGNMENT_DELAY 32'd0;
cyclesPassed <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrlInit;
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY 8'd0;
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
dlyWAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY 25'd0;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
mesgRdCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY 78'h0AAAAAAAAAAAAAAAAAAA;
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWtCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY 1'd1;
rdSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
rdSyncWord <= `BSV_ASSIGNMENT_DELAY 1'd0;
tog50 <= `BSV_ASSIGNMENT_DELAY 1'd0;
unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
wrtSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (bytesRead$EN) bytesRead <= `BSV_ASSIGNMENT_DELAY bytesRead$D_IN;
if (bytesThisMessage$EN)
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY bytesThisMessage$D_IN;
if (bytesWritten$EN)
bytesWritten <= `BSV_ASSIGNMENT_DELAY bytesWritten$D_IN;
if (cyclesPassed$EN)
cyclesPassed <= `BSV_ASSIGNMENT_DELAY cyclesPassed$D_IN;
if (dlyCtrl$EN) dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrl$D_IN;
if (dlyHoldoffBytes$EN)
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY dlyHoldoffBytes$D_IN;
if (dlyHoldoffCycles$EN)
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY dlyHoldoffCycles$D_IN;
if (dlyRAG$EN) dlyRAG <= `BSV_ASSIGNMENT_DELAY dlyRAG$D_IN;
if (dlyRdOpOther$EN)
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY dlyRdOpOther$D_IN;
if (dlyRdOpZero$EN)
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY dlyRdOpZero$D_IN;
if (dlyReadCredit_value$EN)
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY
dlyReadCredit_value$D_IN;
if (dlyReadyToWrite_value$EN)
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY
dlyReadyToWrite_value$D_IN;
if (dlyWAG$EN) dlyWAG <= `BSV_ASSIGNMENT_DELAY dlyWAG$D_IN;
if (dlyWordsStored_value$EN)
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY
dlyWordsStored_value$D_IN;
if (mesgLengthSoFar$EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN;
if (mesgRdCount$EN)
mesgRdCount <= `BSV_ASSIGNMENT_DELAY mesgRdCount$D_IN;
if (mesgWF_rCache$EN)
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY mesgWF_rCache$D_IN;
if (mesgWF_rRdPtr$EN)
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rRdPtr$D_IN;
if (mesgWF_rWrPtr$EN)
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rWrPtr$D_IN;
if (mesgWtCount$EN)
mesgWtCount <= `BSV_ASSIGNMENT_DELAY mesgWtCount$D_IN;
if (rdSerAddr$EN) rdSerAddr <= `BSV_ASSIGNMENT_DELAY rdSerAddr$D_IN;
if (rdSerEmpty$EN)
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY rdSerEmpty$D_IN;
if (rdSerPos$EN) rdSerPos <= `BSV_ASSIGNMENT_DELAY rdSerPos$D_IN;
if (rdSerUnroll$EN)
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY rdSerUnroll$D_IN;
if (rdSyncWord$EN)
rdSyncWord <= `BSV_ASSIGNMENT_DELAY rdSyncWord$D_IN;
if (tog50$EN) tog50 <= `BSV_ASSIGNMENT_DELAY tog50$D_IN;
if (unrollCnt$EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wmemiRdReq$EN)
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY wmemiRdReq$D_IN;
if (wmemiRdResp1$EN)
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp1$D_IN;
if (wmemiRdResp2$EN)
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp2$D_IN;
if (wmemiWrReq$EN)
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY wmemiWrReq$D_IN;
if (wmemi_busyWithMessage$EN)
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY
wmemi_busyWithMessage$D_IN;
if (wmemi_dhF_c_r$EN)
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_c_r$D_IN;
if (wmemi_dhF_q_0$EN)
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_0$D_IN;
if (wmemi_dhF_q_1$EN)
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_1$D_IN;
if (wmemi_errorSticky$EN)
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemi_errorSticky$D_IN;
if (wmemi_operateD$EN)
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN;
if (wmemi_peerIsReady$EN)
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN;
if (wmemi_reqF_c_r$EN)
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_c_r$D_IN;
if (wmemi_reqF_q_0$EN)
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_0$D_IN;
if (wmemi_reqF_q_1$EN)
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_1$D_IN;
if (wmemi_trafficSticky$EN)
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmemi_trafficSticky$D_IN;
if (wrtSerAddr$EN)
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY wrtSerAddr$D_IN;
if (wrtSerPos$EN) wrtSerPos <= `BSV_ASSIGNMENT_DELAY wrtSerPos$D_IN;
if (wrtSerUnroll$EN)
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY wrtSerUnroll$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (rdSerMeta$EN) rdSerMeta <= `BSV_ASSIGNMENT_DELAY rdSerMeta$D_IN;
if (rdSerStage$EN) rdSerStage <= `BSV_ASSIGNMENT_DELAY rdSerStage$D_IN;
if (rdSerStage_1$EN)
rdSerStage_1 <= `BSV_ASSIGNMENT_DELAY rdSerStage_1$D_IN;
if (rdSerStage_2$EN)
rdSerStage_2 <= `BSV_ASSIGNMENT_DELAY rdSerStage_2$D_IN;
if (rdSerStage_3$EN)
rdSerStage_3 <= `BSV_ASSIGNMENT_DELAY rdSerStage_3$D_IN;
if (readMeta$EN) readMeta <= `BSV_ASSIGNMENT_DELAY readMeta$D_IN;
if (wmemi_statusR$EN)
wmemi_statusR <= `BSV_ASSIGNMENT_DELAY wmemi_statusR$D_IN;
if (wrtSerStage$EN) wrtSerStage <= `BSV_ASSIGNMENT_DELAY wrtSerStage$D_IN;
if (wrtSerStage_1$EN)
wrtSerStage_1 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_1$D_IN;
if (wrtSerStage_2$EN)
wrtSerStage_2 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_2$D_IN;
if (wrtSerStage_3$EN)
wrtSerStage_3 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_3$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wmemi_isReset_isInReset$EN)
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmemi_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
if (wsiS_isReset_isInReset$EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bytesRead = 32'hAAAAAAAA;
bytesThisMessage = 24'hAAAAAA;
bytesWritten = 32'hAAAAAAAA;
cyclesPassed = 32'hAAAAAAAA;
dlyCtrl = 32'hAAAAAAAA;
dlyHoldoffBytes = 32'hAAAAAAAA;
dlyHoldoffCycles = 32'hAAAAAAAA;
dlyRAG = 23'h2AAAAA;
dlyRdOpOther = 32'hAAAAAAAA;
dlyRdOpZero = 32'hAAAAAAAA;
dlyReadCredit_value = 8'hAA;
dlyReadyToWrite_value = 16'hAAAA;
dlyWAG = 23'h2AAAAA;
dlyWordsStored_value = 25'h0AAAAAA;
mesgLengthSoFar = 14'h2AAA;
mesgRdCount = 32'hAAAAAAAA;
mesgWF_rCache = 78'h2AAAAAAAAAAAAAAAAAAA;
mesgWF_rRdPtr = 13'h0AAA;
mesgWF_rWrPtr = 13'h0AAA;
mesgWtCount = 32'hAAAAAAAA;
rdSerAddr = 32'hAAAAAAAA;
rdSerEmpty = 1'h0;
rdSerMeta = 32'hAAAAAAAA;
rdSerPos = 2'h2;
rdSerStage = 32'hAAAAAAAA;
rdSerStage_1 = 32'hAAAAAAAA;
rdSerStage_2 = 32'hAAAAAAAA;
rdSerStage_3 = 32'hAAAAAAAA;
rdSerUnroll = 16'hAAAA;
rdSyncWord = 1'h0;
readMeta = 32'hAAAAAAAA;
tog50 = 1'h0;
unrollCnt = 16'hAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wmemiRdReq = 32'hAAAAAAAA;
wmemiRdResp1 = 32'hAAAAAAAA;
wmemiRdResp2 = 32'hAAAAAAAA;
wmemiWrReq = 32'hAAAAAAAA;
wmemi_busyWithMessage = 1'h0;
wmemi_dhF_c_r = 2'h2;
wmemi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky = 1'h0;
wmemi_isReset_isInReset = 1'h0;
wmemi_operateD = 1'h0;
wmemi_peerIsReady = 1'h0;
wmemi_reqF_c_r = 2'h2;
wmemi_reqF_q_0 = 52'hAAAAAAAAAAAAA;
wmemi_reqF_q_1 = 52'hAAAAAAAAAAAAA;
wmemi_statusR = 8'hAA;
wmemi_trafficSticky = 1'h0;
wrtSerAddr = 32'hAAAAAAAA;
wrtSerPos = 2'h2;
wrtSerStage = 32'hAAAAAAAA;
wrtSerStage_1 = 32'hAAAAAAAA;
wrtSerStage_2 = 32'hAAAAAAAA;
wrtSerStage_3 = 32'hAAAAAAAA;
wrtSerUnroll = 16'hAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3739 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3739,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h24065 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DelayWorker dlyCtrl:%0x",
v__h24065,
dlyCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4058 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4058,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3914 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3914,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
endmodule // mkDelayWorker8B
|
`include "./c_frag.sim.v"
`include "./t_frag.sim.v"
`include "./b_frag.sim.v"
(* MODES="SINGLE;SPLIT" *)
module C_FRAG_MODES (TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, TZ, CZ);
// Routing ports
input wire TBS;
input wire TAB;
input wire TSL;
input wire TA1;
input wire TA2;
input wire TB1;
input wire TB2;
input wire BAB;
input wire BSL;
input wire BA1;
input wire BA2;
input wire BB1;
input wire BB2;
output wire TZ;
output wire CZ;
parameter MODE = "SINGLE";
// A single C_FRAG
generate if (MODE == "SINGLE") begin
(* pack="C_FRAG_to_FF" *)
wire cz;
C_FRAG c_frag (
.TBS(TBS),
.TAB(TAB),
.TSL(TSL),
.TA1(TA1),
.TA2(TA2),
.TB1(TB1),
.TB2(TB2),
.TZ (TZ),
.BAB(BAB),
.BSL(BSL),
.BA1(BA1),
.BA2(BA2),
.BB1(BB1),
.BB2(BB2),
.CZ (cz)
);
assign CZ = cz;
// A split C_FRAG consisting of a T_FRAG and a B_FRAG, both can host the
// same cells.
end else if (MODE == "SPLIT") begin
(* pack="B_FRAG_to_FF" *)
wire cz;
// The top part a.k.a. T_FRAG
T_FRAG t_frag (
.TBS(TBS),
.XAB(TAB),
.XSL(TSL),
.XA1(TA1),
.XA2(TA2),
.XB1(TB1),
.XB2(TB2),
.XZ (TZ)
);
// The bottom part a.k.a. B_FRAG
B_FRAG b_frag (
.TBS(TBS),
.XAB(BAB),
.XSL(BSL),
.XA1(BA1),
.XA2(BA2),
.XB1(BB1),
.XB2(BB2),
.XZ (cz)
);
assign CZ = cz;
end endgenerate
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH * 32 != DATA_WIDTH) begin
$error("Error: HDR_WIDTH must be equal to DATA_WIDTH/32");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
axis_baser_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
axis_baser_tx_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
module avr109tx (
input rst,
input clk,
input[7:0] tx_data,
input tx_avail,
output txd,
output tx_ready
);
parameter CLK_FREQUENCY = 1000000;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam BAUDDIV = (CLK_FREQUENCY / BAUD_RATE);
localparam LOG2_BAUDDIV = log2(BAUDDIV);
reg [8:0] txshift_d, txshift_q;
reg [3:0] txcnt_d, txcnt_q;
reg tx_active_d, tx_active_q;
reg [LOG2_BAUDDIV-1:0] txbaud_d, txbaud_q;
assign txd = txshift_q[0];
assign tx_ready = ~tx_active_q;
always @(*) begin
txshift_d = txshift_q;
txcnt_d = txcnt_q;
tx_active_d = tx_active_q;
txbaud_d = txbaud_q;
if (tx_active_q) begin
if (txbaud_q == BAUDDIV-1) begin
txshift_d = {1'b1, txshift_q[8:1]};
if (txcnt_q == 9)
tx_active_d = 0;
txcnt_d = txcnt_q + 1;
txbaud_d = 0;
end else begin
txbaud_d = txbaud_q + 1;
end
end else if (tx_avail) begin
txshift_d = {tx_data, 1'b0};
txcnt_d = 0;
txbaud_d = 0;
tx_active_d = 1;
end
end
always @(posedge clk) begin
if (rst) begin
txshift_q <= 9'b111111111;
txcnt_q <= 4'b0;
tx_active_q <= 1'b0;
txbaud_q <= {LOG2_BAUDDIV{1'b0}};
end else begin
txshift_q <= txshift_d;
txcnt_q <= txcnt_d;
tx_active_q <= tx_active_d;
txbaud_q <= txbaud_d;
end
end
endmodule // avr109tx
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_umult.v
// /___/ /\ Timestamp: Thu Jun 07 01:13:23 2018
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// # of Modules : 1
// Design Name : gsu_umult
// Xilinx : E:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gsu_umult (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [15 : 0] p;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000011 ;
wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000003 (
.A({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , a[7], a[6],
a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , b[7], b[6],
b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ,
p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8], p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]})
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000011 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
//
// Copyright (c) 2015 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module pdp1_write_decoder(ma_op, ma_ac, ma_io, ma_cd, ma_w, ma_r);
input [0:4] ma_op;
input [0:17] ma_ac;
input [0:17] ma_io;
input [0:17] ma_cd;
output reg ma_w;
output reg [0:17] ma_r;
always @(ma_op or ma_ac or ma_io or ma_cd) begin
ma_w = 1'b1;
case(ma_op)
`PDP1_OP_CAL:
ma_r <= ma_ac;
`PDP1_OP_DAC:
ma_r <= ma_ac;
`PDP1_OP_DAP:
ma_r <= {ma_cd[0:5], ma_ac[6:17]};
`PDP1_OP_DIP:
ma_r <= {ma_ac[0:5], ma_cd[6:17]};
`PDP1_OP_DIO:
ma_r <= ma_io;
`PDP1_OP_DZM:
ma_r <= 0;
default:
ma_w <= 0;
endcase // case (ma_op)
end
endmodule // pdp1_write_decoder
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_SYMBOL_V
`define SKY130_FD_SC_LP__O311A_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_SYMBOL_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500519446 : 255;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The mini-decode module to decode the instruction in IFU
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1en,
output dec_rs2en,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
e203_exu_decode u_e203_exu_decode(
.i_instr(instr),
.i_pc(`E203_PC_SIZE'b0),
.i_prdt_taken(1'b0),
.i_muldiv_b2b(1'b0),
.i_misalgn (1'b0),
.i_buserr (1'b0),
.dbg_mode (1'b0),
.dec_misalgn(),
.dec_buserr(),
.dec_ilegl(),
.dec_rs1x0(),
.dec_rs2x0(),
.dec_rs1en(dec_rs1en),
.dec_rs2en(dec_rs2en),
.dec_rdwen(),
.dec_rs1idx(dec_rs1idx),
.dec_rs2idx(dec_rs2idx),
.dec_rdidx(),
.dec_info(),
.dec_imm(),
.dec_pc(),
.dec_mulhsu(dec_mulhsu),
.dec_mul (dec_mul ),
.dec_div (dec_div ),
.dec_rem (dec_rem ),
.dec_divu (dec_divu ),
.dec_remu (dec_remu ),
.dec_rv32(dec_rv32),
.dec_bjp (dec_bjp ),
.dec_jal (dec_jal ),
.dec_jalr(dec_jalr),
.dec_bxx (dec_bxx ),
.dec_jalr_rs1idx(dec_jalr_rs1idx),
.dec_bjp_imm (dec_bjp_imm )
);
endmodule
|
`include "../source/rcpu.v"
`include "../source/RAM2.v"
`timescale 1 us / 1 us
module testRCPU;
reg clk;
reg rst;
wire[31:0] addr;
wire[15:0] read;
wire[15:0] write;
wire we;
wire re;
wire ready;
RAM2 ram(
.clk (clk),
.rst (rst),
.addr (addr[15:0]),
.rdata (read),
.wdata (write),
.we (we),
.re (re),
.ready (ready)
);
rcpu cpu(
.clk (!clk),
.rst (rst),
.memAddr (addr),
.memRead (read),
.memWrite (write),
.memWE (we),
.memRE (re),
.memReady (ready)
);
integer i;
integer clocks = 0;
integer stalled = 0;
initial begin
$dumpfile ("../test.vcd");
$dumpvars (0);
$dumpvars (1, ram.memory[0]);
$dumpvars (1, ram.memory[1]);
for (i = 16'hD000; i>16'hCFE0; i = i - 1)
$dumpvars (1, ram.memory[i]);
end
always #5 clk = !clk;
always @ (posedge clk) begin
clocks <= clocks + 1;
if (cpu.stall)
stalled <= stalled + 1;
end
initial begin
clk = 0;
rst = 1;
#1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9
#10000 $finish;
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the 2-bit 2-input XOR gate
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "xor2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_xor2_2bit();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the 2-bit 2-input XOR gate
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] y; // Output signal out
// Declare "reg" signals: inputs to the DUT
reg [1:0] a; // Input signal - a
reg [1:0] b; // Input signal - b
/**
* Instantiate an instance of the 2-bit 2-input XOR gate
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
a,b,y);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
a = 2'd0;
b = 2'd0;
// @t=10,
#10
a = 2'd0;
b = 2'd1;
// @t=20,
#10
a = 2'd1;
b = 2'd0;
// @t=30,
#10
a = 2'd1;
b = 2'd1;
// ----------------------
// @t=40,
#10
a = 2'd2;
b = 2'd0;
// @t=50,
#10
a = 2'd0;
b = 2'd2;
// @t=60,
#10
a = 2'd1;
b = 2'd2;
// @t=70,
#10
a = 2'd2;
b = 2'd1;
// @t=80,
#10
a = 2'd2;
b = 2'd2;
// ----------------------
// @t=90,
#10
a = 2'd3;
b = 2'd0;
// @t=100,
#10
a = 2'd0;
b = 2'd3;
// @t=110,
#10
a = 2'd3;
b = 2'd1;
// @t=120,
#10
a = 2'd1;
b = 2'd3;
// @t=130,
#10
a = 2'd3;
b = 2'd2;
// @t=140,
#10
a = 2'd2;
b = 2'd3;
// @t=150,
#10
a = 2'd3;
b = 2'd3;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5QGen2x8If128.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix V Avalong Streaming Interface to PCI
// Express module and the Terasic DE5 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5QGen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// ----------LEDs----------
output [7:0] LED,
// ----------PCIE----------
input PCIE_RESET_N,
input PCIE_REFCLK,
// ----------PCIE Serial RX----------
input [C_NUM_LANES-1:0] PCIE_RX_IN,
// ----------PCIE Serial TX----------
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------Oscillators----------
input OSC_BANK3D_50MHZ
);
wire npor;
wire pin_perst;
// ----------TL Config interface----------
wire [3:0] tl_cfg_add;
wire [31:0] tl_cfg_ctl;
wire [52:0] tl_cfg_sts;
// ----------Rx/TX Interfaces----------
wire [0:0] rx_st_sop;
wire [0:0] rx_st_eop;
wire [0:0] rx_st_err;
wire [0:0] rx_st_valid;
wire [0:0] rx_st_empty;
wire rx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
wire [0:0] tx_st_sop;
wire [0:0] tx_st_eop;
wire [0:0] tx_st_err;
wire [0:0] tx_st_valid;
wire tx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
wire [0:0] tx_st_empty;
// ----------Clocks & Locks----------
wire pld_clk;
wire coreclkout_hip;
wire refclk;
wire pld_core_ready;
wire reset_status;
wire serdes_pll_locked;
// ----------Interrupt Interfaces----------
wire app_msi_req;
wire app_msi_ack;
// ----------Reconfiguration Controller signals----------
wire mgmt_clk_clk;
wire mgmt_rst_reset;
// ----------Reconfiguration Driver Signals----------
wire reconfig_xcvr_clk;
wire reconfig_xcvr_rst;
wire [7:0] rx_in;
wire [7:0] tx_out;
// ------------Status Interface------------
wire derr_cor_ext_rcv;
wire derr_cor_ext_rpl;
wire derr_rpl;
wire dlup;
wire dlup_exit;
wire ev128ns;
wire ev1us;
wire hotrst_exit;
wire [3:0] int_status;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssmstate;
wire rx_par_err;
wire [1:0] tx_par_err;
wire cfg_par_err;
wire [7:0] ko_cpl_spc_header;
wire [11:0] ko_cpl_spc_data;
// ----------Clocks----------
assign pld_clk = coreclkout_hip;
assign mgmt_clk_clk = PCIE_REFCLK;
assign reconfig_xcvr_clk = PCIE_REFCLK;
assign refclk = PCIE_REFCLK;
assign pld_core_ready = serdes_pll_locked;
// ----------Resets----------
assign reconfig_xcvr_rst = 1'b0;
assign mgmt_rst_reset = 1'b0;
assign pin_perst = PCIE_RESET_N;
assign npor = PCIE_RESET_N;
// ----------LED's----------
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------//
QSysDE5QGen2x8If128
pcie_system_inst
(
// Outputs
.rx_st_startofpacket (rx_st_sop[0:0]),
.rx_st_endofpacket (rx_st_eop[0:0]),
.rx_st_valid (rx_st_valid[0:0]),
.rx_st_empty (rx_st_empty[0:0]),
.rx_st_data (rx_st_data[127:0]),
.tx_st_ready (tx_st_ready),
.pciehip_reset_status (reset_status),
.pciehip_serdes_pll_locked (serdes_pll_locked),
.pciecfg_tl_cfg_add (tl_cfg_add[3:0]),
.pciecfg_tl_cfg_ctl (tl_cfg_ctl[31:0]),
.pciecfg_tl_cfg_sts (tl_cfg_sts[52:0]),
.pciecoreclk_clk (coreclkout_hip),
.pcieserial_tx_out0 (PCIE_TX_OUT[0]),
.pcieserial_tx_out1 (PCIE_TX_OUT[1]),
.pcieserial_tx_out2 (PCIE_TX_OUT[2]),
.pcieserial_tx_out3 (PCIE_TX_OUT[3]),
.pcieserial_tx_out4 (PCIE_TX_OUT[4]),
.pcieserial_tx_out5 (PCIE_TX_OUT[5]),
.pcieserial_tx_out6 (PCIE_TX_OUT[6]),
.pcieserial_tx_out7 (PCIE_TX_OUT[7]),
.pciemsi_app_msi_ack (app_msi_ack),
.pciestat_derr_cor_ext_rcv (derr_cor_ext_rcv),
.pciestat_derr_cor_ext_rpl (derr_cor_ext_rpl),
.pciestat_derr_rpl (derr_rpl),
.pciestat_dlup (dlup),
.pciestat_dlup_exit (dlup_exit),
.pciestat_ev128ns (ev128ns),
.pciestat_ev1us (ev1us),
.pciestat_hotrst_exit (hotrst_exit),
.pciestat_int_status (int_status),
.pciestat_l2_exit (l2_exit),
.pciestat_lane_act (lane_act),
.pciestat_ltssmstate (ltssmstate),
.pciestat_rx_par_err (rx_par_err),
.pciestat_tx_par_err (tx_par_err),
.pciestat_cfg_par_err (cfg_par_err),
.pciestat_ko_cpl_spc_header (ko_cpl_spc_header),
.pciestat_ko_cpl_spc_data (ko_cpl_spc_data),
// Inputs
.rx_st_ready (rx_st_ready),
.tx_st_startofpacket (tx_st_sop[0:0]),
.tx_st_endofpacket (tx_st_eop[0:0]),
.tx_st_valid (tx_st_valid[0:0]),
.tx_st_empty (tx_st_empty[0:0]),
.tx_st_data (tx_st_data[127:0]),
.pciehip_pld_core_ready (pld_core_ready),
.pcienpor_npor (npor),
.pcienpor_pin_perst (pin_perst),
.pcierefclk_clk (refclk),
.reconfigrefclk_clk (reconfig_xcvr_clk),
.pciepld_clk (pld_clk),
.reconfigrst_reset (reconfig_xcvr_rst),
.mgmtrst_reset (mgmt_rst_reset),
.mgmtclk_clk (mgmt_clk_clk),
.reconfigpldclk_clk (pld_clk),
.pcieserial_rx_in0 (PCIE_RX_IN[0]),
.pcieserial_rx_in1 (PCIE_RX_IN[1]),
.pcieserial_rx_in2 (PCIE_RX_IN[2]),
.pcieserial_rx_in3 (PCIE_RX_IN[3]),
.pcieserial_rx_in4 (PCIE_RX_IN[4]),
.pcieserial_rx_in5 (PCIE_RX_IN[5]),
.pcieserial_rx_in6 (PCIE_RX_IN[6]),
.pcieserial_rx_in7 (PCIE_RX_IN[7]),
.pciemsi_app_msi_req (app_msi_req),
.drvstat_derr_cor_ext_rcv (derr_cor_ext_rcv),
.drvstat_derr_cor_ext_rpl (derr_cor_ext_rpl),
.drvstat_derr_rpl (derr_rpl),
.drvstat_dlup (dlup),
.drvstat_dlup_exit (dlup_exit),
.drvstat_ev128ns (ev128ns),
.drvstat_ev1us (ev1us),
.drvstat_hotrst_exit (hotrst_exit),
.drvstat_int_status (int_status),
.drvstat_l2_exit (l2_exit),
.drvstat_lane_act (lane_act),
.drvstat_ltssmstate (ltssmstate),
.drvstat_rx_par_err (rx_par_err),
.drvstat_tx_par_err (tx_par_err),
.drvstat_cfg_par_err (cfg_par_err),
.drvstat_ko_cpl_spc_header (ko_cpl_spc_header),
.drvstat_ko_cpl_spc_data (ko_cpl_spc_data));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// RIFFA channel interface
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de5
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready),
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid[0:0]),
.TX_ST_EOP (tx_st_eop[0:0]),
.TX_ST_SOP (tx_st_sop[0:0]),
.TX_ST_EMPTY (tx_st_empty[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop[0:0]),
.RX_ST_SOP (rx_st_sop[0:0]),
.RX_ST_VALID (rx_st_valid[0:0]),
.RX_ST_EMPTY (rx_st_empty[0:0]),
.TX_ST_READY (tx_st_ready),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog wrapper for lpflow_decapkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_8 (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base (
.VPWR(VPWR),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_8 ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
|
/**
* bsg_mem_1rw_sync_mask_write_byte_banked.v
*
* This module has the same interface/functionality as
* bsg_mem_1rw_sync_mask_write_byte.
*
* This module can be used for breaking a big SRAM block into
* smaller blocks. This might be useful, if the SRAM generator does not
* support sizes of SRAM that are too wide or too deep.
* It is also useful for power and delay perspective, since only one depth
* bank is activated while reading or writing.
*
*
* - width_p : width of the total memory
* - els_p : depth of the total memory
*
* - num_width_bank_p : Number of banks for the memory's width. width_p has
* to be a multiple of this number.
* - num_depth_bank_p : Number of banks for the memory's depth. els_p has to
* be a multiple of this number.
*
*/
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_byte_banked
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter write_mask_width_lp=(data_width_p>>3)
// bank parameters
, parameter num_width_bank_p=1
, parameter num_depth_bank_p=1
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter bank_depth_lp=(els_p/num_depth_bank_p)
, parameter bank_addr_width_lp=`BSG_SAFE_CLOG2(bank_depth_lp)
, parameter depth_bank_idx_width_lp=`BSG_SAFE_CLOG2(num_depth_bank_p)
, parameter bank_width_lp=(data_width_p/num_width_bank_p)
, parameter bank_mask_width_lp=(bank_width_lp>>3)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output [data_width_p-1:0] data_o
);
if (num_depth_bank_p==1) begin: db1
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
bsg_mem_1rw_sync_mask_write_byte #(
.data_width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_i)
,.addr_i(addr_i)
,.data_i(data_i[bank_width_lp*i+:bank_width_lp])
,.write_mask_i(write_mask_i[bank_mask_width_lp*i+:bank_mask_width_lp])
,.data_o(data_o[bank_width_lp*i+:bank_width_lp])
);
end
end
else begin: dbn
wire [depth_bank_idx_width_lp-1:0] depth_bank_idx_li = addr_i[0+:depth_bank_idx_width_lp];
wire [bank_addr_width_lp-1:0] bank_addr_li = addr_i[depth_bank_idx_width_lp+:bank_addr_width_lp];
logic [num_depth_bank_p-1:0] bank_v_li;
logic [num_depth_bank_p-1:0][data_width_p-1:0] bank_data_lo;
bsg_decode_with_v #(
.num_out_p(num_depth_bank_p)
) demux_v (
.i(depth_bank_idx_li)
,.v_i(v_i)
,.o(bank_v_li)
);
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
for (genvar j = 0; j < num_depth_bank_p; j++) begin: db
bsg_mem_1rw_sync_mask_write_byte #(
.data_width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(bank_v_li[j])
,.w_i(w_i)
,.addr_i(bank_addr_li)
,.data_i(data_i[i*bank_width_lp+:bank_width_lp])
,.write_mask_i(write_mask_i[i*bank_mask_width_lp+:bank_mask_width_lp])
,.data_o(bank_data_lo[j][i*bank_width_lp+:bank_width_lp])
);
end
end
logic [depth_bank_idx_width_lp-1:0] depth_bank_idx_r;
bsg_dff_en #(
.width_p(depth_bank_idx_width_lp)
) depth_bank_idx_dff (
.clk_i(clk_i)
,.en_i(v_i & ~w_i)
,.data_i(depth_bank_idx_li)
,.data_o(depth_bank_idx_r)
);
bsg_mux #(
.els_p(num_depth_bank_p)
,.width_p(data_width_p)
) data_out_mux (
.data_i(bank_data_lo)
,.sel_i(depth_bank_idx_r)
,.data_o(data_o)
);
end
// synopsys translate_off
initial begin
assert (data_width_p % 8 == 0)
else $error("data_width_p is not multiple of 8. %m");
assert(els_p % num_depth_bank_p == 0)
else $error("[BSG_ERROR] num_depth_bank_p does not divide even with els_p. %m");
assert(data_width_p % num_width_bank_p == 0)
else $error("[BSG_ERROR] num_width_bank_p does not divide even with width_p. %m");
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte_banked)
|
/****************************************
Adder Unit
- 32bit Adder
Make : 2010/12/07
Update :
****************************************/
`default_nettype none
`include "core.h"
module adder_n
#(
parameter N = 32
)(
//iDATA
input [N-1:0] iDATA_0,
input [N-1:0] iDATA_1,
input [4:0] iADDER_CMD,
//oDATA
output [N-1:0] oDATA,
output oSF,
output oOF,
output oCF,
output oPF,
output oZF
);
/****************************************
This -> Output
****************************************/
assign {oZF, oPF, oOF, oSF, oCF, oDATA} = func_adder_execution(iADDER_CMD, iDATA_0, iDATA_1);
//ZF, PF, OF, SF, CF, Data
function [36:0] func_adder_execution;
input [4:0] func_cmd;
input [31:0] func_data0;
input [31:0] func_data1;
reg [32:0] func_pri_op0;
reg [32:0] func_pri_op1;
reg [32:0] func_pri_out;
begin
case(func_cmd)
`EXE_ADDER_ADD :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_SUB :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = ({1'b0, ~func_data1} + 32'h1);
func_pri_out = func_pri_op0 + func_pri_op1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0],( func_data0[31] != func_data1[31] && func_data0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_NEG:
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = ~func_data0 + {{N-1{1'b0}}, 1'b1};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_COUT :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], 31'h0 , func_pri_out[32]};
end
`EXE_ADDER_SEXT8 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {24{func_data1[7]}}, func_data1[7:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_SEXT16 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {16{func_data1[15]}}, func_data1[15:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
default:
begin/*
//$display("[ERROR] : adder_n.v func_addder_execution Error");
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'b0}};
*/
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'h0}};
end
endcase
end
endfunction
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A41OI_BEHAVIORAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_BEHAVIORAL_PP_V |
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
`define bsg_mux_one_hot_gen_macro(words,bits) \
if (harden_p && els_p == words && width_p == bits) \
begin: macro \
bsg_rp_tsmc_40_mux_w``words``_b``bits w``words``_b``bits \
(.* \
); \
end
module bsg_mux_one_hot #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [els_p-1:0] sel_one_hot_i
,output [width_p-1:0] data_o
);
wire [els_p-1:0][width_p-1:0] data_masked;
genvar i,j;
`bsg_mux_one_hot_gen_macro(3,14)
else
`bsg_mux_one_hot_gen_macro(3,4)
else
begin : notmacro
for (i = 0; i < els_p; i++)
begin : mask
assign data_masked[i] = data_i[i] & { width_p { sel_one_hot_i[i] } };
end
for (i = 0; i < width_p; i++)
begin: reduce
wire [els_p-1:0] gather;
for (j = 0; j < els_p; j++)
assign gather[j] = data_masked[j][i];
assign data_o[i] = | gather;
end
end
endmodule // bsg_mux_one_hot
`BSG_ABSTRACT_MODULE(bsg_mux_one_hot)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2b (
VPWR,
VGND,
X ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: tes_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altpll bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" clk2_divide_by=1 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" clk4_divide_by=1 clk4_duty_cycle=50 clk4_multiply_by=1 clk4_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=tes_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_USED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module tes_pll_altpll
(
areset,
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 1,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.clk2_divide_by = 1,
pll1.clk2_duty_cycle = 50,
pll1.clk2_multiply_by = 1,
pll1.clk2_phase_shift = "0",
pll1.clk3_divide_by = 1,
pll1.clk3_duty_cycle = 50,
pll1.clk3_multiply_by = 1,
pll1.clk3_phase_shift = "0",
pll1.clk4_divide_by = 1,
pll1.clk4_duty_cycle = 50,
pll1.clk4_multiply_by = 1,
pll1.clk4_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //tes_pll_altpll
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tes_pll (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4)/* synthesis synthesis_clearbox = 1 */;
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire [0:0] sub_wire8 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
tes_pll_altpll tes_pll_altpll_component (
.areset (areset),
.inclk (sub_wire7),
.clk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "tes_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_8_V
`define SKY130_FD_SC_LS__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_8_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//finalproject_cpu_ociram_sp_ram, which is an nios_sp_ram
finalproject_cpu_ociram_sp_ram_module finalproject_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam finalproject_cpu_ociram_sp_ram.lpm_file = "finalproject_cpu_ociram_default_contents.dat";
`else
defparam finalproject_cpu_ociram_sp_ram.lpm_file = "finalproject_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam finalproject_cpu_ociram_sp_ram.lpm_file = "finalproject_cpu_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h08000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001d1d :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h08000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000001100000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000001100000);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 26: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 28: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 28: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h8000020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 28: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//finalproject_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
finalproject_cpu_nios2_oci_td_mode finalproject_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
finalproject_cpu_nios2_oci_compute_input_tm_cnt the_finalproject_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
finalproject_cpu_nios2_oci_fifo_wrptr_inc the_finalproject_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
finalproject_cpu_nios2_oci_fifo_cnt_inc the_finalproject_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
finalproject_cpu_oci_test_bench the_finalproject_cpu_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifo_head[35 : 32]), fifo_head[31 : 0]} : itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 26: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
finalproject_cpu_nios2_oci_debug the_finalproject_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
finalproject_cpu_nios2_ocimem the_finalproject_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
finalproject_cpu_nios2_avalon_reg the_finalproject_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
finalproject_cpu_nios2_oci_break the_finalproject_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
finalproject_cpu_nios2_oci_xbrk the_finalproject_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
finalproject_cpu_nios2_oci_dbrk the_finalproject_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
finalproject_cpu_nios2_oci_itrace the_finalproject_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
finalproject_cpu_nios2_oci_dtrace the_finalproject_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
finalproject_cpu_nios2_oci_fifo the_finalproject_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
finalproject_cpu_nios2_oci_pib the_finalproject_cpu_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
finalproject_cpu_nios2_oci_im the_finalproject_cpu_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
finalproject_cpu_jtag_debug_module_wrapper the_finalproject_cpu_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 28: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 28: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 26: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 28: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_jmp_direct_pc_hi;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 26: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 26: 0] F_pc_no_crst_nxt;
wire [ 26: 0] F_pc_nxt;
wire [ 26: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 28: 0] F_pcb;
wire [ 28: 0] F_pcb_nxt;
wire [ 28: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 28: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 28: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 28: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_finalproject_cpu_test_bench, which is an e_instance
finalproject_cpu_test_bench the_finalproject_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000001100000;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 33554440 :
(F_pc_sel_nxt == 2'b01)? 71303688 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[28 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 33554432;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign F_jmp_direct_pc_hi = F_pc[26];
assign D_jmp_direct_target_waddr = {F_jmp_direct_pc_hi, D_iw[31 : 6]};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//finalproject_cpu_register_bank_a, which is an nios_sdp_ram
finalproject_cpu_register_bank_a_module finalproject_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam finalproject_cpu_register_bank_a.lpm_file = "finalproject_cpu_rf_ram_a.dat";
`else
defparam finalproject_cpu_register_bank_a.lpm_file = "finalproject_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam finalproject_cpu_register_bank_a.lpm_file = "finalproject_cpu_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//finalproject_cpu_register_bank_b, which is an nios_sdp_ram
finalproject_cpu_register_bank_b_module finalproject_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam finalproject_cpu_register_bank_b.lpm_file = "finalproject_cpu_rf_ram_b.dat";
`else
defparam finalproject_cpu_register_bank_b.lpm_file = "finalproject_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam finalproject_cpu_register_bank_b.lpm_file = "finalproject_cpu_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[28 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
W_cpuid_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[28 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000001100000;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000001100000;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
finalproject_cpu_nios2_oci the_finalproject_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
module crc (/*AUTOARG*/
// Outputs
crc_out,
// Inputs
clk, crc_rst, data_in, data_valid
);
// system signal
input clk;
input crc_rst;
// CRC comput signal
input [31:0] data_in;
input data_valid;
output [31:0] crc_out;
reg crc_valid;
wire [31:0] new_bit;
wire [31:0] crc_bit;
reg [31:0] crc_out;
always @(posedge clk)
begin
if(crc_rst)
crc_out <= 32'h52325032;
else if(data_valid)
begin
crc_out <= new_bit;
end
end
assign crc_bit = data_in ^ crc_out ;
assign new_bit[31] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^
crc_bit[28] ^ crc_bit[27] ^ crc_bit[25] ^
crc_bit[24] ^ crc_bit[23] ^ crc_bit[15] ^
crc_bit[11] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[5];
assign new_bit[30] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^
crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^
crc_bit[23] ^ crc_bit[22] ^ crc_bit[14] ^
crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[4];
assign new_bit[29] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^
crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^
crc_bit[23] ^ crc_bit[22] ^ crc_bit[21] ^
crc_bit[13] ^ crc_bit[9] ^ crc_bit[7] ^
crc_bit[6] ^ crc_bit[3];
assign new_bit[28] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^
crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^
crc_bit[22] ^ crc_bit[21] ^ crc_bit[20] ^
crc_bit[12] ^ crc_bit[8] ^ crc_bit[6] ^
crc_bit[5] ^ crc_bit[2];
assign new_bit[27] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^
crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^
crc_bit[21] ^ crc_bit[20] ^ crc_bit[19] ^
crc_bit[11] ^ crc_bit[7] ^ crc_bit[5] ^
crc_bit[4] ^ crc_bit[1];
assign new_bit[26] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^
crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^
crc_bit[22] ^ crc_bit[20] ^ crc_bit[19] ^
crc_bit[18] ^ crc_bit[10] ^ crc_bit[6] ^
crc_bit[4] ^ crc_bit[3] ^ crc_bit[0];
assign new_bit[25] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^
crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^
crc_bit[18] ^ crc_bit[17] ^ crc_bit[15] ^
crc_bit[11] ^ crc_bit[8] ^ crc_bit[3] ^ crc_bit[2];
assign new_bit[24] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^
crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^
crc_bit[17] ^ crc_bit[16] ^ crc_bit[14] ^
crc_bit[10] ^ crc_bit[7] ^ crc_bit[2] ^ crc_bit[1];
assign new_bit[23] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^
crc_bit[26] ^ crc_bit[20] ^ crc_bit[19] ^
crc_bit[17] ^ crc_bit[16] ^ crc_bit[15] ^
crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^
crc_bit[1] ^ crc_bit[0];
assign new_bit[22] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^
crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^
crc_bit[19] ^ crc_bit[18] ^ crc_bit[16] ^
crc_bit[14] ^ crc_bit[12] ^ crc_bit[11] ^
crc_bit[9] ^ crc_bit[0];
assign new_bit[21] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^
crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^
crc_bit[18] ^ crc_bit[17] ^ crc_bit[13] ^
crc_bit[10] ^ crc_bit[9] ^ crc_bit[5];
assign new_bit[20] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[26] ^
crc_bit[25] ^ crc_bit[23] ^ crc_bit[21] ^
crc_bit[17] ^ crc_bit[16] ^ crc_bit[12] ^
crc_bit[9] ^ crc_bit[8] ^ crc_bit[4];
assign new_bit[19] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[25] ^
crc_bit[24] ^ crc_bit[22] ^ crc_bit[20] ^
crc_bit[16] ^ crc_bit[15] ^ crc_bit[11] ^
crc_bit[8] ^ crc_bit[7] ^ crc_bit[3];
assign new_bit[18] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^
crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^
crc_bit[19] ^ crc_bit[15] ^ crc_bit[14] ^
crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2];
assign new_bit[17] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^
crc_bit[25] ^ crc_bit[23] ^ crc_bit[22] ^
crc_bit[20] ^ crc_bit[18] ^ crc_bit[14] ^
crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^
crc_bit[5] ^ crc_bit[1];
assign new_bit[16] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[26] ^
crc_bit[24] ^ crc_bit[22] ^ crc_bit[21] ^
crc_bit[19] ^ crc_bit[17] ^ crc_bit[13] ^
crc_bit[12] ^ crc_bit[8] ^ crc_bit[5] ^
crc_bit[4] ^ crc_bit[0];
assign new_bit[15] = crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^
crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^
crc_bit[16] ^ crc_bit[15] ^ crc_bit[12] ^
crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^
crc_bit[5] ^ crc_bit[4] ^ crc_bit[3];
assign new_bit[14] = crc_bit[29] ^ crc_bit[26] ^ crc_bit[23] ^
crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^
crc_bit[15] ^ crc_bit[14] ^ crc_bit[11] ^
crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^
crc_bit[4] ^ crc_bit[3] ^ crc_bit[2];
assign new_bit[13] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[25] ^
crc_bit[22] ^ crc_bit[19] ^ crc_bit[18] ^
crc_bit[16] ^ crc_bit[14] ^ crc_bit[13] ^
crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^
crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[1];
assign new_bit[12] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^
crc_bit[24] ^ crc_bit[21] ^ crc_bit[18] ^
crc_bit[17] ^ crc_bit[15] ^ crc_bit[13] ^
crc_bit[12] ^ crc_bit[9] ^ crc_bit[6] ^
crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^
crc_bit[1] ^ crc_bit[0];
assign new_bit[11] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[27] ^
crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^
crc_bit[20] ^ crc_bit[17] ^ crc_bit[16] ^
crc_bit[15] ^ crc_bit[14] ^ crc_bit[12] ^
crc_bit[9] ^ crc_bit[4] ^ crc_bit[3] ^
crc_bit[1] ^ crc_bit[0];
assign new_bit[10] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^
crc_bit[26] ^ crc_bit[19] ^ crc_bit[16] ^
crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^
crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
assign new_bit[9] = crc_bit[29] ^ crc_bit[24] ^ crc_bit[23] ^
crc_bit[18] ^ crc_bit[13] ^ crc_bit[12] ^
crc_bit[11] ^ crc_bit[9] ^ crc_bit[5] ^
crc_bit[4] ^ crc_bit[2] ^ crc_bit[1];
assign new_bit[8] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[23] ^
crc_bit[22] ^ crc_bit[17] ^ crc_bit[12] ^
crc_bit[11] ^ crc_bit[10] ^ crc_bit[8] ^
crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
assign new_bit[7] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[25] ^
crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^
crc_bit[21] ^ crc_bit[16] ^ crc_bit[15] ^
crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^
crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
assign new_bit[6] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^
crc_bit[22] ^ crc_bit[21] ^ crc_bit[20] ^
crc_bit[14] ^ crc_bit[11] ^ crc_bit[8] ^
crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^
crc_bit[4] ^ crc_bit[2] ^ crc_bit[1];
assign new_bit[5] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[24] ^
crc_bit[21] ^ crc_bit[20] ^ crc_bit[19] ^
crc_bit[13] ^ crc_bit[10] ^ crc_bit[7] ^
crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^
crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
assign new_bit[4] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^
crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^
crc_bit[19] ^ crc_bit[18] ^ crc_bit[15] ^
crc_bit[12] ^ crc_bit[11] ^ crc_bit[8] ^
crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
crc_bit[2] ^ crc_bit[0];
assign new_bit[3] = crc_bit[31] ^ crc_bit[27] ^ crc_bit[25] ^
crc_bit[19] ^ crc_bit[18] ^ crc_bit[17] ^
crc_bit[15] ^ crc_bit[14] ^ crc_bit[10] ^
crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^
crc_bit[3] ^ crc_bit[2] ^ crc_bit[1];
assign new_bit[2] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[26] ^
crc_bit[24] ^ crc_bit[18] ^ crc_bit[17] ^
crc_bit[16] ^ crc_bit[14] ^ crc_bit[13] ^
crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^
crc_bit[6] ^ crc_bit[2] ^ crc_bit[1] ^ crc_bit[0];
assign new_bit[1] = crc_bit[28] ^ crc_bit[27] ^ crc_bit[24] ^
crc_bit[17] ^ crc_bit[16] ^ crc_bit[13] ^
crc_bit[12] ^ crc_bit[11] ^ crc_bit[9] ^
crc_bit[7] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
assign new_bit[0] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^
crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^
crc_bit[24] ^ crc_bit[16] ^ crc_bit[12] ^
crc_bit[10] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[0];
endmodule
|
`timescale 1ns/10ps
module SeqSim;
reg clock;
reg reset;
reg [19:0] inst;
reg inst_en;
reg [7:0] ireg_0;
reg [7:0] ireg_1;
reg [7:0] ireg_2;
reg [7:0] ireg_3;
wire [7:0] next;
wire [11:0] oreg;
wire [7:0] oreg_wen;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Seq_CI,1'bx,3'b010,4'h1,8'hAA};
inst_en = 1;
#4 inst = {`Seq_CR,1'bx,3'b011,4'h2,6'bxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'hEE;
#4 inst = {`Seq_JI,8'h1A,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_JR,14'bxxxxxxxxxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'h7B;
#4 inst = {`Seq_JZ,8'h2A,6'bxxxxxx,2'h3};
inst_en = 1;
ireg_3 = 8'h00;
#4 inst = {`Seq_JZ,8'h4A,6'bxxxxxx,2'h0};
inst_en = 1;
ireg_0 = 8'h11;
#4 inst = {`Seq_JN,8'hB0,6'bxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'h22;
#4 inst = {`Seq_JN,8'h8A,6'bxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'h00;
#4 inst = {`Seq_WZ,14'bxxxxxxxxxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'hA1;
#8 ireg_1 = 8'h00;
#4 inst = {`Seq_WN,14'bxxxxxxxxxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'h00;
#8 ireg_2 = 8'hA1;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`Seq_CI,1'bx,3'b011,4'h4,8'hBE};
inst_en = 0;
#4 inst = {`Seq_JR,14'bxxxxxxxxxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'h07;
// Test bad instruction.
#4 inst = {8'hF,16'hAEF0};
inst_en = 1;
#4 inst = {`Seq_JZ,8'hEF,6'bxxxxxx,2'h3};
inst_en = 1;
ireg_3 = 8'h00;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Seq_JI,8'h48,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
// Test WZ and WN with nothing to wait for.
#4 inst = {`Seq_WZ,14'bxxxxxxxxxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'h00;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_WN,14'bxxxxxxxxxxxxxx,2'h3};
inst_en = 1;
ireg_3 = 8'h10;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
// Test WZ and WN with inst_en going down.
#4 inst = {`Seq_WZ,14'bxxxxxxxxxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'hAA;
#4 inst_en = 0;
#8 inst_en = 1;
#4 ireg_2 = 8'h00;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_WZ,14'bxxxxxxxxxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'hAA;
#4 inst_en = 0;
#8 ireg_1 = 8'h00;
#4 inst_en = 1;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_WN,14'bxxxxxxxxxxxxxx,2'h2};
inst_en = 1;
ireg_2 = 8'h00;
#4 inst_en = 0;
#8 inst_en = 1;
#4 ireg_2 = 8'hAA;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
#4 inst = {`Seq_WN,14'bxxxxxxxxxxxxxx,2'h1};
inst_en = 1;
ireg_1 = 8'h00;
#4 inst_en = 0;
#8 ireg_1 = 8'hAA;
#4 inst_en = 1;
#4 inst = {`Seq_NO,16'bxxxxxxxxxxxxxxxx};
inst_en = 1;
end
Seq
seq (.clock(clock),
.reset(reset),
.inst(inst),
.inst_text("NOT OF INTEREST"),
.inst_en(inst_en),
.ireg_0(ireg_0),
.ireg_1(ireg_1),
.ireg_2(ireg_2),
.ireg_3(ireg_3),
.next(next),
.oreg(oreg),
.oreg_wen(oreg_wen));
endmodule // SeqSim
|
// soc_system.v
// Generated using ACDS version 13.1 162 at 2014.12.19.15:54:10
`timescale 1 ps / 1 ps
module soc_system (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_0_hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_0_hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_0_hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_0_hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_0_hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents, // hps_0_f2h_stm_hw_events.stm_hwevents
input wire hps_0_f2h_warm_reset_req_reset_n, // hps_0_f2h_warm_reset_req.reset_n
input wire hps_0_f2h_debug_reset_req_reset_n, // hps_0_f2h_debug_reset_req.reset_n
input wire hps_0_f2h_cold_reset_req_reset_n, // hps_0_f2h_cold_reset_req.reset_n
output wire [1:0] pio_alivetest_cpu_s0_extcon_export, // pio_alivetest_cpu_s0_extcon.export
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [15:0] sdram_wire_dq, // .dq
output wire [1:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
output wire [1:0] pio_alivetest_cpu_s1_extcon_export, // pio_alivetest_cpu_s1_extcon.export
output wire system_pll_locked_export, // system_pll_locked.export
output wire sdram_pll_locked_export, // sdram_pll_locked.export
inout wire i2c_cpu_s0_i2c_exports_scl, // i2c_cpu_s0_i2c_exports.scl
inout wire i2c_cpu_s0_i2c_exports_sda, // .sda
inout wire i2c_cpu_s1_i2c_exports_scl, // i2c_cpu_s1_i2c_exports.scl
inout wire i2c_cpu_s1_i2c_exports_sda, // .sda
output wire pwm_cpu_s0_1_conduit_end_readdatavalid_n, // pwm_cpu_s0_1_conduit_end.readdatavalid_n
output wire clk_sdram_clk, // clk_sdram.clk
output wire pwm_cpu_s0_2_conduit_end_readdatavalid_n, // pwm_cpu_s0_2_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_3_conduit_end_readdatavalid_n, // pwm_cpu_s0_3_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_4_conduit_end_readdatavalid_n, // pwm_cpu_s0_4_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_5_conduit_end_readdatavalid_n, // pwm_cpu_s0_5_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_6_conduit_end_readdatavalid_n, // pwm_cpu_s0_6_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_7_conduit_end_readdatavalid_n, // pwm_cpu_s0_7_conduit_end.readdatavalid_n
output wire pwm_cpu_s0_8_conduit_end_readdatavalid_n // pwm_cpu_s0_8_conduit_end.readdatavalid_n
);
wire system_pll_outclk0_clk; // system_pll:outclk_0 -> [cpu_s0:clk, cpu_s1:clk, fifo_bridge_cpuM_cpus0:clk, fifo_bridge_cpuM_cpus1:clk, fifo_bridge_cpus0_cpus1:clk, fpga_only_master:clk_clk, hps_only_master:clk_clk, intr_capturer_0:clk, irq_mapper_002:clk, irq_mapper_003:clk, irq_mapper_004:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, irq_synchronizer_003:sender_clk, irq_synchronizer_004:sender_clk, irq_synchronizer_005:sender_clk, mm_interconnect_0:system_pll_outclk0_clk, mm_interconnect_1:system_pll_outclk0_clk, mm_interconnect_2:system_pll_outclk0_clk, mm_interconnect_3:system_pll_outclk0_clk, mm_interconnect_4:system_pll_outclk0_clk, onchip_sram:clk, rst_controller:clk, s0_io_clockCrossing_bridge:s0_clk, s1_io_clockCrossing_bridge:s0_clk, sdram_clockCrossing_Bridge:s0_clk, sysid_qsys:clock]
wire system_pll_outclk1_clk; // system_pll:outclk_1 -> [i2c_cpu_s0:wb_clk_i, i2c_cpu_s1:wb_clk_i, irq_synchronizer:receiver_clk, irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, irq_synchronizer_003:receiver_clk, irq_synchronizer_004:receiver_clk, irq_synchronizer_005:receiver_clk, jtag_uart_cpu_s0:clk, jtag_uart_cpu_s1:clk, mm_interconnect_5:system_pll_outclk1_clk, mm_interconnect_7:system_pll_outclk1_clk, pio_aliveTest_cpu_s0:clk, pio_aliveTest_cpu_s1:clk, rst_controller_001:clk, s0_io_clockCrossing_bridge:m0_clk, s1_io_clockCrossing_bridge:m0_clk, timer_cpu_s0:clk, timer_cpu_s1:clk]
wire sdram_pll_outclk0_clk; // sdram_pll:outclk_0 -> [mm_interconnect_6:sdram_pll_outclk0_clk, rst_controller_002:clk, sdram:clk, sdram_clockCrossing_Bridge:m0_clk]
wire pwm_pll_outclk0_clk; // pwm_pll:outclk_0 -> [mm_interconnect_5:pwm_pll_outclk0_clk, pwm_cpu_s0_1:clk, pwm_cpu_s0_2:clk, pwm_cpu_s0_3:clk, pwm_cpu_s0_4:clk, pwm_cpu_s0_5:clk, pwm_cpu_s0_6:clk, pwm_cpu_s0_7:clk, pwm_cpu_s0_8:clk, rst_controller_004:clk]
wire hps_only_master_master_waitrequest; // mm_interconnect_0:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_0:hps_only_master_master_writedata
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_0:hps_only_master_master_address
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_0:hps_only_master_master_write
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_0:hps_only_master_master_read
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_0:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_0:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_0:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire mm_interconnect_0_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arsize; // mm_interconnect_0:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlock; // mm_interconnect_0:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awcache; // mm_interconnect_0:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire mm_interconnect_0_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_arready
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_arid; // mm_interconnect_0:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire mm_interconnect_0_hps_0_f2h_axi_slave_rready; // mm_interconnect_0:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire mm_interconnect_0_hps_0_f2h_axi_slave_bready; // mm_interconnect_0:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awsize; // mm_interconnect_0:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awprot; // mm_interconnect_0:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire mm_interconnect_0_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arprot; // mm_interconnect_0:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_0:hps_0_f2h_axi_slave_bid
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlen; // mm_interconnect_0:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire mm_interconnect_0_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_awready
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_awid; // mm_interconnect_0:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire mm_interconnect_0_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_bvalid
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_wid; // mm_interconnect_0:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlock; // mm_interconnect_0:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awburst; // mm_interconnect_0:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_bresp
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_aruser; // mm_interconnect_0:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_awuser; // mm_interconnect_0:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_0:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_0_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_rvalid
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arburst; // mm_interconnect_0:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [63:0] mm_interconnect_0_hps_0_f2h_axi_slave_wdata; // mm_interconnect_0:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_0_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_wready
wire [63:0] mm_interconnect_0_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_0:hps_0_f2h_axi_slave_rdata
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_araddr; // mm_interconnect_0:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arcache; // mm_interconnect_0:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlen; // mm_interconnect_0:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_0:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_0:hps_0_f2h_axi_slave_rid
wire mm_interconnect_0_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_rresp
wire mm_interconnect_0_hps_0_f2h_axi_slave_wlast; // mm_interconnect_0:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire mm_interconnect_0_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_0:hps_0_f2h_axi_slave_rlast
wire [0:0] mm_interconnect_1_sysid_qsys_control_slave_address; // mm_interconnect_1:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_1_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_1:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_1_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_1:intr_capturer_0_avalon_slave_0_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_1:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_1:fpga_only_master_master_writedata
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_1:fpga_only_master_master_address
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_1:fpga_only_master_master_write
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_1:fpga_only_master_master_read
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_1:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_1:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_1:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire [31:0] mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_writedata; // mm_interconnect_2:fifo_bridge_cpuM_cpus0_s0_writedata -> fifo_bridge_cpuM_cpus0:cpu1_writedata
wire [7:0] mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_address; // mm_interconnect_2:fifo_bridge_cpuM_cpus0_s0_address -> fifo_bridge_cpuM_cpus0:cpu1_address
wire mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_write; // mm_interconnect_2:fifo_bridge_cpuM_cpus0_s0_write -> fifo_bridge_cpuM_cpus0:cpu1_write
wire mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_read; // mm_interconnect_2:fifo_bridge_cpuM_cpus0_s0_read -> fifo_bridge_cpuM_cpus0:cpu1_read
wire [31:0] mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_readdata; // fifo_bridge_cpuM_cpus0:cpu1_readdata -> mm_interconnect_2:fifo_bridge_cpuM_cpus0_s0_readdata
wire cpu_s0_data_master_waitrequest; // mm_interconnect_2:cpu_s0_data_master_waitrequest -> cpu_s0:d_waitrequest
wire [31:0] cpu_s0_data_master_writedata; // cpu_s0:d_writedata -> mm_interconnect_2:cpu_s0_data_master_writedata
wire [27:0] cpu_s0_data_master_address; // cpu_s0:d_address -> mm_interconnect_2:cpu_s0_data_master_address
wire cpu_s0_data_master_write; // cpu_s0:d_write -> mm_interconnect_2:cpu_s0_data_master_write
wire cpu_s0_data_master_read; // cpu_s0:d_read -> mm_interconnect_2:cpu_s0_data_master_read
wire [31:0] cpu_s0_data_master_readdata; // mm_interconnect_2:cpu_s0_data_master_readdata -> cpu_s0:d_readdata
wire cpu_s0_data_master_debugaccess; // cpu_s0:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_2:cpu_s0_data_master_debugaccess
wire [3:0] cpu_s0_data_master_byteenable; // cpu_s0:d_byteenable -> mm_interconnect_2:cpu_s0_data_master_byteenable
wire [31:0] mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_writedata; // mm_interconnect_2:fifo_bridge_cpus0_cpus1_s0_writedata -> fifo_bridge_cpus0_cpus1:cpu1_writedata
wire [7:0] mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_address; // mm_interconnect_2:fifo_bridge_cpus0_cpus1_s0_address -> fifo_bridge_cpus0_cpus1:cpu1_address
wire mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_write; // mm_interconnect_2:fifo_bridge_cpus0_cpus1_s0_write -> fifo_bridge_cpus0_cpus1:cpu1_write
wire mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_read; // mm_interconnect_2:fifo_bridge_cpus0_cpus1_s0_read -> fifo_bridge_cpus0_cpus1:cpu1_read
wire [31:0] mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_readdata; // fifo_bridge_cpus0_cpus1:cpu1_readdata -> mm_interconnect_2:fifo_bridge_cpus0_cpus1_s0_readdata
wire mm_interconnect_2_cpu_s0_jtag_debug_module_waitrequest; // cpu_s0:jtag_debug_module_waitrequest -> mm_interconnect_2:cpu_s0_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_2_cpu_s0_jtag_debug_module_writedata; // mm_interconnect_2:cpu_s0_jtag_debug_module_writedata -> cpu_s0:jtag_debug_module_writedata
wire [8:0] mm_interconnect_2_cpu_s0_jtag_debug_module_address; // mm_interconnect_2:cpu_s0_jtag_debug_module_address -> cpu_s0:jtag_debug_module_address
wire mm_interconnect_2_cpu_s0_jtag_debug_module_write; // mm_interconnect_2:cpu_s0_jtag_debug_module_write -> cpu_s0:jtag_debug_module_write
wire mm_interconnect_2_cpu_s0_jtag_debug_module_read; // mm_interconnect_2:cpu_s0_jtag_debug_module_read -> cpu_s0:jtag_debug_module_read
wire [31:0] mm_interconnect_2_cpu_s0_jtag_debug_module_readdata; // cpu_s0:jtag_debug_module_readdata -> mm_interconnect_2:cpu_s0_jtag_debug_module_readdata
wire mm_interconnect_2_cpu_s0_jtag_debug_module_debugaccess; // mm_interconnect_2:cpu_s0_jtag_debug_module_debugaccess -> cpu_s0:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_2_cpu_s0_jtag_debug_module_byteenable; // mm_interconnect_2:cpu_s0_jtag_debug_module_byteenable -> cpu_s0:jtag_debug_module_byteenable
wire mm_interconnect_2_s0_io_clockcrossing_bridge_s0_waitrequest; // s0_io_clockCrossing_bridge:s0_waitrequest -> mm_interconnect_2:s0_io_clockCrossing_bridge_s0_waitrequest
wire [0:0] mm_interconnect_2_s0_io_clockcrossing_bridge_s0_burstcount; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_burstcount -> s0_io_clockCrossing_bridge:s0_burstcount
wire [31:0] mm_interconnect_2_s0_io_clockcrossing_bridge_s0_writedata; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_writedata -> s0_io_clockCrossing_bridge:s0_writedata
wire [9:0] mm_interconnect_2_s0_io_clockcrossing_bridge_s0_address; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_address -> s0_io_clockCrossing_bridge:s0_address
wire mm_interconnect_2_s0_io_clockcrossing_bridge_s0_write; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_write -> s0_io_clockCrossing_bridge:s0_write
wire mm_interconnect_2_s0_io_clockcrossing_bridge_s0_read; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_read -> s0_io_clockCrossing_bridge:s0_read
wire [31:0] mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdata; // s0_io_clockCrossing_bridge:s0_readdata -> mm_interconnect_2:s0_io_clockCrossing_bridge_s0_readdata
wire mm_interconnect_2_s0_io_clockcrossing_bridge_s0_debugaccess; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_debugaccess -> s0_io_clockCrossing_bridge:s0_debugaccess
wire mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdatavalid; // s0_io_clockCrossing_bridge:s0_readdatavalid -> mm_interconnect_2:s0_io_clockCrossing_bridge_s0_readdatavalid
wire [3:0] mm_interconnect_2_s0_io_clockcrossing_bridge_s0_byteenable; // mm_interconnect_2:s0_io_clockCrossing_bridge_s0_byteenable -> s0_io_clockCrossing_bridge:s0_byteenable
wire [3:0] cpu_s0_instruction_master_burstcount; // cpu_s0:i_burstcount -> mm_interconnect_2:cpu_s0_instruction_master_burstcount
wire cpu_s0_instruction_master_waitrequest; // mm_interconnect_2:cpu_s0_instruction_master_waitrequest -> cpu_s0:i_waitrequest
wire [27:0] cpu_s0_instruction_master_address; // cpu_s0:i_address -> mm_interconnect_2:cpu_s0_instruction_master_address
wire cpu_s0_instruction_master_read; // cpu_s0:i_read -> mm_interconnect_2:cpu_s0_instruction_master_read
wire [31:0] cpu_s0_instruction_master_readdata; // mm_interconnect_2:cpu_s0_instruction_master_readdata -> cpu_s0:i_readdata
wire cpu_s0_instruction_master_readdatavalid; // mm_interconnect_2:cpu_s0_instruction_master_readdatavalid -> cpu_s0:i_readdatavalid
wire mm_interconnect_2_sdram_clockcrossing_bridge_s0_waitrequest; // sdram_clockCrossing_Bridge:s0_waitrequest -> mm_interconnect_2:sdram_clockCrossing_Bridge_s0_waitrequest
wire [3:0] mm_interconnect_2_sdram_clockcrossing_bridge_s0_burstcount; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_burstcount -> sdram_clockCrossing_Bridge:s0_burstcount
wire [31:0] mm_interconnect_2_sdram_clockcrossing_bridge_s0_writedata; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_writedata -> sdram_clockCrossing_Bridge:s0_writedata
wire [25:0] mm_interconnect_2_sdram_clockcrossing_bridge_s0_address; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_address -> sdram_clockCrossing_Bridge:s0_address
wire mm_interconnect_2_sdram_clockcrossing_bridge_s0_write; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_write -> sdram_clockCrossing_Bridge:s0_write
wire mm_interconnect_2_sdram_clockcrossing_bridge_s0_read; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_read -> sdram_clockCrossing_Bridge:s0_read
wire [31:0] mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdata; // sdram_clockCrossing_Bridge:s0_readdata -> mm_interconnect_2:sdram_clockCrossing_Bridge_s0_readdata
wire mm_interconnect_2_sdram_clockcrossing_bridge_s0_debugaccess; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_debugaccess -> sdram_clockCrossing_Bridge:s0_debugaccess
wire mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdatavalid; // sdram_clockCrossing_Bridge:s0_readdatavalid -> mm_interconnect_2:sdram_clockCrossing_Bridge_s0_readdatavalid
wire [3:0] mm_interconnect_2_sdram_clockcrossing_bridge_s0_byteenable; // mm_interconnect_2:sdram_clockCrossing_Bridge_s0_byteenable -> sdram_clockCrossing_Bridge:s0_byteenable
wire [31:0] mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_writedata; // mm_interconnect_3:fifo_bridge_cpuM_cpus0_s1_writedata -> fifo_bridge_cpuM_cpus0:cpu2_writedata
wire [7:0] mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_address; // mm_interconnect_3:fifo_bridge_cpuM_cpus0_s1_address -> fifo_bridge_cpuM_cpus0:cpu2_address
wire mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_write; // mm_interconnect_3:fifo_bridge_cpuM_cpus0_s1_write -> fifo_bridge_cpuM_cpus0:cpu2_write
wire mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_read; // mm_interconnect_3:fifo_bridge_cpuM_cpus0_s1_read -> fifo_bridge_cpuM_cpus0:cpu2_read
wire [31:0] mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_readdata; // fifo_bridge_cpuM_cpus0:cpu2_readdata -> mm_interconnect_3:fifo_bridge_cpuM_cpus0_s1_readdata
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awvalid
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arsize
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arlock
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awcache
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_3:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arid
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_3:hps_0_h2f_lw_axi_master_rready
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_3:hps_0_h2f_lw_axi_master_bready
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awsize
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awprot
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arvalid
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arprot
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_3:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arlen
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_3:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awid
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_3:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_wid
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awlock
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awburst
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_3:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_3:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_3:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_3:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_3:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arburst
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_3:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_3:hps_0_h2f_lw_axi_master_araddr
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_3:hps_0_h2f_lw_axi_master_arcache
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awlen
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_3:hps_0_h2f_lw_axi_master_awaddr
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_3:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_3:hps_0_h2f_lw_axi_master_wvalid
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_3:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_3:hps_0_h2f_lw_axi_master_wlast
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_3:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire [31:0] mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_writedata; // mm_interconnect_3:fifo_bridge_cpuM_cpus1_s1_writedata -> fifo_bridge_cpuM_cpus1:cpu2_writedata
wire [7:0] mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_address; // mm_interconnect_3:fifo_bridge_cpuM_cpus1_s1_address -> fifo_bridge_cpuM_cpus1:cpu2_address
wire mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_write; // mm_interconnect_3:fifo_bridge_cpuM_cpus1_s1_write -> fifo_bridge_cpuM_cpus1:cpu2_write
wire mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_read; // mm_interconnect_3:fifo_bridge_cpuM_cpus1_s1_read -> fifo_bridge_cpuM_cpus1:cpu2_read
wire [31:0] mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_readdata; // fifo_bridge_cpuM_cpus1:cpu2_readdata -> mm_interconnect_3:fifo_bridge_cpuM_cpus1_s1_readdata
wire [31:0] mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_writedata; // mm_interconnect_4:fifo_bridge_cpus0_cpus1_s1_writedata -> fifo_bridge_cpus0_cpus1:cpu2_writedata
wire [7:0] mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_address; // mm_interconnect_4:fifo_bridge_cpus0_cpus1_s1_address -> fifo_bridge_cpus0_cpus1:cpu2_address
wire mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_write; // mm_interconnect_4:fifo_bridge_cpus0_cpus1_s1_write -> fifo_bridge_cpus0_cpus1:cpu2_write
wire mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_read; // mm_interconnect_4:fifo_bridge_cpus0_cpus1_s1_read -> fifo_bridge_cpus0_cpus1:cpu2_read
wire [31:0] mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_readdata; // fifo_bridge_cpus0_cpus1:cpu2_readdata -> mm_interconnect_4:fifo_bridge_cpus0_cpus1_s1_readdata
wire cpu_s1_instruction_master_waitrequest; // mm_interconnect_4:cpu_s1_instruction_master_waitrequest -> cpu_s1:i_waitrequest
wire [27:0] cpu_s1_instruction_master_address; // cpu_s1:i_address -> mm_interconnect_4:cpu_s1_instruction_master_address
wire cpu_s1_instruction_master_read; // cpu_s1:i_read -> mm_interconnect_4:cpu_s1_instruction_master_read
wire [31:0] cpu_s1_instruction_master_readdata; // mm_interconnect_4:cpu_s1_instruction_master_readdata -> cpu_s1:i_readdata
wire cpu_s1_instruction_master_readdatavalid; // mm_interconnect_4:cpu_s1_instruction_master_readdatavalid -> cpu_s1:i_readdatavalid
wire [31:0] mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_writedata; // mm_interconnect_4:fifo_bridge_cpuM_cpus1_s0_writedata -> fifo_bridge_cpuM_cpus1:cpu1_writedata
wire [7:0] mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_address; // mm_interconnect_4:fifo_bridge_cpuM_cpus1_s0_address -> fifo_bridge_cpuM_cpus1:cpu1_address
wire mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_write; // mm_interconnect_4:fifo_bridge_cpuM_cpus1_s0_write -> fifo_bridge_cpuM_cpus1:cpu1_write
wire mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_read; // mm_interconnect_4:fifo_bridge_cpuM_cpus1_s0_read -> fifo_bridge_cpuM_cpus1:cpu1_read
wire [31:0] mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_readdata; // fifo_bridge_cpuM_cpus1:cpu1_readdata -> mm_interconnect_4:fifo_bridge_cpuM_cpus1_s0_readdata
wire mm_interconnect_4_s1_io_clockcrossing_bridge_s0_waitrequest; // s1_io_clockCrossing_bridge:s0_waitrequest -> mm_interconnect_4:s1_io_clockCrossing_bridge_s0_waitrequest
wire [0:0] mm_interconnect_4_s1_io_clockcrossing_bridge_s0_burstcount; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_burstcount -> s1_io_clockCrossing_bridge:s0_burstcount
wire [31:0] mm_interconnect_4_s1_io_clockcrossing_bridge_s0_writedata; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_writedata -> s1_io_clockCrossing_bridge:s0_writedata
wire [9:0] mm_interconnect_4_s1_io_clockcrossing_bridge_s0_address; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_address -> s1_io_clockCrossing_bridge:s0_address
wire mm_interconnect_4_s1_io_clockcrossing_bridge_s0_write; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_write -> s1_io_clockCrossing_bridge:s0_write
wire mm_interconnect_4_s1_io_clockcrossing_bridge_s0_read; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_read -> s1_io_clockCrossing_bridge:s0_read
wire [31:0] mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdata; // s1_io_clockCrossing_bridge:s0_readdata -> mm_interconnect_4:s1_io_clockCrossing_bridge_s0_readdata
wire mm_interconnect_4_s1_io_clockcrossing_bridge_s0_debugaccess; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_debugaccess -> s1_io_clockCrossing_bridge:s0_debugaccess
wire mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdatavalid; // s1_io_clockCrossing_bridge:s0_readdatavalid -> mm_interconnect_4:s1_io_clockCrossing_bridge_s0_readdatavalid
wire [3:0] mm_interconnect_4_s1_io_clockcrossing_bridge_s0_byteenable; // mm_interconnect_4:s1_io_clockCrossing_bridge_s0_byteenable -> s1_io_clockCrossing_bridge:s0_byteenable
wire [31:0] mm_interconnect_4_onchip_sram_s1_writedata; // mm_interconnect_4:onchip_sram_s1_writedata -> onchip_sram:writedata
wire [16:0] mm_interconnect_4_onchip_sram_s1_address; // mm_interconnect_4:onchip_sram_s1_address -> onchip_sram:address
wire mm_interconnect_4_onchip_sram_s1_chipselect; // mm_interconnect_4:onchip_sram_s1_chipselect -> onchip_sram:chipselect
wire mm_interconnect_4_onchip_sram_s1_clken; // mm_interconnect_4:onchip_sram_s1_clken -> onchip_sram:clken
wire mm_interconnect_4_onchip_sram_s1_write; // mm_interconnect_4:onchip_sram_s1_write -> onchip_sram:write
wire [31:0] mm_interconnect_4_onchip_sram_s1_readdata; // onchip_sram:readdata -> mm_interconnect_4:onchip_sram_s1_readdata
wire [3:0] mm_interconnect_4_onchip_sram_s1_byteenable; // mm_interconnect_4:onchip_sram_s1_byteenable -> onchip_sram:byteenable
wire cpu_s1_data_master_waitrequest; // mm_interconnect_4:cpu_s1_data_master_waitrequest -> cpu_s1:d_waitrequest
wire [31:0] cpu_s1_data_master_writedata; // cpu_s1:d_writedata -> mm_interconnect_4:cpu_s1_data_master_writedata
wire [27:0] cpu_s1_data_master_address; // cpu_s1:d_address -> mm_interconnect_4:cpu_s1_data_master_address
wire cpu_s1_data_master_write; // cpu_s1:d_write -> mm_interconnect_4:cpu_s1_data_master_write
wire cpu_s1_data_master_read; // cpu_s1:d_read -> mm_interconnect_4:cpu_s1_data_master_read
wire [31:0] cpu_s1_data_master_readdata; // mm_interconnect_4:cpu_s1_data_master_readdata -> cpu_s1:d_readdata
wire cpu_s1_data_master_debugaccess; // cpu_s1:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_4:cpu_s1_data_master_debugaccess
wire [3:0] cpu_s1_data_master_byteenable; // cpu_s1:d_byteenable -> mm_interconnect_4:cpu_s1_data_master_byteenable
wire mm_interconnect_4_cpu_s1_jtag_debug_module_waitrequest; // cpu_s1:jtag_debug_module_waitrequest -> mm_interconnect_4:cpu_s1_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_4_cpu_s1_jtag_debug_module_writedata; // mm_interconnect_4:cpu_s1_jtag_debug_module_writedata -> cpu_s1:jtag_debug_module_writedata
wire [8:0] mm_interconnect_4_cpu_s1_jtag_debug_module_address; // mm_interconnect_4:cpu_s1_jtag_debug_module_address -> cpu_s1:jtag_debug_module_address
wire mm_interconnect_4_cpu_s1_jtag_debug_module_write; // mm_interconnect_4:cpu_s1_jtag_debug_module_write -> cpu_s1:jtag_debug_module_write
wire mm_interconnect_4_cpu_s1_jtag_debug_module_read; // mm_interconnect_4:cpu_s1_jtag_debug_module_read -> cpu_s1:jtag_debug_module_read
wire [31:0] mm_interconnect_4_cpu_s1_jtag_debug_module_readdata; // cpu_s1:jtag_debug_module_readdata -> mm_interconnect_4:cpu_s1_jtag_debug_module_readdata
wire mm_interconnect_4_cpu_s1_jtag_debug_module_debugaccess; // mm_interconnect_4:cpu_s1_jtag_debug_module_debugaccess -> cpu_s1:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_4_cpu_s1_jtag_debug_module_byteenable; // mm_interconnect_4:cpu_s1_jtag_debug_module_byteenable -> cpu_s1:jtag_debug_module_byteenable
wire [31:0] mm_interconnect_5_pwm_cpu_s0_3_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_3_s0_writedata -> pwm_cpu_s0_3:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_3_s0_write; // mm_interconnect_5:pwm_cpu_s0_3_s0_write -> pwm_cpu_s0_3:avs_s0_write
wire [31:0] mm_interconnect_5_pwm_cpu_s0_5_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_5_s0_writedata -> pwm_cpu_s0_5:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_5_s0_write; // mm_interconnect_5:pwm_cpu_s0_5_s0_write -> pwm_cpu_s0_5:avs_s0_write
wire [0:0] s0_io_clockcrossing_bridge_m0_burstcount; // s0_io_clockCrossing_bridge:m0_burstcount -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_burstcount
wire s0_io_clockcrossing_bridge_m0_waitrequest; // mm_interconnect_5:s0_io_clockCrossing_bridge_m0_waitrequest -> s0_io_clockCrossing_bridge:m0_waitrequest
wire [9:0] s0_io_clockcrossing_bridge_m0_address; // s0_io_clockCrossing_bridge:m0_address -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_address
wire [31:0] s0_io_clockcrossing_bridge_m0_writedata; // s0_io_clockCrossing_bridge:m0_writedata -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_writedata
wire s0_io_clockcrossing_bridge_m0_write; // s0_io_clockCrossing_bridge:m0_write -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_write
wire s0_io_clockcrossing_bridge_m0_read; // s0_io_clockCrossing_bridge:m0_read -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_read
wire [31:0] s0_io_clockcrossing_bridge_m0_readdata; // mm_interconnect_5:s0_io_clockCrossing_bridge_m0_readdata -> s0_io_clockCrossing_bridge:m0_readdata
wire s0_io_clockcrossing_bridge_m0_debugaccess; // s0_io_clockCrossing_bridge:m0_debugaccess -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_debugaccess
wire [3:0] s0_io_clockcrossing_bridge_m0_byteenable; // s0_io_clockCrossing_bridge:m0_byteenable -> mm_interconnect_5:s0_io_clockCrossing_bridge_m0_byteenable
wire s0_io_clockcrossing_bridge_m0_readdatavalid; // mm_interconnect_5:s0_io_clockCrossing_bridge_m0_readdatavalid -> s0_io_clockCrossing_bridge:m0_readdatavalid
wire [31:0] mm_interconnect_5_pwm_cpu_s0_1_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_1_s0_writedata -> pwm_cpu_s0_1:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_1_s0_write; // mm_interconnect_5:pwm_cpu_s0_1_s0_write -> pwm_cpu_s0_1:avs_s0_write
wire [31:0] mm_interconnect_5_pio_alivetest_cpu_s0_s1_writedata; // mm_interconnect_5:pio_aliveTest_cpu_s0_s1_writedata -> pio_aliveTest_cpu_s0:writedata
wire [1:0] mm_interconnect_5_pio_alivetest_cpu_s0_s1_address; // mm_interconnect_5:pio_aliveTest_cpu_s0_s1_address -> pio_aliveTest_cpu_s0:address
wire mm_interconnect_5_pio_alivetest_cpu_s0_s1_chipselect; // mm_interconnect_5:pio_aliveTest_cpu_s0_s1_chipselect -> pio_aliveTest_cpu_s0:chipselect
wire mm_interconnect_5_pio_alivetest_cpu_s0_s1_write; // mm_interconnect_5:pio_aliveTest_cpu_s0_s1_write -> pio_aliveTest_cpu_s0:write_n
wire [31:0] mm_interconnect_5_pio_alivetest_cpu_s0_s1_readdata; // pio_aliveTest_cpu_s0:readdata -> mm_interconnect_5:pio_aliveTest_cpu_s0_s1_readdata
wire [15:0] mm_interconnect_5_timer_cpu_s0_s1_writedata; // mm_interconnect_5:timer_cpu_s0_s1_writedata -> timer_cpu_s0:writedata
wire [2:0] mm_interconnect_5_timer_cpu_s0_s1_address; // mm_interconnect_5:timer_cpu_s0_s1_address -> timer_cpu_s0:address
wire mm_interconnect_5_timer_cpu_s0_s1_chipselect; // mm_interconnect_5:timer_cpu_s0_s1_chipselect -> timer_cpu_s0:chipselect
wire mm_interconnect_5_timer_cpu_s0_s1_write; // mm_interconnect_5:timer_cpu_s0_s1_write -> timer_cpu_s0:write_n
wire [15:0] mm_interconnect_5_timer_cpu_s0_s1_readdata; // timer_cpu_s0:readdata -> mm_interconnect_5:timer_cpu_s0_s1_readdata
wire mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_waitrequest; // jtag_uart_cpu_s0:av_waitrequest -> mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_writedata; // mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_writedata -> jtag_uart_cpu_s0:av_writedata
wire [0:0] mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_address; // mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_address -> jtag_uart_cpu_s0:av_address
wire mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_chipselect; // mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_chipselect -> jtag_uart_cpu_s0:av_chipselect
wire mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_write; // mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_write -> jtag_uart_cpu_s0:av_write_n
wire mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_read; // mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_read -> jtag_uart_cpu_s0:av_read_n
wire [31:0] mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_readdata; // jtag_uart_cpu_s0:av_readdata -> mm_interconnect_5:jtag_uart_cpu_s0_avalon_jtag_slave_readdata
wire [31:0] mm_interconnect_5_pwm_cpu_s0_7_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_7_s0_writedata -> pwm_cpu_s0_7:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_7_s0_write; // mm_interconnect_5:pwm_cpu_s0_7_s0_write -> pwm_cpu_s0_7:avs_s0_write
wire mm_interconnect_5_i2c_cpu_s0_mm_slave_waitrequest; // i2c_cpu_s0:wb_ack_o -> mm_interconnect_5:i2c_cpu_s0_mm_slave_waitrequest
wire [7:0] mm_interconnect_5_i2c_cpu_s0_mm_slave_writedata; // mm_interconnect_5:i2c_cpu_s0_mm_slave_writedata -> i2c_cpu_s0:wb_dat_i
wire [2:0] mm_interconnect_5_i2c_cpu_s0_mm_slave_address; // mm_interconnect_5:i2c_cpu_s0_mm_slave_address -> i2c_cpu_s0:wb_adr_i
wire mm_interconnect_5_i2c_cpu_s0_mm_slave_chipselect; // mm_interconnect_5:i2c_cpu_s0_mm_slave_chipselect -> i2c_cpu_s0:wb_cyc_i
wire mm_interconnect_5_i2c_cpu_s0_mm_slave_write; // mm_interconnect_5:i2c_cpu_s0_mm_slave_write -> i2c_cpu_s0:wb_we_i
wire [7:0] mm_interconnect_5_i2c_cpu_s0_mm_slave_readdata; // i2c_cpu_s0:wb_dat_o -> mm_interconnect_5:i2c_cpu_s0_mm_slave_readdata
wire [31:0] mm_interconnect_5_pwm_cpu_s0_2_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_2_s0_writedata -> pwm_cpu_s0_2:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_2_s0_write; // mm_interconnect_5:pwm_cpu_s0_2_s0_write -> pwm_cpu_s0_2:avs_s0_write
wire [31:0] mm_interconnect_5_pwm_cpu_s0_6_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_6_s0_writedata -> pwm_cpu_s0_6:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_6_s0_write; // mm_interconnect_5:pwm_cpu_s0_6_s0_write -> pwm_cpu_s0_6:avs_s0_write
wire [31:0] mm_interconnect_5_pwm_cpu_s0_8_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_8_s0_writedata -> pwm_cpu_s0_8:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_8_s0_write; // mm_interconnect_5:pwm_cpu_s0_8_s0_write -> pwm_cpu_s0_8:avs_s0_write
wire [31:0] mm_interconnect_5_pwm_cpu_s0_4_s0_writedata; // mm_interconnect_5:pwm_cpu_s0_4_s0_writedata -> pwm_cpu_s0_4:avs_s0_writedata
wire mm_interconnect_5_pwm_cpu_s0_4_s0_write; // mm_interconnect_5:pwm_cpu_s0_4_s0_write -> pwm_cpu_s0_4:avs_s0_write
wire [3:0] sdram_clockcrossing_bridge_m0_burstcount; // sdram_clockCrossing_Bridge:m0_burstcount -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_burstcount
wire sdram_clockcrossing_bridge_m0_waitrequest; // mm_interconnect_6:sdram_clockCrossing_Bridge_m0_waitrequest -> sdram_clockCrossing_Bridge:m0_waitrequest
wire [25:0] sdram_clockcrossing_bridge_m0_address; // sdram_clockCrossing_Bridge:m0_address -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_address
wire [31:0] sdram_clockcrossing_bridge_m0_writedata; // sdram_clockCrossing_Bridge:m0_writedata -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_writedata
wire sdram_clockcrossing_bridge_m0_write; // sdram_clockCrossing_Bridge:m0_write -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_write
wire sdram_clockcrossing_bridge_m0_read; // sdram_clockCrossing_Bridge:m0_read -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_read
wire [31:0] sdram_clockcrossing_bridge_m0_readdata; // mm_interconnect_6:sdram_clockCrossing_Bridge_m0_readdata -> sdram_clockCrossing_Bridge:m0_readdata
wire sdram_clockcrossing_bridge_m0_debugaccess; // sdram_clockCrossing_Bridge:m0_debugaccess -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_debugaccess
wire [3:0] sdram_clockcrossing_bridge_m0_byteenable; // sdram_clockCrossing_Bridge:m0_byteenable -> mm_interconnect_6:sdram_clockCrossing_Bridge_m0_byteenable
wire sdram_clockcrossing_bridge_m0_readdatavalid; // mm_interconnect_6:sdram_clockCrossing_Bridge_m0_readdatavalid -> sdram_clockCrossing_Bridge:m0_readdatavalid
wire mm_interconnect_6_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_6:sdram_s1_waitrequest
wire [15:0] mm_interconnect_6_sdram_s1_writedata; // mm_interconnect_6:sdram_s1_writedata -> sdram:az_data
wire [24:0] mm_interconnect_6_sdram_s1_address; // mm_interconnect_6:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_6_sdram_s1_chipselect; // mm_interconnect_6:sdram_s1_chipselect -> sdram:az_cs
wire mm_interconnect_6_sdram_s1_write; // mm_interconnect_6:sdram_s1_write -> sdram:az_wr_n
wire mm_interconnect_6_sdram_s1_read; // mm_interconnect_6:sdram_s1_read -> sdram:az_rd_n
wire [15:0] mm_interconnect_6_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_6:sdram_s1_readdata
wire mm_interconnect_6_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_6:sdram_s1_readdatavalid
wire [1:0] mm_interconnect_6_sdram_s1_byteenable; // mm_interconnect_6:sdram_s1_byteenable -> sdram:az_be_n
wire [0:0] s1_io_clockcrossing_bridge_m0_burstcount; // s1_io_clockCrossing_bridge:m0_burstcount -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_burstcount
wire s1_io_clockcrossing_bridge_m0_waitrequest; // mm_interconnect_7:s1_io_clockCrossing_bridge_m0_waitrequest -> s1_io_clockCrossing_bridge:m0_waitrequest
wire [9:0] s1_io_clockcrossing_bridge_m0_address; // s1_io_clockCrossing_bridge:m0_address -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_address
wire [31:0] s1_io_clockcrossing_bridge_m0_writedata; // s1_io_clockCrossing_bridge:m0_writedata -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_writedata
wire s1_io_clockcrossing_bridge_m0_write; // s1_io_clockCrossing_bridge:m0_write -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_write
wire s1_io_clockcrossing_bridge_m0_read; // s1_io_clockCrossing_bridge:m0_read -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_read
wire [31:0] s1_io_clockcrossing_bridge_m0_readdata; // mm_interconnect_7:s1_io_clockCrossing_bridge_m0_readdata -> s1_io_clockCrossing_bridge:m0_readdata
wire s1_io_clockcrossing_bridge_m0_debugaccess; // s1_io_clockCrossing_bridge:m0_debugaccess -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_debugaccess
wire [3:0] s1_io_clockcrossing_bridge_m0_byteenable; // s1_io_clockCrossing_bridge:m0_byteenable -> mm_interconnect_7:s1_io_clockCrossing_bridge_m0_byteenable
wire s1_io_clockcrossing_bridge_m0_readdatavalid; // mm_interconnect_7:s1_io_clockCrossing_bridge_m0_readdatavalid -> s1_io_clockCrossing_bridge:m0_readdatavalid
wire mm_interconnect_7_i2c_cpu_s1_mm_slave_waitrequest; // i2c_cpu_s1:wb_ack_o -> mm_interconnect_7:i2c_cpu_s1_mm_slave_waitrequest
wire [7:0] mm_interconnect_7_i2c_cpu_s1_mm_slave_writedata; // mm_interconnect_7:i2c_cpu_s1_mm_slave_writedata -> i2c_cpu_s1:wb_dat_i
wire [2:0] mm_interconnect_7_i2c_cpu_s1_mm_slave_address; // mm_interconnect_7:i2c_cpu_s1_mm_slave_address -> i2c_cpu_s1:wb_adr_i
wire mm_interconnect_7_i2c_cpu_s1_mm_slave_chipselect; // mm_interconnect_7:i2c_cpu_s1_mm_slave_chipselect -> i2c_cpu_s1:wb_cyc_i
wire mm_interconnect_7_i2c_cpu_s1_mm_slave_write; // mm_interconnect_7:i2c_cpu_s1_mm_slave_write -> i2c_cpu_s1:wb_we_i
wire [7:0] mm_interconnect_7_i2c_cpu_s1_mm_slave_readdata; // i2c_cpu_s1:wb_dat_o -> mm_interconnect_7:i2c_cpu_s1_mm_slave_readdata
wire [15:0] mm_interconnect_7_timer_cpu_s1_s1_writedata; // mm_interconnect_7:timer_cpu_s1_s1_writedata -> timer_cpu_s1:writedata
wire [2:0] mm_interconnect_7_timer_cpu_s1_s1_address; // mm_interconnect_7:timer_cpu_s1_s1_address -> timer_cpu_s1:address
wire mm_interconnect_7_timer_cpu_s1_s1_chipselect; // mm_interconnect_7:timer_cpu_s1_s1_chipselect -> timer_cpu_s1:chipselect
wire mm_interconnect_7_timer_cpu_s1_s1_write; // mm_interconnect_7:timer_cpu_s1_s1_write -> timer_cpu_s1:write_n
wire [15:0] mm_interconnect_7_timer_cpu_s1_s1_readdata; // timer_cpu_s1:readdata -> mm_interconnect_7:timer_cpu_s1_s1_readdata
wire mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_waitrequest; // jtag_uart_cpu_s1:av_waitrequest -> mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_writedata; // mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_writedata -> jtag_uart_cpu_s1:av_writedata
wire [0:0] mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_address; // mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_address -> jtag_uart_cpu_s1:av_address
wire mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_chipselect; // mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_chipselect -> jtag_uart_cpu_s1:av_chipselect
wire mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_write; // mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_write -> jtag_uart_cpu_s1:av_write_n
wire mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_read; // mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_read -> jtag_uart_cpu_s1:av_read_n
wire [31:0] mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_readdata; // jtag_uart_cpu_s1:av_readdata -> mm_interconnect_7:jtag_uart_cpu_s1_avalon_jtag_slave_readdata
wire [31:0] mm_interconnect_7_pio_alivetest_cpu_s1_s1_writedata; // mm_interconnect_7:pio_aliveTest_cpu_s1_s1_writedata -> pio_aliveTest_cpu_s1:writedata
wire [1:0] mm_interconnect_7_pio_alivetest_cpu_s1_s1_address; // mm_interconnect_7:pio_aliveTest_cpu_s1_s1_address -> pio_aliveTest_cpu_s1:address
wire mm_interconnect_7_pio_alivetest_cpu_s1_s1_chipselect; // mm_interconnect_7:pio_aliveTest_cpu_s1_s1_chipselect -> pio_aliveTest_cpu_s1:chipselect
wire mm_interconnect_7_pio_alivetest_cpu_s1_s1_write; // mm_interconnect_7:pio_aliveTest_cpu_s1_s1_write -> pio_aliveTest_cpu_s1:write_n
wire [31:0] mm_interconnect_7_pio_alivetest_cpu_s1_s1_readdata; // pio_aliveTest_cpu_s1:readdata -> mm_interconnect_7:pio_aliveTest_cpu_s1_s1_readdata
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_003_receiver2_irq; // fifo_bridge_cpuM_cpus0:cpu1_irq -> irq_mapper_003:receiver2_irq
wire irq_mapper_003_receiver3_irq; // fifo_bridge_cpus0_cpus1:cpu1_irq -> irq_mapper_003:receiver3_irq
wire [31:0] cpu_s0_d_irq_irq; // irq_mapper_003:sender_irq -> cpu_s0:d_irq
wire irq_mapper_004_receiver2_irq; // fifo_bridge_cpuM_cpus1:cpu1_irq -> irq_mapper_004:receiver2_irq
wire irq_mapper_004_receiver3_irq; // fifo_bridge_cpus0_cpus1:cpu2_irq -> irq_mapper_004:receiver3_irq
wire [31:0] cpu_s1_d_irq_irq; // irq_mapper_004:sender_irq -> cpu_s1:d_irq
wire irq_mapper_003_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper_003:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // timer_cpu_s0:irq -> irq_synchronizer:receiver_irq
wire irq_mapper_003_receiver1_irq; // irq_synchronizer_001:sender_irq -> irq_mapper_003:receiver1_irq
wire [0:0] irq_synchronizer_001_receiver_irq; // jtag_uart_cpu_s0:av_irq -> irq_synchronizer_001:receiver_irq
wire irq_mapper_003_receiver4_irq; // irq_synchronizer_002:sender_irq -> irq_mapper_003:receiver4_irq
wire [0:0] irq_synchronizer_002_receiver_irq; // i2c_cpu_s0:wb_inta_o -> irq_synchronizer_002:receiver_irq
wire irq_mapper_004_receiver0_irq; // irq_synchronizer_003:sender_irq -> irq_mapper_004:receiver0_irq
wire [0:0] irq_synchronizer_003_receiver_irq; // timer_cpu_s1:irq -> irq_synchronizer_003:receiver_irq
wire irq_mapper_004_receiver1_irq; // irq_synchronizer_004:sender_irq -> irq_mapper_004:receiver1_irq
wire [0:0] irq_synchronizer_004_receiver_irq; // jtag_uart_cpu_s1:av_irq -> irq_synchronizer_004:receiver_irq
wire irq_mapper_004_receiver4_irq; // irq_synchronizer_005:sender_irq -> irq_mapper_004:receiver4_irq
wire [0:0] irq_synchronizer_005_receiver_irq; // i2c_cpu_s1:wb_inta_o -> irq_synchronizer_005:receiver_irq
wire irq_mapper_receiver0_irq; // fifo_bridge_cpuM_cpus0:cpu2_irq -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver1_irq]
wire irq_mapper_receiver1_irq; // fifo_bridge_cpuM_cpus1:cpu2_irq -> [irq_mapper:receiver1_irq, irq_mapper_002:receiver0_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu_s0:reset_n, cpu_s1:reset_n, fifo_bridge_cpuM_cpus0:reset, fifo_bridge_cpuM_cpus1:reset, fifo_bridge_cpus0_cpus1:reset, intr_capturer_0:rst_n, irq_mapper_002:reset, irq_mapper_003:reset, irq_mapper_004:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, irq_synchronizer_003:sender_reset, irq_synchronizer_004:sender_reset, irq_synchronizer_005:sender_reset, mm_interconnect_0:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_1:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:intr_capturer_0_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_2:cpu_s0_reset_n_reset_bridge_in_reset_reset, mm_interconnect_3:fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset, mm_interconnect_4:cpu_s1_reset_n_reset_bridge_in_reset_reset, onchip_sram:reset, rst_translator:in_reset, s0_io_clockCrossing_bridge:s0_reset, s1_io_clockCrossing_bridge:s0_reset, sdram_clockCrossing_Bridge:s0_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu_s0:reset_req, cpu_s1:reset_req, onchip_sram:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [i2c_cpu_s0:wb_rst_i, i2c_cpu_s1:wb_rst_i, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, irq_synchronizer_003:receiver_reset, irq_synchronizer_004:receiver_reset, irq_synchronizer_005:receiver_reset, jtag_uart_cpu_s0:rst_n, jtag_uart_cpu_s1:rst_n, mm_interconnect_5:s0_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset_reset, mm_interconnect_7:s1_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset_reset, pio_aliveTest_cpu_s0:reset_n, pio_aliveTest_cpu_s1:reset_n, s0_io_clockCrossing_bridge:m0_reset, s1_io_clockCrossing_bridge:m0_reset, timer_cpu_s0:reset_n, timer_cpu_s1:reset_n]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_6:sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset, sdram:reset_n, sdram_clockCrossing_Bridge:m0_reset]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [pwm_pll:rst, sdram_pll:rst, system_pll:rst]
wire rst_controller_004_reset_out_reset; // rst_controller_004:reset_out -> [mm_interconnect_5:pwm_cpu_s0_1_clock_reset_reset_bridge_in_reset_reset, pwm_cpu_s0_1:reset, pwm_cpu_s0_2:reset, pwm_cpu_s0_3:reset, pwm_cpu_s0_4:reset, pwm_cpu_s0_5:reset, pwm_cpu_s0_6:reset, pwm_cpu_s0_7:reset, pwm_cpu_s0_8:reset]
wire rst_controller_005_reset_out_reset; // rst_controller_005:reset_out -> [mm_interconnect_0:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_3:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset]
soc_system_hps_0 #(
.F2S_Width (2),
.S2F_Width (2)
) hps_0 (
.f2h_cold_rst_req_n (hps_0_f2h_cold_reset_req_reset_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (hps_0_f2h_debug_reset_req_reset_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (hps_0_f2h_warm_reset_req_reset_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (hps_0_f2h_stm_hw_events_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_0_hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_0_hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_0_hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_0_hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_0_hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_0_hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_0_hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (), // h2f_axi_master.awid
.h2f_AWADDR (), // .awaddr
.h2f_AWLEN (), // .awlen
.h2f_AWSIZE (), // .awsize
.h2f_AWBURST (), // .awburst
.h2f_AWLOCK (), // .awlock
.h2f_AWCACHE (), // .awcache
.h2f_AWPROT (), // .awprot
.h2f_AWVALID (), // .awvalid
.h2f_AWREADY (), // .awready
.h2f_WID (), // .wid
.h2f_WDATA (), // .wdata
.h2f_WSTRB (), // .wstrb
.h2f_WLAST (), // .wlast
.h2f_WVALID (), // .wvalid
.h2f_WREADY (), // .wready
.h2f_BID (), // .bid
.h2f_BRESP (), // .bresp
.h2f_BVALID (), // .bvalid
.h2f_BREADY (), // .bready
.h2f_ARID (), // .arid
.h2f_ARADDR (), // .araddr
.h2f_ARLEN (), // .arlen
.h2f_ARSIZE (), // .arsize
.h2f_ARBURST (), // .arburst
.h2f_ARLOCK (), // .arlock
.h2f_ARCACHE (), // .arcache
.h2f_ARPROT (), // .arprot
.h2f_ARVALID (), // .arvalid
.h2f_ARREADY (), // .arready
.h2f_RID (), // .rid
.h2f_RDATA (), // .rdata
.h2f_RRESP (), // .rresp
.h2f_RLAST (), // .rlast
.h2f_RVALID (), // .rvalid
.h2f_RREADY (), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
soc_system_onchip_sram onchip_sram (
.clk (system_pll_outclk0_clk), // clk1.clk
.address (mm_interconnect_4_onchip_sram_s1_address), // s1.address
.clken (mm_interconnect_4_onchip_sram_s1_clken), // .clken
.chipselect (mm_interconnect_4_onchip_sram_s1_chipselect), // .chipselect
.write (mm_interconnect_4_onchip_sram_s1_write), // .write
.readdata (mm_interconnect_4_onchip_sram_s1_readdata), // .readdata
.writedata (mm_interconnect_4_onchip_sram_s1_writedata), // .writedata
.byteenable (mm_interconnect_4_onchip_sram_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_system_hps_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (system_pll_outclk0_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_sysid_qsys sysid_qsys (
.clock (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_1_sysid_qsys_control_slave_address) // .address
);
soc_system_hps_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (system_pll_outclk0_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (system_pll_outclk0_clk), // clock.clk
.rst_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_pio_aliveTest_cpu_s0 pio_alivetest_cpu_s0 (
.clk (system_pll_outclk1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_5_pio_alivetest_cpu_s0_s1_address), // s1.address
.write_n (~mm_interconnect_5_pio_alivetest_cpu_s0_s1_write), // .write_n
.writedata (mm_interconnect_5_pio_alivetest_cpu_s0_s1_writedata), // .writedata
.chipselect (mm_interconnect_5_pio_alivetest_cpu_s0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_5_pio_alivetest_cpu_s0_s1_readdata), // .readdata
.out_port (pio_alivetest_cpu_s0_extcon_export) // external_connection.export
);
soc_system_cpu_s0 cpu_s0 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (cpu_s0_data_master_address), // data_master.address
.d_byteenable (cpu_s0_data_master_byteenable), // .byteenable
.d_read (cpu_s0_data_master_read), // .read
.d_readdata (cpu_s0_data_master_readdata), // .readdata
.d_waitrequest (cpu_s0_data_master_waitrequest), // .waitrequest
.d_write (cpu_s0_data_master_write), // .write
.d_writedata (cpu_s0_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_s0_data_master_debugaccess), // .debugaccess
.i_address (cpu_s0_instruction_master_address), // instruction_master.address
.i_read (cpu_s0_instruction_master_read), // .read
.i_readdata (cpu_s0_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_s0_instruction_master_waitrequest), // .waitrequest
.i_burstcount (cpu_s0_instruction_master_burstcount), // .burstcount
.i_readdatavalid (cpu_s0_instruction_master_readdatavalid), // .readdatavalid
.d_irq (cpu_s0_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_2_cpu_s0_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_2_cpu_s0_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_2_cpu_s0_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_2_cpu_s0_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_2_cpu_s0_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_2_cpu_s0_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_2_cpu_s0_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_2_cpu_s0_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
soc_system_timer_cpu_s0 timer_cpu_s0 (
.clk (system_pll_outclk1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_5_timer_cpu_s0_s1_address), // s1.address
.writedata (mm_interconnect_5_timer_cpu_s0_s1_writedata), // .writedata
.readdata (mm_interconnect_5_timer_cpu_s0_s1_readdata), // .readdata
.chipselect (mm_interconnect_5_timer_cpu_s0_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_5_timer_cpu_s0_s1_write), // .write_n
.irq (irq_synchronizer_receiver_irq) // irq.irq
);
soc_system_jtag_uart_cpu_s0 jtag_uart_cpu_s0 (
.clk (system_pll_outclk1_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_synchronizer_001_receiver_irq) // irq.irq
);
soc_system_sdram sdram (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_6_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_6_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_6_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_6_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_6_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_6_sdram_s1_write), // .write_n
.za_data (mm_interconnect_6_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_6_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_6_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
CPU_FiFo_Bridge fifo_bridge_cpum_cpus0 (
.clk (system_pll_outclk0_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // clock_reset.reset
.cpu1_address (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_address), // s0.address
.cpu1_read (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_read), // .read
.cpu1_readdata (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_readdata), // .readdata
.cpu1_write (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_write), // .write
.cpu1_writedata (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_writedata), // .writedata
.cpu1_irq (irq_mapper_003_receiver2_irq), // irq0.irq
.cpu2_address (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_address), // s1.address
.cpu2_read (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_read), // .read
.cpu2_readdata (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_readdata), // .readdata
.cpu2_writedata (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_writedata), // .writedata
.cpu2_write (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_write), // .write
.cpu2_irq (irq_mapper_receiver0_irq) // irq1.irq
);
soc_system_cpu_s1 cpu_s1 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (cpu_s1_data_master_address), // data_master.address
.d_byteenable (cpu_s1_data_master_byteenable), // .byteenable
.d_read (cpu_s1_data_master_read), // .read
.d_readdata (cpu_s1_data_master_readdata), // .readdata
.d_waitrequest (cpu_s1_data_master_waitrequest), // .waitrequest
.d_write (cpu_s1_data_master_write), // .write
.d_writedata (cpu_s1_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_s1_data_master_debugaccess), // .debugaccess
.i_address (cpu_s1_instruction_master_address), // instruction_master.address
.i_read (cpu_s1_instruction_master_read), // .read
.i_readdata (cpu_s1_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_s1_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (cpu_s1_instruction_master_readdatavalid), // .readdatavalid
.d_irq (cpu_s1_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_4_cpu_s1_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_4_cpu_s1_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_4_cpu_s1_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_4_cpu_s1_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_4_cpu_s1_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_4_cpu_s1_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_4_cpu_s1_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_4_cpu_s1_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
soc_system_timer_cpu_s0 timer_cpu_s1 (
.clk (system_pll_outclk1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_7_timer_cpu_s1_s1_address), // s1.address
.writedata (mm_interconnect_7_timer_cpu_s1_s1_writedata), // .writedata
.readdata (mm_interconnect_7_timer_cpu_s1_s1_readdata), // .readdata
.chipselect (mm_interconnect_7_timer_cpu_s1_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_7_timer_cpu_s1_s1_write), // .write_n
.irq (irq_synchronizer_003_receiver_irq) // irq.irq
);
soc_system_jtag_uart_cpu_s0 jtag_uart_cpu_s1 (
.clk (system_pll_outclk1_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_synchronizer_004_receiver_irq) // irq.irq
);
soc_system_pio_aliveTest_cpu_s0 pio_alivetest_cpu_s1 (
.clk (system_pll_outclk1_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_7_pio_alivetest_cpu_s1_s1_address), // s1.address
.write_n (~mm_interconnect_7_pio_alivetest_cpu_s1_s1_write), // .write_n
.writedata (mm_interconnect_7_pio_alivetest_cpu_s1_s1_writedata), // .writedata
.chipselect (mm_interconnect_7_pio_alivetest_cpu_s1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_7_pio_alivetest_cpu_s1_s1_readdata), // .readdata
.out_port (pio_alivetest_cpu_s1_extcon_export) // external_connection.export
);
CPU_FiFo_Bridge fifo_bridge_cpus0_cpus1 (
.clk (system_pll_outclk0_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // clock_reset.reset
.cpu1_address (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_address), // s0.address
.cpu1_read (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_read), // .read
.cpu1_readdata (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_readdata), // .readdata
.cpu1_write (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_write), // .write
.cpu1_writedata (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_writedata), // .writedata
.cpu1_irq (irq_mapper_003_receiver3_irq), // irq0.irq
.cpu2_address (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_address), // s1.address
.cpu2_read (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_read), // .read
.cpu2_readdata (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_readdata), // .readdata
.cpu2_writedata (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_writedata), // .writedata
.cpu2_write (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_write), // .write
.cpu2_irq (irq_mapper_004_receiver3_irq) // irq1.irq
);
CPU_FiFo_Bridge fifo_bridge_cpum_cpus1 (
.clk (system_pll_outclk0_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // clock_reset.reset
.cpu1_address (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_address), // s0.address
.cpu1_read (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_read), // .read
.cpu1_readdata (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_readdata), // .readdata
.cpu1_write (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_write), // .write
.cpu1_writedata (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_writedata), // .writedata
.cpu1_irq (irq_mapper_004_receiver2_irq), // irq0.irq
.cpu2_address (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_address), // s1.address
.cpu2_read (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_read), // .read
.cpu2_readdata (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_readdata), // .readdata
.cpu2_writedata (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_writedata), // .writedata
.cpu2_write (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_write), // .write
.cpu2_irq (irq_mapper_receiver1_irq) // irq1.irq
);
soc_system_system_pll system_pll (
.refclk (clk_clk), // refclk.clk
.rst (rst_controller_003_reset_out_reset), // reset.reset
.outclk_0 (system_pll_outclk0_clk), // outclk0.clk
.outclk_1 (system_pll_outclk1_clk), // outclk1.clk
.locked (system_pll_locked_export) // locked.export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (10),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (4),
.RESPONSE_FIFO_DEPTH (4),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) s0_io_clockcrossing_bridge (
.m0_clk (system_pll_outclk1_clk), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (system_pll_outclk0_clk), // s0_clk.clk
.s0_reset (rst_controller_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_address), // .address
.s0_write (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_write), // .write
.s0_read (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (s0_io_clockcrossing_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (s0_io_clockcrossing_bridge_m0_readdata), // .readdata
.m0_readdatavalid (s0_io_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (s0_io_clockcrossing_bridge_m0_burstcount), // .burstcount
.m0_writedata (s0_io_clockcrossing_bridge_m0_writedata), // .writedata
.m0_address (s0_io_clockcrossing_bridge_m0_address), // .address
.m0_write (s0_io_clockcrossing_bridge_m0_write), // .write
.m0_read (s0_io_clockcrossing_bridge_m0_read), // .read
.m0_byteenable (s0_io_clockcrossing_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (s0_io_clockcrossing_bridge_m0_debugaccess) // .debugaccess
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (26),
.BURSTCOUNT_WIDTH (4),
.COMMAND_FIFO_DEPTH (4),
.RESPONSE_FIFO_DEPTH (16),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) sdram_clockcrossing_bridge (
.m0_clk (sdram_pll_outclk0_clk), // m0_clk.clk
.m0_reset (rst_controller_002_reset_out_reset), // m0_reset.reset
.s0_clk (system_pll_outclk0_clk), // s0_clk.clk
.s0_reset (rst_controller_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_2_sdram_clockcrossing_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_2_sdram_clockcrossing_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_2_sdram_clockcrossing_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_2_sdram_clockcrossing_bridge_s0_address), // .address
.s0_write (mm_interconnect_2_sdram_clockcrossing_bridge_s0_write), // .write
.s0_read (mm_interconnect_2_sdram_clockcrossing_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_2_sdram_clockcrossing_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_2_sdram_clockcrossing_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (sdram_clockcrossing_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (sdram_clockcrossing_bridge_m0_readdata), // .readdata
.m0_readdatavalid (sdram_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (sdram_clockcrossing_bridge_m0_burstcount), // .burstcount
.m0_writedata (sdram_clockcrossing_bridge_m0_writedata), // .writedata
.m0_address (sdram_clockcrossing_bridge_m0_address), // .address
.m0_write (sdram_clockcrossing_bridge_m0_write), // .write
.m0_read (sdram_clockcrossing_bridge_m0_read), // .read
.m0_byteenable (sdram_clockcrossing_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_clockcrossing_bridge_m0_debugaccess) // .debugaccess
);
soc_system_sdram_pll sdram_pll (
.refclk (clk_clk), // refclk.clk
.rst (rst_controller_003_reset_out_reset), // reset.reset
.outclk_0 (sdram_pll_outclk0_clk), // outclk0.clk
.outclk_1 (clk_sdram_clk), // outclk1.clk
.locked (sdram_pll_locked_export) // locked.export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (10),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (4),
.RESPONSE_FIFO_DEPTH (4),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) s1_io_clockcrossing_bridge (
.m0_clk (system_pll_outclk1_clk), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (system_pll_outclk0_clk), // s0_clk.clk
.s0_reset (rst_controller_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_address), // .address
.s0_write (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_write), // .write
.s0_read (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (s1_io_clockcrossing_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (s1_io_clockcrossing_bridge_m0_readdata), // .readdata
.m0_readdatavalid (s1_io_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (s1_io_clockcrossing_bridge_m0_burstcount), // .burstcount
.m0_writedata (s1_io_clockcrossing_bridge_m0_writedata), // .writedata
.m0_address (s1_io_clockcrossing_bridge_m0_address), // .address
.m0_write (s1_io_clockcrossing_bridge_m0_write), // .write
.m0_read (s1_io_clockcrossing_bridge_m0_read), // .read
.m0_byteenable (s1_io_clockcrossing_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (s1_io_clockcrossing_bridge_m0_debugaccess) // .debugaccess
);
oc_i2c_master i2c_cpu_s0 (
.wb_clk_i (system_pll_outclk1_clk), // mm_clk.clk
.wb_rst_i (rst_controller_001_reset_out_reset), // mm_clk_reset.reset
.wb_dat_i (mm_interconnect_5_i2c_cpu_s0_mm_slave_writedata), // mm_slave.writedata
.wb_dat_o (mm_interconnect_5_i2c_cpu_s0_mm_slave_readdata), // .readdata
.wb_we_i (mm_interconnect_5_i2c_cpu_s0_mm_slave_write), // .write
.wb_cyc_i (mm_interconnect_5_i2c_cpu_s0_mm_slave_chipselect), // .chipselect
.wb_ack_o (mm_interconnect_5_i2c_cpu_s0_mm_slave_waitrequest), // .waitrequest_n
.wb_adr_i (mm_interconnect_5_i2c_cpu_s0_mm_slave_address), // .address
.scl (i2c_cpu_s0_i2c_exports_scl), // i2c_exports.export
.sda (i2c_cpu_s0_i2c_exports_sda), // .export
.wb_inta_o (irq_synchronizer_002_receiver_irq) // interrupt_sender.irq
);
oc_i2c_master i2c_cpu_s1 (
.wb_clk_i (system_pll_outclk1_clk), // mm_clk.clk
.wb_rst_i (rst_controller_001_reset_out_reset), // mm_clk_reset.reset
.wb_dat_i (mm_interconnect_7_i2c_cpu_s1_mm_slave_writedata), // mm_slave.writedata
.wb_dat_o (mm_interconnect_7_i2c_cpu_s1_mm_slave_readdata), // .readdata
.wb_we_i (mm_interconnect_7_i2c_cpu_s1_mm_slave_write), // .write
.wb_cyc_i (mm_interconnect_7_i2c_cpu_s1_mm_slave_chipselect), // .chipselect
.wb_ack_o (mm_interconnect_7_i2c_cpu_s1_mm_slave_waitrequest), // .waitrequest_n
.wb_adr_i (mm_interconnect_7_i2c_cpu_s1_mm_slave_address), // .address
.scl (i2c_cpu_s1_i2c_exports_scl), // i2c_exports.export
.sda (i2c_cpu_s1_i2c_exports_sda), // .export
.wb_inta_o (irq_synchronizer_005_receiver_irq) // interrupt_sender.irq
);
pwm pwm_cpu_s0_1 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_1_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_1_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_1_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
soc_system_pwm_pll pwm_pll (
.refclk (clk_clk), // refclk.clk
.rst (rst_controller_003_reset_out_reset), // reset.reset
.outclk_0 (pwm_pll_outclk0_clk), // outclk0.clk
.locked () // locked.export
);
pwm pwm_cpu_s0_2 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_2_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_2_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_2_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_3 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_3_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_3_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_3_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_4 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_4_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_4_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_4_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_5 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_5_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_5_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_5_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_6 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_6_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_6_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_6_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_7 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_7_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_7_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_7_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
pwm pwm_cpu_s0_8 (
.clk (pwm_pll_outclk0_clk), // clock.clk
.reset (rst_controller_004_reset_out_reset), // clock_reset.reset
.avs_s0_write (mm_interconnect_5_pwm_cpu_s0_8_s0_write), // s0.write
.avs_s0_writedata (mm_interconnect_5_pwm_cpu_s0_8_s0_writedata), // .writedata
.out_signal (pwm_cpu_s0_8_conduit_end_readdatavalid_n) // conduit_end.readdatavalid_n
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_005_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.intr_capturer_0_reset_sink_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // intr_capturer_0_reset_sink_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.sysid_qsys_control_slave_address (mm_interconnect_1_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_2 mm_interconnect_2 (
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.cpu_s0_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_s0_reset_n_reset_bridge_in_reset.reset
.cpu_s0_data_master_address (cpu_s0_data_master_address), // cpu_s0_data_master.address
.cpu_s0_data_master_waitrequest (cpu_s0_data_master_waitrequest), // .waitrequest
.cpu_s0_data_master_byteenable (cpu_s0_data_master_byteenable), // .byteenable
.cpu_s0_data_master_read (cpu_s0_data_master_read), // .read
.cpu_s0_data_master_readdata (cpu_s0_data_master_readdata), // .readdata
.cpu_s0_data_master_write (cpu_s0_data_master_write), // .write
.cpu_s0_data_master_writedata (cpu_s0_data_master_writedata), // .writedata
.cpu_s0_data_master_debugaccess (cpu_s0_data_master_debugaccess), // .debugaccess
.cpu_s0_instruction_master_address (cpu_s0_instruction_master_address), // cpu_s0_instruction_master.address
.cpu_s0_instruction_master_waitrequest (cpu_s0_instruction_master_waitrequest), // .waitrequest
.cpu_s0_instruction_master_burstcount (cpu_s0_instruction_master_burstcount), // .burstcount
.cpu_s0_instruction_master_read (cpu_s0_instruction_master_read), // .read
.cpu_s0_instruction_master_readdata (cpu_s0_instruction_master_readdata), // .readdata
.cpu_s0_instruction_master_readdatavalid (cpu_s0_instruction_master_readdatavalid), // .readdatavalid
.cpu_s0_jtag_debug_module_address (mm_interconnect_2_cpu_s0_jtag_debug_module_address), // cpu_s0_jtag_debug_module.address
.cpu_s0_jtag_debug_module_write (mm_interconnect_2_cpu_s0_jtag_debug_module_write), // .write
.cpu_s0_jtag_debug_module_read (mm_interconnect_2_cpu_s0_jtag_debug_module_read), // .read
.cpu_s0_jtag_debug_module_readdata (mm_interconnect_2_cpu_s0_jtag_debug_module_readdata), // .readdata
.cpu_s0_jtag_debug_module_writedata (mm_interconnect_2_cpu_s0_jtag_debug_module_writedata), // .writedata
.cpu_s0_jtag_debug_module_byteenable (mm_interconnect_2_cpu_s0_jtag_debug_module_byteenable), // .byteenable
.cpu_s0_jtag_debug_module_waitrequest (mm_interconnect_2_cpu_s0_jtag_debug_module_waitrequest), // .waitrequest
.cpu_s0_jtag_debug_module_debugaccess (mm_interconnect_2_cpu_s0_jtag_debug_module_debugaccess), // .debugaccess
.fifo_bridge_cpuM_cpus0_s0_address (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_address), // fifo_bridge_cpuM_cpus0_s0.address
.fifo_bridge_cpuM_cpus0_s0_write (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_write), // .write
.fifo_bridge_cpuM_cpus0_s0_read (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_read), // .read
.fifo_bridge_cpuM_cpus0_s0_readdata (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_readdata), // .readdata
.fifo_bridge_cpuM_cpus0_s0_writedata (mm_interconnect_2_fifo_bridge_cpum_cpus0_s0_writedata), // .writedata
.fifo_bridge_cpus0_cpus1_s0_address (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_address), // fifo_bridge_cpus0_cpus1_s0.address
.fifo_bridge_cpus0_cpus1_s0_write (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_write), // .write
.fifo_bridge_cpus0_cpus1_s0_read (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_read), // .read
.fifo_bridge_cpus0_cpus1_s0_readdata (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_readdata), // .readdata
.fifo_bridge_cpus0_cpus1_s0_writedata (mm_interconnect_2_fifo_bridge_cpus0_cpus1_s0_writedata), // .writedata
.s0_io_clockCrossing_bridge_s0_address (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_address), // s0_io_clockCrossing_bridge_s0.address
.s0_io_clockCrossing_bridge_s0_write (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_write), // .write
.s0_io_clockCrossing_bridge_s0_read (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_read), // .read
.s0_io_clockCrossing_bridge_s0_readdata (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdata), // .readdata
.s0_io_clockCrossing_bridge_s0_writedata (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_writedata), // .writedata
.s0_io_clockCrossing_bridge_s0_burstcount (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_burstcount), // .burstcount
.s0_io_clockCrossing_bridge_s0_byteenable (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_byteenable), // .byteenable
.s0_io_clockCrossing_bridge_s0_readdatavalid (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.s0_io_clockCrossing_bridge_s0_waitrequest (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_waitrequest), // .waitrequest
.s0_io_clockCrossing_bridge_s0_debugaccess (mm_interconnect_2_s0_io_clockcrossing_bridge_s0_debugaccess), // .debugaccess
.sdram_clockCrossing_Bridge_s0_address (mm_interconnect_2_sdram_clockcrossing_bridge_s0_address), // sdram_clockCrossing_Bridge_s0.address
.sdram_clockCrossing_Bridge_s0_write (mm_interconnect_2_sdram_clockcrossing_bridge_s0_write), // .write
.sdram_clockCrossing_Bridge_s0_read (mm_interconnect_2_sdram_clockcrossing_bridge_s0_read), // .read
.sdram_clockCrossing_Bridge_s0_readdata (mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdata), // .readdata
.sdram_clockCrossing_Bridge_s0_writedata (mm_interconnect_2_sdram_clockcrossing_bridge_s0_writedata), // .writedata
.sdram_clockCrossing_Bridge_s0_burstcount (mm_interconnect_2_sdram_clockcrossing_bridge_s0_burstcount), // .burstcount
.sdram_clockCrossing_Bridge_s0_byteenable (mm_interconnect_2_sdram_clockcrossing_bridge_s0_byteenable), // .byteenable
.sdram_clockCrossing_Bridge_s0_readdatavalid (mm_interconnect_2_sdram_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.sdram_clockCrossing_Bridge_s0_waitrequest (mm_interconnect_2_sdram_clockcrossing_bridge_s0_waitrequest), // .waitrequest
.sdram_clockCrossing_Bridge_s0_debugaccess (mm_interconnect_2_sdram_clockcrossing_bridge_s0_debugaccess) // .debugaccess
);
soc_system_mm_interconnect_3 mm_interconnect_3 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset.reset
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_005_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.fifo_bridge_cpuM_cpus0_s1_address (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_address), // fifo_bridge_cpuM_cpus0_s1.address
.fifo_bridge_cpuM_cpus0_s1_write (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_write), // .write
.fifo_bridge_cpuM_cpus0_s1_read (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_read), // .read
.fifo_bridge_cpuM_cpus0_s1_readdata (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_readdata), // .readdata
.fifo_bridge_cpuM_cpus0_s1_writedata (mm_interconnect_3_fifo_bridge_cpum_cpus0_s1_writedata), // .writedata
.fifo_bridge_cpuM_cpus1_s1_address (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_address), // fifo_bridge_cpuM_cpus1_s1.address
.fifo_bridge_cpuM_cpus1_s1_write (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_write), // .write
.fifo_bridge_cpuM_cpus1_s1_read (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_read), // .read
.fifo_bridge_cpuM_cpus1_s1_readdata (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_readdata), // .readdata
.fifo_bridge_cpuM_cpus1_s1_writedata (mm_interconnect_3_fifo_bridge_cpum_cpus1_s1_writedata) // .writedata
);
soc_system_mm_interconnect_4 mm_interconnect_4 (
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.cpu_s1_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_s1_reset_n_reset_bridge_in_reset.reset
.cpu_s1_data_master_address (cpu_s1_data_master_address), // cpu_s1_data_master.address
.cpu_s1_data_master_waitrequest (cpu_s1_data_master_waitrequest), // .waitrequest
.cpu_s1_data_master_byteenable (cpu_s1_data_master_byteenable), // .byteenable
.cpu_s1_data_master_read (cpu_s1_data_master_read), // .read
.cpu_s1_data_master_readdata (cpu_s1_data_master_readdata), // .readdata
.cpu_s1_data_master_write (cpu_s1_data_master_write), // .write
.cpu_s1_data_master_writedata (cpu_s1_data_master_writedata), // .writedata
.cpu_s1_data_master_debugaccess (cpu_s1_data_master_debugaccess), // .debugaccess
.cpu_s1_instruction_master_address (cpu_s1_instruction_master_address), // cpu_s1_instruction_master.address
.cpu_s1_instruction_master_waitrequest (cpu_s1_instruction_master_waitrequest), // .waitrequest
.cpu_s1_instruction_master_read (cpu_s1_instruction_master_read), // .read
.cpu_s1_instruction_master_readdata (cpu_s1_instruction_master_readdata), // .readdata
.cpu_s1_instruction_master_readdatavalid (cpu_s1_instruction_master_readdatavalid), // .readdatavalid
.cpu_s1_jtag_debug_module_address (mm_interconnect_4_cpu_s1_jtag_debug_module_address), // cpu_s1_jtag_debug_module.address
.cpu_s1_jtag_debug_module_write (mm_interconnect_4_cpu_s1_jtag_debug_module_write), // .write
.cpu_s1_jtag_debug_module_read (mm_interconnect_4_cpu_s1_jtag_debug_module_read), // .read
.cpu_s1_jtag_debug_module_readdata (mm_interconnect_4_cpu_s1_jtag_debug_module_readdata), // .readdata
.cpu_s1_jtag_debug_module_writedata (mm_interconnect_4_cpu_s1_jtag_debug_module_writedata), // .writedata
.cpu_s1_jtag_debug_module_byteenable (mm_interconnect_4_cpu_s1_jtag_debug_module_byteenable), // .byteenable
.cpu_s1_jtag_debug_module_waitrequest (mm_interconnect_4_cpu_s1_jtag_debug_module_waitrequest), // .waitrequest
.cpu_s1_jtag_debug_module_debugaccess (mm_interconnect_4_cpu_s1_jtag_debug_module_debugaccess), // .debugaccess
.fifo_bridge_cpuM_cpus1_s0_address (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_address), // fifo_bridge_cpuM_cpus1_s0.address
.fifo_bridge_cpuM_cpus1_s0_write (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_write), // .write
.fifo_bridge_cpuM_cpus1_s0_read (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_read), // .read
.fifo_bridge_cpuM_cpus1_s0_readdata (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_readdata), // .readdata
.fifo_bridge_cpuM_cpus1_s0_writedata (mm_interconnect_4_fifo_bridge_cpum_cpus1_s0_writedata), // .writedata
.fifo_bridge_cpus0_cpus1_s1_address (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_address), // fifo_bridge_cpus0_cpus1_s1.address
.fifo_bridge_cpus0_cpus1_s1_write (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_write), // .write
.fifo_bridge_cpus0_cpus1_s1_read (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_read), // .read
.fifo_bridge_cpus0_cpus1_s1_readdata (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_readdata), // .readdata
.fifo_bridge_cpus0_cpus1_s1_writedata (mm_interconnect_4_fifo_bridge_cpus0_cpus1_s1_writedata), // .writedata
.onchip_sram_s1_address (mm_interconnect_4_onchip_sram_s1_address), // onchip_sram_s1.address
.onchip_sram_s1_write (mm_interconnect_4_onchip_sram_s1_write), // .write
.onchip_sram_s1_readdata (mm_interconnect_4_onchip_sram_s1_readdata), // .readdata
.onchip_sram_s1_writedata (mm_interconnect_4_onchip_sram_s1_writedata), // .writedata
.onchip_sram_s1_byteenable (mm_interconnect_4_onchip_sram_s1_byteenable), // .byteenable
.onchip_sram_s1_chipselect (mm_interconnect_4_onchip_sram_s1_chipselect), // .chipselect
.onchip_sram_s1_clken (mm_interconnect_4_onchip_sram_s1_clken), // .clken
.s1_io_clockCrossing_bridge_s0_address (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_address), // s1_io_clockCrossing_bridge_s0.address
.s1_io_clockCrossing_bridge_s0_write (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_write), // .write
.s1_io_clockCrossing_bridge_s0_read (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_read), // .read
.s1_io_clockCrossing_bridge_s0_readdata (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdata), // .readdata
.s1_io_clockCrossing_bridge_s0_writedata (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_writedata), // .writedata
.s1_io_clockCrossing_bridge_s0_burstcount (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_burstcount), // .burstcount
.s1_io_clockCrossing_bridge_s0_byteenable (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_byteenable), // .byteenable
.s1_io_clockCrossing_bridge_s0_readdatavalid (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_readdatavalid), // .readdatavalid
.s1_io_clockCrossing_bridge_s0_waitrequest (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_waitrequest), // .waitrequest
.s1_io_clockCrossing_bridge_s0_debugaccess (mm_interconnect_4_s1_io_clockcrossing_bridge_s0_debugaccess) // .debugaccess
);
soc_system_mm_interconnect_5 mm_interconnect_5 (
.pwm_pll_outclk0_clk (pwm_pll_outclk0_clk), // pwm_pll_outclk0.clk
.system_pll_outclk1_clk (system_pll_outclk1_clk), // system_pll_outclk1.clk
.pwm_cpu_s0_1_clock_reset_reset_bridge_in_reset_reset (rst_controller_004_reset_out_reset), // pwm_cpu_s0_1_clock_reset_reset_bridge_in_reset.reset
.s0_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // s0_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset.reset
.s0_io_clockCrossing_bridge_m0_address (s0_io_clockcrossing_bridge_m0_address), // s0_io_clockCrossing_bridge_m0.address
.s0_io_clockCrossing_bridge_m0_waitrequest (s0_io_clockcrossing_bridge_m0_waitrequest), // .waitrequest
.s0_io_clockCrossing_bridge_m0_burstcount (s0_io_clockcrossing_bridge_m0_burstcount), // .burstcount
.s0_io_clockCrossing_bridge_m0_byteenable (s0_io_clockcrossing_bridge_m0_byteenable), // .byteenable
.s0_io_clockCrossing_bridge_m0_read (s0_io_clockcrossing_bridge_m0_read), // .read
.s0_io_clockCrossing_bridge_m0_readdata (s0_io_clockcrossing_bridge_m0_readdata), // .readdata
.s0_io_clockCrossing_bridge_m0_readdatavalid (s0_io_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.s0_io_clockCrossing_bridge_m0_write (s0_io_clockcrossing_bridge_m0_write), // .write
.s0_io_clockCrossing_bridge_m0_writedata (s0_io_clockcrossing_bridge_m0_writedata), // .writedata
.s0_io_clockCrossing_bridge_m0_debugaccess (s0_io_clockcrossing_bridge_m0_debugaccess), // .debugaccess
.i2c_cpu_s0_mm_slave_address (mm_interconnect_5_i2c_cpu_s0_mm_slave_address), // i2c_cpu_s0_mm_slave.address
.i2c_cpu_s0_mm_slave_write (mm_interconnect_5_i2c_cpu_s0_mm_slave_write), // .write
.i2c_cpu_s0_mm_slave_readdata (mm_interconnect_5_i2c_cpu_s0_mm_slave_readdata), // .readdata
.i2c_cpu_s0_mm_slave_writedata (mm_interconnect_5_i2c_cpu_s0_mm_slave_writedata), // .writedata
.i2c_cpu_s0_mm_slave_waitrequest (~mm_interconnect_5_i2c_cpu_s0_mm_slave_waitrequest), // .waitrequest
.i2c_cpu_s0_mm_slave_chipselect (mm_interconnect_5_i2c_cpu_s0_mm_slave_chipselect), // .chipselect
.jtag_uart_cpu_s0_avalon_jtag_slave_address (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_address), // jtag_uart_cpu_s0_avalon_jtag_slave.address
.jtag_uart_cpu_s0_avalon_jtag_slave_write (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_write), // .write
.jtag_uart_cpu_s0_avalon_jtag_slave_read (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_read), // .read
.jtag_uart_cpu_s0_avalon_jtag_slave_readdata (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_cpu_s0_avalon_jtag_slave_writedata (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_cpu_s0_avalon_jtag_slave_waitrequest (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_cpu_s0_avalon_jtag_slave_chipselect (mm_interconnect_5_jtag_uart_cpu_s0_avalon_jtag_slave_chipselect), // .chipselect
.pio_aliveTest_cpu_s0_s1_address (mm_interconnect_5_pio_alivetest_cpu_s0_s1_address), // pio_aliveTest_cpu_s0_s1.address
.pio_aliveTest_cpu_s0_s1_write (mm_interconnect_5_pio_alivetest_cpu_s0_s1_write), // .write
.pio_aliveTest_cpu_s0_s1_readdata (mm_interconnect_5_pio_alivetest_cpu_s0_s1_readdata), // .readdata
.pio_aliveTest_cpu_s0_s1_writedata (mm_interconnect_5_pio_alivetest_cpu_s0_s1_writedata), // .writedata
.pio_aliveTest_cpu_s0_s1_chipselect (mm_interconnect_5_pio_alivetest_cpu_s0_s1_chipselect), // .chipselect
.pwm_cpu_s0_1_s0_write (mm_interconnect_5_pwm_cpu_s0_1_s0_write), // pwm_cpu_s0_1_s0.write
.pwm_cpu_s0_1_s0_writedata (mm_interconnect_5_pwm_cpu_s0_1_s0_writedata), // .writedata
.pwm_cpu_s0_2_s0_write (mm_interconnect_5_pwm_cpu_s0_2_s0_write), // pwm_cpu_s0_2_s0.write
.pwm_cpu_s0_2_s0_writedata (mm_interconnect_5_pwm_cpu_s0_2_s0_writedata), // .writedata
.pwm_cpu_s0_3_s0_write (mm_interconnect_5_pwm_cpu_s0_3_s0_write), // pwm_cpu_s0_3_s0.write
.pwm_cpu_s0_3_s0_writedata (mm_interconnect_5_pwm_cpu_s0_3_s0_writedata), // .writedata
.pwm_cpu_s0_4_s0_write (mm_interconnect_5_pwm_cpu_s0_4_s0_write), // pwm_cpu_s0_4_s0.write
.pwm_cpu_s0_4_s0_writedata (mm_interconnect_5_pwm_cpu_s0_4_s0_writedata), // .writedata
.pwm_cpu_s0_5_s0_write (mm_interconnect_5_pwm_cpu_s0_5_s0_write), // pwm_cpu_s0_5_s0.write
.pwm_cpu_s0_5_s0_writedata (mm_interconnect_5_pwm_cpu_s0_5_s0_writedata), // .writedata
.pwm_cpu_s0_6_s0_write (mm_interconnect_5_pwm_cpu_s0_6_s0_write), // pwm_cpu_s0_6_s0.write
.pwm_cpu_s0_6_s0_writedata (mm_interconnect_5_pwm_cpu_s0_6_s0_writedata), // .writedata
.pwm_cpu_s0_7_s0_write (mm_interconnect_5_pwm_cpu_s0_7_s0_write), // pwm_cpu_s0_7_s0.write
.pwm_cpu_s0_7_s0_writedata (mm_interconnect_5_pwm_cpu_s0_7_s0_writedata), // .writedata
.pwm_cpu_s0_8_s0_write (mm_interconnect_5_pwm_cpu_s0_8_s0_write), // pwm_cpu_s0_8_s0.write
.pwm_cpu_s0_8_s0_writedata (mm_interconnect_5_pwm_cpu_s0_8_s0_writedata), // .writedata
.timer_cpu_s0_s1_address (mm_interconnect_5_timer_cpu_s0_s1_address), // timer_cpu_s0_s1.address
.timer_cpu_s0_s1_write (mm_interconnect_5_timer_cpu_s0_s1_write), // .write
.timer_cpu_s0_s1_readdata (mm_interconnect_5_timer_cpu_s0_s1_readdata), // .readdata
.timer_cpu_s0_s1_writedata (mm_interconnect_5_timer_cpu_s0_s1_writedata), // .writedata
.timer_cpu_s0_s1_chipselect (mm_interconnect_5_timer_cpu_s0_s1_chipselect) // .chipselect
);
soc_system_mm_interconnect_6 mm_interconnect_6 (
.sdram_pll_outclk0_clk (sdram_pll_outclk0_clk), // sdram_pll_outclk0.clk
.sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset.reset
.sdram_clockCrossing_Bridge_m0_address (sdram_clockcrossing_bridge_m0_address), // sdram_clockCrossing_Bridge_m0.address
.sdram_clockCrossing_Bridge_m0_waitrequest (sdram_clockcrossing_bridge_m0_waitrequest), // .waitrequest
.sdram_clockCrossing_Bridge_m0_burstcount (sdram_clockcrossing_bridge_m0_burstcount), // .burstcount
.sdram_clockCrossing_Bridge_m0_byteenable (sdram_clockcrossing_bridge_m0_byteenable), // .byteenable
.sdram_clockCrossing_Bridge_m0_read (sdram_clockcrossing_bridge_m0_read), // .read
.sdram_clockCrossing_Bridge_m0_readdata (sdram_clockcrossing_bridge_m0_readdata), // .readdata
.sdram_clockCrossing_Bridge_m0_readdatavalid (sdram_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.sdram_clockCrossing_Bridge_m0_write (sdram_clockcrossing_bridge_m0_write), // .write
.sdram_clockCrossing_Bridge_m0_writedata (sdram_clockcrossing_bridge_m0_writedata), // .writedata
.sdram_clockCrossing_Bridge_m0_debugaccess (sdram_clockcrossing_bridge_m0_debugaccess), // .debugaccess
.sdram_s1_address (mm_interconnect_6_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_6_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_6_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_6_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_6_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_6_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_6_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_6_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_6_sdram_s1_chipselect) // .chipselect
);
soc_system_mm_interconnect_7 mm_interconnect_7 (
.system_pll_outclk1_clk (system_pll_outclk1_clk), // system_pll_outclk1.clk
.s1_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // s1_io_clockCrossing_bridge_m0_reset_reset_bridge_in_reset.reset
.s1_io_clockCrossing_bridge_m0_address (s1_io_clockcrossing_bridge_m0_address), // s1_io_clockCrossing_bridge_m0.address
.s1_io_clockCrossing_bridge_m0_waitrequest (s1_io_clockcrossing_bridge_m0_waitrequest), // .waitrequest
.s1_io_clockCrossing_bridge_m0_burstcount (s1_io_clockcrossing_bridge_m0_burstcount), // .burstcount
.s1_io_clockCrossing_bridge_m0_byteenable (s1_io_clockcrossing_bridge_m0_byteenable), // .byteenable
.s1_io_clockCrossing_bridge_m0_read (s1_io_clockcrossing_bridge_m0_read), // .read
.s1_io_clockCrossing_bridge_m0_readdata (s1_io_clockcrossing_bridge_m0_readdata), // .readdata
.s1_io_clockCrossing_bridge_m0_readdatavalid (s1_io_clockcrossing_bridge_m0_readdatavalid), // .readdatavalid
.s1_io_clockCrossing_bridge_m0_write (s1_io_clockcrossing_bridge_m0_write), // .write
.s1_io_clockCrossing_bridge_m0_writedata (s1_io_clockcrossing_bridge_m0_writedata), // .writedata
.s1_io_clockCrossing_bridge_m0_debugaccess (s1_io_clockcrossing_bridge_m0_debugaccess), // .debugaccess
.i2c_cpu_s1_mm_slave_address (mm_interconnect_7_i2c_cpu_s1_mm_slave_address), // i2c_cpu_s1_mm_slave.address
.i2c_cpu_s1_mm_slave_write (mm_interconnect_7_i2c_cpu_s1_mm_slave_write), // .write
.i2c_cpu_s1_mm_slave_readdata (mm_interconnect_7_i2c_cpu_s1_mm_slave_readdata), // .readdata
.i2c_cpu_s1_mm_slave_writedata (mm_interconnect_7_i2c_cpu_s1_mm_slave_writedata), // .writedata
.i2c_cpu_s1_mm_slave_waitrequest (~mm_interconnect_7_i2c_cpu_s1_mm_slave_waitrequest), // .waitrequest
.i2c_cpu_s1_mm_slave_chipselect (mm_interconnect_7_i2c_cpu_s1_mm_slave_chipselect), // .chipselect
.jtag_uart_cpu_s1_avalon_jtag_slave_address (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_address), // jtag_uart_cpu_s1_avalon_jtag_slave.address
.jtag_uart_cpu_s1_avalon_jtag_slave_write (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_write), // .write
.jtag_uart_cpu_s1_avalon_jtag_slave_read (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_read), // .read
.jtag_uart_cpu_s1_avalon_jtag_slave_readdata (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_cpu_s1_avalon_jtag_slave_writedata (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_cpu_s1_avalon_jtag_slave_waitrequest (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_cpu_s1_avalon_jtag_slave_chipselect (mm_interconnect_7_jtag_uart_cpu_s1_avalon_jtag_slave_chipselect), // .chipselect
.pio_aliveTest_cpu_s1_s1_address (mm_interconnect_7_pio_alivetest_cpu_s1_s1_address), // pio_aliveTest_cpu_s1_s1.address
.pio_aliveTest_cpu_s1_s1_write (mm_interconnect_7_pio_alivetest_cpu_s1_s1_write), // .write
.pio_aliveTest_cpu_s1_s1_readdata (mm_interconnect_7_pio_alivetest_cpu_s1_s1_readdata), // .readdata
.pio_aliveTest_cpu_s1_s1_writedata (mm_interconnect_7_pio_alivetest_cpu_s1_s1_writedata), // .writedata
.pio_aliveTest_cpu_s1_s1_chipselect (mm_interconnect_7_pio_alivetest_cpu_s1_s1_chipselect), // .chipselect
.timer_cpu_s1_s1_address (mm_interconnect_7_timer_cpu_s1_s1_address), // timer_cpu_s1_s1.address
.timer_cpu_s1_s1_write (mm_interconnect_7_timer_cpu_s1_s1_write), // .write
.timer_cpu_s1_s1_readdata (mm_interconnect_7_timer_cpu_s1_s1_readdata), // .readdata
.timer_cpu_s1_s1_writedata (mm_interconnect_7_timer_cpu_s1_s1_writedata), // .writedata
.timer_cpu_s1_s1_chipselect (mm_interconnect_7_timer_cpu_s1_s1_chipselect) // .chipselect
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper_002 irq_mapper_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver1_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver0_irq), // receiver1.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
soc_system_irq_mapper_003 irq_mapper_003 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_003_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_003_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_003_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_003_receiver3_irq), // receiver3.irq
.receiver4_irq (irq_mapper_003_receiver4_irq), // receiver4.irq
.sender_irq (cpu_s0_d_irq_irq) // sender.irq
);
soc_system_irq_mapper_003 irq_mapper_004 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_004_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_004_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_004_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_004_receiver3_irq), // receiver3.irq
.receiver4_irq (irq_mapper_004_receiver4_irq), // receiver4.irq
.sender_irq (cpu_s1_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_003_receiver0_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_001 (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_001_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_003_receiver1_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_002 (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_002_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_003_receiver4_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_003 (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_003_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_004_receiver0_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_004 (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_004_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_004_receiver1_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_005 (
.receiver_clk (system_pll_outclk1_clk), // receiver_clk.clk
.sender_clk (system_pll_outclk0_clk), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_005_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_004_receiver4_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (system_pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (system_pll_outclk1_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_004 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pwm_pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_004_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_005 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_005_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Data Path Mask Generator
// File : ded_mskgen.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_mskgen
#(parameter BYTES = 4)
(
input de_clk, // drawing engine clock
de_rstn, // drawing engine reset
mclock, // memory controller clock
mc_acken, // memory controller pop enable
mc_popen, // memory controller pop enable
input ld_msk, // load mask registers
input line_actv_4, // line command active bit
blt_actv_4, // blt command active bit
input [1:0] clp_4, // clipping control register
input mem_req, // memory request signal
input mem_rd, // memory read signal
input [BYTES-1:0] pc_msk_in, // pixel cache mask
input [31:0] clpx_bus_2, // clipping {xmax[15:4],xmin[15:4]}
input [15:0] x_bus, // bus from execution X dest counter
input [6:0] xalu_bus, // bus from execution unit X alu
input trnsp_4, // Transparent bit
input [BYTES-1:0] trns_msk_in, // Transparentcy mask
input ps16_2, // pixel size equals 16
input ps32_2, // pixel size equals 32
input mc_eop, // mc end of page delayed
input [3:0] mask_4, // plane mask
input [6:0] lft_enc_4,
input [6:0] rht_enc_4,
input [11:0] clp_min_4, // left clipping pointer
input [11:0] clp_max_4, // right clipping pointer
input [3:0] cmin_enc_4,
input [3:0] cmax_enc_4,
input y_clip_4,
input sol_4,
input eol_4,
input [13:0] x_count_4, // current X position
input mc_eop4,
output reg [BYTES-1:0] pixel_msk, // pixel mask for the memory controller
output reg clip_ind, // Clip indicator
output reg [6:0] lft_enc_2,
output reg [6:0] rht_enc_2,
output [11:0] clp_min_2, // left clipping pointer
output [11:0] clp_max_2, // right clipping pointer
output reg [3:0] cmin_enc_2,
output reg [3:0] cmax_enc_2
);
wire iclip_ind; // Clip indicator
wire [BYTES-1:0] trns_msk; // Transparentcy mask
reg last_mask; // end of line pulse level 4
/* register the mask bits from the execution unit. */
reg mc_eop_del;
reg [15:0] pixel_msk_2d_del;// pixel mask for the memory controller
reg [15:0] pixel_msk_2d_del2;// pixel mask for the memory controller
reg blt_actv_4_d, sol_4_d;
reg [BYTES-1:0] pc_msk_del;
reg [15:0] clp_msk;
wire [15:0] cmin_msk;
wire [15:0] cmax_msk;
reg [15:0] lft;
reg [15:0] rht;
wire [15:0] rht_msk;
wire [15:0] lft_msk;
wire [15:0] mid_msk;
reg cmin_en; // clipping min mask enable
reg cmax_en; // clipping max mask enable
reg xl_cmin;
reg cmaxl_x;
wire drw_outside_4; // draw outside of clipping box
wire drw_inside_4; // draw inside of clipping box
wire x_clip;
reg [15:0] pixel_msk_0; // pixel mask for the memory controller
reg [1:0] sub_page;
reg [1:0] sub_page_1;
reg [1:0] sub_page_2;
reg [1:0] sub_page_3;
reg [1:0] sub_page_4;
// Latch the mask values
always @(posedge de_clk or negedge de_rstn) begin
if (!de_rstn) begin
lft_enc_2<=0;
rht_enc_2 <=0;
end else if (ld_msk) begin
lft_enc_2 <=x_bus[6:0];
rht_enc_2<=xalu_bus-7'b1;
end
end
assign clp_min_2 = clpx_bus_2[15:4];
assign clp_max_2 = clpx_bus_2[31:20];
// Latch the encode mask values
// clpx_bus_2 = {xmax,xmin}
always @* begin
cmin_enc_2 = clpx_bus_2[3:0];
casex ({ps16_2, ps32_2})
2'b1x: cmax_enc_2 = clpx_bus_2[19:16]+4'b0001; // 16 bpp
2'b01: cmax_enc_2 = clpx_bus_2[19:16]+4'b0011; // 32 bpp
2'b00: cmax_enc_2 = clpx_bus_2[19:16]; // 8 bpp
endcase
end
always @* begin
// create the mask enable control bits
`ifdef BYTE16
cmin_en = (x_count_4 == clp_min_4);
cmax_en = (x_count_4 == clp_max_4);
`endif
`ifdef BYTE8
cmin_en = (x_count_4[12:1] == clp_min_4);
cmax_en = (x_count_4[12:1] == clp_max_4);
`endif
`ifdef BYTE4
cmin_en = (x_count_4[13:2] == clp_min_4);
cmax_en = (x_count_4[13:2] == clp_max_4);
`endif
end
`ifdef BYTE4
always @* begin
if (x_count_4[13] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[13] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[13:2] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[13] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[13] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[13:2] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
`ifdef BYTE8
always @* begin
if (x_count_4[12] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[12] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[12:1] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[12] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[12] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[12:1] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
`ifdef BYTE16
always @* begin
if (x_count_4[11] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[11] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[11:0] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[11] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[11] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[11:0] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
assign drw_outside_4 = (clp_4[1] & clp_4[0]);
assign drw_inside_4 = (clp_4[1] & ~clp_4[0]);
assign x_clip = (drw_outside_4 & !(xl_cmin | cmaxl_x)) ||
(drw_inside_4 & (xl_cmin | cmaxl_x));
always @(posedge mclock) mc_eop_del <= mc_eop;
always @(posedge mclock or negedge de_rstn) begin
if (!de_rstn) clip_ind <= 0;
else if (mc_eop_del) clip_ind <= 0;
else if (iclip_ind & mc_popen) clip_ind <= 1;
end
// combine all of the masks
assign cmin_msk = left_clip(drw_outside_4,cmin_enc_4);
assign cmax_msk = rght_clip(drw_outside_4,cmax_enc_4);
assign iclip_ind =
(blt_actv_4 & drw_outside_4 & x_clip & y_clip_4 &
!(cmin_en | cmax_en)) |
(blt_actv_4 & drw_inside_4 & y_clip_4) |
(blt_actv_4 & drw_inside_4 & x_clip & !(cmin_en | cmax_en)) |
(blt_actv_4 & drw_inside_4 & cmin_en & cmax_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmin_en & cmax_en & y_clip_4) |
(blt_actv_4 & drw_inside_4 & cmin_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmin_en & y_clip_4) |
(blt_actv_4 & drw_inside_4 & cmax_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmax_en & y_clip_4);
assign rht_msk = ((blt_actv_4_d) & last_mask & sol_4_d) ? (rht | lft) :
((blt_actv_4_d) & last_mask) ? rht : 16'hFFFF;
assign lft_msk = ((blt_actv_4_d) & sol_4_d & !last_mask) ? lft : 16'hFFFF;
assign mid_msk = (blt_actv_4_d & last_mask) ? 16'hFFFF :
((blt_actv_4_d & sol_4_d) ? 16'hFFFF :
((blt_actv_4_d) ? 16'h0 : 16'hFFFF));
assign trns_msk = (trnsp_4 && !line_actv_4) ? ~trns_msk_in : 16'h0;
always @(posedge mclock) begin
// Delay Controls
blt_actv_4_d <= blt_actv_4;
sol_4_d <= sol_4;
// Delay the rht, lft mask, and the last_mask signal
lft <= {1'b0, {15{1'b1}}} >> (~lft_enc_4[3:0]);
rht <= {{15{1'b1}}, 1'b0} << (rht_enc_4[3:0]);
last_mask <= (eol_4 & mc_eop4);
clp_msk <= (blt_actv_4 & drw_outside_4 & x_clip & y_clip_4 & !(cmin_en | cmax_en)) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & y_clip_4) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & x_clip & !(cmin_en | cmax_en)) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & cmin_en & cmax_en & !y_clip_4) ? (cmin_msk | cmax_msk) :
(blt_actv_4 & drw_outside_4 & cmin_en & cmax_en & y_clip_4) ? (cmin_msk & cmax_msk) :
(blt_actv_4 & drw_inside_4 & cmin_en & !y_clip_4) ? cmin_msk :
(blt_actv_4 & drw_outside_4 & cmin_en & y_clip_4) ? cmin_msk :
(blt_actv_4 & drw_inside_4 & cmax_en & !y_clip_4) ? cmax_msk :
(blt_actv_4 & drw_outside_4 & cmax_en & y_clip_4) ? cmax_msk :
16'h0;
sub_page_4 <= sub_page_3;
sub_page_3 <= sub_page_2;
sub_page_2 <= sub_page_1;
sub_page_1 <= sub_page;
if(mc_acken) sub_page <= 1'b0;
else if(mc_popen) sub_page <= sub_page + 1'b1;
pixel_msk_2d_del <= (lft_msk & rht_msk & mid_msk) | clp_msk;
pixel_msk_2d_del2 <= pixel_msk_2d_del;
pc_msk_del <= pc_msk_in;
// Pipe stage added to increase MC clock speed
// trans mask has to be last because of delays of cx_reg
// pixel_msk_0 <= line_actv_4 ? pc_msk_del : (pixel_msk_0 | trns_msk | ~{(BYTES/2){mask_4}});
`ifdef BYTE16 pixel_msk_0 <= line_actv_4 ? pc_msk_del : pixel_msk_2d_del2; `endif
`ifdef BYTE8 pixel_msk_0 <= line_actv_4 ? {2{pc_msk_del}} : pixel_msk_2d_del2; `endif
`ifdef BYTE4 pixel_msk_0 <= line_actv_4 ? {4{pc_msk_del}} : pixel_msk_2d_del2; `endif
if (BYTES == 16)
pixel_msk <= pixel_msk_0 | ((!line_actv_4) ? trns_msk : 16'h0) | ~{4{mask_4}};
else if (BYTES == 8)
case (sub_page_4[0])
1'b0: pixel_msk <= pixel_msk_0[7:0] | ((!line_actv_4) ? trns_msk : 8'h0) | ~{2{mask_4}};
1'b1: pixel_msk <= pixel_msk_0[15:8] | ((!line_actv_4) ? trns_msk : 8'h0) | ~{2{mask_4}};
endcase
else
case (sub_page_4[1:0])
2'b00: pixel_msk <= pixel_msk_0[3:0] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b01: pixel_msk <= pixel_msk_0[7:4] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b10: pixel_msk <= pixel_msk_0[11:8] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b11: pixel_msk <= pixel_msk_0[15:12] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
endcase
end
// function to generate the left clipping mask
function [15:0] left_clip;
input inv_msk;
input [3:0] msk_in;
reg [15:0] mask;
begin
/* left clip mask */
case(msk_in) /* synopsys full_case parallel_case */
0: mask = 16'b0000000000000000;
1: mask = 16'b0000000000000001;
2: mask = 16'b0000000000000011;
3: mask = 16'b0000000000000111;
4: mask = 16'b0000000000001111;
5: mask = 16'b0000000000011111;
6: mask = 16'b0000000000111111;
7: mask = 16'b0000000001111111;
8: mask = 16'b0000000011111111;
9: mask = 16'b0000000111111111;
10: mask = 16'b0000001111111111;
11: mask = 16'b0000011111111111;
12: mask = 16'b0000111111111111;
13: mask = 16'b0001111111111111;
14: mask = 16'b0011111111111111;
15: mask = 16'b0111111111111111;
endcase
if(inv_msk)left_clip=~mask;
else left_clip=mask;
end
endfunction
// function to generate the right clipping mask and window max.
function [15:0] rght_clip;
input inv_msk;
input [3:0] msk_in;
reg [15:0] mask;
begin
/* right mask */
case(msk_in) /* synopsys full_case parallel_case */
0: mask = 16'b1111111111111110;
1: mask = 16'b1111111111111100;
2: mask = 16'b1111111111111000;
3: mask = 16'b1111111111110000;
4: mask = 16'b1111111111100000;
5: mask = 16'b1111111111000000;
6: mask = 16'b1111111110000000;
7: mask = 16'b1111111100000000;
8: mask = 16'b1111111000000000;
9: mask = 16'b1111110000000000;
10: mask = 16'b1111100000000000;
11: mask = 16'b1111000000000000;
12: mask = 16'b1110000000000000;
13: mask = 16'b1100000000000000;
14: mask = 16'b1000000000000000;
15: mask = 16'b0000000000000000;
endcase
if(inv_msk)rght_clip=~mask;
else rght_clip=mask;
end
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__XOR2_PP_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_PP_BLACKBOX_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fx2_to_bus #(
parameter WIDTH = 16 // 16 bit bus from FX2
) (
input wire [WIDTH-1:0] ADD,
input wire RD_B, // neg active, two clock cycles
input wire WR_B, // neg active
input wire BUS_CLK, // FCLK
output wire [WIDTH-1:0] BUS_ADD,
output wire BUS_RD,
output wire BUS_WR,
output wire CS_FPGA
);
// remove offset from FX2
assign BUS_ADD = ADD - 16'h4000;
// chip select FPGA
assign CS_FPGA = ~ADD[15] & ADD[14];
// generate read strobe which one clock cycle long
// this is very important to prevent corrupted data
reg RD_B_FF;
always @(posedge BUS_CLK) begin
RD_B_FF <= RD_B;
end
assign BUS_RD = ~RD_B & RD_B_FF;
assign BUS_WR = ~WR_B;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_2_V
`define SKY130_FD_SC_LP__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_2_V
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Thu Mar 20 13:11:40 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module dds(aclk, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
(* * Syntax and semantics of the linear language *)
(* ** Imports and settings *)
From Coq
Require Import Setoid Morphisms Lia.
From mathcomp Require Import all_ssreflect all_algebra.
Require Import ZArith Utf8.
Import Relations.
Require sem_one_varmap_facts.
Import ssrZ.
Import ssrring.
Import psem psem_facts sem_one_varmap compiler_util label sem_one_varmap_facts.
Require Import constant_prop constant_prop_proof.
Require Export linearization linear_sem.
Import Memory.
Require Import arch_decl arch_extra.
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Section ASM_EXTRA.
Context {reg xreg rflag cond asm_op extra_op} {asm_e : asm_extra reg xreg rflag cond asm_op extra_op}.
Notation spointer := (sword Uptr) (only parsing).
Lemma wunsigned_sub_small (p: pointer) (n: Z) :
(0 <= n < wbase Uptr →
wunsigned (p - wrepr Uptr n) <= wunsigned p →
wunsigned (p - wrepr Uptr n) = wunsigned p - n)%Z.
Proof.
move=> n_range.
rewrite wunsigned_sub_if wunsigned_repr_small //.
case: ZleP => //.
by lia.
Qed.
Lemma wunsigned_top_stack_after_aligned_alloc m e m' :
(0 <= sf_stk_sz e →
0 <= sf_stk_extra_sz e →
stack_frame_allocation_size e < wbase Uptr →
is_align (top_stack m) (sf_align e) →
alloc_stack m (sf_align e) (sf_stk_sz e) (sf_stk_extra_sz e) = ok m' →
wunsigned (top_stack m) = wunsigned (top_stack m') + stack_frame_allocation_size e)%Z.
Proof.
move => sz_pos extra_pos sf_noovf sp_align ok_m'.
rewrite (alloc_stack_top_stack ok_m') (top_stack_after_aligned_alloc _ sp_align) -/(stack_frame_allocation_size _) wrepr_opp wunsigned_sub.
- lia.
have sf_pos : (0 <= stack_frame_allocation_size e)%Z.
- rewrite /stack_frame_allocation_size.
have := round_ws_range (sf_align e) (sf_stk_sz e + sf_stk_extra_sz e).
lia.
assert (top_stack_range := wunsigned_range (top_stack m)).
split; last lia.
rewrite Z.le_0_sub.
exact: (aligned_alloc_no_overflow sz_pos extra_pos sf_noovf sp_align ok_m').
Qed.
Local Open Scope seq_scope.
Lemma all_has {T} (p q: pred T) (s: seq T) :
all p s →
has q s →
exists2 t, List.In t s & p t && q t.
Proof.
elim: s => // t s ih /= /andP[] pt ps /orP[] r.
- exists t; first by left.
by rewrite pt.
by case: (ih ps r) => y Y Z; exists y; first right.
Qed.
Lemma align_bind ii a p1 l :
(let: (lbl, lc) := align ii a p1 in (lbl, lc ++ l)) =
align ii a (let: (lbl, lc) := p1 in (lbl, lc ++ l)).
Proof. by case: p1 a => lbl lc []. Qed.
Section CAT.
Context
(p:sprog)
(lparams: linearization_params)
(extra_free_registers: instr_info -> option var).
Let linear_i := linear_i p extra_free_registers lparams.
Let Pi (i:instr) :=
forall fn lbl tail,
linear_i fn i lbl tail =
let: (lbl, lc) := linear_i fn i lbl [::] in (lbl, lc ++ tail).
Let Pr (i:instr_r) :=
forall ii, Pi (MkI ii i).
Let Pc (c:cmd) :=
forall fn lbl tail,
linear_c (linear_i fn) c lbl tail =
let: (lbl, lc) := linear_c (linear_i fn) c lbl [::] in (lbl, lc ++ tail).
Let Pf (fd:sfundef) := True.
Let HmkI: forall i ii, Pr i -> Pi (MkI ii i).
Proof. by []. Qed.
Let Hskip : Pc [::].
Proof. by []. Qed.
Let Hseq : forall i c, Pi i -> Pc c -> Pc (i::c).
Proof.
move=> i c Hi Hc fn lbl l /=.
by rewrite Hc; case: linear_c => lbl1 lc1; rewrite Hi (Hi _ lbl1 lc1); case: linear_i => ??; rewrite catA.
Qed.
Let Hassgn : forall x tg ty e, Pr (Cassgn x tg ty e).
Proof. by move => x tg [] // sz e ii lbl c /=; case: assert. Qed.
Let Hopn : forall xs t o es, Pr (Copn xs t o es).
Proof. by []. Qed.
Let Hif : forall e c1 c2, Pc c1 -> Pc c2 -> Pr (Cif e c1 c2).
Proof.
move=> e c1 c2 Hc1 Hc2 ii fn lbl l /=.
case Heq1: (c1)=> [|i1 l1].
+ by rewrite Hc2 (Hc2 _ _ [:: _]); case: linear_c => lbl1 lc1; rewrite cats1 /= cat_rcons.
rewrite -Heq1=> {Heq1 i1 l1};case Heq2: (c2)=> [|i2 l2].
+ by rewrite Hc1 (Hc1 _ _ [::_]); case: linear_c => lbl1 lc1; rewrite cats1 /= cat_rcons.
rewrite -Heq2=> {Heq2 i2 l2}.
rewrite Hc1 (Hc1 _ _ [::_]); case: linear_c => lbl1 lc1.
rewrite Hc2 (Hc2 _ _ [::_ & _]); case: linear_c => lbl2 lc2.
by rewrite /= !cats1 /= -!cat_rcons catA.
Qed.
Let Hfor : forall v dir lo hi c, Pc c -> Pr (Cfor v (dir, lo, hi) c).
Proof. by []. Qed.
Let Hwhile : forall a c e c', Pc c -> Pc c' -> Pr (Cwhile a c e c').
Proof.
move=> a c e c' Hc Hc' ii fn lbl l /=.
case: is_bool => [ [] | ].
+ rewrite Hc' (Hc' _ _ [:: _]) align_bind; f_equal; case: linear_c => lbl1 lc1.
by rewrite Hc (Hc _ _ (_ ++ _)); case: linear_c => lbl2 lc2; rewrite !catA cats1 -cat_rcons.
+ by apply Hc.
case: c' Hc' => [ _ | i c' ].
+ by rewrite Hc (Hc _ _ [:: _]) align_bind; case: linear_c => lbl1 lc1; rewrite /= cats1 cat_rcons.
move: (i :: c') => { i c' } c' Hc'.
rewrite Hc (Hc _ _ [:: _]); case: linear_c => lbl1 lc1.
rewrite Hc' (Hc' _ _ (_ :: _)); case: linear_c => lbl2 lc2.
rewrite /=. f_equal. f_equal.
by case: a; rewrite /= cats1 -catA /= cat_rcons.
Qed.
Let Hcall : forall i xs f es, Pr (Ccall i xs f es).
Proof.
move => ini xs fn es ii fn' lbl tail /=.
case: get_fundef => // fd; case: ifP => //.
case: sf_return_address => // [ ra | ra_ofs ] _; first by rewrite cats0 -catA.
case: extra_free_registers => // ra.
by rewrite cats0 -catA.
Qed.
Lemma linear_i_nil fn i lbl tail :
linear_i fn i lbl tail =
let: (lbl, lc) := linear_i fn i lbl [::] in (lbl, lc ++ tail).
Proof.
apply (@instr_Rect _ _ Pr Pi Pc HmkI Hskip Hseq Hassgn Hopn Hif Hfor Hwhile Hcall).
Qed.
Lemma linear_c_nil fn c lbl tail :
linear_c (linear_i fn) c lbl tail =
let: (lbl, lc) := linear_c (linear_i fn) c lbl [::] in (lbl, lc ++ tail).
Proof.
apply (@cmd_rect _ _ Pr Pi Pc HmkI Hskip Hseq Hassgn Hopn Hif Hfor Hwhile Hcall).
Qed.
End CAT.
(* Predicate describing valid labels occurring inside instructions:
“valid_labels fn lo hi i” expresses that labels in instruction “i” are within the range [lo; hi[
and that remote labels to a function other than “fn” are always 1.
*)
Definition valid_labels (fn: funname) (lo hi: label) (i: linstr) : bool :=
match li_i i with
| Lopn _ _ _
| Lalign
| Ligoto _
=> true
| Llabel lbl
| LstoreLabel _ lbl
| Lcond _ lbl
=> (lo <=? lbl) && (lbl <? hi)
| Lgoto (fn', lbl) =>
if fn' == fn then (lo <=? lbl) && (lbl <? hi) else lbl == 1
end%positive.
Definition valid (fn: funname) (lo hi: label) (lc: lcmd) : bool :=
all (valid_labels fn lo hi) lc.
Lemma valid_cat fn min max lc1 lc2 :
valid fn min max (lc1 ++ lc2) = valid fn min max lc1 && valid fn min max lc2.
Proof. exact: all_cat. Qed.
Lemma valid_add_align fn lbl1 lbl2 ii a c :
valid fn lbl1 lbl2 (add_align ii a c) = valid fn lbl1 lbl2 c.
Proof. by case: a. Qed.
Lemma valid_le_min min2 fn min1 max lc :
(min1 <=? min2)%positive ->
valid fn min2 max lc ->
valid fn min1 max lc.
Proof.
move => /Pos_leb_trans h; apply: sub_all; rewrite /valid_labels => -[_/=] [] // => [ lbl | [ fn' lbl ] | _ lbl | _ lbl ].
2: case: ifP => // _.
all: by case/andP => /h ->.
Qed.
Lemma valid_le_max max1 fn max2 min lc :
(max1 <=? max2)%positive ->
valid fn min max1 lc ->
valid fn min max2 lc.
Proof.
move => /Pos_lt_leb_trans h; apply: sub_all; rewrite /valid_labels => -[_/=] [] // => [ lbl | [ fn' lbl ] | _ lbl | _ lbl ].
2: case: ifP => // _.
all: by case/andP => -> /h.
Qed.
Lemma find_labelE lbl c :
find_label lbl c =
if c is i :: c'
then
if is_label lbl i
then ok O
else Let r := find_label lbl c' in ok r.+1
else type_error.
Proof.
case: c => // i c; rewrite /find_label /=.
case: (is_label lbl i) => //.
rewrite ltnS.
by case: ifP.
Qed.
Lemma find_label_cat_hd lbl c1 c2:
~~ has (is_label lbl) c1 ->
find_label lbl (c1 ++ c2) =
(Let pc := find_label lbl c2 in ok (size c1 + pc)).
Proof.
rewrite /find_label find_cat size_cat => /negbTE ->.
by rewrite ltn_add2l;case:ifP.
Qed.
(** Disjoint labels: all labels in “c” are below “lo” or above “hi”. *)
Definition disjoint_labels (lo hi: label) (c: lcmd) : Prop :=
∀ lbl, (lo <= lbl < hi)%positive → ~~ has (is_label lbl) c.
Arguments disjoint_labels _%positive _%positive _.
Lemma disjoint_labels_cat lo hi P Q :
disjoint_labels lo hi P →
disjoint_labels lo hi Q →
disjoint_labels lo hi (P ++ Q).
Proof.
by move => p q lbl r; rewrite has_cat negb_or (p _ r) (q _ r).
Qed.
Lemma disjoint_labels_w lo' hi' lo hi P :
(lo' <= lo)%positive →
(hi <= hi')%positive →
disjoint_labels lo' hi' P →
disjoint_labels lo hi P.
Proof. move => L H k lbl ?; apply: k; lia. Qed.
Lemma disjoint_labels_wL lo' lo hi P :
(lo' <= lo)%positive →
disjoint_labels lo' hi P →
disjoint_labels lo hi P.
Proof. move => L; apply: (disjoint_labels_w L); lia. Qed.
Lemma disjoint_labels_wH hi' lo hi P :
(hi <= hi')%positive →
disjoint_labels lo hi' P →
disjoint_labels lo hi P.
Proof. move => H; apply: (disjoint_labels_w _ H); lia. Qed.
Lemma valid_disjoint_labels fn A B C D P :
valid fn A B P →
(D <= A)%positive ∨ (B <= C)%positive →
disjoint_labels C D P.
Proof.
move => V U lbl [L H]; apply/negP => K.
have {V K} [i _ /andP[] ] := all_has V K.
case: i => ii [] // lbl' /andP[] /Pos.leb_le a /Pos.ltb_lt b /eqP ?; subst lbl'.
lia.
Qed.
Lemma valid_has_not_label fn A B P lbl :
valid fn A B P →
(lbl < A ∨ B <= lbl)%positive →
~~ has (is_label lbl) P.
Proof.
move => /(valid_disjoint_labels) - /(_ lbl (lbl + 1)%positive) V R; apply: V; lia.
Qed.
Definition LSem_step p lparams s1 s2 :
lsem1 p lparams s1 s2 -> lsem p lparams s1 s2 := rt_step _ _ s1 s2.
Lemma snot_spec gd s e b :
sem_pexpr gd s e = ok (Vbool b) →
sem_pexpr gd s (snot e) = sem_pexpr gd s (Papp1 Onot e).
Proof.
elim: e b => //.
- by case => // e _ b; rewrite /= /sem_sop1 /=; t_xrbindP => z -> b' /to_boolI -> _ /=;
rewrite negbK.
- by case => // e1 He1 e2 He2 b /=; t_xrbindP => v1 h1 v2 h2 /sem_sop2I [b1 [b2 [b3]]] []
/to_boolI hb1 /to_boolI hb2 [?] ?; subst v1 v2 b3;
rewrite /= (He1 _ h1) (He2 _ h2) /= h1 h2;
apply: (f_equal (@Ok _ _)); rewrite /= ?negb_and ?negb_or.
move => st p hp e1 he1 e2 he2 b /=.
t_xrbindP => bp vp -> /= -> trv1 v1 h1 htr1 trv2 v2 h2 htr2 /= h.
have : exists (b1 b2:bool), st = sbool /\ sem_pexpr gd s e1 = ok (Vbool b1) /\ sem_pexpr gd s e2 = ok (Vbool b2).
+ rewrite h1 h2;case: bp h => ?;subst.
+ have [??]:= truncate_val_boolI htr1;subst st v1.
by move: htr2; rewrite /truncate_val; t_xrbindP => /= b2 /to_boolI -> ?;eauto.
have [??]:= truncate_val_boolI htr2;subst st v2.
by move: htr1; rewrite /truncate_val; t_xrbindP => /= b1 /to_boolI -> ?;eauto.
move=> [b1 [b2 [-> []/dup[]hb1 /he1 -> /dup[]hb2 /he2 ->]]] /=.
by rewrite hb1 hb2 /=; case bp.
Qed.
Lemma add_align_nil ii a c : add_align ii a c = add_align ii a [::] ++ c.
Proof. by case: a. Qed.
Section LINEARIZE_PARAMS.
Context (mov_op : asm_op) (lparams : linearization_params).
(* Maybe we want to just have [Context (mov_eop : extended_op)]? *)
Let mov_eop : extended_op := BaseOp (None, mov_op).
Record h_linearization_params := {
spec_mov_op : forall lp (s: estate) fn pc x lbl ptr ii,
vtype x == sword Uptr
-> encode_label (label_in_lprog lp) (fn, lbl) = Some ptr
-> let i := LstoreLabel {| v_var := x; v_info := xH; |} lbl in
let vm := evm s in
let s' := with_vm s (vm.[x <- pof_val (vtype x) (Vword ptr)])%vmap in
eval_instr lp mov_eop (MkLI ii i) (of_estate s fn pc)
= ok (of_estate s' fn pc.+1);
spec_lp_allocate_stack_frame :
forall (lp: lprog) (s: estate) sp_rsp ii fn pc ts sz,
let rsp := vid sp_rsp in
let vm := evm s in
let i :=
let args := lparams.(lp_allocate_stack_frame) (VarI rsp xH) sz in
MkLI ii (Lopn args.1.1 args.1.2 args.2)
in
let ts' := pword_of_word (ts + wrepr Uptr sz) in
let s' := with_vm s (vm.[rsp <- ok ts'])%vmap in
(vm.[rsp])%vmap = ok (pword_of_word ts)
-> eval_instr lp mov_eop i (of_estate s fn pc)
= ok (of_estate s' fn pc.+1);
spec_lp_free_stack_frame :
forall (lp: lprog) (s: estate) sp_rsp ii fn pc ts sz,
let rsp := vid sp_rsp in
let vm := evm s in
let i :=
let args := lparams.(lp_free_stack_frame) (VarI rsp xH) sz in
MkLI ii (Lopn args.1.1 args.1.2 args.2)
in
let ts' := pword_of_word (ts - wrepr Uptr sz) in
let s' := with_vm s (vm.[rsp <- ok ts'])%vmap in
(vm.[rsp])%vmap = ok (pword_of_word ts)
-> eval_instr lp mov_eop i (of_estate s fn pc)
= ok (of_estate s' fn pc.+1);
spec_lp_ensure_rsp_alignment :
forall (lp: lprog) (s1: estate) rsp_id ws ts' ii fn pc,
let vrsp := Var (sword Uptr) rsp_id in
let vrspi := VarI vrsp xH in
let rsp' := align_word ws ts' in
get_var (evm s1) vrsp = ok (Vword ts')
->
wf_vm (evm s1) ->
let i :=
let args := lparams.(lp_ensure_rsp_alignment) vrspi ws in
MkLI ii (Lopn args.1.1 args.1.2 args.2)
in
exists vm', [/\
eval_instr
lp
mov_eop
i
(of_estate s1 fn pc)
= ok (of_estate (with_vm s1 vm') fn pc.+1),
vm' = (evm s1).[vrsp <- ok (pword_of_word rsp')]%vmap [\sv_of_flags rflags],
forall x, Sv.In x (sv_of_flags rflags) -> ~ is_ok (vm'.[x]%vmap) -> (evm s1).[x]%vmap = vm'.[x]%vmap
& wf_vm vm'];
spec_lp_lassign :
forall (lp: lprog) (s1 s2: estate) x e ws ws'
(w: word ws) (w': word ws') ii fn pc,
let i :=
let args := lparams.(lp_lassign) x ws e in
MkLI ii (Lopn args.1.1 args.1.2 args.2)
in
sem_pexpr [::] s1 e = ok (Vword w')
-> truncate_word ws w' = ok w
-> write_lval [::] x (Vword w) s1 = ok s2
-> eval_instr
lp
mov_eop
i
(of_estate s1 fn pc)
= ok (of_estate s2 fn pc.+1);
}.
Section HLPARAMS.
Context
(hlparams: h_linearization_params).
Lemma spec_lassign lp s1 s2 x e ws ws' (w:word ws) (w':word ws') ii fn pc :
sem_pexpr [::] s1 e = ok (Vword w') ->
truncate_word ws w' = ok w ->
write_lval [::] x (Vword w) s1 = ok s2 ->
eval_instr
lp
mov_eop
(lassign lparams ii x ws e)
(of_estate s1 fn pc)
= ok (of_estate s2 fn pc.+1).
Proof. exact: spec_lp_lassign. Qed.
Lemma spec_lmove :
forall (lp: lprog) (s1 s2: estate) x ws (w: word ws) y ii fn pc,
get_gvar [::] (evm s1) y = ok (Vword w)
-> write_var x (Vword w) s1 = ok s2
-> eval_instr
lp
mov_eop
(lmove lparams ii x ws y)
(of_estate s1 fn pc)
= ok (of_estate s2 fn pc.+1).
Proof.
move=> lp s1 s2 x ws w y ii fn pc.
move=> Hsem_pexpr.
rewrite /lmove.
apply (spec_lassign lp (x:=Lvar _) (e:=Pvar _) _ _ _ Hsem_pexpr).
by rewrite truncate_word_u.
Qed.
End HLPARAMS.
End LINEARIZE_PARAMS.
(** Technical lemma about the compilation: monotony and unicity of labels. *)
Section VALIDITY.
Context
(p: sprog)
(extra_free_registers: instr_info -> option var)
(lp: lprog)
(mov_op : asm_op)
(lparams: linearization_params)
(hlparams: h_linearization_params mov_op lparams).
Let Pr (i: instr_r) : Prop :=
∀ ii fn lbl,
let: (lbli, li) :=
linear_i p extra_free_registers lparams fn (MkI ii i) lbl [::] in
(lbl <= lbli)%positive ∧ valid fn lbl lbli li.
Let Pi (i: instr) : Prop :=
∀ fn lbl,
let: (lbli, li) :=
linear_i p extra_free_registers lparams fn i lbl [::] in
(lbl <= lbli)%positive ∧ valid fn lbl lbli li.
Let Pc (c: cmd) : Prop :=
∀ fn lbl,
let: (lblc, lc) :=
linear_c (linear_i p extra_free_registers lparams fn) c lbl [::] in
(lbl <= lblc)%positive ∧ valid fn lbl lblc lc.
Let HMkI i ii : Pr i → Pi (MkI ii i).
Proof. exact. Qed.
Let Hnil : Pc [::].
Proof. move => fn lbl /=; split => //; lia. Qed.
Let Hcons (i : instr) (c : cmd) : Pi i → Pc c → Pc (i :: c).
Proof.
move => hi hc fn lbl /=.
case: linear_c (hc fn lbl) => lblc lc [Lc Vc]; rewrite linear_i_nil.
case: linear_i (hi fn lblc) => lbli li [Li Vi]; split; first lia.
rewrite valid_cat; apply/andP; split.
- apply: valid_le_min _ Vi; apply/Pos.leb_le; lia.
apply: valid_le_max _ Vc; apply/Pos.leb_le; lia.
Qed.
Let Hassign (x : lval) (tg : assgn_tag) (ty : stype) (e : pexpr) : Pr (Cassgn x tg ty e).
Proof. move => ii fn lbl /=; case: ty; split => //; exact: Pos.le_refl. Qed.
Let Hopn (xs : lvals) (t : assgn_tag) (o : sopn) (es : pexprs) : Pr (Copn xs t o es).
Proof. split => //; exact: Pos.le_refl. Qed.
Let Hif (e : pexpr) (c1 c2 : cmd) : Pc c1 → Pc c2 → Pr (Cif e c1 c2).
Proof.
move => hc1 hc2 ii fn lbl /=.
case: c1 hc1 => [ | i1 c1 ] hc1.
- rewrite linear_c_nil.
case: linear_c (hc2 fn (next_lbl lbl)); rewrite /next_lbl => lblc2 lc2 [L2 V2]; split; first lia.
have lbl_lt_lblc2 : (lbl <? lblc2)%positive by apply/Pos.ltb_lt; lia.
rewrite /= valid_cat /= /valid_labels /= Pos.leb_refl /= lbl_lt_lblc2 /= andbT.
apply: valid_le_min _ V2; apply/Pos.leb_le; lia.
case: c2 hc2 => [ | i2 c2 ] hc2.
- rewrite linear_c_nil.
case: linear_c (hc1 fn (next_lbl lbl)); rewrite /next_lbl => lblc1 lc1 [L1 V1]; split; first lia.
have lbl_lt_lblc1 : (lbl <? lblc1)%positive by apply/Pos.ltb_lt; lia.
rewrite /= valid_cat /= /valid_labels /= Pos.leb_refl /= lbl_lt_lblc1 /= andbT.
apply: valid_le_min _ V1; apply/Pos.leb_le; lia.
rewrite linear_c_nil.
case: linear_c (hc1 fn (next_lbl (next_lbl lbl))); rewrite /next_lbl => lblc1 lc1 [L1 V1].
rewrite linear_c_nil.
case: linear_c (hc2 fn lblc1) => lblc2 lc2 [L2 V2]; split; first lia.
have lbl_lt_lblc2 : (lbl <? lblc2)%positive by apply/Pos.ltb_lt; lia.
have lblp1_lt_lblc2 : (lbl + 1 <? lblc2)%positive by apply/Pos.ltb_lt; lia.
have lbl_le_lblp1 : (lbl <=? lbl + 1)%positive by apply/Pos.leb_le; lia.
rewrite /= valid_cat /= valid_cat /= /valid_labels /= Pos.leb_refl /= eqxx lbl_lt_lblc2 lblp1_lt_lblc2 lbl_le_lblp1 /= andbT.
apply/andP; split.
- apply: valid_le_min _ V2; apply/Pos.leb_le; lia.
apply: valid_le_min; last apply: valid_le_max _ V1.
all: apply/Pos.leb_le; lia.
Qed.
Let Hfor (v : var_i) (d: dir) (lo hi : pexpr) (c : cmd) : Pc c → Pr (Cfor v (d, lo, hi) c).
Proof. split => //; exact: Pos.le_refl. Qed.
Let Hwhile (a : expr.align) (c : cmd) (e : pexpr) (c' : cmd) : Pc c → Pc c' → Pr (Cwhile a c e c').
Proof.
move => hc hc' ii fn lbl /=.
case: is_boolP => [ [] | {e} e ].
- rewrite linear_c_nil.
case: linear_c (hc' fn (next_lbl lbl)); rewrite /next_lbl => lblc' lc' [Lc' Vc'].
rewrite linear_c_nil.
case: linear_c (hc fn lblc') => lblc lc [Lc Vc] /=; split; first lia.
have lbl_lt_lblc : (lbl <? lblc)%positive by apply/Pos.ltb_lt; lia.
rewrite valid_add_align /= !valid_cat /= /valid_labels /= Pos.leb_refl eqxx lbl_lt_lblc /= andbT.
apply/andP; split.
- apply: valid_le_min _ Vc; apply/Pos.leb_le; lia.
apply: valid_le_max; last apply: valid_le_min _ Vc'; apply/Pos.leb_le; lia.
- by case: linear_c (hc fn lbl).
case: c' hc' => [ | i' c' ] hc'.
- rewrite linear_c_nil.
case: linear_c (hc fn (next_lbl lbl)); rewrite /next_lbl => lblc lc [Lc Vc] /=; split; first lia.
have lbl_lt_lblc : (lbl <? lblc)%positive by apply/Pos.ltb_lt; lia.
rewrite valid_add_align /= valid_cat /= /valid_labels /= Pos.leb_refl lbl_lt_lblc /= andbT.
apply: valid_le_min _ Vc; apply/Pos.leb_le; lia.
rewrite linear_c_nil.
case: linear_c (hc fn (next_lbl (next_lbl lbl))); rewrite /next_lbl => lblc lc [Lc Vc].
rewrite linear_c_nil.
case: linear_c (hc' fn lblc) => lblc' lc' [Lc' Vc'] /=; split; first lia.
have lbl_lt_lblc' : (lbl <? lblc')%positive by apply/Pos.ltb_lt; lia.
have lbl_le_lblp1 : (lbl <=? lbl + 1)%positive by apply/Pos.leb_le; lia.
have lblp1_lt_lblc' : (lbl + 1 <? lblc')%positive by apply/Pos.ltb_lt; lia.
rewrite valid_add_align /= valid_cat /= valid_cat /= /valid_labels /= eqxx Pos.leb_refl lbl_lt_lblc' lbl_le_lblp1 lblp1_lt_lblc' /= andbT.
apply/andP; split.
- apply: valid_le_min _ Vc'; apply/Pos.leb_le; lia.
apply: valid_le_min; last apply: valid_le_max _ Vc.
all: apply/Pos.leb_le; lia.
Qed.
Remark valid_allocate_stack_frame fn lbl b ii z :
valid fn lbl (lbl + 1)%positive (allocate_stack_frame p lparams b ii z).
Proof. by rewrite /allocate_stack_frame; case: eqP. Qed.
Let Hcall (i : inline_info) (xs : lvals) (f : funname) (es : pexprs) : Pr (Ccall i xs f es).
Proof.
move => ii fn lbl /=.
case: get_fundef => [ fd | ]; last by split => //; lia.
case: eqP; first by split => //; lia.
have lbl_lt_lblp1 : (lbl <? lbl + 1)%positive by apply/Pos.ltb_lt; lia.
case: sf_return_address => // ra _.
- rewrite /next_lbl; split; first lia.
rewrite valid_cat /= valid_cat /= !valid_allocate_stack_frame /= /valid_labels /= Pos.leb_refl lbl_lt_lblp1 /= andbT.
by case: eqP => _ //; rewrite Pos.leb_refl lbl_lt_lblp1.
rewrite /next_lbl; case: extra_free_registers => [ ra' | ] ; last by split => //; lia.
split; first lia.
rewrite valid_cat /= valid_cat !valid_allocate_stack_frame /= /valid_labels /= Pos.leb_refl lbl_lt_lblp1 /= andbT.
by case: eqP => _ //; rewrite Pos.leb_refl lbl_lt_lblp1.
Qed.
Definition linear_has_valid_labels : ∀ c, Pc c :=
@cmd_rect _ _ Pr Pi Pc HMkI Hnil Hcons Hassign Hopn Hif Hfor Hwhile Hcall.
Definition linear_has_valid_labels_instr : ∀ i, Pi i :=
@instr_Rect _ _ Pr Pi Pc HMkI Hnil Hcons Hassign Hopn Hif Hfor Hwhile Hcall.
End VALIDITY.
Section PROOF.
Context
(p: sprog)
(extra_free_registers: instr_info -> option var)
(p': lprog)
(mov_op : asm_op)
(lparams: linearization_params)
(hlparams: h_linearization_params mov_op lparams).
Let mov_eop := BaseOp (None, mov_op).
Let vgd : var := vid p.(p_extra).(sp_rip).
Let vrsp : var := vid p.(p_extra).(sp_rsp).
Let var_tmp : var_i := vid lparams.(lp_tmp).
Hypothesis var_tmp_not_magic : ~~ Sv.mem var_tmp (magic_variables p).
Hypothesis linear_ok : linear_prog p extra_free_registers lparams = ok p'.
Notation linear_i := (linear_i p extra_free_registers lparams).
Notation linear_c fn := (linear_c (linear_i fn)).
Notation sem_I := (sem_one_varmap.sem_I p extra_free_registers var_tmp).
Notation sem_i := (sem_one_varmap.sem_i p extra_free_registers var_tmp).
Notation sem := (sem_one_varmap.sem p extra_free_registers var_tmp).
Notation valid_c fn c :=
(linear_has_valid_labels p extra_free_registers lparams c fn).
Notation valid_i fn i :=
(linear_has_valid_labels_instr p extra_free_registers lparams i fn).
Definition checked_i fn i : bool :=
if get_fundef (p_funcs p) fn is Some fd
then
if check_i p extra_free_registers fn fd.(f_extra).(sf_align) i is Ok tt
then true
else false
else false.
Lemma checked_iE fn i :
checked_i fn i →
exists2 fd, get_fundef (p_funcs p) fn = Some fd & check_i p extra_free_registers fn fd.(f_extra).(sf_align) i = ok tt.
Proof.
rewrite /checked_i; case: get_fundef => // fd h; exists fd; first by [].
by case: check_i h => // - [].
Qed.
Definition checked_c fn c : bool :=
if get_fundef (p_funcs p) fn is Some fd
then
if check_c (check_i p extra_free_registers fn fd.(f_extra).(sf_align)) c is Ok tt
then true
else false
else false.
Lemma checked_cE fn c :
checked_c fn c →
exists2 fd, get_fundef (p_funcs p) fn = Some fd & check_c (check_i p extra_free_registers fn fd.(f_extra).(sf_align)) c = ok tt.
Proof.
rewrite /checked_c; case: get_fundef => // fd h; exists fd; first by [].
by case: check_c h => // - [].
Qed.
Lemma checked_cI fn i c :
checked_c fn (i :: c) →
checked_i fn i ∧ checked_c fn c.
Proof.
by case/checked_cE => fd ok_fd; rewrite /checked_c /checked_i ok_fd /= ; t_xrbindP => - [] -> ->.
Qed.
Local Lemma p_globs_nil : p_globs p = [::].
Proof.
by move: linear_ok; rewrite /linear_prog; t_xrbindP => _ _ _ /assertP /eqP /size0nil.
Qed.
Local Lemma checked_prog fn fd :
get_fundef (p_funcs p) fn = Some fd →
check_fd p extra_free_registers lparams fn fd = ok tt.
Proof.
move: linear_ok; rewrite /linear_prog; t_xrbindP => ? ok_p _ /assertP /eqP _ hp'.
move: ok_p; rewrite /check_prog; t_xrbindP => r C _ M.
by have [[]]:= get_map_cfprog_name_gen C M.
Qed.
Lemma get_fundef_p' f fd :
get_fundef (p_funcs p) f = Some fd →
get_fundef (lp_funcs p') f
= Some (linear_fd p extra_free_registers lparams f fd).
Proof.
move: linear_ok; rewrite /linear_prog; t_xrbindP => _ _ _ _ <- /=.
by rewrite /get_fundef assoc_map2 => ->.
Qed.
Lemma lp_ripE : lp_rip p' = sp_rip p.(p_extra).
Proof. by move: linear_ok; rewrite /linear_prog; t_xrbindP => _ _ _ _ <-. Qed.
Lemma lp_rspE : lp_rsp p' = sp_rsp p.(p_extra).
Proof. by move: linear_ok; rewrite /linear_prog; t_xrbindP => _ _ _ _ <-. Qed.
Lemma lp_globsE : lp_globs p' = sp_globs p.(p_extra).
Proof. by move: linear_ok; rewrite /linear_prog; t_xrbindP => _ _ _ _ <-. Qed.
Local Coercion emem : estate >-> mem.
Local Coercion evm : estate >-> vmap.
(** Relation between source and target memories
- There is a well-aligned valid block in the target
*)
Record match_mem (m m': mem) : Prop :=
MM {
read_incl : ∀ p w, read m p U8 = ok w → read m' p U8 = ok w
; valid_incl : ∀ p, validw m p U8 → validw m' p U8
; valid_stk : ∀ p,
(wunsigned (stack_limit m) <= wunsigned p < wunsigned(stack_root m))%Z
→ validw m' p U8
}.
Lemma mm_free m1 m1' :
match_mem m1 m1' →
match_mem (free_stack m1) m1'.
Proof.
case => Hrm Hvm Hsm; split.
(* read *)
+ move=> p1 w1 Hr.
apply: Hrm. rewrite -Hr. apply: fss_read_old; [ exact: free_stackP | exact: readV Hr ].
(* valid *)
+ move=> p1 Hv.
assert (Hs := free_stackP). move: (Hs m1)=> Hm1. move: (Hs m1')=> Hm1'.
have Heq := (fss_valid Hm1). have Heq' := (fss_valid Hm1').
apply Hvm. rewrite Heq in Hv. move: Hv. move=>/andP [] Hv1 Hv2.
apply Hv1.
(* stack *)
assert (Hs := free_stackP). move: (Hs m1)=> Hm1. move: (Hs m1')=> Hm1'.
have Heq := (fss_valid Hm1).
move=> p1 Hs'. apply Hsm. have <- := fss_root Hm1. by have <- := fss_limit Hm1.
Qed.
Lemma mm_read_ok : ∀ m m' a s v,
match_mem m m' →
read m a s = ok v →
read m' a s = ok v.
Proof.
move=> m m' p'' s v [] Hrm Hvm Hsm Hr.
have := read_read8 Hr. move=> [] Ha Hi.
have : validw m' p'' s. apply /validwP.
split=>//. move=> i Hi'. apply Hvm. move: (Hi i Hi')=> Hr'.
by have Hv := readV Hr'. move=> Hv. rewrite -Hr.
apply eq_read. move=> i Hi'. move: (Hi i Hi')=> Hr'.
move: (Hrm (add p'' i) (LE.wread8 v i) Hr'). move=> Hr''.
by rewrite Hr' Hr''.
Qed.
Lemma mm_write : ∀ m1 m1' p s (w:word s) m2,
match_mem m1 m1' →
write m1 p w = ok m2 →
exists2 m2', write m1' p w = ok m2' & match_mem m2 m2'.
Proof.
move=> m1 m1' p'' sz w m2 Hm Hw.
case: Hm=> H1 H2 H3. have /validwP := (write_validw Hw).
move=> [] Ha Hi.
have /writeV : validw m1' p'' sz. apply /validwP. split=> //. move=> i Hi'.
move: (Hi i Hi')=> Hv. by move: (H2 (add p'' i) Hv). move=> Hw'.
move: (Hw' w). move=> [] m2' Hw''. exists m2'.
+ by apply Hw''.
constructor.
(* read *)
+ move=> p1 w1 Hr2. have hr1:= write_read8 Hw p1.
have hr2 := write_read8 Hw'' p1. move: Hr2. rewrite hr2 hr1 /=.
case: ifP=> // _. by apply H1.
(* valid *)
+ move=> p1 Hv. have Hv1 := (CoreMem.write_validw_eq Hw).
have Hv2 := (CoreMem.write_validw_eq Hw''). rewrite Hv2.
apply H2. by rewrite -Hv1.
(* stack *)
move=> p1 H. have Hv1 := (CoreMem.write_validw_eq Hw).
have Hv2 := (CoreMem.write_validw_eq Hw''). rewrite Hv2.
apply H3. have Hst := write_mem_stable Hw. case: Hst.
by move=> -> -> _.
Qed.
Lemma mm_alloc m1 m1' al sz es' m2 :
match_mem m1 m1' →
alloc_stack m1 al sz es' = ok m2 →
match_mem m2 m1'.
Proof.
case => Hvm Hrm Hs /alloc_stackP[] Hvr Hve Hveq Ha Hs' Hs'' Hsr Hsl Hf.
constructor.
(* read *)
+ move=> p1 w1 /dup[] Hr1.
move: (Hve p1) (Hvr p1).
have -> := readV Hr1.
case: validw.
* by move => _ <- // /Hvm.
by move => ->.
(* valid *)
+ move => p1; rewrite Hveq => /orP[]; first exact: Hrm.
move => range; apply: Hs; move: range; rewrite !zify => - [] lo.
change (wsize_size U8) with 1%Z.
generalize (top_stack_below_root _ m1); rewrite -/(top_stack m1).
lia.
(* stack *)
move=> p1 Hs'''. apply Hs. by rewrite -Hsr -Hsl.
Qed.
Lemma mm_write_invalid m m1' a s (w: word s) :
match_mem m m1' →
(wunsigned (stack_limit m) <= wunsigned a ∧ wunsigned a + wsize_size s <= wunsigned (top_stack m))%Z →
is_align a s →
exists2 m2', write m1' a w = ok m2' & match_mem m m2'.
Proof.
case => Hrm Hvm Hs Hs' al.
have /writeV : validw m1' a s.
- apply/validwP; split; first exact: al.
move => k [] klo khi; apply: Hs.
have a_range := wunsigned_range a.
assert (r_range := wunsigned_range (stack_root m)).
generalize (top_stack_below_root _ m); rewrite -/(top_stack m) => R.
rewrite wunsigned_add; lia.
move => /(_ w) [] m' ok_m'; exists m'; first exact: ok_m'.
split.
- move => x y ok_y.
rewrite (CoreMem.writeP_neq ok_m'); first exact: Hrm.
move => i j [] i_low i_hi; change (wsize_size U8) with 1%Z => j_range.
have ? : j = 0%Z by lia.
subst j => { j_range }.
rewrite add_0 => ?; subst x.
apply/negP: (readV ok_y).
apply: stack_region_is_free.
rewrite -/(top_stack m) wunsigned_add; first lia.
have := wunsigned_range a.
generalize (wunsigned_range (top_stack m)).
lia.
1-2: move => b; rewrite (CoreMem.write_validw_eq ok_m').
- exact/Hvm.
exact/Hs.
Qed.
Section MATCH_MEM_SEM_PEXPR.
Context (m m': mem) (vm: vmap) (M: match_mem m m').
Let P (e: pexpr) : Prop :=
∀ v,
sem_pexpr [::] {| emem := m ; evm := vm |} e = ok v →
sem_pexpr [::] {| emem := m' ; evm := vm |} e = ok v.
Let Q (es: pexprs) : Prop :=
∀ vs,
sem_pexprs [::] {| emem := m ; evm := vm |} es = ok vs →
sem_pexprs [::] {| emem := m' ; evm := vm |} es = ok vs.
Lemma match_mem_sem_pexpr_pair : (∀ e, P e) ∧ (∀ es, Q es).
Proof.
apply: pexprs_ind_pair; split.
- by [].
- by move => e ihe es ihes vs /=; t_xrbindP => ? /ihe -> /= ? /ihes -> /= ->.
1-4: by rewrite /P /=.
- move => aa sz x e ihe vs /=.
by apply: on_arr_gvarP => ??? -> /=; t_xrbindP => ?? /ihe -> /= -> /= ? -> /= ->.
- move => aa sz len x e ihe v /=.
by apply: on_arr_gvarP => ??? -> /=; t_xrbindP => ?? /ihe -> /= -> /= ? -> /= ->.
- by move => sz x e ihe v /=; t_xrbindP => ?? -> /= -> /= ?? /ihe -> /= -> /= ? /(mm_read_ok M) -> /= ->.
- by move => op e ihe v /=; t_xrbindP => ? /ihe ->.
- by move => op e1 ih1 e2 ih2 v /=; t_xrbindP => ? /ih1 -> ? /ih2 ->.
- by move => op es ih vs /=; t_xrbindP => ? /ih; rewrite -/(sem_pexprs [::] _ es) => ->.
by move => ty e ihe e1 ih1 e2 ih2 v /=; t_xrbindP => ?? /ihe -> /= -> ?? /ih1 -> /= -> ?? /ih2 -> /= -> /= ->.
Qed.
Lemma match_mem_sem_pexpr e : P e.
Proof. exact: (proj1 match_mem_sem_pexpr_pair). Qed.
Lemma match_mem_sem_pexprs es : Q es.
Proof. exact: (proj2 match_mem_sem_pexpr_pair). Qed.
End MATCH_MEM_SEM_PEXPR.
Lemma match_mem_write_lval m1 vm1 m1' m2 vm2 x v :
match_mem m1 m1' →
write_lval [::] x v {| emem := m1 ; evm := vm1 |} = ok {| emem := m2 ; evm := vm2 |} →
exists2 m2',
write_lval [::] x v {| emem := m1' ; evm := vm1 |} = ok {| emem := m2' ; evm := vm2 |} &
match_mem m2 m2'.
Proof.
move => M; case: x => /= [ _ ty | x | ws x e | aa ws x e | aa ws n x e ].
- case/write_noneP => - [] -> -> h; exists m1'; last exact: M.
rewrite /write_none.
by case: h => [ [u ->] | [ -> -> ] ].
- rewrite /write_var /=; t_xrbindP =>_ -> <- -> /=.
by exists m1'.
- t_xrbindP => ?? -> /= -> /= ?? /(match_mem_sem_pexpr M) -> /= -> /= ? -> /= ? /(mm_write M)[] ? -> /= M' <- <-.
eexists; first reflexivity; exact: M'.
all: apply: on_arr_varP; rewrite /write_var; t_xrbindP => ??? -> /= ?? /(match_mem_sem_pexpr M) -> /= -> /= ? -> /= ? -> /= ? -> /= <- <-.
all: by exists m1'.
Qed.
Lemma match_mem_write_lvals m1 vm1 m1' m2 vm2 xs vs :
match_mem m1 m1' →
write_lvals [::] {| emem := m1 ; evm := vm1 |} xs vs = ok {| emem := m2 ; evm := vm2 |} →
exists2 m2',
write_lvals [::] {| emem := m1' ; evm := vm1 |} xs vs = ok {| emem := m2' ; evm := vm2 |} &
match_mem m2 m2'.
Proof.
elim: xs vs vm1 m1 m1'.
- by case => // vm1 m1 m1' M [] <- <- {m2 vm2}; exists m1'.
by move => x xs ih [] // v vs vm1 m1 m1' M /=; t_xrbindP => - [] ?? /(match_mem_write_lval M)[] m2' -> M2 /ih - /(_ _ M2).
Qed.
Definition is_linear_of (fn: funname) (c: lcmd) : Prop :=
exists2 fd, get_fundef (lp_funcs p') fn = Some fd & fd.(lfd_body) = c.
Definition is_ra_of (fn: funname) (ra: return_address_location) : Prop :=
exists2 fd, get_fundef (p_funcs p) fn = Some fd & fd.(f_extra).(sf_return_address) = ra.
(** Export functions allocate their own stack frames
* whereas internal functions have their frame allocated by the caller *)
Definition is_sp_for_call (fn: funname) (m: mem) (ptr: pointer) : Prop :=
exists2 fd,
get_fundef (p_funcs p) fn = Some fd &
let e := fd.(f_extra) in
if e.(sf_return_address) is RAnone
then ptr = top_stack m
else
is_align (top_stack m) e.(sf_align) ∧
let sz := stack_frame_allocation_size e in ptr = (top_stack m - wrepr Uptr sz)%R.
Definition value_of_ra
(m: mem)
(vm: vmap)
(ra: return_address_location)
(target: option (remote_label * lcmd * nat))
: Prop :=
match ra, target with
| RAnone, None => True
| RAreg (Var (sword ws) _ as ra), Some ((caller, lbl), cbody, pc) =>
if (ws == Uptr)%CMP
then [/\ is_linear_of caller cbody,
find_label lbl cbody = ok pc &
exists2 ptr,
encode_label (label_in_lprog p') (caller, lbl) = Some ptr &
vm.[ra] = ok (pword_of_word (zero_extend ws ptr))
]
else False
| RAstack ofs, Some ((caller, lbl), cbody, pc) =>
[/\ is_linear_of caller cbody,
find_label lbl cbody = ok pc &
exists2 ptr, encode_label (label_in_lprog p') (caller, lbl) = Some ptr &
exists2 sp, vm.[ vrsp ] = ok (pword_of_word sp) & read m (sp + wrepr Uptr ofs)%R Uptr = ok ptr
]
| _, _ => False
end%vmap.
(* Export functions save and restore the contents of “to-save” registers. *)
Definition is_callee_saved_of (fn: funname) (s: seq var) : Prop :=
exists2 fd,
get_fundef (p_funcs p) fn = Some fd &
let e := f_extra fd in
if sf_return_address e is RAnone then
s = map fst (sf_to_save e)
else s = [::].
(* Execution of linear programs preserve meta-data stored in the stack memory *)
Definition preserved_metadata (m m1 m2: mem) : Prop :=
∀ p : pointer,
(wunsigned (top_stack m) <= wunsigned p < wunsigned (stack_root m))%Z →
~~ validw m p U8 →
read m1 p U8 = read m2 p U8.
Instance preserved_metadata_equiv m : Equivalence (preserved_metadata m).
Proof.
split; first by [].
- by move => x y xy ptr r nv; rewrite xy.
move => x y z xy yz ptr r nv.
by rewrite xy; first exact: yz.
Qed.
Lemma preserved_metadataE (m m' m1 m2: mem) :
stack_stable m m' →
validw m =2 validw m' →
preserved_metadata m' m1 m2 →
preserved_metadata m m1 m2.
Proof.
move => ss e h ptr r nv.
apply: h.
- by rewrite -(ss_top_stack ss) -(ss_root ss).
by rewrite -e.
Qed.
Lemma write_lval_preserves_metadata x v v' s s' t t' :
write_lval [::] x v s = ok s' →
write_lval [::] x v' t = ok t' →
vm_uincl s t →
match_mem s t →
preserved_metadata (emem s) (emem t) (emem t').
Proof.
case: x.
- move => /= _ ty /write_noneP[] <- _ /write_noneP[] -> _; reflexivity.
- move => x /write_var_emem -> /write_var_emem ->; reflexivity.
- case: s t => m vm [] tv tvm /=.
move => sz x e ok_s' ok_t' X M.
move: ok_s' => /=; t_xrbindP => a xv ok_xv ok_a ofs ev ok_ev ok_ofs w ok_w m' ok_m' _{s'}.
move: ok_t' => /=.
have [ xv' -> /= xv_xv' ] := get_var_uincl X ok_xv.
rewrite (value_uincl_word xv_xv' ok_a) /=.
have /= ok_ev' := match_mem_sem_pexpr M ok_ev.
have /(_ _ X) := sem_pexpr_uincl _ ok_ev'.
case => ev' -> ev_ev' /=.
rewrite (value_uincl_word ev_ev' ok_ofs) /=.
t_xrbindP => w' ok_w' tm' ok_tm' <-{t'} /=.
move => ptr ptr_range /negP ptr_not_valid.
rewrite (CoreMem.writeP_neq ok_tm'); first reflexivity.
apply: disjoint_range_U8 => i i_range ?; subst ptr.
apply: ptr_not_valid.
rewrite -valid8_validw.
have /andP[ _ /allP ] := write_validw ok_m'.
apply.
rewrite in_ziota !zify; Lia.lia.
- move => aa sz x e; apply: on_arr_varP; rewrite /write_var; t_xrbindP => ???????????????.
apply: on_arr_varP; rewrite /write_var; t_xrbindP => ???????????????.
subst; reflexivity.
move => aa sz k x e; apply: on_arr_varP; rewrite /write_var; t_xrbindP => ???????????????.
apply: on_arr_varP; rewrite /write_var; t_xrbindP => ???????????????.
subst; reflexivity.
Qed.
Lemma write_lvals_preserves_metadata xs vs vs' s s' t t' :
List.Forall2 value_uincl vs vs' →
write_lvals [::] s xs vs = ok s' →
write_lvals [::] t xs vs' = ok t' →
vm_uincl s t →
match_mem s t →
preserved_metadata (emem s) (emem t) (emem t').
Proof.
move => h; elim: h xs s t => {vs vs'}.
- case => // ?? [] -> [] -> _ _; reflexivity.
move => v v' vs vs' v_v' vs_vs' ih [] // x xs s t /=.
apply: rbindP => s1 ok_s1 ok_s' ok_t' X M.
have [ vm ok_vm X' ] := write_uincl X v_v' ok_s1.
have [ m' ok_t1 M' ] := match_mem_write_lval M ok_vm.
move: ok_t'.
rewrite (surj_estate t) ok_t1 /= => ok_t'.
etransitivity.
- exact: write_lval_preserves_metadata ok_s1 ok_t1 X M.
apply: preserved_metadataE;
last apply: (ih _ _ _ ok_s' ok_t').
- exact: write_lval_stack_stable ok_s1.
- exact: write_lval_validw ok_s1.
- exact: X'.
exact: M'.
Qed.
Lemma preserved_metadata_alloc m al sz sz' m' m1 m2 :
(0 <= sz)%Z →
alloc_stack m al sz sz' = ok m' →
preserved_metadata m' m1 m2 →
preserved_metadata m m1 m2.
Proof.
move => sz_pos ok_m' h a [] a_lo a_hi /negbTE a_not_valid.
have A := alloc_stackP ok_m'.
have [_ top_goes_down ] := ass_above_limit A.
apply: h.
- split; last by rewrite A.(ass_root).
apply: Z.le_trans a_lo.
etransitivity; last apply: top_goes_down.
lia.
rewrite A.(ass_valid) a_not_valid /= !zify.
change (wsize_size U8) with 1%Z.
lia.
Qed.
(* ---------------------------------------------------- *)
Variant ex2_6 (T1 T2: Type) (A B C D E F : T1 → T2 → Prop) : Prop :=
Ex2_6 x1 x2 of A x1 x2 & B x1 x2 & C x1 x2 & D x1 x2 & E x1 x2 & F x1 x2.
Let Pi (k: Sv.t) (s1: estate) (i: instr) (s2: estate) : Prop :=
∀ fn lbl,
checked_i fn i →
let: (lbli, li) := linear_i fn i lbl [::] in
∀ m1 vm1 P Q,
wf_vm vm1 →
match_mem s1 m1 →
vm_uincl s1 vm1 →
disjoint_labels lbl lbli P →
is_linear_of fn (P ++ li ++ Q) →
ex2_6
(λ m2 vm2, lsem
p'
mov_eop
(Lstate m1 vm1 fn (size P))
(Lstate m2 vm2 fn (size (P ++ li)))
)
(λ _ vm2, vm1 = vm2 [\ k ])
(λ _ vm2, wf_vm vm2)
(λ _ vm2, vm_uincl s2 vm2)
(λ m2 _, preserved_metadata s1 m1 m2)
(λ m2 _, match_mem s2 m2).
Let Pi_r (ii: instr_info) (k: Sv.t) (s1: estate) (i: instr_r) (s2: estate) : Prop :=
∀ fn lbl,
checked_i fn (MkI ii i) →
let: (lbli, li) := linear_i fn (MkI ii i) lbl [::] in
(if extra_free_registers ii is Some fr then
[/\ fr <> vgd, fr <> vrsp, vtype fr = sword Uptr & s1.[fr]%vmap = Error ErrAddrUndef]
else True) →
∀ m1 vm1 P Q,
wf_vm vm1 →
match_mem s1 m1 →
vm_uincl s1 vm1 →
disjoint_labels lbl lbli P →
is_linear_of fn (P ++ li ++ Q) →
ex2_6
(λ m2 vm2, lsem
p'
mov_eop
(Lstate m1 vm1 fn (size P))
(Lstate m2 vm2 fn (size (P ++ li)))
)
(λ _ vm2, vm1 = vm2 [\ Sv.union k (extra_free_registers_at extra_free_registers ii)])
(λ _ vm2, wf_vm vm2)
(λ _ vm2, vm_uincl s2 vm2)
(λ m2 _, preserved_metadata s1 m1 m2)
(λ m2 _, match_mem s2 m2).
Let Pc (k: Sv.t) (s1: estate) (c: cmd) (s2: estate) : Prop :=
∀ fn lbl,
checked_c fn c →
let: (lblc, lc) := linear_c fn c lbl [::] in
∀ m1 vm1 P Q,
wf_vm vm1 →
match_mem s1 m1 →
vm_uincl s1 vm1 →
disjoint_labels lbl lblc P →
is_linear_of fn (P ++ lc ++ Q) →
ex2_6
(λ m2 vm2, lsem
p'
mov_eop
(Lstate m1 vm1 fn (size P))
(Lstate m2 vm2 fn (size (P ++ lc)))
)
(λ _ vm2, vm1 = vm2 [\ k ])
(λ _ vm2, wf_vm vm2)
(λ _ vm2, vm_uincl s2 vm2)
(λ m2 _, preserved_metadata s1 m1 m2)
(λ m2 _, match_mem s2 m2).
Let Pfun (ii: instr_info) (k: Sv.t) (s1: estate) (fn: funname) (s2: estate) : Prop :=
∀ m1 vm1 body ra lret sp callee_saved,
wf_vm vm1 →
match_mem s1 m1 →
vm_uincl
(kill_vars match ra with
| RAnone => Sv.singleton var_tmp
| RAreg x => Sv.singleton x
| RAstack _ => Sv.empty
end s1).[vrsp <- ok (pword_of_word sp)]%vmap vm1 →
is_linear_of fn body →
(* RA contains a safe return address “lret” *)
is_ra_of fn ra →
value_of_ra m1 vm1 ra lret →
(* RSP points to the top of the stack according to the calling convention *)
is_sp_for_call fn s1 sp →
(* To-save variables are initialized in the initial linear state *)
is_callee_saved_of fn callee_saved →
vm_initialized_on vm1 callee_saved →
ex2_6
(λ m2 vm2,
if lret is Some ((caller, lbl), _cbody, pc)
then lsem p' mov_eop (Lstate m1 vm1 fn 1) (Lstate m2 vm2 caller pc.+1)
else lsem p' mov_eop (Lstate m1 vm1 fn 0) (Lstate m2 vm2 fn (size body)))
(λ _ vm2, vm1 = vm2 [\ if ra is RAnone then Sv.diff k (sv_of_list id callee_saved) else Sv.union k (extra_free_registers_at extra_free_registers ii)])
(λ _ vm2, wf_vm vm2)
(λ _ vm2, s2.[vrsp <- ok (pword_of_word sp)] <=[\ sv_of_list id callee_saved ] vm2)
(λ m2 _, preserved_metadata s1 m1 m2)
(λ m2 _, match_mem s2 m2).
Lemma label_in_lfundef fn body (lbl: label) :
lbl \in label_in_lcmd body →
is_linear_of fn body →
(fn, lbl) \in label_in_lprog p'.
Proof.
clear.
rewrite /label_in_lprog => X [] fd ok_fd ?; subst body.
apply/flattenP => /=.
exists [seq (fn, lbl) | lbl <- label_in_lcmd (lfd_body fd) ];
last by apply/map_f: X.
apply/in_map.
by exists (fn, fd); first exact: get_fundef_in'.
Qed.
Local Lemma Hnil : sem_Ind_nil Pc.
Proof.
move => s1 fn lbl _ m1 vm1 P Q M X D C; rewrite cats0; exists m1 vm1 => //; exact: rt_refl.
Qed.
Local Lemma Hcons : sem_Ind_cons p extra_free_registers var_tmp Pc Pi.
Proof.
move => ki kc s1 s2 s3 i c exec_i hi _ hc.
move => fn lbl /checked_cI[] chk_i chk_c /=.
case: (linear_c fn) (valid_c fn c lbl) (hc fn lbl chk_c) => lblc lc [Lc Vc] Sc.
rewrite linear_i_nil.
case: linear_i (valid_i fn i lblc) (hi fn lblc chk_i) => lbli li [Li Vi] Si.
move => m1 vm1 P Q Wc Mc Xc Dc C.
have D : disjoint_labels lblc lbli P.
+ apply: (disjoint_labels_wL _ Dc); exact: Lc.
have C' : is_linear_of fn (P ++ li ++ lc ++ Q).
+ by move: C; rewrite !catA.
have [ m2 vm2 Ei Ki Wi Xi Hi Mi ] := Si m1 vm1 P (lc ++ Q) Wc Mc Xc D C'.
have Di : disjoint_labels lbl lblc (P ++ li).
+ apply: disjoint_labels_cat.
* apply: (disjoint_labels_wH _ Dc); exact: Li.
apply: (valid_disjoint_labels Vi); lia.
have Ci : is_linear_of fn ((P ++ li) ++ lc ++ Q).
+ by move: C; rewrite !catA.
have [ m3 vm3 ] := Sc m2 vm2 (P ++ li) Q Wi Mi Xi Di Ci.
rewrite -!catA => E K W X H M.
exists m3 vm3; [ | | exact: W | exact: X | | exact: M ]; cycle 2.
+ etransitivity; first exact: Hi.
apply: preserved_metadataE H.
+ exact: sem_I_stack_stable exec_i.
exact: sem_I_validw_stable exec_i.
+ exact: lsem_trans Ei E.
apply: vmap_eq_exceptT; apply: vmap_eq_exceptI.
2: exact: Ki.
3: exact: K.
all: SvD.fsetdec.
Qed.
Local Lemma HmkI : sem_Ind_mkI p extra_free_registers var_tmp Pi Pi_r.
Proof.
move => ii k i s1 s2 ok_fr _ h _ fn lbl chk.
move: h => /(_ fn lbl chk); case: linear_i (valid_i fn (MkI ii i) lbl) => lbli li [L V] S.
move => m1 vm1 P Q W M X D C.
have E :
match extra_free_registers ii return Prop with
| Some fr =>
[/\ fr ≠ vgd, fr ≠ vrsp, vtype fr = spointer
& ((kill_extra_register extra_free_registers ii s1).[fr])%vmap = Error ErrAddrUndef]
| None => True
end.
+ rewrite /kill_extra_register /kill_extra_register_vmap.
rewrite /efr_valid in ok_fr.
case: extra_free_registers ok_fr
=> // fr /and3P [] /eqP hrip /eqP hrsp /andP[] /eqP hty not_while;
split => //=.
rewrite /=; case heq: s1.[fr]%vmap (W fr) (X fr) => [vfr | efr /=].
+ by move=> _ _; rewrite Fv.setP_eq hty.
rewrite heq; case: vm1.[fr]%vmap.
+ by move=> _ _; case efr.
by move=> [] // _; case: (efr).
have {S E} S := S E.
have [ | {W M X} ] := S _ vm1 _ _ W M _ D C.
- by apply: vm_uincl_trans; first exact: kill_extra_register_vm_uincl.
move => m2 vm2 E K W X H M.
exists m2 vm2.
- exact: E.
- apply: vmap_eq_exceptI K; SvD.fsetdec.
- exact: W.
- exact: X.
- exact: preserved_metadataE H.
exact: M.
Qed.
Lemma find_instrE fn body :
is_linear_of fn body →
∀ m vm n,
find_instr p' (Lstate m vm fn n) = oseq.onth body n.
Proof. by rewrite /find_instr => - [] fd /= -> ->. Qed.
Lemma find_instr_skip fn P Q :
is_linear_of fn (P ++ Q) →
∀ m vm n,
find_instr p' (Lstate m vm fn (size P + n)) = oseq.onth Q n.
Proof.
move => h m vm n; rewrite (find_instrE h).
rewrite !oseq.onth_nth map_cat nth_cat size_map.
rewrite ltnNge leq_addr /=;f_equal;rewrite -minusE -plusE; lia.
Qed.
Local Lemma Hasgn : sem_Ind_assgn p Pi_r.
Proof.
move => ii s1 s2 x tg ty e v v'; rewrite p_globs_nil => ok_v ok_v' ok_s2.
move => fn lbl /checked_iE[] fd ok_fd.
case: ty ok_v' ok_s2 => // sz.
apply: rbindP => w /of_val_word [sz'] [w'] [hle ? ?]; subst v w => -[<-] {v'} ok_s2 chk.
move => fr_undef m1 vm1 P Q W1 M1 X1 D1 C1.
have [ v' ok_v' ] := sem_pexpr_uincl X1 ok_v.
case/value_uinclE => [sz''] [w] [?]; subst v' => /andP[] hle' /eqP ?; subst w'.
rewrite (zero_extend_idem _ hle) in ok_s2.
have [ vm2 /(match_mem_write_lval M1) [ m2 ok_s2' M2 ] ok_vm2 ] := write_uincl X1 (value_uincl_refl _) ok_s2.
exists m2 vm2; [ | | | exact: ok_vm2 | | exact: M2]; last first.
+ exact: write_lval_preserves_metadata ok_s2 ok_s2' X1 M1.
+ exact: wf_write_lval ok_s2'.
+ apply: vmap_eq_exceptI; first exact: SvP.MP.union_subset_1.
by have := vrvP ok_s2'.
apply: LSem_step.
rewrite -(addn0 (size P)) /lsem1 /step /= (find_instr_skip C1) /=.
rewrite /of_estate size_cat addn1 addn0.
apply: (spec_lassign hlparams _ (s1:={|evm:=_; emem:=_|}) (s2:={|evm:=_; emem:=_|}))
(match_mem_sem_pexpr M1 ok_v') _ ok_s2'.
by rewrite /truncate_word (cmp_le_trans hle hle').
Qed.
Local Lemma Hopn : sem_Ind_opn p Pi_r.
Proof.
move => ii s1 s2 tg op xs es; rewrite /sem_sopn; t_xrbindP => rs vs.
rewrite p_globs_nil => ok_vs ok_rs ok_s2.
move => fn lbl /checked_iE[] fd ok_fd chk.
move => fr_undef m1 vm1 P Q W1 M1 X1 D1 C1.
have [ vs' /(match_mem_sem_pexprs M1) ok_vs' vs_vs' ] := sem_pexprs_uincl X1 ok_vs.
have [ rs' ok_rs' rs_rs' ] := vuincl_exec_opn vs_vs' ok_rs.
have [ vm2 /(match_mem_write_lvals M1) [ m2 ok_s2' M2 ] ok_vm2 ] := writes_uincl X1 rs_rs' ok_s2.
exists m2 vm2; [ | | | exact: ok_vm2 | | exact: M2 ]; last first.
+ exact: write_lvals_preserves_metadata ok_s2 ok_s2' X1 M1.
+ exact: wf_write_lvals ok_s2'.
+ apply: vmap_eq_exceptI; first exact: SvP.MP.union_subset_1.
by have := vrvsP ok_s2'.
apply: LSem_step.
rewrite -(addn0 (size P)) /lsem1 /step /= (find_instr_skip C1) /= /eval_instr /to_estate /=.
by rewrite /sem_sopn ok_vs' /= ok_rs' /= ok_s2' /= size_cat addn0 addn1.
Qed.
Remark next_lbl_neq (lbl: label) :
((lbl + 1)%positive == lbl) = false.
Proof.
apply/eqP => k.
suff : (lbl < lbl)%positive by lia.
rewrite -{2}k; lia.
Qed.
Lemma eval_jumpE fn body :
is_linear_of fn body →
∀ lbl s,
eval_jump p' (fn, lbl) s = Let pc := find_label lbl body in ok (setcpc s fn pc.+1).
Proof. by case => ? /= -> ->. Qed.
Local Lemma Hif_true : sem_Ind_if_true p extra_free_registers var_tmp Pc Pi_r.
Proof.
move => ii k s1 s2 e c1 c2; rewrite p_globs_nil => ok_e E1 Hc1 fn lbl /checked_iE[] fd ok_fd /=; apply: rbindP => -[] chk_c1 _.
case: c1 E1 Hc1 chk_c1 => [ | i1 c1 ] E1 Hc1 chk_c1; last case: c2 => [ | i2 c2 ].
+ case/semE: E1 => hk ?; subst s2.
rewrite /= linear_c_nil; case: (linear_c fn) (valid_c fn c2 (next_lbl lbl)) => lbl2 lc2.
rewrite /next_lbl => - [L V].
move => fr_undef m1 vm1 P Q W1 M1 X1 D C1.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
exists m1 vm1; [ | | exact: W1 | exact: X1 | by [] | exact: M1 ]; last by [].
apply: LSem_step.
rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C1) /= /eval_instr /to_estate /li_i (eval_jumpE C1) /to_estate /= ok_e' /=.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite find_labelE /= -catA find_label_cat_hd; last first.
* apply: (valid_has_not_label V); left; rewrite /next_lbl; lia.
rewrite /= find_labelE /is_label /= eqxx /= /setcpc /= addn0.
by rewrite size_cat /= size_cat /= -addn1 -addnA.
+ rewrite linear_c_nil.
case: (linear_c fn) (Hc1 fn (next_lbl lbl)) => lbl1 lc1.
rewrite /checked_c ok_fd chk_c1 => /(_ erefl) S.
move => fr_undef m1 vm1 P Q W1 M1 X1 D C1.
set P' := rcons P (MkLI ii (Lcond (snot e) lbl)).
have D' : disjoint_labels (next_lbl lbl) lbl1 P'.
- rewrite /P' -cats1; apply: disjoint_labels_cat; last by [].
apply: disjoint_labels_wL _ D; rewrite /next_lbl; lia.
set Q' := MkLI ii (Llabel lbl) :: Q.
have C' : is_linear_of fn (P' ++ lc1 ++ Q').
- by move: C1; rewrite /P' /Q' -cats1 /= -!catA.
have {S} [ m2 vm2 E K2 W2 X2 H2 M2 ] := S m1 vm1 P' Q' W1 M1 X1 D' C'.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
have K2' := vmap_eq_exceptI (@SvP.MP.union_subset_1 _ _) K2.
exists m2 vm2; [ | exact: K2' | exact: W2 | exact: X2 | exact: H2 | exact: M2 ].
apply: lsem_step; last apply: lsem_trans.
2: exact: E.
- by rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C1) /= /eval_instr /li_i (eval_jumpE C1) /to_estate /= (snot_spec ok_e') /= ok_e' /= /setpc /= addn0 /P' /Q' size_rcons.
apply: LSem_step.
rewrite catA in C'.
rewrite /lsem1 /step -(addn0 (size (P' ++ lc1))) (find_instr_skip C') /= /eval_instr /= /setpc /=.
by rewrite /P' /Q' -cats1 -!catA !size_cat addn0 /= size_cat /= !addnS addn0.
rewrite linear_c_nil.
case: (linear_c fn) (valid_c fn (i1 :: c1) (next_lbl (next_lbl lbl))) (Hc1 fn (next_lbl (next_lbl lbl))) => lbl1 lc1.
rewrite /next_lbl => -[L V].
rewrite /checked_c ok_fd chk_c1 => /(_ erefl) E.
rewrite linear_c_nil.
case: (linear_c fn) (valid_c fn (i2 :: c2) lbl1) => lbl2 lc2 [L2 V2].
move => fr_undef m1 vm1 P Q W1 M1 X1 D C.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
set P' := P ++ {| li_ii := ii; li_i := Lcond e lbl |} :: lc2 ++ [:: {| li_ii := ii; li_i := Lgoto (fn, (lbl + 1)%positive) |}; {| li_ii := ii; li_i := Llabel lbl |} ].
have D' : disjoint_labels (lbl + 1 + 1) lbl1 P'.
+ apply: disjoint_labels_cat; first by apply: disjoint_labels_w _ _ D; lia.
apply: disjoint_labels_cat; first by apply: (valid_disjoint_labels V2); lia.
move => lbl' [A B]; rewrite /= orbF /is_label /=; apply/eqP => ?; subst lbl'; lia.
set Q' := {| li_ii := ii; li_i := Llabel (lbl + 1) |} :: Q.
have C' : is_linear_of fn (P' ++ lc1 ++ Q').
+ by move: C; rewrite /P' /Q' /= -!catA /= -!catA.
have {E} [ m2 vm2 E K2 W2 X2 H2 M2 ] := E m1 vm1 P' Q' W1 M1 X1 D' C'.
have K2' := vmap_eq_exceptI (@SvP.MP.union_subset_1 _ _) K2.
exists m2 vm2; [ | exact: K2' | exact: W2 | exact: X2 | exact: H2 | exact: M2 ].
apply: lsem_step; last apply: lsem_trans.
2: exact: E.
- rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE C) /to_estate /= ok_e' /=.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite find_labelE /= -catA find_label_cat_hd; last first.
* apply: (valid_has_not_label V2); lia.
by rewrite /= find_labelE /= find_labelE /is_label /= eqxx /= /setcpc /= /P' /Q' size_cat /= size_cat /= !addnS.
apply: LSem_step.
rewrite catA in C'.
rewrite /lsem1 /step -(addn0 (size (P' ++ lc1))) (find_instr_skip C') /= /eval_instr /= /setpc /=.
by rewrite /P' /Q' -!catA /= -!catA; repeat rewrite !size_cat /=; rewrite !addnS !addn0.
Qed.
Local Lemma Hif_false : sem_Ind_if_false p extra_free_registers var_tmp Pc Pi_r.
Proof.
move => ii k s1 s2 e c1 c2; rewrite p_globs_nil => ok_e E2 Hc2 fn lbl /checked_iE[] fd ok_fd /=; apply: rbindP => -[] _ chk_c2.
case: c1 => [ | i1 c1 ]; last case: c2 E2 Hc2 chk_c2 => [ | i2 c2 ].
+ rewrite linear_c_nil.
case: (linear_c fn) (Hc2 fn (next_lbl lbl)) => lbl2 lc2.
rewrite /checked_c ok_fd chk_c2 => /(_ erefl) S.
move => fr_undef m1 vm1 P Q W1 M1 X1 D C.
set P' := rcons P (MkLI ii (Lcond e lbl)).
have D' : disjoint_labels (next_lbl lbl) lbl2 P'.
- rewrite /P' -cats1; apply: disjoint_labels_cat; last by [].
apply: disjoint_labels_wL _ D; rewrite /next_lbl; lia.
set Q' := MkLI ii (Llabel lbl) :: Q.
have C' : is_linear_of fn (P' ++ lc2 ++ Q').
- by move: C; rewrite /P' /Q' -cats1 /= -!catA.
have {S} [ m2 vm2 E K2 W2 X2 H2 M2 ] := S m1 vm1 P' Q' W1 M1 X1 D' C'.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
have K2' := vmap_eq_exceptI (@SvP.MP.union_subset_1 _ _) K2.
exists m2 vm2; [ | exact: K2' | exact: W2 | exact: X2 | exact: H2 | exact: M2 ].
apply: lsem_step; last apply: lsem_trans.
2: exact: E.
- by rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE C) /to_estate /= ok_e' /= /setpc /= addn0 /P' /Q' size_rcons.
apply: LSem_step.
rewrite catA in C'.
rewrite /lsem1 /step -(addn0 (size (P' ++ lc2))) (find_instr_skip C') /= /eval_instr /= /setpc /=.
by rewrite /P' /Q' -cats1 -!catA !size_cat addn0 /= size_cat /= !addnS addn0.
+ case/semE => hk ? _ _; subst s2.
rewrite linear_c_nil; case: (linear_c fn) (valid_c fn (i1 :: c1) (next_lbl lbl)) => lbl1 lc1.
rewrite /next_lbl => - [L V].
move => fr_undef m1 vm1 P Q W1 M1 X1 D C.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
exists m1 vm1; [ | | exact: W1 | exact: X1 | by [] | exact: M1 ]; last by [].
apply: LSem_step.
rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE C) /to_estate /= (snot_spec ok_e') /= ok_e' /=.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite find_labelE /= -catA find_label_cat_hd; last first.
- apply: (valid_has_not_label V); left; rewrite /next_lbl; lia.
rewrite /= find_labelE /is_label /= eqxx /= /setcpc /= addn0.
by rewrite size_cat /= size_cat /= -addn1 -addnA.
rewrite linear_c_nil => _ Hc2 chk_c2.
case: (linear_c fn) (valid_c fn (i1 :: c1) (next_lbl (next_lbl lbl))) => lbl1 lc1.
rewrite /next_lbl => -[L V].
rewrite linear_c_nil.
case: (linear_c fn) (valid_c fn (i2 :: c2) lbl1) (Hc2 fn lbl1) => lbl2 lc2 [L2 V2].
rewrite /checked_c ok_fd chk_c2 => /(_ erefl) E.
move => fr_undef m1 vm1 P Q W1 M1 X1 D C.
have [ b /(match_mem_sem_pexpr M1) ok_e' /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
set P' := rcons P {| li_ii := ii; li_i := Lcond e lbl |}.
have D' : disjoint_labels lbl1 lbl2 P'.
+ rewrite /P' -cats1; apply: disjoint_labels_cat; last by [].
apply: disjoint_labels_wL _ D; lia.
set Q' := {| li_ii := ii; li_i := Lgoto (fn, (lbl + 1)%positive) |} :: {| li_ii := ii; li_i := Llabel lbl |} :: lc1 ++ [:: {| li_ii := ii; li_i := Llabel (lbl + 1) |}].
have C' : is_linear_of fn (P' ++ lc2 ++ Q' ++ Q).
+ by move: C; rewrite /P' /Q' /= -cats1 /= -!catA /= -!catA.
have {E} [ m2 vm2 E K2 W2 X2 H2 M2 ] := E m1 vm1 P' (Q' ++ Q) W1 M1 X1 D' C'.
have K2' := vmap_eq_exceptI (@SvP.MP.union_subset_1 _ _) K2.
exists m2 vm2; [ | exact: K2' | exact: W2 | exact: X2 | exact: H2 | exact: M2 ].
apply: lsem_step; last apply: lsem_trans.
2: exact: E.
+ rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE C) /to_estate /= ok_e' /= /setpc /=.
by rewrite /P' /Q' /= size_rcons addn0.
apply: LSem_step.
rewrite catA in C'.
rewrite /lsem1 /step -(addn0 (size (P' ++ lc2))) (find_instr_skip C') /= /eval_instr /li_i (eval_jumpE C') /= /setcpc /=.
rewrite /P' -cats1.
rewrite -!catA find_label_cat_hd; last by apply: D; lia.
rewrite find_labelE /= find_label_cat_hd; last by apply: (valid_has_not_label V2); lia.
rewrite find_labelE /= find_labelE /is_label /= next_lbl_neq find_label_cat_hd; last by apply: (valid_has_not_label V); lia.
by rewrite find_labelE /is_label /= eqxx /= /setcpc /Q' !size_cat /= size_cat /= size_cat /= !addnS !addnA.
Qed.
(* Inversion lemmas about lsem: can skip align and label instructions *)
Lemma lsem_skip_align m vm fn P m' vm' n ii a Q :
is_linear_of fn (P ++ add_align ii a [::] ++ Q) →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := size P |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size (P ++ add_align ii a [::]) + n |} →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := size (P ++ add_align ii a [::]) |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size (P ++ add_align ii a [::]) + n |}.
Proof.
case: a; last by rewrite cats0.
move => C /lsem_split_start[].
- rewrite size_cat => - [] _ _ K; exfalso; move: K; clear.
rewrite /addn /addn_rec; lia.
case => s h E; apply: lsem_trans E.
move: C h; rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= /setpc => /ok_inj <-{s} /=.
rewrite size_cat /= addn1.
exact: rt_refl.
Qed.
Lemma lsem_skip_label m vm fn P m' vm' n ii lbl Q :
is_linear_of fn (P ++ [:: {| li_ii := ii ; li_i := Llabel lbl |} ] ++ Q) →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := size P |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size P + n.+1 |} →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := (size P).+1 |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size P + n.+1 |}.
Proof.
move => C /lsem_split_start[].
- case => _ _ K; exfalso; move: K; clear.
rewrite /addn /addn_rec; lia.
case => s h E; apply: lsem_trans E.
move: C h; rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= /setpc => /ok_inj <-{s} /=.
exact: rt_refl.
Qed.
Lemma lsem_skip_goto m vm fn P m' vm' n ii jj lbl Q R :
is_linear_of fn (P ++ [:: {| li_ii := ii ; li_i := Lgoto (fn, lbl) |} ] ++ Q ++ [:: {| li_ii := jj ; li_i := Llabel lbl |} ] ++ R ) →
~~ has (is_label lbl) P →
~~ has (is_label lbl) Q →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := size P |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size P + n.+1 |} →
lsem p' mov_eop {| lmem := m ; lvm := vm ; lfn := fn ; lpc := (size P + size Q).+2 |} {| lmem := m' ; lvm := vm' ; lfn := fn ; lpc := size P + n.+1 |}.
Proof.
move => C Dp Dq /lsem_split_start[].
- case => _ _ K; exfalso; move: K; clear.
rewrite /addn /addn_rec; lia.
case => s h E; apply: lsem_trans E.
move: (C) h; rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /=.
case: C => fd -> -> /=.
rewrite find_label_cat_hd; last exact: Dp.
rewrite find_labelE /= find_label_cat_hd; last exact: Dq.
rewrite find_labelE /is_label /= eqxx /setcpc /= addn0 addnS => /ok_inj <-{s} /=.
exact: rt_refl.
Qed.
Local Lemma Hwhile_true : sem_Ind_while_true p extra_free_registers var_tmp Pc Pi Pi_r.
Proof.
red. clear Pfun.
move => ii k k' krec s1 s2 s3 s4 a c e c' Ec Hc ok_e Ec' Hc' Ew Hw.
move => fn lbl /checked_iE[] fd ok_fd /=.
set ι := λ i, {| li_ii := ii ; li_i := i |}.
have {Hw} := Hw fn lbl.
rewrite /checked_i ok_fd /=.
case: eqP.
- by move => ?; subst e.
t_xrbindP => e_neq_false Hw [] ok_c ok_c'.
move: Hw.
rewrite ok_c ok_c' => /(_ erefl).
move: ok_e Ew e_neq_false.
rewrite p_globs_nil.
case: is_boolP.
{ (* expression is the “true” literal *)
(* The context is inconsistent, but well, do the proof nonetheless *)
case => // _ Ew _.
rewrite linear_c_nil.
move: {Hc'} (Hc' fn (next_lbl lbl)).
rewrite /checked_c ok_fd ok_c' => /(_ erefl).
case: (linear_c fn c' (next_lbl lbl) [::]) (valid_c fn c' (next_lbl lbl)) => lblc' lc'.
rewrite /next_lbl => - [L' V'] Hc'.
rewrite linear_c_nil.
move: {Hc} (Hc fn lblc').
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c lblc' [::]) (valid_c fn c lblc') => lblc lc [L V] Hc /= Hw _.
rewrite add_align_nil.
move => m vm P Q W M X D C.
have {Hc} := Hc m vm (P ++ add_align ii a [::] ++ [:: ι (Llabel lbl) ]) (lc' ++ [:: ι (Lgoto (fn, lbl)) ] ++ Q) W M X.
case.
- apply: disjoint_labels_cat; last apply: disjoint_labels_cat.
+ apply: disjoint_labels_wL D; lia.
+ by case: (a).
move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
- by move: C; rewrite -!/(ι _) /= -!catA /= -!catA cat1s.
move => m1 vm1 E1 K1 W1 X1 H1 M1.
have {Hc'} := Hc' m1 vm1 ((P ++ add_align ii a [::] ++ [:: ι (Llabel lbl) ]) ++ lc) ([:: ι (Lgoto (fn, lbl)) ] ++ Q) W1 M1 X1.
case.
- repeat apply: disjoint_labels_cat.
+ apply: disjoint_labels_w D; lia.
+ by case: (a).
+ move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
apply: (valid_disjoint_labels V); left; lia.
- by move: C; rewrite /= -!catA /= -!catA.
move => m2 vm2 E2 K2 W2 X2 H2 M2.
have {Hw} := Hw m2 vm2 P Q W2 M2 X2 D.
case.
- by rewrite add_align_nil.
move => m3 vm3 E3 K3 W3 X3 H3 M3.
exists m3 vm3; [ | | exact: W3 | exact: X3 | | exact: M3 ]; cycle 1.
- transitivity vm2; last (apply: vmap_eq_exceptI K3; SvD.fsetdec).
transitivity vm1; last (apply: vmap_eq_exceptI K2; SvD.fsetdec).
apply: vmap_eq_exceptI K1; SvD.fsetdec.
- etransitivity; first exact: H1.
apply: preserved_metadataE; last (etransitivity; first exact: H2); last first.
+ apply: preserved_metadataE; last exact: H3.
* exact: sem_stack_stable Ec'.
exact: sem_validw_stable Ec'.
+ exact: sem_validw_stable Ec.
exact: sem_stack_stable Ec.
apply: lsem_trans; last apply: (lsem_trans E1); last apply: (lsem_trans E2).
- (* align; label *)
apply: (@lsem_step_end _ _ _ p' _ {| lfn := fn; lpc := size (P ++ add_align ii a [::]) |}); last first.
+ move: C.
rewrite -!catA catA -{1}(addn0 (size _)) /lsem1 /step => /find_instr_skip ->.
rewrite /eval_instr /= /setpc /= addn0 !size_cat addnA addn1.
reflexivity.
case: a C {Ew E1 E2 E3} => C; last first.
+ rewrite cats0; exact: rt_refl.
apply: LSem_step.
move: C.
rewrite -catA /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
by rewrite /eval_instr /= /setpc /= size_cat /= addn1.
apply: lsem_step.
- move: (C).
rewrite -cat1s !catA -catA.
rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= (get_fundef_p' ok_fd) /= /setcpc /=.
case: C; rewrite (get_fundef_p' ok_fd) => _ /Some_inj <- /= ->.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite -!catA find_label_cat_hd; last by case: (a).
rewrite find_labelE /= /is_label /= eqxx /= addn0.
reflexivity.
rewrite add_align_nil catA size_cat in E3.
rewrite -!catA in C.
have {} E3 := lsem_skip_align C E3.
rewrite !catA -cat1s -!catA catA in C.
have := lsem_skip_label C E3.
rewrite -/(size _) !size_cat /= !size_cat /= !addnA.
exact.
}
(* arbitrary expression *)
move => {} e ok_e Ew e_neq_false.
case: c' Ec' Hc' ok_c' Ew => [ | i c' ].
{ (* second body is empty *)
move => /semE[] ??; subst k' s2 => _ _ Ew.
rewrite linear_c_nil.
move: {Hc} (Hc fn (next_lbl lbl)).
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c (next_lbl lbl) [::]) (valid_c fn c (next_lbl lbl)) => lblc lc.
rewrite /next_lbl => - [L V] Hc /= Hw _.
rewrite add_align_nil.
move => m vm P Q W M X D C.
have {Hc} := Hc m vm (P ++ add_align ii a [::] ++ [:: ι (Llabel lbl) ]) ([:: ι (Lcond e lbl) ] ++ Q) W M X.
case.
- apply: disjoint_labels_cat; last apply: disjoint_labels_cat.
+ apply: disjoint_labels_wL D; rewrite /next_lbl; lia.
+ by case: (a).
rewrite /next_lbl => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
- by move: C; rewrite -!/(ι _) /= -!catA /= -!catA.
move => m1 vm1 E1 K1 W1 X1 H1 M1.
have [ b /(match_mem_sem_pexpr M1) {} ok_e /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
have {Hw} := Hw m1 vm1 P Q W1 M1 X1 D.
case.
- by rewrite add_align_nil.
move => m3 vm3 E3 K3 W3 X3 H3 M3.
exists m3 vm3; [ | | exact: W3 | exact: X3 | | exact: M3 ]; cycle 1.
- transitivity vm1; last (apply: vmap_eq_exceptI K3; SvD.fsetdec).
apply: vmap_eq_exceptI K1; SvD.fsetdec.
- etransitivity; first exact: H1.
apply: preserved_metadataE; last exact: H3.
+ exact: sem_stack_stable Ec.
exact: sem_validw_stable Ec.
apply: lsem_trans; last apply: (lsem_trans E1).
- (* align; label *)
apply: (@lsem_step_end _ _ _ p' _ {| lfn := fn; lpc := size (P ++ add_align ii a [::]) |}); last first.
+ move: C.
rewrite -!catA catA -{1}(addn0 (size _)) /lsem1 /step => /find_instr_skip ->.
rewrite /eval_instr /= /setpc /= addn0 !size_cat addnA addn1.
reflexivity.
case: a C {Ew E1 E3} => C; last first.
+ rewrite cats0; exact: rt_refl.
apply: LSem_step.
move: C.
rewrite -catA /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
by rewrite /eval_instr /= /setpc /= size_cat /= addn1.
apply: lsem_step.
- move: (C).
rewrite /lsem1 /step -{1}(addn0 (size _)) -cat1s !catA -catA => /find_instr_skip ->.
rewrite /eval_instr /= /to_estate ok_e /= (get_fundef_p' ok_fd) /=.
case: C; rewrite (get_fundef_p' ok_fd) => _ /Some_inj <- /= ->.
rewrite -!catA find_label_cat_hd; last by apply: D; lia.
rewrite find_label_cat_hd; last by case: (a).
rewrite find_labelE /= /is_label /= eqxx /= addn0 /setcpc /=.
reflexivity.
rewrite add_align_nil catA size_cat in E3.
rewrite -!catA in C.
have {} E3 := lsem_skip_align C E3.
rewrite !catA -cat1s -!catA catA in C.
have := lsem_skip_label C E3.
rewrite -/(size _) !size_cat /= !size_cat /= !addnA.
exact.
}
(* General case *)
clear Pi Pi_r => Ec' Hc' ok_c' Ew.
rewrite linear_c_nil.
move: {Hc} (Hc fn (next_lbl (next_lbl lbl))).
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c (next_lbl (next_lbl lbl)) [::]) (valid_c fn c (next_lbl (next_lbl lbl))) => lblc lc.
rewrite /next_lbl => - [L V] Hc.
rewrite linear_c_nil.
move: {Hc'} (Hc' fn lblc).
rewrite /checked_c ok_fd ok_c' => /(_ erefl).
case: (linear_c fn (i :: c') lblc [::]) (valid_c fn (i :: c') lblc) => lblc' lc' [L' V'] Hc' /= Hw _.
rewrite add_align_nil.
move => m vm P Q W M X D C.
have {Hc} := Hc m vm (P ++ ι (Lgoto (fn, lbl)) :: add_align ii a [::] ++ [:: ι (Llabel (lbl + 1)) ] ++ lc' ++ [:: ι (Llabel lbl) ]) ([:: ι (Lcond e (lbl + 1)) ] ++ Q) W M X.
case.
- apply: disjoint_labels_cat; last apply: disjoint_labels_cat.
+ apply: disjoint_labels_w D; lia.
+ by case: (a).
apply: disjoint_labels_cat; last apply: disjoint_labels_cat.
+ move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
+ apply: (valid_disjoint_labels V'); left; lia.
move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
- move: C; rewrite -!/(ι _) /= -!catA -!cat_cons -!catA -(cat1s _ lc) -(cat1s _ Q); exact.
move => m1 vm1 E1 K1 W1 X1 H1 M1.
have [ b /(match_mem_sem_pexpr M1) {} ok_e /value_uincl_bool1 ? ] := sem_pexpr_uincl X1 ok_e; subst b.
have {Hc'} := Hc' m1 vm1 (P ++ ι (Lgoto (fn, lbl)) :: add_align ii a [::] ++ [:: ι (Llabel (lbl + 1)) ]) (ι (Llabel lbl) :: lc ++ ι (Lcond e (lbl + 1)) :: Q) W1 M1 X1.
case.
- apply: disjoint_labels_cat; last apply: disjoint_labels_cat.
+ apply: disjoint_labels_wL D; lia.
+ by case: (a).
move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
- move: C; rewrite -!/(ι _) /= -!catA -!cat_cons -(cat1s _ Q) -(cat1s _ lc') -!catA; exact.
move => m2 vm2 E2 K2 W2 X2 H2 M2.
have {Hw} := Hw m2 vm2 P Q W2 M2 X2 D.
case.
- by rewrite add_align_nil.
move => m3 vm3 E3 K3 W3 X3 H3 M3.
exists m3 vm3; [ | | exact: W3 | exact: X3 | | exact: M3 ]; cycle 1.
- transitivity vm2; last (apply: vmap_eq_exceptI K3; SvD.fsetdec).
transitivity vm1; last (apply: vmap_eq_exceptI K2; SvD.fsetdec).
apply: vmap_eq_exceptI K1; SvD.fsetdec.
- etransitivity; first exact: H1.
apply: preserved_metadataE; last (etransitivity; first exact: H2); last first.
+ apply: preserved_metadataE; last exact: H3.
* exact: sem_stack_stable Ec'.
exact: sem_validw_stable Ec'.
+ exact: sem_validw_stable Ec.
exact: sem_stack_stable Ec.
apply: lsem_step; last apply: (lsem_trans E1).
- move: (C).
rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= (get_fundef_p' ok_fd) /=.
case: C; rewrite (get_fundef_p' ok_fd) => _ /Some_inj <- /= ->.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite -!catA find_labelE /= find_label_cat_hd; last by case: (a).
rewrite find_labelE /is_label /= eq_sym next_lbl_neq -!catA find_label_cat_hd; last first.
+ apply: (valid_has_not_label V'); left; lia.
rewrite find_labelE /= /is_label /= eqxx /= /setcpc /=.
by repeat rewrite size_cat /= !addnS.
apply: lsem_step; last apply: (lsem_trans E2).
- move: (C).
rewrite -!cat_cons !catA -(cat1s _ lc') -(cat1s _ lc) !catA -catA.
rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= (get_fundef_p' ok_fd) /=.
case: C; rewrite (get_fundef_p' ok_fd) => _ /Some_inj <- /= ->.
rewrite /to_estate ok_e /= /setcpc /=.
rewrite find_label_cat_hd; last by apply: D; lia.
rewrite -!catA find_labelE /= find_label_cat_hd; last by case: (a).
rewrite find_labelE /= /is_label /= eqxx /=.
by repeat rewrite size_cat /= !addnS.
apply: lsem_step.
- move: C.
rewrite -!cat_cons -(cat1s _ lc) -(cat1s _ lc') !catA -catA -catA -catA.
rewrite /lsem1 /step -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= /setpc /=.
reflexivity.
have {} C : is_linear_of fn (P ++ [:: ι (Lgoto (fn, lbl)) ] ++ (add_align ii a [::] ++ ι (Llabel (lbl + 1)) :: lc') ++ [:: ι (Llabel lbl)] ++ lc ++ ι (Lcond e (lbl + 1)) :: Q).
- move: C; clear.
rewrite -!cat_cons -!catA -(cat1s _ (add_align _ _ _)) -(cat1s _ lc) -(cat1s _ Q) -!catA.
exact.
rewrite size_cat add_align_nil in E3.
have := lsem_skip_goto C _ _ E3.
rewrite -/(size _); repeat rewrite size_cat /=.
rewrite !addnA !addnS !addn0 addSn.
apply.
- apply: D; lia.
have h : (lbl < lblc)%positive by lia.
have := @valid_has_not_label _ _ _ _ lbl V' (or_introl h).
rewrite has_cat /is_label /= eq_sym next_lbl_neq negb_or => ->.
by case: (a).
Qed.
Local Lemma Hwhile_false : sem_Ind_while_false p extra_free_registers var_tmp Pc Pi_r.
Proof.
move => ii k s1 s2 a c e c' Ec Hc; rewrite p_globs_nil => ok_e fn lbl /checked_iE[] fd ok_fd /=.
case: eqP.
{ (* expression is the “false” literal *)
move => ?; subst e.
move => ok_c /=.
move: {Hc} (Hc fn lbl).
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c lbl [::]) => lblc lc.
move => Hc _.
move => m vm P Q W M X D C.
have {Hc} [ m' vm' E K W' X' H' M' ] := Hc m vm P Q W M X D C.
exists m' vm'; [ exact: E | | exact: W' | exact: X' | exact: H' | exact: M' ].
apply: vmap_eq_exceptI K; SvD.fsetdec.
}
(* arbitrary expression *)
t_xrbindP => e_not_trivial [] ok_c ok_c'.
replace (is_bool e) with (@None bool);
last by case: is_boolP ok_e e_not_trivial => // - [].
case: c' ok_c' => [ | i c' ] ok_c'.
{ (* second body is empty *)
rewrite linear_c_nil.
move: {Hc} (Hc fn (next_lbl lbl)).
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c (next_lbl lbl) [::]) => lblc lc.
move => Hc _.
rewrite /= add_align_nil.
move => m vm P Q W M X D.
rewrite -cat1s !catA.
set prefix := (X in X ++ lc).
do 2 rewrite -catA.
set suffix := (X in lc ++ X).
move => C.
have {Hc} [ | m' vm' E K W' X' H' M' ] := Hc m vm prefix suffix W M X _ C.
- apply: disjoint_labels_cat; first apply: disjoint_labels_cat.
+ apply: disjoint_labels_wL _ D; rewrite /next_lbl; lia.
+ by case: (a).
clear.
rewrite /next_lbl => lbl' range.
rewrite /is_label /= orbF; apply/eqP; lia.
have [ ] := sem_pexpr_uincl X' ok_e.
case => // - [] // /(match_mem_sem_pexpr M') {} ok_e _.
exists m' vm'; [ | | exact: W' | exact: X' | exact: H' | exact: M' ]; last first.
- apply: vmap_eq_exceptI K; SvD.fsetdec.
apply: lsem_trans; last apply: (lsem_trans E).
- apply: (@lsem_trans _ _ _ _ _ {| lmem := m ; lvm := vm ; lfn := fn ; lpc := size (P ++ add_align ii a [::]) |}).
+ subst prefix; case: a C {E} => C; last by rewrite cats0; exact: rt_refl.
apply: LSem_step.
move: C.
rewrite /lsem1 /step -!catA -(addn0 (size _)) => /find_instr_skip ->.
by rewrite /eval_instr /= size_cat addn0 addn1.
apply: LSem_step.
move: C.
rewrite /lsem1 /step -catA -(addn0 (size _)) => /find_instr_skip ->.
by rewrite /eval_instr /= (size_cat _ [:: _]) addn0 addn1.
apply: LSem_step.
move: C.
rewrite /lsem1 /step catA -(addn0 (size _)) => /find_instr_skip ->.
by rewrite /eval_instr /= /to_estate /= ok_e /= (size_cat _ [:: _]) addn0 addn1.
}
(* general case *)
rewrite linear_c_nil.
move: {Hc} (Hc fn (next_lbl (next_lbl lbl))).
rewrite /checked_c ok_fd ok_c => /(_ erefl).
case: (linear_c fn c (next_lbl (next_lbl lbl)) [::]) (valid_c fn c (next_lbl (next_lbl lbl))) => lblc lc.
rewrite /next_lbl => -[L V] Hc _.
rewrite linear_c_nil.
case: (linear_c fn (i :: c') lblc [::]) (valid_c fn (i :: c') lblc) => lblc' lc' [L' V'].
rewrite /= add_align_nil.
move => m vm P Q W M X D.
rewrite -cat1s -(cat1s _ (lc' ++ _)) -(cat1s _ (lc ++ _)) !catA.
set prefix := (X in X ++ lc).
do 2 rewrite -catA.
set suffix := (X in lc ++ X).
move => C.
have {Hc} [ | m' vm' E K W' X' H' M' ] := Hc m vm prefix suffix W M X _ C.
- subst prefix; move: L' V' D; clear.
rewrite /next_lbl => L' V' D.
repeat apply: disjoint_labels_cat; try by [].
+ apply: disjoint_labels_w _ D; lia.
+ by case: (a).
+ move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
+ apply: (valid_disjoint_labels V'); left; lia.
move => lbl' range; rewrite /is_label /= orbF; apply/eqP; lia.
have [ ] := sem_pexpr_uincl X' ok_e.
case => // - [] // /(match_mem_sem_pexpr M') {} ok_e _.
exists m' vm'; [ | | exact: W' | exact: X' | exact: H' | exact: M' ]; last first.
- apply: vmap_eq_exceptI K; SvD.fsetdec.
apply: lsem_trans; last apply: (lsem_trans E).
- (* goto *)
apply: LSem_step.
move: (C).
rewrite /lsem1 /step -!catA -{1}(addn0 (size _)) => /find_instr_skip ->.
rewrite /eval_instr /= (get_fundef_p' ok_fd) /=.
case: C; rewrite (get_fundef_p' ok_fd) => _ /Some_inj <- /= ->.
rewrite -!catA find_label_cat_hd; last by apply: D; lia.
rewrite find_labelE /= find_label_cat_hd; last by case: (a).
rewrite find_labelE /is_label /= eq_sym next_lbl_neq.
rewrite find_label_cat_hd; last by apply: (valid_has_not_label V'); lia.
rewrite find_labelE /is_label /= eqxx /= /setcpc /=.
by rewrite !size_cat /= !addnS !addn0 !addnA !addSn.
(* cond false *)
apply: LSem_step.
move: (C).
rewrite /lsem1 /step -(addn0 (size _)) catA => /find_instr_skip ->.
rewrite /eval_instr /= ok_e /=.
by rewrite !size_cat /= !size_cat /= !addnS !addnA !addn0 !addSn.
Qed.
Lemma find_entry_label fn fd :
sf_return_address (f_extra fd) ≠ RAnone →
find_label xH (lfd_body (linear_fd p extra_free_registers lparams fn fd)) = ok 0.
Proof. by rewrite /linear_fd /linear_body; case: sf_return_address. Qed.
Local Lemma Hcall : sem_Ind_call p extra_free_registers var_tmp Pi_r Pfun.
Proof.
move => ii k s1 s2 ini res fn' args xargs xres ok_xargs ok_xres exec_call ih fn lbl /checked_iE[] fd ok_fd chk_call.
case linear_eq: linear_i => [lbli li].
move => fr_undef m1 vm2 P Q W M X D C.
move: chk_call => /=.
apply rbindP => _ /assertP /negbTE fn'_neq_fn.
case ok_fd': (get_fundef _ fn') => [ fd' | ] //; t_xrbindP => _ /assertP ok_ra _ /assertP ok_align _.
have := get_fundef_p' ok_fd'.
set lfd' := linear_fd _ _ _ _ fd'.
move => ok_lfd'.
move: linear_eq; rewrite /= ok_fd' fn'_neq_fn.
move: (checked_prog ok_fd') => /=; rewrite /check_fd.
t_xrbindP => -[] chk_body [] ok_to_save _ /assertP ok_stk_sz _ /assertP ok_ret_addr _ /assertP ok_save_stack _.
have ok_body' : is_linear_of fn' (lfd_body lfd').
- by rewrite /is_linear_of; eauto.
move: ih; rewrite /Pfun; move => /(_ _ _ _ _ _ _ _ _ _ _ ok_body') ih A.
have lbl_valid : (fn, lbl) \in (label_in_lprog p').
- clear -A C ok_ra hlparams.
apply: (label_in_lfundef _ C).
case: sf_return_address A ok_ra => [ | ra | z ] //=.
2: case: extra_free_registers => // ra.
1-2: by case => _ <- _; rewrite /label_in_lcmd !pmap_cat /= !mem_cat inE eqxx !orbT.
assert (h := encode_label_dom lbl_valid).
case ok_ptr: encode_label h => [ ptr | // ] _.
case/sem_callE: (exec_call) => ? m s' k' args' res'; rewrite ok_fd' => /Some_inj <- ra_sem ok_ss sp_aligned T ok_m ok_args' wt_args' exec_cbody ok_res' wt_res' T' s2_eq.
rewrite /ra_valid in ra_sem.
rewrite /top_stack_aligned in sp_aligned.
rewrite /ra_vm.
case ra_eq: (sf_return_address _) ok_ra ok_ret_addr ra_sem sp_aligned A => [ // | ra | z ] ok_ra ok_ret_addr ra_sem sp_aligned /=.
{ (* Internal function, return address in register [ra]. *)
have ok_ra_of : is_ra_of fn' (RAreg ra) by rewrite /is_ra_of; exists fd'; assumption.
have empty_callee_saved : is_callee_saved_of fn' [::]
by rewrite /is_callee_saved_of; exists fd'; last rewrite ra_eq.
move: ih => /(_ _ _ _ _ _ _ _ _ _ ok_ra_of _ _ empty_callee_saved) ih.
case => ? ?; subst lbli li.
case/andP: ra_sem => ra_neq_GD /andP[] ra_neq_RSP ra_not_written.
move: C; rewrite /allocate_stack_frame; case: eqP => stack_size /= C.
{ (* Nothing to allocate *)
set vm := vm2.[ra <- pof_val (vtype ra) (Vword ptr)]%vmap.
have {W} W : wf_vm vm.
+ rewrite /vm => x; rewrite Fv.setP; case: eqP => ?; last exact: W.
by subst; move/eqP: ok_ret_addr => ->.
move: C.
set P' := P ++ _.
move => C.
have RA : value_of_ra m1 vm (RAreg ra) (Some ((fn, lbl), P', (size P).+2)).
+ rewrite /vm.
case: (ra) ok_ret_addr => /= ? vra /eqP ->; rewrite eq_refl; split.
* exact: C.
* rewrite /P' find_label_cat_hd; last by apply: D; rewrite /next_lbl; Psatz.lia.
by rewrite /find_label /is_label /= eqxx /= addn2.
exists ptr; first exact: ok_ptr.
rewrite /pof_val to_pword_u zero_extend_u.
by rewrite Fv.setP_eq /=.
move: ih => /(_ _ vm _ _ W M _ RA) ih.
have XX : vm_uincl (kill_var ra s1).[vrsp <- ok (pword_of_word (top_stack (emem s1)))]%vmap vm.
+ move => x; rewrite /vm Fv.setP; case: eqP.
* move => ?; subst x.
rewrite Fv.setP_neq //.
move: (X vrsp).
by rewrite T.
move => _; move: x.
apply: set_vm_uincl; first exact: X.
by move/eqP: ok_ret_addr => /= ->.
have SP : is_sp_for_call fn' s1 (top_stack (emem s1)).
+ exists fd'; first exact: ok_fd'.
move: sp_aligned.
by rewrite /= ra_eq stack_size GRing.subr0.
move: ih => /(_ _ XX SP erefl).
case => m' vm' exec_fn' K' W' /vmap_uincl_ex_empty X' H' M' ?; subst k.
eexists; first apply: lsem_step; only 2: apply: lsem_step.
+ rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) addn0 /=.
by apply (hlparams.(spec_mov_op)
{| emem := m1; evm := vm2; |}
_ _
ok_ret_addr
ok_ptr).
+ rewrite /lsem1 /step -addn1 (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE ok_body').
rewrite /lfd' find_entry_label; last by rewrite ra_eq.
by rewrite /setcpc /=.
+ rewrite size_cat addn3; exact: exec_fn'.
+ rewrite -K' /vm /saved_stack_vm => x x_notin_k.
rewrite Fv.setP_neq //.
apply/eqP; clear -x_notin_k.
SvD.fsetdec.
+ exact: W'.
+ move => x; move: (X' x); rewrite Fv.setP; case: eqP; last by [].
move => ?; subst => /=.
case: vm'.[_]%vmap => //=.
move => rsp /andP /= [] /cmp_le_antisym /(_ (pw_proof _)).
case: rsp => /= ? rsp u ?; subst => /eqP.
rewrite zero_extend_u => <- {rsp} /=.
have := sem_one_varmap_facts.sem_call_valid_RSP exec_call.
by rewrite /valid_RSP pword_of_wordE => ->.
+ exact: H'.
exact: M'.
}
(* Allocate a stack frame *)
move: (X vrsp).
rewrite T.
case vm2_rsp: vm2.[_]%vmap => [ top_ptr | // ] /= /pword_of_word_uincl[].
case: top_ptr vm2_rsp => ? ? le_refl vm2_rsp /= ? ?; subst.
set top := (top_stack (emem s1) - wrepr Uptr (stack_frame_allocation_size (f_extra fd')))%R.
set vm := vm2.[vrsp <- ok (pword_of_word top)].[ra <- pof_val (vtype ra) (Vword ptr)]%vmap.
have {W} W : wf_vm vm.
+ rewrite /vm => x; rewrite Fv.setP; case: eqP => x_ra.
* by subst; move/eqP: ok_ret_addr => ->.
rewrite Fv.setP; case: eqP => x_rsp; first by subst.
exact: W.
move: C.
set P' := P ++ _.
move => C.
have RA : value_of_ra m1 vm (RAreg ra) (Some ((fn, lbl), P', size P + 3)).
+ rewrite /vm.
case: (ra) ok_ret_addr => /= ? vra /eqP ->; rewrite eq_refl; split.
* exact: C.
* rewrite /P' find_label_cat_hd; last by apply: D; rewrite /next_lbl; Psatz.lia.
by rewrite /find_label /is_label /= eqxx /=.
exists ptr; first exact: ok_ptr.
rewrite /pof_val to_pword_u zero_extend_u.
by rewrite Fv.setP_eq /=.
move: ih => /(_ _ vm _ _ W M _ RA) ih.
have XX : vm_uincl (kill_var ra s1).[vrsp <- ok (pword_of_word top)]%vmap vm.
+ move => x; rewrite /vm Fv.setP; case: eqP => x_rsp.
* by subst; rewrite Fv.setP_neq // Fv.setP_eq.
rewrite !(@Fv.setP _ _ ra); case: eqP => x_ra.
* by subst; move/eqP: ok_ret_addr => ->.
rewrite Fv.setP_neq; last by apply/eqP.
exact: X.
have SP : is_sp_for_call fn' s1 top.
+ exists fd'; first exact: ok_fd'.
by rewrite /= ra_eq.
move: ih => /(_ _ XX SP erefl).
case => m' vm' exec_fn' K' W' /vmap_uincl_ex_empty X' H' M' ?; subst k.
exists m' vm'.[vrsp <- ok (pword_of_word (top_stack (emem s1)))]%vmap.
+ apply: lsem_step; last apply: lsem_step; last apply: lsem_step; last apply: lsem_step_end.
* rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) addn0 /=.
apply (hlparams.(spec_lp_free_stack_frame) p' (s:={|emem:=_; evm:=_|})).
by rewrite vm2_rsp pword_of_wordE.
* rewrite /lsem1 /step -addn1 (find_instr_skip C) addn1 /=.
by apply (hlparams.(spec_mov_op) {|emem:=_; evm:=_|} _ _ ok_ret_addr ok_ptr).
* rewrite /lsem1 /step -addn2 (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE ok_body').
rewrite /lfd' find_entry_label; last by rewrite ra_eq.
by rewrite /setcpc /=.
* exact: exec_fn'.
rewrite /lsem1 /step -addn1 -addnA (find_instr_skip C) /=.
rewrite size_cat /=.
move: (X' vrsp).
rewrite Fv.setP_eq /=.
case Hvm': vm'.[_]%vmap =>
//= [-[? ? le_refl']] /pword_of_word_uincl[] /= ??;
subst.
rewrite pword_of_wordE in Hvm'.
rewrite (@spec_lp_allocate_stack_frame
_
_
hlparams
_
{| emem := m'; evm := vm'; |}
_ _ _ _ _ _
Hvm').
rewrite /= /of_estate /with_vm /=.
rewrite -addn1 -addnA.
rewrite -GRing.addrA GRing.addNr GRing.addr0.
reflexivity.
+ move => x x_notin_k.
rewrite Fv.setP; case: eqP => x_neq_rsp.
* by subst; rewrite vm2_rsp pword_of_wordE.
rewrite -K' // /vm !Fv.setP_neq //; apply/eqP => //.
move: x_notin_k; clear.
rewrite !Sv.union_spec Sv.singleton_spec; intuition.
+ move => x; rewrite Fv.setP; case: eqP => ?; last exact: W'.
by subst.
+ have := sem_one_varmap_facts.sem_call_valid_RSP exec_call.
rewrite /= /valid_RSP /set_RSP => h x /=.
rewrite (Fv.setP vm'); case: eqP => x_rsp.
* by subst; rewrite h.
by move: (X' x); rewrite Fv.setP_neq //; apply/eqP.
+ exact: H'.
exact: M'.
}
(* Internal function, return address at offset [z]. *)
case fr_eq: extra_free_registers ok_ra fr_undef ok_ret_addr => [fr | //] _.
move=> [] fr_neq_RIP fr_neq_RSP fr_well_typed fr_undef /and4P[] z_pos /lezP z_bound sf_aligned_for_ptr z_aligned [] ? ?; subst lbli li.
have ok_ra_of : is_ra_of fn' (RAstack z) by rewrite /is_ra_of; exists fd'; assumption.
have empty_callee_saved : is_callee_saved_of fn' [::]
by rewrite /is_callee_saved_of; exists fd'; last rewrite ra_eq.
move: ih => /(_ _ _ _ _ _ _ _ _ _ ok_ra_of _ _ empty_callee_saved) ih.
move: (X vrsp).
rewrite T.
case vm2_rsp: vm2.[_]%vmap => [ top_ptr | // ] /= /pword_of_word_uincl[].
case: top_ptr vm2_rsp => ? ? le_refl vm2_rsp /= ? ?; subst.
rewrite /allocate_stack_frame.
case: ifP.
+ move => /eqP K; exfalso.
case/and3P: ok_stk_sz => /lezP A /lezP B _.
move: z_bound. move => /=.
move/lezP: z_pos.
have := round_ws_range (sf_align (f_extra fd')) (sf_stk_sz (f_extra fd') + sf_stk_extra_sz (f_extra fd')).
move: K A B; clear.
rewrite /stack_frame_allocation_size /=.
assert (h := wsize_size_pos reg_size).
by lia.
move => sz_nz k_eq.
have : (z + wsize_size Uptr <= stack_frame_allocation_size (f_extra fd'))%Z.
* etransitivity; first exact: z_bound.
exact: proj1 (round_ws_range _ _).
move => {z_bound} z_bound.
have : exists2 m1', write m1 (top_stack_after_alloc (top_stack (emem s1)) (sf_align (f_extra fd'))
(sf_stk_sz (f_extra fd') + sf_stk_extra_sz (f_extra fd')) + wrepr Uptr z)%R ptr = ok m1' &
match_mem s1 m1'.
+ apply: mm_write_invalid; first exact: M; last first.
* apply: is_align_add z_aligned.
apply: is_align_m; last exact: do_align_is_align.
exact: sf_aligned_for_ptr.
have := (Memory.alloc_stackP ok_m).(ass_above_limit).
rewrite (alloc_stack_top_stack ok_m).
rewrite top_stack_after_aligned_alloc // wrepr_opp.
move: ok_stk_sz z_pos z_bound; clear.
rewrite !zify -/(stack_frame_allocation_size (f_extra fd')) => - [] sz_pos [] extra_pos sz_noof z_pos z_bound.
set L := stack_limit (emem s1).
have L_range := wunsigned_range L.
move: (stack_frame_allocation_size _) z_bound sz_noof => S z_bound sz_noof.
move: (top_stack (emem s1)) => T above_limit.
have S_range : (0 <= S < wbase Uptr)%Z.
- by assert (h := wsize_size_pos Uptr); lia.
have X : (wunsigned (T - wrepr Uptr S) <= wunsigned T)%Z.
* move: (sf_stk_sz _) sz_pos above_limit => n; lia.
have {X} TmS := wunsigned_sub_small S_range X.
rewrite TmS in above_limit.
have T_range := wunsigned_range T.
by rewrite wunsigned_add TmS; assert (h:=wsize_size_pos Uptr); lia.
case => m1' ok_m1' M1'.
move: ih => /(_ _ _ _ _ _ M1') ih {fr_neq_RIP}.
case: fr fr_well_typed C fr_eq fr_neq_RSP fr_undef => ? fr /= -> C fr_eq fr_neq_RSP fr_undef.
set vm1' := vm2.[vrsp <- ok (pword_of_word (top_stack_after_alloc (top_stack (emem s1)) (sf_align (f_extra fd')) (sf_stk_sz (f_extra fd') + sf_stk_extra_sz (f_extra fd'))))].[ {| vtype := sword Uptr ; vname := fr |} <- ok (pword_of_word ptr)]%vmap.
have {W} W : wf_vm vm1'.
+ rewrite /vm1' => x; rewrite Fv.setP; case: eqP => ?; first by subst.
rewrite Fv.setP; case: eqP => ?; first by subst.
exact: W.
move: C.
rewrite /allocate_stack_frame sz_nz /=.
set body := P ++ _.
move => C.
set sp := top_stack_after_alloc (top_stack (emem s1)) (sf_align (f_extra fd')) (sf_stk_sz (f_extra fd') + sf_stk_extra_sz (f_extra fd')).
move/eqP: fr_neq_RSP => fr_neq_RSP.
have XX : vm_uincl s1.[vrsp <- ok (pword_of_word sp)] vm1'.
+ rewrite /vm1' => x; rewrite Fv.setP; case: eqP => x_rsp.
* by subst; rewrite Fv.setP_neq // Fv.setP_eq.
rewrite Fv.setP; case: eqP => x_fr.
* by subst; rewrite fr_undef.
by rewrite Fv.setP_neq //; apply/eqP.
move: ih => /(_ vm1' _ _ W XX).
have RA : value_of_ra m1' vm1' (RAstack z) (Some ((fn, lbl), body, size P + 4)).
+ split.
* exact: C.
* rewrite /body find_label_cat_hd; last by apply: D; rewrite /next_lbl; lia.
by do 5 rewrite find_labelE; rewrite /= /is_label /= eqxx.
exists ptr; first by [].
exists sp.
* by rewrite /vm1' Fv.setP_neq // Fv.setP_eq.
exact: writeP_eq ok_m1'.
move => /(_ _ RA).
have SP : is_sp_for_call fn' s1 sp.
+ exists fd'; first exact: ok_fd'.
rewrite /= ra_eq; split; first by [].
by rewrite /sp top_stack_after_aligned_alloc // wrepr_opp.
move => /(_ SP erefl) []m2' vm2' exec_fn' K' W' /vmap_uincl_ex_empty X' H' M'; subst k.
exists m2' (vm2'.[vrsp <- ok (pword_of_word (sp + wrepr Uptr (stack_frame_allocation_size (f_extra fd'))))])%vmap.
- apply: lsem_step; only 2: apply: lsem_step; only 3: apply: lsem_step; only 4: apply: lsem_step; only 5: apply: lsem_trans.
+ rewrite /lsem1 /step -(addn0 (size P)) (find_instr_skip C) /=.
have Hvm2 :
({| emem := m1; evm := vm2; |}.[vrsp])%vmap
= ok (pword_of_word (@top_stack _ mem _ _ s1)).
- by rewrite vm2_rsp pword_of_wordE.
rewrite (hlparams.(spec_lp_free_stack_frame) _ _ _ _ _ Hvm2).
rewrite /of_estate -addn1 -addnA add0n.
reflexivity.
+ rewrite /lsem1 /step (find_instr_skip C) /=.
rewrite (hlparams.(spec_mov_op) {| emem := m1; evm := _; |} _ _ _ ok_ptr); last done.
rewrite /pof_val /vtype to_pword_u.
rewrite addn1 -addn2.
rewrite -wrepr_opp -(@top_stack_after_aligned_alloc arch_pd); last by [].
reflexivity.
+ rewrite /lsem1 /step (find_instr_skip C) /=.
rewrite /lstore /lassign.
set ts' := top_stack_after_alloc _ _ _.
set x := Var _ p.(p_extra).(sp_rsp).
set r := Var _ fr.
set lx := Lmem _ _ _.
set e := Pvar _.
set ls := of_estate _ _ _.
have Hsem_pexpr : sem_pexpr [::] (to_estate ls) e = ok (Vword ptr).
* by rewrite /= /get_gvar /= /get_var Fv.setP_eq.
have Htruncate_word : truncate_word Uptr ptr = ok ptr.
* by rewrite truncate_word_u.
have Hwrite_lval :
write_lval [::] lx (Vword ptr) (to_estate ls)
= ok {|
emem := m1';
evm := (vm2
.[x <- ok (pword_of_word ts')]
.[r <- ok (pword_of_word ptr)]
)%vmap;
|}.
* rewrite /= /get_var Fv.setP_neq //.
rewrite Fv.setP_eq /= !truncate_word_u /=.
by rewrite ok_m1' /with_mem.
rewrite (spec_lassign hlparams
_ _ _ _
Hsem_pexpr
Htruncate_word
Hwrite_lval).
rewrite -addn1 -addnA.
reflexivity.
+ rewrite /lsem1 /step (find_instr_skip C) /= /eval_instr /li_i (eval_jumpE ok_body').
rewrite /lfd' find_entry_label; last by rewrite ra_eq.
by rewrite /setcpc /=.
+ exact: exec_fn'.
apply: LSem_step.
rewrite -addn1 -addnA /lsem1 /step (find_instr_skip C) /=.
rewrite size_cat /=.
have Hvm2 :
({| emem := m2'; evm := vm2'; |}.[vrsp])%vmap = ok (pword_of_word sp).
* rewrite /=.
move: (X' vrsp).
rewrite Fv.setP_eq /=.
case: vm2'.[_]%vmap =>
//= [-[?? le_refl']] /pword_of_word_uincl[] /= ??;
subst.
by rewrite pword_of_wordE.
rewrite (hlparams.(spec_lp_allocate_stack_frame) _ _ _ _ _ Hvm2) /=.
rewrite /= /of_estate /with_vm /=.
by rewrite -addn1 -addnA.
- move => x x_out.
rewrite Fv.setP; case: eqP => x_rsp.
+ by subst; rewrite vm2_rsp pword_of_wordE /sp top_stack_after_aligned_alloc // wrepr_opp GRing.subrK.
rewrite -K' // /vm1' !Fv.setP_neq //; apply/eqP => // ?; subst.
apply: x_out.
rewrite /extra_free_registers_at fr_eq; clear.
rewrite /Uptr /=.
SvD.fsetdec.
- move => x; rewrite Fv.setP; case: eqP => ?; last exact: W'.
by subst.
- rewrite /sp top_stack_after_aligned_alloc // wrepr_opp GRing.subrK.
move => x; rewrite Fv.setP; case: eqP => x_rsp.
+ subst.
by rewrite (ss_top_stack (sem_call_stack_stable exec_call)) s2_eq /= /set_RSP Fv.setP_eq.
by move: (X' x); rewrite Fv.setP_neq //; apply/eqP.
- etransitivity; last exact: H'.
have := alloc_stackP ok_m.
clear - ok_m ok_m1' ok_stk_sz z_pos z_bound sp_aligned => A a [] a_lo a_hi _.
have top_range := ass_above_limit A.
rewrite (CoreMem.writeP_neq ok_m1'); first reflexivity.
apply: disjoint_range_U8 => i i_range ? {ok_m1'}; subst a.
move: a_lo {a_hi}.
rewrite (top_stack_after_aligned_alloc _ sp_aligned) -/(stack_frame_allocation_size (f_extra fd')).
rewrite addE -!GRing.addrA.
replace (wrepr _ _ + _)%R with (- wrepr Uptr (stack_frame_allocation_size (f_extra fd') - z - i))%R; last first.
+ by rewrite !wrepr_add !wrepr_opp; ssring.
rewrite wunsigned_sub; first by lia.
assert (X := wunsigned_range (top_stack (emem s1))).
split; last by lia.
move: ok_stk_sz z_pos; rewrite !zify => /= ok_stk_sz sz_pos.
transitivity (wunsigned (top_stack (emem s1)) - (stack_frame_allocation_size (f_extra fd')))%Z;
last by rewrite /=; lia.
rewrite Z.le_0_sub.
apply: aligned_alloc_no_overflow.
1-2: lia.
+ by case: ok_stk_sz => _ [] _.
+ exact: sp_aligned.
exact: ok_m.
exact: M'.
Qed.
Lemma RSP_in_magic :
Sv.In vrsp (magic_variables p).
Proof. by rewrite Sv.add_spec Sv.singleton_spec; right. Qed.
Lemma push_to_save_has_no_label ii lbl m :
~~ has (is_label lbl) (push_to_save p lparams ii m).
Proof.
elim: m => // - [] x ofs m /= /negbTE ->.
by case: is_word_type.
Qed.
Lemma not_magic_neq_rsp x :
~~ Sv.mem x (magic_variables p) →
(x == vrsp) = false.
Proof.
rewrite /magic_variables => /Sv_memP ?; apply/eqP => ?; SvD.fsetdec.
Qed.
Lemma all_disjoint_aligned_betweenP (lo hi: Z) (al: wsize) A (m: seq A) (slot: A → cexec (Z * wsize)) :
all_disjoint_aligned_between lo hi al m slot = ok tt →
if m is a :: m' then
exists ofs ws,
[/\ slot a = ok (ofs, ws),
(lo <= ofs)%Z,
(ws ≤ al)%CMP,
is_align (wrepr Uptr ofs) ws &
all_disjoint_aligned_between (ofs + wsize_size ws) hi al m' slot = ok tt
]
else
(lo <= hi)%Z.
Proof.
case: m lo => [ | a m ] lo.
- by apply: rbindP => _ /ok_inj <- /assertP /lezP.
apply: rbindP => last /=.
apply: rbindP => mid.
case: (slot a) => // - [] ofs ws /=.
t_xrbindP => _ /assertP /lezP lo_le_ofs _ /assertP ok_ws _ /assertP aligned_ofs <-{mid} ih last_le_hi.
exists ofs, ws; split => //.
by rewrite /all_disjoint_aligned_between ih.
Qed.
Lemma all_disjoint_aligned_between_range (lo hi: Z) (al: wsize) A (m: seq A) (slot: A → cexec (Z * wsize)) :
all_disjoint_aligned_between lo hi al m slot = ok tt →
(lo <= hi)%Z.
Proof.
apply: rbindP => last h /assertP /lezP last_le_hi.
apply: Z.le_trans last_le_hi.
elim: m lo h.
- by move => ? /ok_inj ->; reflexivity.
move => a m ih lo /=; t_xrbindP => mid [] ofs x _; t_xrbindP => _ /assertP /lezP lo_le_ofs _ _ _ /assertP _ <-{mid} /ih.
have := wsize_size_pos x.
lia.
Qed.
(* Convenient weaker form of preserved-metatada *)
Lemma preserved_metadata_w m al sz sz' m' m1 m2:
alloc_stack m al sz sz' = ok m' →
(0 <= sz)%Z →
preserved_metadata m' m1 m2 →
∀ p,
(wunsigned (top_stack m') <= wunsigned p < wunsigned (top_stack m))%Z →
~~ validw m' p U8 → read m1 p U8 = read m2 p U8.
Proof.
move => ok_m' sz_pos M a [] a_lo a_hi; apply: M; split; first exact: a_lo.
have A := alloc_stackP ok_m'.
rewrite A.(ass_root).
apply: Z.lt_le_trans; first exact: a_hi.
exact: top_stack_below_root.
Qed.
Lemma stack_slot_in_bounds m al sz sz' m' ofs ws i :
alloc_stack m al sz sz' = ok m' →
(0 <= sz)%Z →
(0 <= sz')%Z →
(sz <= ofs)%Z →
(ofs + wsize_size ws <= sz + sz')%Z →
(0 <= i < wsize_size ws)%Z →
(wunsigned (top_stack m') + sz <= wunsigned (add (top_stack m' + wrepr Uptr ofs)%R i)
∧ wunsigned (add (top_stack m' + wrepr Uptr ofs)%R i) < wunsigned (top_stack m))%Z.
Proof.
move => ok_m' sz_pos sz'_pos ofs_lo ofs_hi i_range.
have A := alloc_stackP ok_m'.
have below_old_top : (wunsigned (top_stack m') + ofs + i < wunsigned (top_stack m))%Z.
- apply: Z.lt_le_trans; last exact: proj2 (ass_above_limit A).
rewrite -!Z.add_assoc -Z.add_lt_mono_l Z.max_r //.
have := wsize_size_pos ws.
lia.
have ofs_no_overflow : (0 <= wunsigned (top_stack m') + ofs)%Z ∧ (wunsigned (top_stack m') + ofs + i < wbase Uptr)%Z.
- split; first by generalize (wunsigned_range (top_stack m')); lia.
apply: Z.lt_trans; last exact: proj2 (wunsigned_range (top_stack m)).
exact: below_old_top.
rewrite !wunsigned_add; lia.
Qed.
Lemma mm_can_write_after_alloc m al sz sz' m' m1 ofs ws (v: word ws) :
alloc_stack m al sz sz' = ok m' →
(0 <= sz)%Z →
(0 <= sz')%Z →
(ws ≤ al)%CMP →
is_align (wrepr Uptr ofs) ws →
(sz <= ofs)%Z →
(ofs + wsize_size ws <= sz + sz')%Z →
match_mem m m1 →
∃ m2,
[/\
write m1 (top_stack m' + wrepr Uptr ofs)%R v = ok m2,
preserved_metadata m m1 m2 &
match_mem m m2
].
Proof.
move => ok_m' sz_pos extra_pos frame_aligned ofs_aligned ofs_lo ofs_hi M.
have A := alloc_stackP ok_m'.
have ofs_no_overflow : (0 <= wunsigned (top_stack m') + ofs)%Z ∧ (wunsigned (top_stack m') + ofs < wbase Uptr)%Z.
- split; first by generalize (wunsigned_range (top_stack m')); lia.
apply: Z.le_lt_trans; last exact: proj2 (wunsigned_range (top_stack m)).
apply: Z.le_trans; last exact: proj2 (ass_above_limit A).
rewrite -Z.add_assoc -Z.add_le_mono_l Z.max_r //.
have := wsize_size_pos ws.
lia.
have ofs_below : (wunsigned (top_stack m') + ofs + wsize_size ws <= wunsigned (top_stack m))%Z.
- apply: Z.le_trans; last exact: proj2 (ass_above_limit A).
by rewrite -!Z.add_assoc -Z.add_le_mono_l Z.max_r.
cut (exists2 m2, write m1 (top_stack m' + wrepr Uptr ofs)%R v = ok m2 & match_mem m m2).
- case => m2 ok_m2 M2; exists m2; split; [ exact: ok_m2 | | exact: M2 ].
move => a [] a_lo a_hi _.
rewrite (write_read8 ok_m2) /=.
case: andP; last by [].
case => _ /ltzP a_below; exfalso.
move: a_below.
rewrite subE wunsigned_add -/(wunsigned (_ + _)) wunsigned_add //; first lia.
split; last by generalize (wunsigned_range a); lia.
have := wsize_size_pos ws; lia.
apply: mm_write_invalid; first exact: M; last first.
- apply: is_align_add ofs_aligned.
apply: is_align_m; first exact: frame_aligned.
rewrite (alloc_stack_top_stack ok_m').
exact: do_align_is_align.
rewrite wunsigned_add; last exact: ofs_no_overflow.
split; last exact: ofs_below.
apply: Z.le_trans; first exact: proj1 (ass_above_limit A).
lia.
Qed.
Lemma pword_uincl ws (w: word ws) (z: pword ws) :
word_uincl w z.(pw_word) →
z = pword_of_word w.
Proof.
case: z => ws' w' ws'_le_ws /= /andP[] ws_le_ws' /eqP ->{w}.
have ? := cmp_le_antisym ws'_le_ws ws_le_ws'.
subst ws'.
by rewrite pword_of_wordE zero_extend_u.
Qed.
Lemma read_after_spill top al vm e m1 to_spill m2 lo hi :
(wunsigned top + hi < wbase Uptr)%Z →
(0 <= lo)%Z →
all_disjoint_aligned_between lo hi al to_spill
(λ '(x, ofs), if is_word_type x.(vtype) is Some ws then ok (ofs, ws) else (Error e)) = ok tt →
foldM (λ '(x, ofs) m,
Let: ws := if vtype x is sword ws then ok ws else Error ErrType in
Let: v := get_var vm x >>= to_word ws in
write m (top + wrepr Uptr ofs)%R v)
m1 to_spill = ok m2 →
[/\
∀ ofs ws, (0 <= ofs)%Z → (ofs + wsize_size ws <= lo)%Z → read m2 (top + wrepr Uptr ofs)%R ws = read m1 (top + wrepr Uptr ofs)%R ws
&
∀ x ofs, (x, ofs) \in to_spill → exists2 ws, is_word_type x.(vtype) = Some ws & exists2 v, get_var vm x >>= to_word ws = ok v & read m2 (top + wrepr Uptr ofs)%R ws = ok v
].
Proof.
move => no_overflow.
elim: to_spill m1 lo.
- by move => _ lo _ _ [->].
case => - [] xt x ofs to_spill ih m0 lo lo_pos /all_disjoint_aligned_betweenP[] y [] ws [] /=.
case: xt => // _ /ok_inj[] <-{y} -> lo_le_ofs ws_aligned ofs_aligned ok_to_spill.
have ofs_below_hi := all_disjoint_aligned_between_range ok_to_spill.
t_xrbindP => m1 _ <- w v ok_v ok_w ok_m1 rec.
have ws_pos := wsize_size_pos ws.
have lo'_pos : (0 <= ofs + wsize_size ws)%Z by lia.
have {ih} [ih1 ih2] := ih _ _ lo'_pos ok_to_spill rec.
split.
- move => i n i_pos i_n_le_lo.
rewrite ih1; only 2-3: lia.
have n_pos := wsize_size_pos n.
have [top_lo _] := wunsigned_range top.
rewrite (writeP_neq ok_m1) //; split; last right.
1-2: rewrite !zify.
1-3: rewrite !wunsigned_add; lia.
move => y ofs_y; rewrite inE; case: eqP.
- case => ->{y} ->{ofs_y} _ /=.
eexists; first reflexivity.
exists w; first by rewrite ok_v.
rewrite ih1; only 2-3: lia.
exact: (writeP_eq ok_m1).
by move => _ /ih2.
Qed.
Lemma Sv_diff_empty (s: Sv.t) :
Sv.Equal (Sv.diff s Sv.empty) s.
Proof. SvD.fsetdec. Qed.
Lemma wf_vm_eval_uincl_pundef vm z:
wf_vm vm -> eval_uincl (pundef_addr (vtype z)) (vm.[z])%vmap.
Proof.
move=> /(_ z); case: (vm.[z])%vmap => //.
+ by move=> ??; apply eval_uincl_undef.
by case => //; case: vtype.
Qed.
Lemma eval_uincl_kill_vars_incl X1 X2 vm1 vm2 z:
wf_vm vm2 ->
Sv.Subset X1 X2 ->
(eval_uincl (kill_vars X1 vm1).[z] vm2.[z] ->
eval_uincl (kill_vars X2 vm1).[z] vm2.[z])%vmap.
Proof.
move=> hwf S;
rewrite !kill_varsE; case:Sv_memP => hin1; case: Sv_memP => hin2 // _; first by SvD.fsetdec.
by apply wf_vm_eval_uincl_pundef.
Qed.
Lemma vm_uincl_kill_vars_set_incl X1 X2 vm1 vm2 x v1 v2:
wf_vm vm2 ->
Sv.Subset X1 X2 ->
eval_uincl v2 v1 ->
vm_uincl ((kill_vars X1 vm1).[x <- v1])%vmap vm2 ->
vm_uincl ((kill_vars X2 vm1).[x <- v2])%vmap vm2.
Proof.
move=> hwf S huv huvm z.
case: (x =P z) (huvm z) => [<- | /eqP ?].
+ by rewrite !Fv.setP_eq; apply: (eval_uincl_trans huv).
by rewrite !Fv.setP_neq //; apply eval_uincl_kill_vars_incl.
Qed.
Local Lemma Hproc : sem_Ind_proc p extra_free_registers var_tmp Pc Pfun.
Proof.
red => ii k s1 _ fn fd args m1' s2' res ok_fd free_ra ok_ss rsp_aligned valid_rsp ok_m1' ok_args wt_args exec_body ih ok_res wt_res valid_rsp' -> m1 vm1 _ ra lret sp callee_saved W M X [] fd' ok_fd' <- [].
rewrite ok_fd => _ /Some_inj <- ?; subst ra.
rewrite /value_of_ra => ok_lret.
case; rewrite ok_fd => _ /Some_inj <- /= ok_sp.
case; rewrite ok_fd => _ /Some_inj <- /= ok_callee_saved.
move: (checked_prog ok_fd); rewrite /check_fd /=.
t_xrbindP => - [] chk_body [] ok_to_save _ /assertP ok_stk_sz _ /assertP ok_ret_addr _ /assertP ok_save_stack _.
have ? : fd' = linear_fd p extra_free_registers lparams fn fd.
- have := get_fundef_p' ok_fd.
by rewrite ok_fd' => /Some_inj.
subst fd'.
move: ok_fd'; rewrite /linear_fd /linear_body /=.
rewrite /ra_valid in free_ra.
rewrite /check_to_save in ok_to_save.
rewrite /ra_undef_vm in exec_body.
rewrite /ra_undef_vm in ih.
rewrite /saved_stack_valid in ok_ss.
rewrite /ra_vm.
rewrite /saved_stack_vm.
case EQ: sf_return_address free_ra ok_to_save ok_callee_saved ok_save_stack ok_ret_addr X ok_lret exec_body ih ok_sp =>
/= [ | ra | rastack ] free_ra ok_to_save ok_callee_saved ok_save_stack ok_ret_addr X ok_lret exec_body ih.
2-3: case => sp_aligned.
all: move => ?; subst sp.
- (* Export function *)
{ case: lret ok_lret => // _.
subst callee_saved.
case E1: sf_save_stack ok_save_stack ok_ss ok_to_save exec_body ih =>
[ | saved_rsp | stack_saved_rsp ] /= ok_save_stack ok_ss ok_to_save exec_body ih ok_fd' wf_to_save.
+ (* No need to save RSP *)
{ have {ih} := ih fn xH.
rewrite /checked_c ok_fd chk_body => /(_ erefl).
case: (linear_c fn) ok_fd' => lbl lbody /= ok_fd' E.
have ok_body : is_linear_of fn (lbody ++ [::]).
+ by rewrite /is_linear_of cats0 ok_fd' /=; eexists; reflexivity.
have M' := mm_alloc M ok_m1'.
case/and4P: ok_save_stack => /eqP to_save_nil /eqP sf_align_1 /eqP stk_sz_0 /eqP stk_extra_sz_0.
have top_stack_preserved : top_stack m1' = top_stack (s1: mem).
+ rewrite (alloc_stack_top_stack ok_m1') sf_align_1.
rewrite top_stack_after_aligned_alloc.
2: exact: is_align8.
by rewrite stk_sz_0 stk_extra_sz_0 -addE add_0.
have X' :
vm_uincl (set_RSP p m1' (kill_vars (ra_undef fd var_tmp) s1)) vm1.
+ apply: vm_uincl_kill_vars_set_incl X => //.
+ by rewrite /ra_undef /ra_vm EQ /=; clear; SvD.fsetdec.
by rewrite top_stack_preserved.
have {E} [m2 vm2] := E m1 vm1 [::] [::] W M' X' (λ _ _, erefl) ok_body.
rewrite /= => E K2 W2 X2 H2 M2.
eexists m2 _; [ exact: E | | exact: W2 | | | exact: mm_free M2 ]; cycle 2.
+ move => a a_range /negbTE nv.
have A := alloc_stackP ok_m1'.
have [L] := ass_above_limit A.
rewrite stk_sz_0 => H.
apply: H2.
* rewrite (ass_root A); lia.
rewrite (ass_valid A) nv /= !zify => - [].
change (wsize_size U8) with 1%Z.
lia.
+ apply: vmap_eq_exceptI; last exact: K2.
rewrite to_save_nil Sv_diff_empty.
exact: Sv_Subset_union_left.
have S : stack_stable m1' s2'.
+ exact: sem_one_varmap_facts.sem_stack_stable exec_body.
move => x; move: (X2 x); rewrite /set_RSP !Fv.setP; case: eqP => // ?; subst.
by rewrite valid_rsp' -(ss_top_stack S) top_stack_preserved.
}
+ (* RSP is saved into register “saved_rsp” *)
{ have {ih} := ih fn xH.
rewrite /checked_c ok_fd chk_body => /(_ erefl).
move: ok_fd'.
case: saved_rsp ok_save_stack ok_ss E1 exec_body => _ saved_stack /= /andP[] /eqP -> /eqP to_save_empty.
move=>
/and3P[]
/eqP saved_stack_not_GD
/eqP saved_stack_not_RSP
/Sv_memP saved_stack_not_written.
move => E1 exec_body.
rewrite linear_c_nil.
case: (linear_c fn) => lbl lbody /=.
rewrite -cat_cons.
set P := (X in X ++ lbody ++ _).
set Q := (X in lbody ++ X).
move => ok_fd' E.
have ok_body : is_linear_of fn (P ++ lbody ++ Q).
+ by rewrite /is_linear_of ok_fd' /=; eauto.
have ok_rsp : get_var vm1 vrsp = ok (Vword (top_stack (emem s1))).
+ move: (X vrsp). rewrite Fv.setP_eq /get_var /=.
by case: _.[_]%vmap => //= - [] sz w ? /pword_of_word_uincl[] /= ? -> {w}; subst.
set vm_save := vm1.[{| vtype := spointer; vname := saved_stack |} <- ok (pword_of_word (top_stack (emem s1)))]%vmap.
set sf_sz := (sf_stk_sz _ + _)%Z.
set alloc := allocate_stack_frame p lparams false xH sf_sz.
have :
∃ vm, [/\
lsem
p'
mov_eop
{|
lmem := m1;
lvm := vm_save;
lfn := fn;
lpc := 1;
|}
{| lmem := m1;
lvm := vm;
lfn := fn;
lpc := size
((head {| li_ii := xH; li_i := Lalign; |} P) :: alloc) + 0;
|}
, wf_vm vm
, vm = vm_save [\ Sv.singleton vrsp ]
& get_var vm vrsp
= ok (Vword (top_stack (emem s1) - wrepr Uptr sf_sz))
].
{ move: ok_body; rewrite /P /allocate_stack_frame.
case: eqP => hsz ok_body.
* (* Nothing to allocate *)
exists vm_save; subst vm_save; split.
- rewrite addn0 /=.
rewrite /alloc /allocate_stack_frame.
rewrite /sf_sz hsz /=.
exact: rt_refl.
- exact: wf_vm_set W.
- reflexivity.
rewrite /sf_sz hsz.
by rewrite wrepr0 GRing.subr0 get_var_set; case: eqP.
(* Subtract frame size *)
eexists; split.
- apply: rt_step.
rewrite /lsem1 /step.
move: ok_body.
rewrite /P -cat1s -catA -(addn0 1) => /find_instr_skip -> /=.
have Hvm :
vm_save.[vrsp]%vmap = ok (pword_of_word (@top_stack _ mem _ _ s1)).
+ move: (X vrsp).
rewrite Fv.setP_eq /= Fv.setP_neq /=;
last move: saved_stack_not_RSP;
last by case: (_ == _) /eqP.
case: _.[_]%vmap => //=.
move=> -[] ws w Uptr_le_ws.
move=> /pword_of_word_uincl[] /= ? -> {w}.
subst.
by rewrite pword_of_wordE.
rewrite (@spec_lp_free_stack_frame
_ _
hlparams
_
{| emem := m1; evm := vm_save; |}
_ _ _ _ _ _
Hvm).
rewrite /of_estate /=.
have -> : size alloc = 1.
+ rewrite /alloc /allocate_stack_frame.
by case: (sf_sz == 0) /eqP.
reflexivity.
- do 2 apply: wf_vm_set.
exact: W.
- clear => x hx.
rewrite Fv.setP_neq //; apply/eqP.
move: hx; clear.
rewrite Sv.singleton_spec; exact/not_eq_sym.
by rewrite get_var_set eqxx.
}
case => vm [] lexec_alloc ok_vm vm_old vm_rsp.
set rsp' := top_stack m1'.
have [vm'' [heval hvm'' hdefvm'' wf_vm'']]:=
(@spec_lp_ensure_rsp_alignment _ _ hlparams p' {|evm:=vm; emem:=m1|} _
(sf_align (f_extra fd)) _ xH fn ((size alloc).+1 + 0) vm_rsp ok_vm).
have X' :
vm_uincl (set_RSP p m1' (kill_vars (ra_undef fd var_tmp) s1)) vm''.
+ move=> z; have := X z; rewrite /set_RSP -/vrsp.
rewrite /= in hvm''.
case: (vrsp =P z) => [<- | /eqP hne].
+ rewrite !Fv.setP_eq hvm''; last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
rewrite Fv.setP_eq (alloc_stack_top_stack ok_m1').
by rewrite /top_stack_after_alloc /align_word wrepr_opp.
rewrite Fv.setP_neq // Fv.setP_neq // !kill_varsE.
case: (Sv_memP _ (ra_undef _ _)).
+ by move=> _ _; apply wf_vm_eval_uincl_pundef.
rewrite /ra_undef /ra_vm EQ.
have -> : {| vtype := sword Uptr; vname := lp_tmp lparams |} = var_tmp by [].
move=> hnin.
case: Sv_memP => ?; first by SvD.fsetdec.
rewrite hvm''; last by SvD.fsetdec.
rewrite Fv.setP_neq // vm_old; last by move/eqP:hne; SvD.fsetdec.
rewrite /vm_save Fv.setP_neq //.
by apply/eqP; move: hnin; rewrite /saved_stack_vm E1 /savedstackreg /=; clear; SvD.fsetdec.
have D : disjoint_labels 1 lbl P.
+ move => lbl' _.
rewrite /P /= has_cat orbF /allocate_stack_frame.
by case: ifP.
move: E => /(_ m1 vm'' P Q wf_vm'' (mm_alloc M ok_m1') X' D ok_body).
case => m2 vm2.
rewrite /= !size_cat /= addn1.
move => E K2 W2 X2 H2 M2.
have saved_rsp : get_var vm2 (Var (sword Uptr) saved_stack) = ok (Vword (top_stack (emem s1))).
+ rewrite /get_var -K2 //.
rewrite hvm''; last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
rewrite Fv.setP_neq; last by apply/eqP => - [] ?; subst.
rewrite vm_old; last by move => /SvD.F.singleton_iff [] ?; subst.
by rewrite /vm_save Fv.setP_eq.
eexists.
+ apply: lsem_step.
* rewrite /lsem1 /step /find_instr ok_fd' /=.
set ts := @top_stack _ mem _ _ s1.
have Hsem_pexpr :
sem_pexpr
[::]
{| emem := m1; evm := vm1; |}
(Pvar (Gvar (vid p.(p_extra).(sp_rsp)) Slocal))
= ok (Vword ts).
- by rewrite /= -ok_rsp.
have Hwrite_lval :
write_lval
[::]
(Lvar (vid saved_stack))
(Vword ts)
{| emem := m1; evm := vm1; |}
= ok
{|
emem := m1;
evm := (vm1.[(vid saved_stack)
<- ok (pword_of_word ts)])%vmap;
|}.
- rewrite /write_lval /write_var /=.
by rewrite -/(to_pword _ (Vword ts)) to_pword_u.
by rewrite (spec_lmove hlparams _ _ _ _ Hsem_pexpr Hwrite_lval).
apply: lsem_trans; first exact: lexec_alloc.
apply: lsem_step.
* rewrite /lsem1 /step.
move: (ok_body).
set sz := (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd))%Z.
set ws := sf_align (f_extra fd).
replace (P ++ lbody ++ Q) with
((head
{| li_ii := xH; li_i := Lalign; |}
P :: allocate_stack_frame p lparams false xH sz)
++ [:: ensure_rsp_alignment p lparams xH ws ]
++ lbody
++ Q);
last by rewrite /P /= -catA.
move => /find_instr_skip -> /=.
Global Opaque Z.opp.
apply heval.
rewrite addn0.
subst alloc.
apply: lsem_step_end; first exact: E.
rewrite /lsem1 /step.
replace (((size _).+1 + size _).+1) with (size (P ++ lbody) + 0);
last by rewrite /= !size_cat addn0 addn1.
move: (ok_body); rewrite catA => /find_instr_skip ->.
set ts := @top_stack _ _ _ Memory.M s1.
rewrite /=.
have Hsem_pexpr :
sem_pexpr
[::]
{| evm := vm2; emem := m2; |}
(Gvar (vid saved_stack) Slocal)
= ok (Vword ts).
* by rewrite /= /get_gvar /= saved_rsp.
have Hwrite_lval :
write_lval
[::]
(vid p.(p_extra).(sp_rsp))
(Vword ts)
{| emem := m2; evm := vm2 |}
= ok
{|
evm := vm2.[vrsp <- ok (pword_of_word ts)]%vmap;
emem := m2;
|}.
* rewrite /= /write_var /=.
by rewrite -/(to_pword _ (Vword ts)) to_pword_u.
rewrite (spec_lmove hlparams p' _ _ _ Hsem_pexpr Hwrite_lval).
rewrite addn0 !size_cat !addn1 !addSn addnS /=.
reflexivity.
+ rewrite to_save_empty Sv_diff_empty.
clear - ok_rsp K2 vm_old hvm''.
move => x.
rewrite !Sv.union_spec !Sv.add_spec Sv.singleton_spec Fv.setP =>
/Decidable.not_or[] x_not_k /Decidable.not_or[] /Decidable.not_or[] x_not_tmp x_not_flags x_not_saved_stack.
case: eqP => x_rsp.
* subst; move: ok_rsp; rewrite /get_var.
case: _.[_]%vmap; last by case.
move => [] /= sz w hle /ok_inj /Vword_inj[] ?; subst => /= ->.
by rewrite pword_of_wordE.
rewrite -K2; last exact: x_not_k.
repeat (rewrite Fv.setP_neq; last by apply/eqP; intuition).
have ?: x \in [seq to_var i | i <- rflags]=false.
+ apply /(mapP (T1:=ceqT_eqType)).
move=> [f ? ?]; subst x.
apply: x_not_flags.
apply /sv_of_flagsP /(mapP(T1:=ceqT_eqType)).
by exists f => //.
rewrite hvm''; last by apply /sv_of_flagsP/negPf.
rewrite Fv.setP_neq; last by apply /eqP.
rewrite vm_old; last by rewrite Sv.singleton_spec; exact/not_eq_sym.
rewrite Fv.setP_neq // eq_sym.
by apply/eqP.
+ exact: wf_vm_set.
+ move => x; rewrite Fv.setP; case: eqP => ?.
* by subst; rewrite Fv.setP_eq.
rewrite Fv.setP_neq; last by apply/eqP.
rewrite /set_RSP Fv.setP_neq; last by apply/eqP.
done.
+ move => a [] a_lo a_hi /negbTE nv.
have A := alloc_stackP ok_m1'.
have [L H] := ass_above_limit A.
apply: H2.
* rewrite (ass_root A).
split; last exact: a_hi.
etransitivity; last exact: a_lo.
suff : (0 <= sf_stk_sz (f_extra fd))%Z by lia.
by case/andP: ok_stk_sz => /lezP.
rewrite (ass_valid A) nv /= !zify => - [].
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) H => n.
lia.
exact: mm_free.
}
(* RSP is saved in stack at offset “stack_saved_rsp” *)
{ have {ih} := ih fn xH.
case/andP: ok_save_stack => ok_save_stack tmp_not_saved.
rewrite /checked_c ok_fd chk_body => /(_ erefl).
move: ok_fd'.
rewrite (linear_c_nil).
case: (linear_c fn) => lbl lbody /=.
rewrite -cat_cons.
case/and3P: ok_stk_sz => /lezP stk_sz_pos /lezP stk_extra_pos /ltzP frame_noof.
have sz_nz : (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd) == 0)%Z = false.
+ move: ok_save_stack; clear - stk_sz_pos stk_extra_pos; rewrite !zify => - [] C [] D _.
apply/eqP.
move: D; rewrite /stack_frame_allocation_size.
have := wsize_size_pos (sf_align (f_extra fd)).
change (wsize_size Uptr) with 8%Z.
move: (sf_stk_sz _) (sf_stk_extra_sz _) stk_sz_pos stk_extra_pos C => n m A B C.
have : (0 <= n + m)%Z by lia.
case: (n + m)%Z.
2-3: move => ?; lia.
move => _ _; assert (h := wsize_size_pos reg_size); lia.
rewrite /allocate_stack_frame sz_nz.
set P := (X in X ++ lbody ++ _).
set Q := (X in lbody ++ X).
move => ok_fd' E.
have ok_body : is_linear_of fn (P ++ lbody ++ Q).
+ by rewrite /is_linear_of ok_fd' /=; eauto.
have ok_rsp : get_var vm1 vrsp = ok (Vword (top_stack (emem s1))).
+ move: (X vrsp). rewrite Fv.setP_eq /get_var /=.
by case: _.[_]%vmap => //= - [] sz w ? /pword_of_word_uincl[] /= ? -> {w}; subst.
set vm_save := (vm1.[var_tmp <- ok (pword_of_word (top_stack (emem s1)))])%vmap.
set vm_rsp := vm_save.[vrsp <- ok (pword_of_word (top_stack (emem s1) - wrepr Uptr (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd))))]%vmap.
case/and4P: ok_save_stack => /lezP rsp_slot_lo /lezP rsp_slot_hi aligned_frame rsp_slot_aligned.
have A := alloc_stackP ok_m1'.
have can_spill := mm_can_write_after_alloc _ ok_m1' stk_sz_pos stk_extra_pos (cmp_le_trans _ aligned_frame).
set top := (top_stack_after_alloc (top_stack (emem s1)) (sf_align (f_extra fd)) (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd))).
have topE : top_stack m1' = top.
+ by rewrite (alloc_stack_top_stack ok_m1').
set ts := top_stack (emem s1). rewrite /ts. rewrite /= in ts.
have [ m2 [] ok_m2 H2 M2 ] := can_spill _ _ _ ts (cmp_le_refl _) rsp_slot_aligned rsp_slot_lo rsp_slot_hi M.
set wtop := (X in pword_of_word X) in vm_rsp.
have vm_rsp_rsp: get_var vm_rsp vrsp = ok (Vword wtop).
+ by rewrite get_var_eq.
have wf_vm_rsp: wf_vm vm_rsp.
+ by do 2 apply wf_vm_set.
have [vm_rsp_aligned [heval hvmrsp hdefvmrsp wf_vm_rsp_aligned]] :=
@spec_lp_ensure_rsp_alignment _ _ hlparams p' {|evm:=vm_rsp; emem:=m1|} _
(sf_align (f_extra fd)) _ xH fn ((1 + 0).+1) vm_rsp_rsp wf_vm_rsp.
rewrite /wtop -/(align_word _ _) -wrepr_opp -/(top_stack_after_alloc _ _ _) -/top in hvmrsp.
have X' :
vm_uincl (set_RSP p m1' (kill_vars (ra_undef fd var_tmp) s1)) vm_rsp_aligned.
+ move=> z; have := X z; rewrite /set_RSP -/vrsp.
case: (vrsp =P z) => [<- | /eqP hne].
+ rewrite !Fv.setP_eq hvmrsp; last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
by rewrite Fv.setP_eq (alloc_stack_top_stack ok_m1').
rewrite Fv.setP_neq // Fv.setP_neq // !kill_varsE.
case: (Sv_memP _ (ra_undef _ _)).
+ by move=> _ _; apply wf_vm_eval_uincl_pundef.
rewrite /ra_undef /ra_vm EQ /= => hnin.
case: Sv_memP => ?; first by SvD.fsetdec.
rewrite hvmrsp /=; last by SvD.fsetdec.
by rewrite /vm_rsp /vm_save !Fv.setP_neq // /=; apply /eqP; SvD.fsetdec.
have D : disjoint_labels 1 lbl P.
+ move => lbl' _.
exact: push_to_save_has_no_label.
have is_ok_vm1_vm_rsp_aligned : ∀ x, is_ok (get_var vm1 x >>= of_val (vtype x)) → is_ok (get_var vm_rsp_aligned x >>= of_val (vtype x)).
+ move=> x ok_x.
have: is_ok (get_var vm_rsp x >>= of_val (vtype x)).
+ move: ok_x; rewrite /vm_rsp /vm_save /get_var => ok_x.
rewrite !Fv.setP.
by repeat (case: eqP => ?; first by (subst; rewrite /= truncate_word_u)).
rewrite /get_var.
case: (SvP.MP.In_dec x (sv_of_flags rflags)) => hin.
+ have /hdefvmrsp := hin.
case: vm_rsp_aligned.[_]%vmap.
+ have hty: vtype x = sbool.
+ by move /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) : hin => [? _ ->].
by case: (x) hty => /= _ xn -> /=.
by move=> _ <- //.
rewrite hvmrsp //.
rewrite Fv.setP.
case: eqP => ?; first by (subst; rewrite /= truncate_word_u).
by case: (_.[_]%vmap).
have :
∃ m3, [/\
foldM (λ '(x, ofs) m,
Let: ws := if vtype x is sword ws then ok ws else Error ErrType in
Let: v := get_var vm_rsp_aligned x >>= to_word ws in
write m (top + wrepr Uptr ofs)%R v) m2 (sf_to_save (f_extra fd)) = ok m3,
preserved_metadata s1 m2 m3,
match_mem s1 m3 &
lsem p' mov_eop {| lmem := m2; lvm := vm_rsp_aligned; lfn := fn; lpc := 4 |}
{| lmem := m3 ; lvm := vm_rsp_aligned ; lfn := fn ; lpc := size P |}
].
+ {
clear ok_m2.
move: ok_body.
rewrite /P /= -(addn4 (size _)).
move: (lbody ++ Q) => suffix.
rewrite -(cat1s _ (_ ++ _)) -!cat_cons.
set prefix := (X in is_linear_of _ (X ++ _ ++ suffix)).
change 4 with (size prefix).
move: prefix.
have : (sf_stk_sz (f_extra fd) + wsize_size Uptr <= stack_saved_rsp + wsize_size Uptr)%Z.
* move: (sf_stk_sz _) rsp_slot_lo; clear => ??; lia.
elim: (sf_to_save (f_extra fd)) (stack_saved_rsp + _)%Z wf_to_save ok_to_save m2 H2 M2
=> [ sz' _ _ | [x ofs] to_save ih lo /= wf_to_save ok_to_save ] m2 H2 M2 sz'_le_lo prefix ok_body.
* by exists m2; split; last exact: rt_refl.
case/andP: wf_to_save => wf_x wf_to_save.
case/all_disjoint_aligned_betweenP: ok_to_save => x_ofs [] x_ws [].
case: is_word_type (@is_word_typeP (vtype x)) => // ws /(_ _ erefl) wt_x /ok_inj[] ??; subst x_ofs x_ws.
move => lo_ofs ok_ws aligned_ofs ok_to_save.
move: ih => /(_ _ wf_to_save ok_to_save) ih.
case get_x: get_var (is_ok_vm1_vm_rsp_aligned _ wf_x) => [ v | // ].
rewrite wt_x /=.
case ok_w: to_word => [ w | // ] _ /=.
have := can_spill _ ofs _ w ok_ws aligned_ofs _ _ M2.
case.
* etransitivity; last exact: lo_ofs.
etransitivity; last exact: sz'_le_lo.
assert (h := wsize_size_pos reg_size).
move: (sf_stk_sz _) => ?; lia.
* exact: all_disjoint_aligned_between_range ok_to_save.
rewrite topE => acc [] ok_acc Hacc ACC.
have : preserved_metadata s1 m1 acc.
* transitivity m2; assumption.
move: ih => /(_ _ _ ACC) ih /ih {} ih.
rewrite wt_x /= in ok_body.
have : (sf_stk_sz (f_extra fd) + wsize_size Uptr <= ofs + wsize_size ws)%Z.
* move: (sf_stk_sz _) sz'_le_lo lo_ofs (wsize_size_pos ws) => /=; lia.
move => /ih {} ih.
move: (ok_body); rewrite -cat_rcons => /ih{ih} [] m3 [] ok_m3 H3 M3.
rewrite size_rcons => exec.
exists m3; split.
* rewrite ok_acc; exact: ok_m3.
* transitivity acc; assumption.
* exact: M3.
rewrite -addn1 -addnA add1n.
apply: lsem_step; last exact: exec.
rewrite /lsem1 /step.
rewrite -{1}(addn0 (size prefix)) (find_instr_skip ok_body).
move /to_wordI : ok_w => [ws' [w' [hle ??]]]; subst v w => /=.
apply: (@spec_lassign _ _ hlparams p' {|emem:=_; evm:=_|} {|emem:=_; evm:=_|} _ _ _ _ _ w') => //.
+ by rewrite /truncate_word hle.
rewrite /= /get_var.
rewrite (hvmrsp vrsp); last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
by rewrite Fv.setP_eq /= !truncate_word_u /= ok_acc.
}
case => m3 [] ok_m3 H3 M3' exec_save_to_stack.
have M3 : match_mem m1' m3 := mm_alloc M3' ok_m1'.
move: E => /(_ m3 vm_rsp_aligned P Q wf_vm_rsp_aligned M3 X' D ok_body).
case => m4 vm4 E K4 W4 X4 H4 M4.
have vm4_get_rsp : get_var vm4 {| vtype := sword Uptr; vname := sp_rsp (p_extra p) |} >>= to_pointer = ok top.
+ rewrite /get_var /= -K4.
+ rewrite hvmrsp; last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
by rewrite Fv.setP_eq /= truncate_word_u.
have /disjointP K := sem_RSP_GD_not_written var_tmp_not_magic exec_body.
move => /K; apply; exact: RSP_in_magic.
have top_no_overflow : (wunsigned top + (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd)) < wbase Uptr)%Z.
+ apply: Z.le_lt_trans; last exact: proj2 (wunsigned_range (top_stack (emem s1))).
etransitivity; last exact: (proj2 A.(ass_above_limit)).
rewrite topE; lia.
have rsp_slot_pos : (0 <= stack_saved_rsp + wsize_size Uptr)%Z.
+ assert (h := wsize_size_pos Uptr); lia.
have [read_in_m3 read_spilled] := read_after_spill top_no_overflow rsp_slot_pos ok_to_save ok_m3.
have read_saved_rsp : read m4 (top + wrepr Uptr stack_saved_rsp)%R Uptr = ok (top_stack (emem s1)).
+ rewrite -(@eq_read _ _ _ _ m3); last first.
* move => i i_range.
have rsp_range := stack_slot_in_bounds ok_m1' stk_sz_pos stk_extra_pos rsp_slot_lo rsp_slot_hi i_range.
apply: (preserved_metadata_w ok_m1') => //.
- rewrite -topE; move: (sf_stk_sz _) stk_sz_pos rsp_range; lia.
rewrite A.(ass_valid).
apply/orP => - [].
- move => /(ass_fresh_alt A); apply.
rewrite !zify -topE; move: (sf_stk_sz _) stk_sz_pos rsp_range; lia.
rewrite !zify -topE.
have [_] := A.(ass_above_limit).
rewrite Z.max_r //.
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) (sf_stk_extra_sz _) stk_sz_pos stk_extra_pos rsp_range => n n' n_pos n'_pos rsp_range h [] _.
lia.
rewrite read_in_m3; [ | lia | reflexivity ].
by rewrite -topE (writeP_eq ok_m2).
have : ∃ vm5,
[/\
lsem p' mov_eop {| lmem := m4; lvm := vm4 ; lfn := fn ; lpc := size (P ++ lbody) |}
{| lmem := m4; lvm := vm5 ; lfn := fn ; lpc := size (P ++ lbody ++ pop_to_save p lparams xH (sf_to_save (f_extra fd))) |},
wf_vm vm5 &
∀ x, vm5.[x] = if x \in (map fst (sf_to_save (f_extra fd))) then vm_rsp_aligned.[x] else vm4.[x]
]%vmap.
{
clear E K4 X4.
move: ok_body ok_to_save wf_to_save read_spilled.
rewrite !catA.
move: [:: _] => suffix.
move: (P ++ lbody).
have : (sf_stk_sz (f_extra fd) + wsize_size Uptr <= stack_saved_rsp + wsize_size Uptr)%Z.
* move: (sf_stk_sz _) rsp_slot_lo; clear => ??; lia.
elim: (sf_to_save _) (stack_saved_rsp + _)%Z vm4 W4 vm4_get_rsp
=> [ | [ x ofs ] to_save ih ] lo vm4 W4 vm4_get_rsp sz'_le_lo prefix ok_body /all_disjoint_aligned_betweenP ok_to_save wf_to_save read_spilled.
* exists vm4; split => //.
rewrite cats0; exact: rt_refl.
case: ok_to_save => x_ofs [] x_ws [].
case: is_word_type (@is_word_typeP (vtype x)) => // ws /(_ _ erefl) wt_x /ok_inj[] ??; subst x_ofs x_ws.
move => lo_ofs ok_ws aligned_ofs ok_to_save.
move: wf_to_save; rewrite /vm_initialized_on /=.
case/andP => /is_ok_vm1_vm_rsp_aligned.
rewrite wt_x => get_x wf_to_save.
case ok_x: get_var get_x => [ v | // ] /=.
case ok_v: to_word => [ w | // ] _.
case: x wt_x ok_body ok_x read_spilled => - [] // _ x /= [->] ok_body ok_x read_spilled.
set vm5 := vm4.[{| vname := x ; vtype := sword ws |} <- ok (pword_of_word w)]%vmap.
have W5: wf_vm vm5.
* exact: wf_vm_set W4.
have vm5_get_rsp : get_var vm5 vrsp >>= to_pointer = ok top.
* case: (vrsp =P {| vname := x ; vtype := sword ws |}) => x_rsp;
last by rewrite /get_var Fv.setP_neq ?vm4_get_rsp //; apply/eqP => ?; exact: x_rsp.
have ? : ws = Uptr by case: x_rsp.
subst.
rewrite x_rsp /get_var Fv.setP_eq /= truncate_word_u.
move: ok_x ok_v.
rewrite /get_var -x_rsp.
rewrite (hvmrsp vrsp); last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
rewrite Fv.setP_eq /= => /ok_inj <- /=.
by rewrite truncate_word_u.
move: ih => /(_ _ _ W5 vm5_get_rsp) ih.
move: (ok_body).
rewrite -cat_rcons => /ih {} ih.
have : (sf_stk_sz (f_extra fd) + wsize_size Uptr <= ofs + wsize_size ws)%Z.
* etransitivity; first exact: sz'_le_lo.
clear -lo_ofs.
have := wsize_size_pos ws.
lia.
move => {} /ih /(_ ok_to_save wf_to_save) [].
* move => x' ofs' saved'; apply: read_spilled.
by rewrite inE saved' orbT.
move => vm6 [] E W6 X6.
exists vm6; split.
* apply: lsem_step; last exact: E.
rewrite /lsem1 /step.
move: ok_body.
rewrite -{1}(addn0 (size prefix)) -catA => /find_instr_skip -> /=.
rewrite /lload.
rewrite size_rcons.
apply: (@spec_lassign _ _ hlparams p' {|emem:=_; evm:=_|} {|emem:=_; evm:=_|}).
+ rewrite /= vm4_get_rsp truncate_word_u /=.
have : read m4 (top + wrepr Uptr ofs)%R ws = get_var vm_rsp_aligned {| vname := x; vtype := sword ws |} >>= to_word ws.
* rewrite -(@eq_read _ _ _ _ m3); last first.
- move=> i i_range.
have ofs_lo : (sf_stk_sz (f_extra fd) <= ofs)%Z.
+ move: (sf_stk_sz _) sz'_le_lo lo_ofs => n.
assert (h := wsize_size_pos Uptr).
lia.
have ofs_hi := all_disjoint_aligned_between_range ok_to_save.
have rsp_range := stack_slot_in_bounds ok_m1' stk_sz_pos stk_extra_pos ofs_lo ofs_hi i_range.
apply: (preserved_metadata_w ok_m1') => //.
- rewrite -topE; move: (sf_stk_sz _) stk_sz_pos rsp_range; lia.
rewrite A.(ass_valid).
apply/orP => - [].
- move => /(ass_fresh_alt A); apply.
rewrite !zify -topE; move: (sf_stk_sz _) stk_sz_pos rsp_range; lia.
rewrite !zify -topE.
have [_] := A.(ass_above_limit).
rewrite Z.max_r //.
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) (sf_stk_extra_sz _) stk_sz_pos stk_extra_pos rsp_range => n n' n_pos n'_pos rsp_range h [] _.
lia.
move: read_spilled => /(_ {| vtype := sword ws ; vname := x|} ofs).
by rewrite inE eqxx => /(_ erefl) [] _ /Some_inj <- [] w' ->.
move => ->.
by rewrite ok_x /= ok_v.
+ by rewrite truncate_word_u.
by rewrite /= /write_var /= sumbool_of_boolET.
* exact: W6.
move => z; move: (X6 z).
rewrite inE.
case: ifP => z_to_save ->; first by rewrite orbT.
case: eqP => /= z_x; last by rewrite Fv.setP_neq //; apply/eqP => ?; exact: z_x.
rewrite z_x Fv.setP_eq.
move: ok_v.
apply: on_vuP ok_x => // /= w' -> <- /to_word_to_pword <-.
clear.
by case: w' => /= ws' w le; rewrite sumbool_of_boolET.
}
case => vm5 [] exec_restore_from_stack wf_vm5 ok_vm5.
have vm5_get_rsp : get_var vm5 {| vtype := sword Uptr; vname := sp_rsp (p_extra p) |} >>= to_pointer = ok top.
+ rewrite /get_var /= ok_vm5.
case: ifP => _; last rewrite -K4.
1-2: by (rewrite (hvmrsp vrsp); last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) []);
rewrite Fv.setP_eq /= truncate_word_u.
have /disjointP K := sem_RSP_GD_not_written var_tmp_not_magic exec_body.
move => /K; apply; exact: RSP_in_magic.
eexists.
+ apply: lsem_step.
* rewrite /lsem1 /step /find_instr ok_fd' /=.
apply: (@spec_lmove _ _ hlparams p' {|emem:=_; evm:=_|} {|emem:=_; evm:=_|}).
+ by rewrite /= /get_gvar /= ok_rsp.
by rewrite /= /write_var /= sumbool_of_boolET.
apply: lsem_step.
* rewrite /lsem1 /step.
move: ok_body.
rewrite /P -cat1s -catA -(addn0 1) => /find_instr_skip -> /=.
apply: (@spec_lp_free_stack_frame _ _ hlparams p').
rewrite Fv.setP_neq; last by move /negbT: (not_magic_neq_rsp var_tmp_not_magic).
move: ok_rsp; rewrite /get_var.
apply: on_vuP => //= -[???] ->.
move=> /Vword_inj /= [?]; subst => /= ->.
by f_equal; apply pword_of_wordE.
apply: lsem_step.
* rewrite /lsem1 /step.
move: ok_body.
replace (P ++ lbody ++ Q)
with
(take 2 P
++ [:: ensure_rsp_alignment p lparams xH (sf_align (f_extra fd)),
lstore lparams xH (VarI vrsp xH) stack_saved_rsp Uptr (mk_lvar var_tmp) &
push_to_save p lparams xH (sf_to_save (f_extra fd)) ] ++ lbody ++ Q);
last by rewrite /P catA.
move => /find_instr_skip -> /=.
rewrite -/vm_save -/vm_rsp.
apply heval.
apply: lsem_step.
* rewrite /lsem1 /step.
move: ok_body.
replace (P ++ lbody ++ Q)
with
(take 3 P
++ [:: lstore lparams xH (VarI vrsp xH) stack_saved_rsp Uptr (mk_lvar var_tmp) &
push_to_save p lparams xH (sf_to_save (f_extra fd)) ] ++ lbody ++ Q);
last by rewrite /P catA.
move => /find_instr_skip -> /=.
rewrite /lstore.
apply: (@spec_lassign _ _ hlparams p').
+ rewrite /= /get_gvar /= /get_var.
rewrite (hvmrsp var_tmp); last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
do 2 (rewrite Fv.setP_neq; last by rewrite eq_sym; apply/negbT; exact: not_magic_neq_rsp var_tmp_not_magic).
by rewrite Fv.setP_eq /=.
+ by rewrite truncate_word_u.
rewrite /= /write_var /= /get_var.
rewrite (hvmrsp vrsp); last by move=> /sv_of_flagsP /(mapP (T1:=ceqT_eqType)) [].
by rewrite Fv.setP_eq /= !truncate_word_u /= -topE ok_m2 /=.
apply: lsem_trans.
* exact: exec_save_to_stack.
apply: lsem_trans.
* exact: E.
apply: lsem_trans.
* exact: exec_restore_from_stack.
apply: LSem_step.
rewrite /lsem1 /step -(addn0 (size _)).
rewrite !catA in ok_body.
move/find_instr_skip: ok_body; rewrite -catA => -> /=.
rewrite /lload.
rewrite !size_cat /= addn0 addn1 !addnS !addnA.
apply: (@spec_lassign _ _ hlparams p' {|emem:=_; evm:=_|} {|emem:=_; evm:=_|}).
+ rewrite /= vm5_get_rsp /= truncate_word_u /=.
by rewrite read_saved_rsp /=.
+ by rewrite truncate_word_u.
by rewrite /= /write_var /= sumbool_of_boolET.
+ move => x /Sv_memP H.
rewrite Fv.setP; case: eqP => x_rsp.
* move: (X x); subst; rewrite Fv.setP_eq.
by case: _.[_]%vmap => //= ? /pword_uincl ->.
move: H.
rewrite SvP.diff_mem negb_and => /orP[]; last first.
* move/negbNE/Sv_memP/sv_of_listP; rewrite map_id /= => hx.
have /eqP {} x_rsp := x_rsp.
rewrite ok_vm5 hx hvmrsp; last first.
- case/sv_of_flagsP/in_map => f hf ?; subst x.
case/in_map: hx => - [] y ofs K ?; subst y.
elim: (sf_to_save _) K (m2) (m3) ok_m3 => //; clear.
case => x j m ih /= [].
* by case => ??; subst.
move => /ih{}ih m1 m3; t_xrbindP => m2 ws.
case: vtype => // ws' /ok_inj ?; subst ws' => ?????; exact: ih.
rewrite !Fv.setP_neq //.
apply/eqP => ?; subst x.
move/negP: tmp_not_saved; apply.
rewrite sv_of_listE; exact: hx.
rewrite !SvP.union_mem Sv_mem_add sv_of_flagsE SvP.empty_mem !orbA !orbF -!orbA.
case/norP => x_ni_k /norP[] x_neq_tmp x_not_flag.
transitivity vm_save.[x]%vmap; first by rewrite /vm_save Fv.setP_neq // neq_sym.
transitivity vm_rsp.[x]%vmap; first by rewrite /vm_rsp Fv.setP_neq //; apply/eqP.
transitivity vm_rsp_aligned.[x]%vmap.
+ rewrite (hvmrsp x); last by apply /sv_of_flagsP.
rewrite Fv.setP_neq //.
by apply /eqP.
transitivity vm4.[x]%vmap; first by rewrite K4 //; apply/Sv_memP.
rewrite ok_vm5; case: ifP => // _.
rewrite K4 //.
exact/Sv_memP.
+ exact: wf_vm_set wf_vm5.
+ move => x; rewrite !Fv.setP; case: eqP => x_rsp; first by subst.
move => /sv_of_listP; rewrite map_id => /negbTE x_not_to_save.
apply: (eval_uincl_trans (X4 x)).
by rewrite ok_vm5 x_not_to_save.
+ etransitivity; first exact: H2.
etransitivity; first exact: H3.
exact: preserved_metadata_alloc ok_m1' H4.
exact: mm_free M4.
}
}
- (* Internal function, return address in register “ra” *)
{ case: ra EQ ok_ret_addr X free_ra ok_lret exec_body ih => // -[] // ws // ra EQ ra_well_typed X /andP[] _ ra_notin_k.
case: lret => // - [] [] [] caller lret cbody pc.
case: (ws =P reg_size) => // E.
subst ws.
move=> [] ok_cbody ok_pc [] retptr ok_retptr ok_ra exec_body ih.
have {ih} := ih fn 2%positive.
rewrite /checked_c ok_fd chk_body => /(_ erefl).
rewrite (linear_c_nil _ _ _ _ _ _ [:: _ ]).
case: (linear_c fn) (valid_c fn (f_body fd) 2%positive) => lbl lbody ok_lbl /= E.
set P := (P in P :: lbody ++ _).
set Q := (Q in P :: lbody ++ Q).
move => ok_fd'.
have ok_body : is_linear_of fn ([:: P ] ++ lbody ++ Q).
+ by rewrite /is_linear_of ok_fd'; eauto.
have X1 : vm_uincl (set_RSP p m1' (kill_vars (ra_undef fd var_tmp) s1)) vm1.
+ apply: vm_uincl_kill_vars_set_incl X => //.
+ by rewrite /ra_undef /ra_vm EQ; SvD.fsetdec.
rewrite (alloc_stack_top_stack ok_m1') top_stack_after_aligned_alloc; last by exact: sp_aligned.
by rewrite wrepr_opp -/(stack_frame_allocation_size fd.(f_extra)).
have D : disjoint_labels 2 lbl [:: P].
+ by move => q [A B]; rewrite /P /is_label /= orbF; apply/eqP => ?; subst; lia.
have {E} [ m2 vm2 E K2 W2 ok_vm2 H2 M2 ] := E m1 vm1 [:: P] Q W (mm_alloc M ok_m1') X1 D ok_body.
eexists; [ | | exact: W2 | | | exact: mm_free M2 ]; cycle 3.
+ move => a [] a_lo a_hi /negbTE nv.
have A := alloc_stackP ok_m1'.
have [L H] := ass_above_limit A.
apply: H2.
* rewrite (ass_root A).
split; last exact: a_hi.
etransitivity; last exact: a_lo.
suff : (0 <= sf_stk_sz (f_extra fd))%Z by lia.
by case/andP: ok_stk_sz => /lezP.
rewrite (ass_valid A) nv /= !zify => - [].
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) H => n.
lia.
+ apply: lsem_trans; first exact: E.
apply: LSem_step.
rewrite catA in ok_body.
rewrite /lsem1 /step -(addn0 (size ([:: P] ++ lbody))) (find_instr_skip ok_body) /= /eval_instr /= /get_gvar /= /get_var /=.
have ra_not_written : (vm2.[ Var spointer ra ] = vm1.[ Var spointer ra ])%vmap.
* symmetry; apply: K2.
have /andP [_ ?] := ra_notin_k.
by apply/Sv_memP.
rewrite ra_not_written ok_ra /= zero_extend_u truncate_word_u.
assert (h := decode_encode_label (label_in_lprog p') (caller, lret)).
move: h.
rewrite ok_retptr /= => -> /=.
case: ok_cbody => fd' -> -> /=; rewrite ok_pc /setcpc /=; reflexivity.
+ apply: vmap_eq_exceptI K2.
apply: Sv_Subset_union_left.
exact: SvP.MP.union_subset_1.
move => ?; rewrite /set_RSP !Fv.setP; case: eqP => // ?; subst.
move: (ok_vm2 vrsp).
have S : stack_stable m1' s2'.
+ exact: sem_one_varmap_facts.sem_stack_stable exec_body.
rewrite valid_rsp' -(ss_top_stack S) (alloc_stack_top_stack ok_m1').
rewrite top_stack_after_aligned_alloc;
last by exact: sp_aligned.
by rewrite wrepr_opp.
}
(* Internal function, return address in stack at offset “rastack” *)
{ case: lret ok_lret => // - [] [] [] caller lret cbody pc [] ok_cbody ok_pc [] retptr ok_retptr [] rsp ok_rsp ok_ra.
have := X vrsp.
rewrite Fv.setP_eq ok_rsp => /andP[] _ /eqP /=.
rewrite zero_extend_u => ?; subst rsp.
have {ih} := ih fn 2%positive.
rewrite /checked_c ok_fd chk_body => /(_ erefl).
rewrite (linear_c_nil _ _ _ _ _ _ [:: _ ]).
case: (linear_c fn) (valid_c fn (f_body fd) 2%positive) => lbl lbody ok_lbl /= E.
set P := (P in P :: lbody ++ _).
set Q := (Q in P :: lbody ++ Q).
move => ok_fd'.
have ok_body : is_linear_of fn ([:: P ] ++ lbody ++ Q).
+ by rewrite /is_linear_of ok_fd'; eauto.
have X1 : vm_uincl (set_RSP p m1' (kill_vars (ra_undef fd var_tmp) s1)) vm1.
+ apply: vm_uincl_kill_vars_set_incl X => //.
+ by rewrite /ra_undef /ra_vm EQ; SvD.fsetdec.
rewrite (alloc_stack_top_stack ok_m1') top_stack_after_aligned_alloc; last by exact: sp_aligned.
by rewrite wrepr_opp -/(stack_frame_allocation_size fd.(f_extra)).
have D : disjoint_labels 2 lbl [:: P].
+ by move => q [A B]; rewrite /P /is_label /= orbF; apply/eqP => ?; subst; lia.
have {E} [ m2 vm2 E K2 W2 ok_vm2 H2 M2 ] := E m1 vm1 [:: P] Q W (mm_alloc M ok_m1') X1 D ok_body.
eexists; [ | | exact: W2 | | | exact: mm_free M2 ]; cycle 3.
+ move => a [] a_lo a_hi /negbTE nv.
have A := alloc_stackP ok_m1'.
have [L H] := ass_above_limit A.
apply: H2.
* rewrite (ass_root A).
split; last exact: a_hi.
etransitivity; last exact: a_lo.
suff : (0 <= sf_stk_sz (f_extra fd))%Z by lia.
by case/andP: ok_stk_sz => /lezP.
rewrite (ass_valid A) nv /= !zify => - [].
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) H => n.
lia.
+ apply: lsem_trans; first exact: E.
apply: LSem_step.
rewrite catA in ok_body.
rewrite /lsem1 /step -(addn0 (size ([:: P] ++ lbody))) (find_instr_skip ok_body) /= /eval_instr /= /get_gvar /= /get_var /=.
move: (ok_vm2 vrsp).
rewrite -(sem_preserved_RSP_GD var_tmp_not_magic exec_body); last exact: RSP_in_magic.
rewrite /= /set_RSP Fv.setP_eq /=.
case: vm2.[_]%vmap => // - [] ??? /pword_of_word_uincl /= [] ??; subst.
rewrite !truncate_word_u /=.
case/and4P: ok_ret_addr; rewrite !zify => rastack_lo rastack_h sf_aligned_for_ptr rastack_aligned.
move: ok_stk_sz; rewrite !zify => - [] stk_sz_pos [] stk_extra_pos sf_noovf.
assert (root_range := wunsigned_range (stack_root m1')).
have A := alloc_stackP ok_m1'.
have top_range := ass_above_limit A.
have top_stackE := wunsigned_top_stack_after_aligned_alloc stk_sz_pos stk_extra_pos sf_noovf sp_aligned ok_m1'.
have rastack_no_overflow : (0 <= wunsigned (top_stack m1') + rastack)%Z ∧ (wunsigned (top_stack m1') + rastack + wsize_size Uptr <= wunsigned (stack_root m1'))%Z.
* assert (top_stack_range := wunsigned_range (top_stack m1')).
assert (old_top_stack_range := wunsigned_range (top_stack (emem s1))).
have sf_large : (1 <= stack_frame_allocation_size (f_extra fd))%Z.
- apply: Z.le_trans; last exact: proj1 (round_ws_range _ _).
apply: Z.le_trans; last exact: rastack_h.
assert (h := wsize_size_pos reg_size); lia.
split; first lia.
rewrite (alloc_stack_top_stack ok_m1') top_stack_after_aligned_alloc // wrepr_opp.
rewrite -/(stack_frame_allocation_size _) wunsigned_sub; last first.
- split; last lia.
rewrite top_stackE; move: (stack_frame_allocation_size _) => n; lia.
rewrite A.(ass_root).
etransitivity; last exact: top_stack_below_root.
rewrite -/(top_stack (emem s1)).
move: stk_extra_pos rastack_lo rastack_h; clear.
have := proj1 (round_ws_range (sf_align (f_extra fd)) (sf_stk_sz (f_extra fd) + sf_stk_extra_sz (f_extra fd))).
rewrite /stack_frame_allocation_size.
move: (sf_stk_sz _ + sf_stk_extra_sz _)%Z => n /=; lia.
have -> : read m2 (top_stack m1' + wrepr Uptr rastack)%R Uptr = read m1 (top_stack m1' + wrepr Uptr rastack)%R Uptr.
* apply: eq_read => i [] i_lo i_hi; symmetry; apply: H2.
- rewrite addE !wunsigned_add; lia.
rewrite (Memory.alloc_stackP ok_m1').(ass_valid).
apply/orP; case.
- apply/negP; apply: stack_region_is_free.
rewrite -/(top_stack _).
have : (rastack + wsize_size _ <= stack_frame_allocation_size (f_extra fd))%Z :=
Z.le_trans _ _ _ rastack_h (proj1 (round_ws_range _ _)).
move: (stack_frame_allocation_size _) top_stackE => n top_stackE.
rewrite addE !wunsigned_add; [| lia..].
by move: top_range rastack_no_overflow i_hi top_stackE => /=; lia.
rewrite addE -GRing.addrA -wrepr_add !zify => - [] _.
rewrite wunsigned_add; last lia.
change (wsize_size U8) with 1%Z.
move: (sf_stk_sz _) rastack_lo => n; lia.
rewrite (alloc_stack_top_stack ok_m1') top_stack_after_aligned_alloc // wrepr_opp ok_ra /= truncate_word_u.
assert (h := decode_encode_label (label_in_lprog p') (caller, lret)).
move: h.
rewrite ok_retptr /= => -> /=.
case: ok_cbody => fd' -> -> /=; rewrite ok_pc /setcpc /=; reflexivity.
+ apply: vmap_eq_exceptI K2.
apply: Sv_Subset_union_left.
exact: SvP.MP.union_subset_1.
move => ?; rewrite /set_RSP !Fv.setP; case: eqP => // ?; subst.
move: (ok_vm2 vrsp).
have S : stack_stable m1' s2'.
+ exact: sem_one_varmap_facts.sem_stack_stable exec_body.
rewrite valid_rsp' -(ss_top_stack S) (alloc_stack_top_stack ok_m1').
rewrite top_stack_after_aligned_alloc;
last by exact: sp_aligned.
by rewrite wrepr_opp.
}
Qed.
Lemma linear_fdP ii k s1 fn s2 :
sem_call p extra_free_registers var_tmp ii k s1 fn s2 →
Pfun ii k s1 fn s2.
Proof.
exact: (@sem_call_Ind _ _ _ _ _ _ _ p extra_free_registers var_tmp Pc Pi Pi_r Pfun Hnil Hcons HmkI Hasgn Hopn Hif_true Hif_false Hwhile_true Hwhile_false Hcall Hproc).
Qed.
Lemma linear_exportcallP callee_saved gd m fn args m' res :
sem_export_call p extra_free_registers var_tmp callee_saved gd m fn args m' res →
∃ fd,
[/\
get_fundef p'.(lp_funcs) fn = Some fd,
fd.(lfd_export) &
∀ lm vm args',
wf_vm vm →
vm.[vid (lp_rsp p')]%vmap = ok (pword_of_word (top_stack m)) →
match_mem m lm →
mapM (λ x : var_i, get_var vm x) fd.(lfd_arg) = ok args' →
List.Forall2 value_uincl args args' →
vm.[vid p'.(lp_rip)]%vmap = ok (pword_of_word gd) →
vm_initialized_on vm ((var_tmp : var) :: lfd_callee_saved fd) →
all2 check_ty_val fd.(lfd_tyin) args' ∧
∃ vm' lm' res',
(* TODO: vm = vm' [\ k ] ; stack_stable m m' ; etc. *)
[/\
lsem_exportcall p' mov_eop callee_saved lm fn vm lm' vm',
match_mem m' lm',
mapM (λ x : var_i, get_var vm' x) fd.(lfd_res) = ok res',
List.Forall2 value_uincl res res' &
all2 check_ty_val fd.(lfd_tyout) res'
]
].
Proof.
case => fd ok_fd Export to_save_not_result RSP_not_result H.
exists (linear_fd p extra_free_registers lparams fn fd); split.
- exact: get_fundef_p' ok_fd.
- exact: Export.
rewrite lp_rspE => lm vm args' ok_vm vm_rsp M ok_args' args_args' vm_rip safe_registers.
have {H}[] := H vm args' ok_vm ok_args' args_args' vm_rsp.
- by move: vm_rip; rewrite lp_ripE.
move => m1 k m2 vm2 res' ok_save_stack ok_callee_saved ok_m1 wt_args' sexec ok_res' res_res' wt_res' vm2_rsp ?; subst m'.
split; first by [].
set k' := Sv.union k (Sv.union match fd.(f_extra).(sf_return_address) with RAreg ra => Sv.singleton ra | RAstack _ => Sv.empty | RAnone => Sv.add var_tmp (sv_of_flags rflags) end (if fd.(f_extra).(sf_save_stack) is SavedStackReg r then Sv.singleton r else Sv.empty)).
set s1 := {| emem := m ; evm := vm |}.
set s2 := {| emem := free_stack m2 ; evm := set_RSP p (free_stack m2) vm2 |}.
have {sexec} /linear_fdP : sem_call p extra_free_registers var_tmp 1%positive k' s1 fn s2.
- econstructor.
+ exact: ok_fd.
+ by rewrite /ra_valid; move/eqP: Export => ->.
+ exact: ok_save_stack.
+ by rewrite /top_stack_aligned; move/eqP: Export => ->.
+ exact: vm_rsp.
+ exact: ok_m1.
+ exact: ok_args'.
+ exact: wt_args'.
+ move: sexec.
rewrite /ra_undef_vm /ra_undef /ra_undef_vm_none /ra_undef_none /ra_vm.
move/eqP: Export => ->.
exact.
+ exact: ok_res'.
+ exact: wt_res'.
+ exact: vm2_rsp.
reflexivity.
case/(_ lm vm (linear_body p extra_free_registers lparams fn fd.(f_extra) fd.(f_body)) RAnone None (top_stack m) (map fst fd.(f_extra).(sf_to_save)) ok_vm M).
- move => x; rewrite !Fv.setP.
case: eqP => ?; first by subst; rewrite vm_rsp.
case: eqP => ?; first subst.
+ move/allP: safe_registers => /(_ var_tmp).
rewrite inE eqxx => /(_ erefl).
rewrite /get_var.
by case: _.[_]%vmap => // - [].
by [].
- by eexists; first exact: get_fundef_p' ok_fd.
- eexists; first exact: ok_fd.
by apply/eqP: Export.
- by [].
- eexists; first exact: ok_fd.
by move/eqP: Export => /= ->.
- eexists; first exact: ok_fd.
by move/eqP: Export => /= ->.
- by move: safe_registers; rewrite /= Export {1}/vm_initialized_on /= => /andP[] _.
move => lmo vmo texec vm_eq_vmo ? s2_vmo ? M'.
have vm2_vmo : ∀ r, r \in f_res fd → (eval_uincl vm2.[r] vmo.[r])%vmap.
- move => r r_in_result.
have r_not_saved : ¬ Sv.In r (sv_of_list id (map fst fd.(f_extra).(sf_to_save))).
+ apply/Sv_memP.
rewrite sv_of_listE map_id -sv_of_listE; apply/Sv_memP => K.
move/disjointP: to_save_not_result => /(_ _ K).
by apply; apply/Sv_memP; rewrite sv_of_listE; apply/map_f.
apply: eval_uincl_trans (s2_vmo r r_not_saved).
have r_not_rsp : vrsp != r.
+ apply/eqP => K.
by move: RSP_not_result; rewrite sv_of_listE; apply/negP/negPn/mapP; exists r.
by rewrite !Fv.setP_neq.
have : ∃ lres : values,
[/\ mapM (λ x : var_i, get_var vmo x) (f_res fd) = ok lres, List.Forall2 value_uincl res lres & all2 check_ty_val (f_tyout fd) lres ].
{
move/mapM_Forall2: ok_res' res_res' (f_tyout fd) wt_res' vm2_vmo.
move: res' res (f_res fd).
elim => [ | r' res' ih ].
+ move => _ _ /List_Forall2_inv_r-> /List_Forall2_inv_r -> [] // _ _.
by exists [::].
move => _ _ /List_Forall2_inv_r[] d [] ds [] -> [] ok_r' ok_res' /List_Forall2_inv_r[] r [] res [] -> [] r_r' res_res'.
case => // ty tys /= /andP[] wt_r' wt_res' vm2_vmo.
have := vm2_vmo d; rewrite inE eqxx => /(_ erefl).
move: ok_r'; rewrite {1 3}/get_var.
case: vm2.[d]%vmap => [ | [] // ] /= v /ok_inj ?; subst r'.
case: vmo.[d]%vmap => // v' v_v' /=.
move: ih => /(_ _ _ ok_res' res_res' _ wt_res')[].
+ by move => x hx; apply: vm2_vmo; rewrite inE hx orbT.
move => lres [] -> /= res_lres wt_lres.
eexists; split; first reflexivity.
+ constructor; last by [].
exact: value_uincl_trans v_v'.
rewrite /= wt_lres andbT.
exact: check_ty_val_uincl v_v'.
}
case => lres [] ok_lres res_lres wt_lres.
exists vmo, lmo, lres; split.
- econstructor; first exact: get_fundef_p' ok_fd.
+ exact: Export.
+ exact: texec.
move => r hr; apply: vm_eq_vmo.
subst k'.
move: ok_callee_saved hr; clear.
rewrite -/(ra_vm _ _) -/(saved_stack_vm _).
move: (Sv.union k _) => X.
clear.
rewrite sv_of_list_map Sv.diff_spec => S hrC [] hrX; apply.
apply: S.
by rewrite Sv.inter_spec.
- exact: M'.
- move/eqP: Export => /= -> /=.
exact: ok_lres.
- exact: res_lres.
exact: wt_lres.
Qed.
End PROOF.
End ASM_EXTRA.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:48:40 04/14/2015
// Design Name:
// Module Name: clockdivide2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clockdivide2(
input clk,
input rst,
input select,
output reg [31:0] OUT1,
output reg [31:0] OUT2,
output clkdivided1hz,
output clkdivided2hz,
output clkselect
);
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT1<=32'd0;
else
if (OUT1 == 32'd50000000)
OUT1<=32'd0;
else
OUT1 <= OUT1 + 1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT2<=32'd0;
else
if (OUT2 == 32'd500000)
OUT2<=32'd0;
else
OUT2 <= OUT2 + 1;
end
assign clkdivided1hz = (OUT1 == 32'd50000000);
assign clkdivided2hz = (OUT2 == 32'd500000);
assign clkselect = (select) ? clkdivided2hz : clkdivided1hz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BLACKBOX_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BLACKBOX_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Park_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Park_Transform
// Source Path: velocityControlHdl/Transform_ABC_to_dq/Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Park_Transform
(
sin_coefficient,
cos_coefficient,
alpha_current,
beta_current,
direct_current,
quadrature_current
);
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
input signed [17:0] alpha_current; // sfix18_En13
input signed [17:0] beta_current; // sfix18_En13
output signed [17:0] direct_current; // sfix18_En15
output signed [17:0] quadrature_current; // sfix18_En15
wire signed [35:0] Product2_out1; // sfix36_En29
wire signed [35:0] Product3_out1; // sfix36_En29
wire signed [35:0] Add1_out1; // sfix36_En29
wire signed [17:0] D_Data_Type_out1; // sfix18_En15
wire signed [35:0] Product1_out1; // sfix36_En29
wire signed [35:0] Product_out1; // sfix36_En29
wire signed [35:0] Add_out1; // sfix36_En29
wire signed [17:0] Q_Data_Type_out1; // sfix18_En15
// Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame.
//
// Park Transform
// <S42>/Product2
assign Product2_out1 = alpha_current * cos_coefficient;
// <S42>/Product3
assign Product3_out1 = beta_current * sin_coefficient;
// <S42>/Add1
assign Add1_out1 = Product2_out1 + Product3_out1;
// <S42>/D_Data_Type
assign D_Data_Type_out1 = ((Add1_out1[35] == 1'b0) && (Add1_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add1_out1[35] == 1'b1) && (Add1_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add1_out1[31:14])));
assign direct_current = D_Data_Type_out1;
// <S42>/Product1
assign Product1_out1 = beta_current * cos_coefficient;
// <S42>/Product
assign Product_out1 = alpha_current * sin_coefficient;
// <S42>/Add
assign Add_out1 = Product1_out1 - Product_out1;
// <S42>/Q_Data_Type
assign Q_Data_Type_out1 = ((Add_out1[35] == 1'b0) && (Add_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add_out1[35] == 1'b1) && (Add_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add_out1[31:14])));
assign quadrature_current = Q_Data_Type_out1;
endmodule // velocityControlHdl_Park_Transform
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:00:19 12/14/2016
// Design Name:
// Module Name: BR_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BR_Top(
input wire clk, clr,
input wire ps2c, ps2d,
output wire hsync, vsync,
output wire [3:0] red, green, blue,
output wire [7:0] an,
output wire [7:0] segment
);
// Keyboard signal
wire [ 3: 0] status;
// VGA signal
wire signed [31:0] scroll;
wire video_on;
wire [ 9: 0] pixel_x, pixel_y;
wire btn_pos, mycar_pos, explode_pos,game_over_pos, score_pos;
wire btn_visible, explode_visible;
wire obstacle_pos [0:4];
wire digit_pos [0:3];
wire iscollide [0:4];
wire [16:0] back_addr, side_addr;
wire [15:0] explode_addr;
wire [13:0] digit_addr [0:3];
wire [14:0] game_over_addr;
wire [13:0] btn_addr, score_addr;
wire [12:0] mycar_addr;
wire [12:0] obstacle_addr [0:4];
wire [ 3:0] high_score [0:3];
Renderer render_unit (.clk(clk), .clr(clr),
.status(status),
.video_on(video_on),
.pixel_x(pixel_x), .pixel_y(pixel_y),
.scroll(scroll),
.btn_pos(btn_pos), .mycar_pos(mycar_pos), .explode_pos(explode_pos), .game_over_pos(game_over_pos), .score_pos(score_pos),
.btn_visible(btn_visible), .explode_visible(explode_visible),
.obstacle_pos0(obstacle_pos[0]), .obstacle_pos1(obstacle_pos[1]), .obstacle_pos2(obstacle_pos[2]), .obstacle_pos3(obstacle_pos[3]), .obstacle_pos4(obstacle_pos[4]),
.digit_pos0(digit_pos[0]), .digit_pos1(digit_pos[1]), .digit_pos2(digit_pos[2]), .digit_pos3(digit_pos[3]),
.iscollide0(iscollide[0]), .iscollide1(iscollide[1]), .iscollide2(iscollide[2]), .iscollide3(iscollide[3]), .iscollide4(iscollide[4]),
.back_addr(back_addr), .side_addr(side_addr), .btn_addr(btn_addr), .mycar_addr(mycar_addr), .explode_addr(explode_addr), .game_over_addr(game_over_addr), .score_addr(score_addr),
.obstacle_addr0(obstacle_addr[0]), .obstacle_addr1(obstacle_addr[1]), .obstacle_addr2(obstacle_addr[2]), .obstacle_addr3(obstacle_addr[3]), .obstacle_addr4(obstacle_addr[4]),
.digit_addr0(digit_addr[0]), .digit_addr1(digit_addr[1]), .digit_addr2(digit_addr[2]), .digit_addr3(digit_addr[3]),
.red(red), .green(green), .blue(blue)
);
Controller control_unit (.clk(clk), .clr(clr),
.ps2c(ps2c), .ps2d(ps2d),
.status(status),
.hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(pixel_x), .pixel_y(pixel_y),
.btn_pos(btn_pos), .mycar_pos(mycar_pos), .explode_pos(explode_pos), .game_over_pos(game_over_pos), .score_pos(score_pos),
.btn_visible(btn_visible), .explode_visible(explode_visible),
.obstacle_pos0(obstacle_pos[0]), .obstacle_pos1(obstacle_pos[1]), .obstacle_pos2(obstacle_pos[2]), .obstacle_pos3(obstacle_pos[3]), .obstacle_pos4(obstacle_pos[4]),
.digit_pos0(digit_pos[0]), .digit_pos1(digit_pos[1]), .digit_pos2(digit_pos[2]), .digit_pos3(digit_pos[3]),
.iscollide0(iscollide[0]), .iscollide1(iscollide[1]), .iscollide2(iscollide[2]), .iscollide3(iscollide[3]), .iscollide4(iscollide[4]),
.scroll(scroll),
.back_addr(back_addr), .side_addr(side_addr), .btn_addr(btn_addr), .mycar_addr(mycar_addr), .game_over_addr(game_over_addr), .score_addr(score_addr),
.obstacle_addr0(obstacle_addr[0]), .obstacle_addr1(obstacle_addr[1]), .obstacle_addr2(obstacle_addr[2]), .obstacle_addr3(obstacle_addr[3]), .obstacle_addr4(obstacle_addr[4]),
.explode_addr(explode_addr),
.digit_addr0(digit_addr[0]), .digit_addr1(digit_addr[1]), .digit_addr2(digit_addr[2]), .digit_addr3(digit_addr[3]),
.high_score0(high_score[0]), .high_score1(high_score[1]), .high_score2(high_score[2]), .high_score3(high_score[3])
);
Model model_unit (.clk(clk), .high_score0(high_score[0]), .high_score1(high_score[1]), .high_score2(high_score[2]), .high_score3(high_score[3]), .segment(segment), .an(an));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_TB_V
`define SKY130_FD_SC_LS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_TB_V
|
// nios_dut_mm_interconnect_0_avalon_st_adapter_011.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_011 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_011_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module mio3_eth_gpac (
input wire RESET_N,
input wire clkin,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire mdio_phy_mdc,
inout wire mdio_phy_mdio,
output wire phy_rst_n,
inout wire SDA, SCL,
output wire [7:0] LED
);
wire RST;
wire BUS_CLK_PLL, CLK250PLL, CLK125PLLTX, CLK125PLLTX90, CLK125PLLRX;
wire PLL_FEEDBACK, LOCKED;
// ------- PLL for communication with FPGA ------- //
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(7), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT3_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT3_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT4_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT4_PHASE(-5.6), // Phase offset for CLKOUT0 (-360.000-360.000).
//-65 -> 0?; - 45 -> 39; -25 -> 100; -5 -> 0;
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(BUS_CLK_PLL),
.CLKOUT1(CLK250PLL),
.CLKOUT2(CLK125PLLTX),
.CLKOUT3(CLK125PLLTX90),
.CLKOUT4(CLK125PLLRX),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(clkin),
// Control Ports
.PWRDWN(0),
.RST(!RESET_N),
// Feedback
.CLKFBIN(PLL_FEEDBACK)
);
wire BUS_CLK;
BUFG BUFG_inst_BUS_CKL (.O(BUS_CLK), .I(BUS_CLK_PLL) );
wire CLK125TX, CLK125TX90, CLK125RX;
BUFG BUFG_inst_CLK125TX ( .O(CLK125TX), .I(CLK125PLLTX) );
BUFG BUFG_inst_CLK125TX90 ( .O(CLK125TX90), .I(CLK125PLLTX90) );
BUFG BUFG_inst_CLK125RX ( .O(CLK125RX), .I(rgmii_rxc) );
assign RST = !RESET_N | !LOCKED;
wire gmii_tx_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
wire gmii_tx_er;
wire gmii_crs;
wire gmii_col;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire [7:0] gmii_rxd;
wire gmii_rx_er;
wire mdio_gem_mdc;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire link_status;
wire [1:0] clock_speed;
wire duplex_status;
rgmii_io rgmii (
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.gmii_txd_int(gmii_txd), // Internal gmii_txd signal.
.gmii_tx_en_int(gmii_tx_en),
.gmii_tx_er_int(gmii_tx_er),
.gmii_col_int(gmii_col),
.gmii_crs_int(gmii_crs),
.gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid.
.gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs.
.gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs.
.eth_link_status(link_status),
.eth_clock_speed(clock_speed),
.eth_duplex_status(duplex_status),
// Following are generated by DCMs
.tx_rgmii_clk_int(CLK125TX), // Internal RGMII transmitter clock.
.tx_rgmii_clk90_int(CLK125TX90), // Internal RGMII transmitter clock w/ 90 deg phase
.rx_rgmii_clk_int(CLK125RX), // Internal RGMII receiver clock
.reset(!phy_rst_n)
);
IOBUF i_iobuf_mdio (
.O(mdio_gem_i),
.IO(mdio_phy_mdio),
.I(mdio_gem_o),
.T(mdio_gem_t)
);
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
wire RBCP_ACK;
wire SiTCP_RST;
WRAP_SiTCP_GMII_XC7K_32K sitcp (
.CLK(BUS_CLK) , // in : System Clock >129MHz
.RST(RST) , // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0) , // in : Load default parameters
.EXT_IP_ADDR(32'hc0a80a10) , // in : IP address[31:0] //192.168.10.16
.EXT_TCP_PORT(16'd24) , // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660) , // in : RBCP port #[15:0]
.PHY_ADDR(5'd3) , // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(EEPROM_CS) , // out : Chip select
.EEPROM_SK(EEPROM_SK) , // out : Serial data clock
.EEPROM_DI(EEPROM_DI) , // out : Serial write data
.EEPROM_DO(1'b0) , // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C() , // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D() , // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E() , // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F() , // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(phy_rst_n) , // out : PHY reset
.GMII_1000M(1'b1) , // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(CLK125TX) , // in : Tx clock
.GMII_TX_EN(gmii_tx_en) , // out : Tx enable
.GMII_TXD(gmii_txd) , // out : Tx data[7:0]
.GMII_TX_ER(gmii_tx_er) , // out : TX error
// RX
.GMII_RX_CLK(CLK125RX) , // in : Rx clock
.GMII_RX_DV(gmii_rx_dv) , // in : Rx data valid
.GMII_RXD(gmii_rxd) , // in : Rx data[7:0]
.GMII_RX_ER(gmii_rx_er) , // in : Rx error
.GMII_CRS(gmii_crs) , // in : Carrier sense
.GMII_COL(gmii_col) , // in : Collision detected
// Management IF
.GMII_MDC(mdio_phy_mdc) , // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i) , // in : Data
.GMII_MDIO_OUT(mdio_gem_o) , // out : Data
.GMII_MDIO_OE(mdio_gem_t) , // out : MDIO output enable
// User I/F
.SiTCP_RST(SiTCP_RST) , // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0) , // in : Reserved input, shoud be 0
.TCP_OPEN_ACK() , // out : Acknowledge for open (=Socket busy)
.TCP_ERROR() , // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ) , // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ) , // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(1'b1) , // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR) , // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA) , // out : Write data[7:0]
.TCP_TX_FULL() , // out : Almost full flag
.TCP_TX_WR(1'b0) , // in : Write enable
.TCP_TX_DATA(8'b0) , // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT) , // out : RBCP active
.RBCP_ADDR(RBCP_ADDR) , // out : Address[31:0]
.RBCP_WD(RBCP_WD) , // out : Data[7:0]
.RBCP_WE(RBCP_WE) , // out : Write enable
.RBCP_RE(RBCP_RE) , // out : Read enable
.RBCP_ACK(RBCP_ACK) , // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
// ------- BUS SYGNALING ------- //
wire BUS_WR, BUS_RD, BUS_RST;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
assign BUS_RST = SiTCP_RST;
rbcp_to_bus irbcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA)
);
// ------- MODULE ADREESSES ------- //
localparam GPIO_BASEADDR = 32'h1000;
localparam GPIO_HIGHADDR = 32'h2000-1;
localparam I2C_BASEADDR = 32'h2000;
localparam I2C_HIGHADDR = 32'h3000-1;
localparam ABUSWIDTH = 32;
// ------- USER MODULES ------- //
wire [7:0] GPIO_IO;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO_IO)
);
assign LED = GPIO_IO[7:0];
// ------- I2C module ------- //
wire I2C_CLK;
clock_divider #(
.DIVISOR(1500)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(I2C_CLK)
);
i2c #(
.BASEADDR(I2C_BASEADDR),
.HIGHADDR(I2C_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(64)
) i_i2c (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.I2C_CLK(I2C_CLK),
.I2C_SDA(SDA),
.I2C_SCL(SCL)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
|
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